Apple A1297 Schematics

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

Schematic / PCB #’s

SCHEM,BLACK_PEARL,MLB,K92

pre-evt 11/22/10 rev3.11.3

ALIASES RESOLVED

1 OF 105

1 OF 132

2009-05-19

SMC

07/12/2010

49

45

K91_BEN

Front Flex Support

04/26/2010

48

44

K17_MLB

PROJECT SPECIFIC CONNS

07/22/2010

47

43

K92_ERIC

External USB Connectors

08/24/2010

46

42

K92_ERIC

SATA Connectors

11/08/2010

45

41

K92_ERIC

FireWire Connector

07/22/2010

43

40

K91_MLB

FireWire Port & PHY Power

10/20/2010

42

39

K91_MLB

FireWire LLC/PHY (FW643)

10/20/2010

41

38

K91_MLB

Ethernet Connector

08/24/2010

40

37

K92_ERIC

ETHERNET PHY (CAESAR IV)

10/19/2010

39

36

K92_ERIC

T29 Power Support

11/09/2010

38

35

T29_REF

T29 Host (2 of 2)

11/09/2010

37

34

T29_REF

T29 Host (1 of 2)

11/09/2010

36

33

T29_REF

ExpressCard Connector

07/27/2010

35

32

K92_ERIC

X19/ALS/CAMERA CONNECTOR

10/21/2010

34

31

K91_MLB

FSB/DDR3/FRAMEBUF Vref Margining

08/26/2010

33

30

K91_YUN

CPU Memory S3 Support

04/26/2010

32

29

K17_MLB

DDR3 SO-DIMM Connector B

06/14/2010

31

28

K92_YUN

DDR3 Byte/Bit Swaps

05/14/2010

30

27

K92_YUN

DDR3 SO-DIMM Connector A

06/14/2010

29

26

K92_YUN

Chipset Support

06/29/2010

28

25

K91_MLB

USB HUBS

06/29/2010

26

24

K92_BEN

CPU & PCH XDP

10/17/2010

25

23

K91_MLB

PCH DECOUPLING

08/06/2010

24

22

K91_YUN

PCH GROUNDS

05/20/2010

23

21

K92_YUN

PCH POWER

07/09/2010

22

20

K91_MLB

PCH MISC

10/20/2010

21

19

K91_MLB

PCH PCI/FLASHCACHE/USB

10/20/2010

20

18

K91_MLB

PCH DMI/FDI/GRAPHICS

10/17/2010

19

17

K91_MLB

PCH SATA/PCIE/CLK/LPC/SPI

10/19/2010

18

16

K91_MLB

CPU DECOUPLING-II

07/21/2010

17

15

K91_MLB

CPU DECOUPLING-I

07/21/2010

16

14

K91_MLB

CPU POWER AND GND

04/26/2010

14

13

K60_MLB

CPU POWER

07/16/2010

13

12

K91_MLB

CPU DDR3 INTERFACES

04/26/2010

12

11

K60_MLB

CPU CLOCK/MISC/JTAG

07/16/2010

11

10

K91_MLB

CPU DMI/PEG/FDI/RSVD

04/26/2010

10

9

K60_MLB

Signal Aliases

04/26/2010

9

8

K17_MLB

Power Aliases

04/26/2010

8

7

K17_MLB

Functional / ICT Test

04/26/2010

7

6

K17_MLB

BOM Configuration

04/26/2010

5

K17_MLB

Revision History

04/26/2010

4

K17_MLB

Revision History

04/26/2010

3

K17_MLB

System Block Diagram

04/26/2010

2

K60_MLB

90

K17_MLB

04/26/2010

98

LCD Backlight Support

89

K92_DINESH

09/07/2010

97

LCD Backlight Driver (LP8545)

88

K92_YUAN

07/28/2010

96

Graphics MUX (GMUX)

87

K91_CHANG

07/21/2010

95

1V0 GPU / 1V5 FB Power Supply

86

K91_MLB

10/22/2010

94

DisplayPort/T29 A Connector

85

K91_MLB

10/22/2010

93

DisplayPort/T29 A MUXing

84

K92_YUN

06/25/2010

92

Muxed Graphics Support

83

K17_MLB

04/26/2010

90

LVDS Display Connector

82

K91_CHANG

07/21/2010

89

GPU (Whistler) CORE SUPPLY

81

K92_BEN

06/01/2010

88

Whistler DP PWR/GNDs

80

K91_MLB

07/17/2010

87

Whistler GPIOs & STRAPs

79

K92_SUMA

10/21/2010

86

Whistler LVDS/DP/GPIO

78

K91_YUN

08/23/2010

85

GDDR5 Frame Buffer B

77

K91_YUN

08/23/2010

84

GDDR5 Frame Buffer A

76

K18_MLB

04/27/2010

82

Whistler FRAME BUFFER I/F

75

K92_BEN

06/03/2010

81

Whistler CORE/FB POWER

74

K91_MLB

10/19/2010

80

Whistler PCI-E

73

K92_YUAN

07/22/2010

79

Power Control 1/ENABLE

72

K91_MLB

10/18/2010

78

Power FETs

71

K91_CHANG

07/21/2010

77

Misc Power Supplies

70

K92_ERIC

09/23/2010

76

CPU VCCIO (1.05V) Power Supply

69

K92_ERIC

09/27/2010

75

CPU IMVP7 & AXG VCore Output

68

K92_ERIC

11/09/2010

74

CPU IMVP7 & AXG VCore Regulator

67

K91_CHANG

07/21/2010

73

1.5V DDR3 Supply

66

K92_ERIC

08/30/2010

72

5V / 3.3V Power Supply

65

K91_CHANG

07/21/2010

71

System Agent Supply

64

K91_CHANG

07/21/2010

70

PBus Supply & Battery Charger

63

K92_CHANG

06/28/2010

69

DC-In & Battery Connectors

62

K92_KAVITHA

11/22/2010

68

AUDIO: JACK TRANSLATORS

61

K92_KAVITHA

11/02/2010

67

AUDIO: JACKS

60

K92_KAVITHA

10/22/2010

66

AUDIO:SPEAKER AMP

59

K92_KAVITHA

10/22/2010

65

AUDIO: HEADPHONE OUT

58

K92_AUDIO

06/16/2010

63

AUDIO: LINE IN

57

K92_KAVITHA

07/30/2010

62

AUDIO:CODEC

56

K92_BEN

05/27/2010

61

SPI ROM

55

K92_DINESH

06/02/2010

59

Digital Accelerometer

54

K92_ERIC

07/27/2010

58

WELLSPRING 2

53

K92_ERIC

10/11/2010

57

WELLSPRING 1

52

K17_MLB

04/26/2010

56

Fan Connectors

51

K92_DINESH

09/24/2010

55

Thermal Sensors

50

K92_DINESH

10/29/2010

54

High Side and CPU/AXG Current Sensing

49

K92_DINESH

09/24/2010

53

Voltage & Load Side Current Sensing

48

K17_MLB

04/26/2010

52

K92 SMBus Connections

47

K91_YUN

09/23/2010

51

LPC+SPI Debug Connector

08/23/2010

Power Supplies BIST

K92_DINESH

132

105

07/28/2010

DEBUG SENSORS AND ADC 2

K92_DINESH

131

104

09/07/2010

DEBUG SENSORS AND ADC

K92_DINESH

130

103

04/27/2010

PCH Power Aliases

K17_MLB

121

102

05/14/2010

PCB Rule Definitions

K17_MLB

109

101

07/22/2010

Project Specific Constraints

K91_MLB

108

100

07/21/2010

GPU (Whistler) CONSTRAINTS

K91_MLB

107

99

05/14/2010

SMC Constraints

K17_MLB

106

98

10/20/2010

T29 Constraints

T29_REF

105

97

07/22/2010

Ethernet/FW Constraints

K91_MLB

104

96

07/22/2010

PCH Constraints 2

K91_MLB

103

95

06/25/2010

PCH Constraints 1

K92_YUN

102

94

05/14/2010

Memory Constraints

K17_MLB

101

93

07/22/2010

CPU Constraints

K91_MLB

100

92

SCHEM,MLB,K92

PCBF,BLACK_PEARL,MLB,K92

820-2914 CRITICAL

1 PCB

07/30/2010

Power Sequencing EG/PCH S0

K92_YUAN

99

91

CRITICAL

SCHEM,BLACK_PEARL,MLB,K92

SCH1

051-8618

LAST_MODIFIED=Tue Nov 23 20:44:38 2010

TITLE=MLB ABBREV=DRAWING

Contents

(.csa)

Date

Page Sync

Table of Contents

04/27/2010

1

K17_MLB

Page Sync

Contents

Date

(.csa)

46

K91_BEN

07/12/2010

50

SMC Support

Sync

(.csa)

Contents

Date

Page

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PERN4PERN1PERN3PERN2

U6610,6620,6630,6640,6650

LINE OUT

LINE IN

PG 73

USX2061

USBDN1

USBDN2

USBDN3

USBDN4

EXPRESSCARD

PG 41

USB

EXTERNAL

J4600,J4610,4720

EXTA

EXTC EXTB

TRACKPAD/

KEYBOARD

PG 73

USX2061

USBDN1

USBDN2

USBDN3

USBDN4

Misc

CS4206ACNZC

PG 17

PG 83

U9600

J9000

XP25-5

GMUX

CONN

LVDS

PG 87

J9400

DISPLAY PORT

U9320

CBTL06141EE

CONN

Mini PCI-E

AIRPORT

PG 31

J3401

U4100

J4310

FW643

FW-800

Conn

PG 40

PG 38

U3900

J4000

PG 37

Conn

E-NET

PG 36

E-NET

GB

BCM57765

PG 16

PEG

PG 16

PCI-E

PG 85

PG 84

J4501

Conn

SATA

ODD

P8 41

J4500

SATA

HD

Conn

CK505

P8 24

SATA 2.0 /3GHZ.

SATA 3.0/ 6GHZ.

PG 18

JTAG

PG 18

PCI

TMDS OUT

DVI OUT

LVDS OUT

HDMI OUT

RGB OUT

DP OUT

SATA

PG 16

CLK

BUFFER

INTEL

U1800

COUGAR POINT

J3500

EXPRESSCARD

PG 32

CONN

PG 16

SMB

IHDA

PG 16

HEADPHONE

U6500

Amp

Conns

Audio

PG 61

J6780,6781,6782,6700,6750

U6200

DIMM’s

Audio

EXPRESSCARD

PG 57

Codec

SMB

PG 48

(UP TO 14 DEVICES)

PG 18

USB

CTRL

0 21 3 7654 8

121110

9

13

LPC

SPI

PG 16

PWR

PG 16

PG 19

U3600

J3401

PG 31

Bluetooth

U6100

SPI

Boot ROM

PG 58

B,0 BSB

SMC

PG 54

ADC

U4900

Speaker

CONN

J5713/J5800

PG 60

Amps

J3402

PG 31

CAMERA

IR

PG 44

J4800

U3600

PG 53/54

J3500

PG 32

Fan

Prt

Ser

PG 47

Port80,serial

J5650,5660

POWER SENSE

FAN CONN AND CONTROL

J5100

PG 53

PG 52

PG 51

LPC Conn

U4900

J6900/J6950

DC/BATT

TEMP SENSOR

PG 63

POWER SUPPLY

U2700

CLOCK

PG 74

U8000

WHISTLBR

PG 19

GPIO

FDI

PG 17

PG 9-13

SANDYBRIDGE

INTEL CPU

PG 17

DMI

RTC

DDR3 /1333MHZ

2 UDIMMs

PG 16

DIMM

J2900

PG 26,28

PG 23

J2500

XDP CONN

SYNC_MASTER=K60_MLB

System Block Diagram

SYNC_DATE=04/26/2010

2 OF 132 2 OF 105

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(6 TO 8.4V)

F6905

SMC_PM_G2_EN

Q9806

VREG5

DELAY

RC

DELAY

RC

DELAY

RC

CPUVTTS0_EN

P1V5CPU_EN

P1V8S0_EN

P1V2S0_EN

R7978

U1800

(PAGE 16-21)

SLP_S4#(H7)

SLP_S3#(P12)

DELAY

RC

(PAGE 45)

P60

(PAGE 87)

SMC

U4900

PL32A

SLP_S5#(E4)

COUGAR_POINT

DELAY

RC

PB18A

XP25-5

EG_RAIL4_EN

U9600

GMUX

PB16B

PB17B

PB17A

2S4P

J6950

EG_RAIL2_EN

EG_RAIL1_EN

EG_RAIL3_EN

PPVBATT_G3H_CONN

DDRREG_EN

PM_SLP_S3_L

PM_SLP_S3_L_R

P5VS3_EN

P3V3S3_EN

PM_SLP_S4_L

PM_SLP_S5_L

PM_ALL_GPU_PGOOD

PBUSVSENS_EN

P3V3S0_EN

P5VS0_EN

&&

LCD_BKLT_EN

SMC_ADAPTER_EN&&PM_SLP_S3_L

BKLT_PLT_RST_L

Q4260

BKLT_EN

ENA

VIN

U9701

(PAGE 88)

LP8545SQX

(PAGE 71)

U7790

VOUT

LTC1872

VIN

VOUT

P3V3S5_EN

P3V3GPU_EN GPUVCORE_EN

CHGR_BGATE

Q7055

P1V0GPU_EN

P1V5FB_EN

PPVBAT_G3H_CHGR_R

(PAGE 86)

1.103V(L/H)

EN1

1.8V(R/H)

ISL6236

EN2

U9500

VIN

P5VS3_EN

VOUT1

VOUT2

POK2

POK1

P3V3S5_EN

EN2

EN1

P1V5FB_PGOOD

A

PP1V0_S0GPU

R5410

P1V0GPU_PGOOD

(PAGE 64)

ADAPTER

IN

AC

J6900

DCIN(16.5V)

6A FUSE

SMC_DCIN_ISENSE

K92 POWER SYSTEM ARCHITECTURE

A

VIN

R7020

PPDCIN_G3H_OR_PBUS_R

BATTERY CHARGER

PBUS SUPPLY/

U7000

ISL6259HRTZ

VOUT

R6990

SMC_BATT_ISENSE

PPVBAT_G3H_CHGR_REG

R7050

A

F7041

8A FUSE

F7040

PGOOD1

PP1V5R1V35_GPU_FB_ISNS

D6990

TPS51980

P5VS3_PGOOD

SMC_GPU_1V5_ISENSE

PPVOUT_S0_LCDBKLT

(PAGE 66)

P1V8_S0_EN

PP10V_FW

U7201

PGOOD2

P3V3S5_PGOOD

Q7830

Q7810

Q7870

P3V3S0_EN

P3V3GPU_EN

P3V3S3_EN

PP3V3_S0_FET

P1V2ENET_EN

PP3V3_S0_GPU

PP3V3_S3

EN

(PAGE 71)

U7760

VOUT

ISL8014A

VIN

U7720

ISL8014

(PAGE 70)

PP3V3_FW_FET

PGOOD

VOUT

P1V8S0_PGOOD

PP1V2_ENET

PP1V8_S0

Q7850

TPS22924

U4201

(PAGE 39)

P1V5_S0_EN

PP3V3_FW_FWPHY

FW_PWR_EN

EN

VIN

Q7922

(PAGE 71)

U7710

ISL8009B

OUT

3.3V

VIN

5V

(R/H)

(L/H)

VOUT1

VOUT2

PP5V_S5

P1V5CPU_EN

RD220

A

MEMVTT_EN

ON

PP5V_S3

(PAGE 54)

SLG5AP020

U7801

PP3V3_S5

VOUT

S3

S5

DDRREG_EN

SMC_CPU_HI_ISENSE

PP5V_S3

VIN

R5388

1.5V

(PAGE 67)

U7300

TPS51916

0.75V

PP1V5_S3RS0

A

CPUIMVP7_VR_ON

PP5V_S3

Q7860

PGOOD

VOUT2

PP5V_S0_FET

PPVTT_S0_DDR_LDO

P5VS0_EN

DDRREG_PGOOD

VIN

U5805

VOUT1

A

VLDOIN

VR_ON

VIN

PPDDR_S3_REG

ISL95831

(PAGE 68)

CPU VCORE

U7400

PGOOD

VOUT

PP1V2_S0

P1V2GMUX_EN

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

PP3V3_ENET

PP3V3_S0

PP1V5_S0

A

SMC_DDR_ISENSE

TPS61045

VOUT

(PAGE 54)

R7350/U5440

SMC_CPU_ISENSE

PP1V05_S0_VMON

PP1V5_S0_VMON

PP3V3_S0_VMON

V2MON

V3MON

V4MON

TRST = 200mS

(PAGE 73)

PG

RST*

PP3V3_S0

U7971

S0PGOOD_PWROK

VCC

P5VS3_PGOOD

P1V8S0_PGOOD

ISL88042IRTJJZ

P1V2ENET_PGOOD

PP18V5_S3

U6201

(PAGE 57)

MAX8840

VOUTEN

VIN

PM_ALL_GPU_PGOOD

U7980

PP1V5_S3

V

PPVCORE_S0_CPU

SMC_CPU_VSENSE

CPUIMVP7_PGOOD

PP4V5_AUDIO_ANALOG

(PAGE 82)

PPBUS_G3H

SMC_PBUS_VSENSE

PP5V_S3_GFXIMVP6_VDD

GPUVCORE_EN

VR_ON

VDD

V

Q5315

GPU VCORE

ISL6263C

VIN

U8900

PGOOD

VOUT

PM6640

3.425V G3HOT

(PAGE 63)

U6990

ENABLE

A

SMC_GPU_ISENSE

U5410

GPUVCORE_PGOOD

V

PP3V42_G3H

PPVCORE_GPU

SMC_GPU_VSENSE

(PAGE 46)

CPUVTTS0_EN

U5000

PP5V_S0_CPUVTTS0

EN

VIN

NCP303LSN

SMC PWRGD

SMC_RESET_L

ISL95870

(PAGE 70)

U7600

1.05V

VIN

PP3V3_S0_PWRCTL

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_S3_L

SMC_ONOFF_L

ALL_SYS_PWRGD

RSMRST_PWRGD

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

(PAGE 45)

U4900

H8S2117

PWRGD(P12)

PWR_BUTTON(P90)

RSMRST_IN(P13)

CPU

SMC

U1000

(PAGE 9-14)

U2850

PM_PCH_PWRGD

U1800

PS_PWRGD

PGOOD

VOUT

SMC AVREF SUPPLY

REF3333

(PAGE 46)

VOUT

CPUVTTS0_PGOOD

R7640

A

99ms DLY

IMVP_VR_ON(P16)

SMC_CPU_FSB_ISENSE

PP3V3_S5_AVREF_SMC

PPCPUVTT_S0

SMC_TPAD_RST_L

COUGAR_POINT

SMC_ONOFF_L

SYS_RERST#

SYSRST(PA2)

RESET*

P17(BTN_OUT)

RES*

PWRBTN#

DRAMPWROK

PLTRST#

PROCPWRGD

RSMRST#

ACPRESENT

(P64)

RSMRST_OUT(P15)

(PAGE 16-21)

SM_DRAMPWROK

VCCCPUPWRGD

SMC_RESET_L

SMC_ADAPTER_EN

IMVP_VR_ON

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PM_MEM_PWRGD

CPU_PWRGD

PLT_RERST_L

PM_PWRBTN_L

(PAGE 39)

EN

U4202

FW_PWR_EN

VIN

TPS22924

U5001

PP3V42_G3H

PPCPUVCCIO_S3

VOUT

PP1V0_FW

SYNC_DATE=04/26/2010

Revision History

SYNC_MASTER=K17_MLB

3 OF 132 3 OF 105

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

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SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROTO2/EVT 11/15/10 rev3.6 for board 820-2914-06.brd release PROTO2/EVT 11/19/10 rev3.7 for board 820-2914-07.brd release

EVT 11/22/10 rev3.9 for board 820-2914-07.brd release

PROTO2/EVT 11/11/10 rev3.0 for board 820-2914-05.brd release

SYNC_DATE=04/26/2010

Revision History

SYNC_MASTER=K17_MLB

4 OF 132 4 OF 105

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Ethernet

BOM Variants

Bar Code Labels / EEEE #’s

K92 BOM GROUPS

Programmed Parts-All Builds

SMC

Alternate Parts

(U5850)

(L7630) (U9390) (Q3200, etc)

(Q3888,Q9430)

PSOC

Module Parts

EFI

GPUROM will NOSUFFED @EVT

SMC_PROG:EVT,BOOTROM_PROG:EVT,ENETROM_PROG:B0_NOSD,TPAD_PROG:EVT,T29ROM:PROG,GMUX_PROG,T29MCU:PROG

K92_PROGPARTS

SNB_CPT_XDP,LPCPLUS:YES,VREFMRGN_NOT

K92_DEVEL:PVT

GPUVID_1P11V,HUB1_2NONREM,HUB2_2NONREM,KB_BL,ENET:B0,T29BST:Y,T29:YES,T29_DP_HPD:ALL_OR

K92_COMMON2

CPUMEM_S0,EXT_HP_AMP,SMC_DEBUG_YES,USBHUB_2514B

K92_COMMON1

SNB_CPT_XDP,DEBUG_ADC,LPCPLUS:YES,VREFMRGN,GMUX_JTAG_CONN,S0PGOOD_ISL,BMON:ENG,CPURIPPLE_ENG,IMVPISNS_ENG,SDRVI2C:MCU

K92_DEVEL:ENG

085-1898

K92_DEVEL:ENG

K92 MLB DEVELOPMENT BOM

639-1465

K92_COMMON,CPU:2_3GHZ,FB_1G_HYNIX,VRAM_HYNIX,EEEE_DG61

PCBA,MLB,CFG4,K92

U6100

1

64 MBIT SPI SERIAL DUAL I/O FLASH

335S0740 CRITICAL

BOOTROM_BLANK

U6100

1

IC,EFI,ROM,PROTO, K90/K90I/K91/K91F/K92

341S2893 CRITICAL

BOOTROM_PROG:PROTO0

341S2991 CRITICAL

U6100

IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92

BOOTROM_PROG:PROTO2

1

IC,PROGRAMMED MCU,32B,LPC1112A,16KB/2KB,HVQFN25

U9330

CRITICAL

1

341S2939

T29MCU:PROG

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

U9330

CRITICAL

1

337S3997

T29MCU:BLANK

IC,GMUX,K92

GMUX_PROG

1

CRITICAL

U9600

341S2996

IC,SGRAM,GDDR5,64MX32,3.6GBPS,C-DIE,HF

333S0571

U8400,U8450,U8500,U8550

4

FB_1G_SAMSUNG

CRITICAL

IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN 8X8

1

U3900

343S0494 CRITICAL

ENET:A0

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

1

U4100

338S0753 CRITICAL

IC,SDRAM,GDDR5,32MX32,1.25GHz,A-DIE1.35V

U8400,U8450,U8500,U8550

4

FB_512_HYNIX

333S0564 CRITICAL

IC,GPU,AMD,WHISTLER,962FCBGA,40NM,ES

U8000

337S3936

1

CRITICAL

U3600

338S0945

T29:YES

1

CRITICAL

Light Ridge,S LHAJ,FCBGA,15x15mmm

1

353S3055

IC, P13VEDP212,x2 DISPLAYPORT 2:1 MUX, QFN

U9390

CRITICAL

341S2899

IC,T29 EEPROM,K92

CRITICAL

1

T29ROM:PROG

U3690

335S0724

1

CRITICAL

GPUROM:BLANK

IC,GPU ROM,K91/F,K92

U8701

IC,GPU ROM,K91/F,K92

U8701

1

CRITICAL341S2957

GPUROM:PROG

CRITICAL

IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA

336S0042

1

GMUX_BLANK

U9600

343S0534

U3900

1

CRITICAL

ENET:B0

IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN 8X8

IC,SMC,DEVELOPMENT-EVT,K92

1

CRITICAL

U4900

341S2862

SMC_PROG:EVT

LBL,P/N LABEL,PCB,28MM X 6 MM

1

EEEE_DG62

CRITICAL826-4393

[EEEE_DG62]

826-4393 CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DG60]

EEEE_DG60

826-4393

EEEE_DG5Y

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DG5Y]

337S4032

IC,CPU,SNB,SR00W,PRQ,D2,2.2,45W,4+2,1.30,6M,BGA

CPU:2_2GHZ

CRITICAL

1

U1000

4

333S0572 CRITICAL

IC,SGRAM,GDDR5,64MX32,3.6GBPS,M-DIE,HF

U8400,U8450,U8500,U8550

FB_1G_HYNIX

IC,PCH,COUGARPOINT SLH9D,PRQ,BD82HM63

U1800

CRITICAL

1

337S4029

SMC_BLANK

U4900

CRITICAL338S0895

1

IC,SMC,HS8/2117,9MMX9MM,TLP

ALL

Silver alt to Gold short pogo pins

870-1699870-2015

U3990

341S2685

IC,ENET ROM,PROTO1,K92

CRITICAL

1

ENETROM_PROG:A0_SD

155S0329155S0457

MAG LAYERS ALT TO MURATAALL

ALL

516S0806516S0805

FOXCONN ALT TO MOLEX

353S2805 353S2603

ALL

Fairchild 8’ alt to 6’wafer

127S0060

Rohm alt to Kemet

ALL

127S0111

157S0055157S0058

ALL

Delta alt to TDK Magnetics

341S2934

BOOTROM_PROG:PROTO1

CRITICAL

1

U6100

IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92

U4900

1

CRITICAL341S2865

IC,SMC,DEVELOPMENT-DVT,K92

SMC_PROG:DVT

Pericom alt to NXP DP Mux

ALL

353S3151353S3055

152S0796152S0915

MAG LAYERS ALT TO CYNTECALL

IC,EEPROM,SERIAL,8KB,SOIC

CRITICAL

1

335S0777

T29ROM:BLANK

U3690

152S0518

MAG LAYERS ALT TO CYNTEC

152S0896

ALL

Silver alt to Gold tall pogo pins

870-1939 870-1698

ALL

341S2384

IR,ENCORE II, CY7C63833-LFXC

CRITICAL

1

U4800

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

[EEEE_DG61]

EEEE_DG61

IC,SGRAM,GDDR5,32MX32.1.25GHz,E-DIE,HF

FB_512_SAMSUNG

4

U8400,U8450,U8500,U8550

333S0543 CRITICAL

IC,CPU,SNB,SR00U,PRQ.D2,2.3,45W,4+2,1.30,8M,BGA

1

337S4033

U1000

CRITICAL

CPU:2_3GHZ

1

SMC_PROG:PROTO1

341S2855

U4900

CRITICAL

IC,SMC,DEVELOPMENT-PROTO1,K92

376S0613

ALL

radar8515240 Toshiba FET

376S0855

152S0905

Cyntec (used on K90i) as alt

ALL

152S1307

ST Micro alt to LT

ALL

353S1658353S3085

K92_COMMON

ALTERNATE,COMMON,K92_COMMON1,K92_COMMON2,K92_PROGPARTS

SNB_CPT_XDP

XDP,XDP_CONN,XDP_CPU_BPM,XDP_PCH

K92_PVT

VREFMRGN_NOT,XDP,XDP_CPU_BPM,BMON:PROD

639-1466

K92_COMMON,CPU:2_3GHZ,FB_1G_SAMSUNG,EEEE_DG62

PCBA,MLB,CFG3,K92

639-1464

PCBA,MLB,CFG2,K92

K92_COMMON,CPU:2_2GHZ,FB_1G_HYNIX,VRAM_HYNIX,EEEE_DG60

PCBA,MLB,K92639-1303

K92_COMMON,CPU:2_2GHZ,FB_1G_SAMSUNG,EEEE_DG5Y

SYNC_DATE=04/26/2010

SYNC_MASTER=K17_MLB

BOM Configuration

ENETROM_PROG:B0_NOSD

CRITICAL

U3990

IC,ENET ROM, PROTO2, EVT,DVT,PVT,K92

1

341S3027

341S3024

1

U5701

TPAD_PROG:EVT

CRITICAL

IC,TP PSOC,proto1,EVT,K90,K90i,K91,K91F,K92T

1

341S3024 CRITICAL

U5701

TPAD_PROG:DVTPVT

IC,TP PSOC,proto1,DVT,pVT,K90,K90i,K91,K91F,K92T

1

TPAD_PROG:PROTO2

341S3024

U5701

CRITICAL

IC,TP PSOC,proto2,K90,K90i,K91,K91F,K92T

CRITICAL341S2902

U5701

IC,TP PSOC,PROTO,K90,K90i,K91,K91F,K92

TPAD_PROG:PROTO1

1

335S0539

U3990

ENETROM_BLANK

CRITICAL

1

IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC

IC,EFI,ROM,PVT, K90/K90I/K91/K91F/K92

1

U6100

CRITICAL

BOOTROM_PROG:PVT

341S2896

1

341S2895 CRITICAL

U6100

IC,EFI,ROM,DVT, K90/K90I/K91/K91F/K92

BOOTROM_PROG:DVT

341S2894

U6100

CRITICAL

IC,EFI,ROM,EVT, K90/K90I/K91/K91F/K92

BOOTROM_PROG:EVT

1

IC,SMC,DEVELOPMENT-PVT,K92

U4900

341S2868

1

CRITICAL

SMC_PROG:PVT

CRITICAL

1

341S2995

IC,SMC,DEVELOPMENT-PROTO2,K92

U4900

SMC_PROG:PROTO2

SMC_PROG:PROTO0

CRITICAL

IC,SMC,DEVELOPMENT-PROTO,K92

1

341S2855

U4900

ALL

add NEC part as 2nd source

128S0264128S0327

add Murata part as 2nd source

138S0676

ALL

138S0691

add ROHM part as 2nd source

376S0972

ALL

376S0612

add new part as 2nd source

376S0859376S0977

ALL

138S0681 138S0638

ALL

add new part as 2nd source

5 OF 132 5 OF 105

NBC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

2 TPs

J5713 (KEY BOARD CONN)

2 TPs

J6781 (LEFT SPEAKER)

NO_TEST=TRUE

2 TP needed

J5800 (IPD FLEX CONN)

J3500 (EXPRESS CARD CONN)

2 TP needed

6 TP needed

2 TPs

FUNC_TEST

4 TPs

NC NO_TESTs

NO_TEST

J4501 (SATA HDD CONN)

3 TPs

J5815 (KBD BACKLIGHT CONN)

3 TPs

4 TPs

J6900 (DC POWER CONN)

J6995 (BAT LED CONN)

3 TPs

4 TPs

J4500 (SATA ODD CONN)

5 TPs

J6780 (MIC FR CONN)

2 TPs 2 TPs 2 TPs

J4800 (FRONT CABLE CONN)

5 TPs

J6950 (MAIN BATT CONN)

FUNC_TEST

J6783 (MIC BK CONN)

J5660 (RIGHT FAN CONN)

2 TPs

NC NO_TESTs

2 TPs

3 TP needed

J3401(AIRPORT/BT CONN)

2 TPs

J6782 (RIGHT & SUB SPEAKER)

J9000 (LVDS CONN)

POWER RAILS

has TP

NO_TEST

NC NO_TESTs

NO_TEST=TRUE

2 TPS

5 TPs

FUNC_TEST

J5650 (LEFT FAN CONN)

Functional Test Points

J3402 (CAMERA/ALS CONN)

I1000

I1001 I1002

I1003

I1004

I1005

I1006

I1007

I1008

I1009

I1010

I1011

I1012

I1013

I1014

I1015 I1016

I1017

I1018 I1019

I1020

I1021

I1022

I1024

I1025

I1026

I1027

I1028

I1029

I1031

I1032

I1033

I1050

I1051

I1052

I1053

I1054

I1055

I1056

I1057

I1058

I1059

I1060

I1061

I1062

I1063

I1064

I1065

I1066

I1067

I1068 I1069

I1070

I1071

I1072

I1073

I1074

I1075

I1076 I1077

I1078

I1079

I1080

I1081

I1082 I1083

I1084

I1085 I1086

I1087

I1088

I1089

I1090 I1091

I1092 I1093

I1094

I1095

I1096

I1097

I1098

I1099 I1100

I1101

I1102

I1103

I1104

I1105

I1106

I1107

I1108

I1109

I1110 I1111

I1112

I1113 I1114

I1115

I1116

I1117

I1131

I1132

I1134

I1135

I1136

I1137

I1140

I1141

I1142

I1143

I1145

I1146

I1148

I1149

I1150

I1151

I1152

I1273

I1436

I1437

I1438

I1439

I1440

I1441

I1442

I1443

I1444

I1445

I1446

I1447

I1448

I1449

I1450

I1451

I1472

I1473 I1474

I1475 I1476

I1478

I1479

I1484 I1485

I1486

I1488

I1490

I1491

I1492

I1539

I1540

I1541 I1542

I1543 I1544

I1545

I1546

I1547

I1548

I1549 I1550

I1561

I1599 I1600

I1601

I1602

I557

I558

I559

I985

I986

I987

I988

I989

I990

I991

I992

I993

I994

I995 I996

I997 I998

SYNC_DATE=04/26/2010

Functional / ICT Test

SYNC_MASTER=K17_MLB

LVDS_CONN_A_CLK_F_P

TRUE

LVDS_DDC_DATA

TRUE

SATA_HDD_D2R_RDRVR_IN_P

TRUE

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_D2R_C_P

TRUE

FAN_LT_PWM

TRUE

FAN_LT_TACH PP5V_S0

TRUE

PP1V8_S0

TRUE

SATA_HDD_D2R_RDRVR_IN_N

MAKE_BASE=TRUE

NC_SDVO_TVCLKINP

TRUE

NC_SDVO_STALLN

TRUE MAKE_BASE=TRUE

TRUE

PP3V3_S0

SMC_RX_L

TRUE

SMC_TCK

TRUE

WS_KBD5

NC_BCM57765_TRAFFICLED_L

SYS_LED_ANODE_R

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_AD<0..3>

TRUE

SPI_ALT_MOSI

TRUE

SPI_ALT_MISO

TRUE

SATA_HDD_D2R_RDRVR_OUT_N

TRUE

SATA_HDD_D2R_RDRVR_OUT_P

LPC_FRAME_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

SMC_TRST_L

TRUE

SMC_TX_L

TRUE

SPI_ALT_CLK

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

SMC_MD1

SPIROM_USE_MLB

TRUE

SPI_ALT_CS_L

TRUE

TP_DVPCLK

NC_FW0_TPBP

NC_FW2_TPBP

TP_FW643_AVREG

MAKE_BASE=TRUE

NC_FW643_AVREG NC_FW643_TDI

MAKE_BASE=TRUE

NC_FW0_TPAP

TRUE

DMI_N2S_N<1>

TRUE

SPKRAMP_BR_OUT_N

SPKRAMP_LFE_OUT_N

TRUE

NC_FW2_TPBN

NC_FW2_TPAN

NC_DP_IG_C_HPD

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

NC_DP_IG_C_MLN<3..0>

TRUE

NC_DP_IG_D_MLP<3..0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLN<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_CTRL_DATA

NC_DP_IG_D_HPD

NC_DP_IG_C_AUXN

NC_DP_IG_C_AUXP

NC_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

TRUE

NC_FW0_TPBN

TP_DC_TEST_A4

TRUE

TP_DC_TEST_D1

TRUE TRUE

TP_EDP_TX_P<3..0>

TRUE

TP_T29_SENSOR_ALERT

TRUE

DMI_S2N_P<1..0>

TRUE

DMI_N2S_P<1>

TRUE

DMI_N2S_N<3>

TRUE

DMI_N2S_P<3>

TRUE

DMI_S2N_N<1..0>

TRUE

TP_DVPDATA<23..0>

TRUE

TP_GPU_JTAG_TRST_L

TRUE

TP_DVPCNTL<2..0>

TRUE

ISSP_SDATA_P1_0

MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

TRUE

SATA_HDD_R2D_RDRVR_OUT_P

TRUE

SATA_HDD_R2D_RDRVR_IN_N

TRUE TRUE

SATA_HDD_R2D_RDRVR_IN_P

TRUE

SATA_HDD_R2D_C_N

TRUE

SATA_HDD_R2D_C_P

TRUE

SATA_HDD_D2R_N

TRUE

SATA_HDD_D2R_P

NC_SATA_SSD2_R2D_CP

TRUE

SATA_HDD_R2D_UF_P

TRUE

SATA_HDD_R2D_UF_N

NC_SATA_SSD2_R2D_CN

NC_SATA_SSD2_D2RN NC_SATA_SSD2_D2RP

NC_SATA_D_R2D_CN

NC_SATA_D_D2RN NC_SATA_D_D2RP

TRUE

SATA_HDD_R2D_RC_UF_N SATA_HDD_R2D_RC_UF_P

TRUE

SATA_HDD_R2D_UF_N

TRUE

SATA_HDD_R2D_UF_P

TRUE

SATA_HDD_R2D_RDRVR_OUT_N

TRUE

T29_A_BIAS_R2D_P0

TRUE

T29_A_BIAS_R2D_N1

TRUE

T29_A_BIAS_R2D_P1

TRUE

T29_A_BIAS_R2D_N0

TRUE

DP_A_BIAS_N_0

TRUE TRUE

DP_A_BIAS_P_0

TRUE

DP_A_BIAS_N_2

TRUE

DP_A_BIAS_P_2

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

TP_NV_WE_CK_L<1..0>

T29_D2R1_BIAS

TRUE

DP_EXTA_ML_P<3..0>

TRUE

TP_NV_DQS<1..0>

PCIE_AP_R2D_P

TRUE

WS_KBD20

TRUE

WS_KBD23

WS_KBD18

TRUE

WS_KBD14

TRUE

PCIE_AP_R2D_N

TRUE

WS_KBD10

TRUE

WS_LEFT_SHIFT_KBD

WS_CONTROL_KBD

TRUE

SATA_ODD_D2R_UF_P

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4P

PP1V8_S0GPU

TRUE

PPVCORE_GPU

TRUE

PP1V8_S0GPU_ISNS_R

TRUE

PP3V3_S0GPU

TRUE

PPVP_FW

TRUE

PPVTTDDR_S3

TRUE

PP3V3_S3

EXCARD_CPPE_L

TRUE

SPKRAMP_BL_OUT_N

TRUE

NC_PCI_CLK33M_OUT3

TRUE

TP_T29_PCIE_RESET0_L

TRUE

T29DPA_D2R1_AUXCH_P

NC_PCI_PAR

T29DPA_ML_P<3..0>

TRUE

WS_KBD16_NUM

TRUE

WS_KBD15_CAP

NC_CE_L_MS_INS_L NC_CE_L_MS_INS_L

MAKE_BASE=TRUE

TRUE

NC_PCH_TP2

MAKE_BASE=TRUE

TRUE

NC_GPU_BUFRST_L

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_CTRL_CLK

NC_DP_IG_C_HPD

NC_CRT_IG_GREEN

TRUE MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

TRUE

NC_SMC_FAN_3_TACH

TRUE

SPKRAMP_BR_OUT_P

TRUE

SPKRAMP_FR_OUT_N

TRUE

SPKRAMP_BL_OUT_P

TRUE

SPKRAMP_FL_OUT_N

TRUE

SPKRAMP_FL_OUT_P

TRUE

PP5V_S0

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

PCIE_WAKE_L

TRUE

PP3V3_S3_EXCARD_SWITCH

WIFI_EVENT_L

TRUE

FAN_RT_PWM

TRUE

AUD_DMIC_SDA_BK

TRUE

LPCPLUS_GPIO

MAKE_BASE=TRUE

TRUE

NC_PCH_TP1

NC_PCH_TP3

TRUE

MAKE_BASE=TRUE

NC_PCH_TP4

TRUE

MAKE_BASE=TRUE

NC_PCH_TP9

NC_PCH_TP12

DP_SDRVA_ML_C_N<2>

TRUE

WS_KBD22

TRUE

ISSP_SCLK_P1_1

TRUE

PM_SYSRST_L

TRUE

LCD_BKLT_PWM

SMC_TDI

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

SMBUS_SMC_A_S3_SCL

SMC_NMI

TRUE

SMC_ONOFF_L

PPVBAT_G3H_CONN

TRUE

PP3V42_G3H_LIDSWITCH_R

TRUE

PP5V_S3_IR_R

TRUE TRUE

SMC_LID_R

TRUE

IR_RX_OUT SYS_LED_ANODE

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SCL

TRUE

NC_SATA_C_R2D_CN

NC_SATA_C_D2RN

Z2_CLKIN

TRUE

PSOC_F_CS_L

TRUE

PSOC_SCLK

TRUE

PSOC_MOSI

TRUE

PSOC_MISO

TRUE

PICKB_L

TRUE

PP3V3_S3

TRUE

T29_R2D_C_N<1..0>

TRUE

T29_R2D_C_P<1..0>

TRUE

SPKRAMP_FR_OUT_P

TRUE

PPVOUT_S0_LCDBKLT

TRUE

SPKRAMP_LFE_OUT_P

TRUE

AUD_DMIC_CLK_BK

TRUE

AUD_DMIC_CLK_FR

TRUE

AUD_DMIC_PWR_FR

TRUE

LED_RETURN_5

TRUE

LED_RETURN_6

LED_RETURN_4

TRUE

LED_RETURN_3

TRUE

LED_RETURN_2

TRUE

LED_RETURN_1

LVDS_CONN_B_CLK_F_N

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

LVDS_CONN_B_DATA_N<2>

TRUE

LVDS_CONN_B_DATA_N<1>

TRUE

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<0>

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_CONN_B_DATA_P<0>

TRUE

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_A_DATA_P<2>

TRUE

LVDS_CONN_A_DATA_P<1>

TRUE TRUE

LVDS_CONN_A_DATA_N<1>

TRUE

LVDS_CONN_A_DATA_N<0>

TRUE

SATA_ODD_R2D_N

TRUE

SATA_ODD_R2D_P

TRUE

SATA_ODD_D2R_UF_N

SMC_ODD_DETECT

TRUE

PP5V_SW_ODD

TRUE

IR_RX_OUT

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_R2D_N

TRUE

SMC_LID_R

TRUE

SMC_BIL_BUTTON_L

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SDA

TRUE

PP3V42_G3H

TRUE

PP18V5_DCIN_FUSE

ADAPTER_SENSE

TRUE

KBDLED_ANODE

TRUE

SMC_KDBLED_PRESENT_L

TRUE

SMC_TDO

TRUE

PP5V_S0_HDD_FLT

PPBUS_G3H

TRUE

PM_SLP_S3_L

TRUE

PPVCORE_S0_CPU

PP5V_S0

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PPDCIN_G3H

TRUE

PP18V5_S4

LPCPLUS_RESET_L

TRUE

SMC_RESET_L

NC_NV_CLE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CN

NC_SATA_D_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_SSD2_D2RN

NC_BCM57765_TRAFFICLED_L

TRUE

MAKE_BASE=TRUE

PCH_VSS_NCTF<2>

TRUE

NC_PCH_TP1

NC_PCH_TP3

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TRUE

NC_BCM57765_SPD100LED_L NC_BCM57765_SPD100LED_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N

TRUE

NC_PCIE_CLK100M_PE7P

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RN

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_SSD2_D2RP

NC_SATA_D_R2D_CP

NC_SATA_C_D2RP

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6N

TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

TRUE

TP_NV_WR_RE_L<1..0>

NC_NV_CLE

NC_NV_DQS<1..0>

TRUE MAKE_BASE=TRUE

TP_NV_DQ<15..0>

MAKE_BASE=TRUE

NC_NV_DQ<15..0>

TRUE

NC_NV_CE_L<3..0>

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK33M_OUT3

TRUE

MAKE_BASE=TRUE

NC_PCI_PME_L

TRUE MAKE_BASE=TRUE

NC_PCI_PME_L

TRUE

MAKE_BASE=TRUE

NC_PCI_PAR

NC_PCI_RESET_L NC_PCI_RESET_L

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT0_L

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT0_L

NC_PCI_GNT2_L

TRUE MAKE_BASE=TRUE

NC_PCI_GNT2_L

NC_PCI_GNT1_L NC_PCI_GNT1_L

MAKE_BASE=TRUE

TRUE

TP_PCI_AD<31..0> NC_PCI_AD<31..0>

MAKE_BASE=TRUE

TRUE

TP_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

NC_PCI_C_BE_L<3..0>

TRUE

NC_PCI_GNT3_L

TRUE MAKE_BASE=TRUE

NC_PCI_GNT3_L

NC_HDA_SDIN3

NC_HDA_SDIN2 NC_HDA_SDIN2

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

NC_LVDS_IG_CTRL_DATA

NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_CLK

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

TRUE

NC_CRT_IG_DDC_DATA

NC_CRT_IG_RED

TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

NC_CRT_IG_GREEN

NC_CRT_IG_BLUE

NC_FW643_TDI

TP_DP_IG_D_MLN<3..0>

TP_DP_IG_D_MLP<3..0>

NC_DP_IG_D_CTRL_CLK

NC_DP_IG_D_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLP

TRUE

NC_GPU_GSTATE<0>

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<1>

MAKE_BASE=TRUE

TRUE

NC_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_LVDS_EG_B_CLKN

MAKE_BASE=TRUE

TRUE

NC_LVDS_EG_B_CLKP NC_LVDS_EG_BKL_PWM

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

TRUE

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_DE

TRUE

PCH_VSS_NCTF<29>

TRUE

PCH_VSS_NCTF<27>

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<15>

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<7>

TRUE

PCH_VSS_NCTF<5>

NC_PCH_TP5

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

TRUE

MAKE_BASE=TRUE

NC_PCH_TP6

TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP8

MAKE_BASE=TRUE

TRUE

NC_PCH_TP11

MAKE_BASE=TRUE

TRUE

NC_PCH_TP12

MAKE_BASE=TRUE

TRUE

NC_PCH_TP9

MAKE_BASE=TRUE

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_PCH_TP18

MAKE_BASE=TRUE

TRUE

NC_PCH_TP17

MAKE_BASE=TRUE

TRUE

NC_PCH_TP15

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

TRUE

MAKE_BASE=TRUE

NC_PCH_NC4

TRUE

MAKE_BASE=TRUE

NC_PCH_NC2

MAKE_BASE=TRUE

TRUE

NC_PCH_TP19

TRUE

MAKE_BASE=TRUE

NC_PCH_NC5

TRUE

MAKE_BASE=TRUE

NC_PCH_NC1

TRUE

MAKE_BASE=TRUE

NC_PCH_SST

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTP

NC_DP_IG_D_AUXP

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

TRUE MAKE_BASE=TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<1>

TRUE

NC_LVDS_EG_BKL_PWM

NC_LVDS_EG_B_CLKP

NC_LVDS_EG_B_CLKN

TP_LVDS_IG_B_CLKN

NC_PCH_NC2

NC_PCH_NC1

NC_DP_IG_D_AUXP

NC_SDVO_TVCLKINP

NC_SDVO_INTN

NC_SDVO_STALLP

NC_PCH_SST

NC_SDVO_STALLN

NC_PCH_TP17

NC_PCH_TP14

NC_PCH_TP15

NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18

NC_PCH_TP16

NC_PCH_TP13

NC_PCH_TP11

NC_PCH_TP8

NC_DP_IG_C_CTRL_DATA

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_C_MLP<3..0>

NC_PCH_TP6

NC_PCH_TP7

NC_PCH_TP5 NC_PCH_TP4

TP_GPU_MIOA_D<9..0>

NC_SDVO_INTP

NC_GPU_BUFRST_L NC_GPU_GSTATE<0> TP_GPU_GSTATE<1>

NC_GPU_MIOA_DE

TP_LVDS_IG_B_CLKP

NC_HDA_SDIN3

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCH_LVDS_VBG

NC_CRT_IG_DDC_DATA

TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

MAKE_BASE=TRUE

TRUE

NC_PCH_LVDS_VBG

NC_CRT_IG_VSYNC

NC_CRT_IG_HSYNC

NC_CRT_IG_RED

TRUE

SYS_LED_ANODE_R

TRUE

PP5V_S3_IR_R

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_R2D_P

PP3V42_G3H

TRUE

PCIE_AP_D2R_P

AP_RESET_CONN_L

TRUE

SMBUS_SMC_0_S0_SDA

TRUE

SMBUS_SMC_0_S0_SCL

TRUE

USB_BT_P

TRUE

USB_BT_N

TRUE

USB_CAMERA_CONN_P

SMBUS_PCH_CLK

TRUE

PP3V3_S0_EXCARD_SWITCH

TRUE

SMBUS_PCH_DATA

TRUE

USB2_EXCARD_CONN_N

TRUE

USB2_EXCARD_CONN_P

TRUE

EXCARD_CLKREQ_CONN_L

TRUE

EXCARD_CPUSB_L

PLT_RESET_SWITCH_L

TRUE TRUE

PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N

TRUE

PCIE_EXCARD_R2D_N

TRUE

PCIE_EXCARD_R2D_P

TRUE

PCIE_CLK100M_EXCARD_CONN_P

TRUE

PCIE_CLK100M_EXCARD_CONN_N

TRUE

PP3V3_S4

TRUE

PP18V5_S4

TRUE

Z2_CS_L Z2_DEBUG3

TRUE

Z2_MISO

TRUE

Z2_MOSI

TRUE

SMBUS_SMC_BSA_SDA

TRUE

AUD_DMIC_SDA_FR

FAN_RT_TACH

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

DP_T29SNK0_ML_C_P<3..0>

TRUE

DP_T29SNK0_ML_N<3..0>

TRUE

DP_T29SNK1_ML_P<3..0>

TRUE

DP_T29SNK0_ML_C_N<3..0>

TRUE

DP_T29SNK0_ML_P<3..0>

TRUE

DP_T29SNK1_ML_C_P<3..0>

TRUE

DP_T29SNK1_AUXCH_P

TRUE

DP_T29SNK1_AUXCH_C_N

TRUE

DP_T29SNK1_AUXCH_C_P

TRUE

DP_T29SNK1_AUXCH_N

TRUE

DP_T29SNK1_ML_C_N<3..0>

TRUE

TP_DP_T29SRC_AUXCH_CN

TRUE

TP_DP_T29SRC_ML_CN<3..0>

TRUE

DP_SDRVA_ML_C_N<0>

TRUE

DP_T29SNK1_ML_N<3..0>

TRUE

DP_SDRVA_ML_C_P<2>

TRUE

DP_SDRVA_ML_N<2>

TRUE

DP_SDRVA_ML_P<2>

TRUE

DP_SDRVA_ML_N<0>

TRUE

DP_SDRVA_ML_P<0>

DP_SDRVA_ML_C_P<0>

TRUE

TP_DP_T29SRC_ML_CP<3..0>

TRUE

TP_DP_T29SRC_AUXCH_CP

TRUE

PP1V5_S0_EXCARD_SWITCH

LVDS_CONN_A_DATA_P<0>

TRUE

LVDS_DDC_CLK

PP3V3_SW_LCD

TRUE

WS_KBD21

TRUE

WS_KBD19

WS_KBD17

TRUE

NC_FW2_TPAP

NC_FW2_TPBIAS

NC_SMC_FAN_2_CTL

TRUE

NC_SMC_FAN_2_TACH

TRUE

PP5V_S3

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_PCH_TP13

MAKE_BASE=TRUE

TRUE

NC_PCH_TP16

TRUE

MAKE_BASE=TRUE

NC_PCH_NC3

TP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTN

NC_SDVO_TVCLKINN

TRUE

T29_D2R_P<1..0> T29_D2R_N<1..0>

TRUE

DP_T29SNK0_AUXCH_N

TRUE

DP_T29SNK0_AUXCH_C_P

T29DPA_ML_N<3..0>

TRUE

T29_R2D_N<1..0>

TRUE

NC_DP_IG_D_AUXN

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXN

SMBUS_SMC_A_S3_SCL

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

PCIE_WAKE_L

TRUE

PP3V3_WLAN

TRUE

AUD_DMIC_PWR_BK

TRUE

USB_CAMERA_CONN_N

PP3V3_S3_BT_F

TRUE

AP_CLKREQ_Q_L

TRUE

PCIE_CLK100M_AP_CONN_N

PP3V42_G3H

TRUE

WS_KBD4

WS_KBD3

TRUE

WS_KBD2

TRUE

WS_KBD1

TRUE

WS_KBD_ONOFF_L

TRUE

WS_LEFT_OPTION_KBD

TRUE

Z2_BOOST_EN

WS_KBD13

TRUE

WS_KBD12

TRUE

WS_KBD11

TRUE

DP_SDRVA_ML_R_P<0>

TRUE

DP_SDRVA_ML_R_N<2>

TRUE

DP_SDRVA_ML_R_P<2>

TRUE

DP_A_BIAS DP_SDRVA_ML_R_N<0>

TRUE

T29DPA_D2R1_AUXCH_N

TRUE

TP_T29_PCIE_RESET3_L

TRUE

TP_T29_PCIE_RESET2_L

T29_R2D_P<1..0>

TRUE

DP_T29SNK0_AUXCH_P

TRUE

DP_T29SNK0_AUXCH_C_N

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

PP3V3_S4

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_DATA

TRUE

TP_DVPCNTL_M<1..0>

TRUE

T29_D2R_C_N<1..0>

T29_D2R_C_P<1..0>

TRUE

MAKE_BASE=TRUE

NC_NV_ALE

NC_NV_RB_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_NV_WR_RE_L<1..0>

TRUE

MAKE_BASE=TRUE

NC_NV_WE_CK_L<1..0>

TRUE

NC_SATA_C_D2RP

NC_PSOC_P1_3

NC_PCIE_CLK100M_PE7P

NC_PCIE_CLK100M_PE7N

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_PE5N

NC_SATA_C_R2D_CP

Z2_KEY_ACT_L

TRUE

Z2_RESET

TRUE

Z2_HOST_INTN

TRUE

Z2_SCLK

TRUE

PCIE_AP_D2R_N

TRUE

NC_NV_RB_L

NC_NV_ALE

TP_NV_CE_L<3..0>

TP_T29_PCIE_RESET1_L

TRUE

PP3V3_S0

TRUE

PP1V2_S0

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

7 OF 132 6 OF 105

83 99

83 84

41 94

6

41 94

6

41 94

52

6 7 8 22 41

47

52 54 65 68 69 70 73 87

104 105

7

14 20 25 71 72

88

102

41 94

6

17

6

17

6 7

12

23 25 26 28

32 35 36

39 40 41

46 48 49

50 51 52

54 57 61

62 72 73 80

83 84 85

88 89 91

100 102

42 45 46 47

45 46 47

53

6

36

6

44

25 47 95

16 45 47 88 95

47

41 94

16 45 47 88 95

17 45 47

45 46 47

45 47

42 45 46 47

47

16 45 47

17 45 47

45 47

19 47 56

47

79

38 40

38

6

38

38 40

9

17 92

60 61

38 40

6

17

6

17

6

17

6

17

6

17

6

17

38 40

12

9

51

9

17 92

9

17 92

9

17 92

9

17 92

9

17 92

79

79 80

79

6

17

41 94

16 41 94

6

41 94

6

41 94

6

16

6

16

6

16

41 94

6

41 94

6

41 94

8

85

8

85

8

85

8

85

8

85

8

85

8

85

8

85

6

85

31 95

53

31 95

53

41 94

6

7

75 79 81

103

7

49 75 82

7

72

103

7

72 75 79 80 82

84

7

39 40

7

30 67

6 7 8

18 24 25 29

30 31 32 48 49 50

54 55

73 88

104

32

60 61

6

18

33

86 97

6

85 86 97

53

6

36

6

36

6

17

6

17

6

17

6

17

45 46

60 61

6 7 8 22 41

47

52

54 65 68 69 70 73 87

104 105

31

6

17 25 31 32 85

32

31 45 46

52

61

19 47

6

85 97

53

17 25 45

88 89

45 46 47

6

31 45 48 54 55 98

6

31 45 48 54 55 98

45 47

45 46 53

63 64

44

6

44

6

44

6

44

44 46

63

6

45 48 63 64 98

6

53 54

6 7 8

18 24 25 29 30

31 32 48 49 50 54 55 73 88

104

33 85 97

60 61

61

83 89

83 99

83 84 99

83 99

83 84 99

41 94

41 45

41

104

6

44

6

41 94

6

44

45 46 63

6

45 48 63 64 98

6

45 48 63 64 98

6 7

25 42 44 45 46 47 48 53 63 64 73

104

63

54

45 46 47

41

7 8

35 39 49 50 63

64 90

17 29 45 73

7

12 14 49 69

105

6 7 8

22 41 47 52

54 65 68 69 70 73

87

104 105

45 46

7

49 63 64

6

54

25 47 88 95

45 46 47 64

6

16

6

16

6

16

6

16

6

36

6

16

6

36

6

36

6

19

6

19

6

16

6

53

6

19

6

19

6

16

6

18

6

18

6

18

6

6 6

6

16

6

16

6

16

6

16

6

18

6

18

6

18

6

17

6

17

6

17

6

17

6

17

6

17

6

38

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

8

18

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

8

18

6

16

6

18

6

17

6

17

6

17

6

17

6

16

6

18

6

17

6

17

6

17

6

44

6

44

6

41 94

6 7

25 42 44 45 46

47 48 53 63 64 73

104

16 31 95

31

31 45 48 51 80 98

24 31 94

31 94

16 23 26 28 30 32 41 48 62 89 95

32

16 23 26 28 30 32 41 48 62 89 95

32

100

32

100

32

16 32

100

16 32

100

32

100

32

100

32

100

32

100

6 7

46 53 54 72

6

54

53 54

6

45 48 63 64 98

31

100

33 79 97

33 97

33 79 97

33 97

33 79 97

33 97

33 79 97

33 97

33 79 97

33

85 97

33 97

85 97

33

32

83 84 99

53

38 40

45 46

6

8

18

6

17

6

17

33 85 97

33 97

33 79 97

85 86 97

85 97

6

17

6

17

6

31 45 48 54 55 98

6

31 45 48 54 55 98

6

17 25 31 32 85

31 46

61

31 94

31

100

6 7

25 42

44 45 46 47

48 53 63 64

73

104

53

54

53

85 97

85

85 97

86 97

33

85 97

33 97

33 79 97

53

6 7

46 53 54 72

6

18

79

85 86 97

6

53

6

19

6

19

6

19

6

19

6

16

6

16

6

53 54

16 31 95

6

33

6 7

12 23 25 26 28

32 35 36

39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91

100 102

7 71

88

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

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8 7 5 4 2 1

T29 Rails

"FW" (FireWire) Rails

3.3V/1.8V Rails

1.5V/1.05V Rails

? mA

Chipset Rails

5V Rails

ENET Rails

DDR Rails

"GPU" Rails

"G3Hot" (Always-Present) Rails

SYNC_DATE=04/26/2010

Power Aliases

SYNC_MASTER=K17_MLB

PP15V_T29

MAKE_BASE=TRUE

VOLTAGE=15V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP15V_T29

PPVIN_S5_HS_COMPUTING_ISNS

PP5V_S5 PP5V_S5

PP3V3_S0

PPVCCSA_S0_CPU

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP5V_S0 PP5V_S0

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

PP3V42_G3H

PP3V3_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

PPBUS_G3H

PPVIN_S5_HS_GPU_ISNS

PPDCIN_G3H

PP3V3_S5

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_S4PP3V3_S4

PP3V3_S4

PP3V3_S5_ISNS_R

PP3V3_SUS PP3V3_SUS

PPBUS_G3H

PPVIN_S5_HS_COMPUTING_ISNS

PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS

PP3V3_S5 PP3V3_S5 PP3V3_S5

VOLTAGE=12.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_HS_OTHER_ISNS

PPVP_FW

PP3V3_T29

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_T29

PPBUS_G3H

PP5V_S3

PP5V_S3_ISNS_R

PPVIN_S5_HS_GPU_ISNS

PP3V3_S3 PP3V3_S3 PP3V3_S3

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S3_ISNS_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S0

PP1V5_S0

PPVIN_S5_HS_OTHER_ISNS

PP3V3_S0GPU

PPVCORE_GPU

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.15V MAKE_BASE=TRUE

PP1V05_S0

PP1V5_S3

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S3RS0_CPUDDR

PP1V5R1V35_GPU_FB_ISNS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0GPU

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.8V

PP1V8_S0GPU_ISNS_R

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V0_S0GPU

MAKE_BASE=TRUE

VOLTAGE=1.0V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 MM

PP1V5_S3RS0

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0GPU

PPVCORE_GPU

PP1V05_S0_CPU_VCCPQE

PP1V5_S3RS0

PP1V0_S0GPU

PP1V8_S0GPU

PP1V5_S3

PP1V5_S3 PP1V5_S3

PP1V5_S3

PP1V8_S0GPU

PP0V75_S0_DDRVTT

PP1V5R1V35_GPU_FB_ISNS

PP1V5_S0GPU_ISNS_R

PP3V3_S0GPU

PP1V0_S0GPU_ISNS_R

PP1V8_S0GPU_ISNS_R

PP1V8_S0GPU

PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU

PP1V0_S0GPU

PP1V8_S0GPU

PP1V5_S3

PP1V5_S3RS0_CPUDDR

PPVTTDDR_S3

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S3RS0_CPUDDR

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0.75V MAKE_BASE=TRUE

PPVTTDDR_S3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0_CPU_VCCPQE

VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V8_S0GPU

PP1V8_S0GPU_ISNS_R

PP1V0_S0GPU

PP1V0_S0GPU_ISNS_R

PP1V5_S3RS0_CPUDDR

PP3V3_S0GPU

PP0V75_S0_DDRVTT

VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 MM

PP1V5_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5R1V35_GPU_FB_ISNS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V5_S0GPU_ISNS_R

PP5V_S5

PPVRTC_G3H

PP1V2_S0

PP3V3_S0GPU

MAKE_BASE=TRUE

VOLTAGE=1.0V

PP1V0_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V5R1V35_GPU_FB_ISNS

MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.3V

PP3V3_S0GPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V5_S3

VOLTAGE=1.5V

PPVRTC_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PPVRTC_G3H

PPDCIN_G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H

MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_HS_GPU_ISNS

PP3V42_G3H

PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_LINE_WIDTH=0.3 MM

PP3V42_G3H

MIN_NECK_WIDTH=0.2 MM

PP5V_S5

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.3 MM

PP5V_S5

MIN_NECK_WIDTH=0.2 MM

PP5V_S3

PP5V_S3 PP5V_S3

PP5V_S3 PP5V_S3 PP5V_S3

PP5V_S3_ISNS_R

PP5V_S0 PP5V_S0

PP5V_S0

MIN_LINE_WIDTH=0.5 MM

PP5V_S0_ISNS_R

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S0_ISNS_R

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM

PP5V_SUS

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_SUS

PP3V3_S0 PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP5V_S3

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_ENET

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP3V3_S0

PP3V42_G3H

PPDCIN_G3H

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PPVIN_S5_HS_GPU_ISNS

PP5V_S5

PP1V05_SUS

PPVIN_S5_HS_COMPUTING_ISNS

PP1V2_ENET

PP3V3_S0

PP1V5_S3_CPU_VCCDQ

PP1V05_SUS

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

PP1V05_S0 PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V05_S0 PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V2_S0

MAKE_BASE=TRUE

VOLTAGE=1.2V

PP1V2_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V5_S0

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

PP1V5_S0

MAKE_BASE=TRUE

PP1V8_S0

PP1V8_S0_CPU_VCCPLL_R

PP1V0_FW_FWPHY

MAKE_BASE=TRUE

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_FWPHY

PP3V3_FW_FWPHY

PPVP_FW

PP1V8_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_S0

PPVCORE_S0_CPU

PP3V3_S3

PPVCORE_S0_CPU

MAKE_BASE=TRUE

VOLTAGE=1.1V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

PPVCORE_S0_AXG

MAKE_BASE=TRUE

VOLTAGE=1.05V

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCCSA_S0_CPU

MAKE_BASE=TRUE

VOLTAGE=0.9V

PPVCCSA_S0_CPU

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_ENET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET PP3V3_ENET PP3V3_ENET

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V2_ENET

PP3V3_S3

PPBUS_G3H

PP1V8_S0

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.4 mm

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PP3V3_S5

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVIN_S5_HS_COMPUTING_ISNS

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP1V8_S0

PP3V3_S3

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S3_ISNS_R

PP3V3_S0

PP3V3_S3_ISNS_R

PP3V3_S3

PP3V3_S0

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S3_ISNS_R

PP3V3_S3

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.4 MM

PPVP_FW

PP3V3_S5

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0_CPU_VCCPLL_R

PP0V75_S0_DDRVTT

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5_ISNS_R

PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS

PP3V3_S3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_SUS

VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_SUS

PP3V3_S5_ISNS_R

PP3V3_S4

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY

PP3V3_S5

PPBUS_G3H

PP3V3_T29 PP3V3_T29 PP3V3_T29 PP3V3_T29

PP1V05_T29

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PP3V3_T29

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP5V_S5

8 OF 132 7 OF 105

7 8

35 86

7 8

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7 8

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7

50 65

67 68 69

70

7

54 66 72

103 104

7

54 66 72

103 104

6 7

12 23 25 26 28 32 35

36 39 40 41 46 48 49 50

51 52 54 57 61 62 72 73 80 83 84 85 88

89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100

102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

35 39 49 50 63 64 90

7

50 82

87

6 7

49 63 64

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

46 53 54 72

6 7

46 53 54 72

6 7

46 53 54 72

7

66

104

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46

71 72 73

6 7 8

35 39 49 50 63 64 90

7

50 65 67 68 69 70

7

50 65 67 68 69 70

7

50 65 67 68 69 70

7

50 65 67 68 69 70

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

7

50 66

6 7

39 40

6 7

39 40

7

16 19 25 33 34 35 88

7

34 35

6 7 8

35

39 49 50

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6 7

29 31 42 43 44 46 67 72 82

104

7

66

104

7

50 82 87

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

7

66

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

7

16 20

22 25 32 41 57 71

7

50 66

7

50 66

6 7

72 75 79 80 82 84

6 7

49 75 82

7 9

10 12 13 14 23 35

39 45 68 70 73

102 104 105

7

26 28 29 67 72

7

12 15

7

10 13 15 29 73

104

7

75 76 77 78

103

6 7

75 79 81

103

6 7

72

103

7

74 75 79 81

103

7

72

100 104

6 7

72 75 79 80 82 84

6 7

72 75 79 80 82 84

6 7

49 75 82

7

10 12 14

7

72

100 104

7

72

100 104

7

74 75 79 81

103

6 7

75 79 81

103

7

26 28 29 67 72

7

26 28 29 67 72

7

26 28 29 67 72

7

26 28 29 67 72

6 7

75 79 81

103

7

26 28 29 67

7

26 28 29 67

7

75 76 77 78

103

7

75 76 77 78

103

7

75 76 77 78

103

7

87

103

6 7

72 75 79 80 82 84

6 7

72 75 79 80 82 84

7

87

103

6 7

72

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

7

26 28 29 67 72

7

10 13 15 29 73

104

6 7

30 67

7

10 13 15 29 73

104

6 7

30 67

7

10 12 14

6 7

75 79 81

103

6 7

72

103

7

74 75 79 81

103

7

87

103

7

10 13 15 29 73

104

6 7

72 75 79 80

82 84

7

26 28 29 67

7

26 28 29 67

7

87

103

7

75 76 77 78

103

7

87

103

7

54 66 72

103 104

7

16 17

20 25

6 7

72 75 79 80 82 84

6 7

72 75 79 80 82 84

7

87

103

7

75 76 77 78

103

6 7

72 75 79 80 82 84

7

26 28 29 67 72

7

16 17 20 25

7

16 17 20 25

6 7

49 63 64

6 7

49 63 64

7

50 82 87

6 7

25 42 44 45

46 47 48

53 63 64

73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46

47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

7

54 66 72

103 104

7

54 66 72

103 104

7

54 66 72

103 104

7

54 66 72

103 104

7

54 66 72

103 104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42

43 44 46 67 72

82

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

7

66

104

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54

65 68 69 70 73

87

104 105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

7

72

104

7

72

104

7

72

104

7

22 72

7

22 72

7

22 72

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62

72 73 80 83 84 85 88 89 91

100 102 6 7

12 23 25 26 28 32 35 36 39 40 41 46 48

49

50 51 52 54 57 61 62 72 73 80 83 84 85

88

89 91

100 102

6 7 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80

83 84 85 88 89 91

100 102

6 7

12

23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91 100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73

80 83 84 85 88 89 91

100 102 6 7 12 23 25 26 28 32 35 36 39 40 41 46 48

49

50 51 52 54 57 61 62 72 73 80 83 84 85

88

89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89

91

100 102 6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72

73 80 83 84 85 88 89 91

100 102 6 7

12 23 25 26 28 32 35 36 39 40 41 46 48

49

50 51 52 54 57 61 62 72 73 80 83 84 85

88

89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

29 31 42 43 44 46 67 72 82

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91

100 102

7

25 36 71 73

7

12 13 15 49 69

6 7

29 31 42 43 44 46 67 72 82

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50

51 52 54 57 61 62 72 73 80 83 84 85 88

89 91

100 102

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

49 63 64

7

50 82 87

7

54 66 72

103 104

7

23 71

7

50 65 67 68 69 70

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54

57 61 62 72 73 80 83 84 85 88 89 91

100

102

6 7

12 23 25 26 28 32 35 36 39 40 41

46 48 49 50 51 52 54 57 61 62 72 73

80 83 84 85 88 89 91

100 102

6 7 12

23 25 26 28 32 35 36 39 40 41 46 48 49

50

51 52 54 57 61 62 72 73 80 83 84 85 88

89 91

100

102

7

23 71

7

23 71

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10

12 13 14 23 35 39 45 68 70 73

102 104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105 7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105 7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105 7 9

10 12 13 14

23 35 39 45 68 70 73

102 104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105 7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

6 7

71 88

7

16 20 22 25 32 41 57 71

7

16 20 22 25 32

41 57 71

7

16 20 22 25 32 41 57 71

7

16 20 22 25 32 41 57 71

7

16 20 22 25 32 41 57 71

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

7

12 14

7

38 39

7

38 39

7

38 39

7

38 39 40

6 7

39 40

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

6 7

12 14 49 69

105

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7

12 14 49 69

105

6 7

12 14 49 69

105

7

12 13 15 49 69

7

12 13 15 49 69

7

12 15 65

7

12 15 65

7

25 36 71 73

7

25 36 71 73

7

25 36 71 73

7

25 36 71 73

7

36 71

7

36 71

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31

32 48 49 50 54 55 73 88

104

6 7 8

35 39 49 50 63 64 90

6 7

14 20 25 71 72 88

102

6 7 8

35 39 49 50

63 64 90

6 7 8

35 39 49 50 63 64 90

6 7 8

35 39 49 50 63 64 90

6 7 8

35 39 49 50 63 64 90

7

50 65 67 68 69 70

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17

19 20 22 23 24 25 29 46 48 56 71 72 73

83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86

91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

14 20 25 71 72 88

102

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

7

72

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54

57 61

62 72

73 80 83 84 85 88 89 91

100 102

7

72

104

6 7 8

18 24 25 29 30 31 32

48 49 50 54 55 73 88

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73

80 83 84 85 88 89 91

100 102

7

72

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7

39 40

7

12 14

7

26 28 29 67

7

66

104

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71

72 73 7

16 17 18 19 20 22 46 71 72 73

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6

7 8

18 24 25 29 30 31 32

48 49 50 54 55 73 88

104

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72

73

7

66

104

6 7

46 53 54 72

6 7

17 19 20 22 23 24 25

29 46 48 56 71 72 73 83 86 91

100 102 104

7

38 39 40

7

38 39 40

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7 8

35 39 49 50 63 64 90

7

16 19 25 33 34 35 88

7

16 19 25 33 34 35 88

7

16 19 25 33 34 35 88

7

16 19 25 33 34 35 88

7

34 35

7

34 35

7

16 19 25 33 34 35 88

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62

72 73 80 83 84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51

52

54 57 61 62 72 73 80 83 84 85 88 89 91 100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91 100 102

6 7

12

23 25 26

28 32 35

36 39 40

41

46 48 49 50 51 52 54 57

61 62 72 73 80 83 84 85

88 89 91

100

102

7

54 66 72

103 104

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Digital Ground

Unused USB ports

T29 / GMUX JTAG Signals

T29_A_BIAS caps

T29 Signals

Unused SD card signals

TM Hole

T29_A_BIAS caps

Unused PEG lanes

GPU signals

TM Hole

Bottom GPU Right

GMUX ALIASES

CPU signals

Thermal Module Holes

Bosses for Flex Protector Bracket

TM Hole

Frame Holes

Rev. A NCs

USB Hub Aliases

Unused T29 Ports

Top GPU Center

DP_A_BIAS caps

Right CPU

Heat spreader mounting boss for PCH

Left CPU

TM Hole

Bottom CPU Left

Bottom GPU Left

AUDIO ALIASES

TM Hole

Heat spreader mounting boss for T29 router

ZT0980

1

STDOFF-4.5OD.98H-1.1-3.48-TH

2 1

SM

XW0900

2 1

XW0901

SM

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0981

1

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0983

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0984

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0987

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0960

3R2P5

1

ZT0989

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0988

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0991

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0930

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0932

3R2P5

1

ZT0971

3R2P5

1

SH0913

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0910

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0914

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0911

1

SH0900

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0903

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0902

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0919

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

SH0917

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0916

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0918

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

SH0920

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0921

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0922

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0923

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

ZT0957

4.0OD1.65H-M1.6X0.35

1

ZT0958

4.0OD1.65H-M1.6X0.35

1

SM

SH0901

2.0DIA-TALL-EMI-MLB-M97-M98

1

ZT0915

3R2P5

SH0924

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0930

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0931

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0932

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0933

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0935

1

SH0934

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

ZT0940

3R2P5

1

ZT0970

3R2P5

2 1

XW0902

SM

1

SH0912

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

2

1

402

100K

5% MF-LF

1/16W

R0902

1

SH0940

STDOFF-4.0OD1.85H-SM

SH0941

1

STDOFF-4.0OD1.85H-SM

1

SH0942

STDOFF-4.0OD2.23H-SM

1

SH0943

STDOFF-4.0OD2.23H-SM

1

ZT0931

STDOFF-4.0OD3.35H-TH

1

ZT0934

STDOFF-4.0OD3.35H-TH

2

1

R0915

10K

402

5% MF-LF

1/16W

2

1

R0916

10K

5%

402

1/16W MF-LF

R0950

805

5%

1/8W

MF-LF

21

0

T29BST:N

2

1

C0905

SIGNAL_MODEL=EMPTY

0.01UF

10%

201

X5R

10V

2

1

C0908

SIGNAL_MODEL=EMPTY

0.01UF

X5R

10%

201

10V

2

1

C0906

SIGNAL_MODEL=EMPTY

10%

0.01UF

201

10V X5R

21

R0926

SIGNAL_MODEL=EMPTY

201

51

5%

1/20W

MF

2

1

C0907

SIGNAL_=EMPTY

X5R 201

0.01UF

10% 10V

21

R0927

SIGNAL_MODEL=EMPTY

51

1/20W

5% MF

201

2

1

C0901

SIGNAL_MODEL=EMPTY

0.01UF

10% 10V X5R 201

21

R0921

SIGNAL_MODEL=EMPTY

MF

51

1/20W

201

5%

21

R0922

SIGNAL_MODEL=EMPTY

51

5%

1/20W

201

MF

2

1

C0902

SIGNAL_MODEL=EMPTY

0.01UF

10V 201

10% X5R

21

R0923

SIGNAL_MODEL=EMPTY

1/20W

5%

51

201

MF

2

1

C0903

SIGNAL_MODEL=EMPTY

10V 201

10% X5R

0.01UF

2

1

C0904

SIGNAL_MODEL=EMPTY

0.01UF

10V 201

10% X5R

21

R0924

SIGNAL_MODEL=EMPTY

5%

1/20W

MF

51

201

2

1

C0911

SIGNAL_MODEL=EMPTY

X5R

10%

201

0.01UF

10V

2

1

C0910

SIGNAL_MODEL=EMPTY

0.01UF

X5R

10V

10%

201

SM

1

SH0936

1.4DIA-SHORT-EMI-MLB-M97-M98

Signal Aliases

SYNC_MASTER=K17_MLB

SYNC_DATE=04/26/2010

PP15V_T29

FW643_WAKE_L

GND

MAKE_BASE=TRUE

PEG_CLKREQ_L

PPBUS_G3H

GND_CHASSIS_AUDIO_JACK

GND

USB_T29A_P

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

TP_ENET_CR_PWREN

TP_SDCONN_WP

VOLTAGE=5V

PP5V_S0_AUDIO_AMP_L

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

DP_A_BIAS_N_2

T29_A_BIAS_R

JTAG_ISP_TDI

JTAG_ISP_TCK

DP_A_BIAS_N_0

LCD_BKLT_EN

LVDS_IG_PANEL_PWR

EG_RESET_L

JTAG_ISP_TDO

MAKE_BASE=TRUE

JTAG_ISP_TDO

JTAG_ISP_TCK

T29_LSEO_LSOE2 T29_LSEO_LSOE2

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

T29_LSEO_LSOE3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_T29_R2D_CN<2..3>

NO_TEST=TRUE

NC_T29_D2RN<2..3>

MAKE_BASE=TRUE

NC_T29_R2D_CP<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_T29_D2RP<2..3>

MAKE_BASE=TRUE

PCIE_T29_R2D_C_N<3..0>

MAKE_BASE=TRUE

PCIE_T29_R2D_C_P<3..0>

T29_LSEO_LSOE2

T29_LSEO_LSOE3

PCIE_T29_D2R_N<3..0>

MAKE_BASE=TRUE

=PEG_D2R_N<11..8>

MAKE_BASE=TRUE

PCIE_T29_D2R_P<3..0>

=PEG_D2R_P<11..8>

MAKE_BASE=TRUE

JTAG_ISP_TCK

DP_IG_HPD

MAKE_BASE=TRUE

DP_IG_DDC_DATA DP_IG_DDC_DATA

DP_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_DDC_CLK

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

NC_ISNS_PVTTS0PCH_P

MAKE_BASE=TRUE

NC_ISNS_PVTTS0PCH_P

MAKE_BASE=TRUE

NC_ISNS_PVTTS0PCH_N NC_ISNS_PVTTS0PCH_N

NC_ISNS_P3V3S0MPCH_N

MAKE_BASE=TRUE

NC_ISNS_P3V3S0MPCH_N

MAKE_BASE=TRUE

NC_ISNS_P3V3S0MPCH_P NC_ISNS_P3V3S0MPCH_P

NC_ISNS_P1V05S0PCH_P

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_P

NC_ISNS_P1V05S0PCH_N

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_N

USB_EXTC_OC_L

MAKE_BASE=TRUE

USB_EXTC_OC_L

USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXCARD_P USB_EXCARD_P

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM TP_LVDS_IG_BKL_PWM

EXCARD_OC_L

MAKE_BASE=TRUE

EXCARD_OC_L

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

NC_LVDS_IG_B_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_XTALOUT NC_GPU_XTALOUT

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

TP_CPU_VTT_SELECT

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

TP_ENET_CR_PWREN

PP5V_S0_AUDIO_AMP_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

FW_PLUG_DET_L

MAKE_BASE=TRUE

FW643_WAKE_L

MAKE_BASE=TRUE

TP_SDCONN_WP

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

TP_SDCONN_CMD

TP_LVDS_MUX_SEL_EG

GND

TP_SDCONN_CMD

PP5V_S0_AUDIO

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

TP_SDCONN_CLK TP_SDCONN_CLK

MAKE_BASE=TRUE

TP_SDCONN_DATA<0..7>

SDCONN_DATA<0..7>

FW_PLUG_DET_L

GND

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

EG_RESET_L

MAKE_BASE=TRUE

=PEG_R2D_C_N<15..12>

=PEG_R2D_C_P<15..12>

=PEG_D2R_N<15..12>

=PEG_D2R_P<15..12>

=PEG_D2R_P<7..0>

PEG_D2R_P<7..0>

MAKE_BASE=TRUE

=PEG_D2R_N<7..0>

PEG_D2R_N<7..0>

MAKE_BASE=TRUE

=PEG_R2D_C_P<7..0>

MAKE_BASE=TRUE

PEG_R2D_C_P<7..0>

=PEG_R2D_C_N<7..0>

NC_PEG_D2R_N<15..12>

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15..12>

NC_PEG_R2D_C_N<15..12>

MAKE_BASE=TRUE

GFX_VID<0..6>

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

LVDS_IG_BKL_ON

CPUIMVP_VID<0..6>

MEMVTT_EN

GFXIMVP_VID<0..6>

MAKE_BASE=TRUE

CPU_VID<0..6>

MAKE_BASE=TRUE

PEG_R2D_C_N<7..0>

PEX_CLKREQ_L

LCD_BKLT_EN

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

GND

PEG_CLKREQ_L

MAKE_BASE=TRUE

MEMVTT_EN

MAKE_BASE=TRUE

T29_A_BIAS_R2D_P0

T29_A_BIAS_R2D_N0

T29_A_BIAS_R2D_P1

T29_A_BIAS_R2D_N1

T29_A_BIAS_R

DP_IG_AUX_CH_P

MAKE_BASE=TRUE

NC_PEG_D2R_P<15..12>

MAKE_BASE=TRUE

TP_SDCONN_DETECT_L

GND

TP_SDCONN_DETECT_L

=PEG_R2D_C_N<11..8>

=PEG_R2D_C_P<11..8>

DP_IG_HPD

MAKE_BASE=TRUE

T29_A_BIAS_D2R_P1

T29_A_BIAS_D2R_N1

T29_A_BIAS_R

T29_LSEO_LSOE3

T29_R2D_C_N<2..3>

T29_D2R_N<2..3>

DP_A_BIAS_P_2 DP_A_BIAS_P_0

T29_D2R_P<2..3>

MAKE_BASE=TRUE

JTAG_ISP_TDI

T29_R2D_C_P<2..3>

MAKE_BASE=TRUE

PEX_CLKREQ_L

USB_T29A_N

PP3V3_S3

PP5V_S0

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.11MM

9 OF 132 8 OF 105

7

35 86

8

38 39

8

16 88

6 7

35 39 49 50 63 64 90

61

24 94

8

18 88

8

36

8

36

60

6

85

8

86

8

86

8

19 33 88

8

19 23 33 88

6

85

8

88 90

8

18 88

8

74 88

8

19 33 88

8

19 33 88

8

19 23 33 88

8

33

33 95

8

33

8

33

33 95

9

33 95

9

8

19 23 33 88

8

17 84

8

17 80 84

8

17 80 84

8

17 80 84

8

17 80 84

8

17 84 94

8

17 84 94

8

17 84 94

8 8

8

24 43

8

24 43

8

24 32

100

8

24 32

100

8

24 32

100

8

24 32

100

6 8

18

6 8

18

8

24 32

8

24 32

6 8

18

6 8

18

6 8

18

6 8

18

8

18

8

18

8

18

8

18

8

18 94

8

18 94

8 8

8

18 94

8

18 94

8

92

8

92

8

36

60

8

19 39

8

38 39

8

36

8

74 82 87 88 91

8

36

8

88

8

36

57

8

36

8

36

8

19 39

8

88

8

74 88

9

74 92

9

74 92

9

74 92

9

92

8

74 82 87 88 91

8

18 88

8

29 67

92

74 92

8

80 88

8

88 90

8

18 88

8

18 88

8

16 88

8

29 67

6

85

6

85

6

85

6

85

8

86

8

86

8

86

8

17 84 94

9

8

36

8

36

9

8

17 84

86

8

86

8

33

97

6

85

6

85

97

8

19 33 88

97

8

80 88

24 94

6 7

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7

22 41 47 52 54 65 68 69 70 73 87

104 105

IN IN IN IN

IN

OUT

IN

IN IN IN IN IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

EDP_HPD

EDP_COMPIO

EDP_ICOMPO

EDP_AUX*

EDP_AUX

EDP_TX_3

EDP_TX_2

EDP_TX_1

EDP_TX_0

EDP_TX_3*

EDP_TX_2*

EDP_TX_1*

EDP_TX_0*

DMI_TX_3*

FDI1_LSYNC

FDI0_LSYNC

FDI_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI_TX_1

FDI_TX_0

FDI_TX_2

FDI_TX_3*

FDI_TX_2*

FDI_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

FDI_TX_4* FDI_TX_5* FDI_TX_6* FDI_TX_7*

FDI_TX_4 FDI_TX_5 FDI_TX_6 FDI_TX_7

(SYM 1 OF 11)

DMI

EMBEDDED DISPLAY PORT

PCI EXPRESS BASED INTERFACE SIGNALS

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

RSVD_96

RSVD_95

RSVD_94

RSVD_93

RSVD_92

RSVD_91

RSVD_90

RSVD_97

RSVD_38 RSVD_39

RSVD_40

RSVD_36

RSVD_41 RSVD_42 RSVD_43

RSVD_45

RSVD_44

RSVD_48 RSVD_49 RSVD_50

RSVD_47

RSVD_46

RSVD_53

RSVD_52

RSVD_51

RSVD_55

RSVD_54

RSVD_57

RSVD_59 RSVD_60

RSVD_58

RSVD_56

RSVD_61

RSVD_63

RSVD_62

RSVD_65

RSVD_64

RSVD_66 RSVD_67

RSVD_69 RSVD_70

RSVD_68

RSVD_71 RSVD_72

RSVD_79 RSVD_80 RSVD_81

RSVD_78

RSVD_82 RSVD_83 RSVD_84

RSVD_86

RSVD_85

RSVD_89

RSVD_88

RSVD_87

CFG_4

CFG_3

CFG_2

CFG_1

CFG_0

CFG_9

CFG_8

CFG_7

CFG_6

CFG_5

CFG_14

CFG_13

CFG_12

CFG_11

CFG_10

CFG_15 CFG_16 CFG_17

RSVD_1

RSVD_5 RSVD_6

RSVD_4

RSVD_3

RSVD_2

RSVD_10 RSVD_11

RSVD_9

RSVD_8

RSVD_7

RSVD_15 RSVD_16

RSVD_14

RSVD_13

RSVD_12

RSVD_20

RSVD_19

RSVD_18

RSVD_17

RSVD_25 RSVD_26

RSVD_24

RSVD_22 RSVD_23

RSVD_31

RSVD_30

RSVD_29

RSVD_28

RSVD_27

RSVD_32 RSVD_33 RSVD_34

RSVD_35

(5 OF 11)

RESERVED

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

IN IN

IN

IN IN

BI BI

NC NC NC NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC NC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

(IPU)

10K PU disables eDP HPD

FOR SANDYBRIDGE PROCESSOR

(IPU)

(IPU) (IPU)

(IPU)

Intel is investigating processor driven VREF_DQ generation.

(IPU)

(DDR_VREF0) (DDR_VREF1)

(THERMDA) (THERMDC)

NOTE:

This connection is to support the same.

(IPU)

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CPU_CFG<4> should be pulled down to enable EDP

These can be Placed close to J2500 and Only for debug access

6

17 92

6

17 92

6

17 92

6

17 92

6

17 92

6

17 92

6

17 92

6

17 92

8

1% MF-LF

402

1/16W

24.9

R1010

1

2

BGA

SANDY-BRIDGE

MOBILE-REV1

OMIT

U1000

N8

N10

T9

R10

R6

R8

U8

U10

N2

N4

R2

R4

P3

P1

T5

U6

AE4 AE2

AC2

AE8

AB1

AG4

AG2

AF3

AF1

AF7

AE6

AG8

AG6

AC8

AB7

AA2

AB3

AD9

W6

V7

W10

W8

Y9

AA8

AA10

AC10

U2

U4

W4

W2

V3

V1

AA6

Y5

G2 H1 F3

G22

F23

K23

H23

F11

H11

K11

J12

F9

E8

H9

G10

H7

J8

G6

F7

K21

H21

F19

H19

K19

J20

H17

G18

K15

K17

G14

F15

J16

H15

K13

H13

C22

A22

D23

B23

B13

D13

C10

A10

D11

B11

B9

D9

D7

B7

F13

E12

A18

C18

B21

D21

D19

B19

F21

E20

C14

A14

B17

D17

D15

B15

F17

E16

SANDY-BRIDGE

BGA

MOBILE-REV1

OMIT

U1000

B57 D57

F55 K55 F57 E58 H57 H55 D53 K57

B55 A54 A58 D55 C56 E54 J54 G56

BB17

AW46 BG26 BB25 BG34 BH35 BJ34 BF35 BF41 BH43 BJ42

AY17

BF43

AW50 BB57 BF63

AD5 AH5 AJ6

BF3 BG4

BD29

BD19 AY45 AY41 BG62 BB43

D49 B53

G52 G64

BD33

AJ10

BE6 AA4 AC4 AC6

C52

D3

C4 C24 D25

BC30

B25

K47 H47

F5 K9 H5 L10 G4 K7 K5

BE32

M9 L6 J2 L2 P7 M5 J4 L4 N6

G48

AW42

K49 H49 J50

AY13 BB13

BA48

BB15 AY15 AW14 BD13 BA16 BE16 BD15 BC14 BF19 BH19

BC42

BF21 BH21 BF23 BH23 BF25 BH25 BJ22 BG22

1K

1/16W

402

MF-LF

1%

R1020

1

2

1K

402

MF-LF

1/16W

1%

R1022

1

2

402

1/16W

0

5%

MF-LF

NOSTUFF

R1021

1 2

0

5%

MF-LF

1/16W

402

NOSTUFF

R1023

1 2

17 92

1/16W

1%

402

24.9

MF-LF

PLACE_NEAR=U1000.AB1:12.7mm

R1030

1

2

MF-LF 402

1% 1/16W

10K

R1031

1

2

51

100

51

100

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1047

1

2

MF-LF

402

5%

1/16W

1K

NOSTUFF

R1046

1

2

1K

MF-LF

402

5%

1/16W

R1045

1

2

5% 1/16W MF-LF

1K

402

EDP

R1044

1

2

1K

MF-LF

402

1/16W

5%

NOSTUFF

R1042

1

2

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1040

1

2

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1041

1

2

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1043

1

2

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1049

1

2

CPU DMI/PEG/FDI/RSVD

CPU_EDP_COMP

TP_EDP_TX_N<2>

CPU_CFG<7>

CPU_CFG<16> CPU_CFG<3> CPU_CFG<1> CPU_CFG<0>

CPU_CFG<6>

NC_PEG_R2D_C_P<14>

CPU_CFG<5>

TP_EDP_AUX_N

TP_EDP_TX_N<3>

TP_EDP_TX_N<1>

FDI_DATA_N<2>

FDI_DATA_N<6>

FDI_DATA_P<5>

CPU_CFG<2>

CPU_CFG<5> CPU_CFG<6>

CPU_CFG<8>

CPU_CFG<7>

NC_PEG_D2R_P<12>

=PEG_D2R_P<3>

CPU_MEM_VREFDQ_B

=PEG_D2R_P<10>

=PEG_D2R_P<4>

=PEG_D2R_P<1> =PEG_D2R_P<2>

CPU_MEM_VREFDQ_A

=PEG_R2D_C_N<4>

FDI_DATA_P<3>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<7>

NC_PEG_D2R_N<13>

FDI_DATA_P<4>

DMI_N2S_P<0>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<6>

CPU_THERMD_N

CPU_THERMD_P

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<3>

NC_PEG_R2D_C_N<14>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<7>

FDI_DATA_P<7>

FDI_DATA_N<5>

FDI_DATA_N<0>

NC_PEG_R2D_C_N<15>

TP_EDP_AUX_P

NC_PEG_D2R_P<13>

=PEG_R2D_C_N<11>

=PEG_D2R_P<9>

=PEG_D2R_P<11>

=PEG_R2D_C_P<10>

NC_PEG_R2D_C_N<12>

=PEG_R2D_C_P<4>

NC_PEG_R2D_C_P<12>

NC_PEG_D2R_P<14>

=PEG_R2D_C_P<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<10>

CPU_CFG<1>

CPU_CFG<10>

CPU_CFG<4>

=PEG_R2D_C_P<1>

FDI_DATA_N<1>

DMI_S2N_P<1>

=PEG_D2R_P<6>

PP0V75_S3_MEM_VREFDQ_B

DMI_S2N_P<3>

DMI_N2S_N<1>

NC_PEG_R2D_C_P<15>

PP0V75_S3_MEM_VREFDQ_A

DMI_N2S_N<0>

DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

FDI_DATA_N<3>

FDI_DATA_N<7>

FDI_DATA_P<6>

FDI_DATA_P<2>

FDI_DATA_P<1>

FDI_DATA_P<0>

DMI_N2S_N<3>

DMI_S2N_P<0>

DMI_S2N_N<0>

CPU_CFG<12>

CPU_CFG<16>

CPU_CFG<9>

CPU_CFG<0>

CPU_CFG<17>

=PEG_R2D_C_P<8>

=PEG_R2D_C_N<5>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<11>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_P<11>

NC_PEG_R2D_C_P<13>

CPU_CFG<2>

CPU_CFG<4>

FDI_DATA_N<4>

DMI_N2S_N<2>

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_P<2>

NC_PEG_D2R_N<14>

=PEG_D2R_P<5>

=PEG_D2R_P<0>

NC_PEG_D2R_N<15>

=PEG_D2R_N<8> =PEG_D2R_N<9> =PEG_D2R_N<10> =PEG_D2R_N<11>

=PEG_D2R_N<7>

NC_PEG_D2R_N<12>

DMI_S2N_N<2>

NC_PEG_R2D_C_N<13>

TP_EDP_TX_N<0>

CPU_CFG<3>

=PEG_D2R_N<4>

=PEG_D2R_N<0>

CPU_PEG_COMP

NC_PEG_D2R_P<15>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1>

FDI_LSYNC<1>

PP1V05_S0

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

=PEG_D2R_P<8>

PP1V05_S0

=PEG_D2R_N<1> =PEG_D2R_N<2> =PEG_D2R_N<3>

=PEG_D2R_N<5> =PEG_D2R_N<6>

FDI_LSYNC<0>

TP_EDP_TX_P<0> TP_EDP_TX_P<1> TP_EDP_TX_P<2> TP_EDP_TX_P<3>

CPU_EDP_HPD

=PEG_D2R_P<7>

10 OF 132

9 OF 105

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

28 30

26 30

23

9

23 92

9

23 92

23

23 92

9

23 92

9

23 92

9

23 92

92

7 9

10 12 13

14 23

35 39 45 68

70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

6

BI BI BI BI BI

IN

OUT

IN IN

OUT

BI

DDR3 MISC

PWR MGMT

JTAG & BPM

CLOCKS

THERMAL

(2 OF 11)

PROC_SELECT*

PROC_DETECT*

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_VREF

SM_DRAMRST*

SM_DRAMPWROK

PM_SYNC

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

BCLK_ITP

BCLK_ITP*

UNCOREPWRGOOD

RESET*

THERMTRIP*

CATERR*

PECI

PROCHOT*

BCLK

BCLK*

DPLL_REF_CLK

DPLL_REF_CLK*

NC

OUT

BI

IN

OUT

IN IN

IN

OUT

IN

IN IN

IN

OUT

BI BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

R1120 and R1121 are Intel recommended values

Unused eDP CLK

(IPU)

(IPD)

(IPU) (IPU)

(IPU)

23 92

PLACE_NEAR=U1800.AY11:157mm

402

1/16W

5%

10K

MF-LF

R1111

1

2

17 29 92

19 23 92

29

16 92

17 92

19 92

19 45 92

1/16W MF-LF

1%

402

75

R1126

1

2

SANDY-BRIDGE

OMIT

BGA

MOBILE-REV1

U1000

D5 C6

K63 K65

C62 D61 E62 F63 D59 F61 F59 G60

H53

H61

AJ4 AJ2

F53

K53

J62 H65

B59

AH9

H51

K51

AY25

BE24

BJ46 BG46 BF45

BJ44

J58

K61 K59

F51

H59 H63

C60

PLACE_NEAR=U1000.BF45:12.7mm

1/16W

200

402

MF-LF

1%

R1114

1

2

PLACE_NEAR=U1000.BG46:12.7mm

MF-LF

1/16W

402

25.5

1%

R1113

1

2

402

1/16W MF-LF

140

1%

PLACE_NEAR=U1000.BJ46:12.7mm

R1112

1

2

92

1/16W

402

5%

MF-LF

68

R1101

1

2

1/16W

PLACE_NEAR=U1000.BJ44:2.54mm

NOSTUFF

402

MF-LF

100

1%

R1130

1

2

NOSTUFF

PLACE_NEAR=U1000.BJ44:2.54mm

MF-LF

402

1/16W

100

1%

R1131

1

2

NOSTUFF

PLACE_NEAR=U1000.BJ44:2.54mm

X5R 402

10%

0.1UF

16V

C1130

1

2

MF-LF 402

1K

5% 1/16W

R1141

1

2

1K

5% 1/16W MF-LF 402

R1140

1

2

402

5%

56

1/16W MF-LF

R1103

12

46 68 92

NOSTUFF

201

1/20W

MF

1K

5%

R1100

1

2

23 92

1%

402

MF-LF

1/16W

200

PLACE_NEAR=R1121.2:1mm

R1120

1

2

402

1%

MF-LF

1/16W

PLACE_NEAR=U1000.AY25:51.562mm

130

R1121

12

16 92

17 92

5% 1/16W

NOSTUFF

402

MF-LF

51

R1104

1

2

1%

402

43.2

MF-LF

1/16W

R1125

12

23 25

201

1/20W MF

NOSTUFF

1K

5%

R1102

1

2

23 25 92

23 92

CPU CLOCK/MISC/JTAG

PM_MEM_PWRGD_R

CPU_SM_RCOMP<2>

CPU_PROCHOT_R_L

CPU_PECI

PLT_RST_CPU_BUF_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

PP1V05_S0

PLT_RESET_LS1V1_L

PP1V5_S3RS0_CPUDDR

PM_THRMTRIP_L

CPU_PROC_SEL_L

CPU_CATERR_L

XDP_BPM_L<0>

XDP_CPU_PRDY_L

XDP_BPM_L<1>

XDP_DBRESET_L

XDP_CPU_TDO

XDP_CPU_TRST_L

XDP_CPU_PREQ_L

ITPCPU_CLK100M_N

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TDI

XDP_BPM_L<5>

CPU_PROCHOT_L

PP1V05_S0

DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P

PP1V05_S0_CPU_VCCPQE

ITPCPU_CLK100M_P

DPLL_REF_CLK_L

DPLL_REF_CLK

PM_SYNC

CPU_PWRGD

CPU_MEM_RESET_L

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1>

PP1V05_S0

PM_MEM_PWRGD

CPU_DDR_VREF

PP1V5_S3RS0_CPUDDR

11 OF 132 10 OF 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

7

10 13 15 29 73

104

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

7

12 14

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

7

10 13 15 29 73

104

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT

SA_CAS* SA_RAS* SA_WE*

SA_DQ_63

SA_DQ_62

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_BS_2

SA_BS_1

SA_BS_0

SA_DQ_47 SA_DQ_48 SA_DQ_49

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_51

SA_DQ_50

SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46

SA_DQ_36

SA_DQ_32 SA_DQ_33

SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31

SA_DQ_34 SA_DQ_35

SA_DQ_26

SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25

SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_9

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5

SA_DQ_0

SA_CK_1

SA_CK_0

SA_CKE_1

SA_CKE_0

SA_CK_1*

SA_CK_0*

SA_CS_1*

SA_CS_0*

SA_ODT_1

SA_ODT_0

SA_DQS_0* SA_DQS_1* SA_DQS_2* SA_DQS_3* SA_DQS_4* SA_DQS_5* SA_DQS_6* SA_DQS_7*

SA_DQS_0 SA_DQS_1

SA_DQS_3

SA_DQS_2

SA_DQS_5

SA_DQS_4

SA_DQS_6 SA_DQS_7

SA_MA_0 SA_MA_1

SA_MA_3

SA_MA_2

SA_MA_5

SA_MA_4

SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9

SA_MA_11

SA_MA_10

SA_MA_12

SA_MA_14

SA_MA_13

SA_MA_15

MEMORY CHANNEL A

(SYM 3 OF 11)

SB_CK_1*

SB_DQ_33

SB_CAS* SB_RAS* SB_WE*

SB_BS_0 SB_BS_1 SB_BS_2

SB_CK_0

SB_CK_0*

SB_CK_1

SB_CKE_0

SB_CKE_1

SB_DQ_0 SB_DQ_1

SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19

SB_DQ_2

SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29

SB_DQ_3

SB_DQ_30 SB_DQ_31 SB_DQ_32

SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39

SB_DQ_4

SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49

SB_DQ_5

SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59

SB_DQ_6

SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SB_DQ_7 SB_DQ_8 SB_DQ_9

SB_CS_0* SB_CS_1*

SB_ODT_1

SB_ODT_0

SB_DQS_0* SB_DQS_1* SB_DQS_2* SB_DQS_3* SB_DQS_4* SB_DQS_5* SB_DQS_6* SB_DQS_7*

SB_DQS_0

SB_DQS_2

SB_DQS_1

SB_DQS_3 SB_DQS_4 SB_DQS_5

SB_DQS_7

SB_DQS_6

SB_MA_1

SB_MA_0

SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6

SB_MA_8

SB_MA_7

SB_MA_10 SB_MA_11

SB_MA_9

SB_MA_13

SB_MA_12

SB_MA_15

SB_MA_14

(SYM 4 OF 11)

MEMORY CHANNEL B

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

27 93

26 27 93

27 93

26 93

27 93

27 28 93

27 93

28 93

SANDY-BRIDGE

MOBILE-REV1

BGA

OMIT

U1000

BA36 BC38 BB19

BE44

BB31 BA32

AW34 AY33

BC18

BD17

BD41 BD45

AL6 AL8

AV7 AY5 AT5 AR6 AW6 AT9 BA6 BA8 BG6 AY9

AP7

AW8 BB7 BC8

BE4 AW12 AV11 BB11 BA12

BE8 BA10

AM5

BD11 BE12 BB49 AY49 BE52 BD51 BD49 BE48 BA52 AY51

AK7

BC54 AY53 AW54 AY55 BD53 BB53 BE56 BA56 BD57 BF61

AL10

BA60 BB61 BE60 BD63 BB59 BC58 AW58 AY59 AL60 AP61

AN10

AW60 AY57 AN60 AR60

AM9 AR10

AR8

AN6

AN8

AU8

AU6

BD5

BC6

BC10

BD9

BB51

BC50

BD55

BB55

BD61

BD59

AV61

AU60

BD27 BA28

AW38 AW22 BA20 BB45 BE20 AW18

BB27 AW26 BB23 BA24 AY21 BD21 BC22 BB21

BB41 BC46

BE36 BA44

BGA

MOBILE-REV1

SANDY-BRIDGE

OMIT

U1000

BJ38 BD37 AY29

BH39

BF33 BH33

BF37 BH37

BD25

BJ26

BE40 BH41

AL4 AK3

BA4 BB1 AV1 AU2 BA2 BB3 BC2

BF7 BF11 BJ10

AP3

BC4

BH7 BH11 BG10 BJ14 BG14 BF17 BJ18 BF13 BH13

AR2

BH17 BG18 BH49 BF47 BH53 BG50 BF49 BH47 BF53 BJ50

AL2

BF55 BH55 BJ58 BH59 BJ54 BG54 BG58 BF59 BA64 BC62

AK1

AU62 AW64 BA62 BC64 AU64 AW62 AR64 AT65 AL64 AM65

AP1

AR62 AT63 AL62 AM63

AR4

AV3

AU4

AN2

AN4

AW4

AW2

BF9

BH9

BH15

BF15

BH51

BF51

BF57

BH57

AY65

AY63

AN64

AN62

BF31 BH31

AY37 BJ30 AW30 BA40 BB29 BE28

BB37 BC34 BF27 BB33 BH27 BG30 BH29 BF29

BG42 BH45

BG38 BF39

26 93

26 27 93

27 93

26 93

28 93

27 28 93

27 93

27 28 93

27 93

28 93

SYNC_DATE=04/26/2010

CPU DDR3 INTERFACES

MEM_B_DQS_N<2>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<1>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<5>

MEM_B_DQ<7>

MEM_B_DQ<9>

MEM_B_CKE<1>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_BA<0>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<8>

MEM_B_DQ<6>

MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<56>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<38>

MEM_A_DQ<24>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_A<15>

MEM_A_A<13> MEM_A_A<14>

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12>

MEM_A_A<8> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_DQ<0>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<26>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<37>

MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52>

MEM_A_DQ<55>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_DQ<57> MEM_A_DQ<58>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CAS_L

12 OF 132 11 OF 105

(9 OF 11)

VIDALERT*

VCCSA_14 VCCSA_15 VCCSA_16

VCCSA_8

VCCIO_SEL

VCCPQE_3

VCCPQE_2

VCCPQE_1

VCCPQE_0

VCCPLL_2

VCCPLL_1

VCCPLL_0

VCCDQ_3

VCCDQ_2

VCCDQ_1

VCCDQ_0

VCCSA_1

VCCSA_0

VCCSA_3 VCCSA_4

VCCSA_2

VCCSA_5 VCCSA_6 VCCSA_7

VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_17

VIDSOUT VIDSCLK

VCCSA_VID_0

VCC_SENSE

VCCSA_VID_1

VAXG_SENSE

VSS_SENSE

VSSAXG_SENSE

VCCIO_SENSE

VDDQ_SENSE

VSS_SENSE_VCCIO

VCCSA_SENSE

VSS_SENSE_VDDQ

VCC_VAL_SENSE

VCC_DIE_SENSE

VAXG_VAL_SENSE

VSS_VAL_SENSE

VSSAXG_VAL_SENSE

VSS_NCTF_0 VSS_NCTF_1 VSS_NCTF_2

VSS_NCTF_4

VSS_NCTF_3

VSS_NCTF_6

VSS_NCTF_5

VSS_NCTF_7

VSS_NCTF_9

VSS_NCTF_8

VSS_NCTF_11

VSS_NCTF_10

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15

DC_TEST_D65

DC_TEST_D1

DC_TEST_C64

DC_TEST_C2

DC_TEST_BJ64

DC_TEST_BJ62

DC_TEST_BJ4

DC_TEST_BJ2

DC_TEST_BH65

DC_TEST_BH63

DC_TEST_BH3

DC_TEST_BH1

DC_TEST_BG64

DC_TEST_BG2

DC_TEST_BF65

DC_TEST_BF1

DC_TEST_B65

DC_TEST_B63

DC_TEST_B3

DC_TEST_A64

DC_TEST_A62

DC_TEST_A4

CORE POWER

(6 OF 11)

VCC_54 VCC_55 VCC_56 VCC_57 VCC_58

VCC_63

VCC_62

VCC_61

VCC_59 VCC_60

VCC_64 VCC_65 VCC_66 VCC_67 VCC_68

VCC_73

VCC_72

VCC_71

VCC_69 VCC_70

VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79

VCC_83

VCC_82

VCC_81

VCC_80

VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89

VCC_93

VCC_92

VCC_90 VCC_91

VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99

VCC_104

VCC_103

VCC_102

VCC_101

VCC_100

VCC_105 VCC_106 VCC_107

VCC_4

VCC_3

VCC_2

VCC_1

VCC_0

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_16

VCC_15

VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53

OUT OUT

OUT

BI

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

HR_PPDG sections 6.2.1 and 6.3.1.

(IPU)

For Future Compatibility

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side. NOTE: Intel validation sense lines per doc 439028 rev1.0

BGA

OMIT

MOBILE-REV1

SANDY-BRIDGE

U1000

A4 A62 A64 B3 B63 B65 BF1 BF65 BG2 BG64 BH1 BH3 BH63 BH65 BJ2 BJ4 BJ62 BJ64 C2 C64 D1 D65

F49

B49

F47

B47

D47

AV23 AT23 AP23 AL23

AJ8

AW10

AK65 AK63 AK61

AV21 AT21 AP21 AL21

W17 W15

N16 N14 M17 M15 M12 M11 L18 L14

W12 U17 U15 U12 T16 T14 T11 N18

K3

AE10 AG10

AY19

B51

D51

A50

BJ60 BJ6

E64 E2 B61 B5 A60 A6

BH61 BH5 BE64 BE2 BD65 BD1 F65 F1

A46

AU10

AW20

C48

E50

A48

OMIT

SANDY-BRIDGE

MOBILE-REV1

BGA

U1000

R46 R42

N43

B29 A44 A40 A38 A34 A32 A28 A26

N39 N37 N33 N30 N26 N24 N20 M46 M42

R40

M40 M36 M34 M29 M27 M23 M21 L44 L40 L38

R36

L34 L32 L28 L26 L22 K45 K43 K41 K37 K35

R34

K31 K29 K25 J44 J40 J38 J34 J32 J28 J26

R29

H45 H43 H41 H37

H35 H31 H29 H25 G44 G40

R27 G38

G34 G32 G28 G26 F45 F43 F41 F37 F35

R23

F31 F29 F25 E44 E40 E38 E34 E32 E28 E26

R21

D45 D43 D41 D37 D35 D31 D29 C44 C40 C38

N45

C34 C32 C28 C26 B45 B43 B41 B37 B35 B31

68 92

70 92

65

MF-LF

402

10K

1/16W

5%

R1320

1

2

MF-LF

5%

0

1/16W

402

R1312

1 2

68 92

1%

402

1/16W

PLACE_NEAR=U1000.A50:2.54mm

MF-LF

130

R1302

1

2

5%

402

1/16W MF-LF

0

R1311

1 2

68 92

MF-LF

5%

PLACE_NEAR=U1000.B51:38mm

43

402

1/16W

R1310

1 2

68 92

75

MF-LF

1%

402

1/16W

PLACE_NEAR=R1310.1:2.54mm

R1300

1

2

1/16W MF-LF

10K

402

5%

R1313

1

2

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AU10:50.8mm

NOSTUFF

100

1/16W

402

MF-LF

1%

R1363

1

2

402

NOSTUFF

PLACE_NEAR=U1000.AW10:50.8mm

PLACE_SIDE=BOTTOM

MF-LF

1/16W

1%

100

R1362

1

2

NOSTUFF

PLACE_SIDE=BOTTOM

MF

1/20W

1%

49.9

201

R1370

1

2

49.9

PLACE_SIDE=BOTTOM

NOSTUFF

1%

MF

1/20W

201

R1371

1

2

PLACE_SIDE=BOTTOM

NOSTUFF

1%

MF

1/20W

49.9

201

R1364

1

2

PLACE_SIDE=BOTTOM

NOSTUFF

49.9

1%

MF

1/20W

201

R1365

1

2

PLACE_SIDE=BOTTOM

MF-LF

402

NOSTUFF

100

1/16W

1%

PLACE_NEAR=U1000.B47:50.8mm

R1360

1

2

PLACE_NEAR=U1000.A46:50.8mm

NOSTUFF

PLACE_SIDE=BOTTOM

MF-LF

1%

100

402

1/16W

R1361

1

2

MF-LF

1/16W

10K

402

5%

R1314

1

2

PLACE_NEAR=U1000.F49:50.8mm

402

1/16W

NOSTUFF

1%

PLACE_SIDE=BOTTOM

100

MF-LF

R1366

1

2

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.E50:50.8mm

100

402

MF-LF

1% 1/16W

R1367

1

2

100

1/16W

1%

MF-LF 402

R1368

1

2

65

SYNC_DATE=07/16/2010

CPU POWER

SYNC_MASTER=K91_MLB

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_VCC_VALSENSE_P

CPU_VCCSENSE_N

CPU_AXG_SENSE_N

CPU_VCCSASENSE

TP_CPU_DIE_SENSE

TP_CPU_VDDQSENSE_N

TP_CPU_VDDQSENSE_P

CPU_VCCIOSENSE_N

CPU_VCCIOSENSE_P

CPU_AXG_SENSE_P

CPU_VIDSCLK_R

CPU_VIDSOUT_R

CPU_VIDALERT_L_R

CPU_VCCSENSE_P

PPVCORE_S0_AXG

CPU_VCCSA_VID<1>

TP_DC_TEST_BF65

PPVCORE_S0_CPU PP1V05_S0

PP1V05_S0

CPU_VCCIO_SEL

CPU_VCCSA_VID<0>

DC_TEST_BH1_BG2

PPVCORE_S0_CPU

PP3V3_S0

DC_TEST_BH3_BJ2

DC_TEST_B65_C64

PPVCCSA_S0_CPU

TP_DC_TEST_A4 TP_DC_TEST_A62

TP_DC_TEST_BF1

TP_DC_TEST_BJ62

TP_DC_TEST_D1 TP_DC_TEST_D65

DC_TEST_BJ64_BH63

DC_TEST_BG64_BH65

DC_TEST_B63_A64

TP_DC_TEST_BJ4

DC_TEST_B3_C2

PP1V5_S3_CPU_VCCDQ

PP1V05_S0

PP1V05_S0_CPU_VCCPQE

PP1V8_S0_CPU_VCCPLL_R

PPVCCSA_S0_CPU

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

PPVCORE_S0_CPU

PPVCORE_S0_AXG

13 OF 132 12 OF 105

7

12 13 15 49

69

6 7

12 14 49 69

105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

6 7

12 14 49 69

105

6 7

12 14 49 69

105

6 7

23 25 26 28 32 35 36 39 40 41 46 48

49 50 51 52 54 57 61 62 72 73 80 83 84

85 88 89 91

100 102

7

12

15 65

6

7

15

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

7

10 14

7

14

7

12 15 65

6 7

12 14

49 69

105

7

12 13

15 49 69

VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

VDDQ_9

VDDQ_8

VDDQ_7

VDDQ_5 VDDQ_6

VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14

VDDQ_19

VDDQ_18

VDDQ_17

VDDQ_15 VDDQ_16

VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25

VDDQ_29

VDDQ_28

VDDQ_27

VDDQ_26

VDDQ_30 VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34 VDDQ_35

VDDQ_39

VDDQ_38

VDDQ_36 VDDQ_37

VDDQ_40 VDDQ_41 VDDQ_42 VDDQ_43 VDDQ_44 VDDQ_45

VDDQ_50

VDDQ_49

VDDQ_48

VDDQ_47

VDDQ_46

VDDQ_51 VDDQ_52 VDDQ_53 VDDQ_54 VDDQ_55

VDDQ_60

VDDQ_59

VDDQ_58

VDDQ_56 VDDQ_57

VDDQ_61 VDDQ_62 VDDQ_63 VDDQ_64 VDDQ_65 VDDQ_66 VDDQ_67 VDDQ_68

VAXG_4

VAXG_3

VAXG_2

VAXG_1

VAXG_0

VAXG_9

VAXG_8

VAXG_7

VAXG_6

VAXG_5

VAXG_14

VAXG_13

VAXG_12

VAXG_11

VAXG_10

VAXG_16

VAXG_15

VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25 VAXG_26 VAXG_27 VAXG_28 VAXG_29 VAXG_30 VAXG_31 VAXG_32 VAXG_33 VAXG_34 VAXG_35 VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43 VAXG_44 VAXG_45 VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56 VAXG_57 VAXG_58 VAXG_59 VAXG_60 VAXG_61 VAXG_62 VAXG_63

IO POWER DDR3

GRAPHIC CORE POWER

(8 OF 11)

(10 OF 11)

VSS_85

VSS_84

VSS_83

VSS_82

VSS_81

VSS_80

VSS_79

VSS_78

VSS_77

VSS_76

VSS_75

VSS_74

VSS_73

VSS_72

VSS_71

VSS_70

VSS_69

VSS_68

VSS_67

VSS_66

VSS_65

VSS_64

VSS_63

VSS_62

VSS_61

VSS_60

VSS_59

VSS_58

VSS_57

VSS_56

VSS_55

VSS_54

VSS_53

VSS_52

VSS_51

VSS_50

VSS_49

VSS_48

VSS_47

VSS_46

VSS_45

VSS_44

VSS_43

VSS_42

VSS_41

VSS_40

VSS_39

VSS_38

VSS_37

VSS_36

VSS_35

VSS_34

VSS_33

VSS_32

VSS_31

VSS_30

VSS_29

VSS_28

VSS_27

VSS_26

VSS_25

VSS_24

VSS_23

VSS_22

VSS_21

VSS_20

VSS_19

VSS_18

VSS_17

VSS_15 VSS_16

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14

VSS_5 VSS_6 VSS_7 VSS_8 VSS_9

VSS_0 VSS_1 VSS_2 VSS_3 VSS_4

VSS_171

VSS_170

VSS_169

VSS_168

VSS_167

VSS_164

VSS_163

VSS_165 VSS_166

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_153

VSS_152

VSS_154 VSS_155 VSS_156

VSS_151

VSS_150

VSS_149

VSS_148

VSS_147

VSS_143

VSS_142

VSS_144 VSS_145 VSS_146

VSS_141

VSS_140

VSS_139

VSS_138

VSS_137

VSS_132 VSS_133 VSS_134 VSS_135 VSS_136

VSS_131

VSS_130

VSS_129

VSS_128

VSS_127

VSS_126

VSS_123

VSS_122

VSS_124 VSS_125

VSS_121

VSS_120

VSS_119

VSS_118

VSS_117

VSS_116

VSS_112 VSS_113 VSS_114 VSS_115

VSS_111

VSS_110

VSS_109

VSS_108

VSS_107

VSS_106

VSS_102

VSS_101

VSS_103 VSS_104 VSS_105

VSS_100

VSS_99

VSS_98

VSS_97

VSS_96

VSS_92

VSS_91

VSS_93 VSS_94 VSS_95

VSS_90

VSS_89

VSS_88

VSS_87

VSS_86

(11 Of 11)

VSS_257

VSS_256

VSS_255

VSS_254

VSS_253

VSS_252

VSS_251

VSS_250

VSS_249

VSS_248

VSS_247

VSS_246

VSS_245

VSS_244

VSS_243

VSS_242

VSS_241

VSS_240

VSS_239

VSS_238

VSS_237

VSS_236

VSS_235

VSS_234

VSS_233

VSS_232

VSS_231

VSS_230

VSS_229

VSS_228

VSS_227

VSS_226

VSS_225

VSS_224

VSS_223

VSS_222

VSS_221

VSS_220

VSS_219

VSS_218

VSS_217

VSS_216

VSS_215

VSS_214

VSS_213

VSS_212

VSS_211

VSS_210

VSS_209

VSS_208

VSS_207

VSS_206

VSS_205

VSS_204

VSS_203

VSS_202

VSS_201

VSS_200

VSS_199

VSS_198

VSS_197

VSS_196

VSS_195

VSS_194

VSS_193

VSS_192

VSS_191

VSS_190

VSS_189

VSS_187 VSS_188

VSS_182 VSS_183 VSS_184 VSS_185 VSS_186

VSS_177 VSS_178 VSS_179 VSS_180 VSS_181

VSS_172 VSS_173 VSS_174 VSS_175 VSS_176

VSS_342

VSS_341

VSS_340

VSS_339

VSS_336

VSS_335

VSS_337 VSS_338

VSS_334

VSS_333

VSS_332

VSS_331

VSS_330

VSS_329

VSS_325

VSS_324

VSS_326 VSS_327 VSS_328

VSS_323

VSS_322

VSS_321

VSS_320

VSS_319

VSS_315

VSS_314

VSS_316 VSS_317 VSS_318

VSS_313

VSS_312

VSS_311

VSS_310

VSS_309

VSS_304 VSS_305 VSS_306 VSS_307 VSS_308

VSS_303

VSS_302

VSS_301

VSS_300

VSS_299

VSS_298

VSS_295

VSS_294

VSS_296 VSS_297

VSS_293

VSS_292

VSS_291

VSS_290

VSS_289

VSS_288

VSS_284 VSS_285 VSS_286 VSS_287

VSS_283

VSS_282

VSS_281

VSS_280

VSS_279

VSS_278

VSS_274

VSS_273

VSS_275 VSS_276 VSS_277

VSS_272

VSS_271

VSS_270

VSS_269

VSS_268

VSS_264

VSS_263

VSS_265 VSS_266 VSS_267

VSS_262

VSS_261

VSS_260

VSS_259

VSS_258

VSS_343

IO POWER

(7 OF 11)

VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36 VCCIO_37

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_38 VCCIO_39

VCCIO_43 VCCIO_44 VCCIO_45 VCCIO_46 VCCIO_47

VCCIO_52

VCCIO_51

VCCIO_50

VCCIO_48 VCCIO_49

VCCIO_53 VCCIO_54 VCCIO_55 VCCIO_56 VCCIO_57 VCCIO_58

VCCIO_62

VCCIO_61

VCCIO_60

VCCIO_59

VCCIO_63 VCCIO_64 VCCIO_65

VCCIO_4

VCCIO_3

VCCIO_2

VCCIO_1

VCCIO_0

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_5

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_17 VCCIO_18 VCCIO_19 VCCIO_20 VCCIO_21 VCCIO_22 VCCIO_23 VCCIO_24 VCCIO_25 VCCIO_26 VCCIO_27 VCCIO_28 VCCIO_29 VCCIO_30 VCCIO_31 VCCIO_32

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SANDY-BRIDGE

MOBILE-REV1

BGA

OMIT

U1000

AH65 AH63

AE64 AE62 AE60 AD65 AD63 AD61 AD58 AD56 AB65 AB63

AH61

AB61 AB58 AB56 AA64 AA62 AA60

Y58 Y56 W64 W62

AH58

W60 V65 V63 V61 V58 V56 T65 T63 T61 T58

AH56

T56 R64 R62 R60 R55 R53 R48 N64 N62 N60

AG64

N58 N56 N52 N49 M65 M63 M61 M59 M55 M53

AG62

M48 L56 L52 L48

AG60 AF58 AF56

BJ36 BJ28

AY47 AY43 AY39 AY35 AY31 AY27 AY23 AV46 AV42 AV40

BG40

AV36 AV34 AV29 AV27 AU45 AU43 AU39 AU37 AU33 AU30

BG32

AU26 AU24 AT46 AT42 AT40 AT36 AT34 AT29 AT27 AR45

BD47

AR43 AR39 AR37 AR33 AR30 AR26 AR24 AP46 AP42 AP40

BD43

AP36 AP34 AP29 AP27 AN45 AN43 AN39 AN37 AN33 AN30

BD39

AN26 AN24 AL46 AL42 AL40 AL36 AL34 AL29 AL27

BD31 BD23 BB35

BGA

SANDY-BRIDGE

MOBILE-REV1

OMIT

U1000

BJ56 BJ52

BG60

AU47 AU41 AU35 AU28 AU22 AU16 AU14 AT61 AT57 AT50

BG56

AT44 AT38 AT31 AT25 AT19 AT11 AT7 AT3 AT1 AR54

BG52

AR47 AR41 AR35 AR28 AR22 AP65 AP63 AP57 AP50 AP44

BG48

AP38 AP31 AP25 AP19 AP17 AP15 AP12 AP11 AP9 AP5

BG44

AN54 AN47 AN41 AN35 AN28 AN22 AM61 AM7 AM3 AM1

BG36

AL57 AL50 AL44 AL38 AL31 AL25 AL19 AK16 AK14 AK11

BG28

AK9 AK5 AJ64 AJ62 AJ60 AJ57 AH7 AH3 AH1 AG57

BG24

AG17 AG15

BG20 BG16

BJ48

BG12

BG8

BF5 BE62 BE58 BE54 BE50 BE46 BE42 BE38

BJ40

BE34 BE30 BE26 BE22 BE18 BE14 BE10 BD35

BD7

BD3

BJ32

BC60 BC56 BC52 BC48 BC44 BC40 BC36 BC32 BC28 BC26

BJ24

BC24 BC20 BC16 BC12 BB65 BB63 BB47 BB39

BB9

BB5

BJ20

BA58 BA54 BA50 BA46 BA42 BA38 BA34 BA30 BA26 BA22

BJ16

BA18 BA14 AY61 AY11

AY7

AY3

AY1 AW56 AW52 AW48

BJ12

AW44 AW40 AW36 AW32 AW28 AW24

AW16 AV65 AV63 AV59

BJ8

AV57 AV50 AV44 AV38 AV31 AV25 AV19 AV9 AV5 AU54

SANDY-BRIDGE

BGA

MOBILE-REV1

OMIT

U1000

AG12 AF65 AF63 AF61 AF11

AF9

AF5 AE57 AD16 AD14

AD7

AD3

AD1 AC64 AC62 AC60 AC57 AB11

AB9

AB5 AA57 AA17 AA15 AA12

Y65

Y63

Y61

Y7 Y3

Y1 W57 V16 V14 V11

V9

V5 U64 U62 U60 U57

T7

T3

T1 R57 R50 R44 R38 R31 R25 R19 R17 R15 R12 P65 P63 P61 P11

P9

P5 N54 N47 N41 N35 N28 N22 M57 M50 M44 M38 M31 M25 M19

M7

M3

M1 L64 L62 L60 L58 L54 L50 L46 L42 L36 L30 L24

L20 L16 L12 L8 K39 K33 K27 K1 J64 J60 J56 J52 J48 J46 J42 J36 J30 J24 J22 J18 J14 J10 J6 H39 H33 H27 H3 G62 G58 G54 G50 G46 G42 G36 G30 G24 G20 G16 G12 G8 F39 F33 F27 E60 E56 E52 E48 E46 E42 E36 E30 E24 E22 E18 E14 E10 E6 E4 D63 D39 D33 D27 C58 C54 C50 C46 C42 C36 C30 C20 C16 C12 C8 B39 B33 B27 A56 A52 A42 A36 A30 A24 A20 A16 A12

A8

BGA

MOBILE-REV1

SANDY-BRIDGE

OMIT

U1000

AV55 AV53

AU20 AU18 AT55 AT53 AT48 AT17 AT15 AT12 AR58 AR56

AV48

AR52 AR49 AR20 AR18 AR16 AR14 AP55 AP53 AP48 AN58

AV17

AN56 AN52 AN49

AN20 AN18 AN16 AN14 AM11 AL55 AL53

AV15

AL48 AL17 AL15 AL12 AK58 AK56 AJ17 AJ15 AJ12 AH16

AV12

AH14 AH11 AF16 AF14 AE17 AE15 AE12 AD11 AC17 AC15

AU58

AC12 AB16 AB14 Y16 Y14 Y11

AU56 AU52 AU49

CPU POWER AND GND

PP1V05_S0PP1V05_S0

PP1V5_S3RS0_CPUDDR

PPVCORE_S0_AXG

14 OF 132 13 OF 105

7 9

10 12 13 14 23 35 39 45

68 70 73

102 104 105

7 9

10 12 13 14 23 35

39 45 68 70 73

102 104

105

7

10 15 29 73

104

7

12 15 49 69

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1600-C16C7):

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

CPU VCCIO/VCCPQ DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1646-C1671):

CPU VCCPLL DECOUPLING

Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

CPU VCORE DECOUPLING

PLACEMENT_NOTE (C1640-C1645):

PLACEMENT_NOTE (C1620-C1623):

PLACEMENT_NOTE (C1624-C16D5):

PLACEMENT_NOTE (C1672-C1681):

Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF)

Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF)

402

10V X5R

10%

1UF

C1612

1

2

10% X5R

402

1UF

10V

C1611

1

2

X5R

10V 402

1UF

10%

C1610

1

2

20% 0201

6.3V

1UF

NOSTUFF

X5R

C16A4

1

2

20% 0201

6.3V X5R

1UF

NOSTUFF

C16A3

1

2

402

X5R

10V

10%

1UF

C1609

1

2

NOSTUFF

20% 0201

X5R

1UF

6.3V

C16A2

1

2

10% 10V X5R 402

1UF

C1608

1

2

X5R

10V

1UF

402

10%

C1607

1

2

20% 0201

6.3V

1UF

NOSTUFF

X5R

C16A1

1

2

6.3V 0201

20% X5R

1UF

NOSTUFF

C16A0

1

2

1

C1631

CRITICAL

6.3V

20%

22UF

Place near inductors on bottom side.

X5R-CERM1 0603

402

X5R

1UF

10V

10%

C1606

1

2

402

X5R

10V

10%

1UF

C1619

1

2

X5R 402

10V

10%

1UF

C1605

1

2

402

10% 10V X5R

1UF

C1618

1

2

10V X5R

10%

402

1UF

C1604

1

2

402

X5R

10V

10%

1UF

C1617

1

2

Place on bottom side of U1000

X5R

1UF

10V 402

10%

C1603

1

2

1UF

10% 10V X5R 402

Place on bottom side of U1000

C1602

1

2

402

X5R

10V

10%

1UF

C1616

1

2

402

X5R

10V

10%

1UF

C1615

1

2

10% X5R

402

Place on bottom side of U100.

1UF

10V

C1601

1

2

10% 10V X5R 402

1UF

C1614

1

2

1UF

Place on bottom side of U1000

10% X5R

10V 402

C1600

1

2

402

X5R

10V

10%

1UF

C1613

1

2

1

C1630

CRITICAL

22UF

20%

Place near inductors on bottom side.

6.3V X5R-CERM1 0603

2

1

C1629

CRITICAL

22UF

Place near inductors on bottom side.

20%

6.3V X5R-CERM1 0603

2.0V D2T-SM

POLY-TANT

20%

470UF-4MOHM

NOSTUFF

Place near inductors on bottom side.

C1643

1

23

2

1

C1627

CRITICAL

Place near inductors on bottom side.

20%

6.3V

22UF

X5R-CERM1 0603

2

1

C1626

20%

Place near inductors on bottom side.

22UF

6.3V

CRITICAL

X5R-CERM1 0603

470UF-4MOHM

Place near inductors on bottom side.

2.0V

20%

D2T-SM

POLY-TANT

CRITICAL

C1642

1

23

470UF-4MOHM

D2T-SM

Place near inductors on bottom side.

2.0V

20% POLY-TANT

CRITICAL

C1641

1

23

Place near inductors on bottom side.

D2T-SM

20%

2.0V

470UF-4MOHM

POLY-TANT

CRITICAL

C1640

1

23

0201

20% X5R

1UF

NOSTUFF

6.3V

C16A6

1

2

20% 0201

6.3V

1UF

X5R

NOSTUFF

C16A5

1

2

CRITICAL

Place near U1000 on bottom side

10UF

20%

6.3V CERM-X5R 0402-1

C1620

1

2

CRITICAL

Place near U1000 on bottom side

CERM-X5R

10UF

6.3V 0402-1

20%

C1621

1

2

CRITICAL

0402-1

6.3V

20%

10UF

Place near U1000 on bottom side

CERM-X5R

C1622

1

2

CRITICAL

Place near U1000 on bottom side

20%

6.3V CERM-X5R

10UF

0402-1

C1623

1

2

1

C1625

22UF

Place near inductors on bottom side.

6.3V

20%

CRITICAL

X5R-CERM1 0603

2

1

C1624

CRITICAL

22UF

20%

Place near inductors on bottom side.

6.3V X5R-CERM1 0603

2

1

C1628

CRITICAL

6.3V

Place near inductors on bottom side.

20%

22UF

0603

X5R-CERM1

2

1

C1632

CRITICAL

22UF

20%

6.3V

Place near inductors on bottom side.

X5R-CERM1 0603

2

1

C1633

CRITICAL

22UF

6.3V

20%

Place near inductors on bottom side.

X5R-CERM1 0603

2

1

C1639

CRITICAL

Place near inductors on bottom side.

22UF

20%

6.3V 0603

X5R-CERM1

2

1

C1638

CRITICAL

20%

6.3V

22UF

Place near inductors on bottom side.

X5R-CERM1 0603

2

CRITICAL

22UF

20%

6.3V

Place near inductors on bottom side.

X5R-CERM1 0603

1

C1637

2

1

20%

6.3V

Place near inductors on bottom side.

0603

X5R-CERM1

22UF

CRITICAL

C1636

2

C1635

CRITICAL

20%

22UF

6.3V

Place near inductors on bottom side.

X5R-CERM1 0603

1

2

1

C1634

CRITICAL

22UF

6.3V

Place near inductors on bottom side.

20% X5R-CERM1

0603

470UF-4MOHM

D2T-SM

POLY-TANT

Place near inductors on bottom side.

20%

2.0V

CRITICAL

C1644

1

23

X5R

10V

10%

1UF

402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

C1686

1

2

1/16W

402

0

MF-LF

5%

R1600

1 2

10%

1UF

10V X5R 402

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

C1685

1

2

10% 10V X5R 402

1UF

C1684

1

2

402

X5R

10%

1UF

10V

C1658

1

2

1UF

10% 10V X5R 402

C1657

1

2

10V

10% X5R

402

1UF

C1656

1

2

402

X5R

10V

10%

1UF

C1655

1

2

402

10V X5R

1UF

10%

C1654

1

2

1UF

X5R

10V

10% 402

C1653

1

2

402

X5R

1UF

10% 10V

C1652

1

2

X5R 402

10V

10%

1UF

C1651

1

2

10% X5R

10V 402

1UF

C1650

1

2

X5R

10%

1UF

Place on bottom side of U1000

10V 402

C1649

1

2

402

10V X5R

10%

1UF

Place on bottom side of U1000

C1648

1

2

10% X5R

402

Place on bottom side of U100.

10V

1UF

C1647

1

2

1UF

Place on bottom side of U1000

10% X5R

10V 402

C1646

1

2

402

X5R

10V

10%

1UF

C1664

1

2

402

10% 10V X5R

1UF

C1663

1

2

10%

402

X5R

10V

1UF

C1662

1

2

402

1UF

X5R

10V

10%

C1661

1

2

402

X5R

10V

10%

1UF

C1660

1

2

10% 10V X5R 402

1UF

C1659

1

2

10%

402

X5R

10V

1UF

C1671

1

2

1UF

402

10% 10V X5R

C1670

1

2

402

X5R

10V

10%

1UF

C1669

1

2

402

X5R

10V

10%

1UF

C1668

1

2

X5R 402

10V

10%

1UF

C1667

1

2

402

10% 10V X5R

1UF

C1666

1

2

402

X5R

10V

10%

1UF

C1665

1

2

Place near U1000 on bottom side

CRITICAL

10UF

6.3V

20% X5R

603

C1675

1

2

CRITICAL

Place near U1000 on bottom side

6.3V

10UF

20% X5R

603

C1674

1

2

CRITICAL

6.3V

20%

Place near U1000 on bottom side

10UF

X5R 603

C1673

1

2

10UF

CRITICAL

6.3V

Place near U1000 on bottom side

20% X5R

603

C1672

1

2

CRITICAL

10UF

20%

6.3V

Place near U1000 on bottom side

X5R 603

C1679

1

2

CRITICAL

10UF

20%

6.3V

Place near U1000 on bottom side

X5R 603

C1678

1

2

CRITICAL

6.3V

10UF

20%

Place near U1000 on bottom side

X5R 603

C1677

1

2

CRITICAL

6.3V

20%

Place near U1000 on bottom side

10UF

X5R 603

C1676

1

2

CRITICAL

20%

6.3V

10UF

Place near U1000 on bottom side

X5R 603

C1681

1

2

CRITICAL

6.3V

20%

10UF

Place near U1000 on bottom side

X5R 603

C1680

1

2

Place near inductors on bottom side

CRITICAL

20% 2V POLY CASE-D2-SM

330UF-0.006OHM

C1682

1

2

0603

MF

1/4W

1%

0.010

R1601

1 2

NOSTUFF

1UF

X5R

20%

6.3V 0201

C16A7

1

2

NOSTUFF

1UF

X5R 0201

6.3V

C16A8

1

2

20%

NOSTUFF

1UF

X5R

20%

6.3V 0201

C16A9

1

2

NOSTUFF

1UF

X5R

20%

6.3V 0201

C16B0

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B1

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B2

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B3

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B4

1

2

NOSTUFF

X5R 0201

1UF

20%

6.3V

C16B5

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B6

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B7

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B8

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B9

1

2

NOSTUFF

1UF

X5R

20%

6.3V 0201

C16C0

1

2

NOSTUFF

1UF

6.3V 0201

20% X5R

C16C7

1

2

6.3V 0201

20% X5R

1UF

NOSTUFF

C16C6

1

2

X5R

20%

6.3V

1UF

NOSTUFF

0201

C16C5

1

2

1UF

X5R

20%

6.3V

NOSTUFF

0201

C16C4

1

2

NOSTUFF

1UF

20%

6.3V 0201

X5R

C16C3

1

2

NOSTUFF

1UF

X5R

20%

0201

6.3V

C16C1

1

2

1UF

X5R

20%

0201

6.3V

NOSTUFF

C16C2

1

2

1

C16D3

Place near inductors on bottom side.

6.3V

20%

22UF

NOSTUFF

X5R-CERM1 0603

2

1

C16D2

Place near inductors on bottom side.

6.3V

20%

22UF

NOSTUFF

X5R-CERM1 0603

2

1

C16D1

Place near inductors on bottom side.

6.3V

22UF

20%

NOSTUFF

X5R-CERM1 0603

2

1

C16D0

Place near inductors on bottom side.

20%

6.3V

22UF

NOSTUFF

X5R-CERM1 0603

330UF-0.006OHM

CASE-D2-SM

CRITICAL

Place near inductors on bottom side

POLY

20% 2V

C1683

1

2

330UF-0.006OHM

PLACE_NEAR=U1000.AK61:5 mm

CASE-D2-SM

CRITICAL

20% 2V POLY

C1687

1

2

SYNC_DATE=07/21/2010

SYNC_MASTER=K91_MLB

CPU DECOUPLING-I

PPVCORE_S0_CPU

PP1V05_S0

PP1V05_S0_CPU_VCCPQE

PP1V8_S0

PP1V8_S0_CPU_VCCPLL_R

16 OF 132 14 OF 105

6 7

12 49 69

105

7 9

10 12 13

23 35 39 45

68 70 73

102 104 105

7

10 12

6 7

20 25 71 72 88

102

7

12

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)

Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

PLACEMENT_NOTE (C1758-C1762):

PLACEMENT_NOTE (C1700-C1708):

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

CPU VDDQ/VCCDQ DECOUPLING

PLACEMENT_NOTE (C1738-C1747):

Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

CPU VCCSA DECOUPLING

Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

PLACEMENT_NOTE (C1726-C1731):

PLACEMENT_NOTE (C1718-C1723):

Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 6x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)

VAXG DECOUPLING

PLACEMENT_NOTE (C1734-C1735):

NOSTUFF

10V 402

X5R

10%

1UF

C1717

1

2

402

NOSTUFF

10% 10V X5R

1UF

C1716

1

2

NOSTUFF

10% 10V X5R 402

1UF

C1715

1

2

NOSTUFF

402

X5R

10V

10%

1UF

C1714

1

2

NOSTUFF

402

X5R

10V

10%

1UF

C1713

1

2

10V

1UF

NOSTUFF

402

10% X5R

C1712

1

2

1UF

10% 10V

402

NOSTUFF

X5R

C1711

1

2

10% X5R

402

1UF

NOSTUFF

10V

C1710

1

2

NOSTUFF

1UF

10% X5R

402

10V

C1709

1

2

1UF

402

10% 10V X5R

C1708

1

2

X5R 402

10V

10%

1UF

C1707

1

2

X5R

1UF

10% 10V

402

C1706

1

2

CERM-X5R

6.3V

10UF

NOSTUFF

20%

0402-1

Place close to U1000 on bottom side

C1725

1

2

Place close to U1000 on bottom side

CERM-X5R

6.3V

20%

10UF

NOSTUFF

0402-1

C1724

1

2

1

C1733

Place near inductors on bottom side.

6.3V

20%

NOSTUFF

22UF

X5R-CERM1 0603

2

1

C1732

NOSTUFF

Place near inductors on bottom side.

6.3V

20%

22UF

X5R-CERM1 0603

X5R

10V

10%

402

1UF

C1705

1

2

Place close to U1000 on bottom side

20%

6.3V

10UF

CERM-X5R 0402-1

C1723

1

2

10V X5R

10%

402

1UF

C1704

1

2

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

C1722

1

2

Place on bottom side of U1000

X5R

10%

1UF

10V 402

C1703

1

2

6.3V

Place close to U1000 on bottom side

10UF

20% CERM-X5R

0402-1

C1721

1

2

1

C1731

Place near inductors on bottom side.

20%

6.3V

22UF

X5R-CERM1 0603

2

1

C1730

22UF

20%

6.3V

Place near inductors on bottom side.

X5R-CERM1 0603

2

1

C1729

6.3V

Place near inductors on bottom side.

20%

22UF

X5R-CERM1 0603

2.0V

20%

D2T-SM

POLY-TANT

NOSTUFF

470UF-4MOHM

Place near inductors on bottom side.

C1737

1

23

Place on bottom side of U1000

10% 10V

402

X5R

1UF

C1702

1

2

1UF

10% X5R

Place on bottom side of U100.

402

10V

C1701

1

2

6.3V

Place close to U1000 on bottom side

10UF

0402-1

CERM-X5R

20%

C1720

1

2

10UF

CERM-X5R

Place close to U1000 on bottom side

20%

6.3V 0402-1

C1719

1

2

X5R

Place on bottom side of U1000

10% 10V

402

1UF

C1700

1

2

Place close to U1000 on bottom side

10UF

20%

0402-1

6.3V CERM-X5R

C1718

1

2

1

C1728

6.3V

22UF

20%

Place near inductors on bottom side.

X5R-CERM1 0603

2

1

C1727

22UF

20%

Place near inductors on bottom side.

6.3V X5R-CERM1 0603

POLY-TANT D2T-SM

20%

Place near inductors on bottom side.

470UF-4MOHM

2.0V

C1735

1

23

2

1

C1726

20%

22UF

Place near inductors on bottom side.

6.3V X5R-CERM1 0603

2.0V D2T-SM

20%

Place near inductors on bottom side.

POLY-TANT

470UF-4MOHM

C1734

1

23

X5R

10%

1UF

10V

402

C1757

1

2

X5R

10V 402

10%

1UF

C1747

1

2

10% 10V

1UF

402

X5R

C1746

1

2

402

X5R

10V

10%

1UF

C1745

1

2

X5R

1UF

10% 10V

402

C1744

1

2

X5R 402

10V

10%

1UF

C1743

1

2

402

10V X5R

10%

1UF

C1742

1

2

X5R

10% 10V

1UF

402

Place on bottom side of U1000

C1741

1

2

X5R 402

Place on bottom side of U1000

10% 10V

1UF

C1740

1

2

402

10% X5R

Place on bottom side of U100.

10V

1UF

C1739

1

2

10V

Place on bottom side of U1000

10% X5R

402

1UF

C1738

1

2

20%

10UF

6.3V X5R

Place close to U1000 on bottom side

603

C1755

1

2

10UF

20%

6.3V

Place close to U1000 on bottom side

X5R 603

C1754

1

2

10UF

20%

Place close to U1000 on bottom side

6.3V X5R 603

C1753

1

2

10UF

6.3V

20%

Place close to U1000 on bottom side

X5R 603

C1752

1

2

6.3V

20%

Place close to U1000 on bottom side

10UF

X5R 603

C1751

1

2

10UF

6.3V

20%

Place close to U1000 on bottom side

X5R 603

C1750

1

2

10UF

Place close to U1000 on bottom side

20%

6.3V X5R 603

C1749

1

2

6.3V

20%

Place close to U1000 on bottom side

10UF

X5R 603

C1748

1

2

10V X5R

10%

402

1UF

C1762

1

2

Place on bottom side of U1000

X5R

10%

402

10V

1UF

C1761

1

2

6.3V

10UF

20% X5R

603

C1767

1

2

20%

6.3V

10UF

X5R 603

C1766

1

2

X5R

1UF

10% 10V

402

Place on bottom side of U1000

C1760

1

2

402

X5R

10% 10V

1UF

Place on bottom side of U100.

C1759

1

2

20%

10UF

6.3V X5R 603

C1765

1

2

6.3V

20%

10UF

X5R 603

C1764

1

2

X5R

Place on bottom side of U1000

1UF

10% 10V

402

C1758

1

2

603

6.3V

20%

10UF

X5R

C1763

1

2

1%

0.010

0603

MF

1/4W

R1700

1 2

20% TANT

2V CASE-B4-SM

270UF

C1768

1

2

Place near inductors on bottom side

CASE-D2-SM

330UF-0.006OHM

2V

20% POLY

CRITICAL

C1756

1

2

SYNC_MASTER=K91_MLB

CPU DECOUPLING-II

SYNC_DATE=07/21/2010

PPVCORE_S0_AXG

PP1V5_S3_CPU_VCCDQ

PPVCCSA_S0_CPU

PP1V5_S3RS0_CPUDDR

17 OF 132 15 OF 105

7

12 13 49 69

7

12

7

12 65

7

10 13 29 73

104

IN

OUT

IN

BI

OUT

BI

IN

IN OUT OUT

IN IN

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

IN

IN IN

IN

OUT

BI

OUT

BI

IN IN OUT OUT

OUT

BI

OUT

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0 HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0

RTCX1 RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

SATA1RXP SATA1TXN

SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5TXN SATA5TXP

SATAICOMPO SATAICOMPI

SATALED*

SATA0GP/GPIO21 SATA1GP/GPIO19

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

JTAG

SPI

SATA

LPC

IHDA

RTC

(1 OF 10)

(2 OF 10)

PCI-E*

PEG

FROM CLK BUFFER

CLOCK

FLEX

SMBUS

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

PERN3

PETP2

PETN2

PERP1

CL_RST1*

CL_DATA1

CL_CLK1

CLKIN_GND1_P

CLKIN_GND1_N

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

XCLK_RCOMP

XTAL25_OUT

XTAL25_IN

CLKIN_PCILOOPBACK

REFCLK14IN

CLKIN_SATA_N CLKIN_SATA_P

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_DP_N CLKOUT_DP_P

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE4P

CLKOUT_PCIE5N

CLKOUT_PCIE3P

CLKOUT_PCIE4N

CLKOUT_PCIE3N

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1N CLKOUT_PCIE1P

CLKOUT_PCIE0N CLKOUT_PCIE0P

PETN1

PERN1

SMBCLK

SMBALERT*/GPIO11

PETP8

PERP8 PETN8

PETP7

PERN8

PETN7

PERP7

PERN7

PETN6 PETP6

PERP6

PERN6

PETP5

PETN5

PERP5

PETP4

PERN5

PETN4

PERP4

PETP3

PERN4

PETN3

PERP3

PERN2 PERP2

PETP1

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0ALERT*/GPIO60

SML0CLK

SMBDATA

IN IN IN

IN

OUT OUT

IN

OUT

OUT OUT

NC

OUT

IN

IN OUT OUT

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1.8V -> 1.1V

DOES THIS NEED LENGTH MATCH???

(IPU)

R1849 cannot be used w/ VCCSUSHDA on S0

Q1850 376S0859 376S0859 VGS 0.35~1V

(IPU)

UNUSED clock terminations for FCIM MODE

25

57 95

47 95

6

45 47 88 95

6

45 47 88 95

6

45 47 88 95

6

45 47 88 95

6

45 47 88 95

6

45 47

6

41 94

6

41 94

6

41 94

6

41 94

36 95

6

31 95

6

31 95

38 95

36 95

31 95

38 95

36 95

31 95

38 95

16 23 39

10 92

74 95

16 95

25 95

48 95

6

23 26 28 30 32

41 48 62 89 95

6

23 26 28 30 32

41 48 62 89 95

6

32

100

6

32

100

32

100

32

100

2

1

R1800

201

MF

330K

5%

1/20W

1M

MF 201

1/20W

5%

R1801

1

2

1

R1802

1/20W

MF

20K

5%

201

2

1

R1803

20K

5%

201

1/20W MF

2

1

C1803

10%

1UF

X5R 402

10V

2

1

1UF

10%

X5R

10V

402

C1802

2

1

R1830

PLACE_NEAR=U1800.Y11:2.54mm

201

1/20W

MF

37.4

1%

2

1

R1820

201

MF

1/20W

5%

10K

2

1

R1890

201

MF 1%

90.9

1/20W

PLACE_NEAR=U1800.Y47:2.54mm

201

1/20W

33

MF

5%

PLACE_NEAR=U1800.N34:1.27mm

R1810

1 2

21

R1811

201

1/20W

33

5%

PLACE_NEAR=U1800.L34:1.27mm

MF

PLACE_NEAR=U1800.K34:1.27mm

21

R1812

201

MF

33

5%

1/20W

21

R1813

PLACE_NEAR=U1800.A36:1.27mm

201

1/20W

MF

5%

33

57 95

48 95

16 33

21

R1860

33

201

1/20W

MF5%

21

R1861

1/20W

MF

33

5%

201

21

R1862

201

MF

33

1/20W

5%

21

20133MF

1/20W

R1863

5%

21

R1864

201

MF

33

1/20W

5%

2

1

R1832

201

1/20W

5%

750

MF

PLACE_NEAR=U1800.AH1:2.54mm

201

MF

1/20W

49.9

1%

R1831

1

2

PLACE_NEAR=U1800.AB12:2.54mm

2

1

R1870

MF

1/20W

5%

10K

201

2

1

R1871

10K

1/20W

201

MF

5%

AP7

T10

V4

U3

T1

T3

P3

Y11 Y10

AB1

AB3

Y1

Y3

AD1

AD3

Y5

Y7

AF1

AF3

AB10

AB8

AH1

AB13

AH4

AH5

AD5

AD7

AP10

AP11

AM8

AM10

P1

AP5

AM1

AM3

V14

C20

A20

K36

H7

H1

K5

J3

K22

L34

A36

A34

C34

G34

E34

K34

N32

C36

N34

D36

C37

B37

A38

C38

U1800

MOBILE

COUGAR-POINT

FCBGA

OMIT

Y14

D20

AB12

C17

G22

E36

V5

V49

V47

Y47

M16

E14

C13

G12

C8

A12

C9

H14

E12

K45

AY38

BB40

AV36

BB36

BB34

AU34

AY32

AU32

AW38

AY40

AU36

AY36

AY34

AV34

BB32

AV32

BC38

BJ40

BG38

BH37

BE36

BJ36

BF34

BJ34

BE38

BG40

BJ38

BG37

BF36

BG36

BE34

BG34

E6

M10

L14

L12

A8

V10

M1

J2

K49

H47

F47

K43

AB40

AB42

AB38

AB37

V46

V45

Y45

Y43

Y36

Y37

AA47

AA48

AB47

AB49

Y39

Y40

AK13

AK14

AM13

AM12

AU22

AV22

AK5

AK7

H45

BG30

BJ30

E24

G24

BE18

BF18

P10

T11

M7

U1800

FCBGA

OMIT

MOBILE

COUGAR-POINT

16 36

16 23 31

16 32

8

16 88

32 95

2

1

R1877

5%

1/20W

MF

4.7K

201

2

1

R1866

10K

NOSTUFF

1/20W

201

MF

5%

16 35

25

23

33 95

36 95

2

1

R1878

201

5%

1/20W

MF

4.7K

2

1

R1855

5%

201

MF

10K

1/20W

2

1

R1854

5%

10K

1/20W MF 201

2

1

R1853

5%

201

MF

1/20W

10K

2

1

R1848

MF

10K

5%

1/20W

201

1/20W

2

1

201

10K

5%

MF

R1847

2

1

R1833

5%

10K

MF

201

NOSTUFF

1/20W

10K

2

1

R1834

5%

201

MF

1/20W

2

1

R1843

5%

201

MF

1/20W

10K

2

1

R1846

1/20W

MF

5%

10K

201 201

2

1

R1845

5%

10K

MF

1/20W

2

1

R1844

MF

5%

1/20W

10K

201

2

1

R1842

5%

MF

10K

1/20W

201

2

1

R1869

1/20W

5%

MF

10K

201

2

1

R1876

10K

5%

201

1/20W

MF

2

1

R1849

NOSTUFF

10K

201

1/20W

5%

2 1

R1840

NOSTUFF

MF5%

1/20W

0

201

2 1

R1841

NOSTUFF

MF

1/20W

5%

201

0

16 23 41

21

R1872

1%

MF-LF

1/16W

604

402

2

1

R1873

1/20W

1%

1K

201

MF

25

41 94

1/20W MF

10K

5%

201

R1897

1

2

10K

5%

201

1/20W MF

R1896

1

2

10K

1/20W

5%

201

MF

1

2

R1895

10K

5%

201

1/20W MF

R1894

1

2

10K

5% 1/20W MF 201

R1893

1

2

10K

5% MF

201

1/20W

R1892

1

2

10K

201

5% MF

1/20W

R1891

1

2

16 23 85

2 1

R1888

201

0

MF

1/20W

5%

NOSTUFF

19 45

PCH SATA/PCIE/CLK/LPC/SPI

SYNC_MASTER=K91_MLB

SYNC_DATE=10/19/2010

PCH_SRTCRST_L

PPVRTC_G3H

RTC_RESET_L

PCH_INTVRMEN_L

PCH_INTRUDER_L

PCH_SRTCRST_L

PCH_INTVRMEN_L

HDA_SYNC_R

NC_HDA_SDIN1

HDA_SDOUT_R

JTAG_T29_TMS

PP3V3_S0_PCH

LPC_R_AD<2>

PCH_SPKR

HDA_SDIN0

ENET_MEDIA_SENSE_RDIV

SPI_CS0_R_L

PCH_SATA3RBIAS

DP_AUXCH_ISOL

SATA_HDD_R2D_C_N

T29_PWR_EN

LPC_FRAME_R_L

LPC_R_AD<1>

LPC_R_AD<0>

LPC_SERIRQ

EXCARD_CLKREQ_L

PCH_SATALED_L

PCH_CLK14P3M_REFCLK

PEG_CLKREQ_L

T29_CLKREQ_L

PCIE_CLK100M_PCH_P PCH_CLK100M_SATA_N

PCIE_CLK100M_PCH_N

NC_SATA_D_R2D_CP

TP_SATA_E_D2RN

PCH_SATAICOMP

PCIE_CLK100M_FW_N

FW_CLKREQ_L

SML_PCH_0_ALERT_L

PEG_B_CLKRQ_L_GPIO56

SATA_HDD_R2D_C_P

HDA_SYNC_R HDA_SDOUT_R

PP1V5_S0

PP3V3_T29

PP3V3_S0_PCH PP3V3_SUS

ENET_CLKREQ_L

AP_CLKREQ_L

FW_CLKREQ_L

PCH_SPKR

JTAG_T29_TMS

SATARDRVR_EN

PPVCCIO_S0_PCH

PCH_SATA3COMP

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_P

TP_LPC_DREQ0_L

TP_SPI_CS1_L

SPI_MISO

SPI_MOSI_R

XDP_PCH_TDO

XDP_PCH_TMS

XDP_PCH_TCK

SATA_ODD_R2D_C_P

HDA_RST_R_L

NC_HDA_SDIN2 NC_HDA_SDIN3

SYSCLK_CLK32K_RTC

TP_SATA_B_D2RN TP_SATA_B_D2RP

ENET_CLKREQ_L

TP_PCIE_CLK100M_PEBN TP_PCIE_CLK100M_PEBP

NC_PCIE_5_R2D_CP

NC_PCIE_5_R2D_CN

TP_SATA_F_D2RN

SATARDRVR_EN

HDA_SYNC

TP_SATA_F_D2RP

NC_PCIE_7_R2D_CP

NC_SATA_D_D2RP

NC_SATA_D_D2RN

SMC_SCI_L

SML_PCH_1_ALERT_L

ITPCPU_CLK100M_P

ITPXDP_CLK100M_N

HDA_RST_R_L

HDA_SDOUT

HDA_RST_L

ITPCPU_CLK100M_N

SYSCLK_CLK25M_SB

PP3V3_SUS

PCH_GPIO11

SMBUS_PCH_CLK SMBUS_PCH_DATA

SML_PCH_0_ALERT_L

SML_PCH_0_CLK

PEG_CLK100M_N PEG_CLK100M_P

DMI_CLK100M_CPU_N

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLK96M_DOT_N

PCH_CLK14P3M_REFCLK

SML_PCH_1_CLK

SML_PCH_1_ALERT_L

PCH_XCLK_RCOMP

NC_PCIE_CLK100M_PE5P

AP_CLKREQ_L

T29_CLKREQ_L

SYSCLK_CLK25M_SB_R

PCH_CLK33M_PCIIN

HDA_SYNC_R

TP_SATA_B_R2D_CP

TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CN

PCH_SATALED_L

TP_SATA_B_R2D_CN

SATA_ODD_R2D_C_N

TP_SATA_F_R2D_CP

SATA_ODD_D2R_N

NC_SATA_D_R2D_CN

PCIE_EXCARD_D2R_P

SATA_ODD_D2R_P

PCIECLKRQ5_L_GPIO44

PPVCCIO_S0_PCH

LPC_AD<3>

PCIE_FW_D2R_N PCIE_FW_D2R_P PCIE_FW_R2D_C_N

PP3V3_SUS

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

DP_AUXCH_ISOL

LPC_FRAME_L

LPC_AD<2>

LPC_AD<1>

HDA_BIT_CLK

XDP_PCH_TDI

TP_PCH_CLKOUT_DPP

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_T29_N

HDA_BIT_CLK_R

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_P

PCIE_CLK100M_FW_P

PCIE_CLK100M_AP_P

PCIECLKRQ5_L_GPIO44

PCIE_CLK100M_EXCARD_N

PEG_B_CLKRQ_L_GPIO56

PCH_INTRUDER_L

RTC_RESET_L

SPI_CLK_R

HDA_BIT_CLK_R

TP_PCH_GPIO65_CLKOUTFLEX1

HDA_SDOUT_R

PEG_CLKREQ_L

TP_PCH_GPIO64_CLKOUTFLEX0

LPC_AD<0>

DMI_CLK100M_CPU_P

PPVCCIO_S0_PCH

TP_PCH_GPIO66_CLKOUTFLEX2

PCH_CLK100M_SATA_N

TP_CLINK_CLK

PCH_CLKIN_GNDP1

ITPXDP_CLK100M_N

TP_PCH_GPIO67_CLKOUTFLEX3

TP_CLINK_RESET_L

TP_CLINK_DATA

ITPXDP_CLK100M_P

PCH_CLKIN_GNDN1

PCIE_AP_D2R_N

SML_PCH_1_DATA

SML_PCH_0_DATA

TP_PCH_CLKOUT_DPN

PCIE_CLK100M_ENET_P

EXCARD_CLKREQ_L

SYSCLK_CLK25M_SB_R

PCIE_CLK100M_T29_P

NC_PCIE_CLK100M_PE5N

PCIE_AP_D2R_P

PCIE_AP_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_AP_R2D_C_N

PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N

PCIE_ENET_R2D_C_P

PP3V3_S0_PCH

PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P

NC_PCIE_5_D2RN NC_PCIE_5_D2RP

NC_PCIE_6_D2RN

NC_PCIE_7_R2D_CN

NC_PCIE_7_D2RP

NC_PCIE_7_D2RN

NC_PCIE_6_R2D_CN

NC_PCIE_6_D2RP

NC_PCIE_8_D2RN

NC_PCIE_6_R2D_CP

NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN

ITPXDP_CLK100M_P

PP3V3_S0_PCH

PCIE_CLK100M_AP_N

PCH_GPIO11

NC_PCIE_8_R2D_CP

PCIE_CLK100M_ENET_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

LPC_R_AD<3>

18 OF 132 16 OF 105

16

7

17 20 25

16

16 95

6

16 95

16 17 18 19 20 22

102

16

35

16 32

16

16 95

8

16 88

16 35

16 95

6

94

16

16 95

7

20 22 25 32 41 57 71

7

19 25 33 34 35 88

16 17 18 19 20 22

102

7

16 17 18 19 20 22 46 71 72

73

16 36

16 23 31

16 23 39

16

16 33

16 17 20 22

102 104

94

16 95

6

16 23 41

6

16

10 92

16 23 92

16 95

10 92

7

16 17 18 19 20 22 46 71 72

73

16

6

16

16 95

16

6

16

16 17 20 22

102 104

7

16 17 18 19 20 22 46 71 72

73

16 23 85

16 95

16

16 95

16 17 20 22

102 104

16 23 92

16

6

16 17 18 19 20 22

102

16 23 92

16 17 18 19 20 22

102

16

IN

OUT

OUT OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

(3 OF 10)

MANAGEMENT

SYSTEM POWER

DMI

FDI

DMI1RXN

DMI2RBIAS

FDI_RXP6

DMI3RXN

DMI0RXN

FDI_RXN5

FDI_RXN4

FDI_RXN2 FDI_RXN3

FDI_RXN1

FDI_RXN0

RI*

BATLOW*/GPIO72

PWROK

SYS_PWROK

SYS_RESET*

DMI_ZCOMP

DMI3TXP

DMI2TXP

DMI1TXP

DMI3TXN

DMI0TXP

DMI1TXN DMI2TXN

SUSACK*

SLP_SUS*

DSWVRMEN

DF_TVS

PMSYNCH

TP23

SLP_LAN*/GPIO29

SLP_A*

SLP_S4*

SLP_S5*/GPIO63

SUS_STAT*/GPIO61

SUSCLK/GPIO62

CLKRUN*/GPIO32

WAKE*

FDI_LSYNC1

FDI_FSYNC1

FDI_LSYNC0

FDI_FSYNC0

FDI_INT

FDI_RXP7

FDI_RXP4 FDI_RXP5

FDI_RXP2

FDI_RXP1

FDI_RXP3

FDI_RXP0

FDI_RXN7

FDI_RXN6

DRAMPWROK

DMI2RXN

DMI0TXN

DMI_IRCOMP

SLP_S3*

PWRBTN*

APWROK

RSMRST*

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DPWROK

SUSWARN*/SUSPWRDNACK/GPIO30

ACPRESENT/GPIO31

(4 OF 10)

DIGITAL DISPLAY INTERFACE

CRT

RSVD

DDPD_3P

DDPD_2P DDPD_3N

DDPD_2N

DDPD_1P

DDPD_1N

DDPD_0P

DDPD_0N

DDPD_HPD

DDPD_AUXN DDPD_AUXP

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_3N DDPC_3P

DDPC_2N DDPC_2P

DDPC_1N

DDPC_0P

DDPC_1P

DDPC_0N

DDPC_HPD

DDPC_AUXP

DDPC_AUXN

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPB_3P

DDPB_3N

DDPB_2N DDPB_2P

DDPB_1P

DDPB_1N

DDPB_0P

DDPB_HPD

DDPB_0N

DDPB_AUXP

DDPB_AUXN

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTN SDVO_INTP

SDVO_STALLN SDVO_STALLP

SDVO_TVCLKINN SDVO_TVCLKINP

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

CRT_IRTN

DAC_IREF

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

IN

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Set to Vcc when High

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low

T29 WAKE

PD on SMC page

9

92

9

92

9

92

9

92

9

92

9

92

PLACE_NEAR=U1800.BJ24:12.7mm

MF

1%

49.9

1/20W

201

R1900

1

2

6

17 25 31 32 85

6

17 45 47

46

17 45 73

17 29 42 45 66 73

6

17 29 45 73

10 29 92

73

17 23 45

46

17 91

45

23 91

6

25 45

9

92

6 9

92

6 9

92

6 9

92

6 9

92

9

92

9

92

9

92

9

92

9

92

9

92

6 9

92

6 9

92

6 9

92

6 9

92

10 92

6

45 47

PLACE_NEAR=U1800.T43:2.54mm

5%

1K

MF

1/20W

201

R1951

1

2

201

1/20W

MF

5%

100K

R1909

1

2

201

1/20W MF

1%

750

R1920

1

2

PLACE_NEAR=U1800.BH21:2.54mm

5% MF

1/20W

201

2.2K

R1981

1

2

MF5%

1/20W

1K

201

R1980

12

MOBILE

FCBGA

COUGAR-POINT

OMIT

U1800

H20

L10

E10

N3

AY1

BC24

BE24

AW24

AY24

BE20

BC20

AW20

AY20

BH21

BG18

BJ18

BB18

AY18

BG20

BJ20

AV18

AU18

BG25

BJ24

E22

B13

A18

AV12 BC10

AW16

AV14 BB10

AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AP14

E20

L22

A10

C21

G10

K14

F4

H4

D10

G16

G8

C12

N14

K16

P12

K3

AY16

B9

BJ14

COUGAR-POINT

OMIT

MOBILE

FCBGA

U1800

N48

T39 M40

P49

M47

T42

T49

M49

T43

AV42 AV40 AV45 AV46 AU48

AU47 AV47

AV49

AT49 AT47 AT40

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

AP47 AP49

P46 P42

AT38

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

AT45 AT43

M43 M36

BH41

AT1

AT10 AT12

AT3 AT4 AT5 AT8

AU2 AU3 AV1

AV10

AV3 AV5 AV7

AY3 AY5 AY7 BA2 BA3 BB1 BB3 BB5 BB7 BC8 BD4 BE8 BF3 BF6 BG4

P38 M39

AP39 AP40

AM42 AM40

AP43 AP45

390K

5% MF

1/20W

201

R1915

1

2

8.2K

5%

201

MF

1/20W

R1991

1

2

45 46 73

17

17 91

1K

1/20W

1%

201

MF

R1985

1

2

1K

1%

MF

201

1/20W

R1925

1

2

1/20W

MF

201

5%

10K

1

2

R1982

1/20W

MF

201

5%

10K

R1983

1

2

1/20W

10K

201

MF

5%

R1905

1

2

MF

0

5%

201

1/20W

R1986

12

17

17 73

100K

201

1/20W

MF

5%

R1921

1

2

100K

5%

MF

1/20W

201

R1922

1

2

100K

5%

MF

1/20W

201

R1923

1

2

201

1/20W

MF

5%

100K

R1924

1

2

6

17 25 31 32 85

6

17 25 31 32 85

PCH DMI/FDI/GRAPHICS

PCH_DMI_COMP

PCIE_WAKE_L

MAKE_BASE=TRUE

PCIE_WAKE_L

FDI_DATA_N<1> FDI_DATA_N<2>

PM_PCH_PWROK

NC_DP_IG_D_CTRL_CLK

NC_DP_IG_C_MLP<3>

PM_MEM_PWRGD

PM_SYSRST_L

NC_CRT_IG_RED

DMI_S2N_N<0>

FDI_DATA_P<7>

PM_PCH_SYS_PWROK

PM_PCH_PWROK

NC_CRT_IG_HSYNC

PCIE_WAKE_L

FDI_FSYNC<1>

DMI_S2N_N<2>

FDI_DATA_P<4>

FDI_LSYNC<0>

DMI_S2N_P<0>

TP_DP_IG_B_MLP<3>

DP_IG_HPD

DP_IG_AUX_CH_P

DMI_S2N_N<3>

NC_DP_IG_D_MLN<2>

NC_DP_IG_D_MLN<3>

NC_DP_IG_C_MLN<1>

NC_DP_IG_D_CTRL_DATA

NC_DP_IG_C_MLP<1>

NC_DP_IG_D_AUXP NC_DP_IG_D_HPD

NC_DP_IG_D_MLN<0>

NC_DP_IG_D_MLP<1>

NC_DP_IG_D_MLP<3>

NC_SDVO_TVCLKINP

NC_SDVO_TVCLKINN

NC_DP_IG_C_MLN<2>

NC_DP_IG_D_MLP<2>

NC_DP_IG_D_AUXN

NC_DP_IG_C_AUXN

NC_DP_IG_D_MLN<1>

NC_DP_IG_D_MLP<0>

FDI_DATA_N<7>

FDI_DATA_P<2>

FDI_DATA_N<0>

FDI_DATA_N<3>

FDI_DATA_N<5>

NC_SDVO_STALLN NC_SDVO_STALLP

NC_SDVO_INTN NC_SDVO_INTP

DP_IG_DDC_CLK

DP_IG_AUX_CH_N

TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<0>

DP_IG_DDC_DATA

NC_DP_IG_C_MLP<0>

NC_DP_IG_C_MLN<0>

NC_DP_IG_C_HPD

NC_DP_IG_C_AUXP

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_CTRL_CLK

TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2> TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3>

NC_DP_IG_C_MLN<3>

NC_CRT_IG_DDC_DATA

NC_CRT_IG_GREEN

NC_CRT_IG_BLUE

PPVRTC_G3H

NC_DP_IG_C_MLP<2>

FDI_DATA_P<5> FDI_DATA_P<6>

FDI_FSYNC<0>

FDI_DATA_N<6>

FDI_DATA_P<0>

NC_CRT_IG_VSYNC

NC_CRT_IG_DDC_CLK

PP3V3_SUS

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_N<0>

PPVCCIO_S0_PCH

DMI_N2S_N<2>

DMI_S2N_N<1>

PCH_DMI2RBIAS

PM_RSMRST_L

FDI_DATA_N<4>

FDI_INT

PM_BATLOW_L

PCIE_WAKE_L

PM_PWRBTN_L

SUSWARN_L

PCH_SUSACK_L

GPIO29_SLP_LAN_L

FDI_LSYNC<1>

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PM_CLKRUN_L

FDI_DATA_P<3>

FDI_DATA_P<1>

DMI_N2S_N<1>

PCH_DAC_IREF

CPU_PROC_SEL_L

PCH_SUSACK_L

SUSWARN_L GPIO29_SLP_LAN_L

PP1V8_S0_PCH

PCH_DF_TVS

PM_SLP_S4_L

PM_SYNC

TP_PCH_TP23

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_SUS_L

TP_PM_SLP_A_L

PM_SLP_S3_L

PCH_DSWVRMEN

PM_SLP_SUS_L

PM_CLKRUN_L

PP3V3_S0_PCH

DMI_N2S_N<3>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_N2S_P<3>

PM_DSW_PWRGD

SMC_ADAPTER_EN

SUSWARN_L

PP3V3_SUS

PCH_RI_L

PP3V3_S5

PP3V3_SUS

19 OF 132 17 OF 105

9

92

9

92

6

9

92

6

9

92

8

84

8

84 94

6

9

92

9

92

9

92

9

92

9

92

6

8

80 84

8

84 94

8

80 84

6

7

16 20 25

6

9

92

9

92

9

92

9

92

6

7

16 17 18 19 20 22 46 71 72 73

16 20 22

102 104

9

92

6

17 25 31 32 85

17 23 45

17

9

92

9

92

10 92

17

20 22

102

17 29 42 45 66 73

6

17 29 45 73

17 45 73

17 73

6

17 45 47

16 18 19 20 22

102

17

7

16 17 18 19 20 22 46 71

72 73 6 7

19 20 22 23 24

25 29 46 48 56 71 72 73 83

86 91

100 102

104

7

16 17 18 19 20 22 46

71 72 73

OUT

USBP2N

USBP1N USBP1P

USBP0N USBP0P

OC7*/GPIO14

OC6*/GPIO10

OC5*/GPIO9

OC4*/GPIO43

OC3*/GPIO42

OC2*/GPIO41

OC1*/GPIO40

OC0*/GPIO59

USBRBIAS*

USBRBIAS

USBP13P

USBP13N

USBP12P

USBP12N

USBP11P

USBP11N

USBP10P

USBP10N

USBP9P

USBP9N

USBP8P

USBP8N

USBP7N USBP7P

USBP6N USBP6P

USBP5N USBP5P

USBP4P

USBP4N

USBP3P

USBP3N

USBP2P

PIRQA* PIRQB* PIRQC* PIRQD*

REQ1*/GPIO50

REQ3*/GPIO54

REQ2*/GPIO52

GNT2*/GPIO53

GNT1*/GPIO51

GNT3*/GPIO55

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

PME*

CLKOUT_PCI0

PLTRST*

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI3 CLKOUT_PCI4

LVDSA_DATA2*

LVDSA_DATA1*

LVDSA_DATA0*

LVDSA_DATA3*

LVDSA_DATA0

LVDSA_DATA2

LVDSA_DATA1

LVDSA_CLK*

LVDSA_DATA3

LVDSA_CLK

LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*

LVDSB_DATA1

LVDSB_DATA0

LVDSB_DATA2 LVDSB_DATA3

LVDSB_CLK* LVDSB_CLK

L_BKLTEN

L_BKLTCTL

LVD_VREFL

LVD_VREFH

LVD_VBG

LVD_IBG

L_VDD_EN

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_CTRL_CLK

(5 OF 10)

USB

PCI

LVDS

OUT OUT OUT

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT OUT OUT

OUT OUT

BI BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Camera

USB HUB 2

USB HUB 1

Unused

88 94

COUGAR-POINT

FCBGA

OMIT

MOBILE

U1800

H49 H43 J48 K42 H40

D47 E42 F46

P45 J47

T45 P39 T40 K47

M45

AF37 AF36

AE48 AE47

AK40

AK39

AN47

AN48

AM49

AM47

AK49

AK47

AJ47

AJ48

AF39

AF40

AH43

AH45

AH49

AH47

AF47

AF49

AF43

AF45

A14 K20 B17 C16 L16 A16 D14 C14

K40 K38 H38 G38

G42 G40 C42 D44

C6

K10

C46 C44 E40

C24 A24

C30 A30

L32 K32

G32 E32

C32 A32

C25 B25

C26 A26

K28 H28

E28 D28

C28 A28

C29 B29

N28 M28

L30 K30

G30 E30

B33

C33

88 94

8

94

88 94

8

94

88 94

8

88 94

6 8

88 94

8

2.37K

1%

1/20W

MF

201

PLACE_NEAR=U1800.AF37:2.54mm

R2050

1

2

5%

MF

NOSTUFF

201

10K

1/20W

R2054

1

2

6 8

8

18 88

8

18 88

84

MF

1/20W

5%

201

10K

R2011

1 2

10K

5%

201

MF

1/20W

R2012

1 2

201

1/20W

MF

10K

5%

R2013

1 2

1/20W

5%

10K

MF

201

R2016

1 2

201

5% MF

10K

1/20W

R2017

1 2

1/20W

MF5%

10K

201

R2018

1 2

1/20W

201

5% MF

10K

R2030

1 2

MF

10K

201

1/20W

5%

R2014

1 2

NOSTUFF

1/20W

MF

201

5%

10K

R2053

1

2

5%

NOSTUFF

10K

1/20W

MF

201

R2052

1

2

201

MF

1/20W

5%

100K

R2055

1

2

1/20W

10K

201

MF

5%

R2061

1

2

10K

MF

201

1/20W

5%

R2062

1

2

MF

1/20W

10K

5%

201

R2064

1

2

MF

201

5%

10K

1/20W

R2065

1

2

5% 1/20W MF 201

10K

R2067

1

2

10K

1/20W

201

MF

5%

R2069

1

2

10K

5%

201

1/20W MF

R2068

1

2

5% MF-LF

402

1/16W

100K

R2015

1

2

5%

1/20W

201

10K

MF

R2031

1 2

24 94

1%

22.6

PLACE_NEAR=U1800.B33:2.54mm

MF

1/20W

201

R2070

1

2

201

5% MF

1/20W

10K

R2010

1 2

25 29 39

25

25 95

25

201

1/20W

5%

10K

MF

R2060

1

2

SYNC_DATE=10/20/2010

PCH PCI/FLASHCACHE/USB

SYNC_MASTER=K91_MLB

PP3V3_S0_PCH

T29_MCU_INT_L

PCI_INTE_L AUD_IP_PERIPHERAL_DET

NC_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT

NC_PCI_PME_L

PCH_USB_RBIAS

USB_HUB_SOFT_RESET_L

SDCONN_STATE_CHANGE

PCH_GPIO43_OC4_L

PCH_GPIO52

JTAG_GMUX_TMS

PCI_INTC_L

PCI_INTA_L

NC_USB_11P

NC_USB_12N NC_USB_12P

NC_USB_13N NC_USB_13P

NC_USB_11N

NC_USB_10N

USB_CAMERA_P

USB_CAMERA_N

USB_HUB2_UP_P

USB_HUB2_UP_N

NC_USB_7P

NC_USB_7N

NC_USB_6P

NC_USB_6N

NC_USB_5P

NC_USB_5N

NC_USB_4P

NC_USB_4N

NC_USB_3P

NC_USB_2P

NC_USB_1P

NC_USB_3N

NC_USB_2N

NC_USB_1N

USB_HUB1_UP_N USB_HUB1_UP_P

LVDS_IG_A_DATA_P<1>

LVDS_IG_DDC_CLK

NC_LVDS_IG_CTRL_CLK

LVDS_IG_PANEL_PWR

TP_LVDS_IG_BKL_PWM

PCH_LVDS_IBG

LVDS_IG_BKL_ON

LVDS_IG_PANEL_PWR

PCH_PCI_GNT1_L

NC_LVDS_IG_CTRL_DATA

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_DDC_DATA

LVDS_IG_BKL_ON

TP_LVDS_IG_B_CLKP

NC_LVDS_IG_A_DATAN<3>

PCH_PCI_GNT3_L PCH_PCI_GNT2_L

LVDS_IG_B_DATA_N<2>

LVDS_IG_A_CLK_P

NC_LVDS_IG_B_DATAN<3>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

NC_PCH_LVDS_VBG

LPC_CLK33M_LPCPLUS_R

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<0>

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_DATA_N<2>

PCH_PCI_GNT3_L

PCH_PCI_GNT2_L

AP_PWR_EN

PCH_GPIO10_OC6_L

SDCONN_STATE_RST_L

PP3V3_S3

PP3V3_SUS

PCH_GPIO14_OC7_L

LVDS_IG_A_DATA_N<0>

LPC_CLK33M_GMUX_R

LPC_CLK33M_SMC_R

PLT_RESET_L

AUD_I2C_INT_L

NC_LVDS_IG_B_DATAP<3>

TP_LVDS_IG_B_CLKN

ENET_PWR_EN

NC_USB_10P

PCH_PCI_GNT1_L

PCI_REQ3_L

PCI_INTD_L

PCI_INTB_L

20 OF 132 18 OF 105

16 17 19 20 22

102

85

62

6

94

23 24

23

88

31

6

8

18 88

8

18 88

18

6

18

6

18

31 73

23

6 7 8

24 25 29 30 31 32 48 49 50 54 55 73

88

104

7

16 17 19 20 22 46 71 72 73

23

25

62

23

18

OUT

BI

IN

CPU

NCTF

MISC

(6 OF 10)

GPIO

RSVD

TP38

SATA3GP/GPIO37

TACH5/GPIO69

TP18

STP_PCI*/GPIO34

GPIO15

SATA4GP/GPIO16

CLKOUT_PCIE7P

A20GATE

TACH3/GPIO7

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

TACH0/GPIO17

GPIO24/MEM_LED

SCLOCK/GPIO22

GPIO27

GPIO28

GPIO35

SATA2GP/GPIO36

SLOAD/GPIO38

SDATAOUT0/GPIO39

PCIECLKRQ6*/GPIO45

PCIECLKRQ7*/GPIO46

SATA5GP/GPIO49

SDATAOUT1/GPIO48

TACH4/GPIO68

GPIO57

TACH6/GPIO70

TACH7/GPIO71

CLKOUT_PCIE6N

CLKOUT_PCIE7N

CLKOUT_PCIE6P

BMBUSY*/GPIO0

TACH2/GPIO6

TACH1/GPIO1

PECI

RCIN*

THRMTRIP*

PROCPWRGD

TP1

TP2

TP3

TP4

TP6

TP5

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP19

TP20

TP21

TP22

TP24

TP25

TP26

TP27

TP29

TP28

TP30

TP31

TP32

TP33

TP34

TP35

TP36

NC_1

INIT3_3V*

TP40

TP39

TP37

VSS_NCTF

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

TS_VSS1 TS_VSS2 TS_VSS3

VSSADAC

TS_VSS4

IN

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC

IN

OUT

IN

BI

IN

OUT

NC

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(PUs necessary?)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

This has internal pull up and should not pulled low.

(IPU)

(NC-ed per Intel chklist)

(PU necessary?)

PD on audio page

ALL RSVD TPs NC-ed per INTEL approval

10 23 92

23 29

6

47

NOSTUFF

1/20W

201

5%

43

MF

R2170

1 2

5%

0

1/20W

201

MF

R2140

1 2

19 23

FCBGA

MOBILE

COUGAR-POINT

OMIT

U1800

P4

T7 V40

V42

V38 V37

G2

E8

E16

P8

K4

D6

C10

T14

C4

P37

T13

K12

AU16

AY11

P5

V8

M5

U2

V3

T5

M3

V13

N2

K1

D40

A42

H36

E38

C40

B41

C41

A40

AY10

BG26

C18

N30

H3

AH12

AM4

AM5

Y13

K24

L24

AB46

BJ26

AB45

B21

M20

BG46

BE28

BC30

BE32

BJ32

BC28

BH25

BE30

BF32

BG32

AV26

BB26

AU28

AY30

AU26

AY26

AV28

BJ16

AW30

BG16

AH38

AH37

AK43

AK45

AH8 AK11 AH10 AK10

A4

A44

BE1 BE49

BF1 BF49

BG2 BG48

BH3 BH47

BJ4 BJ44

A45

BJ45 BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

A46

F1

F49

A5 A6

B3 B47 BD1

BD49

U47

19 88

201

1/20W

MF

NOSTUFF

1K

5%

R2130

1

2

1/20W

201

10K

MF

5%

R2185

1

2

8

19 39

23 62

19 41

8

19 23 33 88

8

19 33 88

6

19 47 56

10 92

MF

390

1/20W

5%

201

R2156

1 2

MF

1/20W

201

10K

5%

R2160

1

2

MF

201

1/20W

5%

10K

R2184

1

2

MF

201

1/20W

10K

5%

R2186

1

2

5%

10K

1/20W

MF

201

R2172

1

2

MF

201

10K

5%

1/20W

R2173

1

2

10K

MF

201

5%

1/20W

R2174

1

2

5%

10K

201

1/20W

MF

R2175

1

2

1/20W

10K

5%

MF

201

NOSTUFF

R2115

1

2

MF

10K

201

5%

1/20W

R2114

1

2

201

5%

10K

1/20W

MF

R2192

1

2

201

MF

1/20W

5%

100K

R2193

1

2

MF

1/20W

201

5%

20K

R2111

1

2

10K

5%

1/20W

201

MF

R2112

1

2

MF

1/20W

201

5%

10K

R2113

1

2

100K

1/20W

5%

201

MF

R2190

1

2

5%

201

1/20W

MF

10K

R2199

1

2

1/20W

MF

201

10K

5%

R2198

1

2

201

MF

1/20W

5%

10K

R2195

1

2

5%

10K

1/20W

MF

201

R2196

1

2

201

MF

5%

10K

1/20W

NOSTUFF

R2197

1

2

5%

10K

201

1/20W

MF

R2155

1

2

10K

201

1/20W

MF

5%

R2150

1

2

16 19 45

19 32 36

1/20W

5%

10K

201

MF

NOSTUFF

R2116

1

2

1/20W

10K

5%

201

MF

R2194

1

2

10K

5%

1/20W

MF

201

R2191

1

2

MF

1/20W

NOSTUFF

201

5%

10K

R2117

1

2

8

19 33 88

19 73

19 39

19 45 46

PCH MISC

SYNC_MASTER=K91_MLB

SYNC_DATE=10/20/2010

PP3V3_SUS

SPIROM_USE_MLB

ODD_PWR_EN_L

PCH_GPIO24

PCH_GPIO12

PM_THRMTRIP_L_R

SMC_RUNTIME_SCI_L PCH_GPIO49_SATA5GP

SMC_RUNTIME_SCI_L

PCH_GPIO15

AUD_IPHS_SWITCH_EN

JTAG_ISP_TDO

PCH_GPIO46

LPCPLUS_GPIO

SMC_SCI_L

GMUX_INT

FW_PLUG_DET_L

PCH_GPIO0

ODD_PWR_EN_L

PCH_GPIO24

PP3V3_S0_PCH

JTAG_ISP_TCK

GMUX_INT

ENET_LOW_PWR

PCH_GPIO68_TACH4

PP3V3_S0_PCH

T29_SW_RESET_L

PCH_A20GATE

JTAG_ISP_TCK

PCH_GPIO70_TACH6

PCH_GPIO68_TACH4

PP3V3_S5

SMC_SCI_L

PCH_GPIO0

PM_THRMTRIP_L

PCH_RCIN_L

PCH_PECI

JTAG_ISP_TDI

PCH_GPIO46

NC_PCIE_CLK100M_PE6N

PCH_INIT3V3_L

NC_PCIE_CLK100M_PE7P

NC_PCIE_CLK100M_PE7N

CPU_PECI

PCH_INIT3V3_L

PCH_PROCPWRGD

PP3V3_S0_PCH

CPU_PWRGD

NC_PCIE_CLK100M_PE6P

PCH_GPIO71_TACH7

PCH_GPIO36_SATA2GP ENET_LOW_PWR

PCH_GPIO12

PP3V3_S0_PCH

PCH_GPIO71_TACH7

PP3V3_T29

PP3V3_S0_PCH

WOL_EN

PCH_GPIO69_TACH5

PP3V3_SUS

PCH_GPIO15

PP3V3_T29

FW_PWR_EN

FW_PLUG_DET_L

JTAG_ISP_TDO

JTAG_ISP_TDI

SPIROM_USE_MLB

FW_PWR_EN

WOL_EN

PCH_GPIO36_SATA2GP

T29_SW_RESET_L

ISOLATE_CPU_MEM_L

PCH_GPIO69_TACH5

NC_GPIO35

21 OF 132 19 OF 105

7

16 17 18 19 20 22 46 71

72 73

6

19 47 56

19 41

19

46

19 45 46

23

19

19 23

19

16 17 18 19 20 22

102

8

19 23 33 88

19 88

19

16 17 18 19 20 22 102

19 35

19

6 7

17 20 22 23 24 25 29 46 48 56 71 72

73 83 86 91

100 102 104

16 19 45

19 23

8

19 33 88

19 23

6

19

6

10 45 92

19

16 17 18 19 20 22

102

6

19

19 23

19 32 36

19

16 17 18 19 20 22

102

19

7

16 19 25

33 34 35 88

16 17 18 19 20 22

102

19 73

19

7

16 17 18 19 20 22 46 71 72

73

19

7

16 19 25 33 34 35 88

19 39

8

19 39

8

19 33 88

19 23

19 35

19

VSSALVDS

VCCTX_LVDS

VCCDFTERM

VCCALVDS

VCCVRM_3_DMI

VCC3_3_7_HVCMOS

VCC3_3_5_PCI

VCCDFTERM

VCCSPI

VCCDFTERM

VCC3_3_6_HVCMOS

VCCIO_18_FDI

VCCIO_21_PCIE

VCCIO_20_PCIE

VCCIO_11_PLLPCIE

VCCIO_25_PCIE

VCCIO_24_PCIE

VCCCLKDMI

VCCCORE

VCCIO_27_DP

VCCIO_26_PCIE

VCCIO_19_PCIE

VCCIO_22_PCIE

VCCIO_10_PLLFDI

VCCIO_23_PCIE

VCCIO_17_FDI

VCCIO_28_DP

VCCDMI_0_FDI

VCCAPLLEXP

VCCCORE

VCCDMI_1_DMI

VCCCORE VCCCORE VCCCORE

VCCAFDIPLL

VCCCORE

VCCVRM_2_FDI

VCCADAC

VCCCORE

FDI CRT

DFT/SPI

DMI

HVCMOS

VCCIO

VCC CORE

LVDS

(7 OF 10)

VCCSUSHDA

VCCSUS3_3_3_USB VCCSUS3_3_4_USB

VCCSUS3_3_2_USB

VCCSUS3_3_1_USB

VCCIO_4_USB

VCCIO_2_USB VCCIO_3_USB

VCCIO_1_USB

VCCIO_0_USB

VCCASW_0_MISC

VCCASW_2_MISC VCCASW_1_MISC

VCCIO_8_SATA

VCCIO_6_SATA VCCIO_7_SATA

VCCAPLLSATA

VCCVRM_1_SATA

VCCIO_9_PLLSATA3

VCCIO_15_SATA3 VCCIO_16_SATA3

VCC3_3_0_SATA

VCCIO_5_PLLSATA

VCC3_3_2_GPIO VCC3_3_3_GPIO VCC3_3_1_GPIO

VCCSUS3_3_7_GPIO VCCSUS3_3_8_GPIO

VCCSUS3_3_5_GPIO VCCSUS3_3_6_GPIO

V5REF

VCCRTC

V_PROC_IO

DCPSUSBYP

VCCACLK

DCPRTC

VCCADPLLA VCCADPLLB

DCPSST

DCPSUS_2_CLK

DCPSUS_1_CLK

VCCDIFFCLKN_2

VCCDIFFCLKN_1

VCCDIFFCLKN_0

VCCDSW3_3

VCCIO_13_CLK

VCC3_3_4_CLK

VCCASW_4_CLK VCCASW_5_CLK VCCASW_6_CLK VCCASW_7_CLK VCCASW_8_CLK

VCCAPLLDMI2

VCCASW_20_CLK

VCCASW_10_CLK VCCASW_11_CLK VCCASW_12_CLK VCCASW_13_CLK VCCASW_14_CLK VCCASW_15_CLK VCCASW_16_CLK VCCASW_17_CLK VCCASW_18_CLK VCCASW_19_CLK

VCCASW_9_CLK

VCCVRM_0_CLK

VCCASW_22_CLK

VCCASW_21_CLK

VCCSSC

VCCSUS3_3_9_USB

VCCIO_14_PLLUSB

V5REF_SUS

VCCSUS3_3_0_SUS

DCPSUS_3_SUS

VCCASW_3_CLK

DCPSUS_0_CLK

VCCIO_12_PLLCLK

CPURTC

HDA

USB

MISC

SATA

PCI/GPIO/

LPC

CLK/MISC

(8 OF 10)

NC

NC NC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AL24 left as NC per DG

VCCAPLLDMI2 pin left as NC per DG

55mA Max, 5mA Idle

PCH output, for decoupling only

1.44 A Max, 474mA Idle

VCCAFDIPLL pin left as NC per DG

VCCAPLLSATA pin left as NC per DG

NC-ed per DG

VCCACLK pin left as NC per DG

10 mA Max, 1mA Idle

NC-ed per DG

OMIT

COUGAR-POINT

FCBGA

MOBILE

U1800

BH29

V33 V34

U48

BG6

AK36

BJ22

AB36

AA23 AC23

AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26

AG16 AG17 AJ16 AJ17

AU20

AT20

AP17

AN19

AN16 AN17

AN21 AN26 AN27 AP21 AP23 AP24 AP26 AT24

AN33 AN34

V1

AM37 AM38 AP36 AP37

AP16

AT16

AK37

FCBGA

COUGAR-POINT

OMIT

MOBILE

U1800

N16

V16

AL24

T17 V19

AN23

V12

P34

M26

BJ8

AJ2

T34

AA16 W16

T38

AD49

BD47 BF47

BH23

AK1

T19

AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26

V21

W29 W31 W33

T21

AA19 AA21 AA24 AA26 AA27 AA29 AA31

AF33 AF34 AG34

T16

N26

AL29

AF17

T26

AH13 AH14

P26 P28 T27 T29

AF13

AC16 AC17 AD17

AF14

A22

AG33

AN24

T23 T24 V23 V24

N20 N22 P20 P22

P24

P32

Y49

AF11

0.1UF

CERM

20% 10V

402

PLACE_NEAR=U1800.A22:2.54mm

C2232

1

2

CERM

10%

1UF

6.3V

402

PLACE_NEAR=U1800.A22:2.54mm

C2231

1

2

CERM

0.1UF

PLACE_NEAR=U1800.V16:2.54mm

20% 10V

402

C2222

1

2

PLACE_NEAR=U1800.N16:2.54mm

0.1UF

CERM

20%

402

10V

C2210

1

2

CERM

PLACE_NEAR=U1800.A22:2.54mm

402

20% 10V

0.1UF

C2233

1

2

PCH POWER

PP1V5_S0

PP3V3_SUS

PP5V_SUS_PCH_V5REFSUS

PPVOUT_G3_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2 mm

PP3V3_SUS

PP3V3_S0_PCH

TP_1V05_S0_PCH_VCCAPLLEXP

PP1V05_S0_PCH_VCCCLKDMI_F

PPVCCIO_S0_PCH

PP3V3_S0_PCH

PPVCCIO_S0_PCH

PP1V8_S0_PCH_VCCTX_LVDS_F

PPVCCIO_S0_PCH

PP1V8_S0

PP1V8_S0_PCH

PP3V3_S0_PCH_VCCA_DAC_F

PP3V3_S5

PP3V3_S0_PCH

TP_PPVOUT_PCH_DCPSUSBYP

PPVCCIO_S0_PCH

PP3V3_S0_PCH

PP1V8_S0

PP5V_S0_PCH_V5REF

PPVCCIO_S0_PCH

PPVRTC_G3H

PP3V3_S5

PPVCCIO_S0_PCH

PP1V8_S0

PPVCCIO_S0_PCH

PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLA_F

PP3V3_SUS

PPVCCIO_S0_PCH

PP3V3_S0_PCH_VCC3_3_CLK_F

PPVCCIO_S0_PCH

22 OF 132 20 OF 105

7

16 22 25 32 41 57 71

7

16 17 18 19 20 22 46 71 72 73

22

7

16 17 18 19 20 22 46 71 72 73

16 17 18 19 20 22

102

22

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

16 17 18 19 20 22

102

16 17 20 22

102 104

16 17 20 22

102 104

22

16 17 20 22

102 104

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

17 22

102

22

6 7

17 19 20 22 23 24 25 29

46 48 56 71 72 73 83 86 91

100 102 104

16 17 18 19 20 22

102

16 17 18 19 20 22

102

16 17 20 22

102 104

16 17 18 19 20 22

102

6 7

14 20 25 71 72 88

102

22

16 17 20 22

102 104

7

16 17 25

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

16 17 20 22

102 104

6 7

14 20 25 71 72 88

102

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

22

7

16 17 18 19 20 22 46 71 72 73

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

22

16 17 20 22

102 104

VSS

(9 OF 10)

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

(10 OF 10)

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OMIT

FCBGA

MOBILE

COUGAR-POINT

U1800

AJ3 N24

AB14

AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2

AB39

AN29 AN3 AN31 AP12 AP13 AP19 AP28 AP30 AP32 AP38

AB4

AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22

AB43

AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24

AB5

AU30 AV11 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8

AB7

AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40

AC19

AW48 AY12 AY22 AY28 AY4 AY42 AY46 AY8 B11 B15

AC2

B19 B23 B27 B31

AC21 AC24

BG29

AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD14 AD16 AD19

H5

AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD4

AA17

AD40 AD42 AD43 AD45 AD46 AD47

AD8 AE2 AE3

AF10

AA2

AF12 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF4

AA3

AF42 AF46

AF5 AF7 AF8

AG19

AG2 AG31 AG48 AH11

AA33

AH3 AH36 AH39 AH40 AH42 AH46

AH7 AJ19 AJ21 AJ24

AA34

AJ33 AJ34 AK12

AK3 AK38

AK4 AK42

AK46 AK8 AL16

AB11

AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34

OMIT

FCBGA

COUGAR-POINT

MOBILE

U1800

B35

B39 B43

B7 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB4 BB46 BC14 BC18

BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48

BD3 BD46

BD5 BE10 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BF30 BF38 BF40

BF8 BG17 BG21 BG22 BG24 BG33 BG41 BG44

BG8 BH11 BH15 BH17 BH19 BH27 BH31 BH33 BH35 BH39 BH43

BH7

C22

D12

D16

D18

D22

D24

D26

D3 D30 D32 D34 D38 D42

D8 E18 E26

F3 F45 G14 G18 G20 G26 G28 G36

G48 H10 H12 H16 H18 H22 H24 H26 H30 H32 H34 H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 M14 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 N47 P11 P16 P18 P30 P40 P43 P47 P7 R2 R48 T12 T31 T33 T36 T37 T4 T46 T47 T8 V11 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W34 W48 Y12 Y38 Y4 Y42 Y46 Y8 V17 AP3 AP1 BE16 BC16 BG28 BJ28

SYNC_MASTER=K92_YUN

SYNC_DATE=05/20/2010

PCH GROUNDS

23 OF 132 21 OF 105

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH VCCCORE BYPASS

(PCH Reference for 5V Tolerance on USB)

PCH VCCSUSHDA BYPASS

PCH VCCIO BYPASS

1 mA

<1 MA

PCH VCCIO BYPASS (PCH USB 1.05V PWR)

69 mA

1 mA S0-S5

(PCH 1.05V CORE PWR)

(PCH SUSPEND USB 3.3V PWR)

PCH VCCSUS3_3 BYPASS

NEED PWR CONSTRAINT

(PCH Reference for 5V Tolerance on PCI)

68 mA

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PCH VCCADPLLB Filter (PCH DPLLB PWR)

(PCH PCI 3.3V PWR)

PCH V5REF Filter & Follower

PCH VCC3_3 BYPASS

PCH V5REF_SUS Filter & Follower

<1 MA S0-S5

NEED PWR CONSTRAINT

PLACE_NEAR=U1800.P34:2.54mm

X5R

10% 10V

1UF

402

C2439

1

2

MF-LF

1/16W

402

5%

100

R2405

2

1

PLACE_NEAR=U1800.M26:2.54mm

20% 10V

402

CERM

0.1UF

C2438

1

2

BAT54DW-X-G

SOT-363

D2400

1

6

5

402

1/16W

5%

10

MF-LF

R2404

2

1

SOT-363

BAT54DW-X-G

D2400

4

3

2

PLACE_NEAR=U1800.AJ2:2.54mm

10% 16V

0.1UF

X5R 402

C2423

1

2

10V

402

CERM

20%

0.1UF

PLACE_NEAR=U1800.AJ16:2.54mm

C2440

1

2

PLACE_NEAR=U1800.P32:2.54mm

402

CERM

20%

0.1UF

10V

C2441

1

2

6.3V

1UF

10% CERM

402

PLACE_NEAR=U1800.AT20:2.54mm

C2419

1

2

PLACE_NEAR=U1800.BH29:2.54mm

10%

402

X5R

16V

0.1UF

C2421

1

2

X5R

16V

402

10%

0.1UF

PLACE_NEAR=U1800.V24:2.54mm

C2413

1

2

402

0.1UF

16V X5R

10%

PLACE_NEAR=U1800.BJ8:2.54mm

C2417

1

2

6.3V

402

20%

4.7UF

X5R

PLACE_NEAR=U1800.BJ8:2.54mm

C2416

1

2

PLACE_NEAR=U1800.P24:2.54mm

10%

0.1UF

402

16V X5R

C2484

1

2

25V

10% X5R

402

0.1UF

PLACE_NEAR=U1800.AA16:2.54mm

C2485

1

2

PLACE_NEAR=U1800.AN27:2.54mm

6.3V

402

1UF

10% CERM

C2463

1

2

10%

6.3V CERM 402

1UF

PLACE_NEAR=U1800.AG33:2.54mm

C2475

1

2

PLACE_NEAR=U1800.AF34:2.54mm

6.3V

402

10%

1UF

CERM

C2434

1

2

PLACE_NEAR=U1800.AF17:2.54mm

CERM

6.3V

402

1UF

10%

C2469

1

2

PLACE_NEAR=U1800.AN27:2.54mm

CERM

6.3V

402

10%

1UF

C2414

1

2

PLACE_NEAR=U1800.AN27:2.54mm

X5R-CERM

16V

10%

0805

10UF

C2401

1

2

402

10%

PLACE_NEAR=U1800.AC17:2.54mm

CERM

6.3V

1UF

C2452

1

2

PLACE_NEAR=U1800.T16:2.54mm

10V

CERM

20%

402

0.1UF

C2499

1

2

10%

6.3V 402

1UF

CERM

PLACE_NEAR=U1800.V1:2.54mm

C2442

1

2

402

X5R

10%

0.1UF

25V

PLACE_NEAR=U1800.T34:2.54mm

C2486

1

2

PLACE_NEAR=U1800.AH13:2.54mm

10%

6.3V 402

CERM

1UF

C2444

1

2

PLACE_NEAR=U1800.P28:2.54mm

402

CERM

10%

1UF

6.3V

C2446

1

2

0.1UF

10% X5R

16V 402

PLACE_NEAR=U1800.V33:2.54mm

C2424

1

2

PLACE_NEAR=U1800.AG26:2.54mm

20%

10UF

CERM

805

6.3V

CRITICAL

C2460

1

2

PLACE_NEAR=U1800.AG24:2.54mm

6.3V CERM

10%

1UF

402

C2482

1

2

6.3V

1UF

CERM

10%

PLACE_NEAR=U1800.AD21:2.54mm

402

C2481

1

2

PLACE_NEAR=U1800.AJ27:2.54mm

6.3V CERM 402

1UF

10%

C2483

1

2

PLACE_NEAR=U1800.AN27:2.54mm

6.3V CERM

1UF

402

10%

C2407

1

2

PLACE_NEAR=U1800.AN27:2.54mm

6.3V

402

10% CERM

1UF

C2429

1

2

PLACE_NEAR=U1800.AC27:2.54mm

22UF

805

CERM

20%

6.3V

C2420

1

2

402

CERM

1UF

10%

6.3V

PLACE_NEAR=U1800.AC27:2.54mm

C2496

1

2

10%

6.3V

402

1UF

CERM

PLACE_NEAR=U1800.AC27:2.54mm

C2456

1

2

402

10%

6.3V CERM

1UF

PLACE_NEAR=U1800.AC27:2.54mm

C2426

1

2

MF-LF

1

5%

1/16W

402

R2415

1 2

402

PLACE_NEAR=U1800.AB36:2.54mm

10% 16V

1UF

X5R

C2411

1

2

0.1UF

X5R

10% 16V

402

PLACE_NEAR=U1800.BJ8:2.54mm

C2430

1

2

CERM

805

6.3V

20%

22UF

PLACE_NEAR=U1800.AC27:2.54mm

C2428

1

2

10%

CERM

402

16V

PLACE_NEAR=U1800.AM37:2.54mm

0.01UF

C2406

1

2

CRITICAL

6.3V

20%

805

CERM

PLACE_NEAR=U1800.AM37:2.54mm

22UF

C2400

1

2

PLACE_NEAR=U1800.AM37:2.54mm

16V

10%

402

CERM

0.01UF

C2408

1

2

CRITICAL

0805

0.1UH

L2407

1 2

201

MF

1/20W

5%

0

R2450

1 2

PLACE_NEAR=U1800.U48:2.54mm

CERM

402

10%

0.01UF

16V

C2455

1

2

10% X5R

16V

0.1UF

PLACE_NEAR=U1800.U48:2.54mm

402

C2451

1

2

CRITICAL

10UF

CERM

PLACE_NEAR=U1800.U48:2.54mm

6.3V 805

20%

C2450

1

2

5%

1

402

1/16W MF-LF

R2451

1 2

CRITICAL

10UF

X5R 603

20%

6.3V

PLACE_NEAR=U1800.T38:2.54mm

C2453

1

2

1UF

402

10V

10% X5R

PLACE_NEAR=U1800.T38:2.54mm

C2454

1

2

CRITICAL

0603

10UH-0.12A-0.36OHM

L2451

1 2

10%

6.3V 402

CERM

1UF

PLACE_NEAR=U1800.P22:2.54mm

C2476

1

2

CRITICAL

20%

2.5V

POLY-TANT

CASE-B2-SM1

PLACE_NEAR=U1800.BD47:2.54MM

220UF

C2491

1

2

10% CERM

402

6.3V

1UF

NO STUFF

PLACE_NEAR=U1800.BD47:2.54MM

C2492

1

2

PLACE_NEAR=U1800.BF47:2.54MM

10%

6.3V

1UF

CERM

NO STUFF

402

C2494

1

2

CRITICAL

PLACE_NEAR=U1800.BF47:2.54MM

220UF

POLY-TANT

2.5V

20%

CASE-B2-SM1

C2493

1

2

CRITICAL

0603

10UH-0.12A-0.36OHM

L2490

1 2

CRITICAL

10UH-0.12A-0.36OHM

0603

L2491

1 2

MF-LF

402

1/16W

0

5%

R2490

1 2

402

1/16W MF-LF

5%

0

R2491

1 2

CRITICAL

10UH-0.45A

1210-HF

L2406

1 2

SYNC_DATE=08/06/2010

PCH DECOUPLING

SYNC_MASTER=K91_YUN

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F

PP5V_SUS

MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCCLKDMI_R

PPVCCIO_S0_PCH

PP1V05_S0_PCH_VCCADPLLA_R

MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPVCCIO_S0_PCH

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLB_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0_PCH_VCCTX_LVDS_F

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.8V

PP1V8_S0_PCH

PP3V3_S0_PCH_VCC3_3_CLK_R MIN_NECK_WIDTH=0.075 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_F MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM

PPVCCIO_S0_PCH

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

PP3V3_S0_PCH_VCCA_DAC_F

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_SUS_PCH_V5REFSUS

PPVCCIO_S0_PCH

PP5V_S0_PCH_V5REF

PP3V3_SUS

PPVCCIO_S0_PCH

PP5V_SUS_PCH_V5REFSUS

PPVCCIO_S0_PCH

PP3V3_S0_PCH

PPVCCIO_S0_PCH

PP3V3_S0_PCH

PPVCCIO_S0_PCH

PP3V3_S5

PP1V8_S0_PCH

PP3V3_S0_PCH

PP5V_S0

PP3V3_S5

PP3V3_S0_PCH

PP1V05_S0_PCH_VCCADPLLB_R

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2MM

PP1V5_S0

PP3V3_SUS

PPVCCIO_S0_PCH

24 OF 132 22 OF 105

20

7

72

16 17 20 22 102 104

20

16 17 20 22

102 104

20

17 20 22 102

20

16 17 20 22

102 104

20 22

20

20 22

16 17 20 22

102 104

20 22

7

16 17 18 19 20 22 46 71 72

73

7

16 17 18 19 20 22 46 71 72

73

16 17 20 22

102 104

20 22

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

16 17 18 19 20 22

102

16 17 20 22

102 104

16 17 18 19 20 22

102

16 17 20 22

102 104

16 17 20 22

102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

17 20 22

102

16 17 18 19 20 22

102

16 17 18 19 20 22

102

16 17 18 19 20 22

102

6 7 8

41 47 52 54 65 68 69 70 73 87

104

105

6 7

17 19 20 22 23 24 25 29 46 48

56 71 72 73 83 86 91

100 102 104

16 17 18 19

20 22

102

16 17 18 19 20 22

102

7

16 20 25 32 41 57 71

7

16 17 18 19 20 22 46 71 72

73

16 17 20 22

102 104

IN

IN IN

IN

IN IN IN IN

IN IN IN

OUT

IN

OUT OUT

NC

IN

OUT

IN

BI IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT OUT

IN IN

NC

BI

IN

IN IN

BI IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OBSDATA_D3

OBSDATA_C3

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

PCH MINI XDP

OBSDATA_C0

PROCESSOR MINI XDP

517S0774

HOOK3

OBSFN_A1

OBSDATA_A1

TDI

TCK0

OBSDATA_D2

DBR#/HOOK7

OBSFN_B0 OBSFN_D0

ITPCLK#/HOOK5

TMS XDP_PRESENT#

OBSFN_B1

SCL

RESET#/HOOK6

OBSDATA_A2

OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

OBSDATA_D0

VCC_OBS_AB

OBSDATA_D1

OBSDATA_A0

OBSDATA_B2

OBSDATA_A1

OBSFN_A1

SCL

OBSDATA_B0

TDO

OBSFN_C1

VCC_OBS_CD

TCK1

TDO

PLACE TDO TERM NEAR

TERM NEAR PCH

HOOK2

OBSFN_D0

OBSDATA_C3

TDI

OBSDATA_B1

SDA

TRSTn

OBSFN_C0

OBSDATA_C2

OBSDATA_C1

OBSFN_C1

OBSDATA_C0

517S0774

TMS

OBSFN_A0

OBSDATA_D0

OBSFN_A0

OBSDATA_B3

DESIGN NOTE:

PLACEMENT NOTE:

SDA

HOOK1

OBSDATA_A3

OBSFN_D1

OBSFN_C0

SNB XDP CONN

TERM NEAR CPU

PLACE TCK/TDI/TMS/TRST*

PLACE TDO TERM NEAR

PLACEMENT NOTE:

ODT AVAILABLE ON JTAG

PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST*

TCK1

OBSFN_B1

OBSFN_B0

OBSDATA_A3

OBSDATA_A2

OBSDATA_A0

PCH XDP CONN

OBSDATA_D1

XDP_PRESENT#

DBR#/HOOK7

VCC_OBS_CD RESET#/HOOK6

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

ITPCLK/HOOK4

OBSFN_D1

TRSTn

OBSDATA_C2

OBSDATA_C1

TCK0

OBSDATA_B0

HOOK3

PWRGD/HOOK0

HOOK2

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_D2

VCC_OBS_AB

HOOK1

PWRGD/HOOK0

PLACEMENT NOTE:

1K series R on PCH Support P. 28

9

92

10 25

10 92

9

10 92

9

PLACE_NEAR=U1000.B57:2.54mm

MF

1K

201

5%

1/20W

XDP

R2501

1 2

9

23 92

16 39

16 31

9

92

19 62

XDP

201

1/20W

MF

5%

0

PLACE_NEAR=U1800.V10:2.54mm

R2576

1 2

1/20W

201

MF

XDP

PLACE_NEAR=U1800.M1:2.54mm

0

5%

R2577

1 2

19

16 41

PLACE_NEAR=U1800.U2:2.54mm

201

5%

0

MF

1/20W

XDP

R2579

1 2

8

19 33 88

19

9

92

25

16 23

9

92

PLACE_NEAR=U1800.A14:2.54mm

1/20W

5%

MF

201

0

XDP

R2580

1 2

18

16 23

9

92

18 24

CRITICAL

F-ST-SM-HF

XDP_CONN

DF40C-60DS-0.4V

J2550

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40 41 42 43 44 45 46 47 48 49

5

50 51 52 53 54 55 56 57 58 59

6

60

7 8 9

PLACE_NEAR=U1800.J3:2.54mm

MF

201

5%

51

XDP

1/20W

R2556

1

2

6

16 23 26 28 30 32 41 48 62 89 95

6

16 23 26 28 30 32 41 48 62 89 95

10 23 25 92

0.1uF

16V

402

X5R

10%

XDP

C2580

1

2

16V

XDP

402

10%

X5R

0.1uF

C2581

1

2

19

5%

PLACE_NEAR=U4900.P17:2.54mm

0

MF

201

1/20W

XDP

R2502

1 2

17 23 45

PLACE_NEAR=U4900.P17:2.54mm

0

5%

MF

201

XDP

1/20W

R2585

1 2

17 23 45

330

201

1/20W

XDP

5%

MF

R2504

1 2

17 91

18

1/20W

PLACE_NEAR=J2550.39:2.54mm

5%

MF

201

1K

XDP

R2584

1 2

45 73 88 91

5%

0

MF

1/20W

201

XDP

PLACE_NEAR=U1800.A16:2.54mm

R2581

1 2

18

10 23 92

10 23 25 92

PLACE_NEAR=U1800.K12:2.54mm

1/20W

0

5%

XDP

MF

201

R2582

1 2

19

XDP

201

1/20W

MF

PLACE_NEAR=U1800.P8:2.54mm

5%

0

R2578

1 2

19 29

XDP

5%

MF

201

0

1/20W

PLACE_NEAR=U1800.K20:2.54mm

R2586

1 2

5%

0

XDP

MF

1/20W

PLACE_NEAR=U1800.C16:2.54mm

201

R2587

1 2

18

9

92

10 23 92

16 92

1/20W

201

MF

5%

0

PLACE_NEAR=R1841.1:2.54mm

XDP

R2515

1 2

PLACE_NEAR=R1840.1:2.54mm

XDP

0

201

5%

1/20W

MF

R2516

1 2

PLACE_NEAR=U1000.G3:2.54mm

XDP

1K

201

1/20W

MF

5%

R2505

1 2

16 85

PLACE_NEAR=J2550.52:2.54mm

201

5%

1/20W

MF

XDP

51

R2550

1

2

10 23 92

PLACE_NEAR=U1800.K5:2.54mm

201

51

5%

1/20W

MF

XDP

R2551

1

2

201

MF

1/20W

5%

51

XDP

PLACE_NEAR=U1800.H7:2.54mm

R2552

1

2

1/20W

XDP_CPU_BPM

5%

0

MF

201

R2560

1 2

5%

0

1/20W

201

MF

XDP_CPU_BPM

R2561

1 2

XDP_CPU_BPM

1/20W

5%

MF

201

0

R2562

1 2

XDP_CPU_BPM

201

5%

1/20W

0

MF

R2563

1 2

201

XDP_CPU_CFG

0

1/20W

MF

5%

R2564

1 2

10 23 92

XDP_CPU_CFG

0

1/20W

MF

201

5%

R2566

1 2

XDP_CPU_CFG

201

1/20W

5%

MF

0

R2567

1 2

XDP_CPU_CFG

0

201

MF

1/20W

5%

R2565

1 2

402

MF-LF

1/16W

5%

NOSTUFF

1K

R2540

1

2

9

23 92

0.1uF

16V

XDP

X5R 402

10%

C2501

1

2

9

92

10% 16V X5R

0.1uF

XDP

402

C2500

1

2

10 92

9

92

9

92

9

92

9

92

6

16 23 26 28 30 32 41 48 62 89

95

6

16 23 26 28 30 32 41 48 62 89 95

10 23 92

1K

1/20W

201

5%

MF

XDP

PLACE_NEAR=U1000.C60:2.54mm

R2500

1 2

9

92

10 19 92

9

92

F-ST-SM-HF

CRITICAL XDP_CONN

DF40C-60DS-0.4V

J2500

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40 41 42 43 44 45 46 47 48 49

5

50 51 52 53 54 55 56 57 58 59

6

60

7 8 9

51

5%

201

1/20W

MF

PLACE_NEAR=J2500.52:2.54mm

XDP

R2510

1

2

PLACE_NEAR=U1000.K61:2.54mm

5%

51

MF

1/20W

201

XDP

R2511

1

2

51

5%

MF

1/20W

201

PLACE_NEAR=U1000.H59:2.54mm

XDP

R2512

1

2

PLACE_NEAR=U1000.H63:2.54mm

51

5%

XDP

MF

1/20W

201

R2513

1

2

PLACE_NEAR=U1000.J58:2.54mm

XDP

5%

51

MF

1/20W

201

R2514

1

2

10 92

SYNC_DATE=10/17/2010

CPU & PCH XDP

SYNC_MASTER=K91_MLB

PP3V3_S0

XDP_CPU_PWRGD

XDP_OBSDATA_B<3>

XDP_OBSDATA_B<2>

XDP_OBSDATA_B<1>

CPU_CFG<13> CPU_CFG<14>

XDP_VR_READY

XDP_CPU_PREQ_L XDP_CPU_PRDY_L

XDP_BPM_L<0>

CPU_CFG<10>

XDP_BPM_L<1>

XDP_CPU_TDI

XDP_CPU_TCK

XDP_PCH_TDI

XDP_PCH_TCK

XDP_CPU_TMS

XDP_CPU_TRST_L

TP_XDP_PCH_OBSFN_B<0>

PCH_GPIO10_OC6_L

XDP_PCH_S5_PWRGD

TP_XDP_PCH_OBSFN_B<1>

XDP_PCH_ENET_PWR_EN

CPU_CFG<11>

XDP_BPM_L<3>

XDP_CPU_PWRBTN_L

PP1V05_S0

CPU_CFG<8>

CPU_CFG<6> CPU_CFG<7>

XDP_CPURST_L

XDP_OBSDATA_B<0>

TP_XDPPCH_HOOK2

XDP_CPU_TMS

CPU_CFG<0>

PM_PCH_SYS_PWROK

TP_XDPPCH_HOOK3

XDP_CPU_CFG<0>

XDP_BPM_L<4>

CPU_PWRGD

CPU_CFG<15>

TP_XDP_PCH_OBSFN_A<0>

PCH_GPIO43_OC4_L XDP_PCH_SDCONN_DET_L

XDP_PCH_PWRBTN_L

PCH_GPIO14_OC7_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

JTAG_ISP_TCK

XDP_BPM_L<2>

XDP_PCH_TDI

CPU_CFG<5>

CPU_CFG<2>

CPU_CFG<9>

XDP_CPU_CLK100M_N

CPU_CFG<4>

PLT_RST_CPU_BUF_L

XDP_CPU_CLK100M_P

XDP_PCH_TDO

PP1V05_SUS

XDP_BPM_L<5>

PP1V05_S0

XDP_CPU_TDOCPU_CFG<17>

AP_CLKREQ_L

ITPXDP_CLK100M_N

XDP_PCH_USB_HUB_SOFT_RST_L

SDCONN_STATE_RST_L

USB_HUB_SOFT_RESET_L

SDCONN_STATE_CHANGE

XDP_DBRESET_L

PM_PWRBTN_L

ENET_PWR_EN

XDP_PCH_TMS

ITPXDP_CLK100M_P

CPU_CFG<0>

CPU_CFG<16>

CPU_CFG<1>

CPU_CFG<12>

ALL_SYS_PWRGD

XDP_BPM_L<6>

XDP_PCH_ISOLATE_CPU_MEM_L

SMBUS_PCH_DATA

TP_XDP_PCH_OBSFN_A<1>

XDP_PCH_GPIO46

XDP_PCH_SDCONN_STATE_RST_L

ISOLATE_CPU_MEM_L

FW_CLKREQ_L

TP_XDP_PCH_TRST_L

XDP_DBRESET_L

XDPPCH_PLTRST_L

TP_XDP_PCH_HOOK5

XDP_PCH_AUD_IPHS_SWITCH_EN

XDP_PCH_TCK

PCH_GPIO36_SATA2GP

XDP_PCH_TDO

XDP_CPU_TDI

PCH_GPIO46

PM_PWRBTN_L

XDP_BPM_L<7>

SMBUS_PCH_CLK

XDP_CPU_TCK

XDP_CPU_TDO XDP_CPU_TRST_L

XDP_PCH_TMS

AUD_IPHS_SWITCH_EN

TP_XDP_PCH_OBSFN_D<1>

TP_XDP_PCH_OBSFN_D<0>

XDP_AP_CLKREQ_L

DP_AUXCH_ISOL

SATARDRVR_EN

PCH_GPIO49_SATA5GP

TP_XDP_PCH_HOOK4

PP3V3_S5

XDP_FW_CLKREQ_L

PCH_GPIO0

CPU_CFG<3>

25 OF 132 23 OF 105

6 7

12 25 26 28 32 35 36 39 40 41 46 48

49 50 51 52 54 57 61 62 72 73 80 83 84

85 88 89 91

100 102

92

10 23 92

16 23

10 23 92

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

92

16 23

7

71

7 9

10 12 13

14 23 35 39

45 68 70 73

102 104 105

10 23 92

16 23

6 7

17 19 20 22 24 25 29 46 48 56 71 72

73 83 86 91

100 102 104

G

D

S

G

D

S

USBDN2_DP/PRT_DIS_P2

USBDN3_DM/PRT_DOS_M3 USBDN3_DP/PRT_DIS_P3

PRTPWR1

HS_IND/CFG_SEL1

SCL/SMBCLK/CFG_SEL0

USBDN4_DP/PRT_DIS_P4

USBDN4_DM/PRT_DIS_M4

SDA/SMBDATA/NON_REM1

OCS4*

OCS3*

RBIAS

VBUS_DET

PRTPWR3

PRTPWR2

USBDN2_DM/PRT_DIS_M2

USBDN1_DP/PRT_DIS_P1

USBDN1_DM/PRT_DIS_M1

SUSP_IND/LOCAL_PWR/NON_REM0

XTAL2

XTAL1/CLKIN

RESET*

USBUP_DP

USBUP_DM

OCS2*

PRTPWR4

OCS1*

VDD33PLL

VDD33CR

VDD33

VDD18

VDD18PLL

THRML_PAD

TEST

(SYM-VER1)

VDDA33

BI

IN

BI BI

USBDN2_DP/PRT_DIS_P2

USBDN3_DM/PRT_DOS_M3 USBDN3_DP/PRT_DIS_P3

PRTPWR1

HS_IND/CFG_SEL1

SCL/SMBCLK/CFG_SEL0

USBDN4_DP/PRT_DIS_P4

USBDN4_DM/PRT_DIS_M4

SDA/SMBDATA/NON_REM1

OCS4*

OCS3*

RBIAS

VBUS_DET

PRTPWR3

PRTPWR2

USBDN2_DM/PRT_DIS_M2

USBDN1_DP/PRT_DIS_P1

USBDN1_DM/PRT_DIS_M1

SUSP_IND/LOCAL_PWR/NON_REM0

XTAL2

XTAL1/CLKIN

RESET*

USBUP_DP

USBUP_DM

OCS2*

PRTPWR4

OCS1*

VDD33PLL

VDD33CR

VDD33

VDD18

VDD18PLL

THRML_PAD

TEST

(SYM-VER1)

VDDA33

BI

BI BI

BI

IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

External A

Trackpad/Keyboard

SD Card/Express Card

IR Receiver

External C

External B

Bluetooth

IPU IPU

IPU

0 0 All ports are removable

1 1 Port 1, 2, and 3 are non removable

1 0 Port 1 and 2 are non removable

NON_REM1 NON_REM0 DESCRIPTION

0 1 Port 1 is non removable

BOM TABLE

T29 unused USB port, only has pull up

5%

402

MF-LF

1/16W

10K

R2641

1

2

SOT-363

2N7002DW-X-G

Q2640

3

5

4

402

5%

20K

1/16W MF-LF

R2640

1 2

SOT-363

2N7002DW-X-G

Q2640

6

2

1

5% 50V CERM 402

100PF

NOSTUFF

C2641

1

2

10%

6.3V 402

CERM-X5R

0.47UF

C2640

1

2

CRITICAL

5%

50V

CERM

402

18PF

C2619

1

2

402

5%

MF-LF

1/16W

1M

CRITICAL

R2630

1 2

CRITICAL

402

CERM

50V

5%

18PF

C2620

1

2

6.3V

20%

10UF

603

X5R

C2604

1

2

0.01UF

CERM

16V

10%

402

C2605

1

2

100PF

CERM

50V 402

5%

C2606

1

2

402

10% 16V CERM

0.01UF

C2600

1

2

FERR-120-OHM-1.5A

0402

L2601

1 2

603

X5R

6.3V

20%

10UF

C2607

1

2

5%

402

50V CERM

100PF

C2601

1

2

0402

1 2

L2600

FERR-120-OHM-1.5A

100PF

CERM

50V 402

5%

C2656

1

2

402

CRITICAL

5%

MF-LF

1/16W

1M

R2680

1 2

0.01UF

CERM

16V

10%

402

C2655

1

2

QFN

USX2061

OMIT

U2600

25

13 17 19 21

12 16 18 20

35

26

24

22

28

11

37

1 2

3 4

6 7

8 9

30 31

27

143423

15

36510

29

33 32

402

MF

12K

1/16W

1%

CRITICAL

R2600

1

2

43 94

42 94

18 94

42 94

44 94

8

94

44 94

8

94

0.1UF

X7R-CERM 402

10% 16V

C2615

1

2

1UF

X5R

16V

10%

402

C2616

1

2

MF-LF

1/16W

5%

402

10K

R2620

1

2

0.1UF

X7R-CERM

16V

10%

402

C2617

1

2

16V X5R

1UF

402

10%

C2618

1

2

0.1UF

402

10% 16V

X7R-CERM

C2608

1

2

6.3V X5R

20%

603

10UF

C2602

1

2

0.1UF

X7R-CERM

16V

10%

402

C2609

1

2

0.1UF

402

10% 16V

X7R-CERM

C2610

1

2

10% 16V

402

X7R-CERM

0.1UF

C2603

1

2

X7R-CERM 402

10% 16V

C2611

1

2

0.1UF 0.1UF

402

10%

C2612

1

2

X7R-CERM

16V

0.01UF

CERM

16V

10%

402

C2613

1

2

0.01UF

CERM

16V

10%

402

C2614

1

2

18 23

5% 1/16W MF-LF

402

100K

R2642

1

2

8

43

42

5%

MF-LF

1/16W

100

402

R2605

1 2

SOD-523

BAT54XV2T1

D2600

12

10K

MF-LF

1/16W 402

5%

R2606

1

2

10K

MF-LF

1/16W 402

5%

R2607

1

2

5%

402

HUB1_NONREM0_0

10K

1/16W MF-LF

R2604

1

2

HUB1_NONREM0_1

402

1/16W MF-LF

5%

10K

R2603

1

2

HUB1_NONREM1_1

1/16W MF-LF

402

10K

5%

R2601

1

2

HUB1_NONREM1_0

MF-LF

1/16W

10K

5%

402

R2602

1

2

16V

10% X5R

402

1

2

1UF

C2668

0.1UF

16V

10%

402

X7R-CERM

C2667

1

2

0.01UF

402

10% 16V CERM

C2664

1

2

X5R 402

10% 16V

1UF

C2666

1

2

X7R-CERM

10% 16V

402

0.1UF

C2665

1

2

0.01UF

10%

402

16V CERM

C2663

1

2

0.1UF

X7R-CERM

16V

10%

402

C2662

1

2

X7R-CERM

0.1UF

10% 16V

402

C2661

1

2

0.1UF

10%

402

16V

X7R-CERM

C2660

1

2

1/16W

10K

MF-LF 402

5%

R2670

1

2

12K

402

1% MF

CRITICAL

1/16W

R2650

1

2

18 94

QFN

OMIT

USX2061

U2650

25

13 17 19 21

12 16 18 20

35

26

24

22

28

11

37

1 2

3 4

6 7

8 9

30 31

27

143423

15

36510

29

33 32

10% 16V

0.1UF

402

X7R-CERM

C2653

1

2

20%

6.3V X5R 603

10UF

C2652

1

2

0.1UF

X7R-CERM

16V

10%

402

C2659

1

2

0.1UF

16V

10%

402

X7R-CERM

C2658

1

2

603

X5R

6.3V

20%

10UF

C2657

1

2

5%

1/16W

100

MF-LF

402

R2655

1 2

CRITICAL

402

18PF

CERM

50V

5%

C2670

1

2

5%

50V

CERM

18PF

402

CRITICAL

C2669

1

2

MF-LF

1/16W 402

10K

5%

R2657

1

2

402

10K

MF-LF

1/16W

5%

R2656

1

2

HUB2_NONREM0_1

5%

402

10K

1/16W MF-LF

R2653

1

2

HUB2_NONREM1_1

10K

1/16W MF-LF

402

5%

R2651

1

2

5%

402

10K

1/16W MF-LF

HUB2_NONREM0_0

R2654

1

2

MF-LF

1/16W

10K

402

5%

HUB2_NONREM1_0

R2652

1

2

FERR-120-OHM-1.5A

0402

L2650

1 2

402

50V CERM

100PF

5%

C2651

1

2

FERR-120-OHM-1.5A

0402

L2651

1 2

402

10% 16V CERM

0.01UF

C2650

1

2

10UF

6.3V 603

20% X5R

C2654

1

2

53 94

6

31 94

6

31 94

CRITICAL

SM-2

24.000MHZ-16PF

Y2600

2 4

1 3

24.000MHZ-16PF

CRITICAL

SM-2

Y2650

2 4

1 3

8

32

100 8

32

100

42 94

8

32

42

SYNC_DATE=06/29/2010

USB HUBS

SYNC_MASTER=K92_BEN

U2600,U2650

USBHUB_2514B

CRITICAL

SMSC USB2514B

2

338S0824

U2600,U2650

USBHUB_2514

CRITICAL

SMSC USB2514

2

338S0720

U2600,U2650

USBHUB_2061

CRITICAL

SMSC USX2061

2

338S0721

HUB2_3NONREM

HUB2_NONREM1_1,HUB2_NONREM0_1

HUB2_2NONREM

HUB2_NONREM1_1,HUB2_NONREM0_0

HUB2_ALLREM

HUB2_NONREM1_0,HUB2_NONREM0_0

HUB2_1NONREM

HUB2_NONREM1_0,HUB2_NONREM0_1

HUB1_NONREM1_1,HUB1_NONREM0_1

HUB1_3NONREM

HUB1_NONREM1_1,HUB1_NONREM0_0

HUB1_2NONREM

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB1_ALLREM

HUB1_NONREM1_0,HUB1_NONREM0_1

HUB1_1NONREM

PP3V3_S3

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

PPUSB_HUB1_VDDPLL3V3

VOLTAGE=3.3V

USB_T29A_N

PP3V3_S3

USB_HUB_SOFT_RESET_L

PP3V3_S5

P3V3S3_EN_RC

PP3V3_S3

USB_HUB_RESET

USB_HUB_RESET_L

PP3V3_S3

USB_HUB2_RBIAS

USB_HUB2_VBUS_DET

USB_HUB_RESET_L

USB_IR_N

NC_USB_HUB1_PRTPWR3

USB_HUB1_TEST

USB_HUB1_CFG_SEL0

USB_EXTB_P

USB_EXTB_N

USB_IR_P

USB_HUB2_TEST

USB_TPAD_P

USB_HUB2_CFG_SEL1

USB_HUB2_CFG_SEL0

USB_HUB2_NONREM1

NC_USB_HUB2_PRTPWR3

NC_USB_HUB2_PRTPWR2

USB_TPAD_N

USB_BT_P

USB_HUB2_NONREM0

USB_HUB_RESET_L

USB_HUB2_UP_P

NC_USB_HUB2_OCS2

NC_USB_HUB2_PRTPWR4

PP3V3_S3

USB_HUB1_NONREM0 USB_HUB1_NONREM1

USB_HUB2_XTAL2

USB_HUB2_XTAL1

USB_HUB1_XTAL1

USB_EXTB_OC_L

USB_HUB1_CFG_SEL1

TP_USB_HUB2_OCS1

TP_USB_HUB2_PRTPWR1

USB_HUB1_UP_N

USB_EXTC_OC_L

TP_USB_HUB1_OCS1

NC_USB_HUB1_PRTPWR4

USB_EXTA_N USB_EXTA_P

USB_EXCARD_P

USB_EXCARD_N

USB_HUB2_UP_N

USB_EXTA_OC_L

NC_USB_HUB1_OCS2

NC_USB_HUB1_PRTPWR2

TP_USB_HUB1_PRTPWR1

USB_EXTC_P

USB_EXTC_N

EXCARD_OC_L

USB_HUB1_UP_P

USB_HUB1_XTAL2

USB_BT_N

PPUSB_HUB2_VDD1V8

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM

PPUSB_HUB1_VDD1V8PLL

MIN_NECK_WIDTH=0.11MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

PPUSB_HUB1_VDD1V8

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

PPUSB_HUB1_VDDA3V3

PPUSB_HUB2_VDDA3V3

MIN_LINE_WIDTH=0.4MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

PPUSB_HUB2_VDDPLL3V3

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

PPUSB_HUB2_VDD1V8PLL

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.11MM

USB_HUB1_VBUS_DET

USB_HUB1_RBIAS

USB_T29A_P

26 OF 132 24 OF 105

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31

32 48 49 50 54 55 73 88

104

6 7

17 19 20 22 23 25 29 46 48 56 71 72

73 83 86 91

100 102 104

6 7 8

18 24 25 29 30 31 32 48 49 50 54

55 73 88

104

6 7 8

18 24 25 29 30 31

32 48 49 50 54 55 73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

24

6 7 8

18 24 25 29 30

31 32 48 49 50 54 55 73

88

104

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

D

GS

OUT

IN

OUT

VBAT

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

PAD

NC NC

OUT

NC

OUT

D

SG

IN

D

SG

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH Reset Button

Ethernet WAKE# Isolation

VDDIO_25M_A: SB power rail for XTAL circuit. VDDIO_25M_B: Ethernet power rail for XTAL circuit. VDDIO_25M_C: T29 power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

to reduce VBAT draw.

No Coin-Cell: 3.3V S5

For SB RTC Power

APN:359S0178

VBAT and +V3.3A are

No bypass necessary

T29 XTAL Power

Buffered CPU reset

VTT voltage divider on CPU page

Series R is R4283

Platform Reset Connections

Unbuffered

Ethernet XTAL Power

GreenClk 25MHz Power

SB XTAL Power

+V3.3A should be first available ~3.3V power

create VDD_RTC_OUT.

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Buffered

Series R is R3803

Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.

System RTC Power Source & 32kHz / 25MHz Clock Generator

internally ORed to

NOTE: 30 PPM crystal required

Coin-Cell & No G3Hot: 3.3V S5

Coin-Cell: VBAT (300-ohm & 10uF RC)

ENET_MEDIA_SENSE ISOLATION CIRCUIT

10 23 92

21

R2896

XDP

MF-LF

5%

0

402

1/16W

21

R2883

MF-LF

402

1/16W

33

5%

21

R2881

5%

402

MF-LF

33

1/16W

6

25 47 88 95

45

31

21

R2856

PLACE_NEAR=U1800.P53

1/20W

5% MF

201

22

21

R2855

1/20W

201

22

PLACE_NEAR=U1800.N52

5% MF

18 95

30

21

R2871

0

5%

402

1/16W MF-LF

6

47 95

45 95

18

88

21

R2857

PLACE_NEAR=U1800.P46

5%

201

1/20W

MF

22

23

21

R2889

XDP

1/16W

5%

402

1K

MF-LF

20%

2

1

C2880

10V

CERM

402

0.1UF

5

4

1

2

3

U2880

SC70-HF

MC74VHC1G08

CRITICAL

MF-LF

2

1

R2880

5% 1/16W

100K

402

32

16 95

21

R2859

PLACE_NEAR=U1800.P48

201

1/20W

MF

22

5%

18

18 25

25 88

21

R2887

5%

402

0

1/16W MF-LF

SILK_PART=SYS RESET

2

1

R2897

OMIT

MF-LF 402

5%

0

1/16W

6

25 47 88 95

90

R2895

4.7K

1/16W MF-LF

2

1

5%

402

6

17 45

18 25 29 39

2

3

Q2830

SSM3K15FV

SOD-VESM-HF

CRITICAL

1

6

17 31 32 85 25 36

2

1

R2830

1/16W

5%

10K

MF-LF 402

25 32 35

16

33

2

1

C2810

402

10% CERM

6.3V

1UF

2

1

C2802

1UF

X5R

10%

402-1

10V

0.1UF

2

1

C2820

20%

402

10V

CERM

2

1

C2822

10V

20%

0.1UF

402

CERM

CRITICAL

3 4

14

6

11

1

5

13

17216107

12

15

8

9

U2800

TQFN

SLG3NB148V

2

1

R2806

NO STUFF

MF-LF

5%

402

1M

1/16W

2

1

C2824

10V

20%

0.1UF

402

CERM

R2805

21

402

0

1/16W

5%

MF-LF

31

42

Y2805

CRITICAL

SM-3.2X2.5MM

25.000MHZ-12PF-30PPM

2 1

C2805

12PF

402

CERM

50V

5%

21

C2806

12PF

5%

50V

CERM

402

10 23 25

2

1

R2890

MF-LF

100K

1/16W

5%

402

4

5

1 3

2

U2890

SC70

74LVC1G07

CRITICAL

2

1

C2890

0.1UF

402

10V

20%

CERM

5%

2

1/16W

R2882

MF-LF

1

402

0

R2888

0

MF-LF

21

5%

402

1/16W

0

21

R2893

402

5%

MF-LF

21

R2800

201

1/20W

0

MF

5%

16

PLACE_NEAR=U1800.N32:5mm

MF

201

1

2

1/20W

5%

10K

R2819

R2810

21

402

1/16W

12K

5%

MF-LF

4

3

CRITICAL

SSM6N37FEAPE

5

SOT563

Q2810

R2811

201

1/20W

5%

MF

2

1

100K

36

SSM6N37FEAPE

6

1

2

SOT563

Q2810

0

5%

MF-LF

1/16W

402

2

1

R2812

Chipset Support

SYNC_MASTER=K91_MLB

SYNC_DATE=06/29/2010

ENET_MEDIA_SENSE_RDIV

SYSCLK_CLK25M_X1

LPC_CLK33M_LPCPLUS

ENET_MEDIA_SENSE

ENET_MEDIA_SENSE_EN_L

LPC_CLK33M_SMC

PP1V5_S0

PP3V3_S3

PCIE_WAKE_L

ENET_MEDIA_SENSE_EN

MAKE_BASE=TRUE

PLT_RST_BUF_L

AP_RESET_L

PLT_RST_BUF_L

LPC_CLK33M_SMC_R

MAKE_BASE=TRUE

ENET_WAKE_L

LPC_CLK33M_GMUX_R

MAKE_BASE=TRUE

LPCPLUS_RESET_L

PLT_RST_CPU_BUF_L

ENET_WAKE_L

SMC_LRESET_L

PP3V3_S0

PCH_CLK33M_PCIIN

XDP_DBRESET_L

LPC_CLK33M_GMUX

SYSCLK_CLK25M_X2

XDPPCH_PLTRST_L

PCA9557D_RESET_L

PP3V3_S0

PCH_CLK33M_PCIOUT

LPCPLUS_RESET_L

GMUX_RESET_L

BKLT_PLT_RST_L

PLT_RESET_L

LPC_CLK33M_GMUX_R

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_T29

PP3V3_T29

PP3V3_S5

PP3V42_G3H

PP1V8_S0

PP3V3_ENET

SYSCLK_CLK25M_ENET_R

SYSCLK_CLK25M_ENET

SYSCLK_CLK32K_RTC

PP3V3_ENET

MAKE_BASE=TRUE

GMUX_RESET_L

MAKE_BASE=TRUE

PLT_RST_CPU_BUF_L

PP3V3_S0

PM_SYSRST_L

PLT_RST_BUF_L

LPC_CLK33M_LPCPLUS_R

ENET_RESET_L_R

PLT_RESET_L

MAKE_BASE=TRUE

28 OF 132 25 OF 105

7

16 20 22

32 41 57 71

6 7 8

18 24 29 30 31 32 48 49 50 54 55

73 88

104

25 32

35

25 36

18 25

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

7

16 17 20

7

16 19 33 34 35 88

6 7

17 19 20 22 23 24 29 46 48 56 71 72

73 83 86 91

100 102 104

6 7

42 44 45 46 47 48 53 63 64 73

104

6 7

14 20 71 72 88

102

7

25 36 71 73

36

7

25 36 71 73

7

25 36 71 73

25 88

10 23

25

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

BI

IN

BI

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI

BI BI

BI

BI BI

BI

OUT

BI

IN

IN IN

BI BI

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

516-0229

(NONE)

SPD ADDR=0xA0(WR)/0xA1(RD)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP0V75_S0_MEM_VTT_A

- =PP1V5_S3_MEM_A

- =PP1V5_S0_MEM_A

Power aliases required by this page:

Page Notes

Signal aliases required by this page:

"Factory" (top) slot

DDR3-SODIMM-DUAL-K6

F-RT-THB

J2900

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

27

0.1UF

10V

20%

402

CERM

C2931

1

2

2.2UF

20%

402-LF

CERM

6.3V

C2930

1

2

27

11 93

11 27 93

27

28 29

27

F-RT-THB

DDR3-SODIMM-DUAL-K6

CRITICAL

J2900

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

27

11 93

27

11 93

11 27 93

27

0.1UF

CERM 402

20% 10V

C2936

1

2

CERM

2.2UF

6.3V

20%

402-LF

C2935

1

2

27

28 45

6

16 23 28 30 32 41 48 62 89 95

6

16 23 28 30 32 41 48 62 89 95

11 93

27

MF-LF

1/16W

402

5%

10K

R2941

1

2

402

5% 1/16W MF-LF

10K

R2940

1

2

6.3V

402-LF

CERM

20%

2.2UF

C2940

1

2

PLACE_NEAR=J2900.75:2.54mm

20%

603

6.3V X5R

10UF

C2900

1

2

10UF

X5R

6.3V

PLACE_NEAR=J2900.75:2.54mm

20%

603

C2901

1

2

PLACE_NEAR=J2900.75:2.54mm

0.1UF

20% 10V

402

CERM

C2910

1

2

CERM

10V

20%

402

0.1UF

PLACE_NEAR=J2900.75:2.54mm

C2911

1

2

CERM

PLACE_NEAR=J2900.75:2.54mm

402

10V

20%

0.1UF

C2912

1

2

0.1UF

20% 10V CERM

PLACE_NEAR=J2900.75:2.54mm

402

C2913

1

2

0.1UF

20% CERM

402

10V

PLACE_NEAR=J2900.75:2.54mm

C2914

1

2

CERM 402

10V

20%

0.1UF

PLACE_NEAR=J2900.75:2.54mm

C2915

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2916

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2917

1

2

CERM 402

20% 10V

0.1UF

PLACE_NEAR=J2900.75:2.54mm

C2918

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2919

1

2

0.1UF

CERM 402

20% 10V

PLACE_NEAR=J2900.75:2.54mm

C2920

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2921

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2922

1

2

PLACE_NEAR=J2900.75:2.54mm

CERM 402

20%

0.1UF

10V

C2923

1

2

10% 10V

1UF

X5R 402

C2950

1

2

10% 10V

1UF

X5R 402

C2951

1

2

10% 10V

1UF

X5R 402

C2952

1

2

10% 10V

1UF

X5R 402

C2953

1

2

SYNC_MASTER=K92_YUN

SYNC_DATE=06/14/2010

DDR3 SO-DIMM Connector A

PP0V75_S0_DDRVTT

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

=MEM_A_DQ<41>

=MEM_A_DQ<55>

=MEM_A_DQ<53>

=MEM_A_DQ<47>

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQ<9>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_A<14>

MEM_A_A<6> MEM_A_A<4>

=MEM_A_DQS_N<5>

=MEM_A_DQ<21>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<2> =MEM_A_DQ<3>

=MEM_A_DQ<1>

=MEM_A_DQ<0>

=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>

=MEM_A_DQ<24>

=MEM_A_DQ<5>

MEM_A_DQS_N<0> =MEM_A_DQS_P<0>

=MEM_A_DQ<6> =MEM_A_DQ<7>

=MEM_A_DQ<12> =MEM_A_DQ<13>

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQ<20>

=MEM_A_DQ<28>

=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>

=MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQ<4>

=MEM_A_DQ<26>

=MEM_A_DQ<16>

MEM_A_CKE<1>

MEM_A_ODT<0>

=MEM_A_DQ<38> =MEM_A_DQ<39>

MEM_A_BA<2>

=MEM_A_DQ<40>

=MEM_A_DQS_P<5>

=MEM_A_DQ<54>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

MEM_EVENT_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<57>

MEM_A_SA<0>

MEM_A_CLK_N<0>

=MEM_A_DQ<35>

=MEM_A_DQS_N<4>

MEM_A_SA<1>

=MEM_A_DQ<33>

MEM_A_CLK_P<0>

=MEM_A_DQS_P<4>

MEM_A_CKE<0>

MEM_A_CS_L<1>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_A<10>

MEM_A_A<1>

MEM_A_A<8>

MEM_A_CS_L<0>

MEM_A_A<2>

MEM_A_RAS_L

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_ODT<1>

=MEM_A_DQ<29>

=MEM_A_DQS_P<2>

=MEM_A_DQ<11>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<15>

=MEM_A_DQ<48> =MEM_A_DQ<49>

=MEM_A_DQ<50>

=MEM_A_DQ<32>

=MEM_A_DQ<56>

=MEM_A_DQ<51>

=MEM_A_DQ<34>

MEM_A_BA<0>

MEM_A_A<3>

MEM_A_A<5>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<36> MEM_A_DQ<37>

=MEM_A_DQ<44> =MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<52>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

PP3V3_S0

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQS_N<2>

=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<25>

=MEM_A_DQ<27>

MEM_RESET_L

=MEM_A_DQ<8>

PP1V5_S3

29 OF 132 26 OF 105

7

28 29 67

30

9

30

6 7

12 23 25 28

32 35 36 39 40 41 46 48

49 50 51 52 54

57 61 62 72 73 80 83 84

85 88 89 91

100 102

7

28 29 67 72

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

CPU CHANNEL B DQS 6 -> DIMM B DQS 6

CPU CHANNEL A DQS 5 -> DIMM A DQS 5

CPU CHANNEL A DQS 6 -> DIMM A DQS 6

CPU CHANNEL A DQS 7 -> DIMM A DQS 7

CPU CHANNEL A DQS 4 -> DIMM A DQS 4

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

CPU CHANNEL A DQS 2 -> DIMM A DQS 2

CPU CHANNEL A DQS 1 -> DIMM A DQS 1

CPU CHANNEL A DQS 3 -> DIMM A DQS 3

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

SYNC_DATE=05/14/2010

SYNC_MASTER=K92_YUN

DDR3 Byte/Bit Swaps

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<5> MEM_A_DQ<4>

MAKE_BASE=TRUE

MEM_A_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<42>

MAKE_BASE=TRUE

MEM_B_DQ<47>MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DQ<35>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<13>

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQ<30>MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_A_DQ<62>

MAKE_BASE=TRUE

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<40>

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<51>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MAKE_BASE=TRUE

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

MAKE_BASE=TRUE

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_A_DQ<11>

MAKE_BASE=TRUE

MEM_B_DQ<11> MEM_B_DQ<10>

MAKE_BASE=TRUE

MEM_B_DQ<18>

MAKE_BASE=TRUE

MEM_B_DQ<17>

MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<32>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MAKE_BASE=TRUE

MEM_B_DQ<40>

MEM_B_DQ<41>

MAKE_BASE=TRUE

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQ<52>

MAKE_BASE=TRUE

MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<59>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<56>

MAKE_BASE=TRUE

MEM_B_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<15>

MAKE_BASE=TRUE

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<12>

MEM_B_DQ<8>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MAKE_BASE=TRUE

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MEM_B_DQ<22>

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<13>

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MEM_A_DQ<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MAKE_BASE=TRUE

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<17> MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<18>

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<54>

MAKE_BASE=TRUE

MEM_B_DQ<55>

MAKE_BASE=TRUE

MEM_B_DQ<43>

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MAKE_BASE=TRUE

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQS_N<1>

MAKE_BASE=TRUE

MEM_B_DQ<0>

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

=MEM_A_DQ<42>

=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>

=MEM_A_DQ<30> =MEM_A_DQ<29>

=MEM_A_DQ<27> =MEM_A_DQ<26> =MEM_A_DQ<25>

=MEM_A_DQ<28>

=MEM_A_DQ<31>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<20>

=MEM_A_DQ<23>

=MEM_A_DQ<1> =MEM_A_DQ<0>

=MEM_A_DQS_P<1>

=MEM_A_DQ<2>

=MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

=MEM_A_DQ<4>

=MEM_A_DQ<7> =MEM_A_DQ<6> =MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQ<22> =MEM_A_DQ<21>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<12>

=MEM_A_DQ<13>

=MEM_A_DQ<15>

=MEM_B_DQ<25>

=MEM_B_DQ<33>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<19> =MEM_B_DQ<18>

=MEM_B_DQ<31>

=MEM_B_DQS_P<3>

=MEM_B_DQ<20>

=MEM_B_DQ<16>

=MEM_B_DQ<12>

=MEM_B_DQ<15>

=MEM_B_DQ<22>

=MEM_B_DQS_P<2>

MEM_B_DQS_N<0>

=MEM_B_DQ<7> =MEM_B_DQ<6>

=MEM_B_DQ<4>

=MEM_B_DQ<29>

=MEM_B_DQ<27>

=MEM_B_DQ<9>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

=MEM_B_DQ<59>

=MEM_B_DQ<61> =MEM_B_DQ<60>

=MEM_B_DQ<63> =MEM_B_DQ<62>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_B_DQ<49>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<52>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQS_P<6>

=MEM_B_DQS_N<6>

=MEM_B_DQ<41>

=MEM_B_DQ<47>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<5>

=MEM_B_DQ<32>

=MEM_B_DQ<36>

MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQS_P<4>

=MEM_B_DQ<39>

=MEM_B_DQS_N<4>

=MEM_B_DQ<24>

=MEM_B_DQ<28>

=MEM_B_DQ<30>

=MEM_B_DQS_N<3>

=MEM_B_DQ<17>

=MEM_B_DQ<21>

=MEM_B_DQ<23>

=MEM_B_DQS_N<2>

=MEM_B_DQ<8>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<5>

MEM_B_DQS_P<0>

=MEM_A_DQ<14>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<45>

=MEM_A_DQ<47>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>

=MEM_A_DQ<56>

=MEM_A_DQ<59> =MEM_A_DQ<58> =MEM_A_DQ<57>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQ<63> =MEM_A_DQ<62>

=MEM_A_DQ<48>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_A_DQ<49>

=MEM_A_DQ<51> =MEM_A_DQ<50>

=MEM_A_DQ<54> =MEM_A_DQ<53> =MEM_A_DQ<52>

=MEM_A_DQ<55>

=MEM_A_DQ<43>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<33>

=MEM_A_DQ<35>

=MEM_A_DQ<36>

=MEM_A_DQ<38> MEM_A_DQ<37>

=MEM_A_DQS_P<4>

=MEM_A_DQ<39>

=MEM_A_DQS_N<4>

=MEM_A_DQ<24>

=MEM_B_DQ<26>

=MEM_B_DQ<48>

=MEM_B_DQ<53>

=MEM_B_DQ<58>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<44>

=MEM_B_DQ<45>

=MEM_B_DQ<40>

=MEM_B_DQ<46>

=MEM_A_DQ<3>

MEM_A_DQS_P<0>

30 OF 132 27 OF 105

11 93

11 93 11 93

11 93

11 93 11 93

11 93

11 26 27 93

11 93

11 93 11 93

11 93

11 27 28 93

11 93

11 27 28 93

11 93

11 26 27 93

11 93

11 27 28 93

26

11 26 27 93

26

28

11 27 28 93

28

11 27 28 93

28

11 27 28 93

26

11 26 27 93

26

28

26

11 93

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

BI BI

NC

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

BI

IN

BI

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

BI

BI BI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

B

8 7 5 4 2 1

- =PP0V75_S0_MEM_VTT_B

- =I2C_SODIMMB_SDA

BOM options provided by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

Power aliases required by this page:

- =I2C_SODIMMB_SCL

(NONE)

Signal aliases required by this page:

"Expansion" (bottom) slot

- =PP1V5_S3_MEM_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

516S0806

SPD ADDR=0xA4(WR)/0xA5(RD)

- =PP1V5_S0_MEM_B

Page Notes

11 93

27

26 45

6

16 23 26 30 32 41 48 62 89 95

6

16 23 26 30 32 41 48 62 89 95

0.1UF

402

20% 10V CERM

C3131

1

2

11 93

27

2.2UF

20%

6.3V

402-LF

CERM

C3130

1

2

1/16W

10K

402

MF-LF

5%

R3141

1

2

10K

5%

402

1/16W MF-LF

R3140

1

2

20%

CERM 402-LF

6.3V

2.2UF

C3140

1

2

10UF

20% X5R

6.3V 603

PLACE_NEAR=J3100.75:2.54mm

C3100

1

2

6.3V

10UF

X5R 603

20%

PLACE_NEAR=J3100.75:2.54mm

C3101

1

2

PLACE_NEAR=J3100.75:2.54mm

CERM 402

10V

20%

0.1UF

C3110

1

2

PLACE_NEAR=J3100.75:2.54mm

0.1UF

402

CERM

10V

20%

C3111

1

2

CERM

0.1UF

20% 10V

402

PLACE_NEAR=J3100.75:2.54mm

C3112

1

2

CERM 402

0.1UF

10V

20%

PLACE_NEAR=J3100.75:2.54mm

C3113

1

2

27

0.1UF

10V 402

CERM

20%

PLACE_NEAR=J3100.75:2.54mm

C3114

1

2

10V CERM

0.1UF

20%

402

PLACE_NEAR=J3100.75:2.54mm

C3115

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3116

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3117

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3118

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3119

1

2

10V

20%

402

CERM

0.1UF

PLACE_NEAR=J3100.75:2.54mm

C3120

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3121

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3122

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3123

1

2

27

1UF

402

X5R

10V

10%

C3153

1

2

1UF

402

X5R

10V

10%

C3152

1

2

11 93

402

X5R

1UF

10V

10%

C3151

1

2

402

X5R

1UF

10V

10%

C3150

1

2

DDR3-SODIMM

F-RT-BGA6

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206 207 208 209 210 211 212

203 204

113

11 27 93

27

26 29

27

CRITICAL

DDR3-SODIMM

F-RT-BGA6

J3100

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

27

11 93

27

11 93

27

11 93

27

11 27 93

27

20%

0.1UF

10V

402

CERM

C3136

1

2

402-LF

20%

CERM

6.3V

2.2UF

C3135

1

2

27

SYNC_MASTER=K92_YUN

SYNC_DATE=06/14/2010

DDR3 SO-DIMM Connector B

=MEM_B_DQ<54>

=MEM_B_DQ<33>

=MEM_B_DQ<42>

=MEM_B_DQ<48> =MEM_B_DQ<49>

=MEM_B_DQS_N<6> =MEM_B_DQS_P<6>

MEM_B_A<3>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_A<10> MEM_B_BA<0>

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_RAS_L

MEM_B_ODT<0>

=MEM_B_DQ<59>

=MEM_B_DQ<13>

MEM_B_A<1>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<12>

=MEM_B_DQ<41>

=MEM_B_DQS_N<4>

MEM_B_CKE<1>

MEM_B_A<15> MEM_B_A<14>

MEM_B_A<11> MEM_B_A<7>

MEM_B_A<2> MEM_B_A<0>

MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_CS_L<0>

PP0V75_S3_MEM_VREFCA_B

=MEM_B_DQ<36> MEM_B_DQ<37>

=MEM_B_DQ<38> =MEM_B_DQ<39>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQS_N<5>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_B_A<13>

=MEM_B_DQ<32>

=MEM_B_DQ<40>

=MEM_B_DQ<46>

=MEM_B_DQS_P<5>

=MEM_B_DQ<47>

=MEM_B_DQ<52> =MEM_B_DQ<53>

=MEM_B_DQ<55>

=MEM_B_DQ<63>

MEM_EVENT_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

=MEM_B_DQ<51>

=MEM_B_DQ<35>

=MEM_B_DQ<56> =MEM_B_DQ<57>

MEM_B_SA<1>

=MEM_B_DQ<58>

=MEM_B_DQ<2> =MEM_B_DQ<3>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<1>

=MEM_B_DQ<0>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQS_N<1> =MEM_B_DQS_P<1>

=MEM_B_DQ<10> =MEM_B_DQ<11>

=MEM_B_DQ<17>

=MEM_B_DQS_N<2> =MEM_B_DQS_P<2>

=MEM_B_DQ<18> =MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQ<5>

MEM_B_DQS_N<0>

=MEM_B_DQ<6> =MEM_B_DQ<7>

=MEM_B_DQ<12>

MEM_RESET_L

=MEM_B_DQ<14> =MEM_B_DQ<15>

=MEM_B_DQ<20> =MEM_B_DQ<21>

=MEM_B_DQ<22> =MEM_B_DQ<23>

=MEM_B_DQ<28> =MEM_B_DQ<29>

=MEM_B_DQS_N<3> =MEM_B_DQS_P<3>

=MEM_B_DQ<30> =MEM_B_DQ<31>

=MEM_B_DQ<4>

=MEM_B_DQ<27>

=MEM_B_DQ<26>

=MEM_B_DQ<16>

=MEM_B_DQ<50>

=MEM_B_DQ<62>

=MEM_B_DQ<34>

=MEM_B_DQS_P<4>

PP3V3_S0

MEM_B_A<4>

PP1V5_S3

MEM_B_A<6>

=MEM_B_DQ<43>

MEM_B_SA<0>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

MEM_B_DQS_P<0>

PP0V75_S0_DDRVTT

MEM_B_WE_L

31 OF 132 28 OF 105

30

9

30

6 7

12 23 25 26 32

35 36 39 40 41 46 48 49 50

51 52 54 57 61 62

72 73 80 83 84 85 88 89 91

100 102

7

26 29 67 72

7

26 29 67

IN IN

IN

OUT

D

SG

D

S G

D

SG

D

S G

D

SG

D

S G

D

S G

D

SG

OUT

IN

D

SG

D

SG

IN

G

D

S

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

60mW max power

S0 to S3 to S0

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

5 0 1 1 1 0 (*) 1 1 1 6 0 1 1 1 1 1 1 1 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

75mA max load @ 0.75V

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

MEMVTT Clamp

1V5 S0 "PGOOD" for CPU

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

Ensures CKE signals are held low in S3

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

4 0 0 1 1 X 1 0 1

3 0 0 0 1 X 1 0 0

2 0 0 1 1 1 1 0 1

1 0 1 1 1 1 1 1 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

19 23

6

17 45 73

18 25 39

1/16W

5%

MF-LF

CPUMEM_S0

402

R3202

1

2

100K

8

29 67

CPUMEM_S0

MF-LF

10K

1/16W

5%

402

R3210

1

2

CPUMEM_S0

100K

MF-LF

402

5%

1/16W

R3215

1

2

26 28

20K

MF-LF 402

1/16W

1

2

R3216

CPUMEM_S0

5%

CPUMEM_S0

SOT563

SSM6N15FEAPE

Q3200

3

5

4

CPUMEM_S0

SSM6N15FEAPE

SOT563

Q3205

3

5

4

CRITICAL

SSM6N15FEAPE

SOT563

CPUMEM_S0

Q3210

6

2

1

SSM6N15FEAPE

CPUMEM_S0

Q3210

3

5

4

SOT563

CPUMEM_S0

SSM6N15FEAPE

CRITICAL

SOT563

Q3200

6

2

1

CPUMEM_S0

SOT563

Q3215

6

2

SSM6N15FEAPE

1

SOT563

3

5

4

CRITICAL

SSM6N15FEAPE

Q3215

CPUMEM_S0

CRITICAL

SOT563

SSM6N15FEAPE

CPUMEM_S0

Q3205

6

2

1

72

CPUMEM_S0

10K

1/16W

5%

402

MF-LF

R3205

1

2

17 42 45 66 73

402

100K

5%

MF-LF

CPUMEM_S0

1/16W

R3201

1

2

8

29 67

SSM6N15FEAPE

SOT563

CPUMEM_S0

Q3250

3

5

4

1/16W MF-LF

5%

100K

402

CPUMEM_S0

R3251

1

2

1

C3251

CERM

20%

0.001UF

50V

NO STUFF

402

CRITICAL

SSM6N15FEAPE

SOT563

CPUMEM_S0

Q3250

6

2

1

MF-LF

10

5%

603

1/10W

CPUMEM_S0

R3250

1

2

MF-LF

1/16W

5%

402

1 2

0

R3217

CPUMEM_S3

10 29

MF-LF

1%

402

1/16W

R3221

1

2

33.2K

402

27.4K

1% 1/16W MF-LF

R3220

1

2

CRITICAL

SOT-563

DMB53D0UV

Q3220

5

3

4

MF-LF

1/16W

5%

10K

402

R3222

1

2

SOT-563

CRITICAL

DMB53D0UV

Q3220

6

2

1

10 17 92

CERM

NO STUFF

402

50V

20%

0.001UF

C3220

1

2

16V X5R

10%

0.1UF

CPUMEM_S0

C3216

402

1

2

SYNC_MASTER=K17_MLB

SYNC_DATE=04/26/2010

CPU Memory S3 Support

MEMRESET_ISOL_LS5V_L

PP1V5_S3

MEM_RESET_L

MAKE_BASE=TRUE

CPU_MEM_RESET_L

PLT_RESET_L

PP3V3_S3

P1V5_S0_DIV

PM_MEM_PWRGD

PM_MEM_PWRGD_L

PP3V3_S5

PP1V5_S3RS0_CPUDDR

PM_SLP_S4_L

PP5V_S3

MEMVTT_EN_L

MEMVTT_EN

PP5V_S3

VTTCLAMP_EN

VTTCLAMP_L

PP0V75_S0_DDRVTT

P1V5CPU_EN_L

P1V5CPU_EN

PM_SLP_S3_L

CPU_MEM_RESET_L

MEMVTT_EN

ISOLATE_CPU_MEM_L

32 OF 132 29 OF 105

7

26 28 67 72

10

29

6 7 8

18 24 25 30 31 32 48 49 50 54 55

73 88

104

6 7

17 19 20 22 23 24 25 46 48 56 71 72

73 83 86 91

100 102 104

7

10 13 15 73

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

7

26 28 67

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

IN

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

D

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8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Addr=0x98(WR)/0x99(RD)

8.59mV / step @ output

MEM B VREF CA

1.5V (DAC: 0x3A)

0.000V - 3.000V (0x00 - 0x74)

GPU Frame Buffer (1.8V, 70% VRef)

Page Notes

C

MEM A VREF CA

+61uA - -61uA (- = sourced)

MEM VREG

MEM B VREF DQ

0.75V (DAC: 0x3A)

0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced)

0.300V - 1.200V (+/- 450mV)

Addr=0x30(WR)/0x31(RD)

RST* on ’platform reset’ so that system

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

1.51mV / step @ output

0.000V - 3.300V (0x00 - 0xFF)

6

D

NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.

5

D

DAC Channel: PCA9557D Pin:

DAC range:

Nominal value

DAC step size:

VRef current:

Margined target:

MEM A VREF DQ

B 21

A

7.69mV / step @ output

C 3 4

- =PP3V3_S3_VREFMRGN

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SDA

Circuitry.

- =PPVTT_S3_DDR_BUF

Power aliases required by this page:

VREFMRGN - Stuffs VREF Margining

VREFMRGN_NOT - Bypasses VREF Margining

Signal aliases required by this page:

10mA max load

BOM options provided by this page:

- =I2C_PCA9557D_SCL

+6.0mA - -5.0mA (- = sourced)

1.056V - 1.442V (+/- 180mV)

(OD)

1.267V (DAC: 0x8B)

both at the same time!

a DAC output, cannot enable

NOTE: MEMVREG and FRAMEBUF share

1.000V - 2.000V (+/- 500mV)

Required zero ohm resistors when no VREF margining circuit stuffed

watchdog will disable margining.

67

10V

20% 402

CERM

0.1UF

VREFMRGN

C3302

1

2

33.2K

MF-LF

VREFMRGN

PLACE_NEAR=R7320.2:1mm

1/16W

1%

402

R3314

1 2

5% 1/16W

VREFMRGN

100K

MF-LF 402

R3313

1

2

VREFMRGN

402

MF-LF

1/16W

5%

100K

R3315

1

2

UCSP

MAX4253

VREFMRGN

U3302

C3

C2

C1

C4

B1

B4

VREFMRGN

UCSP

MAX4253

U3303

A3

A2

A1

A4

B1

B4

CRITICAL

VREFMRGN

UCSP

MAX4253

U3302

A3

A2

A1

A4

B1

B4

CRITICAL VREFMRGN MAX4253

UCSP

U3303

C3

C2

C1

C4

B1

B4

MAX4253

VREFMRGN

UCSP

U3304

A3

A2

A1

A4

B1

B4

CRITICAL

MAX4253

VREFMRGN

UCSP

U3304

C3

C2

C1

C4

B1

B4

200

VREFMRGN

MF-LF

402

1%

1/16W

PLACE_NEAR=J2900.126:2.54mm

R3309

1 2

VREFMRGN

1/16W

1%

402

MF-LF

200

PLACE_NEAR=J3100.126:2.54mm

R3311

1 2

OMIT

NONE

402

NONE

SHORT

R3318

1 2

NONE

OMIT

SHORT

NONE

402

NONE

R3319

1 2

25

PLACE_NEAR=J2900.1:2.54mm

VREFMRGN

1/16W

1%

402

MF-LF

200

R3303

1 2

1/16W

VREFMRGN

MF-LF

402

1%

PLACE_NEAR=R3303.2:1mm

133

R3304

1 2

PLACE_NEAR=J3100.1:2.54mm

1/16W

1%

402

MF-LF

200

VREFMRGN

R3305

1 2

402

MF-LF

1%

1/16W

VREFMRGN

PLACE_NEAR=R3305.2:1mm

133

R3306

1 2

VREFMRGN

0

5% 1/16W MF-LF 402

R3317

1

2

VREFMRGN

0

5%

1/16W

402

MF-LF

R3316

1

2

402

1/16W

100K

5%

VREFMRGN

MF-LF

R3302

1

2

1/16W

VREFMRGN

402

100K

5% MF-LF

R3301

1

2

1/16W

1%

402

MF-LF

VREFMRGN

PLACE_NEAR=R3309.2:1mm

133

R3310

1 2

100K

MF-LF

5%

402

VREFMRGN

1/16W

R3307

1

2

CRITICAL VREFMRGN

QFN

PCA9557

U3301

3 4 5

8

6 7 9 10 11 12 13 14

15

1 2

17

16

VREFMRGN

402

0.1UF

10V

CERM

20%

C3304

1

2

402

1/16W

VREFMRGN

1%

133

MF-LF

PLACE_NEAR=R3311.2:1mm

R3312

1 2

VREFMRGN

100K

MF-LF 402

5% 1/16W

R3308

1

2

6

16 23 26 28 30 32 41 48 62 89 95

6

16 23 26 28 30 32 41 48 62 89 95

VREFMRGN

MSOP

CRITICAL

DAC5574

U3300

9

10

3

6

7

8

1

2

4

5

6

16 23 26 28 30 32 41 48 62 89 95

6

16 23 26 28 30 32 41 48 62 89 95

VREFMRGN

0.1UF

CERM 402

20% 10V

C3301

1

2

VREFMRGN

2.2UF

CERM

402-LF

20%

6.3V

C3300

1

2

VREFMRGN

0.1UF

20% 10V

CERM

402

C3305

1

2

0.1UF

10V

20%

CERM

402

VREFMRGN

C3303

1

2

VREFMRGN_NOT

2

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

R3309,R3311

VREFMRGN_NOT

2

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

R3303,R3305

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=K91_YUN

SYNC_DATE=08/26/2010

VREFMRGN_MEMVREG_EN

VREFMRGN_FRAMEBUF_BUF_R

VREFMRGN_FRAMEBUF_BUF

PPVTTDDR_S3

PCA9557D_RESET_L

VREFMRGN_DQ_SODIMMB_BUF

VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

DDRREG_FB

VREFMRGN_SODIMMB_DQ

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PP0V75_S3_MEM_VREFDQ_A

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

VREFMRGN_DQ_SODIMMA_BUF

SMBUS_PCH_DATA

VREFMRGN_DQ_SODIMMA_EN

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_CTRL

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

VREFMRGN_MEMVREG_FBVREF_R

VREFMRGN_FRAMEBUF_EN

VREFMRGN_MEMVREG_BUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

PP3V3_S3

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_SODIMMS_CA

VREFMRGN_SODIMMA_DQ

VREFMRGN_CA_SODIMMB_BUF

33 OF 132 30 OF 105

6 7

67

9

26

9

28

26

28

6 7 8

18 24 25 29 31 32 48 49 50

54 55 73 88

104