Apple A1297 Schematics

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

Schematic / PCB #’s

SCHEM,BLACK_PEARL,MLB,K92

pre-evt 11/22/10 rev3.11.3

ALIASES RESOLVED

1 OF 105

1 OF 132

2009-05-19

SMC

07/12/2010

49

45

K91_BEN

Front Flex Support

04/26/2010

48

44

K17_MLB

PROJECT SPECIFIC CONNS

07/22/2010

47

43

K92_ERIC

External USB Connectors

08/24/2010

46

42

K92_ERIC

SATA Connectors

11/08/2010

45

41

K92_ERIC

FireWire Connector

07/22/2010

43

40

K91_MLB

FireWire Port & PHY Power

10/20/2010

42

39

K91_MLB

FireWire LLC/PHY (FW643)

10/20/2010

41

38

K91_MLB

Ethernet Connector

08/24/2010

40

37

K92_ERIC

ETHERNET PHY (CAESAR IV)

10/19/2010

39

36

K92_ERIC

T29 Power Support

11/09/2010

38

35

T29_REF

T29 Host (2 of 2)

11/09/2010

37

34

T29_REF

T29 Host (1 of 2)

11/09/2010

36

33

T29_REF

ExpressCard Connector

07/27/2010

35

32

K92_ERIC

X19/ALS/CAMERA CONNECTOR

10/21/2010

34

31

K91_MLB

FSB/DDR3/FRAMEBUF Vref Margining

08/26/2010

33

30

K91_YUN

CPU Memory S3 Support

04/26/2010

32

29

K17_MLB

DDR3 SO-DIMM Connector B

06/14/2010

31

28

K92_YUN

DDR3 Byte/Bit Swaps

05/14/2010

30

27

K92_YUN

DDR3 SO-DIMM Connector A

06/14/2010

29

26

K92_YUN

Chipset Support

06/29/2010

28

25

K91_MLB

USB HUBS

06/29/2010

26

24

K92_BEN

CPU & PCH XDP

10/17/2010

25

23

K91_MLB

PCH DECOUPLING

08/06/2010

24

22

K91_YUN

PCH GROUNDS

05/20/2010

23

21

K92_YUN

PCH POWER

07/09/2010

22

20

K91_MLB

PCH MISC

10/20/2010

21

19

K91_MLB

PCH PCI/FLASHCACHE/USB

10/20/2010

20

18

K91_MLB

PCH DMI/FDI/GRAPHICS

10/17/2010

19

17

K91_MLB

PCH SATA/PCIE/CLK/LPC/SPI

10/19/2010

18

16

K91_MLB

CPU DECOUPLING-II

07/21/2010

17

15

K91_MLB

CPU DECOUPLING-I

07/21/2010

16

14

K91_MLB

CPU POWER AND GND

04/26/2010

14

13

K60_MLB

CPU POWER

07/16/2010

13

12

K91_MLB

CPU DDR3 INTERFACES

04/26/2010

12

11

K60_MLB

CPU CLOCK/MISC/JTAG

07/16/2010

11

10

K91_MLB

CPU DMI/PEG/FDI/RSVD

04/26/2010

10

9

K60_MLB

Signal Aliases

04/26/2010

9

8

K17_MLB

Power Aliases

04/26/2010

8

7

K17_MLB

Functional / ICT Test

04/26/2010

7

6

K17_MLB

BOM Configuration

04/26/2010

5

K17_MLB

Revision History

04/26/2010

4

K17_MLB

Revision History

04/26/2010

3

K17_MLB

System Block Diagram

04/26/2010

2

K60_MLB

90

K17_MLB

04/26/2010

98

LCD Backlight Support

89

K92_DINESH

09/07/2010

97

LCD Backlight Driver (LP8545)

88

K92_YUAN

07/28/2010

96

Graphics MUX (GMUX)

87

K91_CHANG

07/21/2010

95

1V0 GPU / 1V5 FB Power Supply

86

K91_MLB

10/22/2010

94

DisplayPort/T29 A Connector

85

K91_MLB

10/22/2010

93

DisplayPort/T29 A MUXing

84

K92_YUN

06/25/2010

92

Muxed Graphics Support

83

K17_MLB

04/26/2010

90

LVDS Display Connector

82

K91_CHANG

07/21/2010

89

GPU (Whistler) CORE SUPPLY

81

K92_BEN

06/01/2010

88

Whistler DP PWR/GNDs

80

K91_MLB

07/17/2010

87

Whistler GPIOs & STRAPs

79

K92_SUMA

10/21/2010

86

Whistler LVDS/DP/GPIO

78

K91_YUN

08/23/2010

85

GDDR5 Frame Buffer B

77

K91_YUN

08/23/2010

84

GDDR5 Frame Buffer A

76

K18_MLB

04/27/2010

82

Whistler FRAME BUFFER I/F

75

K92_BEN

06/03/2010

81

Whistler CORE/FB POWER

74

K91_MLB

10/19/2010

80

Whistler PCI-E

73

K92_YUAN

07/22/2010

79

Power Control 1/ENABLE

72

K91_MLB

10/18/2010

78

Power FETs

71

K91_CHANG

07/21/2010

77

Misc Power Supplies

70

K92_ERIC

09/23/2010

76

CPU VCCIO (1.05V) Power Supply

69

K92_ERIC

09/27/2010

75

CPU IMVP7 & AXG VCore Output

68

K92_ERIC

11/09/2010

74

CPU IMVP7 & AXG VCore Regulator

67

K91_CHANG

07/21/2010

73

1.5V DDR3 Supply

66

K92_ERIC

08/30/2010

72

5V / 3.3V Power Supply

65

K91_CHANG

07/21/2010

71

System Agent Supply

64

K91_CHANG

07/21/2010

70

PBus Supply & Battery Charger

63

K92_CHANG

06/28/2010

69

DC-In & Battery Connectors

62

K92_KAVITHA

11/22/2010

68

AUDIO: JACK TRANSLATORS

61

K92_KAVITHA

11/02/2010

67

AUDIO: JACKS

60

K92_KAVITHA

10/22/2010

66

AUDIO:SPEAKER AMP

59

K92_KAVITHA

10/22/2010

65

AUDIO: HEADPHONE OUT

58

K92_AUDIO

06/16/2010

63

AUDIO: LINE IN

57

K92_KAVITHA

07/30/2010

62

AUDIO:CODEC

56

K92_BEN

05/27/2010

61

SPI ROM

55

K92_DINESH

06/02/2010

59

Digital Accelerometer

54

K92_ERIC

07/27/2010

58

WELLSPRING 2

53

K92_ERIC

10/11/2010

57

WELLSPRING 1

52

K17_MLB

04/26/2010

56

Fan Connectors

51

K92_DINESH

09/24/2010

55

Thermal Sensors

50

K92_DINESH

10/29/2010

54

High Side and CPU/AXG Current Sensing

49

K92_DINESH

09/24/2010

53

Voltage & Load Side Current Sensing

48

K17_MLB

04/26/2010

52

K92 SMBus Connections

47

K91_YUN

09/23/2010

51

LPC+SPI Debug Connector

08/23/2010

Power Supplies BIST

K92_DINESH

132

105

07/28/2010

DEBUG SENSORS AND ADC 2

K92_DINESH

131

104

09/07/2010

DEBUG SENSORS AND ADC

K92_DINESH

130

103

04/27/2010

PCH Power Aliases

K17_MLB

121

102

05/14/2010

PCB Rule Definitions

K17_MLB

109

101

07/22/2010

Project Specific Constraints

K91_MLB

108

100

07/21/2010

GPU (Whistler) CONSTRAINTS

K91_MLB

107

99

05/14/2010

SMC Constraints

K17_MLB

106

98

10/20/2010

T29 Constraints

T29_REF

105

97

07/22/2010

Ethernet/FW Constraints

K91_MLB

104

96

07/22/2010

PCH Constraints 2

K91_MLB

103

95

06/25/2010

PCH Constraints 1

K92_YUN

102

94

05/14/2010

Memory Constraints

K17_MLB

101

93

07/22/2010

CPU Constraints

K91_MLB

100

92

SCHEM,MLB,K92

PCBF,BLACK_PEARL,MLB,K92

820-2914 CRITICAL

1 PCB

07/30/2010

Power Sequencing EG/PCH S0

K92_YUAN

99

91

CRITICAL

SCHEM,BLACK_PEARL,MLB,K92

SCH1

051-8618

LAST_MODIFIED=Tue Nov 23 20:44:38 2010

TITLE=MLB ABBREV=DRAWING

Contents

(.csa)

Date

Page Sync

Table of Contents

04/27/2010

1

K17_MLB

Page Sync

Contents

Date

(.csa)

46

K91_BEN

07/12/2010

50

SMC Support

Sync

(.csa)

Contents

Date

Page

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PERN4PERN1PERN3PERN2

U6610,6620,6630,6640,6650

LINE OUT

LINE IN

PG 73

USX2061

USBDN1

USBDN2

USBDN3

USBDN4

EXPRESSCARD

PG 41

USB

EXTERNAL

J4600,J4610,4720

EXTA

EXTC EXTB

TRACKPAD/

KEYBOARD

PG 73

USX2061

USBDN1

USBDN2

USBDN3

USBDN4

Misc

CS4206ACNZC

PG 17

PG 83

U9600

J9000

XP25-5

GMUX

CONN

LVDS

PG 87

J9400

DISPLAY PORT

U9320

CBTL06141EE

CONN

Mini PCI-E

AIRPORT

PG 31

J3401

U4100

J4310

FW643

FW-800

Conn

PG 40

PG 38

U3900

J4000

PG 37

Conn

E-NET

PG 36

E-NET

GB

BCM57765

PG 16

PEG

PG 16

PCI-E

PG 85

PG 84

J4501

Conn

SATA

ODD

P8 41

J4500

SATA

HD

Conn

CK505

P8 24

SATA 2.0 /3GHZ.

SATA 3.0/ 6GHZ.

PG 18

JTAG

PG 18

PCI

TMDS OUT

DVI OUT

LVDS OUT

HDMI OUT

RGB OUT

DP OUT

SATA

PG 16

CLK

BUFFER

INTEL

U1800

COUGAR POINT

J3500

EXPRESSCARD

PG 32

CONN

PG 16

SMB

IHDA

PG 16

HEADPHONE

U6500

Amp

Conns

Audio

PG 61

J6780,6781,6782,6700,6750

U6200

DIMM’s

Audio

EXPRESSCARD

PG 57

Codec

SMB

PG 48

(UP TO 14 DEVICES)

PG 18

USB

CTRL

0 21 3 7654 8

121110

9

13

LPC

SPI

PG 16

PWR

PG 16

PG 19

U3600

J3401

PG 31

Bluetooth

U6100

SPI

Boot ROM

PG 58

B,0 BSB

SMC

PG 54

ADC

U4900

Speaker

CONN

J5713/J5800

PG 60

Amps

J3402

PG 31

CAMERA

IR

PG 44

J4800

U3600

PG 53/54

J3500

PG 32

Fan

Prt

Ser

PG 47

Port80,serial

J5650,5660

POWER SENSE

FAN CONN AND CONTROL

J5100

PG 53

PG 52

PG 51

LPC Conn

U4900

J6900/J6950

DC/BATT

TEMP SENSOR

PG 63

POWER SUPPLY

U2700

CLOCK

PG 74

U8000

WHISTLBR

PG 19

GPIO

FDI

PG 17

PG 9-13

SANDYBRIDGE

INTEL CPU

PG 17

DMI

RTC

DDR3 /1333MHZ

2 UDIMMs

PG 16

DIMM

J2900

PG 26,28

PG 23

J2500

XDP CONN

SYNC_MASTER=K60_MLB

System Block Diagram

SYNC_DATE=04/26/2010

2 OF 132 2 OF 105

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(6 TO 8.4V)

F6905

SMC_PM_G2_EN

Q9806

VREG5

DELAY

RC

DELAY

RC

DELAY

RC

CPUVTTS0_EN

P1V5CPU_EN

P1V8S0_EN

P1V2S0_EN

R7978

U1800

(PAGE 16-21)

SLP_S4#(H7)

SLP_S3#(P12)

DELAY

RC

(PAGE 45)

P60

(PAGE 87)

SMC

U4900

PL32A

SLP_S5#(E4)

COUGAR_POINT

DELAY

RC

PB18A

XP25-5

EG_RAIL4_EN

U9600

GMUX

PB16B

PB17B

PB17A

2S4P

J6950

EG_RAIL2_EN

EG_RAIL1_EN

EG_RAIL3_EN

PPVBATT_G3H_CONN

DDRREG_EN

PM_SLP_S3_L

PM_SLP_S3_L_R

P5VS3_EN

P3V3S3_EN

PM_SLP_S4_L

PM_SLP_S5_L

PM_ALL_GPU_PGOOD

PBUSVSENS_EN

P3V3S0_EN

P5VS0_EN

&&

LCD_BKLT_EN

SMC_ADAPTER_EN&&PM_SLP_S3_L

BKLT_PLT_RST_L

Q4260

BKLT_EN

ENA

VIN

U9701

(PAGE 88)

LP8545SQX

(PAGE 71)

U7790

VOUT

LTC1872

VIN

VOUT

P3V3S5_EN

P3V3GPU_EN GPUVCORE_EN

CHGR_BGATE

Q7055

P1V0GPU_EN

P1V5FB_EN

PPVBAT_G3H_CHGR_R

(PAGE 86)

1.103V(L/H)

EN1

1.8V(R/H)

ISL6236

EN2

U9500

VIN

P5VS3_EN

VOUT1

VOUT2

POK2

POK1

P3V3S5_EN

EN2

EN1

P1V5FB_PGOOD

A

PP1V0_S0GPU

R5410

P1V0GPU_PGOOD

(PAGE 64)

ADAPTER

IN

AC

J6900

DCIN(16.5V)

6A FUSE

SMC_DCIN_ISENSE

K92 POWER SYSTEM ARCHITECTURE

A

VIN

R7020

PPDCIN_G3H_OR_PBUS_R

BATTERY CHARGER

PBUS SUPPLY/

U7000

ISL6259HRTZ

VOUT

R6990

SMC_BATT_ISENSE

PPVBAT_G3H_CHGR_REG

R7050

A

F7041

8A FUSE

F7040

PGOOD1

PP1V5R1V35_GPU_FB_ISNS

D6990

TPS51980

P5VS3_PGOOD

SMC_GPU_1V5_ISENSE

PPVOUT_S0_LCDBKLT

(PAGE 66)

P1V8_S0_EN

PP10V_FW

U7201

PGOOD2

P3V3S5_PGOOD

Q7830

Q7810

Q7870

P3V3S0_EN

P3V3GPU_EN

P3V3S3_EN

PP3V3_S0_FET

P1V2ENET_EN

PP3V3_S0_GPU

PP3V3_S3

EN

(PAGE 71)

U7760

VOUT

ISL8014A

VIN

U7720

ISL8014

(PAGE 70)

PP3V3_FW_FET

PGOOD

VOUT

P1V8S0_PGOOD

PP1V2_ENET

PP1V8_S0

Q7850

TPS22924

U4201

(PAGE 39)

P1V5_S0_EN

PP3V3_FW_FWPHY

FW_PWR_EN

EN

VIN

Q7922

(PAGE 71)

U7710

ISL8009B

OUT

3.3V

VIN

5V

(R/H)

(L/H)

VOUT1

VOUT2

PP5V_S5

P1V5CPU_EN

RD220

A

MEMVTT_EN

ON

PP5V_S3

(PAGE 54)

SLG5AP020

U7801

PP3V3_S5

VOUT

S3

S5

DDRREG_EN

SMC_CPU_HI_ISENSE

PP5V_S3

VIN

R5388

1.5V

(PAGE 67)

U7300

TPS51916

0.75V

PP1V5_S3RS0

A

CPUIMVP7_VR_ON

PP5V_S3

Q7860

PGOOD

VOUT2

PP5V_S0_FET

PPVTT_S0_DDR_LDO

P5VS0_EN

DDRREG_PGOOD

VIN

U5805

VOUT1

A

VLDOIN

VR_ON

VIN

PPDDR_S3_REG

ISL95831

(PAGE 68)

CPU VCORE

U7400

PGOOD

VOUT

PP1V2_S0

P1V2GMUX_EN

PM_SLP_S3_L&&WOL_EN||SMC_ADAPTER_EN

PP3V3_ENET

PP3V3_S0

PP1V5_S0

A

SMC_DDR_ISENSE

TPS61045

VOUT

(PAGE 54)

R7350/U5440

SMC_CPU_ISENSE

PP1V05_S0_VMON

PP1V5_S0_VMON

PP3V3_S0_VMON

V2MON

V3MON

V4MON

TRST = 200mS

(PAGE 73)

PG

RST*

PP3V3_S0

U7971

S0PGOOD_PWROK

VCC

P5VS3_PGOOD

P1V8S0_PGOOD

ISL88042IRTJJZ

P1V2ENET_PGOOD

PP18V5_S3

U6201

(PAGE 57)

MAX8840

VOUTEN

VIN

PM_ALL_GPU_PGOOD

U7980

PP1V5_S3

V

PPVCORE_S0_CPU

SMC_CPU_VSENSE

CPUIMVP7_PGOOD

PP4V5_AUDIO_ANALOG

(PAGE 82)

PPBUS_G3H

SMC_PBUS_VSENSE

PP5V_S3_GFXIMVP6_VDD

GPUVCORE_EN

VR_ON

VDD

V

Q5315

GPU VCORE

ISL6263C

VIN

U8900

PGOOD

VOUT

PM6640

3.425V G3HOT

(PAGE 63)

U6990

ENABLE

A

SMC_GPU_ISENSE

U5410

GPUVCORE_PGOOD

V

PP3V42_G3H

PPVCORE_GPU

SMC_GPU_VSENSE

(PAGE 46)

CPUVTTS0_EN

U5000

PP5V_S0_CPUVTTS0

EN

VIN

NCP303LSN

SMC PWRGD

SMC_RESET_L

ISL95870

(PAGE 70)

U7600

1.05V

VIN

PP3V3_S0_PWRCTL

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_S3_L

SMC_ONOFF_L

ALL_SYS_PWRGD

RSMRST_PWRGD

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

(PAGE 45)

U4900

H8S2117

PWRGD(P12)

PWR_BUTTON(P90)

RSMRST_IN(P13)

CPU

SMC

U1000

(PAGE 9-14)

U2850

PM_PCH_PWRGD

U1800

PS_PWRGD

PGOOD

VOUT

SMC AVREF SUPPLY

REF3333

(PAGE 46)

VOUT

CPUVTTS0_PGOOD

R7640

A

99ms DLY

IMVP_VR_ON(P16)

SMC_CPU_FSB_ISENSE

PP3V3_S5_AVREF_SMC

PPCPUVTT_S0

SMC_TPAD_RST_L

COUGAR_POINT

SMC_ONOFF_L

SYS_RERST#

SYSRST(PA2)

RESET*

P17(BTN_OUT)

RES*

PWRBTN#

DRAMPWROK

PLTRST#

PROCPWRGD

RSMRST#

ACPRESENT

(P64)

RSMRST_OUT(P15)

(PAGE 16-21)

SM_DRAMPWROK

VCCCPUPWRGD

SMC_RESET_L

SMC_ADAPTER_EN

IMVP_VR_ON

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PM_MEM_PWRGD

CPU_PWRGD

PLT_RERST_L

PM_PWRBTN_L

(PAGE 39)

EN

U4202

FW_PWR_EN

VIN

TPS22924

U5001

PP3V42_G3H

PPCPUVCCIO_S3

VOUT

PP1V0_FW

SYNC_DATE=04/26/2010

Revision History

SYNC_MASTER=K17_MLB

3 OF 132 3 OF 105

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROTO2/EVT 11/15/10 rev3.6 for board 820-2914-06.brd release PROTO2/EVT 11/19/10 rev3.7 for board 820-2914-07.brd release

EVT 11/22/10 rev3.9 for board 820-2914-07.brd release

PROTO2/EVT 11/11/10 rev3.0 for board 820-2914-05.brd release

SYNC_DATE=04/26/2010

Revision History

SYNC_MASTER=K17_MLB

4 OF 132 4 OF 105

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Ethernet

BOM Variants

Bar Code Labels / EEEE #’s

K92 BOM GROUPS

Programmed Parts-All Builds

SMC

Alternate Parts

(U5850)

(L7630) (U9390) (Q3200, etc)

(Q3888,Q9430)

PSOC

Module Parts

EFI

GPUROM will NOSUFFED @EVT

SMC_PROG:EVT,BOOTROM_PROG:EVT,ENETROM_PROG:B0_NOSD,TPAD_PROG:EVT,T29ROM:PROG,GMUX_PROG,T29MCU:PROG

K92_PROGPARTS

SNB_CPT_XDP,LPCPLUS:YES,VREFMRGN_NOT

K92_DEVEL:PVT

GPUVID_1P11V,HUB1_2NONREM,HUB2_2NONREM,KB_BL,ENET:B0,T29BST:Y,T29:YES,T29_DP_HPD:ALL_OR

K92_COMMON2

CPUMEM_S0,EXT_HP_AMP,SMC_DEBUG_YES,USBHUB_2514B

K92_COMMON1

SNB_CPT_XDP,DEBUG_ADC,LPCPLUS:YES,VREFMRGN,GMUX_JTAG_CONN,S0PGOOD_ISL,BMON:ENG,CPURIPPLE_ENG,IMVPISNS_ENG,SDRVI2C:MCU

K92_DEVEL:ENG

085-1898

K92_DEVEL:ENG

K92 MLB DEVELOPMENT BOM

639-1465

K92_COMMON,CPU:2_3GHZ,FB_1G_HYNIX,VRAM_HYNIX,EEEE_DG61

PCBA,MLB,CFG4,K92

U6100

1

64 MBIT SPI SERIAL DUAL I/O FLASH

335S0740 CRITICAL

BOOTROM_BLANK

U6100

1

IC,EFI,ROM,PROTO, K90/K90I/K91/K91F/K92

341S2893 CRITICAL

BOOTROM_PROG:PROTO0

341S2991 CRITICAL

U6100

IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92

BOOTROM_PROG:PROTO2

1

IC,PROGRAMMED MCU,32B,LPC1112A,16KB/2KB,HVQFN25

U9330

CRITICAL

1

341S2939

T29MCU:PROG

IC,MCU,32B,LPC1112A,16KB/2KB,HVQFN25

U9330

CRITICAL

1

337S3997

T29MCU:BLANK

IC,GMUX,K92

GMUX_PROG

1

CRITICAL

U9600

341S2996

IC,SGRAM,GDDR5,64MX32,3.6GBPS,C-DIE,HF

333S0571

U8400,U8450,U8500,U8550

4

FB_1G_SAMSUNG

CRITICAL

IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN 8X8

1

U3900

343S0494 CRITICAL

ENET:A0

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

1

U4100

338S0753 CRITICAL

IC,SDRAM,GDDR5,32MX32,1.25GHz,A-DIE1.35V

U8400,U8450,U8500,U8550

4

FB_512_HYNIX

333S0564 CRITICAL

IC,GPU,AMD,WHISTLER,962FCBGA,40NM,ES

U8000

337S3936

1

CRITICAL

U3600

338S0945

T29:YES

1

CRITICAL

Light Ridge,S LHAJ,FCBGA,15x15mmm

1

353S3055

IC, P13VEDP212,x2 DISPLAYPORT 2:1 MUX, QFN

U9390

CRITICAL

341S2899

IC,T29 EEPROM,K92

CRITICAL

1

T29ROM:PROG

U3690

335S0724

1

CRITICAL

GPUROM:BLANK

IC,GPU ROM,K91/F,K92

U8701

IC,GPU ROM,K91/F,K92

U8701

1

CRITICAL341S2957

GPUROM:PROG

CRITICAL

IC,PLD,LATTICE,LFXP2-5E-5,132 BALL CSBGA

336S0042

1

GMUX_BLANK

U9600

343S0534

U3900

1

CRITICAL

ENET:B0

IC,ASIC,GBIT ETHNET&SD CTRLR,686 QFN 8X8

IC,SMC,DEVELOPMENT-EVT,K92

1

CRITICAL

U4900

341S2862

SMC_PROG:EVT

LBL,P/N LABEL,PCB,28MM X 6 MM

1

EEEE_DG62

CRITICAL826-4393

[EEEE_DG62]

826-4393 CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DG60]

EEEE_DG60

826-4393

EEEE_DG5Y

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE_DG5Y]

337S4032

IC,CPU,SNB,SR00W,PRQ,D2,2.2,45W,4+2,1.30,6M,BGA

CPU:2_2GHZ

CRITICAL

1

U1000

4

333S0572 CRITICAL

IC,SGRAM,GDDR5,64MX32,3.6GBPS,M-DIE,HF

U8400,U8450,U8500,U8550

FB_1G_HYNIX

IC,PCH,COUGARPOINT SLH9D,PRQ,BD82HM63

U1800

CRITICAL

1

337S4029

SMC_BLANK

U4900

CRITICAL338S0895

1

IC,SMC,HS8/2117,9MMX9MM,TLP

ALL

Silver alt to Gold short pogo pins

870-1699870-2015

U3990

341S2685

IC,ENET ROM,PROTO1,K92

CRITICAL

1

ENETROM_PROG:A0_SD

155S0329155S0457

MAG LAYERS ALT TO MURATAALL

ALL

516S0806516S0805

FOXCONN ALT TO MOLEX

353S2805 353S2603

ALL

Fairchild 8’ alt to 6’wafer

127S0060

Rohm alt to Kemet

ALL

127S0111

157S0055157S0058

ALL

Delta alt to TDK Magnetics

341S2934

BOOTROM_PROG:PROTO1

CRITICAL

1

U6100

IC,EFI,ROM,PROTO1, K90/K90I/K91/K91F/K92

U4900

1

CRITICAL341S2865

IC,SMC,DEVELOPMENT-DVT,K92

SMC_PROG:DVT

Pericom alt to NXP DP Mux

ALL

353S3151353S3055

152S0796152S0915

MAG LAYERS ALT TO CYNTECALL

IC,EEPROM,SERIAL,8KB,SOIC

CRITICAL

1

335S0777

T29ROM:BLANK

U3690

152S0518

MAG LAYERS ALT TO CYNTEC

152S0896

ALL

Silver alt to Gold tall pogo pins

870-1939 870-1698

ALL

341S2384

IR,ENCORE II, CY7C63833-LFXC

CRITICAL

1

U4800

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

[EEEE_DG61]

EEEE_DG61

IC,SGRAM,GDDR5,32MX32.1.25GHz,E-DIE,HF

FB_512_SAMSUNG

4

U8400,U8450,U8500,U8550

333S0543 CRITICAL

IC,CPU,SNB,SR00U,PRQ.D2,2.3,45W,4+2,1.30,8M,BGA

1

337S4033

U1000

CRITICAL

CPU:2_3GHZ

1

SMC_PROG:PROTO1

341S2855

U4900

CRITICAL

IC,SMC,DEVELOPMENT-PROTO1,K92

376S0613

ALL

radar8515240 Toshiba FET

376S0855

152S0905

Cyntec (used on K90i) as alt

ALL

152S1307

ST Micro alt to LT

ALL

353S1658353S3085

K92_COMMON

ALTERNATE,COMMON,K92_COMMON1,K92_COMMON2,K92_PROGPARTS

SNB_CPT_XDP

XDP,XDP_CONN,XDP_CPU_BPM,XDP_PCH

K92_PVT

VREFMRGN_NOT,XDP,XDP_CPU_BPM,BMON:PROD

639-1466

K92_COMMON,CPU:2_3GHZ,FB_1G_SAMSUNG,EEEE_DG62

PCBA,MLB,CFG3,K92

639-1464

PCBA,MLB,CFG2,K92

K92_COMMON,CPU:2_2GHZ,FB_1G_HYNIX,VRAM_HYNIX,EEEE_DG60

PCBA,MLB,K92639-1303

K92_COMMON,CPU:2_2GHZ,FB_1G_SAMSUNG,EEEE_DG5Y

SYNC_DATE=04/26/2010

SYNC_MASTER=K17_MLB

BOM Configuration

ENETROM_PROG:B0_NOSD

CRITICAL

U3990

IC,ENET ROM, PROTO2, EVT,DVT,PVT,K92

1

341S3027

341S3024

1

U5701

TPAD_PROG:EVT

CRITICAL

IC,TP PSOC,proto1,EVT,K90,K90i,K91,K91F,K92T

1

341S3024 CRITICAL

U5701

TPAD_PROG:DVTPVT

IC,TP PSOC,proto1,DVT,pVT,K90,K90i,K91,K91F,K92T

1

TPAD_PROG:PROTO2

341S3024

U5701

CRITICAL

IC,TP PSOC,proto2,K90,K90i,K91,K91F,K92T

CRITICAL341S2902

U5701

IC,TP PSOC,PROTO,K90,K90i,K91,K91F,K92

TPAD_PROG:PROTO1

1

335S0539

U3990

ENETROM_BLANK

CRITICAL

1

IC,FLASH,SERIAL,SPI,1MBIT,2V7,8P,SOIC

IC,EFI,ROM,PVT, K90/K90I/K91/K91F/K92

1

U6100

CRITICAL

BOOTROM_PROG:PVT

341S2896

1

341S2895 CRITICAL

U6100

IC,EFI,ROM,DVT, K90/K90I/K91/K91F/K92

BOOTROM_PROG:DVT

341S2894

U6100

CRITICAL

IC,EFI,ROM,EVT, K90/K90I/K91/K91F/K92

BOOTROM_PROG:EVT

1

IC,SMC,DEVELOPMENT-PVT,K92

U4900

341S2868

1

CRITICAL

SMC_PROG:PVT

CRITICAL

1

341S2995

IC,SMC,DEVELOPMENT-PROTO2,K92

U4900

SMC_PROG:PROTO2

SMC_PROG:PROTO0

CRITICAL

IC,SMC,DEVELOPMENT-PROTO,K92

1

341S2855

U4900

ALL

add NEC part as 2nd source

128S0264128S0327

add Murata part as 2nd source

138S0676

ALL

138S0691

add ROHM part as 2nd source

376S0972

ALL

376S0612

add new part as 2nd source

376S0859376S0977

ALL

138S0681 138S0638

ALL

add new part as 2nd source

5 OF 132 5 OF 105

NBC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

2 TPs

J5713 (KEY BOARD CONN)

2 TPs

J6781 (LEFT SPEAKER)

NO_TEST=TRUE

2 TP needed

J5800 (IPD FLEX CONN)

J3500 (EXPRESS CARD CONN)

2 TP needed

6 TP needed

2 TPs

FUNC_TEST

4 TPs

NC NO_TESTs

NO_TEST

J4501 (SATA HDD CONN)

3 TPs

J5815 (KBD BACKLIGHT CONN)

3 TPs

4 TPs

J6900 (DC POWER CONN)

J6995 (BAT LED CONN)

3 TPs

4 TPs

J4500 (SATA ODD CONN)

5 TPs

J6780 (MIC FR CONN)

2 TPs 2 TPs 2 TPs

J4800 (FRONT CABLE CONN)

5 TPs

J6950 (MAIN BATT CONN)

FUNC_TEST

J6783 (MIC BK CONN)

J5660 (RIGHT FAN CONN)

2 TPs

NC NO_TESTs

2 TPs

3 TP needed

J3401(AIRPORT/BT CONN)

2 TPs

J6782 (RIGHT & SUB SPEAKER)

J9000 (LVDS CONN)

POWER RAILS

has TP

NO_TEST

NC NO_TESTs

NO_TEST=TRUE

2 TPS

5 TPs

FUNC_TEST

J5650 (LEFT FAN CONN)

Functional Test Points

J3402 (CAMERA/ALS CONN)

I1000

I1001 I1002

I1003

I1004

I1005

I1006

I1007

I1008

I1009

I1010

I1011

I1012

I1013

I1014

I1015 I1016

I1017

I1018 I1019

I1020

I1021

I1022

I1024

I1025

I1026

I1027

I1028

I1029

I1031

I1032

I1033

I1050

I1051

I1052

I1053

I1054

I1055

I1056

I1057

I1058

I1059

I1060

I1061

I1062

I1063

I1064

I1065

I1066

I1067

I1068 I1069

I1070

I1071

I1072

I1073

I1074

I1075

I1076 I1077

I1078

I1079

I1080

I1081

I1082 I1083

I1084

I1085 I1086

I1087

I1088

I1089

I1090 I1091

I1092 I1093

I1094

I1095

I1096

I1097

I1098

I1099 I1100

I1101

I1102

I1103

I1104

I1105

I1106

I1107

I1108

I1109

I1110 I1111

I1112

I1113 I1114

I1115

I1116

I1117

I1131

I1132

I1134

I1135

I1136

I1137

I1140

I1141

I1142

I1143

I1145

I1146

I1148

I1149

I1150

I1151

I1152

I1273

I1436

I1437

I1438

I1439

I1440

I1441

I1442

I1443

I1444

I1445

I1446

I1447

I1448

I1449

I1450

I1451

I1472

I1473 I1474

I1475 I1476

I1478

I1479

I1484 I1485

I1486

I1488

I1490

I1491

I1492

I1539

I1540

I1541 I1542

I1543 I1544

I1545

I1546

I1547

I1548

I1549 I1550

I1561

I1599 I1600

I1601

I1602

I557

I558

I559

I985

I986

I987

I988

I989

I990

I991

I992

I993

I994

I995 I996

I997 I998

SYNC_DATE=04/26/2010

Functional / ICT Test

SYNC_MASTER=K17_MLB

LVDS_CONN_A_CLK_F_P

TRUE

LVDS_DDC_DATA

TRUE

SATA_HDD_D2R_RDRVR_IN_P

TRUE

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_D2R_C_P

TRUE

FAN_LT_PWM

TRUE

FAN_LT_TACH PP5V_S0

TRUE

PP1V8_S0

TRUE

SATA_HDD_D2R_RDRVR_IN_N

MAKE_BASE=TRUE

NC_SDVO_TVCLKINP

TRUE

NC_SDVO_STALLN

TRUE MAKE_BASE=TRUE

TRUE

PP3V3_S0

SMC_RX_L

TRUE

SMC_TCK

TRUE

WS_KBD5

NC_BCM57765_TRAFFICLED_L

SYS_LED_ANODE_R

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_AD<0..3>

TRUE

SPI_ALT_MOSI

TRUE

SPI_ALT_MISO

TRUE

SATA_HDD_D2R_RDRVR_OUT_N

TRUE

SATA_HDD_D2R_RDRVR_OUT_P

LPC_FRAME_L

TRUE

PM_CLKRUN_L

TRUE

SMC_TMS

TRUE

SMC_TRST_L

TRUE

SMC_TX_L

TRUE

SPI_ALT_CLK

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

SMC_MD1

SPIROM_USE_MLB

TRUE

SPI_ALT_CS_L

TRUE

TP_DVPCLK

NC_FW0_TPBP

NC_FW2_TPBP

TP_FW643_AVREG

MAKE_BASE=TRUE

NC_FW643_AVREG NC_FW643_TDI

MAKE_BASE=TRUE

NC_FW0_TPAP

TRUE

DMI_N2S_N<1>

TRUE

SPKRAMP_BR_OUT_N

SPKRAMP_LFE_OUT_N

TRUE

NC_FW2_TPBN

NC_FW2_TPAN

NC_DP_IG_C_HPD

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_DP_IG_C_CTRL_CLK

MAKE_BASE=TRUE

NC_DP_IG_C_MLN<3..0>

TRUE

NC_DP_IG_D_MLP<3..0>

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_MLN<3..0>

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_CTRL_DATA

NC_DP_IG_D_HPD

NC_DP_IG_C_AUXN

NC_DP_IG_C_AUXP

NC_DP_IG_C_MLP<3..0>

MAKE_BASE=TRUE

TRUE

NC_FW0_TPBN

TP_DC_TEST_A4

TRUE

TP_DC_TEST_D1

TRUE TRUE

TP_EDP_TX_P<3..0>

TRUE

TP_T29_SENSOR_ALERT

TRUE

DMI_S2N_P<1..0>

TRUE

DMI_N2S_P<1>

TRUE

DMI_N2S_N<3>

TRUE

DMI_N2S_P<3>

TRUE

DMI_S2N_N<1..0>

TRUE

TP_DVPDATA<23..0>

TRUE

TP_GPU_JTAG_TRST_L

TRUE

TP_DVPCNTL<2..0>

TRUE

ISSP_SDATA_P1_0

MAKE_BASE=TRUE

NC_SDVO_TVCLKINN

TRUE

SATA_HDD_R2D_RDRVR_OUT_P

TRUE

SATA_HDD_R2D_RDRVR_IN_N

TRUE TRUE

SATA_HDD_R2D_RDRVR_IN_P

TRUE

SATA_HDD_R2D_C_N

TRUE

SATA_HDD_R2D_C_P

TRUE

SATA_HDD_D2R_N

TRUE

SATA_HDD_D2R_P

NC_SATA_SSD2_R2D_CP

TRUE

SATA_HDD_R2D_UF_P

TRUE

SATA_HDD_R2D_UF_N

NC_SATA_SSD2_R2D_CN

NC_SATA_SSD2_D2RN NC_SATA_SSD2_D2RP

NC_SATA_D_R2D_CN

NC_SATA_D_D2RN NC_SATA_D_D2RP

TRUE

SATA_HDD_R2D_RC_UF_N SATA_HDD_R2D_RC_UF_P

TRUE

SATA_HDD_R2D_UF_N

TRUE

SATA_HDD_R2D_UF_P

TRUE

SATA_HDD_R2D_RDRVR_OUT_N

TRUE

T29_A_BIAS_R2D_P0

TRUE

T29_A_BIAS_R2D_N1

TRUE

T29_A_BIAS_R2D_P1

TRUE

T29_A_BIAS_R2D_N0

TRUE

DP_A_BIAS_N_0

TRUE TRUE

DP_A_BIAS_P_0

TRUE

DP_A_BIAS_N_2

TRUE

DP_A_BIAS_P_2

NC_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4P

TP_NV_WE_CK_L<1..0>

T29_D2R1_BIAS

TRUE

DP_EXTA_ML_P<3..0>

TRUE

TP_NV_DQS<1..0>

PCIE_AP_R2D_P

TRUE

WS_KBD20

TRUE

WS_KBD23

WS_KBD18

TRUE

WS_KBD14

TRUE

PCIE_AP_R2D_N

TRUE

WS_KBD10

TRUE

WS_LEFT_SHIFT_KBD

WS_CONTROL_KBD

TRUE

SATA_ODD_D2R_UF_P

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4P

PP1V8_S0GPU

TRUE

PPVCORE_GPU

TRUE

PP1V8_S0GPU_ISNS_R

TRUE

PP3V3_S0GPU

TRUE

PPVP_FW

TRUE

PPVTTDDR_S3

TRUE

PP3V3_S3

EXCARD_CPPE_L

TRUE

SPKRAMP_BL_OUT_N

TRUE

NC_PCI_CLK33M_OUT3

TRUE

TP_T29_PCIE_RESET0_L

TRUE

T29DPA_D2R1_AUXCH_P

NC_PCI_PAR

T29DPA_ML_P<3..0>

TRUE

WS_KBD16_NUM

TRUE

WS_KBD15_CAP

NC_CE_L_MS_INS_L NC_CE_L_MS_INS_L

MAKE_BASE=TRUE

TRUE

NC_PCH_TP2

MAKE_BASE=TRUE

TRUE

NC_GPU_BUFRST_L

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_CTRL_CLK

NC_DP_IG_C_HPD

NC_CRT_IG_GREEN

TRUE MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

TRUE

NC_SMC_FAN_3_TACH

TRUE

SPKRAMP_BR_OUT_P

TRUE

SPKRAMP_FR_OUT_N

TRUE

SPKRAMP_BL_OUT_P

TRUE

SPKRAMP_FL_OUT_N

TRUE

SPKRAMP_FL_OUT_P

TRUE

PP5V_S0

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

PCIE_WAKE_L

TRUE

PP3V3_S3_EXCARD_SWITCH

WIFI_EVENT_L

TRUE

FAN_RT_PWM

TRUE

AUD_DMIC_SDA_BK

TRUE

LPCPLUS_GPIO

MAKE_BASE=TRUE

TRUE

NC_PCH_TP1

NC_PCH_TP3

TRUE

MAKE_BASE=TRUE

NC_PCH_TP4

TRUE

MAKE_BASE=TRUE

NC_PCH_TP9

NC_PCH_TP12

DP_SDRVA_ML_C_N<2>

TRUE

WS_KBD22

TRUE

ISSP_SCLK_P1_1

TRUE

PM_SYSRST_L

TRUE

LCD_BKLT_PWM

SMC_TDI

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

SMBUS_SMC_A_S3_SCL

SMC_NMI

TRUE

SMC_ONOFF_L

PPVBAT_G3H_CONN

TRUE

PP3V42_G3H_LIDSWITCH_R

TRUE

PP5V_S3_IR_R

TRUE TRUE

SMC_LID_R

TRUE

IR_RX_OUT SYS_LED_ANODE

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SCL

TRUE

NC_SATA_C_R2D_CN

NC_SATA_C_D2RN

Z2_CLKIN

TRUE

PSOC_F_CS_L

TRUE

PSOC_SCLK

TRUE

PSOC_MOSI

TRUE

PSOC_MISO

TRUE

PICKB_L

TRUE

PP3V3_S3

TRUE

T29_R2D_C_N<1..0>

TRUE

T29_R2D_C_P<1..0>

TRUE

SPKRAMP_FR_OUT_P

TRUE

PPVOUT_S0_LCDBKLT

TRUE

SPKRAMP_LFE_OUT_P

TRUE

AUD_DMIC_CLK_BK

TRUE

AUD_DMIC_CLK_FR

TRUE

AUD_DMIC_PWR_FR

TRUE

LED_RETURN_5

TRUE

LED_RETURN_6

LED_RETURN_4

TRUE

LED_RETURN_3

TRUE

LED_RETURN_2

TRUE

LED_RETURN_1

LVDS_CONN_B_CLK_F_N

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

LVDS_CONN_B_DATA_N<2>

TRUE

LVDS_CONN_B_DATA_N<1>

TRUE

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<0>

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_CONN_B_DATA_P<0>

TRUE

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_A_DATA_P<2>

TRUE

LVDS_CONN_A_DATA_P<1>

TRUE TRUE

LVDS_CONN_A_DATA_N<1>

TRUE

LVDS_CONN_A_DATA_N<0>

TRUE

SATA_ODD_R2D_N

TRUE

SATA_ODD_R2D_P

TRUE

SATA_ODD_D2R_UF_N

SMC_ODD_DETECT

TRUE

PP5V_SW_ODD

TRUE

IR_RX_OUT

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_R2D_N

TRUE

SMC_LID_R

TRUE

SMC_BIL_BUTTON_L

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SDA

TRUE

PP3V42_G3H

TRUE

PP18V5_DCIN_FUSE

ADAPTER_SENSE

TRUE

KBDLED_ANODE

TRUE

SMC_KDBLED_PRESENT_L

TRUE

SMC_TDO

TRUE

PP5V_S0_HDD_FLT

PPBUS_G3H

TRUE

PM_SLP_S3_L

TRUE

PPVCORE_S0_CPU

PP5V_S0

TRUE

PP3V3_S5

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PPDCIN_G3H

TRUE

PP18V5_S4

LPCPLUS_RESET_L

TRUE

SMC_RESET_L

NC_NV_CLE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CN

NC_SATA_D_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_SATA_SSD2_D2RN

NC_BCM57765_TRAFFICLED_L

TRUE

MAKE_BASE=TRUE

PCH_VSS_NCTF<2>

TRUE

NC_PCH_TP1

NC_PCH_TP3

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

TRUE

NC_BCM57765_SPD100LED_L NC_BCM57765_SPD100LED_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE7N

TRUE

NC_PCIE_CLK100M_PE7P

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RN

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_SSD2_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_SATA_SSD2_D2RP

NC_SATA_D_R2D_CP

NC_SATA_C_D2RP

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

TRUE

TRUE MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE6N

TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

TRUE

TP_NV_WR_RE_L<1..0>

NC_NV_CLE

NC_NV_DQS<1..0>

TRUE MAKE_BASE=TRUE

TP_NV_DQ<15..0>

MAKE_BASE=TRUE

NC_NV_DQ<15..0>

TRUE

NC_NV_CE_L<3..0>

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK33M_OUT3

TRUE

MAKE_BASE=TRUE

NC_PCI_PME_L

TRUE MAKE_BASE=TRUE

NC_PCI_PME_L

TRUE

MAKE_BASE=TRUE

NC_PCI_PAR

NC_PCI_RESET_L NC_PCI_RESET_L

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT0_L

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT0_L

NC_PCI_GNT2_L

TRUE MAKE_BASE=TRUE

NC_PCI_GNT2_L

NC_PCI_GNT1_L NC_PCI_GNT1_L

MAKE_BASE=TRUE

TRUE

TP_PCI_AD<31..0> NC_PCI_AD<31..0>

MAKE_BASE=TRUE

TRUE

TP_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

NC_PCI_C_BE_L<3..0>

TRUE

NC_PCI_GNT3_L

TRUE MAKE_BASE=TRUE

NC_PCI_GNT3_L

NC_HDA_SDIN3

NC_HDA_SDIN2 NC_HDA_SDIN2

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

NC_LVDS_IG_CTRL_DATA

NC_LVDS_IG_CTRL_CLK NC_LVDS_IG_CTRL_CLK

TRUE MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

TRUE

NC_CRT_IG_DDC_DATA

NC_CRT_IG_RED

TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

NC_CRT_IG_GREEN

NC_CRT_IG_BLUE

NC_FW643_TDI

TP_DP_IG_D_MLN<3..0>

TP_DP_IG_D_MLP<3..0>

NC_DP_IG_D_CTRL_CLK

NC_DP_IG_D_CTRL_DATA

TRUE MAKE_BASE=TRUE

NC_SDVO_STALLP

TRUE

NC_GPU_GSTATE<0>

MAKE_BASE=TRUE

TRUE

NC_GPU_GSTATE<1>

MAKE_BASE=TRUE

TRUE

NC_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_LVDS_EG_B_CLKN

MAKE_BASE=TRUE

TRUE

NC_LVDS_EG_B_CLKP NC_LVDS_EG_BKL_PWM

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

TRUE

MAKE_BASE=TRUE

TRUE

NC_LVDS_IG_B_CLKP NC_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_DE

TRUE

PCH_VSS_NCTF<29>

TRUE

PCH_VSS_NCTF<27>

PCH_VSS_NCTF<25>

TRUE

PCH_VSS_NCTF<21>

TRUE

PCH_VSS_NCTF<19>

TRUE

PCH_VSS_NCTF<17>

TRUE

PCH_VSS_NCTF<15>

TRUE

PCH_VSS_NCTF<12>

TRUE

PCH_VSS_NCTF<11>

TRUE

PCH_VSS_NCTF<7>

TRUE

PCH_VSS_NCTF<5>

NC_PCH_TP5

TRUE

MAKE_BASE=TRUE

NC_PCH_TP7

TRUE

MAKE_BASE=TRUE

NC_PCH_TP6

TRUE

MAKE_BASE=TRUE

NC_PCH_TP2

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCH_TP8

MAKE_BASE=TRUE

TRUE

NC_PCH_TP11

MAKE_BASE=TRUE

TRUE

NC_PCH_TP12

MAKE_BASE=TRUE

TRUE

NC_PCH_TP9

MAKE_BASE=TRUE

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_PCH_TP18

MAKE_BASE=TRUE

TRUE

NC_PCH_TP17

MAKE_BASE=TRUE

TRUE

NC_PCH_TP15

MAKE_BASE=TRUE

TRUE

NC_PCH_TP14

TRUE

MAKE_BASE=TRUE

NC_PCH_NC4

TRUE

MAKE_BASE=TRUE

NC_PCH_NC2

MAKE_BASE=TRUE

TRUE

NC_PCH_TP19

TRUE

MAKE_BASE=TRUE

NC_PCH_NC5

TRUE

MAKE_BASE=TRUE

NC_PCH_NC1

TRUE

MAKE_BASE=TRUE

NC_PCH_SST

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTP

NC_DP_IG_D_AUXP

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_CTRL_CLK

TRUE MAKE_BASE=TRUE

NC_DP_IG_D_HPD

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXN

TRUE MAKE_BASE=TRUE

NC_DP_IG_C_AUXP

TRUE MAKE_BASE=TRUE

PCH_VSS_NCTF<9>

TRUE

PCH_VSS_NCTF<1>

TRUE

NC_LVDS_EG_BKL_PWM

NC_LVDS_EG_B_CLKP

NC_LVDS_EG_B_CLKN

TP_LVDS_IG_B_CLKN

NC_PCH_NC2

NC_PCH_NC1

NC_DP_IG_D_AUXP

NC_SDVO_TVCLKINP

NC_SDVO_INTN

NC_SDVO_STALLP

NC_PCH_SST

NC_SDVO_STALLN

NC_PCH_TP17

NC_PCH_TP14

NC_PCH_TP15

NC_PCH_NC3 NC_PCH_NC4 NC_PCH_NC5 NC_PCH_TP19 NC_PCH_TP18

NC_PCH_TP16

NC_PCH_TP13

NC_PCH_TP11

NC_PCH_TP8

NC_DP_IG_C_CTRL_DATA

TP_DP_IG_C_MLN<3..0>

TP_DP_IG_C_MLP<3..0>

NC_PCH_TP6

NC_PCH_TP7

NC_PCH_TP5 NC_PCH_TP4

TP_GPU_MIOA_D<9..0>

NC_SDVO_INTP

NC_GPU_BUFRST_L NC_GPU_GSTATE<0> TP_GPU_GSTATE<1>

NC_GPU_MIOA_DE

TP_LVDS_IG_B_CLKP

NC_HDA_SDIN3

TRUE

MAKE_BASE=TRUE

TRUE MAKE_BASE=TRUE

NC_PCH_LVDS_VBG

NC_CRT_IG_DDC_DATA

TRUE MAKE_BASE=TRUE

NC_CRT_IG_DDC_CLK

TRUE MAKE_BASE=TRUE

NC_CRT_IG_BLUE

TRUE MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

TRUE MAKE_BASE=TRUE

NC_HDA_SDIN1

MAKE_BASE=TRUE

TRUE

NC_PCH_LVDS_VBG

NC_CRT_IG_VSYNC

NC_CRT_IG_HSYNC

NC_CRT_IG_RED

TRUE

SYS_LED_ANODE_R

TRUE

PP5V_S3_IR_R

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_R2D_P

PP3V42_G3H

TRUE

PCIE_AP_D2R_P

AP_RESET_CONN_L

TRUE

SMBUS_SMC_0_S0_SDA

TRUE

SMBUS_SMC_0_S0_SCL

TRUE

USB_BT_P

TRUE

USB_BT_N

TRUE

USB_CAMERA_CONN_P

SMBUS_PCH_CLK

TRUE

PP3V3_S0_EXCARD_SWITCH

TRUE

SMBUS_PCH_DATA

TRUE

USB2_EXCARD_CONN_N

TRUE

USB2_EXCARD_CONN_P

TRUE

EXCARD_CLKREQ_CONN_L

TRUE

EXCARD_CPUSB_L

PLT_RESET_SWITCH_L

TRUE TRUE

PCIE_EXCARD_D2R_P PCIE_EXCARD_D2R_N

TRUE

PCIE_EXCARD_R2D_N

TRUE

PCIE_EXCARD_R2D_P

TRUE

PCIE_CLK100M_EXCARD_CONN_P

TRUE

PCIE_CLK100M_EXCARD_CONN_N

TRUE

PP3V3_S4

TRUE

PP18V5_S4

TRUE

Z2_CS_L Z2_DEBUG3

TRUE

Z2_MISO

TRUE

Z2_MOSI

TRUE

SMBUS_SMC_BSA_SDA

TRUE

AUD_DMIC_SDA_FR

FAN_RT_TACH

TRUE

PCIE_CLK100M_AP_CONN_P

TRUE

DP_T29SNK0_ML_C_P<3..0>

TRUE

DP_T29SNK0_ML_N<3..0>

TRUE

DP_T29SNK1_ML_P<3..0>

TRUE

DP_T29SNK0_ML_C_N<3..0>

TRUE

DP_T29SNK0_ML_P<3..0>

TRUE

DP_T29SNK1_ML_C_P<3..0>

TRUE

DP_T29SNK1_AUXCH_P

TRUE

DP_T29SNK1_AUXCH_C_N

TRUE

DP_T29SNK1_AUXCH_C_P

TRUE

DP_T29SNK1_AUXCH_N

TRUE

DP_T29SNK1_ML_C_N<3..0>

TRUE

TP_DP_T29SRC_AUXCH_CN

TRUE

TP_DP_T29SRC_ML_CN<3..0>

TRUE

DP_SDRVA_ML_C_N<0>

TRUE

DP_T29SNK1_ML_N<3..0>

TRUE

DP_SDRVA_ML_C_P<2>

TRUE

DP_SDRVA_ML_N<2>

TRUE

DP_SDRVA_ML_P<2>

TRUE

DP_SDRVA_ML_N<0>

TRUE

DP_SDRVA_ML_P<0>

DP_SDRVA_ML_C_P<0>

TRUE

TP_DP_T29SRC_ML_CP<3..0>

TRUE

TP_DP_T29SRC_AUXCH_CP

TRUE

PP1V5_S0_EXCARD_SWITCH

LVDS_CONN_A_DATA_P<0>

TRUE

LVDS_DDC_CLK

PP3V3_SW_LCD

TRUE

WS_KBD21

TRUE

WS_KBD19

WS_KBD17

TRUE

NC_FW2_TPAP

NC_FW2_TPBIAS

NC_SMC_FAN_2_CTL

TRUE

NC_SMC_FAN_2_TACH

TRUE

PP5V_S3

TRUE

NC_PCH_TP10

MAKE_BASE=TRUE

TRUE

NC_PCH_TP13

MAKE_BASE=TRUE

TRUE

NC_PCH_TP16

TRUE

MAKE_BASE=TRUE

NC_PCH_NC3

TP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

TRUE

NC_SDVO_INTN

NC_SDVO_TVCLKINN

TRUE

T29_D2R_P<1..0> T29_D2R_N<1..0>

TRUE

DP_T29SNK0_AUXCH_N

TRUE

DP_T29SNK0_AUXCH_C_P

T29DPA_ML_N<3..0>

TRUE

T29_R2D_N<1..0>

TRUE

NC_DP_IG_D_AUXN

MAKE_BASE=TRUE

TRUE

NC_DP_IG_D_AUXN

SMBUS_SMC_A_S3_SCL

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

PCIE_WAKE_L

TRUE

PP3V3_WLAN

TRUE

AUD_DMIC_PWR_BK

TRUE

USB_CAMERA_CONN_N

PP3V3_S3_BT_F

TRUE

AP_CLKREQ_Q_L

TRUE

PCIE_CLK100M_AP_CONN_N

PP3V42_G3H

TRUE

WS_KBD4

WS_KBD3

TRUE

WS_KBD2

TRUE

WS_KBD1

TRUE

WS_KBD_ONOFF_L

TRUE

WS_LEFT_OPTION_KBD

TRUE

Z2_BOOST_EN

WS_KBD13

TRUE

WS_KBD12

TRUE

WS_KBD11

TRUE

DP_SDRVA_ML_R_P<0>

TRUE

DP_SDRVA_ML_R_N<2>

TRUE

DP_SDRVA_ML_R_P<2>

TRUE

DP_A_BIAS DP_SDRVA_ML_R_N<0>

TRUE

T29DPA_D2R1_AUXCH_N

TRUE

TP_T29_PCIE_RESET3_L

TRUE

TP_T29_PCIE_RESET2_L

T29_R2D_P<1..0>

TRUE

DP_T29SNK0_AUXCH_P

TRUE

DP_T29SNK0_AUXCH_C_N

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

WS_KBD8

TRUE

WS_KBD9

TRUE

PP3V3_S4

TRUE MAKE_BASE=TRUE

NC_LVDS_IG_CTRL_DATA

TRUE

TP_DVPCNTL_M<1..0>

TRUE

T29_D2R_C_N<1..0>

T29_D2R_C_P<1..0>

TRUE

MAKE_BASE=TRUE

NC_NV_ALE

NC_NV_RB_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_NV_WR_RE_L<1..0>

TRUE

MAKE_BASE=TRUE

NC_NV_WE_CK_L<1..0>

TRUE

NC_SATA_C_D2RP

NC_PSOC_P1_3

NC_PCIE_CLK100M_PE7P

NC_PCIE_CLK100M_PE7N

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE6N

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_PE5N

NC_SATA_C_R2D_CP

Z2_KEY_ACT_L

TRUE

Z2_RESET

TRUE

Z2_HOST_INTN

TRUE

Z2_SCLK

TRUE

PCIE_AP_D2R_N

TRUE

NC_NV_RB_L

NC_NV_ALE

TP_NV_CE_L<3..0>

TP_T29_PCIE_RESET1_L

TRUE

PP3V3_S0

TRUE

PP1V2_S0

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

7 OF 132 6 OF 105

83 99

83 84

41 94

6

41 94

6

41 94

52

6 7 8 22 41

47

52 54 65 68 69 70 73 87

104 105

7

14 20 25 71 72

88

102

41 94

6

17

6

17

6 7

12

23 25 26 28

32 35 36

39 40 41

46 48 49

50 51 52

54 57 61

62 72 73 80

83 84 85

88 89 91

100 102

42 45 46 47

45 46 47

53

6

36

6

44

25 47 95

16 45 47 88 95

47

41 94

16 45 47 88 95

17 45 47

45 46 47

45 47

42 45 46 47

47

16 45 47

17 45 47

45 47

19 47 56

47

79

38 40

38

6

38

38 40

9

17 92

60 61

38 40

6

17

6

17

6

17

6

17

6

17

6

17

38 40

12

9

51

9

17 92

9

17 92

9

17 92

9

17 92

9

17 92

79

79 80

79

6

17

41 94

16 41 94

6

41 94

6

41 94

6

16

6

16

6

16

41 94

6

41 94

6

41 94

8

85

8

85

8

85

8

85

8

85

8

85

8

85

8

85

6

85

31 95

53

31 95

53

41 94

6

7

75 79 81

103

7

49 75 82

7

72

103

7

72 75 79 80 82

84

7

39 40

7

30 67

6 7 8

18 24 25 29

30 31 32 48 49 50

54 55

73 88

104

32

60 61

6

18

33

86 97

6

85 86 97

53

6

36

6

36

6

17

6

17

6

17

6

17

45 46

60 61

6 7 8 22 41

47

52

54 65 68 69 70 73 87

104 105

31

6

17 25 31 32 85

32

31 45 46

52

61

19 47

6

85 97

53

17 25 45

88 89

45 46 47

6

31 45 48 54 55 98

6

31 45 48 54 55 98

45 47

45 46 53

63 64

44

6

44

6

44

6

44

44 46

63

6

45 48 63 64 98

6

53 54

6 7 8

18 24 25 29 30

31 32 48 49 50 54 55 73 88

104

33 85 97

60 61

61

83 89

83 99

83 84 99

83 99

83 84 99

41 94

41 45

41

104

6

44

6

41 94

6

44

45 46 63

6

45 48 63 64 98

6

45 48 63 64 98

6 7

25 42 44 45 46 47 48 53 63 64 73

104

63

54

45 46 47

41

7 8

35 39 49 50 63

64 90

17 29 45 73

7

12 14 49 69

105

6 7 8

22 41 47 52

54 65 68 69 70 73

87

104 105

45 46

7

49 63 64

6

54

25 47 88 95

45 46 47 64

6

16

6

16

6

16

6

16

6

36

6

16

6

36

6

36

6

19

6

19

6

16

6

53

6

19

6

19

6

16

6

18

6

18

6

18

6

6 6

6

16

6

16

6

16

6

16

6

18

6

18

6

18

6

17

6

17

6

17

6

17

6

17

6

17

6

38

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

8

18

6

17

6

17

6

17

6

17

6

17

6

17

6

17

6

8

18

6

16

6

18

6

17

6

17

6

17

6

17

6

16

6

18

6

17

6

17

6

17

6

44

6

44

6

41 94

6 7

25 42 44 45 46

47 48 53 63 64 73

104

16 31 95

31

31 45 48 51 80 98

24 31 94

31 94

16 23 26 28 30 32 41 48 62 89 95

32

16 23 26 28 30 32 41 48 62 89 95

32

100

32

100

32

16 32

100

16 32

100

32

100

32

100

32

100

32

100

6 7

46 53 54 72

6

54

53 54

6

45 48 63 64 98

31

100

33 79 97

33 97

33 79 97

33 97

33 79 97

33 97

33 79 97

33 97

33 79 97

33

85 97

33 97

85 97

33

32

83 84 99

53

38 40

45 46

6

8

18

6

17

6

17

33 85 97

33 97

33 79 97

85 86 97

85 97

6

17

6

17

6

31 45 48 54 55 98

6

31 45 48 54 55 98

6

17 25 31 32 85

31 46

61

31 94

31

100

6 7

25 42

44 45 46 47

48 53 63 64

73

104

53

54

53

85 97

85

85 97

86 97

33

85 97

33 97

33 79 97

53

6 7

46 53 54 72

6

18

79

85 86 97

6

53

6

19

6

19

6

19

6

19

6

16

6

16

6

53 54

16 31 95

6

33

6 7

12 23 25 26 28

32 35 36

39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91

100 102

7 71

88

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

T29 Rails

"FW" (FireWire) Rails

3.3V/1.8V Rails

1.5V/1.05V Rails

? mA

Chipset Rails

5V Rails

ENET Rails

DDR Rails

"GPU" Rails

"G3Hot" (Always-Present) Rails

SYNC_DATE=04/26/2010

Power Aliases

SYNC_MASTER=K17_MLB

PP15V_T29

MAKE_BASE=TRUE

VOLTAGE=15V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP15V_T29

PPVIN_S5_HS_COMPUTING_ISNS

PP5V_S5 PP5V_S5

PP3V3_S0

PPVCCSA_S0_CPU

PP3V3_S0

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP5V_S0 PP5V_S0

PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0 PP5V_S0

PP3V42_G3H

PP3V3_S3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

PPBUS_G3H

PPVIN_S5_HS_GPU_ISNS

PPDCIN_G3H

PP3V3_S5

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_S4PP3V3_S4

PP3V3_S4

PP3V3_S5_ISNS_R

PP3V3_SUS PP3V3_SUS

PPBUS_G3H

PPVIN_S5_HS_COMPUTING_ISNS

PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS PPVIN_S5_HS_COMPUTING_ISNS

PP3V3_S5 PP3V3_S5 PP3V3_S5

VOLTAGE=12.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_HS_OTHER_ISNS

PPVP_FW

PP3V3_T29

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_T29

PPBUS_G3H

PP5V_S3

PP5V_S3_ISNS_R

PPVIN_S5_HS_GPU_ISNS

PP3V3_S3 PP3V3_S3 PP3V3_S3

MAKE_BASE=TRUE

VOLTAGE=5V

PP5V_S3_ISNS_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S0

PP1V5_S0

PPVIN_S5_HS_OTHER_ISNS

PP3V3_S0GPU

PPVCORE_GPU

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.15V MAKE_BASE=TRUE

PP1V05_S0

PP1V5_S3

PP1V5_S3_CPU_VCCDQ

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S3RS0_CPUDDR

PP1V5R1V35_GPU_FB_ISNS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0GPU

MIN_LINE_WIDTH=0.6 MM VOLTAGE=1.8V

PP1V8_S0GPU_ISNS_R

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP1V0_S0GPU

MAKE_BASE=TRUE

VOLTAGE=1.0V

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 MM

PP1V5_S3RS0

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0GPU

PPVCORE_GPU

PP1V05_S0_CPU_VCCPQE

PP1V5_S3RS0

PP1V0_S0GPU

PP1V8_S0GPU

PP1V5_S3

PP1V5_S3 PP1V5_S3

PP1V5_S3

PP1V8_S0GPU

PP0V75_S0_DDRVTT

PP1V5R1V35_GPU_FB_ISNS

PP1V5_S0GPU_ISNS_R

PP3V3_S0GPU

PP1V0_S0GPU_ISNS_R

PP1V8_S0GPU_ISNS_R

PP1V8_S0GPU

PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU PP1V0_S0GPU

PP1V0_S0GPU

PP1V8_S0GPU

PP1V5_S3

PP1V5_S3RS0_CPUDDR

PPVTTDDR_S3

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.5V MAKE_BASE=TRUE

PP1V5_S3RS0_CPUDDR

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0.75V MAKE_BASE=TRUE

PPVTTDDR_S3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_S0_CPU_VCCPQE

VOLTAGE=1.05V MAKE_BASE=TRUE

PP1V8_S0GPU

PP1V8_S0GPU_ISNS_R

PP1V0_S0GPU

PP1V0_S0GPU_ISNS_R

PP1V5_S3RS0_CPUDDR

PP3V3_S0GPU

PP0V75_S0_DDRVTT

VOLTAGE=0.75V MAKE_BASE=TRUE

PP0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 MM

PP1V5_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5R1V35_GPU_FB_ISNS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V5_S0GPU_ISNS_R

PP5V_S5

PPVRTC_G3H

PP1V2_S0

PP3V3_S0GPU

MAKE_BASE=TRUE

VOLTAGE=1.0V

PP1V0_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V5R1V35_GPU_FB_ISNS

MIN_LINE_WIDTH=0.3 MM VOLTAGE=3.3V

PP3V3_S0GPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V5_S3

VOLTAGE=1.5V

PPVRTC_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PPVRTC_G3H

PPDCIN_G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H

MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_HS_GPU_ISNS

PP3V42_G3H

PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H PP3V42_G3H

MAKE_BASE=TRUE

VOLTAGE=3.42V

MIN_LINE_WIDTH=0.3 MM

PP3V42_G3H

MIN_NECK_WIDTH=0.2 MM

PP5V_S5

MAKE_BASE=TRUE

VOLTAGE=5V

MIN_LINE_WIDTH=0.3 MM

PP5V_S5

MIN_NECK_WIDTH=0.2 MM

PP5V_S3

PP5V_S3 PP5V_S3

PP5V_S3 PP5V_S3 PP5V_S3

PP5V_S3_ISNS_R

PP5V_S0 PP5V_S0

PP5V_S0

MIN_LINE_WIDTH=0.5 MM

PP5V_S0_ISNS_R

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_S0_ISNS_R

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM

PP5V_SUS

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_SUS

PP3V3_S0 PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP5V_S3

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_ENET

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP3V3_S0

PP3V42_G3H

PPDCIN_G3H

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PPVIN_S5_HS_GPU_ISNS

PP5V_S5

PP1V05_SUS

PPVIN_S5_HS_COMPUTING_ISNS

PP1V2_ENET

PP3V3_S0

PP1V5_S3_CPU_VCCDQ

PP1V05_SUS

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0

PP1V05_S0 PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V05_S0 PP1V05_S0 PP1V05_S0

PP1V05_S0

PP1V2_S0

MAKE_BASE=TRUE

VOLTAGE=1.2V

PP1V2_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V5_S0

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.5V

PP1V5_S0

MAKE_BASE=TRUE

PP1V8_S0

PP1V8_S0_CPU_VCCPLL_R

PP1V0_FW_FWPHY

MAKE_BASE=TRUE

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_FWPHY

PP3V3_FW_FWPHY

PPVP_FW

PP1V8_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=1.8V MAKE_BASE=TRUE

PP1V8_S0

PPVCORE_S0_CPU

PP3V3_S3

PPVCORE_S0_CPU

MAKE_BASE=TRUE

VOLTAGE=1.1V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

PPVCORE_S0_AXG

MAKE_BASE=TRUE

VOLTAGE=1.05V

PPVCORE_S0_AXG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PPVCCSA_S0_CPU

MAKE_BASE=TRUE

VOLTAGE=0.9V

PPVCCSA_S0_CPU

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_ENET

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET PP3V3_ENET PP3V3_ENET

MAKE_BASE=TRUE

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP1V2_ENET

PP3V3_S3

PPBUS_G3H

PP1V8_S0

PPBUS_G3H

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.4 mm

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PP3V3_S5

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPVIN_S5_HS_COMPUTING_ISNS

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5 PP3V3_S5

PP3V3_S5

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP1V8_S0

PP3V3_S3

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP3V3_S3_ISNS_R

PP3V3_S0

PP3V3_S3_ISNS_R

PP3V3_S3

PP3V3_S0

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_S3_ISNS_R

PP3V3_S3

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.4 MM

PPVP_FW

PP3V3_S5

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0_CPU_VCCPLL_R

PP0V75_S0_DDRVTT

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PP3V3_S5_ISNS_R

PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS PP3V3_SUS

PP3V3_S3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP3V3_SUS

VOLTAGE=3.3V

MAKE_BASE=TRUE

PP3V3_SUS

PP3V3_S5_ISNS_R

PP3V3_S4

MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM

PP3V3_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY

PP3V3_S5

PPBUS_G3H

PP3V3_T29 PP3V3_T29 PP3V3_T29 PP3V3_T29

PP1V05_T29

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PP3V3_T29

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP5V_S5

8 OF 132 7 OF 105

7 8

35 86

7 8

35 86

7 8

35

86

7

50 65

67 68 69

70

7

54 66 72

103 104

7

54 66 72

103 104

6 7

12 23 25 26 28 32 35

36 39 40 41 46 48 49 50

51 52 54 57 61 62 72 73 80 83 84 85 88

89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100

102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

35 39 49 50 63 64 90

7

50 82

87

6 7

49 63 64

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

46 53 54 72

6 7

46 53 54 72

6 7

46 53 54 72

7

66

104

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46

71 72 73

6 7 8

35 39 49 50 63 64 90

7

50 65 67 68 69 70

7

50 65 67 68 69 70

7

50 65 67 68 69 70

7

50 65 67 68 69 70

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

7

50 66

6 7

39 40

6 7

39 40

7

16 19 25 33 34 35 88

7

34 35

6 7 8

35

39 49 50

63 64 90

6 7

29 31 42 43 44 46 67 72 82

104

7

66

104

7

50 82 87

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

7

66

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

7

16 20

22 25 32 41 57 71

7

50 66

7

50 66

6 7

72 75 79 80 82 84

6 7

49 75 82

7 9

10 12 13 14 23 35

39 45 68 70 73

102 104 105

7

26 28 29 67 72

7

12 15

7

10 13 15 29 73

104

7

75 76 77 78

103

6 7

75 79 81

103

6 7

72

103

7

74 75 79 81

103

7

72

100 104

6 7

72 75 79 80 82 84

6 7

72 75 79 80 82 84

6 7

49 75 82

7

10 12 14

7

72

100 104

7

72

100 104

7

74 75 79 81

103

6 7

75 79 81

103

7

26 28 29 67 72

7

26 28 29 67 72

7

26 28 29 67 72

7

26 28 29 67 72

6 7

75 79 81

103

7

26 28 29 67

7

26 28 29 67

7

75 76 77 78

103

7

75 76 77 78

103

7

75 76 77 78

103

7

87

103

6 7

72 75 79 80 82 84

6 7

72 75 79 80 82 84

7

87

103

6 7

72

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

7

26 28 29 67 72

7

10 13 15 29 73

104

6 7

30 67

7

10 13 15 29 73

104

6 7

30 67

7

10 12 14

6 7

75 79 81

103

6 7

72

103

7

74 75 79 81

103

7

87

103

7

10 13 15 29 73

104

6 7

72 75 79 80

82 84

7

26 28 29 67

7

26 28 29 67

7

87

103

7

75 76 77 78

103

7

87

103

7

54 66 72

103 104

7

16 17

20 25

6 7

72 75 79 80 82 84

6 7

72 75 79 80 82 84

7

87

103

7

75 76 77 78

103

6 7

72 75 79 80 82 84

7

26 28 29 67 72

7

16 17 20 25

7

16 17 20 25

6 7

49 63 64

6 7

49 63 64

7

50 82 87

6 7

25 42 44 45

46 47 48

53 63 64

73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46

47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

7

54 66 72

103 104

7

54 66 72

103 104

7

54 66 72

103 104

7

54 66 72

103 104

7

54 66 72

103 104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42

43 44 46 67 72

82

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

7

66

104

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105 6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54

65 68 69 70 73

87

104 105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

7

72

104

7

72

104

7

72

104

7

22 72

7

22 72

7

22 72

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62

72 73 80 83 84 85 88 89 91

100 102 6 7

12 23 25 26 28 32 35 36 39 40 41 46 48

49

50 51 52 54 57 61 62 72 73 80 83 84 85

88

89 91

100 102

6 7 12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80

83 84 85 88 89 91

100 102

6 7

12

23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91 100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73

80 83 84 85 88 89 91

100 102 6 7 12 23 25 26 28 32 35 36 39 40 41 46 48

49

50 51 52 54 57 61 62 72 73 80 83 84 85

88

89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89

91

100 102 6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72

73 80 83 84 85 88 89 91

100 102 6 7

12 23 25 26 28 32 35 36 39 40 41 46 48

49

50 51 52 54 57 61 62 72 73 80 83 84 85

88

89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

29 31 42 43 44 46 67 72 82

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91

100 102

7

25 36 71 73

7

12 13 15 49 69

6 7

29 31 42 43 44 46 67 72 82

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50

51 52 54 57 61 62 72 73 80 83 84 85 88

89 91

100 102

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

49 63 64

7

50 82 87

7

54 66 72

103 104

7

23 71

7

50 65 67 68 69 70

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54

57 61 62 72 73 80 83 84 85 88 89 91

100

102

6 7

12 23 25 26 28 32 35 36 39 40 41

46 48 49 50 51 52 54 57 61 62 72 73

80 83 84 85 88 89 91

100 102

6 7 12

23 25 26 28 32 35 36 39 40 41 46 48 49

50

51 52 54 57 61 62 72 73 80 83 84 85 88

89 91

100

102

7

23 71

7

23 71

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10

12 13 14 23 35 39 45 68 70 73

102 104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105 7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105 7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105 7 9

10 12 13 14

23 35 39 45 68 70 73

102 104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105 7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

6 7

71 88

7

16 20 22 25 32 41 57 71

7

16 20 22 25 32

41 57 71

7

16 20 22 25 32 41 57 71

7

16 20 22 25 32 41 57 71

7

16 20 22 25 32 41 57 71

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

7

12 14

7

38 39

7

38 39

7

38 39

7

38 39 40

6 7

39 40

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

6 7

12 14 49 69

105

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7

12 14 49 69

105

6 7

12 14 49 69

105

7

12 13 15 49 69

7

12 13 15 49 69

7

12 15 65

7

12 15 65

7

25 36 71 73

7

25 36 71 73

7

25 36 71 73

7

25 36 71 73

7

36 71

7

36 71

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31

32 48 49 50 54 55 73 88

104

6 7 8

35 39 49 50 63 64 90

6 7

14 20 25 71 72 88

102

6 7 8

35 39 49 50

63 64 90

6 7 8

35 39 49 50 63 64 90

6 7 8

35 39 49 50 63 64 90

6 7 8

35 39 49 50 63 64 90

7

50 65 67 68 69 70

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7 17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17

19 20 22 23 24 25 29 46 48 56 71 72 73

83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86

91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

14 20 25 71 72 88

102

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

7

72

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54

57 61

62 72

73 80 83 84 85 88 89 91

100 102

7

72

104

6 7 8

18 24 25 29 30 31 32

48 49 50 54 55 73 88

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73

80 83 84 85 88 89 91

100 102

7

72

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7

39 40

7

12 14

7

26 28 29 67

7

66

104

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71

72 73 7

16 17 18 19 20 22 46 71 72 73

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6

7 8

18 24 25 29 30 31 32

48 49 50 54 55 73 88

104

7

16 17 18 19 20 22 46 71 72 73

7

16 17 18 19 20 22 46 71 72

73

7

66

104

6 7

46 53 54 72

6 7

17 19 20 22 23 24 25

29 46 48 56 71 72 73 83 86 91

100 102 104

7

38 39 40

7

38 39 40

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71 72 73 83 86 91

100 102 104

6 7 8

35 39 49 50 63 64 90

7

16 19 25 33 34 35 88

7

16 19 25 33 34 35 88

7

16 19 25 33 34 35 88

7

16 19 25 33 34 35 88

7

34 35

7

34 35

7

16 19 25 33 34 35 88

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62

72 73 80 83 84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51

52

54 57 61 62 72 73 80 83 84 85 88 89 91 100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46 48 49 50 51 52 54 57 61 62 72 73 80 83 84 85 88 89 91 100 102

6 7

12

23 25 26

28 32 35

36 39 40

41

46 48 49 50 51 52 54 57

61 62 72 73 80 83 84 85

88 89 91

100

102

7

54 66 72

103 104

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Digital Ground

Unused USB ports

T29 / GMUX JTAG Signals

T29_A_BIAS caps

T29 Signals

Unused SD card signals

TM Hole

T29_A_BIAS caps

Unused PEG lanes

GPU signals

TM Hole

Bottom GPU Right

GMUX ALIASES

CPU signals

Thermal Module Holes

Bosses for Flex Protector Bracket

TM Hole

Frame Holes

Rev. A NCs

USB Hub Aliases

Unused T29 Ports

Top GPU Center

DP_A_BIAS caps

Right CPU

Heat spreader mounting boss for PCH

Left CPU

TM Hole

Bottom CPU Left

Bottom GPU Left

AUDIO ALIASES

TM Hole

Heat spreader mounting boss for T29 router

ZT0980

1

STDOFF-4.5OD.98H-1.1-3.48-TH

2 1

SM

XW0900

2 1

XW0901

SM

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0981

1

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0983

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0984

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0987

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0960

3R2P5

1

ZT0989

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0988

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0991

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0930

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0932

3R2P5

1

ZT0971

3R2P5

1

SH0913

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0910

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0914

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0911

1

SH0900

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0903

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0902

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0919

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

SH0917

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0916

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0918

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

SH0920

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0921

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0922

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0923

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

ZT0957

4.0OD1.65H-M1.6X0.35

1

ZT0958

4.0OD1.65H-M1.6X0.35

1

SM

SH0901

2.0DIA-TALL-EMI-MLB-M97-M98

1

ZT0915

3R2P5

SH0924

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0930

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0931

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0932

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0933

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0935

1

SH0934

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

ZT0940

3R2P5

1

ZT0970

3R2P5

2 1

XW0902

SM

1

SH0912

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

2

1

402

100K

5% MF-LF

1/16W

R0902

1

SH0940

STDOFF-4.0OD1.85H-SM

SH0941

1

STDOFF-4.0OD1.85H-SM

1

SH0942

STDOFF-4.0OD2.23H-SM

1

SH0943

STDOFF-4.0OD2.23H-SM

1

ZT0931

STDOFF-4.0OD3.35H-TH

1

ZT0934

STDOFF-4.0OD3.35H-TH

2

1

R0915

10K

402

5% MF-LF

1/16W

2

1

R0916

10K

5%

402

1/16W MF-LF

R0950

805

5%

1/8W

MF-LF

21

0

T29BST:N

2

1

C0905

SIGNAL_MODEL=EMPTY

0.01UF

10%

201

X5R

10V

2

1

C0908

SIGNAL_MODEL=EMPTY

0.01UF

X5R

10%

201

10V

2

1

C0906

SIGNAL_MODEL=EMPTY

10%

0.01UF

201

10V X5R

21

R0926

SIGNAL_MODEL=EMPTY

201

51

5%

1/20W

MF

2

1

C0907

SIGNAL_=EMPTY

X5R 201

0.01UF

10% 10V

21

R0927

SIGNAL_MODEL=EMPTY

51

1/20W

5% MF

201

2

1

C0901

SIGNAL_MODEL=EMPTY

0.01UF

10% 10V X5R 201

21

R0921

SIGNAL_MODEL=EMPTY

MF

51

1/20W

201

5%

21

R0922

SIGNAL_MODEL=EMPTY

51

5%

1/20W

201

MF

2

1

C0902

SIGNAL_MODEL=EMPTY

0.01UF

10V 201

10% X5R

21

R0923

SIGNAL_MODEL=EMPTY

1/20W

5%

51

201

MF

2

1

C0903

SIGNAL_MODEL=EMPTY

10V 201

10% X5R

0.01UF

2

1

C0904

SIGNAL_MODEL=EMPTY

0.01UF

10V 201

10% X5R

21

R0924

SIGNAL_MODEL=EMPTY

5%

1/20W

MF

51

201

2

1

C0911

SIGNAL_MODEL=EMPTY

X5R

10%

201

0.01UF

10V

2

1

C0910

SIGNAL_MODEL=EMPTY

0.01UF

X5R

10V

10%

201

SM

1

SH0936

1.4DIA-SHORT-EMI-MLB-M97-M98

Signal Aliases

SYNC_MASTER=K17_MLB

SYNC_DATE=04/26/2010

PP15V_T29

FW643_WAKE_L

GND

MAKE_BASE=TRUE

PEG_CLKREQ_L

PPBUS_G3H

GND_CHASSIS_AUDIO_JACK

GND

USB_T29A_P

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

TP_ENET_CR_PWREN

TP_SDCONN_WP

VOLTAGE=5V

PP5V_S0_AUDIO_AMP_L

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

DP_A_BIAS_N_2

T29_A_BIAS_R

JTAG_ISP_TDI

JTAG_ISP_TCK

DP_A_BIAS_N_0

LCD_BKLT_EN

LVDS_IG_PANEL_PWR

EG_RESET_L

JTAG_ISP_TDO

MAKE_BASE=TRUE

JTAG_ISP_TDO

JTAG_ISP_TCK

T29_LSEO_LSOE2 T29_LSEO_LSOE2

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

T29_LSEO_LSOE3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_T29_R2D_CN<2..3>

NO_TEST=TRUE

NC_T29_D2RN<2..3>

MAKE_BASE=TRUE

NC_T29_R2D_CP<2..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_T29_D2RP<2..3>

MAKE_BASE=TRUE

PCIE_T29_R2D_C_N<3..0>

MAKE_BASE=TRUE

PCIE_T29_R2D_C_P<3..0>

T29_LSEO_LSOE2

T29_LSEO_LSOE3

PCIE_T29_D2R_N<3..0>

MAKE_BASE=TRUE

=PEG_D2R_N<11..8>

MAKE_BASE=TRUE

PCIE_T29_D2R_P<3..0>

=PEG_D2R_P<11..8>

MAKE_BASE=TRUE

JTAG_ISP_TCK

DP_IG_HPD

MAKE_BASE=TRUE

DP_IG_DDC_DATA DP_IG_DDC_DATA

DP_IG_DDC_CLK

MAKE_BASE=TRUE

DP_IG_DDC_CLK

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

MAKE_BASE=TRUE

DP_IG_AUX_CH_N

NC_ISNS_PVTTS0PCH_P

MAKE_BASE=TRUE

NC_ISNS_PVTTS0PCH_P

MAKE_BASE=TRUE

NC_ISNS_PVTTS0PCH_N NC_ISNS_PVTTS0PCH_N

NC_ISNS_P3V3S0MPCH_N

MAKE_BASE=TRUE

NC_ISNS_P3V3S0MPCH_N

MAKE_BASE=TRUE

NC_ISNS_P3V3S0MPCH_P NC_ISNS_P3V3S0MPCH_P

NC_ISNS_P1V05S0PCH_P

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_P

NC_ISNS_P1V05S0PCH_N

MAKE_BASE=TRUE

NC_ISNS_P1V05S0PCH_N

USB_EXTC_OC_L

MAKE_BASE=TRUE

USB_EXTC_OC_L

USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXCARD_P USB_EXCARD_P

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM TP_LVDS_IG_BKL_PWM

EXCARD_OC_L

MAKE_BASE=TRUE

EXCARD_OC_L

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN TP_LVDS_IG_B_CLKN

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

NC_LVDS_IG_B_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_XTALOUT NC_GPU_XTALOUT

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

TP_CPU_VTT_SELECT

MAKE_BASE=TRUE

TP_CPU_VTT_SELECT

TP_ENET_CR_PWREN

PP5V_S0_AUDIO_AMP_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm

FW_PLUG_DET_L

MAKE_BASE=TRUE

FW643_WAKE_L

MAKE_BASE=TRUE

TP_SDCONN_WP

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

TP_SDCONN_CMD

TP_LVDS_MUX_SEL_EG

GND

TP_SDCONN_CMD

PP5V_S0_AUDIO

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

MAKE_BASE=TRUE

TP_SDCONN_CLK TP_SDCONN_CLK

MAKE_BASE=TRUE

TP_SDCONN_DATA<0..7>

SDCONN_DATA<0..7>

FW_PLUG_DET_L

GND

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

EG_RESET_L

MAKE_BASE=TRUE

=PEG_R2D_C_N<15..12>

=PEG_R2D_C_P<15..12>

=PEG_D2R_N<15..12>

=PEG_D2R_P<15..12>

=PEG_D2R_P<7..0>

PEG_D2R_P<7..0>

MAKE_BASE=TRUE

=PEG_D2R_N<7..0>

PEG_D2R_N<7..0>

MAKE_BASE=TRUE

=PEG_R2D_C_P<7..0>

MAKE_BASE=TRUE

PEG_R2D_C_P<7..0>

=PEG_R2D_C_N<7..0>

NC_PEG_D2R_N<15..12>

MAKE_BASE=TRUE

NC_PEG_R2D_C_P<15..12>

NC_PEG_R2D_C_N<15..12>

MAKE_BASE=TRUE

GFX_VID<0..6>

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

LVDS_IG_BKL_ON

CPUIMVP_VID<0..6>

MEMVTT_EN

GFXIMVP_VID<0..6>

MAKE_BASE=TRUE

CPU_VID<0..6>

MAKE_BASE=TRUE

PEG_R2D_C_N<7..0>

PEX_CLKREQ_L

LCD_BKLT_EN

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

GND

PEG_CLKREQ_L

MAKE_BASE=TRUE

MEMVTT_EN

MAKE_BASE=TRUE

T29_A_BIAS_R2D_P0

T29_A_BIAS_R2D_N0

T29_A_BIAS_R2D_P1

T29_A_BIAS_R2D_N1

T29_A_BIAS_R

DP_IG_AUX_CH_P

MAKE_BASE=TRUE

NC_PEG_D2R_P<15..12>

MAKE_BASE=TRUE

TP_SDCONN_DETECT_L

GND

TP_SDCONN_DETECT_L

=PEG_R2D_C_N<11..8>

=PEG_R2D_C_P<11..8>

DP_IG_HPD

MAKE_BASE=TRUE

T29_A_BIAS_D2R_P1

T29_A_BIAS_D2R_N1

T29_A_BIAS_R

T29_LSEO_LSOE3

T29_R2D_C_N<2..3>

T29_D2R_N<2..3>

DP_A_BIAS_P_2 DP_A_BIAS_P_0

T29_D2R_P<2..3>

MAKE_BASE=TRUE

JTAG_ISP_TDI

T29_R2D_C_P<2..3>

MAKE_BASE=TRUE

PEX_CLKREQ_L

USB_T29A_N

PP3V3_S3

PP5V_S0

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.11MM

9 OF 132 8 OF 105

7

35 86

8

38 39

8

16 88

6 7

35 39 49 50 63 64 90

61

24 94

8

18 88

8

36

8

36

60

6

85

8

86

8

86

8

19 33 88

8

19 23 33 88

6

85

8

88 90

8

18 88

8

74 88

8

19 33 88

8

19 33 88

8

19 23 33 88

8

33

33 95

8

33

8

33

33 95

9

33 95

9

8

19 23 33 88

8

17 84

8

17 80 84

8

17 80 84

8

17 80 84

8

17 80 84

8

17 84 94

8

17 84 94

8

17 84 94

8 8

8

24 43

8

24 43

8

24 32

100

8

24 32

100

8

24 32

100

8

24 32

100

6 8

18

6 8

18

8

24 32

8

24 32

6 8

18

6 8

18

6 8

18

6 8

18

8

18

8

18

8

18

8

18

8

18 94

8

18 94

8 8

8

18 94

8

18 94

8

92

8

92

8

36

60

8

19 39

8

38 39

8

36

8

74 82 87 88 91

8

36

8

88

8

36

57

8

36

8

36

8

19 39

8

88

8

74 88

9

74 92

9

74 92

9

74 92

9

92

8

74 82 87 88 91

8

18 88

8

29 67

92

74 92

8

80 88

8

88 90

8

18 88

8

18 88

8

16 88

8

29 67

6

85

6

85

6

85

6

85

8

86

8

86

8

86

8

17 84 94

9

8

36

8

36

9

8

17 84

86

8

86

8

33

97

6

85

6

85

97

8

19 33 88

97

8

80 88

24 94

6 7

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7

22 41 47 52 54 65 68 69 70 73 87

104 105

IN IN IN IN

IN

OUT

IN

IN IN IN IN IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT OUT OUT

OUT

EDP_HPD

EDP_COMPIO

EDP_ICOMPO

EDP_AUX*

EDP_AUX

EDP_TX_3

EDP_TX_2

EDP_TX_1

EDP_TX_0

EDP_TX_3*

EDP_TX_2*

EDP_TX_1*

EDP_TX_0*

DMI_TX_3*

FDI1_LSYNC

FDI0_LSYNC

FDI_TX_3

FDI0_FSYNC FDI1_FSYNC

FDI_INT

FDI_TX_1

FDI_TX_0

FDI_TX_2

FDI_TX_3*

FDI_TX_2*

FDI_TX_1*

DMI_TX_1* DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI_TX_0*

DMI_RX_2*

DMI_RX_0 DMI_RX_1 DMI_RX_2 DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO

PEG_RX_2*

PEG_RX_0* PEG_RX_1*

PEG_RX_3* PEG_RX_4* PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8* PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0 PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7 PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11 PEG_RX_12 PEG_RX_13 PEG_RX_14 PEG_RX_15

PEG_TX_1* PEG_TX_2*

PEG_TX_0*

PEG_TX_3* PEG_TX_4* PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8* PEG_TX_9*

PEG_TX_11* PEG_TX_12* PEG_TX_13* PEG_TX_14* PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2 PEG_TX_3 PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7 PEG_TX_8

PEG_TX_9 PEG_TX_10 PEG_TX_11 PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

FDI_TX_4* FDI_TX_5* FDI_TX_6* FDI_TX_7*

FDI_TX_4 FDI_TX_5 FDI_TX_6 FDI_TX_7

(SYM 1 OF 11)

DMI

EMBEDDED DISPLAY PORT

PCI EXPRESS BASED INTERFACE SIGNALS

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

RSVD_96

RSVD_95

RSVD_94

RSVD_93

RSVD_92

RSVD_91

RSVD_90

RSVD_97

RSVD_38 RSVD_39

RSVD_40

RSVD_36

RSVD_41 RSVD_42 RSVD_43

RSVD_45

RSVD_44

RSVD_48 RSVD_49 RSVD_50

RSVD_47

RSVD_46

RSVD_53

RSVD_52

RSVD_51

RSVD_55

RSVD_54

RSVD_57

RSVD_59 RSVD_60

RSVD_58

RSVD_56

RSVD_61

RSVD_63

RSVD_62

RSVD_65

RSVD_64

RSVD_66 RSVD_67

RSVD_69 RSVD_70

RSVD_68

RSVD_71 RSVD_72

RSVD_79 RSVD_80 RSVD_81

RSVD_78

RSVD_82 RSVD_83 RSVD_84

RSVD_86

RSVD_85

RSVD_89

RSVD_88

RSVD_87

CFG_4

CFG_3

CFG_2

CFG_1

CFG_0

CFG_9

CFG_8

CFG_7

CFG_6

CFG_5

CFG_14

CFG_13

CFG_12

CFG_11

CFG_10

CFG_15 CFG_16 CFG_17

RSVD_1

RSVD_5 RSVD_6

RSVD_4

RSVD_3

RSVD_2

RSVD_10 RSVD_11

RSVD_9

RSVD_8

RSVD_7

RSVD_15 RSVD_16

RSVD_14

RSVD_13

RSVD_12

RSVD_20

RSVD_19

RSVD_18

RSVD_17

RSVD_25 RSVD_26

RSVD_24

RSVD_22 RSVD_23

RSVD_31

RSVD_30

RSVD_29

RSVD_28

RSVD_27

RSVD_32 RSVD_33 RSVD_34

RSVD_35

(5 OF 11)

RESERVED

OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

IN IN

IN

IN IN

BI BI

NC NC NC NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

NC NC NC

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC NC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS

(IPU)

10K PU disables eDP HPD

FOR SANDYBRIDGE PROCESSOR

(IPU)

(IPU) (IPU)

(IPU)

Intel is investigating processor driven VREF_DQ generation.

(IPU)

(DDR_VREF0) (DDR_VREF1)

(THERMDA) (THERMDC)

NOTE:

This connection is to support the same.

(IPU)

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

CPU_CFG<4> should be pulled down to enable EDP

These can be Placed close to J2500 and Only for debug access

6

17 92

6

17 92

6

17 92

6

17 92

6

17 92

6

17 92

6

17 92

6

17 92

8

1% MF-LF

402

1/16W

24.9

R1010

1

2

BGA

SANDY-BRIDGE

MOBILE-REV1

OMIT

U1000

N8

N10

T9

R10

R6

R8

U8

U10

N2

N4

R2

R4

P3

P1

T5

U6

AE4 AE2

AC2

AE8

AB1

AG4

AG2

AF3

AF1

AF7

AE6

AG8

AG6

AC8

AB7

AA2

AB3

AD9

W6

V7

W10

W8

Y9

AA8

AA10

AC10

U2

U4

W4

W2

V3

V1

AA6

Y5

G2 H1 F3

G22

F23

K23

H23

F11

H11

K11

J12

F9

E8

H9

G10

H7

J8

G6

F7

K21

H21

F19

H19

K19

J20

H17

G18

K15

K17

G14

F15

J16

H15

K13

H13

C22

A22

D23

B23

B13

D13

C10

A10

D11

B11

B9

D9

D7

B7

F13

E12

A18

C18

B21

D21

D19

B19

F21

E20

C14

A14

B17

D17

D15

B15

F17

E16

SANDY-BRIDGE

BGA

MOBILE-REV1

OMIT

U1000

B57 D57

F55 K55 F57 E58 H57 H55 D53 K57

B55 A54 A58 D55 C56 E54 J54 G56

BB17

AW46 BG26 BB25 BG34 BH35 BJ34 BF35 BF41 BH43 BJ42

AY17

BF43

AW50 BB57 BF63

AD5 AH5 AJ6

BF3 BG4

BD29

BD19 AY45 AY41 BG62 BB43

D49 B53

G52 G64

BD33

AJ10

BE6 AA4 AC4 AC6

C52

D3

C4 C24 D25

BC30

B25

K47 H47

F5 K9 H5 L10 G4 K7 K5

BE32

M9 L6 J2 L2 P7 M5 J4 L4 N6

G48

AW42

K49 H49 J50

AY13 BB13

BA48

BB15 AY15 AW14 BD13 BA16 BE16 BD15 BC14 BF19 BH19

BC42

BF21 BH21 BF23 BH23 BF25 BH25 BJ22 BG22

1K

1/16W

402

MF-LF

1%

R1020

1

2

1K

402

MF-LF

1/16W

1%

R1022

1

2

402

1/16W

0

5%

MF-LF

NOSTUFF

R1021

1 2

0

5%

MF-LF

1/16W

402

NOSTUFF

R1023

1 2

17 92

1/16W

1%

402

24.9

MF-LF

PLACE_NEAR=U1000.AB1:12.7mm

R1030

1

2

MF-LF 402

1% 1/16W

10K

R1031

1

2

51

100

51

100

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1047

1

2

MF-LF

402

5%

1/16W

1K

NOSTUFF

R1046

1

2

1K

MF-LF

402

5%

1/16W

R1045

1

2

5% 1/16W MF-LF

1K

402

EDP

R1044

1

2

1K

MF-LF

402

1/16W

5%

NOSTUFF

R1042

1

2

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1040

1

2

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1041

1

2

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1043

1

2

NOSTUFF

1K

402

5%

MF-LF

1/16W

R1049

1

2

CPU DMI/PEG/FDI/RSVD

CPU_EDP_COMP

TP_EDP_TX_N<2>

CPU_CFG<7>

CPU_CFG<16> CPU_CFG<3> CPU_CFG<1> CPU_CFG<0>

CPU_CFG<6>

NC_PEG_R2D_C_P<14>

CPU_CFG<5>

TP_EDP_AUX_N

TP_EDP_TX_N<3>

TP_EDP_TX_N<1>

FDI_DATA_N<2>

FDI_DATA_N<6>

FDI_DATA_P<5>

CPU_CFG<2>

CPU_CFG<5> CPU_CFG<6>

CPU_CFG<8>

CPU_CFG<7>

NC_PEG_D2R_P<12>

=PEG_D2R_P<3>

CPU_MEM_VREFDQ_B

=PEG_D2R_P<10>

=PEG_D2R_P<4>

=PEG_D2R_P<1> =PEG_D2R_P<2>

CPU_MEM_VREFDQ_A

=PEG_R2D_C_N<4>

FDI_DATA_P<3>

=PEG_R2D_C_P<9>

=PEG_R2D_C_P<7>

NC_PEG_D2R_N<13>

FDI_DATA_P<4>

DMI_N2S_P<0>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<6>

CPU_THERMD_N

CPU_THERMD_P

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<3>

NC_PEG_R2D_C_N<14>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<7>

FDI_DATA_P<7>

FDI_DATA_N<5>

FDI_DATA_N<0>

NC_PEG_R2D_C_N<15>

TP_EDP_AUX_P

NC_PEG_D2R_P<13>

=PEG_R2D_C_N<11>

=PEG_D2R_P<9>

=PEG_D2R_P<11>

=PEG_R2D_C_P<10>

NC_PEG_R2D_C_N<12>

=PEG_R2D_C_P<4>

NC_PEG_R2D_C_P<12>

NC_PEG_D2R_P<14>

=PEG_R2D_C_P<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<10>

CPU_CFG<1>

CPU_CFG<10>

CPU_CFG<4>

=PEG_R2D_C_P<1>

FDI_DATA_N<1>

DMI_S2N_P<1>

=PEG_D2R_P<6>

PP0V75_S3_MEM_VREFDQ_B

DMI_S2N_P<3>

DMI_N2S_N<1>

NC_PEG_R2D_C_P<15>

PP0V75_S3_MEM_VREFDQ_A

DMI_N2S_N<0>

DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

FDI_DATA_N<3>

FDI_DATA_N<7>

FDI_DATA_P<6>

FDI_DATA_P<2>

FDI_DATA_P<1>

FDI_DATA_P<0>

DMI_N2S_N<3>

DMI_S2N_P<0>

DMI_S2N_N<0>

CPU_CFG<12>

CPU_CFG<16>

CPU_CFG<9>

CPU_CFG<0>

CPU_CFG<17>

=PEG_R2D_C_P<8>

=PEG_R2D_C_N<5>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<13>

CPU_CFG<11>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<5> =PEG_R2D_C_P<6>

=PEG_R2D_C_P<11>

NC_PEG_R2D_C_P<13>

CPU_CFG<2>

CPU_CFG<4>

FDI_DATA_N<4>

DMI_N2S_N<2>

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_P<2>

NC_PEG_D2R_N<14>

=PEG_D2R_P<5>

=PEG_D2R_P<0>

NC_PEG_D2R_N<15>

=PEG_D2R_N<8> =PEG_D2R_N<9> =PEG_D2R_N<10> =PEG_D2R_N<11>

=PEG_D2R_N<7>

NC_PEG_D2R_N<12>

DMI_S2N_N<2>

NC_PEG_R2D_C_N<13>

TP_EDP_TX_N<0>

CPU_CFG<3>

=PEG_D2R_N<4>

=PEG_D2R_N<0>

CPU_PEG_COMP

NC_PEG_D2R_P<15>

=PEG_R2D_C_N<0> =PEG_R2D_C_N<1>

FDI_LSYNC<1>

PP1V05_S0

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

=PEG_D2R_P<8>

PP1V05_S0

=PEG_D2R_N<1> =PEG_D2R_N<2> =PEG_D2R_N<3>

=PEG_D2R_N<5> =PEG_D2R_N<6>

FDI_LSYNC<0>

TP_EDP_TX_P<0> TP_EDP_TX_P<1> TP_EDP_TX_P<2> TP_EDP_TX_P<3>

CPU_EDP_HPD

=PEG_D2R_P<7>

10 OF 132

9 OF 105

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

9

23 92

28 30

26 30

23

9

23 92

9

23 92

23

23 92

9

23 92

9

23 92

9

23 92

92

7 9

10 12 13

14 23

35 39 45 68

70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

6

BI BI BI BI BI

IN

OUT

IN IN

OUT

BI

DDR3 MISC

PWR MGMT

JTAG & BPM

CLOCKS

THERMAL

(2 OF 11)

PROC_SELECT*

PROC_DETECT*

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_VREF

SM_DRAMRST*

SM_DRAMPWROK

PM_SYNC

PREQ*

TMS

TRST*

TDI TDO

DBR*

BPM_0* BPM_1* BPM_2* BPM_3* BPM_4* BPM_5* BPM_6* BPM_7*

TCK

PRDY*

BCLK_ITP

BCLK_ITP*

UNCOREPWRGOOD

RESET*

THERMTRIP*

CATERR*

PECI

PROCHOT*

BCLK

BCLK*

DPLL_REF_CLK

DPLL_REF_CLK*

NC

OUT

BI

IN

OUT

IN IN

IN

OUT

IN

IN IN

IN

OUT

BI BI BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

R1120 and R1121 are Intel recommended values

Unused eDP CLK

(IPU)

(IPD)

(IPU) (IPU)

(IPU)

23 92

PLACE_NEAR=U1800.AY11:157mm

402

1/16W

5%

10K

MF-LF

R1111

1

2

17 29 92

19 23 92

29

16 92

17 92

19 92

19 45 92

1/16W MF-LF

1%

402

75

R1126

1

2

SANDY-BRIDGE

OMIT

BGA

MOBILE-REV1

U1000

D5 C6

K63 K65

C62 D61 E62 F63 D59 F61 F59 G60

H53

H61

AJ4 AJ2

F53

K53

J62 H65

B59

AH9

H51

K51

AY25

BE24

BJ46 BG46 BF45

BJ44

J58

K61 K59

F51

H59 H63

C60

PLACE_NEAR=U1000.BF45:12.7mm

1/16W

200

402

MF-LF

1%

R1114

1

2

PLACE_NEAR=U1000.BG46:12.7mm

MF-LF

1/16W

402

25.5

1%

R1113

1

2

402

1/16W MF-LF

140

1%

PLACE_NEAR=U1000.BJ46:12.7mm

R1112

1

2

92

1/16W

402

5%

MF-LF

68

R1101

1

2

1/16W

PLACE_NEAR=U1000.BJ44:2.54mm

NOSTUFF

402

MF-LF

100

1%

R1130

1

2

NOSTUFF

PLACE_NEAR=U1000.BJ44:2.54mm

MF-LF

402

1/16W

100

1%

R1131

1

2

NOSTUFF

PLACE_NEAR=U1000.BJ44:2.54mm

X5R 402

10%

0.1UF

16V

C1130

1

2

MF-LF 402

1K

5% 1/16W

R1141

1

2

1K

5% 1/16W MF-LF 402

R1140

1

2

402

5%

56

1/16W MF-LF

R1103

12

46 68 92

NOSTUFF

201

1/20W

MF

1K

5%

R1100

1

2

23 92

1%

402

MF-LF

1/16W

200

PLACE_NEAR=R1121.2:1mm

R1120

1

2

402

1%

MF-LF

1/16W

PLACE_NEAR=U1000.AY25:51.562mm

130

R1121

12

16 92

17 92

5% 1/16W

NOSTUFF

402

MF-LF

51

R1104

1

2

1%

402

43.2

MF-LF

1/16W

R1125

12

23 25

201

1/20W MF

NOSTUFF

1K

5%

R1102

1

2

23 25 92

23 92

CPU CLOCK/MISC/JTAG

PM_MEM_PWRGD_R

CPU_SM_RCOMP<2>

CPU_PROCHOT_R_L

CPU_PECI

PLT_RST_CPU_BUF_L

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

PP1V05_S0

PLT_RESET_LS1V1_L

PP1V5_S3RS0_CPUDDR

PM_THRMTRIP_L

CPU_PROC_SEL_L

CPU_CATERR_L

XDP_BPM_L<0>

XDP_CPU_PRDY_L

XDP_BPM_L<1>

XDP_DBRESET_L

XDP_CPU_TDO

XDP_CPU_TRST_L

XDP_CPU_PREQ_L

ITPCPU_CLK100M_N

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TDI

XDP_BPM_L<5>

CPU_PROCHOT_L

PP1V05_S0

DMI_CLK100M_CPU_N

DMI_CLK100M_CPU_P

PP1V05_S0_CPU_VCCPQE

ITPCPU_CLK100M_P

DPLL_REF_CLK_L

DPLL_REF_CLK

PM_SYNC

CPU_PWRGD

CPU_MEM_RESET_L

CPU_SM_RCOMP<0> CPU_SM_RCOMP<1>

PP1V05_S0

PM_MEM_PWRGD

CPU_DDR_VREF

PP1V5_S3RS0_CPUDDR

11 OF 132 10 OF 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

7

10 13 15 29 73

104

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

7

12 14

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

7

10 13 15 29 73

104

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT

SA_CAS* SA_RAS* SA_WE*

SA_DQ_63

SA_DQ_62

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_BS_2

SA_BS_1

SA_BS_0

SA_DQ_47 SA_DQ_48 SA_DQ_49

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_51

SA_DQ_50

SA_DQ_37 SA_DQ_38 SA_DQ_39 SA_DQ_40 SA_DQ_41 SA_DQ_42 SA_DQ_43 SA_DQ_44 SA_DQ_45 SA_DQ_46

SA_DQ_36

SA_DQ_32 SA_DQ_33

SA_DQ_27 SA_DQ_28 SA_DQ_29 SA_DQ_30 SA_DQ_31

SA_DQ_34 SA_DQ_35

SA_DQ_26

SA_DQ_16 SA_DQ_17 SA_DQ_18 SA_DQ_19 SA_DQ_20 SA_DQ_21 SA_DQ_22 SA_DQ_23 SA_DQ_24 SA_DQ_25

SA_DQ_10 SA_DQ_11 SA_DQ_12 SA_DQ_13 SA_DQ_14 SA_DQ_15

SA_DQ_9

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_1 SA_DQ_2 SA_DQ_3 SA_DQ_4 SA_DQ_5

SA_DQ_0

SA_CK_1

SA_CK_0

SA_CKE_1

SA_CKE_0

SA_CK_1*

SA_CK_0*

SA_CS_1*

SA_CS_0*

SA_ODT_1

SA_ODT_0

SA_DQS_0* SA_DQS_1* SA_DQS_2* SA_DQS_3* SA_DQS_4* SA_DQS_5* SA_DQS_6* SA_DQS_7*

SA_DQS_0 SA_DQS_1

SA_DQS_3

SA_DQS_2

SA_DQS_5

SA_DQS_4

SA_DQS_6 SA_DQS_7

SA_MA_0 SA_MA_1

SA_MA_3

SA_MA_2

SA_MA_5

SA_MA_4

SA_MA_6 SA_MA_7 SA_MA_8 SA_MA_9

SA_MA_11

SA_MA_10

SA_MA_12

SA_MA_14

SA_MA_13

SA_MA_15

MEMORY CHANNEL A

(SYM 3 OF 11)

SB_CK_1*

SB_DQ_33

SB_CAS* SB_RAS* SB_WE*

SB_BS_0 SB_BS_1 SB_BS_2

SB_CK_0

SB_CK_0*

SB_CK_1

SB_CKE_0

SB_CKE_1

SB_DQ_0 SB_DQ_1

SB_DQ_10 SB_DQ_11 SB_DQ_12 SB_DQ_13 SB_DQ_14 SB_DQ_15 SB_DQ_16 SB_DQ_17 SB_DQ_18 SB_DQ_19

SB_DQ_2

SB_DQ_20 SB_DQ_21 SB_DQ_22 SB_DQ_23 SB_DQ_24 SB_DQ_25 SB_DQ_26 SB_DQ_27 SB_DQ_28 SB_DQ_29

SB_DQ_3

SB_DQ_30 SB_DQ_31 SB_DQ_32

SB_DQ_34 SB_DQ_35 SB_DQ_36 SB_DQ_37 SB_DQ_38 SB_DQ_39

SB_DQ_4

SB_DQ_40 SB_DQ_41 SB_DQ_42 SB_DQ_43 SB_DQ_44 SB_DQ_45 SB_DQ_46 SB_DQ_47 SB_DQ_48 SB_DQ_49

SB_DQ_5

SB_DQ_50 SB_DQ_51 SB_DQ_52 SB_DQ_53 SB_DQ_54 SB_DQ_55 SB_DQ_56 SB_DQ_57 SB_DQ_58 SB_DQ_59

SB_DQ_6

SB_DQ_60 SB_DQ_61 SB_DQ_62 SB_DQ_63

SB_DQ_7 SB_DQ_8 SB_DQ_9

SB_CS_0* SB_CS_1*

SB_ODT_1

SB_ODT_0

SB_DQS_0* SB_DQS_1* SB_DQS_2* SB_DQS_3* SB_DQS_4* SB_DQS_5* SB_DQS_6* SB_DQS_7*

SB_DQS_0

SB_DQS_2

SB_DQS_1

SB_DQS_3 SB_DQS_4 SB_DQS_5

SB_DQS_7

SB_DQS_6

SB_MA_1

SB_MA_0

SB_MA_2 SB_MA_3 SB_MA_4 SB_MA_5 SB_MA_6

SB_MA_8

SB_MA_7

SB_MA_10 SB_MA_11

SB_MA_9

SB_MA_13

SB_MA_12

SB_MA_15

SB_MA_14

(SYM 4 OF 11)

MEMORY CHANNEL B

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

27 93

26 27 93

27 93

26 93

27 93

27 28 93

27 93

28 93

SANDY-BRIDGE

MOBILE-REV1

BGA

OMIT

U1000

BA36 BC38 BB19

BE44

BB31 BA32

AW34 AY33

BC18

BD17

BD41 BD45

AL6 AL8

AV7 AY5 AT5 AR6 AW6 AT9 BA6 BA8 BG6 AY9

AP7

AW8 BB7 BC8

BE4 AW12 AV11 BB11 BA12

BE8 BA10

AM5

BD11 BE12 BB49 AY49 BE52 BD51 BD49 BE48 BA52 AY51

AK7

BC54 AY53 AW54 AY55 BD53 BB53 BE56 BA56 BD57 BF61

AL10

BA60 BB61 BE60 BD63 BB59 BC58 AW58 AY59 AL60 AP61

AN10

AW60 AY57 AN60 AR60

AM9 AR10

AR8

AN6

AN8

AU8

AU6

BD5

BC6

BC10

BD9

BB51

BC50

BD55

BB55

BD61

BD59

AV61

AU60

BD27 BA28

AW38 AW22 BA20 BB45 BE20 AW18

BB27 AW26 BB23 BA24 AY21 BD21 BC22 BB21

BB41 BC46

BE36 BA44

BGA

MOBILE-REV1

SANDY-BRIDGE

OMIT

U1000

BJ38 BD37 AY29

BH39

BF33 BH33

BF37 BH37

BD25

BJ26

BE40 BH41

AL4 AK3

BA4 BB1 AV1 AU2 BA2 BB3 BC2

BF7 BF11 BJ10

AP3

BC4

BH7 BH11 BG10 BJ14 BG14 BF17 BJ18 BF13 BH13

AR2

BH17 BG18 BH49 BF47 BH53 BG50 BF49 BH47 BF53 BJ50

AL2

BF55 BH55 BJ58 BH59 BJ54 BG54 BG58 BF59 BA64 BC62

AK1

AU62 AW64 BA62 BC64 AU64 AW62 AR64 AT65 AL64 AM65

AP1

AR62 AT63 AL62 AM63

AR4

AV3

AU4

AN2

AN4

AW4

AW2

BF9

BH9

BH15

BF15

BH51

BF51

BF57

BH57

AY65

AY63

AN64

AN62

BF31 BH31

AY37 BJ30 AW30 BA40 BB29 BE28

BB37 BC34 BF27 BB33 BH27 BG30 BH29 BF29

BG42 BH45

BG38 BF39

26 93

26 27 93

27 93

26 93

28 93

27 28 93

27 93

27 28 93

27 93

28 93

SYNC_DATE=04/26/2010

CPU DDR3 INTERFACES

MEM_B_DQS_N<2>

MEM_B_A<15>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

MEM_B_DQS_P<7>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<7>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<4>

MEM_B_DQS_N<3>

MEM_B_DQS_N<1>

MEM_B_DQS_N<0>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_DQ<1>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<5>

MEM_B_DQ<7>

MEM_B_DQ<9>

MEM_B_CKE<1>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_BA<0>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<8>

MEM_B_DQ<6>

MEM_B_DQ<4>

MEM_B_DQ<0>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<56>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<38>

MEM_A_DQ<24>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_A<15>

MEM_A_A<13> MEM_A_A<14>

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12>

MEM_A_A<8> MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<5> MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_DQS_P<7>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<2>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQS_N<7>

MEM_A_DQS_N<6>

MEM_A_DQS_N<5>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<2>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_CKE<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_DQ<0>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<6> MEM_A_DQ<7> MEM_A_DQ<8> MEM_A_DQ<9>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<25>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<26>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<36>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<37>

MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52>

MEM_A_DQ<55>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_BA<0> MEM_A_BA<1> MEM_A_BA<2>

MEM_A_DQ<57> MEM_A_DQ<58>

MEM_A_DQ<62> MEM_A_DQ<63>

MEM_A_WE_L

MEM_A_RAS_L

MEM_A_CAS_L

12 OF 132 11 OF 105

(9 OF 11)

VIDALERT*

VCCSA_14 VCCSA_15 VCCSA_16

VCCSA_8

VCCIO_SEL

VCCPQE_3

VCCPQE_2

VCCPQE_1

VCCPQE_0

VCCPLL_2

VCCPLL_1

VCCPLL_0

VCCDQ_3

VCCDQ_2

VCCDQ_1

VCCDQ_0

VCCSA_1

VCCSA_0

VCCSA_3 VCCSA_4

VCCSA_2

VCCSA_5 VCCSA_6 VCCSA_7

VCCSA_9 VCCSA_10 VCCSA_11 VCCSA_12 VCCSA_13

VCCSA_17

VIDSOUT VIDSCLK

VCCSA_VID_0

VCC_SENSE

VCCSA_VID_1

VAXG_SENSE

VSS_SENSE

VSSAXG_SENSE

VCCIO_SENSE

VDDQ_SENSE

VSS_SENSE_VCCIO

VCCSA_SENSE

VSS_SENSE_VDDQ

VCC_VAL_SENSE

VCC_DIE_SENSE

VAXG_VAL_SENSE

VSS_VAL_SENSE

VSSAXG_VAL_SENSE

VSS_NCTF_0 VSS_NCTF_1 VSS_NCTF_2

VSS_NCTF_4

VSS_NCTF_3

VSS_NCTF_6

VSS_NCTF_5

VSS_NCTF_7

VSS_NCTF_9

VSS_NCTF_8

VSS_NCTF_11

VSS_NCTF_10

VSS_NCTF_12 VSS_NCTF_13 VSS_NCTF_14 VSS_NCTF_15

DC_TEST_D65

DC_TEST_D1

DC_TEST_C64

DC_TEST_C2

DC_TEST_BJ64

DC_TEST_BJ62

DC_TEST_BJ4

DC_TEST_BJ2

DC_TEST_BH65

DC_TEST_BH63

DC_TEST_BH3

DC_TEST_BH1

DC_TEST_BG64

DC_TEST_BG2

DC_TEST_BF65

DC_TEST_BF1

DC_TEST_B65

DC_TEST_B63

DC_TEST_B3

DC_TEST_A64

DC_TEST_A62

DC_TEST_A4

CORE POWER

(6 OF 11)

VCC_54 VCC_55 VCC_56 VCC_57 VCC_58

VCC_63

VCC_62

VCC_61

VCC_59 VCC_60

VCC_64 VCC_65 VCC_66 VCC_67 VCC_68

VCC_73

VCC_72

VCC_71

VCC_69 VCC_70

VCC_74 VCC_75 VCC_76 VCC_77 VCC_78 VCC_79

VCC_83

VCC_82

VCC_81

VCC_80

VCC_84 VCC_85 VCC_86 VCC_87 VCC_88 VCC_89

VCC_93

VCC_92

VCC_90 VCC_91

VCC_94 VCC_95 VCC_96 VCC_97 VCC_98 VCC_99

VCC_104

VCC_103

VCC_102

VCC_101

VCC_100

VCC_105 VCC_106 VCC_107

VCC_4

VCC_3

VCC_2

VCC_1

VCC_0

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_16

VCC_15

VCC_17 VCC_18 VCC_19 VCC_20 VCC_21 VCC_22 VCC_23 VCC_24 VCC_25 VCC_26 VCC_27 VCC_28 VCC_29 VCC_30 VCC_31 VCC_32 VCC_33 VCC_34 VCC_35 VCC_36 VCC_37 VCC_38 VCC_39 VCC_40 VCC_41 VCC_42 VCC_43 VCC_44 VCC_45 VCC_46 VCC_47 VCC_48 VCC_49 VCC_50 VCC_51 VCC_52 VCC_53

OUT OUT

OUT

BI

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

HR_PPDG sections 6.2.1 and 6.3.1.

(IPU)

For Future Compatibility

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side. NOTE: Intel validation sense lines per doc 439028 rev1.0

BGA

OMIT

MOBILE-REV1

SANDY-BRIDGE

U1000

A4 A62 A64 B3 B63 B65 BF1 BF65 BG2 BG64 BH1 BH3 BH63 BH65 BJ2 BJ4 BJ62 BJ64 C2 C64 D1 D65

F49

B49

F47

B47

D47

AV23 AT23 AP23 AL23

AJ8

AW10

AK65 AK63 AK61

AV21 AT21 AP21 AL21

W17 W15

N16 N14 M17 M15 M12 M11 L18 L14

W12 U17 U15 U12 T16 T14 T11 N18

K3

AE10 AG10

AY19

B51

D51

A50

BJ60 BJ6

E64 E2 B61 B5 A60 A6

BH61 BH5 BE64 BE2 BD65 BD1 F65 F1

A46

AU10

AW20

C48

E50

A48

OMIT

SANDY-BRIDGE

MOBILE-REV1

BGA

U1000

R46 R42

N43

B29 A44 A40 A38 A34 A32 A28 A26

N39 N37 N33 N30 N26 N24 N20 M46 M42

R40

M40 M36 M34 M29 M27 M23 M21 L44 L40 L38

R36

L34 L32 L28 L26 L22 K45 K43 K41 K37 K35

R34

K31 K29 K25 J44 J40 J38 J34 J32 J28 J26

R29

H45 H43 H41 H37

H35 H31 H29 H25 G44 G40

R27 G38

G34 G32 G28 G26 F45 F43 F41 F37 F35

R23

F31 F29 F25 E44 E40 E38 E34 E32 E28 E26

R21

D45 D43 D41 D37 D35 D31 D29 C44 C40 C38

N45

C34 C32 C28 C26 B45 B43 B41 B37 B35 B31

68 92

70 92

65

MF-LF

402

10K

1/16W

5%

R1320

1

2

MF-LF

5%

0

1/16W

402

R1312

1 2

68 92

1%

402

1/16W

PLACE_NEAR=U1000.A50:2.54mm

MF-LF

130

R1302

1

2

5%

402

1/16W MF-LF

0

R1311

1 2

68 92

MF-LF

5%

PLACE_NEAR=U1000.B51:38mm

43

402

1/16W

R1310

1 2

68 92

75

MF-LF

1%

402

1/16W

PLACE_NEAR=R1310.1:2.54mm

R1300

1

2

1/16W MF-LF

10K

402

5%

R1313

1

2

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.AU10:50.8mm

NOSTUFF

100

1/16W

402

MF-LF

1%

R1363

1

2

402

NOSTUFF

PLACE_NEAR=U1000.AW10:50.8mm

PLACE_SIDE=BOTTOM

MF-LF

1/16W

1%

100

R1362

1

2

NOSTUFF

PLACE_SIDE=BOTTOM

MF

1/20W

1%

49.9

201

R1370

1

2

49.9

PLACE_SIDE=BOTTOM

NOSTUFF

1%

MF

1/20W

201

R1371

1

2

PLACE_SIDE=BOTTOM

NOSTUFF

1%

MF

1/20W

49.9

201

R1364

1

2

PLACE_SIDE=BOTTOM

NOSTUFF

49.9

1%

MF

1/20W

201

R1365

1

2

PLACE_SIDE=BOTTOM

MF-LF

402

NOSTUFF

100

1/16W

1%

PLACE_NEAR=U1000.B47:50.8mm

R1360

1

2

PLACE_NEAR=U1000.A46:50.8mm

NOSTUFF

PLACE_SIDE=BOTTOM

MF-LF

1%

100

402

1/16W

R1361

1

2

MF-LF

1/16W

10K

402

5%

R1314

1

2

PLACE_NEAR=U1000.F49:50.8mm

402

1/16W

NOSTUFF

1%

PLACE_SIDE=BOTTOM

100

MF-LF

R1366

1

2

NOSTUFF

PLACE_SIDE=BOTTOM

PLACE_NEAR=U1000.E50:50.8mm

100

402

MF-LF

1% 1/16W

R1367

1

2

100

1/16W

1%

MF-LF 402

R1368

1

2

65

SYNC_DATE=07/16/2010

CPU POWER

SYNC_MASTER=K91_MLB

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_VCC_VALSENSE_P

CPU_VCCSENSE_N

CPU_AXG_SENSE_N

CPU_VCCSASENSE

TP_CPU_DIE_SENSE

TP_CPU_VDDQSENSE_N

TP_CPU_VDDQSENSE_P

CPU_VCCIOSENSE_N

CPU_VCCIOSENSE_P

CPU_AXG_SENSE_P

CPU_VIDSCLK_R

CPU_VIDSOUT_R

CPU_VIDALERT_L_R

CPU_VCCSENSE_P

PPVCORE_S0_AXG

CPU_VCCSA_VID<1>

TP_DC_TEST_BF65

PPVCORE_S0_CPU PP1V05_S0

PP1V05_S0

CPU_VCCIO_SEL

CPU_VCCSA_VID<0>

DC_TEST_BH1_BG2

PPVCORE_S0_CPU

PP3V3_S0

DC_TEST_BH3_BJ2

DC_TEST_B65_C64

PPVCCSA_S0_CPU

TP_DC_TEST_A4 TP_DC_TEST_A62

TP_DC_TEST_BF1

TP_DC_TEST_BJ62

TP_DC_TEST_D1 TP_DC_TEST_D65

DC_TEST_BJ64_BH63

DC_TEST_BG64_BH65

DC_TEST_B63_A64

TP_DC_TEST_BJ4

DC_TEST_B3_C2

PP1V5_S3_CPU_VCCDQ

PP1V05_S0

PP1V05_S0_CPU_VCCPQE

PP1V8_S0_CPU_VCCPLL_R

PPVCCSA_S0_CPU

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

PPVCORE_S0_CPU

PPVCORE_S0_AXG

13 OF 132 12 OF 105

7

12 13 15 49

69

6 7

12 14 49 69

105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

7 9

10 12 13 14 23 35 39 45 68 70 73

102

104 105

6 7

12 14 49 69

105

6 7

12 14 49 69

105

6 7

23 25 26 28 32 35 36 39 40 41 46 48

49 50 51 52 54 57 61 62 72 73 80 83 84

85 88 89 91

100 102

7

12

15 65

6

7

15

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

7

10 14

7

14

7

12 15 65

6 7

12 14

49 69

105

7

12 13

15 49 69

VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4

VDDQ_9

VDDQ_8

VDDQ_7

VDDQ_5 VDDQ_6

VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14

VDDQ_19

VDDQ_18

VDDQ_17

VDDQ_15 VDDQ_16

VDDQ_20 VDDQ_21 VDDQ_22 VDDQ_23 VDDQ_24 VDDQ_25

VDDQ_29

VDDQ_28

VDDQ_27

VDDQ_26

VDDQ_30 VDDQ_31 VDDQ_32 VDDQ_33 VDDQ_34 VDDQ_35

VDDQ_39

VDDQ_38

VDDQ_36 VDDQ_37

VDDQ_40 VDDQ_41 VDDQ_42 VDDQ_43 VDDQ_44 VDDQ_45

VDDQ_50

VDDQ_49

VDDQ_48

VDDQ_47

VDDQ_46

VDDQ_51 VDDQ_52 VDDQ_53 VDDQ_54 VDDQ_55

VDDQ_60

VDDQ_59

VDDQ_58

VDDQ_56 VDDQ_57

VDDQ_61 VDDQ_62 VDDQ_63 VDDQ_64 VDDQ_65 VDDQ_66 VDDQ_67 VDDQ_68

VAXG_4

VAXG_3

VAXG_2

VAXG_1

VAXG_0

VAXG_9

VAXG_8

VAXG_7

VAXG_6

VAXG_5

VAXG_14

VAXG_13

VAXG_12

VAXG_11

VAXG_10

VAXG_16

VAXG_15

VAXG_17 VAXG_18 VAXG_19 VAXG_20 VAXG_21 VAXG_22 VAXG_23 VAXG_24 VAXG_25 VAXG_26 VAXG_27 VAXG_28 VAXG_29 VAXG_30 VAXG_31 VAXG_32 VAXG_33 VAXG_34 VAXG_35 VAXG_36 VAXG_37 VAXG_38 VAXG_39 VAXG_40 VAXG_41 VAXG_42 VAXG_43 VAXG_44 VAXG_45 VAXG_46 VAXG_47 VAXG_48 VAXG_49 VAXG_50 VAXG_51 VAXG_52 VAXG_53 VAXG_54 VAXG_55 VAXG_56 VAXG_57 VAXG_58 VAXG_59 VAXG_60 VAXG_61 VAXG_62 VAXG_63

IO POWER DDR3

GRAPHIC CORE POWER

(8 OF 11)

(10 OF 11)

VSS_85

VSS_84

VSS_83

VSS_82

VSS_81

VSS_80

VSS_79

VSS_78

VSS_77

VSS_76

VSS_75

VSS_74

VSS_73

VSS_72

VSS_71

VSS_70

VSS_69

VSS_68

VSS_67

VSS_66

VSS_65

VSS_64

VSS_63

VSS_62

VSS_61

VSS_60

VSS_59

VSS_58

VSS_57

VSS_56

VSS_55

VSS_54

VSS_53

VSS_52

VSS_51

VSS_50

VSS_49

VSS_48

VSS_47

VSS_46

VSS_45

VSS_44

VSS_43

VSS_42

VSS_41

VSS_40

VSS_39

VSS_38

VSS_37

VSS_36

VSS_35

VSS_34

VSS_33

VSS_32

VSS_31

VSS_30

VSS_29

VSS_28

VSS_27

VSS_26

VSS_25

VSS_24

VSS_23

VSS_22

VSS_21

VSS_20

VSS_19

VSS_18

VSS_17

VSS_15 VSS_16

VSS_10 VSS_11 VSS_12 VSS_13 VSS_14

VSS_5 VSS_6 VSS_7 VSS_8 VSS_9

VSS_0 VSS_1 VSS_2 VSS_3 VSS_4

VSS_171

VSS_170

VSS_169

VSS_168

VSS_167

VSS_164

VSS_163

VSS_165 VSS_166

VSS_162

VSS_161

VSS_160

VSS_159

VSS_158

VSS_157

VSS_153

VSS_152

VSS_154 VSS_155 VSS_156

VSS_151

VSS_150

VSS_149

VSS_148

VSS_147

VSS_143

VSS_142

VSS_144 VSS_145 VSS_146

VSS_141

VSS_140

VSS_139

VSS_138

VSS_137

VSS_132 VSS_133 VSS_134 VSS_135 VSS_136

VSS_131

VSS_130

VSS_129

VSS_128

VSS_127

VSS_126

VSS_123

VSS_122

VSS_124 VSS_125

VSS_121

VSS_120

VSS_119

VSS_118

VSS_117

VSS_116

VSS_112 VSS_113 VSS_114 VSS_115

VSS_111

VSS_110

VSS_109

VSS_108

VSS_107

VSS_106

VSS_102

VSS_101

VSS_103 VSS_104 VSS_105

VSS_100

VSS_99

VSS_98

VSS_97

VSS_96

VSS_92

VSS_91

VSS_93 VSS_94 VSS_95

VSS_90

VSS_89

VSS_88

VSS_87

VSS_86

(11 Of 11)

VSS_257

VSS_256

VSS_255

VSS_254

VSS_253

VSS_252

VSS_251

VSS_250

VSS_249

VSS_248

VSS_247

VSS_246

VSS_245

VSS_244

VSS_243

VSS_242

VSS_241

VSS_240

VSS_239

VSS_238

VSS_237

VSS_236

VSS_235

VSS_234

VSS_233

VSS_232

VSS_231

VSS_230

VSS_229

VSS_228

VSS_227

VSS_226

VSS_225

VSS_224

VSS_223

VSS_222

VSS_221

VSS_220

VSS_219

VSS_218

VSS_217

VSS_216

VSS_215

VSS_214

VSS_213

VSS_212

VSS_211

VSS_210

VSS_209

VSS_208

VSS_207

VSS_206

VSS_205

VSS_204

VSS_203

VSS_202

VSS_201

VSS_200

VSS_199

VSS_198

VSS_197

VSS_196

VSS_195

VSS_194

VSS_193

VSS_192

VSS_191

VSS_190

VSS_189

VSS_187 VSS_188

VSS_182 VSS_183 VSS_184 VSS_185 VSS_186

VSS_177 VSS_178 VSS_179 VSS_180 VSS_181

VSS_172 VSS_173 VSS_174 VSS_175 VSS_176

VSS_342

VSS_341

VSS_340

VSS_339

VSS_336

VSS_335

VSS_337 VSS_338

VSS_334

VSS_333

VSS_332

VSS_331

VSS_330

VSS_329

VSS_325

VSS_324

VSS_326 VSS_327 VSS_328

VSS_323

VSS_322

VSS_321

VSS_320

VSS_319

VSS_315

VSS_314

VSS_316 VSS_317 VSS_318

VSS_313

VSS_312

VSS_311

VSS_310

VSS_309

VSS_304 VSS_305 VSS_306 VSS_307 VSS_308

VSS_303

VSS_302

VSS_301

VSS_300

VSS_299

VSS_298

VSS_295

VSS_294

VSS_296 VSS_297

VSS_293

VSS_292

VSS_291

VSS_290

VSS_289

VSS_288

VSS_284 VSS_285 VSS_286 VSS_287

VSS_283

VSS_282

VSS_281

VSS_280

VSS_279

VSS_278

VSS_274

VSS_273

VSS_275 VSS_276 VSS_277

VSS_272

VSS_271

VSS_270

VSS_269

VSS_268

VSS_264

VSS_263

VSS_265 VSS_266 VSS_267

VSS_262

VSS_261

VSS_260

VSS_259

VSS_258

VSS_343

IO POWER

(7 OF 11)

VCCIO_33 VCCIO_34 VCCIO_35 VCCIO_36 VCCIO_37

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_38 VCCIO_39

VCCIO_43 VCCIO_44 VCCIO_45 VCCIO_46 VCCIO_47

VCCIO_52

VCCIO_51

VCCIO_50

VCCIO_48 VCCIO_49

VCCIO_53 VCCIO_54 VCCIO_55 VCCIO_56 VCCIO_57 VCCIO_58

VCCIO_62

VCCIO_61

VCCIO_60

VCCIO_59

VCCIO_63 VCCIO_64 VCCIO_65

VCCIO_4

VCCIO_3

VCCIO_2

VCCIO_1

VCCIO_0

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_5

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_17 VCCIO_18 VCCIO_19 VCCIO_20 VCCIO_21 VCCIO_22 VCCIO_23 VCCIO_24 VCCIO_25 VCCIO_26 VCCIO_27 VCCIO_28 VCCIO_29 VCCIO_30 VCCIO_31 VCCIO_32

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SANDY-BRIDGE

MOBILE-REV1

BGA

OMIT

U1000

AH65 AH63

AE64 AE62 AE60 AD65 AD63 AD61 AD58 AD56 AB65 AB63

AH61

AB61 AB58 AB56 AA64 AA62 AA60

Y58 Y56 W64 W62

AH58

W60 V65 V63 V61 V58 V56 T65 T63 T61 T58

AH56

T56 R64 R62 R60 R55 R53 R48 N64 N62 N60

AG64

N58 N56 N52 N49 M65 M63 M61 M59 M55 M53

AG62

M48 L56 L52 L48

AG60 AF58 AF56

BJ36 BJ28

AY47 AY43 AY39 AY35 AY31 AY27 AY23 AV46 AV42 AV40

BG40

AV36 AV34 AV29 AV27 AU45 AU43 AU39 AU37 AU33 AU30

BG32

AU26 AU24 AT46 AT42 AT40 AT36 AT34 AT29 AT27 AR45

BD47

AR43 AR39 AR37 AR33 AR30 AR26 AR24 AP46 AP42 AP40

BD43

AP36 AP34 AP29 AP27 AN45 AN43 AN39 AN37 AN33 AN30

BD39

AN26 AN24 AL46 AL42 AL40 AL36 AL34 AL29 AL27

BD31 BD23 BB35

BGA

SANDY-BRIDGE

MOBILE-REV1

OMIT

U1000

BJ56 BJ52

BG60

AU47 AU41 AU35 AU28 AU22 AU16 AU14 AT61 AT57 AT50

BG56

AT44 AT38 AT31 AT25 AT19 AT11 AT7 AT3 AT1 AR54

BG52

AR47 AR41 AR35 AR28 AR22 AP65 AP63 AP57 AP50 AP44

BG48

AP38 AP31 AP25 AP19 AP17 AP15 AP12 AP11 AP9 AP5

BG44

AN54 AN47 AN41 AN35 AN28 AN22 AM61 AM7 AM3 AM1

BG36

AL57 AL50 AL44 AL38 AL31 AL25 AL19 AK16 AK14 AK11

BG28

AK9 AK5 AJ64 AJ62 AJ60 AJ57 AH7 AH3 AH1 AG57

BG24

AG17 AG15

BG20 BG16

BJ48

BG12

BG8

BF5 BE62 BE58 BE54 BE50 BE46 BE42 BE38

BJ40

BE34 BE30 BE26 BE22 BE18 BE14 BE10 BD35

BD7

BD3

BJ32

BC60 BC56 BC52 BC48 BC44 BC40 BC36 BC32 BC28 BC26

BJ24

BC24 BC20 BC16 BC12 BB65 BB63 BB47 BB39

BB9

BB5

BJ20

BA58 BA54 BA50 BA46 BA42 BA38 BA34 BA30 BA26 BA22

BJ16

BA18 BA14 AY61 AY11

AY7

AY3

AY1 AW56 AW52 AW48

BJ12

AW44 AW40 AW36 AW32 AW28 AW24

AW16 AV65 AV63 AV59

BJ8

AV57 AV50 AV44 AV38 AV31 AV25 AV19 AV9 AV5 AU54

SANDY-BRIDGE

BGA

MOBILE-REV1

OMIT

U1000

AG12 AF65 AF63 AF61 AF11

AF9

AF5 AE57 AD16 AD14

AD7

AD3

AD1 AC64 AC62 AC60 AC57 AB11

AB9

AB5 AA57 AA17 AA15 AA12

Y65

Y63

Y61

Y7 Y3

Y1 W57 V16 V14 V11

V9

V5 U64 U62 U60 U57

T7

T3

T1 R57 R50 R44 R38 R31 R25 R19 R17 R15 R12 P65 P63 P61 P11

P9

P5 N54 N47 N41 N35 N28 N22 M57 M50 M44 M38 M31 M25 M19

M7

M3

M1 L64 L62 L60 L58 L54 L50 L46 L42 L36 L30 L24

L20 L16 L12 L8 K39 K33 K27 K1 J64 J60 J56 J52 J48 J46 J42 J36 J30 J24 J22 J18 J14 J10 J6 H39 H33 H27 H3 G62 G58 G54 G50 G46 G42 G36 G30 G24 G20 G16 G12 G8 F39 F33 F27 E60 E56 E52 E48 E46 E42 E36 E30 E24 E22 E18 E14 E10 E6 E4 D63 D39 D33 D27 C58 C54 C50 C46 C42 C36 C30 C20 C16 C12 C8 B39 B33 B27 A56 A52 A42 A36 A30 A24 A20 A16 A12

A8

BGA

MOBILE-REV1

SANDY-BRIDGE

OMIT

U1000

AV55 AV53

AU20 AU18 AT55 AT53 AT48 AT17 AT15 AT12 AR58 AR56

AV48

AR52 AR49 AR20 AR18 AR16 AR14 AP55 AP53 AP48 AN58

AV17

AN56 AN52 AN49

AN20 AN18 AN16 AN14 AM11 AL55 AL53

AV15

AL48 AL17 AL15 AL12 AK58 AK56 AJ17 AJ15 AJ12 AH16

AV12

AH14 AH11 AF16 AF14 AE17 AE15 AE12 AD11 AC17 AC15

AU58

AC12 AB16 AB14 Y16 Y14 Y11

AU56 AU52 AU49

CPU POWER AND GND

PP1V05_S0PP1V05_S0

PP1V5_S3RS0_CPUDDR

PPVCORE_S0_AXG

14 OF 132 13 OF 105

7 9

10 12 13 14 23 35 39 45

68 70 73

102 104 105

7 9

10 12 13 14 23 35

39 45 68 70 73

102 104

105

7

10 15 29 73

104

7

12 15 49 69

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1600-C16C7):

Intel recommendation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

CPU VCCIO/VCCPQ DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1646-C1671):

CPU VCCPLL DECOUPLING

Apple Implementation: 2x 330uF, 10x 10uF 0603, 26x 1uF 0402

CPU VCORE DECOUPLING

PLACEMENT_NOTE (C1640-C1645):

PLACEMENT_NOTE (C1620-C1623):

PLACEMENT_NOTE (C1624-C16D5):

PLACEMENT_NOTE (C1672-C1681):

Apple Implementation: 4x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 16x 22uF 0603, 4x 10uF 0402, 20x 1uF 0402, 28x 1uF 0201 (NOSTUFF), 4x 22uF 0603 (NOSTUFF)

Intel recommendation: 4x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 16x 22uF 0805, 4x 10uF 0603, 20x 1uF 0402, 28x 1uF 0402 (NOSTUFF)

402

10V X5R

10%

1UF

C1612

1

2

10% X5R

402

1UF

10V

C1611

1

2

X5R

10V 402

1UF

10%

C1610

1

2

20% 0201

6.3V

1UF

NOSTUFF

X5R

C16A4

1

2

20% 0201

6.3V X5R

1UF

NOSTUFF

C16A3

1

2

402

X5R

10V

10%

1UF

C1609

1

2

NOSTUFF

20% 0201

X5R

1UF

6.3V

C16A2

1

2

10% 10V X5R 402

1UF

C1608

1

2

X5R

10V

1UF

402

10%

C1607

1

2

20% 0201

6.3V

1UF

NOSTUFF

X5R

C16A1

1

2

6.3V 0201

20% X5R

1UF

NOSTUFF

C16A0

1

2

1

C1631

CRITICAL

6.3V

20%

22UF

Place near inductors on bottom side.

X5R-CERM1 0603

402

X5R

1UF

10V

10%

C1606

1

2

402

X5R

10V

10%

1UF

C1619

1

2

X5R 402

10V

10%

1UF

C1605

1

2

402

10% 10V X5R

1UF

C1618

1

2

10V X5R

10%

402

1UF

C1604

1

2

402

X5R

10V

10%

1UF

C1617

1

2

Place on bottom side of U1000

X5R

1UF

10V 402

10%

C1603

1

2

1UF

10% 10V X5R 402

Place on bottom side of U1000

C1602

1

2

402

X5R

10V

10%

1UF

C1616

1

2

402

X5R

10V

10%

1UF

C1615

1

2

10% X5R

402

Place on bottom side of U100.

1UF

10V

C1601

1

2

10% 10V X5R 402

1UF

C1614

1

2

1UF

Place on bottom side of U1000

10% X5R

10V 402

C1600

1

2

402

X5R

10V

10%

1UF

C1613

1

2

1

C1630

CRITICAL

22UF

20%

Place near inductors on bottom side.

6.3V X5R-CERM1 0603

2

1

C1629

CRITICAL

22UF

Place near inductors on bottom side.

20%

6.3V X5R-CERM1 0603

2.0V D2T-SM

POLY-TANT

20%

470UF-4MOHM

NOSTUFF

Place near inductors on bottom side.

C1643

1

23

2

1

C1627

CRITICAL

Place near inductors on bottom side.

20%

6.3V

22UF

X5R-CERM1 0603

2

1

C1626

20%

Place near inductors on bottom side.

22UF

6.3V

CRITICAL

X5R-CERM1 0603

470UF-4MOHM

Place near inductors on bottom side.

2.0V

20%

D2T-SM

POLY-TANT

CRITICAL

C1642

1

23

470UF-4MOHM

D2T-SM

Place near inductors on bottom side.

2.0V

20% POLY-TANT

CRITICAL

C1641

1

23

Place near inductors on bottom side.

D2T-SM

20%

2.0V

470UF-4MOHM

POLY-TANT

CRITICAL

C1640

1

23

0201

20% X5R

1UF

NOSTUFF

6.3V

C16A6

1

2

20% 0201

6.3V

1UF

X5R

NOSTUFF

C16A5

1

2

CRITICAL

Place near U1000 on bottom side

10UF

20%

6.3V CERM-X5R 0402-1

C1620

1

2

CRITICAL

Place near U1000 on bottom side

CERM-X5R

10UF

6.3V 0402-1

20%

C1621

1

2

CRITICAL

0402-1

6.3V

20%

10UF

Place near U1000 on bottom side

CERM-X5R

C1622

1

2

CRITICAL

Place near U1000 on bottom side

20%

6.3V CERM-X5R

10UF

0402-1

C1623

1

2

1

C1625

22UF

Place near inductors on bottom side.

6.3V

20%

CRITICAL

X5R-CERM1 0603

2

1

C1624

CRITICAL

22UF

20%

Place near inductors on bottom side.

6.3V X5R-CERM1 0603

2

1

C1628

CRITICAL

6.3V

Place near inductors on bottom side.

20%

22UF

0603

X5R-CERM1

2

1

C1632

CRITICAL

22UF

20%

6.3V

Place near inductors on bottom side.

X5R-CERM1 0603

2

1

C1633

CRITICAL

22UF

6.3V

20%

Place near inductors on bottom side.

X5R-CERM1 0603

2

1

C1639

CRITICAL

Place near inductors on bottom side.

22UF

20%

6.3V 0603

X5R-CERM1

2

1

C1638

CRITICAL

20%

6.3V

22UF

Place near inductors on bottom side.

X5R-CERM1 0603

2

CRITICAL

22UF

20%

6.3V

Place near inductors on bottom side.

X5R-CERM1 0603

1

C1637

2

1

20%

6.3V

Place near inductors on bottom side.

0603

X5R-CERM1

22UF

CRITICAL

C1636

2

C1635

CRITICAL

20%

22UF

6.3V

Place near inductors on bottom side.

X5R-CERM1 0603

1

2

1

C1634

CRITICAL

22UF

6.3V

Place near inductors on bottom side.

20% X5R-CERM1

0603

470UF-4MOHM

D2T-SM

POLY-TANT

Place near inductors on bottom side.

20%

2.0V

CRITICAL

C1644

1

23

X5R

10V

10%

1UF

402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

C1686

1

2

1/16W

402

0

MF-LF

5%

R1600

1 2

10%

1UF

10V X5R 402

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

C1685

1

2

10% 10V X5R 402

1UF

C1684

1

2

402

X5R

10%

1UF

10V

C1658

1

2

1UF

10% 10V X5R 402

C1657

1

2

10V

10% X5R

402

1UF

C1656

1

2

402

X5R

10V

10%

1UF

C1655

1

2

402

10V X5R

1UF

10%

C1654

1

2

1UF

X5R

10V

10% 402

C1653

1

2

402

X5R

1UF

10% 10V

C1652

1

2

X5R 402

10V

10%

1UF

C1651

1

2

10% X5R

10V 402

1UF

C1650

1

2

X5R

10%

1UF

Place on bottom side of U1000

10V 402

C1649

1

2

402

10V X5R

10%

1UF

Place on bottom side of U1000

C1648

1

2

10% X5R

402

Place on bottom side of U100.

10V

1UF

C1647

1

2

1UF

Place on bottom side of U1000

10% X5R

10V 402

C1646

1

2

402

X5R

10V

10%

1UF

C1664

1

2

402

10% 10V X5R

1UF

C1663

1

2

10%

402

X5R

10V

1UF

C1662

1

2

402

1UF

X5R

10V

10%

C1661

1

2

402

X5R

10V

10%

1UF

C1660

1

2

10% 10V X5R 402

1UF

C1659

1

2

10%

402

X5R

10V

1UF

C1671

1

2

1UF

402

10% 10V X5R

C1670

1

2

402

X5R

10V

10%

1UF

C1669

1

2

402

X5R

10V

10%

1UF

C1668

1

2

X5R 402

10V

10%

1UF

C1667

1

2

402

10% 10V X5R

1UF

C1666

1

2

402

X5R

10V

10%

1UF

C1665

1

2

Place near U1000 on bottom side

CRITICAL

10UF

6.3V

20% X5R

603

C1675

1

2

CRITICAL

Place near U1000 on bottom side

6.3V

10UF

20% X5R

603

C1674

1

2

CRITICAL

6.3V

20%

Place near U1000 on bottom side

10UF

X5R 603

C1673

1

2

10UF

CRITICAL

6.3V

Place near U1000 on bottom side

20% X5R

603

C1672

1

2

CRITICAL

10UF

20%

6.3V

Place near U1000 on bottom side

X5R 603

C1679

1

2

CRITICAL

10UF

20%

6.3V

Place near U1000 on bottom side

X5R 603

C1678

1

2

CRITICAL

6.3V

10UF

20%

Place near U1000 on bottom side

X5R 603

C1677

1

2

CRITICAL

6.3V

20%

Place near U1000 on bottom side

10UF

X5R 603

C1676

1

2

CRITICAL

20%

6.3V

10UF

Place near U1000 on bottom side

X5R 603

C1681

1

2

CRITICAL

6.3V

20%

10UF

Place near U1000 on bottom side

X5R 603

C1680

1

2

Place near inductors on bottom side

CRITICAL

20% 2V POLY CASE-D2-SM

330UF-0.006OHM

C1682

1

2

0603

MF

1/4W

1%

0.010

R1601

1 2

NOSTUFF

1UF

X5R

20%

6.3V 0201

C16A7

1

2

NOSTUFF

1UF

X5R 0201

6.3V

C16A8

1

2

20%

NOSTUFF

1UF

X5R

20%

6.3V 0201

C16A9

1

2

NOSTUFF

1UF

X5R

20%

6.3V 0201

C16B0

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B1

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B2

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B3

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B4

1

2

NOSTUFF

X5R 0201

1UF

20%

6.3V

C16B5

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B6

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B7

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B8

1

2

NOSTUFF

1UF

X5R

20% 0201

6.3V

C16B9

1

2

NOSTUFF

1UF

X5R

20%

6.3V 0201

C16C0

1

2

NOSTUFF

1UF

6.3V 0201

20% X5R

C16C7

1

2

6.3V 0201

20% X5R

1UF

NOSTUFF

C16C6

1

2

X5R

20%

6.3V

1UF

NOSTUFF

0201

C16C5

1

2

1UF

X5R

20%

6.3V

NOSTUFF

0201

C16C4

1

2

NOSTUFF

1UF

20%

6.3V 0201

X5R

C16C3

1

2

NOSTUFF

1UF

X5R

20%

0201

6.3V

C16C1

1

2

1UF

X5R

20%

0201

6.3V

NOSTUFF

C16C2

1

2

1

C16D3

Place near inductors on bottom side.

6.3V

20%

22UF

NOSTUFF

X5R-CERM1 0603

2

1

C16D2

Place near inductors on bottom side.

6.3V

20%

22UF

NOSTUFF

X5R-CERM1 0603

2

1

C16D1

Place near inductors on bottom side.

6.3V

22UF

20%

NOSTUFF

X5R-CERM1 0603

2

1

C16D0

Place near inductors on bottom side.

20%

6.3V

22UF

NOSTUFF

X5R-CERM1 0603

330UF-0.006OHM

CASE-D2-SM

CRITICAL

Place near inductors on bottom side

POLY

20% 2V

C1683

1

2

330UF-0.006OHM

PLACE_NEAR=U1000.AK61:5 mm

CASE-D2-SM

CRITICAL

20% 2V POLY

C1687

1

2

SYNC_DATE=07/21/2010

SYNC_MASTER=K91_MLB

CPU DECOUPLING-I

PPVCORE_S0_CPU

PP1V05_S0

PP1V05_S0_CPU_VCCPQE

PP1V8_S0

PP1V8_S0_CPU_VCCPLL_R

16 OF 132 14 OF 105

6 7

12 49 69

105

7 9

10 12 13

23 35 39 45

68 70 73

102 104 105

7

10 12

6 7

20 25 71 72 88

102

7

12

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Apple Implementation: 2x 470uF 4mOhm, 1x 470uF 4mOhm (NOSTUFF), 6x 22uF 0603, 2x 22uF 0603 (NOSTUFF), 6x 10uF 0402, 2x 10uF 0402 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)

Intel recommendation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

PLACEMENT_NOTE (C1758-C1762):

PLACEMENT_NOTE (C1700-C1708):

Intel recommendation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

CPU VDDQ/VCCDQ DECOUPLING

PLACEMENT_NOTE (C1738-C1747):

Apple Implementation: 1x 330uF, 8x 10uF 0603, 10x 1uF 0402

CPU VCCSA DECOUPLING

Apple Implementation: 1x 330uF, 5x 10uF 0603, 5x 1uF 0402

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

PLACEMENT_NOTE (C1726-C1731):

PLACEMENT_NOTE (C1718-C1723):

Intel recommendation: 2x 470uF 4mOhm, 2x 470uF 4mOhm (NOSTUFF), 6x 22uF 0805, 2x 22uF 0805 (NOSTUFF), 6x 10uF 0603, 2x 10uF 0603 (NOSTUFF), 9x 1uF 0402, 9x 1uF 0402 (NOSTUFF)

VAXG DECOUPLING

PLACEMENT_NOTE (C1734-C1735):

NOSTUFF

10V 402

X5R

10%

1UF

C1717

1

2

402

NOSTUFF

10% 10V X5R

1UF

C1716

1

2

NOSTUFF

10% 10V X5R 402

1UF

C1715

1

2

NOSTUFF

402

X5R

10V

10%

1UF

C1714

1

2

NOSTUFF

402

X5R

10V

10%

1UF

C1713

1

2

10V

1UF

NOSTUFF

402

10% X5R

C1712

1

2

1UF

10% 10V

402

NOSTUFF

X5R

C1711

1

2

10% X5R

402

1UF

NOSTUFF

10V

C1710

1

2

NOSTUFF

1UF

10% X5R

402

10V

C1709

1

2

1UF

402

10% 10V X5R

C1708

1

2

X5R 402

10V

10%

1UF

C1707

1

2

X5R

1UF

10% 10V

402

C1706

1

2

CERM-X5R

6.3V

10UF

NOSTUFF

20%

0402-1

Place close to U1000 on bottom side

C1725

1

2

Place close to U1000 on bottom side

CERM-X5R

6.3V

20%

10UF

NOSTUFF

0402-1

C1724

1

2

1

C1733

Place near inductors on bottom side.

6.3V

20%

NOSTUFF

22UF

X5R-CERM1 0603

2

1

C1732

NOSTUFF

Place near inductors on bottom side.

6.3V

20%

22UF

X5R-CERM1 0603

X5R

10V

10%

402

1UF

C1705

1

2

Place close to U1000 on bottom side

20%

6.3V

10UF

CERM-X5R 0402-1

C1723

1

2

10V X5R

10%

402

1UF

C1704

1

2

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

C1722

1

2

Place on bottom side of U1000

X5R

10%

1UF

10V 402

C1703

1

2

6.3V

Place close to U1000 on bottom side

10UF

20% CERM-X5R

0402-1

C1721

1

2

1

C1731

Place near inductors on bottom side.

20%

6.3V

22UF

X5R-CERM1 0603

2

1

C1730

22UF

20%

6.3V

Place near inductors on bottom side.

X5R-CERM1 0603

2

1

C1729

6.3V

Place near inductors on bottom side.

20%

22UF

X5R-CERM1 0603

2.0V

20%

D2T-SM

POLY-TANT

NOSTUFF

470UF-4MOHM

Place near inductors on bottom side.

C1737

1

23

Place on bottom side of U1000

10% 10V

402

X5R

1UF

C1702

1

2

1UF

10% X5R

Place on bottom side of U100.

402

10V

C1701

1

2

6.3V

Place close to U1000 on bottom side

10UF

0402-1

CERM-X5R

20%

C1720

1

2

10UF

CERM-X5R

Place close to U1000 on bottom side

20%

6.3V 0402-1

C1719

1

2

X5R

Place on bottom side of U1000

10% 10V

402

1UF

C1700

1

2

Place close to U1000 on bottom side

10UF

20%

0402-1

6.3V CERM-X5R

C1718

1

2

1

C1728

6.3V

22UF

20%

Place near inductors on bottom side.

X5R-CERM1 0603

2

1

C1727

22UF

20%

Place near inductors on bottom side.

6.3V X5R-CERM1 0603

POLY-TANT D2T-SM

20%

Place near inductors on bottom side.

470UF-4MOHM

2.0V

C1735

1

23

2

1

C1726

20%

22UF

Place near inductors on bottom side.

6.3V X5R-CERM1 0603

2.0V D2T-SM

20%

Place near inductors on bottom side.

POLY-TANT

470UF-4MOHM

C1734

1

23

X5R

10%

1UF

10V

402

C1757

1

2

X5R

10V 402

10%

1UF

C1747

1

2

10% 10V

1UF

402

X5R

C1746

1

2

402

X5R

10V

10%

1UF

C1745

1

2

X5R

1UF

10% 10V

402

C1744

1

2

X5R 402

10V

10%

1UF

C1743

1

2

402

10V X5R

10%

1UF

C1742

1

2

X5R

10% 10V

1UF

402

Place on bottom side of U1000

C1741

1

2

X5R 402

Place on bottom side of U1000

10% 10V

1UF

C1740

1

2

402

10% X5R

Place on bottom side of U100.

10V

1UF

C1739

1

2

10V

Place on bottom side of U1000

10% X5R

402

1UF

C1738

1

2

20%

10UF

6.3V X5R

Place close to U1000 on bottom side

603

C1755

1

2

10UF

20%

6.3V

Place close to U1000 on bottom side

X5R 603

C1754

1

2

10UF

20%

Place close to U1000 on bottom side

6.3V X5R 603

C1753

1

2

10UF

6.3V

20%

Place close to U1000 on bottom side

X5R 603

C1752

1

2

6.3V

20%

Place close to U1000 on bottom side

10UF

X5R 603

C1751

1

2

10UF

6.3V

20%

Place close to U1000 on bottom side

X5R 603

C1750

1

2

10UF

Place close to U1000 on bottom side

20%

6.3V X5R 603

C1749

1

2

6.3V

20%

Place close to U1000 on bottom side

10UF

X5R 603

C1748

1

2

10V X5R

10%

402

1UF

C1762

1

2

Place on bottom side of U1000

X5R

10%

402

10V

1UF

C1761

1

2

6.3V

10UF

20% X5R

603

C1767

1

2

20%

6.3V

10UF

X5R 603

C1766

1

2

X5R

1UF

10% 10V

402

Place on bottom side of U1000

C1760

1

2

402

X5R

10% 10V

1UF

Place on bottom side of U100.

C1759

1

2

20%

10UF

6.3V X5R 603

C1765

1

2

6.3V

20%

10UF

X5R 603

C1764

1

2

X5R

Place on bottom side of U1000

1UF

10% 10V

402

C1758

1

2

603

6.3V

20%

10UF

X5R

C1763

1

2

1%

0.010

0603

MF

1/4W

R1700

1 2

20% TANT

2V CASE-B4-SM

270UF

C1768

1

2

Place near inductors on bottom side

CASE-D2-SM

330UF-0.006OHM

2V

20% POLY

CRITICAL

C1756

1

2

SYNC_MASTER=K91_MLB

CPU DECOUPLING-II

SYNC_DATE=07/21/2010

PPVCORE_S0_AXG

PP1V5_S3_CPU_VCCDQ

PPVCCSA_S0_CPU

PP1V5_S3RS0_CPUDDR

17 OF 132 15 OF 105

7

12 13 49 69

7

12

7

12 65

7

10 13 29 73

104

IN

OUT

IN

BI

OUT

BI

IN

IN OUT OUT

IN IN

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

IN

IN IN

IN

OUT

BI

OUT

BI

IN IN OUT OUT

OUT

BI

OUT

SATA1RXN

SATA0TXP

SATA0TXN

SATA2RXN SATA2RXP

SATA5RXP

SATA0RXP

LDRQ0*

RTCRST*

SRTCRST*

INTRUDER*

INTVRMEN

HDA_BCLK

HDA_SYNC

HDA_RST*

SPKR

HDA_SDIN0 HDA_SDIN1

HDA_SDIN3

HDA_SDIN2

HDA_SDO

HDA_DOCK_EN*/GPIO33 HDA_DOCK_RST*/GPIO13

JTAG_TCK

JTAG_TMS

JTAG_TDI

JTAG_TDO

SPI_CS0*

SPI_CLK

SPI_CS1*

SPI_MOSI

SPI_MISO

FWH0/LAD0

RTCX1 RTCX2

SATA1TXP

SATA0RXN

SERIRQ

LDRQ1*/GPIO23

FWH1/LAD1 FWH2/LAD2 FWH3/LAD3

FWH4/LFRAME*

SATA1RXP SATA1TXN

SATA2TXN SATA2TXP

SATA3RXN SATA3RXP SATA3TXN SATA3TXP

SATA4RXN SATA4RXP SATA4TXN SATA4TXP

SATA5RXN

SATA5TXN SATA5TXP

SATAICOMPO SATAICOMPI

SATALED*

SATA0GP/GPIO21 SATA1GP/GPIO19

SATA3COMPI

SATA3RCOMP0

SATA3RBIAS

JTAG

SPI

SATA

LPC

IHDA

RTC

(1 OF 10)

(2 OF 10)

PCI-E*

PEG

FROM CLK BUFFER

CLOCK

FLEX

SMBUS

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

PERN3

PETP2

PETN2

PERP1

CL_RST1*

CL_DATA1

CL_CLK1

CLKIN_GND1_P

CLKIN_GND1_N

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

XCLK_RCOMP

XTAL25_OUT

XTAL25_IN

CLKIN_PCILOOPBACK

REFCLK14IN

CLKIN_SATA_N CLKIN_SATA_P

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

CLKOUT_DP_N CLKOUT_DP_P

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKOUT_PEG_B_N CLKOUT_PEG_B_P

CLKOUT_PCIE5P

PCIECLKRQ5*/GPIO44

CLKOUT_PCIE4P

CLKOUT_PCIE5N

CLKOUT_PCIE3P

CLKOUT_PCIE4N

CLKOUT_PCIE3N

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1N CLKOUT_PCIE1P

CLKOUT_PCIE0N CLKOUT_PCIE0P

PETN1

PERN1

SMBCLK

SMBALERT*/GPIO11

PETP8

PERP8 PETN8

PETP7

PERN8

PETN7

PERP7

PERN7

PETN6 PETP6

PERP6

PERN6

PETP5

PETN5

PERP5

PETP4

PERN5

PETN4

PERP4

PETP3

PERN4

PETN3

PERP3

PERN2 PERP2

PETP1

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0ALERT*/GPIO60

SML0CLK

SMBDATA

IN IN IN

IN

OUT OUT

IN

OUT

OUT OUT

NC

OUT

IN

IN OUT OUT

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1.8V -> 1.1V

DOES THIS NEED LENGTH MATCH???

(IPU)

R1849 cannot be used w/ VCCSUSHDA on S0

Q1850 376S0859 376S0859 VGS 0.35~1V

(IPU)

UNUSED clock terminations for FCIM MODE

25

57 95

47 95

6

45 47 88 95

6

45 47 88 95

6

45 47 88 95

6

45 47 88 95

6

45 47 88 95

6

45 47

6

41 94

6

41 94

6

41 94

6

41 94

36 95

6

31 95

6

31 95

38 95

36 95

31 95

38 95

36 95

31 95

38 95

16 23 39

10 92

74 95

16 95

25 95

48 95

6

23 26 28 30 32

41 48 62 89 95

6

23 26 28 30 32

41 48 62 89 95

6

32

100

6

32

100

32

100

32

100

2

1

R1800

201

MF

330K

5%

1/20W

1M

MF 201

1/20W

5%

R1801

1

2

1

R1802

1/20W

MF

20K

5%

201

2

1

R1803

20K

5%

201

1/20W MF

2

1

C1803

10%

1UF

X5R 402

10V

2

1

1UF

10%

X5R

10V

402

C1802

2

1

R1830

PLACE_NEAR=U1800.Y11:2.54mm

201

1/20W

MF

37.4

1%

2

1

R1820

201

MF

1/20W

5%

10K

2

1

R1890

201

MF 1%

90.9

1/20W

PLACE_NEAR=U1800.Y47:2.54mm

201

1/20W

33

MF

5%

PLACE_NEAR=U1800.N34:1.27mm

R1810

1 2

21

R1811

201

1/20W

33

5%

PLACE_NEAR=U1800.L34:1.27mm

MF

PLACE_NEAR=U1800.K34:1.27mm

21

R1812

201

MF

33

5%

1/20W

21

R1813

PLACE_NEAR=U1800.A36:1.27mm

201

1/20W

MF

5%

33

57 95

48 95

16 33

21

R1860

33

201

1/20W

MF5%

21

R1861

1/20W

MF

33

5%

201

21

R1862

201

MF

33

1/20W

5%

21

20133MF

1/20W

R1863

5%

21

R1864

201

MF

33

1/20W

5%

2

1

R1832

201

1/20W

5%

750

MF

PLACE_NEAR=U1800.AH1:2.54mm

201

MF

1/20W

49.9

1%

R1831

1

2

PLACE_NEAR=U1800.AB12:2.54mm

2

1

R1870

MF

1/20W

5%

10K

201

2

1

R1871

10K

1/20W

201

MF

5%

AP7

T10

V4

U3

T1

T3

P3

Y11 Y10

AB1

AB3

Y1

Y3

AD1

AD3

Y5

Y7

AF1

AF3

AB10

AB8

AH1

AB13

AH4

AH5

AD5

AD7

AP10

AP11

AM8

AM10

P1

AP5

AM1

AM3

V14

C20

A20

K36

H7

H1

K5

J3

K22

L34

A36

A34

C34

G34

E34

K34

N32

C36

N34

D36

C37

B37

A38

C38

U1800

MOBILE

COUGAR-POINT

FCBGA

OMIT

Y14

D20

AB12

C17

G22

E36

V5

V49

V47

Y47

M16

E14

C13

G12

C8

A12

C9

H14

E12

K45

AY38

BB40

AV36

BB36

BB34

AU34

AY32

AU32

AW38

AY40

AU36

AY36

AY34

AV34

BB32

AV32

BC38

BJ40

BG38

BH37

BE36

BJ36

BF34

BJ34

BE38

BG40

BJ38

BG37

BF36

BG36

BE34

BG34

E6

M10

L14

L12

A8

V10

M1

J2

K49

H47

F47

K43

AB40

AB42

AB38

AB37

V46

V45

Y45

Y43

Y36

Y37

AA47

AA48

AB47

AB49

Y39

Y40

AK13

AK14

AM13

AM12

AU22

AV22

AK5

AK7

H45

BG30

BJ30

E24

G24

BE18

BF18

P10

T11

M7

U1800

FCBGA

OMIT

MOBILE

COUGAR-POINT

16 36

16 23 31

16 32

8

16 88

32 95

2

1

R1877

5%

1/20W

MF

4.7K

201

2

1

R1866

10K

NOSTUFF

1/20W

201

MF

5%

16 35

25

23

33 95

36 95

2

1

R1878

201

5%

1/20W

MF

4.7K

2

1

R1855

5%

201

MF

10K

1/20W

2

1

R1854

5%

10K

1/20W MF 201

2

1

R1853

5%

201

MF

1/20W

10K

2

1

R1848

MF

10K

5%

1/20W

201

1/20W

2

1

201

10K

5%

MF

R1847

2

1

R1833

5%

10K

MF

201

NOSTUFF

1/20W

10K

2

1

R1834

5%

201

MF

1/20W

2

1

R1843

5%

201

MF

1/20W

10K

2

1

R1846

1/20W

MF

5%

10K

201 201

2

1

R1845

5%

10K

MF

1/20W

2

1

R1844

MF

5%

1/20W

10K

201

2

1

R1842

5%

MF

10K

1/20W

201

2

1

R1869

1/20W

5%

MF

10K

201

2

1

R1876

10K

5%

201

1/20W

MF

2

1

R1849

NOSTUFF

10K

201

1/20W

5%

2 1

R1840

NOSTUFF

MF5%

1/20W

0

201

2 1

R1841

NOSTUFF

MF

1/20W

5%

201

0

16 23 41

21

R1872

1%

MF-LF

1/16W

604

402

2

1

R1873

1/20W

1%

1K

201

MF

25

41 94

1/20W MF

10K

5%

201

R1897

1

2

10K

5%

201

1/20W MF

R1896

1

2

10K

1/20W

5%

201

MF

1

2

R1895

10K

5%

201

1/20W MF

R1894

1

2

10K

5% 1/20W MF 201

R1893

1

2

10K

5% MF

201

1/20W

R1892

1

2

10K

201

5% MF

1/20W

R1891

1

2

16 23 85

2 1

R1888

201

0

MF

1/20W

5%

NOSTUFF

19 45

PCH SATA/PCIE/CLK/LPC/SPI

SYNC_MASTER=K91_MLB

SYNC_DATE=10/19/2010

PCH_SRTCRST_L

PPVRTC_G3H

RTC_RESET_L

PCH_INTVRMEN_L

PCH_INTRUDER_L

PCH_SRTCRST_L

PCH_INTVRMEN_L

HDA_SYNC_R

NC_HDA_SDIN1

HDA_SDOUT_R

JTAG_T29_TMS

PP3V3_S0_PCH

LPC_R_AD<2>

PCH_SPKR

HDA_SDIN0

ENET_MEDIA_SENSE_RDIV

SPI_CS0_R_L

PCH_SATA3RBIAS

DP_AUXCH_ISOL

SATA_HDD_R2D_C_N

T29_PWR_EN

LPC_FRAME_R_L

LPC_R_AD<1>

LPC_R_AD<0>

LPC_SERIRQ

EXCARD_CLKREQ_L

PCH_SATALED_L

PCH_CLK14P3M_REFCLK

PEG_CLKREQ_L

T29_CLKREQ_L

PCIE_CLK100M_PCH_P PCH_CLK100M_SATA_N

PCIE_CLK100M_PCH_N

NC_SATA_D_R2D_CP

TP_SATA_E_D2RN

PCH_SATAICOMP

PCIE_CLK100M_FW_N

FW_CLKREQ_L

SML_PCH_0_ALERT_L

PEG_B_CLKRQ_L_GPIO56

SATA_HDD_R2D_C_P

HDA_SYNC_R HDA_SDOUT_R

PP1V5_S0

PP3V3_T29

PP3V3_S0_PCH PP3V3_SUS

ENET_CLKREQ_L

AP_CLKREQ_L

FW_CLKREQ_L

PCH_SPKR

JTAG_T29_TMS

SATARDRVR_EN

PPVCCIO_S0_PCH

PCH_SATA3COMP

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

PCH_CLK100M_SATA_P

TP_LPC_DREQ0_L

TP_SPI_CS1_L

SPI_MISO

SPI_MOSI_R

XDP_PCH_TDO

XDP_PCH_TMS

XDP_PCH_TCK

SATA_ODD_R2D_C_P

HDA_RST_R_L

NC_HDA_SDIN2 NC_HDA_SDIN3

SYSCLK_CLK32K_RTC

TP_SATA_B_D2RN TP_SATA_B_D2RP

ENET_CLKREQ_L

TP_PCIE_CLK100M_PEBN TP_PCIE_CLK100M_PEBP

NC_PCIE_5_R2D_CP

NC_PCIE_5_R2D_CN

TP_SATA_F_D2RN

SATARDRVR_EN

HDA_SYNC

TP_SATA_F_D2RP

NC_PCIE_7_R2D_CP

NC_SATA_D_D2RP

NC_SATA_D_D2RN

SMC_SCI_L

SML_PCH_1_ALERT_L

ITPCPU_CLK100M_P

ITPXDP_CLK100M_N

HDA_RST_R_L

HDA_SDOUT

HDA_RST_L

ITPCPU_CLK100M_N

SYSCLK_CLK25M_SB

PP3V3_SUS

PCH_GPIO11

SMBUS_PCH_CLK SMBUS_PCH_DATA

SML_PCH_0_ALERT_L

SML_PCH_0_CLK

PEG_CLK100M_N PEG_CLK100M_P

DMI_CLK100M_CPU_N

PCIE_CLK100M_PCH_N PCIE_CLK100M_PCH_P

PCH_CLK96M_DOT_N

PCH_CLK14P3M_REFCLK

SML_PCH_1_CLK

SML_PCH_1_ALERT_L

PCH_XCLK_RCOMP

NC_PCIE_CLK100M_PE5P

AP_CLKREQ_L

T29_CLKREQ_L

SYSCLK_CLK25M_SB_R

PCH_CLK33M_PCIIN

HDA_SYNC_R

TP_SATA_B_R2D_CP

TP_SATA_E_D2RP TP_SATA_E_R2D_CN TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CN

PCH_SATALED_L

TP_SATA_B_R2D_CN

SATA_ODD_R2D_C_N

TP_SATA_F_R2D_CP

SATA_ODD_D2R_N

NC_SATA_D_R2D_CN

PCIE_EXCARD_D2R_P

SATA_ODD_D2R_P

PCIECLKRQ5_L_GPIO44

PPVCCIO_S0_PCH

LPC_AD<3>

PCIE_FW_D2R_N PCIE_FW_D2R_P PCIE_FW_R2D_C_N

PP3V3_SUS

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

DP_AUXCH_ISOL

LPC_FRAME_L

LPC_AD<2>

LPC_AD<1>

HDA_BIT_CLK

XDP_PCH_TDI

TP_PCH_CLKOUT_DPP

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_T29_N

HDA_BIT_CLK_R

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_P

PCIE_CLK100M_FW_P

PCIE_CLK100M_AP_P

PCIECLKRQ5_L_GPIO44

PCIE_CLK100M_EXCARD_N

PEG_B_CLKRQ_L_GPIO56

PCH_INTRUDER_L

RTC_RESET_L

SPI_CLK_R

HDA_BIT_CLK_R

TP_PCH_GPIO65_CLKOUTFLEX1

HDA_SDOUT_R

PEG_CLKREQ_L

TP_PCH_GPIO64_CLKOUTFLEX0

LPC_AD<0>

DMI_CLK100M_CPU_P

PPVCCIO_S0_PCH

TP_PCH_GPIO66_CLKOUTFLEX2

PCH_CLK100M_SATA_N

TP_CLINK_CLK

PCH_CLKIN_GNDP1

ITPXDP_CLK100M_N

TP_PCH_GPIO67_CLKOUTFLEX3

TP_CLINK_RESET_L

TP_CLINK_DATA

ITPXDP_CLK100M_P

PCH_CLKIN_GNDN1

PCIE_AP_D2R_N

SML_PCH_1_DATA

SML_PCH_0_DATA

TP_PCH_CLKOUT_DPN

PCIE_CLK100M_ENET_P

EXCARD_CLKREQ_L

SYSCLK_CLK25M_SB_R

PCIE_CLK100M_T29_P

NC_PCIE_CLK100M_PE5N

PCIE_AP_D2R_P

PCIE_AP_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_AP_R2D_C_N

PCIE_FW_R2D_C_P

PCIE_EXCARD_D2R_N

PCIE_ENET_R2D_C_P

PP3V3_S0_PCH

PCIE_EXCARD_R2D_C_N PCIE_EXCARD_R2D_C_P

NC_PCIE_5_D2RN NC_PCIE_5_D2RP

NC_PCIE_6_D2RN

NC_PCIE_7_R2D_CN

NC_PCIE_7_D2RP

NC_PCIE_7_D2RN

NC_PCIE_6_R2D_CN

NC_PCIE_6_D2RP

NC_PCIE_8_D2RN

NC_PCIE_6_R2D_CP

NC_PCIE_8_D2RP NC_PCIE_8_R2D_CN

ITPXDP_CLK100M_P

PP3V3_S0_PCH

PCIE_CLK100M_AP_N

PCH_GPIO11

NC_PCIE_8_R2D_CP

PCIE_CLK100M_ENET_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

LPC_R_AD<3>

18 OF 132 16 OF 105

16

7

17 20 25

16

16 95

6

16 95

16 17 18 19 20 22

102

16

35

16 32

16

16 95

8

16 88

16 35

16 95

6

94

16

16 95

7

20 22 25 32 41 57 71

7

19 25 33 34 35 88

16 17 18 19 20 22

102

7

16 17 18 19 20 22 46 71 72

73

16 36

16 23 31

16 23 39

16

16 33

16 17 20 22

102 104

94

16 95

6

16 23 41

6

16

10 92

16 23 92

16 95

10 92

7

16 17 18 19 20 22 46 71 72

73

16

6

16

16 95

16

6

16

16 17 20 22

102 104

7

16 17 18 19 20 22 46 71 72

73

16 23 85

16 95

16

16 95

16 17 20 22

102 104

16 23 92

16

6

16 17 18 19 20 22

102

16 23 92

16 17 18 19 20 22

102

16

IN

OUT

OUT OUT

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

(3 OF 10)

MANAGEMENT

SYSTEM POWER

DMI

FDI

DMI1RXN

DMI2RBIAS

FDI_RXP6

DMI3RXN

DMI0RXN

FDI_RXN5

FDI_RXN4

FDI_RXN2 FDI_RXN3

FDI_RXN1

FDI_RXN0

RI*

BATLOW*/GPIO72

PWROK

SYS_PWROK

SYS_RESET*

DMI_ZCOMP

DMI3TXP

DMI2TXP

DMI1TXP

DMI3TXN

DMI0TXP

DMI1TXN DMI2TXN

SUSACK*

SLP_SUS*

DSWVRMEN

DF_TVS

PMSYNCH

TP23

SLP_LAN*/GPIO29

SLP_A*

SLP_S4*

SLP_S5*/GPIO63

SUS_STAT*/GPIO61

SUSCLK/GPIO62

CLKRUN*/GPIO32

WAKE*

FDI_LSYNC1

FDI_FSYNC1

FDI_LSYNC0

FDI_FSYNC0

FDI_INT

FDI_RXP7

FDI_RXP4 FDI_RXP5

FDI_RXP2

FDI_RXP1

FDI_RXP3

FDI_RXP0

FDI_RXN7

FDI_RXN6

DRAMPWROK

DMI2RXN

DMI0TXN

DMI_IRCOMP

SLP_S3*

PWRBTN*

APWROK

RSMRST*

DMI0RXP DMI1RXP DMI2RXP DMI3RXP

DPWROK

SUSWARN*/SUSPWRDNACK/GPIO30

ACPRESENT/GPIO31

(4 OF 10)

DIGITAL DISPLAY INTERFACE

CRT

RSVD

DDPD_3P

DDPD_2P DDPD_3N

DDPD_2N

DDPD_1P

DDPD_1N

DDPD_0P

DDPD_0N

DDPD_HPD

DDPD_AUXN DDPD_AUXP

DDPD_CTRLDATA

DDPD_CTRLCLK

DDPC_3N DDPC_3P

DDPC_2N DDPC_2P

DDPC_1N

DDPC_0P

DDPC_1P

DDPC_0N

DDPC_HPD

DDPC_AUXP

DDPC_AUXN

DDPC_CTRLDATA

DDPC_CTRLCLK

DDPB_3P

DDPB_3N

DDPB_2N DDPB_2P

DDPB_1P

DDPB_1N

DDPB_0P

DDPB_HPD

DDPB_0N

DDPB_AUXP

DDPB_AUXN

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTN SDVO_INTP

SDVO_STALLN SDVO_STALLP

SDVO_TVCLKINN SDVO_TVCLKINP

CRT_BLUE CRT_GREEN CRT_RED

CRT_DDC_CLK CRT_DDC_DATA

CRT_HSYNC CRT_VSYNC

CRT_IRTN

DAC_IREF

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

IN

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Set to Vcc when High

DF_TVS:DMI & FDI Term Voltage

Set to Vss when Low

T29 WAKE

PD on SMC page

9

92

9

92

9

92

9

92

9

92

9

92

PLACE_NEAR=U1800.BJ24:12.7mm

MF

1%

49.9

1/20W

201

R1900

1

2

6

17 25 31 32 85

6

17 45 47

46

17 45 73

17 29 42 45 66 73

6

17 29 45 73

10 29 92

73

17 23 45

46

17 91

45

23 91

6

25 45

9

92

6 9

92

6 9

92

6 9

92

6 9

92

9

92

9

92

9

92

9

92

9

92

9

92

6 9

92

6 9

92

6 9

92

6 9

92

10 92

6

45 47

PLACE_NEAR=U1800.T43:2.54mm

5%

1K

MF

1/20W

201

R1951

1

2

201

1/20W

MF

5%

100K

R1909

1

2

201

1/20W MF

1%

750

R1920

1

2

PLACE_NEAR=U1800.BH21:2.54mm

5% MF

1/20W

201

2.2K

R1981

1

2

MF5%

1/20W

1K

201

R1980

12

MOBILE

FCBGA

COUGAR-POINT

OMIT

U1800

H20

L10

E10

N3

AY1

BC24

BE24

AW24

AY24

BE20

BC20

AW20

AY20

BH21

BG18

BJ18

BB18

AY18

BG20

BJ20

AV18

AU18

BG25

BJ24

E22

B13

A18

AV12 BC10

AW16

AV14 BB10

AY14 BE14 BH13 BC12 BJ12 BG10 BG9

BG14 BB14 BF14 BG13 BE12 BG12 BJ10 BH9

AP14

E20

L22

A10

C21

G10

K14

F4

H4

D10

G16

G8

C12

N14

K16

P12

K3

AY16

B9

BJ14

COUGAR-POINT

OMIT

MOBILE

FCBGA

U1800

N48

T39 M40

P49

M47

T42

T49

M49

T43

AV42 AV40 AV45 AV46 AU48

AU47 AV47

AV49

AT49 AT47 AT40

AY47 AY49 AY43 AY45 BA47 BA48 BB47 BB49

AP47 AP49

P46 P42

AT38

BB43 BB45 BF44 BE44 BF42 BE42 BJ42 BG42

AT45 AT43

M43 M36

BH41

AT1

AT10 AT12

AT3 AT4 AT5 AT8

AU2 AU3 AV1

AV10

AV3 AV5 AV7

AY3 AY5 AY7 BA2 BA3 BB1 BB3 BB5 BB7 BC8 BD4 BE8 BF3 BF6 BG4

P38 M39

AP39 AP40

AM42 AM40

AP43 AP45

390K

5% MF

1/20W

201

R1915

1

2

8.2K

5%

201

MF

1/20W

R1991

1

2

45 46 73

17

17 91

1K

1/20W

1%

201

MF

R1985

1

2

1K

1%

MF

201

1/20W

R1925

1

2

1/20W

MF

201

5%

10K

1

2

R1982

1/20W

MF

201

5%

10K

R1983

1

2

1/20W

10K

201

MF

5%

R1905

1

2

MF

0

5%

201

1/20W

R1986

12

17

17 73

100K

201

1/20W

MF

5%

R1921

1

2

100K

5%

MF

1/20W

201

R1922

1

2

100K

5%

MF

1/20W

201

R1923

1

2

201

1/20W

MF

5%

100K

R1924

1

2

6

17 25 31 32 85

6

17 25 31 32 85

PCH DMI/FDI/GRAPHICS

PCH_DMI_COMP

PCIE_WAKE_L

MAKE_BASE=TRUE

PCIE_WAKE_L

FDI_DATA_N<1> FDI_DATA_N<2>

PM_PCH_PWROK

NC_DP_IG_D_CTRL_CLK

NC_DP_IG_C_MLP<3>

PM_MEM_PWRGD

PM_SYSRST_L

NC_CRT_IG_RED

DMI_S2N_N<0>

FDI_DATA_P<7>

PM_PCH_SYS_PWROK

PM_PCH_PWROK

NC_CRT_IG_HSYNC

PCIE_WAKE_L

FDI_FSYNC<1>

DMI_S2N_N<2>

FDI_DATA_P<4>

FDI_LSYNC<0>

DMI_S2N_P<0>

TP_DP_IG_B_MLP<3>

DP_IG_HPD

DP_IG_AUX_CH_P

DMI_S2N_N<3>

NC_DP_IG_D_MLN<2>

NC_DP_IG_D_MLN<3>

NC_DP_IG_C_MLN<1>

NC_DP_IG_D_CTRL_DATA

NC_DP_IG_C_MLP<1>

NC_DP_IG_D_AUXP NC_DP_IG_D_HPD

NC_DP_IG_D_MLN<0>

NC_DP_IG_D_MLP<1>

NC_DP_IG_D_MLP<3>

NC_SDVO_TVCLKINP

NC_SDVO_TVCLKINN

NC_DP_IG_C_MLN<2>

NC_DP_IG_D_MLP<2>

NC_DP_IG_D_AUXN

NC_DP_IG_C_AUXN

NC_DP_IG_D_MLN<1>

NC_DP_IG_D_MLP<0>

FDI_DATA_N<7>

FDI_DATA_P<2>

FDI_DATA_N<0>

FDI_DATA_N<3>

FDI_DATA_N<5>

NC_SDVO_STALLN NC_SDVO_STALLP

NC_SDVO_INTN NC_SDVO_INTP

DP_IG_DDC_CLK

DP_IG_AUX_CH_N

TP_DP_IG_B_MLP<0> TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<0>

DP_IG_DDC_DATA

NC_DP_IG_C_MLP<0>

NC_DP_IG_C_MLN<0>

NC_DP_IG_C_HPD

NC_DP_IG_C_AUXP

NC_DP_IG_C_CTRL_DATA

NC_DP_IG_C_CTRL_CLK

TP_DP_IG_B_MLP<1> TP_DP_IG_B_MLN<2> TP_DP_IG_B_MLP<2> TP_DP_IG_B_MLN<3>

NC_DP_IG_C_MLN<3>

NC_CRT_IG_DDC_DATA

NC_CRT_IG_GREEN

NC_CRT_IG_BLUE

PPVRTC_G3H

NC_DP_IG_C_MLP<2>

FDI_DATA_P<5> FDI_DATA_P<6>

FDI_FSYNC<0>

FDI_DATA_N<6>

FDI_DATA_P<0>

NC_CRT_IG_VSYNC

NC_CRT_IG_DDC_CLK

PP3V3_SUS

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2>

DMI_N2S_N<0>

PPVCCIO_S0_PCH

DMI_N2S_N<2>

DMI_S2N_N<1>

PCH_DMI2RBIAS

PM_RSMRST_L

FDI_DATA_N<4>

FDI_INT

PM_BATLOW_L

PCIE_WAKE_L

PM_PWRBTN_L

SUSWARN_L

PCH_SUSACK_L

GPIO29_SLP_LAN_L

FDI_LSYNC<1>

PM_CLK32K_SUSCLK_R

LPC_PWRDWN_L

PM_CLKRUN_L

FDI_DATA_P<3>

FDI_DATA_P<1>

DMI_N2S_N<1>

PCH_DAC_IREF

CPU_PROC_SEL_L

PCH_SUSACK_L

SUSWARN_L GPIO29_SLP_LAN_L

PP1V8_S0_PCH

PCH_DF_TVS

PM_SLP_S4_L

PM_SYNC

TP_PCH_TP23

PM_SLP_S4_L

PM_SLP_S5_L

PM_SLP_S3_L

PM_SLP_S5_L

PM_SLP_SUS_L

TP_PM_SLP_A_L

PM_SLP_S3_L

PCH_DSWVRMEN

PM_SLP_SUS_L

PM_CLKRUN_L

PP3V3_S0_PCH

DMI_N2S_N<3>

DMI_S2N_P<3>

DMI_S2N_P<2>

DMI_S2N_P<1>

DMI_N2S_P<3>

PM_DSW_PWRGD

SMC_ADAPTER_EN

SUSWARN_L

PP3V3_SUS

PCH_RI_L

PP3V3_S5

PP3V3_SUS

19 OF 132 17 OF 105

9

92

9

92

6

9

92

6

9

92

8

84

8

84 94

6

9

92

9

92

9

92

9

92

9

92

6

8

80 84

8

84 94

8

80 84

6

7

16 20 25

6

9

92

9

92

9

92

9

92

6

7

16 17 18 19 20 22 46 71 72 73

16 20 22

102 104

9

92

6

17 25 31 32 85

17 23 45

17

9

92

9

92

10 92

17

20 22

102

17 29 42 45 66 73

6

17 29 45 73

17 45 73

17 73

6

17 45 47

16 18 19 20 22

102

17

7

16 17 18 19 20 22 46 71

72 73 6 7

19 20 22 23 24

25 29 46 48 56 71 72 73 83

86 91

100 102

104

7

16 17 18 19 20 22 46

71 72 73

OUT

USBP2N

USBP1N USBP1P

USBP0N USBP0P

OC7*/GPIO14

OC6*/GPIO10

OC5*/GPIO9

OC4*/GPIO43

OC3*/GPIO42

OC2*/GPIO41

OC1*/GPIO40

OC0*/GPIO59

USBRBIAS*

USBRBIAS

USBP13P

USBP13N

USBP12P

USBP12N

USBP11P

USBP11N

USBP10P

USBP10N

USBP9P

USBP9N

USBP8P

USBP8N

USBP7N USBP7P

USBP6N USBP6P

USBP5N USBP5P

USBP4P

USBP4N

USBP3P

USBP3N

USBP2P

PIRQA* PIRQB* PIRQC* PIRQD*

REQ1*/GPIO50

REQ3*/GPIO54

REQ2*/GPIO52

GNT2*/GPIO53

GNT1*/GPIO51

GNT3*/GPIO55

PIRQE*/GPIO2 PIRQF*/GPIO3 PIRQG*/GPIO4 PIRQH*/GPIO5

PME*

CLKOUT_PCI0

PLTRST*

CLKOUT_PCI2

CLKOUT_PCI1

CLKOUT_PCI3 CLKOUT_PCI4

LVDSA_DATA2*

LVDSA_DATA1*

LVDSA_DATA0*

LVDSA_DATA3*

LVDSA_DATA0

LVDSA_DATA2

LVDSA_DATA1

LVDSA_CLK*

LVDSA_DATA3

LVDSA_CLK

LVDSB_DATA0* LVDSB_DATA1* LVDSB_DATA2* LVDSB_DATA3*

LVDSB_DATA1

LVDSB_DATA0

LVDSB_DATA2 LVDSB_DATA3

LVDSB_CLK* LVDSB_CLK

L_BKLTEN

L_BKLTCTL

LVD_VREFL

LVD_VREFH

LVD_VBG

LVD_IBG

L_VDD_EN

L_CTRL_DATA L_DDC_CLK L_DDC_DATA

L_CTRL_CLK

(5 OF 10)

USB

PCI

LVDS

OUT OUT OUT

OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT OUT OUT

OUT OUT

BI BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Camera

USB HUB 2

USB HUB 1

Unused

88 94

COUGAR-POINT

FCBGA

OMIT

MOBILE

U1800

H49 H43 J48 K42 H40

D47 E42 F46

P45 J47

T45 P39 T40 K47

M45

AF37 AF36

AE48 AE47

AK40

AK39

AN47

AN48

AM49

AM47

AK49

AK47

AJ47

AJ48

AF39

AF40

AH43

AH45

AH49

AH47

AF47

AF49

AF43

AF45

A14 K20 B17 C16 L16 A16 D14 C14

K40 K38 H38 G38

G42 G40 C42 D44

C6

K10

C46 C44 E40

C24 A24

C30 A30

L32 K32

G32 E32

C32 A32

C25 B25

C26 A26

K28 H28

E28 D28

C28 A28

C29 B29

N28 M28

L30 K30

G30 E30

B33

C33

88 94

8

94

88 94

8

94

88 94

8

88 94

6 8

88 94

8

2.37K

1%

1/20W

MF

201

PLACE_NEAR=U1800.AF37:2.54mm

R2050

1

2

5%

MF

NOSTUFF

201

10K

1/20W

R2054

1

2

6 8

8

18 88

8

18 88

84

MF

1/20W

5%

201

10K

R2011

1 2

10K

5%

201

MF

1/20W

R2012

1 2

201

1/20W

MF

10K

5%

R2013

1 2

1/20W

5%

10K

MF

201

R2016

1 2

201

5% MF

10K

1/20W

R2017

1 2

1/20W

MF5%

10K

201

R2018

1 2

1/20W

201

5% MF

10K

R2030

1 2

MF

10K

201

1/20W

5%

R2014

1 2

NOSTUFF

1/20W

MF

201

5%

10K

R2053

1

2

5%

NOSTUFF

10K

1/20W

MF

201

R2052

1

2

201

MF

1/20W

5%

100K

R2055

1

2

1/20W

10K

201

MF

5%

R2061

1

2

10K

MF

201

1/20W

5%

R2062

1

2

MF

1/20W

10K

5%

201

R2064

1

2

MF

201

5%

10K

1/20W

R2065

1

2

5% 1/20W MF 201

10K

R2067

1

2

10K

1/20W

201

MF

5%

R2069

1

2

10K

5%

201

1/20W MF

R2068

1

2

5% MF-LF

402

1/16W

100K

R2015

1

2

5%

1/20W

201

10K

MF

R2031

1 2

24 94

1%

22.6

PLACE_NEAR=U1800.B33:2.54mm

MF

1/20W

201

R2070

1

2

201

5% MF

1/20W

10K

R2010

1 2

25 29 39

25

25 95

25

201

1/20W

5%

10K

MF

R2060

1

2

SYNC_DATE=10/20/2010

PCH PCI/FLASHCACHE/USB

SYNC_MASTER=K91_MLB

PP3V3_S0_PCH

T29_MCU_INT_L

PCI_INTE_L AUD_IP_PERIPHERAL_DET

NC_PCI_CLK33M_OUT3 PCH_CLK33M_PCIOUT

NC_PCI_PME_L

PCH_USB_RBIAS

USB_HUB_SOFT_RESET_L

SDCONN_STATE_CHANGE

PCH_GPIO43_OC4_L

PCH_GPIO52

JTAG_GMUX_TMS

PCI_INTC_L

PCI_INTA_L

NC_USB_11P

NC_USB_12N NC_USB_12P

NC_USB_13N NC_USB_13P

NC_USB_11N

NC_USB_10N

USB_CAMERA_P

USB_CAMERA_N

USB_HUB2_UP_P

USB_HUB2_UP_N

NC_USB_7P

NC_USB_7N

NC_USB_6P

NC_USB_6N

NC_USB_5P

NC_USB_5N

NC_USB_4P

NC_USB_4N

NC_USB_3P

NC_USB_2P

NC_USB_1P

NC_USB_3N

NC_USB_2N

NC_USB_1N

USB_HUB1_UP_N USB_HUB1_UP_P

LVDS_IG_A_DATA_P<1>

LVDS_IG_DDC_CLK

NC_LVDS_IG_CTRL_CLK

LVDS_IG_PANEL_PWR

TP_LVDS_IG_BKL_PWM

PCH_LVDS_IBG

LVDS_IG_BKL_ON

LVDS_IG_PANEL_PWR

PCH_PCI_GNT1_L

NC_LVDS_IG_CTRL_DATA

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_DDC_DATA

LVDS_IG_BKL_ON

TP_LVDS_IG_B_CLKP

NC_LVDS_IG_A_DATAN<3>

PCH_PCI_GNT3_L PCH_PCI_GNT2_L

LVDS_IG_B_DATA_N<2>

LVDS_IG_A_CLK_P

NC_LVDS_IG_B_DATAN<3>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

NC_PCH_LVDS_VBG

LPC_CLK33M_LPCPLUS_R

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<0>

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_DATA_N<2>

PCH_PCI_GNT3_L

PCH_PCI_GNT2_L

AP_PWR_EN

PCH_GPIO10_OC6_L

SDCONN_STATE_RST_L

PP3V3_S3

PP3V3_SUS

PCH_GPIO14_OC7_L

LVDS_IG_A_DATA_N<0>

LPC_CLK33M_GMUX_R

LPC_CLK33M_SMC_R

PLT_RESET_L

AUD_I2C_INT_L

NC_LVDS_IG_B_DATAP<3>

TP_LVDS_IG_B_CLKN

ENET_PWR_EN

NC_USB_10P

PCH_PCI_GNT1_L

PCI_REQ3_L

PCI_INTD_L

PCI_INTB_L

20 OF 132 18 OF 105

16 17 19 20 22

102

85

62

6

94

23 24

23

88

31

6

8

18 88

8

18 88

18

6

18

6

18

31 73

23

6 7 8

24 25 29 30 31 32 48 49 50 54 55 73

88

104

7

16 17 19 20 22 46 71 72 73

23

25

62

23

18

OUT

BI

IN

CPU

NCTF

MISC

(6 OF 10)

GPIO

RSVD

TP38

SATA3GP/GPIO37

TACH5/GPIO69

TP18

STP_PCI*/GPIO34

GPIO15

SATA4GP/GPIO16

CLKOUT_PCIE7P

A20GATE

TACH3/GPIO7

LAN_PHY_PWR_CTRL/GPIO12

GPIO8

TACH0/GPIO17

GPIO24/MEM_LED

SCLOCK/GPIO22

GPIO27

GPIO28

GPIO35

SATA2GP/GPIO36

SLOAD/GPIO38

SDATAOUT0/GPIO39

PCIECLKRQ6*/GPIO45

PCIECLKRQ7*/GPIO46

SATA5GP/GPIO49

SDATAOUT1/GPIO48

TACH4/GPIO68

GPIO57

TACH6/GPIO70

TACH7/GPIO71

CLKOUT_PCIE6N

CLKOUT_PCIE7N

CLKOUT_PCIE6P

BMBUSY*/GPIO0

TACH2/GPIO6

TACH1/GPIO1

PECI

RCIN*

THRMTRIP*

PROCPWRGD

TP1

TP2

TP3

TP4

TP6

TP5

TP7

TP8

TP9

TP10

TP11

TP12

TP13

TP14

TP15

TP16

TP17

TP19

TP20

TP21

TP22

TP24

TP25

TP26

TP27

TP29

TP28

TP30

TP31

TP32

TP33

TP34

TP35

TP36

NC_1

INIT3_3V*

TP40

TP39

TP37

VSS_NCTF

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

VSS_NCTF

VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF VSS_NCTF

TS_VSS1 TS_VSS2 TS_VSS3

VSSADAC

TS_VSS4

IN

NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC NC

NC NC NC NC

IN

OUT

IN

BI

IN

OUT

NC

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

(PUs necessary?)

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

This has internal pull up and should not pulled low.

(IPU)

(NC-ed per Intel chklist)

(PU necessary?)

PD on audio page

ALL RSVD TPs NC-ed per INTEL approval

10 23 92

23 29

6

47

NOSTUFF

1/20W

201

5%

43

MF

R2170

1 2

5%

0

1/20W

201

MF

R2140

1 2

19 23

FCBGA

MOBILE

COUGAR-POINT

OMIT

U1800

P4

T7 V40

V42

V38 V37

G2

E8

E16

P8

K4

D6

C10

T14

C4

P37

T13

K12

AU16

AY11

P5

V8

M5

U2

V3

T5

M3

V13

N2

K1

D40

A42

H36

E38

C40

B41

C41

A40

AY10

BG26

C18

N30

H3

AH12

AM4

AM5

Y13

K24

L24

AB46

BJ26

AB45

B21

M20

BG46

BE28

BC30

BE32

BJ32

BC28

BH25

BE30

BF32

BG32

AV26

BB26

AU28

AY30

AU26

AY26

AV28

BJ16

AW30

BG16

AH38

AH37

AK43

AK45

AH8 AK11 AH10 AK10

A4

A44

BE1 BE49

BF1 BF49

BG2 BG48

BH3 BH47

BJ4 BJ44

A45

BJ45 BJ46

BJ5

BJ6

C2

C48

D1

D49

E1

E49

A46

F1

F49

A5 A6

B3 B47 BD1

BD49

U47

19 88

201

1/20W

MF

NOSTUFF

1K

5%

R2130

1

2

1/20W

201

10K

MF

5%

R2185

1

2

8

19 39

23 62

19 41

8

19 23 33 88

8

19 33 88

6

19 47 56

10 92

MF

390

1/20W

5%

201

R2156

1 2

MF

1/20W

201

10K

5%

R2160

1

2

MF

201

1/20W

5%

10K

R2184

1

2

MF

201

1/20W

10K

5%

R2186

1

2

5%

10K

1/20W

MF

201

R2172

1

2

MF

201

10K

5%

1/20W

R2173

1

2

10K

MF

201

5%

1/20W

R2174

1

2

5%

10K

201

1/20W

MF

R2175

1

2

1/20W

10K

5%

MF

201

NOSTUFF

R2115

1

2

MF

10K

201

5%

1/20W

R2114

1

2

201

5%

10K

1/20W

MF

R2192

1

2

201

MF

1/20W

5%

100K

R2193

1

2

MF

1/20W

201

5%

20K

R2111

1

2

10K

5%

1/20W

201

MF

R2112

1

2

MF

1/20W

201

5%

10K

R2113

1

2

100K

1/20W

5%

201

MF

R2190

1

2

5%

201

1/20W

MF

10K

R2199

1

2

1/20W

MF

201

10K

5%

R2198

1

2

201

MF

1/20W

5%

10K

R2195

1

2

5%

10K

1/20W

MF

201

R2196

1

2

201

MF

5%

10K

1/20W

NOSTUFF

R2197

1

2

5%

10K

201

1/20W

MF

R2155

1

2

10K

201

1/20W

MF

5%

R2150

1

2

16 19 45

19 32 36

1/20W

5%

10K

201

MF

NOSTUFF

R2116

1

2

1/20W

10K

5%

201

MF

R2194

1

2

10K

5%

1/20W

MF

201

R2191

1

2

MF

1/20W

NOSTUFF

201

5%

10K

R2117

1

2

8

19 33 88

19 73

19 39

19 45 46

PCH MISC

SYNC_MASTER=K91_MLB

SYNC_DATE=10/20/2010

PP3V3_SUS

SPIROM_USE_MLB

ODD_PWR_EN_L

PCH_GPIO24

PCH_GPIO12

PM_THRMTRIP_L_R

SMC_RUNTIME_SCI_L PCH_GPIO49_SATA5GP

SMC_RUNTIME_SCI_L

PCH_GPIO15

AUD_IPHS_SWITCH_EN

JTAG_ISP_TDO

PCH_GPIO46

LPCPLUS_GPIO

SMC_SCI_L

GMUX_INT

FW_PLUG_DET_L

PCH_GPIO0

ODD_PWR_EN_L

PCH_GPIO24

PP3V3_S0_PCH

JTAG_ISP_TCK

GMUX_INT

ENET_LOW_PWR

PCH_GPIO68_TACH4

PP3V3_S0_PCH

T29_SW_RESET_L

PCH_A20GATE

JTAG_ISP_TCK

PCH_GPIO70_TACH6

PCH_GPIO68_TACH4

PP3V3_S5

SMC_SCI_L

PCH_GPIO0

PM_THRMTRIP_L

PCH_RCIN_L

PCH_PECI

JTAG_ISP_TDI

PCH_GPIO46

NC_PCIE_CLK100M_PE6N

PCH_INIT3V3_L

NC_PCIE_CLK100M_PE7P

NC_PCIE_CLK100M_PE7N

CPU_PECI

PCH_INIT3V3_L

PCH_PROCPWRGD

PP3V3_S0_PCH

CPU_PWRGD

NC_PCIE_CLK100M_PE6P

PCH_GPIO71_TACH7

PCH_GPIO36_SATA2GP ENET_LOW_PWR

PCH_GPIO12

PP3V3_S0_PCH

PCH_GPIO71_TACH7

PP3V3_T29

PP3V3_S0_PCH

WOL_EN

PCH_GPIO69_TACH5

PP3V3_SUS

PCH_GPIO15

PP3V3_T29

FW_PWR_EN

FW_PLUG_DET_L

JTAG_ISP_TDO

JTAG_ISP_TDI

SPIROM_USE_MLB

FW_PWR_EN

WOL_EN

PCH_GPIO36_SATA2GP

T29_SW_RESET_L

ISOLATE_CPU_MEM_L

PCH_GPIO69_TACH5

NC_GPIO35

21 OF 132 19 OF 105

7

16 17 18 19 20 22 46 71

72 73

6

19 47 56

19 41

19

46

19 45 46

23

19

19 23

19

16 17 18 19 20 22

102

8

19 23 33 88

19 88

19

16 17 18 19 20 22 102

19 35

19

6 7

17 20 22 23 24 25 29 46 48 56 71 72

73 83 86 91

100 102 104

16 19 45

19 23

8

19 33 88

19 23

6

19

6

10 45 92

19

16 17 18 19 20 22

102

6

19

19 23

19 32 36

19

16 17 18 19 20 22

102

19

7

16 19 25

33 34 35 88

16 17 18 19 20 22

102

19 73

19

7

16 17 18 19 20 22 46 71 72

73

19

7

16 19 25 33 34 35 88

19 39

8

19 39

8

19 33 88

19 23

19 35

19

VSSALVDS

VCCTX_LVDS

VCCDFTERM

VCCALVDS

VCCVRM_3_DMI

VCC3_3_7_HVCMOS

VCC3_3_5_PCI

VCCDFTERM

VCCSPI

VCCDFTERM

VCC3_3_6_HVCMOS

VCCIO_18_FDI

VCCIO_21_PCIE

VCCIO_20_PCIE

VCCIO_11_PLLPCIE

VCCIO_25_PCIE

VCCIO_24_PCIE

VCCCLKDMI

VCCCORE

VCCIO_27_DP

VCCIO_26_PCIE

VCCIO_19_PCIE

VCCIO_22_PCIE

VCCIO_10_PLLFDI

VCCIO_23_PCIE

VCCIO_17_FDI

VCCIO_28_DP

VCCDMI_0_FDI

VCCAPLLEXP

VCCCORE

VCCDMI_1_DMI

VCCCORE VCCCORE VCCCORE

VCCAFDIPLL

VCCCORE

VCCVRM_2_FDI

VCCADAC

VCCCORE

FDI CRT

DFT/SPI

DMI

HVCMOS

VCCIO

VCC CORE

LVDS

(7 OF 10)

VCCSUSHDA

VCCSUS3_3_3_USB VCCSUS3_3_4_USB

VCCSUS3_3_2_USB

VCCSUS3_3_1_USB

VCCIO_4_USB

VCCIO_2_USB VCCIO_3_USB

VCCIO_1_USB

VCCIO_0_USB

VCCASW_0_MISC

VCCASW_2_MISC VCCASW_1_MISC

VCCIO_8_SATA

VCCIO_6_SATA VCCIO_7_SATA

VCCAPLLSATA

VCCVRM_1_SATA

VCCIO_9_PLLSATA3

VCCIO_15_SATA3 VCCIO_16_SATA3

VCC3_3_0_SATA

VCCIO_5_PLLSATA

VCC3_3_2_GPIO VCC3_3_3_GPIO VCC3_3_1_GPIO

VCCSUS3_3_7_GPIO VCCSUS3_3_8_GPIO

VCCSUS3_3_5_GPIO VCCSUS3_3_6_GPIO

V5REF

VCCRTC

V_PROC_IO

DCPSUSBYP

VCCACLK

DCPRTC

VCCADPLLA VCCADPLLB

DCPSST

DCPSUS_2_CLK

DCPSUS_1_CLK

VCCDIFFCLKN_2

VCCDIFFCLKN_1

VCCDIFFCLKN_0

VCCDSW3_3

VCCIO_13_CLK

VCC3_3_4_CLK

VCCASW_4_CLK VCCASW_5_CLK VCCASW_6_CLK VCCASW_7_CLK VCCASW_8_CLK

VCCAPLLDMI2

VCCASW_20_CLK

VCCASW_10_CLK VCCASW_11_CLK VCCASW_12_CLK VCCASW_13_CLK VCCASW_14_CLK VCCASW_15_CLK VCCASW_16_CLK VCCASW_17_CLK VCCASW_18_CLK VCCASW_19_CLK

VCCASW_9_CLK

VCCVRM_0_CLK

VCCASW_22_CLK

VCCASW_21_CLK

VCCSSC

VCCSUS3_3_9_USB

VCCIO_14_PLLUSB

V5REF_SUS

VCCSUS3_3_0_SUS

DCPSUS_3_SUS

VCCASW_3_CLK

DCPSUS_0_CLK

VCCIO_12_PLLCLK

CPURTC

HDA

USB

MISC

SATA

PCI/GPIO/

LPC

CLK/MISC

(8 OF 10)

NC

NC NC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AL24 left as NC per DG

VCCAPLLDMI2 pin left as NC per DG

55mA Max, 5mA Idle

PCH output, for decoupling only

1.44 A Max, 474mA Idle

VCCAFDIPLL pin left as NC per DG

VCCAPLLSATA pin left as NC per DG

NC-ed per DG

VCCACLK pin left as NC per DG

10 mA Max, 1mA Idle

NC-ed per DG

OMIT

COUGAR-POINT

FCBGA

MOBILE

U1800

BH29

V33 V34

U48

BG6

AK36

BJ22

AB36

AA23 AC23

AG27 AG29 AJ23 AJ26 AJ27 AJ29 AJ31

AD21 AD23 AF21 AF23 AG21 AG23 AG24 AG26

AG16 AG17 AJ16 AJ17

AU20

AT20

AP17

AN19

AN16 AN17

AN21 AN26 AN27 AP21 AP23 AP24 AP26 AT24

AN33 AN34

V1

AM37 AM38 AP36 AP37

AP16

AT16

AK37

FCBGA

COUGAR-POINT

OMIT

MOBILE

U1800

N16

V16

AL24

T17 V19

AN23

V12

P34

M26

BJ8

AJ2

T34

AA16 W16

T38

AD49

BD47 BF47

BH23

AK1

T19

AC26 AC27 AC29 AC31 AD29 AD31

W21 W23 W24 W26

V21

W29 W31 W33

T21

AA19 AA21 AA24 AA26 AA27 AA29 AA31

AF33 AF34 AG34

T16

N26

AL29

AF17

T26

AH13 AH14

P26 P28 T27 T29

AF13

AC16 AC17 AD17

AF14

A22

AG33

AN24

T23 T24 V23 V24

N20 N22 P20 P22

P24

P32

Y49

AF11

0.1UF

CERM

20% 10V

402

PLACE_NEAR=U1800.A22:2.54mm

C2232

1

2

CERM

10%

1UF

6.3V

402

PLACE_NEAR=U1800.A22:2.54mm

C2231

1

2

CERM

0.1UF

PLACE_NEAR=U1800.V16:2.54mm

20% 10V

402

C2222

1

2

PLACE_NEAR=U1800.N16:2.54mm

0.1UF

CERM

20%

402

10V

C2210

1

2

CERM

PLACE_NEAR=U1800.A22:2.54mm

402

20% 10V

0.1UF

C2233

1

2

PCH POWER

PP1V5_S0

PP3V3_SUS

PP5V_SUS_PCH_V5REFSUS

PPVOUT_G3_PCH_DCPRTC

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.2 mm

PP3V3_SUS

PP3V3_S0_PCH

TP_1V05_S0_PCH_VCCAPLLEXP

PP1V05_S0_PCH_VCCCLKDMI_F

PPVCCIO_S0_PCH

PP3V3_S0_PCH

PPVCCIO_S0_PCH

PP1V8_S0_PCH_VCCTX_LVDS_F

PPVCCIO_S0_PCH

PP1V8_S0

PP1V8_S0_PCH

PP3V3_S0_PCH_VCCA_DAC_F

PP3V3_S5

PP3V3_S0_PCH

TP_PPVOUT_PCH_DCPSUSBYP

PPVCCIO_S0_PCH

PP3V3_S0_PCH

PP1V8_S0

PP5V_S0_PCH_V5REF

PPVCCIO_S0_PCH

PPVRTC_G3H

PP3V3_S5

PPVCCIO_S0_PCH

PP1V8_S0

PPVCCIO_S0_PCH

PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLA_F

PP3V3_SUS

PPVCCIO_S0_PCH

PP3V3_S0_PCH_VCC3_3_CLK_F

PPVCCIO_S0_PCH

22 OF 132 20 OF 105

7

16 22 25 32 41 57 71

7

16 17 18 19 20 22 46 71 72 73

22

7

16 17 18 19 20 22 46 71 72 73

16 17 18 19 20 22

102

22

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

16 17 18 19 20 22

102

16 17 20 22

102 104

16 17 20 22

102 104

22

16 17 20 22

102 104

6 7

14 20 25 71 72 88

102

6 7

14 20 25 71 72 88

102

17 22

102

22

6 7

17 19 20 22 23 24 25 29

46 48 56 71 72 73 83 86 91

100 102 104

16 17 18 19 20 22

102

16 17 18 19 20 22

102

16 17 20 22

102 104

16 17 18 19 20 22

102

6 7

14 20 25 71 72 88

102

22

16 17 20 22

102 104

7

16 17 25

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

16 17 20 22

102 104

6 7

14 20 25 71 72 88

102

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

22

7

16 17 18 19 20 22 46 71 72 73

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

22

16 17 20 22

102 104

VSS

(9 OF 10)

VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS

VSS

VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS

(10 OF 10)

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS

VSS

VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS VSS VSS

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OMIT

FCBGA

MOBILE

COUGAR-POINT

U1800

AJ3 N24

AB14

AL48 AM11 AM14 AM36 AM39 AM43 AM45 AM46 AM7 AN2

AB39

AN29 AN3 AN31 AP12 AP13 AP19 AP28 AP30 AP32 AP38

AB4

AP4 AP42 AP46 AP8 AR2 AR48 AT11 AT13 AT18 AT22

AB43

AT26 AT28 AT30 AT32 AT34 AT39 AT42 AT46 AT7 AU24

AB5

AU30 AV11 AV16 AV20 AV24 AV30 AV38 AV4 AV43 AV8

AB7

AW14 AW18 AW2 AW22 AW26 AW28 AW32 AW34 AW36 AW40

AC19

AW48 AY12 AY22 AY28 AY4 AY42 AY46 AY8 B11 B15

AC2

B19 B23 B27 B31

AC21 AC24

BG29

AC33 AC34 AC48 AD10 AD11 AD12 AD13 AD14 AD16 AD19

H5

AD24 AD26 AD27 AD33 AD34 AD36 AD37 AD38 AD39

AD4

AA17

AD40 AD42 AD43 AD45 AD46 AD47

AD8 AE2 AE3

AF10

AA2

AF12 AF16 AF19 AF24 AF26 AF27 AF29 AF31 AF38

AF4

AA3

AF42 AF46

AF5 AF7 AF8

AG19

AG2 AG31 AG48 AH11

AA33

AH3 AH36 AH39 AH40 AH42 AH46

AH7 AJ19 AJ21 AJ24

AA34

AJ33 AJ34 AK12

AK3 AK38

AK4 AK42

AK46 AK8 AL16

AB11

AL17 AL19 AL2 AL21 AL23 AL26 AL27 AL31 AL33 AL34

OMIT

FCBGA

COUGAR-POINT

MOBILE

U1800

B35

B39 B43

B7 BB12 BB16 BB20 BB22 BB24 BB28 BB30 BB38

BB4 BB46 BC14 BC18

BC2 BC22 BC26 BC32 BC34 BC36 BC40 BC42 BC48

BD3 BD46

BD5 BE10 BE22 BE26 BE40 BF10 BF12 BF16 BF20 BF22 BF24 BF26 BF28 BF30 BF38 BF40

BF8 BG17 BG21 BG22 BG24 BG33 BG41 BG44

BG8 BH11 BH15 BH17 BH19 BH27 BH31 BH33 BH35 BH39 BH43

BH7

C22

D12

D16

D18

D22

D24

D26

D3 D30 D32 D34 D38 D42

D8 E18 E26

F3 F45 G14 G18 G20 G26 G28 G36

G48 H10 H12 H16 H18 H22 H24 H26 H30 H32 H34 H46 K18 K26 K39 K46 K7 L18 L2 L20 L26 L28 L36 L48 M12 M14 M18 M22 M24 M30 M32 M34 M38 M4 M42 M46 M8 N18 N47 P11 P16 P18 P30 P40 P43 P47 P7 R2 R48 T12 T31 T33 T36 T37 T4 T46 T47 T8 V11 V26 V27 V29 V31 V36 V39 V43 V7 W17 W19 W2 W27 W34 W48 Y12 Y38 Y4 Y42 Y46 Y8 V17 AP3 AP1 BE16 BC16 BG28 BJ28

SYNC_MASTER=K92_YUN

SYNC_DATE=05/20/2010

PCH GROUNDS

23 OF 132 21 OF 105

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH VCCCORE BYPASS

(PCH Reference for 5V Tolerance on USB)

PCH VCCSUSHDA BYPASS

PCH VCCIO BYPASS

1 mA

<1 MA

PCH VCCIO BYPASS (PCH USB 1.05V PWR)

69 mA

1 mA S0-S5

(PCH 1.05V CORE PWR)

(PCH SUSPEND USB 3.3V PWR)

PCH VCCSUS3_3 BYPASS

NEED PWR CONSTRAINT

(PCH Reference for 5V Tolerance on PCI)

68 mA

PCH VCCADPLLA Filter (PCH DPLLA PWR)

PCH VCCADPLLB Filter (PCH DPLLB PWR)

(PCH PCI 3.3V PWR)

PCH V5REF Filter & Follower

PCH VCC3_3 BYPASS

PCH V5REF_SUS Filter & Follower

<1 MA S0-S5

NEED PWR CONSTRAINT

PLACE_NEAR=U1800.P34:2.54mm

X5R

10% 10V

1UF

402

C2439

1

2

MF-LF

1/16W

402

5%

100

R2405

2

1

PLACE_NEAR=U1800.M26:2.54mm

20% 10V

402

CERM

0.1UF

C2438

1

2

BAT54DW-X-G

SOT-363

D2400

1

6

5

402

1/16W

5%

10

MF-LF

R2404

2

1

SOT-363

BAT54DW-X-G

D2400

4

3

2

PLACE_NEAR=U1800.AJ2:2.54mm

10% 16V

0.1UF

X5R 402

C2423

1

2

10V

402

CERM

20%

0.1UF

PLACE_NEAR=U1800.AJ16:2.54mm

C2440

1

2

PLACE_NEAR=U1800.P32:2.54mm

402

CERM

20%

0.1UF

10V

C2441

1

2

6.3V

1UF

10% CERM

402

PLACE_NEAR=U1800.AT20:2.54mm

C2419

1

2

PLACE_NEAR=U1800.BH29:2.54mm

10%

402

X5R

16V

0.1UF

C2421

1

2

X5R

16V

402

10%

0.1UF

PLACE_NEAR=U1800.V24:2.54mm

C2413

1

2

402

0.1UF

16V X5R

10%

PLACE_NEAR=U1800.BJ8:2.54mm

C2417

1

2

6.3V

402

20%

4.7UF

X5R

PLACE_NEAR=U1800.BJ8:2.54mm

C2416

1

2

PLACE_NEAR=U1800.P24:2.54mm

10%

0.1UF

402

16V X5R

C2484

1

2

25V

10% X5R

402

0.1UF

PLACE_NEAR=U1800.AA16:2.54mm

C2485

1

2

PLACE_NEAR=U1800.AN27:2.54mm

6.3V

402

1UF

10% CERM

C2463

1

2

10%

6.3V CERM 402

1UF

PLACE_NEAR=U1800.AG33:2.54mm

C2475

1

2

PLACE_NEAR=U1800.AF34:2.54mm

6.3V

402

10%

1UF

CERM

C2434

1

2

PLACE_NEAR=U1800.AF17:2.54mm

CERM

6.3V

402

1UF

10%

C2469

1

2

PLACE_NEAR=U1800.AN27:2.54mm

CERM

6.3V

402

10%

1UF

C2414

1

2

PLACE_NEAR=U1800.AN27:2.54mm

X5R-CERM

16V

10%

0805

10UF

C2401

1

2

402

10%

PLACE_NEAR=U1800.AC17:2.54mm

CERM

6.3V

1UF

C2452

1

2

PLACE_NEAR=U1800.T16:2.54mm

10V

CERM

20%

402

0.1UF

C2499

1

2

10%

6.3V 402

1UF

CERM

PLACE_NEAR=U1800.V1:2.54mm

C2442

1

2

402

X5R

10%

0.1UF

25V

PLACE_NEAR=U1800.T34:2.54mm

C2486

1

2

PLACE_NEAR=U1800.AH13:2.54mm

10%

6.3V 402

CERM

1UF

C2444

1

2

PLACE_NEAR=U1800.P28:2.54mm

402

CERM

10%

1UF

6.3V

C2446

1

2

0.1UF

10% X5R

16V 402

PLACE_NEAR=U1800.V33:2.54mm

C2424

1

2

PLACE_NEAR=U1800.AG26:2.54mm

20%

10UF

CERM

805

6.3V

CRITICAL

C2460

1

2

PLACE_NEAR=U1800.AG24:2.54mm

6.3V CERM

10%

1UF

402

C2482

1

2

6.3V

1UF

CERM

10%

PLACE_NEAR=U1800.AD21:2.54mm

402

C2481

1

2

PLACE_NEAR=U1800.AJ27:2.54mm

6.3V CERM 402

1UF

10%

C2483

1

2

PLACE_NEAR=U1800.AN27:2.54mm

6.3V CERM

1UF

402

10%

C2407

1

2

PLACE_NEAR=U1800.AN27:2.54mm

6.3V

402

10% CERM

1UF

C2429

1

2

PLACE_NEAR=U1800.AC27:2.54mm

22UF

805

CERM

20%

6.3V

C2420

1

2

402

CERM

1UF

10%

6.3V

PLACE_NEAR=U1800.AC27:2.54mm

C2496

1

2

10%

6.3V

402

1UF

CERM

PLACE_NEAR=U1800.AC27:2.54mm

C2456

1

2

402

10%

6.3V CERM

1UF

PLACE_NEAR=U1800.AC27:2.54mm

C2426

1

2

MF-LF

1

5%

1/16W

402

R2415

1 2

402

PLACE_NEAR=U1800.AB36:2.54mm

10% 16V

1UF

X5R

C2411

1

2

0.1UF

X5R

10% 16V

402

PLACE_NEAR=U1800.BJ8:2.54mm

C2430

1

2

CERM

805

6.3V

20%

22UF

PLACE_NEAR=U1800.AC27:2.54mm

C2428

1

2

10%

CERM

402

16V

PLACE_NEAR=U1800.AM37:2.54mm

0.01UF

C2406

1

2

CRITICAL

6.3V

20%

805

CERM

PLACE_NEAR=U1800.AM37:2.54mm

22UF

C2400

1

2

PLACE_NEAR=U1800.AM37:2.54mm

16V

10%

402

CERM

0.01UF

C2408

1

2

CRITICAL

0805

0.1UH

L2407

1 2

201

MF

1/20W

5%

0

R2450

1 2

PLACE_NEAR=U1800.U48:2.54mm

CERM

402

10%

0.01UF

16V

C2455

1

2

10% X5R

16V

0.1UF

PLACE_NEAR=U1800.U48:2.54mm

402

C2451

1

2

CRITICAL

10UF

CERM

PLACE_NEAR=U1800.U48:2.54mm

6.3V 805

20%

C2450

1

2

5%

1

402

1/16W MF-LF

R2451

1 2

CRITICAL

10UF

X5R 603

20%

6.3V

PLACE_NEAR=U1800.T38:2.54mm

C2453

1

2

1UF

402

10V

10% X5R

PLACE_NEAR=U1800.T38:2.54mm

C2454

1

2

CRITICAL

0603

10UH-0.12A-0.36OHM

L2451

1 2

10%

6.3V 402

CERM

1UF

PLACE_NEAR=U1800.P22:2.54mm

C2476

1

2

CRITICAL

20%

2.5V

POLY-TANT

CASE-B2-SM1

PLACE_NEAR=U1800.BD47:2.54MM

220UF

C2491

1

2

10% CERM

402

6.3V

1UF

NO STUFF

PLACE_NEAR=U1800.BD47:2.54MM

C2492

1

2

PLACE_NEAR=U1800.BF47:2.54MM

10%

6.3V

1UF

CERM

NO STUFF

402

C2494

1

2

CRITICAL

PLACE_NEAR=U1800.BF47:2.54MM

220UF

POLY-TANT

2.5V

20%

CASE-B2-SM1

C2493

1

2

CRITICAL

0603

10UH-0.12A-0.36OHM

L2490

1 2

CRITICAL

10UH-0.12A-0.36OHM

0603

L2491

1 2

MF-LF

402

1/16W

0

5%

R2490

1 2

402

1/16W MF-LF

5%

0

R2491

1 2

CRITICAL

10UH-0.45A

1210-HF

L2406

1 2

SYNC_DATE=08/06/2010

PCH DECOUPLING

SYNC_MASTER=K91_YUN

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

PP1V05_S0_PCH_VCCCLKDMI_F

PP5V_SUS

MIN_NECK_WIDTH=0.25MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM

PP1V05_S0_PCH_VCCCLKDMI_R

PPVCCIO_S0_PCH

PP1V05_S0_PCH_VCCADPLLA_R

MIN_NECK_WIDTH=0.2MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.05V

PP1V05_S0_PCH_VCCADPLLA_F

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PPVCCIO_S0_PCH

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLB_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V8_S0_PCH_VCCTX_LVDS_F

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.5MM

VOLTAGE=1.8V

PP1V8_S0_PCH

PP3V3_S0_PCH_VCC3_3_CLK_R MIN_NECK_WIDTH=0.075 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 MM

VOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_F MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.075 MM

PPVCCIO_S0_PCH

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

PP3V3_S0_PCH_VCCA_DAC_F

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.25MM

MIN_LINE_WIDTH=0.3MM

VOLTAGE=5V MAKE_BASE=TRUE

PP5V_SUS_PCH_V5REFSUS

PPVCCIO_S0_PCH

PP5V_S0_PCH_V5REF

PP3V3_SUS

PPVCCIO_S0_PCH

PP5V_SUS_PCH_V5REFSUS

PPVCCIO_S0_PCH

PP3V3_S0_PCH

PPVCCIO_S0_PCH

PP3V3_S0_PCH

PPVCCIO_S0_PCH

PP3V3_S5

PP1V8_S0_PCH

PP3V3_S0_PCH

PP5V_S0

PP3V3_S5

PP3V3_S0_PCH

PP1V05_S0_PCH_VCCADPLLB_R

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2MM

PP1V5_S0

PP3V3_SUS

PPVCCIO_S0_PCH

24 OF 132 22 OF 105

20

7

72

16 17 20 22 102 104

20

16 17 20 22

102 104

20

17 20 22 102

20

16 17 20 22

102 104

20 22

20

20 22

16 17 20 22

102 104

20 22

7

16 17 18 19 20 22 46 71 72

73

7

16 17 18 19 20 22 46 71 72

73

16 17 20 22

102 104

20 22

16 17 20 22

102 104

16 17 20 22

102 104

16 17 20 22

102 104

16 17 18 19 20 22

102

16 17 20 22

102 104

16 17 18 19 20 22

102

16 17 20 22

102 104

16 17 20 22

102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

17 20 22

102

16 17 18 19 20 22

102

16 17 18 19 20 22

102

16 17 18 19 20 22

102

6 7 8

41 47 52 54 65 68 69 70 73 87

104

105

6 7

17 19 20 22 23 24 25 29 46 48

56 71 72 73 83 86 91

100 102 104

16 17 18 19

20 22

102

16 17 18 19 20 22

102

7

16 20 25 32 41 57 71

7

16 17 18 19 20 22 46 71 72

73

16 17 20 22

102 104

IN

IN IN

IN

IN IN IN IN

IN IN IN

OUT

IN

OUT OUT

NC

IN

OUT

IN

BI IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT OUT

IN IN

NC

BI

IN

IN IN

BI IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

OBSDATA_D3

OBSDATA_C3

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

PCH MINI XDP

OBSDATA_C0

PROCESSOR MINI XDP

517S0774

HOOK3

OBSFN_A1

OBSDATA_A1

TDI

TCK0

OBSDATA_D2

DBR#/HOOK7

OBSFN_B0 OBSFN_D0

ITPCLK#/HOOK5

TMS XDP_PRESENT#

OBSFN_B1

SCL

RESET#/HOOK6

OBSDATA_A2

OBSDATA_B1

OBSDATA_B2 OBSDATA_B3

OBSDATA_D0

VCC_OBS_AB

OBSDATA_D1

OBSDATA_A0

OBSDATA_B2

OBSDATA_A1

OBSFN_A1

SCL

OBSDATA_B0

TDO

OBSFN_C1

VCC_OBS_CD

TCK1

TDO

PLACE TDO TERM NEAR

TERM NEAR PCH

HOOK2

OBSFN_D0

OBSDATA_C3

TDI

OBSDATA_B1

SDA

TRSTn

OBSFN_C0

OBSDATA_C2

OBSDATA_C1

OBSFN_C1

OBSDATA_C0

517S0774

TMS

OBSFN_A0

OBSDATA_D0

OBSFN_A0

OBSDATA_B3

DESIGN NOTE:

PLACEMENT NOTE:

SDA

HOOK1

OBSDATA_A3

OBSFN_D1

OBSFN_C0

SNB XDP CONN

TERM NEAR CPU

PLACE TCK/TDI/TMS/TRST*

PLACE TDO TERM NEAR

PLACEMENT NOTE:

ODT AVAILABLE ON JTAG

PLACEMENT NOTE: PLACE TCK/TDI/TMS/TRST*

TCK1

OBSFN_B1

OBSFN_B0

OBSDATA_A3

OBSDATA_A2

OBSDATA_A0

PCH XDP CONN

OBSDATA_D1

XDP_PRESENT#

DBR#/HOOK7

VCC_OBS_CD RESET#/HOOK6

ITPCLK/HOOK4

NOTE: XDP_DBRESET_L pulled-up to 3.3V on P. 28

ITPCLK/HOOK4

OBSFN_D1

TRSTn

OBSDATA_C2

OBSDATA_C1

TCK0

OBSDATA_B0

HOOK3

PWRGD/HOOK0

HOOK2

ITPCLK#/HOOK5

OBSDATA_D3

OBSDATA_D2

VCC_OBS_AB

HOOK1

PWRGD/HOOK0

PLACEMENT NOTE:

1K series R on PCH Support P. 28

9

92

10 25

10 92

9

10 92

9

PLACE_NEAR=U1000.B57:2.54mm

MF

1K

201

5%

1/20W

XDP

R2501

1 2

9

23 92

16 39

16 31

9

92

19 62

XDP

201

1/20W

MF

5%

0

PLACE_NEAR=U1800.V10:2.54mm

R2576

1 2

1/20W

201

MF

XDP

PLACE_NEAR=U1800.M1:2.54mm

0

5%

R2577

1 2

19

16 41

PLACE_NEAR=U1800.U2:2.54mm

201

5%

0

MF

1/20W

XDP

R2579

1 2

8

19 33 88

19

9

92

25

16 23

9

92

PLACE_NEAR=U1800.A14:2.54mm

1/20W

5%

MF

201

0

XDP

R2580

1 2

18

16 23

9

92

18 24

CRITICAL

F-ST-SM-HF

XDP_CONN

DF40C-60DS-0.4V

J2550

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40 41 42 43 44 45 46 47 48 49

5

50 51 52 53 54 55 56 57 58 59

6

60

7 8 9

PLACE_NEAR=U1800.J3:2.54mm

MF

201

5%

51

XDP

1/20W

R2556

1

2

6

16 23 26 28 30 32 41 48 62 89 95

6

16 23 26 28 30 32 41 48 62 89 95

10 23 25 92

0.1uF

16V

402

X5R

10%

XDP

C2580

1

2

16V

XDP

402

10%

X5R

0.1uF

C2581

1

2

19

5%

PLACE_NEAR=U4900.P17:2.54mm

0

MF

201

1/20W

XDP

R2502

1 2

17 23 45

PLACE_NEAR=U4900.P17:2.54mm

0

5%

MF

201

XDP

1/20W

R2585

1 2

17 23 45

330

201

1/20W

XDP

5%

MF

R2504

1 2

17 91

18

1/20W

PLACE_NEAR=J2550.39:2.54mm

5%

MF

201

1K

XDP

R2584

1 2

45 73 88 91

5%

0

MF

1/20W

201

XDP

PLACE_NEAR=U1800.A16:2.54mm

R2581

1 2

18

10 23 92

10 23 25 92

PLACE_NEAR=U1800.K12:2.54mm

1/20W

0

5%

XDP

MF

201

R2582

1 2

19

XDP

201

1/20W

MF

PLACE_NEAR=U1800.P8:2.54mm

5%

0

R2578

1 2

19 29

XDP

5%

MF

201

0

1/20W

PLACE_NEAR=U1800.K20:2.54mm

R2586

1 2

5%

0

XDP

MF

1/20W

PLACE_NEAR=U1800.C16:2.54mm

201

R2587

1 2

18

9

92

10 23 92

16 92

1/20W

201

MF

5%

0

PLACE_NEAR=R1841.1:2.54mm

XDP

R2515

1 2

PLACE_NEAR=R1840.1:2.54mm

XDP

0

201

5%

1/20W

MF

R2516

1 2

PLACE_NEAR=U1000.G3:2.54mm

XDP

1K

201

1/20W

MF

5%

R2505

1 2

16 85

PLACE_NEAR=J2550.52:2.54mm

201

5%

1/20W

MF

XDP

51

R2550

1

2

10 23 92

PLACE_NEAR=U1800.K5:2.54mm

201

51

5%

1/20W

MF

XDP

R2551

1

2

201

MF

1/20W

5%

51

XDP

PLACE_NEAR=U1800.H7:2.54mm

R2552

1

2

1/20W

XDP_CPU_BPM

5%

0

MF

201

R2560

1 2

5%

0

1/20W

201

MF

XDP_CPU_BPM

R2561

1 2

XDP_CPU_BPM

1/20W

5%

MF

201

0

R2562

1 2

XDP_CPU_BPM

201

5%

1/20W

0

MF

R2563

1 2

201

XDP_CPU_CFG

0

1/20W

MF

5%

R2564

1 2

10 23 92

XDP_CPU_CFG

0

1/20W

MF

201

5%

R2566

1 2

XDP_CPU_CFG

201

1/20W

5%

MF

0

R2567

1 2

XDP_CPU_CFG

0

201

MF

1/20W

5%

R2565

1 2

402

MF-LF

1/16W

5%

NOSTUFF

1K

R2540

1

2

9

23 92

0.1uF

16V

XDP

X5R 402

10%

C2501

1

2

9

92

10% 16V X5R

0.1uF

XDP

402

C2500

1

2

10 92

9

92

9

92

9

92

9

92

6

16 23 26 28 30 32 41 48 62 89

95

6

16 23 26 28 30 32 41 48 62 89 95

10 23 92

1K

1/20W

201

5%

MF

XDP

PLACE_NEAR=U1000.C60:2.54mm

R2500

1 2

9

92

10 19 92

9

92

F-ST-SM-HF

CRITICAL XDP_CONN

DF40C-60DS-0.4V

J2500

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40 41 42 43 44 45 46 47 48 49

5

50 51 52 53 54 55 56 57 58 59

6

60

7 8 9

51

5%

201

1/20W

MF

PLACE_NEAR=J2500.52:2.54mm

XDP

R2510

1

2

PLACE_NEAR=U1000.K61:2.54mm

5%

51

MF

1/20W

201

XDP

R2511

1

2

51

5%

MF

1/20W

201

PLACE_NEAR=U1000.H59:2.54mm

XDP

R2512

1

2

PLACE_NEAR=U1000.H63:2.54mm

51

5%

XDP

MF

1/20W

201

R2513

1

2

PLACE_NEAR=U1000.J58:2.54mm

XDP

5%

51

MF

1/20W

201

R2514

1

2

10 92

SYNC_DATE=10/17/2010

CPU & PCH XDP

SYNC_MASTER=K91_MLB

PP3V3_S0

XDP_CPU_PWRGD

XDP_OBSDATA_B<3>

XDP_OBSDATA_B<2>

XDP_OBSDATA_B<1>

CPU_CFG<13> CPU_CFG<14>

XDP_VR_READY

XDP_CPU_PREQ_L XDP_CPU_PRDY_L

XDP_BPM_L<0>

CPU_CFG<10>

XDP_BPM_L<1>

XDP_CPU_TDI

XDP_CPU_TCK

XDP_PCH_TDI

XDP_PCH_TCK

XDP_CPU_TMS

XDP_CPU_TRST_L

TP_XDP_PCH_OBSFN_B<0>

PCH_GPIO10_OC6_L

XDP_PCH_S5_PWRGD

TP_XDP_PCH_OBSFN_B<1>

XDP_PCH_ENET_PWR_EN

CPU_CFG<11>

XDP_BPM_L<3>

XDP_CPU_PWRBTN_L

PP1V05_S0

CPU_CFG<8>

CPU_CFG<6> CPU_CFG<7>

XDP_CPURST_L

XDP_OBSDATA_B<0>

TP_XDPPCH_HOOK2

XDP_CPU_TMS

CPU_CFG<0>

PM_PCH_SYS_PWROK

TP_XDPPCH_HOOK3

XDP_CPU_CFG<0>

XDP_BPM_L<4>

CPU_PWRGD

CPU_CFG<15>

TP_XDP_PCH_OBSFN_A<0>

PCH_GPIO43_OC4_L XDP_PCH_SDCONN_DET_L

XDP_PCH_PWRBTN_L

PCH_GPIO14_OC7_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

JTAG_ISP_TCK

XDP_BPM_L<2>

XDP_PCH_TDI

CPU_CFG<5>

CPU_CFG<2>

CPU_CFG<9>

XDP_CPU_CLK100M_N

CPU_CFG<4>

PLT_RST_CPU_BUF_L

XDP_CPU_CLK100M_P

XDP_PCH_TDO

PP1V05_SUS

XDP_BPM_L<5>

PP1V05_S0

XDP_CPU_TDOCPU_CFG<17>

AP_CLKREQ_L

ITPXDP_CLK100M_N

XDP_PCH_USB_HUB_SOFT_RST_L

SDCONN_STATE_RST_L

USB_HUB_SOFT_RESET_L

SDCONN_STATE_CHANGE

XDP_DBRESET_L

PM_PWRBTN_L

ENET_PWR_EN

XDP_PCH_TMS

ITPXDP_CLK100M_P

CPU_CFG<0>

CPU_CFG<16>

CPU_CFG<1>

CPU_CFG<12>

ALL_SYS_PWRGD

XDP_BPM_L<6>

XDP_PCH_ISOLATE_CPU_MEM_L

SMBUS_PCH_DATA

TP_XDP_PCH_OBSFN_A<1>

XDP_PCH_GPIO46

XDP_PCH_SDCONN_STATE_RST_L

ISOLATE_CPU_MEM_L

FW_CLKREQ_L

TP_XDP_PCH_TRST_L

XDP_DBRESET_L

XDPPCH_PLTRST_L

TP_XDP_PCH_HOOK5

XDP_PCH_AUD_IPHS_SWITCH_EN

XDP_PCH_TCK

PCH_GPIO36_SATA2GP

XDP_PCH_TDO

XDP_CPU_TDI

PCH_GPIO46

PM_PWRBTN_L

XDP_BPM_L<7>

SMBUS_PCH_CLK

XDP_CPU_TCK

XDP_CPU_TDO XDP_CPU_TRST_L

XDP_PCH_TMS

AUD_IPHS_SWITCH_EN

TP_XDP_PCH_OBSFN_D<1>

TP_XDP_PCH_OBSFN_D<0>

XDP_AP_CLKREQ_L

DP_AUXCH_ISOL

SATARDRVR_EN

PCH_GPIO49_SATA5GP

TP_XDP_PCH_HOOK4

PP3V3_S5

XDP_FW_CLKREQ_L

PCH_GPIO0

CPU_CFG<3>

25 OF 132 23 OF 105

6 7

12 25 26 28 32 35 36 39 40 41 46 48

49 50 51 52 54 57 61 62 72 73 80 83 84

85 88 89 91

100 102

92

10 23 92

16 23

10 23 92

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

92

16 23

7

71

7 9

10 12 13

14 23 35 39

45 68 70 73

102 104 105

10 23 92

16 23

6 7

17 19 20 22 24 25 29 46 48 56 71 72

73 83 86 91

100 102 104

G

D

S

G

D

S

USBDN2_DP/PRT_DIS_P2

USBDN3_DM/PRT_DOS_M3 USBDN3_DP/PRT_DIS_P3

PRTPWR1

HS_IND/CFG_SEL1

SCL/SMBCLK/CFG_SEL0

USBDN4_DP/PRT_DIS_P4

USBDN4_DM/PRT_DIS_M4

SDA/SMBDATA/NON_REM1

OCS4*

OCS3*

RBIAS

VBUS_DET

PRTPWR3

PRTPWR2

USBDN2_DM/PRT_DIS_M2

USBDN1_DP/PRT_DIS_P1

USBDN1_DM/PRT_DIS_M1

SUSP_IND/LOCAL_PWR/NON_REM0

XTAL2

XTAL1/CLKIN

RESET*

USBUP_DP

USBUP_DM

OCS2*

PRTPWR4

OCS1*

VDD33PLL

VDD33CR

VDD33

VDD18

VDD18PLL

THRML_PAD

TEST

(SYM-VER1)

VDDA33

BI

IN

BI BI

USBDN2_DP/PRT_DIS_P2

USBDN3_DM/PRT_DOS_M3 USBDN3_DP/PRT_DIS_P3

PRTPWR1

HS_IND/CFG_SEL1

SCL/SMBCLK/CFG_SEL0

USBDN4_DP/PRT_DIS_P4

USBDN4_DM/PRT_DIS_M4

SDA/SMBDATA/NON_REM1

OCS4*

OCS3*

RBIAS

VBUS_DET

PRTPWR3

PRTPWR2

USBDN2_DM/PRT_DIS_M2

USBDN1_DP/PRT_DIS_P1

USBDN1_DM/PRT_DIS_M1

SUSP_IND/LOCAL_PWR/NON_REM0

XTAL2

XTAL1/CLKIN

RESET*

USBUP_DP

USBUP_DM

OCS2*

PRTPWR4

OCS1*

VDD33PLL

VDD33CR

VDD33

VDD18

VDD18PLL

THRML_PAD

TEST

(SYM-VER1)

VDDA33

BI

BI BI

BI

IN

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

External A

Trackpad/Keyboard

SD Card/Express Card

IR Receiver

External C

External B

Bluetooth

IPU IPU

IPU

0 0 All ports are removable

1 1 Port 1, 2, and 3 are non removable

1 0 Port 1 and 2 are non removable

NON_REM1 NON_REM0 DESCRIPTION

0 1 Port 1 is non removable

BOM TABLE

T29 unused USB port, only has pull up

5%

402

MF-LF

1/16W

10K

R2641

1

2

SOT-363

2N7002DW-X-G

Q2640

3

5

4

402

5%

20K

1/16W MF-LF

R2640

1 2

SOT-363

2N7002DW-X-G

Q2640

6

2

1

5% 50V CERM 402

100PF

NOSTUFF

C2641

1

2

10%

6.3V 402

CERM-X5R

0.47UF

C2640

1

2

CRITICAL

5%

50V

CERM

402

18PF

C2619

1

2

402

5%

MF-LF

1/16W

1M

CRITICAL

R2630

1 2

CRITICAL

402

CERM

50V

5%

18PF

C2620

1

2

6.3V

20%

10UF

603

X5R

C2604

1

2

0.01UF

CERM

16V

10%

402

C2605

1

2

100PF

CERM

50V 402

5%

C2606

1

2

402

10% 16V CERM

0.01UF

C2600

1

2

FERR-120-OHM-1.5A

0402

L2601

1 2

603

X5R

6.3V

20%

10UF

C2607

1

2

5%

402

50V CERM

100PF

C2601

1

2

0402

1 2

L2600

FERR-120-OHM-1.5A

100PF

CERM

50V 402

5%

C2656

1

2

402

CRITICAL

5%

MF-LF

1/16W

1M

R2680

1 2

0.01UF

CERM

16V

10%

402

C2655

1

2

QFN

USX2061

OMIT

U2600

25

13 17 19 21

12 16 18 20

35

26

24

22

28

11

37

1 2

3 4

6 7

8 9

30 31

27

143423

15

36510

29

33 32

402

MF

12K

1/16W

1%

CRITICAL

R2600

1

2

43 94

42 94

18 94

42 94

44 94

8

94

44 94

8

94

0.1UF

X7R-CERM 402

10% 16V

C2615

1

2

1UF

X5R

16V

10%

402

C2616

1

2

MF-LF

1/16W

5%

402

10K

R2620

1

2

0.1UF

X7R-CERM

16V

10%

402

C2617

1

2

16V X5R

1UF

402

10%

C2618

1

2

0.1UF

402

10% 16V

X7R-CERM

C2608

1

2

6.3V X5R

20%

603

10UF

C2602

1

2

0.1UF

X7R-CERM

16V

10%

402

C2609

1

2

0.1UF

402

10% 16V

X7R-CERM

C2610

1

2

10% 16V

402

X7R-CERM

0.1UF

C2603

1

2

X7R-CERM 402

10% 16V

C2611

1

2

0.1UF 0.1UF

402

10%

C2612

1

2

X7R-CERM

16V

0.01UF

CERM

16V

10%

402

C2613

1

2

0.01UF

CERM

16V

10%

402

C2614

1

2

18 23

5% 1/16W MF-LF

402

100K

R2642

1

2

8

43

42

5%

MF-LF

1/16W

100

402

R2605

1 2

SOD-523

BAT54XV2T1

D2600

12

10K

MF-LF

1/16W 402

5%

R2606

1

2

10K

MF-LF

1/16W 402

5%

R2607

1

2

5%

402

HUB1_NONREM0_0

10K

1/16W MF-LF

R2604

1

2

HUB1_NONREM0_1

402

1/16W MF-LF

5%

10K

R2603

1

2

HUB1_NONREM1_1

1/16W MF-LF

402

10K

5%

R2601

1

2

HUB1_NONREM1_0

MF-LF

1/16W

10K

5%

402

R2602

1

2

16V

10% X5R

402

1

2

1UF

C2668

0.1UF

16V

10%

402

X7R-CERM

C2667

1

2

0.01UF

402

10% 16V CERM

C2664

1

2

X5R 402

10% 16V

1UF

C2666

1

2

X7R-CERM

10% 16V

402

0.1UF

C2665

1

2

0.01UF

10%

402

16V CERM

C2663

1

2

0.1UF

X7R-CERM

16V

10%

402

C2662

1

2

X7R-CERM

0.1UF

10% 16V

402

C2661

1

2

0.1UF

10%

402

16V

X7R-CERM

C2660

1

2

1/16W

10K

MF-LF 402

5%

R2670

1

2

12K

402

1% MF

CRITICAL

1/16W

R2650

1

2

18 94

QFN

OMIT

USX2061

U2650

25

13 17 19 21

12 16 18 20

35

26

24

22

28

11

37

1 2

3 4

6 7

8 9

30 31

27

143423

15

36510

29

33 32

10% 16V

0.1UF

402

X7R-CERM

C2653

1

2

20%

6.3V X5R 603

10UF

C2652

1

2

0.1UF

X7R-CERM

16V

10%

402

C2659

1

2

0.1UF

16V

10%

402

X7R-CERM

C2658

1

2

603

X5R

6.3V

20%

10UF

C2657

1

2

5%

1/16W

100

MF-LF

402

R2655

1 2

CRITICAL

402

18PF

CERM

50V

5%

C2670

1

2

5%

50V

CERM

18PF

402

CRITICAL

C2669

1

2

MF-LF

1/16W 402

10K

5%

R2657

1

2

402

10K

MF-LF

1/16W

5%

R2656

1

2

HUB2_NONREM0_1

5%

402

10K

1/16W MF-LF

R2653

1

2

HUB2_NONREM1_1

10K

1/16W MF-LF

402

5%

R2651

1

2

5%

402

10K

1/16W MF-LF

HUB2_NONREM0_0

R2654

1

2

MF-LF

1/16W

10K

402

5%

HUB2_NONREM1_0

R2652

1

2

FERR-120-OHM-1.5A

0402

L2650

1 2

402

50V CERM

100PF

5%

C2651

1

2

FERR-120-OHM-1.5A

0402

L2651

1 2

402

10% 16V CERM

0.01UF

C2650

1

2

10UF

6.3V 603

20% X5R

C2654

1

2

53 94

6

31 94

6

31 94

CRITICAL

SM-2

24.000MHZ-16PF

Y2600

2 4

1 3

24.000MHZ-16PF

CRITICAL

SM-2

Y2650

2 4

1 3

8

32

100 8

32

100

42 94

8

32

42

SYNC_DATE=06/29/2010

USB HUBS

SYNC_MASTER=K92_BEN

U2600,U2650

USBHUB_2514B

CRITICAL

SMSC USB2514B

2

338S0824

U2600,U2650

USBHUB_2514

CRITICAL

SMSC USB2514

2

338S0720

U2600,U2650

USBHUB_2061

CRITICAL

SMSC USX2061

2

338S0721

HUB2_3NONREM

HUB2_NONREM1_1,HUB2_NONREM0_1

HUB2_2NONREM

HUB2_NONREM1_1,HUB2_NONREM0_0

HUB2_ALLREM

HUB2_NONREM1_0,HUB2_NONREM0_0

HUB2_1NONREM

HUB2_NONREM1_0,HUB2_NONREM0_1

HUB1_NONREM1_1,HUB1_NONREM0_1

HUB1_3NONREM

HUB1_NONREM1_1,HUB1_NONREM0_0

HUB1_2NONREM

HUB1_NONREM1_0,HUB1_NONREM0_0

HUB1_ALLREM

HUB1_NONREM1_0,HUB1_NONREM0_1

HUB1_1NONREM

PP3V3_S3

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

PPUSB_HUB1_VDDPLL3V3

VOLTAGE=3.3V

USB_T29A_N

PP3V3_S3

USB_HUB_SOFT_RESET_L

PP3V3_S5

P3V3S3_EN_RC

PP3V3_S3

USB_HUB_RESET

USB_HUB_RESET_L

PP3V3_S3

USB_HUB2_RBIAS

USB_HUB2_VBUS_DET

USB_HUB_RESET_L

USB_IR_N

NC_USB_HUB1_PRTPWR3

USB_HUB1_TEST

USB_HUB1_CFG_SEL0

USB_EXTB_P

USB_EXTB_N

USB_IR_P

USB_HUB2_TEST

USB_TPAD_P

USB_HUB2_CFG_SEL1

USB_HUB2_CFG_SEL0

USB_HUB2_NONREM1

NC_USB_HUB2_PRTPWR3

NC_USB_HUB2_PRTPWR2

USB_TPAD_N

USB_BT_P

USB_HUB2_NONREM0

USB_HUB_RESET_L

USB_HUB2_UP_P

NC_USB_HUB2_OCS2

NC_USB_HUB2_PRTPWR4

PP3V3_S3

USB_HUB1_NONREM0 USB_HUB1_NONREM1

USB_HUB2_XTAL2

USB_HUB2_XTAL1

USB_HUB1_XTAL1

USB_EXTB_OC_L

USB_HUB1_CFG_SEL1

TP_USB_HUB2_OCS1

TP_USB_HUB2_PRTPWR1

USB_HUB1_UP_N

USB_EXTC_OC_L

TP_USB_HUB1_OCS1

NC_USB_HUB1_PRTPWR4

USB_EXTA_N USB_EXTA_P

USB_EXCARD_P

USB_EXCARD_N

USB_HUB2_UP_N

USB_EXTA_OC_L

NC_USB_HUB1_OCS2

NC_USB_HUB1_PRTPWR2

TP_USB_HUB1_PRTPWR1

USB_EXTC_P

USB_EXTC_N

EXCARD_OC_L

USB_HUB1_UP_P

USB_HUB1_XTAL2

USB_BT_N

PPUSB_HUB2_VDD1V8

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM

PPUSB_HUB1_VDD1V8PLL

MIN_NECK_WIDTH=0.11MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

PPUSB_HUB1_VDD1V8

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM

VOLTAGE=3.3V

PPUSB_HUB1_VDDA3V3

PPUSB_HUB2_VDDA3V3

MIN_LINE_WIDTH=0.4MM VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

PPUSB_HUB2_VDDPLL3V3

MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V

PPUSB_HUB2_VDD1V8PLL

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.11MM

USB_HUB1_VBUS_DET

USB_HUB1_RBIAS

USB_T29A_P

26 OF 132 24 OF 105

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31

32 48 49 50 54 55 73 88

104

6 7

17 19 20 22 23 25 29 46 48 56 71 72

73 83 86 91

100 102 104

6 7 8

18 24 25 29 30 31 32 48 49 50 54

55 73 88

104

6 7 8

18 24 25 29 30 31

32 48 49 50 54 55 73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

24

6 7 8

18 24 25 29 30

31 32 48 49 50 54 55 73

88

104

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

D

GS

OUT

IN

OUT

VBAT

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

PAD

NC NC

OUT

NC

OUT

D

SG

IN

D

SG

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PCH Reset Button

Ethernet WAKE# Isolation

VDDIO_25M_A: SB power rail for XTAL circuit. VDDIO_25M_B: Ethernet power rail for XTAL circuit. VDDIO_25M_C: T29 power rail for XTAL circuit.

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

to reduce VBAT draw.

No Coin-Cell: 3.3V S5

For SB RTC Power

APN:359S0178

VBAT and +V3.3A are

No bypass necessary

T29 XTAL Power

Buffered CPU reset

VTT voltage divider on CPU page

Series R is R4283

Platform Reset Connections

Unbuffered

Ethernet XTAL Power

GreenClk 25MHz Power

SB XTAL Power

+V3.3A should be first available ~3.3V power

create VDD_RTC_OUT.

Coin-Cell & G3Hot: 3.42V G3Hot

No Coin-Cell: 3.42V G3Hot (no RC)

Buffered

Series R is R3803

Note: Based on K91/K92 layout, ENET,AP and BKLT are moved to Buffered reset.

System RTC Power Source & 32kHz / 25MHz Clock Generator

internally ORed to

NOTE: 30 PPM crystal required

Coin-Cell & No G3Hot: 3.3V S5

Coin-Cell: VBAT (300-ohm & 10uF RC)

ENET_MEDIA_SENSE ISOLATION CIRCUIT

10 23 92

21

R2896

XDP

MF-LF

5%

0

402

1/16W

21

R2883

MF-LF

402

1/16W

33

5%

21

R2881

5%

402

MF-LF

33

1/16W

6

25 47 88 95

45

31

21

R2856

PLACE_NEAR=U1800.P53

1/20W

5% MF

201

22

21

R2855

1/20W

201

22

PLACE_NEAR=U1800.N52

5% MF

18 95

30

21

R2871

0

5%

402

1/16W MF-LF

6

47 95

45 95

18

88

21

R2857

PLACE_NEAR=U1800.P46

5%

201

1/20W

MF

22

23

21

R2889

XDP

1/16W

5%

402

1K

MF-LF

20%

2

1

C2880

10V

CERM

402

0.1UF

5

4

1

2

3

U2880

SC70-HF

MC74VHC1G08

CRITICAL

MF-LF

2

1

R2880

5% 1/16W

100K

402

32

16 95

21

R2859

PLACE_NEAR=U1800.P48

201

1/20W

MF

22

5%

18

18 25

25 88

21

R2887

5%

402

0

1/16W MF-LF

SILK_PART=SYS RESET

2

1

R2897

OMIT

MF-LF 402

5%

0

1/16W

6

25 47 88 95

90

R2895

4.7K

1/16W MF-LF

2

1

5%

402

6

17 45

18 25 29 39

2

3

Q2830

SSM3K15FV

SOD-VESM-HF

CRITICAL

1

6

17 31 32 85 25 36

2

1

R2830

1/16W

5%

10K

MF-LF 402

25 32 35

16

33

2

1

C2810

402

10% CERM

6.3V

1UF

2

1

C2802

1UF

X5R

10%

402-1

10V

0.1UF

2

1

C2820

20%

402

10V

CERM

2

1

C2822

10V

20%

0.1UF

402

CERM

CRITICAL

3 4

14

6

11

1

5

13

17216107

12

15

8

9

U2800

TQFN

SLG3NB148V

2

1

R2806

NO STUFF

MF-LF

5%

402

1M

1/16W

2

1

C2824

10V

20%

0.1UF

402

CERM

R2805

21

402

0

1/16W

5%

MF-LF

31

42

Y2805

CRITICAL

SM-3.2X2.5MM

25.000MHZ-12PF-30PPM

2 1

C2805

12PF

402

CERM

50V

5%

21

C2806

12PF

5%

50V

CERM

402

10 23 25

2

1

R2890

MF-LF

100K

1/16W

5%

402

4

5

1 3

2

U2890

SC70

74LVC1G07

CRITICAL

2

1

C2890

0.1UF

402

10V

20%

CERM

5%

2

1/16W

R2882

MF-LF

1

402

0

R2888

0

MF-LF

21

5%

402

1/16W

0

21

R2893

402

5%

MF-LF

21

R2800

201

1/20W

0

MF

5%

16

PLACE_NEAR=U1800.N32:5mm

MF

201

1

2

1/20W

5%

10K

R2819

R2810

21

402

1/16W

12K

5%

MF-LF

4

3

CRITICAL

SSM6N37FEAPE

5

SOT563

Q2810

R2811

201

1/20W

5%

MF

2

1

100K

36

SSM6N37FEAPE

6

1

2

SOT563

Q2810

0

5%

MF-LF

1/16W

402

2

1

R2812

Chipset Support

SYNC_MASTER=K91_MLB

SYNC_DATE=06/29/2010

ENET_MEDIA_SENSE_RDIV

SYSCLK_CLK25M_X1

LPC_CLK33M_LPCPLUS

ENET_MEDIA_SENSE

ENET_MEDIA_SENSE_EN_L

LPC_CLK33M_SMC

PP1V5_S0

PP3V3_S3

PCIE_WAKE_L

ENET_MEDIA_SENSE_EN

MAKE_BASE=TRUE

PLT_RST_BUF_L

AP_RESET_L

PLT_RST_BUF_L

LPC_CLK33M_SMC_R

MAKE_BASE=TRUE

ENET_WAKE_L

LPC_CLK33M_GMUX_R

MAKE_BASE=TRUE

LPCPLUS_RESET_L

PLT_RST_CPU_BUF_L

ENET_WAKE_L

SMC_LRESET_L

PP3V3_S0

PCH_CLK33M_PCIIN

XDP_DBRESET_L

LPC_CLK33M_GMUX

SYSCLK_CLK25M_X2

XDPPCH_PLTRST_L

PCA9557D_RESET_L

PP3V3_S0

PCH_CLK33M_PCIOUT

LPCPLUS_RESET_L

GMUX_RESET_L

BKLT_PLT_RST_L

PLT_RESET_L

LPC_CLK33M_GMUX_R

PPVRTC_G3H

SYSCLK_CLK25M_X2_R

SYSCLK_CLK25M_SB

SYSCLK_CLK25M_T29

PP3V3_T29

PP3V3_S5

PP3V42_G3H

PP1V8_S0

PP3V3_ENET

SYSCLK_CLK25M_ENET_R

SYSCLK_CLK25M_ENET

SYSCLK_CLK32K_RTC

PP3V3_ENET

MAKE_BASE=TRUE

GMUX_RESET_L

MAKE_BASE=TRUE

PLT_RST_CPU_BUF_L

PP3V3_S0

PM_SYSRST_L

PLT_RST_BUF_L

LPC_CLK33M_LPCPLUS_R

ENET_RESET_L_R

PLT_RESET_L

MAKE_BASE=TRUE

28 OF 132 25 OF 105

7

16 20 22

32 41 57 71

6 7 8

18 24 29 30 31 32 48 49 50 54 55

73 88

104

25 32

35

25 36

18 25

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

7

16 17 20

7

16 19 33 34 35 88

6 7

17 19 20 22 23 24 29 46 48 56 71 72

73 83 86 91

100 102 104

6 7

42 44 45 46 47 48 53 63 64 73

104

6 7

14 20 71 72 88

102

7

25 36 71 73

36

7

25 36 71 73

7

25 36 71 73

25 88

10 23

25

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

BI

IN

BI

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI

BI BI

BI

BI BI

BI

OUT

BI

IN

IN IN

BI BI

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

516-0229

(NONE)

SPD ADDR=0xA0(WR)/0xA1(RD)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

- =I2C_SODIMMA_SCL

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

- =PP0V75_S0_MEM_VTT_A

- =PP1V5_S3_MEM_A

- =PP1V5_S0_MEM_A

Power aliases required by this page:

Page Notes

Signal aliases required by this page:

"Factory" (top) slot

DDR3-SODIMM-DUAL-K6

F-RT-THB

J2900

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

27

0.1UF

10V

20%

402

CERM

C2931

1

2

2.2UF

20%

402-LF

CERM

6.3V

C2930

1

2

27

11 93

11 27 93

27

28 29

27

F-RT-THB

DDR3-SODIMM-DUAL-K6

CRITICAL

J2900

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

27

11 93

27

11 93

11 27 93

27

0.1UF

CERM 402

20% 10V

C2936

1

2

CERM

2.2UF

6.3V

20%

402-LF

C2935

1

2

27

28 45

6

16 23 28 30 32 41 48 62 89 95

6

16 23 28 30 32 41 48 62 89 95

11 93

27

MF-LF

1/16W

402

5%

10K

R2941

1

2

402

5% 1/16W MF-LF

10K

R2940

1

2

6.3V

402-LF

CERM

20%

2.2UF

C2940

1

2

PLACE_NEAR=J2900.75:2.54mm

20%

603

6.3V X5R

10UF

C2900

1

2

10UF

X5R

6.3V

PLACE_NEAR=J2900.75:2.54mm

20%

603

C2901

1

2

PLACE_NEAR=J2900.75:2.54mm

0.1UF

20% 10V

402

CERM

C2910

1

2

CERM

10V

20%

402

0.1UF

PLACE_NEAR=J2900.75:2.54mm

C2911

1

2

CERM

PLACE_NEAR=J2900.75:2.54mm

402

10V

20%

0.1UF

C2912

1

2

0.1UF

20% 10V CERM

PLACE_NEAR=J2900.75:2.54mm

402

C2913

1

2

0.1UF

20% CERM

402

10V

PLACE_NEAR=J2900.75:2.54mm

C2914

1

2

CERM 402

10V

20%

0.1UF

PLACE_NEAR=J2900.75:2.54mm

C2915

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2916

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2917

1

2

CERM 402

20% 10V

0.1UF

PLACE_NEAR=J2900.75:2.54mm

C2918

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2919

1

2

0.1UF

CERM 402

20% 10V

PLACE_NEAR=J2900.75:2.54mm

C2920

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2921

1

2

CERM 402

20%

0.1UF

10V

PLACE_NEAR=J2900.75:2.54mm

C2922

1

2

PLACE_NEAR=J2900.75:2.54mm

CERM 402

20%

0.1UF

10V

C2923

1

2

10% 10V

1UF

X5R 402

C2950

1

2

10% 10V

1UF

X5R 402

C2951

1

2

10% 10V

1UF

X5R 402

C2952

1

2

10% 10V

1UF

X5R 402

C2953

1

2

SYNC_MASTER=K92_YUN

SYNC_DATE=06/14/2010

DDR3 SO-DIMM Connector A

PP0V75_S0_DDRVTT

MEM_A_BA<1>

PP0V75_S3_MEM_VREFCA_A

=MEM_A_DQ<41>

=MEM_A_DQ<55>

=MEM_A_DQ<53>

=MEM_A_DQ<47>

PP0V75_S3_MEM_VREFDQ_A

=MEM_A_DQ<9>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_A<14>

MEM_A_A<6> MEM_A_A<4>

=MEM_A_DQS_N<5>

=MEM_A_DQ<21>

=MEM_A_DQ<22> =MEM_A_DQ<23>

=MEM_A_DQ<2> =MEM_A_DQ<3>

=MEM_A_DQ<1>

=MEM_A_DQ<0>

=MEM_A_DQS_N<1> =MEM_A_DQS_P<1>

=MEM_A_DQ<24>

=MEM_A_DQ<5>

MEM_A_DQS_N<0> =MEM_A_DQS_P<0>

=MEM_A_DQ<6> =MEM_A_DQ<7>

=MEM_A_DQ<12> =MEM_A_DQ<13>

=MEM_A_DQ<14> =MEM_A_DQ<15>

=MEM_A_DQ<20>

=MEM_A_DQ<28>

=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>

=MEM_A_DQ<30> =MEM_A_DQ<31>

=MEM_A_DQ<4>

=MEM_A_DQ<26>

=MEM_A_DQ<16>

MEM_A_CKE<1>

MEM_A_ODT<0>

=MEM_A_DQ<38> =MEM_A_DQ<39>

MEM_A_BA<2>

=MEM_A_DQ<40>

=MEM_A_DQS_P<5>

=MEM_A_DQ<54>

=MEM_A_DQ<61>

=MEM_A_DQ<60>

=MEM_A_DQS_P<7>

=MEM_A_DQS_N<7>

=MEM_A_DQ<63>

=MEM_A_DQ<62>

MEM_EVENT_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<57>

MEM_A_SA<0>

MEM_A_CLK_N<0>

=MEM_A_DQ<35>

=MEM_A_DQS_N<4>

MEM_A_SA<1>

=MEM_A_DQ<33>

MEM_A_CLK_P<0>

=MEM_A_DQS_P<4>

MEM_A_CKE<0>

MEM_A_CS_L<1>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_A<10>

MEM_A_A<1>

MEM_A_A<8>

MEM_A_CS_L<0>

MEM_A_A<2>

MEM_A_RAS_L

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_ODT<1>

=MEM_A_DQ<29>

=MEM_A_DQS_P<2>

=MEM_A_DQ<11>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<15>

=MEM_A_DQ<48> =MEM_A_DQ<49>

=MEM_A_DQ<50>

=MEM_A_DQ<32>

=MEM_A_DQ<56>

=MEM_A_DQ<51>

=MEM_A_DQ<34>

MEM_A_BA<0>

MEM_A_A<3>

MEM_A_A<5>

=MEM_A_DQ<43>

=MEM_A_DQ<42>

=MEM_A_DQ<36> MEM_A_DQ<37>

=MEM_A_DQ<44> =MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<52>

=MEM_A_DQ<59>

=MEM_A_DQ<58>

PP3V3_S0

=MEM_A_DQ<10>

=MEM_A_DQ<17>

=MEM_A_DQS_N<2>

=MEM_A_DQ<18> =MEM_A_DQ<19>

=MEM_A_DQ<25>

=MEM_A_DQ<27>

MEM_RESET_L

=MEM_A_DQ<8>

PP1V5_S3

29 OF 132 26 OF 105

7

28 29 67

30

9

30

6 7

12 23 25 28

32 35 36 39 40 41 46 48

49 50 51 52 54

57 61 62 72 73 80 83 84

85 88 89 91

100 102

7

28 29 67 72

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU CHANNEL A DQS 0 -> DIMM A DQS 0

CPU CHANNEL B DQS 6 -> DIMM B DQS 6

CPU CHANNEL A DQS 5 -> DIMM A DQS 5

CPU CHANNEL A DQS 6 -> DIMM A DQS 6

CPU CHANNEL A DQS 7 -> DIMM A DQS 7

CPU CHANNEL A DQS 4 -> DIMM A DQS 4

CPU CHANNEL B DQS 7 -> DIMM B DQS 7

CPU CHANNEL B DQS 0 -> DIMM B DQS 0

CPU CHANNEL B DQS 1 -> DIMM B DQS 1

CPU CHANNEL A DQS 2 -> DIMM A DQS 2

CPU CHANNEL A DQS 1 -> DIMM A DQS 1

CPU CHANNEL A DQS 3 -> DIMM A DQS 3

CPU CHANNEL B DQS 5 -> DIMM B DQS 5

CPU CHANNEL B DQS 4 -> DIMM B DQS 4

CPU CHANNEL B DQS 3 -> DIMM B DQS 3

CPU CHANNEL B DQS 2 -> DIMM B DQS 2

SYNC_DATE=05/14/2010

SYNC_MASTER=K92_YUN

DDR3 Byte/Bit Swaps

MAKE_BASE=TRUE

MEM_A_DQ<6>

MAKE_BASE=TRUE

MEM_A_DQ<5> MEM_A_DQ<4>

MAKE_BASE=TRUE

MEM_A_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<42>

MAKE_BASE=TRUE

MEM_B_DQ<47>MEM_A_DQ<47>

MAKE_BASE=TRUE

MEM_A_DQ<35>

MAKE_BASE=TRUE

MEM_A_DQ<24>

MEM_A_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQ<5>

MAKE_BASE=TRUE

MEM_B_DQ<13>

MEM_A_DQ<25>

MAKE_BASE=TRUE

MEM_A_DQ<31>

MAKE_BASE=TRUE

MEM_A_DQ<28>

MAKE_BASE=TRUE

MEM_A_DQ<34>

MAKE_BASE=TRUE

MEM_A_DQ<43>

MAKE_BASE=TRUE

MEM_A_DQ<45>

MAKE_BASE=TRUE

MEM_A_DQ<46>

MAKE_BASE=TRUE

MEM_A_DQS_N<6>

MAKE_BASE=TRUE

MEM_A_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQ<30>MEM_A_DQ<30>

MAKE_BASE=TRUE

MEM_A_DQ<53>

MAKE_BASE=TRUE

MEM_A_DQS_P<7>

MEM_A_DQ<62>

MAKE_BASE=TRUE

MEM_A_DQ<61>

MAKE_BASE=TRUE

MEM_A_DQ<60>

MAKE_BASE=TRUE

MEM_A_DQ<57>

MAKE_BASE=TRUE

MEM_A_DQ<56>

MAKE_BASE=TRUE

MEM_A_DQ<58>

MAKE_BASE=TRUE

MEM_A_DQ<59>

MAKE_BASE=TRUE

MEM_A_DQ<63>

MAKE_BASE=TRUE

MEM_A_DQ<48>

MEM_A_DQ<44>

MAKE_BASE=TRUE

MEM_A_DQ<42>

MAKE_BASE=TRUE

MEM_A_DQ<41>

MAKE_BASE=TRUE MAKE_BASE=TRUE

MEM_A_DQ<40>

MEM_A_DQS_P<6>

MAKE_BASE=TRUE

MEM_A_DQ<55>

MAKE_BASE=TRUE

MEM_A_DQ<52>

MAKE_BASE=TRUE

MEM_A_DQ<54>

MEM_A_DQ<50>

MAKE_BASE=TRUE

MEM_A_DQ<51>

MAKE_BASE=TRUE

MEM_A_DQ<49>

MEM_A_DQ<26>

MAKE_BASE=TRUE

MEM_A_DQ<27>

MAKE_BASE=TRUE

MEM_A_DQS_N<4>

MAKE_BASE=TRUE

MEM_A_DQS_P<4>

MAKE_BASE=TRUE

MEM_A_DQ<37>

MAKE_BASE=TRUE

MEM_A_DQ<38>

MAKE_BASE=TRUE

MEM_A_DQ<36>

MAKE_BASE=TRUE

MEM_A_DQ<32>

MAKE_BASE=TRUE

MEM_A_DQ<33>

MAKE_BASE=TRUE

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

MAKE_BASE=TRUE

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MAKE_BASE=TRUE

MEM_A_DQ<29>

MAKE_BASE=TRUE

MEM_A_DQ<11>

MAKE_BASE=TRUE

MEM_B_DQ<11> MEM_B_DQ<10>

MAKE_BASE=TRUE

MEM_B_DQ<18>

MAKE_BASE=TRUE

MEM_B_DQ<17>

MEM_B_DQ<31>

MAKE_BASE=TRUE

MEM_B_DQ<27>

MAKE_BASE=TRUE

MEM_B_DQ<25>

MAKE_BASE=TRUE

MEM_B_DQS_N<4>

MAKE_BASE=TRUE

MEM_B_DQ<39>

MAKE_BASE=TRUE

MEM_B_DQS_P<4>

MAKE_BASE=TRUE

MEM_B_DQ<37>

MAKE_BASE=TRUE

MEM_B_DQ<34>

MAKE_BASE=TRUE

MEM_B_DQ<35>

MAKE_BASE=TRUE

MEM_B_DQ<36>

MAKE_BASE=TRUE

MEM_B_DQ<32>

MAKE_BASE=TRUE

MEM_B_DQS_P<5>

MAKE_BASE=TRUE

MEM_B_DQ<40>

MEM_B_DQ<41>

MAKE_BASE=TRUE

MEM_B_DQS_N<6>

MAKE_BASE=TRUE

MEM_B_DQS_P<6>

MAKE_BASE=TRUE

MEM_B_DQ<52>

MAKE_BASE=TRUE

MEM_B_DQ<50>

MAKE_BASE=TRUE

MEM_B_DQ<49>

MAKE_BASE=TRUE

MEM_B_DQ<48>

MAKE_BASE=TRUE

MEM_B_DQS_P<7>

MAKE_BASE=TRUE

MEM_B_DQS_N<7>

MAKE_BASE=TRUE

MEM_B_DQ<62>

MAKE_BASE=TRUE

MEM_B_DQ<63>

MAKE_BASE=TRUE

MEM_B_DQ<60>

MAKE_BASE=TRUE

MEM_B_DQ<61>

MAKE_BASE=TRUE

MEM_B_DQ<59>

MAKE_BASE=TRUE

MEM_B_DQ<57>

MAKE_BASE=TRUE

MEM_B_DQ<58>

MAKE_BASE=TRUE

MEM_B_DQ<56>

MAKE_BASE=TRUE

MEM_B_DQ<6>

MAKE_BASE=TRUE

MEM_B_DQ<7>

MAKE_BASE=TRUE

MEM_B_DQS_P<1>

MEM_B_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<3>

MAKE_BASE=TRUE

MEM_B_DQ<4>

MAKE_BASE=TRUE

MEM_B_DQ<1>

MAKE_BASE=TRUE

MEM_B_DQ<20>

MAKE_BASE=TRUE

MEM_B_DQ<15>

MAKE_BASE=TRUE

MEM_B_DQ<9>

MAKE_BASE=TRUE

MEM_B_DQ<12>

MEM_B_DQ<8>

MAKE_BASE=TRUE

MEM_B_DQ<19>

MAKE_BASE=TRUE

MEM_B_DQS_P<3>

MAKE_BASE=TRUE

MEM_B_DQ<22>

MEM_B_DQS_N<0>

MAKE_BASE=TRUE

MEM_B_DQS_N<3>

MAKE_BASE=TRUE

MEM_B_DQS_N<5>

MAKE_BASE=TRUE

MEM_B_DQ<29>

MAKE_BASE=TRUE

MEM_B_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<12>

MAKE_BASE=TRUE

MEM_A_DQ<13>

MEM_A_DQ<14>

MAKE_BASE=TRUE

MEM_A_DQ<7>

MEM_A_DQ<0>

MAKE_BASE=TRUE

MEM_A_DQS_N<1>

MAKE_BASE=TRUE

MEM_A_DQS_P<1>

MAKE_BASE=TRUE

MEM_A_DQ<15>

MAKE_BASE=TRUE

MEM_A_DQ<10>

MAKE_BASE=TRUE

MEM_A_DQ<9>

MAKE_BASE=TRUE

MEM_A_DQ<8>

MAKE_BASE=TRUE

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MAKE_BASE=TRUE

MEM_A_DQ<19>

MAKE_BASE=TRUE

MEM_A_DQ<17> MEM_A_DQ<16>

MAKE_BASE=TRUE

MEM_A_DQ<18>

MEM_A_DQ<20>

MAKE_BASE=TRUE

MEM_A_DQ<23>

MAKE_BASE=TRUE

MEM_A_DQ<22>

MAKE_BASE=TRUE

MEM_A_DQ<21>

MAKE_BASE=TRUE

MEM_A_DQS_N<0>

MAKE_BASE=TRUE

MEM_A_DQ<1>

MAKE_BASE=TRUE

MEM_A_DQ<2>

MAKE_BASE=TRUE

MEM_B_DQ<51>

MAKE_BASE=TRUE

MEM_B_DQ<53>

MAKE_BASE=TRUE

MEM_B_DQ<54>

MAKE_BASE=TRUE

MEM_B_DQ<55>

MAKE_BASE=TRUE

MEM_B_DQ<43>

MEM_B_DQ<44>

MAKE_BASE=TRUE

MEM_B_DQ<45>

MAKE_BASE=TRUE

MEM_B_DQ<46>

MAKE_BASE=TRUE

MEM_B_DQ<33>

MAKE_BASE=TRUE

MEM_B_DQ<38>

MAKE_BASE=TRUE

MEM_B_DQ<24>

MAKE_BASE=TRUE

MEM_B_DQ<26>

MAKE_BASE=TRUE

MEM_B_DQ<28>

MAKE_BASE=TRUE

MEM_B_DQ<21>

MAKE_BASE=TRUE

MEM_B_DQ<23>

MAKE_BASE=TRUE

MEM_B_DQS_P<2>

MAKE_BASE=TRUE

MEM_B_DQS_N<2>

MAKE_BASE=TRUE

MEM_B_DQ<14>

MAKE_BASE=TRUE

MEM_B_DQS_N<1>

MAKE_BASE=TRUE

MEM_B_DQ<0>

MEM_B_DQS_P<0>

MAKE_BASE=TRUE

=MEM_A_DQ<42>

=MEM_A_DQS_N<3> =MEM_A_DQS_P<3>

=MEM_A_DQ<30> =MEM_A_DQ<29>

=MEM_A_DQ<27> =MEM_A_DQ<26> =MEM_A_DQ<25>

=MEM_A_DQ<28>

=MEM_A_DQ<31>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<20>

=MEM_A_DQ<23>

=MEM_A_DQ<1> =MEM_A_DQ<0>

=MEM_A_DQS_P<1>

=MEM_A_DQ<2>

=MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

=MEM_A_DQ<4>

=MEM_A_DQ<7> =MEM_A_DQ<6> =MEM_A_DQ<5>

=MEM_A_DQS_P<0>

=MEM_A_DQ<22> =MEM_A_DQ<21>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<12>

=MEM_A_DQ<13>

=MEM_A_DQ<15>

=MEM_B_DQ<25>

=MEM_B_DQ<33>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<19> =MEM_B_DQ<18>

=MEM_B_DQ<31>

=MEM_B_DQS_P<3>

=MEM_B_DQ<20>

=MEM_B_DQ<16>

=MEM_B_DQ<12>

=MEM_B_DQ<15>

=MEM_B_DQ<22>

=MEM_B_DQS_P<2>

MEM_B_DQS_N<0>

=MEM_B_DQ<7> =MEM_B_DQ<6>

=MEM_B_DQ<4>

=MEM_B_DQ<29>

=MEM_B_DQ<27>

=MEM_B_DQ<9>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

=MEM_B_DQ<59>

=MEM_B_DQ<61> =MEM_B_DQ<60>

=MEM_B_DQ<63> =MEM_B_DQ<62>

=MEM_B_DQS_N<7> =MEM_B_DQS_P<7>

=MEM_B_DQ<49>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<52>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQS_P<6>

=MEM_B_DQS_N<6>

=MEM_B_DQ<41>

=MEM_B_DQ<47>

=MEM_B_DQS_P<5>

=MEM_B_DQS_N<5>

=MEM_B_DQ<32>

=MEM_B_DQ<36>

MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQS_P<4>

=MEM_B_DQ<39>

=MEM_B_DQS_N<4>

=MEM_B_DQ<24>

=MEM_B_DQ<28>

=MEM_B_DQ<30>

=MEM_B_DQS_N<3>

=MEM_B_DQ<17>

=MEM_B_DQ<21>

=MEM_B_DQ<23>

=MEM_B_DQS_N<2>

=MEM_B_DQ<8>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQS_P<1>

=MEM_B_DQS_N<1>

=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<5>

MEM_B_DQS_P<0>

=MEM_A_DQ<14>

=MEM_A_DQS_P<6>

=MEM_A_DQS_N<6>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<45>

=MEM_A_DQ<47>

=MEM_A_DQ<32>

=MEM_A_DQ<34>

=MEM_A_DQS_N<2> =MEM_A_DQS_P<2>

=MEM_A_DQ<56>

=MEM_A_DQ<59> =MEM_A_DQ<58> =MEM_A_DQ<57>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQ<63> =MEM_A_DQ<62>

=MEM_A_DQ<48>

=MEM_A_DQS_N<7> =MEM_A_DQS_P<7>

=MEM_A_DQ<49>

=MEM_A_DQ<51> =MEM_A_DQ<50>

=MEM_A_DQ<54> =MEM_A_DQ<53> =MEM_A_DQ<52>

=MEM_A_DQ<55>

=MEM_A_DQ<43>

=MEM_A_DQ<44>

=MEM_A_DQ<46>

=MEM_A_DQS_P<5>

=MEM_A_DQS_N<5>

=MEM_A_DQ<33>

=MEM_A_DQ<35>

=MEM_A_DQ<36>

=MEM_A_DQ<38> MEM_A_DQ<37>

=MEM_A_DQS_P<4>

=MEM_A_DQ<39>

=MEM_A_DQS_N<4>

=MEM_A_DQ<24>

=MEM_B_DQ<26>

=MEM_B_DQ<48>

=MEM_B_DQ<53>

=MEM_B_DQ<58>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<44>

=MEM_B_DQ<45>

=MEM_B_DQ<40>

=MEM_B_DQ<46>

=MEM_A_DQ<3>

MEM_A_DQS_P<0>

30 OF 132 27 OF 105

11 93

11 93 11 93

11 93

11 93 11 93

11 93

11 26 27 93

11 93

11 93 11 93

11 93

11 27 28 93

11 93

11 27 28 93

11 93

11 26 27 93

11 93

11 27 28 93

26

11 26 27 93

26

28

11 27 28 93

28

11 27 28 93

28

11 27 28 93

26

11 26 27 93

26

28

26

11 93

IN

BI

BI BI

OUT

BI IN

IN

IN IN

IN

IN IN

BI BI

BI

BI BI

NC

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

BI

IN

BI

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

BI

BI BI

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PP0V75_S0_MEM_VTT_B

- =I2C_SODIMMB_SDA

BOM options provided by this page:

DDR3 DECOUPLING AND GND RETURN CAPS (SPACE EVENLY AT CONNECTOR)

Power aliases required by this page:

- =I2C_SODIMMB_SCL

(NONE)

Signal aliases required by this page:

"Expansion" (bottom) slot

- =PP1V5_S3_MEM_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

516S0806

SPD ADDR=0xA4(WR)/0xA5(RD)

- =PP1V5_S0_MEM_B

Page Notes

11 93

27

26 45

6

16 23 26 30 32 41 48 62 89 95

6

16 23 26 30 32 41 48 62 89 95

0.1UF

402

20% 10V CERM

C3131

1

2

11 93

27

2.2UF

20%

6.3V

402-LF

CERM

C3130

1

2

1/16W

10K

402

MF-LF

5%

R3141

1

2

10K

5%

402

1/16W MF-LF

R3140

1

2

20%

CERM 402-LF

6.3V

2.2UF

C3140

1

2

10UF

20% X5R

6.3V 603

PLACE_NEAR=J3100.75:2.54mm

C3100

1

2

6.3V

10UF

X5R 603

20%

PLACE_NEAR=J3100.75:2.54mm

C3101

1

2

PLACE_NEAR=J3100.75:2.54mm

CERM 402

10V

20%

0.1UF

C3110

1

2

PLACE_NEAR=J3100.75:2.54mm

0.1UF

402

CERM

10V

20%

C3111

1

2

CERM

0.1UF

20% 10V

402

PLACE_NEAR=J3100.75:2.54mm

C3112

1

2

CERM 402

0.1UF

10V

20%

PLACE_NEAR=J3100.75:2.54mm

C3113

1

2

27

0.1UF

10V 402

CERM

20%

PLACE_NEAR=J3100.75:2.54mm

C3114

1

2

10V CERM

0.1UF

20%

402

PLACE_NEAR=J3100.75:2.54mm

C3115

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3116

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3117

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3118

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3119

1

2

10V

20%

402

CERM

0.1UF

PLACE_NEAR=J3100.75:2.54mm

C3120

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3121

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3122

1

2

10V

0.1UF

20%

402

CERM

PLACE_NEAR=J3100.75:2.54mm

C3123

1

2

27

1UF

402

X5R

10V

10%

C3153

1

2

1UF

402

X5R

10V

10%

C3152

1

2

11 93

402

X5R

1UF

10V

10%

C3151

1

2

402

X5R

1UF

10V

10%

C3150

1

2

DDR3-SODIMM

F-RT-BGA6

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206 207 208 209 210 211 212

203 204

113

11 27 93

27

26 29

27

CRITICAL

DDR3-SODIMM

F-RT-BGA6

J3100

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

27

11 93

27

11 93

27

11 93

27

11 27 93

27

20%

0.1UF

10V

402

CERM

C3136

1

2

402-LF

20%

CERM

6.3V

2.2UF

C3135

1

2

27

SYNC_MASTER=K92_YUN

SYNC_DATE=06/14/2010

DDR3 SO-DIMM Connector B

=MEM_B_DQ<54>

=MEM_B_DQ<33>

=MEM_B_DQ<42>

=MEM_B_DQ<48> =MEM_B_DQ<49>

=MEM_B_DQS_N<6> =MEM_B_DQS_P<6>

MEM_B_A<3>

MEM_B_CLK_P<0> MEM_B_CLK_N<0>

MEM_B_A<10> MEM_B_BA<0>

MEM_B_CAS_L

MEM_B_CS_L<1>

MEM_B_ODT<1>

MEM_B_CLK_P<1>

MEM_B_RAS_L

MEM_B_ODT<0>

=MEM_B_DQ<59>

=MEM_B_DQ<13>

MEM_B_A<1>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<12>

=MEM_B_DQ<41>

=MEM_B_DQS_N<4>

MEM_B_CKE<1>

MEM_B_A<15> MEM_B_A<14>

MEM_B_A<11> MEM_B_A<7>

MEM_B_A<2> MEM_B_A<0>

MEM_B_CLK_N<1>

MEM_B_BA<1>

MEM_B_CS_L<0>

PP0V75_S3_MEM_VREFCA_B

=MEM_B_DQ<36> MEM_B_DQ<37>

=MEM_B_DQ<38> =MEM_B_DQ<39>

=MEM_B_DQ<45>

=MEM_B_DQ<44>

=MEM_B_DQS_N<5>

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_B_A<13>

=MEM_B_DQ<32>

=MEM_B_DQ<40>

=MEM_B_DQ<46>

=MEM_B_DQS_P<5>

=MEM_B_DQ<47>

=MEM_B_DQ<52> =MEM_B_DQ<53>

=MEM_B_DQ<55>

=MEM_B_DQ<63>

MEM_EVENT_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

=MEM_B_DQ<51>

=MEM_B_DQ<35>

=MEM_B_DQ<56> =MEM_B_DQ<57>

MEM_B_SA<1>

=MEM_B_DQ<58>

=MEM_B_DQ<2> =MEM_B_DQ<3>

PP0V75_S3_MEM_VREFDQ_B

=MEM_B_DQ<1>

=MEM_B_DQ<0>

=MEM_B_DQ<9>

=MEM_B_DQ<8>

=MEM_B_DQS_N<1> =MEM_B_DQS_P<1>

=MEM_B_DQ<10> =MEM_B_DQ<11>

=MEM_B_DQ<17>

=MEM_B_DQS_N<2> =MEM_B_DQS_P<2>

=MEM_B_DQ<18> =MEM_B_DQ<19>

=MEM_B_DQ<25>

=MEM_B_DQ<24>

=MEM_B_DQ<5>

MEM_B_DQS_N<0>

=MEM_B_DQ<6> =MEM_B_DQ<7>

=MEM_B_DQ<12>

MEM_RESET_L

=MEM_B_DQ<14> =MEM_B_DQ<15>

=MEM_B_DQ<20> =MEM_B_DQ<21>

=MEM_B_DQ<22> =MEM_B_DQ<23>

=MEM_B_DQ<28> =MEM_B_DQ<29>

=MEM_B_DQS_N<3> =MEM_B_DQS_P<3>

=MEM_B_DQ<30> =MEM_B_DQ<31>

=MEM_B_DQ<4>

=MEM_B_DQ<27>

=MEM_B_DQ<26>

=MEM_B_DQ<16>

=MEM_B_DQ<50>

=MEM_B_DQ<62>

=MEM_B_DQ<34>

=MEM_B_DQS_P<4>

PP3V3_S0

MEM_B_A<4>

PP1V5_S3

MEM_B_A<6>

=MEM_B_DQ<43>

MEM_B_SA<0>

=MEM_B_DQS_P<7>

=MEM_B_DQS_N<7>

=MEM_B_DQ<61>

=MEM_B_DQ<60>

MEM_B_DQS_P<0>

PP0V75_S0_DDRVTT

MEM_B_WE_L

31 OF 132 28 OF 105

30

9

30

6 7

12 23 25 26 32

35 36 39 40 41 46 48 49 50

51 52 54 57 61 62

72 73 80 83 84 85 88 89 91

100 102

7

26 29 67 72

7

26 29 67

IN IN

IN

OUT

D

SG

D

S G

D

SG

D

S G

D

SG

D

S G

D

S G

D

SG

OUT

IN

D

SG

D

SG

IN

G

D

S

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

60mW max power

S0 to S3 to S0

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

5 0 1 1 1 0 (*) 1 1 1 6 0 1 1 1 1 1 1 1 7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

75mA max load @ 0.75V

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

MEMVTT Clamp

1V5 S0 "PGOOD" for CPU

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

Ensures CKE signals are held low in S3

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

4 0 0 1 1 X 1 0 1

3 0 0 0 1 X 1 0 0

2 0 0 1 1 1 1 0 1

1 0 1 1 1 1 1 1 1

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

19 23

6

17 45 73

18 25 39

1/16W

5%

MF-LF

CPUMEM_S0

402

R3202

1

2

100K

8

29 67

CPUMEM_S0

MF-LF

10K

1/16W

5%

402

R3210

1

2

CPUMEM_S0

100K

MF-LF

402

5%

1/16W

R3215

1

2

26 28

20K

MF-LF 402

1/16W

1

2

R3216

CPUMEM_S0

5%

CPUMEM_S0

SOT563

SSM6N15FEAPE

Q3200

3

5

4

CPUMEM_S0

SSM6N15FEAPE

SOT563

Q3205

3

5

4

CRITICAL

SSM6N15FEAPE

SOT563

CPUMEM_S0

Q3210

6

2

1

SSM6N15FEAPE

CPUMEM_S0

Q3210

3

5

4

SOT563

CPUMEM_S0

SSM6N15FEAPE

CRITICAL

SOT563

Q3200

6

2

1

CPUMEM_S0

SOT563

Q3215

6

2

SSM6N15FEAPE

1

SOT563

3

5

4

CRITICAL

SSM6N15FEAPE

Q3215

CPUMEM_S0

CRITICAL

SOT563

SSM6N15FEAPE

CPUMEM_S0

Q3205

6

2

1

72

CPUMEM_S0

10K

1/16W

5%

402

MF-LF

R3205

1

2

17 42 45 66 73

402

100K

5%

MF-LF

CPUMEM_S0

1/16W

R3201

1

2

8

29 67

SSM6N15FEAPE

SOT563

CPUMEM_S0

Q3250

3

5

4

1/16W MF-LF

5%

100K

402

CPUMEM_S0

R3251

1

2

1

C3251

CERM

20%

0.001UF

50V

NO STUFF

402

CRITICAL

SSM6N15FEAPE

SOT563

CPUMEM_S0

Q3250

6

2

1

MF-LF

10

5%

603

1/10W

CPUMEM_S0

R3250

1

2

MF-LF

1/16W

5%

402

1 2

0

R3217

CPUMEM_S3

10 29

MF-LF

1%

402

1/16W

R3221

1

2

33.2K

402

27.4K

1% 1/16W MF-LF

R3220

1

2

CRITICAL

SOT-563

DMB53D0UV

Q3220

5

3

4

MF-LF

1/16W

5%

10K

402

R3222

1

2

SOT-563

CRITICAL

DMB53D0UV

Q3220

6

2

1

10 17 92

CERM

NO STUFF

402

50V

20%

0.001UF

C3220

1

2

16V X5R

10%

0.1UF

CPUMEM_S0

C3216

402

1

2

SYNC_MASTER=K17_MLB

SYNC_DATE=04/26/2010

CPU Memory S3 Support

MEMRESET_ISOL_LS5V_L

PP1V5_S3

MEM_RESET_L

MAKE_BASE=TRUE

CPU_MEM_RESET_L

PLT_RESET_L

PP3V3_S3

P1V5_S0_DIV

PM_MEM_PWRGD

PM_MEM_PWRGD_L

PP3V3_S5

PP1V5_S3RS0_CPUDDR

PM_SLP_S4_L

PP5V_S3

MEMVTT_EN_L

MEMVTT_EN

PP5V_S3

VTTCLAMP_EN

VTTCLAMP_L

PP0V75_S0_DDRVTT

P1V5CPU_EN_L

P1V5CPU_EN

PM_SLP_S3_L

CPU_MEM_RESET_L

MEMVTT_EN

ISOLATE_CPU_MEM_L

32 OF 132 29 OF 105

7

26 28 67 72

10

29

6 7 8

18 24 25 30 31 32 48 49 50 54 55

73 88

104

6 7

17 19 20 22 23 24 25 46 48 56 71 72

73 83 86 91

100 102 104

7

10 13 15 73

104

6 7

29 31 42 43 44 46 67 72 82

104

6 7

29 31 42 43 44 46 67 72 82

104

7

26 28 67

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

IN

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Addr=0x98(WR)/0x99(RD)

8.59mV / step @ output

MEM B VREF CA

1.5V (DAC: 0x3A)

0.000V - 3.000V (0x00 - 0x74)

GPU Frame Buffer (1.8V, 70% VRef)

Page Notes

C

MEM A VREF CA

+61uA - -61uA (- = sourced)

MEM VREG

MEM B VREF DQ

0.75V (DAC: 0x3A)

0.000V - 1.501V (0x00 - 0x74) +3.4mA - -3.4mA (- = sourced)

0.300V - 1.200V (+/- 450mV)

Addr=0x30(WR)/0x31(RD)

RST* on ’platform reset’ so that system

NOTE: Margining will be disabled across all soft-resets and sleep/wake cycles.

1.51mV / step @ output

0.000V - 3.300V (0x00 - 0xFF)

6

D

NOTE: Must not enable more than two SO-DIMM margining buffers at once or VRef source may be overloaded.

5

D

DAC Channel: PCA9557D Pin:

DAC range:

Nominal value

DAC step size:

VRef current:

Margined target:

MEM A VREF DQ

B 21

A

7.69mV / step @ output

C 3 4

- =PP3V3_S3_VREFMRGN

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SDA

Circuitry.

- =PPVTT_S3_DDR_BUF

Power aliases required by this page:

VREFMRGN - Stuffs VREF Margining

VREFMRGN_NOT - Bypasses VREF Margining

Signal aliases required by this page:

10mA max load

BOM options provided by this page:

- =I2C_PCA9557D_SCL

+6.0mA - -5.0mA (- = sourced)

1.056V - 1.442V (+/- 180mV)

(OD)

1.267V (DAC: 0x8B)

both at the same time!

a DAC output, cannot enable

NOTE: MEMVREG and FRAMEBUF share

1.000V - 2.000V (+/- 500mV)

Required zero ohm resistors when no VREF margining circuit stuffed

watchdog will disable margining.

67

10V

20% 402

CERM

0.1UF

VREFMRGN

C3302

1

2

33.2K

MF-LF

VREFMRGN

PLACE_NEAR=R7320.2:1mm

1/16W

1%

402

R3314

1 2

5% 1/16W

VREFMRGN

100K

MF-LF 402

R3313

1

2

VREFMRGN

402

MF-LF

1/16W

5%

100K

R3315

1

2

UCSP

MAX4253

VREFMRGN

U3302

C3

C2

C1

C4

B1

B4

VREFMRGN

UCSP

MAX4253

U3303

A3

A2

A1

A4

B1

B4

CRITICAL

VREFMRGN

UCSP

MAX4253

U3302

A3

A2

A1

A4

B1

B4

CRITICAL VREFMRGN MAX4253

UCSP

U3303

C3

C2

C1

C4

B1

B4

MAX4253

VREFMRGN

UCSP

U3304

A3

A2

A1

A4

B1

B4

CRITICAL

MAX4253

VREFMRGN

UCSP

U3304

C3

C2

C1

C4

B1

B4

200

VREFMRGN

MF-LF

402

1%

1/16W

PLACE_NEAR=J2900.126:2.54mm

R3309

1 2

VREFMRGN

1/16W

1%

402

MF-LF

200

PLACE_NEAR=J3100.126:2.54mm

R3311

1 2

OMIT

NONE

402

NONE

SHORT

R3318

1 2

NONE

OMIT

SHORT

NONE

402

NONE

R3319

1 2

25

PLACE_NEAR=J2900.1:2.54mm

VREFMRGN

1/16W

1%

402

MF-LF

200

R3303

1 2

1/16W

VREFMRGN

MF-LF

402

1%

PLACE_NEAR=R3303.2:1mm

133

R3304

1 2

PLACE_NEAR=J3100.1:2.54mm

1/16W

1%

402

MF-LF

200

VREFMRGN

R3305

1 2

402

MF-LF

1%

1/16W

VREFMRGN

PLACE_NEAR=R3305.2:1mm

133

R3306

1 2

VREFMRGN

0

5% 1/16W MF-LF 402

R3317

1

2

VREFMRGN

0

5%

1/16W

402

MF-LF

R3316

1

2

402

1/16W

100K

5%

VREFMRGN

MF-LF

R3302

1

2

1/16W

VREFMRGN

402

100K

5% MF-LF

R3301

1

2

1/16W

1%

402

MF-LF

VREFMRGN

PLACE_NEAR=R3309.2:1mm

133

R3310

1 2

100K

MF-LF

5%

402

VREFMRGN

1/16W

R3307

1

2

CRITICAL VREFMRGN

QFN

PCA9557

U3301

3 4 5

8

6 7 9 10 11 12 13 14

15

1 2

17

16

VREFMRGN

402

0.1UF

10V

CERM

20%

C3304

1

2

402

1/16W

VREFMRGN

1%

133

MF-LF

PLACE_NEAR=R3311.2:1mm

R3312

1 2

VREFMRGN

100K

MF-LF 402

5% 1/16W

R3308

1

2

6

16 23 26 28 30 32 41 48 62 89 95

6

16 23 26 28 30 32 41 48 62 89 95

VREFMRGN

MSOP

CRITICAL

DAC5574

U3300

9

10

3

6

7

8

1

2

4

5

6

16 23 26 28 30 32 41 48 62 89 95

6

16 23 26 28 30 32 41 48 62 89 95

VREFMRGN

0.1UF

CERM 402

20% 10V

C3301

1

2

VREFMRGN

2.2UF

CERM

402-LF

20%

6.3V

C3300

1

2

VREFMRGN

0.1UF

20% 10V

CERM

402

C3305

1

2

0.1UF

10V

20%

CERM

402

VREFMRGN

C3303

1

2

VREFMRGN_NOT

2

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

R3309,R3311

VREFMRGN_NOT

2

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

R3303,R3305

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=K91_YUN

SYNC_DATE=08/26/2010

VREFMRGN_MEMVREG_EN

VREFMRGN_FRAMEBUF_BUF_R

VREFMRGN_FRAMEBUF_BUF

PPVTTDDR_S3

PCA9557D_RESET_L

VREFMRGN_DQ_SODIMMB_BUF

VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_DAC

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

DDRREG_FB

VREFMRGN_SODIMMB_DQ

SMBUS_PCH_DATA

SMBUS_PCH_CLK

PP0V75_S3_MEM_VREFDQ_A

VOLTAGE=0.75V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 mm VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

VREFMRGN_DQ_SODIMMA_BUF

SMBUS_PCH_DATA

VREFMRGN_DQ_SODIMMA_EN

MIN_LINE_WIDTH=0.3 mm

PP3V3_S3_VREFMRGN_CTRL

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

VREFMRGN_MEMVREG_FBVREF_R

VREFMRGN_FRAMEBUF_EN

VREFMRGN_MEMVREG_BUF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

PP3V3_S3

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_SODIMMS_CA

VREFMRGN_SODIMMA_DQ

VREFMRGN_CA_SODIMMB_BUF

33 OF 132 30 OF 105

6 7

67

9

26

9

28

26

28

6 7 8

18 24 25 29 31 32 48 49 50

54 55 73 88

104

BI

IN

BI

SYM_VER-1

IN

S

G

D

IN

BI

SYM_VER-1

OUT

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

OUT

BI

IN

OUT OUT

IN

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

3V S3 WLAN FET

TPCP8102

P-TYPE

MOSFET

Supervisor & CLKFREG # Isolation

BLUETOOTH

1A PEAK

AIRPORT

1 A (EDP)

516S0582

518S0816

206 mA nominal max

Delay = 60 ms +/- 20%

ALS CAMERA

275 mA peak

155S0367

LOADING

20-30 MOHM @2.5V

107S0137

CHANNEL

RDS(ON)

PLACE_NEAR=J3402.6:2.54MM

FERR-120-OHM-1.5A

0402-LF

L3408

12

0.1uF

402

10V

20% CERM

C3452

1

2

18

6

45 48 54 55 98

6

45 48 54 55 98

PLACE_NEAR=J3402.3:2.54MM

CRITICAL

90-OHM DLP0NS

L3407

1 2

34

73

MF-LF

5%

10K

1/16W

402

R3451

1

2

MF-LF

1/16W

33K

5%

402

R3450

1 2

0.033UF

16V X5R 402

10%

C3451

1

2

23V1K-SM

TPCP8102

CRITICAL

Q3450

5 6 7 8

4

1 2 3

X5R

10%

402-1

16V

0.1UF

C3450

1 2

FERR-120-OHM-3A

0603

L3404

1 2

20%

0.1uF

10V 402

PLACE_NEAR=J3401.29:2.54MM

CERM

C3421

1

2

PLACE_NEAR=J3401.29:2.54MM

CERM

10V

20%

402

0.1uF

C3422

1

2

16 95

6

24 94

6

24 94

PLACE_NEAR=J3401.15:2.54mm

10% 16V X5R

402-1

0.1UF

C3431

1 2

10% 16V

0.1UF

402-1

PLACE_NEAR=J3401.17:2.54mm

X5R

C3430

1 2

DLP11S

PLACE_NEAR=J3401.11:2.54mm

CRITICAL

90-OHM-100MA

L3401

1 2

34

PLACE_NEAR=J3401.27:2.54MM

FERR-120-OHM-1.5A

0402-LF

L3406

12

6

17 25 32 85

CRITICAL

F-ST-SM

500913-0302

J3401

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

10% 16V

0.01UF

CERM 402

C3432

1

2

F-RT-SM

CCR20-6K710S

CRITICAL

J3402

7

8

1

2

3

4

5

6

TDFN

SLG4AP016V

CRITICAL

U3440

6

5

7

3

8

4

2

9

1

25

18 73

16 23

CERM

20% 10V

402

0.1uF

C3440

1

2

232K

MF-LF 402

1/16W

1%

R3454

1

2

402

MF-LF

1/16W

1%

100K

R3455

1

2

100K

1%

402

MF-LF

1/16W

R3453

1

2

6

45 48 51 80 98

6

45 48 51 80 98

100 103

6

45 46

1%

0612

1W MF

0.005

CRITICAL

R3452

12 34

NOSTUFF

10%

0.1UF

16V X5R-CERM 0201

C3470

1

2

0201

0.6NH+/-0.1NH-0.85A

OMIT_TABLE

L3470

1 2

0201

X5R-CERM

16V

NOSTUFF

10%

0.1UF

C3471

1

2

NOSTUFF

0201

10% X5R-CERM

0.1UF

16V

C3473

1

2

0.6NH+/-0.1NH-0.85A

0201

OMIT_TABLE

L3471

1 2

NOSTUFF

0.1UF

16V

10% X5R-CERM

0201

C3472

1

2

NOSTUFF

0201

0.1UF

16V

10% X5R-CERM

C3475

1

2

0201

OMIT_TABLE

0.6NH+/-0.1NH-0.85A

L3473

1 2

NOSTUFF

16V

0.1UF

10%

0201

X5R-CERM

C3474

1

2

NOSTUFF

16V X5R-CERM

10%

0201

0.1UF

C3477

1

2

0.6NH+/-0.1NH-0.85A

0201

OMIT_TABLE

L3474

1 2

NOSTUFF

16V

10%

0.1UF

X5R-CERM 0201

C3476

1

2

6

16 95

6

16 95

X19/ALS/CAMERA CONNECTOR

SYNC_DATE=10/21/2010

SYNC_MASTER=K91_MLB

L3470,L3471,L3473,L3474

117S0002

4

RES, 0OHM, 0201

PP3V3_WLAN_R

MIN_LINE_WIDTH=1 mm

MIN_NECK_WIDTH=0.5 mm

ISNS_AIRPORT_P

P3V3WLAN_SS

USB_CAMERA_N

USB_CAMERA_P

PP5V_S3

AP_RESET_L

P3V3WLAN_VMON

AP_PWR_EN

AP_CLKREQ_L

PP3V3_S3

PM_WLAN_EN_L

PCIE_WAKE_L

USB_CAMERA_CONN_N

USB_CAMERA_CONN_P

SMBUS_SMC_A_S3_SDA

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_ALSCAMERA_F SMBUS_SMC_A_S3_SCL

PCIE_CLK100M_AP_N

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_S3_BT_F

WIFI_EVENT_L

SMBUS_SMC_0_S0_SCL

MIN_NECK_WIDTH=0.4 mm MIN_LINE_WIDTH=1 mm

PP3V3_WLAN_F

PP3V3_S3

SMBUS_SMC_0_S0_SDA

AP_RESET_CONN_L

PCIE_AP_D2R_PI_P

AP_CLKREQ_Q_L

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_CONN_N

PCIE_CLK100M_AP_CONN_P

PCIE_AP_D2R_PI_N

USB_BT_P

PCIE_AP_R2D_C_N

ISNS_AIRPORT_N

PCIE_AP_R2D_C_P

PP3V3_S3

PCIE_AP_R2D_PI_N

USB_BT_N

PP3V3_WLAN_F

PCIE_AP_R2D_N

PCIE_AP_D2R_N

PP3V3_WLAN

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.2 mm

PCIE_AP_R2D_P

PCIE_AP_R2D_PI_P

PCIE_AP_D2R_P

34 OF 132 31 OF 105

6 7

29 42 43 44 46 67 72 82

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6

94

6

94

6

31 104

6 7 8

18 24 25 29 30 31 32 48 49 50 54 55

73 88

104

6

95

6

100

6

100

95

6 7 8

18 24 25 29

30 31 32 48 49 50

54 55 73 88

104

95

31

104

6

46

6

95

NC NC

NC

NC NC

OUT

SYM_VER-1

BI

IN

IN IN

OUT

NC

BI

IN

OUT

NC

DET_OUT

DET_IN

RST_IN*

DET_CHNGD*

LOW_PWR

RST_OUT*

VDD

THRM

GND PAD

(IPU)

(OD)

DLY

XOR

LOGIC

RST

IN

THRML_PAD

RCLKEN

GND

NC4

NC3

NC2

NC1

VOUT1P5

CPPE*

PERST*

NC0

OC*

SYSRST*

STBY*

AUXOUT

VOUT3P3

VIN1P5

VIN3P3

CPUSB*

SHDN*

AUXIN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DETECT-CHANGED PCH GPIO LATCH CIRCUIT

R3514 and R3512 mutually exclusive

when R3511 is NOT STUFFED.

Must STUFF R3512 and NOSTUFF R3514

10ms regardless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

deasserts for >80ms, then asserts for

When ENET_LOW_PWR deasserts, RST_OUT#

to bypass reset logic

DLY block is 20ms nominal

OUTPUT DECOUPLING

(IPU)

All pull-ups to AUXIN rail

518S0647

EXPRESSCARD/34 FLEX CONNECTOR

INPUT DECOUPLING

X5R

6.3V

603

20%

10uF

C3505

1

2

16

8

24

10%

402-1

X5R

16V

0.1UF

C3502

1

2

PLACE_NEAR=J3500.3:4mm

DLP0NS

90-OHM

L3502

1 2

34

20%

603

6.3V

10uF

X5R

C3503

1

2

16V X5R

402-1

0.1UF

10%

C3571

1 2

PLACE_NEAR=J3500.24:4mm

DLP11S

90-OHM-100MA

PLACE_NEAR=J3500.19:4mm

L3503

1 2

34

16V X5R

402-1

0.1UF

10%

C3570

1 2

PLACE_NEAR=J3500.25:4mm

8

24 32

100

8

24 32

100

16 95

16

100

16

100

6

16

100

CERM

10V

20%

402

0.1uF

C3500

1

2

6

16

100

6

17 25 31 85

6

16 23 26 28 30 41 48 62 89

95

6

16 23 26 28 30 41 48 62 89 95

5

4

1

2

3

U3551

74HC1G00GWDG

SC70-5

CRITICAL

502250-8627

F-RT-SM

J3500

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

4

5

6

7

8

9

21

R3504

OMIT

NONE

NONE NONE

402

SHORT

21

R3503

SHORT

OMIT

NONE

NONE NONE

402

21

R3502

OMIT

SHORT

NONE

402

0

MF-LF

5%

402

1/16W

R3505

1 2

25 35

36 96

R3514

21

0

1/16W

5%

MF-LF

402

1/16W

2

1

MF-LF

NOSTUFF

R3512

0

5%

402

C3510

402-1

2

1

10V X5R

1UF

10%

5

9

4

3

2

7

6

8

TDFN

SLG4AP014V

1

CRITICAL

U3511

19 36

25

CRITICAL

QFN

TPS2231

U3500

17

15

10 9

7

4

5 13

14 16

19

8

18

20

1 6

21

12

2

11

3

10uF

603

20% X5R

6.3V

C3535

1

2

CERM

20% 10V

402

0.1uF

C3534

1

2

603

10uF

20%

6.3V X5R

C3531

1

2

CERM

20% 10V

402

0.1uF

C3530

1

2

20%

2

1

C3550

0.1uF

402

CERM

10V

2

1

R3561

1% 1/16W MF-LF

402

100K

2

1

C3560

0.1uF

402

10V

20%

CERM

16V 402-1

0.1UF

10% X5R

C3501

1

2

C2

A2

C1

B1

U3561

BGA

SN74LVC1G04YZPR

6.3V

20%

603

X5R

10uF

C3504

1

2

5

4

1

2

3

U3560

SC70-5

74HC1G00GWDG

SYNC_DATE=07/27/2010SYNC_MASTER=K92_ERIC

ExpressCard Connector

EXCARD_CPUSB_L

EXCARD_CLKREQ_L

EXCARD_RCLKEN

EXCARD_CLKREQ_CONN_L

PP3V3_S0

EXCARD_CLKREQ_CONN

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

USB_EXCARD_P

USB_EXCARD_N

PCIE_EXCARD_R2D_P

PCIE_EXCARD_R2D_N

PCIE_CLK100M_EXCARD_CONN_P

PCIE_CLK100M_EXCARD_CONN_N

MAKE_BASE=TRUE

USB_EXCARD_P

USB_EXCARD_N

MAKE_BASE=TRUE

USB2_EXCARD_CONN_P

USB2_EXCARD_CONN_N

EXCARD_RESET_R_L

PP3V3_S0_EXCARD_R

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.3mm

VOLTAGE=3.3V

EXCARD_CPPE_L

EXCARD_CP

PCIE_EXCARD_D2R_N

PCIE_EXCARD_D2R_P

PCIE_CLK100M_EXCARD_CONN_P EXCARD_CPPE_L PP3V3_S0_EXCARD_SWITCH

PCIE_EXCARD_R2D_N

PCIE_EXCARD_R2D_P

PLT_RESET_SWITCH_L PCIE_WAKE_L PP1V5_S0_EXCARD_SWITCH SMBUS_PCH_CLK

USB2_EXCARD_CONN_P

USB2_EXCARD_CONN_N

EXCARD_CPUSB_L

SMBUS_PCH_DATA

PP1V5_S0_EXCARD_SWITCH

PP3V3_S3_EXCARD_SWITCH

EXCARD_CLKREQ_CONN_L

PCIE_CLK100M_EXCARD_CONN_N

PP3V3_S0_EXCARD_SWITCH

PP1V5_S0

PP3V3_S3_EXCARD_R

EXCARD_CPUSB_L

PLT_RST_BUF_L

PP1V5_S0

PP3V3_S0

PP3V3_S3

TP_EXCARD_STBY_L

EXCARD_RCLKEN

PP3V3_S3

PP1V5_S0_EXCARD_SWITCH

MIN_NECK_WIDTH=0.11mm

VOLTAGE=1.5V

MIN_LINE_WIDTH=.6mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=.6mm MIN_NECK_WIDTH=0.2mm

PP3V3_S0_EXCARD_SWITCH

VOLTAGE=3.3V

MIN_LINE_WIDTH=.3mm MIN_NECK_WIDTH=0.2mm

PP3V3_S3_EXCARD_SWITCH

EXCARD_OC_L

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2mm

PP1V5_S0_EXCARD_R

MIN_LINE_WIDTH=0.6mm

EXCARD_CPPE_L

PLT_RESET_SWITCH_L

SLG_ENET_RESET_OUT_L

ENET_RESET_L

ENET_RESET_L_R

ENET_LOW_PWR

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V

PP3V3_S3_EXCARD_R

PP3V3_S3

35 OF 132 32 OF 105

6

32

6

32

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6

32

100

6

32

100

6

32

100

6

32

100

6

32

100

6

32

100

6

32

6

32

100

6

32

6

32

6

32

100

6

32

100

6

32

6

32

6

32

100

6

32

100

6

32

6

32

6

32

6

32

6

32

100

6

32

7

16 20 22 25

32 41 57 71

32

6

32

7

16 20 22 25 32 41 57 71

6 7

12 23 25 26 28 32 35

36 39 40 41 46 48 49 50 51

52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7 8

18 24 25 29 30 31

32 48 49 50 54 55 73 88

104

32

6 7 8

18 24 25 29 30 31 32

48 49 50 54 55 73 88

104

6

32

6

32

6

32

6

32

6

32

6 7 8

18 24 25 29 30 31 32 48 49 50 54

55 73 88

104

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

OUT

IN IN

OUT

BI

DPSNK0_ML_LANE_3P DPSNK0_ML_LANE_3N

DPSNK0_ML_LANE_2P

DPSRC0_HOT_PLUG_DET

TEST_POINT_2 TEST_POINT_3

DPSNK0_HOT_PLUG_DET

DPSNK0_AUX_CHN

DPSNK0_AUX_CHP

DPSNK0_ML_LANE_0N

DPSNK0_ML_LANE_0P

DPSNK0_ML_LANE_1N

DPSNK0_ML_LANE_1P

DPSNK0_ML_LANE_2N

TEST_POINT_0

TEST_EN

THERM_DP

EE_CLK

EE_CS*

EE_DO

EE_DI

PCIE_CLKREQ_3*

PCIE_CLKREQ_2*

PCIE_CLKREQ_1*

PCIE_CLKREQ_0*

DPSNK1_ML_LANE_1P

DPSNK1_ML_LANE_2N

DPSNK1_ML_LANE_2P

DPSNK1_ML_LANE_3N

DPSNK1_ML_LANE_3P

DP_RES_1

DP_RES_0

DP_ATEST

DPSRC0_AUX_CHN

DPSRC0_AUX_CHP

DPSRC0_ML_LANE_0N

DPSRC0_ML_LANE_0P

DPSRC0_ML_LANE_1N

DPSRC0_ML_LANE_1P

DPSRC0_ML_LANE_2N

DPSRC0_ML_LANE_2P

DPSRC0_ML_LANE_3N

DPSRC0_ML_LANE_3P

TMU_CLK_OUT

TMU_CLK_IN

XTAL_25_IN

XTAL_25_OUT

REFCLK_100_IN_P REFCLK_100_IN_N

TDO

TCK

TMS

TDI

PCIE_RST_3*

PCIE_RST_1* PCIE_RST_2*

PCIE_RST_0*

RBIAS

RSENSE

PERST*

WAKE*

PER_1_P

PER_2_P

PER_3_P

MONDC0

MONOBSN

MONOBSP

MONDC1

PER_3_N

PER_2_N

PER_0_N

PER_0_P

PET_3_P PET_3_N

PET_2_N

PET_2_P

PET_1_P PET_1_N

PET_0_N

PET_0_P

TEST_POINT_1

DPSNK1_ML_LANE_0N

PER_1_N

DPSNK1_ML_LANE_0P

DPSNK1_ML_LANE_1N

DPSNK1_AUX_CHP

DPSNK1_HOT_PLUG_DET

DPSNK1_AUX_CHN

PRT0_T29T_N

PRT0_T29R_P PRT0_T29R_N

T29_0_LSEO T29_0_LSOE

PRT1_T29T_P PRT1_T29T_N

PRT1_T29R_P PRT1_T29R_N

T29_1_LSEO T29_1_LSOE

T29_SDA T29_SCL

PRT2_T29T_P PRT2_T29T_N

PRT2_T29R_P PRT2_T29R_N

T29_2_LSEO T29_2_LSOE

PRT3_T29T_P PRT3_T29T_N

PRT3_T29R_P PRT3_T29R_N

T29_3_LSEO T29_3_LSOE

PRT0_T29T_P

PORT2

PCIE GEN2

RECEIVE

TRANSMIT

PORTS

(SYM 1 OF 2)

JTAG

POWER ON RESET

MISC

CLOCKS

SOURCE PORT 0

DISPLAY

PORT3

PORT0PORT1

CLK REQUEST

EEPROM

TEST PORT

SINK PORT 0SINK PORT 1

BI

IN

BI

IN IN IN

OUT

IN

D

VCC

THM

VSS

PAD

Q

C

S_L

W_L

HOLD_L

OUT IN

OUT

IN

OUT

IN IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(T29_SPI_MOSI) (T29_SPI_MISO)

Not used in host mode.

100pF SRF > 40MHz

Use B1 GND ball for THERM_DN

SNK1 AC Coupling

SNK0 AC Coupling

NOTE: All unused LSOE/EO pairs should be aliased

(T29_SPI_CLK) (T29_SPI_CS_L)

together. Other signals okay to float (TP/NC).

DEBUG: For monitoring clock

DEBUG: For monitoring current/voltage

3.3K

MF-LF

402

5%

1/16W

R3690

1

2

14.0K

MF-LF

1%

1/16W

402

R3685

1

2

CERM

50V

5%

BYPASS=U3600.Y19::2mm

100PF

402

C3685

1

2

10% 16V CERM 402

BYPASS=U3600.Y19::5.08mm

0.01UF

C3686

1

2

80 84

0

5% 1/16W MF-LF 402

R3625

1

2

5% 1/16W

100K

402

MF-LF

R3632

1

2

85

6

85 97

6

85 97

85

6

85 97

6

85 97

6

85 97

6

85 97

6

85 97

6

85 97

8

33

8

33

8

5%

1/16W

100K

MF-LF

402

R3630

1

2

5%

MF-LF

100K

402

1/16W

R3631

1

2

1/16W MF-LF

NO STUFF

402

10K

5%

R3699

1

2

48 85 97

CRITICAL

FCBGA

T29

OMIT_TABLE

U3600

Y19 Y21 AA20

W2

V1

V5

Y9

AA10

Y7

AA8

Y5

AA6

Y3

AA4

U6

V7

U4

U14

V15

U12

V13

U10

V11

U8

V9

U16

W16

V3

Y11

AA12

Y13

AA14

Y15

AA16

Y17

AA18

L2

N2

P1 M1

B21

A20

M17

K17

P3 N4 M3 L4

K1 J2 K3 J4

T19

V19

M19

P19

H19

K19

D19

F19

E6

T21

V21

M21

P21

H21

K21

D21

F21

C2

C4

A4

A6

C6

C8

A8

A10

C10

C12

A12

A14

C14

C16

A16

A18

E16

G16

H17

E14

J6 K5

G6 H5

G4 H3

G2 H1

F5

F3

R2

T3

T1

E4 P5 N6 M5 L6

A2

R4

E2

U2

F1

P17 R16

1/16W

402

0

5%

MF-LF

R3629

1

2

3.3K

5%

402

MF-LF

1/16W

R3693

1

2

MF-LF 402

10K

5% 1/16W

R3698

1

2

10K

MF-LF

1/16W

5%

402

R3623

1

2

5%

402

1/16W

10K

MF-LF

R3622

1

2

402

MF-LF

10K

5% 1/16W

R3621

1

2

X5R

16V

0.1uF

10%

402

C3629

1 2

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

0.1uF

X5R

10% 16V

402

C3628

1 2

X5R

0.1uF

16V 402

10%

C3627

1 2

402

0.1uF

X5R

10% 16V

C3626

1 2

402

16V

X5R

0.1uF

10%

C3625

1 2

0.1uF

10%

402X5R

16V

C3624

1 2

402X5R

16V10%

0.1uF

C3623

1 2

X5R

0.1uF

10% 16V

402

C3622

1 2

603

MF-LF

1/16W

0.5%

1.0K

R3655

1

2

0.1uF

16V 402X5R

10%

C3621

1 2

16V 402

0.1uF

10% X5R

C3620

1 2

16V 402X5R

10%

0.1uF

C3630

1 2

16V 402X5R

10%

0.1uF

C3631

1 2

402

16V10%

X5R

0.1uF

C3632

1 2

16V 402

10%

0.1uF

X5R

C3633

1 2

16V 402

10% X5R

0.1uF

C3634

1 2

16V 402X5R

10%

0.1uF

C3635

1 2

16V 402

10% X5R

0.1uF

C3636

1 2

16V 402X5R

10%

0.1uF

C3637

1 2

16V 402X5R

10%

0.1uF

C3638

1 2

16V10%

0.1uF

X5R 402

C3639

1 2

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

6

79 97

402

6.3V

1UF

10%

CERM

C3690

1

2

6

79 97

6

79 97

5%

1/16W MF-LF

402

10K

R3651

2 1

8

19 88

16

8

19 23 88

8

19 88

MF-LF

1/16W

5%

402

1K

R3696

1

2

MF-LF

1/16W

402

806

1%

R3695

1 2

25

OMIT_TABLE

CRITICAL

M95160

MLP

2KX8-1.8V

U3690

6

5

7

2

1

9

8

4

3

85

8

33

8

33

35

16 95

0.1uF

10% 16V X5R 402

C3601

1 2

X5R

0.1uF

10% 16V 402

C3600

1 2

0.1uF

402X5R16V10%

C3602

1 2

0.1uF

402X5R16V10%

C3603

1 2

16V X5R 40210%

NO STUFF

0.1uF

C3615

1 2

0.1uF

X5R 402

NO STUFF

10% 16V

C3616

1 2

MF-LF

1/16W

402

5%

3.3K

R3692

1

2

0

402

MF-LF1/16W

5%

NO STUFF

R3611

1 2

MF-LF0402

1/16W

5%

NO STUFF

R3610

1 2

10% 16V

0.1uF

X5R 402

C3604

1 2

10% 16V X5R 402

0.1uF

C3605

1 2

X5R 402

0.1uF

10% 16V

C3606

1 2

X5R

0.1uF

16V10% 402

C3607

1 2

0.1uF

10% X5R 40216V

C3640

1 2

16V

0.1uF

10% 402X5R

C3641

1 2

X5R

0.1uF

10% 40216V

C3642

1 2

1/16W

5% MF-LF

402

3.3K

R3691

1

2

0.1uF

40210% 16V X5R

C3643

1 2

16V X5R 40210%

0.1uF

C3645

1 2

0.1uF

40216V X5R10%

C3644

1 2

16V

0.1uF

10% 402X5R

C3646

1 2

402X5R

0.1uF

10% 16V

C3647

1 2

35

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

8

95

T29 Host (1 of 2)

SYNC_DATE=11/09/2010

SYNC_MASTER=T29_REF

T29_LSEO_LSOE3 T29_LSEO_LSOE3

T29_LSEO_LSOE2

PCIE_T29_R2D_C_N<2>

PP3V3_T29

T29_SPI_MISO

I2C_T29_SCL

I2C_T29_SDA

T29ROM_HOLD_L

T29ROM_WP_L

T29_SPI_CS_L T29_SPI_CLK

T29_SPI_MOSI

PP3V3_T29

PCIE_T29_D2R_P<1>

PCIE_T29_D2R_P<2>

PCIE_T29_D2R_N<2>

PCIE_T29_D2R_N<3>

TP_T29_MONDC0

PCIE_T29_R2D_C_P<3>

PCIE_T29_R2D_C_N<3>

PP3V3_T29

PCIE_T29_D2R_N<0>

TP_T29_MONDC1

SYSCLK_CLK25M_T29

TP_T29_MONOBSP

TP_T29_MONOBSN

PCIE_T29_R2D_C_N<1>

PCIE_T29_R2D_C_P<1>

PCIE_T29_R2D_C_P<0>

PCIE_T29_R2D_C_P<2>

PCIE_T29_D2R_N<1>

PCIE_T29_D2R_P<0>

PCIE_T29_D2R_P<3>

PCIE_T29_R2D_C_N<0>

DP_T29SNK0_ML_C_P<0>

DP_T29SNK0_ML_C_N<0>

DP_T29SNK0_ML_C_P<1>

DP_T29SNK0_ML_C_N<1>

DP_T29SNK0_ML_C_N<2>

DP_T29SNK0_ML_C_P<2>

DP_T29SNK0_ML_C_P<3>

DP_T29SNK0_AUXCH_C_P

DP_T29SNK0_AUXCH_C_N

DP_T29SNK1_ML_C_P<0>

DP_T29SNK1_ML_C_N<0>

DP_T29SNK1_ML_C_P<1>

DP_T29SNK1_ML_C_N<1>

DP_T29SNK1_ML_C_P<2>

DP_T29SNK1_ML_C_N<2>

DP_T29SNK1_ML_C_P<3>

DP_T29SNK1_ML_C_N<3>

DP_T29SNK1_AUXCH_C_P

DP_T29SNK1_AUXCH_C_N

DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_N<0>

DP_T29SNK0_ML_P<0>

DP_T29SNK0_ML_N<1>

DP_T29SNK0_ML_P<3>

DP_T29SNK1_ML_P<0>

DP_T29SNK1_ML_N<0>

DP_T29SNK0_AUXCH_P

DP_T29SNK0_ML_N<2>

DP_T29SNK0_ML_P<2>

DP_T29SNK1_ML_N<2>

DP_T29SNK1_ML_N<3>

DP_T29SNK1_AUXCH_P

DP_T29SNK1_AUXCH_N

DP_T29SNK1_ML_P<1>

DP_T29SNK1_ML_N<1>

DP_T29SNK1_ML_P<2>

DP_T29SNK1_ML_P<3>

T29_R2D_C_P<0>

NC_T29_D2RN<3>

NC_T29_D2RP<3>

NC_T29_R2D_CN<3>

NC_T29_R2D_CP<3>

NC_T29_D2RN<2>

NC_T29_D2RP<2>

NC_T29_R2D_CN<2>

NC_T29_R2D_CP<2>

T29_D2R_N<1>

T29_D2R_P<1>

T29_R2D_C_N<1>

T29_R2D_C_P<1>

T29_LSOE<0>

T29_LSEO<0>

T29_D2R_N<0>

T29_D2R_P<0>

T29_R2D_C_N<0>

DP_T29SNK1_AUXCH_N DP_T29SNK1_HPD

DP_T29SNK1_AUXCH_P

DP_T29SNK1_ML_N<1> DP_T29SNK1_ML_P<0>

PCIE_T29_R2D_N<1>

DP_T29SNK1_ML_N<0>

TP_T29_TEST_POINT_1

PCIE_T29_D2R_C_P<0> PCIE_T29_D2R_C_N<0>

PCIE_T29_D2R_C_N<1>

PCIE_T29_D2R_C_P<1>

PCIE_T29_D2R_C_P<2> PCIE_T29_D2R_C_N<2>

PCIE_T29_D2R_C_N<3>

PCIE_T29_D2R_C_P<3>

PCIE_T29_R2D_P<0> PCIE_T29_R2D_N<0>

PCIE_T29_R2D_N<2>

PCIE_T29_R2D_N<3>

T29_MONDC1

T29_MONDC0

PCIE_T29_R2D_P<3>

PCIE_T29_R2D_P<2>

PCIE_T29_R2D_P<1>

T29_RESET_L

T29_RSENSE

T29_RBIAS

TP_T29_PCIE_RESET0_L

TP_T29_PCIE_RESET2_L

TP_T29_PCIE_RESET1_L

TP_T29_PCIE_RESET3_L JTAG_ISP_TDI

JTAG_T29_TMS JTAG_ISP_TCK JTAG_ISP_TDO

PCIE_CLK100M_T29_N

PCIE_CLK100M_T29_P

TP_T29_XTAL25OUT

SYSCLK_CLK25M_T29_R

T29_TMU_CLK_IN

T29_TMU_CLK_OUT

TP_DP_T29SRC_ML_CP<3> TP_DP_T29SRC_ML_CN<3>

TP_DP_T29SRC_ML_CP<2> TP_DP_T29SRC_ML_CN<2>

TP_DP_T29SRC_ML_CP<1> TP_DP_T29SRC_ML_CN<1>

TP_DP_T29SRC_ML_CP<0> TP_DP_T29SRC_ML_CN<0>

TP_DP_T29SRC_AUXCH_CP TP_DP_T29SRC_AUXCH_CN

T29_DP_ATEST

T29_DP_RES

DP_T29SNK1_ML_P<3> DP_T29SNK1_ML_N<3>

DP_T29SNK1_ML_P<2> DP_T29SNK1_ML_N<2>

DP_T29SNK1_ML_P<1>

T29_CLKREQ_ISOL_L T29_GPIO<1> T29_GPIO<2> T29_RSVD

T29_THERMD_P T29_TEST_EN

TP_T29_TEST_POINT_0

DP_T29SNK0_ML_N<2> DP_T29SNK0_ML_P<1>

DP_T29SNK0_ML_N<1> DP_T29SNK0_ML_P<0>

DP_T29SNK0_ML_N<0> DP_T29SNK0_AUXCH_P

DP_T29SNK0_AUXCH_N DP_T29SNK0_HPD

T29_TEST_POINT_3

TP_T29_TEST_POINT_2

DP_T29SRC_HPD

DP_T29SNK0_ML_P<2>

DP_T29SNK0_ML_N<3>

DP_T29SNK0_ML_P<3>

T29_PCIE_WAKE_L

T29_MONOBSN

T29_MONOBSP

DP_T29SNK0_ML_C_N<3>

DP_T29SNK0_ML_N<3>

DP_T29SNK0_AUXCH_N

T29_LSEO<1> T29_LSOE<1>

36 OF 132 33 OF 105

7

16 19 25 33 34 35 88

97

7

16 19 25 33 34 35 88

7

16 19 25 33 34 35 88

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

95

6

33 97

95

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

51

100

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

VCC3P3_DP_RX1 VCC3P3_DP_RX1

VCC3P3_DP_TXRX VCC3P3_DP_TXRX

VDD3P3DP_PLL

VCC3P3_DP_TXRXBIAS

VSSDP

VSSDP VSSDP VSSDP

VSSDP

VSSDP_PLL

VSSDP

VSSPE

VSSPE VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE

VCC1P0

VCC1P0 VCC1P0

VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE VCC1P0_PE

VDD1P0_DP_TXRX

VDD1P0_DP_RX1

VDD1P0_DP_TXRX

VDD1P0_DP_PLL

VSS VSS VSS

VSS

VSS VSS VSS

VSS

VSS VSS

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE

VSSPE

VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE VSSPE

VSSPE

VCC1P0_PE

VCC3P3 VCC3P3 VCC3P3

VCC3P3_T29 VCC3P3_T29

GND VCC

(SYM 2 OF 2)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from Vendor slide (<REDACTED> power measure 1.ppt), emailed 6/21/2010, TDP @ 90C.

0-ohms are placeholders for now, replace

2100 mA (Single Port) 2250 mA (Dual Port) EDP: 3000 mA

135 mA (Single-Port)

with proper values after characterization.

152 mA (Dual-Port) EDP: 200 mA

0402

FERR-120-OHM-1.5A

L3730

1 2

6.3V

1UF

CERM 402

10%

C3712

1

2

1UF

6.3V

10%

402

CERM

C3713

1

2

0

1/16W MF-LF

5%

402

R3720

1 2

6.3V

10%

402

CERM

1UF

C3714

1

2

CERM

6.3V

20%

2.2UF

402-LF

C3730

1

2

6.3V

10%

402

CERM

1UF

C3720

1

2

6.3V

10%

402

CERM

1UF

C3721

1

2

6.3V

10%

402

CERM

1UF

C3722

1

2

1UF

CERM 402

10%

6.3V

C3708

1

2

10UF

X5R 603

20%

6.3V

C3700

1

2

6.3V

20%

603

X5R

10UF

C3701

1

2

6.3V

10%

402

CERM

1UF

C3753

1

2

6.3V

10%

402

CERM

1UF

C3752

1

2

6.3V

10%

402

CERM

1UF

C3744

1

2

6.3V

10%

402

CERM

1UF

C3743

1

2

1UF

CERM 402

10%

6.3V

C3709

1

2

6.3V CERM

20%

2.2UF

402-LF

C3770

1

2

CERM

6.3V

20%

2.2UF

402-LF

C3760

1

2

FERR-120-OHM-1.5A

0402

L3770

1 2

CERM

6.3V

10%

402

1UF

C3751

1

2

CERM

1UF

402

10%

6.3V

C3750

1

2

MF-LF

0

402

5%

1/16W

R3760

1 2

MF-LF

0

402

5%

1/16W

R3750

1 2

1UF

CERM

402

10%

6.3V

C3745

1

2

603

6.3V

20%

10UF

X5R

C3746

1

2

6.3V

20%

603

X5R

10UF

C3747

1

2

6.3V

10%

402

1UF

CERM

C3710

1

2

1UF

CERM 402

10%

6.3V

C3711

1

2

FCBGA

OMIT_TABLE

CRITICAL

T29

U3600

H9 H11 H13

K9 K11 K13

M9 M11 M13

H15 K15 M15

E8 E10 E12 G14

H7 M7 K7

P7 R6

P9 P11

P15

G10 G12

R14

R8 R10 R12

P13

G8

J8

N10 N12 N14

J10 J12 J14

L8 L10 L12 L14

N8

T5 T7

W10 W12 W14 Y1 AA2

T9 T11 T15 T17 V17 W4 W6 W8

T13

B1

B3

C18 C20

D1

D3

D5

D7

D9 D11 D13 D15

B5

D17 E18 E20

F7

F9 F11 F13 F15 F17 G18

B7

G20 J16 J18 J20 L16 L18 L20 N16 N18 N20

B9

R18 R20 U18 U20 W18 W20

B11 B13 B15 B17 B19

1UF

6.3V

10% 402

CERM

C3705

1

2

CERM 402

10%

6.3V

1UF

C3706

1

2

CERM 402

10%

6.3V

1UF

C3707

1

2

SYNC_MASTER=T29_REF

SYNC_DATE=11/09/2010

T29 Host (2 of 2)

PP3V3_T29

PP1V05_T29_VDD_DPPLL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.05V

PP1V05_T29_VDD_DP

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V05_T29

PP3V3_T29_DPBIAS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_T29_PLL

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_T29_DP

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

37 OF 132 34 OF 105

7

16 19 25 33 35 88

7

35

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

OUT

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

GND

VOUT

ON

VIN

IN

D

G S

D

S G

D

S G

IN

SGD

NC

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

<Ra>

Max Current = 1A

Vout = 15.47V

Freq = 300KHz

Page Notes

- =PPVIN_SW_T29BST (8-13V Boost Input)

- =PP18V_T29_REG (18V Boost Output)

- =PP1V05_T29_FET (1.05V FET Output)

U3810 & U3815/U3816

50 mOhm Max

Max Current = 3.4A (85C)

T29 15V Boost Regulator

for 2S.

Changes required

8-13V Input

3.3V T29 Switch

Load Switch 18 mOhm Typ

TPS22924C

Max Output: 2A per IC

DLY = 60 ms +/- 20%

Max Current = 1.7A (85C)

R(on)

Part Type

U3816.A2:

Pull-up provided by SB page.

Platform (PCIe) Reset

Open-Drain GPIO

1.05V T29 Switch

Supervisor & CLKREQ# Isolation

Power aliases required by this page:

Vout = 1.6V * (1 + Ra / Rb)

<Rb>

GND inside package,

SGND shorted to

no XW necessary.

Max Vgs: 10V

<R1>

add property on another page.

Voltage not specified here,

Rds(on): 46mOhm @ 4.5V Vgs

Vds(max): -30V

SI8409DB:

Vgs(max): +/-12V

Id(max): 3.7A @ 70C

Vgs(th): -1.4V

<R2>

- =PP3V3_T29_FET (3.3V FET Output)

- =PP3V3_T29_P3V3T29FET (3.3V FET Input)

Signal aliases required by this page:

- =PP1V05_T29_P1V05T29FET (1.05V FET Input)

- =T29_RESET_L

- =T29_CLKREQ_L

- =PP3V3_S0_T29PWRCTL

BOM options provided by this page: T29BST:Y - Stuffs 18V boost circuitry.

UVLO = 4.55V (falling), 4.95 (rising)

UVLO(rising) = UVLO(falling) + (2uA * R1)

UVLO(falling) = 1.22 * (R1 + R2) / R2

TPS22924

CSP

CRITICAL

U3810

C1

C2

A2 B2

A1 B1

CSP

CRITICAL

TPS22924

U3815

C1

C2

A2 B2

A1 B1

33

1/16W

402

MF-LF

5%

10K

R3803

2

1

16

0.1UF

10% X5R

25V 402

C3800

1

2

25 32

33 35

402

CERM

1UF

10%

6.3V

C3810

1

2

1UF

10%

6.3V CERM

402

C3815

1

2

CRITICAL

TDFN

6

5

7

3

8

4

2

9

1

SLG4AP016V

U3800

402

MF-LF

1/16W

5%

100K

R3807

1

2

19

CRITICAL

CSP

PLACE_NEAR=U3815.B2:3 mm

U3816

C1

C2

A2 B2

A1 B1

TPS22924

16

85 86

330K

1/16W MF-LF

5%

402

T29BST:Y

R3881

1

2

470K

1/16W

5%

402

MF-LF

T29BST:Y

R3880

1

2

X5R

10% 25V

0.1UF

402

T29BST:Y

C3880

1

2

SOD-VESM-HF

SSM3K15FV

T29BST:Y

Q3805

3

1

2

73.2K

402

1% 1/16W MF-LF

T29BST:Y

R3892

1

2

330K

MF-LF

1/16W 402

5%

T29BST:Y

R3887

1

2

SSM6N37FEAPE

SOT563

T29BST:Y

Q3888

3

5

4

SOT563

SSM6N37FEAPE

T29BST:Y

Q3888

6

2

1

1%

41.2K

MF-LF

402

1/16W

T29BST:Y

R3894

1

2

10%

402

CERM-X5R

6.3V

0.33UF

T29BST:Y

C3894

1

2

330K

MF-LF

1/16W 402

5%

T29BST:Y

R3888

1

2

45 91

50V CERM

100PF

5%

402

NO STUFF

C3889

1

2

MF-LF

1%

402

1/16W

15.8K

R3896

1

2

T29BST:Y

1206

50V

4.7UF

10%

T29BST:Y

C3895

1

2

X7R-CERM

50V

X7R-CERM

1206

4.7UF

10%

T29BST:Y

C3896

1

2

1206

X7R-CERM

4.7UF

10% 50V

T29BST:Y

C3897

1

2

CERM 402

NO STUFF

100PF

5% 50V

C3887

1

2

805

X5R

10V

10%

C3892

1

2

4.7UF

T29BST:Y

BGA

SI8409DB

CRITICAL T29BST:Y

Q3880

2 3

1

4

MF-LF

402

1/16W

1%

10K

T29BST:Y

R3893

1

2

402

1%

200K

1/16W MF-LF

T29BST:Y

R3891

1

2

10% X5R

805

25V

10UF

T29BST:Y

C3890

1

2

805

X5R

10UF

10% 25V

T29BST:Y

C3891

1

2

10UH-4A-68-MOHM

PCMB063T-100MS

CRITICAL T29BST:Y

L3895

1 2

NO STUFF

402

5%

100PF

CERM

50V

C3888

1

2

LT3957

QFN

CRITICAL T29BST:Y

U3890

25

31

1213141516

17

28

1 2 10 35 36

33

6

3

42324

37

32

8

9

20

21

34

30

27

38

1/16W MF-LF

1%

T29BST:Y

137K

1

2

R3895

402

12

SM

PLACE_NEAR=C3895.1:2 mm

XW3895

1/16W

402

MF-LF

5%

0

T29BST:Y

R3889

1

2

DFLS230L

POWERDI-123

CRITICAL T29BST:Y

D3895

1

2

1206

10%

4.7UF

X7R-CERM

50V

T29BST:Y

C3898

1

2

10%

0.001UF

402

X7R

50V

T29BST:Y

C3899

1

2

10%

0.01UF

402

X7R

50V

T29BST:Y

C3893

1

2

T29 Power Support

SYNC_MASTER=T29_REF

SYNC_DATE=11/09/2010

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

DIDT=TRUE

SWITCH_NODE=TRUE

T29BST_BOOST

T29BST_SNS2

PP15V_T29

PPBUS_G3H

GND_T29BST_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

T29_A_HV_EN

SMC_DELAYED_PWRGD

T29BST_SS

T29BST_RT

T29BST_INTVCC

T29BST_SHDN_DIV

T29BST_PWREN_DIV_L

PPVIN_SW_T29BST

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

T29BST_VC

T29BST_EN_UVLO

T29BST_PWREN_L

T29BST_VC_RC

T29BST_SNS1

PP3V3_T29

T29_PWR_EN

T29_CLKREQ_L

PLT_RST_BUF_L

T29_SW_RESET_L

T29_RESET_L

T29_CLKREQ_ISOL_L

PP1V05_S0

PP1V05_T29

PP3V3_S0

PP1V05_T29

PP3V3_T29

MAKE_BASE=TRUE

T29_CLKREQ_ISOL_L

T29BST_FBX

T29BST_VSNS

38 OF 132 35 OF 105

7 8

86

6 7 8

39 49 50 63 64 90

7

16 19 25 33 34 35 88

7 9

10 12 13

14 23 39 45 68

70 73

102 104

105

7

34 35

6 7

12 23 25

26 28 32 35 36

39 40 41 46 48

49 50 51 52 54

57 61 62 72 73

80 83 84 85 88

89 91

100 102

6 7

12 23 25 26 28 32 35 36 39

40 41 46 48 49 50 51 52 54 57 61

62 72 73 80 83 84 85 88 89 91

100

102

7

34 35

7

16 19 25 33 34 35 88

33 35

IN

OUT

IN

OUT

IN

BI

BI BI

BI BI BI BI BI

NC

BI

BI BI

OUT

IN

OUT

VDDC

SR_LX

PCIE_PLLVDDL

SR_VFB

SR_VDDP

SR_VDD

SCLK SI/LINKLED*

CS*

SO

SPD100LED*/SERIAL_DO TRAFFICLED*/SERIAL_DI

TRD0_P

TRD1_P

TRD0_N

TRD1_N

TRD2_N

TRD2_P

TRD3_N

TRD3_P

GPIO_1/CR_BUS_PWR

GPIO_0

RE*/GPIO_2

VMAIN_PRSNT

PCIE_TXD_N PCIE_TXD_P

PCIE_RXD_N

PCIE_RXD_P

PCIE_REFCLK_N

PCIE_REFCLK_P

PERST*

CLKREQ*

WAKE*

LOW_PWR

SD_DETECT/WE*

CR_CMD/CLE

CR_CLK/RY_BY*

CR_DATA0 CR_DATA1

CR_DATA3

CR_DATA2

CR_DATA4 CR_DATA5 CR_DATA6

CE*/MS_INS*

CR_DATA7

CR_LED/ALE

XD_DETECT

THRM_PAD

XTALI XTALO

RDAC

GPHY_PLLVDDL

AVDDH

VDDO

XTALVDDH

BIASVDDH

AVDDL

SMD_DATA

SMB_CLK

CR_WP*/XD_WP*

OUT

BI

BI BI

NC

RESET*

CS*

SCK

SO

WP*

SI

GND

VCC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPD)

281mA (1000base-T max power, Caesar IV)

Must isolate from PCIe WAKE# if PHY

N-channel FET isolation suggested.

=ENET_WAKE_L to PCIE_WAKE_L.

(Required ROM size TBD)

(IPD)

No MS (Memory Stick) Insert feature needed.

internal SR. IPD has a race condition.

NOTE: "IPx" == Programmable pull-up/down

SD_DETECT can only be used active low due to errata.

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

(IPD)

(IPU)

Atmel AT45DB011D (1Mbit) ROM. If a different

other 3 SPI pins configures ENET for the

(IPU)

Control signal to light LED or control SD bus power.

(IPx)

(IPU)

(IPD)

(OD)

(IPD)

Current Limiting

(OD)

o

(OD)

NOTE: ENETM requires SI pull-down instead of SO.

PHY Non-Volatile Memory

If PHY is always powered then alias

is powered-down in S3/S5. Standard

ROM contains MAC address, PCIe config

???mA (1000base-T, Caesar V)

ROM is used then the straps must change.

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

Internal 1.2V Switching Regulator pins.

Required for proper PHY operation.

info as well as code for Bonjour proxy.

(See note)

WAKE#

SR_DISABLE must be pulled down to use

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

the card reader on-chip I/O. Connect only to U3900 pin 20.

BCM57765 supports both active-levels for WP.

NOTE: Pull-down on SO plus internal pull-ups on

VDD for Card Reader I/O

Special Star routing needed on these pins. Decoupling on Pg 37.

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

Resistor

2

1

C3921

402

16V

10%

X7R-CERM

0.1UF

10UF

X5R 805

10%

2

1

6.3V

C3935

CRITICAL

2

1

C3925

X5R-CERM 603

10%

4.7UF

6.3V

21

L3925

SM

CRITICAL

FERR-600-OHM-0.5A

2

1

C3920

10%

6.3V 603

X5R-CERM

4.7UF

21

L3920

SM

CRITICAL

FERR-600-OHM-0.5A

21

L3900

CRITICAL

SM

FERR-600-OHM-0.5A

21

L3905

FERR-600-OHM-0.5A

CRITICAL

SM

2

1

R3942

1/16W

1K

402

5% MF-LF

16 95

32 96

16

25

19 32

25

21

C3951

10% X5R

402

0.1uF

16V

21

C3950

402

X5R

16V

10%

0.1uF

21

X5R

10% 16V

0.1uF

402

C3956

21

C3955

0.1uF

10% 16V X5R 402

2

1

R3965

1%

1.24K

MF-LF 402

1/16W

16 95

37 96

2

1

MF-LF 402

5%

4.7K

1/16W

R3941

2

1

R3940

5%

MF-LF

1/16W

4.7K

402

8

1 2

5%

402

0

R3943

1/16W MF-LF

2

1

R3990

4.7K

402

5% MF-LF

NOSTUFF

1/16W

8

10% X5R-CERM

6.3V

2

1

4.7UF

603

C3970

402

X7R-CERM

1

C3971

0.1UF

10% 16V

2

402

X7R-CERM

2

1

C3972

16V

10%

0.1UF

25

2

1

R3910

MF-LF

402

4.7K

5%

1/16W

17

19

18

3

58

206256

7

61

35

50 49

46 47

44 43

40 41

67

69

13

151416

68

2

65

10

6

64

1

66

38

11

28

27

33 34

31 30

32

29

59

8

4

5

36

63

57

60

55

54

53

52

22

23

24

25

26

21

12

37

45

39

48

42

U3900

CRITICAL

OMIT

BCM57765B0

QFN-8X8

9

51

2

MF-LF

402

1K

1/16W

1

5%

R3980

8

21

L3910

FERR-600-OHM-0.5A

CRITICAL

SM

8

2

1

C3910

0.1UF

16V

10%

402

X7R-CERM

8

2

1

C3900

402

X7R-CERM

16V

10%

0.1UF

2

1

C3911

X7R-CERM

16V

10%

402

0.1UF

2

1

C3990

402

16V X7R-CERM

0.1UF

10%

2

1

C3905

X7R-CERM

16V

0.1UF

10% 402

2

1

C3930

603

10%

4.7UF

X5R-CERM

6.3V

1

C3931

10% 16V

402

0.1UF

X7R-CERM

2

21

L3930

CRITICAL

SM

FERR-600-OHM-0.5A

2

1

C3915

10%

6.3V

X5R-CERM

603

4.7UF

2

1

C3916

10% 16V

402

X7R-CERM

0.1UF

5

6

8

12

3

7

4

AT45DB011D

OMIT

SOIC-8S1

U3990

2

1

R3997

1/16W

5%

402

MF-LF

4.7K

2

C3936

X7R-CERM

402

10% 16V

0.1UF

1

2

1

0.1UF

X7R-CERM

10% 16V

402

C3926

SYNC_MASTER=K92_ERIC SYNC_DATE=10/19/2010

ETHERNET PHY (CAESAR IV)

PP3V3R1V8_ENET_LR_OUT_REG

ENET_SR_LX

BCM57765_MOSI

PP3V3R1V8_ENET_LR_OUT_REG

BCM57765_MISO

BCM57765_CS_L

BCM57765_SCLK

PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_N

ENET_WAKE_L

PP3V3_ENET

BCM57765_SCLK BCM57765_MISO

BCM57765_CS_L

BCM57765_MOSI

NC_BCM57765_SPD100LED_L NC_BCM57765_TRAFFICLED_L

PCIE_ENET_D2R_C_P

PCIE_ENET_R2D_N

PCIE_ENET_R2D_P

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

ENET_RESET_L ENET_CLKREQ_L ENET_WAKE_R_L

ENET_LOW_PWR

TP_SDCONN_DATA<5>

NC_CE_L_MS_INS_L

TP_SDCONN_WP

TP_ENET_CR_PWREN

BDM57765_SR_DISABLE

SYSCLK_CLK25M_ENET

BCM57765_RDAC

ENET_VMAIN_PRSNT

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

PP3V3_S0

MIN_LINE_WIDTH=0.4 mm

PP1V2_ENET_PHY_GPHYPLL

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V2_ENET_PHY_PCIEPLL

PP1V2_ENET

BCM57765_SMB_CLK BCM57765_SMB_DATA

PCIE_ENET_D2R_C_N

ENET_MDI_N<2>

ENET_MDI_P<2>

ENET_MDI_P<0>

TP_SDCONN_DATA<7>

ENET_MDI_N<3>

ENET_MDI_P<3>

PP1V2_ENET

TP_SDCONN_DATA<0> TP_SDCONN_DATA<1>

TP_SDCONN_DATA<4>

TP_SDCONN_DATA<6>

TP_SDCONN_DATA<3>

TP_SDCONN_DATA<2>

TP_SDCONN_CLK

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP3V3R1V8_ENET_LR_OUT_REG

ENET_MDI_P<1>

ENET_MDI_N<0>

PP3V3_S3_ENET_PHY_AVDDH

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

PP3V3_S3_ENET_PHY_BIASVDDH

MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

PP3V3_S3_ENET_PHY_XTALVDDH

PP3V3_ENET

TP_SDCONN_CMD

TP_SDCONN_DETECT_L

ENET_MEDIA_SENSE

ENET_MDI_N<1>

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V2_ENET_PHY_AVDDL

36 OF 105

39 OF 132

36

71

36

7

25 36 71 73

36

6

95

6

6 7

12 23 25 26 28 32 35 39 40 41 46 48

49 50 51 52 54 57 61 62 72 73 80 83 84

85 88 89 91

100 102

7

36 71

95

7

36 71

36

7

25 36 71 73

BI

RX

TX

BI

RX

TX

BI

IONCNC

IONCIO

IO

NC

GND

IONCNC

IONCIO

IO

NC

GND

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

sides of the board

Signal aliases required by this page:

(NONE)

514-0636

Place one of 0.1uf cap close to each centertap pin of transformer

mirrored on opposite

BOM options provided by this page:

Power aliases required by this page:

Page Notes

Transformers should be

36 96

TLA-6T213HF

SM

CRITICAL

T4000

1

10

11

12

2

3

4

5

6 7

8

9

402

1/16W

5%

MF-LF

75

R4000

1

2

402

1/16W

5%

MF-LF

75

R4001

1

2

402

1/16W

5% MF-LF

75

R4002

1

2

402

1/16W

5% MF-LF

75

R4003

1

2

1000PF

CRITICAL

CERM 1206

2KV

10%

C4008

1 2

36 96

10%

0.1UF

402-1

X5R

16V

C4006

1

2

10% 402-1

X5R

16V

0.1UF

C4004

1

2

10% 402-1

X5R

16V

0.1UF

C4002

1

2

CRITICAL

SM

TLA-6T213HF

T4001

1

10

11

12

2

3

4

5

6 7

8

9

10% 402-1

X5R

16V

0.1UF

C4000

1

2

36 96

F-RT-TH

RJ45-M97-3

CRITICAL

J4000

1

10

11 12

2 3 4 5 6 7 8

9

SLP2510P8

CRITICAL

RCLAMP0524P

PLACE_NEAR=T4001.1:5mm

NOSTUFF

D4001

3

5 4 2 16 7 9

10

SLP2510P8

CRITICAL

RCLAMP0524P

PLACE_NEAR=T4000.5:5mm

NOSTUFF

D4000

3

5 4 2 16 7 9

10

36 96

Ethernet Connector

SYNC_MASTER=K92_ERIC SYNC_DATE=08/24/2010

ENET_MDI_N<2>

ENET_MDI_P<1>

ENET_MDI_P<2>

ENET_MDI_P<0>

ENET_MDI_P<3>

ENET_MDI_N<3> ENETCONN_N<3>

ENETCONN_P<3>

ENETCONN_P<0>

ENETCONN_CTAP

ENET_MDI_N<1>

ENET_CTAP2

ENETCONN_P<1>

ENET_CTAP1

ENET_CTAP0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

ENET_BOB_SMITH_CAP

ENET_CTAP3

ENETCONN_P<2>

ENETCONN_N<1>

ENETCONN_N<2>

ENETCONN_N<0>ENET_MDI_N<0>

40 OF 132 37 OF 105

100

DS2

ATBUSH ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620* JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK SCIFDAIN SCIFDOUT

SCIFMC

SCL SDA

SE SM

TDO

TPA1N

TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P

TPBIAS0 TPBIAS1 TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC NC NC

NC

IN IN

IN

OUT

IN IN IN

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

IN

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

110 mA Digital Core

25 mA PCIe SerDes

NT-9

(IPD) (IPD)

(IPD)

NT-7

NT-12 (IPD)

(IPU)

(IPD) NT-20

(IPD) NT-19

(Reserved)

NT-OUT

NT-14 (IPD)

NT-5

NT-17

NT-16 (IPD)

(OD)

NT-4 (IPU)

17 mA PCIe SerDes

0 mA VReg PWR

114 mA FireWire PHY

7 mA I/O

138 mA

(IPU) NT-8

(IPD) NT-11

NT-15 (IPD)

(IPU)

NOTE: NT-xx notes show NAND tree order.

NT-3 (IPU)

FIXME!!! - TYPO IN SYMBOL REGCTL

NT-13

NT-1 (IPU)

NT-2 (IPU)

NT-6

(IPD) NT-18

(IPD) NT-21

NT-10 (IPD)

135 mA

191

MF-LF

1% 1/16W

402

R4170

1

2

0.33UF

CERM-X5R

6.3V 402

10%

C4162

1

2

470K

5% 1/16W MF-LF

402

R4162

1

2

OMIT

CRITICAL

FW643

BGA

U4100

B13 A13 A11

A10

L13

L2

F12 E12 E13

D12

K13

D1

J2

K1

J12 J13

N8 N7 N5 N6

N4

B11

N9 N10

D13

L8

G2 G1 H1 F2

N12 M11

M13 N13

M4 N2 M1 M3

B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4

B7 C3 A2

B10

N1

E1 D2

H13

A1

B1

M12N3N11

B12

C13E2E10H2H12K2L1

C1

C12F1G12J1L3

L11M2A12D5D6D8L5

L10L6L9

K12

L12

B2

D4

F7

F8

F10

G4G6G7

G8

G10

H4

H6D7H7

H8

H10

J4J5J9

J10

K4K5K7D9K8K9L7

K6

K10

D10

E4E5E9F4F6

C2

G13

F13

22PF

CERM

5%

50V 402

C4151

1 2

50V

22PF

CERM

5%

402

C4150

1 2

200K

MF-LF

1%

1/16W

PLACE_NEAR=U4100.B10:2mm

402

R4160

1

2

412

MF-LF

1%

1/16W

402

R4150

1 2

10K

MF-LF

5% 1/16W

402

R4163

1

2

10K

MF-LF

5% 1/16W

402

R4164

1

2

FW643_LDO

10K

MF-LF

5%

1/16W

402

R4165

1

2

PLACE_NEAR=U1800.BJ36:2.54mm

0.1UF

16V

X5R

402-1

10%

C4176

1 2

PLACE_NEAR=U1800.BG36:2.54mm

0.1UF

16V

X5R

402-1

10%

C4175

1 2

10K

MF-LF

5% 1/16W

402

R4166

1

2

PLACE_NEAR=U1800.AU34:2.54mm

16V

402-1

0.1UF

X5R

10%

C4171

1 2

0.1UF

PLACE_NEAR=U1800.AV34:2.54mm

10% 16V X5R

402-1

C4170

1 2

1UF

CERM

6.3V 402

10%

C4130

1

2

1UF

CERM

6.3V 402

10%

C4131

1

2

1UF

CERM

6.3V 402

10%

C4100

1

2

1UF

CERM

6.3V 402

10%

C4101

1

2

1UF

CERM

6.3V 402

10%

C4132

1

2

1UF

CERM

6.3V 402

10%

C4102

1

2

1UF

10%

6.3V CERM 402

C4103

1

2

1UF

CERM

6.3V 402

10%

C4135

1

2

1UF

CERM

6.3V 402

10%

C4136

1

2

6.3V

1UF

CERM 402

10%

C4104

1

2

1UF

CERM

6.3V 402

10%

C4110

1

2

1UF

CERM

6.3V 402

10%

C4105

1

2

1UF

CERM

6.3V 402

10%

C4106

1

2

1UF

CERM

6.3V 402

10%

C4120

1

2

1UF

CERM

6.3V 402

10%

C4121

1

2

1UF

CERM

6.3V 402

10%

C4122

1

2

1UF

CERM

6.3V 402

10%

C4123

1

2

1UF

CERM

6.3V 402

10%

C4124

1

2

0.1UF

CERM

20% 10V

402

C4141

1

2

1UF

CERM

6.3V 402

10%

C4111

1

2

1UF

CERM

6.3V 402

10%

C4140

1

2

16 95

8

39

2.94K

MF-LF

1%

1/16W

402

R4161

1

2

40

6

40

40 96

6

40

6

40

6

40

6

40

40 96

6

40

6

40

39 40

6

40

120-OHM-0.3A-EMI

0402-LF

L4130

1 2

120-OHM-0.3A-EMI

0402-LF

L4135

1 2

39

120-OHM-0.3A-EMI

0402-LF

L4110

1 2

CRITICAL

SM-3.2X2.5MM

24.576MHZ

Y4150

2 4

1 3

0

1/16W MF-LF

402

5%

R4100

1 2

SYNC_DATE=10/20/2010

SYNC_MASTER=K91_MLB

FireWire LLC/PHY (FW643)

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_R

PP3V3_FW_FWPHY

FW_CLK24P576M_XO_R FW_CLK24P576M_XI

TP_FW643_SE

PCIE_FW_D2R_P

PCIE_FW_D2R_N

PCIE_FW_R2D_C_N

PCIE_FW_R2D_C_P

TP_FW643_VAUX_ENABLE

FW643_TRST_L

FW643_WAKE_L FW643_REGCTL FW643_VAUX_DETECT

PCIE_CLK100M_FW_P

PCIE_FW_D2R_C_P

PP3V3_FW_FWPHY

FW_CLKREQ_PHY_L

TP_FW643_TMS

NC_FW643_TDI

TP_FW643_TCK

PCIE_FW_R2D_P

PCIE_FW_R2D_N

TP_FW643_SCIFCLK

FW643_TPCPS

PP1V0_FW_FWPHY

FW643_R0

NC_FW2_TPBN

FW643_PU_RST_L

TP_FW643_SDA

FW_RESET_L

TP_FW643_SCIFDOUT TP_FW643_SCIFMC

FW_CLK24P576M_XO

PPVP_FW_CPS

TP_FW643_OCR10_CTL

TP_FW643_AVREG

TP_FW643_FW620_L

TP_FW643_SM

TP_FW643_VBUF

FW_PORT1_TPA_P

FW_PORT1_TPA_N

NC_FW2_TPAN NC_FW2_TPAP NC_FW0_TPBN

FW_PORT1_TPB_N FW_PORT1_TPB_P

NC_FW2_TPBP NC_FW0_TPBIAS

NC_FW2_TPBIAS

FW643_REXT

FWPHY_DS2

FWPHY_DS0 FWPHY_DS1

FW_P1_TPBIAS

NC_FW0_TPBP

NC_FW0_TPAP

NC_FW0_TPAN

TP_FW643_NAND_TREE

TP_FW643_TDO

PCIE_FW_D2R_C_N

PCIE_CLK100M_FW_N

TP_FW643_JASI_EN

TP_FW643_CE

TP_FW643_MODE_A

FW643_SCL

TP_FW643_SCIFDAIN

PP1V0_FW_FWPHY_AVDD

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_FW_FWPHY_VDDA

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_FW_FWPHY_VP25

41 OF 132 38 OF 105

7

38 39 40

95

7

38 39 40

6

95

7

39

40

6

95

G

D

S

IN

G

D

S

OUT

IN

S

G

D

(SYM-VER2)

G

S

(SYM-VER1)

D

GND

VOUT

ON

VIN

GND

VOUT

ON

VIN

IN

OUT

IN

OUT

IN

D

G S

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FireWire Port 5K Pull-Down Detect

All FireWire devices require 5K pull-down on TPB pair.

Q4262 provides for fast-off of Q4260 in S0 (Late-VG detection)

Supervisor & CLKREQ# Isolation

Pull-up provided by another page.

3.3V FW Switch

1.0V FW Switch

Part

U4201 & U4202

When PHY is powered, FW_5KPD_DET_L acts as legacy PME# signal.

LSI FireWire PHY requires 1.0V. To avoid an extra power supply,

1.05V is used with a series R

Max Current = 1.7A (85C)

Load Switch

50 mOhm Max

FireWire Port Power Switch

2) FW643 WAKE# (PME#) when PHY is powered.

- =FW_CLKREQ_L

- =FW_PME_L

Pull-up provided on another page.

1) 5K Pull-down Detect when FW_PWR_EN is low.

Host can detect as load on TPBIAS signal. Current source only active when FW_PWR_EN is low.

Power aliases required by this page:

Page Notes

- =PP3V3_S0_FWLATEVG

- =PP1V0_FW_FET_R (1.0V FET Output)

(NONE)

- =PP1V05_S0_FWPWRCTL (5KPD Bias Rail)

- =PP3V3_FW_FWPHY (PHY 3.3V Power)

- =PP3V3_FW_FET (3.3V FET Output)

- =PP1V05_FW_P1V0FWFET (1.0V FET Input)

BOM options provided by this page:

- =PP1V0_FW_FWPHY (PHY 1.0V)

- =PP3V3_S0_FWPWRCTL

Max Output: 2A

R(on)

18 mOhm Typ

TPS22924C

to reduce voltage.

Type

DLY = 60 ms +/- 20%

Dual-purpose output:

- =PP3V3_FW_P3V3FWFET (3.3V FET Input)

- =PPBUS_FW_FET (FW VP FET Output)

- =PPBUS_S5_FWPWRSW (FW VP FET Input)

Signal aliases required by this page:

FireWire PHY WAKE# Support

402

25V X5R

10%

0.1UF

C4260

1

2

1/16W

5%

402

MF-LF

300K

R4260

1

2

1/16W

5%

402

MF-LF

470K

R4261

1

2

1.1A-24V

MINISMDC110H24

CRITICAL

F4260

1 2

CRITICAL

CRS08-1.5A-30V

SM

D4260

1 2

SOT563

BC847CDXV6TXG

CRITICAL

Q4270

2

6

1

SOT563

BC847CDXV6TXG

CRITICAL

Q4270

5

3

4

MF-LF

5%

402

1/16W

330K

R4270

1

2

56K

MF-LF

402

5%

1/16W

R4271

1

2

5% 1/16W MF-LF

402

12K

R4273

1

2

PLACE_NEAR=C4360.1:2 mm

MF-LF

402

5%

1K

1/16W

R4272

1

2

CRITICAL

DMB53D0UV

SOT-563

Q4275

6

2

1

CRITICAL

SOT-563

DMB53D0UV

Q4275

5

3

4

10%

0.1UF

402

X5R

16V

C4270

1

2

38 40

1/16W MF-LF

5%

1K

402

R4275

1

2

19 39

DMB53D0UV

SOT-563

CRITICAL

Q4276

5

3

4

CRITICAL

DMB53D0UV

SOT-563

Q4276

6

2

1

5% 1/16W MF-LF 402

100K

R4276

1

2

NO STUFF

0.1UF

10% 16V X5R 402

C4276

1

2

MF-LF

5%

1/16W

402

10K

R4277

1

2

8

19

8

38 39

CRITICAL

SOT-363

BSS8402DW

Q4262

3

5

4

402

1/16W

5%

MF-LF

10K

R4262

1

2

CRITICAL

BSS8402DW

SOT-363

Q4262

6

2

1

402

25V X5R

10%

0.1UF

NO STUFF

C4261

1

2

10

5% 1/16W MF-LF

402

R4263

1

2

CRITICAL

CSP

TPS22924

U4201

C1

C2

A2 B2

A1 B1

TPS22924

CSP

CRITICAL

U4202

C1

C2

A2 B2

A1 B1

40

402

MF

1/16W

1%

0.549

R4202

1

2

38

1/16W 402

5%

10K

MF-LF

R4283

2

1

19 39

16 23

402

25V X5R

10%

0.1UF

C4290

1

2

18 25 29

38 39

CRITICAL

FDC638P_G

SM

Q4260

1

2

5

6

3

4

CRITICAL

SSM3K15FV

SOD-VESM-HF

Q4261

3

1

2

402

CERM

6.3V

10%

1UF

C4201

1

2

CERM

6.3V

10%

1UF

402

C4202

1

2

TDFN

CRITICAL

SLG4AP016V

U4290

6

5

7

3

8

4

2

9

1

402

5% MF-LF

1/16W

100K

R4290

1

2

SYNC_MASTER=K91_MLB

SYNC_DATE=10/20/2010

FireWire Port & PHY Power

FWPORT_FASTOFF_L_DIV

PLT_RESET_L

FW_PWR_EN

MAKE_BASE=TRUE

FW_CLKREQ_PHY_L

PP1V0_FW_FWPHY

FW_RESET_L

FW_CLKREQ_PHY_L

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

PPBUS_FW_FWPWRSW_D

MIN_LINE_WIDTH=0.5 mm

PP3V3_FW_FWPHY

FWPORT_PWREN_L

PP3V3_S0

FWPORT_FASTOFF_L

MIN_NECK_WIDTH=0.25 mm

PPBUS_FW_FWPWRSW_F

MIN_LINE_WIDTH=0.5 mm VOLTAGE=12.6V

FW643_WAKE_L

FW_PLUG_DET_L

FW_PWR_EN

FW_P1_TPBIAS

FW_WAKE

PP3V3_FW_FWPHY

PP1V05_S0

FW_P1_TPBIAS_R

FWDET_EMIT

FWDET_MIRROR

MAKE_BASE=TRUE

FW643_WAKE_L

PPVP_FW

PP1V0_FW_FWPHY

PP3V3_S0

MAKE_BASE=TRUE

FW_5KPD_DET_L

FW_5KPD_DET_RC

FW_PWR_EN_L

FWPORT_PWR_EN

FW_RESET_R_L

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V

PP1V05_FW_FET

PP1V05_S0

FW_CLKREQ_L

PP3V3_S0

PP3V3_FW_FWPHY

FWPORT_PWREN_L_DIV

PPBUS_G3H

42 OF 132 39 OF 105

38 39

7

38 39

7

38 39 40

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

7

38 39 40

7 9

10 12 13 14 23 35

39 45 68 70 73

102 104

105

6 7

40

7

38 39

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

7 9

10 12 13 14 23 35 39 45 68 70 73

102 104 105

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

7

38 39 40

6 7 8

35 49 50 63 64 90

SC/NC

TPA+

TPA(R)

VG

VPTPB+

TPB(R)

TPB-

TPA-

CHASSIS

GND

SGD

(SYM-VER2)

G

S

(SYM-VER1)

D

NC

VCC

VCLMP

D1-

GND

D2-

D2+

D1+

FWPWR_EN

OUT

BI

IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

- =PPVP_FW_PHY_CPS_FET (From Port)

- =PPVP_FW_PHY_CPS (To PHY)

- =PP3V3_FW_FWPHY

- =PP3V3_S0_FWLATEVG

NOTE: This page is expected to contain

Power aliases required by this page:

Page Notes

FW643 has internal leakage path from TPCPS pin to VDD33.

FireWire PHY Config Straps

Configures PHY for:

- Port "1" Bilingual (1394B)

(All unused port signals TP/NC)

- =PPVP_FW_PORT1

To FW643

From Port

- =FW_PHY_DS0

- =FW_PHY_DS1

- =FW_PHY_DS2

BOM options provided by this page: (NONE)

Disabled per LSI instructions

Unused FireWire Ports

Signal aliases required by this page:

FireWire TPA/TPB pairs to their appropriate connectors and/or to

FireWire Design Guide (FWDG 0.6, 5/14/03)

FET blocks current to TPCPS until VDD33 is powered.

FW643 TPCPS Leakage Protection

Place close to FireWire PHY

Termination

(FW_PORT1_TPB_N)

(GND)

(FW_PORT1_TPA_N)

AREF needs to be isolated from all

beta-only device, there is no DC path

BREF should be hard-connected to logic

Note: Trace PPVP_FW_PORT1 must handle up to 5A

(FW_PORT1_TPB_N)

local grounds per 1394b spec

ground for speed signaling and connection

between them (to avoid ground offset issue)

When a bilingual device is connected to a

(FW_PORT1_BREF)

514S0605

TPA<R> TPA+

TPA-

VG

BILINGUAL

TPB+ VP

NC

TPB<R>

TPB-

INPUT

OUTPUT

PORT 1

(FW_PORT1_TPB_P)

Cable Power

"Snapback" & "Late VG" Protection

(FW_PORT1_TPA_P)

(FW_PORT1_TPA_N)

(FW_PORT1_TPB_P)

(FW_PORT1_TPA_P)

1394b implementation based on Apple

properly terminate unused signals.

the necessary aliases to map the

1/16W

1%

402

MF-LF

56.2

SIGNAL_MODEL=EMPTY

R4363

1

2

1/16W

1%

402

MF-LF

4.99K

R4364

1

2

SIGNAL_MODEL=EMPTY

56.2

MF-LF 402

1% 1/16W

R4362

1

2

220pF

CERM 402

5% 25V

C4364

1

2

56.2

MF-LF

402

1%

1/16W

SIGNAL_MODEL=EMPTY

R4361

1

2

0.33UF

CERM-X5R 402

10%

6.3V

C4360

1

2

1/16W

1%

402

MF-LF

56.2

SIGNAL_MODEL=EMPTY

R4360

1

2

PLACE_NEAR=J4310.5:2 mm

50V

10% X7R

603-1

0.1uF

C4319

1

2

1/16W

5%

402

1M

PLACE_NOTE=J4310.5:2 mm

MF-LF

R4319

1

2

50V

10% 402

0.01UF

X7R

C4314

1

2

CRITICAL

FERR-250-OHM

SM

L4310

1 2

F-RT-TH

CRITICAL

1394B-M97

J4310

1

10 11 12 13

2

3

4

5

6

7

8

9

10K

MF-LF 402

1% 1/16W

R4381

1

2

1/16W

1%

402

MF-LF

10K

R4382

1

2

10K

MF-LF 402

1% 1/16W

R4380

1

2

SOT-363

BSS8402DW

Q4300

3

5

4

CRITICAL

BSS8402DW

SOT-363

Q4300

6

2

1

1/16W

5%

402

MF-LF

330K

R4312

1

2

1/16W

5%

402

MF-LF

470K

R4311

1

2

TPD4S1394

CRITICAL

LLP

U4350

7

8

5

6

4

2

1

3

PLACE_NEAR=U4350.1:2 mm

0.1UF

402

X5R

16V

10%

C4350

1

2

MF-LF

402

1/16W

5%

100K

R4350

1

2

39

38 40

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

38 40 96

38 39

SYNC_DATE=07/22/2010

FireWire Connector

SYNC_MASTER=K91_MLB

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

FW_PORT1_AREF

MIN_LINE_WIDTH=0.5 mm VOLTAGE=33V

PPVP_FW_PORT1_F

MIN_NECK_WIDTH=0.25 mm

PPVP_FW

PP3V3_S0

FWPORT_PWR_EN

TP_FWLATEVG_VCLMP

FW_P1_TPBIAS

FW_PORT1_TPA_N FW_PORT1_TPB_P

FW_PORT1_TPB_C

FW_PORT1_TPA_P

FW_PORT1_TPB_N

PPVP_FW_CPS

MAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_FW_FWPHY

CPS_EN_L

NC_FW2_TPAN NC_FW2_TPBP NC_FW2_TPBN

NC_FW0_TPBN

NC_FW2_TPAP

NC_FW2_TPBIAS

NC_FW0_TPAP NC_FW0_TPAN NC_FW0_TPBP

NC_FW0_TPBIAS

MAKE_BASE=TRUE

NC_FW2_TPBN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW2_TPBP

NO_TEST=TRUE

NC_FW2_TPAN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW2_TPBIAS

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW0_TPBN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FW0_TPBP

NO_TEST=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW0_TPAP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FW0_TPBIAS

MAKE_BASE=TRUE

FWPHY_DS1

MAKE_BASE=TRUE

FWPHY_DS1

FWPHY_DS2

FWPHY_DS0

FWPHY_DS2

MAKE_BASE=TRUE

FWPHY_DS0

MAKE_BASE=TRUE

PP3V3_FW_FWPHY

PPVP_FW

CPS_EN_L_DIV

43 OF 132 40 OF 105

38

40 96

38

40 96

38

40 96

38

40 96

6 7

39 40

6 7

12 23 25 26 28 32 35

36 39 41 46 48 49 50 51 52 54

57 61 62 72 73 80 83 84 85 88

89 91

100 102

38 40

7

38 39 40

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

6

38 40

38

40

38 40

7

38 39 40

6 7

39 40

OUT OUT

OUT

SYM_VER-1

IN

OUT

S

G

D

SYM_VER-1

IN

EN

A_INN

A_INP

TEST

B_PRE0/I2C_ADDR0

APRE0/I2C_ADDR1

I2C_EN*

A_OUTP

B_INN

A_OUTN

B_INP

REXT

B_PRE1/SDA_CTL

A_PRE1/SCL_CTL

VDD

THRM

GND

B_OUTP

B_OUTN

PAD

BI

IN

OUT

NC

SYM_VER-1

D

SG

D

SG

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

R2D values for 3dB de-emphasis

D2R values for 3dB de-emphasis

Indicates disc presence

0x96/0x97 0x98/0x99

0xB8/0xB9

0xB6/0xB7

H

Address (R/W)

H

H L

L

Write:0xB6 Read:0xB7

Internally PD ~150K

516S0617

338S0907

ODD Power Control

516S0350

SATA HDD Port

SATA ODD Port

ADDR1 ADDR0

ensure the drive is unpowered in S3/S5.

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

0.01UF

GND_VOID=TRUE

16V10% 402

CERM

C4516

1 2

0.01UF

GND_VOID=TRUE

16V10% 402

CERM

C4515

1 2

GND_VOID=TRUE

10%

CERM

402

0.01UF

16V

C4511

1 2

0.01UF

16V 402

CERM

10%

GND_VOID=TRUE

C4510

1 2

0.005

MF

1W

1%

0612

CRITICAL

R4599

1 2 3 4

100 103

MF

1% 1W

0.005

CRITICAL

0612

R4598

123

4

100 103

40210%

CERM

16V

0.01UF

C4526

1 2

16V

CERM

0.01UF

10% 402

C4525

1 2

CRITICAL

90-OHM-100MA

DLP11S

PLACE_NEAR=J4500.11:4mm

FL4525

1 2

34

16 94

6

45

MF-LF

1/16W

5%

33K

402

R4590

1

2

CRITICAL

TPCP8102

23V1K-SM

Q4590

5 6 7 8

4

1 2 3

M-ST-SM-LF

55560-0168

CRITICAL

J4500

1

10

1112

1314

1516

2

34

56

78

9

TCM0806-4SM

12-OHM-100MA-8.5GHZ

CRITICAL

FL4501

1

2 3

4

16 23

0

5% 1/16W MF-LF 402

R4511

1

2

NO STUFF

4.7K

402

5% 1/16W MF-LF

R4510

1

2

19

402

MF-LF

4.99K

1%

1/16W

R4512

1

2

GND_VOID=TRUE

402

0.01UF

16V10%

CERM

C4512

1 2

GND_VOID=TRUE

0.01UF

40216V10%

CERM

C4513

1 2

GND_VOID=TRUE

0.01UF

402

CERM

10% 16V

C4517

1 2

GND_VOID=TRUE

10% 402

CERM

16V

0.01UF

C4518

1 2

PS8521A

TQFN

CRITICAL

U4510

2

1

14

15

19

9

12 11

4 5

8

17

7

3

13

10

20

18

21

6

16

402

20% CERM

PLACE_NEAR=U4510.6:2mm

16V

0.01UF

C4519

1

2

402

1/16W MF-LF

5%

4.7K

R4513

1

2

NO STUFF

5% 1/16W MF-LF

402

4.7K

R4515

1

2

6

16 23 26 28 30 32 48 62 89 95

6

16 23 26 28 30 32 48 62 89 95

6

16 94

6

16 94

6

16 94

6

16 94

402

20% 10V CERM

0.1UF

PLACE_NEAR=U4510.16:2mm

C4514

1

2

402

CERM

50V

5%

C4533

15PF

GND_VOID=TRUE

402

MF-LF

1/16W

1%

R4533

41.2

GND_VOID=TRUE

MF-LF

402

R4534

1/16W

1%

41.2

GND_VOID=TRUE

402

MF-LF

R4535

1/16W

1%

41.2

GND_VOID=TRUE

402

MF-LF

R4536

GND_VOID=TRUE

41.2

1%

1/16W

C4534

402

CERM

50V

5%

15PF

GND_VOID=TRUE

C4535

402

CERM

50V

5%

15PF

GND_VOID=TRUE

C4536

GND_VOID=TRUE

15PF

5%

50V

CERM

402

PLACE_NEAR=J4500.5:4mm

DLP11S

90-OHM-100MA

CRITICAL

FL4520

12

3 4

SSM6N15FEAPE

SOT563

Q4596

3

5

4

1/16W

100K

5%

402

MF-LF

R4597

1

2

CRITICAL

SOT563

SSM6N15FEAPE

Q4596

6

2

1

5%

1/16W

100K

402

MF-LF

R4596

1

2

100K

MF-LF

1/16W

5%

402

R4595

1 2

10%

402

CERM

10V

0.068UF

C4595

1

2

16V

10%

CERM

402

0.01UF

C4596

1 2

16V10%

0.01UF

402

CERM

C4521

1 2

10%

0.01UF

CERM

16V 402

C4520

1 2

CRITICAL

FERR-70-OHM-4A

0603

PLACE_NEAR=J4501.1:3mm

L4500

1 2

CERM

0.1UF

PLACE_NEAR=L4500.1:3mm

20% 10V

402

C4501

1

2

402

CERM

PLACE_NEAR=L4500.2:3mm

20%

0.1UF

10V

C4502

1

2

M-ST-SM

QT500166-L020

CRITICAL

J4501

1

10 11 12 13 14 15 16

2

3 4 5 6 7 8 9

SYNC_MASTER=K92_ERIC

SATA Connectors

SYNC_DATE=11/08/2010

PP5V_S0_HDD_FLT MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm VOLTAGE=5V

PP5V_SW_ODD

SATA_HDD_R2D_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_HDD_R2D_RDRVR_OUT_N

PP1V5_S0

SATARDRVR_I2C_ADDR1

SATA_ODD_R2D_UF_N

SATA_ODD_R2D_UF_P

SMBUS_PCH_CLK

SATA_HDD_R2D_C_N

SATA_HDD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_D2R_P

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

PP5V_SW_ODD_R

PP3V3_S0

ISNS_ODD_N

ISNS_ODD_P

ODD_PWR_EN

ODD_PWR_EN_L

SATARDRVR_I2C_ADDR1

SATARDRVR_I2C_EN_L

PP1V5_S0

SATA_HDD_D2R_RDRVR_OUT_N

SATA_HDD_D2R_RDRVR_OUT_P

SATA_HDD_R2D_RDRVR_IN_N

SATA_HDD_R2D_RDRVR_IN_P

PP1V5_S0

ODD_PWR_EN_LS5V_L

ODD_PWR_SS

PP5V_S0

SATA_ODD_R2D_P SATA_ODD_R2D_N

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_C_P

PP3V3_S0

SATARDRVR_I2C_ADDR0

SATA_ODD_D2R_UF_N

SMC_ODD_DETECT

SATARDRVR_REXT

SATA_ODD_D2R_C_N

SATA_ODD_R2D_C_P

SATARDRVR_EN

SATARDRVR_I2C_ADDR0

SATA_ODD_D2R_N

SATA_HDD_R2D_RDRVR_OUT_P

SATA_HDD_D2R_RDRVR_IN_P

SATA_HDD_D2R_RDRVR_IN_N

SATA_HDD_R2D_N

ISNS_HDD_P

PP5V_S0

SMBUS_PCH_DATA

SATARDRVR_TEST

MIN_LINE_WIDTH=0.6mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

PP5V_S0_HDD_R

ISNS_HDD_N

SATA_HDD_R2D_UF_P

SATA_HDD_R2D_RC_UF_P

SATA_HDD_R2D_RC_UF_N

SATA_HDD_R2D_UF_N

SATA_HDD_D2R_C_N

SATA_HDD_D2R_RC_C_N

SATA_HDD_D2R_C_P

SATA_HDD_D2R_RC_C_P

45 OF 132 41 OF 105

6

104

6

94

6

94

7

16 20 22 25 32 41 57 71

41

94

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

41

7

16 20 22 25 32 41 57 71

6

94

6

94

6

94

6

94

7

16 20 22 25 32 41 57 71

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104 105

6

94

6

94

6

94

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

41

6

94

41

6 94

6

94

6

94

6

94

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104

105

6

94

6

94

6

94

6

94

OUT

BI

SYM_VER-1

IN

OUT

IN

SYM_VER-1

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

GND

THRM

OUT2

OUT1

ILIM

IN_0 IN_1

EN2

FAULT1* FAULT2*

EN1

PAD

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current limit per port (R4600): 2.18A min / 2.63A max

USB/SMC Debug Mux

We can add protection to 5V if we want, but leaving NC for now

Place L4605 and L4615 at connector pin

Left USB Port A

Left USB Port B

SEL=1 Choose USB

SEL=0 Choose SMC

USB Port Power Switch

0603

FERR-120-OHM-3A

CRITICAL

L4605

1 2

CRITICAL

NOSTUFF

CASE-B2-SM

POLY-TANT

6.3V

20%

100UF

C4696

1

2

603

20% X5R

6.3V

10UF

C4695

1

2

402

CERM

10V

20%

0.1UF

C4691

1

2

24

24 94

20%

SMC_DEBUG_YES

0.1UF

10V 402

CERM

C4650

1

2

1/16W 402

10K

5% MF-LF

SMC_DEBUG_YES

R4650

1

2

90-OHM-100MA

DLP11S

CRITICAL

L4600

1 2

34

6

45 46 47

6

45 46 47

45

402

5%

0

MF-LF

1/16W

SMC_DEBUG_NO

R4651

1 2

MF-LF

1/16W

5%

402

0

SMC_DEBUG_NO

R4652

1 2

20%

0.01uF

402

16V

CERM

C4605

1

2

402

CERM

16V

0.01uF

20%

C4615

1

2

0603

FERR-120-OHM-3A

CRITICAL

L4615

1 2

DLP11S

90-OHM-100MA

CRITICAL

L4610

1 2

34

6.3V X5R

10UF

603

20%

C4617

1

2

CRITICAL

6.3V POLY-TANT CASE-B2-SM

220UF-35MOHM

20%

C4616

24 94

24

SLP1210N6

CRITICAL

RCLAMP0502N

D4600

1

5 42 3

6

CRITICAL

RCLAMP0502N

SLP1210N6

D4610

1

5 42 3

6

603

10UF

X5R

20%

6.3V

C4690

1

2

USB

CRITICAL

F-RT-TH-M97-4

J4600

1 2 3 4

5 6

7 8

USB

CRITICAL

F-RT-TH-M97-4

J4610

1 2 3 4

5 6

7 8

CRITICAL

TPS2561DR

SON

U4600

4 5

10

6

1

7

2 3

9 8

11

5%

5.1K

1/16W

402

MF-LF

R4690

1

2

402

X5R

10% 10V

0.47UF

C4692

1

2

PI3USB102ZLE

CRITICAL

TQFN

SMC_DEBUG_YES

U4650

6

7

3

4

5

8

10

9

2

1

23.2K

1% 1/16W MF-LF

402

R4600

1

2

SYNC_MASTER=K92_ERIC

External USB Connectors

SYNC_DATE=08/24/2010

USB_EXTB_OC_L

USB_PWR_EN

USB_ILIM

PM_SLP_S4_L

USB2_EXTA_MUXED_N

USB_DEBUGPRT_EN_L

SMC_TX_L

SMC_RX_L

PP3V42_G3H

USB_EXTB_N

USB_EXTB_P

USB_EXTA_N

USB_EXTA_P

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm

PP5V_S3_RTUSB_A_F

USB2_LT1_N USB2_LT1_P

USB_LT2_N

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

USB_LT2_P

PP5V_S3_RTUSB_B_F

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

USB2_EXTA_MUXED_P

USB_EXTA_OC_L

PP5V_S3_RTUSB_A_ILIM

VOLTAGE=5V

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

46 OF 132 42 OF 105

43

17 29 45 66 73

100

6 7

25 44 45 46

47 48 53 63 64 73

104

100

6 7

29 31 43 44 46 67 72 82

104

OUT

BI

SYM_VER-1

BI

IOIONC

GND

VBUS

NC

FAULT*

IN_1

IN_0

ILIM

OUT1

OUT2

EN

GND

THRM

PAD

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LEFT USB PORT C

Current limit (R4700): 2.19A min / 2.76A max

USB Port Power Switch

10UF

X5R

20%

603

6.3V

C4780

1

2

CERM

0.1UF

402

10V

20%

C4781

1

2

8

24

10UF

X5R 603

20%

6.3V

C4785

1

2

100UF

6.3V

20%

POLY-TANT

CASE-B2-SM

CRITICAL

C4786

1

2

24 94

PLACE_NEAR=J4720.2:8mm

DLP11S

90-OHM-100MA

CRITICAL

L4720

1 2

34

20%

0.01uF

CERM

402

16V

C4725

1

2

24 94

CRITICAL

0603

FERR-120-OHM-3A

PLACE_NEAR=J4720.1:8mm

L4725

1 2

CRITICAL

RCLAMP0502N

SLP1210N6

D4720

1

5 42 3

6

CRITICAL

TPS2557DRB

SON

U4780

4

8

1

5

2 3

6 7

9

F-RT-TH-M97-4

USB

CRITICAL

J4720

1

2

3

4

5

6

7

8

1% 1/16W MF-LF

402

44.2K

R4700

1

2

42

PROJECT SPECIFIC CONNS

SYNC_MASTER=K92_ERIC SYNC_DATE=07/22/2010

USB_ILIM2

USB_EXTC_OC_L

USB_PWR_EN

PP5V_S3

PP5V_S3_RTUSB_C_ILIM

VOLTAGE=5V

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm MIN_LINE_WIDTH=0.5 mm

VOLTAGE=5V

MIN_NECK_WIDTH=0.375 mm

PP5V_S3_RTUSB_C_F

USB_EXTC_N

USB_LT3_N

USB_LT3_P

USB_EXTC_P

47 OF 132 43 OF 105

6 7

29 31 42 44 46 67 72 82

104

100

BI BI

VCC

P1.0/D+ P1.1/DP1.2/VREG P1.3/SSEL P1.4/SCLK

P1.5/SMOSI

P1.6/SMISO

P0.0

P0.1 INT0/P0.2 INT1/P0.3

TIO1/P0.6

NC

TIO0/P0.5

INT2/P0.4

VSSPAD

THRML

IN

NC NC NC NC

NC NC NC NC NC NC NC NC

NC NC NC NC NC

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

24 94

X5R

10V

10%

1UF

402-1

C4803

1

2

CY7C63803-LQXC

OMIT

CRITICAL

QFN

U4800

5 4 3

8

9 10 20 21 22 23 24

7 6

12 13 15 16 17 18 19

25

2 1

14

11

X7R-CERM

10% 16V

402

0.1UF

C4801

1

2

10%

402

50V

0.001UF

CERM

C4804

1

2

MF-LF

5%

100

1/16W

402

R4800

1 2

6

44

FF18-6A-R11AD-B-3H

CRITICAL

F-RT-SM

J4800

1 2 3 4 5 6

PLACE_NEAR=J4800.1:5mm

10%

X7R-CERM

0.1UF

402

16V

C4805

1

2

PLACE_NEAR=J4800.2:5mm

X7R-CERM

10% 16V

0.1UF

402

C4806

1

2

PLACE_NEAR=J4800.4:5mm

10% 50V

0.001UF

CERM 402

C4807

1

2

PLACE_NEAR=J4800.1:5mm

5%

10

402

1/16W

MF-LF

R4805

1 2

PLACE_NEAR=J4800.2:5mm

MF-LF

1/16W

402

5%

10

R4806

1 2

PLACE_NEAR=J4800.5:5mm

10% 50V

0.001UF

CERM 402

C4808

1

2

PLACE_NEAR=J4800.4:5mm

402

MF-LF

1/16W

100

5%

R4807

1 2

PLACE_NEAR=J4800.5:5mm

4.7

402

MF-LF

1/16W

5%

R4808

1 2

SHORT

NONE NONE

NONE

402

OMIT

R4801

1 2

SYNC_MASTER=K17_MLB

SYNC_DATE=04/26/2010

Front Flex Support

VOLTAGE=5V

PP5V_S3_IR_USB

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.2 mm

PP5V_S3

SMC_LID

SMC_LID_R

SYS_LED_ANODE

SYS_LED_ANODE_R

PP3V42_G3H

IR_RX_OUT

PP5V_S3

IR_VREF_FILTER

IR_RX_OUT

IR_RX_OUT_RC

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PP5V_S3_IR_R

PP3V42_G3H_LIDSWITCH_R

VOLTAGE=3.42V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_P USB_IR_N

DIFFERENTIAL_PAIR=USB2_IR

48 OF 132

P/N 338S0633

518S0692

44 OF 105

6 7

29 31 42 43 44 46 67 72 82

104

45 46 53

6

46

6

6 7

25 42 45 46 47 48 53 63 64 73

104

6

44

6 7

29 31 42 43 44 46 67 72 82

104

6

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT IN

OUT

BI

IN

OUT

BI OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

IN

OUT

P11

P82 P83

P35

P96

P95

P94

P93

P92

P91

P90

P86

P85

P84

P81

P80

P77

P67

P52

P51

P50

P47

P46

P45

P44

P43

P42

P41

P40

P37

P36

P34

P33

P32

P31

P30

P27

P26

P25

P24

P23

P21

P17

P12

P66P16

P15

P14

P13

P22

P20

P63

P61

P60

P65

P64

P62

P70 P71 P72 P73 P74 P75 P76

P97

P10

(1 OF 3)

PEVREF/PH4

PECI/PH3

PH2

PG5

PG4

PG3

PG2

PG1

PG0

PF7

PF6

PF5

PF4

PF3

PF2

PF1

PF0

PE4

PE3

PE2

PE1

PE0

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PA7

PA6

PA3

PA2

PA1

PA0

PA4 PA5

PG6 PG7

PH0 PH1

PEVSTP/PH5

(2 OF 3)

EXTAL

XTAL

RES*

VSS

AVSS

ETRST*

NMI

MD2

MD1

NC

AVCC

VCC

VCL

AVREF

(3 OF 3)

NC

INBI

OUT

IN

OUT

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NOTE: Unused pins have "SMC_Pxx" names. Unused pins designed as outputs can be left floating, those designated as inputs require pull-ups.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

(OC)

(OC) (OC)

(OC)

If SMS interrupt is not used, pull up to SMC rail.

6.3V

20% 805

CERM

22UF

C4902

1

2

6

17 47

6

46 47 64

6

46 53

402

PLACE_NEAR=U4900.E1:3mm

6.3V

10%

CERM-X5R

0.47UF

C4907

1

2

402

0.1UF

CERM

10V

20%

C4903

1

2

402

PLACE_NEAR=U4900.M12:3mm

0.1UF

CERM

20% 10V

C4920

1

2

5%

402

1/16W MF-LF

PLACE_NEAR=U4900.M12:3mm

4.7

R4999

1 2

402

10V

20% CERM

0.1UF

C4904

1

2

SM

PLACE_NEAR=U4900.L3:4mm

XW4900

12

17 23

35 91

402

10V

20% CERM

0.1UF

C4905

1

2

17

66 73

23 73 88 91

46

402

10V

20% CERM

0.1UF

C4906

1

2

46 49

46 50

46 49

46 50

46 49

46 49 63 64

6

42 45 46 47

6

42 45 46 47

66 73

48 98

103 104

5%

10K

201

1/20W

MF

R4909

1

2

6

47

6

47

5%

10K

201

1/20W MF

R4901

1

2

5%

10K

201

1/20W MF

R4902

1

2

5%

10K

201

1/20W MF

R4998

1

2

42

63

46 73

6

41

46

52

6

46

6

46

6

46

6

46

52

46 49

46 50

6

46 47

46

6

46 47

6

46 47

6

46 47

44 46 53

6

48 63 64 98

6

48 63 64 98

6

31 48 54 55 98

6

31 48 54 55 98

48 51 98

46

46 49

6

42 45 46 47

6

42 45 46 47

46 55

80

6

16 47

26 28

6

17 25

6

47

16 19

6

17 47

80

17 46 73

6

46 63

46

OMIT

DF2117RVPLP20HV

TLP-145V

U4900

B12 A13 A12 B13 D11 C13 C12 D10

D13 E11 D12 F11 E13 E12 F13 E10

A9 D9 C8 B7 A8 D8 D7 D6

D4 A5 B4 A1 C2 B2 C1 C3

G2 F3 E4

L13 K12 K11 J12 K13 J10 J11 H12

N10 M11 L10 N11 N12 M13 N13 L12

A7 B6 C7 D5 A6 B5 C6

J4 G3 H2 G1 H4 G4 F4 F1

OMIT

TLP-145V

DF2117RVPLP20HV

U4900

N3 N1 M3 M2 N2 L1 K3 L2

B8 C9

B9 A10 C10 B10 C11 A11

G11 G13 F12 H13 G10 G12 H11 J13

M10

N9 K10

L8

M9

N8

K9

L7

K1 J3 K2 J1 K4

A4 B3 C4

K5

N5 M6 L5 M5 N4 L4 M4

M8 N7 K8 K7 K6 N6 M7 L6

E2 F2 J2

TLP-145V

DF2117RVPLP20HV

OMIT

U4900

M12

L11

L9

H3

A2

D1 H1

E5

E3

D3

B1M1H10

E1

D2

L3

F10

B11

C5

A3

46

6

31 46

5%

402

1/16W MF-LF

43

R4910

1 2

5%

402

1/16W MF-LF

0

R4911

1 2

5%

402

1/16W MF-LF

0

R4912

1 2

402

10V

CERM

0.1UF

20%

C4910

1

2

46 73 86

46 53

19 46

6

16 47 88 95

6

16 47 88 95

6

16 47 88 95

6

16 47 88 95

6

16 47 88 95

25

25 95

54

6

31 48 51 80 98

6

17 29 73

17 29 42 66 73

17 73

46

6

31 48 51 80 98

48 98

103 104

46

SMC

SYNC_MASTER=K91_BEN

SYNC_DATE=07/12/2010

PM_SLP_S3_L

SMC_ADAPTER_EN

SMC_BIL_BUTTON_L

SMC_TDO

SMC_LID

TP_SMC_PF5

SMBUS_SMC_BSA_SCL

CPU_PECI_R

S5_PWRGD

LPC_AD<0> LPC_AD<1>

LPC_FRAME_L

SMC_TX_L SMC_RX_L SMBUS_SMC_0_S0_SCL

SMC_GFX_OVERTEMP_L

SMC_FAN_0_TACH

SMC_GPU_VSENSE

SMC_CPU_VSENSE

SMC_GFX_ISENSE

SMC_GFX_VSENSE

SMC_TMS

PM_DSW_PWRGD

ALL_SYS_PWRGD

TP_SMC_P10

SMC_CPUVCCIO_ISENSE

SMC_P1V5S3_ISENSE

SMC_PM_G2_EN

SMBUS_SMC_B_S0_SCL

SMC_TDI

MIN_LINE_WIDTH=0.25 MM VOLTAGE=3.3V

PP3V3_S5_SMC_AVCC

MIN_NECK_WIDTH=0.1 MM

SMC_PROCHOT_3_3_L

SMC_GPU_ISENSE

SMC_CASE_OPEN SMC_TCK

G3_POWERON_L

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SDA

SMC_PROCHOT SMC_THRMTRIP

PM_PECI_PWRGD_R

SMC_CPU_HI_ISENSE

SMC_BMON_ISENSE

SMC_DCIN_ISENSE

SMC_SYS_KBDLED

SMC_GFX_THROTTLE_L

SMBUS_SMC_MGMT_SDA

LPC_AD<3>

TP_SMC_P41

SMC_EXTAL

SMC_XTAL

SMC_RESET_L

GND_SMC_AVSS

SMC_TRST_L

SMC_NMI

SMC_KBC_MDE

SMC_MD1

PP3V42_G3H

SMC_VCL

PP3V3_S5_AVREF_SMC

CPU_PECI

SMC_OTHER_HI_ISENSE

SMC_CPU_ISENSE

SMC_SYS_LED

SMBUS_SMC_A_S3_SCL

PVCCIO_S0_SMC_R

SMC_GPU_HI_ISENSE

SMC_DCIN_VSENSE

SMBUS_SMC_BSA_SDA

SMS_INT_L

PM_PECI_PWRGD

PP1V05_S0

SMC_DP_HPD_L

SYS_ONEWIRE

SMBUS_SMC_0_S0_SDA

SMC_CLK32K

SMBUS_SMC_MGMT_SCL

SMC_RX_L

SMC_TX_L

PM_CLKRUN_L

SMC_SCI_L

LPC_PWRDWN_L

SMC_LRESET_L LPC_CLK33M_SMC LPC_SERIRQ

PM_SLP_S5_L

PM_SLP_S4_L

SMC_PME_S4_WAKE_L

SMC_BC_ACOK

SMC_ONOFF_L

WIFI_EVENT_L

SMC_FAN_1_TACH NC_SMC_FAN_2_TACH NC_SMC_FAN_3_TACH

NC_SMC_FAN_3_CTL

NC_SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_BATLOW_L

PM_SYSRST_L

TP_SMC_RSTGATE_L

LPC_AD<2>

SMC_BMON_MUX_SEL

SMC_DELAYED_PWRGD PM_PWRBTN_L

TP_SMC_P20

TP_SMC_P24

SMC_PB4

SMC_S4_WAKESRC_EN

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

MEM_EVENT_L

USB_DEBUGPRT_EN_L

TP_SPI_DESCRIPTOR_OVERRIDE_L

SMC_PA0_PU

SMC_SA_ISENSE

SMC_PBUS_VSENSE

TP_SMC_P43

49 OF 132 45 OF 105

46

46 49 50

6 7

25 42 44 46 47 48 53 63 64 73

104

6

46

10 19 92

73

7 9

10 12 13 14 23 35 39 68 70 73

102 104

105

46 50

46

D

S G

IN

OUT

BI

IN

D

S G

IN

E

Q2

C

BD

Q1

GS

OUT

G

D

S

OUT

IN

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

OUT

IN

OUT

IN

OUT

D

G S

IN

OUT

IN

D

GS

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SMC Crystal Circuit

BATLOW# Isolation

(IPU)

MR1* and MR2* must both be low to cause manual reset.

Mobiles: 3.42V

(IPU)

System (Sleep) LED Circuit

TO SMC

SMC FSB to 3.3V Level Shifting

TO CPU

Desktops: 5V

Debug Power "Buttons"

NOTE: Internal pull-ups are to VIN, not V+.

Internal 20K pull-up on PM_BATLOW_L in PCH.

Used on mobiles to support SMC reset via keyboard.

SMC Reset "Button", Supervisor & AVREF Supply

4

5

3

Q5059

SOT563

SSM6N15FEAPE

CRITICAL

21

R5070

MF

1/20W

201

10K

5%

21

R5071

1/20W

201

100K

5% MF

21

R5073

1/20W

201

10K

5% MF

21

R5074

MF

1/20W

201

100K

5%

21

R5077

MF

1/20W

2015%

10K

21

R5078

MF 201

1/20W

5%

10K

21

R5079

MF 201

10K

5%

1/20W

21

R5080

MF

1/20W

201

10K

5%

21

R5085

MF

1/20W

2015%

10K

21

R5086

MF

1/20W

2015%

10K

21

R5088

MF5%

1/20W

201

10K

45

19

2

1

R5015

1/10W

0

OMIT

603

MF-LF

5%

PLACE_SIDE=TOP

SILK_PART=PWR_BTN

21

R5062

3.3K

MF-LF

1/16W

402

5%

10 68 92

45

1

2

6

Q5059

SOT563

SSM6N15FEAPE

CRITICAL

21

R5091

100K

5%

1/20W

201MF

21

R5089

1/20W

201MF5%

10K

21

R5081

MF

1/20W

201

10K

5%

21

R5010

0

MF-LF

1/16W

402

5%

2

1

Y5010

5X3.2-SM

20.00MHZ

CRITICAL

21

C5011

50V

CERM

15pF

402

5%

21

C5010

15pF

CERM

50V 402

5%

21

R5087

470K

MF

1/20W

2015%

21

R5093

NOSTUFF

MF

1/20W

2015%

10K

21

R5072

MF

1/20W

201

10K

5%

45

2

1

R5032

1%

1.47K

MF-LF

1/16W

402

2

1

R5031

1%

523

MF-LF

1/16W

402

2

1

R5030

1%

20

MF-LF

1/16W 402

1 2463

5

Q5030

SOT-563

DMB54D0UV

CRITICAL

6

44

4

3

5

Q5060

DMB53D0UV

SOT-563

CRITICAL

2

1

R5061

100K

MF-LF

1/16W 402

5%

1

2

6

Q5060

DMB53D0UV

SOT-563

CRITICAL

2

1

R5060

10K

MF-LF

1/16W 402

5%

45

SILK_PART=PWR_BTN

2

1

R5016

OMIT

603

1/10W

0

PLACE_SIDE=BOTTOM

MF-LF

5%

2

1

R5001

1/10W 603

0

MF-LF

5%

PLACEMENT_NOTE=Place R5001 on BOTTOM side

SILK_PART=SMC_RST

OMIT

6

45 46 53

53

2

1

C5001

0.01UF

16V

10%

CERM

402

2

1

C5020

0.47UF

6.3V

10%

CERM-X5R

402

7

3

1

9

5

8

6

2

4

DFN

CRITICAL

VREF-3.3V-VDET-3.0V

U5010

2

1

10uF

X5R

6.3V 603

20%

C5025

2

1

C5026

0.01UF

CERM

16V

10% 402

2

1

R5000

MF-LF

1/16W 402

5%

1K

6

45 47 64

17

21

R5012

22

402

5% 1/16W MF-LF

PLACE_NEAR=U1800.N14:5.1mm

45

84 85

45

2

1

3

Q5020

SOD-VESM-HF

CRITICAL

SSM3K15FV

21

R5090

100K

MF 2015%

1/20W

45 46 53 45 46 53

2

1

R5076

MF

1/20W

5%

201

100K

2

1

R5020

MF

5%

100K

201

1/20W

21

R5094

201MF

1/20W

100K

5%

NOSTUFF

45 73

2

1

3

Q5040

SOD-VESM-HF

SSM3K15FV

CRITICAL

17

2

1

R5040

100K

5%

1/20W

MF

201

21

R5041

5%

0

1/16W

MF-LF

402

NOSTUFF

6

45 46 53

SMC Support

SYNC_DATE=07/12/2010

SYNC_MASTER=K91_BEN

PP3V42_G3H

GND_SMC_AVSS

MIN_NECK_WIDTH=0.1 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

SMC_SA_ISENSE

SMC_DCIN_ISENSE

SMC_BMON_ISENSE

SMC_GPU_HI_ISENSE

TP_SMC_P20

MAKE_BASE=TRUE

TP_SMC_P43

SMC_CLK32K

SMC_PROCHOT

SMC_GPU_ISENSE

MAKE_BASE=TRUE

SMC_GFX_ISENSESMC_GFX_ISENSE

SMC_BATLOW_L

PM_BATLOW_L

PP3V3_S5

PP3V3_SUS

DP_A_EXT_HPD

SMC_RX_L

PP3V42_G3H

SMC_TDI

SMC_ADAPTER_EN

WIFI_EVENT_L

SMC_TCK SMC_BIL_BUTTON_L

SMS_INT_L

SMC_PA0_PU

SMC_PB4

SMC_PME_S4_WAKE_L

PP3V3_S4

SMC_DP_HPD_L

SMC_BMON_MUX_SEL

SMC_RUNTIME_SCI_L

SMC_S4_WAKESRC_EN

SMC_GPU_ISENSE

SMS_INT_L

NC_SMC_FAN_3_TACH

NC_SMC_FAN_3_CTL

PP3V42_G3H

PM_CLK32K_SUSCLK_R

TP_SMC_P43

TP_SMC_P41

SMC_PBUS_VSENSE

SMC_ONOFF_L

PP3V3_WLAN

TP_SMC_P24

MAKE_BASE=TRUE

PP3V42_G3H

SMC_OTHER_HI_ISENSE TP_SMC_P10

MAKE_BASE=TRUE

TP_SMC_PF5

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

SMC_BMON_ISENSE

MAKE_BASE=TRUE

G3_POWERON_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

SMC_THRMTRIP

SMC_TDO

SMC_TMS

SMC_TX_L

SMC_LID

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

SMC_ONOFF_L SMC_MANUAL_RST_L

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

SMC_DCIN_ISENSE SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_CPUVCCIO_ISENSE

MAKE_BASE=TRUE

SMC_BC_ACOK

PM_THRMTRIP_L_R

SMC_SYS_LED

SYS_LED_L

SMC_TPAD_RST_L

SYS_LED_ANODE

PP5V_S3

SMC_XTAL_R

SMC_XTAL

TP_SMC_RSTGATE_L

SYS_LED_ILIM

CPU_PROCHOT_BUF

CPU_PROCHOT_L_R

CPU_PROCHOT_L

SMC_P1V5S3_ISENSE

PP3V3_S0

SMC_ONOFF_L

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_GPU_HI_ISENSE

PP3V3_S4

MIN_NECK_WIDTH=0.1 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

NC_SMC_FAN_2_CTL

SMC_CPU_VSENSE

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

SMC_BC_ACOK

MAKE_BASE=TRUE

SMC_GFX_VSENSE

NC_SMC_FAN_2_TACH

SMS_INT_L

MAKE_BASE=TRUE

TP_SMC_P10

SMC_CPUVCCIO_ISENSE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_GPU_VSENSE

MAKE_BASE=TRUE

SMC_P1V5S3_ISENSE

MAKE_BASE=TRUE

SMC_SA_ISENSE

SMC_DCIN_VSENSE

SMC_CPU_VSENSE

SMC_GPU_VSENSE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

SMC_PROCHOT_3_3_L

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

TP_SMC_P20 TP_SMC_P24

SMC_EXTAL

MAKE_BASE=TRUE

TP_SMC_P41

SMC_BC_ACOK

SMC_CASE_OPEN

TP_SMC_PF5

SYS_LED_L_VDIV

SMC_GFX_VSENSE

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

SMC_RESET_L

50 OF 132 46 OF 105

6 7

25 42 44 45 46 47 48

53 63 64 73

104

45 49 50 45 46 49

45 46 50

45 46

45 46 49

45 46 50 45 46 50

6 7

17 19 20 22 23 24 25 29 48 56 71 72

73 83 86 91

100 102 104

7

16 17 18 19 20 22 71 72 73

6

42 45 47

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6

45 47

17 45 73

6

31 45

6

45 47

6

45 63

45 46 55

45

6 7

46 53 54 72

45 46 50

19 45

45 73 86

45 46 49

45 46 55

6

45 46

6

45 46

6 7

25 42 44 45 46 47 48 53 63 64 73

104

45 46

45 46 49

6

45 46 53

6

31

45 46

6 7

25 42 44 45 46 47 48

53 63 64 73

104

45 46 50

45 46

45 46 50

45

45 46

6

45 47

6

45 47

6

42 45 47

44 45 53

45 46 49

6

45 46

6

45 46

45 46 50

45 46 49

45 46 49 63 64

6 7 29 31 42 43

44 67 72 82

104

45

45 46

45 46 49

6 7

12 23 25 26 28 32 35 36 39 40 41 48

49 50 51 52 54 57 61 62 72 73 80 83 84

85 88 89 91

100 102

45 46 50

6 7

46 53 54 72

6

45

6

45 46

45 46 49

6

45 46

45 46 49 63 64

45 46 49

6

45 46

45 46 55

45 46

45 46 49

6

45 46

45 46 50

45 46 49

45 46 50

45 46

45

45 46

45 46 49 63 64

45

45 46

45 46 49

OUT

IN

IN OUT

OUT

OUT IN

OUT IN OUT

IN

BI BI

OUT

IN

BI

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SPI Bus Series Termination

516S0573

LPC+SPI Connector

LPCPLUS:YES

PLACE_NEAR=J5100.12:5mm

47

402

MF-LF

1/16W

5%

R5126

1

2

56

PLACE_NEAR=R5127.2:5mm

47

MF-LF

5%

1/16W

402

R5122

1 2

1/16W

5%

MF-LF

402

15

PLACE_NEAR=U1800.AY1:5mm

R5112

1 2

16 95

LPCPLUS:YES

PLACE_NEAR=J5100.9:5mm

47

5% 1/16W MF-LF 402

R5127

1

2

LPCPLUS:YES

1/16W MF-LF

0

402

5%

PLACE_NEAR=J5100.11:5mm

R5128

1

2

6

42 45 46

6

45

6

45

6

45 46

LPCPLUS:YES

55909-0374

M-ST-SM

CRITICAL

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

6

19

6

42 45 46

6

45

6

45 46 64

6

45 46

6

45 46

6

25 88 95

6

47

6

16 45 88 95

6

17 45

6

47

6

16 45 88 95

6

16 45 88 95

6

45 46

6

17 45

6

16 45

6

47

6

47

6

19 56

6

16 45 88 95

6

16 45 88 95

6

25 95

56

PLACE_NEAR=U1800.AV3:5mm

402

MF-LF

1/16W

5%

15

R5110

1 2

16 95

56

PLACE_NEAR=U1800.BA2:5mm

1/16W

5%

MF-LF

402

15

R5111

1 2

16 95

56

PLACE_NEAR=U6100.2:5mm

15

402

MF-LF

5%

1/16W

R5123

1 2

16 95

PLACE_NEAR=R5125.2:5mm

47

402

1/16W

5%

MF-LF

R5120

1 2

LPCPLUS:YES

PLACE_NEAR=J5100.14:5mm

47

402

MF-LF

1/16W

5%

R5125

1

2

PLACE_NEAR=R5126.2:5mm

1/16W

47

MF-LF

5%

402

R5121

1 2

LPC+SPI Debug Connector

SYNC_DATE=09/23/2010

SYNC_MASTER=K91_YUN

SPI_ALT_MOSI

LPC_PWRDWN_L

LPC_SERIRQ

SPI_ALT_CS_L

SPI_ALT_CLK

LPC_AD<1>

SPI_MOSI_R

SPI_MLB_MISO

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_ALT_CS_L

SPI_ALT_CLK

SPI_ALT_MISO

SPI_CS0_L

SPI_CS0_R_L

SPI_CLK_R

SPI_CLK

SPI_MISO

SPI_MOSI

PP3V42_G3H

LPC_CLK33M_LPCPLUS LPC_AD<2> LPC_AD<3>

SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L LPCPLUS_GPIO

LPC_AD<0>

SPI_ALT_MOSI SPI_ALT_MISO

PM_CLKRUN_L

LPC_FRAME_L

SMC_TMS

SMC_TDO

LPCPLUS_RESET_L

SMC_TRST_L

SPIROM_USE_MLB

SMC_TX_L

SMC_MD1

PP5V_S0

51 OF 132 47 OF 105

6

47

6

47

6

47

6

47

95

6 7

25 42 44 45 46 48 53 63 64 73

104

6 7 8

22 41 52 54 65 68 69 70 73 87

104

105

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(Write: 0x94 Read: 0x95)

DP SDRV "A"

U9310

U9701

(MASTER)

LED BACKLIGHT

(WRITE: 0x58 READ: 0x59)

J2600 & J2650

XDP Connectors

(Write: 0xA4 Read: 0xA5)

(Write: 0x98 Read: 0x99)

U4900U1800

EMC1414: U5550

(Write: 0x98 Read: 0x99)

SMC

(MASTER)

U9310

DP SDRV "A"

(Write: 0x94 Read: 0x95)

Battery Manager - (Write: 0x16 Read: 0x17)

SMC "0" SMBus Connections

(Write: 0xA0 Read: 0xA1)

VRef DACs

T29 PortA MCU

(Write: 0x26 Read: 0x27)

U9330

(Write: 0x90 Read: 0x91)

Battery Temp - (Write: 0x92 Read: 0x93)

(Write: 0x82 Read: 0x83)

Whistler: U8000

GPU Temp (Int)

SMS

U5920

(Write: 0x30 Read: 0x31)

(Write: 0x88 Read: 0x89)

(Write: 0xB6 Read: 0xB7)

SATA Redriver

U4510

GPU Temp (Ext)

J3401

(Write: 0x72 Read: 0x73)

Lid Angle detect, SMS

(Write: 0x32 Read: 0x33)

SMC "A" SMBus Connections

(Write: 0x98 Read: 0x99)

J5800U4900

(MASTER)

EMC1414: U5570

CPU Temp

ALS

(Write: 0x72 Read: 0x73)

SMC

U6800

Mikey

U2901

J3500

(Address via ARP)

SO-DIMM "B"

J3100

(Write: 0x30 Read: 0x31)

Margin Control

SMC "Management" SMBus Connections

U2900

PCH "SMLink 0" Connections

ExpressCard Slot

X19 Temp

(MASTER)

U3600

The bus formerly known as "Battery B"

(MASTER)

U4900

SMC "Battery A" SMBus Connections

J3401

Trackpad

U4900

(MASTER)

SMC

J2900

U1800

(MASTER)

PCH "SMLink 1" Connections

SMLink 1 is slave port to access PCH & CPU via PECI.

Battery LED Driver - (Write: 0x36 Read: 0x37)

(MASTER)

Battery

SMC

U4900

J6955

ISL6258 - U7000

(See Table)

Battery

Battery Charger

(Write: 0x12 Read: 0x13)

PCH

(MASTER)

T29

T29 Temp

NOTE: SMC RMT bus remains powered and may be active in S3 state

Sensor ADC A

(Write: 0x10 Read: 0x11)

UD100

Sensor ADC B

(Write: 0x32 Read: 0x33)

SMC

UD210

SO-DIMM "A"

PCH SMBus "0" Connections

T29 SMBus Connections

EMC1412: U5520

(Write: 0x90 Read: 0x91)

SMC "B" SMBus Connections

2

1

R5200

MF-LF

1K

1/16W

5%

402

2

1

R5201

402

1/16W

1K

MF-LF

5%

2

1

R5291

4.7K

5%

MF-LF 402

1/16W

2

1

R5290

4.7K

MF-LF

5%

1/16W

402

2

MF-LF 402

5% 1/16W

4.7K

1

R5261

2

1

R5260

MF-LF

402

5%

1/16W

4.7K

2

1

R5280

402

2.0K

1/16W

5%

MF-LF

2

1

R5281

402

2.0K

MF-LF

5% 1/16W

2

1

R5270

402

1K

MF-LF

1/16W

5%

2

1

R5271

5%

1K

402

MF-LF

1/16W

2

1

R5251

MF-LF 402

1/16W

5%

4.7K

2

1

R5250

1/16W MF-LF

5%

4.7K

402

2

1

R5210

MF-LF

402

5%

1/16W

8.2K

2

1

R5211

402

5% 1/16W

8.2K

MF-LF

2

1

R5221

MF-LF 402

5% 1/16W

8.2K

NO STUFF

2

1

R5220

MF-LF

402

5%

1/16W

8.2K

NO STUFF

21

R5223

MF-LF

1/16W

5%

0

402

21

R5222

0

5% 1/16W MF-LF

402

2

1

R5231

402

5%

4.7K

MF-LF

1/16W

2

1

R5230

1/16W

402

4.7K

MF-LF

5%

2

1

R5235

SDRVI2C:MCU

402

MF-LF

1/16W

5%

0

2

1

R5234

SDRVI2C:MCU

0

5% 1/16W MF-LF

402

2

1

R5236

0

5%

402

MF-LF

1/16W

SDRVI2C:SB

2

1

R5237

1/16W MF-LF

402

5%

0

SDRVI2C:SB

SYNC_MASTER=K17_MLB

SYNC_DATE=04/26/2010

K92 SMBus Connections

PP3V3_S0

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA

PP3V3_S0

I2C_T29_SCL

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

PP3V3_S5

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

SMBUS_PCH_DATA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SML_PCH_1_CLK

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

SML_PCH_0_CLK

SML_PCH_0_DATA

MAKE_BASE=TRUE

SML_PCH_1_DATA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

PP3V3_S0

SMBUS_PCH_CLK

SMBUS_SMC_BSA_SCL

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_BSA_SDA

PP3V42_G3H

SMBUS_SMC_0_S0_SCL

PP3V3_S0

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_0_S0_SDA

PP3V3_S0

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

PP3V3_S3

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_PCH_DATA

SMBUS_PCH_CLK

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_0_S0_SCL

I2C_T29_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

I2C_DPSDRVA_SDA

I2C_DPSDRVA_SCL

MAKE_BASE=TRUE

I2C_DPSDRVA_SCL

MAKE_BASE=TRUE

I2C_DPSDRVA_SDA

I2C_T29_SCL

MAKE_BASE=TRUE

I2C_T29_SDA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_BSA_SCL

SMBUS_PCH_CLK

PP3V3_S0

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SMBUS_PCH_CLK

MAKE_BASE=TRUE

I2C_DPSDRVA_SDA

MAKE_BASE=TRUE

I2C_DPSDRVA_SCL I2C_DPSDRVA_SCL

I2C_DPSDRVA_SDA

SMBUS_PCH_DATA

MAKE_BASE=TRUE

SMBUS_PCH_CLK

MAKE_BASE=TRUE

52 OF 132 48 OF 105

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

45

48 51 98

45

48 51 98

45 48 51 98

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

33 48 85 97

45

48 98

103 104

45

48 98

103 104

6 7

17 19 20 22 23 24 25 29 46 56 71 72

73 83 86 91

100 102 104

45 48 98 103

104

45 48 98 103

104

6

16 23

26 28 30

32 41 48

62 89 95

6

31

45 48 51

80 98

6

31

45 48 51

80 98

16 95

6

45 48

63 64 98

6

45 48

63 64 98

6

45 48

63 64 98

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6

16 23

26 28 30

32 41 48

62 89 95

6

45 48

63 64 98

6

31

45 48 51

80 98

6

31

45 48 51

80 98

45 48 51 98

6

45 48 63

64 98

6 7

25 42 44 45 46 47 53 63 64 73

104

6

31 45 48

51 80 98

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

45 48 98

103

104

6

31 45 48

51 80 98

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6

16 23 26 28

30 32 41 48 62

89 95

6

16 23 26 28

30 32 41 48 62

89 95

6

16 23

26 28 30

32 41 48

62 89 95

6

16 23

26 28 30

32 41 48

62 89 95

6

16 23

26 28 30

32 41 48

62 89 95

6

16 23

26 28 30

32 41 48

62 89 95

6

16 23

26 28 30

32 41 48

62 89 95

6

31 45 48

54 55 98

6

31

45 48 54

55 98

45 48 51 98

6

31 45 48

54 55 98

45 48 51 98

6 7 8

18 24 25 29 30 31 32 49 50 54 55

73 88

104

6

31

45 48 54

55 98

6

31

45 48 54

55 98

6

31

45 48 54

55 98

6

31

45 48 54

55 98

6

31

45 48 54

55 98

6

16 23

26 28 30

32 41 48

62 89 95

6

16 23

26 28 30

32 41 48

62 89 95

6

16 23

26 28 30

32 41 48

62 89 95

45 48 98 103

104

45 48 98 103

104

45 48 98

103

104

6

31

45 48 51

80 98

33 48 85 97

48 85

33 48 85 97

6

31

45 48 51

80 98

6

45 48 63

64 98

6

16 23 26 28

30 32 41 48 62

89 95

6

16 23 26 28

30 32 41 48 62

89 95

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6

16 23 26

28 30 32 41

48 62 89

95

6

16 23 26

28 30 32 41

48 62 89

95

6

16 23 26

28 30 32 41

48 62 89

95

6

16 23 26

28 30 32 41

48 62 89

95

48 85

6

16 23 26 28 30 32

41 48 62

89 95

6

16 23 26 28 30 32

41 48 62

89 95

OUT

IN

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

S

D

N-CHANNEL

G

D

G

P-CHANNEL

IN

OUT

IN

V+ V-

THRM

OUT

IN

V+ V-

THRM

OUT

V+ V-

THRM

IN

OUT

V+ V-

THRM

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

AXG Vcore Voltage Sense / Filter

GPU Vcore Voltage Sense / Filter

divider when in S0.

PBUS Voltage Sense Enable & Filter

RTHEVENIN = 4573 Ohms

SMC Key VD0R

SMC Key IC1C

SMC Key IC2C

SMC Key IM0C

RTHEVENIN = 4573 Ohms

DC-In Voltage Sense Enable & Filter

Enables PBUS VSense

EDP:18A Vi=Voltage across R7350=0.006V=0.018V

DDR3 1.5V S3 Current Sense / Filter

SMC Key VN0R

SMC_ADC11

SMC_ADC9

Gain: 182x

SMC_ADC2

SMC Key VG0C

SMC_ADC4

SMC Key VP0R

GAIN:549X

CPU SA Current Sense / Filter

Gain: 154x

EDP:28A

EDP:6A

EDP:21.329A

Vi=Voltage across R7640=0.02139V

Vi=Voltage across R7140=0.006V

SMC Key IG0C

SMC_ADC3

SMC_ADC7

SMC_ADC8

SMC_ADC6

SMC_ADC0

SMC Key VC0C

CPU Vcore Voltage Sense / Filter

Enables DC-In VSense divider when AC present.

Gain: 3.75x

GPU VCore Load Side Current Sense / Filter

Vimon=31xVoltage across R8940=0.868V

CPU 1.05V VCCIO Current Sense / Filter

45 46

20%

6.3V X5R 402

PLACE_NEAR=U4900.N12:5MM

0.22UF

C5330

1

2

1/16W

1%

4.53K

MF-LF

402

PLACE_NEAR=U4900.N12:5MM

R5330

1 2

72 73

1%

1/16W

402

100K

MF-LF

R5302

1

2

100K

1% 1/16W MF-LF

402

R5301

1

2

45 46

PLACE_NEAR=U4900.L8:5MM

6.3V

20% X5R

402

0.22UF

C5304

1

2

402

1/16W MF-LF

1%

27.4K

PLACE_NEAR=U4900.L8:5MM

R5303

1

2

1% 1/16W MF-LF

402

5.49K

PLACE_NEAR=U4900.L8:5MM

R5304

1

2

CRITICAL

NTUD3169CZ

SOT-963

Q5300

6

3

2

5

1

4

45 46

27.4K

402

1% 1/16W MF-LF

PLACE_NEAR=U4900.N9:5MM

R5313

1

2

MF-LF

1/16W

1%

100K

402

R5312

1

2

CRITICAL

SOT-963

NTUD3169CZ

Q5310

6

3

2

5

1

4

6.3V X5R 402

PLACE_NEAR=U4900.N9:5MM

20%

0.22UF

C5314

1

2

5.49K

MF-LF

1% 1/16W

402

PLACE_NEAR=U4900.N9:5MM

R5314

1

2

100K

MF-LF

402

1/16W

1%

R5311

1

2

45 46 63 64

45 46

0.22UF

6.3V X5R 402

20%

PLACE_NEAR=U4900.L10:5MM

C5335

1

2

PLACE_NEAR=U4900.L10:5MM

4.53K

1/16W

1%

402

MF-LF

R5335

1 2

SM

PLACE_NEAR=R8940.1:5 MM

XW5335

1 2

82

SIGNAL_MODEL=EMPTY

MF-LF

402

1/16W

1%

10K

R5306

1 2

402

2.87K

1/16W

1%

MF-LF

SIGNAL_MODEL=EMPTY

R5305

1 2

402

MF-LF

4.02K

1/16W

1%

SIGNAL_MODEL=EMPTY

R5307

1 2

DFN

OPA2333

CRITICAL

U5310

3

2

1

9

4

8

402

1/16W

4.53K

MF-LF

1%

PLACE_NEAR=U4900.N11:5mm

R5308

1 2

45 46

PLACE_NEAR=U4900.N11:5mm

X5R

0.22UF

20%

6.3V 402

C5308

1

2

70

100

70

100

1/16W

1%

MF-LF

6.49K

402

R5324

1 2

1/16W 402

1% MF-LF

1M

R5325

1

2

1M

1/16W

1%

MF-LF

402

SIGNAL_MODEL=EMPTY

R5326

1 2

402

MF-LF

1/16W

1%

6.49K

R5323

1 2

CRITICAL

DFN

OPA2333

U5310

5

6

7

9

4

8

4.53K

MF-LF

402

1/16W

1%

PLACE_NEAR=U4900.L12:5mm

R5327

1 2

0.22UF

PLACE_NEAR=U4900.L12:5mm

20%

6.3V X5R 402

C5327

1

2

45 46

CERM

0.1UF

402

20% 10V

C5310

1

2

45 46

402

MF-LF

1/16W

1%

4.53K

PLACE_NEAR=U4900.M10:5mm

R5367

1 2

6.3V X5R

20%

0.22UF

402

PLACE_NEAR=U4900.M10:5mm

C5367

1

2

MF-LF

1.82K

1%

402

1/16W

R5363

1 2

DFN

CRITICAL

OPA2333

U5360

3

2

1

9

4

8

MF-LF

402

1M

1/16W

1%

SIGNAL_MODEL=EMPTY

R5366

1 2

1M

1% 1/16W

402

MF-LF

R5365

1

2

1.82K

MF-LF

1%

402

1/16W

R5364

1 2

65

100

65

100

45 46

4.53K

PLACE_NEAR=U4900.N13:5mm

402

1/16W

1%

MF-LF

R5377

1 2

PLACE_NEAR=U4900.N13:5mm

0.22UF

X5R 402

6.3V

20%

C5377

1

2

402

1/16W

1%

MF-LF

5.49K

R5373

1 2

CRITICAL

OPA2333

DFN

U5360

5

6

7

9

4

8

1/16W

402

1M

MF-LF

1%

SIGNAL_MODEL=EMPTY

R5376

1 2

1M

1% MF-LF

1/16W 402

R5375

1

2

5.49K

1/16W

1%

402

MF-LF

R5374

1 2

67

100

67

100

CERM

0.1UF

20% 10V

402

C5360

1

2

PLACE_NEAR=R7550.2:5 MM

SM

XW5330

1 2

45 46

402

PLACE_NEAR=U4900.N10:5MM

4.53K

1/16W MF-LF

1%

R5320

1 2

PLACE_NEAR=U4900.N10:5MM

20%

6.3V X5R 402

0.22UF

C5320

1

2

SM

PLACE_NEAR=R7510.2:5 MM

XW5320

1 2

SYNC_MASTER=K92_DINESH

SYNC_DATE=09/24/2010

Voltage & Load Side Current Sensing

GPUVCORE_IOUT

PM_SLP_S3_R_L

PDCINVSENS_EN_L_DIV

GND_SMC_AVSS

DCINVSENS_EN_L

SMC_BC_ACOK

SMC_CPUVCCIO_ISENSE

CPUVCCIOS0_CS_P

VCCSAS0_CS_P

CPUVCCIOISNS_R_P

VCCSAISNS_R_N

ISENSE_CPUVCCIO_IOUT

VCCSAISNS_R_P

CPUVCCIOISNS_R_N

PP3V3_S3

ISENSE_P1V5S3_IOUT

GPUISENS_P

ISENSE_SA_IOUT

GND_SMC_AVSS

VCCSAS0_CS_N

SMC_SA_ISENSE

CPUVCCIOS0_CS_N

GND_SMC_AVSS

SMC_GPU_ISENSE

GND_SMC_AVSSGND_SMC_AVSS

PPDCIN_G3H

DCIN_S5_VSENSE

GND_SMC_AVSS

SMC_CPU_VSENSE

GFXVSENSE_IN

PPVCORE_S0_AXG

PPVCORE_GPU

PPVCORE_S0_CPU

GND_SMC_AVSS

CPUVSENSE_IN

SMC_GFX_VSENSE

GPUVSENSE_IN

GND_SMC_AVSS

SMC_P1V5S3_ISENSE

ISNS_1V5_S3_N

SMC_DCIN_VSENSE

PBUSVSENS_EN_L

ISNS_1V5_S3_R_N

SMC_GPU_VSENSE

ISNS_1V5_S3_R_P

ISNS_1V5_S3_P

GND_SMC_AVSS

PBUS_S0_VSENSE

SMC_PBUS_VSENSE

PBUSVSENS_EN_L_DIV

GPUISENS_N

PP3V3_S0

GFXIMVP6_IMON

PPBUS_G3H

53 OF 132 49 OF 105

45 46 49 50

100

6 7 8

18 24 25 29 30 31 32 48 50 54 55

73 88

104

100

45 46 49 50

6 7

63 64

45 46 49 50

7

12 13 15

69

6 7

75 82

6 7

12 14 69

105

45 46 49 50

100

45 46 49 50

100

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 50 51 52 54 57 61 62 72 73 80 83 84

85 88 89 91

100 102

6 7 8

35 39

50 63 64 90

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN-

IN+ REF

V+

GND

OUT

V-

V+

+

-

IN

V-

V+

+

-

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Rsense value and INA gain need to be scrubbed!!

COMPUTING High Side Current Sense / Filter

RC values chosen per K17 Radar 7337775

CHARGER BMON High Side (BATTERY DISCHARGE) Current Sense, MUX & Filter

For Production, Bmon=36*18.33A*R7050=3.3V

SMC Key IN0C

SMC_ADC14

SMC Key IG0R

(Effective Sense R is 0.25mOhm due to summing of the 3 cores)

Max VOut: 3.3V at 3.3A

GRAPHICS High Side Current Sense / Filter

EDP: 33A TDP: 21.5A

GFX/IG VCore Load Side Current Sense / Filter

SMC_ADC5

SMC Key IC0R

SMC Key IB0R

SMC Key IO0R

SMC_ADC13

Power Drop across R5400 at EDP becomes 1.21W

OTHER High Side Current Sense / Filter

EDP Current:20.1A

Sense R is 0.75mOhm

DC-IN (AMON) Current Sense Filter

For engineering, stuff BMON_ENG

Scale: 28.58A / V

Gain:139.96x

SMC Key IC0C SMC_ADC1

Charger/Load side

For production, stuff BMON_PROD

EDP Current:4.9A

SMC Key ID0R

EDP Current:4.6A

For engineering, Bmon=6.6A*100*R7050=3.3V

battery to PBUS (battery discharge)

EDP Current:6.6A

From charger

NOTE: Monitoring current from

Sense R is R7050, 5mOhm

(100V/V)

Max VOut: 3.3V at 94.311A

Gain:100x

Gain:50x

EDP Current:12.546A

Battery side

Gain:200x

SMC_ADC10

CPU VCore Load Side Current Sense / Filter

Gain:50x

EDP: 94A TDP :45A

SMC_ADC12 ISL6259 Gain: 36x

SMC_ADC15

Sense R is R7510, R7520 & R7530

Sense R is R7550, 0.75mOhm

Gain:133.33x

Scale: 10A / V

2

1

C5420

10V CERM 402

BMON:ENG

0.1uF

20%

64

12

R5420

MF-LF

5%

1/16W

0

402

BMON:PROD

PLACE_NEAR=U5421.1:5MM

2

1

C5421

402

CERM

10V

20%

BMON:ENG

0.1uF

45 46

5

6

2

1

3 4

U5421

CRITICAL

NC7SB3157P6XG

SC70

BMON:ENG

45 46

64

100

64

100

45 46

2

1

C5441

0.22UF

6.3V

20% 402

X5R

PLACE_NEAR=U4900.K10:5MM

21

R5441

MF-LF

4.53K

1%

1/16W

402

PLACE_NEAR=U4900.K10:5MM

64

2

1

C5403

X5R

6.3V 402

20%

0.22UF

PLACE_NEAR=U4900.N8:5MM

21

402

MF-LF

1/16W

1%

4.53K

R5403

PLACE_NEAR=U4900.N8:5MM

45 46

21

R5433

402

MF-LF

4.53K

1/16W

1%

PLACE_NEAR=U4900.L7:5MM

2

1

C5433

PLACE_NEAR=U4900.L7:5MM

20%

0.22UF

6.3V X5R 402

45 46

21

R5422

MF-LF

1/16W

1%

402

PLACE_NEAR=U4900.M9:5MM

45.3K

2

1

C5422

402

0.022UF

10%

PLACE_NEAR=U4900.M9:5MM

CERM-X5R

16V

2

1

R5423

MF-LF

1/16W

5%

BMON:ENG

100K

402

3

1

6

4

5

2

U5400

CRITICAL

INA213

SC70

6 7 8

35 39 49 50 63

64 90

7

65 67 68 69 70

2

1

C5401

0.1UF

CERM

10V 402

20%

2

1

C5431

10V CERM

0.1UF

402

20%

7

66

3

1

6

4

5

2

U5430

CRITICAL

INA213

SC70

6 7 8

35 39 49

50 63 64 90

45 46

2

1

C5413

402

X5R

20%

6.3V

0.22UF

PLACE_NEAR=U4900.K9:5MM

21

R5413

4.53K

PLACE_NEAR=U4900.K9:5MM

1/16W

402

MF-LF

1%

2

1

C5411

0.1UF

10V CERM 402

20%

3

1

6

4

5

2

U5410

CRITICAL

SC70

INA210

6 7 8

35 39

49 50 63 64 90

7

82 87

432

1

R5400

0.003

0612

MF

CRITICAL

1%

1W

432

1

R5410

CRITICAL

0.003

0612

1%

1W

MF

432

1

R5430

0.005

0612

CRITICAL

1W

MF 1%

3

1

6

4

5

2

U5420

INA214

CRITICAL

BMON:ENG

SC70

45 46

2

1

C5451

IMVPISNS_ENG

6.3V 402

X5R

0.22UF

20%

PLACE_NEAR=U4900.M11:5MM

21

R5451

IMVPISNS_ENG

1/16W

1%

402

4.53K

PLACE_NEAR=U4900.M11:5MM

MF-LF

2

1

C5450

PLACE_NEAR=U5450.5:3MM

IMVPISNS_ENG

10V

20%

402

CERM

0.1UF

21

R5455

SIGNAL_MODEL=EMPTY

732K

MF-LF

402

IMVPISNS_ENG

1%

1/16W

5

2

4

3

1

U5450

CRITICAL

IMVPISNS_ENG

SC70-5

OPA333DCKG4

IMVPISNS_ENG

1/16W

402

R5452

1 2

MF-LF

3.48K

1%

IMVPISNS_ENG

1/16W

402

R5453

1 2

MF-LF

3.48K

1%

21

R5457

5.23K

IMVPISNS_ENG

0.5%

402

MF

1/16W

PLACE_NEAR=R7520.3:5MM

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7530.3:5MM

IMVPISNS_ENG

402

5.23K

0.5%

1/16W

MF

R5458

1 2

68 69

69

100

69

2

1

C5461

IMVPISNS_ENG

PLACE_NEAR=U4900.M13:5MM

X5R 402

20%

6.3V

0.22UF

21

R5461

MF-LF

IMVPISNS_ENG

PLACE_NEAR=U4900.M13:5MM

1%

4.53K

402

1/16W

2

1

C5460

PLACE_NEAR=U5460.5:3MM

IMVPISNS_ENG

0.1UF

10V 402

CERM

20%

2

1

R5454

SIGNAL_MODEL=EMPTY

MF-LF

1%

402

732K

IMVPISNS_ENG

1/16W

5

2

4

3

1

U5460

OPA333DCKG4

CRITICAL

IMVPISNS_ENG

SC70-5

21

R5465

IMVPISNS_ENG

402

MF-LF

1/16W

SIGNAL_MODEL=EMPTY

1%

732K

21

R5462

IMVPISNS_ENG

MF-LF

1/16W

1%

402

5.49K

21

R5463

IMVPISNS_ENG

1/16W MF-LF

1%

5.49K

402

2

1

R5464

SIGNAL_MODEL=EMPTY

1/16W MF-LF

732K

1%

402

IMVPISNS_ENG

69

100

69

100

21

R5456

0.5%

5.23K

IMVPISNS_ENG

1/16W

MF

402

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7510.3:5MM

68 69

100

69

SIGNAL_MODEL=EMPTY

1/16W

402

PLACE_NEAR=R7530.4:5MM

R5472

1 2

MF

5.23K

0.5%

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7520.4:5MM

1/16W

402

R5471

1 2

MF

5.23K

0.5%

PLACE_NEAR=R7510.4:5MM

SIGNAL_MODEL=EMPTY

1/16W

402

R5470

1 2

5.23K

MF

0.5%

21

R5467

SIGNAL_MODEL=EMPTY

0

1/16W

PLACE_NEAR=R7550.4:5MM

5%

MF-LF

IMVPISNS_ENG

402

21

R5466

402

0

5% 1/16W MF-LF

IMVPISNS_ENG

SIGNAL_MODEL=EMPTY

PLACE_NEAR=R7550.3:5MM

SYNC_DATE=10/29/2010

High Side and CPU/AXG Current Sensing

SYNC_MASTER=K92_DINESH

PP3V3_S0

CPUIMVP_ISNS1G_P

GND_SMC_AVSS

CPUIMVP_ISNS1G_R_P

GND_SMC_AVSS

CPUIMVP_ISUM_R_P

CPUIMVP_ISNS_N

SMC_OTHER_HI_ISENSE

GND_SMC_AVSS

CPUIMVP_ISNS1G_N

CPUIMVP_ISNS2_P

CPUIMVP_ISNS1_P

CPUIMVP_ISNS1_N

CPUIMVP_ISUM_IOUT

HS_GPU_IOUT

CHGR_BMON

SMC_GPU_HI_ISENSE

GND_SMC_AVSS

ISNS_HS_COMPUTING_P

GND_SMC_AVSS

ISNS_HS_OTHER_P

ISNS_HS_GPU_P

PPVIN_S5_HS_OTHER_ISNS

ISNS_HS_OTHER_N

PP3V3_S3

SMC_DCIN_ISENSE

PPBUS_G3H

PP3V3_S0

CHGR_CSO_R_N

CHGR_CSO_R_P BMON_INA_OUT

CHGR_AMON

ISNS_HS_GPU_N

PPBUS_G3H

PPVIN_S5_HS_GPU_ISNS

ISNS_HS_COMPUTING_N

PPBUS_G3H

SMC_GFX_ISENSE

HS_COMPUTING_IOUT

GND_SMC_AVSS

SMC_CPU_ISENSE

PP3V3_S0

CPUIMVP_ISNS2_N

CPUIMVP_ISNS3_N

CPUIMVP_ISNS3_P

PPVIN_S5_HS_COMPUTING_ISNS

SMC_CPU_HI_ISENSE

PP3V3_S0

CPUIMVP_ISNS1G_R_N

CPUIMVP_ISUMG_R_P

CPUIMVP_ISUM_R_N

CPUIMVP_ISUMG_R_N

CPUIMVP_ISUMG_IOUT

HS_OTHER_IOUT

BMON_AMUX_OUT

SMC_BMON_MUX_SEL

SMC_BMON_ISENSE

PP3V3_S0

CPUIMVP_ISNS_P

54 OF 132 50 OF 105

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

45 46 49 50

100

45 46 49 50

100

45 46 49 50

100

6 7 8

18 24 25 29 30 31 32 48 49 54 55

73 88

104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

100

45 46 49 50

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39

40 41 46 48 49 50 51 52 54 57

61 62 72 73 80 83 84 85 88 89 91

100

102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

100

BI

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

ALERT*

THERM*/ADDR

DP1

SMCLK

SMDATA

VDD

DN1

DP2/DN3

DN2/DP3

GND

BI

BI BI

BI

V+

GNDS

SDA

SCL

A0

ALERT

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

T29 Proximity

SMC Key THSP

Placement note:

Place U5520 close to T29 router on BOTTOM side

Read Address: 0x91

GPU Proximity/GPU Die/Left Heat Pipe/Right Fin Stack

Detect GPU Die Temperature

Place Q5503 on top side under left heat pipe near GPU

SMB Bus B

CPU Proximity/CPU Die/PCH Proximity/LVDS Connector Proximity

Write Address: 0x90

T29 Die

Placement note:

Read Address: 0x99

Place U5550 on bottom side under GPU

Note: EMC1414 can perform Beta

Compensation for External Diode 1 only

Placement note:

Detect CPU Die Temperature

Detect PCH Proximity Temperature

Write Address: 0x98

Placement note:

Place U5570 under CPU

Placement note:

close to the right fin stack

Place Q5501 on bottom side

Detect Right Fin Stack Temperature

Write Address: 0x98

Placement note:

Read Address: 0x99

Place Q5504 under PCH

Detect Left Heat Pipe Temperature

Use GND pin B1 on U3600 for N leg

Detect LVDS Connector Proximity Temperature

Place Q5502 on bottom side close to the LVDS Connector

Placement note:

402

MF-LF

1/16W

5%

10K

R5572

1

2

1/16W

10K

MF-LF

5%

402

R5571

1

2

CRITICAL

BC846BMXXH

SOT732-3

Q5504

1

3

2

6

31 45 48 80 98

6

31 45 48 80 98

MF-LF

402

5%

10K

1/16W

R5551

1

2

5%

402

1/16W

10K

MF-LF

R5552

1

2

402

0.1uF

20% 10V CERM

C5550

1

2

5%

47

1/16W MF-LF

402

R5550

1 2

PLACE_NEAR=U5550.2:5mm

PLACE_NEAR=U5550.3:5mm

SIGNAL_MODEL=EMPTY

0.0022uF

CERM

402

50V

10%

C5551

1

2

SIGNAL_MODEL=EMPTY

50V

10%

0.0022uF

CERM

402

PLACE_NEAR=U5550.5:5mm

PLACE_NEAR=U5550.4:5mm

C5552

1

2

79

100

79

100

CRITICAL

BC846BMXXH

SOT732-3

Q5503

1

3

2

EMC1414-A

CRITICAL

MSOP

U5550

83

5

2

4

6

10

9

7

1

CRITICAL

BC846BMXXH

SOT732-3

Q5501

1

3

2

CRITICAL

MSOP

EMC1414-A

U5570

83

5

2

4

6

10

9

7

1

CRITICAL

SOT732-3

BC846BMXXH

Q5502

1

3

2

PLACE_NEAR=U5570.3:5mm

0.0022uF

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5570.2:5mm

10% 50V

402

CERM

C5571

1

2

9

100

9

100

33 51

100

PLACE_NEAR=U3600.B1:2mm

SM

XW5520

1 2

20% 10V CERM 402

0.1uF

C5520

1

2

45 48 51 98

PLACE_NEAR=U3600 PLACE_SIDE=BOTTOM

TMP105

WCSP-6

CRITICAL

U5520

C2

B2

A2

B1

A1

C1

PLACE_SIDE=BOTTOM

NOSTUFF

402

MF-LF

5% 1/16W

10K

R5520

1

2

45 48 51 98

402

CERM

10V

20%

0.1uF

C5570

1

2

47

5%

402

MF-LF

1/16W

R5570

1 2

SIGNAL_MODEL=EMPTY

PLACE_NEAR=U5570.4:5mm PLACE_NEAR=U5570.5:5mm

CERM

50V

10%

402

0.0022uF

C5590

1

2

Thermal Sensors

SYNC_DATE=09/24/2010

SYNC_MASTER=K92_DINESH

T29_THERMD_N

GPUTHMSNS_D_P

T29_THERMD_P

MAKE_BASE=TRUE

T29_THERMD_P

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

CPU_THERMD_N

CPU_THERMD_P

PP3V3_S0

GPU_TDIODE_P

GPUTHMSNS_ALERT_L

GPUTHMSNS_THM_L

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

PP3V3_S0

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

CPUTHMSNS_ALERT_L

CPUTHMSNS_THM_L

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

GPUTHMSNS_D_N

VOLTAGE=3.3V

PP3V3_S0_GPUTHMSNS_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.38 mm

SMBUS_SMC_B_S0_SCL

GPU_TDIODE_N

SMBUS_SMC_B_S0_SDA

TP_T29_SENSOR_ALERT

PP3V3_S0

55 OF 132 51 OF 105

100

33 51

100

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

100

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

G

S D

G

S D

IN

OUT OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Right Fan

Left Fan

518S0521518S0521

MF-LF

5%

402

47K

1/16W

R5650

1

2

47K

402

MF-LF

5%

1/16W

R5655

1 2

1/16W

5%

47K

MF-LF

402

R5660

1

2

5% 1/16W MF-LF

47K

402

R5665

1 2

100K

1/16W

5%

MF-LF

402

R5651

1

2

SOT-363

2N7002DW-X-G

Q5660

3

5

4

1/16W

402

MF-LF

5%

100K

R5661

1

2

SOT-363

2N7002DW-X-G

Q5660

6

2

1

78171-0004

CRITICAL

M-RT-SM

J5650

5

6

1 2 3 4

M-RT-SM

CRITICAL

78171-0004

J5660

5

6

1 2 3 4

45

45 45

45

SYNC_DATE=04/26/2010

SYNC_MASTER=K17_MLB

Fan Connectors

FAN_LT_PWM

SMC_FAN_1_CTL

SMC_FAN_1_TACH

SMC_FAN_0_CTL

FAN_RT_PWM

PP5V_S0

FAN_RT_TACH

PP3V3_S0

FAN_LT_TACH

PP5V_S0 PP3V3_S0

SMC_FAN_0_TACH

56 OF 132 52 OF 105

6 6

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104 105

6

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6

6 7 8

22 41 47 52 54 65 68 69 70 73 87

104 105 6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

IN

NC

OUT

NC

IN_A1

OUT_B

IN_A3_B2

GND

THRM

OUT_A

VDD

IN_A2

IN_B1

PAD

(IPD)

IN_A1

OUT_B

IN_A3_B2

GND

THRM

OUT_A

VDD

IN_A2

IN_B1

PAD

(IPD)

D

SG

D

SG

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

0.021 V

14MA (MAX)

- SPI HOST TO Z2

- USB INTERFACES TO MLB

ISSP SCLK/I2C SCL

- TRACKPAD PICK BUTTONS

- KEYBOARD SCANNER

PIN NAME

36E-3 W

518S0637

LID OPEN => SMC_LID_LC ~ 3.42V

96E-6 W

75.2E-6 W

294E-6 W

0.72E-3 W

16.32E-6 W

0.255E-6 W

4.7 OHM

1.5 OHM

0.2 OHM

10 OHM

2.55 KOHM

4MA (MAX)

8MA (TYP)

60MA (MAX)

3V3 LDO

VDD VOUT

80UA

V+

10UA

IC

CURRENT

R_SNS V_SNS POWER

0.0255 V

0.204 V

0.6 V

0.012 V

0.0188 V

18V BOOSTER

VIN

VDD

PSOC

Pull-up in U5010.

TMP102

LID CLOSE => SMC_LID_LC < 0.50V

WHEN THE LID IS CLOSED

THE TPAD BUTTONS WILL BE DISABLE

Keyboard Connector

Keys ANDed with PSOC power to isolate when PSOC is not powered.

SMC Manual Reset & Isolation

ISSP SDATA/I2C SDA

337S2983

(PP3V3_S4_PSOC)

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

PSOC USB CONTROLLER

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

PLACE THESE COMPONENTS CLOSE TO J5800

TPAD Buttons Disable

BYPASS=U5701.49:50:11 mm

603

X5R

6.3V

20%

4.7UF

C5706

1

2

16V 402

X7R-CERM

10%

0.1UF

BYPASS=U5701.49:50:8 mm

C5705

1

2

5% 50V CERM 402

100PF

BYPASS=U5701.49:50:5 mm

C5704

1

2

0.1UF

402

X7R-CERM

10%

BYPASS=U5701.22:19:8 mm

16V

C5703

1

2

50V

100PF

5%

402

CERM

BYPASS=U5701.22:19:5 mm

C5702

1

2

20%

6.3V X5R 603

4.7UF

BYPASS=U5701.22:19:11 mm

C5701

1

2

24

1/16W MF-LF

5%

402

R5702

1 2

CRITICAL

OMIT

CY8C24794

MLF

U5701

20

21

45544653475248

51

25182617271628

15

41

2

42

1

435644

55

3310

34

9

35

8

36

7

37

6

38

5

39

4

40

3

2914

3013

3112

3211

24

235722 49

19

50

402

5%

MF-LF

1/16W

24

R5701

1 2

44 45 46

20%

0.1UF

402

10V

CERM

PLACEMENT_NOTE=NEAR J5713

C5710

1

2

402

5%

MF-LF

1/16W

1K

R5710

1 2

470

1%

402

1/16W MF-LF

R5714

1 2

402

1%

MF-LF

1/16W

10K

R5715

1 2

CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

J5713

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

6

45 46

402

0

5%

MF-LF

1/16W

R5704

2 1

CRITICAL

SLG4AP006

TDFN

U5755

5

2

3

7

6

4

8

9

1

16V

10%

402

0.1UF

X7R-CERM

C5755

1

2

X7R-CERM

16V

10%

402

0.1UF

C5750

1

2

TDFN

SLG4AP006

CRITICAL

U5750

5

2

3

7

6

4

8

9

1

CRITICAL

SSM6N15FEAPE

SOT563

Q5701

6

2

1

SOT563

SSM6N15FEAPE

Q5701

3

5

4

46

45 46

73

MF-LF

1/16W

5%

220K

402

R5703

1

2

SYNC_DATE=10/11/2010SYNC_MASTER=K92_ERIC

WELLSPRING 1

Z2_DEBUG3

PICKB_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP3V3_S4_PSOC

PP3V3_S4

SMC_PME_S4_WAKE_L

BUTTON_DISABLE

Z2_KEY_ACT_L

TP_ISSP_SCLK_P1_1

WS_CONTROL_KEY

Z2_HOST_INTN

WS_KBD22

WS_KBD14

Z2_CLKIN

NC_PSOC_P1_3

USB_TPAD_N

USB_TPAD_R_N

TP_P7_7

USB_TPAD_R_P

Z2_CS_L

PSOC_MISO

WS_KBD5

TP_ISSP_SDATA_P1_0

WS_KBD4

WS_KBD20

WS_KBD23

WS_KBD21

WS_KBD11

WS_KBD7

WS_KBD10

WS_KBD12

WS_KBD8

WS_KBD2

PSOC_MOSI

WS_KBD16_NUM

PP3V42_G3H

PP3V3_S4

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KEY

WS_LEFT_SHIFT_KEY

PSOC_SCLK

WS_KBD10

WS_KBD1

Z2_SCLK

Z2_MOSI

WS_KBD5 WS_KBD6 WS_KBD7

SMC_TPAD_RST

SMC_TPAD_RST_L

BUTTON_DISABLE

SMC_LID

Z2_MISO

PSOC_F_CS_L

SMC_ONOFF_L

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

WS_LEFT_SHIFT_KBD

WS_KBD_ONOFF_L

USB_TPAD_P

WS_KBD15_C

WS_KBD16N

WS_KBD17

WS_KBD18

WS_KBD19

WS_KBD1

WS_KBD4

WS_KBD18

WS_KBD17

WS_KBD14

WS_KBD13

WS_KBD11 WS_KBD12

WS_KBD9

WS_KBD21

WS_KBD20

WS_KBD19

WS_KBD22 WS_KBD23

WS_KBD8

WS_KBD15_CAP

WS_KBD16N

WS_KBD15_C

WS_LEFT_SHIFT_KEY

WS_CONTROL_KEY

WS_LEFT_OPTION_KBD

WS_CONTROL_KBD

WS_LEFT_OPTION_KEY

WS_KBD2

PP3V3_S4

WS_KBD9

WS_KBD13

Z2_RESET

TPAD_VBUS_EN

WS_KBD6

WS_KBD3

TP_PSOC_SCL TP_PSOC_SDA

PP3V42_G3H

WS_KBD3

53 OF 105

57 OF 132

6

54

6

54

6 7

46 53 54 72

53

6

54

53

6

54

6

53

6

53

6

54

6

24 94

100

6

54

6

54

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

54

6

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

46 53 54 72

6

53

6

54

6

53

6

53

6

54

6

54

6

53

6

53

6

53

6

54

6

54

6

53

6

53

6

53

6

24 94

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6

53

6 7

46 53 54 72

6

53

6

53

6

54

6

53

6

53

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6

53

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

BI

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

518S0691

J5815 pin 1 is grounded

BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION

R5853 always stuffed, R5854 only grounded when KB BL flex connected.

- STARTUP TIME LESS THAN 2MS

- RIPPLE TO MEET ERS

516S0689

- 100-300 KHZ CLEAN SPECTRUM

- R5812,R5813,C5818 MODIFIED

BOOSTER +18.5VDC FOR SENSORS

(SMC_KBDLED_PRESENT_L)

Keyboard Backlight Connector

tristate and read SMC_SYS_KBDLED:

If HIGH, keyboard backlight not present

If LOW, keyboard backlight present

To detect Keyboard backlight, SMC will

Keyboard Backlight Driver & Detection

on keyboard backlight flex

IPD Flex Connector

- DROOP LINE REGULATION

55560-0228

CRITICAL

M-ST-SM

J5800

1

10

1112 1314 1516 1718 19

2

20

2122

34 56 78 9

SOD-323

CRITICAL

B0520WSXG

D5802

1 2

X5R

603-1

25V

1UF

10%

C5819

1

2

0

5%

402

MF-LF

1/16W

R5806

1 2

10%

402

0.1UF

16V

X7R-CERM

C5816

1

2

0

402

5%

MF-LF

1/16W

R5805

2 1

16V

2.2UF

603

X5R

10%

C5817

1

2

QFN

TPS61045

CRITICAL

U5805

5

3

4

6

1

7

8

9

2

3.3UH-870MA

VLF3010AT-SM-HF

CRITICAL

L5801

1 2

100K

MF-LF

1/16W 402

1%

R5811

1

2

45

4.7K

KB_BL

402

MF-LF

1/16W

5%

R5854

1

2

MF-LF

470K

5%

1/16W

402

R5853

1

2

LT3491

KB_BL

CRITICAL

DFN

U5850

4

6

2

5

3

7

1

1/16W

5%

NO STUFF

402

MF-LF

10K

R5852

1

2

KB_BL

10% X5R

402-1

1UF

10V

C5850

1

2

KB_BL

402

MF-LF

1/16W

1%

10

R5855

1

2

KB_BL

1098AS-SM

10UH-0.58A-0.35OHM

CRITICAL

L5850

1 2

KB_BL

35V

1UF

603

X5R

10%

C5855

1

2

CRITICAL

KB_BL

FF18-4A-R11AD-B-3H

F-RT-SM

J5815

1 2 3 4

39PF

5%

402

CERM

50V

C5818

1

2

MF-LF

1/16W

1M

1%

402

R5812

1

2

MF-LF

71.5K

1% 1/16W

402

R5813

1

2

402

1000PF

NP0-C0G

5% 25V

C5815

1

2

NO STUFF

402

5%

MF-LF

0

1/16W

R5800

1 2

WELLSPRING 2

SYNC_DATE=07/27/2010SYNC_MASTER=K92_ERIC

Z2_CLKIN

PP3V3_S4

MIN_NECK_WIDTH=0.2 MM

KBDLED_ANODE

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

KBDLED_SW

MIN_NECK_WIDTH=0.2 MM SWITCH_NODE=TRUE

PP18V5_S4_R

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

SMC_KDBLED_PRESENT_L

PP5V_S0

PSOC_F_CS_L

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

PP3V3_S3_TPAD

MIN_LINE_WIDTH=0.5 mm

Z2_MOSI

Z2_DEBUG3

Z2_HOST_INTN

Z2_SCLK

PP18V5_S4

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM VOLTAGE=18.5V

PP18V5_S4

PP3V3_S3

Z2_BOOST_EN

Z2_MISO

Z2_CS_L

Z2_KEY_ACT_L

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

PSOC_SCLK

PSOC_MOSI

PSOC_MISO

PICKB_L

Z2_RESET

PP5V_S5_P18V5S5_VIN

MIN_LINE_WIDTH=0.50MM VOLTAGE=5V

MIN_NECK_WIDTH=0.20MM

Z2_BOOST_EN

P18V5S4_FB

VOLTAGE=5V

MIN_LINE_WIDTH=0.50MM

PP5V_S4_P18V5S5

MIN_NECK_WIDTH=0.20MM

SWITCH_NODE=TRUE

P18V5S4_SW

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP5V_S5

KBDLED_CAP

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0

SMC_SYS_KBDLED

58 OF 132 54 OF 105

6

53

6 7

46 53 72

6

6 7 8

22 41 47 52 65 68 69 70 73 87

104

105

6

53

6

53

6

53

6

53

6

53

6

54

6

54

6 7 8

18 24 25 29 30 31 32 48 49 50 55

73 88

104

6

54

6

53

6

53

6

53

6

31 45 48 55 98

6

31 45 48 55 98

6

53

6

53

6

53

6

53

6

53

6

54

7

66 72

103 104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 57 61 62 72 73 80 83 84

85 88 89 91

100 102

INT2

VDD

VDD_IO

SDO

GND

NC

RESERVED

INT1CSSDA/SDI/SDO

SCL/SPC

NC NC

OUT

BI

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

placed on board bottom-side (view thru top):

Front of system

Circle indicates pin 1 location when placed

338S0687

+X

+Y

in correct orientation

+Z (dn)

Desired orientation when

NOTE: SDA and SCL have internal pull-ups to VDD_IO.

SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)

CRITICAL

PLACEMENT_NOTE=See schematic for orientation.

LIS331DLH

LGA

U5920

8

5

121316

11

9

2 3

10 15

4

6

7

14

1

10% X5R

201

0.1UF

6.3V

BYPASS=U5920.14:13:8 mm

C5922

1

2

20%

10UF

6.3V X5R 603

BYPASS=U5920.14:13:8 mm

C5926

1

2

201

MF

5%

1/20W

10K

R5920

1

2

201

MF

1/20W

5%

10K

R5921

1

2

MF

0

5%

1/20W

201

R5922

1 2

5% MF

0

1/20W

201

R5923

1 2

MF

201

1/20W

5%

10K

R5924

1

2

45 46

6

31 45 48 54 98

6

31 45 48 54 98

10K

201

NOSTUFF

1/20W

5% MF

R5925

1

2

Digital Accelerometer

SYNC_DATE=06/02/2010

SYNC_MASTER=K92_DINESH

SMS_I2C_SEL

PP3V3_S3

SMBUS_SMC_A_S3_SCL

SMS_ADDR_SELECT I2C_SMC_SMS_SDA_R

TP_SMS_INT2

SMS_INT_L

I2C_SMC_SMS_SCL_R

SMBUS_SMC_A_S3_SDA

59 OF 132 55 OF 105

6 7 8

18 24 25 29 30 31 32 48 49 50 54

73 88

104

OUT

IN

IN IN

IN

WP*

SI

HOLD*

VSS

SCK

CE*

VDD

SO

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ROM will ignore SPI cycles.

NOTE: If HOLD* is asserted

402

20%

CERM

0.1UF

10V

C6100

1

2

402

3.3K

5% MF-LF

1/16W

R6101

1

2

47

47 47

6

19 47

CRITICAL

OMIT

64MBIT

SST25VF064C

SOIC

U6100

1

7

6

5

2

8

4

3

SPI ROM

SYNC_MASTER=K92_BEN

SYNC_DATE=05/27/2010

PP3V3_S5

SPIROM_USE_MLB

SPI_MLB_MOSI

SPI_MLB_CS_L SPI_WP_L

SPI_MLB_MISO

SPI_MLB_CLK

61 OF 132 56 OF 105

6 7

17 19 20 22 23 24 25 29 46 48 71 72

73 83 86 91

100 102 104

IN

OUT

IN IN

IN

OUT OUT

OUT

IN

BP

NC

SHDN*

IN OUT

GND

OUT

IN

OUT OUT

IN IN

OUT

OUT OUT

OUT

IN

/SPDIF_OUT2

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

HP AMP CNTRL

LFE SPKR AMP (FC/LFE)

PIN 39 & THERMAL PAD

PLACE XW6206 BETWEEN

DAC2/3 FSOUTPUTDIFF= 2.67VRMS DAC2/3 FSOUTPUTSE= 1.34VRMS

SE FSINPUT= 1.22VRMS

AUDIO 4.5V REGULATOR

APPLE P/N 353S2234

DAC1 FSOUTPUT= 1.34VRMS

NC

MAC SPKR AMP CNTRL

DIGITAL MIC DATA LINE

DIGITAL MIC CLOCK LINE

DIFF FSINPUT= 2.45VRMS

WFR SPKR AMPS (L2/R2)

WIN SPKR AMP CNTRL

EXTERNAL MIC INPUT

INTERNAL MIC INPUT

AUDIO CODEC

APPLE P/N 353S3199

62

16 95

2.2UF

402-LF

20%

6.3V CERM

C6211

1

2

2.2UF

20% CERM

6.3V 402-LF

C6212

1

2

57 58

402

2.67K

1% 1/16W MF-LF

R6200

1

2

402

X5R

20%

4V

4.7UF

C6200

1

2

60

X5R

10%

402

10V

0.47UF

C6201

1

2

1%

100K

402

MF-LF

1/16W

R6203

1

2

402

NOSTUFF

1/16W

5%

0

MF-LF

R6204

1

2

CRITICAL

10%

CASE-R-HF

20V

TANT

1UF

C6213

1

2

10UF

20% POLY-TANT

CASE-B2-SM

16V

CRITICAL

C6214

1

2

SM

SIGNAL_MODEL=EMPTY

XW6201

1 2

62

100

62

100

58

60

100

60 100

POLY-TANT

20% 16V

10UF

CASE-B2-SM

C6202

1

2

61

X5R

10%

1

402

0.47UF

10V

C6203

2

16V

10UF

20% POLY-TANT

CASE-B2-SM

C6204

1

2

10%

402

X5R

10V

0.47UF

C6205

1

2

402-1

10% X5R

10V

1UF

C6206

1

2

402

10% X5R

10V

0.47UF

C6207

1

2

CRITICAL

X5R

20% 10V

10UF

805

C6208

1

2

58 59

57 59

61

58

8

57

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

57 58

10%

0.1UF

402-1

X5R

16V

C6250

1

2

0402

FERR-220-OHM

L6250

1 2

16 95

SM

XW6200

1 2

10%

402

10V

1UF

X5R

C6251

1

2

10%

402

50V

0.001UF

CERM

C6252

1

2

0.01UF

10%

402

16V

CERM

C6253

1 2

402

10% X5R

10V

1UF

C6254

1

2

CRITICAL

MAX8840-4.5V

UDFN

U6201

4

2

1

5

6

3

402

MF-LF

5%

1K

1/16W

R6250

1 2

60

100

16 95

60

100

60

100

62

100

62

100

62

59

MF-LF

22

402

21

1/16W

5%

R6201

33

1/16W MF-LF

5%

402

R6202

1 2

58 60

16 95

BAT54XV2T1

1

SOD-523

D6200

2

6.3V CERM

402-LF

20%

2.2UF

C6209

1

2

402-LF

6.3V CERM

20%

2.2UF

C6210

1

2

SM

XW6206

1

2

61

FERR-220-OHM

0402

L6251

1 2

SM

XW6251

1 2

5%

33

402

MF-LF

1/16W

R6205

1 2

16 95

SM

XW6202

1 2

3

13

12

2

44

14

11

34

29

45

24

9

15

41

37

36

33

48

22

43 42

47

35

49

46

40

39

28

26

25

23

21

18 17

16

10

7

4

38

8 5

1

6

20

19

27

31 30 32

QFN

U6200

CRITICAL

CS4206B

SYNC_DATE=07/30/2010

AUDIO:CODEC

SYNC_MASTER=K92_KAVITHA

PP1V5_S0

AUD_LO3_R_P AUD_LO3_R_N

AUD_GPIO_3

AUD_GPIO_2

AUD_SENSE_A

AUD_GPIO_1

AUD_DMIC_SDA1

CS4206_FP

HDA_RST_L

TP_AUD_LO2_L_N

VBIAS_DAC

CS4206_FLYP

PP4V5_AUDIO_ANALOG

CS4206_FN

AUD_LO2_R_N

AUD_LO2_R_P

CS4206_SPDIF_OUT

AUD_LI_C

CS4206_FLYC

CS4206_FLYN

AUD_SPDIF_IN

TP_AUD_LO2_L_P

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.60MM

VOLTAGE=0V

GND_AUDIO_HPAMP

PP5V_S0_AUDIO

MIN_LINE_WIDTH=0.30MM

AUD_HP_PORT_R

MIN_NECK_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MMMIN_LINE_WIDTH=0.20MM

AUD_INT_HP_REF

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

CS4206_VCOM

GND_AUDIO_CODEC

AUD_LI_R

AUD_LI_L

AUD_MIC_INL_P AUD_MIC_INL_N

AUD_CODEC_MICBIAS

HDA_SYNC

CODEC_DMIC_CLK

MIN_LINE_WIDTH=0.30MM

AUD_HP_PORT_L

MIN_NECK_WIDTH=0.20MM

AUD_SDI_R

HDA_SDOUT

PP3V3_S0

HDA_BIT_CLK

AUD_MIC_INR_N

AUD_MIC_INR_P

CS4206_VREF_ADC

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_LO3_L_P AUD_LO3_L_N

AUD_SPDIF_OUT

HDA_SDIN0

AUD_HP_PORT_L

AUD_HP_PORT_L_N

AUD_HP_PORT_L_P

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

VOLTAGE=0V

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

MAX8840_BP

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

AUD_4V5_REG_IN

VOLTAGE=5V MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

PP5V_AUDIO_HPAMP

VOLTAGE=5V MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=0V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.60MM

GND_AUDIO_HPAMP

AUD_REG_SHDN_L

GND_AUDIO_HPAMP

PP3V3_S0

PP4V5_AUDIO_ANALOG

AUD_DMIC_CLK

PP5V_S0_AUDIO

GND_AUDIO_HPAMP

GND_AUDIO_CODEC

62 OF 132 57 OF 105

7

16 20 22 25 32 41 71

57 59

57 58 62

95

57 59

60

57 58 62

57 58

59

57 59

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

8

57

57 59

57 58 62

IN

OUT

IN

OUT

IN

V-

V+

V-

V+

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FC = 5 HZ Max VIN = 2VRMS, CODEC VIN = 1.14 VRMS

CODEC Nom SE RIN = 20K OHMS

SE-TO-DIFF CONVERTER

NET RIN = 18K OHMS

7.87K

1/16W MF-LF

1%

402

R6306

1 2

10% 50V CERM 402

820PF

NOSTUFF

C6304

1

2

CRITICAL

SMA-HF1

TANT

16V

10%

3.3UF

C6303

12

402

1%

MF-LF

1/16W

7.87K

R6300

1 2

1%

MF-LF

402

1/16W

21.5K

R6301

1

2

SMA-HF1

TANT

16V

10%

3.3UF

CRITICAL

C6302

12

61

CRITICAL

3.3UF

SMA-HF1

TANT

16V

10%

C6300

12

57

57 58 62

820PF

402

CERM

50V

10%

NOSTUFF

C6301

1

2

57 60

X5R

20%

4.7UF

402

6.3V

C6350

1

2

0.47UF

402

X5R

10V

10%

C6351

1

2

10

1% 1/16W MF-LF 402

R6303

1

2

60

100

60

100

10%

TANT

SMA-HF1

16V

3.3UF

CRITICAL

C6353

12

61

402

1%

2.21K

MF-LF

1/16W

R6355

1 2

1/16W MF-LF

402

1%

2.21K

R6357

1 2

2.21K

1/16W

1%

402

MF-LF

R6358

1 2

2.21K

1/16W

402

1%

MF-LF

R6356

1 2

CRITICAL

SMA-HF1

TANT

16V

10%

3.3UF

C6352

1

2

61

21K

1% 1/16W MF-LF

402

R6350

1

2

21K

1% 1/16W MF-LF

402

R6351

1

2

21K

1/16W MF-LF

1%

402

R6353

1 2

MAX4253

UCSP

CRITICAL

U6350

C3

C2

C1

C4

B1

B4

CRITICAL

MAX4253

UCSP

U6350

A3

A2

A1

A4

B1

B4

402

1/16W

21.5K

MF-LF

1%

R6305

1

2

21K

1/16W MF-LF

1%

402

R6354

1 2

SYNC_MASTER=K92_AUDIO

AUDIO: LINE IN

SYNC_DATE=06/16/2010

AUD_SE_DIFF_P_INV

AUD_SE_DIFF_N_INV

GND_AUDIO_CODEC

AUD_SE_DIFF_IN

AUD_HP_PORT_R

AUD_LO1_R_P

PP4V5_AUDIO_ANALOG

AUD_GPIO_2

AUD_LO1_R_N

AUD_SE_DIFF_IN_R

GND_AUDIO_CODEC

AUD_LI_INR

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_LI_C

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

AUD_LI_R

MIN_NECK_WIDTH=.2MM

MIN_LINE_WIDTH=.3MM

AUD_LI_LF

MIN_NECK_WIDTH=.2MM

MIN_LINE_WIDTH=.3MM

AUD_LI_RF

AUD_SE_DIFF_VBIAS

MIN_NECK_WIDTH=0.15MM

MIN_LINE_WIDTH=0.20MM

AUD_LI_INL

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_LI_L

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

AUD_LI_GND

63 OF 132 58 OF 105

57 58 62

57 59

57

IN

IN IN

LIN

PVEE

CN CP

ROUT

LOUT

VSS2

VSS1

THRM

AVDD

PVDD

RIN

PDN*

PAD

IN

OUT

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE C6503 NEAR AVDD PIN (3)

PLACE C6500 & C6501 NEAR PVDD PIN (5)

LP:42.10 KHZ

1ST ORDER DAC FILTER

VOLTAGE GAIN:1.53

APN:353S2347

HEADPHONE AMPLIFIER (AK4201)

57

59

402

5%

MF-LF

0

1/16W

R6501

1 2

402

100K

MF-LF

1/16W

5%

R6500

1

2

0.1UF

402-1

16V X5R

10%

C6503

1

2

EXT_HP_AMP

CRITICAL

AK4201EU

USON

U6500

3

6 7

1 2

8

5

10

12 11

13

4

9

10%

402

X5R

1UF

10V

CRITICAL

C6504

1

2

402

13.7K

1% 1/16W MF-LF

R6531

1

2

10%

402

X5R

1UF

10V

CRITICAL

C6505

1

2

402

MF-LF

21K

1%

1/16W

R6530

1 2

0603

FERR-220-OHM-2.5A

L6535

1 2

X5R

20%

805

10V

10UF

C6500

1

2

10%

402

50V CERM

0.001UF

C6501

1

2

59 61

57 58

59

57

402

1%

1/16W

13.7K

MF-LF

R6520

1 2

1/16W

1%

MF-LF

402

13.7K

R6510

1 2

402

1%

1/16W

21K

MF-LF

R6521

1 2

402

50V

5%

CERM

180PF

CRITICAL

C6521

1 2

5%

CERM

50V 402

CRITICAL

180PF

C6511

1 2

21K

1%

402

1/16W MF-LF

R6511

1 2

402

21K

1% 1/16W MF-LF

R6516

1

2

402

MF-LF

1/16W

21K

1%

R6526

1

2

SM

XW6501

1 2

SYNC_DATE=10/22/2010

AUDIO: HEADPHONE OUT

SYNC_MASTER=K92_KAVITHA

GND_AUDIO_HPAMP

AUD_HPAMP_INL_M AUD_HPAMP_INR_M

AUD_HPAMP_MUTE_L

AUD_HPAMP_INL_M

AUD_HPAMP_OUTR

AUD_HPAMP_INR_M

AUD_LO_GND_R

AUD_HPAMP_OUTL

AUD_HP_PORT_L

AUD_HP_PORT_R

AUD_GPIO_1

AUD_LO_FDBK

PP5V_AUDIO_HPAMP

AK4201_VSS2

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

AK4201_CN

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

AK4201_CP

MIN_LINE_WIDTH=0.40MM

AK4201_PVEE

MIN_NECK_WIDTH=0.110MM

MIN_NECK_WIDTH=0.20 MM

AUD_LO_GND_R

MIN_LINE_WIDTH=0.60 MM

VOLTAGE=0V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

AUD_HPAMP_OUTR

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

AUD_HPAMP_OUTL

65 OF 132 59 OF 105

57

59 61

57

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

VDD

EDGE

GND

GAIN

SD*

OUT+ OUT-

IN-

IN+

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Spk amp placed on the top side(flipped from K17) To prevent criss cross routes, the N and P are swapped on the input and output

Spk amp placed on the top side(flipped from K17)

5X MONO SPEAKER AMPLIFIERS (SSM2375)

APN: 353S2958

PLACE C6641/C6642 CLOSE TO PVDD PIN

PLACE C6625 CLOSE TO VDD PIN

PLACE C6651/C6652 CLOSE TO PVDD PIN

L6602 SHOULD BRIDGE SPLIT BETWEEN

PLACE C6631/C6632 CLOSE TO PVDD PIN

PLACE C6611/C6612 CLOSE TO PVDD PIN

GND_AUDIO_CODEC & DIGITAL GND

FC (SPEAKERS FL/FR/LFE) = ~90 HZ

FC (SPEAKERS BL/BR) = ~737 HZ

GAIN = +3 DB (BR, FL, FR, LFE), +9 DB (BL)

PLACE C6621/C6622 CLOSE TO PVDD PIN

GND_AUDIO_CODEC & DIGITAL GND

L6601 SHOULD BRIDGE SPLIT BETWEEN

To prevent criss cross routes, the N and P are swapped on the input and output

Spk amp placed on the top side(flipped from K17) To prevent criss cross routes, the N and P are swapped on the input and output

402

100K

1/16W MF-LF

5%

R6600

1

2

FERR-1000-OHM

0402

L6601

1 2

57

57 58

FERR-1000-OHM

0402

L6610

1 2

6

61

6

61

6

61

0402

FERR-1000-OHM

L6620

1 2

57

100

6

61

0402

FERR-1000-OHM

L6630

1 2

58

100

6

61

6

61

0402

FERR-1000-OHM

L6640

1 2

57

100

6

61

6

61

CASE-AL1

20%

TANT

CRITICAL

100UF

6.3V

C6622

1

2

CASE-AL1

20%

TANT

6.3V

100UF

CRITICAL

C6642

1

2

CRITICAL

100UF

TANT

20%

6.3V

CASE-AL1

C6652

1

2

FERR-1000-OHM

0402

L6650

1 2

57

100

6

61

6

61

FERR-1000-OHM

0402

L6611

1 2

57

0402

FERR-1000-OHM

L6621

1 2

57

100

0402

FERR-1000-OHM

L6631

1 2

58

100

0402

FERR-1000-OHM

L6641

1 2

57

100

0402

FERR-1000-OHM

L6651

1 2

57

100

0.0027UF

402

CERM

50V

10%

CRITICAL

C6613

1 2

50V

10%

402

CERM

0.0027UF

CRITICAL

C6614

1 2

10% 50V

CERM

402

0.0027UF

CRITICAL

C6633

1 2

402

CERM

50V

0.0027UF

CRITICAL

10%

C6634

1 2

10% 25V

0402

X7R

CRITICAL

0.022UF

C6623

1 2

X7R

10%

0402

25V

0.022UF

CRITICAL

C6624

1 2

0.022UF

CRITICAL

0402

25V

10% X7R

C6643

1 2

0402

X7R

10% 25V

0.022UF

CRITICAL

C6644

1 2

0402

25V

10% X7R

0.022UF

CRITICAL

C6653

1 2

X7R

0402

0.022UF

25V

10%

CRITICAL

C6654

1 2

100K

402

1/16W MF-LF

5%

R6601

1

2

0402

FERR-1000-OHM

L6602

1 2

57

0

5%

MF-LF

402

1/16W

R6602

1 2

1UF

402

X5R

10% 10V

NOSTUFF

C6600

1

2

POLY-TANT

2012-LLP

6.3V

47UF

CRITICAL

20%

C6612

1

2

47UF

20%

6.3V

2012-LLP

CRITICAL

POLY-TANT

C6632

1

2

NOSTUFF

BAT54XV2T1

SOD-523

D6600

12

CRITICAL

SSM2375

WLCSP

U6610

B2

A3

C1

A1

B1

B3

C3

A2

C2

0.1UF

402-1

X5R

16V

10%

C6611

1

2

0.1UF

10% 16V X5R 402-1

C6621

1

2

10% 16V X5R 402-1

0.1UF

C6631

1

2

10% 16V X5R 402-1

0.1UF

C6641

1

2

10% 16V X5R 402-1

0.1UF

C6651

1

2

SSM2375

WLCSP

CRITICAL

U6620

B2

A3

C1

A1

B1

B3

C3

A2

C2

WLCSP

CRITICAL

SSM2375

U6630

B2

A3

C1

A1

B1

B3

C3

A2

C2

SSM2375

WLCSP

CRITICAL

U6640

B2

A3

C1

A1

B1

B3

C3

A2

C2

SSM2375

CRITICAL

WLCSP

U6650

B2

A3

C1

A1

B1

B3

C3

A2

C2

402

MF-LF

1/16W

5%

47K

R6610

1

2

SYNC_DATE=10/22/2010

SYNC_MASTER=K92_KAVITHA

AUDIO:SPEAKER AMP

AUD_SPKRAMP_WIN_SHDN_L

AUD_HP_PORT_L_N

SPKRAMP_FL_IN_L_P

AUD_GPIO_2

AUD_GPIO_2_L

AUD_HP_PORT_L_P

PP5V_S0_AUDIO_AMP_L

SPKRAMP_BL_IN_L_P

PP5V_S0_AUDIO_AMP_R

SPKRAMP_FL_OUT_N

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SPKRAMP_FL_OUT_P

MIN_NECK_WIDTH=0.20 MM

SPKRAMP_BL_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRAMP_BL_OUT_N

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SPKRAMP_FR_OUT_N

TP_LFE_GAIN

TP_FL_GAIN

BL_GAIN

AUD_LO3_L_N

SPKRAMP_BL_IN_L_N

AUD_GPIO_3

SSM2375BL_IN_P SSM2375BL_IN_N

AUD_SPKRAMP_MAC_SHDN_L

SSM2375FL_IN_N

TP_FR_GAIN

TP_BR_GAIN

AUD_LO3_L_P

AUD_LO1_R_N

SPKRAMP_BR_IN_L_N

SPKRAMP_FR_IN_L_N

AUD_LO3_R_N

AUD_LO2_R_N

SPKRAMP_BR_IN_L_P

SSM2375FR_IN_P

SPKRAMP_LFE_IN_L_P

AUD_LO2_R_P

SPKRAMP_LFE_IN_L_N

AUD_LO1_R_P

AUD_LO3_R_P

SSM2375LFE_IN_P

AUD_SPKRAMP_MAC_SHDN_L

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SPKRAMP_BR_OUT_N

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRAMP_BR_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SPKRAMP_FR_OUT_P

SPKRAMP_LFE_OUT_N

MIN_LINE_WIDTH=0.50 MM MIN_NECK_WIDTH=0.20 MM

SPKRAMP_FR_IN_L_P

AUD_SPKRAMP_WIN_SHDN_L

SSM2375FL_IN_P

PP5V_S0_AUDIO_AMP_L

SSM2375BR_IN_P

SPKRAMP_FL_IN_L_N

PP5V_S0_AUDIO_AMP_R

SSM2375BR_IN_N

SSM2375FR_IN_N

SSM2375LFE_IN_N

AUD_SPKRAMP_WIN_SHDN_L

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.50 MM

SPKRAMP_LFE_OUT_P

PP5V_S0_AUDIO_AMP_R

66 OF 132 60 OF 105

60

8

60

8

60

100

60

100

60

100

60

100

8

60

100

8

60

100

60

8

60

IN IN

OUT

IN

IN IN

OUT

IN IN

AUDIO

MICROPHONE

DETECT FOR PT

GROUND

RIGHT

LEFT

SWITCH

POF

SHIELD

SHELL

PINS

C - GND

A - VIN B - VCC

OPERATING VOLTAGE 3.3

GROUND

RIGHT

LEFT

SWITCH

DETECT FOR PT

AUDIO

PINS

SHELL

SHIELD

POF

A - VDD B - GND

C - VOUT

OPERATING VOLTAGE 3.3

OUT

IN

OUT

OUT OUT

OUT

BI

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

AUDIO JACK 2 LINE IN JACK, SPDIF RX

AUDIO JACK 1 LO/HP JACK, SPDIF TX

APN: 514-0632

APN: 518S0672

RETURN FOR HF NOISE

SPEAKER CONNECTORS

APN: 514-0633

APN: 518S0521

MIC CONNECTORS: single anlg mic + 1 dig mic

APN: 518S0521

APN: 518S0520

6

60

6

60

6

60

6

60

21

R6755

1/16W

10

MF-LF

5%

402

2

1

402

CRITICAL

DZ6704

6.8V-100PF

2

1

DZ6752

402

CRITICAL

6.8V-100PF

21

L6754

0402

600-OHM-300MA

6.8V-100PF

DZ6705

2

1

CRITICAL

402

DZ6702

CRITICAL

2

402

6.8V-100PF

1

2

1

402

6.8V-100PF

DZ6703

CRITICAL

2

1

DZ6750

SOD882

ESDALC5-1BM2

CRITICAL

2

1

DZ6751

402

6.8V-100PF

CRITICAL

59

FERR-1200-OHM-200MA

CRITICAL

0402

L6706

1 2

21

L6700

FERR-1000-OHM

0402

1

DZ6701

6.8V-100PF

402

CRITICAL

2

21

L6703

FERR-1000-OHM

0402

21

L6751

0402

FERR-1000-OHM

6

60

6

60

21

L6752

0402

FERR-1000-OHM

4

3

2

1

6

5

J6781

CRITICAL

M-RT-SM

78171-0004

21

L6753

FERR-1000-OHM

0402

6

60

6

60

62

2

1

C6781

5%

50V

CERM

100PF

NOSTUFF

402

2

1

C6782

CERM

5%

402

NOSTUFF

100PF

50V

2

1

C6783

5%

50V

CERM

402

100PF

NOSTUFF

2

1

C6784

5% CERM

402

100PF

NOSTUFF

50V

6

60

6

60

6

5

4

3

2

1

8

7

J6782

78171-6006

M-RT-SM

CRITICAL

9

8

7

6 5

4

3

2

13

12

11

10

1

J6700

CRITICAL

F-RT-TH

SPDIF-TX-K20

8

7

6

9

5

4

3

2

12

11

10

1

J6750

F-RT-TH

SPDIF-RX-K20

CRITICAL

21

L6702

FERR-1000-OHM

0402

62

57

CRITICAL

1

402

2

DZ6700

6.8V-100PF

2

1

C6700

402

10V

10% X5R

1UF

2

1

C6750

10% 10V X5R 402

1UF

62

21

R6750

5% 1/16W MF-LF

0

402

58

2

1

DZ6753

SOD882

ESDALC5-1BM2

CRITICAL

57

21

L6785

0402

600-OHM-300MA

21

L6784

600-OHM-300MA

0402

21

L6783

600-OHM-300MA

0402

62

100

62

100

4

3

2

1

6

5

J6783

CRITICAL

M-RT-SM

78171-0004

CRITICAL

3

2

1

5

4

J6780

78171-0003

M-RT-SM

62

21

XW6701

SM

21

XW6702

SM

CRITICAL

DX6706

SOD882

ESDALC5-1BM2

OMIT_TABLE

57

58

59

21

CRITICAL

0603

L6707

FERR-220-OHM-2.5A

FERR-220-OHM

21

L6705

0402

CRITICAL

21

L6704

CRITICAL

FERR-220-OHM

0402

62

21

R6701

10K

5%

MF-LF

402

1/16W

377S0112

1

EMC supressor

DX6706

SYNC_MASTER=K92_KAVITHA

AUDIO: JACKS

SYNC_DATE=11/02/2010

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ1_TIP

MIN_NECK_WIDTH=0.20MM

AUD_CONNJ1_RING

MIN_LINE_WIDTH=0.40MM

AUD_CONNJ1_TIPDET

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

AUD_SPDIF_OUT

MIN_NECK_WIDTH=0.20MM

AUD_CONNJ1_SLEEVE2

MIN_LINE_WIDTH=0.40MM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

AUD_CONNJ1_SLEEVE

PP3V3_S0

SPKRAMP_BL_OUT_N

AUD_LO_GND_R

PP3V3_S0

AUD_DMIC_SDA1

AUD_J1_SLEEVEDET_R

BI_MIC_SHIELD

BI_MIC_P

BI_MIC_N

HS_MIC_HI

SPKRAMP_BR_OUT_N

SPKRAMP_FR_OUT_N

SPKRAMP_FR_OUT_P

SPKRAMP_LFE_OUT_P

SPKRAMP_BL_OUT_P

SPKRAMP_FL_OUT_N

AUD_DMIC_SDA_BK

AUD_DMIC_CLK_BK

AUD_DMIC_PWR_BK

AUD_DMIC_CLK

AUD_LI_GND

AUD_HPAMP_OUTL

AUD_J2_OPT_OUT

GND_CHASSIS_AUDIO_JACK

AUD_SPDIF_IN

AUD_J1_PERIPHDET_R

AUD_J2_TIPDET_R

AUD_LI_INR

AUD_LI_INL

AUD_HPAMP_OUTR

MIN_LINE_WIDTH=0.40MM

AUD_CONNJ2_RING

MIN_NECK_WIDTH=0.20MM

SPKRAMP_BR_OUT_P

SPKRAMP_LFE_OUT_N

AUD_CONNJ2_TIP

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

AUD_CONNJ2_TIPDET

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ2_SLEEVE

AUD_J1_TIPDET_R

SPKRAMP_FL_OUT_P

HS_MIC_LO

MIN_LINE_WIDTH=0.40MM MIN_NECK_WIDTH=0.20MM

AUD_CONNJ1_SLEEVEDET

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM VOLTAGE=0V

GND_CHASSIS_AUDIO_JACK

PP3V3_S0

67 OF 132 61 OF 105

6 7

12 23 25 26 28

32 35 36 39 40 41 46 48 49

50 51 52 54 57 61

62 72 73 80 83 84 85 88 89

91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6

8

61

8

61

6 7

12 23 25 26

28 32 35 36 39 40

41 46 48 49 50

51 52 54 57 61 62

72 73 80 83 84

85 88 89 91

100

102

OUT

IN

D

SG

D

SG

D

SG

D

SG

D

G S

OUT

IN

OUT

IN

BI

OUT

IN

OUT

IN

D

SG

D

SG

OUT

CS

HDET

AGND

DGND

ENABLE

AVDD

SDA

BYPASS

DETECT

MICBIAS

INT*

SCL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

LINE IN

PORT B DETECT

(SPDIF DELEGATE)

(LINE OUT)

CONVERTER

0X03 (3)

CODEC OUTPUT SIGNAL PATHS

NC

0X0D (13,B,RIGHT)

GPIO_2 GPIO_2

N/A

MICBIAS (80%)

WIN SHDN

N/A

0X0D (B)

N/A

0x0F (15)

0X12 (12,C)

0X08 (8)

PIN COMPLEX

MIKEY

SPDIF IN INTERNAL MIC

N/A

FUNCTION

NC

PORT C DETECT (LINE IN)

VREF

MAC OS SHDN

CONVERTER

0X09 (9,V23)

0X02 (2)

0X04 (4)

PIN COMPLEX

GPIO_2

0x10 (16)

0X09 (9,A)

MIKEY

PORT A DETECT

0X03 (3)

SPEAKER LFE

0X05 (5)

SPEAKERS FL/FR

SPEAKERS BL/BR

0X0A (10,D)

0X02 (2)

FUNCTION HP/LINE OUT

0X02 (2)

VOLUME/MUTE

CODEC INPUT SIGNAL PATHS

0X07 (7) 0X06 (6) 0X06 (6)

0X0D (13,V22,B,LEFT)

N/A

GPIO_3

N/A

0X0B (11)

NC

"MIKEY"/EXTERNAL MICROPHONE

APN 353S2640

PLACE L6800/C6800 CLOSE TO Q6800/01/02

SPDIF OUT

0X04 (4)

0X02 (2) 0X09 (A)

DET ASSIGNMENT

KEEP DET TRACE AS SHORT AS POSS

EXTERNAL MIC

EXTRACTION NOTIFICATION CKT

0X12 (C)

DET ASSIGNMENT

INTERNAL MICROPHONE

0.1UF

402

20% CERM

10V

C6801

1

2

402

1/16W MF-LF

5%

47K

R6802

1 2

57 62

61

10%

0.1UF

402-1

X5R

16V

C6800

1

2

0402

FERR-1000-OHM

L6800

1 2

402

1/16W

100K

5%

MF-LF

R6803

1 2

402

220K

5% 1/16W MF-LF

R6804

1

2

10%

402

16V CERM

0.01UF

C6802

1

2

61 62

0.1UF

402

CERM

20%

10V

C6811

1

2

402

270K

MF-LF

5% 1/16W

R6811

1

2

402

47K

MF-LF

5%

1/16W

R6812

1 2

61

SOT563

SSM6N15FEAPE

Q6800

3

5

4

SSM6N15FEAPE

SOT563

Q6800

6

2

1

Q6801

SOT563

SSM6N15FEAPE

3

5

4

SSM6N15FEAPE

SOT563

Q6801

6

2

1

SOD-VESM-HF

SSM3K15FV

Q6802

3

1

2

57 62

1/16W

402

2.2K

5%

R6855

1 2

MF-LF

402

5% 1/16W MF-LF

100K

R6852

1

2

57

100

16V

CRITICAL

TANT-POLY 2012-LLP

20%

C6854

1

2

10UF

10%

402

25V X7R

0.01UF

C6882

1

2

FERR-1000-OHM

0402

L6880

1 2

10UF

X5R

CRITICAL

20%

6.3V 603

C6880

1

2

402

0

1/16W MF-LF

5%

R6890

1 2

402

5%

0

1/16W MF-LF

R6891

1 2

402

0

1/16W MF-LF

5%

R6892

1 2

MF-LF

1/16W

402

0

5%

R6893

1 2

100K

402

1/16W MF-LF

5%

R6880

1

2

402

MF-LF

1/16W

5%

2.2K

R6882

1

2

4.7UF

20%

6.3V TANT 603-HF

CRITICAL

C6883

1

2

6

16 23 26 28 30 32 41 48 89 95

19 23

6

16 23 26 28 30 32 41 48 89 95

18

402

5% 50V CERM

NOSTUFF

15PF

C6887

1

2

402

5%

100K

1/16W MF-LF

R6883

1

2

61

57

100

50V

10%

402

CERM

0.001UF

C6881

1

2

NOSTUFF

1/16W MF-LF

0

5%

402

R6884

1

2

402

5%

MF-LF

1/16W

2.2K

R6885

1 2

402

1K

5% 1/16W MF-LF

R6881

1

2

62

402

5%

1/16W

15K

MF-LF

R6860

1 2

0.1UF

402

CERM

10V

20%

C6860

1

2

SOT563

SSM6N15FEAPE

Q6803

3

5

4

402

5% MF-LF

220K

1/16W

R6861

1

2

SSM6N15FEAPE

SOT563

Q6803

6

2

1

402

5% 1/16W MF-LF

100K

R6862

1

2

402

5% 1/16W MF-LF

0

R6863

1 2

18

10%

402

0.0082UF

X7R

25V

C6886

1

2

57

100

XW6800

SM

21

SM

XW6850

1 2

57

100

3.40K

MF-LF

1% 1/16W

402

R6851

1

2

402

1% MF-LF

1/16W

R6850

1

2

3.40K

10%

0.0082UF

25V X7R 402

C6852

1

2

10%

402

X5R

CRITICAL

0.47UF

10V

C6850

1 2

C6851

CRITICAL

10% 10V

402

0.47UF

X5R

1 2

0.47UF

10%

402

X5R

CRITICAL

10V

C6884

1 2

10%

402

X5R

10V

CRITICAL

0.47UF

C6885

1 2

1/16W

10K

1%

MF-LF

402

R6813

1

2

402

1/16W

39.2K

MF-LF

1%

R6806

1

2

402

1% MF-LF

1/16W

20.0K

R6805

1

2

402

MF-LF

270K

5% 1/16W

R6801

1

2

WCSP

CRITICAL

CD3282A1

U6880

D2

A2

D1

B2

B1

C2

A3

A1

D3

C1

C3 B3

402

MF-LF

1%

10K

1/16W

R6886

1

2

MF-LF

402

0

1/16W

5%

R6894

1 2

XW6851

SM

SYNC_MASTER=K92_KAVITHA

SYNC_DATE=11/22/2010

AUDIO: JACK TRANSLATORS

BI_MIC_SHIELD

AUD_MIC_INR_P

GND_AUDIO_CODEC

HS_RST_L

BI_MIC_N

AUD_I2C_INT_L

AUD_IPHS_SWITCH_EN

HS_MIC_HI_R

AUD_MIC_INR_N

PP3V3_S0_AUDIO_F

HS_MIC_LO

AUD_MIC_INL_N

GND_AUDIO_CODEC

VOLTAGE=3.3V

PP3V3_S0_HS_RX

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

PP3V3_S0_AUDIO_F

MIN_LINE_WIDTH=0.20MM MIN_NECK_WIDTH=0.15MM

VOLTAGE=3.3V

AUD_OUTJACK_INSERT_L

AUD_IP_PERIPHERAL_DET

AUD_MIC_INL_P

HS_INT_L

HS_SDA

SMBUS_PCH_CLK

HS_SCL

PP3V3_S0

HS_MIC_BIAS

AUD_J1_SLEEVEDET_R

AUD_J1_PERIPHDET_INV

AUD_J1_SLEEVEDET_INV

PERIPHDET_FILT

AUD_J1_PERIPHDET_R

INT_MIC_BIAS

HS_SW_DET HS_RX_BP

AUD_PORTA_DET_L

AUD_SENSE_A

AUD_J1_DET_RC

GND_AUDIO_CODEC

AUD_SENSE_A

AUD_INJACK_INSERT_L

GND_AUDIO_CODEC

PP3V3_S0

PP3V3_S0_AUDIO_F

GND_AUDIO_CODEC

AUD_J2_DET_RC

PP3V3_S0_AUDIO_F

AUD_J1_SLEEVEDET_R

AUD_CODEC_MICBIAS

GND_AUDIO_CODEC

AUD_PERIPH_DET_R

AUD_J2_TIPDET_R

GND_AUDIO_CODEC

AUD_J1_TIPDET_R

PP3V3_S0_AUDIO_F

AUD_PORTB_DET_L

GND_AUDIO_CODEC

PERIPHDET_UNFILT

SMBUS_PCH_DATA

AUD_J1_PERIPHDET_R

HS_MIC_HI

INT_MIC_RET

BI_MIC_P

68 OF 132 62 OF 105

61

57 58 62

61

100

57 58 62

62

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

61 62

57 58 62

6 7

12 23 25 26 28 32 35 36 39 40 41

46 48 49 50 51 52 54 57 61 62 72 73 80

83 84 85 88 89 91

100 102

62

57 58 62

62

57 58 62

62

57 58 62

61 62

61

100

IN

BI

OUT

Y

B

A

IN

VCC

EXT INT

NC

GND

NC

BYP

GND

REF

TON

SW

FB

EN

REF3

THRM

VIN

VCC

PAD

P3 P4 P5 P6 P7 P8

P1 P2

P9

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Supply needs to guarantee 3.31V delivered to SMC VRef generator

BIL Connector

1-Wire OverVoltage & ESD Protection

MagSafe DC Power Jack

PWR

GND

518S0720

SIG

f = 470 kHz

Vout = 3.425

300mA max output

353S2776

BATTERY CONNECTOR

3.425V "G3Hot" Supply

GND

518-0375

6

45 48 63 64 98

CRITICAL

1206-1

6AMP-24V

F6905

1 2

50V

20% CERM

603

0.01UF

C6905

1

2

45

6

45 46

50V

10%

402

CERM

0.001UF

C6954

1

2

402

47PF

CERM

5% 50V

C6953

1

2

47PF

402

CERM

5%

50V

C6952

1

2

CERM

50V

402

10%

0.001UF

C6955

1

2

CRITICAL

M-RT-SM

78048-0573

J6900

1

2 3

4 5

CRITICAL

FF18-5A-R11AD-B-3H

F-RT-SM

J6995

1

2

3 4

5

5%

402

MF-LF

2.0K

1/16W

R6929

1

2

CRITICAL

SOT665

TC7SZ08AFEAPE

U6901

2

1

3

5

4

PLACE_NEAR=U6901.5:3mm

0.1UF

CERM

402

20% 10V

C6908

1

2

45 46 49 64

SC70-5

MAX9940

U6900

5

2

4

3

1

CRITICAL

CRITICAL NO STUFF

RCLAMP2402B

SC-75

D6900

3

1

2

805

MF

1/3W

1%

47

R6990

1 2

10% 35V

X5R-CERM

4.7UF

0805

1

2

C6990

CRITICAL

SOT-323

BAT30CWFILM

D6990

1

2

3

1M

MF-LF

1/16W

5%

402

R6995

1

2

402

25V

1UF

X5R

10%

C6991

1

2

CRITICAL

PM6640

DFN

9

4

2

5

1

10

6

11

3

8

7

U6990

16V

402-1

10%

0.1UF

X5R

C6994

1

2

C6999

22UF

20%

6.3V X5R-CERM1

1

0603

2

CRITICAL

D52LC-SM

L6995

1 2

33UH-20%-0.44A-0.455OHM

0.1UF

10V

CERM

20% 402

C6995

1

2

M-RT-TH

J6950

10

11

12 13

1

2

3 4

5

6 7

8

9

BAT-K90-K91-K92

CRITICAL

402

10%

0.1UF

X5R

25V

C6950

1

2

10%

X5R

25V

603-1

1UF

C6960

1

2

CRITICAL

RCLAMP2402B

SC-75

D6950

3

1

2

402

1/16W

5%

R6950

1

2

10K

MF-LF

6

45 48 63 64 98

SYNC_DATE=06/28/2010

DC-In & Battery Connectors

SYNC_MASTER=K92_CHANG

PP3V42_G3H

SMBUS_SMC_BSA_SDA

PPVBAT_G3H_CONN

SMBUS_SMC_BSA_SCL SYS_DETECT_L

P3V42G3H_SW

DIDT=TRUE

MIN_LINE_WIDTH=0.5 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

PPDCIN_S5_P3V42G3H

VOLTAGE=18.5V

PP18V5_DCIN_FUSE

MIN_NECK_WIDTH=0.20mm VOLTAGE=18.5V

MIN_LINE_WIDTH=1mm

P3V42G3H_REF3

P3V42G3H_FB

P3V42G3H_TON

PPDCIN_G3H

SMBUS_SMC_BSA_SDA SMBUS_SMC_BSA_SCL SMC_BIL_BUTTON_L

PP3V42_G3H

SMC_BC_ACOK

SYS_ONEWIRE

PP3V42_G3H

SMC_BC_ACOK_BUF

PPDCIN_G3H

ADAPTER_SENSE

VOLTAGE=18.5V

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PPBUS_G3H

69 OF 132 63 OF 105

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 45 48 63 64 98

6

64

6

45 48 63 64 98

6

6 7

49 63 64

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

25 42 44 45 46 47 48 53 63 64 73

104

6 7

49 63 64

6

6 7 8

35 39 49 50 64 90

OUT

IN BI

OUT

AMON BMON ACOK

LGATE

PHASE

BOOT

SGATE AGATE

CSIP CSIN

DCIN

VNEG CSOP CSON

THRM_PAD

PGND

VDDP

VDD

BGATE

UGATE ICOMP VCOMP

ACIN

SDA VFRQ CELL

VHST

SCL

SMB_RST_N

IN

S

G

D

G

D

S

IN

NC

G

S

D

S

D

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Max Current = 8A (L7030 limit) f = 400 kHz

(CHGR_SGATE)

TO/FROM BATTERY

Divider sets ACIN threshold at 13.55V

sparkitecture requirements

(CHGR_DCIN)

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

FROM ADAPTER

(CHGR_AGATE)

ACIN pin threshold is 3.2V, +/- 50mV

30mA max load

(CHGR_BGATE)

(AGND)

(GND)

(CHGR_CSO_P)

36V/V

(OD)

TO SYSTEM

20V/V

(PPVBAT_G3H_CHGR_R)

Input impedance of ~40K meets

Inrush Limiter

Reverse-Current Protection

353S2929

1%

9.31K

1/16W MF-LF 402

R7011

1

2

0.068UF

CERM

10V 402

10%

C7042

1

2

470PF

50V CERM 402

10%

C7016

1

2

1%

MF-LF

1/16W

3.01K

402

R7016

1

2

10%

402

50V

X7R-CERM

220PF

C7015

1

2

402

1/16W MF-LF

5%

330K

R7015

1

2

10V

1UF

X5R 402

10%

C7002

1

2

10V

1UF

402-1

X5R

10%

C7000

1

2

MF-LF

1/16W

5%

402

4.7

R7001

1 2

30.1K

1% MF-LF

1/16W 402

R7010

1

2

CERM

0.01uF

16V 402

10%

C7057

1

2

16V X5R

402-1

0.1UF

10%

C7056

1

2

SM

PLACE_NEAR=U7000.29:1mm PLACE_NEAR=U7000.22:1mm

XW7000

1 2

402

10V

1UF

X5R

10%

C7001

1

2

25V X5R 402

0.1UF

10%

C7021

1

2

25V X5R 402

0.1UF

10%

C7022

1

2

10V 402

10%

0.047UF

CERM

C7020

1

2

402

0.22UF

CERM

10V

PLACE_NEAR=U7000.25:2mm

10%

C7025

1

2

CRITICAL

RJK0305DPB

LFPAK-HF

Q7035

5

4

1 2 3

1/16W

10

MF-LF

5%

402

R7022

1 2

MF-LF

10

1/16W

402

5%

R7021

1 2

CASE-D2-SM

POLY-TANT

25V

CRITICAL 22UF

20%

C7030

1

2

CASE-D2-SM

20% POLY-TANT

25V

22UF

CRITICAL

C7031

1

2

5%

1/16W

402

2.2

MF-LF

R7051

1 2

MF-LF

5%

1/16W

0

402

R7052

1 2

20%

0.22UF

603

25V X5R

C7005

1

2

50

6

45 48 63 98

6

45 48 63 98

CERM

0.01UF

16V 402

10%

C7011

1

2

1UF

16V X5R 402

10%

C7050

1

2

50V

CERM

0.001UF

402

10%

C7026

1

2

45 46 49 63

CRITICAL

0612

MF-LF

1W

0.5%

0.020

R7020

123

4

50V

0.001UF

X7R 402

10%

C7037

1

2

CERM

NO STUFF

50V

470PF

402

10%

C7039

1

2

NO STUFF

180

5%

MF-LF

1/10W

603

R7039

1

2

0.001UF

50V X7R 402

10%

C7045

1

2

ISL6259

CRITICAL

TQFN

U7000

3

14

1

9

16

15

25

6

27

28

17

18

2

5

21

22

23

11 10

26

13

29

24

7

19

20

4

12

8

1/16W

100K

5% MF-LF

NO STUFF

402

R7002

1

2

73

SO-8

SI7137DP

CRITICAL

Q7055

5

4

1 2 3

CRITICAL

BAT30CWFILM

SOT-323

D7005

1

2

3

1/16W MF-LF

1%

1K

402

R7012

1

2

4.7UH-10.2A

FDA1254F-SM

CRITICAL

L7030

1

2

3

LFPAK-SM

CRITICAL

RJK0332DPB-01

Q7030

5

4

1 2 3

CASE-D2-SM

POLY-TANT

25V

CRITICAL

20%

22UF

C7040

1

2

1/16W

20

402

5%

MF-LF

R7005

1 2

25V

1UF

603-1

X5R

10%

C7035

1

2

25V

1UF

603-1

X5R

10%

C7036

1

2

603-1

1UF

25V X5R

10%

C7055

1

2

5%

0

1/16W MF-LF

402

R7000

1 2

10%

0.1UF

402

X5R

25V

C7085

1

2

402

MF-LF

1/16W

1%

470K

R7085

1

2

402

MF-LF

332K

1/16W

1%

R7086

1

2

MF-LF

1/16W

5%

62K

402

R7081

1

2

5%

100K

402

MF-LF

1/16W

R7080

1

2

DIRECTFET-MC

CRITICAL

IRF9395TRPBF

Q7080

879

10

6

3

415

2

1206

8AMP-24V

CRITICAL

F7041

1 2

CRITICAL

8AMP-24V

1206

F7040

1 2

1W

1% MF

0.005

CRITICAL

0612

R7050

12 34

PBus Supply & Battery Charger

SYNC_MASTER=K91_CHANG

SYNC_DATE=07/21/2010

PPDCIN_G3H

PP5V1_CHGR_VDD

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.2 mm VOLTAGE=5.1V

CHGR_DCIN

SMBUS_SMC_BSA_SDA

CHGR_SGATE

CHGR_CSI_N

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_AGATE_DIV

CHGR_VCOMP_R

CHGR_VCOMP

CHGR_CSO_N

CHGR_VNEG

SMBUS_SMC_BSA_SCL

CHGR_VNEG_R

CHGR_PHASE_RC

DIDT=TRUE

CHGR_ICOMP

SMC_BC_ACOK

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

CHGR_BOOT

DIDT=TRUE

GND_CHGR_AGND

SMC_RESET_L

CHGR_ACIN

PP3V42_G3H

CHGR_VFRQ

CHGR_RST_L

CHGR_AMON

VOLTAGE=0V

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

CHGR_CSI_P

CHGR_CELL

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CONN

PPBUS_G3H

CHGR_DCIN_D_R

GATE_NODE=TRUE

DIDT=TRUE

CHGR_LGATE

MIN_NECK_WIDTH=0.2 mmMIN_LINE_WIDTH=0.6 mm

CHGR_BMON

CHGR_CSO_P CHGR_BGATE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

SWITCH_NODE=TRUE

CHGR_PHASE

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm

PPVBAT_G3H_CHGR_REG

PPVBAT_G3H_CHGR_R

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

CHGR_CSO_R_N

CHGR_CSO_R_P

CHGR_UGATE

GATE_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.3 mm

CHGR_SGATE_DIV

CHGR_CSI_R_P

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

PPDCIN_G3H_INRUSH

CHGR_CSI_R_N

MIN_LINE_WIDTH=0.6 mm VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

PPDCIN_G3H_CHGR

CHGR_AGATE

70 OF 132 64 OF 105

6 7

49 63

98

64

6 7

25 42 44 45 46 47 48 53 63 73

104

64

98

6

63

6 7 8

35 39 49 50 63 90

98

50

100

50

100

OUT

IN

FB

EN

PVCC

VCC

SREF

VO

OCSET

PGOOD

FSEL

RTN

PHASE

LGATE

UGATE

BOOT

PGND

GND

SET0

SET1

VID0

VID1

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

6A Max Output f = 300 kHz

(VCCSAS0_VO)

(VCCSAS0_OCSET)

1 0 0.8V

0 0 0.9V

VID1 VID0 Voltage

OCP = R7141 x 8.5uA / R7140 OCP = 8.5A

73

SM

PLACE_NEAR=U7100.3:1mm

XW7100

1 2

5%

MF-LF

2.2

1/16W

402

R7101

1

2

10UF

20% X5R

10V 603

C7101

1

2

603

1/10W

5%

MF-LF

0

R7130

1

2

10%

402

0.22UF

CERM

10V

C7130

1

2

1000PF

NP0-C0G

402

5%

25V

C7140

12

402

1K

1% 1/16W MF-LF

R7141

1

2

402

1K

1% 1/16W MF-LF

R7142

1

2

PLACE_NEAR=Q7100.2:1.5mm

402

NP0-C0G

1000PF

5% 25V

C7122

1

2

0612

0.001

CRITICAL

1% 1W

MF-1

R7140

1 2 3 4

SIZ700DT

POWERPAIR-6X3.7

CRITICAL

Q7100

1

6

4 5

2 3 7

8

1.0UH-7.7A

CRITICAL

FDV0630H-SM

L7100

1 2

10%

X5R-CERM

16V

CRITICAL

10UF

0805

C7120

1

2

16V

10%

0.1UF

X7R-CERM

402

C7121

1

2

402

5% NP0-C0G

25V

1000PF

C7105

1

2

OMIT_TABLE

ISL95870A

UTQFN

CRITICAL

U7100

1815

10

13

3

1

11

2

14

16

20

4

8

9

7

17

19

6

5

12

MF-LF

1/16W

1%

402

113K

R7147

1

2

MF-LF

1/16W

1%

140K

402

R7148

1

2

MF-LF

1/16W

1%

47.5K

402

R7149

1

2

12

0805

10%

X5R-CERM

16V

CRITICAL

10UF

C7119

1

2

402

16V

10%

0.022UF

CERM-X5R

C7103

1

2

PLACE_NEAR=C1763.2:3mm

SM

XW7101

1

2

402

MF-LF

1/16W

5%

0

R7103

1

2

X5R 603

2.2UF

16V

10%

C7102

1

2

IC,ISL95870A,PWM,2BIT-VID,RMOT-SNSE,20P

U7100353S3074 1 CRITICAL

SYNC_DATE=07/21/2010

SYNC_MASTER=K91_CHANG

System Agent Supply

MIN_NECK_WIDTH=0.2 mm

VCCSAS0_BOOT_RC

DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

VCCSAS0_CS_P

PPVIN_S5_HS_COMPUTING_ISNS PP5V_S0

PPVCCSA_S0_REG_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.05V

VCCSAS0_CS_N

MIN_NECK_WIDTH=0.2 mm SWITCH_NODE=TRUE DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_LL

CPU_VCCSA_VID<1>

DIDT=TRUE

VCCSAS0_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE

VCCSAS0_DRVH

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

PPVCCSA_S0_CPU

VCCSAS0_SET1

VCCSAS0_SREF

VCCSAS0_OCSET

VCCSAS0_FSEL

MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V

PP5V_S0_VCCSAS0_VCC

MIN_NECK_WIDTH=0.2 mm

VCCSAS0_RTN

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VCCSAS0_AGND

VCCSAS0_SET0

PVCCSA_EN

VCCSAS0_VBST

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

PVCCSA_PGOOD

VCCSAS0_VO

CPU_VCCSASENSE

71 OF 132 65 OF 105

49

100

7

50 67 68 69 70

6 7 8

22 41 47 52 54 68 69 70 73 87

104

105

49

100

7

12 15

OUT

IN

EN

EN2EN1

DRVL2

SKIPSEL1 SKIPSEL2

DRVL1

V5SW

VBST2VBST1

VREG5

VREF2

VIN

THRM_PAD

SW2SW1

RF

PGOOD2PGOOD1

GND

DRVH2DRVH1

CSP2 CSN2CSN1

COMP2COMP1

VREG3

VFB1 VFB2

OCSEL

MODE

CSP1

IN

VSW

PGND

TGR

TG

BG

VIN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

f = 400 kHZ

Vout = 5V 100mA MAX OUTPUT

f = 400 kHZ

(P5VP3V3_VREF2)

Vout = 5.0V Vout = 3.3V

14.4A MAX OUTPUT

10A MAX OUTPUT

(P5VP3V3_VREF2)

10% 25V

603-1

1UF

X5R

C7200

1

2

CRITICAL

2.2UH-14A

IHLP2525CZ-SM1

L7260

2

1

603-1

50V

10% X7R

0.1UF

C7264

1

2

10UF

20%

6.3V 603

X5R

C7290

1

2

10% 50V X7R

0.1UF

603-1

C7224

1

2

CRITICAL

CASE-D3L-SM1

6.3V

20%

330UF

POLY-TANT

C7252

1

2

20% 10V X5R 805

10UF

C7250

1

2

10% 25V X5R 603-1

1UF

C7281

1

2

402

X5R-CERM

20%

2.2UF

10V

C7203

1

2

6.3V

10UF

603

20% X5R

C7205

1

2

402

MF-LF

1/16W

1%

249K

R7206

1

2

73

PLACE_NEAR=L7260.2:3mm

SM

XW7261

1

2

0.22UF

402

CERM

10V

10%

C7201

1

2

402

MF-LF

23.2K

1%

1/16W

R7260

1

2

10K

1% 1/16W MF-LF

402

R7261

1

2

402

MF-LF

1/16W

1%

40.2K

R7220

1

2

10K

1% 1/16W MF-LF 402

R7221

1

2

CRITICAL

CASE-D2E-SM

POLY-TANT

16V

20%

68UF

C7280

1

2

CRITICAL

CASE-D2E-SM

POLY-TANT

16V

20%

68UF

C7240

1

2

0.1UF

10% 25V X5R 402

C7288

1 2

PLACE_NEAR=L7260.1:3mm

SM

XW7260

1

2

0.1UF

402-1

10% 16V X5R

C7218

1 2

1%

5.11K

402

MF-LF

1/16W

R7247

1 2

MF-LF

1/16W

1%

402

9.09K

R7256

1

2

PLACE_NEAR=L7220.1:3mm

SM

XW7220

1

2

PLACE_NEAR=L7220.2:3mm

SM

XW7221

1

2

1%

10K

402

MF-LF

1/16W

R7236

1

2

20.0K

402

MF-LF

1/16W

NO STUFF

1%

R7237

1

2

10% 100V CERM 402

4700PF

C7236

1

2

5%

50V

CERM

402

47PF

C7237

1

2

PLACE_NEAR=L7260.2:3mm

SM

XW7262

1

2

PLACE_NEAR=L7220.1:3mm

SM

XW7222

1

2

CASE-D3L-SM1

6.3V

20%

330UF

CRITICAL

POLY-TANT

C7292

1

2

NO STUFF

1%

MF-LF

402

20.0K

1/16W

R7239

1

2

402

50V CERM

47PF

5%

C7239

1

2

402

10K

1% MF-LF

1/16W

R7238

1

2

4700PF

402

CERM

100V

10%

C7238

1

2

17 29 42 45 73

402

0

5% MF-LF

1/16W

R7249

1

2

0.0033UF

402

CERM

50V

10%

NO STUFF

C7299

1

2

NO STUFF

603

MF-LF

1/10W

5%

1

R7299

1

2

603

MF-LF

5%

10

NO STUFF

1/10W

R7298

1

2

402

X7R

50V

10%

0.001UF

C7272

1

2

10% 50V X7R 402

0.001UF

C7283

1

2

0.001UF

402

X7R

50V

10%

C7270

1

2

10% 50V X7R 402

0.001UF

C7271

1

2

CRITICAL

TPS51980

QFN

U7201

10

15

8

17

7

18

1

24

30

27

12

4

21

28

11

14

5

20

3

6

19

32

25

33

2

31

26

9

16

23

13

22

29

16V

CASE-D2E-SM

20%

CRITICAL

68UF

POLY-TANT

C7242

1

2

CRITICAL

CASE-D2E-SM

POLY-TANT

16V

20%

68UF

C7282

1

2

45 73

RJK0214DPA

WPAK2

CRITICAL

Q7260

2

1

6

7

3 4 5

CRITICAL

SON5X6

CSD58864Q5D

Q7220

5

9

3

4

1

6 7 8

1%

1.07K

1/16W

402

MF-LF

R7246

1 2

6.65K

402

MF-LF

1/16W

1%

R7216

1

2

1/16W 402

MF-LF

5%

0

R7263

1

2

MF-LF

1/16W

5%

402

4.7

R7244

1

2

X5R

25V

10%

1UF

603-1

C7241

1

2

PIMB104E2R2MS-SM

2.2UH-22A-5.8M-OHM

CRITICAL

L7220

1

2

73

45 73

MF-LF

5%

0

NO STUFF

402

1/16W

R7248

1

2

X7R

NO STUFF

10% 50V

402

0.001UF

C7298

1

2

5V / 3.3V Power Supply

SYNC_MASTER=K92_ERIC SYNC_DATE=08/30/2010

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS3_TG

P5VS3_CSP1 P5VS3_CSN1

P5VS3_MODE

P5VS3_COMP1_R

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS3_VBST

DIDT=TRUE

GATE_NODE=TRUE

P5VS3_DRVL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_S5_ISNS_R

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

P3V3S5_SNUBR

MIN_LINE_WIDTH=0.6 mm

P3V3S5_COMP2_R

PP5V_S5

MIN_LINE_WIDTH=0.6 mm

P5VS3_SNUBR

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS3_VSW

DIDT=TRUE

PP5V_S3_ISNS_R

P3V3S5_VFB2_R

P5VS3_VFB1_R

PP5V_S3_ISNS_R

SMC_PM_G2_EN

S5_PWRGD

P5VS3_DRVH

DIDT=TRUE

GATE_NODE=TRUEMIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

P3V3S5_EN

MIN_LINE_WIDTH=0.6 mm

P5VS3_LL

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P5VS3_PGOOD

P5VS3_COMP1

P5VS3_CSP1_R

P3V3S5_CSP2_R

P5VS3_VFB1

PM_SLP_S4_L

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVH

PPVIN_S5_HS_OTHER_ISNS

P5VP3V3_VREG3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_VBST

DIDT=TRUE

P3V3S5_TG

MIN_LINE_WIDTH=0.6 mm DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P3V3S5_LL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

DIDT=TRUE

P3V3S5_DRVL P3V3S5_CSP2

P3V3S5_CSN2 P3V3S5_RF

P3V3S5_VFB2 P3V3S5_COMP2

P5VP3V3_VREF2

72 OF 132 66 OF 105

7

104

7

54 72

103 104

7

66

104

7

66

104

7

50

VSW

PGND

TGR

TG

BG

VIN

IN

OUT

V5IN

REFIN

S5

VREF

S3

MODE TRIP

SW

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

DRVH

VBST

VLDOIN

THRM

VTT

GND

PGND

PADGND

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(DDRREG_VDDQSNS)

C7360, C7361 close to memory

(VDDQ/VTTREF Enable)

(DDRREG_DRVH)

18A max output

(DDRREG_DRVL)

(DDRREG_LL)

Vout = 1.5V

f = 400 kHz

(Q7335 limit)

(VTT Enable)

10mA max load

603

20% X5R

10UF

10V

C7300

1

2

CRITICAL

68UF

CASE-D2E-SM

16V

POLY-TANT

20%

C7330

1

2

SON5X6

CSD58864Q5D

CRITICAL

Q7330

5

9

3

4

1

6 7 8

4.7

402

1/16W

5%

MF-LF

R7330

1 2

68UF

CASE-D2E-SM

16V

CRITICAL

20%

POLY-TANT

C7331

1

2

25V

10%

603-1

X5R

1UF

C7332

1

2

10%

0.1UF

X7R

603-1

50V

C7325

1 2

0.001UF

X7R 402

10% 50V

C7333

1

2

CASE-B4-SM

2V TANT

270UF

20%

CRITICAL

C7340

1

2

FDU1040D-SM

CRITICAL

1.0UH-21A

L7330

1 2

CASE-B4-SM

CRITICAL

20%

270UF

TANT

2V

C7341

1

2

10UF

X5R 603

20%

6.3V

C7345

1

2

50V

10%

402

X7R

0.001UF

C7346

1

2

SM

XW7301

1

2

73

CRITICAL

1W

MF-1

0.001

1%

0612

R7350

2 1

4 3

49

100

49

100

TPS51916

CRITICAL

QFN

U7300

14

11

7

19

10

20

8

17 16

13

21

18

12 15

9

2

6

3

4

5

1

91

PLACE_NEAR=C7361.1:3mm

SM

XW7360

1 2

SM

PLACE_NEAR=U7300.7:1mm

XW7300

1

2

10V

CERM

0.22UF

402

10%

C7350

1

2

10UF

CRITICAL

20%

6.3V X5R 603

PLACE_NEAR=C3101.1:1mm

C7360

1

2

8

29

10% X5R

16V 402

0.1UF

C7315

1

2

6.3V

10UF

PLACE_NEAR=C3101.1:3mm

CRITICAL

20% X5R

603

C7361

1

2

MF-LF

1/16W 402

1%

200K

R7317

1

2

MF-LF

1/16W 402

1%

47.5K

R7318

1

2

20.0K

1% 1/16W MF-LF 402

R7315

1

2

402

MF-LF

1/16W

100K

1%

R7316

1

2

0.01UF

10% 16V CERM 402

C7316

1

2

X5R

10UF

603

10V

20%

C7301

1

2

1UF

X5R

10% 25V

603-1

C7334

1

2

1.5V DDR3 Supply

SYNC_MASTER=K91_CHANG

SYNC_DATE=07/21/2010

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm VOLTAGE=0V

GND_DDRREG_SGND

DDRREG_FB

TP_DDRREG_PGOOD

MEMVTT_EN DDRREG_EN

DDRREG_TRIP

ISNS_1V5_S3_N

ISNS_1V5_S3_P

PP1V5_S3

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_DRVH_R

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_VSW

DIDT=TRUE

SWITCH_NODE=TRUE

DDRREG_MODE

DDRREG_1V8_VREF

PPVTTDDR_S3

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

GATE_NODE=TRUE

DIDT=TRUE

DDRREG_DRVH

SWITCH_NODE=TRUE

DIDT=TRUE

DDRREG_LL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.17 mm

PP5V_S3

PP0V75_S0_DDRVTT

GATE_NODE=TRUE

DDRREG_DRVL

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DDRREG_VTTSNS

MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST

MIN_NECK_WIDTH=0.17 mm

PPVIN_S5_HS_COMPUTING_ISNS

VOLTAGE=1.5V MIN_NECK_WIDTH=0.1 MM MIN_LINE_WIDTH=0.8 MM

PPDDR_S3_REG_R

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

DDRREG_VDDQSNS

PP1V5_S3

73 OF 132 67 OF 105

30

7

26 28 29 67 72

6 7

30

6 7

29 31 42 43 44 46 72 82

104

7

50 65 68 69 70

7

26 28 29 67 72

IN IN IN

OUT OUT

IN

OUT

OUT OUT OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

IN

OUT

IMAXA

SR

IMAXB

ALERT*

THERMA THERMB

VDIO

POKB

CLK

EN

POKA

CSPA3 VRHOT*

DRVPWMA

GNDSB

GNDSA

THRM

CSPB1

DHB LXB

BSTB

DLA2

DLB

CSNB

FBB

LXA1

DHA1

BSTA1

TON

DLA1

CSPA1

CSPAAVE

FBA

CSNA

BSTA2

CSPA2

DHA2 LXA2

VCC

VDDA

VDDB

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

21

R7401

402

10

5%

MF-LF

1/16W

2

1

C7401

402

10V

X5R-CERM

2.2UF

20%

2

1

C7402

20%

402

10V X5R-CERM

PLACE_NEAR=U7400.24:2mm

2.2UF

12 92

2

1

C7414

CERM 402

50V

5%

100PF

NO STUFF

2

1

C7404

0402

5%

2200PF

CERM

10V

SIGNAL_MODEL=EMPTY

402

MF-LF

21

R7406

300

5%

1/16W

R7410

21

402

1

5%

MF-LF

1/16W

SIGNAL_MODEL=EMPTY

C7408

150PF

402

5%

50V

CERM

10%

CERM

402

C7409

470PF

21

50V

NO STUFF

SIGNAL_MODEL=EMPTY

40.2K

21

R7409

MF-LF

1/16W

1%

402

91

73

10 46 92

69

2 1

XW7400

SM

MF-LF

21

R7402

402

1%

1/16W

90.9K

2

1

R7468

402

5.76K

1% 1/16W MF-LF

2

1

R7466

5.76K

402

1% 1/16W MF-LF

2

1

C7403

X5R-CERM

20%

402

PLACE_NEAR=U7400.15:2mm

2.2UF

10V

2

1

R7462

215K

402

MF-LF

1/16W

1%

2

1

R7460

215K

1% 1/16W MF-LF 402

2

1

R7463

137K

402

1% 1/16W MF-LF

2

1

R7461

137K

402

MF-LF

1/16W

1%

NO STUFF

C7415

100PF

2

1

CERM

5% 50V

402

2

5%

100PF

CERM

NO STUFF

402

C7416

50V

1

C7405

5%

SIGNAL_MODEL=EMPTY

2

1

0402

2200PF

CERM

10V

69

SIGNAL_MODEL=EMPTY

2

1

C7406

10V 0402

5%

2200PF

CERM

2

1

C7417

402

NO STUFF

5%

100PF

CERM

50V

21

402

10

1/16W

5%

MF-LF

R7440

SIGNAL_MODEL=EMPTY

21

10

5% 1/16W MF-LF

402

R7441

SIGNAL_MODEL=EMPTY

12 92

2

1

402

25V NP0-C0G

5%

C7440

SIGNAL_MODEL=EMPTY

1000PF

2

1

C7441

25V

1000PF

5%

402

NP0-C0G

SIGNAL_MODEL=EMPTY

12.7K

R7412

1 2

402

MF-LF

1/16W

1%

2

1

402

5%

1000PF

NP0-C0G

25V

SIGNAL_MODEL=EMPTY

C7412

R7413

21

10

5%

SIGNAL_MODEL=EMPTY

402

MF-LF

1/16W

12 92

C7422

2

1

5%

1000PF

NP0-C0G

25V 402

SIGNAL_MODEL=EMPTY

21

R7423

402

5%

1/16W

10

MF-LF

SIGNAL_MODEL=EMPTY

8.06K

21

1%

MF-LF

1/16W

402

R7422

50 69

100

50 69

2

1

C7419

5% CERM

50V 402

100PF

NO STUFF

2

1

402

100PF

5% 50V CERM

NO STUFF

C7418

69

2

1

C7407

0.001UF

50V

SIGNAL_MODEL=EMPTY

10% CERM

402

2

1

402

NONE

NOSTUFF

NONE

OMIT

SIGNAL_MODEL=EMPTY

C7442

2

1

OMIT

NONE NONE

NOSTUFF

NONE

402

C7443

SIGNAL_MODEL=EMPTY

2

1

R7479

1/16W

1%

54.9

MF-LF

402

PLACE_NEAR=U7400.18:2mm

2

1

R7480

1% MF-LF

402

1/16W

130

PLACE_NEAR=U7400.16:2mm

1/16W

1

300

2

R7407

402

5%

MF-LF

R7408

1/16W

2

402

MF-LF

1

5%

300

2

1

R7469

100KOHM

0402

PLACE_NEAR=Q7510.1:1mm

CRITICAL

2

1

R7467

100KOHM

CRITICAL

0402

PLACE_NEAR=Q7550.1:1mm

2

1

R7464

402

NONE NONE NONE

NOSTUFF

OMIT

2

1

R7465

402

1% 1/16W MF-LF

200K

MAX15092GTL

QFN

U7400

CRITICAL

SYNC_DATE=11/09/2010SYNC_MASTER=K92_ERIC

CPU IMVP7 & AXG VCore Regulator

CPUIMVP_ISUM_R

CPUIMVP_FBA_R

CPUIMVP_FBB

CPUIMVP_FBA

PP1V05_S0

CPU_VCCSENSE_N

CPU_AXG_SENSE_N

CPUIMVP_ISNS3_P

CPUIMVP_ISNS2_P

CPUIMVP_ISNS1_P

CPUIMVP_ISUM3_P

PPVIN_S5_HS_COMPUTING_ISNS

GND_CPUIMVP_SGND

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

CPU_VCCSENSE_P

CPU_AXG_SENSE_P

CPUIMVP_FBB_R

PP5V_S0

MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0_CPUIMVP_VCC

MIN_LINE_WIDTH=0.4 MM

CPUIMVP_PHASE2

CPUIMVP_UGATE2

CPUIMVP_ISUM2_P

CPUIMVP_BOOT2

CPUIMVP_ISUM_N CPUIMVP_FBA

CPUIMVP_ISUM

CPUIMVP_ISUM1_P

CPUIMVP_LGATE1

CPUIMVP_TON

CPUIMVP_BOOT1 CPUIMVP_UGATE1 CPUIMVP_PHASE1

CPUIMVP_FBB

CPUIMVP_ISUMG_N

CPUIMVP_LGATE1G

CPUIMVP_LGATE2

CPUIMVP_BOOT1G

CPUIMVP_PHASE1G

CPUIMVP_UGATE1G

CPUIMVP_ISUMG_P

CPU_VCCSENSE_R

CPU_AXG_SENSE_R

CPUIMVP_PWM3

CPU_PROCHOT_L

CPUIMVP_ISUM3_P

CPUIMVP_PGOOD

CPUIMVP_VR_ON

CPU_VIDSCLK

CPUIMVP_AXG_PGOOD

CPU_VIDSOUT

CPUIMVP_NTCG

CPUIMVP_NTC

CPU_VIDALERT_L

CPUIMVP_IMAXB

CPUIMVP_SLEW

CPUIMVP_IMAXA

74 OF 132 68 OF 105

68

7 9

10 12 13 14 23 35 39 45 70 73

102

104 105

68 69

7

50 65 67 69 70

6 7 8

22 41 47 52 54 65 69 70 73 87

104

105

69

68

68 69

IN

IN IN

IN

D

G

S

G

D

G

S

IN

VSW

PGND

TGR

TG

BG

VIN

D

S

G

D

S

G

SKIP*

PWN

THRM

DL

LX

VDD

BST

DH

PAD

GND

D

G

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

376S0930

PHASE 3

152S1019

THESE TWO CAPS ARE FOR EMC

376S0930

152S1019

THESE TWO CAPS ARE FOR EMC

Additonal Input Bulk Caps

376S0872

152S1019

THESE TWO CAPS ARE FOR EMC

PHASE 2

376S0872

376S0906

376S0930

AXG PHASE

152S1019

THESE TWO CAPS ARE FOR EMC

PHASE 1

376S0772

402

10% CERM

NOSTUFF

0.001UF

50V

C7512

1

2

PIMA104E-SM

CRITICAL

0.36UH-20%-40A-0.00075OHM

L7510

1 2

CRITICAL

16V X5R-CERM

10UF

10%

0805

C7515

1

2

16V POLY-TANT

20%

68UF

CRITICAL

CASE-D2E-SM

C7513

1

2

0805

10UF

CRITICAL

X5R-CERM

16V

10%

C7516

1

2

1UF

X5R

16V

10%

402

C7517

1

2

0.001UF

X7R

50V

10%

402

C7518

1

2

0.001UF

10% 50V X7R 402

C7519

1

2

68

CRITICAL

68UF

20% 16V POLY-TANT CASE-D2E-SM

C7514

1

2

68

CRITICAL

DIRECTFET-MX

IRF6798MTRPBF

Q7525

1 2 6 7

5

3 4

50V

10% 402

CERM

NOSTUFF

0.001UF

C7522

1

2

NOSTUFF

1/10W

603

MF-LF

5%

2.2

R7522

1

2

CRITICAL

0.36UH-20%-40A-0.00075OHM

PIMA104E-SM

L7520

1 2

CRITICAL

68UF

20% 16V POLY-TANT CASE-D2E-SM

C7523

1

2

20% 16V POLY-TANT

68UF

CASE-D2E-SM

CRITICAL

C7524

1

2

10UF

X5R-CERM

10%

0805

16V

CRITICAL

C7525

1

2

10UF

CRITICAL

16V X5R-CERM

10%

0805

C7526

1

2

CRITICAL

0.00075

0612

MF

1W

1%

R7520

1 2 3 4

402

1UF

10% 16V X5R

C7527

1

2

0.001UF

402

10% 50V X7R

C7528

1

2

402

0.001UF

X7R

50V

10%

C7529

1

2

10% 50V

0.001UF

402

X7R

C7539

1

2

0.001UF

10% X7R

50V 402

C7538

1

2

402

X5R

10% 16V

1UF

C7537

1

2

10UF

CRITICAL

16V X5R-CERM

10% 0805

C7536

1

2

CRITICAL

10UF

16V X5R-CERM

10% 0805

C7535

1

2

CASE-D2E-SM

POLY-TANT

CRITICAL

20%

68UF

16V

C7534

1

2

1%

0.00075

1W MF

CRITICAL

0612

R7530

1 2 3 4

0.36UH-20%-40A-0.00075OHM

CRITICAL

PIMA104E-SM

L7530

1 2

CASE-D2E-SM

68UF

20% 16V POLY-TANT

CRITICAL

C7533

1

2

S1

CRITICAL

IRF6710

Q7530

1 2 5 64

3

MF-LF

5%

2.2

NOSTUFF

1/10W

603

R7532

1

2

NOSTUFF

CERM

0.001UF

10% 50V

402

C7532

1

2

CRITICAL

DIRECTFET-MX

IRF6798MTRPBF

Q7535

1 2 6 7

5

3 4

0.22UF

CERM

10V 402

10%

C7531

1

2

MF-LF

5%

0

1/16W

402

R7531

1

2

X5R 402

16V

10%

1UF

C7541

1

2

68

0.22UF

10% CERM

10V 402

C7521

1

2

5%

MF-LF

0

1/16W

402

R7521

1

2

0

5%

MF-LF

402

1/16W

R7511

1

2

0.22UF

10V CERM

10%

402

C7511

1

2

1/16W MF-LF 402

10K

5%

R7547

1

2

50V

0.001UF

X7R 402

10%

C7559

1

2

402

10%

0.001UF

X7R

50V

C7558

1

2

1UF

10% 16V X5R 402

C7557

1

2

10UF

X5R-CERM 0805

10% 16V

CRITICAL

C7556

1

2

68UF

16V

CRITICAL

POLY-TANT CASE-D2E-SM

20%

C7554

1

2

CRITICAL

68UF

POLY-TANT

16V

20%

CASE-D2E-SM

C7553

1

2

5% MF-LF

2.2

1/10W 603

NOSTUFF

R7552

1

2

NOSTUFF

10%

402

CERM

50V

0.001UF

C7552

1

2

CERM

402

10V

10%

0.22UF

C7551

1

2

68

20%

CRITICAL

16V POLY-TANT

68UF

CASE-D2E-SM

C7564

1

2

20% 16V POLY-TANT

68UF

CRITICAL

CASE-D2E-SM

C7565

1

2

20% POLY-TANT

CRITICAL

68UF

16V CASE-D2E-SM

C7566

1

2

20%

CRITICAL

16V POLY-TANT

68UF

CASE-D2E-SM

C7567

1

2

20%

CRITICAL

16V POLY-TANT

68UF

CASE-D2E-SM

C7568

1

2

20%

CRITICAL

16V POLY-TANT

68UF

CASE-D2E-SM

C7569

1

2

20%

CRITICAL

POLY-TANT

68UF

CASE-D2E-SM

16V

C7563

1

2

20%

CRITICAL

16V POLY-TANT CASE-D2E-SM

68UF

C7562

1

2

CRITICAL

20% 16V POLY-TANT

68UF

CASE-D2E-SM

C7561

1

2

MF-LF

1/16W

402

1%

46.4

R7513

1

2

10.2

MF-LF 402

1% 1/16W

R7514

1

2

CRITICAL

SON5X6

CSD58864Q5D

Q7550

5

9

3

4

1

6 7 8

CRITICAL

IRF6723M2DPBF

DIRECTFET-MA

Q7510

8 7

2

1

DIRECTFET-MA

CRITICAL

IRF6723M2DPBF

Q7510

6 5

3

4

CRITICAL

1%

0.00075

1W MF

0612

R7550

12 34

0805

10UF

16V X5R-CERM

10%

CRITICAL

C7555

1

2

402

10% CERM

50V

330PF

NOSTUFF

C7571

1

2

NOSTUFF

330PF

10% CERM

50V 402

C7572

1

2

402

330PF

10% CERM

50V

NOSTUFF

C7573

1

2

402

NOSTUFF

50V CERM

330PF

10%

C7574

1

2

CRITICAL

0.36UH-20%-40A-0.00075OHM

PIMA104E-SM

L7550

1 2

MAX17491

TQFN

CRITICAL

U7541

1

8

4

3

7

2

6

9

5

5% 1/16W MF-LF

4.7

402

R7555

1 2

1% 1/16W MF-LF

46.4

402

R7523

1

2

1/16W

1%

MF-LF

46.4

402

R7533

1

2

1/16W

1%

MF-LF

46.4

402

R7553

1

2

402

10.2

1% MF-LF

1/16W

R7524

1

2

402

10.2

1% MF-LF

1/16W

R7534

1

2

402

10.2

1% MF-LF

1/16W

R7554

1

2

MF-LF

1/16W

402

0

5%

R7556

1 2

CRITICAL

0.00075

1W

1% MF

0612

R7510

12 34

DIRECTFET-MX

IRF6798MTRPBF

CRITICAL

Q7515

1 2 6 7

5

3 4

5%

MF-LF

2.2

1/10W

603

NOSTUFF

R7512

1

2

SYNC_MASTER=K92_ERIC SYNC_DATE=09/27/2010

CPU IMVP7 & AXG VCore Output

CPUIMVP_ISNS1_P CPUIMVP_ISNS1_N

PPVCORE_S0_CPU_PH1

PPVCORE_S0_CPU

PPVCORE_S0_CPU_PH1_L

CPUIMVP_ISUM_N

GATE_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_UGATE1

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

CPUIMVP_PHASE1

SWITCH_NODE=TRUE

CPUIMVP_ISUM1_P

DIDT=TRUE

CPUIMVP_PH1_SNUB

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

CPUIMVP_PHASE2

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_LGATE2

PPVIN_S5_HS_COMPUTING_ISNS

DIDT=TRUE

CPUIMVP_PH2_SNUB

CPUIMVP_BOOT1_RC

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

CPUIMVP_BOOT1

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

CPUIMVP_ISUM3_P

CPUIMVP_ISUM_N

CPUIMVP_ISNS3_N

PPVCORE_S0_CPU

CPUIMVP_ISUM_N

CPUIMVP_ISUM2_P

CPUIMVP_ISNS2_N

PPVCORE_S0_CPU

PP5V_S0

CPUIMVP_BOOT1G_R

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM DIDT=TRUE

CPUIMVP_BOOT1G

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_LGATE3

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

PPVCORE_S0_CPU_PH2_L

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1G

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

DIDT=TRUE

CPUIMVP_UGATE1G_R

MIN_LINE_WIDTH=0.5 MM DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_CPU_PH2

MIN_LINE_WIDTH=0.25 MM

DIDT=TRUE

CPUIMVP_BOOT3_RC

MIN_NECK_WIDTH=0.25 MM

GATE_NODE=TRUE

DIDT=TRUE

CPUIMVP_UGATE2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

CPUIMVP_ISNS3_P

PPVCORE_S0_CPU_PH3

CPUIMVP_ISNS1G_P CPUIMVP_ISNS1G_N

PPVCORE_S0_AXG_L

PPVCORE_S0_AXG

CPUIMVP_ISNS2_P

PPVCORE_S0_CPU_PH3_L

CPUIMVP_ISUMG_N

CPUIMVP_ISUMG_P

CPUIMVP_SKIP

CPUIMVP_PWM3

CPUIMVP_AXG_SNUB

DIDT=TRUE

CPUIMVP_BOOT2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_NECK_WIDTH=0.25 MM

CPUIMVP_BOOT2_RC

DIDT=TRUE

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_LGATE1

CPUIMVP_BOOT3

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1G

CPUIMVP_PHASE1G

MIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=1.5 MM

DIDT=TRUE

CPUIMVP_PH3_SNUB

CPUIMVP_UGATE3

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

CPUIMVP_VSWG

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.5 MM

PPVIN_S5_HS_COMPUTING_ISNS

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=1.5 MM

CPUIMVP_PHASE3

SWITCH_NODE=TRUE

DIDT=TRUE

75 OF 132 69 OF 105

50 68

100

50

100

6 7

12 14 49 69

105

68 69

68

7

50 65 67 68 69 70

68

68 69

50

6 7

12 14 49 69

105

68 69

68

50

6 7

12 14 49

69

105

6 7 8

22 41 47 52 54 65 68 70 73 87

104

105

50 68

50

100

50

100

7

12 13 15 49

50 68

68

7

50 65 67 68 69 70

OUT

IN

BOOT

UGATE

LGATE

PHASE

RTN

FSEL

PGOOD

OCSET

VO

SREF

VCC

PVCC

GND

PGND

EN

FB

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(CPUVCCIOS0_OCSET)

<Rb>

21A Max Output

Vout = 1.05V

f = 300 kHz

<Ra>

CPU VCCIO (1.05V S0) Regulator

(CPUVCCIOS0_VO)

OCP = R7641 x 8.5uA / R7640 Vout = 0.5V * (1 + Ra / Rb)

OCP = 25.6A

2

1

R7644

MF-LF

1/16W

1%

3.01K

402

SIGNAL_MODE=EMPTY

73

2

1

C7602

10%

603

X5R

16V

2.2UF

2

1

R7603

5%

0

1/16W 402

MF-LF

21

XW7600

PLACE_NEAR=U7600.1:1mm

SM

1

8

13

11

4

2

14

10

9

16

7

15

5

6

3

12

U7600

CRITICAL

UTQFN

ISL95870

2

1

R7601

2.2

603

MF-LF

5%

1/10W

2

1

C7601

603

10V X5R

20%

10UF

321

4

5

Q7635

CRITICAL

RJK0208DPA

WPAK

321

4

5

Q7630

RJK0365DPA-01

CRITICAL

WPAK

2

1

C7630

1UF

16V

10% X5R

402

2

1

R7642

1% 1/16W MF-LF

3.01K

402

2

1

R7641

1% 1/16W MF-LF

3.01K

402

2 1

C7640

1000PF

NP0-C0G

402

5%

25V

2

1

C7623

402

NP0-C0G

25V

5%

1000PF

PLACE_NEAR=L7630.2:1.5mm

2

1

C7620

CRITICAL

20%

68UF

16V

POLY-TANT

CASE-D2E-SM

2

1

C7621

16V

68UF

CASE-D2E-SM

POLY-TANT

20%

CRITICAL

2

1

C7622

PLACE_NEAR=Q7630.1:1.5mm

25V

5%

1000PF

402

NP0-C0G

2

1

C7648

CRITICAL

NO STUFF

CASE-B4-SM

270UF

TANT

20% 2V

2

1

C7649

NO STUFF

CRITICAL

270UF

CASE-B4-SM

20%

TANT

2V

2

1

R7630

603

1/10W

5%

MF-LF

2.2

2

1

C7604

5%

CERM

50V 402

47PF

21

L7630

CRITICAL

PIMB104T-SM

0.68UH-22A-2.4MOHM

43

21

R7640

CRITICAL

0.001

MF-1

1W

0612

1%

2

1

C7605

5%

47PF

CERM

50V 402

2

1

C7603

402

0.047UF

16V

10% X7R

1%

2

1

R7645

2.74K

MF-LF 402

1/16W

2

1

R7605

2.74K

1%

MF-LF

1/16W

402

2

MF-LF

1/16W

1%

1

R7604

3.01K

SIGNAL_MODE=EMPTY

CPU VCCIO (1.05V) Power Supply

SYNC_DATE=09/23/2010SYNC_MASTER=K92_ERIC

CPU_VCCIOSENSE_N

CPUVCCIOS0_FSEL

PP5V_S0

CPUVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_VBST

DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm DIDT=TRUE

MIN_LINE_WIDTH=0.3 mm

CPUVCCIOS0_BOOT_RC

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

CPUVCCIOS0_LL

PP5V_S0_CPUVCCIOS0_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

CPUVCCIOS0_OCSET

CPUVCCIOS0_VO

CPUVCCIOS0_RTN

CPUVCCIOS0_AGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

CPUVCCIOS0_DRVH

MIN_NECK_WIDTH=0.2 mm GATE_NODE=TRUE DIDT=TRUE

CPUVCCIOS0_EN

CPUVCCIOS0_SREF

CPUVCCIOS0_FB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PPCPUVCCIO_S0_REG_R

PP1V05_S0

CPUVCCIOS0_CS_P CPUVCCIOS0_CS_N

CPU_VCCIOSENSE_P

CPUVCCIOS0_PGOOD

76 OF 132 70 OF 105

12 92

6 7 8

22 41 47 52 54 65 68 69 73 87

104

105

7

50 65 67 68 69

7 9

10 12

13 14 23

35 39 45

68 73

102 104

105

49

100

49

100

12 92

NC

IN

BIAS

NC

OUT

THRM

EN

PADGND

OUT

IN

NC

LX

VDD

VIN

THRM_PAD

PGND

SGND

EN

PG

SYNCH

LX

VFB

NC

IN

EN

MODE

VID1

LX

VOUT

VIN

VID0

SYNC/PWM

THRM

PGND

GND PAD

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1.8V S0 Regulator

353S2535

Vout = 0.8V * (1 + Ra / Rb)

<Ra>

Max Current = 0.8A

Vout = 1.508V

Freq = 1.6MHZ

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

1.5V S0 Regulator

<Rb>

152S1302

<Ra>

Vout = 1.794V Max Current = 4A Freq = 1 MHz

152S0771

MAX CURRENT = 0.7A

Max Current = 0.35A

Vout = 1.05V

70mA is required to support pull-ups. Alternative is strong voltage

Pull-ups (3) must be 51 ohms to support XDP (not required in production).

Cougar Point-M requires JTAG pull-ups to be powered at 1.05V in S5.

1.05V S5 LDO

dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

353S2719

FREQ = 1MHZ

Vout = 1.2V

1.2V S0 (GMUX) Regulator

CAESAR IV 1.2V INT.VR CMPTS

CRITICAL

PIMB053T-SM

1.0UH-7A

L7720

1 2

2.2UF

10%

6.3V

XDP_PCH

402

X5R

C7741

1

2

TPS720105

XDP_PCH

CRITICAL

SON

U7740

4

3

5

6

2

1

7

XDP_PCH

10%

6.3V CERM

402

1UF

C7740

1

2

90.9K

402

1% 1/16W MF-LF

R7721

1

2

22UF

805

CERM

6.3V

20%

CRITICAL

C7722

1

2

73

20%

805

CERM

6.3V

CRITICAL

22UF

C7720

1

2

MF-LF

113K

1%

1/16W

402

R7720

1

2

CRITICAL

20%

6.3V CERM 805

22UF

C7721

1

2

402

50V CERM

47PF

5%

C7723

1

2

402

5%

1000PF

NP0-C0G

25V

C7724

1

2

CRITICAL

QFN

ISL8014A

U7720

5 14

15

6

16

13

7

11

12

9

10

4

17

3

8

1

2

402

X5R

20%

6.3V

4.7UF

C7737

1

2

CRITICAL

402

4V X5R

10UF

20%

C7735

1

2

0.1UF

402

10% X5R

16V

C7738

1

2

0.1UF

10% X5R

402

16V

C7736

1

2

CRITICAL

PCAA031B-SM

4.7UH-0.8A

L7730

1 2

402

5%

0

MF-LF

1/16W

R7761

1

2

NO STUFF

402

5%

0

1/16W MF-LF

R7760

1

2

73

CRITICAL

20%

10UF

X5R

4V 402

C7760

1

2

SC194A

CRITICAL

MLP10

U7760

4

8

10

2

9

3

11

6

7

1

5

16V X5R

10%

0.1UF

402

C7764

1

2

PLACE_NEAR=L7760.2:1MM

SM

XW7761

1 2

P1V2S0_SW

CRITICAL

PCAA031B-SM

2.2UH-1.2A

L7760

1 2

CRITICAL

CERM

6.3V

22UF

20%

805

C7761

1

2

73

CRITICAL

ISL8009B

DFN

U7710

2

7

8

3

54

9

6

1

CRITICAL

CERM

6.3V

805

22UF

20%

C7750

1

2

CRITICAL

IHLP1616BZ-SM

2.2UH-3.25A

L7770

1 2

1%

113K

1/16W MF-LF 402

R7781

1

2

47PF

CERM

402

50V

5%

C7776

1

2

1/16W

402

MF-LF

1%

100K

R7780

1

2

6.3V

20%

CERM

22UF

805

CRITICAL

C7771

1

2

73

Misc Power Supplies

SYNC_DATE=07/21/2010

SYNC_MASTER=K91_CHANG

PP3V3_ENET

PP1V2_ENET

PP3V3_S5

P1V8S0_FB

PP3V3_SUS

PP1V05_SUS

SWITCH_NODE=TRUE DIDT=TRUE

ENET_SR_LX

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

P1V2S0_FB

PP1V2_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

DIDT=TRUE

SWITCH_NODE=TRUE

P1V2S0_SYNC_PWM

P1V2S0_EN

PP1V8_S0

DIDT=TRUE

P1V8S0_SW

SWITCH_NODE=TRUE

P1V8S0_PGOOD

P1V5S0_EN

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.4 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

1V5_S0_SW

1V5_S0_FB

PP1V5_S0

P1V8S0_EN

P1V5S0_PGOOD

PP3V3_S5

77 OF 132 71 OF 105

7

25 36 73

7

36 71

7

36 71

6 7

17 19 20 22 23 24

25 29 46 48 56 71 72 73

83 86 91

100 102 104

7

16 17 18 19 20 22 46 72 73

7

23

36

6 7

88

6 7

14 20 25 72 88

102

7

16 20 22 25 32 41 57

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

17 19 20 22 23

24 25 29 46 48 56 71 72 73

83 86 91

100 102 104

IN

D

SG

S

D

G

D

G S

D

S

G

D

S

G

THRM

GND

G

PG

SHDN*

D

VCC

S

ON

PAD

OUT

IN

D

S

G

D

SG

IN

D

S

G

IN

D

G S

IN

D

SG

S

G

D

IN

D

G S

S

G

D

EN

C_SR

DRAIN

VCC

GND

THRM

C_DELAY

NC

R_BLEED

SOURCE

EN_POL_CTRL

PAD

D

S

G

D

SG

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

N-TYPE 18 mOhm @4.5V

input side

3.3V Standby(S4) FET

LOADING

1.5V S3/S0 FET

N-TYPE 6 mOhm @4.5V 5 A (EDP)

5V_SUS FET input filter

MOSFET CHANNEL

MOSFET CHANNEL RDS(ON) LOADING

3.3V Standby FET

5 mA ?(EDP)

P-TYPE 8V/5V

26 mOhm @1.8V

376S0945

SiA427

3.3V S3 FET

MOSFET CHANNEL RDS(ON)

NCP4543

1.8V GPU FET

1.5V S3/S0 FET

5V_SUS FET

5V SUS FET

3.3V S0 FET

P-TYPE 20V/12V

5.5 mOhm @4.5V

5.6 A (EDP)

SI7615DN

SiA413

2 mA (EDP)

29 mOhm @4.5V

P-TYPE 12V

CHANNEL RDS(ON) LOADING

CHANNEL

3 A (EDP)

26 mOhm @1.8V

3.3V_SUS FET

P-TYPE 8V/5V

100? mA (EDP)

3.3V S0 GPU FET

0.11A (EDP)

LOADING

RDS(ON)

RDS(ON) LOADING

5.0V S0 FET

RDS(ON)

SiA427

CHANNEL

MOSFET

LOADING

MOSFET

P-TYPE 8V/5V

SiA427

CHANNEL

MOSFET

SI7108DN

LOADING

RDS(ON)

CHANNEL

MOSFET

P-TYPE 8V/5V

LOADING

SiA427

MOSFET

3.3V SUS FET

3.3V S0 GPU FET

8 A (EDP)

5.5 MOHM @4.5V

P-TYPE 20V/12V

SI7615DN

LOADING

RDS(ON)

CHANNEL

MOSFET

5.0V S0 FET

26 mOhm @1.8V

3.3V S0 FET

1.8V GPU FET

353S3093

load side

U7880 default Turn on delay EN--> on is 200~650us.

2.4A (EDP)

APN 376S0651

402

10% 10V

1UF

X5R

C7871

1

2

CERM

16V

10%

402

0.01UF

C7870

1 2

1K

MF-LF

5%

402

1/16W

R7870

1 2

5%

51K

MF-LF

402

1/16W

R7872

1

2

88 91

29

402

CERM

16V

10%

0.01UF

C7810

1 2

0.033UF

16V

402

10%

X5R

C7811

1

2

47K

402

5% 1/16W MF-LF

R7810

1 2

MF-LF

100K

5%

1/16W

1

2

402

R7812

73

SSM6N15FEAPE

SOT563

Q7812

6

2

1

SI7108DN

CRITICAL

PWRPK-1212-8-HF

Q7801

5

4

1 2 3

SOD-VESM-HF

SSM3K15FV

Q7872

3

1

2

SC70-6L

CRITICAL

SIA427DJ

Q7810

1

3

4 7

SIA427DJ

CRITICAL

SC70-6L

Q7870

1

3

4 7

TDFN

CRITICAL

U7801

5

7

4

2

8

6

3

9

1

SLG5AP020

0.1UF

CERM

10V

20%

402

C7801

1

2

MF-LF

402

5%

0

1/16W

R7801

1 2

91

0.1UF

402

10V

20%

CERM

1

2

PLACE_NEAR=U7880.2:2.54mm

C7880

16V

10%

402

X5R

0.033UF

C7821

1

2

SIA427DJ

SC70-6L

CRITICAL

Q7820

1

3

4 7

0.01UF

10% 16V

402

CERM

C7820

1 2

1/16W

5%

MF-LF

402

100K

R7822

1

2

Q7802

SOT563

SSM6N15FEAPE

3

5

4

1/16W MF-LF

402

5%

12K

R7820

1 2

72 73

0.033UF

10% 16V X5R 402

C7841

1

2

SIA413DJ

SC70-6L

CRITICAL

Q7840

1

3

4 7

0.01UF

10% 16V

CERM

402

C7840

1 2

1/16W MF-LF

5%

402

220K

R7842

1

2

5%

402

MF-LF

1/16W

3.3K

R7840

1 2

72 73

SSM3K15FV

SOD-VESM-HF

Q7842

3

1

2

49 72 73

SSM6N15FEAPE

SOT563

Q7812

3

5

4

47K

5% 1/16W MF-LF

402

R7832

1

2

33K

5% 1/16W MF-LF

402

R7830

1 2

0.033UF

X5R

10% 16V

402

C7831

1

2

0.01UF

10% 16V

CERM

402

C7830

1 2

CRITICAL

SI7615DN

PWRPK-1212-8

Q7830

5

4

1 2 3

49 72 73

SSM3K15FV

SOD-VESM-HF

Q7865

3

1

2

402

MF-LF

1/16W

5%

220K

R7862

1

2

402

MF-LF

1/16W

5%

10K

R7860

1 2

402

X5R

16V

10%

0.033UF

C7861

1

2

402

CERM

16V

10%

0.01UF

C7860

1

2

SI7615DN

PWRPK-1212-8

CRITICAL

Q7860

5

4

1 2 3

402

10% 10V

1UF

X5R

NO STUFF

C7802

1

2

19

8

7

6

13

18

14

3

16

15 12

11

10

9

5

4

17

1

U7880

CRITICAL

QFN

NCP4543IMN5RG-A

0.1UF

10V

CERM

20%

402

NO STUFF

C7881

1

2

5%

25V

1000PF

402

NP0-C0G

NO STUFF

C7882

1

2

2.2UF

20%

X5R-CERM

10V

402

NO STUFF

C7843

1

2

1/16W

PLACE_NEAR=Q7840.4:5mm

402

5%

MF-LF

0

R7843

1 2

MF-LF

1 2

402

0

R7803

1/16W

5%

CRITICAL

SIA427DJ

SC70-6L

NO STUFF

Q7800

1

3

4 7

NO STUFF

0.01UF

402

CERM

10% 16V

1 2

C7800

X5R

10%

402

16V

NO STUFF

1

2

0.033UF

C7809

5%

402

MF-LF

1/16W

NO STUFF

5.1K

R7800

1 2

220K

1/16W

402

5%

MF-LF

NO STUFF

R7802

1

2

SSM6N15FEAPE

SOT563

Q7802

6

2

1

73

Power FETs

SYNC_MASTER=K91_MLB

SYNC_DATE=10/18/2010

PP3V3_S3_ISNS_R

P3V3S3_SS

P3V3S3_S4

P3V3S4_EN_L

PP1V8_S0

VOLTAGE=5.0V

MIN_NECK_WIDTH=0.2 MM MIN_LINE_WIDTH=0.4 MM

PP5V_S5_P5VSUSFET_R

GPUFET_C_SR

PP1V8_S0GPU_ISNS_R

GPUFET_C_DELAY

P3V3S0_EN_L

P3V3GPU_EN_L

PP1V5_S3RS0

P3V3GPU_EN

P5VSUS_SS

PM_SUS_EN

PP5V_S3

P5V0S0_EN_L

PP5V_S5_P5VSUSFET_R

PP1V5_S3

P1V5S3RS0FET_GATE

PP5V_S5

PP5V_S0_ISNS_R

P5V0S0_SS

PM_SLP_S3_R_L

PM_SUS_EN

TP_P1V5S3RS0_RAMP_DONE

PP3V3_S0GPU

P1V5S3RS0FET_GATE_R

P3V3SUS_SS

P3V3SUS_EN_L

P3V3S0_SS

PP3V3_S5

PP3V3_SUS

PP3V3_S5

P3V3GPU_SS

P1V5CPU_EN

P3V3S3_EN_L

PM_SLP_S3_R_L

PP3V3_S0

P1V8GPU_EN

PP3V3_S0

PP3V3_S5

PP5V_SUS

P5VSUS_EN_L

P3V3S3_EN

P3V3_S4_EN

PP3V3_S4

PP5V_S5

PP3V3_S5

PP1V8_S0GPU_ISNS_R

78 OF 132 72 OF 105

7

104

6 7

14 20 25 71 88

102

72

6 7

72

103

7

100 104

6 7

29 31 42 43 44 46 67 82

104

72

7

26 28 29 67

7

54 66 72

103 104

7

104

6 7

75 79 80 82 84

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

7

16 17 18 19 20 22 46 71 73

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80

83 84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

7

22

6 7

46 53 54

7

54 66 72

103 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

6 7

72

103

G

D

S

IN

G

D

S

IN

OUT

G

DS

OUT

IN

OUT

D

G S

IN

OUT

IN

NC

Q3

Q2

Q4

Q1

SENSE

CT

VDD

GND

RESET*

MR*

IN

G

D

S

G

D

S

OUT

IN

OUT

NC

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

D

G S

OUT

VCC

A

Y

GND

B

C

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

S0 Rail PGOOD (BJT Version)

PM_SLP_SUS_L:100K pull down on PCH page

PP1V5_S3RS0

Q3: 0.640V

3.3V w/Divider: 2.345V Q4: 0.660V

S0 Rail PGOOD Circuitry

(ISL Version in development)

threhold is 3.07V

Worst-Case Thresholds:

Q2: 0.XXXV

VFRQ High: Variable Frequency

Thresholds: VDD: 2.734V-3.010V

3.3V ENET FET

ENET Enable Generation

SMC-->PM_DSW_PWRGD

3.3V,5V S3 ENABLE

SMC_PM_G2_ENABLE

1 1

0

353S2809

(IPU)

P1V5S0_PGOOD from U7710

PM_SLP_S3_L

1

PM_SLP_S4_L

0

1

0

01

1

0

1 0 0

0

PM_SLP_S5_L

0

Deep Sleep (S4)

(PM_SLP_S3_R_L)

(AC_EN_L)

(PM_SLP_S3_L)

CHGR VFRQ Generation

3.3V SUS Detect

353S2310

NOTE: S3 term is guaranteed by S3 pull-up

Sleep (S3)

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

(PM_SLP_S4_L)

S0 ENABLE

PM_SLP_S4_L:100K pull down in PCH page

V3MON: 0.572V-0.630V

VFRQ Low: Fix Frequency

V4MON: 0.572V-0.630V

V2MON: 2.815V-3.099V

on open-drain AP_PWR_EN signal.

PM_RSMRST_L goes to U1800.C21

U7930 Sense input

Min delay time

No stuff C7931, 12ms

Run (S0)

State

CPUVCORE ENABLE

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

1

SMC_BATLOW_L:100K pull up on SMC page

PM_SLP_S5_L:100K pull down on PCH page

S5 Rail Enables & PGOOD

3.3V/5.0V Sus ENABLE

PM_SLP_S3_L:100K pull down in PCH page

3.3V/5.0V S4 ENABLE

Battery Off (G3Hot)

Deep Sleep (S5)

2N7002DW-X-G

SOT-363

Q7920

6

2

1

17 45 46

19

6

17 29 45 73

1/16W MF-LF

10K

5%

402

R7921

1

2

402

1/16W

100K

MF-LF

5%

R7922

1 2

SOT-363

2N7002DW-X-G

Q7925

6

2

1

18 31

31

10% 16V

402

X5R

0.033UF

C7921

1

2

SOT-23-HF

NTR4101P

CRITICAL

Q7922

3

1

2

402

CERM

16V

10%

0.01UF

C7922

12

17 29 42 45

66 73

67 73

72 73

PLACE_NEAR=Q7812.2:6mm

MF-LF

5%

402

0

1/16W

R7912

1

2

NO STUFF

10%

402

6.3V CERM-X5R

0.47UF

C7912

1

2

68

402

PLACE_NEAR=U7400.7:5mm

1/16W

0

5%

MF-LF

R7974

1 2

49 72 73

70 73

71 73

65 73

5.1K

1/16W

PLACE_NEAR=U7300.16:6mm

402

5%

MF-LF

R7911

1

2

10%

6.3V CERM-X5R 402

0.47UF

C7910

1

2

17 29 42 45 66 73

PLACE_NEAR=U7720.5:6mm

6.3V

0.47UF

10%

CERM-X5R 402

C7986

1

2

PLACE_NEAR=U7720.5:6mm

402

5.1K

MF-LF

1/16W

5%

R7986

1

2

402

MF-LF

1/16W

PLACE_NEAR=U7760.4:6mm

20K

5%

R7985

2

1

PLACE_NEAR=U7600.3:6mm

1/16W

5%

MF-LF 402

20K

R7981

1

2

1UF

CERM-X5R 402

PLACE_NEAR=U7760.4:6mm

10%

6.3V

C7985

1

2

0.47UF

6.3V

10%

402

CERM-X5R

PLACE_NEAR=U7600.3:6mm

C7981

1

2

PLACE_NEAR=U7100.15:6mm

402

10%

6.3V

0.47UF

CERM-X5R

C7987

1

2

5%

1/16W

402

MF-LF

PLACE_NEAR=U7100.15:6mm

33K

R7987

1

2

100K

402

MF-LF

1/16W

5%

R7931

1 2

64

SOD-VESM-HF

SSM3K15FV

Q7931

3

1

2

6

17 29 45 73

45 46 73 86

1/16W MF-LF

402

5%

0

PLACE_NEAR=U7400.7:5mm

R7975

1 2

45

PLACE_NEAR=U7400.7:5mm

1/16W

402

0

5%

MF-LF

NO STUFF

R7976

1 2

1/16W

0

NO STUFF

5%

402

MF-LF

R7929

1

2

402

10K

MF-LF

1/16W

5%

R7967

1

2

23 45 73 88 91

1/16W MF-LF

5%

402

100

R7957

1

2

1/16W

402

5%

MF-LF

100

R7966

1 2

MF-LF

1/16W

5%

402

100

R7964

1 2

1/16W

5%

MF-LF

402

100

R7965

1 2

71

66

MF-LF

402

1/16W

5%

100

R7963

1 2

S0PGOOD_ISL

330

5%

1/16W

402

MF-LF

R7962

1 2

70 73

65

MF-LF

402

1%

1/16W

150K

R7956

1

2

MF-LF

1K

1/16W

402

5%

R7953

1 2

15.0K

MF-LF 402

1/16W

1%

R7951

1

2

7.15K

1/16W

1%

MF-LF 402

R7952

1

2

DFN2015H4-8

CRITICAL

ASMCC0179

Q7950

5

7

1

6

4

8

2

3

402

1K

5% 1/16W MF-LF

R7954

1 2

5%

1/16W

402

MF-LF

1K

R7955

1 2

TPS3808G33DBVRG4

SOT23-6

CRITICAL

U7930

4

2

3

15

6

0.001UF

50V CERM 402

NO STUFF

20%

C7931

1

2

402

100K

5% 1/16W MF-LF

R7933

1

2

PLACE_NEAR=U7930.6:2.3mm

402

10V

20%

0.1uF

CERM

C7930

1

2

1/16W

5%

402

MF-LF

100

R7968

1 2

71

SOT-363

2N7002DW-X-G

Q7920

3

5

4

2N7002DW-X-G

SOT-363

Q7925

3

5

4

100

MF-LF

1/16W

5%

402

R7978

1 2

402

MF-LF

1/16W

5%

10K

R7988

1 2

71 73

6.3V CERM-X5R

10%

0.47UF

402

PLACE_NEAR=U7710.2:6mm

C7988

1

2

17

45 66 73

0.0033UF

NO STUFF

10%

402

50V CERM

C7942

1

2

100

MF-LF

PLACE_NEAR=U7201.21:7mm

1/16W

5%

402

R7940

1 2

66 73

45 66 73

100K

5%

402

MF-LF

1/16W

PLACE_NEAR=U7201.20:7mm

R7941

1

2

0.1uF

S0PGOOD_ISL

20% 10V

CERM

402

C7960

1

2

ISL88042IRTEZ

TDFN

CRITICAL

S0PGOOD_ISL

U7960

4

1

8

9

3 5 6

2

7

MF-LF

S0PGOOD_ISL

402

1%

1/16W

6.04K

R7972

1

2

MF-LF

15.0K

1/16W

S0PGOOD_ISL

1%

402

R7973

1

2

S0PGOOD_ISL

10K

1/16W

402

MF-LF

1%

R7970

1

2

S0PGOOD_ISL

10K

1%

1/16W

MF-LF

402

R7971

1

2

S0PGOOD_ISL

6.04K

1/16W

1%

MF-LF

402

R7960

1

2

1%

S0PGOOD_ISL

15.0K

1/16W

MF-LF

402

R7961

1

2

SOD-VESM-HF

SSM3K15FV

Q7921

3

1

2

53

402

MF-LF

1/16W

5%

3.3K

PLACE_NEAR=U5701.4:6mm

R7913

1 2

SOT891

74AUP1G3208

U7940

1

3

6

2

5

4

CERM

0.1uF

20% 10V

402

PLACE_NEAR=U7940.1:2.3mm

C7940

1

2

1/16W MF-LF

0

5%

NO STUFF

402

R7917

1 2

17

45 46

72 73

NO STUFF

PLACE_NEAR=U1800.G18:5mm

402

1/16W MF-LF

5%

0

R7916

1 2

17 45

SYNC_MASTER=K92_YUAN SYNC_DATE=07/22/2010

Power Control 1/ENABLE

MAKE_BASE=TRUE

SMC_S4_WAKESRC_EN

PP3V3_SUS

PM_SLP_S3_ENET

SMC_S4_WAKESRC_EN

PM_SLP_S3_L

P3V3_S4_EN

PM_SLP_S3_R_L

MAKE_BASE=TRUE

PM_SLP_S5_L

P3V3_S4_EN

MAKE_BASE=TRUE

PP3V3_SUS

VMON_PP5V_DIV

PP1V05_S0

PP5V_S0

PP1V5_S3RS0_CPUDDR

PM_SLP_S4_L

TPAD_VBUS_EN

Sus_PGOOD_CT

PM_RSMRST_L

P3V3S3_EN

DDRREG_EN

PM_SLP_S3_L

PM_WLAN_EN_L

P3V3ENET_SS

PP3V3_S3

P1V2S0_EN

S0PGD_BJT_GND_R

MAKE_BASE=TRUE

SMC_PM_G2_EN

P3V3S5_EN

MAKE_BASE=TRUE

P3V3S5_EN

S5_PWRGD

MAKE_BASE=TRUE

AC_EN_L

PVCCSA_PGOOD

VMON_Q2_BASE

WOL_EN

PM_SLP_S3_R_L

S0PGD_C

CPUVCCIOS0_PGOOD

P5VS3_PGOOD

VMON_Q4_BASE

CPUVCCIOS0_PGOOD

SMC_ADAPTER_EN

PM_SLP_S3_R_L

S5_PWRGD

P1V5S0_PGOOD

PP3V3_S0

CHGR_VFRQ

PP3V42_G3H

P1V8S0_PGOOD

PP3V3_S0

VMON_PP1V05_DIV

VMON_PP1V5_DIV

ALL_SYS_PWRGD_R

PP3V3_S5

P1V8S0_EN

AP_PWR_EN

PP3V3_ENET

PM_SLP_S3_R_L

PM_PECI_PWRGD

CPUIMVP_VR_ON

VMON_Q3_BASE

PP3V42_G3H

MAKE_BASE=TRUE

PM_SLP_S4_L

CPUVCCIOS0_EN

P1V5S0_EN

MAKE_BASE=TRUE

P1V5S0_EN

P1V2S0_EN

MAKE_BASE=TRUE

CPUVCCIOS0_EN

P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_EN

SMC_PM_G2_EN

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

PVCCSA_EN

ALL_SYS_PWRGD

PP3V3_S5

ALL_SYS_PWRGD

PP3V3_S0

PP1V05_S0

VMON_3V3_DIV

PP1V5_S3RS0_CPUDDR

PM_SUS_EN

PP3V3_S5

SMC_BATLOW_L

MAKE_BASE=TRUE

PM_SUS_EN

PM_SLP_SUS_L

ALL_SYS_PWRGD

79 OF 132 73 OF 105

45 46 73 86

7

16 17 18 19 20 22 46 71 72 73

49 72 73

72

73

7

16 17 18 19 20 22 46 71 72

73

6 7 8 22 41

47 52

54 65

68 69

70 87

104 105

7

10 13 15 29 73

104

6 7 8

18 24 25 29 30 31 32 48 49 50 54

55 88

104

66 73

70 73

45 66 73

6 7 12 23 25 26

28 32 35 36

39 40 41 46

48 49 50 51

52 54 57 61

62 72 73 80

83 84 85 88

89 91

100 102

6 7 25

42

44

45

46

47

48

53

63

64

73 104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102

104

7

25 36 71

6 7

25 42 44 45 46 47 48

53 63 64 73

104

71 73

70 73

72 73

67 73

71

73

65 73

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

23 45 73 88 91

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

7 9

10 12 13 14 23 35 39 45

68 70 73

102 104 105

7

10 13 15 29 73

104

72 73

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86 91

100 102 104

72 73

23 45 73 88 91

OUT

PCIE_TX4P PCIE_TX4N

PCIE_TX5P PCIE_TX5N

PCIE_TX6P PCIE_TX6N

PCIE_TX7P PCIE_TX7N

PCIE_TX8P PCIE_TX8N

PCIE_TX9P PCIE_TX9N

PCIE_TX10P PCIE_TX10N

PCIE_TX11P PCIE_TX11N

PCIE_TX12P PCIE_TX12N

PCIE_TX13P PCIE_TX13N

PCIE_TX14P PCIE_TX14N

PCIE_TX15P PCIE_TX15N

PCIE_TX3P PCIE_TX3N

PCIE_TX2P PCIE_TX2N

PCIE_TX1P PCIE_TX1N

PCIE_TX0P PCIE_TX0N

PCIE_CALRP PCIE_CALRN

PCIE_RX3P PCIE_RX3N

PCIE_RX2N

PCIE_RX2P

PCIE_RX1N

PCIE_RX0N

PCIE_RX0P

PCIE_RX7N

PCIE_RX7P

PCIE_RX6N

PCIE_RX6P

PCIE_RX5N

PCIE_RX4P PCIE_RX4N

PCIE_RX5P

PCIE_RX11N

PCIE_RX11P

PCIE_RX10N

PCIE_RX10P

PCIE_RX9N

PCIE_RX9P

PCIE_RX8N

PCIE_RX12P

PCIE_RX15N

PCIE_RX15P

PCIE_RX14N

PCIE_RX14P

PCIE_RX13N

PCIE_RX12N

PCIE_RX13P

PCIE_REFCLKP

PWRGOOD

PERST*

PCIE_REFCLKN

PCIE_RX8P

PCIE_RX1P

(1 OF 9)

PCIE

NC NC

NC

NC NC

IN

IN IN

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BOM options provided by this page:

Signal aliases required by this page:

(NONE)

Page Notes

(NONE)

- =PP1V2_GPU_PEX_PLLXVDD

- =PP1V2_GPU_PEX_IOVDD

- =PP1V2_GPU_PEX_IOVDDQ

Power aliases required by this page:

201

6.3V

X5R

0.1UF

10%

C8020

1 2

8

92

8

92

6.3V

X5R 201

0.1UF

10%

C8069

1 2

X5R 201

0.1UF

10%

6.3V

C8070

1 2

8

92

8

92

6.3V

X5R 201

0.1UF

10%

C8067

1 2

6.3V

X5R 201

0.1UF

10%

C8021

1 2

6.3V

X5R 201

0.1UF

10%

C8068

1 2

8

92

8

92

6.3V

X5R 201

0.1UF

10%

C8065

1 2

6.3V

X5R 201

0.1UF

10%

C8066

1 2

8

92

8

92

6.3V

X5R 201

0.1UF

10%

C8063

1 2

6.3V

X5R 201

0.1UF

10%

C8064

1 2

8

92

8

92

6.3V

X5R 201

0.1UF

10%

C8061

1 2

6.3V

X5R 201

0.1UF

10%

C8062

1 2

8

92

8

92

6.3V

X5R 201

0.1UF

10%

C8059

1 2

6.3V

X5R 201

0.1UF

10%

C8060

1 2

8

92

8

92

X5R 201

0.1UF

10%

6.3V

C8057

1 2

6.3V

X5R 201

0.1UF

10%

C8058

1 2

0

MF-LF

5%

402

1/16W

R8000

1 2

6.3V

X5R 201

0.1UF

10%

C8034

1 2

6.3V

X5R 201

0.1UF

10%

C8035

1 2

6.3V

X5R 201

0.1UF

10%

C8032

1 2

6.3V

X5R 201

0.1UF

10%

C8033

1 2

FCBGA

WHISTLER

40NM-ES

OMIT

U8000

Y29

Y30

AA36

AB35

Y37

AA38

K37

L38

J36

K35

H37

J38

G36

H35

F37

G38

E37

F35

W36

Y35

V37

W38

U36

V35

T37

U38

R36

T35

P37

R38

N36

P35

M37

N38

L36

M35

Y32

Y33

L32

L33

L29

L30

K32

K33

J32

J33

K29

K30

H32

H33

W32

W33

U32

U33

U29

U30

T32

T33

T29

T30

P32

P33

P29

P30

N32

N33

N29

N30

AA30

AH16

MF-LF

1/16W

1%

402

1.27K

R8002

1

2

2.0K

402

1%

MF-LF

1/16W

R8001

1

2

6.3V

X5R 201

0.1UF

10%

C8030

1 2

6.3V

X5R 201

0.1UF

10%

C8031

1 2

6.3V

X5R 201

0.1UF

10%

C8028

1 2

6.3V

X5R 201

0.1UF

10%

C8029

1 2

8

82 87 88 91

5%

0

MF-LF

1/16W

402

NOSTUFF

R8003

1 2

1/16W

5%

10K

402

MF-LF

R8004

1

2

6.3V

X5R 201

0.1UF

10%

C8026

1 2

6.3V

X5R 201

0.1UF

10%

C8027

1 2

6.3V

X5R 201

0.1UF

10%

C8024

1 2

6.3V

X5R 201

0.1UF

10%

C8025

1 2

6.3V

X5R 201

0.1UF

10%

C8022

1 2

6.3V

X5R 201

0.1UF

10%

C8023

1 2

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

8

92

16 95

8

88

6.3V

X5R 201

0.1UF

10%

C8055

1 2

6.3V

X5R 201

0.1UF

10%

C8056

1 2

8

92

8

92

Whistler PCI-E

SYNC_DATE=10/19/2010

SYNC_MASTER=K91_MLB

PEG_R2D_N<2>

PEG_D2R_C_P<6>

PEG_D2R_C_P<0>

PEG_D2R_P<2>

PEG_D2R_P<6>

PEG_D2R_N<6>

EG_RESET_L

PM_ALL_GPU_PGOOD

PEG_R2D_N<6>

PEG_D2R_C_P<7>

PEG_CALRP

GPU_RESET_R_L

GPU_PWRGOOD

PP1V0_S0GPU

PEG_CLK100M_N

PEG_D2R_C_N<7>

PEG_D2R_N<0>

PEG_R2D_N<4>

PEG_D2R_C_P<4>

PEG_R2D_C_P<0>

PEG_R2D_P<3>

PEG_R2D_N<1>

PEG_R2D_P<6>

PEG_R2D_N<7>

PEG_R2D_P<2> PEG_R2D_N<2>

PEG_R2D_P<7>

PEG_D2R_C_P<4> PEG_D2R_C_N<4>

PEG_D2R_C_P<5> PEG_D2R_C_N<5>

PEG_D2R_C_P<6> PEG_D2R_C_N<6>

PEG_D2R_C_P<7> PEG_D2R_C_N<7>

PEG_D2R_C_P<3> PEG_D2R_C_N<3>

PEG_D2R_C_P<2> PEG_D2R_C_N<2>

PEG_D2R_C_P<1> PEG_D2R_C_N<1>

PEG_D2R_C_P<0> PEG_D2R_C_N<0>

PEG_R2D_N<3>

PEG_R2D_N<0>

PEG_R2D_P<0>

PEG_R2D_N<6>

PEG_R2D_N<5>

PEG_R2D_P<4>

PEG_R2D_P<5>

PEG_R2D_P<1>

PEG_D2R_P<0>

PEG_D2R_C_P<1>

PEG_D2R_P<1>

PEG_D2R_C_N<1>

PEG_D2R_N<1>

PEG_D2R_C_P<2>

PEG_D2R_C_N<2>

PEG_D2R_N<2>

PEG_R2D_P<0>

PEG_R2D_P<1>

PEG_R2D_C_P<1>

PEG_R2D_C_P<2>

PEG_R2D_C_N<2>

PEG_D2R_C_P<3>

PEG_D2R_P<3>

PEG_R2D_C_P<3>

PEG_D2R_C_N<3>

PEG_D2R_N<3>

PEG_D2R_P<4>

PEG_D2R_C_N<4>

PEG_D2R_N<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_C_N<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_R2D_N<3>

PEG_R2D_N<4>

PEG_R2D_P<5>

PEG_R2D_N<5>

PEG_R2D_P<6>

PEG_R2D_P<7>

PEG_R2D_N<7>

PEG_R2D_C_N<3>

PEG_R2D_C_P<4>

PEG_R2D_C_N<4>

PEG_R2D_C_P<5>

PEG_R2D_C_N<5>

PEG_R2D_C_P<6>

PEG_R2D_C_N<6>

PEG_R2D_C_P<7>

PEG_R2D_C_N<7>

PEG_D2R_C_P<5>

PEG_R2D_N<0>

PEG_D2R_C_N<0>

PEG_CLK100M_P

PEG_CALRN

PEG_D2R_C_N<5>

PEG_R2D_C_N<0>

PEG_R2D_C_N<1>

PEG_R2D_P<4>

PEG_R2D_P<3>

PEG_R2D_N<1>

PEG_R2D_P<2>

80 OF 132 74 OF 105

74 92

7

75 79 81

103

74 92

74 92 74 92

74 92

VDDC_V22

MPV18_H8

MPV18_H7

VDDR1_U11 VDDR1_Y7 VDDR1_Y11

VDDR1_U7

VDDR1_L12

VDDR1_L7

VDDR1_L16

VDDR1_N11 VDDR1_P7 VDDR1_R11

VDDR1_M11

VDDR1_L26

VDDR1_L23

VDDR1_L21

VDDR1_G20 VDDR1_G23 VDDR1_G26

VDDR1_K13

VDDR1_K11

VDDR1_K8

VDDR1_J9

VDDR1_J7

VDDR1_H10

VDDR1_G29

VDDR1_AD11

VDDR1_AC7

VDDR1_G17

VDDR1_G14

VDDR1_G11

VDDR1_AL9

VDDR1_AK8

VDDR1_AJ7

VDDR1_AG10

VDDR1_AF7

PCIE_VDDC_N28

PCIE_VDDC_M28

PCIE_VDDC_L28

PCIE_VDDC_H29

PCIE_VDDC_R28

PCIE_VDDC_U28

PCIE_VDDC_T28

SPV10

SPVSS

FB_VDDC

FB_VDDCI

FB_GND

PCIE_VDDR_AA31 PCIE_VDDR_AA32

PCIE_VDDR_W29 PCIE_VDDR_W30

PCIE_VDDR_AA34

PCIE_VDDR_V28

PCIE_VDDR_AB37

PCIE_VDDR_AA33

PCIE_VDDR_Y31

PCIE_VDDC_G30

SPV18

VDDR4_AD12

VDDR4_AG15

VDDR4_AG13

VDDR4_AF15

VDDR4_AF13

VDDR3_AG23 VDDR3_AG24

NC/VDDRHB

NC/VSSRHB

NC/VSSRHA

NC/VDDRHA

VDDR4_AF11 VDDR4_AF12 VDDR4_AG11

VDDR3_AF23

VDD_CT_AG27

VDD_CT_AG26

VDD_CT_AF26 VDD_CT_AF27

VDDR3_AF24

BIF_VDDC_T27

VDDC_U16

VDDC_U23

VDDC_U18 VDDC_U21

VDDC_U26 VDDC_V17 VDDC_V20

VDDC_V24 VDDC_V27 VDDC_Y16

VDDC_Y21

VDDC_Y26

VDDC_Y23

VDDC_Y18

VDDC_Y28

VDDC_T24

VDDC_AA24

VDDC_AA20 VDDC_AA22

VDDC_AA17

VDDC_AA15

VDDC_AA27 VDDC_AB16 VDDC_AB18 VDDC_AB21 VDDC_AB23

VDDC_AB28

VDDC_AB26

VDDC_AC17

VDDC_AC24

VDDC_AC20 VDDC_AC22

VDDC_AC27 VDDC_AD18 VDDC_AD21 VDDC_AD23 VDDC_AD26 VDDC_AF17 VDDC_AF20

VDDC_AG18

VDDC_AF22 VDDC_AG16

BIF_VDDC_N27

VDDC_AG21 VDDC_AH22 VDDC_AH27 VDDC_AH28

VDDC_M26 VDDC_N24

VDDC_R23

VDDC_R18 VDDC_R21

VDDC_R26 VDDC_T17

VDDC_T22

VDDC_T20

VDDCI_AC15

VDDCI_T15

VDDCI_T12

VDDCI_R16

VDDCI_M23

VDDCI_M18

VDDCI_M16

VDDCI_M15

VDDCI_AD16

VDDCI_AC12

VDDCI_AB13

VDDCI_AA13

VDDCI_AD13

VDDCI_R13

VDDCI_R12

VDDCI_N22

PCIE_VDDC_G31

PCIE_VDDC_H30 PCIE_VDDC_J29 PCIE_VDDC_J30

VDDCI_V15 VDDCI_Y13

VDDCI_N13

VDDCI_N20

VDDCI_N17

VDDCI_N15

PCIE

ISOLATED CORE I/O

VOLT

SENSE

PLL I/O

LEVEL

TRNSL

CORE

MEM I/O

(7 OF 9)

NC NC

NC

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TBD mA

- =PP3V3_GPU_VDDR4

- =PP3V3_GPU_VDDR3

- =PP1V8_GPU_MEM_PLL

- =PP1V8_GPU_PLL

- =PP1V8_GPU_PCIE_VDDR

- =PP1V8_GPU_PCIE_VDDC

219mA

1920mA

504mA

75mA 120mA

150mA

Page Notes

60 mA

(NONE)

Signal aliases required by this page:

(NONE)

BOM options provided by this page:

- =PPVCORE_GPU

- =PP1V0_GPU_PLL

- =PP1V8_GPU_VDD_CT

- =PP1V5R1V35_GPU_FB_VDDR1

Power aliases required by this page:

OMIT

FCBGA

WHISTLER

40NM-ES

U8000

N27

T27

AH29

AF28

AG28

H7 H8

M20 M21

U12 V12

G30 G31 H29 H30 J29 J30 L28 M28 N28 R28 T28 U28

AA31 AA32 AA33 AA34 AB37

V28 W29 W30 Y31

AN9

AM10

AN10

AF26 AF27 AG26 AG27

AA15 AA17 AA20 AA22 AA24 AA27 AB16 AB18 AB21 AB23 AB26 AB28 AC17 AC20 AC22 AC24 AC27 AD18 AD21 AD23 AD26 AF17 AF20 AF22 AG16 AG18 AG21 AH22 AH27 AH28 M26 N24

R18 R21 R23 R26 T17 T20 T22 T24

U16 U18 U21 U23 U26 V17 V20 V22 V24 V27 Y16 Y18 Y21 Y23 Y26 Y28

AA13 AB13 AC12 AC15 AD13 AD16 M15 M16 M18 M23 N13 N15 N17 N20 N22 R12 R13 R16 T12 T15 V15 Y13

AC7

AD11

AF7

AG10

AJ7 AK8 AL9 G11 G14 G17 G20 G23 G26 G29 H10

J7 J9

K11 K13

K8

L12 L16 L21 L23 L26

L7

M11 N11

P7

R11

U11

U7

Y11

Y7

AF23 AF24 AG23 AG24

AD12 AF11 AF12

AF13 AF15

AG11

AG13 AG15

FERR-220-OHM-2A

CRITICAL

0603

L8140

1 2

603

X5R

20%

10UF

10V

C8145

1

2

402

10%

1UF

X5R

25V

C8146

1

2

402

10%

1UF

X5R

25V

C8147

1

2

10%

402

X5R

25V

1UF

C8148

1

2

6.3V X5R

10%

0.1UF

201

C8149

1

2

6.3V

10% X5R

201

0.1UF

C8150

1

2

402

10%

1UF

X5R

25V

C8154

1

2

402

10%

1UF

X5R

25V

C8153

1

2

402

25V X5R

1UF

10%

C8152

1

2

10V 603

20%

10UF

X5R

C8151

1

2

402

1UF

10% X5R

25V

C8157

1

2

402

1UF

10% X5R

25V

C8156

1

2

402

10%

1UF

X5R

25V

C8155

1

2

402

25V

10%

1UF

X5R

C8158

1

2

603

10UF

10V X5R

20%

C8100

1

2

1UF

25V 402

X5R

10%

C8110

1

2

10%

402

1UF

25V X5R

C8111

1

2

402

1UF

10% 25V X5R

C8112

1

2

1UF

402

10% 25V X5R

C8113

1

2

402

10% 25V X5R

1UF

C8114

1

2

10UF

10V 603

X5R

20%

C8101

1

2

603

10UF

10V X5R

20%

C8102

1

2

603

X5R

20% 10V

10UF

C8103

1

2

10UF

10V X5R

20%

603

C8104

1

2

402

10%

1UF

25V X5R

C8108

1

2

402

10%

1UF

25V X5R

C8109

1

2

X5R

6.3V

0.1UF

10%

201

C8117

1

2

X5R

6.3V

0.1UF

10%

201

C8118

1

2

X5R

6.3V

10%

0.1UF

201

C8119

1

2

X5R

6.3V

10%

0.1UF

201

C8120

1

2

X5R

6.3V

10%

0.1UF

201

C8121

1

2

X5R

6.3V

10%

0.1UF

201

C8122

1

2

X5R

6.3V

10%

0.1UF

201

C8123

1

2

X5R

6.3V

0.1UF

10%

201

C8124

1

2

X5R

6.3V

0.1UF

10%

201

C8116

1

2

X5R 402

10%

1UF

25V

C8136

1

2

25V

10%

402

1UF

X5R

C8135

1

2

402

10% X5R

25V

1UF

C8134

1

2

603

10UF

10V X5R

20%

C8133

1

2

1UF

402

10% X5R

25V

C8127

1

2

402

10%

1UF

X5R

25V

C8126

1

2

603

X5R

10UF

20% 10V

C8125

1

2

402

1UF

10% X5R

25V

C8128

1

2

X5R

6.3V

10%

0.1UF

201

C8129

1

2

CRITICAL

0402

120OHM-0.3A

L8120

1 2

402

10% 25V X5R

1UF

C8139

1

2

402

10%

1UF

X5R

25V

C8138

1

2

603

10V X5R

10UF

20%

C8137

1

2

X5R

6.3V

10%

0.1UF

201

C8140

1

2

X5R

6.3V

10%

0.1UF

201

C8141

1

2

CRITICAL

470OHM-1A-150MOHM

0603

L8131

1 2

402

25V X5R

1UF

10%

C8143

1

2

603

10V

10UF

20% X5R

C8142

1

2

CRITICAL

120OHM-0.3A

0402

L8132

1 2

0.1UF

X5R

10%

6.3V 201

C8144

1

2

SM

XW8100

1 2

82

CRITICAL

470OHM-1A-150MOHM

0603

L8130

1 2

X5R

25V

1UF

10%

402

C8131

1

2

20%

10UF

X5R

10V 603

C8130

1

2

6.3V

0.1UF

10% X5R

201

C8132

1

2

402

25V X5R

1UF

10%

C8166

1

2

402

25V X5R

1UF

10%

C8165

1

2

402

25V X5R

1UF

10%

C8164

1

2

402

25V X5R

1UF

10%

C8163

1

2

402

25V X5R

1UF

10%

C8162

1

2

25V X5R 402

1UF

10%

C8161

1

2

402

25V X5R

1UF

10%

C8160

1

2

402

25V X5R

1UF

10%

C8167

1

2

402

25V X5R

1UF

10%

C8168

1

2

402

25V X5R

1UF

10%

C8169

1

2

402

25V X5R

1UF

10%

C8179

1

2

402

25V X5R

1UF

10%

C8178

1

2

402

25V X5R

1UF

10%

C8177

1

2

402

25V X5R

1UF

10%

C8176

1

2

402

25V X5R

1UF

10%

C8175

1

2

25V 402

X5R

1UF

10%

C8174

1

2

402

25V X5R

1UF

10%

C8173

1

2

402

25V X5R

1UF

10%

C8172

1

2

402

25V

1UF

10% X5R

C8171

1

2

25V 402

1UF

10% X5R

C8170

1

2

402

25V X5R

1UF

10%

C8189

1

2

402

25V X5R

1UF

10%

C8188

1

2

402

25V X5R

1UF

10%

C8187

1

2

402

25V X5R

1UF

10%

C8186

1

2

402

25V X5R

1UF

10%

C8185

1

2

402

25V X5R

1UF

10%

C8184

1

2

402

25V X5R

1UF

10%

C8183

1

2

402

25V X5R

1UF

10%

C8182

1

2

402

25V X5R

1UF

10%

C8181

1

2

402

25V X5R

1UF

10%

C8180

1

2

X5R

6.3V

0.1UF

10%

201

C8115

1

2

402

1UF

10% 25V X5R

C8107

1

2

402

1UF

10% 25V X5R

C8106

1

2

1UF

402

10% 25V X5R

C8105

1

2

603

10V X5R

10UF

20%

C8199

1

2

603

20%

10UF

X5R

10V

C8198

1

2

603

20%

10UF

X5R

10V

C8197

1

2

603

20%

10UF

X5R

10V

C8196

1

2

603

10V X5R

10UF

20%

C8195

1

2

603

10V X5R

10UF

20%

C8194

1

2

20%

603

10UF

X5R

10V

C8193

1

2

X5R 603

20%

10UF

10V

C8192

1

2

X5R 603

20%

10UF

10V

C8191

1

2

10UF

603

20% 10V X5R

C8190

1

2

402

10%

1UF

X5R

25V

C81A9

1

2

402

10%

1UF

X5R

25V

C81A8

1

2

402

10%

1UF

X5R

25V

C81A7

1

2

402

25V X5R

1UF

10%

C81A6

1

2

X5R 402

25V

1UF

10%

C81A5

1

2

402

25V X5R

1UF

10%

C81A4

1

2

402

25V X5R

1UF

10%

C81A3

1

2

402

25V X5R

1UF

10%

C81A2

1

2

402

1UF

25V X5R

10%

C81A1

1

2

402

25V X5R

1UF

10%

C81A0

1

2

603

10UF

10V X5R

20%

C81B2

1

2

603

10UF

20% 10V X5R

C81B1

1

2

603

10UF

20% X5R

10V

C81B0

1

2

X5R

6.3V

10%

0.1UF

201

C81C1

1

2

402

10%

1UF

25V X5R

C81C0

1

2

CRITICAL

120OHM-0.3A

0402

L8150

1 2

CRITICAL

FERR-120-OHM-3A

0603

L8155

1 2

Whistler CORE/FB POWER

SYNC_DATE=06/03/2010

SYNC_MASTER=K92_BEN

PP1V8_S0GPU

PP3V3_S0GPU

GPU_GND_SENSE

GPU_VDD_SENSE

PP1V0_GPU_PLL

PP1V8_GPU_VDDR4

PP1V8_S0GPU

PP1V0_S0GPU

GND_GPU_PLL

PP1V0_S0GPU

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V

MIN_LINE_WIDTH=0.25 mm

PP1V0_GPU_PLL

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP1V8_GPU_VDD_CT

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_GPU_PLL

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_GPU_VDDR4

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V

PP1V0_GPU_PCIE_VDDC

VOLTAGE=1.8V

PP1V8_GPU_MEM_PLL

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_PCIE_VDDR

PPVCORE_GPU

PP1V5R1V35_GPU_FB_ISNS

GND_GPU_PLL

MIN_LINE_WIDTH=0.25 mm VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

81 OF 132 75 OF 105

6 7

75 79 81

103

6 7

75 79 81

103

6 7

75 79 81

103

6 7

72 79 80 82 84

75

6 7

75 79 81

103

6 7

75 79 81

103

7

74 75 79 81

103

75

7

74 75 79 81

103

6 7

49 82

7

76 77 78

103

75

BI

BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

OUT

DQA0_31/DQA_31

DQA0_27/DQA_27

DQA0_29/DQA_29

DQA0_25/DQA_25

DQA0_21/DQA_21 DQA0_22/DQA_22 DQA0_23/DQA_23 DQA0_24/DQA_24

DQA0_28/DQA_28

DQA0_26/DQA_26

DQA0_30/DQA_30

DQA0_20/DQA_20

DQA0_16/DQA_16 DQA0_17/DQA_17 DQA0_18/DQA_18 DQA0_19/DQA_19

DQA0_12/DQA_12 DQA0_13/DQA_13 DQA0_14/DQA_14

DQA0_4/DQA_4

DQA0_3/DQA_3

DQA0_0/DQA_0

DQA0_9/DQA_9

DQA0_8/DQA_8

DQA0_7/DQA_7

DQA0_6/DQA_6

DQA0_5/DQA_5

MEM_CALRN1

MEM_CALRN0

MEM_CALRN2

MEM_CALRP0 MEM_CALRP1 MEM_CALRP2

MVREFSA

DQA1_29/DQA_61 DQA1_30/DQA_62 DQA1_31/DQA_63

MVREFDA

DQA1_28/DQA_60

DQA1_24/DQA_56 DQA1_25/DQA_57 DQA1_26/DQA_58 DQA1_27/DQA_59

DQA1_23/DQA_55

DQA1_19/DQA_51 DQA1_20/DQA_52 DQA1_21/DQA_53 DQA1_22/DQA_54

DQA1_15/DQA_47 DQA1_16/DQA_48 DQA1_17/DQA_49

DQA1_9/DQA_41 DQA1_10/DQA_42 DQA1_11/DQA_43 DQA1_12/DQA_44 DQA1_13/DQA_45 DQA1_14/DQA_46

DQA1_18/DQA_50

DQA1_8/DQA_40

DQA1_3/DQA_35

DQA1_5/DQA_37

DQA1_4/DQA_36

DQA1_6/DQA_38 DQA1_7/DQA_39

DQA1_0/DQA_32 DQA1_1/DQA_33 DQA1_2/DQA_34

EDCA0_1/QSA_1/RDQSA_1 EDCA0_2/QSA_2/RDQSA_2

WCKA1_0*/DQMA_5

MAA0_7/MMA_7

MAA0_2/MMA_2

MAA0_0/MMA_0 MAA0_1/MMA_1

MAA0_4/MMA_4

MAA0_3/MMA_3

MAA1_8

MAA0_8

CLKA1

CLKA0

ADBIA1/ODTA1

CKEA0

DDBIA1_3/QSA_7B/WDQSA_7

DDBIA0_1/QSA_1B/WDQSA_1 DDBIA0_2/QSA_2B/WDQSA_2 DDBIA0_3/QSA_3B/WDQSA_3

DDBIA0_0/QSA_0B/WDQSA_0

EDCA1_2/QSA_6/RDQSA_6

DQA0_15/DQA_15

DQA0_1/DQA_1 DQA0_2/DQA_2

DQA0_10/DQA_10 DQA0_11/DQA_11

MAA0_6/MMA_6

MAA1_0/MMA_8

WCKA0_0/DQMA_0

WCKA0_0*/DQMA_1

MAA1_5/MMA_13_BA2

WCKA1_0/DQMA_4

WCKA1_1/DQMA_6

WCKA1_1*/DQMA_7

EDCA0_0/QSA_0/RDQSA_0

WCKA0_1/DQMA_2

EDCA0_3/QSA_3/RDQSA_3

EDCA1_0/QSA_4/RDQSA_4 EDCA1_1/QSA_5/RDQSA_5

DDBIA1_0/QSA_4B/WDQSA_4 DDBIA1_1/QSA_5B/WDQSA_5

RASA1*

CASA0* CASA1*

CSA0_0* CSA0_1*

CSA1_0* CSA1_1*

CKEA1

WEA0* WEA1*

CLKA0*

RASA0*

ADBIA0/ODTA0

CLKA1*

DDBIA1_2/QSA_6B/WDQSA_6

MAA0_5/MMA_5

MAA1_1/MMA_9

MAA1_2/MMA_10

MAA1_4/MMA_12

MAA1_6/MMA_14_BA0

MAA1_3/MMA_11

MAA1_7/MMA_A15_BA1

WCKA0_1*/DQMA_3

EDCA1_3/QSA_7/RDQSA_7

MEM INTERFACE A

(4 OF 9)

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

BI BI

BI BI BI BI

BI BI

NC

OUT OUT

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

DQB0_31/DQB_31

DQB1_1/DQB33

MAB0_4/MAB_4

MAB0_6/MAB_6

MAB1_1/MAB_9

DQB1_0/DQB32

DQB0_30/DQB_30

CKEB1

CKEB0

CSB1_1*

WEB1*

WEB0*

RASB1*

RASB0*

CLKB1*

CASB0* CASB1*

CSB0_0* CSB0_1*

CSB1_0*

ADBIB1/ODTB1

ADBIB0/ODTB0

DDBIB1_2/QSB_6B/WDQSB_6 DDBIB1_3/QSB_7B/WDQSB_7

DDBIB1_0/QSB_4B/WDQSB_4 DDBIB1_1/QSB_5B/WDQSB_5

CLKB0

CLKB0*

CLKB1

DDBIB0_2/QSB_2B/WDQSB_2

DDBIB0_1/QSB_1B/WDQSB_1

DDBIB0_3/QSB_3B/WDQSB_3

DDBIB0_0/QSB_0B/WDQSB_0

MAB0_8 MAB1_8

DRAM_RST

EDCB1_3/QSB_7/RDQSB_7

EDCB1_1/QSB_5/RDQSB_5 EDCB1_2/QSB_6/RDQSB_6

EDCB1_0/QSB_4/RDQSB_4

EDCB0_3/QSB_3/RDQSB_3

EDCB0_1/QSB_1/RDQSB_1 EDCB0_2/QSB_2/RDQSB_2

EDCB0_0/QSB_0/RDQSB_0

WCKB1_1*/DQMB_7

WCKB1_1/DQMB_6

WCKB1_0/DQMB_4

WCKB1_0*/DQMB_5

WCKB0_1*/DQMB_3

WCKB0_1/DQMB_2

MAB1_3/MAB_11

MAB1_6/BA0

MAB1_5/BA2

MAB1_7/BA1

MAB1_2/MAB_10

MAB1_4/MAB_12

WCKB0_0/DQMB_0

WCKB0_0*/DQMB_1

MAB0_7/MAB_7

MAB0_5/MAB_5

MAB0_2/MAB_2 MAB0_3/MAB_3

MAB0_1/MAB_1

MAB0_0/MAB_0

MAB1_0/MAB_8

DQB1_8/DQB40

DQB1_3/DQB35

DQB1_2/DQB34

DQB1_7/DQB39

DQB1_6/DQB38

DQB1_4/DQB36 DQB1_5/DQB37

DQB0_0/DQB_0 DQB0_1/DQB_1

DQB0_3/DQB_3 DQB0_4/DQB_4

DQB0_2/DQB_2

DQB0_9/DQB_9

DQB0_8/DQB_8

DQB0_6/DQB_6 DQB0_7/DQB_7

DQB0_5/DQB_5

DQB0_11/DQB_11

DQB0_10/DQB_10

DQB0_20/DQB_20 DQB0_21/DQB_21

DQB0_15/DQB_15

DQB0_12/DQB_12 DQB0_13/DQB_13 DQB0_14/DQB_14

DQB0_18/DQB_18 DQB0_19/DQB_19

DQB0_17/DQB_17

DQB0_16/DQB_16

DQB0_23/DQB_23 DQB0_24/DQB_24

DQB0_22/DQB_22

DQB0_25/DQB_25

DQB0_27/DQB_27

DQB0_26/DQB_26

DQB0_28/DQB_28 DQB0_29/DQB_29

DQB1_10/DQB42 DQB1_11/DQB43

DQB1_13/DQB45

DQB1_12/DQB44

DQB1_16/DQB48

DQB1_14/DQB46 DQB1_15/DQB47

DQB1_18/DQB50

DQB1_17/DQB49

DQB1_21/DQB53

DQB1_20/DQB52

DQB1_19/DQB51

DQB1_23/DQB55

DQB1_22/DQB54

DQB1_26/DQB58

DQB1_24/DQB56 DQB1_25/DQB57

DQB1_27/DQB59 DQB1_28/DQB60

DQB1_30/DQB62 DQB1_31/DQB63

DQB1_29/DQB61

MVREFDB MVREFSB

TESTEN

CLKTESTA CLKTESTB

DQB1_9/DQB41

MEM INTERFACE B

(5 OF 9)

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT OUT OUT OUT OUT OUT

BI

OUT OUT OUT OUT OUT OUT OUT OUT

BI

BI BI

BI

BI BI BI

BI

OUT OUT

OUT

OUT OUT

OUT

NC

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Power aliases required by this page:

Page Notes

BOM options provided by this page:

Signal aliases required by this page:

(NONE)

- =PP1V5R1V35_FB_CAL

- =PP1V5R1V35_FB_REF

77 99

WHISTLER

40NM-ES

FCBGA

OMIT

U8000

J21 G19

K20 K17

K21 J20

H27 G27

J14 H14

K24 K27

M13 K16

A34 E30 E26 C20

C16 C12 J11 F8

C37 C35

C30 A30 F28 C28 A28 E28 D27 F26 C26 A26

A35

F24 C24 A24 E24 C22 A22 F22 D21 A20 F20

E34

D19 E18

G32 D33 F32 E32 D31 F30

C18 A18

F12 A12 D11 F10 A10 C10 G13 H13 J13 H11

F18

G10

G8 K9

K10

G9 A8 C8 E8 A6 C6

D17

E6 A5

A16 F16 D15 E14 F14 D13

C34 D29 D25 E20

E16 E12 J10 D7

G24 J23 H24 J24 H26 J26 H21 G21

H23

H19 H20 L13 G16 J16 H16 J17 H17

J19

L27 N12

AG12

M27 M12

AH12

L18 L20

K23 K19

A32 C32

D23 E22

C14 A14

E10 D9

K26 L15

77 99

78 99

40NM-ES

FCBGA

OMIT

WHISTLER

U8000

T7 W7

W10 AA10

U10 AA11

L9 L8

AD8 AD7

AK10 AL10

P10 L10

AD10 AC10

G7 K1 P1 W4

AC4 AH3 AJ8 AM3

C5 C3

J4 K6 K5 L4 M6 M1 M3 M5 N4 P6

E3

P5 R4 T6 T1 U4 V6 V1 V3 Y6 Y1

E1

Y3 Y5

F1 F3 F5 G4 H5 H6

AA4 AB6

AF6 AG4 AH5 AH6 AJ4 AK3 AF8 AF9 AG8 AG7

AB1

AK9 AL7 AM8 AM7 AK1 AL4 AM6 AM1 AN4 AP3

AB3

AP1 AP5

AD6 AD1 AD3 AD5 AF1 AF3

AH11

F6 K3 P3 V5

AB5 AH1 AJ9 AM5

P8 T9 P9 N7 N8 N9 U9 U8

T8

Y9 W9 AC8 AC9 AA7 AA8 Y8 AA9

W8

Y12

AA12

T10 Y10

AD28

H3 H1

T3 T5

AE4 AF5

AK6 AK5

N10 AB11

78 99

77 99

78 99

10K

5% 1/16W MF-LF

402

R8250

1

2

243

4021%1/16W MF-LF

R8210

1 2

MF-LF

243

1/16W

402

1%

R8211

1 2

243

1/16W1%MF-LF

402

R8212

1 2

243

402

MF-LF1/16W

1%

R8214

1 2

402

MF-LF1/16W

1%

243

R8213

1 2

1/16W

243

1%

MF-LF

402

R8215

1 2

40.2

1% 1/16W MF-LF 402

PLACE_NEAR=U8000.L18:2.54MM

R8200

1

2

100

1% 1/16W MF-LF 402

PLACE_NEAR=U8000.L18:2.54MM

R8201

1

2

16V X5R

0.1UF

10%

402-1

PLACE_NEAR=U8000.L18:2.54MM

C8200

1

2

402-1

10%

0.1UF

X5R

16V

NOSTUFF

C8251

1

2

402-1

10%

0.1UF

X5R

16V

NOSTUFF

C8252

1

2

50V

5% CERM

120PF

402

C8260

1

2

MF-LF

1/16W

5%

5.1K

402

R8260

1

2

5%

51

1/16W MF-LF

402

R8262

1 2

402

MF-LF

1/16W

10

5%

R8261

1 2

402

MF-LF

1/16W

1%

51.1

NOSTUFF

R8251

1

2

402

MF-LF

1/16W

1%

51.1

NOSTUFF

R8252

1

2

77 78 99

402-1

10%

0.1UF

X5R

16V

PLACE_NEAR=U8000.L20:2.54MM

C8201

1

2

402

MF-LF

1/16W

1%

40.2

PLACE_NEAR=U8000.L20:2.54MM

R8202

1

2

402

MF-LF

1/16W

1%

100

PLACE_NEAR=U8000.L20:2.54MM

R8203

1

2

402-1

10%

0.1UF

X5R

16V

PLACE_NEAR=U8000.Y12:2.54MM

C8202

1

2

402

MF-LF

1/16W

1%

40.2

PLACE_NEAR=U8000.Y12:2.54MM

R8204

1

2

402

1/16W

1%

100

MF-LF

PLACE_NEAR=U8000.Y12:2.54MM

R8205

1

2

402-1

10%

0.1UF

X5R

16V

PLACE_NEAR=U8000.AA12:2.54MM

C8203

1

2

402

1/16W

40.2

MF-LF

1%

PLACE_NEAR=U8000.AA12:2.54MM

R8206

1

2

402

MF-LF

1%

100

PLACE_NEAR=U8000.AA12:2.54MM

1/16W

R8207

1

2

SYNC_MASTER=K18_MLB

SYNC_DATE=04/27/2010

Whistler FRAME BUFFER I/F

GPU_CLK_TEST_N

FB_B_VREFS

FB_CALRP2

FB_B_VREFS

FB_B_VREFD

FB_B1_DQ<31>

FB_A0_DQ<10>

FB_A0_DQ<12>

FB_A1_CLK_N

FB_A1_CLK_P

FB_A0_CLK_N

FB_A1_ABI_L

FB_A1_DBI_L<3>

FB_A1_DBI_L<2>

PP1V5R1V35_GPU_FB_ISNS

GPU_CLK_TEST_RC_N

FB_B1_CS_L

FB_B1_WE_L

FB_A_VREFD

FB_A_VREFS

FB_B_VREFD

PP1V5R1V35_GPU_FB_ISNS

GPU_FB_RESET_L

GPU_CLK_TEST_RC_P

FB_B0_DQ<0>

FB_B0_DQ<4>

FB_B1_DBI_L<2>

FB_B0_DQ<9> FB_B0_DQ<10>

FB_B1_DBI_L<3>

FB_RESET_L

FB_RESET_RC_L

FB_B1_ABI_L

FB_B0_ABI_L

FB_A1_DQ<23> FB_A1_DQ<24>

FB_A1_DQ<29>

FB_A1_WCLK_N<0> FB_A1_WCLK_P<1>

FB_B1_DQ<9>

FB_B1_DQ<1>

FB_A1_EDC<2>

FB_A0_DQ<8> FB_A0_DQ<9>

FB_A0_EDC<1>

FB_B1_DQ<8>

FB_B1_DQ<10> FB_B1_DQ<11>

FB_A1_EDC<3>

FB_A1_DQ<31>

FB_A1_DQ<30>

FB_A1_DQ<28>

FB_A1_DQ<27>

FB_A1_DQ<26>

FB_A1_DQ<25>

FB_A1_DQ<22>

FB_A1_DQ<21>

FB_A1_DQ<20>

FB_A1_DQ<19>

FB_A1_DQ<17>

FB_A1_DQ<16>

FB_A1_DQ<15>

FB_A1_DQ<14>

FB_A1_DQ<13>

FB_A1_DQ<12>

FB_A1_DQ<11>

FB_A1_DQ<10>

FB_A1_DQ<9>

FB_A1_DQ<8>

FB_A1_DQ<7>

FB_A1_DQ<6>

FB_A1_DQ<5>

FB_A1_DQ<4>

FB_A1_DQ<3>

FB_A1_DQ<1>

FB_A1_DQ<0>

FB_A0_DQ<31>

FB_A0_DQ<30>

FB_A0_DQ<29>

FB_A0_DQ<28>

FB_A0_DQ<27>

FB_A0_DQ<26>

FB_A0_DQ<25>

FB_A0_DQ<24>

FB_A0_DQ<23>

FB_A0_DQ<22>

FB_A0_DQ<21>

FB_A0_DQ<20>

FB_A0_DQ<18> FB_A0_DQ<19>

FB_A0_DQ<17>

FB_A0_DQ<16>

FB_A0_DQ<15>

FB_A0_DQ<13> FB_A0_DQ<14>

FB_A0_DQ<11>

FB_A0_DQ<5>

FB_A0_DQ<3>

FB_A0_DQ<1>

FB_A1_A<8>

FB_A0_A<8>

FB_A1_WE_L

FB_A1_CKE_L FB_A0_WE_L

FB_A0_CKE_L

FB_A1_CS_L

FB_A0_CS_L

FB_A1_CAS_L

FB_A0_CAS_L

FB_A1_RAS_L

FB_A0_RAS_L

FB_B1_DQ<29>

FB_B1_DQ<26> FB_B1_DQ<27>

FB_B1_DQ<24> FB_B1_DQ<25>

FB_B1_DQ<23>

FB_B1_DQ<21> FB_B1_DQ<22>

FB_B1_DQ<19> FB_B1_DQ<20>

FB_B1_DQ<18>

FB_B1_DQ<17>

FB_B1_DQ<14>

FB_B1_DQ<13>

FB_B0_DQ<29>

FB_B0_DQ<28>

FB_B0_DQ<26> FB_B0_DQ<27>

FB_B0_DQ<25>

FB_B0_DQ<22>

FB_B0_DQ<24>

FB_B0_DQ<23>

FB_B0_DQ<16> FB_B0_DQ<17>

FB_B0_DQ<19>

FB_B0_DQ<18>

FB_B0_DQ<14>

FB_B0_DQ<13>

FB_B0_DQ<12>

FB_B0_DQ<15>

FB_B0_DQ<21>

FB_B0_DQ<20>

FB_B0_DQ<11>

FB_B0_DQ<5>

FB_B0_DQ<7>

FB_B0_DQ<6>

FB_B0_DQ<8>

FB_B0_DQ<2> FB_B0_DQ<3>

FB_B0_DQ<1>

FB_B1_DQ<5>

FB_B1_DQ<4>

FB_B1_DQ<6> FB_B1_DQ<7>

FB_B1_DQ<2> FB_B1_DQ<3>

FB_B1_A<0>

FB_B0_A<0> FB_B0_A<1>

FB_B0_A<3>

FB_B0_A<2>

FB_B0_A<5>

FB_B0_A<7>

FB_B0_WCLK_N<0>

FB_B0_WCLK_P<0>

FB_B1_A<4>

FB_B1_A<2>

FB_B1_A<7>

FB_B1_A<5> FB_B1_A<6>

FB_B1_A<3>

FB_B0_WCLK_P<1> FB_B0_WCLK_N<1>

FB_B1_WCLK_N<0>

FB_B1_WCLK_P<0>

FB_B1_WCLK_P<1> FB_B1_WCLK_N<1>

FB_B0_EDC<0>

FB_B0_EDC<2>

FB_B0_EDC<1>

FB_B0_EDC<3> FB_B1_EDC<0>

FB_B1_EDC<2>

FB_B1_EDC<1>

FB_B1_EDC<3>

FB_B1_A<8>

FB_B0_A<8>

FB_B0_DBI_L<0>

FB_B0_DBI_L<3>

FB_B0_DBI_L<1> FB_B0_DBI_L<2>

FB_B1_CLK_P

FB_B0_CLK_N

FB_B0_CLK_P

FB_B1_DBI_L<1>

FB_B1_DBI_L<0>

FB_B0_CS_L

FB_B1_CAS_L

FB_B0_CAS_L

FB_B1_CLK_N FB_B0_RAS_L

FB_B1_RAS_L

FB_B0_WE_L

FB_B0_CKE_L FB_B1_CKE_L

FB_B0_DQ<30>

FB_B1_DQ<0>

FB_B1_A<1>

FB_B0_A<6>

FB_B0_A<4>

FB_B0_DQ<31>

FB_A0_CLK_P

FB_A1_DBI_L<0> FB_A1_DBI_L<1>

FB_A0_ABI_L

FB_A0_DBI_L<3>

FB_A0_DBI_L<2>

FB_A0_DBI_L<1>

FB_A0_DBI_L<0>

FB_A1_EDC<1>

FB_A1_EDC<0>

FB_A0_EDC<3>

FB_A1_WCLK_N<1>

FB_A0_EDC<2>

FB_A0_EDC<0>

FB_A0_WCLK_N<1> FB_A1_WCLK_P<0>

FB_A0_WCLK_P<1>

FB_A0_WCLK_N<0>

FB_A1_A<7>

FB_A0_WCLK_P<0>

FB_A1_A<5>

FB_A1_A<4>

FB_A1_A<3>

FB_A1_A<2>

FB_A1_A<0>

FB_A0_A<7>

FB_A0_A<6>

FB_A0_A<5>

FB_A0_A<2>

FB_A0_A<1>

FB_A0_A<0>

FB_A1_DQ<2>

FB_A0_DQ<4>

FB_A0_DQ<2>

FB_A0_DQ<0>

FB_A1_DQ<18>

FB_CALRN0

FB_CALRN2

FB_CALRP1

PP1V5R1V35_GPU_FB_ISNS

FB_CALRN1

FB_CALRP0

FB_B1_DQ<16>

FB_B1_DQ<15>

FB_A_VREFD FB_A_VREFS

GPU_CLK_TEST_P

GPU_TEST_EN

FB_B1_DQ<30>

FB_B1_DQ<28>

FB_B1_DQ<12>

FB_A0_A<3> FB_A0_A<4>

FB_A1_A<1>

FB_A1_A<6>

FB_A0_DQ<7>

FB_A0_DQ<6>

82 OF 132 76 OF 105

76

7

75 76 77 78

103

76

7

75 76 77 78

103

7

75 76 77 78

103

7

75 76 77

78

103

7

75 76 77 78

103

76

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7 A9/A1

DBI2*

WE*

BA2/A4 BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MFZQ(MF=0)

(1 OF 2)

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7 A9/A1

DBI2*

WE*

BA2/A4 BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MFZQ(MF=0)

(1 OF 2)

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

NC

BI BI BI BI

IN IN IN IN

IN

IN IN

IN IN IN IN

IN

BI BI BI BI

IN IN

IN

BI BI

BI

IN

IN IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Power aliases required by this page:

(NONE)

Signal aliases required by this page:

- =PP1V5R1V35_S0_FB_VDD

BOM options provided by this page:

(NONE)

Page Notes

402

10%

1UF

CERM-X5R

6.3V

C8484

1

2

402

1%

2.37K

MF-LF

1/16W

R8484

1

2

6.3V CERM-X5R

1UF

10%

402

C8485

1

2

1/16W MF-LF 402

1%

5.49K

R8485

1

2

402

4.7UF

20%

6.3V X5R

C8400

1

2

402

4.7UF

20%

6.3V X5R

C8401

1

2

4.7UF

402

20%

6.3V X5R

C8402

1

2

402

4.7UF

20%

6.3V X5R

C8403

1

2

4.7UF

402

20%

6.3V X5R

C8404

1

2

402

4.7UF

20%

6.3V X5R

C8405

1

2

X5R

6.3V

20%

4.7UF

402

C8450

1

2

X5R

6.3V

20%

4.7UF

402

C8451

1

2

X5R

6.3V

20%

4.7UF

402

C8452

1

2

402

4.7UF

20%

6.3V X5R

C8453

1

2

X5R

6.3V

20%

4.7UF

402

C8454

1

2

X5R

6.3V

20%

4.7UF

402

C8455

1

2

201

120

1%

1/20W

MF

R8403

1

2

MF

1/20W

1%

120

201

R8404

1

2

120

201

1%

1/20W

MF

R8400

1

2

201

120

1%

1/20W

MF

R8453

1

2

MF

1/20W

1%

120

201

R8454

1

2

120

201

1%

1/20W

MF

R8450

1

2

H5GQ1H24AFR-T2C

32MX32-1.25GHZ-MFL

OMIT

BGA

U8450

H4 K5

K4 H5

J4

H11 K10 K11 H10

L3

J12 J11

J3

G12

D2 D13 P13 P2

A4 A2

B11 B13 E11 E13 F11 F13 U11 U13 T11 T13

B4

N11 N13 M11 M13 U4 U2 T4 T2 N4 N2

B2

M4 M2

E4 E2 F4 F2 A11 A13

C2 C13 R13

R2

J1

A5 J5 U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

32MX32-1.25GHZ-MFL

BGA

OMIT

H5GQ1H24AFR-T2C

U8400

H4 K5

K4 H5

J4

H11 K10 K11 H10

L3

J12 J11

J3

G12

D2 D13 P13 P2

A4 A2

B11 B13 E11 E13 F11 F13 U11 U13 T11 T13

B4

N11 N13 M11 M13 U4 U2 T4 T2 N4 N2

B2

M4 M2

E4 E2 F4 F2 A11 A13

C2 C13 R13

R2

J1

A5 J5 U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

BGA

OMIT

32MX32-1.25GHZ-MFL

H5GQ1H24AFR-T2C

U8400

C5

C10

L14 P11

R5

R10

D11

G1

G4 G11 G14

L1

L4 L11

B1

B3

F1

F3 F12 F14

G2 G13

H3 H12

K3 K12

B12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3

B14

P12 P14

T1

T3 T12 T14

D1

D3 D12 D14

E5 E10

J14 A10 U10

B5 B10

L10 P10 T5 T10

D10 G5 G10 H1 H14 K1 K14 L5

A1 A3

E1 E3 E12 E14 F5 F10 H2 H13 K2 K13

A12

M5 M10 N1 N3 N12 N14 R1 R3 R4 R11

A14

R12 R14 U1 U3 U12 U14

C1 C3 C4 C11 C12 C14

76 99

76 77 78 99

76 99

402

MF-LF

1/16W

1%

60.4

R8401

1

2

60.4

402

MF-LF

1/16W

1%

R8402

1

2

402

6.3V CERM-X5R

1UF

10%

C8406

1

2

402

10%

1UF

CERM-X5R

6.3V

C8407

1

2

402

6.3V CERM-X5R

1UF

10%

C8408

1

2

402

10%

1UF

CERM-X5R

6.3V

C8409

1

2

402

6.3V CERM-X5R

1UF

10%

C8410

1

2

402

10%

1UF

CERM-X5R

6.3V

C8411

1

2

402

6.3V CERM-X5R

1UF

10%

C8412

1

2

402

6.3V CERM-X5R

1UF

10%

C8413

1

2

10%

1UF

CERM-X5R

6.3V 402

C8414

1

2

10%

1UF

6.3V 402

CERM-X5R

C8415

1

2

0.1UF

X5R

6.3V

10%

201

C8416

1

2

X5R

6.3V

10%

0.1UF

201

C8417

1

2

X5R

6.3V

10%

0.1UF

201

C8418

1

2

X5R

6.3V

0.1UF

10%

201

C8419

1

2

X5R

6.3V

10%

0.1UF

201

C8420

1

2

X5R

6.3V

10%

0.1UF

201

C8421

1

2

X5R

6.3V

0.1UF

10%

201

C8422

1

2

X5R

6.3V

10%

0.1UF

201

C8423

1

2

X5R

6.3V

0.1UF

10%

201

C8424

1

2

X5R

6.3V

10%

0.1UF

201

C8425

1

2

402

10%

1UF

CERM-X5R

6.3V

C8430

1

2

402

6.3V CERM-X5R

1UF

10%

C8431

1

2

402

2.37K

1% 1/16W MF-LF

R8430

1

2

402

5.49K

1% 1/16W MF-LF

R8431

1

2

402

10%

1UF

CERM-X5R

6.3V

C8432

1

2

402

6.3V CERM-X5R

1UF

10%

C8433

1

2

402

2.37K

1% 1/16W MF-LF

R8432

1

2

402

5.49K

1% 1/16W MF-LF

R8433

1

2

402

10%

1UF

CERM-X5R

6.3V

C8434

1

2

402

6.3V CERM-X5R

1UF

10%

C8435

1

2

402

2.37K

1% 1/16W MF-LF

R8434

1

2

402

5.49K

1% 1/16W MF-LF

R8435

1

2

76 99

402

MF-LF

60.4

1% 1/16W

R8452

1

2

60.4

1% 1/16W MF-LF 402

R8451

1

2

76 99

76 77 78 99

76 99

32MX32-1.25GHZ-MFL

BGA

OMIT

H5GQ1H24AFR-T2C

U8450

C5

C10

L14 P11

R5

R10

D11

G1

G4 G11 G14

L1

L4 L11

B1

B3

F1

F3 F12 F14

G2 G13

H3 H12

K3 K12

B12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3

B14

P12 P14

T1

T3 T12 T14

D1

D3 D12 D14

E5 E10

J14 A10 U10

B5 B10

L10 P10 T5 T10

D10 G5 G10 H1 H14 K1 K14 L5

A1 A3

E1 E3 E12 E14 F5 F10 H2 H13 K2 K13

A12

M5 M10 N1 N3 N12 N14 R1 R3 R4 R11

A14

R12 R14 U1 U3 U12 U14

C1 C3 C4 C11 C12 C14

402

CERM-X5R

6.3V

1UF

10%

C8459

1

2

402

6.3V

10%

1UF

CERM-X5R

C8463

1

2

402

CERM-X5R

6.3V

1UF

10%

C8458

1

2

402

6.3V CERM-X5R

10%

1UF

C8462

1

2

X5R

6.3V

10%

0.1UF

201

C8467

1

2

X5R

6.3V

0.1UF

10%

201

C8466

1

2

402

CERM-X5R

10%

1UF

6.3V

C8457

1

2

6.3V CERM-X5R

1UF

10%

402

C8461

1

2

10%

1UF

6.3V 402

CERM-X5R

C8456

1

2

10%

1UF

6.3V 402

CERM-X5R

C8460

1

2

10%

1UF

CERM-X5R

6.3V 402

C8465

1

2

CERM-X5R 402

6.3V

1UF

10%

C8464

1

2

6.3V

10%

0.1UF

X5R 201

C8471

1

2

X5R

6.3V

0.1UF

10%

201

C8475

1

2

6.3V

10%

0.1UF

X5R 201

C8470

1

2

X5R

6.3V

10%

0.1UF

201

C8474

1

2

6.3V

0.1UF

10% X5R

201

C8469

1

2

X5R

6.3V

0.1UF

10%

201

C8473

1

2

6.3V X5R

0.1UF

10%

201

C8468

1

2

X5R

6.3V

10%

0.1UF

201

C8472

1

2

76 99

402

10%

1UF

6.3V CERM-X5R

C8480

1

2

2.37K

1% 1/16W MF-LF 402

R8480

1

2

6.3V 402

10%

1UF

CERM-X5R

C8481

1

2

MF-LF

1/16W 402

1%

5.49K

R8481

1

2

6.3V

10%

402

1UF

CERM-X5R

C8482

1

2

402

1/16W MF-LF

1%

2.37K

R8482

1

2

6.3V

1UF

10%

402

CERM-X5R

C8483

1

2

5.49K

1% 1/16W MF-LF 402

R8483

1

2

GDDR5 Frame Buffer A

SYNC_MASTER=K91_YUN

SYNC_DATE=08/23/2010

PP1V5R1V35_GPU_FB_ISNS

FB_A0_CLK_P

FB_A0_DQ<11> FB_A0_DQ<14> FB_A0_DQ<13>

FB_A0_EDC<0>

FB_A0_DQ<27>

FB_A0_DQ<30>

FB_A0_DQ<31>

FB_A0_A<2>

FB_A0_A<4>

FB_A0_A<1>

FB_A0_DQ<10>

FB_A0_DQ<29>

FB_A1_VREFD1

FB_A0_VREFD1

FB_A0_VREFD1 FB_A0_VREFD2

PP1V5R1V35_GPU_FB_ISNS

FB_A0_VREFC

PP1V5R1V35_GPU_FB_ISNS

FB_A0_A<5>

FB_A0_A<3>

FB_A0_DQ<0> FB_A0_DQ<1> FB_A0_DQ<2> FB_A0_DQ<3> FB_A0_DQ<4> FB_A0_DQ<5> FB_A0_DQ<6> FB_A0_DQ<7> FB_A0_DQ<8>

FB_A0_DQ<28> FB_A0_DQ<26>

FB_A0_DQ<24> FB_A0_DQ<25> FB_A0_DQ<20> FB_A0_DQ<23> FB_A0_DQ<21> FB_A0_DQ<22> FB_A0_DQ<17> FB_A0_DQ<18> FB_A0_DQ<16> FB_A0_DQ<19>

FB_A0_DBI_L<0> FB_A0_DBI_L<1> FB_A0_DBI_L<3> FB_A0_DBI_L<2>

FB_A0_A<8>

FB_A0_VREFC

FB_A0_WCLK_P<1> FB_A0_WCLK_N<1>

FB_A0_ABI_L

FB_A0_A<7>

FB_A0_CS_L

FB_A0_VREFD2

PP1V5R1V35_GPU_FB_ISNS

FB_A0_CKE_L

FB_A0_A<0>

FB_A1_VREFD2

FB_A1_VREFC

PP1V5R1V35_GPU_FB_ISNS

FB_A1_VREFD1

PP1V5R1V35_GPU_FB_ISNS

FB_A1_VREFC

PP1V5R1V35_GPU_FB_ISNS

FB_A1_VREFD2

PP1V5R1V35_GPU_FB_ISNS

FB_A0_A<6>

FB_A0_CLK_N

FB_A0_WE_L

FB_A0_WCLK_N<0>

FB_A0_WCLK_P<0>

FB_A0_EDC<2>

FB_A0_EDC<3>

FB_A0_RAS_L

FB_A0_SEN FB_RESET_L

FB_A0_DQ<12> FB_A0_DQ<15>

FB_A0_EDC<1>

FB_A0_DQ<9>

FB_A0_CAS_L

FB_A0_MF

FB_A0_ZQ

FB_A1_CAS_L

FB_A1_A<6>

FB_A1_A<5>

FB_A1_DQ<27>

FB_A1_WCLK_N<0>

FB_A1_WCLK_P<1> FB_A1_WCLK_N<1>

FB_RESET_L

FB_A1_EDC<1> FB_A1_EDC<2>

FB_A1_DQ<25>

FB_A1_A<0>

FB_A1_CKE_L

FB_A1_A<2>

FB_A1_DQ<2> FB_A1_DQ<4> FB_A1_DQ<6> FB_A1_DQ<5>

FB_A1_DQ<9> FB_A1_DQ<8> FB_A1_DQ<11> FB_A1_DQ<10>

FB_A1_A<3>

FB_A1_A<4>

FB_A1_WE_L

FB_A1_DBI_L<2>

FB_A1_A<1>

FB_A1_A<7>

FB_A1_CLK_N

FB_A1_DQ<24>

FB_A1_ABI_L

FB_A1_CLK_P

FB_A1_CS_L

FB_A1_DBI_L<1>

FB_A1_DBI_L<3>

FB_A1_DQ<1> FB_A1_DQ<0> FB_A1_DQ<3>

FB_A1_DQ<7>

FB_A1_DQ<12>

FB_A1_DQ<21> FB_A1_DQ<22> FB_A1_DQ<23> FB_A1_DQ<20> FB_A1_DQ<18> FB_A1_DQ<19> FB_A1_DQ<17> FB_A1_DQ<16>

FB_A1_DQ<30> FB_A1_DQ<28>

FB_A1_EDC<0>

FB_A1_EDC<3>

FB_A1_RAS_L

FB_A1_DQ<13>

FB_A1_DQ<15>

FB_A1_DQ<29>

FB_A1_DBI_L<0>

FB_A1_DQ<14>

FB_A1_A<8>

FB_A1_DQ<26>

FB_A1_DQ<31>

FB_A1_WCLK_P<0>

FB_A1_SEN

FB_A1_ZQ FB_A1_MF

84 OF 132 77 OF 105

7

75

76 77

78

103

7

75 76 77 78

103

7

75 76 77 78

103

77

7

75 76

77 78

103

77

7

75 76

77 78

103

77

7

75 76

77 78

103

77

7

75 76 77 78

103

77

7

75 76

77 78

103

77

7

75 76

77 78

103

77

7

75 76 77 78

103

IN

BI

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7 A9/A1

DBI2*

WE*

BA2/A4 BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MFZQ(MF=0)

(1 OF 2)

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

NC

BI BI BI BI

IN IN IN IN

IN

IN IN

IN IN IN IN

IN

BI BI BI BI

IN IN

IN

BI BI

BI

IN

IN IN

VSSQ

VSS

VREFD

VREFC

VDDQ

VDD

(2 OF 2)

BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN

IN IN

IN

NC

WCK01

DQ24

DQ31

NC

DQ14

DBI0*

DQ27

DQ15

DQ13

RAS*

EDC3

EDC0

DQ26

DQ25

DQ23

DQ22

DQ21

DQ20

DQ19

DQ18

DQ17

DQ16

DQ12

DQ7

DQ2

DQ1

DQ0

DBI3*

DBI1*

CS*

CK

ABI*

DQ30

CK*

A8/A7 A9/A1

DBI2*

WE*

BA2/A4 BA3/A3

DQ11

DQ10

DQ9

DQ8

DQ6

DQ5

DQ4

DQ3

BA0/A2

CKE*

A10/A0

DQ28

EDC2

EDC1

RESET*

WCK23*

WCK23

WCK01*

DQ29

BA1/A5

A11/A6

CAS*

SEN

MFZQ(MF=0)

(1 OF 2)

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Power aliases required by this page:

BOM options provided by this page:

(NONE)

- =PP1V5R1V35_S0_FB_VDD

Page Notes

(NONE)

Signal aliases required by this page:

6.3V CERM-X5R

1UF

402

10%

C8584

1

2

MF-LF

1/16W

2.37K

1%

402

R8584

1

2

402

6.3V CERM-X5R

1UF

10%

C8585

1

2

5.49K

1% MF-LF

1/16W 402

R8585

1

2

76 99

10%

1UF

CERM-X5R

6.3V 402

C8533

1

2

10%

1UF

6.3V CERM-X5R 402

C8507

1

2

1UF

10%

6.3V CERM-X5R 402

C8506

1

2

X5R

6.3V

20%

4.7UF

402

C8500

1

2

402

4.7UF

20%

6.3V X5R

C8501

1

2

402

4.7UF

20%

6.3V X5R

C8502

1

2

402

4.7UF

20%

6.3V X5R

C8505

1

2

402

4.7UF

20%

6.3V X5R

C8504

1

2

402

4.7UF

20%

6.3V X5R

C8503

1

2

X5R

6.3V

20%

4.7UF

402

C8550

1

2

X5R

6.3V

20%

4.7UF

402

C8551

1

2

X5R

6.3V

20%

4.7UF

402

C8552

1

2

X5R

6.3V

20%

4.7UF

402

C8553

1

2

X5R

6.3V

20%

4.7UF

402

C8554

1

2

X5R

6.3V

20%

4.7UF

402

C8555

1

2

201

120

1%

1/20W

MF

R8504

1

2

MF

1/20W

1%

120

201

R8503

1

2

MF

1/20W

1%

201

120

R8553

1

2

201

1%

1/20W

MF

120

R8554

1

2

MF

1/20W

1%

201

120

R8550

1

2

H5GQ1H24AFR-T2C

32MX32-1.25GHZ-MFL

BGA

OMIT

U8500

H4 K5

K4 H5

J4

H11 K10 K11 H10

L3

J12 J11

J3

G12

D2 D13 P13 P2

A4 A2

B11 B13 E11 E13 F11 F13 U11 U13 T11 T13

B4

N11 N13 M11 M13 U4 U2 T4 T2 N4 N2

B2

M4 M2

E4 E2 F4 F2 A11 A13

C2 C13 R13

R2

J1

A5 J5 U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

H5GQ1H24AFR-T2C

BGA

OMIT

32MX32-1.25GHZ-MFL

U8500

C5

C10

L14 P11

R5

R10

D11

G1

G4 G11 G14

L1

L4 L11

B1

B3

F1

F3 F12 F14

G2 G13

H3 H12

K3 K12

B12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3

B14

P12 P14

T1

T3 T12 T14

D1

D3 D12 D14

E5 E10

J14 A10 U10

B5 B10

L10 P10 T5 T10

D10 G5 G10 H1 H14 K1 K14 L5

A1 A3

E1 E3 E12 E14 F5 F10 H2 H13 K2 K13

A12

M5 M10 N1 N3 N12 N14 R1 R3 R4 R11

A14

R12 R14 U1 U3 U12 U14

C1 C3 C4 C11 C12 C14

76 99

76 77 78 99

MF

1/20W

1%

120

201

R8500

1

2

76 99

MF-LF

1%

60.4

1/16W 402

R8501

1

2

60.4

1% 1/16W

402

MF-LF

R8502

1

2

1UF

10%

6.3V CERM-X5R 402

C8508

1

2

6.3V CERM-X5R

1UF

10%

402

C8509

1

2

CERM-X5R

6.3V 402

1UF

10%

C8510

1

2

CERM-X5R 402

10%

1UF

6.3V

C8511

1

2

CERM-X5R

6.3V 402

1UF

10%

C8512

1

2

1UF

CERM-X5R

6.3V

10%

402

C8513

1

2

CERM-X5R

10%

1UF

6.3V 402

C8514

1

2

CERM-X5R

10%

1UF

6.3V 402

C8515

1

2

X5R

6.3V

10%

0.1UF

201

C8516

1

2

X5R

6.3V

10%

0.1UF

201

C8517

1

2

X5R

6.3V

10%

0.1UF

201

C8518

1

2

X5R

6.3V

10%

0.1UF

201

C8519

1

2

X5R

6.3V

10%

0.1UF

201

C8520

1

2

X5R

6.3V

10%

0.1UF

201

C8521

1

2

X5R

6.3V

10%

0.1UF

201

C8522

1

2

X5R

6.3V

10%

0.1UF

201

C8523

1

2

X5R

6.3V

10%

0.1UF

201

C8524

1

2

X5R

6.3V

10%

0.1UF

201

C8525

1

2

6.3V CERM-X5R

1UF

10%

402

C8530

1

2

10%

1UF

CERM-X5R

6.3V 402

C8531

1

2

MF-LF

1/16W

2.37K

402

1%

R8530

1

2

MF-LF

1/16W

5.49K

402

1%

R8531

1

2

6.3V CERM-X5R

1UF

10%

402

C8532

1

2

MF-LF

1/16W

2.37K

402

1%

R8532

1

2

MF-LF

1/16W

5.49K

402

1%

R8533

1

2

6.3V CERM-X5R

1UF

10%

402

C8534

1

2

10%

1UF

CERM-X5R

6.3V 402

C8535

1

2

MF-LF

1/16W

2.37K

402

1%

R8534

1

2

MF-LF

1/16W

5.49K

402

1%

R8535

1

2

76 99

60.4

1% 1/16W MF-LF 402

R8552

1

2

60.4

1% 1/16W MF-LF 402

R8551

1

2

76 99

76 77 78 99

76 99

H5GQ1H24AFR-T2C

BGA

OMIT

32MX32-1.25GHZ-MFL

U8550

C5

C10

L14 P11

R5

R10

D11

G1

G4 G11 G14

L1

L4 L11

B1

B3

F1

F3 F12 F14

G2 G13

H3 H12

K3 K12

B12

L2 L13

M1

M3 M12 M14

N5 N10

P1

P3

B14

P12 P14

T1

T3 T12 T14

D1

D3 D12 D14

E5 E10

J14 A10 U10

B5 B10

L10 P10 T5 T10

D10 G5 G10 H1 H14 K1 K14 L5

A1 A3

E1 E3 E12 E14 F5 F10 H2 H13 K2 K13

A12

M5 M10 N1 N3 N12 N14 R1 R3 R4 R11

A14

R12 R14 U1 U3 U12 U14

C1 C3 C4 C11 C12 C14

6.3V

1UF

10% CERM-X5R

402

C8559

1

2

CERM-X5R

1UF

6.3V 402

10%

C8563

1

2

10%

1UF

6.3V CERM-X5R 402

C8558

1

2

1UF

CERM-X5R

6.3V 402

10%

C8562

1

2

X5R

6.3V

10%

0.1UF

201

C8567

1

2

X5R

6.3V

0.1UF

10%

201

C8566

1

2

10%

1UF

6.3V CERM-X5R 402

C8557

1

2

6.3V CERM-X5R

1UF

10%

402

C8561

1

2

10%

1UF

6.3V CERM-X5R 402

C8556

1

2

1UF

CERM-X5R

6.3V 402

10%

C8560

1

2

10%

1UF

CERM-X5R

6.3V 402

C8565

1

2

CERM-X5R

10%

1UF

6.3V 402

C8564

1

2

X5R

6.3V

0.1UF

10%

201

C8571

1

2

X5R

6.3V

10%

0.1UF

201

C8575

1

2

X5R

6.3V

0.1UF

10%

201

C8570

1

2

X5R

6.3V

10%

0.1UF

201

C8574

1

2

X5R

6.3V

0.1UF

10%

201

C8569

1

2

X5R

6.3V

10%

0.1UF

201

C8573

1

2

X5R

6.3V

10%

0.1UF

201

C8568

1

2

X5R

6.3V

0.1UF

10%

201

C8572

1

2

76 99

CERM-X5R 402

10%

1UF

6.3V

C8580

1

2

402

2.37K

1% 1/16W MF-LF

R8580

1

2

CERM-X5R

1UF

10%

6.3V 402

C8581

1

2

5.49K

1% MF-LF

1/16W 402

R8581

1

2

H5GQ1H24AFR-T2C

BGA

OMIT

32MX32-1.25GHZ-MFL

U8550

H4 K5

K4 H5

J4

H11 K10 K11 H10

L3

J12 J11

J3

G12

D2 D13 P13 P2

A4 A2

B11 B13 E11 E13 F11 F13 U11 U13 T11 T13

B4

N11 N13 M11 M13 U4 U2 T4 T2 N4 N2

B2

M4 M2

E4 E2 F4 F2 A11 A13

C2 C13 R13

R2

J1

A5 J5 U5

G3

J2

J10

D4

D5

P4

P5

L12

J13

CERM-X5R

1UF

10%

402

6.3V

C8582

1

2

2.37K

1%

402

1/16W MF-LF

R8582

1

2

CERM-X5R

10%

402

6.3V

1UF

C8583

1

2

MF-LF

1/16W 402

5.49K

1%

R8583

1

2

SYNC_DATE=08/23/2010

GDDR5 Frame Buffer B

SYNC_MASTER=K91_YUN

FB_B0_DQ<7>

FB_B0_DQ<6>

FB_B0_EDC<3>

FB_B0_DQ<28>

FB_B0_EDC<1>

FB_B0_RAS_L

FB_B0_ABI_L

FB_B0_EDC<2>

FB_B0_DQ<5>

FB_B0_DQ<8>

PP1V5R1V35_GPU_FB_ISNS

FB_B0_A<2>

FB_B0_A<3>

FB_B0_DQ<16>

FB_B0_CKE_L

FB_B0_DQ<10>

FB_B0_DQ<12>

FB_B0_DQ<11>

FB_B0_DBI_L<0>

FB_B1_CLK_P

FB_B1_EDC<2>

PP1V5R1V35_GPU_FB_ISNS

FB_B1_VREFD2

FB_B1_DQ<0> FB_B1_DQ<3> FB_B1_DQ<1> FB_B1_DQ<2> FB_B1_DQ<6> FB_B1_DQ<5> FB_B1_DQ<7> FB_B1_DQ<4> FB_B1_DQ<8> FB_B1_DQ<9> FB_B1_DQ<10> FB_B1_DQ<11> FB_B1_DQ<12> FB_B1_DQ<13> FB_B1_DQ<14> FB_B1_DQ<15> FB_B1_DQ<23> FB_B1_DQ<22> FB_B1_DQ<21> FB_B1_DQ<20> FB_B1_DQ<19> FB_B1_DQ<18> FB_B1_DQ<16> FB_B1_DQ<17> FB_B1_DQ<31> FB_B1_DQ<26> FB_B1_DQ<30> FB_B1_DQ<29> FB_B1_DQ<27> FB_B1_DQ<28> FB_B1_DQ<24> FB_B1_DQ<25>

FB_B1_DBI_L<0> FB_B1_DBI_L<1> FB_B1_DBI_L<2> FB_B1_DBI_L<3>

FB_B1_A<8>

FB_B1_A<2> FB_B1_A<5> FB_B1_A<4> FB_B1_A<3>

FB_B1_A<7> FB_B1_A<1> FB_B1_A<0> FB_B1_A<6> FB_B1_CKE_L

FB_B1_CS_L FB_B1_WE_L FB_B1_CAS_L FB_B1_RAS_L

FB_B1_CLK_N

PP1V5R1V35_GPU_FB_ISNS

FB_B1_VREFC

FB_B1_WCLK_P<0> FB_B1_WCLK_N<0>

FB_B1_WCLK_P<1> FB_B1_WCLK_N<1>

FB_RESET_L

FB_B1_EDC<0> FB_B1_EDC<1>

FB_B1_EDC<3>

PP1V5R1V35_GPU_FB_ISNS

FB_B1_VREFD1

FB_B1_VREFD1 FB_B1_VREFD2

FB_B1_VREFC

FB_B0_DQ<0> FB_B0_DQ<1> FB_B0_DQ<2> FB_B0_DQ<3> FB_B0_DQ<4>

FB_B0_DQ<9>

FB_B0_DQ<13>

FB_B0_DQ<25> FB_B0_DQ<26> FB_B0_DQ<27> FB_B0_DQ<24> FB_B0_DQ<23> FB_B0_DQ<22> FB_B0_DQ<19> FB_B0_DQ<21> FB_B0_DQ<20> FB_B0_DQ<18> FB_B0_DQ<17>

FB_B0_DBI_L<1> FB_B0_DBI_L<3> FB_B0_DBI_L<2>

FB_B0_A<8>

FB_B0_A<5>

FB_B0_A<7> FB_B0_A<1>

FB_B0_CS_L

FB_B0_A<0> FB_B0_A<6>

PP1V5R1V35_GPU_FB_ISNS

FB_B0_VREFC

FB_B0_WCLK_P<0> FB_B0_WCLK_N<0>

FB_B0_WCLK_P<1> FB_B0_WCLK_N<1>

PP1V5R1V35_GPU_FB_ISNS

FB_B0_VREFD1

PP1V5R1V35_GPU_FB_ISNS

FB_B0_VREFD2

FB_B0_VREFD1 FB_B0_VREFD2

FB_B0_VREFC

FB_B0_DQ<30>

FB_B0_DQ<31>

FB_B0_DQ<14>

FB_B1_ABI_L

FB_B0_DQ<15>

FB_B0_CAS_L

FB_B1_SEN

FB_B1_MF

FB_B1_ZQFB_B1_ZQ

FB_RESET_L

FB_B0_CLK_P

FB_B0_DQ<29>

FB_B0_A<4>

FB_B0_CLK_N

FB_B0_WE_L

FB_B0_EDC<0>

PP1V5R1V35_GPU_FB_ISNS

FB_B0_SEN

FB_B0_MF

FB_B0_ZQ

85 OF 132 78 OF 105

7

75 76 77 78

103

7

75 76

77 78

103

7

75 76 77 78

103

78

7

75 76 77 78

103

7

75 76

77 78

103

78

7

75 76

77 78

103

78

7

75 76 77 78

103

78

7

75 76

77 78

103

78

7

75 76

77 78

103

78

78 78

7

75

76 77

78

103

B*

R

R*

G

B

G*

Y/NC

B2/NC

C/NC

B2*/NC

G2*/NC

COMP/NC

G2/NC

R2/NC

VDD1DI VSS1DI

AVDD

AVSSQ

RSET

VSYNC

R2*/NC

HSYNC

DDC2DATA

AUX2P

AUX1N

DDC2CLK

AUX1P

DDC1DATA

DDC1CLK

A2VSSQ/TSVSSQ

H2SYNC/GENLK_CLK

V2SYNC/GENLK_VSYNC

VDD2DI/NC

A2VDD/NC

VSS2DI/NC

A2VDDQ/NC

R2SET/NC

DDC6DATA

DDC6CLK

AUX2N

DDCCLK_AUX3P

DDCCLK_AUX4P

DDCDATA_AUX3N

DDCCLK_AUX5P

DDCDATA_AUX4N

DDCDATA_AUX5N

DDCCLK_AUX7P

DDCDATA_AUX7N

TX1P_DPA1P

TX0P_DPA2P TX0M_DPA2N

TXCAP_DPA3P TXCAM_DPA3N

TX1M_DPA1N

TX1M_DPC1N

TX1P_DPC1P

TX0M_DPC2N

TX0P_DPC2P

TXCCP_DPC3P TXCCM_DPC3N

TX5M_DPB0N

TX5P_DPB0P

TX4M_DPB1N

TX4P_DPB1P

TX3M_DPB2N

TX3P_DPB2P

TX2M_DPA0N

TX2P_DPA0P

TXCBM_DPB3N

TXCBP_DPB3P

TXCDM_DPD3N

TXCDP_DPD3P

TX2P_DPC0P TX2M_DPC0N

TX3P_DPD2P

TX4P_DPD1P

TX3M_DPD2N

TX5P_DPD0P

TX4M_DPD1N

TX5M_DPD0N

GPIO_13

GPIO_9_ROMSI

GPIO_8_ROMSO

GPIO_7_BLON

GPIO_11 GPIO_12

GPIO_6

GPIO_2

GPIO_0 GPIO_1

GPIO_14_HPD2

GENERICD

GENERICC

GENERICB

JTAG_TDO

GENERICA

JTAG_TDI

JTAG_TMS

JTAG_TCK

JTAG_TRST*

GPIO_19_CTF

GPIO_18_HPD3

GPIO_16

GENERICE_HPD4

GPIO_23_CLKREQ*

GPIO_17_THERMAL_INT

GPIO_21_BB_EN GPIO_22_ROMCS*

GPIO_15_PWRCNTL_0

GPIO_20_PWRCNTL_1

GPIO_10_ROMSCK

GPIO_5_AC_BATT

GPIO_4_SMBCLK

GPIO_3_SMBDATA

HPD1

VREFG

DPLL_PVDD DPLL_PVSS

XTALIN XTALOUT

XO_IN

XO_IN2

DPLUS DMINUS

DPLL_VDDC

TS_FDO

TSVDD TSVSS

TSA/NC

GENERICF_HPD5 GENERICG_HPD6

DVPDATA_3

DVPDATA_2

DVPCNTL_2

DVPCNTL_1

DVPCNTL_0

DVPDATA_0 DVPDATA_1

DVPCLK

DVPDATA_8

DVPDATA_10

DVPDATA_6 DVPDATA_7

DVPDATA_5

DVPDATA_4

DVPDATA_9

DVPDATA_11 DVPDATA_12 DVPDATA_13 DVPDATA_14

DVPDATA_23

DVPDATA_21 DVPDATA_22

DVPDATA_15

DVPDATA_20

DVPDATA_19

DVPCNTL_MVP_1

DVPCNTL_MVP_0

SWAPLOCKB

SWAPLOCKA

SDA

SCL

DVPDATA_16 DVPDATA_17 DVPDATA_18

(2 OF 9)

MULTI GFX

I2C

GPIO

PLL/CLKTHERMAL

DPADPBDPCDPD

DAC1DAC2

DDC/AUX

(3 OF 9)

LVTMDP

LVDS CNTL

VARY_BL

DIGON

TXCLK_UP_DPF3P TXCLK_UN_DPF3N

TXOUT_U0P_DPF2P TXOUT_U0N_DPF2N

TXOUT_U1P_DPF1P TXOUT_U1N_DPF1N

TXOUT_U2P_DPF0P TXOUT_U2N_DPF0N

TXOUT_U3P TXOUT_U3N

TXCLK_LP_DPE3P TXCLK_LN_DPE3N

TXOUT_L0P_DPE2P TXOUT_L0N_DPE2N

TXOUT_L1P_DPE1P TXOUT_L1N_DPE1N

TXOUT_L2P_DPE0P TXOUT_L2N_DPE0N

TXOUT_L3P TXOUT_L3N

NC NC

NC

NC NC

NC

NC NC

NC

NC NC

OUT OUT

OUT

BI

BI BI

NC NC

BI

NC NC

OUT OUT

OUT

NC NC

IN

OUT

NC NC

OUT OUT

BI BI

OUT OUT

NC NC

BI BI

OUT

NC NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

75mA

(GND_GPU_TSVSS)

(GND_GPU_DPLL)

20mA

125mA

- =PP3V3_GPU_I2C

- =PP1V0_GPU_TS

(NONE)

Straps for audio on DP and HDMI

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V0_GPU_DPLL

- =PP1V8_GPU_DPLL

(NONE)

- =PP1V8_GPU_VREFG

NOTE:

AMD STRAPS FOR IDENTIFYING VRAM VENDOR & SIZE FOR WHISTLER

K92 Hynix 1G - STUFF R8613, NOSTUFF R8612, STUFF R8611

K92 Samsung 1G - NOSTUFF R8613, NOSTUFF R8612, STUFF R8611

Power aliases required by this page:

Page Notes

40NM-ES

OMIT

FCBGA

WHISTLER

U8000

AG33

AD33

AL27

AM27

AM20

AN20

AD34 AE34

AF37 AE38

AF31

AF30

AC32

AF32

AM26 AN26

AM19 AL19

AJ30 AJ31

AL30

AL29

AN21

AK30

AM30

AM29

AM21

AK29

AG29

AM32 AN32

AN31

AF29

AR1

AP8 AW8 AR3

AR8 AU8

AU1 AU3

AV7 AN7 AV9

AT9 AR10 AW10 AU10 AP10 AV11 AT11

AW3

AR12 AW12 AU12 AP12

AP6

AW5

AU5

AR6

AW6

AU6

AT7

AE36 AD35

AD31

AD30

AJ19 AK19 AJ20 AK20 AJ24 AH26 AH24

AD29 AC29

AH20 AH18

AJ16 AK16 AL16 AM16 AM14 AM13 AK14 AG30 AN14 AM17

AN16

AL13 AJ14 AK13 AN13

AH23 AJ23 AH17 AJ17 AK17 AJ13 AH15

AK24

AC36

AK23

AN23

AM24

AL24

AM23

AD39 AD37

AC31

AC30

AA29

AB34

AK26 AJ26

AJ21 AK21

AK32

AL31

AJ32 AJ33

AF33

AR24

AR14

AT25

AT15

AV25

AV15

AU26

AU16

AR26

AR16

AT27

AT17

AU30

AR20

AV31

AT21

AT31

AV21

AR32

AU22

AU32

AR22

AT33

AT23

AV23

AU24

AT29

AR30

AV13

AU14

AT19

AU20

AC33

AG31

AH13

AC34

AG32

AC38

AW34

AW35

AV33 AU34

AD32

WHISTLER

FCBGA

40NM-ES

OMIT

U8000

AJ27

AR34

AP34

AL36

AK35

AU35

AW37

AU39

AR37

AR35

AP35

AP37

AN36

AK37

AJ38

AJ36

AH35

AH37

AG38

AG36

AF35

AK27

SM

XW8602

1 2

85 99

80 84

84 99

84

88 99

80 88

MF-LF

1/16W

5%

4.7K

402

R8600

1

2

4.7K

402

MF-LF

1/16W

5%

R8601

1

2

80 99

51

100

51

100

470OHM-1A-150MOHM

0603

CRITICAL

L8600

1 2

603

10V X5R

10UF

20%

C8601

1

2

402

10%

1UF

25V X5R

C8602

1

2

0.1UF

16V X5R

10%

402-1

C8603

1

2

1/16W MF-LF

499

402

1%

R8602

1

2

402

MF-LF

1/16W

1%

249

R8603

1

2

0.1UF

10% X5R

16V 402-1

C8606

1

2

1UF

10% 25V X5R 402

C8605

1

2

0603

470OHM-1A-150MOHM

CRITICAL

L8601

1 2

603

10V X5R

10UF

20%

C8604

1

2

SM

XW8600

1 2

SM

XW8601

1 2

120OHM-0.3A

0402

L8602

1 2

X5R

20%

10UF

10V 603

C8607

1

2

10%

1UF

X5R

25V 402

C8608

1

2

16V X5R

10%

0.1UF

402-1

C8609

1

2

16V X5R

10%

0.1UF

402-1

C8600

1

2

MF-LF 402

1/16W

5%

10K

R8605

1

2

402

10K

1/16W MF-LF

5%

R8604

1

2

10K

5% 1/16W MF-LF 402

R8606

1

2

10K

402

MF-LF

5%

1/16W

OMIT

R8610

1

2

402

10K

5% 1/16W MF-LF

R8611

1

2

NOSTUFF

MF-LF

10K

1/16W

402

5%

R8612

1

2

VRAM_HYNIX

10K

1/16W MF-LF

402

5%

R8613

1

2

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

84

SYNC_MASTER=K92_SUMA SYNC_DATE=10/21/2010

Whistler LVDS/DP/GPIO

DVPDATA<3>

PP1V8_S0GPU

DVPDATA<0> DVPDATA<1> DVPDATA<2>

DP_T29SNK1_ML_C_N<0>

DP_T29SNK1_ML_C_P<0>

DP_T29SNK1_ML_C_N<1>

DP_T29SNK1_ML_C_P<1>

DP_T29SNK1_ML_C_P<2>

DP_T29SNK1_ML_C_N<3>

DP_T29SNK1_ML_C_P<3>

DP_T29SNK0_ML_C_N<0>

DP_T29SNK0_ML_C_P<0>

DP_T29SNK0_ML_C_P<3>

DP_T29SNK0_ML_C_P<2> DP_T29SNK0_ML_C_N<2>

DP_T29SNK1_ML_C_N<2>

DP_T29SNK0_ML_C_P<1> DP_T29SNK0_ML_C_N<1>

LVDS_EG_B_DATA_N<0>

DP_EG_DDC_CLK

DP_T29SNK0_ML_C_N<3>

DP_EXTA_ML_C_P<1> DP_EXTA_ML_C_N<1>

DP_EXTA_ML_C_P<0> DP_EXTA_ML_C_N<0>

TP_DVPDATA<15>

PEX_CLKREQ_L_R

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

GND_GPU_TVSSQ

MIN_LINE_WIDTH=0.25 mm

TP_GPU_JTAG_TCK

DP_T29SNK0_HPD_GPU

TP_DVPDATA<4>

TP_DVPDATA<9>

TP_DVPDATA<13> TP_DVPDATA<14>

TP_DVPDATA<18>

TP_DVPDATA<17>

PP1V0_S0GPU

TP_DVPDATA<16>

TP_DVPCNTL_M<1>

TP_DVPDATA<19>

TP_DVPDATA<12>

TP_DVPDATA<5>

TP_DVPDATA<10>

TP_DVPCNTL<0> TP_DVPCNTL<1>

GPU_CLK100M

GPU_CLK27M

GPU_TDIODE_N

PP1V8_S0GPU

DP_EG_HPD

TP_DVPDATA<23>

TP_DVPDATA<22>

TP_DVPDATA<20> TP_DVPDATA<21>

TP_DVPCNTL<2>

TP_DVPDATA<11>

PP1V8_S0GPU

TP_GPU_JTAG_TDI

GPU_VCORE_VID3 FBVDD_ALTVO

TP_GPU_JTAG_TRST_L

TP_GPU_JTAG_TMS TP_GPU_JTAG_TDO

NC_GPU_GENERICA NC_GPU_GENERICB NC_GPU_GENERICC DP_CA_DET_EG_R NC_GPU_GENERICE NC_GPU_GENERICF NC_GPU_GENERICG

DP_EXTA_ML_C_P<2> DP_EXTA_ML_C_N<2>

DP_EXTA_ML_C_N<3>

LVDS_EG_BLK_PWM EG_LCD_PWR_EN

NC_LVDS_EG_B_CLK_P NC_LVDS_EG_B_CLK_N

LVDS_EG_B_DATA_P<0>

LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2>

NC_LVDS_EG_B_DATA_P<3> NC_LVDS_EG_B_DATA_N<3>

LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_N<0> LVDS_EG_A_DATA_P<1>

NC_LVDS_EG_A_DATA_P<3> NC_LVDS_EG_A_DATA_N<3>

PP3V3_S0GPU

VOLTAGE=1.8V

PP1V8_S0GPU

PP1V8_GPU_DPLL

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

PP1V0_GPU_DPLL

VOLTAGE=1V

VOLTAGE=0V

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

GND_GPU_TSVSS

TP_DVPDATA<6> TP_DVPDATA<7> TP_DVPDATA<8>

GPU_ROM_CS_L

GPU_ROM_SI

GPU_ROM_SO

GPU_VCORE_VID0

GPU_AC_BATT

GPU_VCORE_VID2

DP_T29SNK1_HPD_GPU

SMC_GFX_THROTTLE_R_L

GPU_CONFIG_1

GPU_CONFIG_0

SMC_GFX_OVERTEMP_R_L

MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_TSVDD

GPU_TDIODE_P

LVDS_EG_A_DATA_N<2>

LVDS_EG_A_DATA_P<2>

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_P<0>

GPU_VCORE_VID1

GPU_CONFIG_2

GPU_I2C_SCL

GPU_PCIE_TX_PWR GPU_GPIO_TX_DEEMP GPU_PCIE_GEN2

EG_BKLT_EN

GPU_SMB_DAT GPU_SMB_CLK

GPU_I2C_SDA

GND_GPU_DPLL

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

PP1V8_S0GPU

GPU_VREFG

DP_EXTA_ML_C_P<3>

GPU_AUD_0

GPU_AUD_1

TP_DVPCLK

TP_DVPCNTL_M<0>

GPU_ROM_SCLK

DP_EG_AUX_CH_P DP_EG_AUX_CH_N

DP_T29SNK1_AUXCH_C_N

DP_T29SNK0_AUXCH_C_P DP_T29SNK0_AUXCH_C_N

DP_T29SNK1_AUXCH_C_P

DP_EG_DDC_DATA

LVDS_EG_DDC_DATA

LVDS_EG_DDC_CLK

PP3V3_S0GPU

86 OF 132 79 OF 105

6 7

75 79 81

103

6

80

6

7

74

75 81

103

6

6 7

75 79 81

103

80 84

6

6 7

75 79 81

103

80

80 82

80 87

6

80

80 99

6 7

72 75 79 80 82 84

6 7

75 79 81

103

6

80

80 82

80

80 82

80

80 82

80

80 88

80

6 7

75 79 81

103

6

80

6 7

72 75 79 80 82 84

IN

BI

OUT

IN

OUT

THM

VDD2

VDD1

XOUT

SSCLK

REFCLK

SSEL0 SSEL1

VSS2

VSS1

XIN/CLKIN

PAD

OUT

HOLD*

S*

D

C

Q

THRM

W*

VCC

PAD

VSS

IN

Y

A

B

08

Y

A

B

08

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

? BOM OPTION NEED CONFIRMATION HERE!

GPU Reference Clocks

GP

Native Func

GPIOs

GP

GPIOs

GP

Config Straps

Native Func

ISOLATION R’s for GPU Int Temp Sense

GP

T29 HPD GPU isolation

Unused signals

402

MF-LF

1%

1/16W

10K

NOSTUFF

R8705

1

2

4.7K

402

1/16W MF-LF

5%

R8752

1

2

4.7K

402

5% 1/16W MF-LF

R8753

1

2

79 84

8

17 84

79 84

8

17 84

1/16W0MF-LF

4025%

R8798

1 2

402

0

5%

1/16W MF-LF

R8799

1 2

45

2.2K

5%

402

1/16W MF-LF

R8797

1

2

NO STUFF

1/16W

5%

402

MF-LF

2.2K

R8796

1

2

79 88

79 80 88

79 80 87

10K

1/16W

5%

MF-LF

402

1

2

R8792

5%

402

MF-LF

10K

1/16W

R8793

1

2

1/16W MF-LF

5%

10K

402

R8794

1

2

NO STUFF

2.2K

402

MF-LF

5%

1/16W

R8750

1

2

402

2.2K

MF-LF

1/16W

5%

NO STUFF

R8751

1

2

Y8700

CRITICAL

SM-2.5X2.0MM

27MHZ-15PPM-18PF

2 4

1 3

5%

30PF

CERM

50V 402

C8700

1

2

5%

30PF

CERM

50V 402

C8701

1

2

402-1

10%

0.1UF

16V X5R

C8702

1

2

0.1UF

402-1

16V X5R

10%

C8703

1

2

L8702

120OHM-0.3A

0402

1 2

120OHM-0.3A

L8703

0402

1 2

CRITICAL

SL16010DC

TDFN

U8700

9

5

7 3

11

4

8

6

2

1

10

79 99

402

1/16W

0

MF-LF

5%

R8731

1 2

1/16W

402

MF-LF

0

5%

1 2

R8730

8

88

402

MF-LF1/16W

5%

0

R8795

1 2

10K

1/16W MF-LF

402

1%

NOSTUFF

R8704

1

2

1/16W MF-LF

1%

NOSTUFF

10K

402

R8703

1

2

MF-LF

1/16W

1%

10K

R8700

402

NOSTUFF

1

2

10K

1%

1/16W

402

MF-LF

R8702

1

2

10K

1/16W

402

1%

NOSTUFF

MF-LF

R8701

1

2

NOSTUFF

402

MF-LF

1/16W

10K

1%

R8708

1

2

NOSTUFF

1/16W MF-LF

R8707

402

1%

10K

1

2

R8706

1/16W MF-LF

1

10K

402

1%

NOSTUFF

2

NOSTUFF

MF-LF

2

1/16W

402

1%

10K

R8711

1

R8710

10K

402

1/16W MF-LF

1%

1

2

NOSTUFF

1/16W MF-LF

402

1%

10K

R8709

1

2

NOSTUFF

R8714

10K

1%

402

MF-LF

1/16W

1

2

1

NOSTUFF

1%

402

MF-LF

1/16W

10K

R8713

2

1

GPU_ROM:YES

R8712

10K

1%

MF-LF

402

1/16W

2

CRITICAL

M25P10A

U8701

UFDFPN8

OMIT_TABLE

6

5

7

2

1

984

3

MF-LF

GPU_ROM:YES

R8726

1 2

402

1/16W

5%

33

GPU_ROM:YES

33

MF-LF

5%

1/16W

402

R8723

1 2

GPU_ROM:YES

5%

MF-LF

1/16W

33

402

R8724

1 2

GPU_ROM:YES

MF-LF

1/16W

33

402

5%

R8725

1 2

10V

GPU_ROM:YES

0.1UF

CERM 402

20%

C8721

1

2

R8721

GPU_ROM:YES

0

5%

MF-LF

402

1/16W

1

2

402

0

1/16W

5%

NO STUFF

MF-LF

R8722

1

2

1

R8720

402

5%

10K

1/16W MF-LF

GPU_ROM:YES

88

0

5%

1/16W MF-LF

402

R8791

1 2

NOSTUFF

R8781

402

0

5%

MF-LF

1/16W

21

402

0

5%

MF-LF

R8780

1 2

1/16W

NOSTUFF

C8741

0.1UF

20%

2

402

1

10V CERM

CRITICAL

7

2

8

4

SOT833

1

74LVC2G08GT

U8741

SOT833

4

8

5

3

74LVC2G08GT

U8741

6

R8741

MF-LF

1/16W

5%

0

1

2

402

Whistler GPIOs & STRAPs

SYNC_DATE=07/17/2010

SYNC_MASTER=K91_MLB

GPU_SMB_CLK GPU_AC_BATT

PP3V3_S0GPU

GPU_GPIO_TX_DEEMP GPU_PCIE_GEN2 GPU_SMB_DAT GPU_SMB_CLK

MAKE_BASE=TRUE

GPU_AC_BATT

EG_BKLT_EN

MAKE_BASE=TRUE

NC_GPU_GENERICA

PP3V3_S0GPU

GPU_VCORE_VID2

GPU_VCORE_VID3

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

DP_T29SNK1_HPD_GPU

MAKE_BASE=TRUE

DP_T29SNK1_HPD

FBVDD_ALTVO

GPU_VCORE_VID2

MAKE_BASE=TRUE

PP3V3_S0

MAKE_BASE=TRUE

GPU_VCORE_VID3

MAKE_BASE=TRUE

FBVDD_ALTVO GPU_ROM_CS_L

MAKE_BASE=TRUE

PEX_CLKREQ_L_R

DP_T29SNK0_HPD

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUEMAKE_BASE=TRUE

GPU_SMB_DAT

GPU_VCORE_VID0

MAKE_BASE=TRUE

DP_T29SNK0_HPD_GPU

MAKE_BASE=TRUE

GPU_PCIE_GEN2

EG_BKLT_EN

GPU_CONFIG_2

MAKE_BASE=TRUE

GPU_ROM_SCLK

GPU_CONFIG_1

DP_T29SNK0_HPD_GPU GPU_VCORE_VID1 GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_ROM_SI

GPU_VCORE_VID0

GPU_AC_BATT

GPU_ROM_SI

MAKE_BASE=TRUE

PEX_CLKREQ_L_R

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GENERICA

MAKE_BASE=TRUE

DP_CA_DET_EG_R

DP_EG_HPD

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_N<3>

MAKE_BASE=TRUE

GPU_SMB_CLK

SMBUS_SMC_0_S0_SCL

GPU_SMB_CLK

GPU_SMB_DAT

GPU_CONFIG_2

FBVDD_ALTVO

PP3V3_S0GPU

DP_IG_DDC_CLK

DP_EG_DDC_DATA

DP_EG_DDC_CLK

GPU_ROM_SCLK

PEX_CLKREQ_L_R

GPU_CONFIG_0

GPU_PCIE_TX_PWR

DP_CA_DET_EG

DP_CA_DET_EG_R

PEX_CLKREQ_L

PEX_CLKREQ_L_R

SMC_GFX_OVERTEMP_R_L

NC_LVDS_EG_B_DATA_N<3>

NC_LVDS_EG_A_DATA_N<3>

NC_LVDS_EG_B_DATA_P<3>

NC_LVDS_EG_A_DATA_P<3>

TP_GPU_JTAG_TRST_L

TP_GPU_JTAG_TMS

TP_GPU_JTAG_TCK

PP3V3_S0GPU

EG_LCD_PWR_EN

GPU_CLK100M

GPU_CLK27M_R

GPU_CLK100M_R

GPU_CLK27M

FBVDD_ALTVO

SMC_GFX_THROTTLE_R_L

SMC_GFX_THROTTLE_L

EG_BKLT_EN

SMC_GFX_OVERTEMP_L

TP_GPU_JTAG_TDO

NC_LVDS_EG_B_CLK_P

GPU_CONFIG_1

GPU_CONFIG_2

GPU_ROM_SI

GPU_ROM_SCLK

GPU_ROM_SCLK_R

GPU_ROM_SO_R

NO_TEST=TRUE

NC_LVDS_EG_B_DATA_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_EG_A_DATA_P<3>

MAKE_BASE=TRUE

NC_LVDS_EG_B_CLK_P

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_GPU_JTAG_TMS

MAKE_BASE=TRUE

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

TP_GPU_JTAG_TCK

PP3V3_GPU_OSC_100M

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

NO_TEST=TRUE

NC_LVDS_EG_B_DATA_N<3>

MAKE_BASE=TRUE

GPU_ROM_WP_L

GPU_GPIO_TX_DEEMP

PP3V3_S0

GPU_ROM_SI_R

GPU_ROM_CS_L

NC_LVDS_EG_B_CLK_N

NO_TEST=TRUE

MAKE_BASE=TRUE

PP3V3_GPU_OSC_27M

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

GPU_OSC_27M_XTALOUT

GPU_ROM_CS_L_R

GPU_SMB_DAT

GPU_ROM_SO

GPU_CONFIG_0

MAKE_BASE=TRUE

GPU_PCIE_GEN2

NC_GPU_GENERICG

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GENERICENC_GPU_GENERICE

DP_CA_DET_EG_R

MAKE_BASE=TRUE

NC_GPU_GENERICB

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GENERICC

PP3V3_S0GPU

DP_EG_HPD

MAKE_BASE=TRUE

NC_GPU_GENERICB

NC_GPU_GENERICF

NO_TEST=TRUE

MAKE_BASE=TRUE

PP3V3_S0

NC_GPU_GENERICC

PP3V3_GPU_VDD33_R

GPU_ROM_CS_L

GPU_ROM_SO

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

GPU_PCIE_TX_PWR

MAKE_BASE=TRUE

GPU_ROM_SCLK

PP3V3_S0GPU

GPU_ROM_SO

DP_T29SNK0_HPD_GPU

GPU_OSC_27M_XTALIN

NC_LVDS_EG_B_CLK_N

DP_T29SNK1_HPD_GPU

TP_GPU_JTAG_TDI

MAKE_BASE=TRUE

TP_GPU_JTAG_TDI

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

TP_GPU_JTAG_TRST_L

DP_T29SNK1_HPD_GPU SMC_GFX_OVERTEMP_R_L

NC_GPU_GENERICF NC_GPU_GENERICG

MAKE_BASE=TRUE

GPU_CONFIG_1

MAKE_BASE=TRUE

GPU_CONFIG_0

MAKE_BASE=TRUE

GPU_GPIO_TX_DEEMP

GPU_PCIE_TX_PWR

DP_IG_DDC_DATA

GPU_ROM_SI

GPU_ROM_SO

EG_BKLT_EN

87 OF 132 80 OF 105

79 80

6 7

72 75 79 80 82 84

79 80

79 80 88

79 80

6 7

72 75 79 80 82 84

79 80 82

79 80

33 84

79 80 87

79 80 82

6 7

12 23 25 26 28 32

35 36 39 40 41 46 48 49

50 51 52 54 57 61 62 72

73 80 83 84 85 88 89 91

100 102

79 80 82

79 80 87

79 80

33 84

79 80

79 80 82

79 80

79 80 88

79 80

79 80 82 79 80 82

79 80

79 80 82

79 80

79 80 84

79 80 99

79 80

6

31 45 48

51 98

79 80

79 80 87

6 7

72 75 79 80 82 84

79 80

99

79 80

99

79 80

99

79 80

99

6

79

80

79 80

6 7

72 75 79 80 82 84

79 80

79 80 99

79 80

79 80 99

79 80

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

79 80

79 80 79 80

79 80

6 7

72 75 79 80 82 84

79 80 84

79 80

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

79 80

6 7

72 75 79 80 82 84

79 80

6

31 45 48

51 98

6

79 80

79 80 88

DPEF_CALR

DP/DPF_VSSR_AM34

DP/DPF_VSSR_AL34

DP/DPF_VSSR_AK39

DPEF/DPF_VDD18_AF34

DP/DPE_VSSR_AU37

DP/DPE_VSSR_AR39

DPEF/DPF_VDD18_AG34

DPEF/DPF_VDD10_AK33 DPEF/DPF_VDD10_AK34

DP/DPF_VSSR_AF39 DP/DPF_VSSR_AH39

DPCD_CALR

DPEF/DPE_VDD10_AM33

DP/DPE_VSSR_AN34 DP/DPE_VSSR_AP39

DP/DPD_VSSR_AW22

DPCD/DPD_VDD10_AP14

DPCD/DPD_VDD18_AP23

DP/DPD_VSSR_AN19

DP/DPD_VSSR_AP19

DPCD/DPC_VDD18_AP21

DPCD/DPC_VDD10_AP13

DPCD/DPC_VDD18_AP20

DPEF/DPE_VDD10_AL33

DPEF/DPE_VDD18_AJ34

DPEF/DPE_VDD18_AH34

DP/DPD_VSSR_AW20

DP/DPD_VSSR_AP18

DP/DPC_VSSR_AW16

DP/DPC_VSSR_AN17 DP/DPC_VSSR_AP16 DP/DPC_VSSR_AP17

DPCD/DPC_VDD10_AT13

DPCD/DPD_VDD10_AP15

DPAB/DPA_VDD18_AN24 DPAB/DPA_VDD18_AP24

DPAB/DPA_VDD10_AP31 DPAB/DPA_VDD10_AP32

DP/DPA_VSSR_AN27 DP/DPA_VSSR_AP27

DP/DPA_VSSR_AW26

DP/DPA_VSSR_AW24

DP/DPA_VSSR_AP28

DPAB/DPB_VDD18_AP25 DPAB/DPB_VDD18_AP26

DPAB/DPB_VDD10_AN33 DPAB/DPB_VDD10_AP33

DP/DPB_VSSR_AP29

DP/DPB_VSSR_AN29

DP/DPB_VSSR_AP30 DP/DPB_VSSR_AW30

DPAB_CALR

DP/DPB_VSSR_AW32

DPAB_VDD18/DPA_PVDD_AU28

DP_VSSR/DPA_PVSS_AV27

DPAB_VDD18/DPB_PVDD_AV29

DP_VSSR/DPB_PVSS_AR28

DPCD_VDD18/DPC_PVDD_AU18

DP_VSSR/DPC_PVSS_AV17

DPEF_VDD18/DPE_PVDD_AM37

DP_VSSR/DPE_PVSS_AN38

DPEF_VDD18/DPF_PVDD_AL38

DPCD/DPD_VDD18_AP22

DP_VSSR/DPF_PVSS_AM35

DPCD_VDD18/DPD_PVDD_AV19

DP_VSSR/DPD_PVSS_AR18

DP/DPC_VSSR_AW14

DP C/D PWR

DP A/B PWR

(6 OF 9)

DP OLL POWER

DP E/F PWR

GND_AF18

GND_AF16

GND_AF10

GND_AD27

GND_AD24

GND_AD22

GND_AD20

GND_AC28

GND_AD15 GND_AD17

GND_AC26

GND_AC23

GND_AC21

GND_AC18

GND_AC16

GND_AB24

GND_AA18

GND_AA16

GND_AA2

GND_A37

GND_A3

GND_AA6

GND_AC2

GND_AD9

GND_AE2 GND_AE6

PCIE_VSS_E39 PCIE_VSS_F34 PCIE_VSS_F39

PCIE_VSS_G34 PCIE_VSS_H31 PCIE_VSS_H34 PCIE_VSS_H39 PCIE_VSS_J31

PCIE_VSS_N34

PCIE_VSS_N31

PCIE_VSS_M39

PCIE_VSS_J34 PCIE_VSS_K31 PCIE_VSS_K34 PCIE_VSS_K39 PCIE_VSS_L31 PCIE_VSS_L34 PCIE_VSS_M34

PCIE_VSS_V34

PCIE_VSS_U34

PCIE_VSS_U31

PCIE_VSS_T39

PCIE_VSS_T34

PCIE_VSS_T31

PCIE_VSS_P31

PCIE_VSS_V39

VSS_MECH_AW39

VSS_MECH_AW1

VSS_MECH_A39

PCIE_VSS_Y39

PCIE_VSS_Y34

PCIE_VSS_W34

PCIE_VSS_W31

PCIE_VSS_R34

PCIE_VSS_P34 PCIE_VSS_P39

GND_AC13

GND_AC11

GND_AC6

GND_AB27

GND_AB22

GND_AB20

GND_AB17

GND_AB15

GND_AA26 GND_AA28 GND_AB12

PCIE_VSS_AB39

PCIE_VSS_G33

GND_AA21 GND_AA23

(8 OF 9)

GND_U17 GND_U20 GND_U22

GND_U15

GND_U24

GND_V21

GND_V18

GND_V16

GND_V11

GND_U27

NC/GND

GND/PX_EN

GND_Y27

GND_Y24

GND_Y22

GND_Y17 GND_Y20

GND_H9

GND_G6

GND_G2

GND_F33

GND_F31

GND_J2 GND_J6

GND_M17

GND_K7

GND_L6

GND_L17

GND_L11

GND_L24

GND_L22

GND_M22 GND_M24

GND_N6

GND_N21

GND_N2

GND_N18

GND_N16

GND_N23 GND_N26

GND_R2 GND_R6

GND_T18

GND_T13 GND_T16

GND_R15 GND_R17

GND_R27

GND_R24

GND_R22

GND_R20

GND_T11

GND_U6

GND_T26

GND_U2

NC/GND

GND_T23

GND_T21

GND_AG2 GND_AG6 GND_AG9

GND_AJ2 GND_AJ6

GND_AF21

GND_AG17 GND_AG20 GND_AG22 GND_AH21

GND_AK7

GND_AL8

GND_AL6

GND_AL2

GND_AL11

GND_AJ10 GND_AJ11 GND_AJ28

GND_AK11 GND_AK31

GND_AM9

GND_AL32

GND_AL26

GND_AL23

GND_AL20

GND_AL17

GND_AL14

GND_AM11 GND_AM31

GND_AN11 GND_AN30

GND_AP11 GND_AR5

GND_AP9

GND_AN8

GND_AP7

GND_AN6

GND_AN2

GND_B7

GND_B23 GND_B25 GND_B27

GND_B13 GND_B15 GND_B17 GND_B19 GND_B21

GND_B11

GND_B9

GND_F11

GND_F7 GND_F9

GND_B33 GND_C1 GND_C39

GND_E35

GND_E5

GND_B29 GND_B31

GND_F29

GND_F27

GND_F17 GND_F19 GND_F21 GND_F23 GND_F25

GND_F13 GND_F15

GND_V23

GND_W6

GND_Y15

GND_W2

GND_V26

GND_L2

GND_K14

GND_J8

GND_J27

(9 OF 9)

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

220mA

300mA

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

- =PP1V0_GPU_DP_CD

- =PP1V0_GPU_DP_AB

- =PP1V8_GPU_DP_EF

- =PP1V8_GPU_DP_CD

- =PP1V0_GPU_DP_EF

BOM options provided by this page:

(NONE)

- =PP1V8_GPU_DP_AB

(NONE)

300mA

220mA

300mA

40NM-ES

OMIT

FCBGA

WHISTLER

U8000

AF39 AH39 AK39 AL34 AM34

AM35

AN17

AN19

AN27

AN29

AN34

AN38

AP16 AP17

AP18 AP19

AP27 AP28

AP29 AP30

AP39

AR18

AR28

AR39 AU37

AV17

AV27

AW14 AW16

AW20 AW22

AW24 AW26

AW30 AW32

AW28

AN33

AP31 AP32

AP33

AN24 AP24

AP25 AP26

AU28

AV29

AW18

AP13

AP14 AP15

AT13

AP20 AP21

AP22 AP23

AU18

AV19

AM39

AK33 AK34

AL33 AM33

AF34 AG34

AH34 AJ34

AL38

AM37

603

10V X5R

10UF

20%

C8800

1

2

0603

470OHM-1A-150MOHM

L8800

1 2

402

10%

1UF

25V X5R

C8801

1

2

16V X5R

10%

402-1

0.1UF

C8802

1

2

402-1

X5R

10% 16V

0.1UF

C8805

1

2

X5R

25V

1UF

10%

402

C8804

1

2

10UF

20% X5R

10V 603

C8803

1

2

0603

470OHM-1A-150MOHM

L8801

1 2

40NM-ES

WHISTLER

OMIT

FCBGA

U8000

A3 A37

AA16 AA18

AA2

AA21 AA23 AA26 AA28

AA6

AB12 AB15 AB17 AB20 AB22 AB24 AB27

AC11 AC13 AC16 AC18

AC2

AC21 AC23 AC26 AC28

AC6

AD15 AD17 AD20 AD22 AD24 AD27

AD9

AE2 AE6 AF10 AF16 AF18

AB39

E39 F34 F39 G33 G34 H31 H34 H39 J31 J34 K31 K34 K39 L31 L34 M34 M39 N31 N34 P31 P34 P39 R34 T31 T34 T39 U31 U34 V34 V39 W31 W34 Y34 Y39

A39 AW1

AW39

402-1

10% X5R

16V

0.1UF

C8808

1

2

X5R

25V

1UF

10%

402

C8807

1

2

20%

10UF

X5R

10V 603

C8806

1

2

0603

470OHM-1A-150MOHM

L8802

1 2

402-1

0.1UF

10% X5R

16V

C8811

1

2

X5R

25V

1UF

10%

402

C8810

1

2

20%

10UF

X5R

10V 603

C8809

1

2

0603

470OHM-1A-150MOHM

L8803

1 2

WHISTLER

40NM-ES

OMIT

FCBGA

U8000

AF21

AG17

AG2

AG20 AG22

AG6 AG9

AH21

AJ10 AJ11

AJ2

AJ28

AJ6

AK11 AK31

AK7

AL11 AL14 AL17

AL2

AL20 AL23 AL26 AL32

AL6 AL8

AM11 AM31

AM9

AN11

AN2

AN30

AN6 AN8

AP11

AP7 AP9

AR5

B11 B13 B15 B17 B19 B21 B23 B25 B27 B29 B31 B33

B7 B9

C1

C39

E35

E5

F11 F13 F15 F17 F19 F21 F23 F25 F27 F29

F31 F33

F7 F9

G2 G6 H9 J2

J27

J6 J8

K14

K7

L11 L17

L2

L22 L24

L6

M17 M22 M24

N16 N18

N2

N21 N23 N26

N6

R15 R17

R2

R20 R22 R24 R27

R6

T11 T13 T16 T18 T21 T23 T26

U15 U17

U2

U20 U22 U24 U27

U6

V11

V16 V18 V21 V23 V26 W2 W6 Y15 Y17 Y20 Y22 Y24 Y27

U13

V13

AL21

MF-LF

150

1/16W

1%

402

R8801

1 2

1%

150

1/16W MF-LF

402

R8800

1 2

MF-LF

150

1/16W

1%

402

R8802

1 2

0.1UF

10% 16V X5R 402-1

C8817

1

2

402

10%

1UF

25V X5R

C8816

1

2

603

10V X5R

20%

10UF

C8815

1

2

470OHM-1A-150MOHM

0603

L8805

1 2

0.1UF

402-1

10% X5R

16V

C8814

1

2

X5R

25V

1UF

10%

402

C8813

1

2

20%

10UF

X5R

10V 603

C8812

1

2

470OHM-1A-150MOHM

0603

L8804

1 2

Whistler DP PWR/GNDs

SYNC_MASTER=K92_BEN

SYNC_DATE=06/01/2010

PP1V8_S0GPU

PP1V0_S0GPU

PP1V8_S0GPU

GPU_DP_EF_CALR

GPU_DP_CD_CALR

PP1V8_GPU_DP_CD

PP1V8_GPU_DP_EF

PP1V8_GPU_DP_CD

PP1V8_GPU_DP_AB

GPU_DP_AB_CALR

PP1V0_GPU_DP_EF

PP1V8_GPU_DP_EF

PP1V0_GPU_DP_EF

PP1V8_GPU_DP_EF

PP1V0_GPU_DP_CD

PP1V8_GPU_DP_CD

PP1V0_GPU_DP_CD

PP1V8_GPU_DP_CD

PP1V0_GPU_DP_AB

PP1V8_GPU_DP_AB

PP1V0_GPU_DP_AB

PP1V8_GPU_DP_AB

PP1V8_S0GPU PP1V0_S0GPU

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V8_GPU_DP_CD

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1V

MIN_NECK_WIDTH=0.2 mm

PP1V0_GPU_DP_CD

PP1V0_GPU_DP_AB

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V

MIN_LINE_WIDTH=0.4 mm

PP1V8_GPU_DP_AB

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_GPU_DP_EF

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V0_GPU_DP_EF

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1V

MIN_LINE_WIDTH=0.4 mm

88 OF 132 81 OF 105

6 7

75 79 81

103

7

74 75 79 81

103

7

74 75 79 81

103

6 7

75 79 81

103

81

6 7

75 79 81

103

7

74 75 79 81

103

81

81 81

PVCC

THRM_PAD

FDE

PGOOD

AF_EN

VR_ON

IMON

VID4

VID3

VID2

VID1

VID0

LGATE

PGND

PHASE

UGATE

BOOT

VSS

VIN

ISP

VO

ISN

ICOMP

RTN

VSEN

VDIFF

FB

COMP

VW

OCSET

SOFT

VDD

RBIAS

OUT

IN

OUT

G

D

S

IN

G

D

S

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

GPU VCore Setpoints not up-to-date!

353S2289

(GFXIMVP6_AGND)

(L8920 limit)

VID2

Voltage

-1

(PPVCORE_GPU_REG)

0

10 1

1

VID4 VID3 VID0VID1

1

-

Max Batt

-

Balanced Max perf

-

30A max output

K18

1 0

0.74675V

0.90125V

0.82400V

Vout = 0.75V - 0.90V

1 1

1 0 0 0

GPU VCore Setpoints

K92 Default Vcore Setpoints

GPU VCore Regulator

150

1/16W MF-LF

1%

402

R8951

1

2

150K

MF-LF

1%

402

1/16W

R8950

1

2

1/16W

5%

MF-LF

402

PLACE_NEAR=U8900.9:7mm

20

R8908

1 2

20

MF-LF

402

5%

1/16W

PLACE_NEAR=U8900.8:7mm

R8920

1 2

1/16W

5%

402

MF-LF

10K

R8907

1

2

5%

402

10K

1/16W MF-LF

R8910

1

2

0.0068UF

25V

CERM

10%

402

C8951

1 2

3.01K

402

1/16W

1% MF-LF

R8953

1

2

402

50V CERM

10%

330PF

C8952

1

2

CERM

402

10%

330PF

50V

C8950

12

0.001UF

10% 402

CERM

50V

C8920

1

2

ISL6263C

QFN

CRITICAL

U8900

30

17

5

6

32

10

28

11

13

21

3

20

31

19

22

1

9

2

33

18

16

7

23 24

25

26 27

14

12

29

8

15

4

SM

PLACE_NEAR=U8900.33:2mm PLACE_NEAR=U8900.15:2mm

XW8900

1 2

680pF

CERM

10% 50V

402

C8953

1

2

7.15K

402

1/16W MF-LF

1%

R8909

1

2

0.001UF

X7R 402

10% 50V

C8922

1

2

CERM

0.001UF

10% 50V

402

C8923

1

2

8

74 87 88 91

CERM

402

10% 50V

0.001UF

C8921

1

2

402

MF-LF

1%

1/16W

10

R8904

1 2

150K

MF-LF

402

1%

1/16W

R8905

2 1

X5R 402

10% 16V

0.033UF

C8904

12

402

10% X5R

10V

1uF

C8901

1

2

MF-LF

1/16W

402

5%

1

R8911

1 2

10V

2.2UF

20%

402

X5R-CERM

C8902

1

2

10% 16V

0.01uF

402

CERM

C8903

1

2

50V

CERM

0.001UF

402

10%

C8972

1

2

CERM

402-1

50V

68PF

5%

C8971

1 2

1/16W

1%

402

9.76K

MF-LF

R8902

2

1

MF-LF

1%

402

9.09K

1/16W

R8901

1

2

16V

10%

0.22UF

603

X7R

C8956

1

2

10UF

X5R 603

20%

6.3V

C8965

1

2

X5R 603

20%

6.3V

10UF

C8966

1

2

CRITICAL 330UF

POLY-TANT D2T-SM2

20%

2.0V

C8943

1

23

MF-LF

1K

5%

1/16W

402

R8930

1

2

POLY-TANT

16V

20%

68UF

CASE-D2E-SM

CRITICAL

C8930

1

2

1UF

X5R 603-1

10% 25V

C8932

1

2

1UF

X5R

603-1

10% 25V

C8933

1

2

1K

1/16W

1%

402

MF-LF

R8903

1

2

50V

330PF

COG 402

5%

C8906

1

2

D2T-SM2

CRITICAL

330UF

POLY-TANT

20%

2.0V

C8942

1

2 3

10UF

20% X5R

603

6.3V

C8968

1

2

603

6.3V X5R-CERM

4.7UF

10%

C8967

1

2

5%

402

MF-LF

1/16W

0

R8994

1 2

2.2K

MF-LF

402

5%

1/16W

GPUVID2_0

R8983

1

2

MF-LF

402

2.2K

5%

GPUVID2_1

1/16W

R8982

1

2

MF-LF

1/16W

5%

402

2.2K

GPUVID1_1

R8984

1

2

1/16W

5%

2.2K

MF-LF

402

GPUVID1_0

R8985

1

2

79 80

0

402

5% 1/16W MF-LF

R8990

1 2

79 80

88 91

0.001UF

X7R

50V 402

10%

C8934

1

2

402

10% 50V

0.001UF

X7R

C8969

1

2

1/16W

2.2K

5%

MF-LF

402

GPUVID0_1

R8987

1

2

402

1%

MF-LF

1/16W

100

R8924

1

2

402

100

MF-LF

1/16W

1%

R8925

12

79 80

5% 1/16W MF-LF

402

0

R8998

1 2

5%

MF-LF

1/16W

0

402

R8993

21

402

5%

MF-LF

1/16W

GPUVID4_1

2.2K

R8991

1

2

MF-LF

1/16W

402

2.2K

5%

GPUVID4_0

R8992

1

2

GPUVID0_0

MF-LF

1/16W

5%

402

2.2K

R8988

1

2

49

0612

CRITICAL

MF-1

1W

0.001

1%

R8940

12 34

1%

7.32K

402

1/16W MF-LF

R8900

1 2

FDU1040D-SM

0.56UH-31A

CRITICAL

L8920

1 2

WPAK

RJK0365DPA-02

CRITICAL

Q8950

5

4

1 2 3

CASE-D2E-SM

68UF

POLY-TANT

16V

20%

CRITICAL

C8931

1

2

79 80

2.2K

5%

1/16W

GPUVID3_1

402

MF-LF

R8995

1

2

2.2K

5%

MF-LF

1/16W

402

GPUVID3_0

R8996

1

2

WPAK

RJK0208DPA

CRITICAL

Q8951

5

4

1 2 3

GPU (Whistler) CORE SUPPLY

SYNC_MASTER=K91_CHANG

SYNC_DATE=07/21/2010

GPUVID_1P11V

GPUVID4_0,GPUVID3_0,GPUVID2_1,GPUVID1_1,GPUVID0_1

GFXIMVP6_LGATE

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_PHASE

SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S3_GFXIMVP6_PVCC

GPUVCORE_EN

GFXIMVP6_VID0

GFXIMVP6_VID4

GFXIMVP6_VID3

GFXIMVP6_VID2

GFXIMVP6_VID1

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_COMP

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_UGATE

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_PHASE_VSUM

GFXIMVP6_BOOT

MIN_LINE_WIDTH=0.3MM

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

GFXIMVP6_VW

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSEN_P

GFXIMVP6_AF_EN GFXIMVP6_FDE

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_OCSET

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM VOLTAGE=1.2V

MIN_LINE_WIDTH=0.6MM

PPVCORE_GPU_REG_R

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VSUM

MIN_NECK_WIDTH=0.1MM

GFXIMVP6_IMON

GFXIMVP6_VDIFF_RC

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GPU_GND_SENSE

VOLTAGE=0V

MIN_NECK_WIDTH=0.10 mm MIN_LINE_WIDTH=0.2 mm

GFXIMVP6_VID4

PM_ALL_GPU_PGOOD

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DROOP

GFXIMVP6_VID3

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_SOFT

GFXIMVP6_VID1

GFXIMVP6_VID0

GFXIMVP6_RBIAS

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GPU_VDD_SENSE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.10 mm MIN_LINE_WIDTH=0.2 mm

GFXIMVP6_VID2

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_DFB

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_FB

MIN_LINE_WIDTH=0.3MM

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

PP5V_S3_GFXIMVP6_VDD

GPU_VCORE_VID3

GPU_VCORE_VID0

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF

GPU_VCORE_VID2

GPU_VCORE_VID1

PP3V3_S0GPU

PPVCORE_GPU

PPVIN_S5_HS_GPU_ISNS

PP5V_S3

GFXIMVP6_VIN

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

GFXIMVP6_VSEN_N

PP3V3_S0GPU

PPVCORE_GPU

GND_GFXIMVP6_AGND

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

89 OF 132 82 OF 105

82

75

82

75

82

6 7

72 75 79 80 82 84

6 7

49 75 82

7

50 87

6 7

29

31 42 43

44 46 67

72

104

6 7

72 75 79

80 82

84

6 7

49 75 82

SYM_VER-1

NC

IN

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

NC

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Panel has 2K pull-ups

100K pull-ups are for

Place close to the connector

518S0651

no-panel case (development).

LCD (LVDS) INTERFACE

0.001UF

10% 50V X7R 402

C9010

1

2

0.1UF

10% 16V X5R

402-1

C9001

1

2

CRITICAL

FERR-250-OHM

SM

L9000

1 2

100K

5% MF-LF

402

1/16W

R9011

1

2

MF-LF

1/16W

5%

100K

402

R9010

1

2

DLP11S

90-OHM-100MA

CRITICAL

L9010

1 2

34

DLP11S

90-OHM-100MA

CRITICAL

L9011

1 2

34

F-RT-SM

20474-040E-11

CRITICAL

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

5

6

7

8

9

0.001UF

10% 50V X7R 402

C9002

1

2

100V X7R 603

1000PF

10%

C9008

1

2

88

402-1

X5R

16V

10%

0.1UF

C9009

1

2

402

MF-LF

1/16W

5%

10K

R9094

1

2

MFET-2X2

FPF1009

CRITICAL

U9000

617

2

3

4

5

402-1

X5R

16V

0.1UF

10%

C9011

1

2

10UF

20%

6.3V X5R 603

C9012

1

2

LVDS Display Connector

SYNC_DATE=04/26/2010

SYNC_MASTER=K17_MLB

PP3V3_SW_LCD

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S5

LVDS_DDC_CLK

LVDS_CONN_A_DATA_N<0> LVDS_CONN_A_DATA_P<0>

LCD_PWR_EN

LED_RETURN_5

LVDS_CONN_B_CLK_F_P

LVDS_CONN_B_CLK_N

LVDS_CONN_B_CLK_P

LED_RETURN_6

LED_RETURN_3

LED_RETURN_1

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_A_DATA_P<2>

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_A_CLK_N

LVDS_CONN_A_CLK_P

LVDS_CONN_B_DATA_P<2>

LVDS_CONN_B_CLK_F_N

PPVOUT_S0_LCDBKLT

LVDS_CONN_A_CLK_F_N

LVDS_CONN_A_DATA_P<1>

LED_RETURN_4

LED_RETURN_2

LVDS_CONN_B_DATA_N<2>

LVDS_CONN_B_DATA_N<1>

PP3V3_S0

LVDS_DDC_DATA

LVDS_CONN_A_CLK_F_P

90 OF 132 83 OF 105

6

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 86 91

100 102 104

6

84

6

84 99

6

84 99

6

89

6

99

84 99

6

89

6

89

6

89

6

84 99

6

84 99

6

84 99

6

84 99

6

84 99

6

84 99

6

84 99

6

99

6

89

103

6

99

6

84 99

6

89

6

89

6

84 99

6

84 99

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 84

85 88 89 91

100 102

6

84

6

99

VCC

C1

C2

C3

C4

A1 B1

A2 B2

A3 B3

A4 B4

GND

THRM

IN

OUT

IN

BI

BI BI

IN

OUT

HPD_2

DAUX2-

DAUX2+

DDC_CLK1 DDC_DAT1

DDC_CLK2 DDC_DAT2

HPD_1

GPU_SEL

XSD*

AUX-

AUX+

DAUX1-

DAUX1+

DDC_CLK DDC_DAT

GND

HPDIN

VDD

BI

OUT

BI

IN BI

BI

IN

BI BI

IN

OUT

IN

D

GS

OUT

IN

Y

B

A

Y

B

A

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(DP_EXTA_HPD)

T29/DP HOT PLUG IN

(DP_EXTA_HPD)

LVDS DDC MUX

LVDS Transmitter Termination

All emulated LVDS outputs require this termination

DP AUX, DDC, & HPD muxing to IG/EG

5

12

QFN1

SN74LV4066A

U9270

1

4

8

11

2

3

9

10

13

6

7

15

14

CRITICAL

88

6

83

79

18

79

18

6

83

20%

CERM

10V 402

0.1UF

C9270

1

2

20K

MF-LF

1/16W 402

R9273

1

2

5%

20K

1/16W

5%

MF-LF

402

R9272

1

2

88 99

201

1/20W

MF

1%

PLACE_NEAR=U9600.A5:7mm

357

R9257

1 2

201

1/20W

MF

1%

PLACE_NEAR=U9600.B3:7mm

357

R9252

1 2

201

1/20W

MF

1%

PLACE_NEAR=U9600.C5:7mm

357

R9255

1 2

201

1/20W

MF

357

1%

PLACE_NEAR=U9600.A1:7mm

R9250

1 2

201

1/20W

MF

1%

357

R9247

PLACE_NEAR=U9600.A3:7mm

1 2

201

1/20W

MF

1%

PLACE_NEAR=U9600.C9:7mm

357

R9242

1 2

PLACE_NEAR=U9600.A2:7mm

357

R9245

1

MF

201

1/20W

1%

2

R9240

201

1/20W

MF

357

PLACE_NEAR=U9600.C8:7mm

1%

1 2

201

1/20W

MF

1%

357

R9237

1 2

PLACE_NEAR=U9600.A10:7mm

201

1/20W

MF

1%

357

R9232

1 2

PLACE_NEAR=U9600.C10:7mm

357

2

MF

201

1/20W

1%

R9235

1

PLACE_NEAR=U9600.B10:7mm

1/20W

1%

357

R9230

1 2

201

MF

PLACE_NEAR=U9600.A9:7mm

201

1/20W

MF

1%

357

1 2

R9227

PLACE_NEAR=U9600.B9:7mm

88 99

201

1/20W

MF

1%

357

PLACE_NEAR=U9600.A7:7mm

R9222

1 2

1/20W

MF

1%

R9225

1 2

201

357

PLACE_NEAR=U9600.A8:7mm

201

1/20W

MF

1%

357

R9220

1 2

PLACE_NEAR=U9600.A6:7mm

83 99

6

83 99

6

83 99

6

83 99

6

83 99

6

83 99

6

83 99

6

83 99

6

83 99

6

83 99

6

83 99

6

83 99

6

83 99

5% 1/16W MF-LF

402

1

2

100K

R9205

19

10

U9220

18

6

7

5

8

11

3

9

12

2

14 13

17 16 20

1

BGA

CBTL03062

4

15

CRITICAL

85

85 99

2

1

C9230

0.1UF

20% 10V CERM 402

1

2

0.1UF

CERM

20% 10V

402

C9220

8

17 80

8

17 80

79 80

8

17 94

8

17 94

79 99

88

100K

2

1

402

MF-LF

1/16W

R9204

5%

8

17

79 80

88

1/16W

2

1

R9202

5%

10K

402

MF-LF

1/16W

R9206

402

MF-LF

5%

0

T29_DP_HPD:MUX_GMUX

402

MF-LF

1/16W

5%

100K

R9281

T29_DP_HPD:MCU_GMUX

2

3

Q9280

1

SOD-VESM-HF

SSM3K15FV

T29_DP_HPD:MCU_GMUX

T29_DP_HPD:ALL_OR

C9210

1

402

2

0.1UF

CERM

20% 10V

88

46 85

85

SOT833

T29_DP_HPD:ALL_OR

5

74LVC2G32GT

3

4

6

8

U9210

CRITICAL

74LVC2G32GT

T29_DP_HPD:ALL_OR

U9210

SOT833

8

2

1

7

4

MF-LF

20K

5% 1/16W

402

R9271

1

2

20K

1/16W MF-LF

402

5%

R9270

1

2

SYNC_MASTER=K92_YUN

Muxed Graphics Support

SYNC_DATE=06/25/2010

DP_EG_HPD

DP_MUX_EN

DP_EG_DDC_DATA

DP_EG_DDC_CLK

DP_IG_HPD

DP_MUX_SEL_EG

DP_T29SNK1_HPD

DP_IG_AUX_CH_N

PP3V3_S0

LVDS_CONN_A_CLK_P

LVDS_CONN_A_DATA_P<2>

LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_CLK_N

LVDS_A_DATA_P<0>

LVDS_A_DATA_P<1>

LVDS_A_DATA_N<1>

LVDS_B_CLK_P

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_N<2>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<0>

LVDS_B_DATA_N<0>

DP_EG_AUX_CH_N

LVDS_CONN_A_DATA_N<0>

DP_IG_AUX_CH_P

DP_EXTA_AUXCH_C_P

DP_EG_AUX_CH_P

LVDS_B_DATA_P<0>

LVDS_CONN_B_CLK_P

LVDS_CONN_B_DATA_N<1>

LVDS_A_DATA_P<2>

LVDS_A_DATA_N<2>

LVDS_CONN_B_DATA_P<2>

LVDS_CONN_B_CLK_N

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_A_DATA_P<1>

LVDS_B_CLK_N

LVDS_B_DATA_N<2>

LVDS_B_DATA_P<2>

LVDS_B_DATA_N<1>

LVDS_B_DATA_P<1>

LVDS_A_DATA_N<0>

LVDS_CONN_A_DATA_N<1>

LVDS_A_CLK_N

LVDS_A_CLK_P

PP3V3_S0GPU

LVDS_DDC_CLK

LVDS_DDC_DATA

PP3V3_S0

LVDS_DDC_SEL_EG

LVDS_DDC_SEL_IG

LVDS_EG_DDC_CLK

LVDS_IG_DDC_CLK

LVDS_EG_DDC_DATA

LVDS_IG_DDC_DATA

DP_IG_DDC_CLK DP_IG_DDC_DATA

DP_A_EXT_HPD

DP_EXTA_DDC_DATA

DP_EXTA_AUXCH_C_N

DP_EXTA_DDC_CLK

T29_HOTPLUG_DET_OR

PP3V3_S0

DP_T29SNK0_HPD

PP3V3_S0

DP_HOTPLUG_DET

DP_EXTA_HPD

92 OF 132 84 OF 105

33 80

6 7

12 23 25 26 28 32 35 36 39

40 41 46 48 49 50 51 52 54 57 61 62 72

73 80 83 84 85 88 89 91

100 102

6 7

72 75 79 80 82

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

12 23 25 26 28 32 35

36 39 40 41 46 48 49 50

51 52 54 57 61 62 72 73

80 83 84 85 88 89 91

100

102

33 80

6 7

12 23 25 26 28 32 35 36 39 40

41 46 48 49 50 51 52 54 57 61 62 72

73 80 83 84 85 88 89 91

100 102

OUT OUT

BI

OUT

IN

IN IN

OUT OUT

IN

IN BI

BI

NC

IN BI

THMPAD

GND

VDD

OUT_D0P OUT_D0N

OUT_D1P

OUT_D2P

OUT_D1N

OUT_D3P

OUT_D2N

OUT_D3N

AC_AUXP AC_AUXN

OUT_HPD

CEXT

IN_D0P IN_D0N

IN_D1N

IN_D2N

IN_D3P

IN_SDA

IN_AUXP IN_AUXN

IN_HPD

I2C_CTL_EN

I2C_ADDR0 I2C_ADDR1

SCL_CTL SDA_CTL

REXT

AUXDDC_OFF

PD

CA_DET

IN_SCL

IN_D3N

IN_D2P

IN_D1P

OUT_AUXN_SDA

OUT_AUXP_SCL

BI BI

IN

BI

OUT

IN

OUT

VDD

PIO1_8/CT16B1_CAP0

PIO1_7/TXD

XTALIN

PIO1_4/AD5/WAKEUP

PIO1_6/RXD

SWDIO/PIO1_3/AD4

R/PIO1_2/AD3

R/PIO1_1/AD2

R/PIO1_0/AD1

RESET#/PIO0_0 PIO0_1/CLKOUT

SWCLK/PIO0_10/SCK/CT16B0_MAT2

PIO0_9/MOSI/CT16B0_MAT1

PIO0_8/MISO/CT16B0_MAT0

PIO0_2/SSEL/CT16B0_CAP0

R/PIO0_11/AD0

PIO0_7/CTS#

PIO0_6/SCK

PIO0_4/SCL PIO0_5/SDA

VSS

THRM

PAD

BI

OUT OUT

IN

AUX-

AUX+

DOUT_1+ DOUT_1-

NC

GND

THMPAD

GPU_SEL

HPD_2

AUX2-

AUX2+

DIN2_1-

DIN2_1+

DIN2_0-

HPD_1

AUX1-

AUX1+

DIN1_1-

DOUT_0-

DIN1_0+ DIN1_0-

DIN1_1+

HPD_IN

DOUT_0+

DIN2_0+

VDD

AUX_SEL

OUT

IN

IN IN

OUT OUT

IN IN

OUT OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

use PCIe WAKE#

=T29_WAKE_L:

R9330 provides pads for programming/debug of MCU, please make accessible. If project has space for 10-pin programming header it should be used.

and DDC, alias nets together at GPU.

(C9372.2)

IC supports input

PS8301 I2C Addresses:

so only 94/B4 are used for this part.

high while Vcc = 0V.

LO=Port A HI=Port B

U9390 BOM table in csa 5!!!

Note: U9390 ML/HPD defaults to T29 mode so that DP/T29 Display can detect host T29 support using I2C pull-ups on ML<3>. U9390 AUX defaults to DP mode

Must be 3.3V DP A port power

used by PS8301

(DP_SDRVA_HPD)

(IPD)

(C9383.2)

DP/T29 A Low-Speed MUX

(All 4 L’s)

(Both L 153S1376)

(C9380/C9381)

(D9382/D9383)

(OD)

(D9372/D9373)

(T29_A_LSX_R2P)

(T29_A_LSX_P2R)

0 0 0x96/0x97

(D9365.2)

(IPD)

1 1 0xB4/0xB5

devices use 96/B6,

Note: Other Parade

0 1 0xB6/0xB7

A1 A0 Addr (W/R)

PS8301 has internal ~150K pull-down on PD

(IPD)

PI3vEDP212 (353S3055) are

CBTL04DP081 (353S3151) and

footprint-compatible parts with

pin 10 for ML and pin 11 for HPD.

10 for ML and HPD, Pericom uses

similar pinouts. NXP uses pin

because 100-ohm pull-downs would defeat DP Sink’s

T29: LSX_A_R2P/P2R (P/N)

(OD)

(IPU)

0x26/0x27 (Wr/Rd)

R2P = Receptacle to Plug

P2R = Plug to Receptacle

detection of DP Source.

SWCLK

SWDIO

I2C Addr:

(D9364.2)

T29: TX_0

T29: TX_1

(D9360.2)

D9372/D9373:

T29: RX_1 Bias Sink

D9364/D9365:

T29 A High-Speed Signals

R9308/R9309 maintain bias on C9308/C9309

(C9370/C9371)

(All 4 D’s)

T29: Unused

transitions from high to low.

to prevent spikes when U9310 AUXDDC_OFF

(DP_SDRVA_AUXCH_P)

AUXCH Snoop Port,

(DP_SDRVA_AUXCH_N)

Must be 3.3V DP A port power

Port A MCU

DP A Super-Driver

during training.

1 0 0x94/0x95

(D9361.2)

(D9360/D9361)

(D9382/D9383)

Biasing

(All 4 D’s)

Parade (pin is 5V-tolerant).

pin even when VCC=0V per

pin. Okay to drive this

(IPD)

(IPU)

If GPU uses common pins for AUX_CH

T29 signals are P/N-swapped after AC

(C9373.2)

(C9383.2)

DP Path Biasing

T29 Path

caps to improve layout.

6

33 97

6

33 97

6

86 97

6

86 97

MF-LF

1/16W

1K

5%

402

R9312

1

2

MF-LF 402

1% 1/16W

4.99K

R9319

1

2

84

NO STUFF

R9311

MF-LF

5%

402

1K

1/16W

1

2

R9310

5%

402

MF-LF

1/16W

1K

1

2

10V

20% CERM

402

0.1UF

C9311

1

2

0.1UF

20% 10V

402

CERM

C9312

1

2

PLACE_NEAR=U9310.11:2 mm

20%

6.3V CERM

402-LF

2.2UF

C9319

1

2

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

6

33 97

0.1uF

16V 402X5R

10%

1 2

C9306

0.1uF

16V 402X5R

10%

1 2

C9307

79 99

0.1uF

10%

402X5R

16V

1 2

C9304

79 99

10% 16V X5R

1 2

402

0.1uF

C9305

79 99

X5R

0.1uF

10%

402

16V

C9302

1 2

79 99

X5R 402

16V10%

0.1uF

C9303

1 2

79 99

16V 402X5R

0.1uF

10%

C9300

1 2

79 99

16V 402X5R

10%

C9301

1 2

0.1uF

79 99

48

X5R

0.1uF

16V 402

10%

C9308

1 2

X5R

10% 16V

0.1uF

402

C9309

1 2

84 99

402

1/16W

100K

MF-LF

5%

R9399

1

2

402

MF-LF

1/16W

5%

100K

R9398

1

2

84

CRITICAL

PS8301TQFN40GTR-A2

QFN

U9310

19

20

39

32

11

6

33

36 35

26

15

16

2

1

5

4

8

7

10

9

3

14 13

17

18

29

30

27

28

24

25

22

23

31

34

12

38 37

41

21

40

6.3V

402-LF

CERM

1

2

20%

2.2UF

C9310

86 97

402

10% X5R

16V

0.1uF

C9363

1 2

402

16V

X5R

10%

0.1uF

C9362

1 2

16V10% 402X5R

0.1uF

C9367

1 2

16V 402

10% X5R

0.1uF

C9366

1 2

85 88

6

86 97

6

86 97

46 84 85

0.1uF

16V10% 402X5R

C9369

1 2

0.1uF

16V10%

X5R 402

C9368

1 2

18

6

17 25 31 32

33

HVQFN25

LPC1112A

CRITICAL

OMIT_TABLE

U9330

2 7

8

9 10 11 12 13

20

23 24

6

15

16 17 18

1

14

19

25

5

22

3

21

4

33 48 97

85 86

33

33 48 97

33

402

MF-LF

1K

5% 1/16W

R9335

1

2

402

MF-LF

1/16W

10K

5%

R9336

1

2

CERM

10V

20%

0.1UF

402

C9330

1

2

33

86

0.1UF

10V 402

1

2

C9331

20% CERM

MF-LF

5%

402

1K

1/16W

R9397

2

1

5%

MF-LF

1/16W

402

1K

R9396

2

1

1M

402

1/16W MF-LF

5%

R9339

1

2

10K

402

1/16W MF-LF

5%

R9338

1

2

86

5%

MF-LF

1/16W

402

OMIT

0

R9330

1

2

51

5% 1/16W

402

MF-LF

R9393

1

2

MF-LF

51

402

1/16W

5%

R9392

1

2

SIGNAL_MODEL=T29DP_MUX

CBTL04DP081

HVQFN

CKPLUS_WAIVE=NdifPr_badTerm

CRITICAL

U9390

18

19

14

15

7

6

32

30

31

26

27

24

25

22

23

2

1

5

4

21

28

10

17

13

8

11

33

39121620

29

OMIT_TABLE

35 86

10K

402

5% 1/16W MF-LF

R9334

1 2

16 23

MF-LF

1/16W

5%

0

SDRV_PD

402

R9318

2

1

MF-LF5%402

1/16W

1M

1 2

R9308

1M

402

5%

1/16W

R9309

21

MF-LF

6

86 97

6

86 97

6

86 97

6

86 97

D9364

SIGNAL_MODEL=EMPTY

TSLP-2-7

GND_VOID=TRUE

BAR90-02LRH

CRITICAL

1 2

2

TSLP-2-7

SIGNAL_MODEL=T29PIN

BAR90-02LRH

GND_VOID=TRUE

CRITICAL

D9373

1

GND_VOID=TRUE

BAR90-02LRH

TSLP-2-7

CRITICAL

SIGNAL_MODEL=T29PIN

1 2

D9372

TSLP-2-7

SIGNAL_MODEL=EMPTY

GND_VOID=TRUE

BAR90-02LRH

CRITICAL

D9365

1 2

GND_VOID=TRUE

TSLP-2-7

BAR90-02LRH

CRITICAL

SIGNAL_MODEL=EMPTY

D9360

1 2

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

CRITICAL

TSLP-2-7

D9382

1 2

BAR90-02LRH

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

TSLP-2-7

CRITICAL

1 2

D9383

BAR90-02LRH

SIGNAL_MODEL=EMPTY

CRITICAL

TSLP-2-7

GND_VOID=TRUE

D9361

1 2

C9370

20%

201

GND_VOID=TRUE

1 2

4V

CERM-X5R-1

0.47UF

GND_VOID=TRUE

1.5K

5%

201

1/20W

MF

1 2

R9372

SIGNAL_MODEL=EMPTY

201

1/20W

1.5K

5% MF

GND_VOID=TRUE

R9373

1 2

SIGNAL_MODEL=EMPTY

1.5K

1/20W

201MF

5%

2

SIGNAL_MODEL=EMPTY

1

R9382

GND_VOID=TRUE

1.5K

5%

201

1/20W

MF

GND_VOID=TRUE

R9383

1 2

SIGNAL_MODEL=EMPTY

6.3V

0.47UF

10%

GND_VOID=TRUE

402

CERM-X5R

1 2

C9373

CERM-X5R

10%

GND_VOID=TRUE

402

C9372

0.47UF

6.3V

21

CERM-X5R-1

C9371

0.47UF

20%

201

GND_VOID=TRUE

4V

1 2

6.3V 402

10% CERM-X5R

C9382

1 2

0.47UF

GND_VOID=TRUE

10% CERM-X5R

6.3V

1 2

402

GND_VOID=TRUE

0.47UF

C9383

0.22UF

X5R 201

20%

6.3V

C9364

1 2

1.5K

201

5%MF1/20W

GND_VOID=TRUE

R9385

1 2

1.5K

5%

1/20W

201MF

GND_VOID=TRUE

R9384

1 2

86 97

1.5K

GND_VOID=TRUE

MF5%201

1/20W

R9375

1 2

1.5K

GND_VOID=TRUE

MF

5%

1/20W

201

R9374

1 2

1.0NH+/-0.1NH

L9383

0201-1

1 2

CRITICAL

OVERSIZE_PAD=0.875 mm^2

1.0NH+/-0.1NH

L9382

0201-1

1 2

CRITICAL

OVERSIZE_PAD=0.875 mm^2

L9372

1.0NH+/-0.1NH

0201-1

1 2

CRITICAL

OVERSIZE_PAD=0.875 mm^2

1.0NH+/-0.1NH

L9373

0201-1

1 2

CRITICAL

OVERSIZE_PAD=0.875 mm^2

30

1/20W 201MF

5%

R9354

1 2

C9390

0.1UF

CERM 402

10V

20%

1

2

C9391

402

CERM

0.1UF

10V

20%

1

2

21

R9360

201MF

5%

1/20W

1.5K

21

R9361

5%

1/20W

201MF

21

R9364

5%

201MF

1/20W

1.5K

21

R9365

MF5%201

1/20W

1.5K

SC70

74LVC1G04DBDCK

2

3

5

4

U9359

CRITICAL

16V

C9359

0.1UF

402

10% X5R

1

2

X5R 201

6.3V

20%

0.22UF

C9365

1 2

20%

6.3V 201X5R

0.22UF

C9360

1 2

201

0.22UF

6.3V

X5R

20%

C9361

1 2

201

CERM-X5R-1

4V

0.47UF

20%

C9380

1 2

GND_VOID=TRUEGND_VOID=TRUE

20%

4V

C9381

1 2

201

0.47UF

CERM-X5R-1

270

201

5% 1/20W MF

R9352

1

2

201

5% MF

270

1/20W

R9353

1

2

30

5% MF 201

1/20W

R9355

1 2

30

1/20W 201MF

5%

R9350

1 2

30

5% MF

201

1/20W

R9351

1 2

6 8

2

5%511/20W

201

MF

PLACE_NEAR=C9361.1:2mm

R9362

1

1/20W

201

5%MF

51

PLACE_NEAR=C9361.1:2mm

R9363

12

201

5%

1/20W

MF

51

PLACE_NEAR=C9361.1:2mm

R9366

12

PLACE_NEAR=C9361.1:2mm

1/20W

201515%MF

R9367

12

SYNC_DATE=10/22/2010

SYNC_MASTER=K91_MLB

DisplayPort/T29 A MUXing

DP_EXTA_AUXCH_N

DP_EXTA_AUXCH_P

DP_EXTA_ML_P<1>

DP_EXTA_ML_N<2>

T29_R2D_N<1>

T29_R2D_N<0>

T29_R2D_P<0>

DP_SDRVA_ML_N<2>

DP_SDRVA_ML_P<2>

DP_SDRVA_ML_N<0>

DP_SDRVA_ML_P<0>

T29_A_BIAS_R2D_P0

T29_D2R_C_P<1> T29_D2R_C_N<1>

T29_R2D_P<1>

DP_EXTA_ML_P<0>

DP_SDRVA_AUXCH_N

DP_SDRVA_ML_N<3>

PP3V3_S0

DP_SDRVA_ML_P<1>

VOLTAGE=3.3V

DP_A_BIAS_N_0

T29DPA_ML_C_N<2>

DP_A_BIAS_P_0

VOLTAGE=3.3V

DP_A_BIAS_P_2

VOLTAGE=3.3V

DP_SDRVA_ML_P<3>

DPSDRVA_I2C_ADDR1

T29_A_RSVD_P

T29_A_RSVD_N

DP_SDRVA_HPD

DP_SDRVA_ML_N<1>

DP_SDRVA_AUXCH_C_P

DP_EXTA_ML_P<3> DP_EXTA_ML_N<3>

DP_EXTA_DDC_CLK

PP3V3_SW_DPAPWR

T29_A_LSX_R2P

T29_D2R1_BIASP

T29_A_HV_EN

I2C_T29_SCL

T29_LSEO<0>

DP_A_PWRDWN

DP_A_CA_DET

DP_SDRVA_ML_C_P<3>

DP_SDRVA_ML_C_P<1>

DPSDRVA_REXT

DP_EXTA_ML_P<2>

T29DPA_ML_N<3>

T29_A_BIAS_R2D_N1

T29_A_BIAS_R2D_N0

T29_A_BIAS_R2D_P1

T29DPA_ML_C_P<2>

DPSDRVA_I2C_ADDR0

DPSDRVA_I2C_CTL_EN

DP_EXTA_ML_N<0>

PP3V3_S0

T29_D2R1_BIASN

DP_A_EXT_AUXCH_N

DP_EXTA_ML_N<3>

DP_A_EXT_HPD

DP_EXTA_ML_P<3>

DP_EXTA_AUXCH_P

DP_EXTA_DDC_DATA

DP_EXTA_AUXCH_C_P

DP_EXTA_ML_C_N<3>

DP_EXTA_ML_P<2>

DP_EXTA_ML_C_P<0>

T29_A_UC_ADDR

T29_LSEO<1>

T29DPA_CONFIG2_RC

PCIE_WAKE_L

I2C_T29_SDA

T29_LSOE<0>

DP_A_EXT_AUXCH_P

T29DPA_ML_P<3>

DP_A_EXT_HPD

DPSDRVA_CEXT

DP_EXTA_ML_P<0>

DP_EXTA_AUXCH_N

DP_EXTA_ML_P<1>

DP_EXTA_HPD

DP_AUXCH_ISOL

I2C_DPSDRVA_SCL

DP_A_PWRDWN_R

DP_EXTA_ML_N<0>

DP_EXTA_ML_N<1>

T29_MCU_INT_L

T29_LSOE<1>

T29DPA_HPD T29_A_BIAS

DP_A_PWRDWN

T29DPA_ML_C_P<0>

T29DPA_ML_N<1> T29DPA_ML_P<1>

T29_A_BIAS

DP_EXTA_AUXCH_C_N

DP_A_PWRDWN

I2C_DPSDRVA_SDA

DP_EXTA_ML_N<2>

T29DPA_ML_C_N<0>

T29_D2R_C_P<0> T29_D2R_C_N<0>

DP_EXTA_ML_N<1>

T29_D2R_P<1>

T29_D2R_N<0> T29_D2R_P<0>

DP_A_BIAS

T29_R2D_C_N<0>

T29_R2D_C_F_N<0>

T29_R2D_C_P<0>

T29_R2D_C_F_P<0>

T29_R2D_C_N<1>

T29_R2D_C_F_N<1>

T29_R2D_C_P<1>

T29_R2D_C_F_P<1>

T29_D2R_N<1>

PP3V3_SW_DPAPWR

DP_SDRVA_ML_C_N<1>

DP_SDRVA_ML_C_N<3>

DP_SDRVA_AUXCH_C_N

DP_SDRVA_AUXCH_P

T29DPA_CONFIG1_RC

T29_A_UC_ADDR

T29_A_LSX_P2R

T29_A_HV_EN_R

DP_A_BIAS_N_2

VOLTAGE=3.3V

DP_SDRVA_ML_C_P<0>

DP_SDRVA_ML_R_P<0> DP_SDRVA_ML_R_N<0>

DP_SDRVA_ML_C_N<0>

DP_SDRVA_ML_C_P<2> DP_SDRVA_ML_C_N<2>

DP_SDRVA_ML_R_N<2>

DP_SDRVA_ML_R_P<2>

DP_EXTA_ML_C_N<0>

PP3V3_S0

DP_EXTA_ML_C_P<3>

DP_EXTA_ML_C_N<2>

DP_EXTA_ML_C_P<2>

DP_EXTA_ML_C_N<1>

DP_EXTA_ML_C_P<1>

93 OF 132 85 OF 105

85

6

85

6

97

6

97

6

97

6

97

6

97

6

97

6

97

6

97

6

85

97

6 7

12 23 25 26 28 32 35 36 39 40 41

46 48 49 50 51 52 54 57 61 62 72 73 80

83 84 85 88 89 91

100 102

97

6 8

97

6

85

85 86

85

85 88

97

6

85

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

85

46 84 85

6

85

6

85

6

85

6

85

85 86

85

6

97

85 86

97

85

6 8

6

97

6

97

6 7

12 23

25 26 28 32

35 36 39 40

41 46 48 49

50 51 52 54

57 61 62 72

73 80 83 84

85 88 89 91

100 102

OUT

IN IN

BI

IN

OUT OUT

BI BI

BI

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

DP_PWR

ML_LANE2P

AUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P ML_LANE3N

ML_LANE2N

CONFIG1 CONFIG2

BOT ROW TOP ROW

TH PINS SM PINS

SHIELD PINS

IN

OC*

OUT

EN

GND

IN

D

SG

D

S G

G

D

S

D

G S

OUT

BI

IN

GND

PGND

OUT

FB

IN

SGD

GND

PGND

OUT

FB

IN

CT

EN*

RTRY*

VIN

THRM

GND

IFLT

ILIM

FLT*

VOUT

PAD

IN IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SI8409DB:

Rds(on): 65mOhm @ 2.5V Vgs

Nominal Min Max IFLT 885mA 876mA 894mA (*)

3.3V Always

Blocking FET, off

TSD 470ms 235ms 724ms

TFLT 18.3ms 13.4ms 26.7ms

Id(max): 3.7A @ 70C

when Source >3.4V

ILIM 935mA 925mA 944mA (*)

Port A HV Power Switch

3.3V/HV MUXed

3.3V/HV Power MUX Port A 3.3V Power Switch

or HV_EN high.

(*) U9410 tolerance unknown

IFLT = 200k / RFLT = 885mA

TFLT = CCT * 38900

20V Max

ZXRE060A REF range: 0.595-0.605V (0.600V nominal) Circuit threshold range: 3.363-3.439V (3.395V nominal)

DP Dir

TSD = CCT * 100000

Note: Bleeder active when

470k R’s for ESD protection

ILIM = 201k / RLIM = 935mA

P = ~27mW

(Both C’s)

T29 Dir

For J9400 T29 SMT pads

<CT>

Low: 0 - 0.8V

(IPU-Weak!)

T29 Dir

(3, 5, 17 & 19):

DP Dir

T29: TX_0

T29: TX_1

T29: LSX_R2P/P2R (P/N)

(Both L’s)

<RLIM>

Circuit threshold range: 2.877-2.941V (2.903V nominal)

DisplayPort/T29 A Connector

HIGH and T29_A_HV_EN

DP Source must pull

Sink HPD range: High: 2.0 - 5.0V

to 100K (DPv1.1a).

greater than or equal

down HPD input with

<RFLT>

wake from T29 devices.

DP_PWR must be S4/S5 to support

Bleeder Resistor

DPAPWRSW_HV_DET is

is LOW.

2.5V / 249 ohm = 10mA

Vgs(th): -1.4V

Vgs(max): +/-12V

Vds(max): -30V

on AC-coupled signals.

T29: Unused

50V

1

2

10% X7R

402

0.01UF

C9400

6

85 97

6

85 97

6

85 97

6

85 97

21

1/16W

5%

12

MF-LF

402

R9403

GND_VOID=TRUE

MF-LF

1/16W

402

21

12

5%

R9404

GND_VOID=TRUE

R9405

21

5%

12

201

1/20W

MF

GND_VOID=TRUE

1

10%

402

2

C9402

50V

0.01UF

X7R

2

L9408

0603

FERR-120-OHM-3A

1

5%

1/16W

21

MF-LF

12

402

R9402

12

21

MF-LF

5%

402

1/16W

R9401

402

0.01UF

2

10% 50V X7R

C9401

1

R9494

2

1

1K

5%

1/20W

MF

201

GND_VOID=TRUE

SIGNAL_MODEL=EMPTY SIGNAL_MODEL=EMPTY

R9495

2

1

1K

5% 1/20W MF 201

GND_VOID=TRUE

C9498

2

1

30PF

50V

5%

402

CERM

C9499

2

1

50V CERM

5%

30PF

402

2

1

R9441

5% MF-LF

1/16W 402

100K

650NH-5%-0.430MA-0.052OHM

CRITICAL

GND_VOID=TRUE

12

L9498

0603

650NH-5%-0.430MA-0.052OHM

L9499

1

GND_VOID=TRUE

2

0603

CRITICAL

6

85 97

6

85 97

6

85 97

4.7K

402

2

1/16W MF-LF

5%

R9425

1

DSPLYPRT-M97-1

F-RT-THSM

GND_VOID=TRUE

19

10 12

15 17

9 11

3 5

22 21

2

14 13

8 7

1

20

6

4

16 18

J9400

CRITICAL

GND_VOID=TRUEGND_VOID=TRUEGND_VOID=TRUE

6.3V

1

603

X5R

2

20%

10UF

C9486

3

5

2

4

U9480

TPS2051B

CRITICAL

SOT23

1

2

1

402

CERM

10V

20%

0.1UF

C9485

2

1

C9481

CERM

402

0.1UF

10V

20%

22UF

2

1

C9480

CRITICAL

20%

6.3V 603

X5R-CERM-1

2

POLY-TANT

6.3V

1

100UF

CASE-B2-SM

20%

C9487

CRITICAL

MMDT3946XG

Q9426

1

6

5

2

3

SOT363

4

402

R9430

2

1

5% MF-LF

1/16W

4.7K

R9426

2

1

1K

402

5% MF-LF

1/16W

MF-LF

2

1

R9432

1/16W 402

5%

10K

2

1

402

1/16W

5%

4.7K

R9429

MF-LF

402

MF-LF

1

2

1/16W

1%

100K

R9427

21.5K

R9428

1

2

402

MF-LF

1/16W

1%

45 46 73

SSM6N37FEAPE

4

5

SOT563

3

Q9430

SOT563

6

1

2

SSM6N37FEAPE

Q9430

1/20W

1M

2

1

R9452

201

MF

5%

201

2

1

R9451

1/20W MF

1M

5%

2

1

C9494

201

X7R

16V

330PF

10%

C9495

330PF

2

1

201

X7R

16V

10%

GND_VOID=TRUE

1/20W

2

1

R9498

5%

2.2K

MF

201

SIGNAL_MODEL=EMPTY

R9499

5% MF

GND_VOID=TRUE

2

1

1/20W 201

2.2K

SIGNAL_MODEL=EMPTY

470K

2

1

1/16W MF-LF

5%

402

R9416

SOT-563

5

3

4

DMB53D0UV

Q9419

1/16W MF-LF

5%

402

R9418

1 2

1K

2

SOT-563

6

DMB53D0UV

Q9419

1

2

1

3

Q9415

SSM3K15FV

SOD-VESM-HF

MF-LF

249

402

1/16W

1%

2 1

R9419

21

0603

L9400

FERR-120-OHM-3A

85

6

85 97

35 85 86

1

3

2

ZXRE060A

SOT353

4

5

CRITICAL

U9426

32

1

4

Q9425

BGA

SI8409DB

CRITICAL

20% 10V

1

402

CERM

2

0.1UF

C9429

NO STUFF

20%

402

10V

CERM

0.1UF

1

2

C9426

U9435

1

5

3

2

SOT353

ZXRE060A

4

CRITICAL

85 86

2

1

C9435

CERM 402

10V

0.1UF

20%

MF-LF

100K

1%

402

1/16W

R9435

1

2

24.9K

402

R9436

MF-LF

1/16W

1%

2

1

1UF

X5R

10V

402

1

2

10%

C9436

R9433

5%

2

1

1/16W

402

MF-LF

220

CERM-X5R

2

1

C9412

0.47UF

402

10%

6.3V 402

2

1

5%

100K

R9410

MF-LF

1/16W

200K

2

1

R9411

1/16W MF-LF

1%

402

0.1UF

10% X7R

50V

1

603-1

2

C9410

2

CRITICAL

10

TPS2590

17

6

4

7

8

14

13

5

1516

9

QFN

11

3

1

12

U9410

50V

C9411

603-1

X7R

10%

2

0.1UF

1

BAR90-02LRH

D9499

SIGNAL_MODEL=T29PIN

GND_VOID=TRUE

CRITICAL

21

TSLP-2-7

D9498

BAR90-02LRH

GND_VOID=TRUE

21

CRITICAL

TSLP-2-7

SIGNAL_MODEL=T29PIN

2

1

R9470

201

470K

5%

GND_VOID=TRUE

1/20W MF

85 97

21

C9472

4V 201

20%

GND_VOID=TRUE

0.47UF

CERM-X5R-1

2

1

GND_VOID=TRUE

1/20W MF 201

5%

470K

R9471

2

1

R9472

470K

5%

201

1/20W MF

GND_VOID=TRUE

2

1

R9473

MF

1/20W 201

GND_VOID=TRUE

5%

470K

21

C9473

201

20%

4V

GND_VOID=TRUE

0.47UF

CERM-X5R-1

21

C9470

201

20%

0.47UF

4V

GND_VOID=TRUE

CERM-X5R-1

21

C9471

0.47UF

201

20%

GND_VOID=TRUE

4V

CERM-X5R-1

21

R9406

5%

12

GND_VOID=TRUE

1/20W

MF

201

21

R9407

5%

12

GND_VOID=TRUE

201

MF

1/20W

21

MF

1/20W

201

12

5%

R9408

PLACE_NEAR=C9490.1:2mm

2

1

5% 1/20W

201

R9490

51

MF

C9490

0.1UF

21

201

X5R

6.3V

10%

8

82

1/16W MF-LF

402

5%

R9437

CRITICAL

SM

STPS2L30AF

D9410

D9425

CRITICAL

DFLS1100

POWERDI-123

2 1

402

2

1

22

5% 1/16W MF-LF

R9424

C9424

0.47UF

402

21

CERM-X5R

6.3V

10%

SYNC_DATE=10/22/2010

DisplayPort/T29 A Connector

SYNC_MASTER=K91_MLB

T29_A_BIAS_D2R_P1

T29DPA_ML_N<3>

T29DPA_D2R1_AUXCH_P T29DPA_D2R1_AUXCH_N

T29DPA_HPD_R

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=3.3V

PP3V3_SW_DPAPWR

DPAPWRSW_CT

DP_A_EXT_AUXCH_N

T29_A_HV_EN

DPAPWRSW_IFLT

T29DPA_ML_C_N<0>

DPAPWRSW_P3V3_ON

TP_DPAPWRSW_FLT_L

DPAPWRSW_HV_DET

MIN_LINE_WIDTH=0.20 MM

DPAPWR_BLDR_E

MIN_NECK_WIDTH=0.20 MM

DPAPWRSW_NPN_E

T29_A_BIAS

DPACONN_20_RC

MIN_NECK_WIDTH=0.20 MM VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM

T29_A_BIAS_R

VOLTAGE=3.3V

T29_D2R_C_N<1>

DPAPWRSW_ON_C

T29_A_BIAS_D2R_N1

DP_A_EXT_AUXCH_P

T29DPA_CONFIG1_RC

T29DPA_ML_N<1>

T29DPA_ML_P<1>

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM VOLTAGE=0V

GND_DPACONN_13

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_7

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

T29DPA_ML_N<0>

T29DPA_ML_P<0>

T29DPA_ML_N<2>

T29DPA_ML_P<2>

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_1

SMC_S4_WAKESRC_EN

T29DPA_ML_C_P<0>

T29DPA_ML_C_N<2>

T29DPA_ML_C_P<2>

DPAPWRSW_HVEN_L_R

T29_A_HV_EN

DPAPWRSW_ILIM

T29DPA_ML_P<3>

T29_D2R_C_N<0>

T29DPA_CONFIG2_RC

MIN_LINE_WIDTH=0.38 MM

GND_DPACONN_8

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

DPAPWR_BLDR_B

DPAPWRSW_HV_DET_L

T29_D2R_C_P<0>

DPAPWRSW_VREF

T29_A_BIAS

PP3V3_S5

MIN_LINE_WIDTH=0.38 MM VOLTAGE=0V

MIN_NECK_WIDTH=0.20 MM

GND_DPACONN_19

VOLTAGE=15V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

PP3V3RHV_SW_DPAPWR

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM VOLTAGE=0V

GND_DPACONN_14

T29_D2R_C_P<1>

DPAPWR_FB_DIV

PP15V_T29

DPAPWR_ON_L_C

DPAPWRSW_P3V3_ON_L

T29_A_HV_EN

T29DPA_HPD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=15V

PPHV_SW_DPAPWR

VOLTAGE=15V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3RHV_SW_DPAPWR_UF

DPAPWRSW_HV_DET_R_L

94 OF 132 86 OF 105

6

97

6

97

85

6

97

6

97

6

97

6

97

35 85 86

85 86

6 7

17 19 20 22

23 24 25 29 46

48 56 71 72 73

83 91

100 102

104

7 8

35

35 85 86

OUT

IN

THRM_PAD

POK1

REF

TON

EN_LDO

VREF3

VIN

LDO

LDOREFIN

BYP FB1 ILIM1

EN1

PVCC

SECFB

GND

PGND

LGATE2

BOOT2

PHASE2

UGATE2

EN2

POK2

SKIP*

OUT2

ILIM2

REFIN2

VCC

OUT1

LGATE1

PHASE1

UGATE1

BOOT1

NC

D

GS

IN

G

D

S

G

D

S

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FBVDDQ

1 0

GPIO7

1.35V

1.503V

Vout = 2(Req/(Ra+Req))

<Ra>

(=PP1V5FB_S0_REG)

(SGND)

<Rb>

353S2312

(Rb should be between 10K and 100K)

Vout = 0.7V * (1 + Ra / Rb)

(Q9510 limit?)

3.5A MAX OUTPUT

Vout = 1.003V

f = 400 kHz

<Rb>

<Ra>

from PVCC to VCC)

(Internal 10-ohm path

Vout = 1.503V 8A MAX OUTPUT F = 500 KHZ

20.0K

402

1/16W MF-LF

1%

R9521

1

2

8

74 82 87 88 91

88 91

MF-LF

1/16W 402

1%

75K

R9535

1

2

CRITICAL

2.2UH-8.0A

PCMB065T-SM

L9510

1 2

CRITICAL

20% 16V

POLY-TANT

68UF

CASE-D2E-SM

C9540

1

2

X5R

1UF

603-1

25V

10%

C9545

1

2

0.1UF

X7R

50V

10%

603-1

C9530

1

2

SIZ700DT

CRITICAL

POWERPAIR-6X3.7

Q9510

1

6

45

237

8

8.66K

MF-LF 402

1% 1/16W

R9520

1

2

402

5%

4.7

1/16W MF-LF

R9500

12

SM

XW9500

1 2

10V

20%

402

CERM

0.1UF

C9585

1

2

35.7K

402

1/16W

1%

MF-LF

R9564

1

2

10%

0.001UF

402

CERM

50V

C9561

1

2

CRITICAL

QFN2

ISL6236

U9500

17 24

9

14 27

4

11

21

12 31

7

8

18 23

10 30

22

16 25

13

28

19

1

32

20

29

33

2

15 26

365

CRITICAL

805

25V

10% X5R

10UF

C9500

1

2

10% X5R

402-1

1UF

10V

C9501

1

2

NO STUFF

5%

100PF

402

CERM

50V

C9520

1

2

130K

1%

1/16W

402

MF-LF

R9585

1

2

10V X5R

1UF

10%

402-1

C9504

1

2

11.8K

1/16W MF-LF

1%

402

R9563

1

2

10%

402-1

10V

1UF

X5R

C9503

1

2

78.7K

MF-LF 402

1% 1/16W

R9562

1

2

CRITICAL

SSM3K15FV

SOD-VESM-HF

Q9565

3

1

2

79 80

X7R 603-1

10%

0.1UF

50V

C9580

1

2

CRITICAL

20% 16V

POLY-TANT

68UF

CASE-D2E-SM

C9590

1

2

603-1

X5R

1UF

10% 25V

C9595

1

2

CRITICAL

PWRPK-12128

SIS426DN

Q9561

5

4

1 2 3

SM

PLACE_NEAR=L9560.2:3mm

XW9565

12

CRITICAL

1.0UH-13A-5.6MOHM

PCMB065T-SM

L9560

1 2

SIS426DN

CRITICAL

PWRPK-12128

Q9560

5

4

1 2 3

CRITICAL

603

20%

10UF

X5R

6.3V

C9565

1

2

PLACE_NEAR=L9510.1:3mm

SM

XW9515

1 2

POLY-TANT

CRITICAL

CASE-B2-SM2

20%

2.5V

220UF

C9560

1

2

402

25V

5%

1000PF

NP0-C0G

C9546

1

2

NP0-C0G 402

1000PF

5% 25V

C9596

1

2

402

NP0-C0G

1000PF

5%

25V

C9516

1

2

402

NP0-C0G

1000PF

5% 25V

C9566

1

2

CRITICAL

10UF

20%

6.3V

603

X5R

C9515

1

2

20%

B2-SM

2.0V

330UF

POLY-TANT

CRITICAL

C9510

1

2

8

74 82 87 88 91

91

1V0 GPU / 1V5 FB Power Supply

SYNC_MASTER=K91_CHANG

SYNC_DATE=07/21/2010

PP1V0_S0GPU_ISNS_R

PP5V_S0

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0GPU_P1V0P1V5_VCC

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

PP5V_S0GPU_VREF

P1V0GPU_VBST

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

P1V0GPU_DRVH

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V0GPU_DRVL

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD P1V5FB_EN

PVIN_S0GPU_P1V0

P1V5FB_TRIP

PP2V_S0GPU_P1V5_REF

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=2V

P1V5_GPU_VSNS

GPU_P1V5_REFIN

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

GATE_NODE=TRUE

P1V5FB_DRVL

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V5FB_VBST

GND_P1V0P1V5_SGND

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM VOLTAGE=0V

GPUFB_VID_L

FBVDD_ALTVO

P1V5FB_DRVH

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

P1V5FB_LL

DIDT=TRUE

MIN_NECK_WIDTH=0.2MM SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

P1V0GPU_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

P1V0GPU_VFB

P1V0S0_VSNS

PPVIN_S5_HS_GPU_ISNS

P1V0GPU_EN

P1V0GPU_TRIP

PP1V5_S0GPU_ISNS_R

95 OF 132 87 OF 105

7

103

6 7 8

22 41 47 52 54 65 68 69 70 73

104

105

7

50 82

7

103

IN

OUT

IN

OUT

IN IN

IN

OUT

D

SG

D

SG

IN

D

SG

D

SG

IN

IN IN

IN

PB14B PB15A PB15B PB16A

PB17A

PT19A

PT16A

PB18B

PT7A

PR11B

PR24A PR24B

PR14A PR14B

PR12B

PR12A

PR11A

PR10B

PR10A

PR6A PR6B PR7A PR7B PR8A

PR9A PR9B

PR8B

PT28A

PT8B

PT8A

PT7B

PT9A PT9B

PL25A PL25B

PL15A

PL14B

PL14A

PL12B

PL11B PL12A

PL9A

PL8A PL8B

PL6B

PL7B

PL7A

PL6A

PB28B

PB27A

PB28A

PB27B

PB26A

PB7B

PB7A

VCCIO2

PT17B

PT17A

PT16B

PT15A

PT14B

PT20B

PT19B

CFG0

GND

GNDIO0

GNDIO1

GNDIO2

GNDIO3

GNDIO4

GNDIO5

GNDIO6

GNDIO7

LRC_GNDPLL

LRC_VCCPLL

PB18A

PB19A PB19B PB20A PB20B

PL2A PL2B

PR2A PR2B

PT14A

PT15B

PT18B

PT20A

TCK TDI TDO TMS TOE

ULC_GNDPLL

ULC_VCCPLL

VCCAUX

VCCIO0

VCCIO1

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCJ

PT18A

VCC

PT28B

PB26B

PL11A

PL10B

PL10A

PL9B

PB16B

PL15B

PB14A

PB17B

BANK6

BANK2 BANK0

BANK5 BANK7BANK4

BANK3 BANK1

(OD)

IN

OUT

IN

BI BI

BI

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

GMUX CPLD

LVDS Receiver Termination

Required Pullups

Required Pulldowns

79 88 99

84

85

84 99

4.7UF

20%

4V

X5R 402

C9600

1

2

84 99

88

84 99

NO STUFF

1% MF

201

1/20W

10K

R9670

1

2

84 99

5%

100K

MF

1/20W

201

R9693

1 2

100K

NO STUFF

5% MF

1/20W

201

R9691

1 2

5%

10K

MF

1/20W

201

R9683

1 2

5%

10K

MF

1/20W

201

R9682

1 2

8

74 82 87 91

10K

5% MF

1/20W

201

R9681

1 2

5%

1K

MF

1/20W

201

R9680

1 2

10V

20%

402

CERM

0.1UF

C9630

1

2

20%

402

10V CERM

0.1UF

C9631

1

2

SIGNAL_MODEL=EMPTY

201

1/20W

MF

100

PLACE_NEAR=U9600.H12:5mm

1%

R9666

1 2

201

1/20W

MF

PLACE_NEAR=U9600.G13:5mm

100

1%

SIGNAL_MODEL=EMPTY

R9665

1 2

201

1/20W

MF

PLACE_NEAR=U9600.G14:5mm

100

1%

SIGNAL_MODEL=EMPTY

R9664

1 2

201

1/20W

MF

PLACE_NEAR=U9600.F12:5mm

100

1%

SIGNAL_MODEL=EMPTY

R9663

1 2

8

80

201

1/20W

MF

PLACE_NEAR=U9600.B2:5mm

100

1%

SIGNAL_MODEL=EMPTY

R9656

1 2

201

1/20W

MF

PLACE_NEAR=U9600.E14:5mm

100

1%

SIGNAL_MODEL=EMPTY

R9662

1 2

201

1/20W

MF1%

PLACE_NEAR=U9600.D13:5mm

100

SIGNAL_MODEL=EMPTY

R9661

1 2

201

1/20W

MF

PLACE_NEAR=U9600.J12:5mm

1%

100

SIGNAL_MODEL=EMPTY

R9660

1 2

201

1/20W

MF

PLACE_NEAR=U9600.G3:5mm

100

1%

SIGNAL_MODEL=EMPTY

R9655

1 2

201

1/20W

MF

100

PLACE_NEAR=U9600.E1:5mm

1%

SIGNAL_MODEL=EMPTY

R9651

1 2

201

1/20W

MF

100

PLACE_NEAR=U9600.E3:5mm

1%

SIGNAL_MODEL=EMPTY

R9652

1 2

201

1/20W

MF

PLACE_NEAR=U9600.G1:5mm

100

1%

SIGNAL_MODEL=EMPTY

R9653

1 2

201

1/20W

MF

PLACE_NEAR=U9600.G2:5mm

1%

100

SIGNAL_MODEL=EMPTY

R9654

1 2

201

1/20W

MF

PLACE_NEAR=U9600.H3:5mm

100

1%

SIGNAL_MODEL=EMPTY

R9650

1 2

NO STUFF

SILK_PART=GMUX_RST

10K

402

MF-LF

1/16W

1%

R9679

1

2

25

18 88 94

MF

1/20W 201

5%

4.7K

R9671

1

2

FERR-220-OHM

0402

L9621

1 2

FERR-220-OHM

0402

L9620

1 2

8

SSM6N15FEAPE

SOT563

Q9607

6

2

1

SSM6N15FEAPE

SOT563

Q9607

3

5

4

1/20W 201

MF

100K

5%

R9676

1

2

NO STUFF

MF-LF

1/16W 402

0

5%

R9675

1

2

18 88 94

201

1/20W

MF

5%

4.7K

R9678

1

2

23 45 73 91

CRITICAL

1909782

M-RT-SM

GMUX_JTAG_CONN

J9600

7

8

1 2 3 4 5 6

MF-LF

402

0

5%

1/16W

R9600

1 2

1/16W

5%

0

MF-LF

402

R9610

1 2

5%

1K

MF

1/20W

201

R9684

1 2

18 88 94

4.7K

MF

1/20W 201

5%

R9672

1

2

MF

1/20W 201

5%

4.7K

R9673

1

2

4.7K

5%

201

1/20W MF

R9674

1

2

SSM6N15FEAPE

SOT563

Q9605

6

2

1

SSM6N15FEAPE

SOT563

Q9605

3

5

4

2015%

10K

MF

1/20W

R9685

1 2

2015%

10K

MF

1/20W

R9686

1 2

18 88 94

1/16W

5%

MF-LF

402

1K

R9605

1 2

18 88 94

CSBGA

XP25-5

CRITICAL

OMIT

U9600

K1

J1B8C6

C12

C13

E13

M14

N10

N6P3M2C1E2

M11

P11

P4 N4 N3 M4 P5 M5 P6 M6 P7 M7 N7 N8 P9

N9 P10 M10 P12 P13 N12 P14

P2

N2

F3

G2

H2

G3

H1

H3

L1

L3

K3

L2

N1

P1

B1

B2

C2

D3

D1

E1

D2

E3

F1

G1

G12 G13 H13 H12 H14 J12 L14 M13 N14 N13

A14 B14 D12 D13 D14 E14 E12 F12 F14 G14

B6 C7 A6 A7 C8 C9 A8 B9 A9 C10 B10 A10 A11 B12 B13 A13

A2 A3 A1 B3 C5 A5

K14 L13 K13 L12

K2

B4

A4

B11C4J3

J13

N11P8C11J2J14M8B5B7A12

C14

F13

M12M9M3N5M1C3F2

K12

18 88 94

25

19

6

25 47 95

6

16 45 47 95

6

16 45 47 95

6

16 45 47 95

6

16 45 47 95

MF

1%

10K

NO STUFF

1/20W

201

R9647

1

2

6

16 45 47 95

83 88

80

8

16

88 91

87 88 91

82 88 91

72 88 91

8

74 88

84 88

84

0.1UF

20%

402

10V CERM

C9604

1

2

10V 402

CERM

20%

0.1UF

C9605

1

2

84 88

6

88 89

8

90

201

10K

NO STUFF

1/20W MF

1%

R9641

1

2

20%

402

10V

0.1UF

CERM

C9606

1

2

10V

0.1UF

20% CERM

402

C9607

1

2

10V

20%

402

CERM

0.1UF

C9608

1

2

CERM

10V

20%

0.1UF

402

C9609

1

2

0.1UF

20% 10V CERM 402

C9610

1

2

CERM

10V

20%

0.1UF

402

C9611

1

2

10V

20%

0.1UF

CERM 402

C9621

1

2

0.1UF

402

10V

20% CERM

C9622

1

2

10V

20%

0.1UF

402

CERM

C9612

1

2

20% 10V

402

0.1UF

CERM

C9613

1

2

10K

1%

1/20W

MF

201

NO STUFF

R9646

1

2

10V CERM

20%

402

0.1UF

C9623

1

2

CERM

0.1UF

10V 402

20%

C9624

1

2

402

10V CERM

20%

0.1UF

C9614

1

2

0.1UF

402

CERM

10V

20%

C9625

1

2

402

20% 10V

0.1UF

CERM

C9615

1

2

CERM 402

10V

20%

0.1UF

C9616

1

2

10V

20%

0.1UF

CERM 402

C9626

1

2

10V

0.1UF

402

CERM

20%

C9627

1

2

10V

20%

402

CERM

0.1UF

C9617

1

2

201

1/20W MF

1%

10K

R9640

1

2

10V

20%

0.1UF

402

CERM

C9628

1

2

CERM

0.1UF

20% 10V

402

C9629

1

2

79 80

8

18

79 80

8

18

79 88 99

201

10K

1/20W

MF

1%

R9645

1

2

79 88 99

SYNC_DATE=07/28/2010SYNC_MASTER=K92_YUAN

Graphics MUX (GMUX)

TP_GMUX_PL6B

GMUX_CFG0

LVDS_DDC_SEL_IG

LVDS_IG_A_DATA_P<1> LVDS_IG_A_DATA_N<1> LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2>

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_N<0>

GMUX_PL6A

LPC_FRAME_L

LPC_AD<0>

LCD_BKLT_EN

JTAG_GMUX_TDO

JTAG_ISP_TCK

EG_RESET_L

LCD_BKLT_PWM

LVDS_DDC_SEL_EG

DP_MUX_SEL_EG

JTAG_GMUX_TDI

JTAG_GMUX_TDO

GMUX_DEBUG_RESET_L

PP3V3_S0

EG_PWRSEQ_EN

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_N<2>

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.09 mm

PP3V3_S0_GMUX_ULC_VCCPLL

GMUX_DEBUG_RESET_L LVDS_A_CLK_P

LVDS_B_CLK_N

LVDS_A_DATA_P<1>

LVDS_A_DATA_P<2>

GND

LVDS_EG_A_DATA_N<1>

JTAG_ISP_TDO

JTAG_GMUX_TDI

GMUX_TOE

PP1V2_S0

PP3V3_S0

GMUX_INT

LVDS_IG_A_CLK_P

LVDS_IG_B_DATA_P<2>

LVDS_IG_A_DATA_N<0>

LVDS_B_DATA_N<1>

LVDS_A_DATA_N<2>

LVDS_A_DATA_N<1>

P1V0GPU_EN

LCD_PWR_EN

DP_A_CA_DET

P3V3GPU_EN

LVDS_B_CLK_P

EG_BKLT_EN

PP3V3_S3

GMUX_S3_PD_EN

LVDS_EG_A_CLK_P

LVDS_EG_A_DATA_N<0>

LVDS_EG_A_DATA_P<0>

DP_HOTPLUG_DET

LVDS_EG_B_DATA_P<2> LVDS_EG_B_DATA_N<2>

GMUX_S3_PD_GND

P1V5FB1V8GPU_R_EN

LVDS_IG_A_CLK_N

JTAG_GMUX_TMS

GPUVCORE_EN

P3V3GPU_EN

LVDS_EG_A_DATA_P<1>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_N<2>

LVDS_EG_A_DATA_N<2>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_CLK_P LVDS_IG_A_DATA_P<0> LVDS_IG_A_DATA_P<1>

LVDS_IG_B_DATA_P<0>

PEX_CLKREQ_L

LVDS_IG_BKL_ON

LVDS_EG_A_DATA_N<0>

PP3V3_S0

LVDS_B_DATA_N<2>

LVDS_B_DATA_P<0>

LVDS_B_DATA_P<1>

LVDS_IG_PANEL_PWR

LVDS_EG_B_DATA_N<1>

LVDS_EG_A_DATA_P<2>

JTAG_GMUX_TDO

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_P<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<1>

TP_GMUX_PL14B

LPC_AD<1>

TP_LVDS_MUX_SEL_EG

LVDS_EG_A_CLK_N

GMUX_VSYNC PM_ALL_GPU_PGOOD

LPC_AD<2> LPC_AD<3>

LPCPLUS_RESET_L LPC_CLK33M_GMUX

PP1V8_S0

LVDS_IG_B_DATA_N<2>

LVDS_A_DATA_N<0>

EG_RESET_L

LVDS_EG_B_DATA_P<1>

LVDS_A_DATA_P<0>

JTAG_ISP_TCK

JTAG_GMUX_TDI

GND GND

LCD_BKLT_PWM

LVDS_IG_A_DATA_P<0>

GND

LVDS_EG_B_DATA_N<0>

EG_LCD_PWR_EN

LVDS_EG_A_DATA_P<0> LVDS_EG_A_DATA_P<1>

LVDS_IG_A_CLK_N

LVDS_EG_B_DATA_N<1>

LVDS_EG_A_CLK_P

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<0>

LVDS_IG_A_DATA_N<2>

LVDS_IG_B_DATA_P<1>

JTAG_GMUX_TMS

LVDS_DDC_SEL_EG

LVDS_EG_B_DATA_P<0>

LVDS_EG_A_DATA_P<2>

LVDS_EG_B_DATA_N<0>

LVDS_EG_A_DATA_N<2>

GPUVCORE_EN

GMUX_RESET_L

PP3V3_S0

PEG_CLKREQ_L

LCD_PWR_EN

DP_CA_DET_EG

P1V5FB1V8GPU_R_EN

P1V0GPU_EN

DP_MUX_SEL_EG

DP_MUX_EN

LVDS_IG_A_DATA_N<0> LVDS_IG_A_DATA_N<1>

LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_N<1>

LVDS_B_DATA_N<0>

EG_PWRSEQ_EN

LVDS_DDC_SEL_IG

LVDS_A_CLK_N

LVDS_B_DATA_P<2>

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.09 mm

MIN_LINE_WIDTH=0.4 mm

PP3V3_S0_GMUX_LRC_VCCPLL

ALL_SYS_PWRGD

PP1V8_S0_GMUX_R

MIN_NECK_WIDTH=0.09 mm

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4 mm

PP3V3_T29

GMUX_VSYNC

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.09 mm

VOLTAGE=3.3V

PP3V3_S0_GMUX_R

T29_JTAG_FET

JTAG_GMUX_TDO

JTAG_ISP_TDI

PP3V3_S0

96 OF 132 88 OF 105

88

8

19 23 33 88

8

74 88

6

88 89

84 88

88

18 88 94

8

19 33

88

6 7

71

6 7

12

23 25 26

28 32 35

36 39 40

41 46 48

49 50 51

52 54 57

61 62 72

73 80 83

84 85 88

89 91

100 102

87 88 91

83 88

6 7 8

18

24 25 29 30 31 32 48 49 50 54 55 73

104

88 91

18 88

82 88 91

72 88 91

79 88 99

18 88 94

79 88 99

6 7

12 23 25

26 28 32 35

36 39 40 41

46 48 49 50

51 52 54 57

61 62 72 73

80 83 84 85

88 89 91

100

102

88

79 88 99

88

6 7

14

20 25 71

72

102

8

19 23 33 88

88

79 88 99

18 88 94

79 88 99

18 88 94

18 88

79 88 99

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72

73 80 83 84 85 88 89 91

100 102

18 88 94

79 88 99

84 88

7

16 19 25 33 34 35

88

8

19 33

6 7

12 23 25 26 28 32 35 36 39 40

41 46 48 49 50 51 52 54 57 61 62 72 73

80 83 84 85 88 89 91

100 102

IN

OUT1

FSET

GD

FILTER

ISET

PWM

EN

FAULT

THRM

GND_L

GND_SW

OUT6

VIN

VDDIO VLDO

FB

SW

OUT2

OUT4

OUT5

VSYNC

OUT3SCLK

SDA

GND_S

PAD

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

(APN: 353S3218)

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

(EEPROM should set EN_I_RES=1)

I_LED=25.1ma I_LED=369/Riset

PLACE XW9710 AWAY FROM U9701.1 AND U9701.15

* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

LCD_BKLT_PWM SHOULD BE KEPT AWAY FROM BOOST CIRCUIT

R9704 SHOULD BE 47K IF RC FILTER IS USED

*PPVOUT_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*L9710, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER.

C9715, C9716 SHOULD BE PLACED ON TOP SIDE. PLACE C9718,C9719 ON BOTTOM SIDE

C9715, C9716 SHOULD BE PLACED IN T-BONE. SAME FOR C9718,C9719

Fpwm=9.62KhZ details in spec

0.020 Ohm is place holder for 0.025 Ohm in 0612 package

6

88

MF-LF

100K

1/16W 402

1%

R9715

1 2

1/16W

402

14.7K

1%

MF-LF

R9714

1

2

MF-LF

1/16W

1%

90.9K

402

R9716

1

2

25V 805

X5R

10%

10UF

PLACE_NEAR=L9710.1:5MM

CRITICAL

C9712

1

2

0.01UF

402

CERM

16V

10%

PLACE_NEAR=U9701.22:3MM

C9714

1

2

10% 25V

PLACE_NEAR=L9710.1:3MM

X5R 402

0.1UF

C9713

1

2

PLACE_NEAR=U9701.22:5MM

25V X5R

1UF

603-1

10%

C9710

1

2

10%

402

16V

0.1UF

X5R

PLACE_NEAR=U9701.8:3MM

C9711

1

2

PLACE_NEAR=U9701.9:10MM

SM

XW9710

1 2

X5R 402

NO STUFF

25V

10%

0.1UF

C9723

1

2

10K

5% 1/16W

402

MF-LF

R9755

1

2

CRITICAL

LP8545SQX-EXTF

LLP1

U9701

4

7

21

20

5

6

15

9

1

3

12

13

14

16

17

18

2

10

11

24

25

82322

19

10.2

TF

402

0.1%

1/16W

PLACE_NEAR=U9701.18:10MM

R9722

1 2

6

83

10.2

TF

402

0.1%

1/16W

PLACE_NEAR=U9701.17:10MM

R9721

1 2

0.1%

10.2

TF

402

1/16W

PLACE_NEAR=U9701.16:10MM

R9720

1 2

10.2

TF

402

0.1%

1/16W

PLACE_NEAR=U9701.14:10MM

R9719

1 2

1/16W

0.1%

TF

402

10.2

PLACE_NEAR=U9701.13:10MM

R9718

1 2

1/16W

301K

MF-LF

402

1%

R9731

1 2

10.2

0.1%

402

TF

1/16W

PLACE_NEAR=U9701.12:10MM

R9717

1 2

6

83

6

83

6

83

6

83

6

83

DFLS260

PLACE_NEAR=D9710.2:3MM

CRITICAL

POWERDI-123

D9701

1 2

MF-LF

402

1/16W

5%

0

R9757

1 2

PWRPK-1212-8

CRITICAL

SI7308DN

Q9701

5

4

1 2 3

100 103

OMIT

0.020

1W

0.5%

CRITICAL

0612

MF-LF

R9700

1 2 3 4

33UH-1.8A-110MOHM

1217AS-2SM

CRITICAL

L9710

1 2

CRITICAL

1210

2.2UF

PLACE_NEAR=D9701.2:3MM

X7R-CERM

100V

10%

C9715

1

2

MF-LF

402

1/16W

0

5%

R9753

1 2

10%

1210

CRITICAL

X7R-CERM

100V

2.2UF

PLACE_NEAR=D9701.2:5MM

C9716

1

2

10%

2.2UF

CRITICAL

PLACE_NEAR=D9701.2:3MM

1210

X7R-CERM

100V

C9718

1

2

X7R-CERM

CRITICAL

1210

PLACE_NEAR=D9701.2:5MM

100V

10%

2.2UF

C9719

1

2

X7R 603

PLACE_NEAR=R9708.1:5MM

10% 100V

1000PF

C9717

1

2

1%

402

MF-LF

63.4K

1/16W

R9708

1

2

1%

402

MF-LF

1/16W

59.0K

R9709

1

2

10K

1/16W MF-LF

5%

402

R9765

1

2

NO STUFF

402

CERM

50V

5%

33PF

C9704

1

2

5% 1/16W MF-LF

402

0

R9704

1 2

0.025OHM,1W,0612,MTL FILM RES

107S0196 CRITICAL

R9700

1

SYNC_DATE=09/07/2010

LCD Backlight Driver (LP8545)

SYNC_MASTER=K92_DINESH

BKL_VSYNC_R

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN1

SMBUS_PCH_CLK

LED_RETURN_1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_FET_CNTL

MIN_NECK_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.6 MM

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_3

BKL_SW

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=50V

PPVOUT_S0_LCDBKLT

BKL_VLDO

PPBUS_S0_LCDBKLT_PWR

SMBUS_PCH_DATA

BKL_ISEN3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LCD_BKLT_PWM

PPBUS_S0_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=0.5 MM

SWITCH_NODE=TRUE

VOLTAGE=50V

MIN_NECK_WIDTH=0.375 MM

ISNS_LCDBKLT_P

PPBUS_S0_LCDBKLT_PWR

PP3V3_S0

VOLTAGE=8.4V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPVIN_BKL

ISNS_LCDBKLT_N

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN4

BKL_ISEN2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_FB

LVDS_BKL_PWM_RC

TP_BKL_FAULT

BKLT_EN

BKL_ISET

BKL_SDA

BKL_SCL

BKL_ISEN6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN5

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

BKL_SGND

BKL_FLT

BKL_FSET

97 OF 132 89 OF 105

6

16 23 26 28 30 32 41

48 62 95

6

83

103

89 90

6

16 23 26 28 30 32 41

48 62 95

89 90

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 91

100 102

D

SG

D

SG

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

FDC638APZ

43 mOhm @4.5V

0.4 A (EDP)

P-TYPE

PPBUS S0 LCDBkLT FET

MOSFET

RDS(ON)

LOADING

CHANNEL

CRITICAL

603-HF

3AMP-32V-467

F9800

1 2

301K

1%

MF-LF

1/16W

402

R9808

1

2

1%

147K

1/16W MF-LF 402

R9809

1

2

16V X5R 402-1

0.1UF

10%

C9802

1

2

CRITICAL

FDC638APZ_SBMS001

SSOT6-HF

Q9806

1 2 5 6

3

4

SOT563

SSM6N15FEAPE

Q9807

6

2

1

SSM6N15FEAPE

SOT563

Q9807

3

5

4

8

88

25

MF-LF

4.7K

5% 1/16W

402

R9840

1

2

SYNC_DATE=04/26/2010

SYNC_MASTER=K17_MLB

LCD Backlight Support

LCD_BKLT_EN

PPBUS_G3H

BKLT_PLT_RST_L

PBUS_S0_LCDBKLT_EN_DIV

BKLT_EN_L

PBUS_S0_LCDBKLT_EN_L

VOLTAGE=10V

PPBUS_S0_LCDBKLT_PWR

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

VOLTAGE=10V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_S0_LCDBKLT_FUSED

98 OF 132 90 OF 105

6 7 8

35 39 49 50 63 64

89

IN

OUT

IN

OUT

IN

Y

A

B

08

Y

A

B

08

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Unused PGOOD signal

up in the following order:

1) GPU_3.3V

2) GPUVcore

3) GPU_1.0V

4) GPU_1.8V;GDDR5 1.5/1.35V

EXT GPU PWRGD Pullup

PCH S0 PWRGD

Whistler GPU requires rails to come

GPU Rail Sequencing

402

1/16W MF-LF

5%

1K

R9950

1

2

23 45 73 88

68

5%

402

MF-LF

1/16W

0

PLACE_NEAR=U9500.27:7mm

R9931

1 2

10%

402

6.3V CERM-X5R

0.47UF

NO STUFF

C9931

1

2

0.47UF

402

CERM-X5R

10%

6.3V

NO STUFF

C9932

1

2

0

5% 1/16W MF-LF

402

PLACE_NEAR=U7880.2:7mm

R9932

1 2

8

74 82 87 88 91

68

67 91

402

MF-LF

1/16W

5%

100K

PLACE_NEAR=U8000.AH16:7mm

R9990

1

2

8

74 82 87 88 91

8

74 82 87 88 91

8

74 82 87 88 91

87 91

87 88 91

82 88 91

72 88 91

72 91

PLACE_NEAR=U1800.p12:7mm

74LVC2G08GT

SOT833

U9950

1

2

4

8

7

74LVC2G08GT

SOT833

U9950

5

6

4

8

3

72 91

1/16W MF-LF

5%

402

NO STUFF

10K

R9991

1

2

MF-LF

0

NO STUFF

5%

1/16W

402

R9963

1 2

17 23

17 91

NO STUFF

MF-LF

1/16W

PLACE_NEAR=U1800.L22:5.54mm

402

5%

0

R9961

1

2

1K

1/16W MF-LF

5%

402

R9962

1 2

0

402

MF-LF

1/16W

5%

R9960

1 2

402

10V CERM

20%

0.1UF

C9950

1

2

Power Sequencing EG/PCH S0

SYNC_DATE=07/30/2010SYNC_MASTER=K92_YUAN

CPUIMVP_AXG_PGOOD

PP3V3_S0

TP_P1V5S3RS0_RAMP_DONE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

GPUVCORE_EN

P1V8GPU_EN

MAKE_BASE=TRUE

P1V8GPU_EN

GPUVCORE_EN

P1V0GPU_EN

MAKE_BASE=TRUE

P1V5FB_EN

P3V3GPU_EN

MAKE_BASE=TRUE

P1V5FB1V8GPU_R_EN

P3V3GPU_EN

P1V0GPU_EN

MAKE_BASE=TRUE

PM_PCH_PWROK

PM_S0_PGOOD

SMC_DELAYED_PWRGD

PM_PCH_PWROK

SYS_PWROK_R

ALL_SYS_PWRGD

PP3V3_S0

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD PM_ALL_GPU_PGOOD

CPUIMVP_PGOOD

PM_PCH_SYS_PWROK

PP3V3_S5 PP3V3_S0

P3V3GPU_EN

GPUVCORE_EN

P1V5FB1V8GPU_R_EN

P1V5FB_EN

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

99 OF 132 91 OF 105

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

67 91

82 88 91

72 91

87 88 91

72 88 91

88 91

87 88 91

35 45

17 91

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

6 7

17 19 20 22 23 24 25 29 46 48 56 71

72 73 83 86

100 102 104

6 7

12 23 25 26 28 32 35 36 39 40 41 46

48 49 50 51 52 54 57 61 62 72 73 80 83

84 85 88 89 91

100 102

72 88 91

82 88 91

88 91

87 91

72 91

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

SOURCE: Calpella SFF DG (DG-407364_v1.5), Section 2.8

PCI-Express

CPU Signal Constraints

NET_TYPE

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

(FSB_CPURST_L)

Some signals require 27.4-ohm single-ended impedance.

Most CPU signals with impedance requirements are 50-ohm single-ended.

CPU Net Properties

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

I115

I120

I121

I122 I123

I124

I125 I126

SYNC_DATE=07/22/2010

SYNC_MASTER=K91_MLB

CPU Constraints

=27P4_OHM_SE

CPU_27P4S

*

7 MIL

=27P4_OHM_SE =27P4_OHM_SE

7 MIL

*

?

CPU_COMP

20 MIL

CPU_ITP

*

?

=2:1_SPACING

?

CPU_AGTL

TOP,BOTTOM

=2x_DIELECTRIC

?

*

CPU_VID

0.457 MM

CPU_VCCSENSE

*

?

25 MIL

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF*

PCIE_85D

=85_OHM_DIFF=85_OHM_DIFF

CLK_PCIE

20 MIL

?

*

=50_OHM_SE=50_OHM_SE

=STANDARD=STANDARD*

=50_OHM_SE =50_OHM_SE

CPU_50S

=55_OHM_SE=55_OHM_SE

*

CPU_55S

=55_OHM_SE =55_OHM_SE

=STANDARD=STANDARD

=3X_DIELECTRIC

PCIE

?

*

PCIE

?

=4X_DIELECTRIC

TOP,BOTTOM

CPU_8MIL

*

?

8 MIL

CPU_AGTL

*

=STANDARD

?

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF*

CLK_PCIE_90D =90_OHM_DIFF

XDP_CPU_TCK

XDP_TCK CPU_50S CPU_ITP

XDP_BPM

XDP_BPM_L<3..0>

CPU_50S CPU_ITP

XDP_CPU_CLK100M_P

CLK_PCIECLK_PCIE_90D

XDP_CLK_ITP

CLK_PCIE_90D CLK_PCIE

XDP_CPU_CLK100M_N

XDP_CLK_ITP

CPU_PSI_L

CPU_8MIL

CPU_55S

PM_DPRSLPVR

CPU_AGTL

CPU_50S

CPU_PEG_COMP

CPU_27P4S

CPU_COMP

ITPCPU_CLK100M_N

CLK_PCIE_90D

XDP_CLK_CPU

CLK_PCIE

CLK_PCIE_90D

XDP_CLK_PCH

ITPXDP_CLK100M_P

CLK_PCIE

CLK_PCIE_90D

ITPXDP_CLK100M_N

CLK_PCIE

XDP_CLK_PCH

XDP_CPU_TDI

CPU_50SXDP_TDI CPU_ITP

CPU_VCCSENSE CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE_N

CPU_AXG_SENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_AXG_SENSE_N

CPU_27P4S

CPU_VCCSENSE

CPU_AXG_VALSENSE_P

GFX_DPRSLPVR

CPU_AGTL

CPU_50S

PM_DPRSLPVR

CPU_AGTL

GFX_VR_EN

CPU_50S

CPU_55S

GFX_VID<6..0>

CPU_8MIL

CPU_VCCSENSE

CPU_27P4S

CPU_VCC_VALSENSE_N

CPU_27P4S

CPU_VCCSENSE

CPU_VCC_VALSENSE_P

XDP_CPU_TRST_L

XDP_TRST_L

CPU_50S CPU_ITP

XDP_CPU_TDO

CPU_50SXDP_TDO CPU_ITP

CPU_COMP1

CPU_27P4S

CPU_COMP CPU_COMP

ITPCPU_CLK100M_P

CLK_PCIE_90D

XDP_CLK_CPU

CLK_PCIE

CPU_8MIL

PM_THRMTRIP_L

CPU_50S

PM_THRMTRIP_L

CPU_PWRGD

CPU_AGTL

CPU_PWRGD

CPU_50S

CPU_AGTL

CPU_PROCHOT_L

CPU_CATERR_L

CPU_50S

CPU_CATERR_L CPU_AGTL

DMI_CLK100M_CPU_N

CLK_PCIE_90D CLK_PCIE

PCIE_85DFDI_DATA PCIE

FDI_DATA_P<7:0>

DMI_CLK100M

CLK_PCIE_90D CLK_PCIE

DMI_CLK100M_CPU_P

CPU_50S

XDP_CPU_PRDY_L

XDP_PRDY_L

CPU_ITP

CPU_50S

XDP_CPU_PREQ_L

XDP_PREQ_l

CPU_ITP

XDP_DBRESET_L

CPU_ITP

XDP_BDRESET_L

CPU_50S

CPU_ITP

XDP_CPU_PWRGOOD

XDP_CPU_PWRGD

CPU_50S

PM_MEM_PWRGD

CPU_AGTLPM_MEM_PWRGD

CPU_50S

PM_SYNC

CPU_AGTL

CPU_50S

CPU_PECI

PCIECPU_PECI

CPU_50S

CPU_AGTL

FDI_INT

CPU_AGTL

CPU_50S

TP_CPU_VTT_SELECT

CPU_AGTL

CPU_50S

CPU_PROC_SEL_L

DMI_N2S

PCIE_85D PCIE

DMI_N2S_N<3:0>

XDP_BPM_L<7..4>

XDP_BPM_L

CPU_ITPCPU_50S

XDP_CPURST_L

CPU_ITPCPU_50S

CPU_VID<6..0>

CPU_8MIL

CPU_55S

CPU_COMP0

CPU_27P4S

CPU_COMP CPU_COMP

CPU_CFG<11..0>

CPU_50S CPU_ITPCPU_CFG

CPU_SM_RCOMP2

CPU_COMPCPU_SM_RCOMP

CPU_27P4S

XDP_CPU_TMS

CPU_50SXDP_TMS CPU_ITP

FDI_LSYNC<1..0>

CPU_AGTL

CPU_50S

FDI_FSYNC<1..0>

CPU_AGTL

CPU_50S

PCIE_85D

DMI_N2S

PCIE

DMI_N2S_P<3:0>

FDI_DATA PCIE_85D

FDI_DATA_N<7:0>

PCIE

DMI_S2N

DMI_S2N_N<3:0>

PCIEPCIE_85D

DMI_S2N

PCIE_85D PCIE

DMI_S2N_P<3:0>

CPUIMVP_IMON

CPU_AGTL

CPU_50S

GFXIMVP_IMON

CPU_AGTL

CPU_50S

PEG_R2D_P<7..0>

PCIEPCIE_85D

PEG_R2D_N<7..0>

PCIEPCIE_85D

PEG_R2D_C_P<7..0>

PCIE

PEG_R2D

PCIE_85D

PEG_D2R

PEG_D2R_P<7..0>

PCIE_85D PCIE

PEG_R2D_C_N<7..0>

PCIE_85D PCIE

PEG_D2R_N<7..0>

PCIE_85D PCIE

PEG_D2R_C_P<7..0>

PCIE_85D PCIE

PCIEPCIE_85D

PEG_D2R_C_N<7..0>

CPU_50S

CPU_VIDSOUT

CPU_VID

CPU_50S CPU_VID

CPU_VIDSCLK

CPU_50S

CPU_VIDALERT_L

CPU_VID

CPU_PEG_RBIAS

CPU_COMP

CPU_27P4S

CPU_COMPCPU_COMP

CPU_27P4S

CPU_COMP3

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCIOSENSE_P

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE CPU_VCCSENSE

CPU_27P4S

CPU_VCCIOSENSE_N

CPU_AXG_VALSENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_COMP

CPU_COMP2

CPU_COMP

CPU_SM_RCOMP

CPU_SM_RCOMP1

CPU_COMP

CPU_27P4S

CPU_SM_RCOMP0

CPU_27P4S

CPU_SM_RCOMP CPU_COMP

CPU_CFG<17..16>

CPU_50S CPU_ITPCPU_CFG

100 OF 132

92 OF 105

10 23

23

9

10 16

16 23

10 23

12 68

12

8

12

10 23

10 16

10 19

10 19 23

10 46 68

10

10 16

9

17

10 16

10 23

10 23 25

23

10 17 29

10 17

10 19 45

9

17

8

10 17

6 9

17

10 23

23

8

9

23

10 23

9

17

9

17

6 9

17

9

17

6 9

17

6 9

17

74

8

74

8

74

8

74

8

74

12 68

12 70

12

9

23

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

A/BA/CMD signals should be matched within [CLK-12.7mm] to [CLK+12.7mm] of CLK pairs.

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

DDR3:

DQ/DM signals should be matched within 0.508mm of associated DQS pair.

CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.

Memory Bus Spacing Group Assignments

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.

CONTROL signals should be matched within [CLK-12.7mm] to [CLK+0.0mm] of CLK pairs.

DQS to clock matching should be within [CLK-12.7mm] and [CLK+25.4mm].

DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.

SOURCE: Calpella SFF Platform DG, Rev 1.5 (#407364), Section 2.2

Need to support MEM_*-style wildcards!

Maximum length of any signal from die pad to SODIMM pad is 139.7mm, from procesor ball to SODIMM pad is 114.3mm.

Memory Bus Constraints

PHYSICAL

SPACING

NET_TYPE

MEM_50S

=50_OHM_SE=50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE

*

?

MEM_CLK2MEM

=4:1_SPACING

=2.5:1_SPACING

MEM_CTRL2MEM

?

*

MEM_CTRL2CTRL

=3:1_SPACING

*

?

MEM_CMD2MEM

MEM_CLK

*

MEM_CMD MEM_CMD

MEM_CTRL

MEM_CMD2MEM

*

MEM_CMD

MEM_CMD2CMD

MEM_CMD

*

MEM_CMD

MEM_DATA

MEM_CMD2MEM

*

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

*

MEM_CLK

MEM_DATA

MEM_DATA2MEM MEM_DATA2MEM

MEM_CTRL

*

MEM_DATA

MEM_DATA2MEM

MEM_CMD

*

MEM_DATA

* *

MEM_CLK

MEM_2OTHER

MEM_CTRL

**

MEM_2OTHER

* *

MEM_DQS

MEM_2OTHER

MEM_DATA

**

MEM_2OTHER

* *

MEM_CMD

MEM_2OTHER

?

=1.5:1_SPACING

*

MEM_CMD2CMD

=3:1_SPACING

MEM_DQS2MEM

*

?

MEM_CLK

*

MEM_CLK

MEM_CLK2MEM

MEM_CTRL

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

*

MEM_CLK

MEM_CLK2MEM

MEM_DATA

MEM_CLK

*

MEM_CMD

*

MEM_CLK

MEM_CLK2MEM

MEM_CTRL2MEM

MEM_CLK

*

MEM_CTRL

MEM_CMD

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DQS

*

MEM_CTRL

*

MEM_DQS

MEM_DQS2MEM

MEM_CLK

*

MEM_DQS2MEM

MEM_CMDMEM_DQS

MEM_DQS

*

MEM_DQS

MEM_DQS2MEM

MEM_DQS

*

MEM_DATA

MEM_DQS2MEM

25 MILS

*

MEM_2OTHER

?

=3:1_SPACING

?

*

MEM_DATA2MEM

=1.5:1_SPACING

*

?

MEM_DATA2DATA

MEM_CMD2MEM

=3:1_SPACING

?

*

MEM_72D

=72_OHM_DIFF=72_OHM_DIFF

=72_OHM_DIFF=72_OHM_DIFF=72_OHM_DIFF

=72_OHM_DIFF*

* =STANDARD =STANDARD

MEM_37S

=37_OHM_SE =37_OHM_SE=37_OHM_SE=37_OHM_SE

MEM_40S

=STANDARD* =STANDARD

=40_OHM_SE =40_OHM_SE=40_OHM_SE =40_OHM_SE

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

=85_OHM_DIFF*

=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

MEM_DQS

*

MEM_DATA

MEM_DATA2MEM

MEM_DATA

*

MEM_DATA2DATA

MEM_DATA

MEM_CTRLMEM_CTRL

*

MEM_CTRL2CTRL

MEM_DATAMEM_CTRL

*

MEM_CTRL2MEM

*

MEM_CTRL

MEM_DQS

MEM_DQS2MEM

SYNC_DATE=05/14/2010

SYNC_MASTER=K17_MLB

Memory Constraints

MEM_A_RAS_L

MEM_CMDMEM_40S

MEM_A_CMD

MEM_40S MEM_CMD

MEM_A_WE_L

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_50SMEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_DATA

MEM_A_BA<2..0>

MEM_A_CMD

MEM_CMDMEM_40S

MEM_CMD

MEM_A_CMD

MEM_A_CAS_L

MEM_40S

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_A_CNTL

MEM_A_CS_L<3..0>

MEM_37S

MEM_CTRL

MEM_A_CNTL

MEM_CTRL

MEM_A_ODT<3..0>

MEM_37S

MEM_A_CMD

MEM_A_A<15..0>

MEM_CMDMEM_40S

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_CLK

MEM_B_CLK_N<5..0>

MEM_72D

MEM_B_CLK

MEM_B_CKE<3..0>

MEM_CTRL

MEM_37S

MEM_B_CNTL

MEM_B_ODT<3..0>

MEM_B_CNTL

MEM_CTRL

MEM_37S

MEM_B_CMD

MEM_B_BA<2..0>

MEM_40S MEM_CMD

MEM_B_CMD

MEM_B_CAS_L

MEM_CMDMEM_40S

MEM_50SMEM_B_DQ_BYTE5

MEM_DATA

MEM_B_DQ<47..40>

MEM_B_CS_L<3..0>

MEM_B_CNTL

MEM_CTRL

MEM_37S

MEM_B_CMD

MEM_CMD

MEM_B_A<15..0>

MEM_40S

MEM_85D

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_DQS

MEM_85D

MEM_B_DQS_N<7>

MEM_B_DQS7

MEM_DQS

MEM_B_CMD

MEM_B_RAS_L

MEM_CMDMEM_40S

MEM_A_CLK_P<5..0>

MEM_A_CLK

MEM_CLKMEM_72D

MEM_A_CLK_N<5..0>

MEM_A_CLK

MEM_CLKMEM_72D

MEM_85D

MEM_A_DQS1

MEM_A_DQS_N<1>

MEM_DQS

MEM_50SMEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_DATA

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_A_DQ<39..32>

MEM_50SMEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_DATA

MEM_85D

MEM_B_DQS_N<6>

MEM_DQS

MEM_B_DQS6

MEM_85D

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_DQS

MEM_85D

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_DQS

MEM_85D

MEM_B_DQS_P<5>

MEM_DQS

MEM_B_DQS5

MEM_85D

MEM_B_DQS4

MEM_B_DQS_N<4>

MEM_DQS

MEM_85D

MEM_B_DQS_N<5>

MEM_DQS

MEM_B_DQS5

MEM_50SMEM_A_DQ_BYTE3

MEM_DATA

MEM_A_DQ<31..24>

MEM_50S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_A_DQ<47..40>

MEM_85D

MEM_A_DQS0

MEM_DQS

MEM_A_DQS_P<0>

MEM_85D

MEM_A_DQS0

MEM_A_DQS_N<0>

MEM_DQS

MEM_85D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQS

MEM_85D

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_DQS

MEM_85D

MEM_A_DQS4

MEM_A_DQS_N<4>

MEM_DQS

MEM_85D

MEM_A_DQS_P<2>

MEM_DQS

MEM_A_DQS2

MEM_85D

MEM_A_DQS2

MEM_A_DQS_N<2>

MEM_DQS

MEM_85D

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_DQS

MEM_85D

MEM_A_DQS3

MEM_A_DQS_N<3>

MEM_DQS

MEM_85D

MEM_A_DQS_P<5>

MEM_DQS

MEM_A_DQS5

MEM_85D

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_DQS

MEM_B_CMD

MEM_B_WE_L

MEM_CMDMEM_40S

MEM_50SMEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_DATA

MEM_50SMEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_DATA

MEM_50SMEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_DATA

MEM_50SMEM_B_DQ_BYTE3

MEM_DATA

MEM_B_DQ<31..24>

MEM_50SMEM_B_DQ_BYTE4

MEM_B_DQ<39..32>

MEM_DATA

MEM_50SMEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_DATA

MEM_85D

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_DQS

MEM_85D

MEM_B_DQS0

MEM_B_DQS_N<0>

MEM_DQS

MEM_85D

MEM_B_DQS1

MEM_B_DQS_N<1>

MEM_DQS

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_DQSMEM_85D

MEM_85D

MEM_B_DQS2

MEM_B_DQS_N<2>

MEM_DQS

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_DQSMEM_85D

MEM_85D

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_DQS

MEM_85D

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_DQS

MEM_A_CNTL

MEM_A_CKE<3..0>

MEM_CTRL

MEM_37S

MEM_B_CLK_P<5..0>

MEM_CLKMEM_72D

MEM_B_CLK

MEM_85D

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_DQS

MEM_85D

MEM_A_DQS6

MEM_A_DQS_N<6>

MEM_DQS

MEM_85D

MEM_A_DQS5

MEM_A_DQS_N<5>

MEM_DQS

MEM_85D

MEM_A_DQS_P<6>

MEM_DQS

MEM_A_DQS6

101 OF 132

93 OF 105

11 26

11 27

11 26

11 27

11 26

11 27

11 28

11 27

11 28

11 27

11 28

11 26

11 27

11 26 27

11 27

11 26 27

11 27

11 28

11 27

11 27 28

11 27

11 27 28

11 27

11 26

11 28

11 27

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

PCH Net Properties

NET_TYPE

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

SATA Interface Constraints

USB 2.0 Interface Constraints

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

SPACING

Digital Video Signal Constraints

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

TOP,BOTTOM

=5:1_SPACING

?

SATA

=50_OHM_SE

*

SATA_50SE

=50_OHM_SE=50_OHM_SE

SYNC_DATE=06/25/2010

SYNC_MASTER=K92_YUN

PCH Constraints 1

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF*

DP_85D

=90_OHM_DIFF

=90_OHM_DIFF* =90_OHM_DIFF

=90_OHM_DIFF

LVDS_85D

=90_OHM_DIFF =90_OHM_DIFF

DISPLAYPORT

TOP,BOTTOM?=4:1_SPACING TOP,BOTTOM

=4:1_SPACING

?

LVDS

=4:1_SPACING

?

LVDS

ISL3,ISL4,ISL9,ISL10

USB_RBIAS

*

?

15 MIL

ISL3,ISL4,ISL9,ISL10

USB

?

=4:1_SPACING

=85_OHM_DIFF

*

USB_85D

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

=STANDARD=STANDARD

PCH_USB_RBIAS

=STANDARD

=STANDARD=STANDARD

=STANDARD

*

=5:1_SPACING

ISL3,ISL4,ISL9,ISL10

SATA

?

TOP,BOTTOM

USB

=4:1_SPACING

SATA_ICOMP

?

*

15 MIL

=37_OHM_SE

SATA_37SE

*

=37_OHM_SE=37_OHM_SE

=90_OHM_DIFF=90_OHM_DIFF*

=90_OHM_DIFF

SATA_90D

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

?

=4:1_SPACING

DISPLAYPORT

ISL3,ISL4,ISL9,ISL10

SATA_HDD_R2D_C_P

SATA_90D SATA

DP_SATA_G3_R2D

SATA_HDD_R2D_C_N

SATASATA_90D

SATA_HDD_R2D_RDRVR_OUT_N

SATASATA_90D

SATA_HDD_R2D_RDRVR_IN_N

SATASATA_90D

SATA_ODD_R2D_N

SATA_90D SATA

SATA_HDD_D2R_C_P

SATA_90D SATA

SATA_HDD_RDVR_D2R

SATA_HDD_D2R_RDRVR_IN_N

SATASATA_90D

USB

USB_85D

USB_HUB1_UP_N

USB_85D

USB

USB_BT_N

SATA

SATA_HDD_R2D_UF_P

SATA_90D

DP_SATA_G3_R2D

SATA_HDD_D2R

SATA_HDD_D2R_P

SATA_90D SATA

SATA_HDD_D2R_N

SATA_90D SATA

SATA_HDD_D2R_RDRVR_OUT_P

SATA_HDD_D2R SATASATA_90D

SATA_HDD_D2R_RDRVR_OUT_N

SATA_90D SATA

SATA_HDD_R2D_RC_UF_P

SATASATA_90D

DP_SATA_G3_R2D

SATA_HDD_R2D_RC_UF_N

SATASATA_90D

SATA_HDD_R2D_RDRVR_IN_P

SATASATA_90D

DP_SATA_G3_R2D

SATA_90D SATA

SATA_ODD_R2D_P

SATA_HDD_D2R

SATA_HDD_D2R_RDRVR_IN_P

SATA_90D SATA

SATA_HDD_D2R_C_N

SATASATA_90D

SATA_ODD_R2D_C_P

SATASATA_90DSATA_ODD_R2D

SATA_ODD_R2D_C_N

SATASATA_90D

SATA_ODD_R2D_UF_P

SATA_ODD_R2D

SATASATA_90D

SATA_ODD_R2D_UF_N

SATA_90D SATA

SATA_ODD_D2R_P

SATA_ODD_D2R

SATA_90D

SATA_ODD_D2R_N

SATA

SATA_90D SATA

SATA_ODD_D2R_C_P

SATA_ODD_D2R

SATA_90D

SATA_ODD_D2R_C_N

SATA

SATA_90D SATASATA_ODD_D2R

SATA_ODD_D2R_UF_P

SATASATA_90D

SATA_ODD_D2R_UF_N

SATA_ICOMP

SATA_50SE

PCH_SATA3_ICOMP

PCH_SATA3COMP

SATA_ICOMP

PCH_SATA_ICOMP

SATA_37SE

PCH_SATAICOMP

USB_HUB2_UP

USB

USB_HUB2_UP_P

USB_85D

SATA_90D

SATA_HDD_R2D_N

SATA

SATA_90D SATA

SATA_HDD_R2D_UF_N

SATA_90D SATA

SATA_HDD_R2D_RDRVR_OUT_P

DP_SATA_G3_R2D

USB

USB_T29A_N

USB_85D

USB

USB_T29A_P

USB_85D

USB_T29A

USB

USB_85D

USB_IR_N

PCH_USB_RBIASPCH_USB_RBIAS

USB_RBIAS

PCH_USB_RBIAS

USB_IR

USB_85D

USB

USB_IR_P

USB

USB_TPAD_N

USB_85D

USB_TPAD

USB_TPAD_P

USB

USB_BT

USB_85D

USB_BT_P

USB

USB_CAMERA_CONN_N

USB_85D

USB

USB_CAMERA_CONN_P

USB

USB_85D

USB_CAMERA

USB_EXTC_N

USB

USB_85D

USB_EXTC

USB_EXTC_P

USB

USB_85D

USB

USB_EXTB_N

USB_85D

USB_EXTB

USB_85D

USB

USB_EXTB_P

USB_85D

USB

USB_EXTA_N

USB_EXTA_P

USB

USB_85D

USB_EXTA

USB_HUB2_UP_N

USB_85D

USB

USB_HUB1_UP

USB_HUB1_UP_P

USB_85D

USB

DP_IG_AUX_CH_N

DISPLAYPORT

DP_AUX_CH

DP_85D

SATA_90D SATA

SATA_HDD_R2D_P

SATA_HDD_RDVR_R2D

LVDS_IG_B_DATA

LVDS_IG_B_DATA_N<2..0>

LVDSLVDS_85D

LVDS_IG_A_DATA_P<2..0>

LVDSLVDS_85D

LVDS_IG_A_DATA

LVDS_IG_A_DATA_N<2..0>

LVDSLVDS_85D

LVDS_IG_A_DATA

LVDS

NC_LVDS_IG_A_DATAN<3>

LVDS_85D

LVDS_IG_A_DATA3

LVDS_IG_B_DATA_P<2..0>

LVDS

LVDS_IG_B_DATA

LVDS_85D

LVDS_85D LVDS

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_DATA3

DP_IG_AUX_CH_P

DISPLAYPORT

DP_AUX_CH

DP_85D

LVDS_IG_A_CLK_P

LVDS_IG_A_CLK

LVDSLVDS_85D

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK

LVDSLVDS_85D

102 OF 132

94 OF 105

6

16 41

6

16 41

6

41

6

41

6

41

6

41

6

41

18 24

6

24 31

6

41

6

16 41

6

16 41

6

41

6

41

6

41

6

41

6

41

6

41

6

41

6

41

16 41

41

16 41

41

6

41

6

41

16

18 24

6

41

6

41

6

41

8

24

8

24

24 44

18

24 44

24 53

6

24 31

6

31

6

31

24 43

24 42

18 24

8

17 84

6

41

18 88

8

18

18 88

8

18

8

17 84

18 88

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

SIO Signal Constraints

SMBus Interface Constraints

NET_TYPE

SPACING

PHYSICAL

SPI Interface Constraints

HD Audio Interface Constraints

LPC Bus Constraints

I253

I254

I255

I256

I257

I258

I259

I260

I261

I262

I263 I264

I265

I266

I267

I268

I269

I270

6 MIL

LPC

?

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE

CLK_LPC_50S

=STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD*

=55_OHM_SE

CLK_SLOW_55S

?

=2x_DIELECTRIC

SMB

*

HDA

=2x_DIELECTRIC

?

8 MIL

*

CLK_SLOW

?

=STANDARD=STANDARD*

=55_OHM_SE

SPI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=50_OHM_SE

* =STANDARD =STANDARD

SMB_50S

=50_OHM_SE=50_OHM_SE =50_OHM_SE

8 MIL

?

SPI

*

=STANDARD*

=50_OHM_SE

HDA_50S

=STANDARD

=50_OHM_SE=50_OHM_SE=50_OHM_SE

*

?

CLK_LPC

8 MIL

=50_OHM_SE

*

=50_OHM_SE

=STANDARD

=50_OHM_SE =50_OHM_SE

LPC_50S

=STANDARD

PCH Constraints 2

SYNC_MASTER=K91_MLB

SYNC_DATE=07/22/2010

PCIE_ENET_R2D

PCIE_85D PCIE

PCIE_ENET_R2D_N

PCIE_AP_D2R

PCIEPCIE_85D

PCIE_AP_D2R_N

PCIE_AP_D2R

PCIEPCIE_85D

PCIE_AP_D2R_PI_P

PCIE_AP_D2R

PCIE_85D PCIE

PCIE_AP_D2R_PI_N

PCIE_AP_D2R

PCIEPCIE_85D

PCIE_AP_D2R_P

PCIE_AP_R2D

PCIE_85D PCIE

PCIE_AP_R2D_C_N

PCIE_ENET_R2D

PCIEPCIE_85D

PCIE_ENET_R2D_P

PCIE_ENET_R2D

PCIEPCIE_85D

PCIE_ENET_R2D_C_P

PCIE_AP_R2D

PCIE_85D PCIE

PCIE_AP_R2D_PI_P

PCIE_AP_R2D

PCIE_85D PCIE

PCIE_AP_R2D_PI_N

PCIE_AP_R2D

PCIE_85D PCIE

PCIE_AP_R2D_C_P

PCIE_FW_D2R

PCIEPCIE_85D

PCIE_FW_D2R_C_P

PCIE_FW_D2R

PCIEPCIE_85D

PCIE_FW_D2R_N

PCIE_FW_D2R

PCIE_FW_D2R_C_N

PCIE_85D PCIE

PCIE_FW_R2D

PCIEPCIE_85D

PCIE_FW_R2D_C_N

PCIE_FW_R2D

PCIEPCIE_85D

PCIE_FW_R2D_C_P

PCIE_FW_D2R

PCIEPCIE_85D

PCIE_FW_D2R_P

PCIE_FW_R2D

PCIEPCIE_85D

PCIE_FW_R2D_N

PCIE_FW_R2D

PCIE

PCIE_FW_R2D_P

PCIE_85D

PCIE_T29_D2R PCIEPCIE_85D

PCIE_T29_D2R_C_N<3..0>

PCIE_T29_D2R PCIEPCIE_85D

PCIE_T29_D2R_C_P<3..0>

PCIE_T29_D2R PCIEPCIE_85D

PCIE_T29_D2R_N<3..0>

PCIE_T29_D2R PCIEPCIE_85D

PCIE_T29_D2R_P<3..0>

PCIE_T29_R2D PCIE_85D PCIE

PCIE_T29_R2D_N<3..0>

PCIE_T29_R2D PCIEPCIE_85D

PCIE_T29_R2D_P<3..0>

PCIE_T29_R2D PCIEPCIE_85D

PCIE_T29_R2D_C_N<3..0>

PCIE_T29_R2D PCIE

PCIE_T29_R2D_C_P<3..0>

PCIE_85D

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_EXCARD_N

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_FW_N

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_AP_N

PCIE_CLK100M_ENET_N

CLK_PCIE_90D CLK_PCIE CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP

CLK_PCIE

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET

CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE

PEG_CLK100M_N

PCIE_CLK100M CLK_PCIE_90D CLK_PCIE

PEG_CLK100M_P

CPU_50S

CLK_PCIE

PCH_CLK33M_PCIIN

PCIE_CLK100M CLK_PCIE_90D CLK_PCIE

PCH_CLK100M_SATA_N

CLK_PCIE

CPU_50S

PCH_CLK14P3M_REFCLK

CLK_PCIECLK_PCIE_90D

PCH_CLK96M_DOT_N

PCIE_CLK100M CLK_PCIE_90D

PCH_CLK100M_SATA_P

CLK_PCIE

PCH_CLK96M_DOT_P

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_T29_

PCIE_CLK100M_T29_P

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_T29_

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_T29_N

PCIE_CLK100M CLK_PCIE

PCIE_CLK100M_PCH_N

CLK_PCIE_90D

PCIE_CLK100M

PCIE_CLK100M_PCH_P

CLK_PCIE_90D CLK_PCIE

SPI_CS0

SPI

SPI_55S

SPI_CS0_R_L

SPI_55S

SPI

SPI_CS0_L

HDA_50S

HDA

HDA_SDIN0

AUD_SDI_R

HDA

HDA_50S

HDA

HDA_RST_L

SPI_MOSI

SPI_55S

SPI_MOSI

SPI

SPI_MOSI

SPI_MOSI_R

SPI_55S

SPI

SPI_CLK

SPI_CLK_R

SPI_55S

SPI

HDA_50S

HDA

HDA_SDOUT_R

HDA_50S

HDA_RST_R_L

HDA_RST_L

HDA

HDA_50S

HDA_SYNC_R

SPI_CLK SPI_55S

SPI_CLK

SPI

HDA_50S

HDA

HDA_SDOUT

SML_PCH_1_CLK

SMB_50S

SMB

SMBUS_PCH_1_CLK

HDA_SYNC

HDA

HDA_50S

SPI_MISO

SPI_55S

SPI

SPI_MISO

SMB_50S

SMB

SMBUS_PCH_1_DATA

SML_PCH_1_DATA

SMBUS_PCH_0_DATA

SML_PCH_0_DATA

SMB

SMB_50S

HDA_50S

HDA

HDA_BIT_CLK

HDA

HDA_50S

HDA_BIT_CLK_R

PCIE_ENET_D2R

PCIE_ENET_D2R_C_P

PCIE_85D PCIE

PCIE_ENET_D2R

PCIE

PCIE_ENET_D2R_N

PCIE_85D

PCIE_ENET_D2R

PCIE

PCIE_ENET_D2R_P

PCIE_85D

PCIE_ENET_R2D

PCIE_85D

PCIE_ENET_R2D_C_N

PCIE

PCIE_AP_R2D

PCIEPCIE_85D

PCIE_AP_R2D_N

PCIE_AP_R2D

PCIEPCIE_85D

PCIE_AP_R2D_P

PCIE_ENET_D2R

PCIE_ENET_D2R_C_N

PCIE_85D PCIE

SMB

SML_PCH_0_CLK

SMBUS_PCH_0_CLK

SMB_50S

SMBUS_PCH_DATA

SMB_50S

SMB

SMBUS_PCH_DATA

SMBUS_PCH_CLK

SMB_50S

SMB

SMBUS_PCH_CLK

LPC_CLK33M_LPCPLUS

CLK_LPC

CLK_LPC_50S

PCH_LPC_CLK0

CLK_LPC_50S

LPC_CLK33M_SMC

CLK_LPC

PCH_LPC_CLK0

CLK_LPC_50S

LPC_CLK33M_SMC_R

CLK_LPC

PCH_LPC_CLK0

LPC_RESET_L

LPC

LPC_50S

LPCPLUS_RESET_L

LPC_FRAME_L

LPC_50S

LPC

LPC_FRAME_L

LPC_50S

LPC

LPC_AD<3..0>

LPC_AD

103 OF 132

95 OF 105

36

6

16 31

31

6

16 31

36

16 36

31

16 31

38

16 38

38

16 38

38

33

8

33

8

33

8

33

8

33

16 32

16 38

16 31

16 36

16 31

16 36

16 74

16 25

16

16 33

16

16 47

47

16 57

57

16 57

47

16 47

16

47

16 57

16 48

16 57

16 47

16 48

16 57

16

36

16 36

6

31

6

31

36

16 48

6

16 23 26 28 30 32 41 48 62 89

6

16 23 26 28 30 32 41 48 62 89

6

25 47

25 45

18 25

6

25 47 88

6

16 45 47 88

6

16 45 47 88

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

Port 0 and 2 Not Used

CAESAR II (Ethernet PHY) Constraints

SOURCE: Broadcom 5764-DS04-RDS Page 38

FireWire Interface Constraints

CAESAR II (Ethernet) Constraints

SOURCE: Broadcom 5764-DS04-RDS Page 38

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

FireWire Net Properties

Ethernet Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

I162 I163

I164

I165

ENET_3X

=3:1_SPACING

*

?

=110_OHM_DIFF=110_OHM_DIFF

FW_110D

=110_OHM_DIFF=110_OHM_DIFF

=110_OHM_DIFF

*

=110_OHM_DIFF

*

=3:1_SPACING

?

FW_TP

?

*

0.6 MM

ENET_MDI

=100_OHM_DIFF

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

ENET_100D

=STANDARD

ENET_50S

=50_OHM_SE

=50_OHM_SE =50_OHM_SE =50_OHM_SE

=STANDARD*

Ethernet/FW Constraints

SYNC_DATE=07/22/2010

SYNC_MASTER=K91_MLB

ENET_MDI

ENET_MDI_N<3..0>

ENET_100D

ENET_MDI

ENET_MDI_P<3..0>

ENET_MDI

ENET_100D

ENET_50S

ENET_3X

BCM5764_CLK25M_XTALO

ENET_3X

BCM5764_CLK25M_XTALI

ENET_50S

ENET_RESET_L

ENET_3X

FW_PORT1_TPA_P

FW_110D

FW_TP

FW_P1_TPA

FW_PORT1_TPA_N

FW_110D

FW_TP

FW_P1_TPA

FW_PORT1_TPB_P

FW_110D

FW_TP

FW_P1_TPB

FW_PORT1_TPB_N

FW_110D

FW_TP

FW_P1_TPB

104 OF 132

96 OF 105

36 37

32 36

38 40

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

T29/DP Net Properties

Only used on hosts supporting T29 video-in

Only used on dual-port hosts.

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

T29 IC Net Properties

DisplayPort Signal Constraints

NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

SOURCE: Bill Cornelius’s T29 Routing Notes

T29 I2C Signal Constraints

T29/DP Connector Signal Constraints

T29 SPI Signal Constraints

T29_I2C

*

?

=2x_DIELECTRIC

T29_I2C_55S

* =STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

=STANDARD

T29_SPI_55S

=55_OHM_SE =55_OHM_SE=55_OHM_SE

* =STANDARD =STANDARD

=55_OHM_SE

T29_SPI =2x_DIELECTRIC

*

?

T29 Constraints

SYNC_DATE=10/20/2010

SYNC_MASTER=T29_REF

T29DP

?

=7x_DIELECTRIC

TOP,BOTTOMT29DP

?

*

=5x_DIELECTRIC

T29DP_80D

*

=80_OHM_DIFF =80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF =80_OHM_DIFF

=80_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

T29DP_100D

*

DISPLAYPORT

DP_85D

DP_T29SNK0_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_ML

DP_T29SNK0_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_ML

DP_T29SNK0_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH

DP_T29SNK0_AUXCH_P DP_T29SNK0_AUXCH_N

DISPLAYPORT

DP_85D

DP_T29SNK0_AUXCH

DP_T29SNK1_ML_C_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK1_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK1_ML_P<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK1_ML

DISPLAYPORT

DP_85D

DP_T29SNK1_ML

DP_T29SNK1_ML_N<3..0>

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_C_N

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH

DP_T29SNK1_AUXCH_P

DP_T29SRC_ML_C_N<3..0>

DISPLAYPORT

DP_85D

DP_T29SRC_AUXCH_C_P

DISPLAYPORT

DP_85D

DP_T29SRC_AUXCH_C_N

DISPLAYPORT

DP_85D

T29_I2C

I2C_T29_SCL

T29_I2C_55S

I2C_T29_SDA

T29_I2C

T29_I2C_55S

T29_SPI_CS_L

T29_SPI_55S

T29_SPI

T29_SPI_CS_L

T29_R2D_C_P<3..0>

T29DP_80D

T29DP

T29_R2D0

T29DP

T29DP_80D

T29_R2D_P<0>

T29_R2D0

T29DP

T29DP_80D

T29_R2D_N<0>

T29_R2D1

T29DP

T29DP_80D

T29_R2D_N<1>

T29_R2D1

T29DP

T29DP_80D

T29_R2D_P<1>

T29DP

T29DP_80D

T29_R2D_C_F_P<1..0>

T29DP

T29DP_80D

T29_R2D_C_F_N<1..0>

DP_SDRVA_ML_C_P<3..0>

T29DP_80D

T29DP

T29DP_80D

T29DP

DP_SDRVA_ML_R_N<3..0>

T29DP_80D

DP_SDRVA_AUXCH_C_N

T29DP

DP_SDRVA_AUXCH

DP_SDRVA_AUXCH_N

T29DP

T29DP_80D

DP_SDRVA_AUXCH_C_P

T29DP

T29DP_80D

T29DP

DP_A_EXT_AUXCH_P

T29_R2D_P<2>

T29DP_80D

T29DP

T29_R2D2

T29DP_80D

T29DP

T29_R2D3

T29_R2D_P<3>

T29_R2D_N<2>

T29DP_80D

T29DP

T29_R2D2

T29_R2D_C_F_N<3..2>

T29DP_80D

T29DP

T29_R2D_C_F_P<3..2>

T29DP_80D

T29DP

DP_SDRVB_ML_C_P<3..0>

T29DP

T29DP_80D

T29DP

T29DP_80D

DP_SDRVB_ML_R_P<3..0>

DP_SDRVB_ML_C_N<3..0>

T29DP

T29DP_80D

T29DP

T29DP_80D

DP_SDRVB_ML_R_N<3..0>

DP_SDRVB_ML_N<2..0:2>

T29DP_80D

T29DP

DP_SDRVB_ML_EVEN

DP_SDRVB_ML_P<2..0:2>

T29DP_80D

T29DP

DP_SDRVB_ML_EVEN

DP_SDRVB_ML_P<3..1:2>

T29DP_80D

T29DP

DP_SDRVB_ML_ODD

DP_SDRVB_ML_N<3..1:2>

T29DP_80D

T29DP

DP_SDRVB_ML_ODD

T29DP_80D

T29DP

DP_SDRVB_AUXCH

DP_SDRVB_AUXCH_P

T29DP_80D

T29DP

DP_SDRVB_AUXCH_C_P

T29DP_80D

T29DP

DP_SDRVB_AUXCH

DP_SDRVB_AUXCH_N

T29DP_80D

T29DP

DP_SDRVB_AUXCH_C_N T29DPB_ML_P<3..0>

T29DP_80D

T29DP

T29DPB_ML_N<3..0>

T29DP_80D

T29DP

T29DP_80D

T29DP

T29DPA_ML_N<3..0>

T29DPA_ML_P<3..0>

T29DP_80D

T29DP

DP_B_EXT_AUXCH_P

T29DP

T29DP_80D

DP_B_EXT_AUXCH_N

T29DP

T29DP_80D

T29DP

T29DPB_ML_C_P<3..0>

T29DP_80D

T29DP

T29DPB_ML_C_N<3..0>

T29_R2D_N<3>

T29DP_80D

T29DP

T29_R2D3

DP_SDRVA_AUXCH

DP_SDRVA_AUXCH_P

T29DP

T29DP_80D

DP_SDRVA_ML_R_P<3..0>

T29DP_80D

T29DP

DP_SDRVA_ML_C_N<3..0>

T29DP_80D

T29DP

T29DP_80D

T29DP

DP_A_EXT_AUXCH_N

T29DP

T29DP_80D

T29DPA_ML_C_N<3..0>

T29DP

T29DP_80D

DP_SDRVA_ML_P<2..0:2>

DP_SDRVA_ML_EVEN DP_SDRVA_ML_EVEN

T29DP

DP_SDRVA_ML_N<2..0:2>

T29DP_80D

T29DP

DP_SDRVA_ML_P<3..1:2>

T29DP_80D

DP_SDRVA_ML_ODD

T29DP_80D

DP_SDRVA_ML_ODD

T29DP

DP_SDRVA_ML_N<3..1:2>

T29_R2D_C_N<3..0>

T29DP_80D

T29DP

T29_SPI_MOSI

T29_SPI_55S

T29_SPI

T29_SPI_MOSI

T29_SPI_MISO

T29_SPI_55S

T29_SPI

T29_SPI_MISO

T29_SPI_CLK

T29_SPI_55S

T29_SPI

DP_T29SRC_ML_C_P<3..0>

DP_85D

DISPLAYPORT

DP_T29SNK1_AUXCH

DISPLAYPORT

DP_85D

DP_T29SNK1_AUXCH_N

T29DP

T29DP_80D

T29DPA_ML_C_P<3..0>

T29DP_100D

T29_D2R_C_P<0>

T29_D2R0

T29DP

T29DP_100D

T29_D2R_C_N<0>

T29_D2R0

T29DP

T29DP_100D

T29DP

T29_D2R1

T29_D2R_C_P<1>

T29DP_100D

T29DP

T29_D2R1

T29_D2R_C_N<1>

T29DP_100D

T29DP

T29DPA_D2R1_AUXCH_P

T29DP_100D

T29DP

T29DPA_D2R1_AUXCH_N

T29DP_100D

T29_D2R_C_P<2>

T29_D2R2

T29DP

T29DP_100D

T29_D2R2

T29DP

T29_D2R_C_N<2>

T29DP_100D

T29_D2R3

T29DP

T29_D2R_C_P<3>

T29DP_100D

T29_D2R_C_N<3>

T29_D2R3

T29DP

T29DP_100D

T29DPB_D2R3_AUXCH_P

T29DP

T29DP_100D

T29DPB_D2R3_AUXCH_N

T29DP

T29DP_100D

T29DP

T29_D2R_P<3..0>

T29DP_100D

T29DP

T29_D2R_N<3..0>

105 OF 132

97 OF 105

6

33 79

6

33 79

6

33

6

33

6

33 79

6

33 79

6

33

6

33

6

33 79

6

33 79

6

33

6

33

6

33 79

6

33 79

6

33

33 48 85

33

6 8

33 85

6

85

6

85

6

85

6

85

6

85

6

85

85 86

97

6

85 86

6

85 86

85

6

85

6

85

85 86

6

85 97

6

85 97

85

6 8

33 85

33

6

33

85 86

6

85 86

6

85 86

6

85 86

6

85 86

6

86

6

86

6 8

33 85

6 8

33 85

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

1TO1_DIFFPAIR

=STANDARD =STANDARD

* 0.1 MM0.1 MM

=STANDARD=STANDARD

SYNC_DATE=05/14/2010

SYNC_MASTER=K17_MLB

SMC Constraints

SMB_50S

SMBUS_SMC_B_S0_SDA

SMB

SMB_50S

SMB

SMBUS_SMC_0_S0_SCL

SMB_50S

SMB

SMBUS_SMC_0_S0_SDA

SMB_50S

SMBUS_SMC_BSA_SCL

SMB

SMB_50S

SMBUS_SMC_MGMT_SCL

SMB

SMB_50S

SMBUS_SMC_MGMT_SDA

SMB

SMB_50S

SMB

SMBUS_SMC_BSA_SDA

1TO1_DIFFPAIR

CHGR_CSI_N

CHGR_CSI

1TO1_DIFFPAIR

CHGR_CSI_P

CHGR_CSO

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO_N

SMB_50S

SMBUS_SMC_B_S0_SCL

SMB

SMB_50S

SMB

SMBUS_SMC_A_S3_SDA

SMB_50S

SMBUS_SMC_A_S3_SCL

SMB

SMBUS_SMC_A_S3_SCL

106 OF 132

98 OF 105

45 48 51

6

31 45 48 51 80

6

31 45 48 51 80

6

45 48 63 64

45 48

103 104

45 48

103 104

6

45 48 63 64

64

45 48 51

6

31 45 48 54 55

6

31 45 48 54 55

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

GDDR5 Frame Buffer Signal Constraints

Whistler Net Properties

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

MUXGFX Net Properties

PHYSICAL

NET_TYPE

SPACING

PHYSICAL

LVDS intra-pair matching should be 0.127 mm. Pairs should be within 0.508mm of entire channel. DisplayPort/TMDS intra-pair matching should be 0.127mm. Inter-pair matching should be within 2.54cm. Max Length 241.3mm.

GDDR5 FB A Net Properties

SOURCE: Calpella SFF DG Rev 1.5 (407364) and Family GPU DG-04202-001-v04.

Max length of LVDS/DisplayPort/TMDS traces: 13 inches.

PHYSICAL

NET_TYPE

SPACING SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

GDDR5 FB B Net Properties

ELECTRICAL_CONSTRAINT_SET

DIsplayPort AUX CH intra-pair matching should be 0.127mm. Max length 330.2mm.

Digital Video Signal Constraints

SPACING

I293

I294 I295

I296

I297 I298

I299

I300 I301

I302

I303 I304

I305

I306 I307

I308

I309

I310

I311

I312 I313

I314

I315

I316

?

=5x_DIELECTRIC

GDDR5_CLK

*

=3x_DIELECTRIC

*

?

GDDR5_DATA

LVDS_85D

*

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF

=80_OHM_DIFF=80_OHM_DIFF

=80_OHM_DIFF

GDDR5_80D

=80_OHM_DIFF

*

=80_OHM_DIFF

*

LVDS

?

=3x_DIELECTRIC

*

DISPLAYPORT

?

=4x_DIELECTRIC

TOP,BOTTOM

LVDS

?

=50_OHM_SE

=STANDARD

GDDR5_45R50SE

12.7 MM

* =STANDARD

=50_OHM_SE

DISPLAYPORT

=4x_DIELECTRIC

TOP,BOTTOM

?

=45_OHM_SE =45_OHM_SE

=45_OHM_SE

* =STANDARD =STANDARD

GDDR5_45SE =45_OHM_SE

*

?

GDDR5_CMD

=2x_DIELECTRIC

=7x_DIELECTRIC

GDDR5_EDC

*

?

DP_85D

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

*

=85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

SYNC_DATE=07/21/2010

GPU (Whistler) CONSTRAINTS

SYNC_MASTER=K91_MLB

DP_EXTA_ML_C_N<3..0>

DP_85D

DISPLAYPORT

DP_85D

DP_EG_AUX_CH_P

DP_AUX_CH

CLK_SLOWCLK_SLOW_55S

GPU_CLK27M

LVDS

NC_LVDS_EG_A_DATA_P<3>

LVDS_EG_A_DATA3

LVDS_85D

DP_85D

DISPLAYPORT

DP_EXTA_AUXCH_C_N

FB_A0_WCLK0

GDDR5_80D

FB_A0_WCLK_P<0>

GDDR5_CMD

GDDR5_45SE GDDR5_DATA

FB_A1_DBI_L3

FB_A1_DBI_L<3>

GDDR5_45SE

FB_A1_DBI_L<2>

FB_A1_DBI_L2

GDDR5_DATA

FB_B0_WCLK0

GDDR5_CMD

FB_B0_WCLK_N<0>

GDDR5_80D

FB_A1_CMD

GDDR5_45R50SE

GDDR5_CMD

FB_A1_ABI_L

FB_A1_CMD

GDDR5_45R50SE

GDDR5_CMD

FB_A1_RAS_L

FB_A0_CMD GDDR5_CMD

FB_A0_CAS_L

GDDR5_45R50SE

FB_A1_CMD

GDDR5_45R50SE

GDDR5_CMD

FB_A1_CKE_L

FB_B1_CMD

FB_B1_CKE_L

GDDR5_CMD

GDDR5_45R50SE

FB_B0_CMD

FB_B0_CKE_L

GDDR5_CMD

GDDR5_45R50SE

FB_A0_CLK GDDR5_80D GDDR5_CLK

FB_A0_CLK_P

FB_A0_CLK GDDR5_80D GDDR5_CLK

FB_A0_CLK_N

FB_B1_CMD

FB_B1_ABI_L

GDDR5_CMD

GDDR5_45R50SE

FB_B0_CMD

FB_B0_ABI_L

GDDR5_CMD

GDDR5_45R50SE

FB_B1_CAS_L

GDDR5_CMD

GDDR5_45R50SE

FB_B1_CMD

FB_B0_CMD

FB_B0_CS_L

GDDR5_CMD

GDDR5_45R50SE

FB_B1_CMD

FB_B1_WE_L

GDDR5_CMD

GDDR5_45R50SE

FB_B1_CMD

FB_B1_CS_L

GDDR5_CMD

GDDR5_45R50SE

FB_B0_CMD

FB_B0_A<8..0>

GDDR5_CMD

GDDR5_45R50SE

FB_B1_CMD GDDR5_CMD

GDDR5_45R50SE

FB_B1_A<8..0>

FB_B1_CLK

FB_B1_CLK_N

GDDR5_CLKGDDR5_80D

FB_B1_CLK

FB_B1_CLK_P

GDDR5_CLKGDDR5_80D

FB_B0_CLK

FB_B0_CLK_N

GDDR5_CLKGDDR5_80D

FB_B0_CLK GDDR5_CLKGDDR5_80D

FB_B0_CLK_P

FB_A0_CMD

GDDR5_45R50SE

FB_A0_CS_L

GDDR5_CMD

FB_A0_CMD

FB_A0_CKE_L

GDDR5_45R50SE

GDDR5_CMD

FB_A1_CMD

GDDR5_45R50SE

GDDR5_CMD

FB_A1_CS_L

FB_A1_CLK GDDR5_CLKGDDR5_80D

FB_A1_CLK_N

FB_A1_CLK GDDR5_CLKGDDR5_80D

FB_A1_CLK_P

FB_B0_CMD

FB_B0_WE_L

GDDR5_CMD

GDDR5_45R50SE

FB_B0_CMD

FB_B0_RAS_L

GDDR5_CMD

GDDR5_45R50SE

FB_A0_CMD

GDDR5_45R50SE

GDDR5_CMD

FB_A0_ABI_L

FB_A1_CMD

FB_A1_A<8..0>

GDDR5_CMD

GDDR5_45R50SE

FB_A0_CMD

FB_A0_A<8..0>

GDDR5_45R50SE

GDDR5_CMD

FB_A0_EDC3

FB_A0_EDC<3>

GDDR5_EDC

GDDR5_45SE

FB_A0_EDC2

FB_A0_EDC<2>

GDDR5_45SE

GDDR5_EDC

FB_A0_EDC1

FB_A0_EDC<1>

GDDR5_EDC

GDDR5_45SE

FB_A1_EDC0

FB_A1_EDC<0>

GDDR5_EDC

GDDR5_45SE

FB_A1_EDC<1>

FB_A1_EDC1

GDDR5_EDC

GDDR5_45SE

FB_A1_EDC<2>

FB_A1_EDC2

GDDR5_EDC

GDDR5_45SE

FB_A1_EDC3

GDDR5_EDC

GDDR5_45SE

FB_A1_EDC<3>

FB_A0_EDC0

FB_A0_EDC<0>

GDDR5_45SE

GDDR5_EDC

FB_A0_DBI_L<0>

FB_A0_DBI_L0

GDDR5_45SE GDDR5_DATA

FB_A0_DBI_L<1>

FB_A0_DBI_L1

GDDR5_DATAGDDR5_45SE

FB_A0_DBI_L<3>

FB_A0_DBI_L3

GDDR5_DATAGDDR5_45SE

FB_A0_DBI_L<2>

FB_A0_DBI_L2

GDDR5_DATAGDDR5_45SE

FB_A1_DBI_L<0>

FB_A1_DBI_L0

GDDR5_45SE GDDR5_DATA

FB_A1_DBI_L<1>

FB_A1_DBI_L1

GDDR5_45SE GDDR5_DATA

FB_A0_WCLK0

FB_A0_WCLK_N<0>

GDDR5_80D GDDR5_CMD

FB_A0_WCLK1

GDDR5_80D GDDR5_CMD

FB_A0_WCLK_P<1>

FB_A0_WCLK1

GDDR5_80D GDDR5_CMD

FB_A0_WCLK_N<1>

FB_A1_WCLK0

GDDR5_80D GDDR5_CMD

FB_A1_WCLK_P<0>

FB_A1_WCLK0

GDDR5_80D GDDR5_CMD

FB_A1_WCLK_N<0>

FB_A1_WCLK1

GDDR5_80D GDDR5_CMD

FB_A1_WCLK_P<1>

FB_A1_WCLK1

GDDR5_80D GDDR5_CMD

FB_A1_WCLK_N<1>

GDDR5_45SE

FB_A0_DQ<7..0>

GDDR5_DATA

FB_A0_DQ_BYTE0 FB_A0_DQ_BYTE1

GDDR5_45SE

FB_A0_DQ<15..8>

GDDR5_DATA

GDDR5_45SE

FB_A0_DQ<23..16>

GDDR5_DATA

FB_A0_DQ_BYTE2

GDDR5_45SE

FB_A0_DQ<31..24>

GDDR5_DATA

FB_A0_DQ_BYTE3

GDDR5_45SE GDDR5_DATA

FB_A1_DQ<7..0>

FB_A1_DQ_BYTE0

FB_A1_DQ<15..8>

GDDR5_45SE GDDR5_DATA

FB_A1_DQ_BYTE1

FB_A1_DQ<23..16>

GDDR5_45SE GDDR5_DATA

FB_A1_DQ_BYTE2

FB_A1_DQ<31..24>

GDDR5_45SE GDDR5_DATA

FB_A1_DQ_BYTE3

GDDR5_CMD

FB_RESET_L

FB_AB_RESET

GDDR5_45R50SE

FB_B0_WCLK1

FB_B0_WCLK_N<1>

GDDR5_CMDGDDR5_80D

FB_B1_WCLK0

FB_B1_WCLK_P<0>

GDDR5_CMDGDDR5_80D

GDDR5_CMD

FB_B1_WCLK1

GDDR5_80D

FB_B1_WCLK_P<1>

FB_B1_WCLK1

FB_B1_WCLK_N<1>

GDDR5_CMDGDDR5_80D

FB_B0_DQ_BYTE2

GDDR5_DATAGDDR5_45SE

FB_B0_DQ<23..16>

FB_B0_DQ_BYTE3

FB_B0_DQ<31..24>

GDDR5_DATAGDDR5_45SE

GDDR5_45SE

FB_B1_DQ<15..8>

FB_B1_DQ_BYTE1

GDDR5_DATA

FB_B0_EDC<0>

FB_B0_EDC0 GDDR5_45SE

GDDR5_EDC

FB_B0_EDC<2>

FB_B0_EDC2

GDDR5_EDC

GDDR5_45SE

FB_B0_EDC<3>

FB_B0_EDC3

GDDR5_EDC

GDDR5_45SE

FB_A1_CMD GDDR5_CMD

FB_A1_WE_L

GDDR5_45R50SE

FB_B1_EDC<3>

FB_B1_EDC3

GDDR5_EDC

GDDR5_45SE

FB_B1_EDC<1>

FB_B1_EDC1 GDDR5_45SE

GDDR5_EDC

FB_B1_EDC<2>

FB_B1_EDC2

GDDR5_EDC

GDDR5_45SE

FB_A0_CMD GDDR5_CMD

FB_A0_WE_L

GDDR5_45R50SE

FB_A1_CMD GDDR5_CMD

FB_A1_CAS_L

GDDR5_45R50SE

FB_B0_DBI_L<3>

FB_B0_DBI_L3

GDDR5_45SE GDDR5_DATA

FB_B0_EDC<1>

FB_B0_EDC1

GDDR5_EDC

GDDR5_45SE

FB_B1_DBI_L<1>

FB_B1_DBI_L1

GDDR5_DATAGDDR5_45SE

FB_B1_DBI_L<0>

FB_B1_DBI_L0

GDDR5_DATAGDDR5_45SE

FB_B1_DBI_L<3>

FB_B1_DBI_L3

GDDR5_DATAGDDR5_45SE

GDDR5_CMD

FB_B1_WCLK0

FB_B1_WCLK_N<0>

GDDR5_80D

FB_B0_DQ_BYTE1

FB_B0_DQ<15..8>

GDDR5_DATAGDDR5_45SE

FB_B1_DQ_BYTE0

FB_B1_DQ<7..0>

GDDR5_DATAGDDR5_45SE

GDDR5_45SE

FB_B1_DQ<23..16>

GDDR5_DATA

FB_B1_DQ_BYTE2

FB_A0_CMD

GDDR5_45R50SE

FB_A0_RAS_L

GDDR5_CMD

FB_B1_CMD

FB_B1_RAS_L

GDDR5_CMD

GDDR5_45R50SE

FB_B0_CMD

FB_B0_CAS_L

GDDR5_CMD

GDDR5_45R50SE

FB_B1_EDC<0>

FB_B1_EDC0 GDDR5_45SE

GDDR5_EDC

FB_B0_DBI_L<0>

FB_B0_DBI_L0

GDDR5_45SE GDDR5_DATA

FB_B0_DBI_L<1>

FB_B0_DBI_L1

GDDR5_45SE GDDR5_DATA

FB_B0_DBI_L<2>

FB_B0_DBI_L2

GDDR5_45SE GDDR5_DATA

FB_B1_DBI_L<2>

FB_B1_DBI_L2

GDDR5_45SE GDDR5_DATA

FB_B0_WCLK0

GDDR5_CMD

FB_B0_WCLK_P<0>

GDDR5_80D

FB_B0_WCLK1

FB_B0_WCLK_P<1>

GDDR5_CMDGDDR5_80D

LVDS_85D LVDS

LVDS_EG_A_CLK_N

LVDS_EG_A_CLK

LVDS_EG_A_DATA

LVDS_85D LVDS

LVDS_EG_A_DATA_N<2..0>

LVDS_85D

LVDS_EG_B_DATA

LVDS

LVDS_EG_B_DATA_N<2..0>

DP_EXTA_AUXCH_C_P

DP_AUX_CH

DISPLAYPORT

DP_85D

LVDS_85D LVDS

LVDS_A_CLK

LVDS_A_CLK_P

LVDS_B_DATA_P<2..0>

LVDS_85D LVDS

LVDS_B_DATA

LVDSLVDS_85D

LVDS_CONN_B_CLK_F_N

LVDSLVDS_85D

LVDS_CONN_A_CLK_P

LVDSLVDS_85D

LVDS_CONN_A_CLK_N

LVDSLVDS_85D

LVDS_CONN_A_DATA_N<2..0>

LVDSLVDS_85D

LVDS_CONN_B_CLK_N

LVDSLVDS_85D

LVDS_CONN_B_DATA_P<2..0> LVDS_CONN_B_DATA_N<2..0>

LVDS_85D LVDS

FB_B0_DQ<7..0>

FB_B0_DQ_BYTE0

GDDR5_DATAGDDR5_45SE

FB_B1_DQ<31..24>

FB_B1_DQ_BYTE3

GDDR5_DATAGDDR5_45SE

LVDS

LVDS_EG_A_DATA_P<2..0>

LVDS_EG_A_DATA

LVDS_85D

LVDS

LVDS_EG_A_CLK_P

LVDS_85D

LVDS_EG_A_CLK

DP_EXTA_ML_C_P<3..0>

DP_ML

DP_85D

DISPLAYPORT

LVDSLVDS_85D

LVDS_CONN_B_CLK_P

LVDS_EG_B_DATA3

LVDS_85D LVDS

NC_LVDS_EG_B_DATA_N<3>

LVDS_85D

LVDS_EG_A_DATA3

LVDS

NC_LVDS_EG_A_DATA_N<3>

CLK_SLOW

GPU_CLK100M

CLK_SLOW_55S

LVDS_B_CLK_P

LVDS_85D LVDS

LVDS_B_CLK

LVDS_A_DATA_N<2..0>

LVDS_A_DATA

LVDS_85D LVDS

LVDS_A_DATA_P<2..0>

LVDS_A_DATA

LVDS_85D LVDS

LVDS_CONN_A_CLK_F_N

LVDSLVDS_85D

LVDS_CONN_A_CLK_F_P

LVDSLVDS_85D

LVDS_EG_B_DATA

LVDS_85D LVDS

LVDS_EG_B_DATA_P<2..0>

LVDS_EG_B_DATA3

LVDS_85D LVDS

NC_LVDS_EG_B_DATA_P<3>

LVDSLVDS_85D

LVDS_CONN_B_CLK_F_P

LVDS_B_DATA_N<2..0>

LVDSLVDS_85D

LVDS_B_DATA

LVDS_B_CLK

LVDS_85D LVDS

LVDS_B_CLK_N

LVDS_A_CLK_N

LVDS_85D

LVDS_A_CLK

LVDS

DP_85D

DISPLAYPORT

DP_EG_AUX_CH_N

LVDS_CONN_A_DATA_P<2..0>

LVDSLVDS_85D

107 OF 132

99 OF 105

79 85

79 84

79 80

84 85

76 77

76 78

76 77

76 77 76 78

76 78

76 77

76 78

76 77

76 78

76 77

76 77 78

76 78

76 77

76 78

76 77

76 78

76 77

76 78

79 88

84 85

84 88

6

83

83 84

6

83 84

6

83 84

6

83 84

76 78

79 88

79 85

83 84

79 80

84 88

6

83

6

83

79 88

79 80

6

83

84 88

79 84

6

83 84

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

Graphics ,SATA Constraint Relaxations

(USB_EXTA)

K92 Specific Net Properties

(USB_EXTB)

(USB_EXTC)

(USB_EXTA)

Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

ELECTRICAL_CONSTRAINT_SET

SPACING

NET_TYPE

PHYSICAL

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

K92 Specific Net Properties

K91 does not have

I249

I250

I251

I252

I255

I256

I281 I282

I283

I284 I285

I286

I287

I288

I291

I292

I299 I300

I301

I302 I303

I304

I305 I306

I311

I312

I313

I314

I315

I316

I317

I318 I319

I320

I321 I322

I329

I330

I331 I332

I333

I334

I335

I336

I337

I338

I339

I340

I341

I342

I343

I344

I345

I346

I347

I348

I349

I350 I351

I352

I353

I354

I355

I356

I357

I358

I359 I360

I361 I362

I363

I364

I367 I368

I369

I370

I371

I372

I373

I374

I375 I376

I377

I378 I379

I380

I381

I382

I383

I384

I385

I386

I387

I388

I389

I390

I391 I392

I395

I396

I397

I398

I399

I400

I401

I402

Project Specific Constraints

SYNC_MASTER=K91_MLB

SYNC_DATE=07/22/2010

CLK_PCIE

GND

*

GND_P2MM

GND

*

GND_P2MM

PCIE

GND_P2MM

GND

SATA

*

CLK_PCIE SB_POWER

*

PWR_P2MM

SATA

*

SB_POWER

GND_P2MM

*

ENET_MDI

GND

=2:1_SPACING

SENSE

* ?

=1:1_DIFFPAIR

DIFFPAIR

*

=1:1_DIFFPAIR

=55_OHM_SE

*

=1:1_DIFFPAIR

=55_OHM_SE

=1:1_DIFFPAIR

THERM_1TO1_55S

=55_OHM_SE

SENSE_1TO1_55S

=1:1_DIFFPAIR

*

=55_OHM_SE =55_OHM_SE

=1:1_DIFFPAIR

=55_OHM_SE

USB

*

SB_POWER PWR_P2MM

=1:1_DIFFPAIR

AUDIODIFF

0.1 MM0.1 MM

10 MM

0.1 MM

*

0.1 MM

100 MILMEM_40S

*

0.09 MM

0.23 MM

BOTTOM

CPU_27P4S

100 MIL

*

MEM_72D 100 MIL0.09 MM

BOTTOM

0.127 MM

6.35 MMMEM_72D

*

0.20 MM

GND_P2MM

1000

THERM

?

=2:1_SPACING

*

=STANDARD

*

GND

?

BGA

LVDS_85D LVDS_85D

GND

GND_P2MM

*

CPU_COMP

CPU_VCCSENSE

GND

*

GND_P2MM

1000

PWR_P2MM

0.20 MM

*

AUDIO

*

?

=2:1_SPACING

MEM_CTRL

GND

*

GND_P2MM

MEM_CMD

*

GND

GND_P2MM

GND

MEM_DQS

*

GND_P2MM

*

GND

MEM_CLK

GND_P2MM

GND

MEM_DATA

*

DP_85D

100_DIFF_BGA

BGA

100_DIFF_BGA

BGA

SATA_90D

BGA

100_DIFF_BGACLK_PCIE_90D

6.35 MMMEM_85D

TOP 0.1 MM

*

25 MILS

ENETCONN

?

GND_P2MM

GND

*

USB

GND

*

LVDS

GND_P2MM

10 mm

PCIE_85D

*

0.09 MM

0.1 MMTOP

USB_85D 500 MIL

SENSE

SENSE_1TO1_55S

ISNS_HS_COMPUTING_N

SENSE_1TO1_55S

ISNS_HS_GPU_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_HS_OTHER_P

SENSE

ISNS_HS_OTHER_N

SENSE_1TO1_55S

ISNS_ODD_P

SENSE

SENSE_1TO1_55S

SENSE

CPUIMVP_ISNS1G_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

CPUIMVP_ISNS1G_P

SENSE

SENSE_1TO1_55S

CPUIMVP_ISNS_N

CPU_THERMD_N

THERM_1TO1_55S

THERM

THERM_1TO1_55S

GPU_TDIODE_N

THERM

T29_THERMD_P

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

T29_THERMD_N

THERM

THERM_1TO1_55S

GPU_TDIODE_P

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_P

SENSE_1TO1_55S

SENSE

CPUIMVP_ISUM_R_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

CPUIMVP_ISNS_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISUMG_R_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_PP3V3_S3_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_PP3V3_S5_N

SENSE_1TO1_55S

SENSE

ISNS_PP3V3_S5_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_PP5V_S3_N

SENSE

SENSE_1TO1_55S

ISNS_PP5V_S3_P

SENSE

ISNS_PP1V05_S0PCH_N

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_CPU_DDR_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_CPU_DDR_N

SENSE

SENSE_1TO1_55S

ISNS_PP5V_S0_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

ISNS_PP5V_S0_N

SENSE

SENSE_1TO1_55S

ISNS_PP1V05_S0PCH_P

SENSE_1TO1_55S

SENSE

ISNS_PP3V3_S3_N

SENSE

SENSE_1TO1_55S

ISNS_HDD_R_N

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_ODD_R_P

SENSE

SENSE_1TO1_55S

ISNS_ODD_R_N

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_R_N

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_HDD_R_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_AIRPORT_R_P

ISNS_PP1V5_S0GPU_R_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_PP1V5_S0GPU_R_N

SENSE_1TO1_55S

SENSE

ISNS_PP1V8_S0GPU_R_N

SENSE_1TO1_55S

SENSE

ISNS_PP1V0_S0GPU_R_N

SENSE_1TO1_55S

SENSE

ISNS_PP1V8_S0GPU_R_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_PP1V0_S0GPU_R_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

CPUIMVP_ISNS1_P

SENSE_1TO1_55SSENSE_DIFFPAIR

CPUIMVP_ISNS1_N

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

CPUIMVP_ISNS1G_R_N

SENSE_1TO1_55S

CPUIMVP_ISUM_R_P

SENSE

SENSE_DIFFPAIR

CPUTHMSNS_D2_P

THERM

THERM_1TO1_55SSENSE_DIFFPAIR

CPUTHMSNS_D2_N

THERM_1TO1_55S

THERM

CPU_THERMD_P

THERM_1TO1_55S

THERM

SENSE_DIFFPAIR

THERM_1TO1_55S

THERM

SENSE_DIFFPAIR

GPUTHMSNS_D_P

THERM

THERM_1TO1_55S

GPUTHMSNS_D_N

CPUIMVP_ISNS1G_R_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

CPUIMVP_ISUMG_R_N

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

ISNS_HS_GPU_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_HS_COMPUTING_P

AUDIODIFF

AUD_LO2_R_N

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_LO2_R_P

AUD_LO3_R_N

AUDIODIFF

AUDIO

AUD_LO3_R_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

AUD_MIC_INL_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_MIC_INL_N

AUDIODIFF

AUDIO

SPKRAMP_BL_IN_L_P

AUDIODIFF

AUDIO

AUDIO_DIFFPAIR

SPKRAMP_BL_IN_L_N

AUDIODIFF

AUDIO

SPKRAMP_FL_IN_L_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

SPKRAMP_FL_IN_L_N

AUDIODIFF

AUDIO

SPKRAMP_BR_IN_L_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

SPKRAMP_BR_IN_L_N

AUDIODIFF

AUDIO

SPKRAMP_FR_IN_L_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

SPKRAMP_FR_IN_L_N

AUDIO

AUDIODIFF

SPKRAMP_LFE_IN_L_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

SPKRAMP_LFE_IN_L_N

AUDIODIFF

AUDIO

SSM2375BL_IN_N

AUDIODIFF

AUDIO

SSM2375BL_IN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

SSM2375FL_IN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

SSM2375FL_IN_N

AUDIODIFF

AUDIO

SSM2375BR_IN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

SSM2375BR_IN_N

AUDIODIFF

AUDIO

SSM2375FR_IN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

SSM2375FR_IN_N

AUDIODIFF

AUDIO

SSM2375LFE_IN_P

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

SENSE_1TO1_55S

SENSE

ISNS_AIRPORT_N

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

CPUVCCIOS0_CS_N

SENSE

SENSE_1TO1_55S

CPUVCCIOISNS_R_N

SENSE_1TO1_55S

SENSE

GPUISENS_P

SENSE_1TO1_55S

SENSE

ISNS_HDD_N

SENSE_DIFFPAIR

SENSE

ISNS_ODD_N

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

CPUVCCIOISNS_R_P

ENET_100D

ENETCONN

ENETCONN_N<3..0>

ENET_100D

ENETCONN

ENETCONN_P<3..0>

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

VCCSAS0_CS_P

SENSE_1TO1_55S

SENSE

VCCSAS0_CS_N

SENSE_1TO1_55SSENSE_DIFFPAIR

VCCSAISNS_R_P

SENSE

ISNS_1V5_S3_R_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE_1TO1_55S

ISNS_1V5_S3_R_N

SENSE

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

CPUVCCIOS0_CS_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

GPUISENS_N

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_1V5_S3_N

SENSE

SENSE_1TO1_55S

ISNS_1V5_S3_P

SENSE

SENSE_1TO1_55SSENSE_DIFFPAIR

ISNS_PP1V0_S0GPU_P

SENSE

SENSE_1TO1_55S

ISNS_PP1V8_S0GPU_N

SENSE

SENSE_1TO1_55S

ISNS_HDD_P

SENSE

ISNS_PP1V5_S0GPU_P

SENSE_1TO1_55SSENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_PP1V5_S0GPU_N

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_LCDBKLT_N

SB_POWER

PP1V5_S3RS0

1TO1_DIFFPAIR

CHGR_CSO_R_P

USB_EXCARD_N

USB_85D

USB

USB_85D

USB_TPAD_R_P

USB

PP3V3_S0

SB_POWER

USB_85D

USB

USB_TPAD_R_N

USB

USB_EXCARD_P

USB_85D

USB_EXCARD

PCIE_CLK100M_AP_CONN_N

CLK_PCIE_90D CLK_PCIE

PCIE_CLK100M_AP_CONN_P

PCIE_CLK100M_AP

CLK_PCIECLK_PCIE_90D

PCIE_EXCARD_R2D_C_N

PCIEPCIE_85D

PCIE_CLK100M_EXCARD_CONN_N

CLK_PCIECLK_PCIE_90D

PCIE_CLK100M_EXCARD_CONN_P

CLK_PCIE

PCIE_CLK100M_EXCARD

CLK_PCIE_90D

PCIE_EXCARD_R2D_P

PCIE_85D PCIE

PCIE_EXCARD_R2D

PCIE_EXCARD_R2D_C_P

PCIE_85D PCIE

PCIE_EXCARD_R2D

USB_85D

USB

USB2_EXTA_MUXED_N

PCIE_EXCARD_D2R_N

PCIE_85D PCIE

PCIE_EXCARD_D2R_P

PCIE_85D PCIE

PCIE_EXCARD_D2R

PCIE_EXCARD_R2D_N

PCIE_85D PCIE

USB_LT3_P

USB_85D

USB

USB_LT3_N

USB_85D

USB

USB_85D

USB

USB2_LT1_N CONN_USB2_BT_P

USB_85D

USB

CONN_USB2_BT_N

USB_85D

USB

USB_LT2_N

USB

USB_85D

USB2_EXCARD_CONN_P

USB_85D

USB

USB_EXCARD

USB2_EXCARD_CONN_N

USB_85D

USB

USB_LT2_P

USB_85D

USB

USB2_LT1_P

USB

USB_85D

CHGR_CSI_R_N

1TO1_DIFFPAIR

USB2_EXTA_MUXED_P

USB

USB_85D

CHGR_CSO_R_N

1TO1_DIFFPAIR

CHGR_CSI_R_P

1TO1_DIFFPAIR

SENSE

SENSE_1TO1_55S

VCCSAISNS_R_N

SB_POWER

PP3V3_S5

SENSE

SENSE_1TO1_55S

ISNS_PP1V0_S0GPU_N

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

ISNS_PP1V8_S0GPU_P

AUDIODIFF

AUDIO

SSM2375LFE_IN_N

AUDIO

AUD_LO3_L_P

AUDIODIFF

AUDIO_DIFFPAIR

AUD_LO1_R_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

BI_MIC_P

AUDIO

AUDIODIFF

AUDIO_DIFFPAIR

AUDIO

AUD_LO3_L_N

AUDIODIFF

AUDIO

AUD_MIC_INR_N

AUDIODIFF

AUDIO

AUD_MIC_INR_P

AUDIO_DIFFPAIR

AUDIODIFF

AUDIO

AUD_LO1_R_N

BI_MIC_N

GND

108 OF 132 100 OF 105

50

41

103

50 69

50

9

51

51 79

33 51

51

51 79

89

103

50

104

103

50 68 69

50 69

50

51

9

51

50

57 60

57 62

60

31

103

31

103

49 70

49

41

103

41

103

49

37

49 65

49

49 70

49

49 67

103

41

103

89

103

7

72

104

50 64

8

24 32

53

6 7

12 23 25 26 28 32 35 36 39

40 41 46 48 49 50 51 52 54 57

61 62 72 73 80 83 84 85 88 89

91

102

53

8

24 32

6

31

6

31

16 32

6

32

6

32

6

32

16 32

42

6

16 32

6

16 32

6

32

43

42

6

32

6

32

42

64

42

50 64

64

49

6 7

17 19 20 22 23 24 25 29 46

48 56 71 72 73 83 86 91

102 104

103

60

57 60

58 60

61 62

57 60

57 62

58 60

61 62