Apple A1297 Schematic
8 7
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
6
5
4
3
SCHEM,CANNAREGIO,K20,DVT1
12/12/08
31
REV
2 1
ZONE
657084
DESCRIPTION OF CHANGE
ECN
ENGINEERING RELEASED
CK
APPD
DATE
12/12/08
ENG
APPD
?
DATE
Date
04/01/2008
04/01/2008
04/01/2008
04/01/2008
05/01/2008
04/01/2008
04/01/2008
N/A
D
C
B
91
92
93
94
95
96
97
98
(.csa)
103
MCP Constraints 2
104
Ethernet Constraints
105
FireWire Constraints
106
SMC Constraints
107
GPU (G96) Constraints
108
Project Specific Constraints
109
PCB Rule Definitions
123
PROJECT SPECIFIC CONNS
Contents
M98_MLB
M98_MLB
M98_MLB
M98_MLB
M98_MLB
M98_MLB
M98_MLB
N/A
11
12
13
14
15
16
17
18
19
20
21
22
23
24
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
42
43
44
45
(.csa)
1
1
2
3
4
5
6
7
8
9
Table of Contents
2
System Block Diagram
3
Power Block Diagram
4
Revision History
5
BOM Configuration
6
JTAG Scan Chain
7
Functional / ICT Test
8
Power Aliases
9
Signal Aliases
10
CPU FSB10
11
CPU Power & Ground
12
CPU Decoupling & VID
13
eXtended Debug Port(MiniXDP)
14
MCP CPU Interface
15
MCP Memory Interface
16
MCP Memory Misc
17
MCP PCIe Interfaces
18
MCP Ethernet & Graphics
19
MCP PCI & LPC
20
MCP SATA & USB
21
MCP HDA & MISC
22
MCP Power & Ground
25
MCP Standard Decoupling
26
MCP Graphics Support
28
SB Misc25
29
FSB/DDR3/FRAMEBUF Vref Margining
31
DDR3 SO-DIMM Connector A
32
DDR3 SO-DIMM Connector B
33
DDR3 Support
34
Right Clutch Connector
35
ExpressCard Connector
37
Ethernet PHY (RTL8211CL)
38
Ethernet & AirPort Support
39
Ethernet Connector
41
FireWire LLC/PHY (FW643)
42
FireWire Port Power
43
FireWire Ports
45
SATA Connectors
46
External USB Connectors
48
Front Flex Support
49
SMC41
50
SMC Support
51
LPC+SPI Debug Connector
52
K20 SMBUS CONNECTIONS
53
Current & Voltage Sensing
Contents
K20_MLB
M98_MLB
RXU_K20
NA
K20_MLB
BEN_K20
K20_MLB
RXU_K20
K20_MLB
M98_MLB
M98_MLB
M98_MLB
M98_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
T18_MLB
M98_MLB
M98_MLB
M98_MLB
BEN_K20
BEN_K20
BEN_K20
M98_MLB
M98_MLB
BEN_K20
SUMA_K20
SUMA_K20
SUMA_K20
M98_MLB
YWU_K20
M98_MLB
M98_MLB
M98_MLB
CHANG_K20
T18_MLB
M98_MLB
CHANG_K20
BEN_K20
YWU_K20
D
TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
C
B
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
Date
SyncPage
04/01/2008
04/01/2008
07/24/2008
NA
04/01/2008
07/11/2008
09/24/2008
05/07/2008
09/24/2008
04/01/2008
04/01/2008
04/01/2008
04/01/2008
06/06/2008
06/06/2008
06/06/2008
06/06/2008
06/06/2008
06/06/2008
06/06/2008
06/06/2008
06/06/2008
04/01/2008
04/01/2008
05/01/2008
10/15/2008
06/10/2008
07/14/2008
04/01/2008
05/01/2008
10/15/2008
07/22/2008
07/15/2008
07/15/2008
04/01/2008
05/28/2008
07/14/2008
05/01/2008
07/14/2008
07/18/2008
06/06/2008
05/01/2008
05/28/2008
07/22/2008
08/20/2008
TABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
(.csa)
54
Current Sensing
55
Thermal Sensors
56
Fan Connectors
57
WELLSPRING 1
58
WELLSPRING 2
59
Sudden Motion Sensor (SMS)
61
SPI ROM
62
AUDIO:CODEC
63
AUDIO: LINE IN
65
AUDIO: HEADPHONE AMP
66
AUDIO:SPEAKER AMP
67
AUDIO: JACKS
68
AUDIO: JACK TRANSLATORS
69
DC-In & Battery Connectors
70
PBus Supply & Battery Charger
71
IMVP6 CPU VCore Regulator
72
5V / 3.3V Power Supply
73
1.5V DDR3 Supply
75
5V_S0 / MCP CORE REGULATOR
76
CPU VTT Power Supply
77
Misc Power Supplies
78
Power Control
79
Power FETs
80
NV G96 PCI-E
81
NV G96 CORE/FB POWER
82
NV G96 FRAME BUFFER I/F
84
GDDR3 Frame Buffer A (Bottom)
85
GDDR3 Frame Buffer B (Bottom)
86
NV G96 GPIO/MIO/MISC
87
G96 GPIOs & Straps
88
NV G96 Video Interfaces
89
GPU (G96) CORE SUPPLY
90
LVDS Display Connector
91
GDDR3 Frame Buffer A (Top)
92
GDDR3 Frame Buffer B (Top)
93
Muxed Graphics Support
94
DisplayPort Connector
95
1.1V / 1V8 FB Power Supply
96
Graphics MUX (GMUX)
97
LCD BACKLIGHT DRIVER
98
LCD Backlight Support
99
Misc Power Supplies
100
CPU/FSB Constraints
101
Memory Constraints
102
MCP Constraints 1
Contents
YWU_K20
YWU_K20
M98_MLB
YMA_K20
K20_MLB
YWU_K20
M98_MLB
AUDIO_K20
AUDIO_K20
AUDIO_K20
AUDIO_K20
AUDIO_K20
AUDIO_K20
RXU_K20
RXU_K20
RXU_K20
RXU_K20
RXU_K20
RXU_K20
RXU_K20
RXU_K20
YMA_K20
YMA_K20
M98_MLB
M98_MLB
K20_MLB
M98_MLB
M98_MLB
K20_MLB
M98_MLB
K20_MLB
RXU_K20
M98_MLB
M99_MLB
M88_MLB
M98_MLB
K20_MLB
RXU_K20
T18_MXMGMUX
KIRAN_K20
YLEE_K20
RXU_K20
M98_MLB
M98_MLB
M98_MLB
Date
SyncPage
08/12/2008
05/28/2008
04/01/2008
05/19/2008
09/24/2008
06/17/2008
05/01/2008
09/29/2008
09/29/2008
09/29/2008
09/29/2008
09/29/2008
09/29/2008
05/21/2008
05/21/2008
05/21/2008
05/21/2008
05/21/2008
05/21/2008
05/21/2008
05/21/2008
09/09/2008
05/19/2008
04/01/2008
04/01/2008
09/24/2008
04/01/2008
04/01/2008
09/24/2008
05/12/2008
09/24/2008
05/21/2008
07/14/2008
04/04/2008
11/01/2007
05/01/2008
09/24/2008
05/21/2008
02/13/2008
12/03/2008
07/18/2008
05/07/2008
04/01/2008
04/01/2008
04/01/2008
Page Sync
TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
A
Schematic / PCB #’s
PART NUMBER
820-2390 CRITICAL
DRAWING
TITLE=MLB
ABBREV=DRAWING
LAST_MODIFIED=Fri Dec 12 16:50:42 2008
QTY
1 SCH
8
DESCRIPTION
SCHEM,CANNAREGIO,K20
PCBF,CANNAREGIO,K20
REFERENCE DES
CRITICAL
BOM OPTION
CRITICAL051-7656
PCB1
7 6
DIMENSIONS ARE IN MILLIMETERS
XX
X.XX
X.XXX
ANGLES
DO NOT SCALE DRAWING
THIRD ANGLE PROJECTION
5
4
3
DRAFTER
ENG APPD
QA APPD
RELEASE
METRIC
MATERIAL/FINISH
NOTED AS
APPLICABLE
DESIGN CK
MFG APPD
DESIGNER
SCALE
NONE
SIZE
2
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
TITLE
SCHEM,CANNAREGIO,K20
DRAWING NUMBER
D
APPLE INC.
051-7656
SHT
1
REV.
A
31
OF
1
123
8 7
6
U1000
INTEL CPU
2.X OR 3.X GHZ
PENRYN
PG 9
5
U1300
XDP CONN
PG 12
4
3
2 1
FSB
D
PG 13
GPIOs
FSB INTERFACE
64-Bit
800/1067/1333 MHz
MAIN
MEMORY
PG 14
2 UDIMMs
DDR2-800MHZ
DDR3-1067/1333MHZ
J2900
DIMM
PG 25,26
J6950
DC/BATT
PG 60
U4900
POWER SUPPLY
D
TEMP SENSOR
USB
PG 39
PG 41
PG 45
PG 48,49
J5100
Port80,serial
LPC Conn
PG 43
C
B
CLK
SYNTH
J4510
SATA
Conn
PG 38
HD
J4520
SATA
Conn
PG 38
C
ODD
1.05V/3GHZ.
1.05V/3GHZ.
SATA
PG 19
NVIDIA
MCP79
U1400
J9000
LVDS
CONN
J9400
DISPLAY PORT
CONN
PG 71
PG 71
LVDS OUT
RGB OUT
DP OUT
HDMI OUT
DVI OUT
TMDS OUT
PG 17
UP TO 20 LANES3
PG 16
PCI-E
B
RGMII
PG 17
PCI
(UP TO FOUR PORTS)
PG 18
Misc
PG 24
SPI
PG 20
LPC
PG 18
PWR
CTRL
USB
PG 19
(UP TO 12 DEVICES)
SMB
PG 20
HDA
PG 20
4
3 8 9
2
10 5 6 7
J4720
Bluetooth
U6100
SPI
Boot ROM
PG 52
J4900
B,0
BSB
FanADC
SMC
PG 41
J4700
TRACKPAD/
PG 40
KEYBOARD
PG 40
J4710
IR
PG 40
J4710
CAMERA
PG 40
POWER SENSE
J5650,5600,5610,5611,5660,5720,5730,5750
FAN CONN AND CONTROL
Ser
Prt
J3900,4635,4655
EXTERNAL
Connectors
SMB
CONN
DIMM’s
PG 44
U6200
U3700
A
J3400 U3900
Mini PCI-E
AirPort
PG 28
8
7 6
GB
E-NET
88E1116
PG 31
E-NET
Conn
PG 33
5
U6301 U6500U6400
Line In
Amp
PG 54
HEADPHONE
Amp Amp
J6800,6801,6802,6803
Audio
Codec
PG 53
U6600,6605,6610,6620
Line Out
PG 56PG 55
Audio
Conns
PG 59
4
Speaker
Amps
PG 57
3
SYNC_MASTER=M98_MLB
APPLE INC.
2
System Block Diagram
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
SHT
051-7656
2
1
SYNC_DATE=04/01/2008
REV.
31
OF
123
A
8 7
6
5
4
3
2 1
K20 POWER SYSTEM ARCHITECTURE
PPDCIN_G3H
J6900
D
AC
ADAPTER
IN
DCIN(16.5V)
F6905
6A FUSE
R7020
SMC_DCIN_ISENSE
A
U7000
VIN
ISL6258A
PBUS SUPPLY/
BATTERY CHARGER
(PAGE 60)
J6950
PPVBATT_G3H_CONN
2S4P
(6 TO 8.4V)
C
GMUX
U9600
XP28
(PAGE 84)
PB16B
PB17A
PB17B
PB18A
PL32A
EG_RAIL1_EN
EG_RAIL2_EN
EG_RAIL3_EN
EG_RAIL4_EN
PM_ALL_GPU_PGOOD
SMC
RC
DELAY
Q7056
BATT_POS_GATE
P1V1GPU_EN
P3V3GPU_EN
GPUVCORE_EN
P1V8_S0GPU_EN
P3V3S5_EN
Q7055
CHGR_BGATE
U4900
RC
(PAGE 42)
P60
SMC_PM_G2_EN
DELAY
PM_G2_P1V05S5_EN
MCP79
SLP_RMGT#(J17)
B
PCI_RESET0#(R10)
U1400
SLP_S5#(H17)
SLP_S3#(G17)
PM_SLP_RMGT_L
R2870
RC
DELAY
PM_SLP_S4_L
PM_SLP_S3_L
MEM_VTT_EN
DDRREG_EN
P5VS3_EN
R6905
VOUT
PPVBAT_G3H_CHGR_R
P1V1_GPU_EN
P1V8_S0GPU_EN
BKLT_PLT_RST_L
&& ENA
LCD_BKLT_EN
PPVBAT_G3H_CHGR_REG
R7050
U5303
SMC_BATT_ISENSE
MCPCORES0_EN
PM_SLP_S3_L_R
Q4260
VIN
EN1
1.103V(L/H)
EN2
1.8V(R/H)
ISL6236
U9500
(PAGE 83)
(PAGE 85~86)
A
VOUT2
P5VS3_EN
P3V3S5_EN
VIN
APP001
U9701
VIN
(PAGE 14~22)
FW_PORTPWR_EN&&(SMC_ADAPTER_EN||PM_SLP_S3_L)
R7878
PM_SLP_S3_L_R
A
DELAY
DELAY
DELAY
DELAY
RC
RC
RC
RC
P1V8S0_EN
MCPDDR_EN
CPUVTTS0_EN
MCPCORES0_EN
DELAY
DELAY
DELAY
P1V05S0_EN
RC
P1V2_S0_EN
RC
P2V5S0_EN
RC
PM_G2_P1V05S5_EN
EN
VIN
1.05V AUX
ISL6269
U7750
(PAGE 66)
VOUT1
POK1
POK2
(PAGE 66)
D6905
D6905
F7040
F7041
8A FUSE
MCP_CORE
EN2
EN1
VIN
(PAGE 64)
PP1V1_S0GPU
R5413
A
P1V1GPU_PGOOD
PM_ALL_GPU_PGOOD
VOUT
LTC1872
U7790
VOUT
PGOOD
VOUT2
5V
VOUT1
ISL6236
POK1
U7500
POK2
PP1V8_S0GPU_ISNS
SMC_GPU_1V8_ISENSE
VIN
EN1
5V
(L/H)
3.3V
EN2
(R/H)
TPS51220
U7201
(PAGE 62)
PGOOD1,2
P5V3V3_PGOOD
PPVOUT_S0_LCDBKLT
PP10V_FW
VOUT
PP1V2R1V05_S5
P1V05_S5_PGOOD
PPVIN_G3H_P3V42G3H
PPBUS_G3H
R7505
A
SMC_MCP_CORE_ISENSE
PP5V_S0
P5V_RTS0_PGOOD
MCPCORES0_PGOOD
DDRREG_EN
MEM_VTT_EN
PP5V_S3
VOUT1
PP3V3_S5
VOUT2
PPBUS_G3H_VSENSE
GPUVCORE_EN
SMC_CPU_HI_ISENSE
V
PPVCORE_S0_MCP
Q7953
P1V05S0_EN
V
SMC_MCP_VSENSE
Q7910
Q7930
Q7970
PP1V05_S0
Q3840
PM_SLP_RMGT_L
Q5315
GPU VCORE
ISL6263C
VR_ON PGOOD
(PAGE 77)
R5388
VIN
1.5V
S5
S3
0.75V
TPS51116
U7300
(PAGE 63)
PP3V3_S5
PM_SLP_S4_L
PM_SLP_S3_L
P3V3GPU_EN
Q3810
PM_SLP_RMGT_L
VIN
U8900
A
IMVP_VR_ON
VLDOIN
VOUT1
VOUT2
PP3V3_S3
PP3V3_S0
PP3V3_S0GPU
P3V3_ENET_PHY
PP1V2R1V05_ENET
ENABLE
3.425V G3HOT
LT3470A
U6990
(PAGE 59)
VOUT
SMC_GPU_ISENSE
GPUVCORE_PGOOD
VR_ON
PP0V9R0V75_S0_DDRVTT
P1V8_S0GPU_EN
A
U5410
CPU VCORE
VIN
ISL9504B
U7100
(PAGE 61)
PP1V8R1V5_S3
P1V2_S0_EN
P2V5S0_EN
P1V8S0_EN
EN
PP3V42_G3H
R0940
P1V0FW_EN
(PAGE 66)
VOUT
PGOOD
VI
TPS62202
U7760
PP3V3_S5
P1V05_S5_PGOOD
SMC_GPU_VSENSE
V
PPVCORE_GPU
U7100
SMC_CPU_ISENSE
VR_PWRGOOD_DELAY
RUN1
LTC3547
U9900
RUN2
(PAGE 87)
RUN1
LTC3547
U7700
RUN2
(PAGE 66)
VOUT
PP3V42_G3H
A
Q7901
MCPDDR_EN
VIN
VOUT1
VOUT2
VIN
VOUT1
VOUT2
PP1V8_GPUIFPX
PP1V8R1V5_S0
PP1V05_S0
SENSE
(PAGE 67)
S5 PWRGD
NCP303LSN
(PAGE 42)
SMC_CPU_VSENSE
V
R5445
SMC_MCP_DDR_ISENSE
A
PP1V2_S0
PP2V5_S0
PM_ALL_GPU_PGOOD
PP1V0_FW
PP1V8_S0
VDD
U7840
TPS3808G
SMC PWRGD
U5000
CPUVTTS0_EN
PPVCORE_S0_CPU
PPMCPDDR_ISNS
PP1V8R1V5_S0
PP3V3_S5
S0PGOOD_PWROK
PP3V3_S0
ADJ1
ADJ2
RSMRST_PWRGD
RESET*
MR*
SMC_RESET_L
EN_PSV
R7894
P5V3V3_PGOOD
P5V_RTS0_PGOOD
MCPCORES0_PGOOD
CPUVTTS0_PGOOD
VCC
U7870
LTC2909
(PAGE 67)
TRST = 200mS
VIN
1.05V
SC417
U7600
(PAGE 65)
U7880
RST*
MIC5232-2.8YD5
U2801
VIN
(PAGE 25)
VOUT
PGOOD
ALL_SYS_PWRGD
RSMRST_PWRGD
VOUT
CPUVTTS0_PGOOD
MCP_PS_PWRGD
U2850
SMC_ONOFF_L
PM_SLP_S4_L
PM_SLP_S4_L
PM_SLP_S3_L
PP3V3_G3_RTC
R7650
PPCPUVTT_S0
A
SMC_CPU_FSB_ISENSE
PS_PWRGD
(PAGE 14~22)
CPU
U1000
(PAGE 10,11)
PWRGD(P12)
RSMRST_IN(P13)
PWR_BUTTON(P90)
SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)
SYNC_MASTER=RXU_K20
APPLE INC.
SMC_TPAD_RST_L
SMC_ONOFF_L
U5001
MCP79
PWRBTN#
RSTBTN#
PWRGD_SB
CPU_RESET#
CPU_PWRGD
PM_SYSRST_DEBOUNCE_L
FSB_CPURST_L
CPU_PWRGD
U1400
PWRGOOD
RESET*
SMC
U4900
(PAGE 42)
RSMRST_OUT(P15)
99ms DLY
IMVP_VR_ON(P16)
P17(BTN_OUT)
SYSRST(PA2)
RES*
PM_RSMRST_L
IMVP_VR_ON
PM_SYSRST_L
PM_PWRBTN_L
SMC_RESET_L
Power Block Diagram
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
DRAWING NUMBER
SIZE
D
SCALE
NONE
SHT
051-7656
3
SYNC_DATE=07/24/2008
REV.
31
OF
123
D
C
B
A
8
7 6
5
4
3
2
1
8 7
Proto:
See earlier schematics for info about proto changes
Pre-EVT:
See earlier schematics for info about Pre-EVT changes
EVT:
10/29/08
csa. 5 Added BKLT_PLL_NOT BOM option K20_COMMON2 BOM group. This stuffs R9713.
csa. 68 Changed net name on input to U6860 from PP3V3_S0_AUDIO to =PP3V3_S0_AUDIO.
D
See <rdar://problem/6327731> K20 PreEVT: iPhone headset detection test fail
csa. 97 Changed R9707 to 2.87K per <rdar://problem/6327135> Change R9707 to 2.87k, 1% resistor
10/29/08
csa. 9 Changed SH0924 to 870-1698 tall emi pogo pin.
11/5/08
csa. 4 Updated Revision History.
csa. 8 Tied =PP3V3_FW_FWPHY and =PP3V3_FW_P1V0FW aliases to PP3V3_S0.
csa. 9 Removed R0942 and R0943 which were for selecting from S0 or S3 for =PP3V3_FW_FWPHY.
Removed R0940 and R0941 which were for selecting from S0 or S3 for =PP3V3_FW_P1V0FW.
Tied =PP3V3_S3_GMUX alias to PP3V3_S3.
csa. 75 Changed U7500 from 353S2312 Intersil ISL6236 to 353S2203 TI SN0802043.
Changed TONSEL from GND to PP5V_S0_MCPREG_VCC. This changes output frequencies to 200/300KHz for 5V/MCPCore.
Added C7562 330uF cap on =PPMCPCORE_S0_REG.
Changed snubber resistors R7598 and R7599 to 1/6W 0402, APN 114S0548.
csa. 87 Changed pulldown values to 10K on GPIO7_FBVDDQ_ALTVO, R8794.
Changed pulldowns R8792 and R8793 from 1K to 4.7K for power consumption.
csa. 90 Removed R9094. Replaced by R9678 on csa. 96 to tie to GMUX_S3_PD_GND.
csa. 96 Added Q9607 dual FET for disabling GMUX power sequence enable configuration pulldowns during S0.
Moved R9094 to R9678 and tied to GMUX_S3_PD_GND.
csa. 97 Changed R9707 to 2.67K 1%. This gives 22.5mA on LED current.
11/10/08
csa. 68 Changed R6885 from 0 ohms to 2.2K.
Changed C6885 from 470 pF to 0.0082 uF.
csa. 87 Changed R8792 and R8793 from 4.7K to 10K pulldowns on EG_LCD_PWR_EN and EG_BKLT_EN.
csa. 96 Changed R9678 pulldown on LCD_PWR_EN from 10K to 4.7K.
Removed BOM options on FET circuit for GMUX_S3_PD_GND.
Added R9684 NO STUFF 0 ohms to tie ALL_SYS_PWRGD to Q9607.
C
11/11/08
csa. 8 removed =PP3V3_S3_P1V0FW and =PP3V3_S3_BKL_VDDIO
csa. 41 changed R4160 from 274K to 200K <rdar://6292976>
csa. 68 changed R6885 from 0 ohm to 2.2K for Mic LPF
csa. 75 NO STUFF R7598, C7598, R7599, C7599 (snubbers)
csa. 87 changed R8795 from 1K to 10K pull down
csa. 96 NO STUFF R9677, C9695, STUFF R9684
11/12/08
csa. 5 removed MCP79 B01 from Module Parts table and added B03
csa. 39 added Bom table for J3900 (514-0636)
csa. 46 added Bom table for J4600, J4610 (514-0638)
csa. 94 added Bom table for J9400 (514-0637)
csa. 123 added Bom table for JC320 (514-0638)
11/13/08
csa. 1 change title to DVT
csa. 32 Added alternate table for J3200 (516S0709, Molex DIMM connector)
11/19/08
csa. 5 changed MCP79 B03 to 338S0710; change to binned G96 338S0714;
added PROD_DIGSMS and TPDT_DEBOUNCE to BOM groups
csa. 68 added bom option TPDT_BYPASS to R6865; TPDT_DEBOUNCE to U6860,C6861,R6860,R6862
csa. 97 changed Q9701 to 376S0757 <radr://6383480>
11/25/08
csa. 5 changed BOM option MCP_B02 to MCP_B03; added BOM option GMUX_1V8
added Mag Layer alternate 155S0457 to Murata 155S0329
csa. 93 added BOM table for 16 LVDS termination resistors to select GMUX_2V5 or GMUX_1V8
added BOM option GMUX_2V5 to 8 parallel resistors so they’ll be NO STUFFed for GMUX_1V8
B
csa. 97 reverted Q9701 to 376S0678 due to parts availability
csa. 99 added BOM table for R9900 to select either 2.5V output or 1.8V output
DVT:
12/02/08
Start of PVT.
csa. 5 removed JTAG_ALLDEV bom option to remove U0600, R0601, C0601, C0602
added 516-0213 (Molex TH SODIMM CONN) as alternate to 516-0201 (Foxconn)
added GMUX_JTAG_CONN bom option to the bom table
csa. 6 added GMUX_JTAG_CONN bom option to J0600
csa. 99 moved OMIT from R9900 to R9901 to select either 150K (GMUX_2V5) or 237K (GMUX_1V8)
12/03/08
csa. 32 removed redundant alternate table for J3200
csa. 97 Per radar 6383480, Change the FET Q9701 from APN: 376S0678 to 376S0757
diode D9701 from APN: 371S0551 to 371S0572
12/09/08
csa. 1 changed title to DVT(1)
csa. 26 NO STUFF C2690, R2690
csa. 32 Refreshed symbol for J3200 for update to BGA SODIMM conn.
csa. 54 changed R5498 to 4.02K for 1.4x gain and R5493 to 2.87K <rdar://6423810>
csa. 89 changed L8920 to 152S0955 (25A Isat); R8900 to 7.15K for 24.6A OCP <rdar://6423810>
12/12/08
csa. 1 changed title to DVT1
csa. 4 removed pre-EVT check in notes from Rev. History
csa. 99 changed text note to reflect 2.5V to 1.8V GMUX rail change
A
6
5
4
3
2 1
D
C
B
31
OF
SYNC_DATE=NA
REV.
31
123
A
SYNC_MASTER=NA
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
SHT
051-7656
4
8
7 6
5
4
3
2
1
BOM Variants
BOM NUMBER
630-9728
630-9727
630-9730
630-9729
D
K20 BOM GROUPS
BOM GROUP
K20_COMMON
K20_COMMON1
K20_COMMON2
K20_DEBUG
K20_PROGPARTS
BOM GROUP
FB_1024_SAMSUNG
FB_1024_QIMONDA
FB_512_SAMSUNG
FB_512_QIMONDA
8 7
BOM NAME
PCBA,BEST,2.66,512SAM_VRAM,K20
PCBA,BEST,2.66,512QIM_VRAM,K20
PCBA,BEST,2.93,512SAM_VRAM,K20
PCBA,BEST,2.93,512QIM_VRAM,K20
ALTERNATE,COMMON,K20_COMMON1,K20_COMMON2,K20_DEBUG,K20_PROGPARTS
ONEWIRE_PU,ISL6258,MEMRESET_HW,MEMRESET_MCP,MCP_B03,MCP_PROD,MCPSEQ_SMC,BMON_ENG,MCP_CS1_NO,FW_LVG_NEW,PROD_DIGSMS,TPDT_DEBOUNCE
BOOT_MODE_USER,GPUVID_1P00V,MUXGFX,DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_GMUX,DP_CA_DET_EG_PLD,BKLT_PLL_NOT,GMUX_1V8
SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG,GMUX_JTAG_CONN
K20_COMMON,EEE_4CM,CPU_2_66GHZ,FB_512_SAMSUNG
K20_COMMON,EEE_4CH,CPU_2_66GHZ,FB_512_QIMONDA
K20_COMMON,EEE_4CQ,CPU_2_93GHZ,FB_512_SAMSUNG
K20_COMMON,EEE_4CP,CPU_2_93GHZ,FB_512_QIMONDA
BOM OPTIONS
GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG
BOM OPTIONS
VRAM8,VRAM_1024_SAMSUNG
VRAM8,VRAM_1024_QIMONDA
VRAM4,VRAM_512_SAMSUNG
VRAM4,VRAM_512_QIMONDA
6
BOM OPTIONS
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_HEAD
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
TABLE_BOMGROUP_ITEM
5
Alternate Parts
PART NUMBER
353S1681
152S0684
104S0023 104S0018
104S0024
152S0876
157S0058
514-0612
514-0613
152S0684
152S0896
152S0915
516S0709
155S0457 155S0329
516-0213 516-0201
ALTERNATE FOR
PART NUMBER
152S0276152S0476
353S1294
138S0602138S0603
152S0368
104S0017
341S2366341S2367
152S0782
157S0055
514-0607
514-0608
152S0421
152S0518
152S0796
516S0706
BOM OPTION
4
REF DES
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
ALL
COMMENTS:
Inductor alternate
TI alt to National
Murata alt to Samsung
Maglayers alt to Dale/Vishay
Cyntec alt to sense resistor
Panasonic alt to FW resistor
Macronix alt to SST
Maglayer alt to Delta
Delta alt to TDK Magnetics
FOXLINK ALT TO FOXCONN XCVR
FOXLINK ALT TO FOXCONN RCVR
MAG LAYERS ALT TO VISHAY
MAG LAYERS ALT TO CYNTEC
MAG LAYERS ALT TO CYNTEC
MOLEX ALT TO FOXCONN
MAG LAYERS ALT TO MURATA
MOLEX ALT TO FOXCONN
3
TABLE_ALT_HEAD
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
2 1
D
Bar Code Labels / EEE #’s
C
PART NUMBER
826-4393
826-4393
826-4393
Module Parts
B
A
PART NUMBER
338S0635
QTY
1
1
1
1
QTY
337S3645
337S3644
338S0714
338S0694
338S0654
338S0710 CRITICAL
335S0610
341S2356 CRITICAL
341S2384
341S2383
337S3643
337S3640
337S3641
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
4
333S0472
333S0481
333S0472
4
8
8
DESCRIPTION
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
IC,PDC,QXXX,QS,2.66,25W,1066,E0,6M,BGA
IC,PDC,QXXX,QS,2.86,35W,1066,E0,6M,BGA
IC,ASSP,GPU,NV G96-GS,LOWLKG,BGA969,LF
IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP
IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12
IC,MCP79XT-B3,35X35MM,BGA1437
IC,SMC,HS8/2117,9MMX9MM,TLP
IC,SMC,DEVELOPMENT,K20
IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP
IC,EFI ROM,DEVELOPMENT,K20
IR,ENCORE II, CY7C63833-LFXC
IC,GMCP,MCP79-A01Q,35x35MM,BGA1437
IC,PSOC +W/USB,56PIN,MLF,M98
IC,PDC,QXXX,QS,2.93,35W,1066,E0,6M,BGA
IC,PDC,SL3BX,PRQ,2.53,35W,1066,C0,6M,BGA
IC,PDC,SLB43.PRQ,2.80,35W,1066,E0,6M,BGA
IC,GMCP,MCP79-B02,35x35MM,BGA1437
IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA
IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA
IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA
IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA
DESCRIPTION
REFERENCE DES
[EEE:4CH]
[EEE:4CM]
[EEE:4CP]
[EEE:4CQ]
REFERENCE DES
U1000
U1000
U8000
U3700
U4100
U1400
U4900
U4900
U6100
U6100
U4800
U1400
U5701
U1000
U1000
U1000
U1400
U8400,U8450,U8500,U8550
U8400,U8450,U8500,U8550
U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250
U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL826-4393
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL338S0563
CRITICAL341S2355
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL333S0481
CRITICAL
CRITICAL
CRITICAL
BOM OPTION
EEE_4CH
EEE_4CM
EEE_4CP
EEE_4CQ
BOM OPTION
CPU_2_66GHZ
CPU_2_86GHZ
MCP_B03
SMC_BLANK
SMC_PROG
BOOTROM_BLANK
BOOTROM_PROG
MCP_A01QCRITICAL338S0603
TPAD_PROG
CPU_2_93GHZ
CPU_2_53GHZ
CPU_2_80GHZ
MCP_B02
VRAM_512_SAMSUNG
VRAM_512_QIMONDA
VRAM_1024_SAMSUNG
VRAM_1024_QIMONDA
BOM Configuration
SYNC_MASTER=K20_MLB
NOTICE OF PROPRIETARY PROPERTY
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
SIZE
APPLE INC.
SCALE
D
NONE
DRAWING NUMBER
051-7656
SHT
SYNC_DATE=04/01/2008
OF
5
123
C
B
A
REV.
31
8
7 6
5
4
3
2
1
8 7
6
5
4
3
2 1
1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)
=PP3V3_S0_XDP
13
8
6
D
61 13 12
C
11
10
8
=PP1V05_S0_CPU
JTAG_ALLDEV
R0601
10K
1/16W
MF-LF
NOSTUFF
R0602
1/16W
MF-LF
To XDP connector
and/or level translator
XDP_TDO
10
JTAG_MCP_TDO
21
XDP
PLACEMENT_NOTE=Place near pin U1000.AB3
R0603
0
1 2
5%
1/16W
MF-LF
402
XDP
R0604
0
1 2
5%
1/16W
MF-LF
402
PLACEMENT_NOTE=Place near pin U1400.F19
XDP_TDO_CONN
JTAG_MCP_TDO_CONN
ry
a
13
OUT
XDP connector
13
OUT
XDP connector
13
13
13
13
21 10
21
21
21
U1000
CPU
88
U1400
MCP
MAKE_BASE=TRUE
From XDP connector
JTAG_ALLDEV
1
C0601
0.1UF
20%
10V
2
CERM
402
1
5%
402
2
13
88
1
0
5%
402
2
88
13
88
13
XDP_TCK
6
XDP_TMS
10
6
XDP_TRST_L
10
6
JTAG_LVL_TRANS_EN_L
1
2
JTAG_ALLDEV
C0602
0.1UF
20%
10V
CERM
402
JTAG_ALLDEV
2
3
4
5
12
VCCA
NLSV4T244
A1
A2
A3
A4
OE*
1
VCCB
U0600
UQFN
GND
6
IN
IN
IN
IN
XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L
JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L
6
10 13 88
10 13 88
6
10 13 88
6
10 13 88
11
or via level translator
10
B1
9
B2
8
B3
7
B4
1
R0606
10K
5%
1/16W
MF-LF
402
2
From XDP connector
MAKE_BASE=TRUE
MAKE_BASE=TRUE
D
C
NOSTUFF
PLACEMENT_NOTE=Place close to U8000
R0605
10K
1 2
5%
1/16W
MF-LF
402
GPU_JTAG_TMS
B
74
74
74
6
74
84
9
84
9
84
U8000
GPU
U9600
GMUX
74
84
9
GPU_JTAG_TDO
JTAG_GMUX_TDO
i
n
6
VCC
U0601
74LVC1G07
2
1
GMUX CPLD Programming Port
CRITICAL
J0600
1909782
M-RT-SM
GMUX_JTAG_CONN
B
7
=PP3V3_S0_XDP
1
2
TDO
TDI
3
TMS
4
5
TCK
6
8
8
6
NC NC
13
YA
4
5
NCNC
SOT886
GND
3
PLACEMENT_NOTE=Place close to U0600
GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TMS
GPU_JTAG_TRST_L
JTAG_GMUX_TCK
i
JTAG_GMUX_TDI
JTAG_GMUX_TMS
m
l
=PP3V3_GPU_VDD33
75
8 6
74 74
TP_GPU_JTAG_TDO
MAKE_BASE=TRUE
re
P
A
8
7 6
5
4
3
SYNC_MASTER=BEN_K20
APPLE INC.
2
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
JTAG Scan Chain
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SIZE
D
SCALE
NONE
SHT
051-7656
6
1
SYNC_DATE=07/11/2008
REV.
OF
123
A
31
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
NO_TEST
LVDS NO_TESTs
NC NO_TESTs
J5800 (IPD FLEX CONN)
FUNC_TEST
FUNC_TEST
6 TPs
NO_TEST
NO_TEST
J5650 (LEFT FAN CONN)
J6995 (BAT LED CONN)
J6950 (MAIN BATT CONN)
J6900 (DC POWER CONN)
FUNC_TEST
POWER RAILS
USB PORTS
J5713 (KEY BOARD CONN)
FUNC_TEST
3 TPs
NC NO_TESTs
NO_TEST
CPU FSB NO_TESTs
ICT Test Points
NO_TEST
J3500 (EXPRESS CARD CONN)
4 TPs
5 TPs
3 TPs
5 TPs
Functional Test Points
per Fan
J5502 (SENSOR CONN)
J5660 (RIGHT FAN CONN)
J6780 (MIC CONN)
J6782 (RIGHT & SUB SPEAKER)
J9000 (LVDS CONN)
J4500 (SATA ODD CONN)
J4501 (SATA HDD CONN)
J5815 (KBD BACKLIGHT CONN)
J4800 (FRONT CABLE CONN)
FB NO_TESTs
2 TP needed
J3401 (AIRPORT/BT/CAMERA CONN)
per Fan
J6781 (LEFT SPEAKER)
NC NO_TESTs
NO_TEST
I1000
I1001
I1002
I1003
I1004
I1005
I1006
I1007
I1008
I1009
I1010
I1011
I1012
I1013
I1014
I1015
I1016
I1017
I1018
I1019
I1020
I1021
I1022
I1024
I1025
I1026
I1027
I1028
I1029
I1031
I1032
I1033
I1034
I1035
I1038
I1039
I1040
I1042
I1043
I1044
I1046
I1047
I1048
I1050
I1051
I1052
I1053
I1054
I1055
I1056
I1057
I1058
I1059
I1060
I1061
I1062
I1063
I1064
I1065
I1066
I1067
I1068
I1069
I1070
I1071
I1072
I1073
I1074
I1075
I1076
I1077
I1078
I1079
I1080
I1081
I1082
I1083
I1084
I1085
I1086
I1087
I1088
I1089
I1090
I1091
I1092
I1093
I1094
I1095
I1096
I1097
I1098
I1099
I1100
I1101
I1102
I1103
I1104
I1105
I1106
I1107
I1108
I1109
I1110
I1111
I1112
I1113
I1114
I1115
I1116
I1117
I1118
I1119
I1120
I1121
I1122
I1123
I1124
I1125
I1126
I1127
I1128
I1129
I1130
I1131
I1132
I1134
I1135
I1136
I1137
I1140
I1141
I1142
I1143
I1145
I1146
I1148
I1149
I1150
I1151
I1152
I1154
I1155
I1156
I1157
I1159
I1160
I1161
I1273
I1274
I1275
I1276
I1277
I1280
I1281
I1282
I1283
I1284
I1285
I1286
I1288
I1290
I1291
I1292
I1293
I1294
I1296
I1297
I557
I558
I559
I600
I602
I603
I604
I605
I606
I607
I608
I610
I611
I612
I613
I614
I615
I616
I617
I618
I620
I621
I622
I623
I624
I625
I626
I627
I636
I637
I638
I639
I640
I709
I714
I720
I722
I723
I724
I725
I726
I727
I728
I729
I730
I731
I732
I733
I734
I735
I736
I737
I738
I739
I740
I741
I742
I743
I744
I751
I752
I756
I761
I762
I763
I764
I765
I766
I767
I768
I769
I770
I771
I772
I774
I981
I982
I985
I986
I987
I988
I989
I990
I991
I992
I993
I994
I995
I996
I997
I998
7
123
31
051-7656
Functional / ICT Test
SYNC_MASTER=K20_MLB
SYNC_DATE=09/24/2008
GND
TRUE
TRUE
GND
TRUE
GND
TRUE
GND
TRUE
GND
GND
TRUE
TRUE
GND
TRUE
GND
TRUE
GND
TRUE
GND
TRUE
GND
TRUE
GND
TRUE
GND
TRUE
GND
NC_SMC_FAN_3_TACH
TRUE
NC_SMC_FAN_2_TACH
TRUE
FSB_ADS_L
TRUE
TP_PCI_CLK1
TRUE
FSB_REQ_L<4..0>
NC_GPU_GSTATE<1>
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_D<9..0>
TRUE
MAKE_BASE=TRUE
NC_GPU_MIOA_DE
MAKE_BASE=TRUE
TRUE
NC_GPU_PGOOD_OUT_L
TRUE
MAKE_BASE=TRUE
TP_GPU_PGOOD_OUT_L
TP_GPU_VCORE_VID3
TP_LPC_DRQ0_L
NC_PCI_INTZ_L
MAKE_BASE=TRUE
TRUE
NC_PCI_INTY_L
MAKE_BASE=TRUE
TRUE
MAKE_BASE=TRUE
TRUE
NC_PCI_INTX_L
NC_PCI_FRAME_L
MAKE_BASE=TRUE
TRUE
NC_PCI_DEVSEL_L
MAKE_BASE=TRUE
TRUE
NC_PCI_AD<31..8>
MAKE_BASE=TRUE
TRUE
NC_PCI_C_BE_L<3..0>
MAKE_BASE=TRUE
TRUE
NC_PCI_CLK0
MAKE_BASE=TRUE
TRUE
NC_PCI_CLK1
TRUE
MAKE_BASE=TRUE
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
WS_CONTROL_KBD
TRUE
WS_LEFT_OPTION_KBD
TRUE
WS_LEFT_SHIFT_KBD
TRUE
WS_KBD_ONOFF_L
TRUE
TRUE
WS_KBD23
TRUE
WS_KBD22
PCIE_MINI_R2D_P
TRUE
TRUE
PCIE_MINI_D2R_N
SPKRAMP_L1_OUT_P
TRUE
TRUE
SPKRAMP_L2_OUT_N
USB_LT3_P
TRUE
PP5V_S3_IR_R
TRUE
TRUE
IR_RX_OUT
BKLT_EN
TRUE
BKL_SW
TRUE
TRUE
BKL_GD
TRUE
FB_A_DQ<63..0>
TRUE
FB_B_DQ<63..0>
TRUE
FB_B_BA<1>
TRUE
FB_B_CAS_L
FB_B_CS0_L
TRUE
FB_B_MA<11>
TRUE
TP_CPU_PECI_MCP
TP_CPU_TEST3
TP_ENET_INTR_L
TP_FW643_AVREG
TP_MEM_A_A<15>
TP_MEM_A_CKE<3>
TP_MEM_A_CLK2N
TP_MEM_A_CLK3N
TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>
TP_MEM_B_CLK2P
TP_MEM_B_CLK5N
TP_MEM_B_ODT<3>
TP_GPU_BUFRST_L
TP_GPU_GSTATE<0>
TP_GPU_GSTATE<1>
TP_GPU_MIOA_D<9..0>
TP_GPU_MIOA_DE
TP_MCP_BUF_SIO_CLK
TP_MCP_GPIO_18
NC_MCP_KBDRSTIN_L
TRUE
MAKE_BASE=TRUE
NC_MCP_SATALED_L
TRUE
MAKE_BASE=TRUE
TP_MCP_SATALED_L
NC_SATA_F_D2RN
MAKE_BASE=TRUE
TRUE
NC_SATA_E_R2D_CP
MAKE_BASE=TRUE
TRUE
TRUE
PP3V3_S5_AVREF_SMC
PP18V5_S3
TRUE
PPDCIN_G3H
TRUE
PPVCORE_S0_MCP
TRUE
PPMCPDDR_ISNS
TRUE
PPVTTDDR_S3
TRUE
TRUE
PP1V8_S0GPU_ISNS
TRUE
PPVCORE_GPU
PP5V_S3
TRUE
TRUE
PP5V_S0
PPVCORE_S0_CPU
TRUE
TRUE
PPVCORE_S0_MCP
TRUE
PP3V3_S5
PP3V3_S0
TRUE
PP2V5_S0
TRUE
PP1V2_S0
TRUE
PP3V3_S3
TRUE
TRUE
PLT_RESET_SWITCH_L
TRUE
BKL_SYNC
TRUE
PP3V3_SW_LCD
=PP3V3_S0_DDC_LCD
TRUE
TRUE
PPVOUT_S0_LCDBKLT
LVDS_DDC_CLK
TRUE
TRUE
PP5V_S3_RTUSB_B_F
TRUE
BKL_FB
FSB_HITM_L
TRUE
LVDS_A_DATA_P<0>
TRUE
TP_PCI_AD<31..8>
TP_PCI_GNT0_L
TP_PCI_INTZ_L
TP_PCI_PAR
TP_PCI_SERR_L
TP_PCIE_CLK100M_PE4P
TP_SATA_C_D2RP
TP_SATA_C_D2RN
TRUE
PP1V8_GPUIFPX
LCD_BKLT_PWM
TRUE
TRUE
SMC_LID_R
PP3V42_G3H_LIDSWITCH_R
TRUE
TRUE
SMC_ONOFF_L
TRUE
LPCPLUS_GPIO
TRUE
ISSP_SDATA_P1_0
TRUE
ISSP_SCLK_P1_1
BKL_SDA
TRUE
TRUE
BKL_SCL
SMC_RESET_L
TRUE
WS_KBD18
TRUE
TRUE
WS_KBD17
TRUE
USB_LT3_N
USB_LT2_P
TRUE
SMC_RX_L
TRUE
TRUE
PM_SYSRST_L
WS_KBD19
TRUE
TRUE
SPI_ALT_CS_L
SMC_TDI
TRUE
SMC_NMI
TRUE
TP_SATA_F_D2RP
TP_SATA_F_R2D_CN
TP_SB_A20GATE
TP_SMC_P41
TP_USB_11P
TP_USB_EXTDP
TP_USB_MININ
TP_USB_MINIP
TP_USB_EXTDN
TP_USB_11N
TP_USB_10P
TP_SATA_F_R2D_CP
TP_SATA_F_D2RN
TP_SATA_E_R2D_CN
TP_SATA_E_D2RP
TP_SATA_E_D2RN
TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN
TP_SATA_D_D2RP
TP_SATA_D_D2RN
TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN
TP_PSOC_P1_3
TP_PEX_CLKREQ_L
TP_PE4_CLKREQ_L
TP_PCIE_PE4_D2RP
TP_PCIE_CLK100M_PE6N
TP_PCIE_CLK100M_PE5P
PP3V3_ENET_PHY
TRUE
PICKB_L
TRUE
PSOC_MISO
TRUE
PSOC_MOSI
TRUE
PSOC_SCLK
TRUE
SMC_KDBLED_PRESENT_L
TRUE
KBDLED_ANODE
TRUE
PP5V_S0_HDD_FLT
TRUE
SATA_ODD_R2D_N
TRUE
SATA_ODD_R2D_P
TRUE
SATA_ODD_D2R_C_N
TRUE
SATA_ODD_D2R_C_P
TRUE
SMC_ODD_DETECT
TRUE
LED_RETURN_6
TRUE
LED_RETURN_4
TRUE
LED_RETURN_3
TRUE
LED_RETURN_2
TRUE
LED_RETURN_1
TRUE
LVDS_CONN_B_CLK_F_N
TRUE
LVDS_CONN_B_CLK_F_P
TRUE
LVDS_CONN_B_DATA_N<2>
TRUE
LVDS_CONN_B_DATA_P<2>
TRUE
LVDS_CONN_B_DATA_N<1>
TRUE
LVDS_CONN_B_DATA_P<1>
TRUE
LVDS_CONN_B_DATA_P<0>
TRUE
LVDS_CONN_A_CLK_F_N
TRUE
LVDS_CONN_A_CLK_F_P
TRUE
LVDS_CONN_A_DATA_N<2>
TRUE
LVDS_CONN_A_DATA_P<2>
TRUE
LVDS_CONN_A_DATA_N<1>
TRUE
LVDS_CONN_A_DATA_P<1>
TRUE
LVDS_DDC_DATA
TRUE
SPKRAMP_R2_OUT_N
TRUE
SPKRAMP_R2_OUT_P
TRUE
TRUE
SPKRAMP_R1_OUT_N
TRUE
SPKRAMP_LFE_OUT_N
TRUE
SPKRAMP_L2_OUT_P
TRUE
SPKRAMP_L1_OUT_N
BI_MIC_HI
TRUE
BI_MIC_SHIELD
TRUE
TRUE
FAN_RT_TACH
TRUE
FAN_RT_PWM
TRUE
FAN_LT_TACH
FAN_LT_PWM
TRUE
TRUE
=PP5V_S0_FAN_LT
TRUE
PP3V3_S0GPU
TRUE
PP0V9R0V75_S0_DDRVTT
PP1V8R1V5_S0
TRUE
LVDS_A_DATA_N<0>
TRUE
LVDS_B_CLK_P
TRUE
TRUE
PP3V42_G3H
TRUE
PPMCPDDR_ISNS
PP1V05_S0
TRUE
PP1V8_S0
TRUE
PPBUS_G3H
TRUE
PM_SLP_S3_L
TRUE
TRUE
PPBUS_CPU_IMVP_ISNS
TRUE
WS_KBD11
WS_KBD13
TRUE
TRUE
PCIE_CLK100M_EXCARD_CONN_N
TRUE
PCIE_EXCARD_R2D_P
PCIE_EXCARD_D2R_P
TRUE
TRUE
EXCARD_CLKREQ_CONN_L
TRUE
EXCARD_CPPE_L
TRUE
EXCARD_CPUSB_L
SMBUS_MCP_0_DATA
TRUE
TRUE
SMBUS_MCP_0_CLK
TRUE
WS_KBD5
TRUE
WS_KBD3
TRUE
WS_KBD4
WS_KBD8
TRUE
WS_KBD10
TRUE
TP_MEM_A_CKE<2>
TP_MEM_A_CLK2P
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK2P
NC_MEM_A_CLK3N
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK3P
TRUE
MAKE_BASE=TRUE
TRUE
NC_MEM_A_CLK2N
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TRUE
NC_MEM_A_CKE<3>
MAKE_BASE=TRUE
TRUE
NC_MEM_A_CKE<2>
MAKE_BASE=TRUE
TRUE
NC_MEM_A_A<15>
MAKE_BASE=TRUE
TRUE
NC_FW643_TDI
MAKE_BASE=TRUE
TRUE
NC_FW643_AVREG
MAKE_BASE=TRUE
TRUE
NC_CPU_TEST3
TRUE
NC_FW0_TPAP
TRUE
NC_FW2_TPAP
TRUE
USB_CAMERA_CONN_P
SMBUS_SMC_A_S3_SDA
TRUE
LED_RETURN_5
TRUE
SPKRAMP_R1_OUT_P
TRUE
TP_PCI_INTW_L
PP5V_S3_BTCAMERA_F
TRUE
TRUE
PCIE_WAKE_L
MINI_CLKREQ_Q_L
TRUE
PCIE_CLK100M_MINI_CONN_N
TRUE
BI_MIC_LO
TRUE
SPKRAMP_LFE_OUT_P
TRUE
TRUE
PP5V_WLAN
LVDS_CONN_A_DATA_N<0>
TRUE
TRUE
NC_ALS_GAIN
TRUE
NC_ESTARLDO_EN
NC_FW0_TPBN
TRUE
NC_FW2_TPAN
TRUE
TRUE
NC_FW0_TPBP
TRUE
NC_FW2_TPBIAS
NC_FW2_TPBN
TRUE
TRUE
NC_FW2_TPBP
TRUE
NC_SMC_FAN_2_CTL
TRUE
NC_SMC_FAN_3_CTL
NC_USB_MINIP
MAKE_BASE=TRUE
TRUE
TP_XDP_OBSDATA_B3 NC_XDP_OBSDATA_B3
MAKE_BASE=TRUE
TRUE
TP_XDP_OBSDATA_B2 NC_XDP_OBSDATA_B2
MAKE_BASE=TRUE
TRUE
NC_USB_MININ
MAKE_BASE=TRUE
TRUE
NC_USB_EXTDP
MAKE_BASE=TRUE
TRUE
NC_USB_EXTDN
MAKE_BASE=TRUE
TRUE
NC_USB_11P
MAKE_BASE=TRUE
TRUE
NC_USB_11N
MAKE_BASE=TRUE
TRUE
NC_USB_10P
MAKE_BASE=TRUE
TRUE
NC_SMC_P41
MAKE_BASE=TRUE
TRUE
NC_SB_A20GATE
MAKE_BASE=TRUE
TRUE
NC_SATA_F_D2RP
MAKE_BASE=TRUE
TRUE
NC_SATA_F_R2D_CN
MAKE_BASE=TRUE
TRUE
NC_SATA_F_R2D_CP
MAKE_BASE=TRUE
TRUE
TP_SATA_E_R2D_CP
NC_SATA_E_R2D_CN
MAKE_BASE=TRUE
TRUE
NC_SATA_E_D2RP
MAKE_BASE=TRUE
TRUE
NC_SATA_E_D2RN
MAKE_BASE=TRUE
TRUE
NC_SATA_D_R2D_CP
MAKE_BASE=TRUE
TRUE
NC_SATA_D_R2D_CN
MAKE_BASE=TRUE
TRUE
NC_SATA_C_R2D_CP
MAKE_BASE=TRUE
TRUE
NC_SATA_D_D2RN
MAKE_BASE=TRUE
TRUE
NC_SATA_D_D2RP
MAKE_BASE=TRUE
TRUE
NC_SATA_C_R2D_CN
MAKE_BASE=TRUE
TRUE
NC_SATA_C_D2RP
MAKE_BASE=TRUE
TRUE
NC_SATA_C_D2RN
MAKE_BASE=TRUE
TRUE
NC_PSOC_P1_3
MAKE_BASE=TRUE
TRUE
NC_PEX_CLKREQ_L
MAKE_BASE=TRUE
TRUE
NC_PE4_CLKREQ_L
MAKE_BASE=TRUE
TRUE
NC_PCIE_PE4_D2RP
MAKE_BASE=TRUE
TRUE
NC_PCIE_CLK100M_PE6N
MAKE_BASE=TRUE
TRUE
TP_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE6P
MAKE_BASE=TRUE
TRUE
TP_PCIE_PE4_D2RN NC_PCIE_PE4_D2RN
MAKE_BASE=TRUE
TRUE
NC_PCIE_CLK100M_PE5P
MAKE_BASE=TRUE
TRUE
TP_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5N
MAKE_BASE=TRUE
TRUE
NC_PCIE_CLK100M_PE4P
MAKE_BASE=TRUE
TRUE
TP_PCI_TRDY_L NC_PCI_TRDY_L
MAKE_BASE=TRUE
TRUE
TP_PCI_STOP_L NC_PCI_STOP_L
MAKE_BASE=TRUE
TRUE
NC_PCI_SERR_L
MAKE_BASE=TRUE
TRUE
TP_PCI_RESET1_L NC_PCI_RESET1_L
MAKE_BASE=TRUE
TRUE
TP_PCI_PERR_L NC_PCI_PERR_L
MAKE_BASE=TRUE
TRUE
TP_PCI_IRDY_L NC_PCI_IRDY_L
MAKE_BASE=TRUE
TRUE
NC_PCI_PAR
MAKE_BASE=TRUE
TRUE
TP_PCI_INTY_L
TP_PCI_INTX_L
NC_PCI_INTW_L
TRUE
MAKE_BASE=TRUE
TP_PCI_GNT1_L NC_PCI_GNT1_L
MAKE_BASE=TRUE
TRUE
NC_PCI_GNT0_L
MAKE_BASE=TRUE
TRUE
TP_PCI_C_BE_L<3..0>
SMC_TX_L
TRUE
TRUE
FSB_HIT_L
FSB_A_L<31..3>
TRUE
TRUE
FSB_DRDY_L
FSB_DSTB_L_N<3..0>
TRUE
TRUE
SMC_MD1
TRUE
FSB_ADSTB_L<1..0>
FSB_D_L<63..0>
TRUE
TRUE
FSB_DBSY_L
TRUE
WS_KBD1
TRUE
WS_KBD2
WS_KBD9
TRUE
SPI_ALT_MISO
TRUE
TRUE
FSB_DSTB_L_P<3..0>
PP3V42_G3H
TRUE
TRUE
SPI_ALT_MOSI
MAKE_BASE=TRUE
TRUE
NC_ENET_INTR_L
MAKE_BASE=TRUE
TRUE
NC_ENET_PWRDWN_L
TRUE
MAKE_BASE=TRUE
NC_CPU_PECI_MCP
TP_FW643_TDI
TP_ENET_PWRDWN_L
DEBUG_RESET_L
TRUE
TP_MCP_KBDRSTIN_L
TP_LVDS_IG_BKL_PWM
TP_LVDS_IG_B_CLKP
TP_LVDS_IG_B_CLKN
TP_LVDS_EG_BKL_PWM
TP_LVDS_EG_B_CLK_P
TP_LVDS_EG_B_CLK_N
NC_MCP_BUF_SIO_CLK
TRUE
MAKE_BASE=TRUE
NC_MCP_GPIO_18
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKN
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_B_CLKP
TRUE
MAKE_BASE=TRUE
NC_LVDS_IG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_BKL_PWM
TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_B_CLK_P
TRUE
MAKE_BASE=TRUE
NC_GPU_VCORE_VID3
TRUE
MAKE_BASE=TRUE
NC_LPC_DRQ0_L
TRUE
MAKE_BASE=TRUE
NC_LVDS_EG_B_CLK_N
TRUE
MAKE_BASE=TRUE
NC_GPU_GSTATE<0>
TRUE
MAKE_BASE=TRUE
TP_MLB_RAM_VENDOR
TP_MLB_RAM_SIZE
TP_MEM_B_ODT<2>
TP_MEM_B_CS_L<3>
TP_MEM_B_CS_L<2>
TP_MEM_B_CLK5P
TP_MEM_B_CLK4P
TP_MEM_B_CLK4N
TP_MEM_B_CLK3P
TP_MEM_B_CLK3N
TP_MEM_B_CKE<2>
TP_MEM_B_A<15>
TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>
TP_MEM_A_CLK5P
NC_GPU_BUFRST_L
TRUE
MAKE_BASE=TRUE
NC_MLB_RAM_VENDOR
TRUE
MAKE_BASE=TRUE
NC_MLB_RAM_SIZE
TRUE
MAKE_BASE=TRUE
NC_MEM_B_ODT<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_ODT<3>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK5P
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CS_L<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CS_L<3>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK4P
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK5N
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK4N
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK3P
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK3N
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CKE<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_B_CLK2P
TRUE
MAKE_BASE=TRUE
NC_MEM_B_A<15>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_ODT<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_ODT<3>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CS_L<3>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CS_L<2>
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK5P
TRUE
MAKE_BASE=TRUE
TP_MEM_A_CLK4N
TP_MEM_A_CLK3P
TP_MEM_A_CLK4P
TP_MEM_A_CLK5N NC_MEM_A_CLK5N
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK4P
TRUE
MAKE_BASE=TRUE
NC_MEM_A_CLK4N
TRUE
MAKE_BASE=TRUE
SYS_LED_ANODE
TRUE
USB2_LT1_N
TRUE
USB2_LT1_P
TRUE
WS_KBD6
TRUE
PP1V5_S0_EXCARD_SWITCH
TRUE
PP5V_S3_RTUSB_A_F
TRUE
TRUE
WS_KBD15_CAP
TRUE
PCIE_MINI_R2D_N
TRUE
WS_KBD21
LPC_CLK33M_LPCPLUS
TRUE
LPC_FRAME_L
TRUE
WS_KBD20
TRUE
TRUE
PCIE_MINI_D2R_P
PCIE_CLK100M_MINI_CONN_P
TRUE
PP1V8R1V5_S3
TRUE
TRUE
MCPTHMSNS_D_N
TRUE
PCIE_EXCARD_R2D_N
CONN_USB2_BT_P
TRUE
USB_CAMERA_CONN_N
TRUE
Z2_MISO
TRUE
TRUE
PP1V1_S0GPU
TRUE
WS_KBD7
Z2_BOOST_EN
TRUE
Z2_BOOT_CFG1
TRUE
TRUE
Z2_RESET
PSOC_F_CS_L
TRUE
TRUE
PP1V8_S0GPU_ISNS_R
Z2_CLKIN
TRUE
TRUE
Z2_KEY_ACT_L
SMBUS_SMC_A_S3_SCL
TRUE
TRUE
PP1V2R1V05_ENET
PPVP_FW
TRUE
TRUE
PP1V0_FW
PP5V_SW_ODD
TRUE
LVDS_CONN_B_DATA_N<0>
TRUE
SMBUS_SMC_A_S3_SDA
TRUE
PPVBAT_G3H_CONN_F
TRUE
SMC_BS_ALRT_L
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SMBUS_SMC_BSA_SCL
TRUE
ADAPTER_SENSE
TRUE
PP18V5_DCIN_FUSE
TRUE
TRUE
PP3V42_G3H
TRUE
PP3V3_S3
SMC_TDO
TRUE
SMC_TRST_L
TRUE
LPC_SERIRQ
TRUE
LPC_PWRDWN_L
TRUE
SMC_TCK
TRUE
SPI_ALT_CLK
TRUE
SMC_TMS
TRUE
TRUE
SMBUS_SMC_A_S3_SCL
FSB_DINV_L<3..0>
TRUE
PP5V_S3_RTUSB_C_F
TRUE
TRUE
USB2_EXCARD_CONN_P
TRUE
SMBUS_SMC_BSA_SDA
TRUE
SMBUS_SMC_BSA_SCL
SMC_BIL_BUTTON_DB_L
TRUE
SATA_HDD_D2R_C_P
TRUE
SATA_HDD_D2R_C_N
TRUE
SATA_HDD_R2D_N
TRUE
SATA_HDD_R2D_P
TRUE
PCIE_EXCARD_D2R_N
TRUE
TRUE
MCPTHMSNS_D_P
SYS_LED_ANODE_R
TRUE
LPC_AD<0..3>
TRUE
PM_CLKRUN_L
TRUE
PPCPUVTT_S0
TRUE
TRUE
CONN_USB2_BT_N
PP3V3_S3_LDO
TRUE
PP18V5_S3
TRUE
TRUE
TPAD_GND_F
TRUE
Z2_DEBUG3
Z2_CS_L
TRUE
TRUE
PCIE_CLK100M_EXCARD_CONN_P
LVDS_CONN_A_DATA_P<0>
TRUE
MINI_RESET_CONN_L
TRUE
PP1V2R1V05_S5
TRUE
TP_PCI_CLK0
TRUE
PCIE_WAKE_L
TRUE
PP3V3_S0_EXCARD_SWITCH
TRUE
PP3V3_S3_EXCARD_SWITCH
USB2_EXCARD_CONN_N
TRUE
TRUE
FSB_LOCK_L
SPIROM_USE_MLB
TRUE
TRUE
LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>
TRUE
LVDS_EG_A_DATA_N<2>
TRUE
TRUE
USB_LT2_N
WS_KBD12
TRUE
TRUE
WS_KBD14
TRUE
WS_KBD16_NUM
84 82 67
91
91
95
95
95
95
95
43
41
91
91
31
43
84
84
31
88
88
90
96
96
79
80
80
80
95
80
96
78
88
95
49
43
42
43
95
95
95
95
95
95
95
95
95
96
96
96
96
96
96
95
95
42
36
90
44
44
94
96
30
96
95
42
88
88
88
88
88
88
88
88
42 91
43
90
94
95
94
59
94
94
42
43
43
43
43
43
94
88
94
94
90
43
43
95
30
88
95
95
95
14
14
90
30
57
57
98
72
73
73
73
73
73
42
50
8
8
8
96
9
8
85
75
85
81
14
84
85
42
43
42
98
96
41
41
42
43
50
50
50
50
90
90
90
90
41
85
85
85
85
85
95
95
81
81
81
81
81
95
95
81
81
81
81
81
57
57
57
57
57
57
58
58
48
84
84
8
8
45
33
96
90
31
21
21
96
44
85
57
17
96
58
57
81
41
14
14
14
14
43
14
14
14
14
8
43
42
96
96
90
43
41
30
96
96
90
96
96
50
50
50
50
50
50
44
81
44
42
44
44
8
8
42
43
41
41
42
42
44
14
96
44
44
59
90
90
90
90
31
96
41
41
96
50
50
50
96
81
17
96
14
84
84
84
96
42
42
10
19
10
74
75
19
19
19
49
49
49
49
49
49
30
17
56
56
96
40
40
85
71
71
71
71
71
71
9
10
18
35
9
16
15
16
16
16
15
16
16
74
75
75
75
75
21
17
20
41
7
8
7
7
8
8
8
8
8
8
7
8
8
8
8
7
31
78
78
8
78
78
39
10
81
19
19
19
19
19
17
20
20
8
84
40
40
41
18
49
49
41
49
49
96
39
39
25
49
43
41
41
20
20
21
42
20
9
9
9
9
20
20
20
20
20
20
20
20
20
20
20
20
20
49
69
17
17
17
17
8
49
49
49
49
50
50
38
38
38
38
38
38
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
78
56
56
56
56
56
56
57
57
48
48
48
48
8
8
8
8
81
81
7
7
8
8
8
21
8
49
49
31
31
17
31
31
31
13
13
49
49
49
49
49
16
15
37
37
30
7
78
56
19
30
7
30
30
57
56
30
78
42
42
37
37
37
37
37
37
42
42
13
13
20
17
17
17
19
19
19
19
19
19
19
19
19
39
10
10
10
10
41
10
10
10
49
49
49
43
10
7
43
35
18
25
21
9
9
9
75
75
75
21
21
16
16
16
16
16
16
16
16
16
9
16
16
16
16
16
16
16
40
39
39
49
31
39
49
30 49
25
19
49
17
30
8
47
31
30
30
49
8
49
50
49
49
49
8
49
49
7
8
8
8
38
78
7
59
41
7
7
59
59
7
7
41
41
19
19
41
43
41
7
10
98
31
7
7
42
38
38
38
38
17
47
40
19
19
8
30
50
7
50
49
49
31
78
30
8
19
7
31
31
31
10
43
81
81
76
39
49
49
49
Preliminary
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
"FW" (FireWire) Rails
500 mA max supply
"GPU" Rails
OR 0.75V
ENET Rails
190 mA
1.8V/DDR 1.5V Rails
5V Rails
Chipset "VCore" Rails
3.3V-2.5V Rails
(1.1V for A01)
1182 mA
4500 mA
139 mA/ 0 mA
105 mA/241 mA
1034 mA
5300 mA
241 mA max load
130 mA
500 mA
4771 mA
"G3Hot" (Always-Present) Rails
051-7656
SYNC_DATE=05/07/2008
8
123
31
SYNC_MASTER=RXU_K20
Power Aliases
=PP3V3_S0_MCP_PLL_VLDO
=PP3V3_GPU_SMBUS_SMC_0_S0
=PP3V3_S0_TPAD
=PP3V3_FW_FWPHY
=PP3V3_FW_P1V0FW
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=6V
MIN_LINE_WIDTH=0.4 mm
PPBUS_G3H
=PPVIN_S5_P5VP3V3
=PPVIN_S0_CPUVTTS0
=PPBUS_S0_LCDBKLT
=PPVIN_S0_P5VRTS0_MCPCORE
=PPVIN_S0GPU_P1V8P1V1
=PPVIN_S0_P1V05S5
=PP3V3_S5_SMC
=PP3V42_G3H_PWRCTL
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V
PP3V42_G3H
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MM
=PPVIN_S5_CPU_IMVP_ISNS
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.5 MM
MAKE_BASE=TRUE
PP1V8_S0
MIN_NECK_WIDTH=0.2 MM
=PP1V8R1V5_S0_MCP_MEM
=PP1V8_S0_REG
=PP3V3R1V8_S0_MCP_IFP_VDD
=PP1V8_S0_MCP_PLL_VLDO
=PP1V5_S0_VMON
=PP1V8R1V5_S0_FET
=PPMCPDDR_ISNS_R
=PP1V5_S0_CPU
=PP1V5_S3_MEMRESET
=PP1V5_S3_MEM_B
=PP1V5_S3_MEM_A
=PPVIN_S0_DDRREG_LDO
=PPDDR_S3_REG
=PP1V8R1V5_S0_MCP_FET
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.5V
PP1V8R1V5_S0
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
PP1V8R1V5_S3
MAKE_BASE=TRUE
VOLTAGE=1.5V
=PP3V3_S5_REG
=PP3V3_S0_LCD
=PP3V3_S0_P3V3S0FET
=PP3V3_S5_ROM
=PP1V5_EXP_S0
=PP1V05_S0_FET
=PP3V3_S0_BATTCHARGERTMPSNSR
=PP3V3_S0_CPUTHMSNS
=PP3V3_S0_FAN_RT
=PP3V3_S0_GPU1V8ISNS
=PPVIN_S5_FWPWRSW
PP1V05_S0
MAKE_BASE=TRUE
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_HDMI_VDD
=PP1V05_S0_VMON
=PP1V05_S0_MCP_PLL_PEX_UF
=PP1V05_S0_MCP_PLL_UF
=PP1V5_S0_EXCARD
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
PP1V5_EXP_S0
VOLTAGE=1.5V
=PP1V05_S0_MCP_FSB
=PP1V05_S0_SMC_LS
=PP1V05_S0_CPU
=PPCPUVTT_S0_REG
=PP1V05_S5_P1V05S0FET
=PP1V05_ENET_P1V05ENETFET
=PP1V05_S5_MCP_VDD_AUXC
=PP1V05_S5_MCP
PP1V05_S0_MCP_SATA_AVDD
MAKE_BASE=TRUE
=PP1V05_S0_MCP_SATA_AVDD0
PP1V05_S0_MCP_PEX_AVDD
MAKE_BASE=TRUE
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_SATA_DVDD0
=PP1V05_S0_MCP_PEX_AVDD1
=PP1V05_S0_MCP_PEX_DVDD1
PP1V05_S0_MCP_PLL_UF
MIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
=PP1V5_S0_MEM_B
=PPMCPDDR_ISNS
=PP1V5_S0_MEM_A
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
PPCPUVTT_S0
MAKE_BASE=TRUE
VOLTAGE=1.05V
PP1V2R1V05_S5
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
VOLTAGE=1.05V
=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_DVDD0
MAKE_BASE=TRUE
VOLTAGE=1.5V
PPMCPDDR_ISNS
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
=PP3V3_S5_MEMRESET
=PP3V3_S0_DPCONN
=PP3V3_S0_P1V2P2V5
=PP3V3_S0_MCP_GPIO
=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR
=PP3V3_S0_MCPDDRISNS
=PP3V3_S5_MCPPWRGD
=PP3V3_FW_LATEVG_ACTIVE
=PPVCORE_S0_CPU
=PPVOUT_FW_FWPWRSW
=PPSPD_S0_MEM_B
VOLTAGE=5V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 mm
PP5V_S3
MIN_LINE_WIDTH=0.5 mm
=PP5V_S3_RTUSB
=PP5V_S3_TPAD
=PP5V_S3_VTTCLAMP
=PP5V_S0_HDD
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
MAKE_BASE=TRUE
PPVCORE_S0_MCP
VOLTAGE=1.05V
=PP3V42_G3H_BMON_ISNS
=PP3V3_S5_RTC_D
=PP5V_S3_AUDIO_PWR
=PP5V_S3_MCPDDRFET
=PP5V_S3_P1V05S0FET
=PP5V_S3_GPUVCORE
=PP5V_S0_ODD
=PP5V_S0_CPUVTTS0
=PP5V_S0_CPU_IMVP
=PP3V3_S0_SMBUS_MCP_1
=PP5V_S3_REG
=PP5V_S0_REG
=PP5V_S0_FAN_RT
=PP3V42_G3H_LIDSWITCH
=PP5V_S3_WLAN
VOLTAGE=3.3V
PP3V3_S0GPU
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.20MM
=PP3V3_S5_LPCPLUS
=PP3V42_G3H_CHGR
=PP3V42_G3H_REG
=PPVIN_S5_SMCVREF
=PP3V42_G3H_BATT
MAKE_BASE=TRUE
VOLTAGE=2.5V
PP2V5_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V
MAKE_BASE=TRUE
PPVCORE_S0_CPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
PPBUS_FW_FWBOOST
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
MAKE_BASE=TRUE
VOLTAGE=6V
PP10V_FW
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=10V
MAKE_BASE=TRUE
PPVP_FW
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=10V
MAKE_BASE=TRUE
=PPBOOST_S5_FW_FET
=PFWBOOST_REG
=PPVIN_PFWBOOST
VOLTAGE=0.75V
MAKE_BASE=TRUE
PPVTTDDR_S3
MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0.9V
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=2 mm
PP0V9R0V75_S0_DDRVTT
MAKE_BASE=TRUE
=PPVTT_S0_DDR_LDO
=PPVTT_S3_DDR_BUF
=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP
=PP5V_S0GPU_P1V1P1V8_GPU
=PP1V2_S0_GMUX
=PP2V5_S0_GMUX
VOLTAGE=1.2V
MAKE_BASE=TRUE
PP1V2_S0
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PP1V8_GPU_REG
=PP1V8_S0GPU_ISNS_R
=PPVCORE_GPU
VOLTAGE=1.2V
MAKE_BASE=TRUE
PPVCORE_GPU
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PP3V3_GPU_VDD33
=PPVCORE_S0_MCP
VOLTAGE=1.05V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V2R1V05_ENET
VOLTAGE=3.3V
PP3V3_ENET_PHY
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_PHY
=PP3V3_ENET_PHY
=PP3V3_ENET_FET
=PP1V05_ENET_FET
=PP3V3_S0GPU_FET
=PP3V3_GPU_VCORELOGIC
=PP3V3_GPU_PWRCTL
=PP3V3_ENET_MCP_RMGT
=PP1V8_S0GPU_ISNS
=PP1V8_GPU_FBVDDQ
=PP1V8_GPU_FB_VDD
=PP3V3_GPU_P1V8S0
=PP1V8_GPU_FBIO
=PP1V8_GPU_FB_VDDQ
=PP1V1_GPU_PEX_IOVDD
=PP1V1_S0GPU_REG
=PP1V8_GPU_IFPX
=PP1V8_GPUIFPX_REG
PP1V1_S0GPU
VOLTAGE=1.1V
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
=PP1V2_S0_REG
=PPMCPCORE_S0_REG
=PP18V5_DCIN_CONN
=PPVCORE_GPU_REG
VOLTAGE=1.8V
PP1V8_S0GPU_ISNS
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.25V
PP1V8_S0GPU_ISNS_R
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.8V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM
PP1V8_GPUIFPX
MAKE_BASE=TRUE
=PP1V1_GPU_IFPCD_IOVDD
=PP1V1_GPU_FBPLLAVDD
=PP1V1_GPU_VID_PLLVDD
=PP1V1_GPU_H_PLLVDD
=PP1V1_GPU_PLLVDD
=PP1V1_GPU_PEX_PLLXVDD
=PP1V1_GPU_PEX_IOVDDQ
=PP3V3_GPU_LVDS_DDC
=PP3V3_GPU_MIO
=PPBOOST_FW_FWPWRSW_F
=PP1V0_FW_FWPHY
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
MAKE_BASE=TRUE
VOLTAGE=1.0V
PP1V0_FW
=PPVCORE_S0_CPU_REG
=PP5V_S0_LPCPLUS
=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_SMCUSBMUX
=PP3V3_S0_LVDSDDCMUX
=PP3V3_S5_MCP_GPIO
=PP3V3_S0_AUDIO
=PP3V3_S0_MCP
=PP3V3_S0_MCP_DAC_UF
=PP3V3_S0_MCP_VPLL_UF
=PP3V3_S0_MCP_PLL_UF
=PP3V3R1V5_S0_MCP_HDA
=PP3V3_S0_HDCPROM
=PP3V3_S0_GMUX
=PPSPD_S0_MEM_A
=PP3V3_S0_DDC_LCD
=PP3V3_S0_PWRCTL
=PP3V3_S0_GPUTHMSNS
MAKE_BASE=TRUE
PPBUS_CPU_IMVP_ISNS
VOLTAGE=6V
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.4 MM
=PP5V_S0_FAN_LT
VOLTAGE=5V
PP5V_S0
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.6 MM
=PP3V3_S0_DPMUX
=PP3V3_S0_SMBUS_MCP_0
=PP3V42_G3H_TPAD
=PP3V42_G3H_CPUCOREISNS
=PP5V_S3_DDRREG
=PP5V_S3_IR
MIN_NECK_WIDTH=0.20MM
PP3V3_S0
MIN_LINE_WIDTH=0.3 MM
VOLTAGE=3.3V
MAKE_BASE=TRUE
=PP3V3_S0_FAN_LT
=PP1V0_FW_REG
=PP3V3_S0_SMC
=PP1V05_S0_MCP_PEX_DVDD
=PPVIN_GPU_GPUVCORE
=PP3V3_S3_P3V3S3FET
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S5_PWRCTL
=PP3V3_S5_P1V05FET
=PP3V3_S5_MCP
=PPBUS_G3H
=PPVBAT_G3H_P3V42G3H
=PPVIN_S3_DDRREG
=PPVIN_S5_CPU_IMVP_ISNS_R
=PP3V3_S0_IMVP
=PP3V3_S0_XDP
=PP3V3_S0_MCPCOREISNS
=PP3V3_S0_XDP
=PP3V3_S0_ODD
=PP3V3_S0_VMON
=PP3V3_S0_EXCARD
=PP3V3_S0_REMTHMSNS
=PP2V5_S0_REG
=PP5V_S3_SYSLED
=PP5V_S3_BTCAMERA
=PPDCIN_S5_CHGR
=PP3V3_S3_P1V5EXPS0
=PP3V3_S3_SMS
=PP3V3_S3_SMS
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_P1V8S0
=PP3V3_S3_TPAD
MAKE_BASE=TRUE
PP3V3_S5
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6 MM
=PP3V3_S3_FET
=PPVIN_S5_CPU_IMVP
PPDCIN_G3H
MAKE_BASE=TRUE
VOLTAGE=18.5V
MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM
=PP3V3_S3_BT
=PP3V3_S3_GMUX
=PP3V3_S5_P1V05ENETFET
=PP3V3_FW_LATEVG
=PPVIN_S0_KBDLED
=PPVIN_S5_BKL
MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
PP3V3_S3
=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO
=PP3V3_S3_VREFMRGN
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_EXCARD
=PP3V3_S0_SMBUS_SMC_B_S0
=PP3V3_S0_LPCPLUS
=PP3V3_S0_FET
61 13
80
23
12
80
79
51
22
11
21
45
75
45
79
73
58
23
78
96
13
13
37
45
42
42
23
24
12
52
68
23
23
24
66
14
10
23
23
19
12
98
63
74
23
23
23
73
72
77
75
20
57
22
23
75
48
9
23
23
8
8
51
51
96
66
44
50
35
66
7
62
65
86
64
83
66
41
67
7
45
7
16
66
18
66
67
68
46
11
29
28
27
63
63
68
7
7
62
78
68
43
66
66
47
47
48
46
36
7
23
8
8
18
67
23
23
31
9
42
6
65
68
33
22
66
23 20
23
8
20
17
17
28
46
27
7
7
17
17
7
29
82
87
18
33
82
46
25
36
11
36
28
7
39
50
68
38
7
45
25
9
68
68
77
38
65
61
44
62
64
48
40
30
7
43
60
59
42
59
7
7
7
36
66
66
7
7
63
26
27
28
68
83
84
84
7
83
46
70
7
6
22
7
7
23
18
32
32
33
33
68
77
67
18
46
70
72
66
71
9
69
83
76
66
7
87 64
59
45
7
7
7
76
71
74
74
74
69
69
81
74
36
35
7
61
43
37
37
44
39
81
18
53
21
24
24
23
21
24
84
27
7
67
47
7
7
7
81
44
49
45
63
40
7
48
66
42
8
77
68
68
67
68
22
60
59
63
45
61
6
46
6
38
67
31
47
87
42
30
60
66
8
8
44
66
49
7
68
61
7
30
84
33
37
50
7
30
21
26
44
31
44
43
68
Preliminary
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Frame Holes
Extra FSB Pull-ups
Exist in MRB but not Intel designs. Here for CYA.
Bosses for Flex Protector Bracket
Digital Ground
If found to be necessary, will move to page14.csa
TM Hole
TM Hole
Left CPU
TM Hole
GPU signals
TM Hole
ETHERNET ALIASES
CPU signals
AUDIO ALIASES
Right CPU
GMUX ALIASES
Bottom Left GPU
Thermal Module Holes
MCP79 PCIe PRSNT# Straps
Top GPU Right
ZT0980
STDOFF-4.5OD.98H-1.1-3.48-TH
2
1
R0930
47K
MF-LF
5%
402
1/16W
21
R0925
402
5%
1/16W
MF-LF
0
17
21
R0902
402
MF-LF
1/16W
5%
10K
2 1
XW0900
SM
2 1
XW0901
SM
21
R0900
402
1%
10
MF-LF
1/16W
21
R0901
402
10
MF-LF
1%
1/16W
ZT0981
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0982
STDOFF-4.5OD.98H-1.1-3.48-TH
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0983
ZT0984
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0985
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0986
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0987
STDOFF-4.5OD.98H-1.1-3.48-TH
ZT0945
3R2P5
1
1
ZT0960
3R2P5
1
ZT0989
STDOFF-4.5OD.98H-1.1-3.48-TH
1
ZT0988
STDOFF-4.5OD.98H-1.1-3.48-TH
1
ZT0991
STDOFF-4.5OD.98H-1.1-3.48-TH
21
R0926
402
0
MF-LF
5%
1/16W
17
84
21
R0927
NO STUFF
0
402
1/16W
5%
MF-LF
ZT0930
STDOFF-4.5OD.98H-1.1-3.48-TH
10 14 88
10 14 88
10 13 14 88
10 14 88
1/16W
2
1
R0960
5%
62
402
MF-LF
NO STUFF
1/16W
2
1
R0970
200
402
5%
MF-LF
NO STUFF
2
1
R0980
1/16W
MF-LF
1%
NO STUFF
402
150
MF-LF
2
1
R0990
1%
402
1/16W
150
NO STUFF
STDOFF-4.0OD3.0H-SM
1
ZT0934
1
ZT0931
STDOFF-4.0OD3.0H-SM
21
R0903
402
5%
1/16W
MF-LF
0
3R2P5
ZT0932
1
1
ZT0971
3R2P5
1
SH0913
SM
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0910
1
SM
1.4DIA-SHORT-EMI-MLB-M97-M98
1
SM
1.4DIA-SHORT-EMI-MLB-M97-M98
SH0912
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
SH0914
1
1
SH0911
1.4DIA-SHORT-EMI-MLB-M97-M98
SM
1
SH0900
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
SH0903
SM
2.0DIA-TALL-EMI-MLB-M97-M98
1
SH0902
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1/16W
NO STUFF
2
1
R0950
220
MF-LF
402
5%
10 14 61 88
1
SH0919
2.0DIA-TALL-EMI-MLB-M97-M98
SM
2.0DIA-TALL-EMI-MLB-M97-M98
1
SM
SH0917
SH0916
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
1
SH0918
SM
2.0DIA-TALL-EMI-MLB-M97-M98
1
SH0920
SM
1.4DIA-SHORT-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
1
SH0921
SM
1
SH0922
SM
2.0DIA-TALL-EMI-MLB-M97-M98
1.4DIA-SHORT-EMI-MLB-M97-M98
1
SH0923
SM
1
ZT0957
4.0OD1.65H-M1.6X0.35
ZT0958
1
4.0OD1.65H-M1.6X0.35
1
SH0901
2.0DIA-TALL-EMI-MLB-M97-M98
SM
1
ZT0915
3R2P5
SH0924
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
SH0930
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
SH0931
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
SH0932
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
SH0933
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
2.0DIA-TALL-EMI-MLB-M97-M98
SH0935
1
SM
2.0DIA-TALL-EMI-MLB-M97-M98
SH0934
1
SM
1
ZT0965
3R2P5
1
ZT0940
3R2P5
3R2P5
ZT0970
1
SYNC_DATE=09/24/2008
SYNC_MASTER=K20_MLB
051-7656
31
123
9
Signal Aliases
VOLTAGE=0V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
GND
GND_BATT_CHGND
=PP1V05_S0_MCP_SATA_DVDD1
=PP1V05_S0_MCP_SATA_AVDD1
=P1V5_EXP_S0_EN
MCP_MII_PD
MAKE_BASE=TRUE
PP3V3_S0
=MCP_MII_RXER
=PP1V8_GPU_FB_VDDQ
GMUX_INT
MAKE_BASE=TRUE
MAKE_BASE=TRUE
JTAG_GMUX_TDO
TP_LVDS_MUX_SEL_EG
MAKE_BASE=TRUE
LVDS_MUX_SEL_EG
PM_ALL_GPU_PGOOD
MAKE_BASE=TRUE
MAKE_BASE=TRUE
DP_IG_HPD
GMUX_JTAG_TDI
ALL_EG_PGOOD
FSB_BREQ0_L
GPU_FB_B_VREF_DIV
MAKE_BASE=TRUE
=PP1V8_GPU_FB_VREF_B
TP_LVDS_IG_BKL_PWM
MAKE_BASE=TRUE
=MCP_HDMI_DDC_DATA
=DVI_HPD_GMUX_INT
GMUX_JTAG_TDO
=PP5V_S3_AUDIO_PWR
MAKE_BASE=TRUE
HDA_BITCLK
NC_LVDS_IG_B_DATAN<3>
NO_TEST=TRUE
MAKE_BASE=TRUE
LVDS_IG_B_DATA_N<3>
LVDS_IG_B_DATA_P<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATAN<3>
LVDS_IG_A_DATA_N<3>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_LVDS_IG_A_DATAP<3>
LVDS_IG_A_DATA_P<3>
TP_LVDS_IG_B_CLKN
MAKE_BASE=TRUE
LVDS_IG_B_CLK_N
MAKE_BASE=TRUE
TP_LVDS_IG_B_CLKP
LVDS_IG_B_CLK_P
TP_CPU_PECI_MCP
MAKE_BASE=TRUE
CPU_PECI_MCP
MAKE_BASE=TRUE
TP_MEM_B_A<15>
MEM_B_A<15>
MAKE_BASE=TRUE
TP_MEM_A_A<15>
MEM_A_A<15>
TP_IMVP6_CLKEN_L
MAKE_BASE=TRUE
VR_PWRGD_CLKEN_L
=SPI_CS1_R_L_USE_MLB
MEM_VTT_EN
MAKE_BASE=TRUE
=DDRVTT_EN
CPU_BSEL<0..2>
MAKE_BASE=TRUE
=MCP_BSEL<0..2>
MAKE_BASE=TRUE
CPU_VID<0..6>
IMVP6_VID<0..6>
=RTL8211_REGOUT
MAKE_BASE=TRUE
NC_RTL8211_REGOUT
=RTL8211_ENSWREG
=PP3V3_ENET_PHY_VDDREG
SMC_MCP_SAFE_MODE
MAKE_BASE=TRUE
PM_SLP_RMGT_L
GPU_FB_A_VREF_DIV
MAKE_BASE=TRUE
CPU_DPRSTP_L
=PP1V8_GPU_FB_VREF_A
MAKE_BASE=TRUE
TP_USB_EXTDP
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PP5V_S3_AUDIO
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
PP5V_S3_AUDIO_AMP
USB_EXTD_P
USB_EXTD_N
TP_USB_MINIP
MAKE_BASE=TRUE
TP_USB_EXTDN
MAKE_BASE=TRUE
USB_MINI_P
USB_MINI_N
MAKE_BASE=TRUE
TP_USB_MININ
=PEG_D2R_P<0..15>
MAKE_BASE=TRUE
PEG_D2R_P<0..15>
=PEG_D2R_N<0..15>
MAKE_BASE=TRUE
PEG_D2R_N<0..15>
=PEG_R2D_C_P<0..15>
=PEG_R2D_C_N<0..15>
PEG_R2D_C_N<0..15>
MAKE_BASE=TRUE
LVDS_BKL_ON
LCD_BKLT_EN
MAKE_BASE=TRUE
=MCP_HDMI_TXC_P
MAKE_BASE=TRUE
DP_IG_ML_P<3>
=MCP_HDMI_TXC_N
DP_IG_ML_N<2..0>
MAKE_BASE=TRUE
DP_IG_DDC_DATA
MAKE_BASE=TRUE
=MCP_MII_CRS
=MCP_MII_COL
EG_CLKREQ_OUT_L
MAKE_BASE=TRUE
PCIE_FW_PRSNT_L
TP_SPI_CS1_R_L_USE_MLB
MAKE_BASE=TRUE
TP_PP3V3_ENET_PHY_VDDREG
MAKE_BASE=TRUE
=P1V05ENET_EN
MCP_SPKR
MAKE_BASE=TRUE
PEG_PRSNT_L
=MCP_HDMI_TXD_P<0..2>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_HPD
GPU_RESET_L
IG_BKLT_EN
IG_LCD_PWR_EN
MAKE_BASE=TRUE
LVDS_IG_PANEL_PWR
MAKE_BASE=TRUE
LVDS_IG_BKL_ON
NO_TEST=TRUE
NC_LVDS_IG_B_DATAP<3>
MAKE_BASE=TRUE
LVDS_IG_BKL_PWM
=PP1V05_S0_MCP_FSB
CPU_NMI
CPU_INTR
FSB_CPURST_L
MAKE_BASE=TRUE
AUD_IPHS_SWITCH_EN
HDA_BIT_CLK
=MCP_HDMI_TXD_N<0..2>
MAKE_BASE=TRUE
DP_IG_ML_P<2..0>
MAKE_BASE=TRUE
DP_IG_ML_N<3>
EG_RESET_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
JTAG_GMUX_TDI
DP_IG_DDC_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
PEG_R2D_C_P<0..15>
GMUX_JTAG_TMS
=P3V3ENET_EN
MAKE_BASE=TRUE
JTAG_GMUX_TMS
GND_CHASSIS_USB
GND_CHASSIS_RIGHTHS
GND_CHASSIS_SATA
GND_CHASSIS_TPAD
GND_CHASSIS_CLUTCH
GND_CHASSIS_DIMM
GND_CHASSIS_LVDS
80 79
23
96
73
22
8
72
84
90
90
90
90
90
90
43
68
88
88 88
55
91
91
91
91
90
90
90
90
90
81
14
58
91
90
90
84
81
90
84
20
20
66
7
18
8
84
6
84
67
81
19
84
26
73
7
18
18
17
8
53
18
18
18
18
7
18
7
18
7
14
7
28
7
27
61
21
25 63
10 14
11 61
32
32
32
41
21
26
72
7
53
56
20
20
7
7
20
20
7
17 69
17 69
17
17 69
86 84
18 81
18
81
75
18
18
33
21
18
18
18
69
84
84 18
18
18
8
19
21
18
81
81
84
6
75
69
19
33
6
Preliminary
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
OUT
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
OUT
BI
BI
BI
BI
LOCK*
INIT*
A20M*
A6*
A3*
A4*
A14*
A16*
REQ0*
REQ1*
REQ2*
REQ3*
REQ4*
BCLK1
BCLK0
THERMTRIP*
THERMDA
PROCHOT*
DBR*
TRST*
TMS
TDO
TDI
TCK
PREQ*
PRDY*
BPM3*
BPM2*
BPM1*
BPM0*
HITM*
HIT*
TRDY*
RS2*
RS1*
RS0*
RESET*
IERR*
BR0*
DBSY*
DRDY*
DEFER*
BNR*
RSVD4
RSVD3
RSVD2
RSVD1
RSVD0
SMI*
LINT1
LINT0
STPCLK*
FERR*
ADSTB1*
A35*
A34*
A33*
A32*
A31*
A30*
A29*
A28*
A19*
A18*
A17*
ADSTB0*
A13*
A12*
BPRI*
A20*
A21*
A22*
A23*
A24*
A26*
A27*
A9*
A8*
A7*
A11*
A25*
THERMDC
IGNNE*
ADS*
A10*
A15*
A5*
RSVD5
RSVD6
RSVD7
RSVD8
1 OF 4
CONTROL
THERMAL
XDP/ITP SIGNALS
H CLK
ADDR GROUP1
ICH
RESERVED
ADDR GROUP0
TEST7
TEST6
DSTBP1*
DINV1*
D31*
D30*
D25*
D11*
D12*
D13*
D14*
DSTBP0*
DINV0*
D9*
D8*
D7*
D6*
D19*
D18*
D0*
D32*
D1*
D2*
D5*
D16*
D20*
D21*
D22*
D23*
D24*
D26*
D27*
D28*
D29*
DSTBN1*
GTLREF
TEST3
TEST4
TEST5
BSEL0
BSEL1
BSEL2
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*
DSTBN2*
DSTBP2*
DINV2*
D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*
DSTBN3*
DSTBP3*
DINV3*
COMP0
COMP1
COMP2
COMP3
DPRSTP*
DPSLP*
DPWR*
PWRGOOD
SLP*
PSI*
D17*
D4*
D3*
DSTBN0*
D15*
D10*
TEST2
TEST1
2 OF 4
DATA GRP 3 DATA GRP 2
MISC
DATA GRP 0DATA GRP 1
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
PIN. MAKE SURE CPU_TEST4 IS
PLACE C1000 CLOSE TO CPU_TEST4
REFERENCED TO GND
0.5" MAX LENGTH FOR CPU_GTLREF
FSB_IERR_L WITH A GND
PLACE TESTPOINT ON
0.1" AWAY
GMCH WITHOUT T (NO STUB)
SHOULD CONNECT TO ICH AND
PM_THRMTRIP#
COMP1,3 CONNECT WITH ZO=55OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".
LAYOUT NOTE:
402
MF-LF
54.9
1/16W
1%
R1002
1
2
MF-LF
402
1/16W
5%
68
R1004
1
2
402
1K
MF-LF
1%
1/16W
R1005
1
2
402
1/16W
2.0K
MF-LF
1%
R1006
1
2
1/16W
MF-LF
1%
54.9
402
R1019
1 2
1%
MF-LF
1/16W
27.4
402
R1018
1 2
54.9
1/16W
MF-LF
1%
402
R1017
1 2
1/16W
MF-LF
1%
27.4
402
R1016
1 2
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
9
14 61 88
14 88
14 88
14 88
61
13 14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
9
88
9
88
9
88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
7
14 88
14 88
14 88
14 88
7
14 88
7
14 88
9
14 88
7
14 88
7
14 88
7
14 88
13 88
13 88
13 88
13 88
13 88
13 88
6
10 88
13 25
14 42 61 88
47 96
14 42 88
14 88
9
13 14 88
14 88
14 88
14 88
14 88
6
10 13 88
6
10 13 88
6
10 13 88
6
10 13 88
47 96
14 88
14 88
14 88
14 88
9
14 88
9
14 88
14 88
14 88
14 88
NOSTUFF
5%
MF-LF
1/16W
0
402
R1030
1 2
402
NOSTUFF
1K
MF-LF
5%
1/16W
R1007
1
2
402
54.9
MF-LF
1%
1/16W
R1003
1
2
54.9
1/16W
MF-LF
1%
402
R1020
1 2
1%
MF-LF
1/16W
54.9
402
R1021
1 2
1%
54.9
MF-LF
1/16W
402
R1022
1 2
14 88
14 88
14 88
14 88
1%
MF-LF
1/16W
402
649
R1023
1 2
402
MF-LF
NOSTUFF
5%
1/16W
1K
R1012
1
2
402
16V
10%
0.1uF
NOSTUFF
X5R
C1000
1
2
MF-LF
1/16W
1%
402
PLACEMENT_NOTE=Place R1024 near ITP connector (if present)
54.9
R1024
1 2
OMIT
PENRYN
FCBGA
U1000
N3
P5
P2
L2
P4
P1
R1
Y2
U5
R3
W6
A6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
J4
U2
V4
W3
AA4
AB2
AA3
L5
L4
K5
M3
N2
J1
H1
M1
V1
A22
A21
E2
AD4
AD3
AD1
AC4
G5
F1
C20
E1
H5
F21
A5
G6
E4
D20
C4
B3
C6
B4
H4
AC2
AC1
D21
K3
H2
K2
J3
L1
C1
F3
F4
G3
M4
N5
T2
V3
B2
F6
D2
D22
D3
A3
D5
AC5
AA6
AB3
A24
B25
C7
AB5
G2
AB6
OMIT
PENRYN
FCBGA
U1000
B22
B23
C21
R26
U26
AA1
Y1
E22
F24
J24
J23
H22
F26
K22
H23
N22
K25
P26
R23
E26
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
G22
T25
N25
Y22
AB24
V24
V26
V23
T22
U25
U23
F23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
AE24
AD24
G25
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
E25
AC22
AD23
AF22
AC23
E23
K24
G24
H25
N24
U22
AC20
E5
B5
D24
J26
L26
Y26
AE25
H26
M26
AA26
AF24
AD26
AE6
D6
D7
C23
D25
C24
AF26
AF1
A26
C3
CPU FSB
10
31
051-7656
123
SYNC_MASTER=M98_MLB
SYNC_DATE=04/01/2008
FSB_DSTB_L_N<3>
CPU_COMP<3>
CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>
CPU_TEST2
XDP_TMS
=PP1V05_S0_CPU
XDP_TDO
XDP_TDI
XDP_TCK
XDP_TRST_L
=PP1V05_S0_CPU
=PP1V05_S0_CPU
=PP1V05_S0_CPU
TP_CPU_RSVD8
TP_CPU_RSVD7
TP_CPU_RSVD6
TP_CPU_RSVD5
FSB_A_L<5>
FSB_A_L<15>
FSB_A_L<10>
FSB_ADS_L
CPU_IGNNE_L
CPU_THERMD_N
FSB_A_L<11>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<27>
FSB_A_L<26>
FSB_A_L<24>
FSB_A_L<23>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<20>
FSB_BPRI_L
FSB_A_L<12>
FSB_A_L<13>
FSB_ADSTB_L<0>
FSB_A_L<17>
FSB_A_L<19>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>
CPU_FERR_L
CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L
TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
FSB_BNR_L
FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L
FSB_BREQ0_L
CPU_IERR_L
FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L
FSB_HIT_L
FSB_HITM_L
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L
CPU_PROCHOT_L
CPU_THERMD_P
PM_THRMTRIP_L
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_REQ_L<0>
FSB_A_L<4>
FSB_A_L<3>
FSB_A_L<6>
CPU_A20M_L
CPU_INIT_L
FSB_LOCK_L
FSB_REQ_L<1>
CPU_TEST1
FSB_D_L<10>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<17>
CPU_PSI_L
FSB_CPUSLP_L
CPU_PWRGD
FSB_DPWR_L
CPU_DPSLP_L
CPU_DPRSTP_L
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<53>
FSB_D_L<52>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<48>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_D_L<47>
FSB_D_L<46>
FSB_D_L<45>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<38>
FSB_D_L<37>
FSB_D_L<36>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
CPU_BSEL<2>
CPU_BSEL<1>
CPU_BSEL<0>
TP_CPU_TEST5
CPU_TEST4
TP_CPU_TEST3
CPU_GTLREF
FSB_DSTB_L_N<1>
FSB_D_L<29>
FSB_D_L<28>
FSB_D_L<27>
FSB_D_L<26>
FSB_D_L<24>
FSB_D_L<23>
FSB_D_L<22>
FSB_D_L<21>
FSB_D_L<20>
FSB_D_L<16>
FSB_D_L<5>
FSB_D_L<2>
FSB_D_L<1>
FSB_D_L<32>
FSB_D_L<0>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<25>
FSB_D_L<30>
FSB_D_L<31>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
TP_CPU_TEST7
TP_CPU_TEST6
FSB_A_L<25>
FSB_A_L<18>
FSB_A_L<16>
FSB_A_L<14>
61
61
61
61
13
13
13
13
12
12
12
12
88
11
88
88
88
11
11
11
13
10
88
13
13
13
10
10
10
10
8
10
10
10
10
8
8
8
88
88
88
88
88
6
6
6
6
6
6
6
6
6
88
7
26
Preliminary
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
VCC
VCCP
VCCA
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VCCSENSE
VSSSENSE
VCC
3 OF 4
VSS VSS
4 OF 4
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
17.0 A (Auto-Halt/Stop-Grant SuperLFM)
30.4 A (LFM)
2500 mA (after VCC stable)
4500 mA (before VCC stable)
16.0 A (Deep Sleep SuperLFM)
16.8 A (Sleep SuperLFM)
41.0 A (HFM)
(CPU CORE POWER)
130 mA
(CPU IO POWER 1.05V)
(CPU INTERNAL PLL POWER 1.5V)
Low Voltage:
23.0 A (Design Target)
18.7 A (LFM)
TBD A (SuperLFM)
TBD A (Sleep SuperLFM)
TBD A (Deeper Sleep)
TBD A (Sleep HFM)
TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (HFM)
TBD A (LFM)
Current numbers from Merom for Santa Rosa EMTS, doc #22221.
TBD A (Auto-Halt/Stop-Grant LFM)
TBD A (Sleep LFM)
25.5 A (SuperLFM)
27.4 A (Sleep HFM)
25.0 A (Deep Sleep HFM)
11.5 A (Deeper Sleep)
9.4 A (Enhanced Deeper Sleep)
TBD A (Sleep HFM)
21.0 A (HFM)
TBD A (Deep Sleep HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)
TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Enhanced Deeper Sleep)
TBD A (Deeper Sleep)
TBD A (Deep Sleep LFM)
TBD A (Deep Sleep HFM)
TBD A (Deep Sleep SuperLFM)
27.4 A (Auto-Halt/Stop-Grant HFM)
44.0 A (Design Target)
Standard Voltage:
Ultra Low Voltage:
17.0 A (Design Target)
TBD A (Enhanced Deeper Sleep)
9
88
9
88
9
88
9
88
9
88
9
88
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
MF-LF
402
100
1%
1/16W
R1101
1
2
9
88
61 88
61 88
MF-LF
402
PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.
1/16W
1%
100
R1100
1
2
OMIT
PENRYN
FCBGA
U1000
A7
A9
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
A10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
A12
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
A13
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
A15
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
A17
AC10
AB10
AB12
AB14
AB15
AB17
AB18
AB20
AB7
AC7
A18
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
A20
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
B7
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
B26
C26
G21
V6
R21
R6
T21
T6
V21
W21
J6
K6
M6
J21
K21
M21
N21
N6
AF7
AD6
AF5
AE5
AF4
AE3
AF3
AE2
AE7
OMIT
PENRYN
FCBGA
U1000
A4
A8
B11
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
B13
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
B16
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
B19
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
B21
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
B24
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
C5
AF21
A25
AF25
B1
C8
C11
C14
A11
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
A14
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
A16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
A19
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
A23
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
AF2
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
B6
P3
P6
P21
P24
R2
R5
R22
R25
T1
T4
B8
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
SYNC_DATE=04/01/2008
SYNC_MASTER=M98_MLB
CPU Power & Ground
051-7656
31
11
123
=PPVCORE_S0_CPU
=PP1V05_S0_CPU
=PP1V5_S0_CPU
CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>
CPU_VCCSENSE_P
CPU_VCCSENSE_N
=PPVCORE_S0_CPU
61 13
45
12
45
12
10
12
11
8
12
11
8
6
8
8
Preliminary
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
WF: Consider sharing bulk cap with NB Vtt?
VCCA (CPU AVdd) DECOUPLING
1x 10uF, 1x 0.01uF
CPU VCORE HF AND BULK DECOUPLING
4x 330uF, 20x 22uF 0805
1x 470uF, 6x 0.1uF 0402
VCCP (CPU I/O) DECOUPLING
X5R-CERM
20%
22UF
6.3V
CRITICAL
603
C1206
1
2
CRITICAL
2.5V
D2T
20%
470UF
POLY
C1235
1
2 3
20%
22UF
6.3V
CRITICAL
603
X5R-CERM
C1204
1
2
CRITICAL
X5R-CERM
6.3V
20%
22UF
603
C1216
1
2
X5R-CERM
20%
6.3V
CRITICAL
603
22UF
C1214
1
2
X5R-CERM
20%
22UF
6.3V
CRITICAL
603
C1208
1
2
22UF
X5R-CERM
6.3V
20%
CRITICAL
603
C1203
1
2
X5R-CERM
20%
22UF
6.3V
CRITICAL
603
C1207
1
2
X5R-CERM
20%
22UF
6.3V
CRITICAL
603
C1202
1
2
6.3V
CRITICAL
22UF
20%
603
X5R-CERM
C1201
1
2
22UF
X5R-CERM
6.3V
20%
603
CRITICAL
C1213
1
2
X5R-CERM
20%
22UF
6.3V
CRITICAL
603
C1212
1
2
20%
22UF
6.3V
X5R-CERM
CRITICAL
603
C1211
1
2
X5R-CERM
22UF
20%
6.3V
CRITICAL
603
C1219
1
2
X5R-CERM
603
CRITICAL
6.3V
20%
22UF
C1200
1
2
X5R-CERM
CRITICAL
6.3V
20%
22UF
603
C1210
1
2
20%
0.1UF
CERM
402
10V
C1236
1
2
20%
6.3V
603
X5R-CERM
22UF
CRITICAL
C1205
1
2
X5R-CERM
22UF
6.3V
CRITICAL
20%
603
C1209
1
2
22UF
X5R-CERM
20%
6.3V
CRITICAL
603
C1215
1
2
22UF
20%
CRITICAL
603
X5R-CERM
6.3V
C1217
1
2
20%
CERM
402
0.1UF
10V
C1237
1
2
20%
CERM
402
0.1UF
10V
C1238
1
2
20%
CERM
402
0.1UF
10V
C1239
1
2
20%
CERM
402
0.1UF
10V
C1240
1
2
20%
CERM
402
0.1UF
10V
C1241
1
2
20%
22UF
6.3V
CRITICAL
603
X5R-CERM
C1218
1
2
PLACEMENT_NOTE=Place near CPU pin B26.
CERM
402
16V
10%
0.01UF
C1281
1
2
X5R
6.3V
20%
10uF
603
C1280
1
2
20%
D2T-SM2
POLY-TANT
2.0V
330UF
CRITICAL
PLACEMENT_NOTE=Place in CPU center cavity.
C1250
1
2 3
20%
D2T-SM2
POLY-TANT
PLACEMENT_NOTE=Place in CPU center cavity.
CRITICAL
330UF
2.0V
C1251
1
2 3
20%
POLY-TANT
CRITICAL
330UF
2.0V
PLACEMENT_NOTE=Place in CPU center cavity.
D2T-SM2
C1252
1
2 3
PLACEMENT_NOTE=Place in CPU center cavity.
20%
D2T-SM2
POLY-TANT
CRITICAL
330UF
2.0V
C1253
1
2 3
CPU Decoupling & VID
SYNC_MASTER=M98_MLB
123
12
31
SYNC_DATE=04/01/2008
051-7656
=PPVCORE_S0_CPU
=PP1V5_S0_CPU
=PP1V05_S0_CPU
61 13 11
45
10
11
11
8
8
8
6
Preliminary
IN
BI
BI
BI
BI
OUT
IN
BI
IN
IN
IN
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
NC
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
TCK0
OBSDATA_A3
OBSDATA_A1
OBSFN_C0
OBSDATA_C0
OBSDATA_C1
OBSDATA_C3
Mini-XDP Connector
VCC_OBS_CD
DBR#/HOOK7
Please avoid any obstructions
on even-numbered side of J1300
NOTE: This is not the standard XDP pinout.
VCC_OBS_AB
TDO
TDI
RESET#/HOOK6
OBSFN_D0
SCL
SDA
TRSTn
HOOK3
HOOK2
HOOK1
TMS
OBSDATA_D0
TCK1
OBSDATA_B2
PWRGD/HOOK0
OBSFN_D1
OBSDATA_B3
XDP_PRESENT#
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
OBSFN_B0
OBSDATA_C2
OBSFN_C1
Direction of XDP module
998-1571
ITPCLK#/HOOK5
ITPCLK/HOOK4
OBSDATA_D3
OBSDATA_D2
OBSDATA_D1OBSDATA_B1
OBSDATA_B0
OBSFN_B1
OBSDATA_A2
OBSDATA_A0
OBSFN_A1
OBSFN_A0
Use with 920-0620 adapter board to support CPU, MCP debugging.
MCP79-specific pinout
10 14 88
1K
402
MF-LF
XDP
5%
1/16W
R1399
1 2
7
21 44 91
7
21 44 91
54.9
MF-LF
1/16W
1%
402
XDP
R1315
1
2
402
0.1uF
XDP
16V
10%
X5R
C1300
1
2
X5R
10%
0.1uF
XDP
16V
402
C1301
1
2
10 88
10 88
6
10 88
9
10 14 88
XDP
402
MF-LF
1/16W
5%
1K
PLACEMENT_NOTE=Place close to CPU to minimize stub.
R1303
1 2
10 88
10 88
10 88
10 88
6
21
6
21
6
21
19 91
19 91
19 91
19 91
19 91
19 91
19 91
19 91
6
21
6
14 88
14 88
6
6
10 88
6
10 88
6
10 88
10 25
19
F-ST-SM
LTH-030-01-G-D-NOPEGS
CRITICAL
XDP_CONN
J1300
1
10
1112
1314
1516
1718
19
2
20
2122
2324
2526
2728
29
3
30
3132
3334
3536
3738
39
4
40
4142
4344
4546
4748
49
5
50
5152
5354
5556
5758
59
6
60
78
9
SYNC_DATE=04/01/2008
051-7656
SYNC_MASTER=M98_MLB
13
31
123
eXtended Debug Port(MiniXDP)
TP_XDP_OBSFN_B0
XDP_BPM_L<3>
=PP3V3_S0_XDP
=PP1V05_S0_CPU
TP_XDP_OBSDATA_B2
MCP_DEBUG<2>
JTAG_MCP_TDI
MCP_DEBUG<4>
MCP_DEBUG<6>
MCP_DEBUG<7>
XDP_CPURST_L
XDP_DBRESET_L
MCP_DEBUG<0>
XDP_TCK
SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK
JTAG_MCP_TCK
PM_LATRIGGER_L
XDP_OBS20
TP_XDP_OBSDATA_B3
XDP_PWRGD
TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1
TP_XDP_OBSFN_B1
XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<4>
XDP_BPM_L<5>
JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L
MCP_DEBUG<1>
MCP_DEBUG<3>
JTAG_MCP_TMS
MCP_DEBUG<5>
FSB_CLK_ITP_P
FSB_CLK_ITP_N
XDP_TDI
XDP_TRST_L
XDP_TDO_CONN
XDP_TMS
CPU_PWRGD
FSB_CPURST_L
61 12 11 10
8 8 6
6
7
88
7
Preliminary
IN
IN
IN
IN
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
BI
BI
CPU_BR0#
CPU_BNR#
BCLK_OUT_NB_N
CPU_BR1#
CPU_REQ4#
CPU_ADS#
CPU_A27#
CPU_A26#
CPU_A25#
CPU_A34#
CPU_D62#
CPU_D61#
CPU_D60#
CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#
CPU_A22#
CPU_A23#
CPU_A24#
CPU_REQ3#
CPU_REQ2#
CPU_DBI3#
CPU_D14#
CPU_D13#
CPU_D12#
CPU_D11#
CPU_D10#
CPU_DPWR#
CPU_RS1#
BCLK_VML_COMP_GND
CPU_COMP_VCC
CPU_TRDY#
CPU_PROCHOT#
CPU_BSEL0
CPU_RS2#
CPU_BSEL1
BCLK_IN_P
BCLK_OUT_CPU_N
CPU_PWRGD
CPU_DSTBP0#
CPU_DSTBP1#
CPU_DBI1#
CPU_DBI0#
CPU_DSTBN1#
CPU_DSTBN0#
CPU_DBI2#
CPU_DSTBP2#
CPU_DSTBN2#
CPU_DSTBP3#
CPU_A4#
CPU_DSTBN3#
CPU_A3#
CPU_A5#
CPU_A9#
CPU_A8#
CPU_A6#
CPU_A7#
CPU_A12#
CPU_A14#
CPU_A13#
CPU_A11#
CPU_A15#
CPU_A16#
CPU_A19#
CPU_A17#
CPU_A18#
CPU_A20#
CPU_A21#
CPU_A35#
CPU_A33#
CPU_ADSTB0#
CPU_REQ0#
CPU_LOCK#
CPU_HIT#
CPU_HITM#
CPU_FERR#
CPU_THERMTRIP#
CPU_PECI
CPU_COMP_GND
CPU_D0#
CPU_D1#
CPU_D3#
CPU_D2#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D8#
CPU_D7#
CPU_D9#
CPU_D15#
CPU_D17#
CPU_D18#
CPU_D16#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D23#
CPU_D22#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D38#
CPU_D37#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D43#
CPU_D42#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D63#
CPU_BPRI#
CPU_DEFER#
BCLK_OUT_CPU_P
BCLK_OUT_ITP_P
BCLK_OUT_ITP_N
BCLK_OUT_NB_P
BCLK_IN_N
CPU_A20M#
CPU_NMI
CPU_INTR
CPU_SMI#
CPU_RESET#
CPU_SLP#
CPU_DPSLP#
CPU_STPCLK#
CPU_DPRSTP#
CPU_D51#
CPU_D50#
CPU_D49#
CPU_D48#
CPU_ADSTB1#
CPU_IGNNE#
CPU_INIT#
BCLK_VML_COMP_VDD
CPU_RS0#
+V_DLL_DLCELL_AVDD
+V_PLL_MCLK
+V_PLL_FSB
+V_PLL_CPU
CPU_A10#
CPU_BSEL2
CPU_DBSY#
CPU_DRDY#
CPU_REQ1#
FSB
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
270 mA (A01)
206 mA
15 mA
29 mA
20 mA
(MCP_BSEL<0>)
(MCP_BSEL<1>)
(MCP_BSEL<2>)
Loop-back clock for delay matching.
9
9
9
10 88
9
10 13 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
10 88
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
10 88
9
10 88
7
10 88
7
10 88
7
10 88
7
10 88
7
10 88
10 88
10 88
10 88
10 88
10 88
10 88
13 88
13 88
10 88
10 88
10 88
10 88
10 88
9
10 88
9
10 88
10 88
10 13 88
10 88
10 88
10 88
10 88
9
10 61 88
9
10 42 61 88
10 42 88
10 88
10 88
49.9
1/16W
1%
402
MF-LF
R1436
1
2
1/16W
1%
402
MF-LF
49.9
R1431
1
2
49.9
MF-LF
402
1%
1/16W
R1430
1
2
49.9
1/16W
1%
402
MF-LF
R1435
1
2
NO STUFF
1K
402
5%
1/16W
MF-LF
R1422
1
2
1K
NO STUFF
402
MF-LF
5%
1/16W
R1421
1
2
1K
5%
402
MF-LF
NO STUFF
1/16W
R1420
1
2
1/16W
402
MF-LF
62
5%
R1415
1
2
1/16W
402
MF-LF
54.9
1%
R1410
1
2
NO STUFF
150
1/16W
402
MF-LF
5%
R1440
1
2
OMIT
MCP79-TOPO-B
(1 OF 11)
BGA
U1400
AK41
AJ40
G41
G42
AL42
AL43
AK42
AL41
AM40
AM39
AF35
AG35
AG39
AE33
AG37
AG38
AG34
AN38
AL39
AG33
AL33
AF41
AJ33
AN36
AJ35
AJ37
AJ36
AJ38
AL37
AL34
AN37
AC34
AJ34
AL38
AL35
AN34
AR39
AN35
AE38
AE34
AC37
AE37
AE35
AB35
AD42
AE36
AK35
AD43
AA41
AE40
AL32
F41
D42
F42
AM42
AM43
Y43
W42
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
Y40
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
W41
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
Y39
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
V42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
Y41
K41
J40
H39
M43
Y42
P42
U41
V41
V35
N35
J41
AD39
AA40
AN32
AN33
AM32
AD41
U40
W37
L36
M41
T40
W39
N37
M39
AH40
AB42
AD40
AH39
AH42
AF42
AC43
AG41
E41
AJ41
AH43
AC38
AA33
AC39
AC33
AC35
H38
AC41
AB41
AC42
AM33
AH41
AG42
AG43
AE41
AG27
AH28
AG28
AH27
1/16W
402
MF-LF
62
5%
R1416
1
2
31
SYNC_DATE=06/06/2008
MCP CPU Interface
051-7656
123
14
SYNC_MASTER=T18_MLB
=MCP_BSEL<1>
=MCP_BSEL<0>
=MCP_BSEL<2>
=PP1V05_S0_MCP_FSB
FSB_BREQ1_L
FSB_ADS_L
FSB_BREQ0_L
CPU_FERR_L
FSB_RS_L<0>
FSB_BNR_L
FSB_DRDY_L
FSB_DBSY_L
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<25>
FSB_A_L<10>
FSB_D_L<7>
FSB_D_L<14>
PP1V05_S0_MCP_PLL_FSB
=PP1V05_S0_MCP_FSB
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>
FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>
FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<35>
FSB_ADSTB_L<0>
FSB_ADSTB_L<1>
FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L
CPU_PECI_MCP
CPU_PROCHOT_L
FSB_RS_L<1>
FSB_RS_L<2>
MCP_BCLK_VML_COMP_VDD
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND
FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<44>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_BPRI_L
FSB_DEFER_L
FSB_CLK_CPU_P
FSB_CLK_CPU_N
FSB_CLK_ITP_P
FSB_CLK_ITP_N
FSB_CLK_MCP_N
FSB_CLK_MCP_P
CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L
CPU_PWRGD
FSB_CPURST_L
FSB_CPUSLP_L
CPU_STPCLK_L
CPU_DPRSTP_L
FSB_D_L<45>
FSB_D_L<43>
FSB_D_L<38>
CPU_DPSLP_L
FSB_DPWR_L
MCP_BCLK_VML_COMP_GND
FSB_D_L<13>
PM_THRMTRIP_L
23
23
22
22
14
14 9 9
8
88
23
8
88
88
88
88
88
88
Preliminary
0A
MEMORY
MEMORY PARTITION 0
CONTROL
MCKE0A_1
MCKE0A_0
MODT0A_1
MODT0A_0
MCS0A_0#
MCS0A_1#
MCLK0A_0_N
MCLK0A_0_P
MCLK0A_1_N
MCLK0A_2_N
MCLK0A_1_P
MCLK0A_2_P
MA0_0
MA0_1
MA0_2
MA0_3
MA0_4
MA0_5
MA0_6
MA0_8
MA0_7
MA0_9
MA0_10
MA0_11
MA0_13
MA0_12
MA0_14
MBA0_2
MBA0_0
MBA0_1
MWE0#
MCAS0#
MRAS0#
MDQS0_0_P
MDQS0_0_N
MDQS0_1_P
MDQS0_2_N
MDQS0_1_N
MDQS0_2_P
MDQS0_3_N
MDQS0_4_P
MDQS0_3_P
MDQS0_4_N
MDQS0_5_N
MDQS0_5_P
MDQS0_6_N
MDQS0_6_P
MDQS0_7_N
MDQS0_7_P
MDQM0_2
MDQM0_1
MDQM0_0
MDQM0_3
MDQM0_4
MDQ0_0
MDQM0_7
MDQM0_5
MDQM0_6
MDQ0_1
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_5
MDQ0_6
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_10
MDQ0_11
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_16
MDQ0_21
MDQ0_20
MDQ0_18
MDQ0_19
MDQ0_17
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_26
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_30
MDQ0_31
MDQ0_35
MDQ0_34
MDQ0_32
MDQ0_36
MDQ0_33
MDQ0_41
MDQ0_37
MDQ0_38
MDQ0_40
MDQ0_39
MDQ0_42
MDQ0_47
MDQ0_46
MDQ0_43
MDQ0_45
MDQ0_44
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_52
MDQ0_48
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_56
MDQ0_57
MDQ0_61
MDQ0_60
MDQ0_58
MDQ0_59
MDQ0_62
MDQ0_63
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
MEMORY
CONTROL
1A
MEMORY PARTITION 1
MDQ1_63
MDQ1_60
MDQ1_59
MDQ1_62
MDQ1_58
MDQ1_61
MDQ1_57
MDQ1_53
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_52
MDQ1_49
MDQ1_51
MDQ1_50
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_43
MDQ1_44
MDQ1_45
MDQ1_42
MDQ1_41
MDQ1_37
MDQ1_38
MDQ1_39
MDQ1_36
MDQ1_35
MDQ1_32
MDQ1_33
MDQ1_34
MDQ1_31
MDQ1_30
MDQ1_27
MDQ1_28
MDQ1_29
MDQ1_22
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_17
MDQ1_19
MDQ1_20
MDQ1_18
MDQ1_21
MDQ1_16
MDQ1_12
MDQ1_13
MDQ1_14
MDQ1_15
MDQ1_11
MDQ1_10
MDQ1_7
MDQ1_8
MDQ1_9
MDQ1_3
MDQ1_6
MDQ1_2
MDQ1_4
MDQ1_5
MDQ1_1
MDQM1_6
MDQM1_5
MDQ1_0
MDQM1_7
MDQM1_4
MDQM1_3
MDQM1_0
MDQM1_1
MDQM1_2
MDQ1_40
MDQS1_7_P
MDQS1_6_N
MDQS1_6_P
MDQS1_7_N
MDQS1_5_N
MDQS1_5_P
MDQS1_4_P
MDQS1_3_P
MDQS1_4_N
MDQS1_2_P
MDQS1_3_N
MDQS1_1_P
MDQS1_2_N
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N
MRAS1#
MCAS1#
MWE1#
MBA1_2
MBA1_1
MBA1_0
MA1_14
MA1_13
MA1_12
MA1_11
MA1_10
MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0
MCLK1A_2_P
MCLK1A_1_P
MCLK1A_2_N
MCLK1A_0_P
MCLK1A_1_N
MCS1A_1#
MCS1A_0#
MCLK1A_0_N
MODT1A_1
MODT1A_0
MCKE1A_0
MCKE1A_1
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
BGA
MCP79-TOPO-B
OMIT
(2 OF 11)
U1400
AR19
AT19
AN19
AW21
AN23
AU15
AR23
AU19
AV19
AN21
AR21
AP21
AU21
AR22
AV21
AW17
AP19
AP23
AP17
AT23
AU23
BC20
BB20
AY24
BA24
AV33
AW33
AR18
AT15
AP35
AR35
AV31
AT31
AW37
AV37
AR33
AU31
AN31
AV29
AN29
AV27
AW38
AR31
AP31
AR29
AP29
AR27
AP27
AR25
AP25
AU27
AT27
AV38
AU25
AR26
AU13
AR14
AT11
AR11
AW13
AV13
AV11
AU11
AR38
AV9
AU9
AY5
AW6
AP11
AW9
AU8
AU7
AV5
AU6
AR37
AR5
AN10
AW5
AV6
AR7
AR6
AN7
AN6
AL7
AL6
AV39
AN9
AP9
AL9
AL8
AW39
AU37
AT37
AR34
AV35
AW29
AN27
AN13
AR10
AU5
AN5
AT39
AU39
AU35
AT35
AU29
AU30
AW25
AV25
AR13
AP13
AW8
AW7
AR9
AR8
AL11
AL10
AV15
AP15
AV17
AR17
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
27 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
BGA
MCP79-TOPO-B
OMIT
(3 OF 11)
U1400
BA18
BB25
BA17
BC28
AW28
BA14
BA29
BA25
BB26
BA26
BA27
AY27
BA28
AY28
BB28
BB17
BB18
BB29
BA15
BB30
AY31
AY19
BA19
BA22
BB22
BB42
BA42
BB16
BB14
AP42
AR41
BC40
BA40
AV41
AV42
AW40
BB40
AY39
BA38
BB36
BA36
AU41
AY40
BA39
AW36
BC36
AY35
BA34
BB32
BA32
AY36
BA35
AU40
AW32
BC32
BA12
AY12
BB9
BB8
AW12
BB12
BB10
BA9
AN40
AY8
BA7
BC4
BB4
BC8
BA8
BA5
BB5
BB2
BA3
AP41
AW3
AW4
BC3
BB3
AY3
AY4
AU3
AU2
AR3
AR4
AT41
AV3
AV2
AT3
AT4
AT40
AW41
AW42
AR42
AY43
BB38
BB34
BA11
AY7
BA2
AT5
AT43
AT42
AY42
BA43
BA37
BB37
BA33
BB33
AY11
BA10
BA6
BB6
AY1
AY2
AT1
AT2
AY15
BB13
AW16
BA16
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
28 89
123
051-7656
31
15
SYNC_MASTER=T18_MLB
SYNC_DATE=06/06/2008
MCP Memory Interface
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>
MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>
TP_MEM_A_CLK2P
TP_MEM_A_CLK2N
MEM_A_CLK_P<1>
MEM_A_CLK_N<1>
MEM_A_CLK_P<0>
MEM_A_CLK_N<0>
MEM_A_CS_L<1>
MEM_A_CS_L<0>
MEM_A_ODT<1>
MEM_A_ODT<0>
MEM_A_CKE<1>
MEM_A_CKE<0>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L
MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>
MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>
TP_MEM_B_CLK2P
TP_MEM_B_CLK2N
MEM_B_CLK_P<1>
MEM_B_CLK_N<1>
MEM_B_CLK_P<0>
MEM_B_CLK_N<0>
MEM_B_CS_L<1>
MEM_B_CS_L<0>
MEM_B_ODT<1>
MEM_B_ODT<0>
MEM_B_CKE<1>
MEM_B_CKE<0>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>
MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
7
7
7
Preliminary
MCLK1B_2_P
MCLK1B_1_N
MCLK1B_0_P
MCLK1B_1_P
MCLK1B_2_N
MCS1B_1#
MCS1B_0#
MCLK1B_0_N
MODT1B_0
MCKE1B_1
MCKE1B_0
MODT1B_1
MRESET0#
GND55
GND56
GND57
GND58
GND60
GND59
GND61
GND62
GND63
GND64
GND52
GND53
GND54
GND51
GND49
GND50
GND48
GND47
GND46
GND44
GND45
GND43
GND42
GND41
GND39
GND40
GND38
GND37
GND36
GND35
GND33
GND34
GND32
GND31
GND30
GND28
GND29
GND27
GND26
GND25
GND24
GND18
GND19
GND17
GND16
GND15
GND13
GND14
GND10
GND12
GND11
GND8
GND9
GND7
GND6
GND5
GND2
GND3
GND4
GND1
MEM_COMP_VDD
MEM_COMP_GND
MODT0B_0
MODT0B_1
MCKE0B_1
MCKE0B_0
MCLK0B_0_N
MCS0B_0#
MCS0B_1#
MCLK0B_2_N
MCLK0B_1_P
MCLK0B_0_P
MCLK0B_1_N
MCLK0B_2_P
+V_PLL_XREF_XS
+V_PLL_CORE
+V_VPLL
+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8
+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM22
+VDD_MEM21
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM30
+VDD_MEM27
+VDD_MEM29
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45
+VDD_MEM42
+V_PLL_DP
+VDD_MEM13
+VDD_MEM12
+VDD_MEM28
+VDD_MEM37
+VDD_MEM36
+VDD_MEM35
GND21
GND20
GND22
GND23
MEMORY CONTROL 0B
MEMORY CONTROL 1B
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
87 mA (A01)
39 mA
TP or NC for DDR2.
19 mA
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
12 mA
17 mA
4771 mA (A01, DDR3)
1%
40.2
1/16W
402
MF-LF
R1610
1
2
MF-LF
402
1%
1/16W
40.2
R1611
1
2
(4 OF 11)
MCP79-TOPO-B
OMIT
BGA
U1400
AA22
AA39
AB22
AB7
AD22
AE20
AF24
AG24
AH35
AK7
AM28
AP12
AT25
AP30
AR36
AU10
F28
BC21
AY9
BC9
D34
F24
G30
G32
H31
K7
M38
M5
M6
M7
M9
N39
N8
P10
P33
P34
P37
P4
P40
P7
R36
R40
R43
R5
T10
T18
T20
AK11
T24
T26
T33
T34
T35
T37
T38
T6
T7
T9
U18
U20
U22
V10
V34
W5
AV23
AN25
BA30
BA31
BB21
BA21
BC24
BB24
AU34
AU33
AY20
BA20
BA23
AY23
BB41
BA41
AU17
AR15
BC16
BA13
AM41
AN41
AN17
AN15
AY16
BC13
AY32
U27
U28
T27
T28
AM17
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AM19
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AM21
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AM23
AY26
AW19
AW24
BC25
AL30
AM31
AM25
AM27
AM29
AN16
BC29
29
MCP Memory Misc
16
123
31
051-7656
SYNC_DATE=06/06/2008
SYNC_MASTER=T18_MLB
MCP_MEM_COMP_VDD
=PP1V8R1V5_S0_MCP_MEM
TP_MEM_B_ODT<3>
TP_MEM_B_ODT<2>
TP_MEM_B_CS_L<3>
TP_MEM_B_CLK3N
TP_MEM_B_CLK3P
TP_MEM_B_CLK4N
TP_MEM_B_CLK4P
TP_MEM_B_CLK5N
TP_MEM_B_CLK5P
PP1V05_S0_MCP_PLL_CORE
TP_MEM_A_CS_L<3>
TP_MEM_A_CS_L<2>
TP_MEM_A_CLK3N
TP_MEM_A_CLK4P
TP_MEM_A_CLK5N
TP_MEM_A_CLK5P
TP_MEM_A_CKE<3>
TP_MEM_A_CKE<2>
TP_MEM_A_ODT<3>
TP_MEM_A_ODT<2>
TP_MEM_A_CLK3P
TP_MEM_A_CLK4N
MCP_MEM_COMP_GND
=PP1V8R1V5_S0_MCP_MEM
MCP_MEM_RESET_L
TP_MEM_B_CS_L<2>
TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>
23
23
16
16
89
8
7
7
7
7
7
7
7
7
7
23
7
7
7
7
7
7
7
7
7
7
7
7
89
8
7
7
Preliminary
PE0_RX0_P
PE0_RX2_N
+AVDD0_PEX11
+AVDD0_PEX7
+AVDD0_PEX8
+AVDD1_PEX3
+AVDD1_PEX2
+AVDD1_PEX1
+AVDD0_PEX13
+AVDD0_PEX12
+AVDD0_PEX10
+AVDD0_PEX9
+AVDD0_PEX6
+AVDD0_PEX5
+AVDD0_PEX4
+AVDD0_PEX3
+AVDD0_PEX2
+AVDD0_PEX1
+V_PLL_PEX
+DVDD1_PEX2
+DVDD1_PEX1
+DVDD0_PEX8
+DVDD0_PEX7
+DVDD0_PEX6
+DVDD0_PEX5
+DVDD0_PEX4
+DVDD0_PEX3
+DVDD0_PEX2
+DVDD0_PEX1
PE0_RX0_N
PE0_RX2_P
PE0_RX4_P
PE0_RX6_P
PEB_PRSNT#
PE1_TX3_N
PE1_TX3_P
PE1_TX2_N
PE1_TX1_N
PE1_TX2_P
PE1_TX0_N
PE1_TX1_P
PE6_REFCLK_N
PEX_RST0#
PE1_TX0_P
PE5_REFCLK_N
PE5_REFCLK_P
PE6_REFCLK_P
PE4_REFCLK_N
PE4_REFCLK_P
PE3_REFCLK_N
PE2_REFCLK_N
PE1_REFCLK_N
PE2_REFCLK_P
PE0_REFCLK_N
PE0_REFCLK_P
PE1_REFCLK_P
PE0_TX15_N
PE0_TX14_N
PE0_TX15_P
PE0_TX13_N
PE0_TX14_P
PE0_TX12_N
PE0_TX12_P
PE0_TX13_P
PE0_TX11_N
PE0_TX11_P
PE0_TX10_N
PE0_TX9_N
PE0_TX10_P
PE0_TX8_N
PE0_TX8_P
PE0_TX9_P
PE0_TX7_N
PE0_TX7_P
PE0_TX6_N
PE0_TX5_N
PE0_TX6_P
PE0_TX4_N
PE0_TX5_P
PE0_TX3_N
PE0_TX3_P
PE0_TX4_P
PE0_TX2_N
PE0_TX2_P
PE0_TX0_N
PE0_TX1_N
PE0_TX1_P
PE0_TX0_P
PEX_CLK_COMP
PE1_RX3_N
PE1_RX3_P
PE1_RX2_N
PE1_RX0_N
PE1_RX1_P
PE1_RX2_P
PE1_RX1_N
PE_WAKE#
PE1_RX0_P
PE0_PRSNT_16#
PE0_RX13_N
PE0_RX14_P
PE0_RX15_P
PE0_RX14_N
PE0_RX15_N
PE0_RX12_P
PE0_RX11_P
PE0_RX13_P
PE0_RX11_N
PE0_RX12_N
PE0_RX10_N
PE0_RX8_P
PE0_RX9_P
PE0_RX10_P
PE0_RX8_N
PE0_RX9_N
PE0_RX5_N
PE0_RX7_P
PE0_RX6_N
PE0_RX7_N
PE0_RX3_P
PE0_RX5_P
PE0_RX3_N
PE0_RX4_N
PE0_RX1_P
PE0_RX1_N
PEC_PRSNT#
PEC_CLKREQ#/GPIO_50
PE3_REFCLK_P
PED_CLKREQ#/GPIO_51
PED_PRSNT#
PEB_CLKREQ#/GPIO_49
PEE_CLKREQ#/GPIO_16
PEE_PRSNT#/GPIO_46
PEF_CLKREQ#/GPIO_17
PEF_PRSNT#/GPIO_47
PEG_CLKREQ#/GPIO_18
PEG_PRSNT#/GPIO_48
PCI EXPRESS
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
IN
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Minimum 1.025V for Gen2 supportMinimum 1.025V for Gen2 support
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
Int PU
84 mA (A01)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
Int PU
206 mA (A01, AVDD0 & 1)
57 mA (A01, DVDD0 & 1)
Int PU (S5)
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.
If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
Int PU
MCP79-TOPO-B
(5 OF 11)
OMIT
BGA
U1400
Y12
AC12
AD12
V12
W12
AA12
AB12
M12
P12
R12
N12
T12
U12
M13
N13
P13
T17
W19
U17
V19
W16
W17
W18
U16
T19
U19
T16
C9
D11
E11
E7
F7
L8
L9
L6
L7
N10
N11
P9
N9
N6
N7
N4
N5
C7
D7
F6
E6
F5
E5
E3
E4
D3
C3
H5
G5
J6
J7
J4
J5
L10
L11
D4
C5
J1
H1
J3
J2
K3
K2
L3
L4
M3
M4
M1
M2
B4
C4
A3
A4
B2
B3
D1
C1
E1
D2
F2
E2
F4
F3
H4
G3
H2
H3
F11
G11
J9
K9
G9
H9
E9
F9
G7
H7
C8
D8
A8
B8
B7
A7
C6
B6
J10
J11
F13
G13
H13
J13
K14
L14
M14
N14
F17
D5
D9
E8
C10
M15
B10
L16
L18
M16
M18
M17
M19
A11
K11
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
69 90
69 90
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
9
7
30 90
7
30 90
9
35
7
30 31
35 90
35 90
7
31 90
7
31 90
30
30
31
31
30 90
30 90
35 90
35 90
35 90
35 90
31 90
31 90
30 90
30 90
31 90
31 90
9
2.37K
402
MF-LF
1%
1/16W
NO STUFF
PLACEMENT_NOTE=Place within 12.7mm of U1400
R1710
1
2
25
84
9
58
SYNC_MASTER=T18_MLB
MCP PCIe Interfaces
17
123
31
051-7656
SYNC_DATE=06/06/2008
PCIE_FW_PRSNT_L
PCIE_MINI_D2R_P
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N
=PP1V05_S0_MCP_PEX_AVDD1
TP_MCP_GPIO_18
MINI_CLKREQ_L
=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_DVDD1
=PP1V05_S0_MCP_PEX_DVDD0
=PEG_D2R_P<0>
=PEG_D2R_N<2>
PP1V05_S0_MCP_PLL_PEX
=PEG_D2R_N<0>
=PEG_D2R_P<2>
=PEG_D2R_P<4>
=PEG_D2R_P<6>
PCIE_MINI_PRSNT_L
TP_PCIE_PE4_R2D_CN
TP_PCIE_PE4_R2D_CP
PCIE_EXCARD_R2D_C_N
PCIE_FW_R2D_C_N
PCIE_EXCARD_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_FW_R2D_C_P
TP_PCIE_CLK100M_PE6N
PCIE_RESET_L
PCIE_MINI_R2D_C_P
TP_PCIE_CLK100M_PE5N
TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P
PCIE_CLK100M_EXCARD_N
PCIE_CLK100M_FW_N
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PEG_CLK100M_N
PEG_CLK100M_P
PCIE_CLK100M_MINI_P
=PEG_R2D_C_N<15>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<10>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<6>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<0>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<1>
=PEG_R2D_C_P<0>
MCP_PEX_CLK_COMP
TP_PCIE_PE4_D2RN
TP_PCIE_PE4_D2RP
PCIE_MINI_D2R_N
PCIE_WAKE_L
PEG_PRSNT_L
=PEG_D2R_N<13>
=PEG_D2R_P<14>
=PEG_D2R_P<15>
=PEG_D2R_P<12>
=PEG_D2R_P<11>
=PEG_D2R_P<13>
=PEG_D2R_N<11>
=PEG_D2R_N<12>
=PEG_D2R_N<10>
=PEG_D2R_P<8>
=PEG_D2R_P<9>
=PEG_D2R_P<10>
=PEG_D2R_N<8>
=PEG_D2R_N<9>
=PEG_D2R_N<5>
=PEG_D2R_P<7>
=PEG_D2R_N<6>
=PEG_D2R_N<7>
=PEG_D2R_P<3>
=PEG_D2R_P<5>
=PEG_D2R_N<3>
=PEG_D2R_N<4>
=PEG_D2R_P<1>
=PEG_D2R_N<1>
FW_CLKREQ_L
PCIE_CLK100M_EXCARD_P
EXCARD_CLKREQ_L
GMUX_JTAG_TCK_L
=PEG_D2R_N<14>
=PEG_D2R_N<15>
GMUX_JTAG_TDO
TP_PE4_PRSNT_L
PCIE_EXCARD_PRSNT_L
TP_PE4_CLKREQ_L
AUD_IP_PERIPHERAL_DET
8
7
8
8
8
23
7
7
7
7
7
90
7
7
7
Preliminary
IN
BI
OUT
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
IN
IN
IN
GPIO_7/NFERR*/IGPU_GPIO_7
+V_DUAL_MACPLL
+VDD_HDMI
+V_PLL_HDMI
+V_PLL_IFPAB
+VDD_IFPB
+VDD_IFPA
+V_TV_DAC
+V_RGB_DAC
+V_DUAL_RMGT2
MII_COMP_GND
MII_COMP_VDD
LCD_PANEL_PWR/GPIO_58
LCD_BKL_ON/GPIO_59
LCD_BKL_CTL/GPIO_57
XTALOUT_TV
GPIO_6/FERR*/IGPU_GPIO_6
HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N
HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
HDMI_TXD1_P/ML0_LANE1_P
HDMI_TXD1_N/ML0_LANE1_N
HDMI_TXD2_P/ML0_LANE0_P
HDMI_TXD2_N/ML0_LANE0_N
HPLUG_DET2/GPIO_22
IFPA_TXC_N
XTALIN_TV
DDC_DATA2/GPIO_24
DDC_CLK2/GPIO_23
RGB_DAC_RSET
RGB_DAC_VREF
TV_DAC_VREF
DP_AUX_CH0_P
DP_AUX_CH0_N
HPLUG_DET3
HDMI_RSET
HDMI_VPROBE
RGMII_MDIO
BUF_25MHZ
DDC_DATA0
DDC_CLK0
RGB_DAC_RED
RGB_DAC_GREEN
RGB_DAC_BLUE
RGB_DAC_HSYNC
RGB_DAC_VSYNC
TV_DAC_RED
TV_DAC_GREEN
IFPA_TXC_P
IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD2_P
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD3_P
IFPA_TXD2_N
IFPB_TXC_P
IFPB_TXC_N
IFPB_TXD5_P
IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD6_P
IFPB_TXD5_N
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N
DDC_DATA3
DDC_CLK3
IFPAB_RSET
IFPAB_VPROBE
TV_DAC_RSET
RGMII_RXD0
RGMII_INTR/GPIO_35
RGMII_RXD3
RGMII_RXCTL/MII_RXDV
RGMII_RXC/MII_RXCLK
RGMII_RXD2
RGMII_RXD1
MII_RESET#
RGMII_MDC
RGMII_PWRDWN/GPIO_37
MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK
TV_DAC_BLUE
TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45
+V_DUAL_RMGT1
MII_VREF
RGMII_TXCTL/MII_TXEN
RGMII_TXC/MII_TXCLK
RGMII_TXD3
RGMII_TXD2
RGMII_TXD1
RGMII_TXD0
+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2
IFPA_TXD3_N
LAN
DACS
FLAT PANEL
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
BI
OUT
BI
OUT
OUT
OUT
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
190 mA (A01, 1.8V)
C / Pr
MCP79 requires a S5 pull-up.
Comp / Pb
206 mA (A01)
103 mA
103 mA
Okay to float XTALIN_TV and XTALOUT_TV.
Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.
Y / Y
TV DAC Disable:
Okay to float all TV_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.
ENET_TXD<0>
1
0MII
RGMII
Interface
Network Interface Select
NOTE: All Apple products set strap to
feature via software. This
avoids a leakage issue since
RGB ONLY
5 mA (A01)
DisplayPort
DP_IG_ML_P/N<3>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<2>
DP_IG_DDC_CLK
TP_DP_IG_AUX_CHP/N
TMDS_IG_DDC_DATA
TMDS_IG_TXD_P/N<2>
TMDS_IG_TXD_P/N<1>
TMDS_IG_DDC_CLK
TMDS_IG_TXD_P/N<0>
TMDS_IG_TXC_P/N
TMDS/HDMI
=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>
MCP Signal
=MCP_HDMI_DDC_CLK
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_DDC_DATA
TMDS_IG_HPD
=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N
8 mA
8 mA
16 mA (A01)
95 mA (A01)
LVDS: Power +VDD_IFPx at 1.8V
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
TV / Component
RGB DAC Disable:
WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases
MII, RGMII products will enable
83 mA (A01)
131 mA (A01)
Dual-channel TMDS: Power +VDD_IFPx at 3.3V
NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
DP_IG_AUX_CH_P/N
DP_IG_HPD
DP_IG_DDC_DATA
DP_IG_ML_P/N<0>
Interface Mode
be used to provide HDMI or dual-channel TMDS without
NOTE: HDMI port requires level-shifting. IFP interface can
level-shifters.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.
(See below)
(See below)
Alias to DVI_HPD for systems using IFP for DVI.
=DVI_HPD_GMUX_INT:
Pull-down (20k) required in all cases.
Alias to HPLUG_DET2 for other systems.
Alias to GMUX_INT for systems with GMUX.
pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.
GPIOs 57-59 (if LCD panel is used):
In MCP79 these pins have undocumented internal
23
32 92
33 92
32 92
32 92
32 92
32 92
32 92
32 92
32 92
24 90
24 90
9
9
9
9
9
9
9
9
9
9
9
81 90
81 90
9
9
24 90
24 90
24 90
24 90
24 90
24 90
24 90
1%
1/16W
MF-LF
402
49.9
R1810
1
2
1/16W
MF-LF
49.9
402
1%
R1811
1
2
81
24
24
9
9
9
(6 OF 11)
BGA
MCP79-TOPO-B
OMIT
U1400
E23
B31
C30
D31
A31
B30
E31
C43
D43
E16
B15
J31
E35
D35
F35
G35
G33
F33
H33
J33
J30
C31
F31
C35
B35
A32
B32
C32
D32
C33
D33
C34
B34
E32
G31
K31
L31
H29
J29
K29
L29
K30
L30
M30
N30
G39
E37
F40
B26
B27
C27
B22
J23
F23
E28
J24
K24
T23
U23
V23
M29
M28
J32
K32
T25
M27
M26
B40
A39
A40
B39
C39
B38
A41
J22
D21
C21
G23
A23
C22
C23
B23
E24
A24
D24
C26
B24
C24
C25
D25
C36
B36
D36
A36
E36
A35
C37
C38
D38
10K
402
1/16W
5%
MF-LF
R1850
1
2
402
5%
100K
1/16W
MF-LF
R1861
1
2
402
MF-LF
5%
1/16W
100K
R1860
1
2
7
43
5%
47K
402
MF-LF
1/16W
R1820
1
2
32 92
84 90
84 90
84 90
84 90
84 90
32 92
84 90
84 90
84 90
9
90
9
90
9
90
9
90
84 90
84 90
84 90
32 92
84 90
84 90
84 90
9
90
9
90
81
81
9
9
24 90
32 92
24 90
32 92
32 92
32 92
18
123
31
051-7656
SYNC_DATE=06/06/2008
SYNC_MASTER=T18_MLB
MCP Ethernet & Graphics
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXC_N
=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_N<3>
MCP_HDMI_RSET
MCP_HDMI_VPROBE
DP_IG_CA_DET
PP1V05_ENET_MCP_PLL_MAC
=PP1V05_S0_MCP_HDMI_VDD
PP3V3_S0_MCP_VPLL
=PP3V3R1V8_S0_MCP_IFP_VDD
PP3V3_S0_MCP_DAC
MCP_MII_COMP_GND
MCP_MII_COMP_VDD
LVDS_IG_PANEL_PWR
LVDS_IG_BKL_ON
=MCP_HDMI_TXC_P
=MCP_HDMI_TXD_N<2>
MCP_CLK27M_XTALIN
LVDS_IG_DDC_DATA
LVDS_IG_DDC_CLK
MCP_TV_DAC_VREF
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N
=MCP_HDMI_HPD
ENET_MDIO
MCP_CLK25M_BUF0_R
MCP_DDC_DATA0
MCP_DDC_CLK0
TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE
TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC
CRT_IG_R_C_PR
CRT_IG_G_Y_Y
LVDS_IG_A_CLK_P
LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<2>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>
=MCP_HDMI_DDC_DATA
=MCP_HDMI_DDC_CLK
MCP_IFPAB_RSET
MCP_IFPAB_VPROBE
MCP_TV_DAC_RSET
ENET_RXD<0>
TP_ENET_INTR_L
ENET_RXD<3>
ENET_RX_CTRL
ENET_CLK125M_RXCLK
ENET_RXD<2>
ENET_RXD<1>
ENET_RESET_L
ENET_MDC
TP_ENET_PWRDWN_L
=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS
CRT_IG_B_COMP_PB
CRT_IG_HSYNC
CRT_IG_VSYNC
MCP_MII_VREF
ENET_TX_CTRL
ENET_CLK125M_TXCLK
ENET_TXD<3>
ENET_TXD<2>
ENET_TXD<1>
ENET_TXD<0>
=PP3V3_ENET_MCP_RMGT
=PP3V3_S0_MCP_GPIO
=PP3V3_ENET_MCP_RMGT
=PP3V3_S5_MCP_GPIO
=PP1V05_ENET_MCP_RMGT
LPCPLUS_GPIO
TP_MCP_RGB_DAC_VREF
TP_MCP_RGB_DAC_RSET
MCP_CLK27M_XTALOUT
LVDS_IG_BKL_PWM
=DVI_HPD_GMUX_INT
23
21
23
24
24
18
19
18
20
23
23
8
24
8
24
92
92
24
24
24
24
24
7
7
8
8
8
8
8
24
24
Preliminary
OUT
OUT
BI
BI
BI
BI
LPC PCIGND
PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#
GND65
LPC_DRQ1#/GPIO_19
LPC_PWRDWN#/GPIO_54/EXT_NMI#
PCI_TRDY#
LPC_DRQ0#
LPC_SERIRQ
PCI_AD4
PCI_AD0
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD5
PCI_AD6
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD10
PCI_AD11
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD21
PCI_AD22
PCI_AD25
PCI_AD23
PCI_AD26
PCI_AD29
PCI_AD31
GND66
GND67
GND69
GND68
GND70
GND71
GND72
GND74
GND73
GND75
GND76
GND77
GND79
GND78
GND80
GND81
GND84
GND83
GND82
GND85
GND86
GND87
GND89
GND88
GND90
GND91
GND92
GND94
GND93
GND95
GND96
GND97
PCI_GNT0#
PCI_CBE2#
PCI_CBE0#
PCI_CBE3#
PCI_IRDY#
PCI_FRAME#
PCI_DEVSEL#
PCI_PAR
PCI_SERR#
PCI_STOP#
PCI_RESET0#
PCI_RESET1#
PCI_CLK2
PCI_CLK1
PCI_CLK0
PCI_CLKIN
LPC_FRAME#
LPC_AD1
LPC_AD0
LPC_RESET0#
LPC_CLK0
LPC_AD3
LPC_AD2
GND99
GND98
GND100
GND102
GND101
GND104
GND103
GND105
GND106
GND107
GND109
GND108
GND110
GND111
GND112
GND115
GND114
GND113
GND116
GND117
GND120
GND119
GND118
GND121
GND122
GND123
GND125
GND124
GND126
GND127
GND128
GND130
GND129
PCI_AD30
PCI_AD27
PCI_AD24
PCI_CLKRUN#/GPIO_42
PCI_AD28
PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#
PCI_GNT4#/GPIO_53/RS232_SOUT#
PCI_GNT1#/FANCTL2
PCI_CBE1#
PCI_PERR#/GPIO_43/RS232_DCD#
PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#
PCI_PME#/GPIO_30
PCI_REQ2#/GPIO_40/RS232_DSR#
PCI_REQ0#
PCI_REQ1#/FANRPM2
IN
BI
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
BI
BI
BI
BI
BI
BI
BI
BI
OUT
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Strap for Boot ROM Selection (See HDA_SDOUT)
Int PU
Int PU
Int PU
Int PU (S5)
7
41 43 84 91
25 84 91
7
41 43 84 91
7
41 43 84 91
7
41 43 84 91
7
41 43 84 91
BGA
(7 OF 11)
MCP79-TOPO-B
OMIT
U1400
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
AD28
AD33
AD34
U24
U26
U39
U4
U8
V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37
V4
V40
V7
W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25
Y26
Y27
AD3
AD2
AD1
AD5
AE9
AE1
AE2
AD4
AE12
AE5
AE6
AC3
AE10
AC9
AC10
AC11
AA1
AA5
Y5
W3
W6
W4
W7
AC4
V3
W8
V2
W9
U3
W11
U2
U5
U1
U6
AE11
T5
U7
AB3
AC6
AB2
AC7
AC8
AA2
AA3
AA6
AA11
W10
R6
R7
R8
R9
AD11
AA9
Y4
R3
U10
R4
U11
P3
P2
N3
N2
N1
AA10
Y1
AB9
T1
T2
V9
T3
U9
T4
R10
R11
AA7
Y2
Y3
7
41 43
7
41 43 25 91
7
41 43
PLACEMENT_NOTE=Place close to pin R8
MF-LF
402
1/16W
5%
22
R1910
1
2
402
MF-LF1/16W
5%
8.2K
R1989
1 2
402
MF-LF1/16W
5%
8.2K
R1991
1 2
402
MF-LF1/16W
5%
8.2K
R1990
1 2
402
MF-LF1/16W
5%
8.2K
R1994
1 2
8.2K
5%
1/16W MF-LF
402
R1992
1 2
19
MF-LF
402
1/16W
5%
10K
R1961
1
2
1/16W MF-LF
402
22
5%
R1960
1 2
5%
1/16W MF-LF22402
R1950
1 2
5%
1/16W MF-LF22402
R1951
1 2
22
5%
1/16W MF-LF
402
R1952
1 2
402
MF-LF1/16W
5%
22
R1953
1 2
25
35
19
19
13
13 91
13 91
13 91
13 91
13 91
13 91
13 91
13 91
9
58
9
9
051-7656
31
123
19
MCP PCI & LPC
SYNC_DATE=06/06/2008
SYNC_MASTER=T18_MLB
CRTMUX_SEL_TV_L
PCI_REQ1_L
PCI_REQ0_L
MCP_RS232_SOUT_L
LPC_AD<1>
LPC_AD<3>
LPC_AD<2>
LPC_FRAME_L
LPC_AD<0>
TP_PCI_GNT0_L
TP_PCI_GNT1_L
MCP_RS232_SOUT_L
TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>
TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_SERR_L
TP_PCI_STOP_L
PM_LATRIGGER_L
TP_PCI_RESET1_L
TP_PCI_CLK0
LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>
LPC_CLK33M_SMC_R
LPC_FRAME_R_L
LPC_RESET_L
LPC_PWRDWN_L
PCI_CLK33M_MCP_R
TP_PCI_CLK1
PCI_CLK33M_MCP
MEM_VTT_EN_R
TP_PCI_PERR_L
TP_PCI_AD<9>
TP_PCI_AD<11>
TP_PCI_AD<10>
TP_PCI_AD<8>
PCI_REQ1_L
PCI_REQ0_L
TP_PCI_AD<15>
TP_PCI_INTY_L
TP_PCI_TRDY_L
TP_PCI_INTW_L
TP_PCI_AD<31>
TP_PCI_AD<30>
TP_PCI_AD<29>
TP_PCI_AD<28>
TP_PCI_AD<27>
TP_PCI_AD<26>
TP_PCI_AD<25>
TP_PCI_AD<24>
TP_PCI_AD<23>
TP_PCI_AD<22>
TP_PCI_AD<21>
TP_PCI_AD<20>
TP_PCI_AD<19>
TP_PCI_AD<18>
TP_PCI_AD<17>
TP_PCI_AD<16>
TP_PCI_AD<14>
TP_PCI_AD<13>
TP_PCI_AD<12>
CRTMUX_SEL_TV_L
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L
MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
MCP_RS232_SIN_L
=PP3V3_S0_MCP_GPIO
PM_CLKRUN_L
LPC_SERIRQ
TP_LPC_DRQ0_L
FW_PME_L
TP_PCI_INTZ_L
TP_PCI_INTX_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
21
91
91
91
91
18
19
19
19
19
7
7
7
7
7
7
7
7
7
7
7
7
7
7
43
91
7
91
7 7
7
7
7
19
19
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
19
8
7
7
7
Preliminary
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
SATA_B0_RX_N
SATA_A0_RX_P
SATA_A1_TX_P
GND160
GND158
GND159
GND157
GND156
GND155
GND153
GND154
GND152
GND151
GND150
GND148
GND149
GND147
GND146
GND145
GND143
GND144
GND142
GND141
GND140
GND139
GND136
GND133
GND134
GND132
GND131
USB_RBIAS_GND
USB11_N
USB11_P
USB10_N
USB10_P
USB9_N
USB9_P
USB7_N
USB8_N
USB8_P
USB7_P
USB6_N
USB6_P
USB5_N
USB4_N
USB4_P
USB5_P
USB2_N
USB2_P
USB0_N
USB1_N
USB1_P
USB0_P
SATA_TERMP
SATA_LED#
SATA_C1_RX_N
SATA_C1_RX_P
SATA_C0_TX_P
SATA_B1_RX_N
SATA_B1_RX_P
SATA_B1_TX_N
SATA_B1_TX_P
SATA_B0_TX_N
SATA_B0_RX_P
SATA_B0_TX_P
SATA_A1_RX_N
SATA_A1_RX_P
SATA_A1_TX_N
SATA_A0_TX_P
GND138
GND137
GND135
USB3_P
USB3_N
USB_OC0#/GPIO_25
USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO
SATA_A0_RX_N
SATA_A0_TX_N
SATA_C1_TX_N
SATA_C1_TX_P
SATA_C0_RX_P
SATA_C0_RX_N
SATA_C0_TX_N
+V_PLL_USB
+V_PLL_SATA
+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4
+DVDD1_SATA2
+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9
+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4
+DVDD1_SATA1
SATA
USB
OUT
OUT
IN
IN
OUT
OUT
IN
IN
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Minimum 1.025V for Gen2 support
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.
84 mA (A01)
43 mA (A01, DVDD0 & 1)
ExpressCard
Minimum 1.025V for Gen2 support
19 mA (A01)
External C
External B
IR
Bluetooth
Camera
External A
External D
AirPort (PCIe Mini-Card)
Geyser Trackpad/Keyboard
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
127 mA (A01, AVDD0 & 1)
If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
39 91
39 91
9
91
9
91
9
91
9
91
30 91
30 91
40 91
40 91
49 91
49 91
30 91
30 91
39 91
39 91
31 91
31 91
91 96 98
91 96 98
39
39
98
31 42
MF-LF
1%
1/16W
402
2.49K
R2010
1
2
806
MF-LF
1%
1/16W
402
R2060
1
2
5%
8.2K
MF-LF
1/16W
402
R2053
1
2
402
1/16W
MF-LF
5%
8.2K
R2052
1
2
5%
8.2K
1/16W
402
MF-LF
R2051
1
2
402
1/16W
MF-LF
5%
8.2K
R2050
1
2
(8 OF 11)
MCP79-TOPO-B
OMIT
BGA
U1400
AD35
AD37
AD38
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24
AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13
AN14
AL14
AM13
AM14
AF19
AG16
AG17
AG19
AH17
AH19
AE16
L28
AJ5
AJ4
AJ6
AJ7
AJ9
AK9
AJ10
AJ11
AJ2
AJ1
AJ3
AK2
AL4
AK3
AL3
AM4
AM2
AM3
AM1
AN1
AN3
AN2
AP2
AP3
E12
AE3
D29
C29
G25
F25
L23
K23
D28
C28
B28
A28
G29
F29
L27
K27
J27
J26
G27
F27
E27
D27
L25
K25
J25
H25
L21
K21
J21
H21
A27
38 90
38 90
38 90
38 90
38 90
38 90
38 90
38 90
SYNC_MASTER=T18_MLB
MCP SATA & USB
051-7656
31
123
20
SYNC_DATE=06/06/2008
=PP1V05_S0_MCP_SATA_AVDD1
=PP1V05_S0_MCP_SATA_DVDD0
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_R2D_C_N
SATA_ODD_R2D_C_P
SATA_HDD_D2R_N
SATA_HDD_D2R_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_C_P
TP_SATA_C_D2RP
TP_SATA_C_D2RN
PP1V05_S0_MCP_PLL_SATA
USB_EXTA_OC_L
TP_USB_11N
TP_USB_11P
TP_USB_10P
USB_EXTC_N
USB_EXCARD_N
USB_EXTB_N
USB_EXTB_P
USB_BT_N
USB_BT_P
USB_TPAD_N
USB_TPAD_P
USB_IR_N
USB_IR_P
USB_CAMERA_N
USB_CAMERA_P
USB_EXTD_N
USB_EXTD_P
USB_MINI_N
USB_EXTA_N
USB_EXTA_P
MCP_SATA_TERMP
TP_SATA_F_D2RP
TP_SATA_F_D2RN
TP_SATA_F_R2D_CN
TP_SATA_E_D2RN
TP_SATA_D_R2D_CN
TP_SATA_C_R2D_CN
TP_SATA_C_R2D_CP
TP_MCP_SATALED_L
TP_SATA_D_D2RN
TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN
TP_SATA_E_D2RP
USB_EXTC_P
USB_EXCARD_P
TP_SATA_D_D2RP
=PP1V05_S0_MCP_SATA_DVDD1
=PP1V05_S0_MCP_SATA_AVDD0
TP_SATA_F_R2D_CP
TP_SATA_D_R2D_CP
USB_EXTB_OC_L
PP3V3_S0_MCP_PLL_USB
MCP_USB_RBIAS_GND
EXCARD_OC_L
TP_USB_10N
USB_EXTC_OC_L
=PP3V3_S5_MCP_GPIO
USB_MINI_P
18
9
8
7
7
23
7
7
7
90
7
7
7
7
7
7
7
7
7
7
7
7
7
9
8
7
7
23
91
8
Preliminary
OUT
OUT
OUT
BI
BI
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
IN
OUT
IN
IN
OUT
IN
IN
IN
IN
OUT
HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK
HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA
MCP_VID2/GPIO_15
MCP_VID1/GPIO_14
MCP_VID0/GPIO_13
THERM_DIODE_N
EXT_SMI/GPIO_32#
FANCTL1/GPIO_62
FANRPM1/GPIO_63
FANCTL0/GPIO_61
FANRPM0/GPIO_60
SIO_PME#
KBRDRSTIN#
PKG_TEST
TEST_MODE_EN
BUF_SIO_CLK
CPUVDD_EN
SMB_DATA0
SMB_CLK0
SPKR
HDA_RESET#
HDA_SYNC
HDA_BITCLK
HDA_SDATA_OUT
XTALIN_RTC
XTALOUT
XTALOUT_RTC
JTAG_TRST#
XTALIN
JTAG_TCK
JTAG_TMS
CPU_VLD
JTAG_TDI
JTAG_TDO
RTC_RST#
PS_PWRGD
PWRGD_SB
INTRUDER#
LID#
LLB#
PWRBTN#
RSTBTN#
CPU_DPRSLPVR
SLP_S5#
SLP_S3#
HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA
HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK
A20GATE
GPIO_12/SUS_STAT#/ACCLMTR
HDA_SDATA_IN0
GPIO_1/PWRDN_OK/SPI_CS1
HDA_PULLDN_COMP
THERM_DIODE_P
SLP_RMGT#
SMB_CLK1/MSMB_CLK
SMB_DATA1/MSMB_DATA
SMB_ALERT#/GPIO_64
SPI_CS0/GPIO_10
SPI_CLK/GPIO_11
SPI_DI/GPIO_8
SPI_DO/GPIO_9
SUS_CLK/GPIO_34
+V_DUAL_HDA1
+V_DUAL_HDA2
+V_PLL_NV_H
+V_PLL_SP_SPREF
HDA
MISC
OUT
IN
IN
OUT
IN
IN
OUT
IN
OUT
OUT
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
(MGPIO2)
(MGPIO3)
Int PU (S5)
Int PU (S5)
17 mA
20 mA
37 mA (A01)
7 mA (A01)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
HDA Output Caps
For EMI Reduction on HDA interface
PCI
not use LPC for BootROM override.
LPC_FRAME# high for SPI1 ROM override.
SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
Int PU
Int PU (S5)
Int PU
Int PU
25 MHz
42 MHz 0
LPC ROMs. So Apple designs will
0
1
HDA_SYNC
24 MHz
0
1
1
0
SPI_CLKSPI_DO
0
1
1
14.31818 MHz
BUF_SIO_CLK Frequency
Frequency
31 MHz
NOTE: Straps not provided on this page.
1 MHz
SPI Frequency Select
Frequency
NOTE: MCP79 does not support FWH, only
LPC
SPI0
SPI1
I/F
HDA_SDOUT
BIOS Boot Select
R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls
1
1
0
0
LPC_FRAME#
0
1
0
1
Int PU
Int PD
Int PD
Int PD
Int PU (S5)
NOTE: MCP79 rev A01 does not support
SPI1 option. Rev B01 will.
Int PU
Int PU (S5)
(MXM_OK for MXM systems)
SAFE mode: For ROMSIP
recovery
USER mode: Normal
Connects to SMC for
automatic recovery.
43 91
7
33 36 41 67 82 84
39 41 42 67
7
13 44 91
44 91
7
13 44 91
44 91
21 64
47 96
21 64
21 64
21 30 33
47 96
9
61 88
41
53 91
9
91
53 91
53 91
53 91
MF-LF
1/16W
1%
402
49.9K
R2121
1
2
1%
49.9K
MF-LF
402
1/16W
R2120
1
2
1K
MF-LF
1%
1/16W
402
R2190
1
2
25 91
41
41
MF-LF
402
5%
22
1/16W
R2170
1 2
MF-LF
5%
1/16W
402
22
R2171
1 2
5%
22
MF-LF
1/16W
402
R2173
1 2
402
5%
10K
MF-LF
1/16W
R2163
1
2
MF-LF
8.2K
5%
1/16W
402
R2160
1
2
5%
10K
MF-LF
BOOT_MODE_SAFE
402
1/16W
R2180
1
2
5%
10K
402
MF-LF
BOOT_MODE_USER
1/16W
R2181
1
2
402
5%
22
1/16W
MF-LF
R2172
1 2
9
43
49.9
MF-LF
1/16W
1%
402
R2110
1
2
402
1/16W
MF-LF
5%
10K
R2150
1
2
6
13
6
13
6
13
6
13
6
10PF
50V
5%
402
CERM
C2171
1
2
50V
10PF
5%
402
CERM
C2173
1
2
50V
10PF
5%
402
CERM
C2170
1
2
50V
10PF
5%
402
CERM
C2172
1
2
BGA
(9 OF 11)
MCP79-TOPO-B
OMIT
U1400
K13
AE7
M22
C17 D17
C18
A12
C12
B12
D12
L26
L24
E15
K17
L17
A15
K15
G15
J14
J15
F15
L15
B20
G19
E19
F19
J19
J18
L13
M25
M24
L20
M20
M21
J16
K16
AE18
AE17
L22
E20
C16
D20
D16
C20
C19
J17
G17
H17
M23
L19
G21
K19
F21
D13
C14
C15
B14
C13
B18
K22
C11
B11
A16
A19
B16
B19
38
21 58
25 25
33 36 41 42
21 27 28 41
402
1/16W
MF-LF
5%
100K
R2147
1
2
10K
5%
1/16W
402
MF-LF
R2142
1
2
402
1/16W
MF-LF
5%
10K
R2141
1
2
22K
5%
MF-LF
1/16W
402
R2157
1
2
22K
5%
MF-LF
1/16W
402
R2156
1
2
402
1/16W
22K
5%
MF-LF
R2155
1
2
402
MF-LF
5%
1/16W
100K
R2151
1
2
1/16W
MF-LF
5%
100K
402
R2154
2
1
MF-LF
402
1/16W
5%
10K
R2143
1
2
10K
5%
MF-LF
1/16W
402
R2140
1
2
9
21 42
25
25
25
25
25
41
41
25
43 91
43 91
43 91
MCP HDA & MISC
SYNC_DATE=06/06/2008
SYNC_MASTER=T18_MLB
21
123
31
051-7656
MCP_SPKR
=PP3V3_S0_MCP
PM_SLP_S4_L
PM_SLP_S3_L
AUD_I2C_INT_L
HDA_SYNC_R
TP_MLB_RAM_SIZE
TP_MLB_RAM_VENDOR
SMC_ADAPTER_EN
SMC_IG_THROTTLE_L
MEM_EVENT_L
=PP3V3_S0_MCP_GPIO
SMC_WAKE_SCI_L
MEM_EVENT_L
ODD_PWR_EN_L
HDA_RST_R_L
HDA_SYNC
ARB_DETECT
SM_INTRUDER_L
PM_RSMRST_L
JTAG_MCP_TRST_L
MCP_TEST_MODE_EN
JTAG_MCP_TMS
MCP_VID<1>
MCP_VID<2>
HDA_BIT_CLK_R
HDA_RST_R_L
HDA_SDOUT_R
HDA_SYNC_R
=PP3V3R1V5_S0_MCP_HDA
PP3V3_G3_RTC
HDA_SDOUT
HDA_BIT_CLK
HDA_RST_L
TP_MCP_KBDRSTIN_L
PM_SYSRST_DEBOUNCE_L
MCP_THMDIODE_N
SMBUS_MCP_0_CLK
SPI_MOSI_R
SPI_MISO
PM_CLK32K_SUSCLK_R
JTAG_MCP_TCK
MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT
RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT
SPI_CS0_R_L
PP1V05_S0_MCP_PLL_NV
MCP_HDA_PULLDN_COMP
TP_SB_A20GATE
PM_SLP_RMGT_L
MCP_VID<1>
SMC_RUNTIME_SCI_L
SPI_CLK_R
=SPI_CS1_R_L_USE_MLB
HDA_BIT_CLK_R
HDA_SDOUT_R
PM_BATLOW_L
SMBUS_MCP_0_DATA
MCP_VID<2>
AP_PWR_EN
SMBUS_MCP_1_DATA
JTAG_MCP_TDO
JTAG_MCP_TDI
MCP_PS_PWRGD
RTC_RST_L
PM_PWRBTN_L
TP_MCP_LID_L
SMBUS_MCP_1_CLK
MCP_THMDIODE_P
MCP_VID<0>
MCP_CPUVDD_EN
HDA_SDIN0
PM_DPRSLPVR
MCP_VID<0>
MCP_CPU_VLD
MCP_GPIO_4
AUD_I2C_INT_L
=PP3V3_S3_MCP_GPIO
AP_PWR_EN
MCP_GPIO_4
=PP3V3R1V5_S0_MCP_HDA
ARB_DETECT
TP_MCP_BUF_SIO_CLK
SMC_IG_THROTTLE_L
41
23
28
19
23
33
23
22
91
42
27
18
91
64
64
91
91
91
91
21
25
91
91
64
58
30
21
8
21
7
7
21
21
8
21
21
21
21
21
21
21
21
8
22
7
23
91
7
21
21
21
21
21
8
21
21
8
21
7
Preliminary
GND
GND161
GND165
GND166
GND164
GND163
GND162
GND167
GND168
GND171
GND170
GND169
GND172
GND173
GND176
GND175
GND174
GND177
GND178
GND181
GND180
GND179
GND182
GND183
GND184
GND187
GND186
GND185
GND188
GND189
GND192
GND191
GND190
GND193
GND194
GND197
GND196
GND195
GND198
GND202
GND201
GND200
GND199
GND203
GND206
GND207
GND205
GND204
GND208
GND212
GND211
GND210
GND209
GND213
GND214
GND217
GND216
GND215
GND218
GND219
GND222
GND221
GND220
GND223
GND224
GND225
GND228
GND227
GND226
GND229
GND230
GND233
GND232
GND231
GND234
GND235
GND238
GND237
GND236
GND239
GND240
GND243
GND242
GND241
GND244
GND248
GND247
GND246
GND245
GND249
GND252
GND251
GND250 GND342
GND341
GND343
GND340
GND339
GND338
GND337
GND336
GND335
GND334
GND333
GND331
GND332
GND330
GND329
GND328
GND326
GND327
GND325
GND324
GND323
GND321
GND322
GND320
GND319
GND318
GND316
GND317
GND315
GND314
GND313
GND311
GND310
GND312
GND309
GND308
GND305
GND306
GND307
GND304
GND303
GND301
GND300
GND302
GND299
GND298
GND296
GND295
GND297
GND294
GND293
GND292
GND291
GND290
GND289
GND288
GND287
GND285
GND286
GND284
GND283
GND282
GND280
GND281
GND279
GND278
GND277
GND275
GND276
GND274
GND273
GND272
GND270
GND269
GND271
GND268
GND267
GND264
GND265
GND266
GND263
GND262
GND259
GND260
GND261
GND258
GND257
GND255
GND254
GND256
GND253
+VTT_CPUCLK
+VDD_CORE42
+3.3V_DUAL_USB2
+VTT_CPU17
+VTT_CPU16
+VTT_CPU15
+VTT_CPU14
+VTT_CPU13
+VTT_CPU12
+VTT_CPU11
+VTT_CPU10
+VTT_CPU1
+VDD_CORE7
+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VTT_CPU51
+VTT_CPU50
+VTT_CPU47
+VTT_CPU46
+VTT_CPU45
+VTT_CPU43
+VTT_CPU42
+VTT_CPU41
+VTT_CPU40
+VTT_CPU39
+VTT_CPU38
+VTT_CPU37
+VTT_CPU36
+VTT_CPU35
+VTT_CPU34
+VTT_CPU32
+VTT_CPU31
+VTT_CPU30
+VTT_CPU29
+VTT_CPU28
+VTT_CPU26
+VTT_CPU25
+VTT_CPU24
+VTT_CPU23
+VTT_CPU22
+VTT_CPU21
+VTT_CPU20
+VTT_CPU19
+VTT_CPU18
+VTT_CPU9
+VTT_CPU8
+VTT_CPU7
+VTT_CPU6
+VTT_CPU5
+VTT_CPU4
+VTT_CPU3
+VDD_CORE38
+VTT_CPU33
+VTT_CPU27
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81
+VBAT
+3.3V_1
+3.3V_8
+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4
+3.3V_DUAL_USB1
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4
+VDD_AUXC1
+VDD_AUXC3
+VDD_AUXC2
+VDD_CORE43
+VTT_CPU2
+VDD_CORE46
+VDD_CORE45
+VDD_CORE44
+VTT_CPU52
+VDD_CORE31
+VTT_CPU49
+VTT_CPU48
+VTT_CPU44
+3.3V_7
+3.3V_6
+3.3V_5
+3.3V_4
+3.3V_3
+3.3V_2
+VDD_CORE20
+VDD_CORE12
+VDD_CORE11
+VDD_CORE10
+VDD_CORE9
+VDD_CORE8
POWER
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
105 mA (A01)
43 mA
1139 mA
250 mA
16996 mA (A01, 1.0V)
23065 mA (A01, 1.2V)
80 uA (S0)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
10 uA (G3)
16 mA
266 mA (A01)
450 mA (A01)
1182 mA (A01)
BGA
OMIT
MCP79-TOPO-B
(11 OF 11)
U1400
AH26
AH33
AH34
AH37
AH38
AJ39
AJ8
AK10
AK33
AK34
AK37
AK4
AK40
AL36
AL40
AL5
AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38
AM5
AM6
AM7
AM9
AP26
AN28
AN30
AN39
AN4
Y7
AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37
AP4
AP40
AP7
AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33
AT6
AT7
AT9
AY21
AY22
L12
AU12
AU28
AP33
AU32
AR30
AU36
AU38
AU4
G28
F20
AV28
AV32
AV36
AV4
AV7
AW11
G20
AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41
AV40
BA1
BA4
AW31
AY6
L35
BC33
BC37
BC41
AY14
BC5
C2
D10
D14
D15
D18
D19
D22
D23
D26
D30
D37
D6
E13
E17
E21
E25
E29
E33
F12
F16
F32
F8
G10
G12
G14
G16
BC12
G22
G24
AW20
G34
G4
G43
G6
G8
H11
H15
AW35
H23
AN8
G40
J12
J8
K10
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
Y11
AH16
T22
(10 OF 11)
BGA
MCP79-TOPO-B
OMIT
U1400
AD10
AE8
AB10
AD9
Y10
AB11
AA8
Y9
G18
H19
J20
K20
G26
H27
J28
K28
A20
T21
U21
V21
AA25
AA26
AA27
AA28
AC16
AC17
AC18
AC19
AC20
AC21
AA17
AC23
AC24
AC25
AC26
AC27
AC28
AD21
AD23
W27
V25
AA18
U25
AE19
AE21
AE23
AE25
AE26
AE27
AE28
AF10
AF11
AA19
AH12
AF2
AF21
AF23
AF25
AF3
AF4
AF7
AH23
AF9
AA20
AG10
AG11
AG12
AG21
AG23
AG25
AG3
AG4
AA21
AG6
AG7
AG5
AG8
AG9
AH1
AH10
AH11
W26
AH2
AA23
W28
AH25
Y21
AH21
AH3
AH4
AH5
AH6
AH7
AH9
AA24
W21
W23
Y23
W25
AF12
AA16
R32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
AC32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
E40
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
J36
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
N32
P32
Y32
AA32
T32
U32
V32
W32
AG32
SYNC_DATE=06/06/2008
SYNC_MASTER=T18_MLB
051-7656
31
123
22
MCP Power & Ground
=PP3V3_S5_MCP
=PP1V05_S5_MCP_VDD_AUXC
=PP3V3_S0_MCP
PP3V3_G3_RTC
=PPVCORE_S0_MCP
=PP1V05_S0_MCP_FSB
23
23
45 14
23
23
21
25
23
9
8
8
8
21
8 8
Preliminary
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
562 mA (A01)
84 mA (A01)
270 mA (A01)
Apple: 2x 2.2uF 0402 (4.4 uF)
NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
MCP 1.05V RMGT Power
Apple: 1x 2.2uF 0402 (2.2 uF)
5 mA (A01)
Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
(No IG vs. EG data)
19 mA (A01)
450 mA (A01)
57 mA (A01) 43 mA (A01)
127 mA (A01)
206 mA (A01)
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
37 mA (A01)
87 mA (A01)
84 mA (A01)
83 mA (A01)
131 mA (A01)105 mA (A01)
MCP PCIE (DVDD) Power
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
16996 mA (A01, 1.0V)
23065 mA (A01, 1.2V)
MCP 3.3V Ethernet Power
MCP79 Ethernet VRef
Apple: 1x 2.2uF 0402 (2.2 uF)
MCP 3.3V AUX/USB Power
266 mA (A01)
MCP 3.3V/1.5V HDA Power
MCP 1.05V AUX Power
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)
NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
MCP FSB (VTT) Power
MCP Memory Power
MCP 3.3V Power
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
MCP Core Power
333 mA (A01)
19 mA (A01)
7 mA (A01)
1182 mA (A01)
MCP SATA (DVDD) Power
5 mA (A01)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)
NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
4771 mA (A01, DDR3)
Apple: 1x 2.2uF 0402 (2.2 uF)
4V
4.7UF
20%
X5R
402
C2582
1
2
20%
4.7UF
4V
X5R
402
C2588
1
2
4.7UF
20%
4V
X5R
402
C2584
1
2
4V
4.7UF
20%
X5R
402
C2586
1
2
CERM
402-LF
20%
2.2UF
6.3V
C2555
1
2
4.7UF
4V
20%
X5R
402
C2502
1
2
X5R
402-1
1UF
10%
10V
C2507
1
2
X5R
402-1
1UF
10%
10V
C2506
1
2
X5R
402-1
1UF
10%
10V
C2505
1
2
X5R
402-1
1UF
10%
10V
C2504
1
2
0.1UF
CERM
20%
402
10V
C2511
1
2
0.1UF
CERM
20%
402
10V
C2510
1
2
0.1UF
CERM
20%
402
10V
C2509
1
2
0.1UF
CERM
20%
402
10V
C2508
1
2
0.1UF
CERM
20%
402
10V
C2513
1
2
0.1UF
CERM
20%
402
10V
C2512
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2536
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2535
1
2
2.2UF
6.3V
20%
402-LF
CERM
C2534
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2533
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2532
1
2
20%
2.2UF
6.3V
402-LF
CERM
C2531
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2530
1
2
X5R
402-1
1UF
10%
10V
C2517
1
2
X5R
402-1
1UF
10%
10V
C2516
1
2
4.7UF
4V
20%
X5R
402
C2515
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2572
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2571
1
2
4V
4.7UF
20%
X5R
402
C2520
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2570
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2574
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2573
1
2
CERM
402-LF
20%
2.2UF
6.3V
C2576
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2575
1
2
2.2UF
6.3V
20%
402-LF
CERM
C2553
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2552
1
2
2.2UF
6.3V
20%
402-LF
CERM
C2551
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2550
1
2
0.1UF
20%
CERM
402
10V
C2549
1
2
0.1UF
20%
CERM
402
10V
C2548
1
2
0.1UF
20%
CERM
402
10V
C2547
1
2
0.1UF
20%
CERM
402
10V
C2546
1
2
0.1UF
20%
CERM
402
10V
C2545
1
2
0.1UF
20%
CERM
402
10V
C2544
1
2
0.1UF
20%
CERM
402
10V
C2543
1
2
20%
CERM
0.1UF
402
10V
C2542
1
2
0.1UF
CERM
20%
402
10V
C2541
1
2
20%
4.7UF
4V
X5R
402
C2540
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2562
1
2
CERM
402-LF
20%
2.2UF
6.3V
C2564
1
2
402
X5R
4V
20%
4.7UF
C2580
1
2
0603
30-OHM-5A
L2570
1 2
30-OHM-5A
0603
L2575
1 2
30-OHM-1.7A
0402
L2582
1 2
30-OHM-1.7A
0402
L2584
1 2
30-OHM-1.7A
0402
L2588
1 2
0402
30-OHM-1.7A
L2586
1 2
0402
30-OHM-1.7A
L2555
1 2
4.7UF
4V
20%
X5R
402
C2500
1
2
4.7UF
4V
20%
X5R
402
C2501
1
2
CERM
20%
0.1uF
402
10V
C2526
1
2
CERM
20%
0.1uF
402
10V
C2525
1
2
6.3V
2.2UF
20%
402-LF
CERM
C2560
1
2
CERM
20%
2.2UF
402-LF
6.3V
C2589
1
2
CERM
0.1UF
20%
402
10V
C2590
1
2
20%
4.7UF
4V
X5R
402
C2595
1
2
30-OHM-1.7A
0402
L2595
1 2
1.47K
1/16W
1%
MF-LF
402
R2590
1
2
0.1UF
CERM
20%
402
10V
C2591
1
2
MF-LF
1%
1/16W
1.47K
402
R2591
1
2
18
CERM
20%
0.1uF
402
10V
C2521
1
2
0.1uF
20%
CERM
402
10V
C2518
1
2
0.1uF
CERM
20%
402
10V
C2519
1
2
CERM
20%
2.2UF
402-LF
6.3V
C2583
1
2
20%
CERM
2.2UF
402-LF
6.3V
C2585
1
2
20%
CERM
2.2UF
402-LF
6.3V
C2587
1
2
CERM
20%
2.2UF
402-LF
6.3V
C2596
1
2
CERM
20%
0.1uF
402
10V
C2529
1
2
20%
4.7uF
4V
X5R
402
C2528
1
2
603
X5R
16V
10%
2.2UF
C2581
1
2
0.2
1%
1/6W
MF
402-HF
R2580
1 2
4.7UF
4V
20%
X5R
402
C2503
1
2
SYNC_DATE=04/01/2008
SYNC_MASTER=M98_MLB
MCP Standard Decoupling
25
31
051-7656
123
=PP3V3_S5_MCP
PP1V05_ENET_MCP_PLL_MAC
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
=PP3V3_S0_MCP
=PP1V8R1V5_S0_MCP_MEM
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
PP1V05_S0_MCP_PLL_NV
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_CORE
VOLTAGE=1.05V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PEX_AVDD
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP3V3_S0_MCP_PLL_USB
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_SATA
=PP1V05_ENET_MCP_PLL_MAC
=PP3V3_ENET_MCP_RMGT
MCP_MII_VREF
=PP3V3R1V5_S0_MCP_HDA
=PP1V05_S0_MCP_FSB
=PP1V05_S5_MCP_VDD_AUXC
=PP1V05_ENET_MCP_RMGT
=PP3V3_S0_MCP_PLL_UF
=PPVCORE_S0_MCP
=PP3V3_ENET_MCP_RMGT
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_PEX_DVDD
VOLTAGE=1.05V
PP1V05_S0_MCP_SATA_AVDD
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP1V05_S0_MCP_PLL_FSB
VOLTAGE=1.05V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V
PP1V05_S0_MCP_PLL_PEX
=PP1V05_S0_MCP_PLL_PEX_UF
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_AVDD_UF
22
22
23
14
45
23 22
21
16
18
21
9
22 18
22
18
66
8
18
8
8
21
16
8
20
20
8
8
8
8
8 8
8
8
8
8 8
8
14
17
8
8
8
Preliminary
A2
A1
SCL
A0
VCC
SDA
WP
GND
IN
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
190 mA (A01, 1.8V)
Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)
95 mA (A01)
16 mA (A01)
Apple: ???
NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
WF: Checklist says 0-ohm resistor placeholder for ferrite bead.
16 mA (A01)
Apple: 2x 2.2uF 0402 (4.4 uF)
206 mA (A01)
NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)
HDCP ROM
206 mA (A01)
WF: Open question on which packge option(s) nVidia can support.
6.3V
2.2UF
20%
402-LF
CERM
NO STUFF
C2650
1
2
30-OHM-1.7A
0402
NO STUFF
L2650
1 2
NO STUFF
20%
402
CERM
10V
0.1UF
C2620
1
2
NO STUFF
402
1K
1%
1/16W
MF-LF
R2630
1
2
20%
402
CERM
NO STUFF
10V
0.1UF
C2630
1
2
20%
4.7UF
4V
402
X5R
C2615
1
2
CERM
4.7UF
6.3V
20%
603
C2640
1
2
30-OHM-1.7A
0402
L2640
1 2
20%
CERM
2.2UF
402-LF
6.3V
C2641
1
2
6.3V
402-LF
2.2UF
20%
CERM
C2616
1
2
SOIC
AT24C08
U2695
1
2
3
4
6
5
8
7
NO STUFF
402
10V
0.1UF
20%
CERM
1
2
C2690
NO STUFF
10K
MF-LF
5%
1/16W
402
R2690
1
2
NO STUFF
44
44
0
5%
1/16W
MF-LF
402
R2651
1
2
402
1/16W
1%
1K
MF-LF
R2620
1
2
CERM
402-LF
20%
2.2UF
6.3V
C2610
1
2
MCP Graphics Support
SYNC_DATE=04/01/2008
SYNC_MASTER=M98_MLB
26
123
31
051-7656
=PP3V3_S0_HDCPROM
PP3V3_S0_MCP_DAC
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
PP3V3_S0_MCP_VPLL
MCP_CLK27M_XTALOUT
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_CLK27M_XTALOUT
MCP_IFPAB_VPROBE
MCP_IFPAB_RSET
TP_MCP_RGB_GREEN
TP_MCP_RGB_HSYNC
TP_MCP_RGB_RED
TP_MCP_RGB_VSYNC
TP_MCP_RGB_BLUE
NC_MCP_RGB_RED
NO_TEST=TRUE
MAKE_BASE=TRUE
CRT_IG_R_C_PR
TP_MCP_RGB_DAC_RSET
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_HSYNC
CRT_IG_HSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_B_COMP_PB
CRT_IG_B_COMP_PB
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_G_Y_Y
CRT_IG_G_Y_Y
=PP3V3R1V8_S0_MCP_IFP_VDD
=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_CLK27M_XTALIN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_TV_DAC_VREF
NO_TEST=TRUE
NC_MCP_TV_DAC_RSET
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_DAC_VREF
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_DAC_RSET
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_CRT_IG_VSYNC
MAKE_BASE=TRUE
CRT_IG_VSYNC
TP_MCP_RGB_DAC_VREF
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF
MCP_CLK27M_XTALIN
NC_MCP_RGB_GREEN
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_MCP_RGB_VSYNC
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_CRT_IG_R_C_PR
NO_TEST=TRUE
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_HSYNC
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_MCP_RGB_BLUE
MAKE_BASE=TRUE
=PP3V3_S0_MCP_DAC_UF
HDCPROM_WP
=PP3V3_S0_MCP_VPLL_UF
=PP1V05_S0_MCP_HDMI_VDD
MCP_HDMI_VPROBE
MCP_HDMI_RSET
90
90
90
90
90
90
18
90
90
90
18
90
90
8
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
8
18
18
18
18
18
8
8
8
18
18
Preliminary
IN
OUT
IN
OUT
OUT
IN
OUT
IN
IN
IN
OUT
OUT
IN
NC
NC
OUT
OUT
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
OUT
OUTY
B
A
VIN
GND
VOUTEN
NC
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
RTC Crystal
but results in MCP79 ROMSIP sequence happening after CPU powers up.
NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).
Reset Button
10K pull-up to 3.3V S0 inside MCP
LPC Reset (Unbuffered)
Platform Reset Connections
PCIE Reset (Unbuffered)
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.
MCP 25MHz Crystal
SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
MCP S0 PWRGD & CPU_VLD
RTC Power Sources
10 13 21
50V
12pF
402
CERM
5%
C2810
1 2
12pF
402
CERM
50V
5%
C2811
1 2
402
1/16W
0
5%
MF-LF
R2810
1 2
NO STUFF
10M
402
5%
MF-LF
1/16W
R2811
1
2
19 84 91
XDP
1/16W
MF-LF
5%
0
402
R2896
1 2
402
1/16W
5%
MF-LF
33
PLACEMENT_NOTE=Place close to U1400
R2883
1 2
402
PLACEMENT_NOTE=Place close to U1400
MF-LF
1/16W
5%
33
R2881
1 2
0
5%
1/16W
402
MF-LF
R2890
1 2
SILK_PART=FP SYS RESET
OMIT
0
5%
1/16W
MF-LF
402
R2897
1
2
7
43
41
21
21
17
402
1/16W
MF-LF
5%
33
PLACEMENT_NOTE=Place close to U1400
R2826
1 2
402
PLACEMENT_NOTE=Place close to U1400
1/16W
MF-LF
33
5%
R2825
1 2
19 91
50V
5%
CERM
402
12pF
C2815
1 2
402
CERM
5%
12pF
50V
C2816
1 2
SM-3.2X2.5MM
25.0000M
CRITICAL
Y2815
2 4
1 3
MF-LF
0
1/16W
5%
402
R2815
1 2
NO STUFF
MF-LF
402
1/16W
5%
1M
R2816
1
2
21
21
41 91
22
1/16W
5%
MF-LF
402
PLACEMENT_NOTE=Place close to U1400
R2829
1 2
21 91
402
33
MF-LF
5%
1/16W
R2899
1 2
NO STUFF
1UF
10%
X5R
10V
402
C2899
1
2
35
402
0
5%
1/16W
MF-LF
R2892
1 2
9
MF-LF
1/16W
5%
402
33
R2870
1 2
19
7
41
7
43 91
41 91
CRITICAL
7X1.5X1.4-SM
32.768K
Y2810
1 4
402
MF-LF
1/16W
5%
0
R2891
1 2
26
0
5%
1/16W
MF-LF
402
R2893
1 2
86
0
5%
1/16W
MF-LF
402
R2895
1 2
31
30
MF-LF
5%
402
0
1/16W
R2894
1 2
PLACEMENT_NOTE=Place close to U1400
5%
1/16W
402
MF-LF
33
R2827
1 2
84
84
21
61
41 67 84
MCPSEQ_MIX
MF-LF
5%
1/16W
0
402
R2851
1 2
0.1UF
402
CERM
10V
MCPSEQ_SMC
20%
C2850
1
2
MCPSEQ_SMC
5%
MF-LF
1/16W
0
402
PLACEMENT_NOTE=Place close to U1400
R2850
1 2
21
MCPSEQ_SMC
402
0
1/16W
5%
MF-LF
R2853
1 2
21
MCPSEQ_MIX
402
0
1/16W
5%
MF-LF
R2852
1 2
TC7SZ08AFEAPE
MCPSEQ_SMC
SOT665
U2850
2
1
3
5
4
402
X5R
10V
10%
1UF
NO STUFF
C2802
1
2
RTC_PS_YES
CRITICAL
U2801
MIC5232-2.8YD5
TSOT-23-5
3
2
4
1
5
MF-LF
1/16W
402
5%
10
NO STUFF
R2801
1
2
NO STUFF
1.0M
603
MF-LF
1/10W
5%
R2802
12
1UF
CERM
402
10%
6.3V
C2801
1
2
CRITICAL
SUPERCAP_YES
3.3V
SM
XHHG
0.08F
2%
C2800
1
2
SUPERCAP_YES
402
MF-LF
1/16W
5%
100
R2800
1
2
MF-LF
5%
0
1/16W
402
R2803
1 2
SYNC_DATE=05/01/2008
SYNC_MASTER=M98_MLB
SB Misc
123
31
28
051-7656
=PP3V3_S5_RTC_D
=PP3V3_S5_MCPPWRGD
VOLTAGE=3.3V
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PP3V3_G3_RTC
RTC_CLK32K_XTALIN
VR_PWRGOOD_DELAY
ALL_SYS_PWRGD
MCP_CLK25M_XTALOUT
MCP_CLK25M_XTALIN
RTC_CLK32K_XTALOUT_R
MCP_CLK25M_XTALOUT_R
PP3V3_G3_SUPERCAP
MCP_PS_PWRGD
MCP_CPU_VLD
MCP_CPUVDD_EN
=GMUX_PCIE_RESET_L
GMUX_PCIE_RESET_L
MAKE_BASE=TRUE
PM_CLK32K_SUSCLK_R
MEM_VTT_EN_R
LPC_CLK33M_SMC_R
PCA9557D_RESET_L
FW_RESET_L
BKLT_PLT_RST_L
EXCARD_RESET_L
MINI_RESET_L
MEM_VTT_EN
LPC_CLK33M_GMUX
PM_CLK32K_SUSCLK
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS
SMC_LRESET_L
DEBUG_RESET_L
LPC_RESET_L
PM_SYSRST_L
PM_SYSRST_DEBOUNCE_L
XDP_DBRESET_L
S0_AND_IMVP_PGOOD
PCIE_RESET_L
RTC_CLK32K_XTALOUT
RTC_DISCHARGE_R
22
8
8
21
Preliminary
OUT
OUT
OUT
V-
V+
V-
V+
V-
V+
V-
V+
V-
V+
V-
V+
RESET*
A0
A1
A2
SCL
SDA
P0
P1
P2
P5
P6
P7
P3
P4
THRM
VCC
GND
PAD
NC
NC
IN
IN
BI
VDD
VOUTD
VOUTC
VOUTB
VOUTA
SCL
SDA
A0
A1
GND
IN
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
DESCRIPTION
REFERENCE DES
BOM OPTION
QTY
PART NUMBER
CRITICAL
BOM options provided by this page:
- =I2C_PCA9557D_SCL
- =I2C_VREFDACS_SDA
NO_VREFMRGN
- =I2C_VREFDACS_SCL
- =PP3V3_S5_VREFMRGN
- =PP3V3_S3_VREFMRGN
- =PPVTT_S3_DDR_BUF
Place close to J3200.126
Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V
Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V
(i.e. not simultaneously) due to current limitation of TPS51116 regulator.
SO-DIMM A and SO-DIMM B Vref settings should be margined separately
MEM B VREF DQMEM A VREF CAMEM A VREF DQ
(per DAC LSB)
VREFMRGN
Place close to J3100.126
Place close to J3100.1
10mA max load
Place close to U1000.AD26
Place close to U8500, U8550
Place close to U8400, U8450
CPU FSB VREF
FRAME BUFFER VREF
MEM B VREF CA
Place close to J3200.1
Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV
Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V
Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA
Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA
Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF
Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00
DAC channel A B A B C D
Required zero ohm resistors when no VREF margining circuit stuffed
ADDR=0x30(WR)/0x31(RD)
Page Notes
Power aliases required by this page:
Signal aliases required by this page:
ADDR=0x98(WR)/0x99(RD)
- =I2C_PCA9557D_SDA
9
1/16W
MF-LF
VREFMRGN
1%
49.9
402
R2916
1 2
10 88
VREFMRGN
0.1UF
20%
CERM
402
10V
C2902
1
2
100
402
1%
VREFMRGN
1/16W
MF-LF
R2914
1 2
5%
VREFMRGN
MF-LF
402
1/16W
100K
R2913
1 2
VREFMRGN
1%
200
1/16W
MF-LF
402
R2903
1 2
MF-LF
1/16W
5%
VREFMRGN
402
100K
R2915
1 2
9
MF-LF
1/16W
402
49.9
1%
VREFMRGN
R2917
1 2
UCSP
MAX4253
VREFMRGN
U2902
C3
C2
C1
C4
B1
B4
UCSP
VREFMRGN
MAX4253
U2903
A3
A2
A1
A4
B1
B4
UCSP
VREFMRGN
MAX4253
U2902
A3
A2
A1
A4
B1
B4
UCSP
MAX4253
VREFMRGN
U2903
C3
C2
C1
C4
B1
B4
UCSP
VREFMRGN
MAX4253
U2904
A3
A1
A4
B1
B4
A2
UCSP
MAX4253
VREFMRGN
U2904
C3
C2
C1
C4
B1
B4
VREFMRGN
1%
200
1/16W
MF-LF
402
R2905
1 2
402
MF-LF
1/16W
200
1%
VREFMRGN
R2909
1 2
VREFMRGN
1%
200
1/16W
MF-LF
402
R2911
1 2
R2918
402
21
NONE
NONE
SHORT
NONE
R2919
402
21
NONE
NONE
NONE
SHORT
5%
100K
1/16W
MF-LF
402
VREFMRGN
R2902
1 2
100K
1/16W
5%
VREFMRGN
MF-LF
402
R2901
1 2
402
100
1%
1/16W
MF-LF
VREFMRGN
R2904
1 2
MF-LF
VREFMRGN
402
1%
1/16W
100
R2906
1 2
402
MF-LF
1/16W
1%
100
VREFMRGN
R2910
1 2
MF-LF
VREFMRGN
402
1/16W
100K
5%
R2907
1 2
CRITICAL
PCA9557
VREFMRGN
QFN
U2901
3
4
5
8
6
7
9
10
11
12
13
14
15
1
2
17
16
VREFMRGN
402
0.1UF
20%
CERM
10V
C2904
1
2
402
100
MF-LF
1%
VREFMRGN
1/16W
R2912
1 2
5%
402
1/16W
100K
MF-LF
VREFMRGN
R2908
1 2
25
44
44
DAC5574
MSOP
VREFMRGN
U2900
9
10
3
6
7
8
1
2
4
5
44
44
10V
402
VREFMRGN
0.1UF
CERM
20%
C2901
1
2
C2900
2.2UF
CERM
402-LF
6.3V
20%
VREFMRGN
1
2
20%
CERM
402
10V
0.1UF
C2905
1
2
VREFMRGN
CERM
0.1UF
VREFMRGN
402
20%
10V
C2903
1
2
FSB/DDR3/FRAMEBUF Vref Margining
SYNC_MASTER=BEN_K20
051-7656
31
123
29
SYNC_DATE=10/15/2008
R2903
CRITICAL
NO_VREFMRGN
1
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
CRITICAL
1
R2911
NO_VREFMRGN
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
1
R2909
CRITICAL
NO_VREFMRGN
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
CRITICAL
1
R2905
NO_VREFMRGN
116S0004
RES,MTL FILM,0,5%,0402,SM,LF
=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA
=PP3V3_S3_VREFMRGN
PP3V3_S3_VREFMRGN_CTRL
PP3V3_S3_VREFMRGN_DAC
=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA
VREFMRGN_CPUFSB
GPU_FB_A_VREF_DIV
GPU_FB_B_VREF_DIV
CPU_GTLREF
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_DQ_SODIMMA_EN
PCA9557D_RESET_L
VREFMRGN_CPUFSB_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_FRAMEBUF_EN
VREFMRGN_DQ_SODIMMB_BUF
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_CA_SODIMMA_BUF
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_DQ_SODIMM
VREFMRGN_DQ_SODIMMA_BUF
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_CA_SODIMM
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_FRAMEBUF_BUF
VREFMRGN_FRAMEBUF_EN
VREFMRGN_CPUFSB_BUF
VREFMRGN_CPUFSB_EN
VREFMRGN_CA_SODIMMB_BUF
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP0V75_S3_MEM_VREFDQ_A
MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
PP0V75_S3_MEM_VREFDQ_B
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP0V75_S3_MEM_VREFCA_A
MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.3 mm
PP0V75_S3_MEM_VREFCA_B
=PPVTT_S3_DDR_BUF
VREFMRGN_FRAMEBUF
VREFMRGN_CA_SODIMMA_EN
63
8
26
26
26
26
26
26
26
26
26
26
26
27
28
27
28
8
26
Preliminary
A6
A7
A11
A5
DQ33
VDD
A10/AP
VDD
VSS
SA1
VTT
VSS
DQS4*
DQS4
VSS
DQ35
VSS
CK0*
SA0
VSS
DQ58
DQ59
DM7
VSS
DQ57
DQ56
DQ50
DQ51
VSS
DQS6*
DQS6
VSS
DQ49
DQ48
DQ43
VSS
DM5
VSS
DQ42
SDA
SCL
VTT
VSS
EVENT*
DQ62
VSS
DQ63
DQS7*
DQS7
DQ60
DQ61
VSS
VSS
DQ55
DQ54
DM6
VSS
DQ53
VSS
DQ52
DQ47
VSS
DQS5
VSS
DQ46
DQ41
VSS
DQ40
DQ34
VSS
DQ32
TEST
VDD
VDD
S1*
A13
CAS*
WE*
BA0
VDD
VDD
CK0
A1
A3
VDD
VDD
A8
A9
A12/BC*
VDD
BA2
NC
VDD
CKE0
VSS
DQS5*
VSS
DQ44
DQ45
DQ39
DQ38
VSS
VSS
DM4
VSS
DQ37
DQ36
VREFCA
VDD
ODT1
NC
S0*
ODT0
BA1
RAS*
VDD
CK1*
VDD
VDD
A0
CK1
A2
VDD
A4
VDD
VDD
A14
A15
CKE1
VDD
VSS
VDDSPD
KEY
(SYMBOL 2 OF 2)
BI
BIBI
BI
IN
BI
BI
BI
BI
BI
BI
IN
BI
IN
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
DQ16
DM3
DQ26
DQ27
DQ4
DQ31
DQ30
DQS3
DQS3*
DQ29
DQ28
DQ23
DQ22
DM2
DQ21
DQ20
DQ15
DQ14
RESET*
DM1
DQ13
DQ12
DQ7
DQ6
DQS0
DQS0*
DQ5
DQ24
DQ25
DQ19
DQ18
DQS2
DQS2*
DQ17
DQ11
DQ10
DQS1
DQS1*
DQ8
DQ9
DM0
DQ0
DQ1
VREFDQ
DQ3
DQ2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
(SYMBOL 1 OF 2)
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
IN
BI
BI
IN
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
NC
NC
NC
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
Page Notes
SPD ADDR=0xA0(WR)/0xA1(RD)
- =PP1V5_S0_MEM_A
- =PPSPD_S0_MEM_A (2.5 - 3.3V)
Signal aliases required by this page:
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
"Factory" (top) slot
(NONE)
- =I2C_SODIMMA_SDA
Power aliases required by this page:
- =PP0V75_S0_MEM_VTT_A
- =I2C_SODIMMA_SCL
- =PP1V5_S3_MEM_A
BOM options provided by this page:
516-0201
516-0201
DDR3-SODIMM-DUAL-M97-3
F-RT-THB
J3100
9897
107
8483
119
80
78
9695
9291
90
86
89
85
109
108
79
115
101
103
102
104
73 74
136
153
170
187
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
137
135
154
152
171
169
188
186
198
77
122
116
120
110
114
121
197
201 202
200
125
75 76
105 106
111 112
117 118
123 124
81 82
87 88
93 94
99
100
199
126
127 128
133 134
138
139
144
145
150
151
155 156
161 162
167 168
172
173
178
179
184
185
189 190
195 196
203 204
113
15 89
15 89
0.1UF
CERM
402
20%
10V
C3131
1
2
6.3V
CERM
402-LF
20%
2.2UF
C3130
1
2
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
28 29
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
CRITICAL
DDR3-SODIMM-DUAL-M97-3
F-RT-THB
J3100
11
28
46
63
5
7
33
35
22
24
34
36
39
41
51
53
15
40
42
50
52
57
59
67
69
56
58
17
68
70
4
6
16
18
21
23
12
10
29
27
47
45
64
62
30
1 2
3
31 32
37 38
43 44
48
49
54
55
8
60
61
65 66
71 72
9
13 14
19 20
25 26
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
9
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
10V
20%
402
CERM
0.1UF
C3136
1
2
402-LF
20%
6.3V
2.2UF
CERM
C3135
1
2
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
21 28 41
44
44
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
10K
5%
402
1/16W
MF-LF
R3141
1
2
10K
MF-LF
1/16W
5%
402
R3140
1
2
2.2UF
20%
CERM
402-LF
6.3V
C3140
1
2
10UF
20%
X5R
6.3V
603
C3100
1
2
6.3V
10UF
X5R
603
20%
C3101
1
2
CERM
402
10V
20%
0.1UF
C3110
1
2
0.1UF
402
CERM
10V
20%
C3111
1
2
CERM
0.1UF
20%
10V
402
C3112
1
2
CERM
402
0.1UF
10V
20%
C3113
1
2
10V
0.1UF
402
CERM
20%
C3114
1
2
0.1UF
20%
402
CERM
10V
C3115
1
2
10V
0.1UF
20%
402
CERM
C3116
1
2
10V
0.1UF
20%
402
CERM
C3117
1
2
10V
0.1UF
20%
402
CERM
C3118
1
2
10V
0.1UF
20%
402
CERM
C3119
1
2
10V
20%
402
CERM
0.1UF
C3120
1
2
10V
0.1UF
20%
402
CERM
C3121
1
2
10V
0.1UF
20%
402
CERM
C3122
1
2
10V
0.1UF
20%
402
CERM
C3123
1
2
SYNC_MASTER=BEN_K20
SYNC_DATE=06/10/2008
DDR3 SO-DIMM Connector A
051-7656
31
123
31
MEM_A_DQ<43>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
=PP1V5_S3_MEM_A
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<11>
MEM_A_A<5>
MEM_A_DQ<32>
MEM_A_A<10>
MEM_A_SA<1>
=PP0V75_S0_MEM_VTT_A
MEM_A_DQS_N<4>
MEM_A_DQS_P<4>
MEM_A_DQ<35>
MEM_A_CLK_N<0>
MEM_A_SA<0>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DM<7>
MEM_A_DQ<60>
MEM_A_DQ<61>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQ<51>
MEM_A_DQ<52>
MEM_A_DQ<42>
MEM_A_DM<5>
MEM_A_DQ<45>
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL
MEM_EVENT_L
MEM_A_DQ<62>
MEM_A_DQ<63>
MEM_A_DQS_N<7>
MEM_A_DQS_P<7>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<49>
MEM_A_DQ<50>
MEM_A_DM<6>
MEM_A_DQ<53>
MEM_A_DQ<48>
MEM_A_DQ<46>
MEM_A_DQ<41>
MEM_A_DQ<44>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_CS_L<1>
MEM_A_A<13>
MEM_A_CAS_L
MEM_A_WE_L
MEM_A_BA<0>
MEM_A_CLK_P<0>
MEM_A_A<1>
MEM_A_A<3>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<12>
MEM_A_BA<2>
MEM_A_CKE<0>
MEM_A_DQ<47>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DM<4>
MEM_A_DQ<37>
MEM_A_DQ<36>
PP0V75_S3_MEM_VREFCA_A
MEM_A_ODT<1>
MEM_A_CS_L<0>
MEM_A_ODT<0>
MEM_A_BA<1>
MEM_A_RAS_L
MEM_A_CLK_N<1>
MEM_A_A<0>
MEM_A_CLK_P<1>
MEM_A_A<2>
MEM_A_A<4>
MEM_A_A<14>
MEM_A_A<15>
MEM_A_CKE<1>
=PPSPD_S0_MEM_A
MEM_A_DQ<16>
MEM_A_DM<3>
MEM_A_DQ<27>
MEM_A_DQ<25>
MEM_A_DQ<4>
MEM_A_DQ<31>
MEM_A_DQ<26>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQ<28>
MEM_A_DQ<29>
MEM_A_DQ<22>
MEM_A_DQ<17>
MEM_A_DM<2>
MEM_A_DQ<20>
MEM_A_DQ<21>
MEM_A_DQ<10>
MEM_A_DQ<15>
MEM_RESET_L
MEM_A_DM<1>
MEM_A_DQ<12>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQ<5>
MEM_A_DQ<24>
MEM_A_DQ<30>
MEM_A_DQ<19>
MEM_A_DQ<23>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQ<18>
MEM_A_DQ<14>
MEM_A_DQ<11>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQ<9>
MEM_A_DQ<13>
MEM_A_DM<0>
MEM_A_DQ<0>
MEM_A_DQ<1>
PP0V75_S3_MEM_VREFDQ_A
MEM_A_DQ<2>
MEM_A_DQ<3>
=PP1V5_S0_MEM_A
8
8
26
8
26
8
Preliminary
IN
BI
BI
BI
OUT
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
NC
IN
VDD
A1
A3
VDD
A5
A8
VDD
A9
VDD
A12/BC*
VSS
DQ42
DQ43
DQ48
DQ49
VSS
VSS
DQ41
DQS4*
DM5
VDD
CKE1
A15
A14
VDD
A11
A7
A6
VDD
A4
A2
CK1
A0
VDD
VDD
CK1*
VDD
RAS*
BA1
ODT0
S0*
NC
ODT1
VDD
VREFCA
VDD
DQ36
DQ37
VSS
DM4
VSS
VSS
DQ38
DQ39
DQ45
DQ44
VSS
DQS5*
VSS
CKE0
VDD
NC
BA2
CK0
VDD
BA0
WE*
A13
S1*
VDD
VDD
TEST
DQ33
DQ32
VSS
DQ34
DQ40
VSS
DQ46
VSS
DQS5
VSS
DQ47
DQ52
VSS
DQ53
VSS
DM6
DQ54
DQ55
VSS
VSS
DQ61
DQ60
DQS7
DQS7*
DQ63
VSS
DQ62
EVENT*
VSS
VTT
SCL
SDA
VSS
DQS6
DQS6*
VSS
DQ51
DQ50
A10/AP
VDD
CK0*
DQ35
VSS
DQS4
VSS
CAS*
VDD
DM7
VSS
DQ56
MTG PIN
MTG PIN
MTG PIN MTG PIN
MTG PIN
MTG PIN
MTG PIN
VSS
DQ57
VTT
SA1
SA0
DQ58
VSS
DQ59
VSS
VDDSPD
MTG PIN
MTG PINS
KEY
(2 OF 2)
BI
BI
BI
BI
BI
BI
IN
BI
IN
BI
BI
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
DQ2
DQ3
VREFDQ
DQ1
DQ0
DM0
DQ9
DQ8
DQS1*
DQS1
DQ10
DQ11
DQ17
DQS2*
DQS2
DQ18
DQ19
DQ25
DQ24
DQ5
DQS0*
DQS0
DQ6
DQ7
DQ12
DQ13
DM1
RESET*
DQ14
DQ15
DQ20
DQ21
DM2
DQ22
DQ23
DQ28
DQ29
DQS3*
DQS3
DQ30
DQ31
DQ4
DQ27
DQ26
DM3
DQ16
(1 OF 2)
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
KEY
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
IN
IN
BI
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
BI
BI
BI
BI
IN
BI
BI
IN
BI
BI
IN
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
IN
BI
BI
BI
BI
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
- =PP1V5_S0_MEM_B
- =PP1V5_S3_MEM_B
- =PP0V75_S0_MEM_VTT_B
(NONE)
Power aliases required by this page:
BOM options provided by this page:
DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)
- =PPSPD_S0_MEM_B (2.5 - 3.3V)
- =I2C_SODIMMB_SDA
- =I2C_SODIMMB_SCL
Signal aliases required by this page:
Page Notes
SPD ADDR=0xA2(WR)/0xA3(RD)
516s0706
516s0706
"Expansion" (bottom) slot
15 89
15 89
15 89
15 89
21 27 41
44
44
10V
20%
402
CERM
0.1UF
C3231
1
2
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
CERM
402-LF
6.3V
20%
2.2UF
C3230
1
2
10K
1/16W
MF-LF
5%
402
R3241
1
2
10K
5%
1/16W
R3240
1
MF-LF
2
402
2
1
C3240
20%
CERM
402-LF
6.3V
2.2UF
603
6.3V
X5R
20%
10UF
C3200
1
2
20%
603
X5R
10UF
6.3V
C3201
1
2
0.1UF
20%
10V
402
CERM
C3210
1
2
20%
10V
CERM
402
0.1UF
C3211
1
2
402
10V
20%
0.1UF
CERM
C3212
1
2
20%
10V
0.1UF
402
CERM
C3213
1
2
15 89
20%
CERM
402
0.1UF
10V
C3214
1
2
10V
CERM
402
20%
0.1UF
C3215
1
2
CERM
402
20%
0.1UF
10V
C3216
1
2
CERM
402
20%
0.1UF
10V
C3217
1
2
CERM
402
20%
0.1UF
10V
C3218
1
2
CERM
402
20%
0.1UF
10V
C3219
1
2
0.1UF
CERM
402
20%
10V
C3220
1
2
CERM
402
20%
0.1UF
10V
C3221
1
2
CERM
402
20%
0.1UF
10V
C3222
1
2
CERM
402
20%
0.1UF
10V
C3223
1
2
15 89
15 89
113
204203
212211
210209
208207
206205
196195
190189
185
184
179
178
173
172
168167
162161
156155
151
150
145
144
139
138
134133
128127
126
199
100
99
9493
8887
8281
124123
118117
112111
106105
7675
125
200
202201
197
121
114
110
120
116
122
77
198
186
188
169
171
152
154
135
137
194
192
182
180
193
191
183
181
176
174
166
164
177
175
165
163
160
158
148
146
159
157
149
147
142
140
132
130
143
141
131
129
187
170
153
136
7473
104
102
103
101
115
79
108
109
85
89
86
90
91 92
95 96
78
80
119
83 84
107
97 98
J3200
DDR3-SODIMM
F-RT-BGA3
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
27 29
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
F-RT-BGA3
CRITICAL
DDR3-SODIMM
J3200
11
28
46
63
5
7
33
35
22
24
34
36
39
41
51
53
15
40
42
50
52
57
59
67
69
56
58
17
68
70
4
6
16
18
21
23
12
10
29
27
47
45
64
62
30
1 2
3
31 32
37 38
43 44
48
49
54
55
8
60
61
65 66
71 72
9
13 14
19 20
25 26
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
9
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
CERM
0.1UF
20%
402
10V
C3236
1
2
2.2UF
6.3V
CERM
20%
402-LF
C3235
1
2
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
15 89
SYNC_MASTER=BEN_K20
32
123
31
051-7656
SYNC_DATE=07/14/2008
DDR3 SO-DIMM Connector B
=PPSPD_S0_MEM_B
MEM_B_SA<0>
MEM_B_A<10>
=PP1V5_S3_MEM_B
=PP0V75_S0_MEM_VTT_B
=PP1V5_S0_MEM_B
MEM_B_DQ<59>
MEM_B_DQ<63>
MEM_B_SA<1>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DM<7>
MEM_B_CAS_L
MEM_B_DQS_P<4>
MEM_B_DQ<35>
MEM_B_CLK_N<0>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQS_N<6>
MEM_B_DQS_P<6>
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL
MEM_EVENT_L
MEM_B_DQ<58>
MEM_B_DQ<62>
MEM_B_DQS_N<7>
MEM_B_DQS_P<7>
MEM_B_DQ<60>
MEM_B_DQ<61>
MEM_B_DQ<50>
MEM_B_DQ<53>
MEM_B_DM<6>
MEM_B_DQ<54>
MEM_B_DQ<48>
MEM_B_DQ<46>
MEM_B_DQS_P<5>
MEM_B_DQ<47>
MEM_B_DQ<41>
MEM_B_DQ<34>
MEM_B_DQ<32>
MEM_B_DQ<37>
MEM_B_CS_L<1>
MEM_B_A<13>
MEM_B_WE_L
MEM_B_BA<0>
MEM_B_CLK_P<0>
MEM_B_DQS_N<5>
MEM_B_DQ<44>
MEM_B_DQ<45>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DM<4>
MEM_B_DQ<36>
MEM_B_DQ<33>
MEM_B_ODT<1>
MEM_B_CS_L<0>
MEM_B_ODT<0>
MEM_B_BA<1>
MEM_B_CLK_N<1>
MEM_B_A<0>
MEM_B_CLK_P<1>
MEM_B_A<2>
MEM_B_A<4>
MEM_B_A<6>
MEM_B_A<7>
MEM_B_A<11>
MEM_B_A<14>
MEM_B_A<15>
MEM_B_CKE<1>
MEM_B_DM<5>
MEM_B_DQS_N<4>
MEM_B_DQ<40>
MEM_B_DQ<49>
MEM_B_DQ<55>
MEM_B_DQ<42>
MEM_B_DQ<43>
MEM_B_A<12>
MEM_B_A<8>
MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<1>
MEM_B_DQ<9>
MEM_B_DM<2>
MEM_B_DQ<18>
MEM_B_DQ<22>
MEM_B_DQ<4>
MEM_B_DQ<23>
MEM_B_DQ<19>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQ<16>
MEM_B_DQ<20>
MEM_B_DQ<11>
MEM_B_DQ<14>
MEM_B_DM<1>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_RESET_L
MEM_B_DM<3>
MEM_B_DQ<25>
MEM_B_DQ<29>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQ<5>
MEM_B_DQ<21>
MEM_B_DQ<17>
MEM_B_DQ<10>
MEM_B_DQ<15>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQ<8>
MEM_B_DQ<30>
MEM_B_DQ<31>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQ<28>
MEM_B_DQ<24>
MEM_B_DM<0>
MEM_B_DQ<0>
MEM_B_DQ<1>
PP0V75_S3_MEM_VREFDQ_B
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_RAS_L
MEM_B_CKE<0>
PP0V75_S3_MEM_VREFCA_B
MEM_B_A<9>
MEM_B_BA<2>
8
8
8
8
26
26
Preliminary
IN
OUT
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
avoid glitch on MEM_RESET_L.
before 1.5V starts to rise to
DDR3 RESET Support
MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.
3.3V input must be stable before
1/16W
5%
MF-LF
1K
402
R3310
1
2
CERM
20%
0.1UF
MEMRESET_HW
402
10V
C3300
1
2
5%
10K
MEMRESET_HW
1/16W
MF-LF
402
R3300
1
2
16
MEMRESET_MCP
MF-LF
5%
1/16W
0
402
R3309
1
2
MMDT3904-X-G
MEMRESET_HW
SOT-363-LF
Q3305
5
3
4
20K
402
1/16W
5%
MEMRESET_HW
MF-LF
R3305
1
2
MEMRESET_HW
SOT-363-LF
MMDT3904-X-G
Q3305
2
6
1
27 28
5%
20K
MEMRESET_HW
1/16W
MF-LF
402
R3301
1
2
DDR3 Support
SYNC_DATE=04/01/2008
SYNC_MASTER=M98_MLB
33
123
31
051-7656
MCP_MEM_RESET_L
=PP1V5_S3_MEMRESET
MEM_RESET
MEM_RESET_RC_L
MEM_RESET_L
=PP3V3_S5_MEMRESET
8
8
Preliminary
OUT
S
G
D
IN
IN
BI
NC
IN
IN
IN
IN
OUT
OUT
BI
BI
OUT
OUT
Y
B
A
IN
NC
NC
SYM_VER-1
SYM_VER-1
SYM_VER-1
D
S G
D
S G
OUT
OUT
IN
D
GS
APPLE INC.
NONE
SCALE
REV.
A
D
C
B
A
D
C
B
8 7
6
5
4
3
2 1
8
7 6
5
4
3
2
1
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
NOTICE OF PROPRIETARY PROPERTY
DRAWING NUMBER
SHT
OF
SIZE
D
5V S3 WLAN FET
FDC606P
P-TYPE
26 mOhm @4.5V
0.8 A (EDP)LOADING
MOSFET
RDS(ON)
CAMERA
ALS
518S0610
CHANNEL
275 mA peak
BLUETOOTH
750 mA nominal max
1000 mA peak
206 mA nominal max
AIRPORT
7
17 31
FDC606P_G
Q3450
SOT-6
4
3
6521
9
8
7
6
5
4
32
31
30
3
29
28
27
26
25
24
23
22
21
20
2
19
18
17
16
15
14
13
12
11
10
1
J3401
CRITICAL
F-RT-SM
20347-325E-12
2 1
L3405
0402-LF
FERR-120-OHM-1.5A
33
44
44
2 1
L3404
FERR-120-OHM-1.5A
0402-LF
2
1
C3452
CERM
402
20%
10V
0.1uF
21
C3430
402X5R10%
0.1uF
16V
PLACEMENT_NOTE=Place close to J3401.
17 90
17 90
21
C3431
PLACEMENT_NOTE=Place close to J3401.
10% 16V X5R
0.1uF
402
17 90
17 90
20 91
20 91
2
1
C3421
CERM
10V
20%
402
PLACEMENT_NOTE=Place close to Q3450.
0.1uF
20 91
20 91
7
17 90
7
17 90
4
5
3
1
2
U3401
TC7SZ08AFEAPE
SOT665
25
24
5
13
U3402
74LVC1G17DRL
SOT-553
2
1
C3420
20%
X5R
10UF
805
10V
PLACEMENT_NOTE=Place close to Q3450.
1
2
5%
33K
1/16W
MF-LF
402
R3453
402
MF-LF
5%
1/16W
62K
R3454
1
2
2
1
C3453
10%
6.3V
1UF
CERM
402
4 3
21
L3401
90-OHM-100MA
DLP11S
PLACEMENT_NOTE=Place close to J3401.
4 3
21
L3402
DLP0NS
90-OHM
PLACEMENT_NOTE=Place close to J3401.
L3403
PLACEMENT_NOTE=Place close to J3401.
1
4 3
2
90-OHM
DLP0NS
1
2
6
Q3401
SSM6N15FEAPE
SOT563
4
5
3
Q3401
SOT563
SSM6N15FEAPE
17
17
21 33
FERR-120-OHM-1.5A
2 1
L3406
0402-LF
2
1
C3462
0.1uF
10V
20%
402
CERM
21
R3404
MF-LF
1/10W
0
5%
603
SSM3K15FV
1
2
3
SOD-VESM-HF
Q3402
1 2
402
1
R3455
1/16W
5%
MF-LF
21
C3450
402
10%
16V
X5R
0.1UF
C3451
10%
2
1
402
X5R
16V
0.033UF
100K
MF-LF
402
5%
1/16W
R3450
1 2
2
1
R3451
10K
5%
402
MF-LF
1/16W
2
1
C3422
0.1uF
10V
20%
CERM
402
PLACEMENT_NOTE=Place close to J3401.
Right Clutch Connector
34
123
31
051-7656
SYNC_MASTER=M98_MLB
SYNC_DATE=05/01/2008
WLAN_SMIT_RC_FET
PM_WLAN_EN_L
PP5V_WLAN_F
USB_CAMERA_CONN_N
I2C_ALS_SDA
PP5V_WLAN
VOLTAGE=5V
MIN_NECK_WIDTH=0.5 mm
MIN_LINE_WIDTH=1 mm
PCIE_MINI_D2R_N
WLAN_SMIT_RC
=PP3V3_S3_WLAN
CONN_USB2_BT_N
USB_BT_N
USB_BT_P
PP3V3_S3_BT_F
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
PCIE_CLK100M_MINI_CONN_P
AP_PWR_EN
PCIE_MINI_R2D_C_N
VOLTAGE=5V
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
PP5V_S3_BTCAMERA_F
USB_CAMERA_CONN_P
I2C_ALS_SCL
PCIE_MINI_R2D_N
CONN_USB2_BT_P
MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V
=PP3V3_S3_BT
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
=PP5V_S3_BTCAMERA
USB_CAMERA_P
WLAN_SMIT_BUF
MINI_RESET_L
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
MINI_CLKREQ_L
PCIE_MINI_R2D_C_P
USB_CAMERA_N
PCIE_MINI_PRSNT_L
MINI_RESET_CONN_L
PCIE_CLK100M_MINI_CONN_N
PCIE_MINI_R2D_P
PCIE_MINI_D2R_P
MINI_CLKREQ_Q_L
PCIE_WAKE_L
MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V
MIN_NECK_WIDTH=0.25 mm
=PP5V_S3_WLAN
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
PP5V_WLAN_F PP5V_WLAN_R
MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V
P5VWLAN_SS
96
96
96
96
90
96
96
90
30
7
7
8
7
7
7
7
7
7
8
8
7
7
7
7
8
30
Preliminary
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