Apple A1297 Schematic

8 7

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

6

5

4

3

SCHEM,CANNAREGIO,K20,DVT1

12/12/08

31

REV

2 1

ZONE

657084

DESCRIPTION OF CHANGE

ECN

ENGINEERING RELEASED

CK
APPD

DATE

12/12/08

ENG
APPD

?

DATE

Date

04/01/2008

04/01/2008

04/01/2008

04/01/2008

05/01/2008

04/01/2008

04/01/2008

N/A

D

C

B

91
92
93
94
95
96
97
98

(.csa)

103

MCP Constraints 2

104

Ethernet Constraints

105

FireWire Constraints

106

SMC Constraints

107

GPU (G96) Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

123

PROJECT SPECIFIC CONNS

Contents

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

N/A

11
12
13
14
15
16
17
18
19
20
21
22
23
24

26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

42
43
44
45

(.csa)

1

1
2
3
4
5
6
7
8
9

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

6

JTAG Scan Chain

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU FSB10

11

CPU Power & Ground

12

CPU Decoupling & VID

13

eXtended Debug Port(MiniXDP)

14

MCP CPU Interface

15

MCP Memory Interface

16

MCP Memory Misc

17

MCP PCIe Interfaces

18

MCP Ethernet & Graphics

19

MCP PCI & LPC

20

MCP SATA & USB

21

MCP HDA & MISC

22

MCP Power & Ground

25

MCP Standard Decoupling

26

MCP Graphics Support

28

SB Misc25

29

FSB/DDR3/FRAMEBUF Vref Margining

31

DDR3 SO-DIMM Connector A

32

DDR3 SO-DIMM Connector B

33

DDR3 Support

34

Right Clutch Connector

35

ExpressCard Connector

37

Ethernet PHY (RTL8211CL)

38

Ethernet & AirPort Support

39

Ethernet Connector

41

FireWire LLC/PHY (FW643)

42

FireWire Port Power

43

FireWire Ports

45

SATA Connectors

46

External USB Connectors

48

Front Flex Support

49

SMC41

50

SMC Support

51

LPC+SPI Debug Connector

52

K20 SMBUS CONNECTIONS

53

Current & Voltage Sensing

Contents

K20_MLB

M98_MLB

RXU_K20

NA

K20_MLB

BEN_K20

K20_MLB

RXU_K20

K20_MLB

M98_MLB

M98_MLB

M98_MLB

M98_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

M98_MLB

M98_MLB

M98_MLB

BEN_K20

BEN_K20

BEN_K20

M98_MLB

M98_MLB

BEN_K20

SUMA_K20

SUMA_K20

SUMA_K20

M98_MLB

YWU_K20

M98_MLB

M98_MLB

M98_MLB

CHANG_K20

T18_MLB

M98_MLB

CHANG_K20

BEN_K20

YWU_K20

D

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

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TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

C

B

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

Date

SyncPage

04/01/2008

04/01/2008

07/24/2008

NA

04/01/2008

07/11/2008

09/24/2008

05/07/2008

09/24/2008

04/01/2008

04/01/2008

04/01/2008

04/01/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

06/06/2008

04/01/2008

04/01/2008

05/01/2008

10/15/2008

06/10/2008

07/14/2008

04/01/2008

05/01/2008

10/15/2008

07/22/2008

07/15/2008

07/15/2008

04/01/2008

05/28/2008

07/14/2008

05/01/2008

07/14/2008

07/18/2008

06/06/2008

05/01/2008

05/28/2008

07/22/2008

08/20/2008

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90

(.csa)

54

Current Sensing

55

Thermal Sensors

56

Fan Connectors

57

WELLSPRING 1

58

WELLSPRING 2

59

Sudden Motion Sensor (SMS)

61

SPI ROM

62

AUDIO:CODEC

63

AUDIO: LINE IN

65

AUDIO: HEADPHONE AMP

66

AUDIO:SPEAKER AMP

67

AUDIO: JACKS

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

IMVP6 CPU VCore Regulator

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

75

5V_S0 / MCP CORE REGULATOR

76

CPU VTT Power Supply

77

Misc Power Supplies

78

Power Control

79

Power FETs

80

NV G96 PCI-E

81

NV G96 CORE/FB POWER

82

NV G96 FRAME BUFFER I/F

84

GDDR3 Frame Buffer A (Bottom)

85

GDDR3 Frame Buffer B (Bottom)

86

NV G96 GPIO/MIO/MISC

87

G96 GPIOs & Straps

88

NV G96 Video Interfaces

89

GPU (G96) CORE SUPPLY

90

LVDS Display Connector

91

GDDR3 Frame Buffer A (Top)

92

GDDR3 Frame Buffer B (Top)

93

Muxed Graphics Support

94

DisplayPort Connector

95

1.1V / 1V8 FB Power Supply

96

Graphics MUX (GMUX)

97

LCD BACKLIGHT DRIVER

98

LCD Backlight Support

99

Misc Power Supplies

100

CPU/FSB Constraints

101

Memory Constraints

102

MCP Constraints 1

Contents

YWU_K20

YWU_K20

M98_MLB

YMA_K20

K20_MLB

YWU_K20

M98_MLB

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

AUDIO_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

RXU_K20

YMA_K20

YMA_K20

M98_MLB

M98_MLB

K20_MLB

M98_MLB

M98_MLB

K20_MLB

M98_MLB

K20_MLB

RXU_K20

M98_MLB

M99_MLB

M88_MLB

M98_MLB

K20_MLB

RXU_K20

T18_MXMGMUX

KIRAN_K20

YLEE_K20

RXU_K20

M98_MLB

M98_MLB

M98_MLB

Date

SyncPage

08/12/2008

05/28/2008

04/01/2008

05/19/2008

09/24/2008

06/17/2008

05/01/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

09/29/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

05/21/2008

09/09/2008

05/19/2008

04/01/2008

04/01/2008

09/24/2008

04/01/2008

04/01/2008

09/24/2008

05/12/2008

09/24/2008

05/21/2008

07/14/2008

04/04/2008

11/01/2007

05/01/2008

09/24/2008

05/21/2008

02/13/2008

12/03/2008

07/18/2008

05/07/2008

04/01/2008

04/01/2008

04/01/2008

Page Sync

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEM

A

Schematic / PCB #’s

PART NUMBER

820-2390 CRITICAL

DRAWING

TITLE=MLB
ABBREV=DRAWING

LAST_MODIFIED=Fri Dec 12 16:50:42 2008

QTY

1 SCH

8

DESCRIPTION

SCHEM,CANNAREGIO,K20

PCBF,CANNAREGIO,K20

REFERENCE DES

CRITICAL

BOM OPTION

CRITICAL051-7656

PCB1

7 6

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

5

4

3

DRAFTER

ENG APPD

QA APPD

RELEASE

METRIC

MATERIAL/FINISH

NOTED AS

APPLICABLE

DESIGN CK

MFG APPD

DESIGNER

SCALE

NONE

SIZE

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TITLE

SCHEM,CANNAREGIO,K20

DRAWING NUMBER

D

APPLE INC.

051-7656

SHT

1

REV.

A

31

OF

1

123

8 7

6

U1000

INTEL CPU

2.X OR 3.X GHZ

PENRYN

PG 9

5

U1300

XDP CONN

PG 12

4

3

2 1

FSB

D

PG 13

GPIOs

FSB INTERFACE

64-Bit

800/1067/1333 MHz

MAIN

MEMORY

PG 14

2 UDIMMs

DDR2-800MHZ
DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

J6950

DC/BATT

PG 60

U4900

POWER SUPPLY

D

TEMP SENSOR

USB

PG 39

PG 41

PG 45

PG 48,49

J5100

Port80,serial

LPC Conn

PG 43

C

B

CLK

SYNTH

J4510

SATA
Conn

PG 38

HD

J4520

SATA
Conn

PG 38

C

ODD

1.05V/3GHZ.

1.05V/3GHZ.

SATA

PG 19

NVIDIA

MCP79

U1400

J9000

LVDS
CONN

J9400

DISPLAY PORT

CONN

PG 71

PG 71

LVDS OUT

RGB OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

PG 17

UP TO 20 LANES3

PG 16

PCI-E

B

RGMII

PG 17

PCI

(UP TO FOUR PORTS)

PG 18

Misc

PG 24

SPI

PG 20

LPC

PG 18

PWR

CTRL

USB

PG 19

(UP TO 12 DEVICES)

SMB

PG 20

HDA

PG 20

4

3 8 9
2

10 5 6 7

J4720

Bluetooth

U6100

SPI

Boot ROM

PG 52

J4900

B,0

BSB

FanADC

SMC

PG 41

J4700

TRACKPAD/

PG 40

KEYBOARD

PG 40

J4710

IR

PG 40

J4710

CAMERA

PG 40

POWER SENSE

J5650,5600,5610,5611,5660,5720,5730,5750

FAN CONN AND CONTROL

Ser

Prt

J3900,4635,4655

EXTERNAL

Connectors

SMB

CONN

DIMM’s

PG 44

U6200

U3700

A

J3400 U3900

Mini PCI-E

AirPort

PG 28

8

7 6

GB

E-NET

88E1116

PG 31

E-NET

Conn

PG 33

5

U6301 U6500U6400

Line In

Amp

PG 54

HEADPHONE

Amp Amp

J6800,6801,6802,6803

Audio
Codec

PG 53

U6600,6605,6610,6620

Line Out

PG 56PG 55

Audio
Conns

PG 59

4

Speaker

Amps

PG 57

3

SYNC_MASTER=M98_MLB

APPLE INC.

2

System Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-7656

2

1

SYNC_DATE=04/01/2008

REV.

31

OF

123

A

8 7

6

5

4

3

2 1

K20 POWER SYSTEM ARCHITECTURE

PPDCIN_G3H

J6900

D

AC

ADAPTER

IN

DCIN(16.5V)

F6905
6A FUSE

R7020

SMC_DCIN_ISENSE

A

U7000

VIN

ISL6258A

PBUS SUPPLY/

BATTERY CHARGER

(PAGE 60)

J6950

PPVBATT_G3H_CONN

2S4P

(6 TO 8.4V)

C

GMUX

U9600

XP28

(PAGE 84)

PB16B

PB17A

PB17B

PB18A

PL32A

EG_RAIL1_EN

EG_RAIL2_EN

EG_RAIL3_EN

EG_RAIL4_EN

PM_ALL_GPU_PGOOD

SMC

RC

DELAY

Q7056

BATT_POS_GATE

P1V1GPU_EN

P3V3GPU_EN

GPUVCORE_EN

P1V8_S0GPU_EN

P3V3S5_EN

Q7055

CHGR_BGATE

U4900

RC

(PAGE 42)

P60

SMC_PM_G2_EN

DELAY

PM_G2_P1V05S5_EN

MCP79

SLP_RMGT#(J17)

B

PCI_RESET0#(R10)

U1400

SLP_S5#(H17)

SLP_S3#(G17)

PM_SLP_RMGT_L

R2870

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

MEM_VTT_EN

DDRREG_EN

P5VS3_EN

R6905

VOUT

PPVBAT_G3H_CHGR_R

P1V1_GPU_EN

P1V8_S0GPU_EN

BKLT_PLT_RST_L

&& ENA

LCD_BKLT_EN

PPVBAT_G3H_CHGR_REG

R7050
U5303

SMC_BATT_ISENSE

MCPCORES0_EN

PM_SLP_S3_L_R

Q4260

VIN

EN1

1.103V(L/H)

EN2

1.8V(R/H)

ISL6236

U9500

(PAGE 83)

(PAGE 85~86)

A

VOUT2

P5VS3_EN

P3V3S5_EN

VIN

APP001

U9701

VIN

(PAGE 14~22)

FW_PORTPWR_EN&&(SMC_ADAPTER_EN||PM_SLP_S3_L)

R7878

PM_SLP_S3_L_R

A

DELAY

DELAY

DELAY

DELAY

RC

RC

RC

RC

P1V8S0_EN

MCPDDR_EN

CPUVTTS0_EN

MCPCORES0_EN

DELAY

DELAY

DELAY

P1V05S0_EN

RC

P1V2_S0_EN

RC

P2V5S0_EN

RC

PM_G2_P1V05S5_EN

EN

VIN

1.05V AUX

ISL6269

U7750

(PAGE 66)

VOUT1

POK1

POK2

(PAGE 66)

D6905

D6905

F7040

F7041

8A FUSE

MCP_CORE

EN2

EN1

VIN

(PAGE 64)

PP1V1_S0GPU

R5413

A

P1V1GPU_PGOOD

PM_ALL_GPU_PGOOD

VOUT

LTC1872

U7790

VOUT

PGOOD

VOUT2

5V

VOUT1

ISL6236

POK1

U7500

POK2

PP1V8_S0GPU_ISNS

SMC_GPU_1V8_ISENSE

VIN

EN1

5V

(L/H)

3.3V

EN2

(R/H)

TPS51220

U7201

(PAGE 62)

PGOOD1,2

P5V3V3_PGOOD

PPVOUT_S0_LCDBKLT

PP10V_FW

VOUT

PP1V2R1V05_S5

P1V05_S5_PGOOD

PPVIN_G3H_P3V42G3H

PPBUS_G3H

R7505

A

SMC_MCP_CORE_ISENSE

PP5V_S0

P5V_RTS0_PGOOD

MCPCORES0_PGOOD

DDRREG_EN

MEM_VTT_EN

PP5V_S3

VOUT1

PP3V3_S5

VOUT2

PPBUS_G3H_VSENSE

GPUVCORE_EN

SMC_CPU_HI_ISENSE

V

PPVCORE_S0_MCP

Q7953

P1V05S0_EN

V

SMC_MCP_VSENSE

Q7910

Q7930

Q7970

PP1V05_S0

Q3840

PM_SLP_RMGT_L

Q5315

GPU VCORE

ISL6263C

VR_ON PGOOD

(PAGE 77)

R5388

VIN

1.5V

S5

S3

0.75V

TPS51116

U7300

(PAGE 63)

PP3V3_S5

PM_SLP_S4_L

PM_SLP_S3_L

P3V3GPU_EN

Q3810

PM_SLP_RMGT_L

VIN

U8900

A

IMVP_VR_ON

VLDOIN

VOUT1

VOUT2

PP3V3_S3

PP3V3_S0

PP3V3_S0GPU

P3V3_ENET_PHY

PP1V2R1V05_ENET

ENABLE

3.425V G3HOT

LT3470A

U6990

(PAGE 59)

VOUT

SMC_GPU_ISENSE

GPUVCORE_PGOOD

VR_ON

PP0V9R0V75_S0_DDRVTT

P1V8_S0GPU_EN

A

U5410

CPU VCORE

VIN

ISL9504B

U7100

(PAGE 61)

PP1V8R1V5_S3

P1V2_S0_EN

P2V5S0_EN

P1V8S0_EN

EN

PP3V42_G3H

R0940

P1V0FW_EN

(PAGE 66)

VOUT

PGOOD

VI

TPS62202

U7760

PP3V3_S5

P1V05_S5_PGOOD

SMC_GPU_VSENSE

V

PPVCORE_GPU

U7100

SMC_CPU_ISENSE

VR_PWRGOOD_DELAY

RUN1

LTC3547

U9900

RUN2

(PAGE 87)

RUN1

LTC3547

U7700

RUN2

(PAGE 66)

VOUT

PP3V42_G3H

A

Q7901

MCPDDR_EN

VIN

VOUT1

VOUT2

VIN

VOUT1

VOUT2

PP1V8_GPUIFPX

PP1V8R1V5_S0

PP1V05_S0

SENSE

(PAGE 67)

S5 PWRGD

NCP303LSN

(PAGE 42)

SMC_CPU_VSENSE

V

R5445

SMC_MCP_DDR_ISENSE

A

PP1V2_S0

PP2V5_S0

PM_ALL_GPU_PGOOD

PP1V0_FW

PP1V8_S0

VDD

U7840

TPS3808G

SMC PWRGD

U5000

CPUVTTS0_EN

PPVCORE_S0_CPU

PPMCPDDR_ISNS

PP1V8R1V5_S0

PP3V3_S5

S0PGOOD_PWROK

PP3V3_S0

ADJ1

ADJ2

RSMRST_PWRGD

RESET*

MR*

SMC_RESET_L

EN_PSV

R7894

P5V3V3_PGOOD

P5V_RTS0_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

VCC

U7870

LTC2909

(PAGE 67)

TRST = 200mS

VIN

1.05V

SC417
U7600

(PAGE 65)

U7880

RST*

MIC5232-2.8YD5

U2801

VIN

(PAGE 25)

VOUT

PGOOD

ALL_SYS_PWRGD

RSMRST_PWRGD

VOUT

CPUVTTS0_PGOOD

MCP_PS_PWRGD

U2850

SMC_ONOFF_L

PM_SLP_S4_L

PM_SLP_S4_L

PM_SLP_S3_L

PP3V3_G3_RTC

R7650

PPCPUVTT_S0

A

SMC_CPU_FSB_ISENSE

PS_PWRGD

(PAGE 14~22)

CPU

U1000

(PAGE 10,11)

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)

SLP_S4_L(P94)

SLP_S3_L(P93)

SYNC_MASTER=RXU_K20

APPLE INC.

SMC_TPAD_RST_L

SMC_ONOFF_L

U5001

MCP79

PWRBTN#

RSTBTN#

PWRGD_SB

CPU_RESET#

CPU_PWRGD

PM_SYSRST_DEBOUNCE_L

FSB_CPURST_L

CPU_PWRGD

U1400

PWRGOOD

RESET*

SMC

U4900

(PAGE 42)

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

P17(BTN_OUT)

SYSRST(PA2)

RES*

PM_RSMRST_L

IMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

Power Block Diagram

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-7656

3

SYNC_DATE=07/24/2008

REV.

31

OF

123

D

C

B

A

8

7 6

5

4

3

2

1

8 7

Proto:

See earlier schematics for info about proto changes

Pre-EVT:

See earlier schematics for info about Pre-EVT changes

EVT:

10/29/08
csa. 5 Added BKLT_PLL_NOT BOM option K20_COMMON2 BOM group. This stuffs R9713.
csa. 68 Changed net name on input to U6860 from PP3V3_S0_AUDIO to =PP3V3_S0_AUDIO.

D

See <rdar://problem/6327731> K20 PreEVT: iPhone headset detection test fail

csa. 97 Changed R9707 to 2.87K per <rdar://problem/6327135> Change R9707 to 2.87k, 1% resistor

10/29/08
csa. 9 Changed SH0924 to 870-1698 tall emi pogo pin.
11/5/08

csa. 4 Updated Revision History.
csa. 8 Tied =PP3V3_FW_FWPHY and =PP3V3_FW_P1V0FW aliases to PP3V3_S0.
csa. 9 Removed R0942 and R0943 which were for selecting from S0 or S3 for =PP3V3_FW_FWPHY.
Removed R0940 and R0941 which were for selecting from S0 or S3 for =PP3V3_FW_P1V0FW.
Tied =PP3V3_S3_GMUX alias to PP3V3_S3.
csa. 75 Changed U7500 from 353S2312 Intersil ISL6236 to 353S2203 TI SN0802043.

Changed TONSEL from GND to PP5V_S0_MCPREG_VCC. This changes output frequencies to 200/300KHz for 5V/MCPCore.

Added C7562 330uF cap on =PPMCPCORE_S0_REG.
Changed snubber resistors R7598 and R7599 to 1/6W 0402, APN 114S0548.
csa. 87 Changed pulldown values to 10K on GPIO7_FBVDDQ_ALTVO, R8794.
Changed pulldowns R8792 and R8793 from 1K to 4.7K for power consumption.
csa. 90 Removed R9094. Replaced by R9678 on csa. 96 to tie to GMUX_S3_PD_GND.

csa. 96 Added Q9607 dual FET for disabling GMUX power sequence enable configuration pulldowns during S0.

Moved R9094 to R9678 and tied to GMUX_S3_PD_GND.
csa. 97 Changed R9707 to 2.67K 1%. This gives 22.5mA on LED current.
11/10/08
csa. 68 Changed R6885 from 0 ohms to 2.2K.
Changed C6885 from 470 pF to 0.0082 uF.
csa. 87 Changed R8792 and R8793 from 4.7K to 10K pulldowns on EG_LCD_PWR_EN and EG_BKLT_EN.
csa. 96 Changed R9678 pulldown on LCD_PWR_EN from 10K to 4.7K.
Removed BOM options on FET circuit for GMUX_S3_PD_GND.
Added R9684 NO STUFF 0 ohms to tie ALL_SYS_PWRGD to Q9607.

C

11/11/08
csa. 8 removed =PP3V3_S3_P1V0FW and =PP3V3_S3_BKL_VDDIO
csa. 41 changed R4160 from 274K to 200K <rdar://6292976>
csa. 68 changed R6885 from 0 ohm to 2.2K for Mic LPF
csa. 75 NO STUFF R7598, C7598, R7599, C7599 (snubbers)
csa. 87 changed R8795 from 1K to 10K pull down
csa. 96 NO STUFF R9677, C9695, STUFF R9684
11/12/08
csa. 5 removed MCP79 B01 from Module Parts table and added B03
csa. 39 added Bom table for J3900 (514-0636)
csa. 46 added Bom table for J4600, J4610 (514-0638)
csa. 94 added Bom table for J9400 (514-0637)
csa. 123 added Bom table for JC320 (514-0638)
11/13/08
csa. 1 change title to DVT
csa. 32 Added alternate table for J3200 (516S0709, Molex DIMM connector)
11/19/08
csa. 5 changed MCP79 B03 to 338S0710; change to binned G96 338S0714;

added PROD_DIGSMS and TPDT_DEBOUNCE to BOM groups
csa. 68 added bom option TPDT_BYPASS to R6865; TPDT_DEBOUNCE to U6860,C6861,R6860,R6862
csa. 97 changed Q9701 to 376S0757 <radr://6383480>
11/25/08
csa. 5 changed BOM option MCP_B02 to MCP_B03; added BOM option GMUX_1V8
added Mag Layer alternate 155S0457 to Murata 155S0329
csa. 93 added BOM table for 16 LVDS termination resistors to select GMUX_2V5 or GMUX_1V8
added BOM option GMUX_2V5 to 8 parallel resistors so they’ll be NO STUFFed for GMUX_1V8

B

csa. 97 reverted Q9701 to 376S0678 due to parts availability
csa. 99 added BOM table for R9900 to select either 2.5V output or 1.8V output

DVT:

12/02/08
Start of PVT.
csa. 5 removed JTAG_ALLDEV bom option to remove U0600, R0601, C0601, C0602

added 516-0213 (Molex TH SODIMM CONN) as alternate to 516-0201 (Foxconn)

added GMUX_JTAG_CONN bom option to the bom table
csa. 6 added GMUX_JTAG_CONN bom option to J0600
csa. 99 moved OMIT from R9900 to R9901 to select either 150K (GMUX_2V5) or 237K (GMUX_1V8)
12/03/08
csa. 32 removed redundant alternate table for J3200
csa. 97 Per radar 6383480, Change the FET Q9701 from APN: 376S0678 to 376S0757
diode D9701 from APN: 371S0551 to 371S0572
12/09/08
csa. 1 changed title to DVT(1)
csa. 26 NO STUFF C2690, R2690
csa. 32 Refreshed symbol for J3200 for update to BGA SODIMM conn.
csa. 54 changed R5498 to 4.02K for 1.4x gain and R5493 to 2.87K <rdar://6423810>
csa. 89 changed L8920 to 152S0955 (25A Isat); R8900 to 7.15K for 24.6A OCP <rdar://6423810>

12/12/08
csa. 1 changed title to DVT1
csa. 4 removed pre-EVT check in notes from Rev. History
csa. 99 changed text note to reflect 2.5V to 1.8V GMUX rail change

A

6

5

4

3

2 1

D

C

B

31

OF

SYNC_DATE=NA

REV.

31

123

A

SYNC_MASTER=NA

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

SHT

051-7656

4

8

7 6

5

4

3

2

1

BOM Variants

BOM NUMBER

630-9728

630-9727

630-9730

630-9729

D

K20 BOM GROUPS

BOM GROUP

K20_COMMON

K20_COMMON1

K20_COMMON2

K20_DEBUG

K20_PROGPARTS

BOM GROUP

FB_1024_SAMSUNG

FB_1024_QIMONDA

FB_512_SAMSUNG

FB_512_QIMONDA

8 7

BOM NAME

PCBA,BEST,2.66,512SAM_VRAM,K20

PCBA,BEST,2.66,512QIM_VRAM,K20

PCBA,BEST,2.93,512SAM_VRAM,K20

PCBA,BEST,2.93,512QIM_VRAM,K20

ALTERNATE,COMMON,K20_COMMON1,K20_COMMON2,K20_DEBUG,K20_PROGPARTS

ONEWIRE_PU,ISL6258,MEMRESET_HW,MEMRESET_MCP,MCP_B03,MCP_PROD,MCPSEQ_SMC,BMON_ENG,MCP_CS1_NO,FW_LVG_NEW,PROD_DIGSMS,TPDT_DEBOUNCE

BOOT_MODE_USER,GPUVID_1P00V,MUXGFX,DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_GMUX,DP_CA_DET_EG_PLD,BKLT_PLL_NOT,GMUX_1V8

SMC_DEBUG_YES,XDP,XDP_CONN,LPCPLUS,VREFMRGN,TPAD_DEBUG,GMUX_JTAG_CONN

K20_COMMON,EEE_4CM,CPU_2_66GHZ,FB_512_SAMSUNG

K20_COMMON,EEE_4CH,CPU_2_66GHZ,FB_512_QIMONDA

K20_COMMON,EEE_4CQ,CPU_2_93GHZ,FB_512_SAMSUNG

K20_COMMON,EEE_4CP,CPU_2_93GHZ,FB_512_QIMONDA

BOM OPTIONS

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

BOM OPTIONS

VRAM8,VRAM_1024_SAMSUNG

VRAM8,VRAM_1024_QIMONDA

VRAM4,VRAM_512_SAMSUNG

VRAM4,VRAM_512_QIMONDA

6

BOM OPTIONS

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

5

Alternate Parts

PART NUMBER

353S1681

152S0684

104S0023 104S0018

104S0024

152S0876

157S0058

514-0612

514-0613

152S0684

152S0896

152S0915

516S0709

155S0457 155S0329

516-0213 516-0201

ALTERNATE FOR
PART NUMBER

152S0276152S0476

353S1294

138S0602138S0603

152S0368

104S0017

341S2366341S2367

152S0782

157S0055

514-0607

514-0608

152S0421

152S0518

152S0796

516S0706

BOM OPTION

4

REF DES

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

ALL

COMMENTS:

Inductor alternate

TI alt to National

Murata alt to Samsung

Maglayers alt to Dale/Vishay

Cyntec alt to sense resistor

Panasonic alt to FW resistor

Macronix alt to SST

Maglayer alt to Delta

Delta alt to TDK Magnetics

FOXLINK ALT TO FOXCONN XCVR

FOXLINK ALT TO FOXCONN RCVR

MAG LAYERS ALT TO VISHAY

MAG LAYERS ALT TO CYNTEC

MAG LAYERS ALT TO CYNTEC

MOLEX ALT TO FOXCONN

MAG LAYERS ALT TO MURATA

MOLEX ALT TO FOXCONN

3

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

2 1

D

Bar Code Labels / EEE #’s

C

PART NUMBER

826-4393

826-4393

826-4393

Module Parts

B

A

PART NUMBER

338S0635

QTY

1

1

1

1

QTY

337S3645

337S3644

338S0714

338S0694

338S0654

338S0710 CRITICAL

335S0610

341S2356 CRITICAL

341S2384

341S2383

337S3643

337S3640

337S3641

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

1

4

333S0472

333S0481

333S0472

4

8

8

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

IC,PDC,QXXX,QS,2.66,25W,1066,E0,6M,BGA

IC,PDC,QXXX,QS,2.86,35W,1066,E0,6M,BGA

IC,ASSP,GPU,NV G96-GS,LOWLKG,BGA969,LF

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P LQFP

IC,FW643-E,1394B PHY/OHCI LINK/PCI-E,12

IC,MCP79XT-B3,35X35MM,BGA1437

IC,SMC,HS8/2117,9MMX9MM,TLP

IC,SMC,DEVELOPMENT,K20

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

IC,EFI ROM,DEVELOPMENT,K20

IR,ENCORE II, CY7C63833-LFXC

IC,GMCP,MCP79-A01Q,35x35MM,BGA1437

IC,PSOC +W/USB,56PIN,MLF,M98

IC,PDC,QXXX,QS,2.93,35W,1066,E0,6M,BGA

IC,PDC,SL3BX,PRQ,2.53,35W,1066,C0,6M,BGA

IC,PDC,SLB43.PRQ,2.80,35W,1066,E0,6M,BGA

IC,GMCP,MCP79-B02,35x35MM,BGA1437

IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

IC,SGRAM,GDDR3,32MX32,800MHZ,136 FBGA

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

DESCRIPTION

REFERENCE DES

[EEE:4CH]

[EEE:4CM]

[EEE:4CP]

[EEE:4CQ]

REFERENCE DES

U1000

U1000

U8000

U3700

U4100

U1400

U4900

U4900

U6100

U6100

U4800

U1400

U5701

U1000

U1000

U1000

U1400

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250

U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL826-4393

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL338S0563

CRITICAL341S2355

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL333S0481

CRITICAL

CRITICAL

CRITICAL

BOM OPTION

EEE_4CH

EEE_4CM

EEE_4CP

EEE_4CQ

BOM OPTION

CPU_2_66GHZ

CPU_2_86GHZ

MCP_B03

SMC_BLANK

SMC_PROG

BOOTROM_BLANK

BOOTROM_PROG

MCP_A01QCRITICAL338S0603

TPAD_PROG

CPU_2_93GHZ

CPU_2_53GHZ

CPU_2_80GHZ

MCP_B02

VRAM_512_SAMSUNG

VRAM_512_QIMONDA

VRAM_1024_SAMSUNG

VRAM_1024_QIMONDA

BOM Configuration

SYNC_MASTER=K20_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7656

SHT

SYNC_DATE=04/01/2008

OF

5

123

C

B

A

REV.

31

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

=PP3V3_S0_XDP

13

8

6

D

61 13 12

C

11

10

8

=PP1V05_S0_CPU

JTAG_ALLDEV

R0601

10K

1/16W
MF-LF

NOSTUFF

R0602

1/16W
MF-LF

To XDP connector
and/or level translator

XDP_TDO

10

JTAG_MCP_TDO

21

XDP

PLACEMENT_NOTE=Place near pin U1000.AB3

R0603

0

1 2

5%
1/16W
MF-LF

402

XDP

R0604

0

1 2

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=Place near pin U1400.F19

XDP_TDO_CONN

JTAG_MCP_TDO_CONN

ry

a

13

OUT

XDP connector

13

OUT

XDP connector

13

13

13

13

21 10

21

21

21

U1000

CPU

88

U1400

MCP

MAKE_BASE=TRUE

From XDP connector

JTAG_ALLDEV

1

C0601

0.1UF

20%
10V

2

CERM
402

1

5%

402

2

13

88

1

0

5%

402

2

88

13

88

13

XDP_TCK

6

XDP_TMS

10

6

XDP_TRST_L

10

6

JTAG_LVL_TRANS_EN_L

1

2

JTAG_ALLDEV

C0602

0.1UF

20%
10V
CERM
402

JTAG_ALLDEV

2

3
4

5

12

VCCA

NLSV4T244

A1
A2
A3
A4

OE*

1

VCCB

U0600

UQFN

GND

6

IN
IN
IN
IN

XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L

JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L

6

10 13 88

10 13 88

6

10 13 88

6

10 13 88

11

or via level translator

10

B1

9

B2

8

B3

7

B4

1

R0606

10K

5%
1/16W
MF-LF
402

2

From XDP connector

MAKE_BASE=TRUE

MAKE_BASE=TRUE

D

C

NOSTUFF

PLACEMENT_NOTE=Place close to U8000

R0605

10K

1 2

5%
1/16W
MF-LF

402

GPU_JTAG_TMS

B

74

74

74

6

74

84

9

84

9

84

U8000

GPU

U9600

GMUX

74

84

9

GPU_JTAG_TDO

JTAG_GMUX_TDO

i

n

6

VCC

U0601

74LVC1G07

2

1

GMUX CPLD Programming Port

CRITICAL

J0600

1909782

M-RT-SM

GMUX_JTAG_CONN

B

7

=PP3V3_S0_XDP

1

2

TDO
TDI

3

TMS

4

5

TCK

6

8

8

6

NC NC

13

YA

4

5

NCNC

SOT886

GND

3

PLACEMENT_NOTE=Place close to U0600

GPU_JTAG_TCK

GPU_JTAG_TDI
GPU_JTAG_TMS
GPU_JTAG_TRST_L

JTAG_GMUX_TCK

i

JTAG_GMUX_TDI
JTAG_GMUX_TMS

m

l

=PP3V3_GPU_VDD33

75

8 6

74 74

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

re

P

A

8

7 6

5

4

3

SYNC_MASTER=BEN_K20

APPLE INC.

2

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

JTAG Scan Chain

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

051-7656

6

1

SYNC_DATE=07/11/2008

REV.

OF

123

A

31

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NO_TEST

LVDS NO_TESTs

NC NO_TESTs

J5800 (IPD FLEX CONN)

FUNC_TEST

FUNC_TEST

6 TPs

NO_TEST

NO_TEST

J5650 (LEFT FAN CONN)

J6995 (BAT LED CONN)

J6950 (MAIN BATT CONN)

J6900 (DC POWER CONN)

FUNC_TEST

POWER RAILS

USB PORTS

J5713 (KEY BOARD CONN)

FUNC_TEST

3 TPs

NC NO_TESTs

NO_TEST

CPU FSB NO_TESTs

ICT Test Points

NO_TEST

J3500 (EXPRESS CARD CONN)

4 TPs

5 TPs

3 TPs

5 TPs

Functional Test Points

per Fan

J5502 (SENSOR CONN)

J5660 (RIGHT FAN CONN)

J6780 (MIC CONN)

J6782 (RIGHT & SUB SPEAKER)

J9000 (LVDS CONN)

J4500 (SATA ODD CONN)

J4501 (SATA HDD CONN)

J5815 (KBD BACKLIGHT CONN)

J4800 (FRONT CABLE CONN)

FB NO_TESTs

2 TP needed

J3401 (AIRPORT/BT/CAMERA CONN)

per Fan

J6781 (LEFT SPEAKER)

NC NO_TESTs

NO_TEST

I1000

I1001

I1002

I1003

I1004

I1005

I1006

I1007

I1008

I1009

I1010
I1011

I1012

I1013

I1014

I1015
I1016

I1017

I1018
I1019

I1020

I1021

I1022

I1024

I1025

I1026

I1027

I1028

I1029

I1031

I1032

I1033

I1034

I1035

I1038
I1039

I1040

I1042

I1043
I1044

I1046
I1047

I1048

I1050

I1051

I1052

I1053

I1054

I1055

I1056

I1057

I1058

I1059

I1060

I1061

I1062

I1063

I1064

I1065

I1066

I1067
I1068

I1069

I1070

I1071

I1072

I1073

I1074

I1075

I1076
I1077

I1078

I1079

I1080

I1081

I1082

I1083

I1084

I1085

I1086
I1087

I1088

I1089

I1090
I1091

I1092
I1093

I1094

I1095

I1096

I1097

I1098

I1099

I1100

I1101

I1102

I1103

I1104

I1105

I1106

I1107

I1108

I1109

I1110
I1111

I1112

I1113
I1114

I1115

I1116

I1117

I1118
I1119

I1120

I1121

I1122

I1123

I1124
I1125

I1126

I1127

I1128

I1129
I1130

I1131
I1132

I1134

I1135

I1136

I1137

I1140

I1141

I1142

I1143

I1145

I1146

I1148

I1149

I1150

I1151
I1152

I1154

I1155

I1156

I1157

I1159

I1160

I1161

I1273

I1274

I1275

I1276
I1277

I1280

I1281

I1282
I1283

I1284

I1285

I1286

I1288

I1290

I1291
I1292

I1293

I1294

I1296

I1297

I557

I558

I559

I600

I602

I603

I604

I605

I606

I607

I608

I610

I611

I612

I613

I614

I615

I616

I617

I618

I620

I621

I622

I623

I624

I625

I626

I627

I636

I637

I638

I639

I640

I709

I714

I720
I722

I723

I724

I725

I726
I727

I728

I729

I730

I731

I732

I733

I734

I735
I736

I737

I738

I739

I740
I741

I742

I743
I744

I751

I752

I756

I761

I762
I763

I764

I765

I766

I767

I768

I769

I770

I771

I772

I774

I981

I982

I985

I986

I987

I988

I989
I990

I991

I992

I993

I994

I995
I996

I997

I998

7

123

31

051-7656

Functional / ICT Test

SYNC_MASTER=K20_MLB

SYNC_DATE=09/24/2008

GND

TRUE

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

GND

TRUE

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

NC_SMC_FAN_3_TACH

TRUE

NC_SMC_FAN_2_TACH

TRUE

FSB_ADS_L

TRUE

TP_PCI_CLK1

TRUE

FSB_REQ_L<4..0>

NC_GPU_GSTATE<1>

TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_D<9..0>

TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_DE

MAKE_BASE=TRUE

TRUE

NC_GPU_PGOOD_OUT_L

TRUE

MAKE_BASE=TRUE

TP_GPU_PGOOD_OUT_L
TP_GPU_VCORE_VID3
TP_LPC_DRQ0_L

NC_PCI_INTZ_L

MAKE_BASE=TRUE

TRUE

NC_PCI_INTY_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCI_INTX_L

NC_PCI_FRAME_L

MAKE_BASE=TRUE

TRUE

NC_PCI_DEVSEL_L

MAKE_BASE=TRUE

TRUE

NC_PCI_AD<31..8>

MAKE_BASE=TRUE

TRUE

NC_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK0

MAKE_BASE=TRUE

TRUE

NC_PCI_CLK1

TRUE
MAKE_BASE=TRUE

TP_PCI_DEVSEL_L
TP_PCI_FRAME_L

WS_CONTROL_KBD

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD_ONOFF_L

TRUE

TRUE

WS_KBD23

TRUE

WS_KBD22

PCIE_MINI_R2D_P

TRUE

TRUE

PCIE_MINI_D2R_N

SPKRAMP_L1_OUT_P

TRUE

TRUE

SPKRAMP_L2_OUT_N

USB_LT3_P

TRUE

PP5V_S3_IR_R

TRUE

TRUE

IR_RX_OUT

BKLT_EN

TRUE

BKL_SW

TRUE

TRUE

BKL_GD

TRUE

FB_A_DQ<63..0>

TRUE

FB_B_DQ<63..0>

TRUE

FB_B_BA<1>

TRUE

FB_B_CAS_L
FB_B_CS0_L

TRUE

FB_B_MA<11>

TRUE

TP_CPU_PECI_MCP
TP_CPU_TEST3
TP_ENET_INTR_L

TP_FW643_AVREG

TP_MEM_A_A<15>

TP_MEM_A_CKE<3>
TP_MEM_A_CLK2N

TP_MEM_A_CLK3N

TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>

TP_MEM_B_CLK2P

TP_MEM_B_CLK5N

TP_MEM_B_ODT<3>

TP_GPU_BUFRST_L
TP_GPU_GSTATE<0>
TP_GPU_GSTATE<1>
TP_GPU_MIOA_D<9..0>
TP_GPU_MIOA_DE

TP_MCP_BUF_SIO_CLK
TP_MCP_GPIO_18

NC_MCP_KBDRSTIN_L

TRUE
MAKE_BASE=TRUE

NC_MCP_SATALED_L

TRUE
MAKE_BASE=TRUE

TP_MCP_SATALED_L

NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_R2D_CP

MAKE_BASE=TRUE

TRUE

TRUE

PP3V3_S5_AVREF_SMC
PP18V5_S3

TRUE

PPDCIN_G3H

TRUE

PPVCORE_S0_MCP

TRUE

PPMCPDDR_ISNS

TRUE

PPVTTDDR_S3

TRUE

TRUE

PP1V8_S0GPU_ISNS

TRUE

PPVCORE_GPU

PP5V_S3

TRUE

TRUE

PP5V_S0
PPVCORE_S0_CPU

TRUE
TRUE

PPVCORE_S0_MCP

TRUE

PP3V3_S5

PP3V3_S0

TRUE

PP2V5_S0

TRUE

PP1V2_S0

TRUE

PP3V3_S3

TRUE

TRUE

PLT_RESET_SWITCH_L

TRUE

BKL_SYNC

TRUE

PP3V3_SW_LCD
=PP3V3_S0_DDC_LCD

TRUE

TRUE

PPVOUT_S0_LCDBKLT
LVDS_DDC_CLK

TRUE

TRUE

PP5V_S3_RTUSB_B_F

TRUE

BKL_FB

FSB_HITM_L

TRUE

LVDS_A_DATA_P<0>

TRUE

TP_PCI_AD<31..8>

TP_PCI_GNT0_L

TP_PCI_INTZ_L

TP_PCI_PAR

TP_PCI_SERR_L

TP_PCIE_CLK100M_PE4P

TP_SATA_C_D2RP

TP_SATA_C_D2RN

TRUE

PP1V8_GPUIFPX

LCD_BKLT_PWM

TRUE

TRUE

SMC_LID_R

PP3V42_G3H_LIDSWITCH_R

TRUE

TRUE

SMC_ONOFF_L

TRUE

LPCPLUS_GPIO

TRUE

ISSP_SDATA_P1_0

TRUE

ISSP_SCLK_P1_1

BKL_SDA

TRUE

TRUE

BKL_SCL

SMC_RESET_L

TRUE

WS_KBD18

TRUE

TRUE

WS_KBD17

TRUE

USB_LT3_N

USB_LT2_P

TRUE

SMC_RX_L

TRUE

TRUE

PM_SYSRST_L

WS_KBD19

TRUE

TRUE

SPI_ALT_CS_L

SMC_TDI

TRUE

SMC_NMI

TRUE

TP_SATA_F_D2RP
TP_SATA_F_R2D_CN

TP_SB_A20GATE
TP_SMC_P41

TP_USB_11P

TP_USB_EXTDP
TP_USB_MININ
TP_USB_MINIP

TP_USB_EXTDN

TP_USB_11N

TP_USB_10P

TP_SATA_F_R2D_CP

TP_SATA_F_D2RN

TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

TP_SATA_E_D2RN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RP

TP_SATA_D_D2RN

TP_SATA_C_R2D_CP

TP_SATA_C_R2D_CN

TP_PSOC_P1_3

TP_PEX_CLKREQ_L

TP_PE4_CLKREQ_L

TP_PCIE_PE4_D2RP

TP_PCIE_CLK100M_PE6N

TP_PCIE_CLK100M_PE5P

PP3V3_ENET_PHY

TRUE

PICKB_L

TRUE

PSOC_MISO

TRUE

PSOC_MOSI

TRUE

PSOC_SCLK

TRUE

SMC_KDBLED_PRESENT_L

TRUE

KBDLED_ANODE

TRUE

PP5V_S0_HDD_FLT

TRUE

SATA_ODD_R2D_N

TRUE

SATA_ODD_R2D_P

TRUE

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_D2R_C_P

TRUE

SMC_ODD_DETECT

TRUE

LED_RETURN_6

TRUE

LED_RETURN_4

TRUE

LED_RETURN_3

TRUE

LED_RETURN_2

TRUE

LED_RETURN_1

TRUE

LVDS_CONN_B_CLK_F_N

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_DATA_N<2>

TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

LVDS_CONN_B_DATA_N<1>

TRUE

LVDS_CONN_B_DATA_P<1>

TRUE

LVDS_CONN_B_DATA_P<0>

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_CONN_A_CLK_F_P

TRUE

LVDS_CONN_A_DATA_N<2>

TRUE

LVDS_CONN_A_DATA_P<2>

TRUE

LVDS_CONN_A_DATA_N<1>

TRUE

LVDS_CONN_A_DATA_P<1>

TRUE

LVDS_DDC_DATA

TRUE

SPKRAMP_R2_OUT_N

TRUE

SPKRAMP_R2_OUT_P

TRUE

TRUE

SPKRAMP_R1_OUT_N

TRUE

SPKRAMP_LFE_OUT_N

TRUE

SPKRAMP_L2_OUT_P

TRUE

SPKRAMP_L1_OUT_N

BI_MIC_HI

TRUE

BI_MIC_SHIELD

TRUE

TRUE

FAN_RT_TACH

TRUE

FAN_RT_PWM

TRUE

FAN_LT_TACH

FAN_LT_PWM

TRUE

TRUE

=PP5V_S0_FAN_LT

TRUE

PP3V3_S0GPU

TRUE

PP0V9R0V75_S0_DDRVTT

PP1V8R1V5_S0

TRUE

LVDS_A_DATA_N<0>

TRUE

LVDS_B_CLK_P

TRUE

TRUE

PP3V42_G3H

TRUE

PPMCPDDR_ISNS

PP1V05_S0

TRUE

PP1V8_S0

TRUE

PPBUS_G3H

TRUE

PM_SLP_S3_L

TRUE

TRUE

PPBUS_CPU_IMVP_ISNS

TRUE

WS_KBD11

WS_KBD13

TRUE

TRUE

PCIE_CLK100M_EXCARD_CONN_N

TRUE

PCIE_EXCARD_R2D_P

PCIE_EXCARD_D2R_P

TRUE

TRUE

EXCARD_CLKREQ_CONN_L

TRUE

EXCARD_CPPE_L

TRUE

EXCARD_CPUSB_L

SMBUS_MCP_0_DATA

TRUE

TRUE

SMBUS_MCP_0_CLK

TRUE

WS_KBD5

TRUE

WS_KBD3

TRUE

WS_KBD4

WS_KBD8

TRUE

WS_KBD10

TRUE

TP_MEM_A_CKE<2>

TP_MEM_A_CLK2P

TRUE
MAKE_BASE=TRUE

NC_MEM_A_CLK2P
NC_MEM_A_CLK3N

TRUE
MAKE_BASE=TRUE

NC_MEM_A_CLK3P

TRUE

MAKE_BASE=TRUE

TRUE

NC_MEM_A_CLK2N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_MEM_A_CKE<3>

MAKE_BASE=TRUE

TRUE

NC_MEM_A_CKE<2>

MAKE_BASE=TRUE

TRUE

NC_MEM_A_A<15>

MAKE_BASE=TRUE

TRUE

NC_FW643_TDI

MAKE_BASE=TRUE

TRUE

NC_FW643_AVREG

MAKE_BASE=TRUE

TRUE

NC_CPU_TEST3

TRUE

NC_FW0_TPAP

TRUE

NC_FW2_TPAP

TRUE

USB_CAMERA_CONN_P

SMBUS_SMC_A_S3_SDA

TRUE

LED_RETURN_5

TRUE

SPKRAMP_R1_OUT_P

TRUE

TP_PCI_INTW_L

PP5V_S3_BTCAMERA_F

TRUE

TRUE

PCIE_WAKE_L

MINI_CLKREQ_Q_L

TRUE

PCIE_CLK100M_MINI_CONN_N

TRUE

BI_MIC_LO

TRUE

SPKRAMP_LFE_OUT_P

TRUE

TRUE

PP5V_WLAN

LVDS_CONN_A_DATA_N<0>

TRUE

TRUE

NC_ALS_GAIN

TRUE

NC_ESTARLDO_EN

NC_FW0_TPBN

TRUE

NC_FW2_TPAN

TRUE

TRUE

NC_FW0_TPBP

TRUE

NC_FW2_TPBIAS

NC_FW2_TPBN

TRUE

TRUE

NC_FW2_TPBP

TRUE

NC_SMC_FAN_2_CTL

TRUE

NC_SMC_FAN_3_CTL

NC_USB_MINIP

MAKE_BASE=TRUE

TRUE

TP_XDP_OBSDATA_B3 NC_XDP_OBSDATA_B3

MAKE_BASE=TRUE

TRUE

TP_XDP_OBSDATA_B2 NC_XDP_OBSDATA_B2

MAKE_BASE=TRUE

TRUE

NC_USB_MININ

MAKE_BASE=TRUE

TRUE

NC_USB_EXTDP

MAKE_BASE=TRUE

TRUE

NC_USB_EXTDN

MAKE_BASE=TRUE

TRUE

NC_USB_11P

MAKE_BASE=TRUE

TRUE

NC_USB_11N

MAKE_BASE=TRUE

TRUE

NC_USB_10P

MAKE_BASE=TRUE

TRUE

NC_SMC_P41

MAKE_BASE=TRUE

TRUE

NC_SB_A20GATE

MAKE_BASE=TRUE

TRUE

NC_SATA_F_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_F_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

TRUE

TP_SATA_E_R2D_CP

NC_SATA_E_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_E_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RN

MAKE_BASE=TRUE

TRUE

NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RP

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RN

MAKE_BASE=TRUE

TRUE

NC_PSOC_P1_3

MAKE_BASE=TRUE

TRUE

NC_PEX_CLKREQ_L

MAKE_BASE=TRUE

TRUE

NC_PE4_CLKREQ_L

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE4_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE6N

MAKE_BASE=TRUE

TRUE

TP_PCIE_CLK100M_PE6P NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

TRUE

TP_PCIE_PE4_D2RN NC_PCIE_PE4_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

TRUE

TP_PCIE_CLK100M_PE5N NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE

TP_PCI_TRDY_L NC_PCI_TRDY_L

MAKE_BASE=TRUE

TRUE

TP_PCI_STOP_L NC_PCI_STOP_L

MAKE_BASE=TRUE

TRUE

NC_PCI_SERR_L

MAKE_BASE=TRUE

TRUE

TP_PCI_RESET1_L NC_PCI_RESET1_L

MAKE_BASE=TRUE

TRUE

TP_PCI_PERR_L NC_PCI_PERR_L

MAKE_BASE=TRUE

TRUE

TP_PCI_IRDY_L NC_PCI_IRDY_L

MAKE_BASE=TRUE

TRUE

NC_PCI_PAR

MAKE_BASE=TRUE

TRUE

TP_PCI_INTY_L

TP_PCI_INTX_L

NC_PCI_INTW_L

TRUE
MAKE_BASE=TRUE

TP_PCI_GNT1_L NC_PCI_GNT1_L

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT0_L

MAKE_BASE=TRUE

TRUE

TP_PCI_C_BE_L<3..0>

SMC_TX_L

TRUE

TRUE

FSB_HIT_L

FSB_A_L<31..3>

TRUE

TRUE

FSB_DRDY_L
FSB_DSTB_L_N<3..0>

TRUE

TRUE

SMC_MD1

TRUE

FSB_ADSTB_L<1..0>
FSB_D_L<63..0>

TRUE

TRUE

FSB_DBSY_L

TRUE

WS_KBD1

TRUE

WS_KBD2

WS_KBD9

TRUE

SPI_ALT_MISO

TRUE

TRUE

FSB_DSTB_L_P<3..0>

PP3V42_G3H

TRUE

TRUE

SPI_ALT_MOSI

MAKE_BASE=TRUE

TRUE

NC_ENET_INTR_L

MAKE_BASE=TRUE

TRUE

NC_ENET_PWRDWN_L

TRUE
MAKE_BASE=TRUE

NC_CPU_PECI_MCP

TP_FW643_TDI

TP_ENET_PWRDWN_L

DEBUG_RESET_L

TRUE

TP_MCP_KBDRSTIN_L

TP_LVDS_IG_BKL_PWM

TP_LVDS_IG_B_CLKP

TP_LVDS_IG_B_CLKN

TP_LVDS_EG_BKL_PWM

TP_LVDS_EG_B_CLK_P

TP_LVDS_EG_B_CLK_N

NC_MCP_BUF_SIO_CLK

TRUE

MAKE_BASE=TRUE

NC_MCP_GPIO_18

TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKN

TRUE
MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKP

TRUE
MAKE_BASE=TRUE

NC_LVDS_IG_BKL_PWM

TRUE

MAKE_BASE=TRUE

NC_LVDS_EG_BKL_PWM

TRUE
MAKE_BASE=TRUE

NC_LVDS_EG_B_CLK_P

TRUE

MAKE_BASE=TRUE

NC_GPU_VCORE_VID3

TRUE

MAKE_BASE=TRUE

NC_LPC_DRQ0_L

TRUE
MAKE_BASE=TRUE

NC_LVDS_EG_B_CLK_N

TRUE
MAKE_BASE=TRUE

NC_GPU_GSTATE<0>

TRUE

MAKE_BASE=TRUE

TP_MLB_RAM_VENDOR

TP_MLB_RAM_SIZE

TP_MEM_B_ODT<2>

TP_MEM_B_CS_L<3>

TP_MEM_B_CS_L<2>

TP_MEM_B_CLK5P

TP_MEM_B_CLK4P

TP_MEM_B_CLK4N

TP_MEM_B_CLK3P

TP_MEM_B_CLK3N

TP_MEM_B_CKE<2>

TP_MEM_B_A<15>

TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>

TP_MEM_A_CLK5P

NC_GPU_BUFRST_L

TRUE

MAKE_BASE=TRUE

NC_MLB_RAM_VENDOR

TRUE
MAKE_BASE=TRUE

NC_MLB_RAM_SIZE

TRUE

MAKE_BASE=TRUE

NC_MEM_B_ODT<2>

TRUE
MAKE_BASE=TRUE

NC_MEM_B_ODT<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK5P

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CS_L<2>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CS_L<3>

TRUE
MAKE_BASE=TRUE

NC_MEM_B_CLK4P

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK5N

TRUE
MAKE_BASE=TRUE

NC_MEM_B_CLK4N

TRUE
MAKE_BASE=TRUE

NC_MEM_B_CLK3P

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK3N

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CKE<2>

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK2P

TRUE

MAKE_BASE=TRUE

NC_MEM_B_A<15>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_ODT<2>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_ODT<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CS_L<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CS_L<2>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK5P

TRUE

MAKE_BASE=TRUE

TP_MEM_A_CLK4N

TP_MEM_A_CLK3P

TP_MEM_A_CLK4P
TP_MEM_A_CLK5N NC_MEM_A_CLK5N

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK4P

TRUE
MAKE_BASE=TRUE

NC_MEM_A_CLK4N

TRUE

MAKE_BASE=TRUE

SYS_LED_ANODE

TRUE

USB2_LT1_N

TRUE

USB2_LT1_P

TRUE

WS_KBD6

TRUE

PP1V5_S0_EXCARD_SWITCH

TRUE

PP5V_S3_RTUSB_A_F

TRUE

TRUE

WS_KBD15_CAP

TRUE

PCIE_MINI_R2D_N

TRUE

WS_KBD21

LPC_CLK33M_LPCPLUS

TRUE

LPC_FRAME_L

TRUE

WS_KBD20

TRUE

TRUE

PCIE_MINI_D2R_P

PCIE_CLK100M_MINI_CONN_P

TRUE

PP1V8R1V5_S3

TRUE

TRUE

MCPTHMSNS_D_N

TRUE

PCIE_EXCARD_R2D_N

CONN_USB2_BT_P

TRUE

USB_CAMERA_CONN_N

TRUE

Z2_MISO

TRUE

TRUE

PP1V1_S0GPU

TRUE

WS_KBD7

Z2_BOOST_EN

TRUE

Z2_BOOT_CFG1

TRUE

TRUE

Z2_RESET
PSOC_F_CS_L

TRUE

TRUE

PP1V8_S0GPU_ISNS_R

Z2_CLKIN

TRUE
TRUE

Z2_KEY_ACT_L

SMBUS_SMC_A_S3_SCL

TRUE

TRUE

PP1V2R1V05_ENET

PPVP_FW

TRUE

TRUE

PP1V0_FW

PP5V_SW_ODD

TRUE

LVDS_CONN_B_DATA_N<0>

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

PPVBAT_G3H_CONN_F

TRUE

SMC_BS_ALRT_L

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SMBUS_SMC_BSA_SCL

TRUE

ADAPTER_SENSE

TRUE

PP18V5_DCIN_FUSE

TRUE

TRUE

PP3V42_G3H

TRUE

PP3V3_S3

SMC_TDO

TRUE

SMC_TRST_L

TRUE

LPC_SERIRQ

TRUE

LPC_PWRDWN_L

TRUE

SMC_TCK

TRUE

SPI_ALT_CLK

TRUE

SMC_TMS

TRUE

TRUE

SMBUS_SMC_A_S3_SCL

FSB_DINV_L<3..0>

TRUE

PP5V_S3_RTUSB_C_F

TRUE

TRUE

USB2_EXCARD_CONN_P

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SMBUS_SMC_BSA_SCL
SMC_BIL_BUTTON_DB_L

TRUE

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_R2D_N

TRUE

SATA_HDD_R2D_P

TRUE

PCIE_EXCARD_D2R_N

TRUE

TRUE

MCPTHMSNS_D_P

SYS_LED_ANODE_R

TRUE

LPC_AD<0..3>

TRUE

PM_CLKRUN_L

TRUE

PPCPUVTT_S0

TRUE

TRUE

CONN_USB2_BT_N

PP3V3_S3_LDO

TRUE

PP18V5_S3

TRUE

TRUE

TPAD_GND_F

TRUE

Z2_DEBUG3

Z2_CS_L

TRUE

TRUE

PCIE_CLK100M_EXCARD_CONN_P

LVDS_CONN_A_DATA_P<0>

TRUE

MINI_RESET_CONN_L

TRUE

PP1V2R1V05_S5

TRUE

TP_PCI_CLK0

TRUE

PCIE_WAKE_L

TRUE

PP3V3_S0_EXCARD_SWITCH

TRUE

PP3V3_S3_EXCARD_SWITCH
USB2_EXCARD_CONN_N

TRUE

TRUE

FSB_LOCK_L

SPIROM_USE_MLB

TRUE

TRUE

LVDS_B_DATA_N<0>
LVDS_B_DATA_P<0>

TRUE

LVDS_EG_A_DATA_N<2>

TRUE

TRUE

USB_LT2_N

WS_KBD12

TRUE

TRUE

WS_KBD14

TRUE

WS_KBD16_NUM

84 82 67

91

91

95

95

95

95

95

43

41

91

91

31

43

84

84

31

88

88

90

96

96

79

80

80

80

95

80

96

78

88

95

49

43

42

43

95

95

95

95

95

95

95

95

95

96

96

96

96

96

96

95

95

42

36

90

44

44

94

96

30

96

95

42

88

88

88

88

88

88

88

88

42 91

43

90

94

95

94

59

94

94

42

43

43

43

43

43

94

88

94

94

90

43

43

95

30

88

95

95

95

14

14

90

30

57

57

98

72

73

73

73

73

73

42

50

8

8

8

96

9

8

85

75

85

81

14

84

85

42

43

42

98

96

41

41

42

43

50

50

50

50

90

90

90

90

41

85

85

85

85

85

95

95

81

81

81

81

81

95

95

81

81

81

81

81

57

57

57

57

57

57

58

58

48

84

84

8

8

45

33

96

90

31

21

21

96

44

85

57

17

96

58

57

81

41

14

14

14

14

43

14

14

14

14

8

43

42

96

96

90

43

41

30

96

96

90

96

96

50

50

50

50

50

50

44

81

44

42

44

44

8

8

42

43

41

41

42

42

44

14

96

44

44

59

90

90

90

90

31

96

41

41

96

50

50

50

96

81

17

96

14

84

84

84

96

42

42

10

19

10

74

75

19

19

19

49

49

49

49

49

49

30

17

56

56

96

40

40

85

71

71

71

71

71

71

9

10

18

35

9

16

15

16

16

16

15

16

16

74

75

75

75

75

21

17

20

41

7

8

7

7

8

8

8

8

8

8

7

8

8

8

8

7

31

78

78

8

78

78

39

10

81

19

19

19

19

19

17

20

20

8

84

40

40

41

18

49

49

41

49

49

96

39

39

25

49

43

41

41

20

20

21

42

20

9

9

9

9

20

20

20

20

20

20

20

20

20

20

20

20

20

49

69

17

17

17

17

8

49

49

49

49

50

50

38

38

38

38

38

38

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

78

56

56

56

56

56

56

57

57

48

48

48

48

8

8

8

8

81

81

7

7

8

8

8

21

8

49

49

31

31

17

31

31

31

13

13

49

49

49

49

49

16

15

37

37

30

7

78

56

19

30

7

30

30

57

56

30

78

42

42

37

37

37

37

37

37

42

42

13

13

20

17

17

17

19

19

19

19

19

19

19

19

19

39

10

10

10

10

41

10

10

10

49

49

49

43

10

7

43

35

18

25

21

9

9

9

75

75

75

21

21

16

16

16

16

16

16

16

16

16

9

16

16

16

16

16

16

16

40

39

39

49

31

39

49

30 49

25

19

49

17

30

8

47

31

30

30

49

8

49

50

49

49

49

8

49

49

7

8

8

8

38

78

7

59

41

7

7

59

59

7

7

41

41

19

19

41

43

41

7

10

98

31

7

7

42

38

38

38

38

17

47

40

19

19

8

30

50

7

50

49

49

31

78

30

8

19

7

31

31

31

10

43

81

81

76

39

49

49

49

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

"FW" (FireWire) Rails

500 mA max supply

"GPU" Rails

OR 0.75V

ENET Rails

190 mA

1.8V/DDR 1.5V Rails

5V Rails

Chipset "VCore" Rails

3.3V-2.5V Rails

(1.1V for A01)

1182 mA

4500 mA

139 mA/ 0 mA

105 mA/241 mA

1034 mA

5300 mA

241 mA max load

130 mA

500 mA

4771 mA

"G3Hot" (Always-Present) Rails

051-7656

SYNC_DATE=05/07/2008

8

123

31

SYNC_MASTER=RXU_K20

Power Aliases

=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_GPU_SMBUS_SMC_0_S0

=PP3V3_S0_TPAD

=PP3V3_FW_FWPHY
=PP3V3_FW_P1V0FW

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=6V

MIN_LINE_WIDTH=0.4 mm

PPBUS_G3H

=PPVIN_S5_P5VP3V3

=PPVIN_S0_CPUVTTS0

=PPBUS_S0_LCDBKLT

=PPVIN_S0_P5VRTS0_MCPCORE

=PPVIN_S0GPU_P1V8P1V1

=PPVIN_S0_P1V05S5

=PP3V3_S5_SMC

=PP3V42_G3H_PWRCTL

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.42V

PP3V42_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 MM

=PPVIN_S5_CPU_IMVP_ISNS

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.5 MM

MAKE_BASE=TRUE

PP1V8_S0

MIN_NECK_WIDTH=0.2 MM

=PP1V8R1V5_S0_MCP_MEM

=PP1V8_S0_REG

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V8_S0_MCP_PLL_VLDO

=PP1V5_S0_VMON

=PP1V8R1V5_S0_FET

=PPMCPDDR_ISNS_R
=PP1V5_S0_CPU

=PP1V5_S3_MEMRESET

=PP1V5_S3_MEM_B

=PP1V5_S3_MEM_A

=PPVIN_S0_DDRREG_LDO

=PPDDR_S3_REG

=PP1V8R1V5_S0_MCP_FET

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.5V

PP1V8R1V5_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V8R1V5_S3

MAKE_BASE=TRUE

VOLTAGE=1.5V

=PP3V3_S5_REG

=PP3V3_S0_LCD
=PP3V3_S0_P3V3S0FET

=PP3V3_S5_ROM

=PP1V5_EXP_S0

=PP1V05_S0_FET

=PP3V3_S0_BATTCHARGERTMPSNSR

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_FAN_RT

=PP3V3_S0_GPU1V8ISNS

=PPVIN_S5_FWPWRSW

PP1V05_S0

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_HDMI_VDD

=PP1V05_S0_VMON

=PP1V05_S0_MCP_PLL_PEX_UF

=PP1V05_S0_MCP_PLL_UF

=PP1V5_S0_EXCARD

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

PP1V5_EXP_S0

VOLTAGE=1.5V

=PP1V05_S0_MCP_FSB

=PP1V05_S0_SMC_LS

=PP1V05_S0_CPU

=PPCPUVTT_S0_REG

=PP1V05_S5_P1V05S0FET

=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S5_MCP

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

=PP1V05_S0_MCP_SATA_AVDD0

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_DVDD1

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

=PP1V5_S0_MEM_B

=PPMCPDDR_ISNS

=PP1V5_S0_MEM_A

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPCPUVTT_S0

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V2R1V05_S5

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_DVDD0

MAKE_BASE=TRUE

VOLTAGE=1.5V

PPMCPDDR_ISNS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

=PP3V3_S5_MEMRESET

=PP3V3_S0_DPCONN

=PP3V3_S0_P1V2P2V5

=PP3V3_S0_MCP_GPIO

=PP3V3_S5_P3V3ENETFET
=PP3V3_S5_DP_PORT_PWR

=PP3V3_S0_MCPDDRISNS

=PP3V3_S5_MCPPWRGD

=PP3V3_FW_LATEVG_ACTIVE

=PPVCORE_S0_CPU

=PPVOUT_FW_FWPWRSW

=PPSPD_S0_MEM_B

VOLTAGE=5V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PP5V_S3

MIN_LINE_WIDTH=0.5 mm

=PP5V_S3_RTUSB

=PP5V_S3_TPAD

=PP5V_S3_VTTCLAMP

=PP5V_S0_HDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

PPVCORE_S0_MCP

VOLTAGE=1.05V

=PP3V42_G3H_BMON_ISNS

=PP3V3_S5_RTC_D

=PP5V_S3_AUDIO_PWR

=PP5V_S3_MCPDDRFET

=PP5V_S3_P1V05S0FET

=PP5V_S3_GPUVCORE

=PP5V_S0_ODD

=PP5V_S0_CPUVTTS0

=PP5V_S0_CPU_IMVP

=PP3V3_S0_SMBUS_MCP_1

=PP5V_S3_REG

=PP5V_S0_REG

=PP5V_S0_FAN_RT

=PP3V42_G3H_LIDSWITCH

=PP5V_S3_WLAN

VOLTAGE=3.3V

PP3V3_S0GPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.20MM

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_CHGR

=PP3V42_G3H_REG

=PPVIN_S5_SMCVREF

=PP3V42_G3H_BATT

MAKE_BASE=TRUE

VOLTAGE=2.5V

PP2V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V
MAKE_BASE=TRUE

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

PPBUS_FW_FWBOOST

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM

MAKE_BASE=TRUE

VOLTAGE=6V

PP10V_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=10V
MAKE_BASE=TRUE

PPVP_FW

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=10V
MAKE_BASE=TRUE

=PPBOOST_S5_FW_FET

=PFWBOOST_REG

=PPVIN_PFWBOOST

VOLTAGE=0.75V
MAKE_BASE=TRUE

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=0.9V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=2 mm

PP0V9R0V75_S0_DDRVTT

MAKE_BASE=TRUE

=PPVTT_S0_DDR_LDO

=PPVTT_S3_DDR_BUF

=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP

=PP5V_S0GPU_P1V1P1V8_GPU

=PP1V2_S0_GMUX

=PP2V5_S0_GMUX

VOLTAGE=1.2V
MAKE_BASE=TRUE

PP1V2_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V8_GPU_REG

=PP1V8_S0GPU_ISNS_R

=PPVCORE_GPU

VOLTAGE=1.2V
MAKE_BASE=TRUE

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP3V3_GPU_VDD33

=PPVCORE_S0_MCP

VOLTAGE=1.05V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V2R1V05_ENET

VOLTAGE=3.3V

PP3V3_ENET_PHY

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_MCP_RMGT
=PP1V05_ENET_PHY

=PP3V3_ENET_PHY

=PP3V3_ENET_FET

=PP1V05_ENET_FET

=PP3V3_S0GPU_FET

=PP3V3_GPU_VCORELOGIC

=PP3V3_GPU_PWRCTL

=PP3V3_ENET_MCP_RMGT

=PP1V8_S0GPU_ISNS

=PP1V8_GPU_FBVDDQ

=PP1V8_GPU_FB_VDD

=PP3V3_GPU_P1V8S0

=PP1V8_GPU_FBIO

=PP1V8_GPU_FB_VDDQ

=PP1V1_GPU_PEX_IOVDD

=PP1V1_S0GPU_REG

=PP1V8_GPU_IFPX

=PP1V8_GPUIFPX_REG

PP1V1_S0GPU

VOLTAGE=1.1V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

=PP1V2_S0_REG

=PPMCPCORE_S0_REG

=PP18V5_DCIN_CONN

=PPVCORE_GPU_REG

VOLTAGE=1.8V

PP1V8_S0GPU_ISNS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V

PP1V8_S0GPU_ISNS_R

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM

PP1V8_GPUIFPX

MAKE_BASE=TRUE

=PP1V1_GPU_IFPCD_IOVDD

=PP1V1_GPU_FBPLLAVDD

=PP1V1_GPU_VID_PLLVDD

=PP1V1_GPU_H_PLLVDD

=PP1V1_GPU_PLLVDD

=PP1V1_GPU_PEX_PLLXVDD

=PP1V1_GPU_PEX_IOVDDQ

=PP3V3_GPU_LVDS_DDC

=PP3V3_GPU_MIO

=PPBOOST_FW_FWPWRSW_F

=PP1V0_FW_FWPHY

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.0V

PP1V0_FW

=PPVCORE_S0_CPU_REG

=PP5V_S0_LPCPLUS

=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V42_G3H_SMCUSBMUX

=PP3V3_S0_LVDSDDCMUX

=PP3V3_S5_MCP_GPIO

=PP3V3_S0_AUDIO

=PP3V3_S0_MCP

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_PLL_UF

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_HDCPROM

=PP3V3_S0_GMUX

=PPSPD_S0_MEM_A

=PP3V3_S0_DDC_LCD

=PP3V3_S0_PWRCTL

=PP3V3_S0_GPUTHMSNS

MAKE_BASE=TRUE

PPBUS_CPU_IMVP_ISNS

VOLTAGE=6V

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.4 MM

=PP5V_S0_FAN_LT

VOLTAGE=5V

PP5V_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.6 MM

=PP3V3_S0_DPMUX

=PP3V3_S0_SMBUS_MCP_0

=PP3V42_G3H_TPAD

=PP3V42_G3H_CPUCOREISNS

=PP5V_S3_DDRREG

=PP5V_S3_IR

MIN_NECK_WIDTH=0.20MM

PP3V3_S0

MIN_LINE_WIDTH=0.3 MM

VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S0_FAN_LT

=PP1V0_FW_REG

=PP3V3_S0_SMC

=PP1V05_S0_MCP_PEX_DVDD

=PPVIN_GPU_GPUVCORE

=PP3V3_S3_P3V3S3FET

=PP3V3_GPU_P3V3GPUFET
=PP3V3_S5_PWRCTL

=PP3V3_S5_P1V05FET
=PP3V3_S5_MCP

=PPBUS_G3H

=PPVBAT_G3H_P3V42G3H

=PPVIN_S3_DDRREG

=PPVIN_S5_CPU_IMVP_ISNS_R

=PP3V3_S0_IMVP

=PP3V3_S0_XDP

=PP3V3_S0_MCPCOREISNS
=PP3V3_S0_XDP

=PP3V3_S0_ODD

=PP3V3_S0_VMON

=PP3V3_S0_EXCARD

=PP3V3_S0_REMTHMSNS

=PP2V5_S0_REG

=PP5V_S3_SYSLED

=PP5V_S3_BTCAMERA

=PPDCIN_S5_CHGR

=PP3V3_S3_P1V5EXPS0

=PP3V3_S3_SMS

=PP3V3_S3_SMS

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_P1V8S0

=PP3V3_S3_TPAD

MAKE_BASE=TRUE

PP3V3_S5

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

=PP3V3_S3_FET

=PPVIN_S5_CPU_IMVP

PPDCIN_G3H

MAKE_BASE=TRUE

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

=PP3V3_S3_BT

=PP3V3_S3_GMUX

=PP3V3_S5_P1V05ENETFET

=PP3V3_FW_LATEVG

=PPVIN_S0_KBDLED

=PPVIN_S5_BKL

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

PP3V3_S3

=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO

=PP3V3_S3_VREFMRGN
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_EXCARD

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_LPCPLUS

=PP3V3_S0_FET

61 13

80

23

12

80

79

51

22

11

21

45

75

45

79

73

58

23

78

96

13

13

37

45

42

42

23

24

12

52

68

23

23

24

66

14

10

23

23

19

12

98

63

74

23

23

23

73

72

77

75

20

57

22

23

75

48

9

23

23

8

8

51

51

96

66

44

50

35

66

7

62

65

86

64

83

66

41

67

7

45

7

16

66

18

66

67

68

46

11

29

28

27

63

63

68

7

7

62

78

68

43

66

66

47

47

48

46

36

7

23

8

8

18

67

23

23

31

9

42

6

65

68

33

22

66

23 20

23

8

20

17

17

28

46

27

7

7

17

17

7

29

82

87

18

33

82

46

25

36

11

36

28

7

39

50

68

38

7

45

25

9

68

68

77

38

65

61

44

62

64

48

40

30

7

43

60

59

42

59

7

7

7

36

66

66

7

7

63

26

27

28

68

83

84

84

7

83

46

70

7

6

22

7

7

23

18

32

32

33

33

68

77

67

18

46

70

72

66

71

9

69

83

76

66

7

87 64

59

45

7

7

7

76

71

74

74

74

69

69

81

74

36

35

7

61

43

37

37

44

39

81

18

53

21

24

24

23

21

24

84

27

7

67

47

7

7

7

81

44

49

45

63

40

7

48

66

42

8

77

68

68

67

68

22

60

59

63

45

61

6

46

6

38

67

31

47

87

42

30

60

66

8

8

44

66

49

7

68

61

7

30

84

33

37

50

7

30

21

26

44

31

44

43

68

Preliminary

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Frame Holes

Extra FSB Pull-ups

Exist in MRB but not Intel designs. Here for CYA.

Bosses for Flex Protector Bracket

Digital Ground

If found to be necessary, will move to page14.csa

TM Hole

TM Hole

Left CPU

TM Hole

GPU signals

TM Hole

ETHERNET ALIASES

CPU signals

AUDIO ALIASES

Right CPU

GMUX ALIASES

Bottom Left GPU

Thermal Module Holes

MCP79 PCIe PRSNT# Straps

Top GPU Right

ZT0980

STDOFF-4.5OD.98H-1.1-3.48-TH

2

1

R0930

47K

MF-LF

5%

402

1/16W

21

R0925

402

5%
1/16W
MF-LF

0

17

21

R0902

402

MF-LF

1/16W

5%

10K

2 1

XW0900

SM

2 1

XW0901

SM

21

R0900

402

1%

10

MF-LF

1/16W

21

R0901

402

10

MF-LF

1%

1/16W

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0983

ZT0984

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0985

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0986

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0987

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0945

3R2P5

1

1

ZT0960

3R2P5

1

ZT0989

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0988

STDOFF-4.5OD.98H-1.1-3.48-TH

1

ZT0991

STDOFF-4.5OD.98H-1.1-3.48-TH

21

R0926

402

0

MF-LF

5%

1/16W

17

84

21

R0927

NO STUFF

0

402

1/16W

5%

MF-LF

ZT0930

STDOFF-4.5OD.98H-1.1-3.48-TH

10 14 88

10 14 88

10 13 14 88

10 14 88

1/16W

2

1

R0960

5%

62

402

MF-LF

NO STUFF

1/16W

2

1

R0970

200

402

5%

MF-LF

NO STUFF

2

1

R0980

1/16W
MF-LF

1%

NO STUFF

402

150

MF-LF

2

1

R0990

1%

402

1/16W

150

NO STUFF

STDOFF-4.0OD3.0H-SM

1

ZT0934

1

ZT0931

STDOFF-4.0OD3.0H-SM

21

R0903

402

5%
1/16W
MF-LF

0

3R2P5

ZT0932

1

1

ZT0971

3R2P5

1

SH0913

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0910

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0912

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0914

1

1

SH0911

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

1

SH0900

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

SH0903

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0902

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1/16W

NO STUFF

2

1

R0950

220

MF-LF
402

5%

10 14 61 88

1

SH0919

2.0DIA-TALL-EMI-MLB-M97-M98

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SM

SH0917

SH0916

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0918

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0920

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0921

SM

1

SH0922

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0923

SM

1

ZT0957

4.0OD1.65H-M1.6X0.35

ZT0958

1

4.0OD1.65H-M1.6X0.35

1

SH0901

2.0DIA-TALL-EMI-MLB-M97-M98

SM

1

ZT0915

3R2P5

SH0924

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0930

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0931

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0932

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0933

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

SH0935

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0934

1

SM

1

ZT0965

3R2P5

1

ZT0940

3R2P5

3R2P5

ZT0970

1

SYNC_DATE=09/24/2008

SYNC_MASTER=K20_MLB

051-7656

31

123

9

Signal Aliases

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GND

GND_BATT_CHGND

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

=P1V5_EXP_S0_EN

MCP_MII_PD

MAKE_BASE=TRUE

PP3V3_S0

=MCP_MII_RXER

=PP1V8_GPU_FB_VDDQ

GMUX_INT

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_GMUX_TDO

TP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

LVDS_MUX_SEL_EG

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_IG_HPD

GMUX_JTAG_TDI

ALL_EG_PGOOD

FSB_BREQ0_L

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_B

TP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

=MCP_HDMI_DDC_DATA

=DVI_HPD_GMUX_INT

GMUX_JTAG_TDO

=PP5V_S3_AUDIO_PWR

MAKE_BASE=TRUE

HDA_BITCLK

NC_LVDS_IG_B_DATAN<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_B_DATA_N<3>

LVDS_IG_B_DATA_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAN<3>

LVDS_IG_A_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_DATA_P<3>

TP_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

LVDS_IG_B_CLK_N

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKP

LVDS_IG_B_CLK_P

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

CPU_PECI_MCP

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MEM_B_A<15>

MAKE_BASE=TRUE

TP_MEM_A_A<15>

MEM_A_A<15>

TP_IMVP6_CLKEN_L

MAKE_BASE=TRUE

VR_PWRGD_CLKEN_L

=SPI_CS1_R_L_USE_MLB

MEM_VTT_EN

MAKE_BASE=TRUE

=DDRVTT_EN

CPU_BSEL<0..2>

MAKE_BASE=TRUE

=MCP_BSEL<0..2>

MAKE_BASE=TRUE

CPU_VID<0..6>

IMVP6_VID<0..6>

=RTL8211_REGOUT

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

=RTL8211_ENSWREG

=PP3V3_ENET_PHY_VDDREG

SMC_MCP_SAFE_MODE

MAKE_BASE=TRUE

PM_SLP_RMGT_L

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

CPU_DPRSTP_L

=PP1V8_GPU_FB_VREF_A

MAKE_BASE=TRUE

TP_USB_EXTDP

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_AUDIO

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_AUDIO_AMP

USB_EXTD_P

USB_EXTD_N

TP_USB_MINIP

MAKE_BASE=TRUE

TP_USB_EXTDN

MAKE_BASE=TRUE

USB_MINI_P

USB_MINI_N

MAKE_BASE=TRUE

TP_USB_MININ

=PEG_D2R_P<0..15>

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

=PEG_D2R_N<0..15>

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

=PEG_R2D_C_P<0..15>

=PEG_R2D_C_N<0..15>

PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

LVDS_BKL_ON

LCD_BKLT_EN

MAKE_BASE=TRUE

=MCP_HDMI_TXC_P

MAKE_BASE=TRUE

DP_IG_ML_P<3>

=MCP_HDMI_TXC_N

DP_IG_ML_N<2..0>

MAKE_BASE=TRUE

DP_IG_DDC_DATA

MAKE_BASE=TRUE

=MCP_MII_CRS

=MCP_MII_COL

EG_CLKREQ_OUT_L

MAKE_BASE=TRUE

PCIE_FW_PRSNT_L

TP_SPI_CS1_R_L_USE_MLB

MAKE_BASE=TRUE

TP_PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

=P1V05ENET_EN

MCP_SPKR

MAKE_BASE=TRUE

PEG_PRSNT_L

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_DDC_CLK

=MCP_HDMI_HPD

GPU_RESET_L

IG_BKLT_EN

IG_LCD_PWR_EN

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

LVDS_IG_BKL_PWM

=PP1V05_S0_MCP_FSB

CPU_NMI

CPU_INTR

FSB_CPURST_L

MAKE_BASE=TRUE

AUD_IPHS_SWITCH_EN

HDA_BIT_CLK

=MCP_HDMI_TXD_N<0..2>

MAKE_BASE=TRUE

DP_IG_ML_P<2..0>

MAKE_BASE=TRUE

DP_IG_ML_N<3>

EG_RESET_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_GMUX_TDI

DP_IG_DDC_CLK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

GMUX_JTAG_TMS

=P3V3ENET_EN

MAKE_BASE=TRUE

JTAG_GMUX_TMS

GND_CHASSIS_USB

GND_CHASSIS_RIGHTHS

GND_CHASSIS_SATA

GND_CHASSIS_TPAD

GND_CHASSIS_CLUTCH

GND_CHASSIS_DIMM

GND_CHASSIS_LVDS

80 79

23

96

73

22

8

72

84

90

90

90

90

90

90

43

68

88

88 88

55

91

91

91

91

90

90

90

90

90

81

14

58

91

90

90

84

81

90

84

20

20

66

7

18

8

84

6

84

67

81

19

84

26

73

7

18

18

17

8

53

18

18

18

18

7

18

7

18

7

14

7

28

7

27

61

21

25 63

10 14

11 61

32

32

32

41

21

26

72

7

53

56

20

20

7

7

20

20

7

17 69

17 69

17

17 69

86 84

18 81

18

81

75

18

18

33

21

18

18

18

69

84

84 18

18

18

8

19

21

18

81

81

84

6

75

69

19

33

6

Preliminary

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN

OUT

IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI
BI
BI

BI
BI
BI

BI

BI

BI
BI

BI
BI
BI
BI
BI

BI

OUT

OUT

OUT

OUT

OUT

IN

IN
IN
IN
IN
IN

IN
IN

IN
IN

OUT

IN
IN

IN

IN

IN
IN

IN

IN

OUT

BI
BI
BI
BI

LOCK*

INIT*

A20M*

A6*

A3*
A4*

A14*

A16*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*
A21*
A22*
A23*
A24*

A26*
A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5
RSVD6
RSVD7
RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

TEST7

TEST6

DSTBP1*
DINV1*

D31*

D30*

D25*

D11*
D12*
D13*
D14*

DSTBP0*
DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32*
D1*
D2*

D5*

D16*

D20*
D21*
D22*
D23*
D24*

D26*
D27*
D28*
D29*

DSTBN1*

GTLREF

TEST3
TEST4
TEST5

BSEL0
BSEL1
BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*
DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PIN. MAKE SURE CPU_TEST4 IS

PLACE C1000 CLOSE TO CPU_TEST4

REFERENCED TO GND

0.5" MAX LENGTH FOR CPU_GTLREF

FSB_IERR_L WITH A GND

PLACE TESTPOINT ON

0.1" AWAY

GMCH WITHOUT T (NO STUB)

SHOULD CONNECT TO ICH AND

PM_THRMTRIP#

COMP1,3 CONNECT WITH ZO=55OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,
MAKE TRACE LENGTH SHORTER THAN 0.5".

LAYOUT NOTE:

402

MF-LF

54.9

1/16W

1%

R1002

1

2

MF-LF
402

1/16W

5%

68

R1004

1

2

402

1K

MF-LF

1%

1/16W

R1005

1

2

402

1/16W

2.0K

MF-LF

1%

R1006

1

2

1/16W
MF-LF

1%

54.9

402

R1019

1 2

1%

MF-LF

1/16W

27.4

402

R1018

1 2

54.9

1/16W
MF-LF

1%

402

R1017

1 2

1/16W
MF-LF

1%

27.4

402

R1016

1 2

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

9

14 61 88

14 88

14 88

14 88

61

13 14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

9

88

9

88

9

88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

7

14 88

14 88

14 88

14 88

7

14 88

7

14 88

9

14 88

7

14 88

7

14 88

7

14 88

13 88

13 88

13 88

13 88

13 88

13 88

6

10 88

13 25

14 42 61 88

47 96

14 42 88

14 88

9

13 14 88

14 88

14 88

14 88

14 88

6

10 13 88

6

10 13 88

6

10 13 88

6

10 13 88

47 96

14 88

14 88

14 88

14 88

9

14 88

9

14 88

14 88

14 88

14 88

NOSTUFF

5%

MF-LF

1/16W

0

402

R1030

1 2

402

NOSTUFF

1K

MF-LF

5%
1/16W

R1007

1

2

402

54.9

MF-LF

1%

1/16W

R1003

1

2

54.9

1/16W
MF-LF

1%

402

R1020

1 2

1%

MF-LF

1/16W

54.9

402

R1021

1 2

1%

54.9

MF-LF

1/16W

402

R1022

1 2

14 88

14 88

14 88

14 88

1%

MF-LF

1/16W

402

649

R1023

1 2

402

MF-LF

NOSTUFF

5%

1/16W

1K

R1012

1

2

402

16V

10%

0.1uF

NOSTUFF

X5R

C1000

1

2

MF-LF

1/16W

1%

402

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

54.9

R1024

1 2

OMIT

PENRYN

FCBGA

U1000

N3
P5

P2

L2
P4

P1

R1

Y2

U5
R3

W6

A6

U4
Y5

U1
R4

T5

T3
W2

W5

Y4

J4

U2

V4

W3
AA4

AB2
AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22

A21

E2

AD4

AD3

AD1
AC4

G5

F1

C20

E1

H5

F21

A5

G6

E4

D20

C4

B3

C6

B4

H4

AC2
AC1

D21

K3

H2

K2

J3

L1

C1

F3
F4

G3

M4

N5

T2

V3

B2

F6

D2

D22

D3

A3

D5

AC5

AA6
AB3

A24

B25

C7

AB5

G2

AB6

OMIT

PENRYN

FCBGA

U1000

B22

B23
C21

R26
U26

AA1
Y1

E22

F24

J24
J23

H22

F26
K22

H23

N22

K25

P26
R23

E26

L23

M24
L22

M23
P25

P23

P22
T24

R24

L25

G22

T25

N25

Y22

AB24
V24

V26

V23
T22

U25
U23

F23

Y25

W22
Y23

W24

W25
AA23

AA24

AB25

AE24

AD24

G25

AA21
AB22

AB21

AC26
AD20

AE22
AF23

AC25

AE21
AD21

E25

AC22

AD23
AF22

AC23

E23

K24
G24

H25

N24

U22

AC20

E5
B5

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6
D7

C23
D25

C24

AF26

AF1

A26

C3

CPU FSB

10

31

051-7656

123

SYNC_MASTER=M98_MLB

SYNC_DATE=04/01/2008

FSB_DSTB_L_N<3>

CPU_COMP<3>

CPU_COMP<0>
CPU_COMP<1>
CPU_COMP<2>

CPU_TEST2

XDP_TMS

=PP1V05_S0_CPU

XDP_TDO

XDP_TDI

XDP_TCK

XDP_TRST_L

=PP1V05_S0_CPU

=PP1V05_S0_CPU

=PP1V05_S0_CPU

TP_CPU_RSVD8

TP_CPU_RSVD7

TP_CPU_RSVD6

TP_CPU_RSVD5

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_IGNNE_L

CPU_THERMD_N

FSB_A_L<11>

FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_BPRI_L

FSB_A_L<12>
FSB_A_L<13>

FSB_ADSTB_L<0>

FSB_A_L<17>

FSB_A_L<19>

FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>

CPU_FERR_L

CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L

TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4

FSB_BNR_L

FSB_DEFER_L
FSB_DRDY_L
FSB_DBSY_L

FSB_BREQ0_L

CPU_IERR_L

FSB_CPURST_L
FSB_RS_L<0>
FSB_RS_L<1>
FSB_RS_L<2>
FSB_TRDY_L

FSB_HIT_L
FSB_HITM_L

XDP_BPM_L<0>
XDP_BPM_L<1>
XDP_BPM_L<2>
XDP_BPM_L<3>
XDP_BPM_L<4>
XDP_BPM_L<5>
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST_L
XDP_DBRESET_L

CPU_PROCHOT_L
CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<0>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<6>

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_REQ_L<1>

CPU_TEST1

FSB_D_L<10>

FSB_D_L<15>
FSB_DSTB_L_N<0>

FSB_D_L<3>
FSB_D_L<4>

FSB_D_L<17>

CPU_PSI_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

TP_CPU_TEST5

CPU_TEST4

TP_CPU_TEST3

CPU_GTLREF

FSB_DSTB_L_N<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<16>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<32>

FSB_D_L<0>

FSB_D_L<18>
FSB_D_L<19>

FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<25>

FSB_D_L<30>
FSB_D_L<31>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

TP_CPU_TEST7

TP_CPU_TEST6

FSB_A_L<25>

FSB_A_L<18>

FSB_A_L<16>

FSB_A_L<14>

61

61

61

61

13

13

13

13

12

12

12

12

88

11

88

88

88

11

11

11

13

10

88

13

13

13

10

10

10

10

8

10

10

10

10

8

8

8

88

88

88

88

88

6

6

6

6

6

6

6

6

6

88

7

26

Preliminary

OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

VCC

VCCP

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

30.4 A (LFM)

2500 mA (after VCC stable)

4500 mA (before VCC stable)

16.0 A (Deep Sleep SuperLFM)

16.8 A (Sleep SuperLFM)

41.0 A (HFM)

(CPU CORE POWER)

130 mA

(CPU IO POWER 1.05V)

(CPU INTERNAL PLL POWER 1.5V)

Low Voltage:

23.0 A (Design Target)

18.7 A (LFM)
TBD A (SuperLFM)

TBD A (Sleep SuperLFM)

TBD A (Deeper Sleep)

TBD A (Sleep HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (HFM)
TBD A (LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep LFM)

25.5 A (SuperLFM)

27.4 A (Sleep HFM)

25.0 A (Deep Sleep HFM)

11.5 A (Deeper Sleep)

9.4 A (Enhanced Deeper Sleep)

TBD A (Sleep HFM)

21.0 A (HFM)

TBD A (Deep Sleep HFM)

TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Enhanced Deeper Sleep)

TBD A (Deeper Sleep)

TBD A (Deep Sleep LFM)

TBD A (Deep Sleep HFM)

TBD A (Deep Sleep SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

44.0 A (Design Target)

Standard Voltage:

Ultra Low Voltage:

17.0 A (Design Target)

TBD A (Enhanced Deeper Sleep)

9

88

9

88

9

88

9

88

9

88

9

88

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

MF-LF
402

100

1%
1/16W

R1101

1

2

9

88

61 88

61 88

MF-LF
402

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

1/16W

1%

100

R1100

1

2

OMIT

PENRYN

FCBGA

U1000

A7
A9

B9

B10
B12

B14

B15
B17

B18

B20

C9

C10

A10

C12

C13

C15
C17

C18

D9
D10

D12

D14
D15

A12

D17
D18

E7

E9
E10

E12

E13
E15

E17

E18

A13

E20

F7

F9

F10

F12
F14

F15

F17
F18

F20

A15

AA7
AA9

AA10
AA12

AA13

AA15
AA17

AA18

AA20

AB9

A17

AC10

AB10
AB12

AB14
AB15

AB17

AB18

AB20
AB7

AC7

A18

AC9
AC12

AC13

AC15
AC17

AC18
AD7

AD9

AD10
AD12

A20

AD14

AD15
AD17

AD18

AE9
AE10

AE12
AE13

AE15

AE17

B7

AE18

AE20
AF9

AF10
AF12

AF14

AF15
AF17

AF18

AF20

B26

C26

G21

V6

R21

R6

T21

T6
V21

W21

J6

K6
M6

J21

K21
M21

N21

N6

AF7

AD6

AF5
AE5

AF4

AE3
AF3

AE2

AE7

OMIT

PENRYN

FCBGA

U1000

A4
A8

B11

W1

W4
W23

W26
Y3

Y6
Y21

Y24

AA2
AA5

B13

AA8

AA11
AA14

AA16

AA19
AA22

AA25
AB1

AB4

AB8

B16

AB11

AB13

AB16
AB19

AB23

AB26
AC3

AC6

AC8

AC11

B19

AC14

AC16
AC19

AC21

AC24
AD2
AD5
AD8

AD11
AD13

B21

AD16

AD19
AD22

AD25

AE1

AE4
AE8

AE11

AE14
AE16

B24

AE19

AE23
AE26

A2
AF6

AF8

AF11
AF13

AF16

AF19

C5

AF21

A25

AF25

B1

C8

C11

C14

A11

C16

C19

C2
C22

C25

D1

D4

D8

D11

D13

A14

D16
D19

D23

D26

E3

E6

E8

E11
E14

E16

A16

E19

E21
E24

F5

F8

F11

F13
F16

F19

F2

A19

F22

F25

G4

G1

G23

G26

H3

H6

H21

H24

A23

J2

J5

J22

J25

K1

K4

K23
K26

L3

L6

AF2

L21

L24

M2

M5

M22
M25

N1

N4

N23

N26

B6

P3

P6

P21
P24

R2

R5
R22

R25
T1

T4

B8

T23
T26

U3
U6

U21
U24

V2

V5

V22
V25

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

CPU Power & Ground

051-7656

31

11

123

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

=PPVCORE_S0_CPU

61 13

45

12

45

12

10

12

11

8

12

11

8

6

8

8

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF

CPU VCORE HF AND BULK DECOUPLING

4x 330uF, 20x 22uF 0805

1x 470uF, 6x 0.1uF 0402

VCCP (CPU I/O) DECOUPLING

X5R-CERM

20%

22UF

6.3V

CRITICAL

603

C1206

1

2

CRITICAL

2.5V

D2T

20%

470UF

POLY

C1235

1

2 3

20%

22UF

6.3V

CRITICAL

603

X5R-CERM

C1204

1

2

CRITICAL

X5R-CERM

6.3V

20%

22UF

603

C1216

1

2

X5R-CERM

20%

6.3V

CRITICAL

603

22UF

C1214

1

2

X5R-CERM

20%

22UF

6.3V

CRITICAL

603

C1208

1

2

22UF

X5R-CERM

6.3V

20%

CRITICAL

603

C1203

1

2

X5R-CERM

20%

22UF

6.3V

CRITICAL

603

C1207

1

2

X5R-CERM

20%

22UF

6.3V

CRITICAL

603

C1202

1

2

6.3V

CRITICAL

22UF

20%

603

X5R-CERM

C1201

1

2

22UF

X5R-CERM

6.3V

20%

603

CRITICAL

C1213

1

2

X5R-CERM

20%

22UF

6.3V

CRITICAL

603

C1212

1

2

20%

22UF

6.3V
X5R-CERM

CRITICAL

603

C1211

1

2

X5R-CERM

22UF

20%

6.3V

CRITICAL

603

C1219

1

2

X5R-CERM
603

CRITICAL

6.3V

20%

22UF

C1200

1

2

X5R-CERM

CRITICAL

6.3V

20%

22UF

603

C1210

1

2

20%

0.1UF

CERM
402

10V

C1236

1

2

20%

6.3V

603

X5R-CERM

22UF

CRITICAL

C1205

1

2

X5R-CERM

22UF

6.3V

CRITICAL

20%

603

C1209

1

2

22UF

X5R-CERM

20%

6.3V

CRITICAL

603

C1215

1

2

22UF

20%

CRITICAL

603

X5R-CERM

6.3V

C1217

1

2

20%
CERM

402

0.1UF

10V

C1237

1

2

20%
CERM

402

0.1UF

10V

C1238

1

2

20%
CERM

402

0.1UF

10V

C1239

1

2

20%
CERM

402

0.1UF

10V

C1240

1

2

20%
CERM

402

0.1UF

10V

C1241

1

2

20%

22UF

6.3V

CRITICAL

603

X5R-CERM

C1218

1

2

PLACEMENT_NOTE=Place near CPU pin B26.

CERM
402

16V

10%

0.01UF

C1281

1

2

X5R

6.3V

20%

10uF

603

C1280

1

2

20%

D2T-SM2

POLY-TANT

2.0V

330UF

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

C1250

1

2 3

20%

D2T-SM2

POLY-TANT

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

330UF

2.0V

C1251

1

2 3

20%

POLY-TANT

CRITICAL

330UF

2.0V

PLACEMENT_NOTE=Place in CPU center cavity.

D2T-SM2

C1252

1

2 3

PLACEMENT_NOTE=Place in CPU center cavity.

20%

D2T-SM2

POLY-TANT

CRITICAL

330UF

2.0V

C1253

1

2 3

CPU Decoupling & VID

SYNC_MASTER=M98_MLB

123

12

31

SYNC_DATE=04/01/2008

051-7656

=PPVCORE_S0_CPU

=PP1V5_S0_CPU

=PP1V05_S0_CPU

61 13 11

45

10

11

11

8

8

8

6

Preliminary

IN

BI

BI

BI
BI

OUT

IN

BI

IN

IN
IN

OUT

OUT
OUT

BI
BI

BI
BI

BI
BI

BI
BI

OUT

IN

IN
IN

IN
OUT
OUT
OUT

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TCK0

OBSDATA_A3

OBSDATA_A1

OBSFN_C0

OBSDATA_C0
OBSDATA_C1

OBSDATA_C3

Mini-XDP Connector

VCC_OBS_CD

DBR#/HOOK7

Please avoid any obstructions
on even-numbered side of J1300

NOTE: This is not the standard XDP pinout.

VCC_OBS_AB

TDO

TDI

RESET#/HOOK6

OBSFN_D0

SCL

SDA

TRSTn

HOOK3

HOOK2

HOOK1

TMS

OBSDATA_D0

TCK1

OBSDATA_B2

PWRGD/HOOK0

OBSFN_D1

OBSDATA_B3

XDP_PRESENT#

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSFN_B0

OBSDATA_C2

OBSFN_C1

Direction of XDP module

998-1571

ITPCLK#/HOOK5

ITPCLK/HOOK4

OBSDATA_D3

OBSDATA_D2

OBSDATA_D1OBSDATA_B1

OBSDATA_B0

OBSFN_B1

OBSDATA_A2

OBSDATA_A0

OBSFN_A1

OBSFN_A0

Use with 920-0620 adapter board to support CPU, MCP debugging.

MCP79-specific pinout

10 14 88

1K

402

MF-LF

XDP

5%

1/16W

R1399

1 2

7

21 44 91

7

21 44 91

54.9

MF-LF

1/16W

1%

402

XDP

R1315

1

2

402

0.1uF

XDP

16V

10%

X5R

C1300

1

2

X5R

10%

0.1uF

XDP

16V

402

C1301

1

2

10 88

10 88

6

10 88

9

10 14 88

XDP

402

MF-LF

1/16W

5%

1K

PLACEMENT_NOTE=Place close to CPU to minimize stub.

R1303

1 2

10 88

10 88

10 88

10 88

6

21

6

21

6

21

19 91

19 91

19 91

19 91

19 91

19 91

19 91

19 91

6

21

6

14 88

14 88

6

6

10 88

6

10 88

6

10 88

10 25

19

F-ST-SM

LTH-030-01-G-D-NOPEGS

CRITICAL
XDP_CONN

J1300

1

10

1112

1314

1516

1718

19

2

20

2122

2324

2526

2728

29

3

30

3132

3334

3536

3738

39

4

40

4142

4344

4546

4748

49

5

50

5152

5354

5556

5758

59

6

60

78

9

SYNC_DATE=04/01/2008

051-7656

SYNC_MASTER=M98_MLB

13

31

123

eXtended Debug Port(MiniXDP)

TP_XDP_OBSFN_B0

XDP_BPM_L<3>

=PP3V3_S0_XDP
=PP1V05_S0_CPU

TP_XDP_OBSDATA_B2

MCP_DEBUG<2>

JTAG_MCP_TDI

MCP_DEBUG<4>

MCP_DEBUG<6>
MCP_DEBUG<7>

XDP_CPURST_L
XDP_DBRESET_L

MCP_DEBUG<0>

XDP_TCK

SMBUS_MCP_0_DATA
SMBUS_MCP_0_CLK

JTAG_MCP_TCK

PM_LATRIGGER_L

XDP_OBS20

TP_XDP_OBSDATA_B3

XDP_PWRGD

TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1

TP_XDP_OBSFN_B1

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<4>

XDP_BPM_L<5>

JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L

MCP_DEBUG<1>

MCP_DEBUG<3>

JTAG_MCP_TMS

MCP_DEBUG<5>

FSB_CLK_ITP_P
FSB_CLK_ITP_N

XDP_TDI

XDP_TRST_L

XDP_TDO_CONN

XDP_TMS

CPU_PWRGD

FSB_CPURST_L

61 12 11 10

8 8 6

6

7

88

7

Preliminary

IN
IN
IN

IN

OUT

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI
BI

BI

BI

BI

IN

BI

OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT

OUT
OUT

IN

BI
BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28#
CPU_A29#
CPU_A30#
CPU_A31#
CPU_A32#

CPU_A22#
CPU_A23#
CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2#
CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6#
CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15#
CPU_A16#

CPU_A19#

CPU_A17#
CPU_A18#

CPU_A20#
CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT#
CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0#
CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4#
CPU_D5#
CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17#
CPU_D18#

CPU_D16#

CPU_D19#
CPU_D20#
CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39#
CPU_D40#
CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#

CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P
BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK#
CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD
+V_PLL_MCLK
+V_PLL_FSB
+V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY#
CPU_DRDY#

CPU_REQ1#

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

270 mA (A01)

206 mA

15 mA

29 mA

20 mA

(MCP_BSEL<0>)

(MCP_BSEL<1>)

(MCP_BSEL<2>)

Loop-back clock for delay matching.

9

9

9

10 88

9

10 13 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

10 88

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

10 88

9

10 88

7

10 88

7

10 88

7

10 88

7

10 88

7

10 88

10 88

10 88

10 88

10 88

10 88

10 88

13 88

13 88

10 88

10 88

10 88

10 88

10 88

9

10 88

9

10 88

10 88

10 13 88

10 88

10 88

10 88

10 88

9

10 61 88

9

10 42 61 88

10 42 88

10 88

10 88

49.9

1/16W

1%

402

MF-LF

R1436

1

2

1/16W

1%

402

MF-LF

49.9

R1431

1

2

49.9

MF-LF

402

1%

1/16W

R1430

1

2

49.9

1/16W

1%

402

MF-LF

R1435

1

2

NO STUFF

1K

402

5%
1/16W
MF-LF

R1422

1

2

1K

NO STUFF

402

MF-LF

5%

1/16W

R1421

1

2

1K

5%

402

MF-LF

NO STUFF

1/16W

R1420

1

2

1/16W

402

MF-LF

62

5%

R1415

1

2

1/16W

402

MF-LF

54.9

1%

R1410

1

2

NO STUFF

150

1/16W

402

MF-LF

5%

R1440

1

2

OMIT

MCP79-TOPO-B

(1 OF 11)

BGA

U1400

AK41

AJ40

G41

G42

AL42

AL43

AK42

AL41

AM40

AM39

AF35

AG35

AG39
AE33

AG37
AG38

AG34

AN38
AL39

AG33

AL33

AF41

AJ33

AN36

AJ35
AJ37

AJ36
AJ38

AL37

AL34
AN37

AC34

AJ34

AL38
AL35

AN34

AR39
AN35

AE38

AE34

AC37
AE37

AE35

AB35

AD42

AE36

AK35

AD43

AA41

AE40

AL32

F41

D42

F42

AM42

AM43

Y43

W42

R42
T39

T42
T41

R41

T43
W35

AA37

W33
W34

Y40

AA36

AA34
AA38

AA35
U38

U36

U35
U33

U34

W38

W41

R33

U37

N34
N33

R34
R35

P35

R39
R37

R38

Y39

L37
L39

L38

N36
N38

J39
J38

J37

L42
M42

V42

P41

N41
N40

M40

H40
K42

H41
L41

H43

H42

Y41

K41

J40

H39
M43

Y42
P42

U41

V41

V35

N35

J41

AD39

AA40

AN32

AN33
AM32

AD41

U40

W37

L36

M41

T40

W39

N37

M39

AH40

AB42
AD40

AH39

AH42
AF42

AC43

AG41

E41

AJ41

AH43

AC38

AA33
AC39

AC33

AC35

H38

AC41
AB41

AC42

AM33

AH41

AG42

AG43

AE41

AG27

AH28

AG28

AH27

1/16W

402

MF-LF

62

5%

R1416

1

2

31

SYNC_DATE=06/06/2008

MCP CPU Interface

051-7656

123

14

SYNC_MASTER=T18_MLB

=MCP_BSEL<1>
=MCP_BSEL<0>

=MCP_BSEL<2>

=PP1V05_S0_MCP_FSB

FSB_BREQ1_L

FSB_ADS_L

FSB_BREQ0_L

CPU_FERR_L

FSB_RS_L<0>

FSB_BNR_L

FSB_DRDY_L

FSB_DBSY_L

FSB_A_L<33>
FSB_A_L<34>

FSB_A_L<25>

FSB_A_L<10>

FSB_D_L<7>

FSB_D_L<14>

PP1V05_S0_MCP_PLL_FSB

=PP1V05_S0_MCP_FSB

FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>
FSB_DINV_L<0>

FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>
FSB_DINV_L<1>

FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>
FSB_DINV_L<2>

FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>
FSB_DINV_L<3>

FSB_A_L<3>
FSB_A_L<4>
FSB_A_L<5>
FSB_A_L<6>
FSB_A_L<7>
FSB_A_L<8>
FSB_A_L<9>

FSB_A_L<11>
FSB_A_L<12>
FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>

FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>

FSB_A_L<35>

FSB_ADSTB_L<0>
FSB_ADSTB_L<1>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_TRDY_L

CPU_PECI_MCP
CPU_PROCHOT_L

FSB_RS_L<1>
FSB_RS_L<2>

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>

FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>

FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>

FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>

FSB_D_L<44>

FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_BPRI_L
FSB_DEFER_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_CLK_ITP_P
FSB_CLK_ITP_N

FSB_CLK_MCP_N

FSB_CLK_MCP_P

CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L

CPU_PWRGD
FSB_CPURST_L

FSB_CPUSLP_L

CPU_STPCLK_L
CPU_DPRSTP_L

FSB_D_L<45>

FSB_D_L<43>

FSB_D_L<38>

CPU_DPSLP_L
FSB_DPWR_L

MCP_BCLK_VML_COMP_GND

FSB_D_L<13>

PM_THRMTRIP_L

23

23

22

22

14

14 9 9

8

88

23

8

88

88

88

88

88

88

Preliminary

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1
MCKE0A_0

MODT0A_1
MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8
MA0_7

MA0_9

MA0_10

MA0_11

MA0_13
MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P
MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2
MDQM0_1
MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4
MDQ0_3
MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9
MDQ0_8
MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12

MDQ0_16

MDQ0_21
MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22

MDQ0_26

MDQ0_29
MDQ0_28
MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35
MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40
MDQ0_39

MDQ0_42

MDQ0_47
MDQ0_46

MDQ0_43

MDQ0_45
MDQ0_44

MDQ0_51
MDQ0_50
MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55
MDQ0_54
MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61
MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT

BI

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI
BI

BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60
MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56
MDQ1_55
MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51
MDQ1_50

MDQ1_48
MDQ1_47
MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42
MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36
MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31
MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11
MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6
MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4
MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N
MDQS1_0_P
MDQS1_0_N

MRAS1#
MCAS1#

MWE1#

MBA1_2
MBA1_1
MBA1_0

MA1_14
MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1#
MCS1A_0#

MCLK1A_0_N

MODT1A_1
MODT1A_0

MCKE1A_0

MCKE1A_1

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

OUT

BI

OUT
OUT
OUT
OUT
OUT
OUT
OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BGA

MCP79-TOPO-B

OMIT

(2 OF 11)

U1400

AR19

AT19

AN19

AW21

AN23

AU15

AR23

AU19

AV19

AN21

AR21

AP21

AU21

AR22

AV21

AW17

AP19

AP23

AP17

AT23

AU23

BC20

BB20

AY24

BA24

AV33

AW33

AR18

AT15

AP35

AR35

AV31

AT31

AW37

AV37

AR33

AU31

AN31

AV29

AN29

AV27

AW38

AR31

AP31

AR29

AP29

AR27

AP27

AR25

AP25

AU27

AT27

AV38

AU25

AR26

AU13

AR14

AT11

AR11

AW13

AV13

AV11

AU11

AR38

AV9

AU9

AY5

AW6

AP11

AW9

AU8

AU7

AV5

AU6

AR37

AR5

AN10

AW5

AV6

AR7

AR6

AN7

AN6

AL7

AL6

AV39

AN9

AP9

AL9

AL8

AW39

AU37

AT37

AR34

AV35

AW29

AN27

AN13

AR10

AU5

AN5

AT39

AU39

AU35

AT35

AU29

AU30

AW25

AV25

AR13

AP13

AW8

AW7

AR9

AR8

AL11

AL10

AV15

AP15

AV17

AR17

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

27 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

BGA

MCP79-TOPO-B

OMIT

(3 OF 11)

U1400

BA18

BB25

BA17

BC28

AW28

BA14

BA29

BA25

BB26

BA26

BA27

AY27

BA28

AY28

BB28

BB17

BB18

BB29

BA15

BB30

AY31

AY19

BA19

BA22

BB22

BB42

BA42

BB16

BB14

AP42

AR41

BC40

BA40

AV41

AV42

AW40

BB40

AY39

BA38

BB36

BA36

AU41

AY40

BA39

AW36

BC36

AY35

BA34

BB32

BA32

AY36

BA35

AU40

AW32

BC32

BA12

AY12

BB9

BB8

AW12

BB12

BB10

BA9

AN40

AY8

BA7

BC4

BB4

BC8

BA8

BA5

BB5

BB2

BA3

AP41

AW3

AW4

BC3

BB3

AY3

AY4

AU3

AU2

AR3

AR4

AT41

AV3

AV2

AT3

AT4

AT40

AW41

AW42

AR42

AY43

BB38

BB34

BA11

AY7

BA2

AT5

AT43

AT42

AY42

BA43

BA37

BB37

BA33

BB33

AY11

BA10

BA6

BB6

AY1

AY2

AT1

AT2

AY15

BB13

AW16

BA16

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

28 89

123

051-7656

31

15

SYNC_MASTER=T18_MLB

SYNC_DATE=06/06/2008

MCP Memory Interface

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>

MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>

TP_MEM_A_CLK2P
TP_MEM_A_CLK2N

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CKE<0>

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>

MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

TP_MEM_B_CLK2P
TP_MEM_B_CLK2N

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_ODT<1>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>

MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>

7

7

7

Preliminary

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55
GND56
GND57
GND58

GND60

GND59

GND61
GND62
GND63
GND64

GND52
GND53
GND54

GND51

GND49
GND50

GND48

GND47

GND46

GND44
GND45

GND43

GND42

GND41

GND39
GND40

GND38

GND37

GND36

GND35

GND33
GND34

GND32

GND31

GND30

GND28
GND29

GND27

GND26

GND25

GND24

GND18
GND19

GND17

GND16

GND15

GND13
GND14

GND10

GND12

GND11

GND8
GND9

GND7

GND6

GND5

GND2
GND3
GND4

GND1

MEM_COMP_VDD
MEM_COMP_GND

MODT0B_0
MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0#
MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE
+V_VPLL

+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8

+VDD_MEM9
+VDD_MEM10
+VDD_MEM11

+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34

+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41

+VDD_MEM43
+VDD_MEM44
+VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22
GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

87 mA (A01)

39 mA

TP or NC for DDR2.

19 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

12 mA

17 mA

4771 mA (A01, DDR3)

1%

40.2

1/16W

402

MF-LF

R1610

1

2

MF-LF

402

1%

1/16W

40.2

R1611

1

2

(4 OF 11)

MCP79-TOPO-B

OMIT

BGA

U1400

AA22

AA39

AB22

AB7

AD22

AE20
AF24

AG24
AH35

AK7

AM28

AP12

AT25

AP30

AR36
AU10

F28

BC21

AY9

BC9
D34

F24

G30

G32
H31

K7

M38

M5

M6

M7
M9

N39

N8

P10

P33

P34
P37

P4

P40

P7

R36

R40
R43

R5

T10

T18

T20

AK11

T24

T26

T33

T34

T35
T37

T38

T6

T7

T9

U18
U20

U22

V10

V34

W5

AV23

AN25

BA30

BA31

BB21

BA21

BC24

BB24

AU34

AU33

AY20

BA20

BA23

AY23

BB41

BA41

AU17
AR15

BC16
BA13

AM41

AN41

AN17

AN15

AY16

BC13

AY32

U27

U28

T27

T28

AM17

AN20
AN24

AT17

AP16
AN22

AP20

AP24
AV16

AR16
AR20

AM19

AR24

AW15
AP22

AP18

AU16
AN18

AU24

AT21
AY29

AV24

AM21

AU20

AU22

AW27
BC17

AV20

AY17
AY18

AM15

AU18
AY25

AM23

AY26
AW19

AW24

BC25
AL30

AM31

AM25
AM27

AM29
AN16

BC29

29

MCP Memory Misc

16

123

31

051-7656

SYNC_DATE=06/06/2008

SYNC_MASTER=T18_MLB

MCP_MEM_COMP_VDD

=PP1V8R1V5_S0_MCP_MEM

TP_MEM_B_ODT<3>

TP_MEM_B_ODT<2>

TP_MEM_B_CS_L<3>

TP_MEM_B_CLK3N

TP_MEM_B_CLK3P

TP_MEM_B_CLK4N

TP_MEM_B_CLK4P

TP_MEM_B_CLK5N

TP_MEM_B_CLK5P

PP1V05_S0_MCP_PLL_CORE

TP_MEM_A_CS_L<3>

TP_MEM_A_CS_L<2>

TP_MEM_A_CLK3N

TP_MEM_A_CLK4P

TP_MEM_A_CLK5N

TP_MEM_A_CLK5P

TP_MEM_A_CKE<3>

TP_MEM_A_CKE<2>

TP_MEM_A_ODT<3>

TP_MEM_A_ODT<2>

TP_MEM_A_CLK3P

TP_MEM_A_CLK4N

MCP_MEM_COMP_GND

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_RESET_L

TP_MEM_B_CS_L<2>

TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>

23

23

16

16

89

8

7

7

7

7

7

7

7

7

7

23

7

7

7

7

7

7

7

7

7

7

7

7

89

8

7

7

Preliminary

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7
+AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N
PE0_TX15_P

PE0_TX13_N
PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N
PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N
PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P
PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16
PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17
PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18
PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN
IN

OUT

OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN

OUT

OUT

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Minimum 1.025V for Gen2 supportMinimum 1.025V for Gen2 support

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

84 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Int PU

206 mA (A01, AVDD0 & 1)

57 mA (A01, DVDD0 & 1)

Int PU (S5)

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

Int PU

MCP79-TOPO-B

(5 OF 11)

OMIT

BGA

U1400

Y12

AC12
AD12

V12

W12

AA12
AB12

M12
P12

R12

N12
T12

U12

M13
N13

P13

T17

W19
U17

V19
W16

W17

W18
U16

T19
U19

T16

C9

D11

E11

E7

F7

L8

L9

L6

L7

N10

N11

P9

N9

N6

N7

N4

N5

C7

D7

F6

E6

F5

E5

E3

E4

D3

C3

H5

G5

J6

J7

J4

J5

L10

L11

D4

C5

J1

H1

J3

J2

K3

K2

L3

L4

M3

M4

M1

M2

B4

C4

A3

A4

B2

B3

D1

C1

E1

D2

F2

E2

F4

F3

H4

G3

H2

H3

F11

G11

J9

K9

G9

H9

E9

F9

G7

H7

C8

D8

A8

B8

B7

A7

C6

B6

J10

J11

F13

G13

H13

J13

K14

L14

M14

N14

F17

D5
D9

E8

C10

M15
B10

L16
L18

M16

M18

M17

M19

A11

K11

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

69 90

69 90

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

7

30 90

7

30 90

9

35

7

30 31

35 90

35 90

7

31 90

7

31 90

30

30

31

31

30 90

30 90

35 90

35 90

35 90

35 90

31 90

31 90

30 90

30 90

31 90

31 90

9

2.37K

402

MF-LF

1%
1/16W

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

R1710

1

2

25

84

9

58

SYNC_MASTER=T18_MLB

MCP PCIe Interfaces

17

123

31

051-7656

SYNC_DATE=06/06/2008

PCIE_FW_PRSNT_L

PCIE_MINI_D2R_P

PCIE_FW_D2R_P
PCIE_FW_D2R_N

PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N

=PP1V05_S0_MCP_PEX_AVDD1

TP_MCP_GPIO_18

MINI_CLKREQ_L

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_DVDD0

=PEG_D2R_P<0>

=PEG_D2R_N<2>

PP1V05_S0_MCP_PLL_PEX

=PEG_D2R_N<0>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

=PEG_D2R_P<6>

PCIE_MINI_PRSNT_L

TP_PCIE_PE4_R2D_CN

TP_PCIE_PE4_R2D_CP

PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P

TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PEG_CLK100M_N

PEG_CLK100M_P

PCIE_CLK100M_MINI_P

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>

=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<13>

=PEG_R2D_C_N<11>

=PEG_R2D_C_P<11>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<6>

=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>

=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<0>

MCP_PEX_CLK_COMP

TP_PCIE_PE4_D2RN

TP_PCIE_PE4_D2RP

PCIE_MINI_D2R_N

PCIE_WAKE_L

PEG_PRSNT_L

=PEG_D2R_N<13>
=PEG_D2R_P<14>

=PEG_D2R_P<15>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<13>

=PEG_D2R_N<11>

=PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_P<8>

=PEG_D2R_P<9>

=PEG_D2R_P<10>

=PEG_D2R_N<8>

=PEG_D2R_N<9>

=PEG_D2R_N<5>

=PEG_D2R_P<7>

=PEG_D2R_N<6>

=PEG_D2R_N<7>

=PEG_D2R_P<3>

=PEG_D2R_P<5>

=PEG_D2R_N<3>

=PEG_D2R_N<4>

=PEG_D2R_P<1>
=PEG_D2R_N<1>

FW_CLKREQ_L

PCIE_CLK100M_EXCARD_P

EXCARD_CLKREQ_L

GMUX_JTAG_TCK_L

=PEG_D2R_N<14>

=PEG_D2R_N<15>

GMUX_JTAG_TDO

TP_PE4_PRSNT_L

PCIE_EXCARD_PRSNT_L

TP_PE4_CLKREQ_L

AUD_IP_PERIPHERAL_DET

8

7

8

8

8

23

7

7

7

7

7

90

7

7

7

Preliminary

IN

BI

OUT

IN
IN
IN
IN

IN
IN

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

IN
IN

OUT
OUT

OUT
OUT
OUT

OUT
OUT

IN

IN
OUT

IN
IN
IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P
HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P
HDMI_TXD0_N/ML0_LANE2_N
HDMI_TXD1_P/ML0_LANE1_P
HDMI_TXD1_N/ML0_LANE1_N
HDMI_TXD2_P/ML0_LANE0_P
HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET
RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P
DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET
HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC
RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P
IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P
IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P
IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36
MII_COL/GPIO_20/MSMB_DATA
MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

OUT
OUT

OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT

OUT

BI

OUT

BI

OUT

OUT

OUT

OUT
OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

190 mA (A01, 1.8V)

C / Pr

MCP79 requires a S5 pull-up.

Comp / Pb

206 mA (A01)

103 mA

103 mA

Okay to float XTALIN_TV and XTALOUT_TV.

Okay to float all RGB_DAC signals.
DDC_CLK0/DDC_DATA0 pull-ups still required.

Y / Y

TV DAC Disable:

Okay to float all TV_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

ENET_TXD<0>

1

0MII

RGMII

Interface

Network Interface Select

NOTE: All Apple products set strap to

feature via software. This
avoids a leakage issue since

RGB ONLY

5 mA (A01)

DisplayPort

DP_IG_ML_P/N<3>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<2>

DP_IG_DDC_CLK

TP_DP_IG_AUX_CHP/N

TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<0>

TMDS_IG_TXC_P/N

TMDS/HDMI

=MCP_HDMI_TXC_P/N
=MCP_HDMI_TXD_P/N<0>

MCP Signal

=MCP_HDMI_DDC_CLK

=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_DDC_DATA

TMDS_IG_HPD

=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N

8 mA
8 mA

16 mA (A01)

95 mA (A01)

LVDS: Power +VDD_IFPx at 1.8V

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

TV / Component

RGB DAC Disable:

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

MII, RGMII products will enable

83 mA (A01)

131 mA (A01)

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

DP_IG_AUX_CH_P/N

DP_IG_HPD

DP_IG_DDC_DATA

DP_IG_ML_P/N<0>

Interface Mode

be used to provide HDMI or dual-channel TMDS without

NOTE: HDMI port requires level-shifting. IFP interface can

level-shifters.

NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

(See below)

(See below)

Alias to DVI_HPD for systems using IFP for DVI.

=DVI_HPD_GMUX_INT:

Pull-down (20k) required in all cases.

Alias to HPLUG_DET2 for other systems.

Alias to GMUX_INT for systems with GMUX.

pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.

GPIOs 57-59 (if LCD panel is used):

In MCP79 these pins have undocumented internal

23

32 92

33 92

32 92

32 92

32 92

32 92

32 92

32 92

32 92

24 90

24 90

9

9

9

9

9

9

9

9

9

9

9

81 90

81 90

9

9

24 90

24 90

24 90

24 90

24 90

24 90

24 90

1%
1/16W
MF-LF

402

49.9

R1810

1

2

1/16W
MF-LF

49.9

402

1%

R1811

1

2

81

24

24

9

9

9

(6 OF 11)

BGA

MCP79-TOPO-B

OMIT

U1400

E23

B31

C30

D31

A31

B30

E31

C43

D43

E16

B15

J31

E35

D35

F35

G35

G33

F33

H33

J33

J30

C31
F31

C35

B35

A32

B32

C32

D32

C33

D33

C34

B34

E32

G31

K31

L31

H29

J29

K29

L29

K30

L30

M30

N30

G39

E37
F40

B26

B27

C27

B22

J23

F23

E28

J24

K24

T23

U23

V23

M29

M28

J32

K32

T25

M27
M26

B40

A39

A40

B39

C39

B38

A41

J22

D21

C21

G23

A23

C22

C23

B23

E24
A24

D24
C26

B24

C24
C25

D25

C36

B36

D36

A36

E36
A35

C37

C38

D38

10K

402

1/16W

5%

MF-LF

R1850

1

2

402

5%

100K

1/16W
MF-LF

R1861

1

2

402

MF-LF

5%

1/16W

100K

R1860

1

2

7

43

5%

47K

402

MF-LF

1/16W

R1820

1

2

32 92

84 90

84 90

84 90

84 90

84 90

32 92

84 90

84 90

84 90

9

90

9

90

9

90

9

90

84 90

84 90

84 90

32 92

84 90

84 90

84 90

9

90

9

90

81

81

9

9

24 90

32 92

24 90

32 92

32 92

32 92

18

123

31

051-7656

SYNC_DATE=06/06/2008

SYNC_MASTER=T18_MLB

MCP Ethernet & Graphics

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_N<3>

MCP_HDMI_RSET
MCP_HDMI_VPROBE

DP_IG_CA_DET

PP1V05_ENET_MCP_PLL_MAC

=PP1V05_S0_MCP_HDMI_VDD

PP3V3_S0_MCP_VPLL

=PP3V3R1V8_S0_MCP_IFP_VDD

PP3V3_S0_MCP_DAC

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_N<2>

MCP_CLK27M_XTALIN

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

MCP_TV_DAC_VREF

DP_IG_AUX_CH_P
DP_IG_AUX_CH_N

=MCP_HDMI_HPD

ENET_MDIO

MCP_CLK25M_BUF0_R

MCP_DDC_DATA0

MCP_DDC_CLK0

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR
CRT_IG_G_Y_Y

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<2>

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

=MCP_HDMI_DDC_DATA

=MCP_HDMI_DDC_CLK

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

MCP_TV_DAC_RSET

ENET_RXD<0>

TP_ENET_INTR_L

ENET_RXD<3>

ENET_RX_CTRL

ENET_CLK125M_RXCLK

ENET_RXD<2>

ENET_RXD<1>

ENET_RESET_L

ENET_MDC

TP_ENET_PWRDWN_L

=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS

CRT_IG_B_COMP_PB

CRT_IG_HSYNC
CRT_IG_VSYNC

MCP_MII_VREF

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S5_MCP_GPIO

=PP1V05_ENET_MCP_RMGT

LPCPLUS_GPIO

TP_MCP_RGB_DAC_VREF

TP_MCP_RGB_DAC_RSET

MCP_CLK27M_XTALOUT

LVDS_IG_BKL_PWM

=DVI_HPD_GMUX_INT

23

21

23

24

24

18

19

18

20

23

23

8

24

8

24

92

92

24

24

24

24

24

7

7

8

8

8

8

8

24

24

Preliminary

OUT

OUT

BI
BI
BI
BI

LPC PCIGND

PCI_INTW#
PCI_INTX#
PCI_INTY#
PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0#
LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5
PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10
PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15
PCI_AD16
PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21
PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66
GND67

GND69

GND68

GND70
GND71
GND72

GND74

GND73

GND75
GND76
GND77

GND79

GND78

GND80
GND81

GND84

GND83

GND82

GND85
GND86
GND87

GND89

GND88

GND90
GND91
GND92

GND94

GND93

GND95
GND96
GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR#
PCI_STOP#

PCI_RESET0#
PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105
GND106
GND107

GND109

GND108

GND110
GND111
GND112

GND115

GND114

GND113

GND116
GND117

GND120

GND119

GND118

GND121
GND122
GND123

GND125

GND124

GND126
GND127
GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS#
PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0#
PCI_REQ1#/FANRPM2

IN

BI

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI

OUT

OUT
OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU
Int PU
Int PU

Int PU (S5)

7

41 43 84 91

25 84 91

7

41 43 84 91

7

41 43 84 91

7

41 43 84 91

7

41 43 84 91

BGA

(7 OF 11)

MCP79-TOPO-B

OMIT

U1400

AB18
H34

AB20
AB21

AB23

AB24
AB25

AB26

AB27
AB28

AB34

AB37
AB4

AB40
AC22

AC36

AC40
AB33

AC5

AD16
AD17

AD18

AD19
AD20

AD24
AD25

AD26

AD27
AD28

AD33

AD34

U24

U26

U39

U4

U8
V16

V17

V18
V20

V22

V24
V26

V27

V28
V33

V37

V4

V40

V7
W20

W22

W24
W36

W40

W43
Y16

Y17
Y18

Y19

Y20
Y22

Y24

Y25

Y26

Y27

AD3
AD2

AD1
AD5

AE9

AE1

AE2

AD4
AE12

AE5

AE6

AC3

AE10

AC9

AC10
AC11

AA1

AA5

Y5

W3

W6

W4

W7

AC4

V3

W8

V2

W9

U3

W11

U2

U5

U1

U6

AE11

T5

U7

AB3

AC6

AB2
AC7

AC8
AA2

AA3
AA6

AA11

W10

R6
R7

R8

R9

AD11

AA9

Y4

R3

U10
R4

U11
P3

P2

N3

N2

N1

AA10

Y1
AB9

T1

T2

V9

T3

U9

T4

R10

R11

AA7

Y2

Y3

7

41 43

7

41 43 25 91

7

41 43

PLACEMENT_NOTE=Place close to pin R8

MF-LF
402

1/16W

5%

22

R1910

1

2

402

MF-LF1/16W

5%

8.2K

R1989

1 2

402

MF-LF1/16W

5%

8.2K

R1991

1 2

402

MF-LF1/16W

5%

8.2K

R1990

1 2

402

MF-LF1/16W

5%

8.2K

R1994

1 2

8.2K

5%

1/16W MF-LF

402

R1992

1 2

19

MF-LF
402

1/16W

5%

10K

R1961

1

2

1/16W MF-LF

402

22

5%

R1960

1 2

5%

1/16W MF-LF22402

R1950

1 2

5%

1/16W MF-LF22402

R1951

1 2

22

5%

1/16W MF-LF

402

R1952

1 2

402

MF-LF1/16W

5%

22

R1953

1 2

25

35

19

19

13

13 91

13 91

13 91

13 91

13 91

13 91

13 91

13 91

9

58

9

9

051-7656

31

123

19

MCP PCI & LPC

SYNC_DATE=06/06/2008

SYNC_MASTER=T18_MLB

CRTMUX_SEL_TV_L

PCI_REQ1_L

PCI_REQ0_L

MCP_RS232_SOUT_L

LPC_AD<1>

LPC_AD<3>

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

TP_PCI_GNT0_L
TP_PCI_GNT1_L

MCP_RS232_SOUT_L

TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>

TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR

TP_PCI_SERR_L
TP_PCI_STOP_L

PM_LATRIGGER_L

TP_PCI_RESET1_L

TP_PCI_CLK0

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

LPC_CLK33M_SMC_R

LPC_FRAME_R_L

LPC_RESET_L

LPC_PWRDWN_L

PCI_CLK33M_MCP_R

TP_PCI_CLK1

PCI_CLK33M_MCP

MEM_VTT_EN_R

TP_PCI_PERR_L

TP_PCI_AD<9>

TP_PCI_AD<11>

TP_PCI_AD<10>

TP_PCI_AD<8>

PCI_REQ1_L

PCI_REQ0_L

TP_PCI_AD<15>

TP_PCI_INTY_L

TP_PCI_TRDY_L

TP_PCI_INTW_L

TP_PCI_AD<31>

TP_PCI_AD<30>

TP_PCI_AD<29>

TP_PCI_AD<28>

TP_PCI_AD<27>

TP_PCI_AD<26>

TP_PCI_AD<25>

TP_PCI_AD<24>

TP_PCI_AD<23>

TP_PCI_AD<22>

TP_PCI_AD<21>

TP_PCI_AD<20>

TP_PCI_AD<19>

TP_PCI_AD<18>

TP_PCI_AD<17>

TP_PCI_AD<16>

TP_PCI_AD<14>

TP_PCI_AD<13>

TP_PCI_AD<12>

CRTMUX_SEL_TV_L
AUD_IPHS_SWITCH_EN
MCP_RS232_SIN_L

MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>

MCP_RS232_SIN_L

=PP3V3_S0_MCP_GPIO

PM_CLKRUN_L

LPC_SERIRQ

TP_LPC_DRQ0_L

FW_PME_L

TP_PCI_INTZ_L

TP_PCI_INTX_L

GMUX_JTAG_TMS
GMUX_JTAG_TDI

21

91

91

91

91

18

19

19

19

19

7

7

7

7

7

7

7

7

7

7

7

7

7

7

43

91

7

91

7 7

7

7

7

19

19

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

19

8

7

7

7

Preliminary

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

IN
IN
IN
IN

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158
GND159

GND157

GND156

GND155

GND153
GND154

GND152

GND151

GND150

GND148
GND149

GND147

GND146

GND145

GND143
GND144

GND142

GND141

GND140

GND139

GND136

GND133
GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N
SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N
SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N
SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P
USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26
USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9

+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT
OUT

IN

IN

OUT
OUT

IN
IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Minimum 1.025V for Gen2 support

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

84 mA (A01)

43 mA (A01, DVDD0 & 1)

ExpressCard

Minimum 1.025V for Gen2 support

19 mA (A01)

External C

External B

IR

Bluetooth

Camera

External A

External D

AirPort (PCIe Mini-Card)

Geyser Trackpad/Keyboard

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

127 mA (A01, AVDD0 & 1)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

39 91

39 91

9

91

9

91

9

91

9

91

30 91

30 91

40 91

40 91

49 91

49 91

30 91

30 91

39 91

39 91

31 91

31 91

91 96 98

91 96 98

39

39

98

31 42

MF-LF

1%
1/16W

402

2.49K

R2010

1

2

806

MF-LF

1%

1/16W

402

R2060

1

2

5%

8.2K

MF-LF

1/16W

402

R2053

1

2

402

1/16W
MF-LF

5%

8.2K

R2052

1

2

5%

8.2K

1/16W

402

MF-LF

R2051

1

2

402

1/16W
MF-LF

5%

8.2K

R2050

1

2

(8 OF 11)

MCP79-TOPO-B

OMIT

BGA

U1400

AD35

AD37
AD38

AE22

AE24
AE39

AE4

AD6
AF16

AF17
AF18

AF20

AF22
AF26

AF27

AF28
AF33

AF34

AF37
AF40

AG18
AG20

AG22

AG26
AG36

AG40

AH18
AH20

AH22

AH24

AJ12

AN11
AK12

AK13

AL12
AM11

AM12
AN12

AL13

AN14

AL14

AM13
AM14

AF19
AG16

AG17

AG19

AH17
AH19

AE16

L28

AJ5

AJ4

AJ6

AJ7

AJ9
AK9

AJ10

AJ11

AJ2
AJ1

AJ3

AK2

AL4
AK3

AL3

AM4

AM2
AM3

AM1

AN1

AN3

AN2

AP2

AP3

E12

AE3

D29

C29

G25

F25

L23

K23

D28

C28

B28

A28

G29

F29

L27

K27

J27

J26

G27

F27

E27

D27

L25

K25

J25

H25

L21

K21
J21

H21

A27

38 90

38 90

38 90

38 90

38 90

38 90

38 90

38 90

SYNC_MASTER=T18_MLB

MCP SATA & USB

051-7656

31

123

20

SYNC_DATE=06/06/2008

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

SATA_HDD_D2R_N
SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

TP_SATA_C_D2RP

TP_SATA_C_D2RN

PP1V05_S0_MCP_PLL_SATA

USB_EXTA_OC_L

TP_USB_11N

TP_USB_11P

TP_USB_10P

USB_EXTC_N

USB_EXCARD_N

USB_EXTB_N

USB_EXTB_P

USB_BT_N

USB_BT_P

USB_TPAD_N

USB_TPAD_P

USB_IR_N

USB_IR_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTD_N

USB_EXTD_P

USB_MINI_N

USB_EXTA_N

USB_EXTA_P

MCP_SATA_TERMP

TP_SATA_F_D2RP

TP_SATA_F_D2RN

TP_SATA_F_R2D_CN

TP_SATA_E_D2RN

TP_SATA_D_R2D_CN

TP_SATA_C_R2D_CN

TP_SATA_C_R2D_CP

TP_MCP_SATALED_L

TP_SATA_D_D2RN

TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

USB_EXTC_P

USB_EXCARD_P

TP_SATA_D_D2RP

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD0

TP_SATA_F_R2D_CP

TP_SATA_D_R2D_CP

USB_EXTB_OC_L

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

EXCARD_OC_L

TP_USB_10N

USB_EXTC_OC_L

=PP3V3_S5_MCP_GPIO

USB_MINI_P

18

9

8

7

7

23

7

7

7

90

7

7

7

7

7

7

7

7

7

7

7

7

7

9

8

7

7

23

91

8

Preliminary

OUT

OUT

OUT

BI

BI

OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

IN
IN

OUT

IN

IN
IN
IN

OUT

HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK

HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

THERM_DIODE_N

EXT_SMI/GPIO_32#

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME#

KBRDRSTIN#

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_RESET#

HDA_SYNC

HDA_BITCLK

HDA_SDATA_OUT

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST#

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI
JTAG_TDO

RTC_RST#

PS_PWRGD

PWRGD_SB

INTRUDER#

LID#
LLB#

PWRBTN#
RSTBTN#

CPU_DPRSLPVR

SLP_S5#

SLP_S3#

HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA

HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK

A20GATE

GPIO_12/SUS_STAT#/ACCLMTR

HDA_SDATA_IN0

GPIO_1/PWRDN_OK/SPI_CS1

HDA_PULLDN_COMP

THERM_DIODE_P

SLP_RMGT#

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT#/GPIO_64

SPI_CS0/GPIO_10
SPI_CLK/GPIO_11

SPI_DI/GPIO_8
SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1
+V_DUAL_HDA2

+V_PLL_NV_H
+V_PLL_SP_SPREF

HDA

MISC

OUT

IN

IN

OUT

IN

IN

OUT

IN

OUT

OUT

IN

IN

IN

IN

IN
IN

IN

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(MGPIO2)

(MGPIO3)

Int PU (S5)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PU

Int PU

25 MHz

42 MHz 0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0

1

1

0

SPI_CLKSPI_DO

0

1

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

I/F

HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by
default, LPC+ debug card pulls

1

1

0

0

LPC_FRAME#

0

1

0

1

Int PU

Int PD

Int PD

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support
SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

(MXM_OK for MXM systems)

SAFE mode: For ROMSIP
recovery

USER mode: Normal

Connects to SMC for
automatic recovery.

43 91

7

33 36 41 67 82 84

39 41 42 67

7

13 44 91

44 91

7

13 44 91

44 91

21 64

47 96

21 64

21 64

21 30 33

47 96

9

61 88

41

53 91

9

91

53 91

53 91

53 91

MF-LF

1/16W

1%

402

49.9K

R2121

1

2

1%

49.9K

MF-LF

402

1/16W

R2120

1

2

1K

MF-LF

1%
1/16W

402

R2190

1

2

25 91

41

41

MF-LF

402

5%

22

1/16W

R2170

1 2

MF-LF

5%

1/16W

402

22

R2171

1 2

5%

22

MF-LF

1/16W

402

R2173

1 2

402

5%

10K

MF-LF

1/16W

R2163

1

2

MF-LF

8.2K

5%
1/16W

402

R2160

1

2

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

R2180

1

2

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

R2181

1

2

402

5%

22

1/16W
MF-LF

R2172

1 2

9

43

49.9

MF-LF

1/16W

1%

402

R2110

1

2

402

1/16W
MF-LF

5%

10K

R2150

1

2

6

13

6

13

6

13

6

13

6

10PF

50V

5%

402

CERM

C2171

1

2

50V

10PF

5%

402

CERM

C2173

1

2

50V

10PF

5%

402

CERM

C2170

1

2

50V

10PF

5%

402

CERM

C2172

1

2

BGA

(9 OF 11)

MCP79-TOPO-B

OMIT

U1400

K13

AE7

M22

C17 D17

C18

A12

C12

B12

D12

L26

L24

E15

K17

L17

A15

K15

G15

J14

J15

F15

L15

B20

G19

E19
F19

J19

J18

L13

M25

M24

L20

M20

M21

J16

K16

AE18

AE17

L22

E20

C16

D20

D16

C20

C19

J17

G17

H17

M23

L19

G21

K19

F21

D13

C14

C15

B14

C13

B18

K22

C11

B11

A16

A19

B16

B19

38

21 58

25 25

33 36 41 42

21 27 28 41

402

1/16W
MF-LF

5%

100K

R2147

1

2

10K

5%
1/16W

402

MF-LF

R2142

1

2

402

1/16W
MF-LF

5%

10K

R2141

1

2

22K

5%

MF-LF

1/16W

402

R2157

1

2

22K

5%

MF-LF

1/16W

402

R2156

1

2

402

1/16W

22K

5%

MF-LF

R2155

1

2

402

MF-LF

5%
1/16W

100K

R2151

1

2

1/16W
MF-LF

5%

100K

402

R2154

2

1

MF-LF
402

1/16W

5%

10K

R2143

1

2

10K

5%

MF-LF

1/16W

402

R2140

1

2

9

21 42

25

25

25

25

25

41

41

25

43 91

43 91

43 91

MCP HDA & MISC

SYNC_DATE=06/06/2008

SYNC_MASTER=T18_MLB

21

123

31

051-7656

MCP_SPKR

=PP3V3_S0_MCP

PM_SLP_S4_L

PM_SLP_S3_L

AUD_I2C_INT_L

HDA_SYNC_R

TP_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

SMC_ADAPTER_EN

SMC_IG_THROTTLE_L

MEM_EVENT_L

=PP3V3_S0_MCP_GPIO

SMC_WAKE_SCI_L

MEM_EVENT_L
ODD_PWR_EN_L

HDA_RST_R_L

HDA_SYNC

ARB_DETECT

SM_INTRUDER_L

PM_RSMRST_L

JTAG_MCP_TRST_L

MCP_TEST_MODE_EN

JTAG_MCP_TMS

MCP_VID<1>
MCP_VID<2>

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDOUT_R

HDA_SYNC_R

=PP3V3R1V5_S0_MCP_HDA

PP3V3_G3_RTC

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

TP_MCP_KBDRSTIN_L

PM_SYSRST_DEBOUNCE_L

MCP_THMDIODE_N

SMBUS_MCP_0_CLK

SPI_MOSI_R

SPI_MISO

PM_CLK32K_SUSCLK_R

JTAG_MCP_TCK

MCP_CLK25M_XTALIN
MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN
RTC_CLK32K_XTALOUT

SPI_CS0_R_L

PP1V05_S0_MCP_PLL_NV

MCP_HDA_PULLDN_COMP

TP_SB_A20GATE

PM_SLP_RMGT_L

MCP_VID<1>

SMC_RUNTIME_SCI_L

SPI_CLK_R

=SPI_CS1_R_L_USE_MLB

HDA_BIT_CLK_R

HDA_SDOUT_R

PM_BATLOW_L

SMBUS_MCP_0_DATA

MCP_VID<2>

AP_PWR_EN

SMBUS_MCP_1_DATA

JTAG_MCP_TDO

JTAG_MCP_TDI

MCP_PS_PWRGD

RTC_RST_L

PM_PWRBTN_L

TP_MCP_LID_L

SMBUS_MCP_1_CLK

MCP_THMDIODE_P

MCP_VID<0>

MCP_CPUVDD_EN

HDA_SDIN0

PM_DPRSLPVR

MCP_VID<0>

MCP_CPU_VLD

MCP_GPIO_4
AUD_I2C_INT_L

=PP3V3_S3_MCP_GPIO

AP_PWR_EN

MCP_GPIO_4

=PP3V3R1V5_S0_MCP_HDA

ARB_DETECT

TP_MCP_BUF_SIO_CLK

SMC_IG_THROTTLE_L

41

23

28

19

23

33

23

22

91

42

27

18

91

64

64

91

91

91

91

21

25

91

91

64

58

30

21

8

21

7

7

21

21

8

21

21

21

21

21

21

21

21

8

22

7

23

91

7

21

21

21

21

21

8

21

21

8

21

7

Preliminary

GND

GND161

GND165
GND166

GND164

GND163

GND162

GND167
GND168

GND171

GND170

GND169

GND172
GND173

GND176

GND175

GND174

GND177
GND178

GND181

GND180

GND179

GND182
GND183
GND184

GND187

GND186

GND185

GND188
GND189

GND192

GND191

GND190

GND193
GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206
GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213
GND214

GND217

GND216

GND215

GND218
GND219

GND222

GND221

GND220

GND223
GND224
GND225

GND228

GND227

GND226

GND229
GND230

GND233

GND232

GND231

GND234
GND235

GND238

GND237

GND236

GND239
GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331
GND332

GND330

GND329

GND328

GND326
GND327

GND325

GND324

GND323

GND321
GND322

GND320

GND319

GND318

GND316
GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305
GND306
GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285
GND286

GND284

GND283

GND282

GND280
GND281

GND279

GND278

GND277

GND275
GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264
GND265
GND266

GND263

GND262

GND259
GND260
GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6

+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19

+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30

+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37

+VDD_CORE39
+VDD_CORE40
+VDD_CORE41

+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3
+3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

105 mA (A01)

43 mA

1139 mA

250 mA

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

80 uA (S0)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

10 uA (G3)

16 mA

266 mA (A01)

450 mA (A01)

1182 mA (A01)

BGA

OMIT

MCP79-TOPO-B

(11 OF 11)

U1400

AH26
AH33

AH34
AH37

AH38

AJ39

AJ8

AK10

AK33
AK34

AK37

AK4
AK40

AL36
AL40

AL5

AM10
AM16

AM18

AM20
AM22

AM24

AM26
AM30

AM34
AM35

AM37

AM38

AM5

AM6

AM7

AM9

AP26

AN28
AN30

AN39

AN4

Y7

AP10
AU26

AP14

AU14
AP28

AP32

AP34
AP36

AP37

AP4

AP40

AP7
AW23

AR28

AR32
AR40

AT10

AR12
AT13

AT29
AT33

AT6

AT7

AT9

AY21

AY22

L12

AU12

AU28
AP33

AU32
AR30

AU36

AU38

AU4

G28

F20
AV28

AV32

AV36

AV4

AV7
AW11

G20

AR43
AW43

AY10

AV12
AY30

AY33

AY34
AY37

AY38
AY41

AV40
BA1

BA4
AW31

AY6

L35
BC33

BC37

BC41
AY14

BC5

C2
D10

D14
D15

D18

D19
D22

D23

D26
D30

D37

D6
E13

E17
E21

E25

E29
E33

F12

F16
F32

F8

G10
G12

G14
G16

BC12

G22
G24

AW20

G34
G4

G43

G6
G8

H11
H15

AW35

H23
AN8

G40

J12
J8

K10

K12
K18

K26
K37

K4

K40
K8

AU1

L40
L43

L5

M10
M34

M35
M37

Y28

Y33
Y34

Y35

Y37
Y38

AB17

AB16
AN26

AD7
M11

AA4

AB19
AY13

P11

Y6
T11

V11

Y11
AH16

T22

(10 OF 11)

BGA

MCP79-TOPO-B

OMIT

U1400

AD10

AE8
AB10

AD9

Y10
AB11

AA8

Y9

G18

H19

J20
K20

G26
H27

J28

K28

A20

T21

U21

V21

AA25

AA26

AA27

AA28
AC16

AC17
AC18

AC19

AC20
AC21

AA17

AC23

AC24
AC25

AC26

AC27
AC28

AD21
AD23

W27

V25

AA18

U25

AE19

AE21
AE23

AE25

AE26
AE27

AE28
AF10

AF11

AA19

AH12

AF2

AF21

AF23
AF25

AF3

AF4
AF7

AH23

AF9

AA20

AG10

AG11
AG12

AG21

AG23
AG25

AG3

AG4

AA21

AG6
AG7

AG5

AG8

AG9
AH1

AH10

AH11

W26

AH2

AA23

W28

AH25

Y21

AH21

AH3

AH4
AH5

AH6

AH7
AH9

AA24

W21
W23

Y23

W25

AF12

AA16

R32

P31

AF32

AE32
AH32

AJ32
AK31

AK32

AD32
AL31

AB32

AC32

B41
B42

C40

C41
C42

D39
D40

D41

E38
E39

E40

F37

F38
F39

G36

G37
G38

H35
H37

J34

J35

J36

K33

K34

K35
L32

L33

L34
M31

M32
M33

N31

N32

P32
Y32

AA32

T32
U32

V32

W32

AG32

SYNC_DATE=06/06/2008

SYNC_MASTER=T18_MLB

051-7656

31

123

22

MCP Power & Ground

=PP3V3_S5_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S0_MCP

PP3V3_G3_RTC

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

23

23

45 14

23

23

21

25

23

9

8

8

8

21

8 8

Preliminary

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

562 mA (A01)

84 mA (A01)

270 mA (A01)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

MCP 1.05V RMGT Power

Apple: 1x 2.2uF 0402 (2.2 uF)

5 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

(No IG vs. EG data)

19 mA (A01)

450 mA (A01)

57 mA (A01) 43 mA (A01)

127 mA (A01)

206 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

37 mA (A01)

87 mA (A01)

84 mA (A01)

83 mA (A01)

131 mA (A01)105 mA (A01)

MCP PCIE (DVDD) Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

MCP 3.3V Ethernet Power

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

MCP 1.05V AUX Power

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP Core Power

333 mA (A01)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

MCP SATA (DVDD) Power

5 mA (A01)

Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

4771 mA (A01, DDR3)

Apple: 1x 2.2uF 0402 (2.2 uF)

4V

4.7UF

20%
X5R

402

C2582

1

2

20%

4.7UF

4V
X5R
402

C2588

1

2

4.7UF

20%

4V
X5R
402

C2584

1

2

4V

4.7UF

20%
X5R

402

C2586

1

2

CERM
402-LF

20%

2.2UF

6.3V

C2555

1

2

4.7UF

4V

20%
X5R

402

C2502

1

2

X5R
402-1

1UF

10%
10V

C2507

1

2

X5R
402-1

1UF

10%
10V

C2506

1

2

X5R
402-1

1UF

10%
10V

C2505

1

2

X5R
402-1

1UF

10%
10V

C2504

1

2

0.1UF

CERM

20%

402

10V

C2511

1

2

0.1UF

CERM

20%

402

10V

C2510

1

2

0.1UF

CERM

20%

402

10V

C2509

1

2

0.1UF

CERM

20%

402

10V

C2508

1

2

0.1UF

CERM

20%

402

10V

C2513

1

2

0.1UF

CERM

20%

402

10V

C2512

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2536

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2535

1

2

2.2UF

6.3V

20%

402-LF

CERM

C2534

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2533

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2532

1

2

20%

2.2UF

6.3V

402-LF

CERM

C2531

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2530

1

2

X5R
402-1

1UF

10%
10V

C2517

1

2

X5R
402-1

1UF

10%
10V

C2516

1

2

4.7UF

4V

20%
X5R

402

C2515

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2572

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2571

1

2

4V

4.7UF

20%
X5R

402

C2520

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2570

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2574

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2573

1

2

CERM
402-LF

20%

2.2UF

6.3V

C2576

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2575

1

2

2.2UF

6.3V

20%

402-LF

CERM

C2553

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2552

1

2

2.2UF

6.3V

20%

402-LF

CERM

C2551

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2550

1

2

0.1UF

20%
CERM

402

10V

C2549

1

2

0.1UF

20%
CERM

402

10V

C2548

1

2

0.1UF

20%
CERM

402

10V

C2547

1

2

0.1UF

20%
CERM

402

10V

C2546

1

2

0.1UF

20%
CERM

402

10V

C2545

1

2

0.1UF

20%
CERM

402

10V

C2544

1

2

0.1UF

20%
CERM

402

10V

C2543

1

2

20%
CERM

0.1UF

402

10V

C2542

1

2

0.1UF

CERM

20%

402

10V

C2541

1

2

20%

4.7UF

4V
X5R
402

C2540

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2562

1

2

CERM
402-LF

20%

2.2UF

6.3V

C2564

1

2

402

X5R

4V

20%

4.7UF

C2580

1

2

0603

30-OHM-5A

L2570

1 2

30-OHM-5A

0603

L2575

1 2

30-OHM-1.7A

0402

L2582

1 2

30-OHM-1.7A

0402

L2584

1 2

30-OHM-1.7A

0402

L2588

1 2

0402

30-OHM-1.7A

L2586

1 2

0402

30-OHM-1.7A

L2555

1 2

4.7UF

4V

20%
X5R

402

C2500

1

2

4.7UF

4V

20%
X5R

402

C2501

1

2

CERM

20%

0.1uF

402

10V

C2526

1

2

CERM

20%

0.1uF

402

10V

C2525

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2560

1

2

CERM

20%

2.2UF

402-LF

6.3V

C2589

1

2

CERM

0.1UF

20%

402

10V

C2590

1

2

20%

4.7UF

4V
X5R
402

C2595

1

2

30-OHM-1.7A

0402

L2595

1 2

1.47K

1/16W

1%

MF-LF

402

R2590

1

2

0.1UF

CERM

20%

402

10V

C2591

1

2

MF-LF

1%

1/16W

1.47K

402

R2591

1

2

18

CERM

20%

0.1uF

402

10V

C2521

1

2

0.1uF

20%
CERM

402

10V

C2518

1

2

0.1uF

CERM

20%

402

10V

C2519

1

2

CERM

20%

2.2UF

402-LF

6.3V

C2583

1

2

20%
CERM

2.2UF

402-LF

6.3V

C2585

1

2

20%
CERM

2.2UF

402-LF

6.3V

C2587

1

2

CERM

20%

2.2UF

402-LF

6.3V

C2596

1

2

CERM

20%

0.1uF

402

10V

C2529

1

2

20%

4.7uF

4V
X5R
402

C2528

1

2

603

X5R

16V

10%

2.2UF

C2581

1

2

0.2

1%

1/6W

MF

402-HF

R2580

1 2

4.7UF

4V

20%
X5R

402

C2503

1

2

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

MCP Standard Decoupling

25

31

051-7656

123

=PP3V3_S5_MCP

PP1V05_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

=PP3V3_S0_MCP

=PP1V8R1V5_S0_MCP_MEM

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_NV

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PEX_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_MCP_PLL_USB

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_SATA

=PP1V05_ENET_MCP_PLL_MAC

=PP3V3_ENET_MCP_RMGT

MCP_MII_VREF

=PP3V3R1V5_S0_MCP_HDA

=PP1V05_S0_MCP_FSB

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_ENET_MCP_RMGT

=PP3V3_S0_MCP_PLL_UF

=PPVCORE_S0_MCP

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_PEX_DVDD

VOLTAGE=1.05V

PP1V05_S0_MCP_SATA_AVDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_PEX

=PP1V05_S0_MCP_PLL_PEX_UF

=PP1V05_S0_MCP_PLL_UF

=PP1V05_S0_MCP_AVDD_UF

22

22

23

14

45

23 22

21

16

18

21

9

22 18

22

18

66

8

18

8

8

21

16

8

20

20

8

8

8

8

8 8

8

8

8

8 8

8

14

17

8

8

8

Preliminary

A2

A1

SCL

A0

VCC

SDA

WP

GND

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

190 mA (A01, 1.8V)

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

95 mA (A01)

16 mA (A01)

Apple: ???

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

16 mA (A01)

Apple: 2x 2.2uF 0402 (4.4 uF)

206 mA (A01)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

HDCP ROM

206 mA (A01)

WF: Open question on which packge option(s) nVidia can support.

6.3V

2.2UF

20%

402-LF

CERM

NO STUFF

C2650

1

2

30-OHM-1.7A

0402

NO STUFF

L2650

1 2

NO STUFF

20%

402

CERM

10V

0.1UF

C2620

1

2

NO STUFF

402

1K

1%
1/16W
MF-LF

R2630

1

2

20%

402

CERM

NO STUFF

10V

0.1UF

C2630

1

2

20%

4.7UF

4V

402

X5R

C2615

1

2

CERM

4.7UF

6.3V

20%

603

C2640

1

2

30-OHM-1.7A

0402

L2640

1 2

20%
CERM

2.2UF

402-LF

6.3V

C2641

1

2

6.3V

402-LF

2.2UF

20%
CERM

C2616

1

2

SOIC

AT24C08

U2695

1

2

3

4

6

5

8

7

NO STUFF

402

10V

0.1UF

20%

CERM

1

2

C2690

NO STUFF

10K

MF-LF

5%

1/16W

402

R2690

1

2

NO STUFF

44

44

0

5%
1/16W
MF-LF
402

R2651

1

2

402

1/16W

1%

1K

MF-LF

R2620

1

2

CERM
402-LF

20%

2.2UF

6.3V

C2610

1

2

MCP Graphics Support

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

26

123

31

051-7656

=PP3V3_S0_HDCPROM

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_VPLL

MCP_CLK27M_XTALOUT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

TP_MCP_RGB_GREEN

TP_MCP_RGB_HSYNC

TP_MCP_RGB_RED

TP_MCP_RGB_VSYNC

TP_MCP_RGB_BLUE

NC_MCP_RGB_RED

NO_TEST=TRUE

MAKE_BASE=TRUE

CRT_IG_R_C_PR

TP_MCP_RGB_DAC_RSET

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

CRT_IG_B_COMP_PB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

CRT_IG_G_Y_Y

=PP3V3R1V8_S0_MCP_IFP_VDD

=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

CRT_IG_VSYNC

TP_MCP_RGB_DAC_VREF

MCP_TV_DAC_RSET

MCP_TV_DAC_VREF

MCP_CLK27M_XTALIN

NC_MCP_RGB_GREEN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

=PP3V3_S0_MCP_DAC_UF

HDCPROM_WP

=PP3V3_S0_MCP_VPLL_UF

=PP1V05_S0_MCP_HDMI_VDD

MCP_HDMI_VPROBE

MCP_HDMI_RSET

90

90

90

90

90

90

18

90

90

90

18

90

90

8

18

18

18

18

18

18

18

18

18

18

18

18

18

18

18

8

18

18

18

18

18

8

8

8

18

18

Preliminary

IN

OUT

IN

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUT

IN

NC
NC

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

OUT

OUTY

B

A

VIN

GND

VOUTEN

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

RTC Crystal

but results in MCP79 ROMSIP sequence happening after CPU powers up.

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

Reset Button

10K pull-up to 3.3V S0 inside MCP

LPC Reset (Unbuffered)

Platform Reset Connections

PCIE Reset (Unbuffered)

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.

MCP 25MHz Crystal

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

MCP S0 PWRGD & CPU_VLD

RTC Power Sources

10 13 21

50V

12pF

402

CERM

5%

C2810

1 2

12pF

402

CERM

50V

5%

C2811

1 2

402

1/16W

0

5%

MF-LF

R2810

1 2

NO STUFF

10M

402

5%

MF-LF

1/16W

R2811

1

2

19 84 91

XDP

1/16W
MF-LF

5%

0

402

R2896

1 2

402

1/16W

5%

MF-LF

33

PLACEMENT_NOTE=Place close to U1400

R2883

1 2

402

PLACEMENT_NOTE=Place close to U1400

MF-LF

1/16W

5%

33

R2881

1 2

0

5%

1/16W

402

MF-LF

R2890

1 2

SILK_PART=FP SYS RESET

OMIT

0

5%
1/16W
MF-LF

402

R2897

1

2

7

43

41

21

21

17

402

1/16W
MF-LF

5%

33

PLACEMENT_NOTE=Place close to U1400

R2826

1 2

402

PLACEMENT_NOTE=Place close to U1400

1/16W
MF-LF

33

5%

R2825

1 2

19 91

50V

5%

CERM

402

12pF

C2815

1 2

402

CERM

5%

12pF

50V

C2816

1 2

SM-3.2X2.5MM

25.0000M

CRITICAL

Y2815

2 4

1 3

MF-LF

0

1/16W

5%

402

R2815

1 2

NO STUFF

MF-LF

402

1/16W

5%

1M

R2816

1

2

21

21

41 91

22

1/16W

5%

MF-LF

402

PLACEMENT_NOTE=Place close to U1400

R2829

1 2

21 91

402

33

MF-LF

5%

1/16W

R2899

1 2

NO STUFF

1UF

10%

X5R

10V

402

C2899

1

2

35

402

0

5%
1/16W
MF-LF

R2892

1 2

9

MF-LF

1/16W

5%

402

33

R2870

1 2

19

7

41

7

43 91

41 91

CRITICAL

7X1.5X1.4-SM

32.768K

Y2810

1 4

402

MF-LF

1/16W

5%

0

R2891

1 2

26

0

5%
1/16W
MF-LF

402

R2893

1 2

86

0

5%
1/16W
MF-LF

402

R2895

1 2

31

30

MF-LF

5%

402

0

1/16W

R2894

1 2

PLACEMENT_NOTE=Place close to U1400

5%

1/16W

402

MF-LF

33

R2827

1 2

84

84

21

61

41 67 84

MCPSEQ_MIX

MF-LF

5%

1/16W

0

402

R2851

1 2

0.1UF

402

CERM

10V

MCPSEQ_SMC

20%

C2850

1

2

MCPSEQ_SMC

5%

MF-LF

1/16W

0

402

PLACEMENT_NOTE=Place close to U1400

R2850

1 2

21

MCPSEQ_SMC

402

0

1/16W

5%

MF-LF

R2853

1 2

21

MCPSEQ_MIX

402

0

1/16W

5%

MF-LF

R2852

1 2

TC7SZ08AFEAPE

MCPSEQ_SMC

SOT665

U2850

2

1

3

5

4

402

X5R

10V

10%

1UF

NO STUFF

C2802

1

2

RTC_PS_YES

CRITICAL

U2801

MIC5232-2.8YD5

TSOT-23-5

3

2

4

1

5

MF-LF

1/16W

402

5%

10

NO STUFF

R2801

1

2

NO STUFF

1.0M

603

MF-LF

1/10W

5%

R2802

12

1UF

CERM

402

10%

6.3V

C2801

1

2

CRITICAL

SUPERCAP_YES

3.3V

SM

XHHG

0.08F

2%

C2800

1

2

SUPERCAP_YES

402

MF-LF

1/16W

5%

100

R2800

1

2

MF-LF

5%

0

1/16W

402

R2803

1 2

SYNC_DATE=05/01/2008

SYNC_MASTER=M98_MLB

SB Misc

123

31

28

051-7656

=PP3V3_S5_RTC_D

=PP3V3_S5_MCPPWRGD

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP3V3_G3_RTC

RTC_CLK32K_XTALIN

VR_PWRGOOD_DELAY

ALL_SYS_PWRGD

MCP_CLK25M_XTALOUT

MCP_CLK25M_XTALIN

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

PP3V3_G3_SUPERCAP

MCP_PS_PWRGD

MCP_CPU_VLD

MCP_CPUVDD_EN

=GMUX_PCIE_RESET_L

GMUX_PCIE_RESET_L

MAKE_BASE=TRUE

PM_CLK32K_SUSCLK_R

MEM_VTT_EN_R

LPC_CLK33M_SMC_R

PCA9557D_RESET_L

FW_RESET_L

BKLT_PLT_RST_L

EXCARD_RESET_L

MINI_RESET_L

MEM_VTT_EN

LPC_CLK33M_GMUX

PM_CLK32K_SUSCLK

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

SMC_LRESET_L

DEBUG_RESET_L

LPC_RESET_L

PM_SYSRST_L

PM_SYSRST_DEBOUNCE_L

XDP_DBRESET_L

S0_AND_IMVP_PGOOD

PCIE_RESET_L

RTC_CLK32K_XTALOUT

RTC_DISCHARGE_R

22

8

8

21

Preliminary

OUT

OUT

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0
A1
A2

SCL
SDA

P0
P1
P2

P5
P6
P7

P3
P4

THRM

VCC

GND

PAD

NC

NC

IN

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

BOM options provided by this page:

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SDA

NO_VREFMRGN

- =I2C_VREFDACS_SCL

- =PP3V3_S5_VREFMRGN

- =PP3V3_S3_VREFMRGN

- =PPVTT_S3_DDR_BUF

Place close to J3200.126

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

MEM B VREF DQMEM A VREF CAMEM A VREF DQ

(per DAC LSB)

VREFMRGN

Place close to J3100.126

Place close to J3100.1

10mA max load

Place close to U1000.AD26

Place close to U8500, U8550

Place close to U8400, U8450

CPU FSB VREF

FRAME BUFFER VREF

MEM B VREF CA

Place close to J3200.1

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA

Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF

Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00

DAC channel A B A B C D

Required zero ohm resistors when no VREF margining circuit stuffed

ADDR=0x30(WR)/0x31(RD)

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

ADDR=0x98(WR)/0x99(RD)

- =I2C_PCA9557D_SDA

9

1/16W
MF-LF

VREFMRGN

1%

49.9

402

R2916

1 2

10 88

VREFMRGN

0.1UF

20%

CERM
402

10V

C2902

1

2

100

402

1%

VREFMRGN

1/16W
MF-LF

R2914

1 2

5%

VREFMRGN

MF-LF

402

1/16W

100K

R2913

1 2

VREFMRGN

1%

200

1/16W
MF-LF

402

R2903

1 2

MF-LF

1/16W

5%

VREFMRGN

402

100K

R2915

1 2

9

MF-LF

1/16W

402

49.9

1%

VREFMRGN

R2917

1 2

UCSP

MAX4253

VREFMRGN

U2902

C3

C2

C1

C4

B1

B4

UCSP

VREFMRGN

MAX4253

U2903

A3

A2

A1

A4

B1

B4

UCSP

VREFMRGN

MAX4253

U2902

A3

A2

A1

A4

B1

B4

UCSP

MAX4253

VREFMRGN

U2903

C3

C2

C1

C4

B1

B4

UCSP

VREFMRGN

MAX4253

U2904

A3

A1

A4

B1

B4

A2

UCSP

MAX4253

VREFMRGN

U2904

C3

C2

C1

C4

B1

B4

VREFMRGN

1%

200

1/16W
MF-LF

402

R2905

1 2

402

MF-LF

1/16W

200

1%

VREFMRGN

R2909

1 2

VREFMRGN

1%

200

1/16W
MF-LF

402

R2911

1 2

R2918

402

21

NONE

NONE

SHORT

NONE

R2919

402

21
NONE
NONE

NONE

SHORT

5%

100K

1/16W
MF-LF

402

VREFMRGN

R2902

1 2

100K

1/16W

5%

VREFMRGN

MF-LF

402

R2901

1 2

402

100

1%
1/16W
MF-LF

VREFMRGN

R2904

1 2

MF-LF

VREFMRGN

402

1%
1/16W

100

R2906

1 2

402

MF-LF

1/16W

1%

100

VREFMRGN

R2910

1 2

MF-LF

VREFMRGN

402

1/16W

100K

5%

R2907

1 2

CRITICAL

PCA9557

VREFMRGN

QFN

U2901

3

4

5

8

6

7

9

10

11

12

13

14

15

1

2

17

16

VREFMRGN

402

0.1UF

20%

CERM

10V

C2904

1

2

402

100

MF-LF

1%

VREFMRGN

1/16W

R2912

1 2

5%

402

1/16W

100K

MF-LF

VREFMRGN

R2908

1 2

25

44

44

DAC5574

MSOP

VREFMRGN

U2900

9

10

3

6

7

8

1

2

4

5

44

44

10V

402

VREFMRGN

0.1UF

CERM

20%

C2901

1

2

C2900

2.2UF

CERM
402-LF

6.3V

20%

VREFMRGN

1

2

20%

CERM
402

10V

0.1UF

C2905

1

2

VREFMRGN

CERM

0.1UF

VREFMRGN

402

20%
10V

C2903

1

2

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=BEN_K20

051-7656

31

123

29

SYNC_DATE=10/15/2008

R2903

CRITICAL

NO_VREFMRGN

1

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL

1

R2911

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

1

R2909

CRITICAL

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

CRITICAL

1

R2905

NO_VREFMRGN

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

=I2C_PCA9557D_SCL
=I2C_PCA9557D_SDA

=PP3V3_S3_VREFMRGN

PP3V3_S3_VREFMRGN_CTRL

PP3V3_S3_VREFMRGN_DAC

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

VREFMRGN_CPUFSB

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

CPU_GTLREF

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_EN

PCA9557D_RESET_L

VREFMRGN_CPUFSB_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_FRAMEBUF_EN

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CA_SODIMM

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMB_BUF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

=PPVTT_S3_DDR_BUF

VREFMRGN_FRAMEBUF

VREFMRGN_CA_SODIMMA_EN

63

8

26

26

26

26

26

26

26

26

26

26

26

27

28

27

28

8

26

Preliminary

A6

A7

A11

A5

DQ33

VDD
A10/AP

VDD

VSS

SA1
VTT

VSS

DQS4*
DQS4
VSS

DQ35

VSS

CK0*

SA0

VSS
DQ58
DQ59

DM7

VSS

DQ57

DQ56

DQ50
DQ51

VSS

DQS6*
DQS6

VSS

DQ49

DQ48

DQ43
VSS

DM5
VSS
DQ42

SDA
SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60
DQ61

VSS

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS
DQ40

DQ34

VSS

DQ32

TEST

VDD

VDD

S1*

A13

CAS*

WE*

BA0
VDD

VDD
CK0

A1

A3

VDD

VDD
A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS
DQ44
DQ45

DQ39

DQ38

VSS

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD
ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

VDD

A0

CK1

A2

VDD

A4

VDD

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI
BIBI

BI

IN

BI
BI

BI
BI

BI
BI

IN

BI

IN

BI

BI
BI

IN

BI
BI

BI
BI

BI
BI

BI
BI

DQ16

DM3

DQ26
DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24
DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8
DQ9

DM0

DQ0
DQ1

VREFDQ

DQ3

DQ2

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

KEY

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

(SYMBOL 1 OF 2)

IN

BI
BI

BI
BI

BI

BI

BI

BI

BI
BI

BI

BI

IN
IN

IN

IN

IN

IN

IN
IN

IN
IN

IN

IN

IN

IN

BI
BI

BI
BI

IN

BI
BI

IN

BI

BI

IN

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

BI
BI

BI
BI

BI

BI

BI

BI

OUT

BI

IN

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI

IN

BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

BI
BI

NC

NC

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

SPD ADDR=0xA0(WR)/0xA1(RD)

- =PP1V5_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

"Factory" (top) slot

(NONE)

- =I2C_SODIMMA_SDA

Power aliases required by this page:

- =PP0V75_S0_MEM_VTT_A

- =I2C_SODIMMA_SCL

- =PP1V5_S3_MEM_A

BOM options provided by this page:

516-0201

516-0201

DDR3-SODIMM-DUAL-M97-3

F-RT-THB

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101
103

102
104

73 74

136

153

170

187

129
131

141
143

130
132

140
142

147
149

157
159

146
148

158
160

163
165

175
177

164
166

174
176

181
183

191
193

180
182

192
194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99

100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

15 89

15 89

0.1UF

CERM
402

20%
10V

C3131

1

2

6.3V
CERM
402-LF

20%

2.2UF

C3130

1

2

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

28 29

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

CRITICAL

DDR3-SODIMM-DUAL-M97-3

F-RT-THB

J3100

11

28

46

63

5
7

33
35

22
24

34
36

39
41

51
53

15

40
42

50
52

57
59

67
69

56
58

17

68
70

4
6

16
18

21
23

12

10

29

27

47

45

64

62

30

1 2
3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

9

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

10V

20%

402

CERM

0.1UF

C3136

1

2

402-LF

20%

6.3V

2.2UF

CERM

C3135

1

2

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

21 28 41

44

44

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

10K

5%

402

1/16W
MF-LF

R3141

1

2

10K

MF-LF

1/16W

5%

402

R3140

1

2

2.2UF

20%

CERM
402-LF

6.3V

C3140

1

2

10UF

20%

X5R

6.3V

603

C3100

1

2

6.3V

10UF

X5R
603

20%

C3101

1

2

CERM
402

10V

20%

0.1UF

C3110

1

2

0.1UF

402

CERM

10V

20%

C3111

1

2

CERM

0.1UF

20%
10V

402

C3112

1

2

CERM
402

0.1UF

10V

20%

C3113

1

2

10V

0.1UF

402

CERM

20%

C3114

1

2

0.1UF

20%

402

CERM

10V

C3115

1

2

10V

0.1UF

20%

402

CERM

C3116

1

2

10V

0.1UF

20%

402

CERM

C3117

1

2

10V

0.1UF

20%

402

CERM

C3118

1

2

10V

0.1UF

20%

402

CERM

C3119

1

2

10V

20%

402

CERM

0.1UF

C3120

1

2

10V

0.1UF

20%

402

CERM

C3121

1

2

10V

0.1UF

20%

402

CERM

C3122

1

2

10V

0.1UF

20%

402

CERM

C3123

1

2

SYNC_MASTER=BEN_K20

SYNC_DATE=06/10/2008

DDR3 SO-DIMM Connector A

051-7656

31

123

31

MEM_A_DQ<43>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

=PP1V5_S3_MEM_A

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<11>

MEM_A_A<5>

MEM_A_DQ<32>

MEM_A_A<10>

MEM_A_SA<1>

=PP0V75_S0_MEM_VTT_A

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQ<35>

MEM_A_CLK_N<0>

MEM_A_SA<0>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DM<7>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<42>

MEM_A_DM<5>

MEM_A_DQ<45>

=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

MEM_EVENT_L

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DM<6>

MEM_A_DQ<53>

MEM_A_DQ<48>

MEM_A_DQ<46>

MEM_A_DQ<41>

MEM_A_DQ<44>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_CS_L<1>

MEM_A_A<13>

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_A<1>

MEM_A_A<3>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<12>

MEM_A_BA<2>

MEM_A_CKE<0>

MEM_A_DQ<47>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DM<4>

MEM_A_DQ<37>

MEM_A_DQ<36>

PP0V75_S3_MEM_VREFCA_A

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_BA<1>

MEM_A_RAS_L

MEM_A_CLK_N<1>

MEM_A_A<0>

MEM_A_CLK_P<1>

MEM_A_A<2>

MEM_A_A<4>

MEM_A_A<14>

MEM_A_A<15>

MEM_A_CKE<1>

=PPSPD_S0_MEM_A

MEM_A_DQ<16>

MEM_A_DM<3>

MEM_A_DQ<27>

MEM_A_DQ<25>

MEM_A_DQ<4>

MEM_A_DQ<31>

MEM_A_DQ<26>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<22>

MEM_A_DQ<17>

MEM_A_DM<2>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<10>

MEM_A_DQ<15>

MEM_RESET_L

MEM_A_DM<1>

MEM_A_DQ<12>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQ<5>

MEM_A_DQ<24>

MEM_A_DQ<30>

MEM_A_DQ<19>

MEM_A_DQ<23>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQ<18>

MEM_A_DQ<14>

MEM_A_DQ<11>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQ<9>
MEM_A_DQ<13>

MEM_A_DM<0>

MEM_A_DQ<0>
MEM_A_DQ<1>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<2>

MEM_A_DQ<3>

=PP1V5_S0_MEM_A

8

8

26

8

26

8

Preliminary

IN

BI

BI
BI

OUT

BI
IN

IN

IN

IN
IN

IN
IN

IN

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI

IN

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

BI
BI

BI
BI

NC

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42
DQ43

DQ48
DQ49

VSS

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15
A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36
DQ37

VSS

DM4

VSS

VSS
DQ38
DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD
NC

BA2

CK0

VDD

BA0

WE*

A13
S1*

VDD

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54
DQ55

VSS

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS
DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN
MTG PIN MTG PIN
MTG PIN

MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI
BI

BI
BI

BI
BI

IN

BI

IN

BI

BI

BI
BI

IN

BI
BI

BI
BI

BI
BI

BI

BI

BI

DQ2
DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1*
DQS1

DQ10
DQ11

DQ17

DQS2*
DQS2

DQ18
DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6
DQ7

DQ12
DQ13

DM1

RESET*

DQ14
DQ15

DQ20
DQ21

DM2

DQ22
DQ23

DQ28
DQ29

DQS3*

DQS3

DQ30
DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

KEY

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

IN

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI
BI

IN
IN

IN

BI

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

IN

BI
BI

IN

BI
BI

IN

BI

BI
BI

BI
BI

BI
BI

BI
BI

BI

IN

BI

BI
BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

(NONE)

Power aliases required by this page:

BOM options provided by this page:

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

Signal aliases required by this page:

Page Notes

SPD ADDR=0xA2(WR)/0xA3(RD)

516s0706

516s0706

"Expansion" (bottom) slot

15 89

15 89

15 89

15 89

21 27 41

44

44

10V

20%

402

CERM

0.1UF

C3231

1

2

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

CERM
402-LF

6.3V

20%

2.2UF

C3230

1

2

10K

1/16W
MF-LF

5%

402

R3241

1

2

10K

5%
1/16W

R3240

1

MF-LF

2

402

2

1

C3240

20%

CERM
402-LF

6.3V

2.2UF

603

6.3V
X5R

20%

10UF

C3200

1

2

20%

603

X5R

10UF

6.3V

C3201

1

2

0.1UF

20%
10V

402

CERM

C3210

1

2

20%
10V
CERM
402

0.1UF

C3211

1

2

402

10V

20%

0.1UF

CERM

C3212

1

2

20%
10V

0.1UF

402

CERM

C3213

1

2

15 89

20%

CERM
402

0.1UF

10V

C3214

1

2

10V
CERM
402

20%

0.1UF

C3215

1

2

CERM
402

20%

0.1UF

10V

C3216

1

2

CERM
402

20%

0.1UF

10V

C3217

1

2

CERM
402

20%

0.1UF

10V

C3218

1

2

CERM
402

20%

0.1UF

10V

C3219

1

2

0.1UF

CERM
402

20%
10V

C3220

1

2

CERM
402

20%

0.1UF

10V

C3221

1

2

CERM
402

20%

0.1UF

10V

C3222

1

2

CERM
402

20%

0.1UF

10V

C3223

1

2

15 89

15 89

113

204203

212211

210209

208207

206205

196195

190189

185

184

179

178

173

172

168167

162161

156155

151

150

145

144

139

138

134133

128127

126

199

100

99

9493

8887

8281

124123

118117

112111

106105

7675

125

200
202201

197

121

114

110

120

116

122

77

198

186
188

169
171

152
154

135
137

194

192

182

180

193

191

183

181

176

174

166

164

177

175

165

163

160

158

148

146

159

157

149

147

142

140

132

130

143

141

131

129

187

170

153

136

7473

104

102

103

101

115

79

108

109

85

89

86

90

91 92

95 96

78
80

119

83 84

107

97 98

J3200

DDR3-SODIMM

F-RT-BGA3

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

27 29

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

F-RT-BGA3

CRITICAL

DDR3-SODIMM

J3200

11

28

46

63

5
7

33
35

22
24

34
36

39
41

51
53

15

40
42

50
52

57
59

67
69

56
58

17

68
70

4
6

16
18

21
23

12

10

29

27

47

45

64

62

30

1 2
3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

9

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

CERM

0.1UF

20%

402

10V

C3236

1

2

2.2UF

6.3V
CERM

20%

402-LF

C3235

1

2

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

15 89

SYNC_MASTER=BEN_K20

32

123

31

051-7656

SYNC_DATE=07/14/2008

DDR3 SO-DIMM Connector B

=PPSPD_S0_MEM_B

MEM_B_SA<0>

MEM_B_A<10>

=PP1V5_S3_MEM_B

=PP0V75_S0_MEM_VTT_B

=PP1V5_S0_MEM_B

MEM_B_DQ<59>

MEM_B_DQ<63>

MEM_B_SA<1>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DM<7>

MEM_B_CAS_L

MEM_B_DQS_P<4>

MEM_B_DQ<35>

MEM_B_CLK_N<0>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

MEM_EVENT_L

MEM_B_DQ<58>

MEM_B_DQ<62>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<50>

MEM_B_DQ<53>

MEM_B_DM<6>

MEM_B_DQ<54>

MEM_B_DQ<48>

MEM_B_DQ<46>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<41>

MEM_B_DQ<34>

MEM_B_DQ<32>

MEM_B_DQ<37>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_CLK_P<0>

MEM_B_DQS_N<5>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DM<4>

MEM_B_DQ<36>

MEM_B_DQ<33>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_ODT<0>

MEM_B_BA<1>

MEM_B_CLK_N<1>

MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_CKE<1>

MEM_B_DM<5>

MEM_B_DQS_N<4>

MEM_B_DQ<40>

MEM_B_DQ<49>

MEM_B_DQ<55>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_A<12>

MEM_B_A<8>
MEM_B_A<5>

MEM_B_A<3>
MEM_B_A<1>

MEM_B_DQ<9>

MEM_B_DM<2>

MEM_B_DQ<18>

MEM_B_DQ<22>

MEM_B_DQ<4>

MEM_B_DQ<23>

MEM_B_DQ<19>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<16>

MEM_B_DQ<20>

MEM_B_DQ<11>

MEM_B_DQ<14>

MEM_B_DM<1>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_RESET_L

MEM_B_DM<3>

MEM_B_DQ<25>

MEM_B_DQ<29>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<5>

MEM_B_DQ<21>

MEM_B_DQ<17>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQ<8>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQ<28>
MEM_B_DQ<24>

MEM_B_DM<0>

MEM_B_DQ<0>
MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_RAS_L

MEM_B_CKE<0>

PP0V75_S3_MEM_VREFCA_B

MEM_B_A<9>

MEM_B_BA<2>

8

8

8

8

26

26

Preliminary

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

avoid glitch on MEM_RESET_L.

before 1.5V starts to rise to

DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

3.3V input must be stable before

1/16W

5%

MF-LF

1K

402

R3310

1

2

CERM

20%

0.1UF

MEMRESET_HW

402

10V

C3300

1

2

5%

10K

MEMRESET_HW

1/16W
MF-LF

402

R3300

1

2

16

MEMRESET_MCP

MF-LF

5%
1/16W

0

402

R3309

1

2

MMDT3904-X-G

MEMRESET_HW

SOT-363-LF

Q3305

5

3

4

20K

402

1/16W

5%

MEMRESET_HW

MF-LF

R3305

1

2

MEMRESET_HW

SOT-363-LF

MMDT3904-X-G

Q3305

2

6

1

27 28

5%

20K

MEMRESET_HW

1/16W
MF-LF

402

R3301

1

2

DDR3 Support

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

33

123

31

051-7656

MCP_MEM_RESET_L

=PP1V5_S3_MEMRESET

MEM_RESET

MEM_RESET_RC_L

MEM_RESET_L

=PP3V3_S5_MEMRESET

8

8

Preliminary

OUT

S

G

D

IN

IN

BI

NC

IN
IN

IN

IN

OUT

OUT

BI

BI

OUT
OUT

Y

B

A

IN

NC

NC

SYM_VER-1

SYM_VER-1

SYM_VER-1

D

S G

D

S G

OUT

OUT

IN

D

GS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

5V S3 WLAN FET

FDC606P

P-TYPE

26 mOhm @4.5V

0.8 A (EDP)LOADING

MOSFET

RDS(ON)

CAMERA

ALS

518S0610

CHANNEL

275 mA peak

BLUETOOTH

750 mA nominal max

1000 mA peak

206 mA nominal max

AIRPORT

7

17 31

FDC606P_G

Q3450

SOT-6

4

3

6521

9

8

7

6

5

4

32

31

30

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3401

CRITICAL

F-RT-SM

20347-325E-12

2 1

L3405

0402-LF

FERR-120-OHM-1.5A

33

44

44

2 1

L3404

FERR-120-OHM-1.5A

0402-LF

2

1

C3452

CERM

402

20%
10V

0.1uF

21

C3430

402X5R10%

0.1uF

16V

PLACEMENT_NOTE=Place close to J3401.

17 90

17 90

21

C3431

PLACEMENT_NOTE=Place close to J3401.

10% 16V X5R

0.1uF

402

17 90

17 90

20 91

20 91

2

1

C3421

CERM

10V

20%

402

PLACEMENT_NOTE=Place close to Q3450.

0.1uF

20 91

20 91

7

17 90

7

17 90

4

5

3

1

2

U3401

TC7SZ08AFEAPE

SOT665

25

24

5

13

U3402

74LVC1G17DRL

SOT-553

2

1

C3420

20%
X5R

10UF

805

10V

PLACEMENT_NOTE=Place close to Q3450.

1

2

5%

33K

1/16W
MF-LF
402

R3453

402

MF-LF

5%
1/16W

62K

R3454

1

2

2

1

C3453

10%

6.3V

1UF

CERM

402

4 3

21

L3401

90-OHM-100MA

DLP11S

PLACEMENT_NOTE=Place close to J3401.

4 3

21

L3402

DLP0NS

90-OHM

PLACEMENT_NOTE=Place close to J3401.

L3403

PLACEMENT_NOTE=Place close to J3401.

1

4 3

2

90-OHM
DLP0NS

1

2

6

Q3401

SSM6N15FEAPE

SOT563

4

5

3

Q3401

SOT563

SSM6N15FEAPE

17

17

21 33

FERR-120-OHM-1.5A

2 1

L3406

0402-LF

2

1

C3462

0.1uF

10V

20%

402

CERM

21

R3404

MF-LF

1/10W

0

5%

603

SSM3K15FV

1

2

3

SOD-VESM-HF

Q3402

1 2

402

1

R3455

1/16W

5%

MF-LF

21

C3450

402

10%
16V
X5R

0.1UF

C3451

10%

2

1

402

X5R

16V

0.033UF

100K

MF-LF

402

5%

1/16W

R3450

1 2

2

1

R3451

10K

5%

402

MF-LF

1/16W

2

1

C3422

0.1uF

10V

20%

CERM

402

PLACEMENT_NOTE=Place close to J3401.

Right Clutch Connector

34

123

31

051-7656

SYNC_MASTER=M98_MLB

SYNC_DATE=05/01/2008

WLAN_SMIT_RC_FET

PM_WLAN_EN_L

PP5V_WLAN_F

USB_CAMERA_CONN_N

I2C_ALS_SDA

PP5V_WLAN

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

PCIE_MINI_D2R_N

WLAN_SMIT_RC

=PP3V3_S3_WLAN

CONN_USB2_BT_N

USB_BT_N

USB_BT_P

PP3V3_S3_BT_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

PCIE_CLK100M_MINI_CONN_P

AP_PWR_EN

PCIE_MINI_R2D_C_N

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PP5V_S3_BTCAMERA_F

USB_CAMERA_CONN_P

I2C_ALS_SCL

PCIE_MINI_R2D_N

CONN_USB2_BT_P

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

=PP3V3_S3_BT

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=PP5V_S3_BTCAMERA

USB_CAMERA_P

WLAN_SMIT_BUF

MINI_RESET_L

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_N

MINI_CLKREQ_L

PCIE_MINI_R2D_C_P

USB_CAMERA_N

PCIE_MINI_PRSNT_L

MINI_RESET_CONN_L

PCIE_CLK100M_MINI_CONN_N

PCIE_MINI_R2D_P

PCIE_MINI_D2R_P

MINI_CLKREQ_Q_L

PCIE_WAKE_L

MIN_LINE_WIDTH=0.5 mm
VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

=PP5V_S3_WLAN

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

PP5V_WLAN_F PP5V_WLAN_R

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

P5VWLAN_SS

96

96

96

96

90

96

96

90

30

7

7

8

7

7

7

7

7

7

8

8

7

7

7

7

8

30

Preliminary

NC
NC

NC

NC
NC

OUT

IN

IN
IN

SYM_VER-1

SYM_VER-1

BI

BI

IN

IN

IN
IN

OUT

OUT

OUT

NC

NC

BI

BI

THRML_PAD

RCLKEN

GND

NC4

NC3

NC2

NC1

VOUT1P5

CPPE*

PERST*

NC0

OC*

SYSRST*

STBY*

AUXOUT

VOUT3P3

VIN1P5

VIN3P3

CPUSB*

SHDN*

AUXIN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0647

INPUT DECOUPLING

OUTPUT DECOUPLING

EXPRESSCARD/34 FLEX CONNECTOR

2

1

C3505

X5R
603

20%

10uF

6.3V

17

41

25

20 42

2

1

0.1uF

X5R
402

10%
16V

C3502

4 3

21

L3502

PLACEMENT_NOTE=Place close to J3500

90-OHM
DLP0NS

2

1

C3503

10uF

6.3V
X5R
603

20%

1

C3571

PLACEMENT_NOTE=Place close to J3500

0.1uF

2

10% 16V X5R 402

4 3

21

L3503

90-OHM-100MA

DLP11S

PLACEMENT_NOTE=Place close to J3500

21

C3570

10%

PLACEMENT_NOTE=Place close to J3500

X5R 40216V

0.1uF

20 91

20 91

17 90

17 90

17 90

17 90

7

17 90

2

1

C3500

CERM
402

20%
10V

0.1uF

7

17 90

7

17 30

44

44

5

4

1

2

3

U3551

SC70-5

74HC1G00GWDG

21

R3501

1/16W

402

MF-LF

0

5%

9

8

7

6

5

4

3

29

28

27

26

25

24

23

22

21

20

2

19

18

17

16

15

14

13

12

11

10

1

J3500

F-RT-SM

502250-8627

CRITICAL

R3504

402

NONE
NONE

SHORT

NONE

R3503

402

NONE
NONE

SHORT

NONE

R3502

402

NONE
NONE

SHORT

NONE

3

11

2

12

21

6

1

20

18

8

19

16

14

13

5

4

7

9

10

15

17

U3500

QFN

TPS2231

CRITICAL

2

1

C3535

6.3V

20%

603

X5R

10uF

2

1

C3534

10V

20%

402

CERM

0.1uF

2

1

6.3V

20%

603

10uF

X5R

C3531

2

1

C3530

10V

20%

402

CERM

0.1uF

2

1

C3550

10V

20%

402

0.1uF

CERM

2

1

R3561

1/16W

1%

MF-LF

100K

402

2

1

C3560

10V

20%

402

CERM

0.1uF

402

21

R3500

0

MF-LF

5%

1/16W

2

1

C3501

0.1uF

16V
X5R

10%

402

C2

A2

C1

B1

U3561

BGA

SN74LVC1G04YZPR

2

1

C3504

10uF

X5R
603

20%

6.3V

41 42

5

4

1

2

3

U3560

SC70-5

74HC1G00GWDG

31

35

SYNC_MASTER=BEN_K20

SYNC_DATE=10/15/2008

ExpressCard Connector

123

051-7656

PP3V3_S0_EXCARD_R
PP1V5_S0_EXCARD_R

PP3V3_S3_EXCARD_R

=PP3V3_S3_EXCARD

=PP3V3_S0_EXCARD

=PP1V5_S0_EXCARD

SMC_EXCARD_PWR_EN

USB2_EXCARD_CONN_N

USB_EXCARD_N

USB_EXCARD_P

USB2_EXCARD_CONN_P

PCIE_EXCARD_R2D_P

PCIE_EXCARD_R2D_C_N

PCIE_CLK100M_EXCARD_P

PP1V5_S0_EXCARD_SWITCH

EXCARD_CLKREQ_CONN_L

PLT_RESET_SWITCH_L

=PP3V3_S0_EXCARD

EXCARD_CPUSB_L

TP_EXCARD_STBY_L

EXCARD_RESET_L

=PP3V3_S3_EXCARD

EXCARD_SHDN_L_R

PCIE_EXCARD_PRSNT_L

EXCARD_CPPE_L

EXCARD_CPUSB_L

EXCARD_CPPE_L

SMC_EXCARD_CP

EXCARD_CLKREQ_L

EXCARD_RCLKEN

EXCARD_CLKREQ_CONN

=PP1V5_S0_EXCARD

=PP3V3_S3_EXCARD

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_N

PCIE_CLK100M_EXCARD_CONN_P

PCIE_CLK100M_EXCARD_CONN_N

PCIE_CLK100M_EXCARD_N

PCIE_EXCARD_D2R_N

PCIE_EXCARD_D2R_P

PCIE_CLK100M_EXCARD_CONN_P

EXCARD_CPPE_L

PCIE_EXCARD_R2D_N

PCIE_EXCARD_R2D_P

=SMBUS_EXCARD_SDA

PP3V3_S3_EXCARD_SWITCH

EXCARD_CLKREQ_CONN_L

PCIE_CLK100M_EXCARD_CONN_N

PP3V3_S0_EXCARD_SWITCH

PLT_RESET_SWITCH_L

USB2_EXCARD_CONN_P

=SMBUS_EXCARD_SCL

PP1V5_S0_EXCARD_SWITCH

PCIE_WAKE_L

PP3V3_S0_EXCARD_SWITCH

EXCARD_CPUSB_L
USB2_EXCARD_CONN_N

EXCARD_RCLKEN

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=.6mm

VOLTAGE=1.5V

PP1V5_S0_EXCARD_SWITCH

EXCARD_CPPE_L

EXCARD_OC_L

PP3V3_S3_EXCARD_SWITCH

MIN_LINE_WIDTH=.3mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2mm

PP3V3_S0_EXCARD_SWITCH

MIN_NECK_WIDTH=0.2mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=.6mm

96

96

90

90

96

96

96

90

90

96

96

96

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

31

8

8

8

7

7

7

7

7

7

8

7

8

17

7

7

7

31

8

8

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

31

7

7

7

7

Preliminary

TXD[2]

TXCTL

AVDD33

FB12

DVDD12

AVDD12

RXC

MDIO

GND

TXD[3]

RXD[0]

MDI+[0]

CKXTAL1
CKXTAL2

CLK125

RSET

PHYRSTB*

MDC

RXCTL

MDI-[2]

MDI+[2]

MDI+[3]

MDI+[1]
MDI-[1]

ENSWREG

TXD[1]

TXD[0]

RXD[3]/AN1

RXD[1]/TXDLY

TXC

MDI-[3]

LED1/PHYAD1

LED2/RXDLY

LED0/PHYAD0

RXD[2]/AN0

MDI-[0]

REGOUT

VDDREG

DVDD33

REFERENCE

RGMII/MII

MEDIA DEPENDENT

MANAGEMENT

CLOCK

RESET

LED

IN
IN
IN
IN

IN

IN
BI

IN

IN

BI

BI

BI

BI

BI
BI

BI
BI

OUT

OUT
OUT
OUT
OUT

OUT

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

C3790 should be placed close to U3700.19

C3790 reserved for EMI
per RealTek request.

Alias to GND for external 1.05V supply.

If internal switcher is not used, VDDREG and REGOUT can float.

( 7mA typ - Energy Detect)

(221mA typ - 1000base-T)

WF: Marvell numbers, update for Realtek

RXDLY = 0 (RXCLK transitions with data)
TXDLY = 0 (No TXCLK Delay)

AN[1:0] = 11 (Full auto-negotiation)

PHYAD = 01 (PHY Address 00001)

Configuration Settings:

If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

If internal switcher is used, must place inductor within 5mm

(43mA typ - 1000base-T)
(19mA typ - Energy Detect)

Alias to =PP3V3_ENET_PHY for internal switcher.

PLACE R3796 CLOSE TO U1400, PIN D24

WF: Marvell numbers, update for Realtek

2.49K

1%

402

1/16W
MF-LF

R3730

1

2

5%
1/16W
MF-LF

10K

402

R3720

1

2

0402-LF

FERR-120-OHM-1.5A

CRITICAL

L3705

1

2

0.1UF

16V
X5R
402

10%

C3705

1

2

OMIT

CRITICAL

RTL8211CLGR

TQFP

U3700

10

40

6

41

42

43

32

28

36

152137

39

3

7

203347

34
35

38

30

2

1

5

4

9

8

12

11

31

29

48

46

19

13

14

16
17

18

22

27

23

24
25

26

44

45

10%

402

X5R

16V

0.1UF

C3706

1

2

10%

402

X5R

16V

0.1UF

C3700

1

2

10%

402

X5R

0.1UF

16V

C3701

1

2

10%

402

X5R

16V

0.1UF

C3702

1

2

18 92

18 92

18 92

18 92

18 92

18 92

18 92

18 92

33 92

34 92

34 92

34 92

34 92

34 92

34 92

34 92

34 92

402

22

1/16W5%MF-LF

R3790

1 2

22

5%

1/16W MF-LF

402

R3791

1 2

22

5%

1/16W MF-LF

402

R3792

1 2

5%

1/16W MF-LF22402

R3793

1 2

5%

1/16W MF-LF22402

R3794

1 2

402

22

MF-LF1/16W

5%

R3795

1 2

18 92

18 92

18 92

18 92

18 92

18 92

1/16W

5%

MF-LF

4.7K

402

R3755

1

2

1/16W

5%

MF-LF

4.7K

402

R3756

1

2

9

1/16W

4.7K

5%

MF-LF

402

R3752

1

2

1/16W

5%

MF-LF

4.7K

402

R3757

1

2

402

MF-LF

4.7K

5%

1/16W

R3750

1

2

402

1/16W

5%

4.7K

MF-LF

R3751

1

2

10%

402

X5R

16V

0.1UF

C3715

1

2

10%

402

X5R

0.1UF

16V

C3716

1

2

CRITICAL

0402-LF

FERR-120-OHM-1.5A

L3715

1

2

402

10%
X5R

16V

0.1UF

C3711

1

2

10%

402

X5R

16V

0.1UF

C3710

1

2

16V

0.1UF

X5R
402

10%

C3714

1

2

NO STUFF

10PF

CERM

402

50V

5%

C3790

1

2

22

R3796

21

5%
1/16W

MF-LF

402

18 92

5%

402

1/16W

4.7K

MF-LF

NO STUFF

R3725

1

2

0

5%
1/16W

402

MF-LF

R3724

1 2

0.1UF

402

NO STUFF

10V
CERM

20%

C3725

1

2

402

5%

22

1/16W
MF-LF

R3731

1

2

051-7656

123

37

31

SYNC_MASTER=SUMA_K20

Ethernet PHY (RTL8211CL)

SYNC_DATE=07/22/2008

ENET_CLK125M_TXCLK_R

ENET_RESET_L

TP_RTL8211_CKXTAL2

ENET_MDIO

ENET_MDC

ENET_TX_CTRL

ENET_TXD<3>

=PP3V3_ENET_PHY_VDDREG

ENET_RXD_R<2>

ENET_RXD_R<0>

ENET_CLK125M_TXCLK

ENET_RX_CTRL

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

ENET_CLK125M_RXCLK

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V05_ENET_PHYAVDD

VOLTAGE=1.05V

=PP1V05_ENET_PHY

ENET_RXD_R<3>

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET_PHYAVDD

ENET_MDI_P<1>

ENET_MDI_N<2>

ENET_MDI_P<0>
ENET_MDI_N<0>

=RTL8211_REGOUT

RTL8211_CLK25M_CKXTAL1

ENET_TXD<2>

=RTL8211_ENSWREG

=PP3V3_ENET_PHY

ENET_RXD_R<1>

RTL8211_RXDLY

RTL8211_PHYAD1

ENET_MDI_N<3>

ENET_MDI_P<3>

ENET_MDI_P<2>

ENET_MDI_N<1>

ENET_RXCTL_R

RTL8211_PHYAD0

ENET_CLK125M_RXCLK_R

ENET_TXD<0>
ENET_TXD<1>

RTL8211_PHYRST_L

RTL8211_CLK125

RTL8211_RSET

9

92

92

8

92

9

8

92

92

Preliminary

G

DS

IN

OUT

OUT

D

SG

IN

D

S G

IN

IN

D

SG

D

SG

D

S

G

D

SG

IN

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

=P1V05ENET_EN. Nets separated on

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

1.05V ENET FET

3.3V ENET FET

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

Pull-up is with power FET.

Non-ARB:

ARB for alternate power options.

Recommend aliasing PM_SLP_RMGT_L and

1.8V Vgs

@ 2.5V Vgs:

I(max) = 1.7A (85C)

Rds(on) = 90mOhm max

ARB for alternate power options.

MOBILE:

=P3V3ENET_EN. Nets separated on

WLAN Enable Generation

Recommend aliasing PM_SLP_RMGT_L and

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

RTL8211 25MHz Clock

NTR4101P

CRITICAL

SOT-23-HF

Q3810

3

1

2

0.01UF

402

16V

CERM

10%

C3810

12

16V
X5R
402

10%

0.033UF

C3811

1

2

402

100K

1/16W
MF-LF

5%

R3810

1 2

18 92

PLACEMENT_NOTE=Place close to U1400

1/16W

5%

MF-LF

22

402

R3895

1 2

32 92

CERM
402

10%
16V

0.01UF

C3841

1

2

10V

CERM

20%

0.1UF

402

C3840

1

2

30

SOT563

SSM6N15FEAPE

Q3805

3

5

4

21 36 41 42

SSM6N15FEAPE

SOT563

Q3801

6

2

1

21 30

7

21 36 41 67 82 84

SOT563

SSM6N15FEAPE

Q3805

6

2

1

SOT563

SSM6N15FEAPE

Q3841

6

2

1

MF-LF

402

1/16W

1%

69.8K

R3842

1

2

CRITICAL

SOT23

SI2312BDS

Q3840

3

1

2

5%

10K

1/16W

402

MF-LF

R3800

1

2

SSM6N15FEAPE

SOT563

Q3801

3

5

4

9

SOT563

SSM6N15FEAPE

Q3841

3

5

4

9

10K

1%

MF-LF

402

1/16W

R3841

1 2

100K

MF-LF

1/16W

5%

402

R3840

1 2

SYNC_DATE=07/15/2008SYNC_MASTER=SUMA_K20

38

123

31

051-7656

Ethernet & AirPort Support

=PP3V3_S5_P1V05ENETFET

=PP3V3_S5_P3V3ENETFET

=PP3V3_ENET_FET

P3V3ENET_SS

=P3V3ENET_EN

RTL8211_CLK25M_CKXTAL1

MCP_CLK25M_BUF0_R

P3V3ENET_EN_L

=PP1V05_ENET_P1V05ENETFET

=P1V05ENET_EN

AC_OR_S0_L

PM_WLAN_EN_L

PM_SLP_S3_L

SMC_ADAPTER_EN

AP_PWR_EN

=PP1V05_ENET_FET

P1V05ENET_EN_L_RC

P1V05ENET_EN_L

P1V05ENET_SS

8

8 8

8

8

Preliminary

BI

RX

TX

BI

RX

TX

BI

BI

BI

BI

BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

(NONE)

mirrored on opposite

Transformers should be

(NONE)

sides of the board

Place one of 0.1uf cap close to each centertap pin of transformer

Page Notes

Signal aliases required by this page:

(NONE)

Power aliases required by this page:

BOM options provided by this page:

32 92

TLA-6T213HF

SM

CRITICAL

T3900

1

10

11

12

2

3

4

5

6 7

8

9

1/16W

5%

402

MF-LF

75

R3900

1

2

1/16W

5%

402

MF-LF

75

R3901

1

2

1/16W

5%

402

MF-LF

75

R3902

1

2

1/16W

5%

402

MF-LF

75

R3903

1

2

2KV

10%

1206

CERM

1000PF

CRITICAL

C3908

1 2

32 92

0.1UF

10%
16V

402

X5R

C3906

1

2

16V

10%

402

X5R

0.1UF

C3904

1

2

16V

10%

402

X5R

0.1UF

C3902

1

2

SM

TLA-6T213HF

CRITICAL

T3901

1

10

11

12

2

3

4

5

6 7

8

9

16V

10%

402

X5R

0.1UF

C3900

1

2

OMIT

F-RT-TH

RJ45-M97-2

CRITICAL

J3900

1

10

11
12

2
3
4
5
6
7
8

9

402-1

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

50V

5%
CERM

C3910

1

2

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5%
50V

402-1

C3941

1

2

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5%
50V

402-1

C3940

1

2

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

402-1

10PF

CERM

5%
50V

C3931

1

2

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5%
50V

402-1

C3930

1

2

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5%
50V

402-1

C3921

1

2

CERM

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

5%
50V

402-1

C3920

1

2

32 92

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5%
50V

402-1

C3911

1

2

32 92

32 92

32 92

32 92

32 92

31

39

051-7656

123

Ethernet Connector

SYNC_MASTER=SUMA_K20 SYNC_DATE=07/15/2008

J3900

CONN,RJ45,HB,10/100TX

514-0636

1

CRITICAL

ENETCONN_P<2>

ENETCONN_P<3>

ENETCONN_P<1>

ENETCONN_N<2>

ENET_CTAP1

ENET_MDI_N<0>

ENET_MDI_N<1> ENETCONN_N<1>

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

ENET_BOB_SMITH_CAP

ENET_CTAP2

ENET_CTAP3

ENET_MDI_P<0>

ENET_MDI_N<2>

ENET_MDI_P<1>

ENET_MDI_P<2>

ENET_MDI_P<3>

ENET_MDI_N<3>

ENETCONN_P<0>

ENETCONN_N<3>

ENET_CTAP0

ENETCONN_N<0>

ENETCONN_CTAP

96

96

96

96

96

96

96

96

Preliminary

DS2

ATBUSH
ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N
TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620*
JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK
SCIFDAIN
SCIFDOUT

SCIFMC

SCL
SDA

SE
SM

TDO

TPA1N

TPA2N
TPA2P
TPB0N
TPB0P
TPB1N
TPB1P
TPB2N
TPB2P

TPBIAS0
TPBIAS1
TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC
NC
NC

NC

IN
IN

IN

IN

OUT

OUT

OUT

OUT

IN
IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI

IN

NC
NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NAND tree order.

NOTE: NT-xx notes show

NT-10 (IPD)

(IPD) NT-18

NT-12 (IPD)

NT-13

FIXME!!! - TYPO IN SYMBOL REGCTL

(IPU)

(IPD) NT-21

(IPU)

(IPD) NT-20

(IPD) NT-19

(IPD)

NT-9

(Reserved)

NT-OUT

NT-14 (IPD)

NT-5

NT-17

NT-6

NT-7

NT-16 (IPD)

NT-2 (IPU)

(OD)

NT-4 (IPU)
NT-3 (IPU)

NT-1 (IPU)

135 mA

110 mA Digital Core

25 mA PCIe SerDes 17 mA PCIe SerDes

0 mA VReg PWR

114 mA FireWire PHY

7 mA I/O

138 mA

(IPD)

(IPD)

(IPU) NT-8

(IPD) NT-11

NT-15 (IPD)

402

MF-LF

1/16W

1%

191

R4170

1

2

10%

402

6.3V

0.33UF

CERM-X5R

C4162

1

2

402

470K

MF-LF

5%

1/16W

R4162

1

2

CRITICAL

OMIT

FW643

BGA

U4100

B13

A13

A11

A10

L13

L2

F12
E12

E13

D12

K13

D1

J2

K1

J12
J13

N8

N7

N5
N6

N4

B11

N9
N10

D13

L8

G2

G1
H1

F2

N12

M11

M13
N13

M4
N2

M1

M3

B8
A8

B5

A5
B3

A3

B9
A9

B6

A6
B4

A4

B7
C3

A2

B10

N1

E1

D2

H13

A1

B1

M12N3N11

B12

C13E2E10H2H12K2L1

C1

C12F1G12J1L3

L11M2A12D5D6D8L5

L10L6L9

K12

L12

B2

D4

F7

F8

F10

G4G6G7

G8

G10

H4

H6D7H7

H8

H10

J4J5J9

J10

K4K5K7D9K8K9L7

K6

K10

D10

E4E5E9F4F6

C2

G13

F13

402

50V

5%

22PF

CERM

C4151

1 2

402

CERM

22PF

5%

50V

C4150

1 2

402

1/16W
MF-LF

R4160

1

2

1%

200K

402

1/16W

1%

MF-LF

412

R4150

1 2

402

1/16W

5%
MF-LF

10K

R4163

1

2

402

1/16W

5%

MF-LF

10K

R4164

1

2

402

10K

MF-LF

5%

1/16W

FW643_LDO

R4165

1

2

10%

402X5R

16V

PLACEMENT_NOTE=Place C4176 close to U4000

0.1UF

C4176

1 2

10%

402X5R

16V

PLACEMENT_NOTE=Place C4175 close to U4000

0.1UF

C4175

1 2

402

1/16W

5%

MF-LF

10K

R4166

1

2

10%

402X5R

16V

PLACEMENT_NOTE=Place C4171 close to U1400

0.1UF

C4171

1 2

10%

402X5R

16V

PLACEMENT_NOTE=Place C4170 close to U1400

0.1UF

C4170

1 2

10%

1UF

402

6.3V
CERM

C4130

1

2

10%

1UF

402

6.3V
CERM

C4131

1

2

10%

1UF

402

6.3V
CERM

C4100

1

2

10%

1UF

402

6.3V
CERM

C4101

1

2

10%

1UF

402

6.3V
CERM

C4132

1

2

10%

1UF

402

6.3V
CERM

C4102

1

2

10%

1UF

402

6.3V
CERM

C4103

1

2

10%

1UF

402

6.3V
CERM

C4135

1

2

10%

1UF

402

6.3V
CERM

C4136

1

2

10%

1UF

402

6.3V
CERM

C4104

1

2

10%

1UF

402

6.3V
CERM

C4110

1

2

10%

1UF

402

6.3V
CERM

C4105

1

2

10%

1UF

402

6.3V
CERM

C4106

1

2

10%

1UF

402

6.3V
CERM

C4120

1

2

10%

1UF

402

6.3V
CERM

C4121

1

2

10%

1UF

402

6.3V
CERM

C4122

1

2

10%

1UF

402

6.3V
CERM

C4123

1

2

10%

1UF

402

6.3V
CERM

C4124

1

2

10V

402

0.1UF

CERM

20%

C4141

1

2

10%

1UF

402

6.3V
CERM

C4111

1

2

10%

1UF

402

6.3V
CERM

C4140

1

2

17 90

17 90

17 90

17 90

17 90

17 90

19

17

402

1/16W

1%

MF-LF

2.94K

R4161

1

2

37

37

37

37 93

37 93

37 93

37 93

37

37

37 93

37 93

37 93

37 93

37

37

37

37

37

120-OHM-0.3A-EMI

0402-LF

L4130

1 2

0402-LF

120-OHM-0.3A-EMI

L4135

1 2

25

120-OHM-0.3A-EMI

0402-LF

L4110

1 2

CRITICAL

SM-3.2X2.5MM

24.576MHZ

Y4150

2 4

1 3

FireWire LLC/PHY (FW643)

SYNC_MASTER=M98_MLB

41

123

31

051-7656

SYNC_DATE=04/01/2008

TP_FW643_SCIFMC

=PP1V0_FW_FWPHY

=PP3V3_FW_FWPHY

FW_CLK24P576M_XO

FW_CLK24P576M_XI

FW643_REGCTL

TP_FW643_OCR10_CTL

TP_FW643_TCK

PCIE_CLK100M_FW_N

TP_FW643_TDI

TP_FW643_AVREG

TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN

TP_FW643_MODE_A

TP_FW643_NAND_TREE

FW_RESET_L

PCIE_CLK100M_FW_P

TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT

TP_FW643_SDA

TP_FW643_SE
TP_FW643_SM

TP_FW643_TDO

TP_FW643_VBUF

FW_PME_L

FW_P1_TPA_P

FW_P1_TPA_N

FW_P2_TPA_N
FW_P2_TPA_P
FW_P0_TPB_N

FW_P1_TPB_N
FW_P1_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P

FW_P0_TPBIAS

FW_CLK24P576M_XO_R

FW643_R0

FW643_REXT

=FW_PHY_DS2

=FW_PHY_DS0

=PP3V3_FW_FWPHY

=FW_PHY_DS1

FW_P0_TPB_P

FW_P0_TPA_P

FW_P0_TPA_N

PCIE_FW_R2D_C_N

PCIE_FW_R2D_N

PCIE_FW_R2D_C_P

PCIE_FW_R2D_P

PCIE_FW_D2R_N

PCIE_FW_D2R_C_N

PCIE_FW_D2R_P

PCIE_FW_D2R_C_P

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VDDA

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_FWPHY_AVDD

FW643_PU_RST_L

FW643_TPCPS

=PPVP_FW_PHY_CPS

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_FW_FWPHY_VP25

TP_FW643_TMS

FW643_TRST_L

FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_L

FW643_SCL

FW_P2_TPBIAS

FW_P1_TPBIAS

37

37

35

35

8

8

7

7

8

90

90

90

90

37

Preliminary

V-

V+

D

SG

IN

IN

D

SG

G

P-CHN

S

D

G

D

S

N-CHN

D

SG

D

SG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PPVP_FW_SUMNODE (power passthru summation node)

Enables port power when machine
is running or on AC.

(NONE)

2.81V on late Vg event and port power is off

is running or on AC.

Enables port power when machine

FireWire Port Power Switch

2.95V when port power is on

FWLATEVG_3V_REF Hysteresis:

Late-VG Event Detection

- FW_PORT_FAULT_PU

- =PP3V3_FW_LATEVG_ACTIVE

BOM options provided by this page:

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

R4219

MF-LF
402

5%
1/16W

2

1

2.0M

2

1

C4219

10V

10%

603

CERM-X5R

0.33UF

2

1

C4210

402

0.1UF

CERM

10V

20%

R4210

21

402

1/16W

200K

1%

MF-LF

2

5

1

3

4

U4210

LMC7211

SM-HF

R4211

2

1

1/16W

5%

402

10K

MF-LF

2

1

C4211

402

CERM

5%

50V

100pF

R4212

2

1

10K

MF-LF

1/16W

1%

402

R4213

2

1

80.6K

MF-LF
402

1%
1/16W

2 1

D4219

MBR0540XXH

SOD-123

CRITICAL

NDS9407

SOI-HF

Q4260

5

6

7

8

4

1

2

3

0.01uF

402

20%
16V

CERM

C4260

1

2

R4260

MF-LF

5%

402

2

1

470K

1/16W

4

5

3

SOT563

Q4261

SSM6N15FEAPE

R4261

5%

330K

1/16W

402

MF-LF

1

2

21 33 41 42

7

21 33 41 67 82 84

3

2

1

D4260

CRITICAL

PWRDI5

PDS540XF

1

2

6

SOT563

SSM6N15FEAPE

Q4261

21

F4260

1.5A-24V

1812L15024HF

CRITICAL

R4262

1 2

10

5%

402

MF-LF

1/16W

FW_LVG_NEW

R4263

1/16W

1

2

MF-LF
402

10K

5%

FW_LVG_NEW

10V

1

2

20%

C4263

402

X5R-CERM

2.2UF

NO STUFF

NTUD3127CXXG

SOT-963

Q4262

3

5

4

FW_LVG_NEW

1

6

FW_LVG_NEW

2

SOT-963

NTUD3127CXXG

Q4262

1

2

6

SOT563

Q4263

SSM6N15FEAPE

4

5

3

SSM6N15FEAPE

SOT563

Q4263

R4266

MF-LF
402

5%
1/16W

1

2

10K

FW_LVG_NEW

10K

402

FW_LVG_NEW

5%

MF-LF

1/16W

2

1

R4265

R4264

2

1/16W
MF-LF
402

5%

0

1

FW_LVG_NEW

31

051-7656

42

123

FireWire Port Power

SYNC_MASTER=YWU_K20

SYNC_DATE=05/28/2008

=PPVIN_S5_FWPWRSW

=PPVIN_S5_FWPWRSW

=PP3V3_FW_LATEVG_ACTIVE

LATEVG_EVENT_L

PP2V4_FW_LATEVG

FWLATEGV_3V_REF

P2V4_FWLATEVG_RC

=PPVOUT_FW_FWPWRSW

SMC_ADAPTER_EN

PPVIN_S5_FWPWRSW_FET

FW_PORTPWR_EN_R

FW_PORTPWR_EN_FET

FWPWR_EN_L_DIV

FWPWR_EN_L

FW_PORTPWR_EN

FW_PORTPWR_EN

PP10V_FW_D

VOLTAGE=10V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

=PPBOOST_S5_FW_FET

=PPBOOST_FW_FWPWRSW_F

PM_SLP_S3_L

FW_PORTPWR_EN_L

PPVIN_S5_FWPWRSW_R

36

36 8 8

8

37

8

36

36

8 8

Preliminary

SC/NC

TPA+

TPA(R)

VG

VPTPB+

TPB(R)

TPB-

TPA-

CHASSIS

GND

SGD

(SYM-VER2)

G

S

(SYM-VER1)

D

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PORT 1

BILINGUAL

OUTPUT

Page Notes

Power aliases required by this page:

- =GND_CHASSIS_FW_PORT1

FireWire TPA/TPB pairs to their

R4390 should be 390 Ohms max for a 3.3V rail

Late-VG Protection Power

- =PPVP_FW_PORT1

- =GND_CHASSIS_FW_EMI_R

Signal aliases required by this page:

NOTE: This page is expected to contain
the necessary aliases to map the

(NONE)

INPUT

TPA+

TPA<R>

TPA-

VG

NC

VP

TPB+

BOM options provided by this page:

1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)

(NONE)

(Common to all ports)

ESD and late-VG rail

(FW_PORT1_BREF)

Cable Power

NOTE: FireWire TPA/TPB pairs are NOT

514S0605

- =PP3V3_FW_LATEVG

to apply to entire TPA/TPB XNets.

assumed that FireWire PHY page will

and should be biased to 2.4V for margin

to at least 2.1V for FW signal integrity

PP2V4_FWLATEVG needs to be biased

for snap-back diodes

- 1-port Portable Power Class (0)

FireWire PHY Config Straps

"Snapback" & "Late VG" Protection

Configures PHY for:

provide the appropriate constraints

constrained on this page. It is

properly terminate unused signals.

appropriate connectors and/or to

- Port "1" Bilingual (1394B)

Note: Trace PPVP_FW_PORT1 must handle up to 5A

TPB­TPB<R>

FW spec calls out 0.33uF

TI PHYs require 1uF even though

Place close to FireWire PHY

Termination

local grounds per 1394b spec

AREF needs to be isolated from all

When a bilingual device is connected to a

between them (to avoid ground offset issue)

BREF should be hard-connected to logic
ground for speed signaling and connection

beta-only device, there is no DC path

(GND_FW_PORT1_VG)

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

R4363

1

2

MF-LF

402

1/16W

1%

4.99K

R4364

1

2

SIGNAL_MODEL=EMPTY

1%
1/16W
MF-LF
402

56.2

R4362

1

2

220pF

CERM
402

5%
25V

C4364

1

2

1%

56.2

MF-LF

1/16W

402

SIGNAL_MODEL=EMPTY

R4361

1

2

0.33UF

CERM-X5R

6.3V

10%

402

C4360

1

2

1/16W

1%

MF-LF
402

56.2

SIGNAL_MODEL=EMPTY

R4360

1

2

50V

10%

603-1

X7R

0.1uF

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

C4319

1

2

1/16W
MF-LF
402

5%

1M

R4319

1

2

50V
X7R

10%

0.01UF

402

C4314

1

2

FERR-250-OHM

SM

CRITICAL

L4310

1 2

0.01uF

50V

10%

402

X7R

C4310

1

2

SOT-363

BAV99DW-X-G

DP4310

1

2

6

10%
50V

0.01uF

402

X7R

C4311

1

2

BAV99DW-X-G

SOT-363

DP4310

4

5

3

SOT-363

BAV99DW-X-G

DP4311

1

2

6

BAV99DW-X-G

SOT-363

DP4311

4

5

3

0.01uF

50V

10%

402

X7R

C4313

1

2

0.01uF

50V

10%
X7R

402

C4312

1

2

1/16W

1%

402

MF-LF

332

R4390

1 2

CRITICAL

SOT23

MMBZ5227BLT1H

D4390

1

3

CRITICAL

F-RT-TH

1394B-M97

J4310

1

10
11
12
13

2

3

4

5

6

7

8

9

MF-LF

402

1%

1/16W

10K

R4381

1

2

402

1/16W

1%

MF-LF

10K

R4382

1

2

402

10K

1/16W
MF-LF

1%

R4380

1

2

BSS8402DW

SOT-363

Q4300

3

5

4

BSS8402DW

SOT-363

Q4300

6

2

1

330K

1/16W
MF-LF

402

5%

R4312

1

2

470K

1/16W

5%

402

MF-LF

R4311

1

2

SYNC_DATE=07/14/2008

SYNC_MASTER=M98_MLB

FireWire Ports

051-7656

31

43

123

FW_PORT1_TPB_P

FW_PORT1_TPA_N

FW_PORT1_AREF

FW_PORT1_TPA_P

FW_PORT1_TPB_N

PPVP_FW_PORT1_F

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

MIN_LINE_WIDTH=0.5 mm

CPS_EN_L_DIV

PP2V4_FW_LATEVG

MAKE_BASE=TRUE

NC_FW0_TPBN

FW_P0_TPA_P

=PPVP_FW_PHY_CPS

CPS_EN_L

=PP3V3_FW_FWPHY

=PPVP_FW_PHY_CPS_FET

FW_P1_TPA_N

MAKE_BASE=TRUE

NC_FW2_TPBPFW_P2_TPB_P

NC_FW2_TPBN

MAKE_BASE=TRUE

FW_P2_TPA_N

MAKE_BASE=TRUE

NC_FW0_TPBP

=PP3V3_FW_FWPHY

=FW_PHY_DS0

=FW_PHY_DS1

=FW_PHY_DS2

MAKE_BASE=TRUE

FWPHY_DS0

FWPHY_DS2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

FWPHY_DS1

FW_P1_TPA_P

=PPVP_FW_PORT1

=PP3V3_FW_LATEVG

FW_P1_TPB_N

FW_PORT1_TPB_C

PP2V4_FW_LATEVG

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.4V

MIN_LINE_WIDTH=0.38 mm

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

FW_PORT1_TPA_P

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_P0_TPB_P

FW_P1_TPB_P

FW_P2_TPB_N

FW_P0_TPB_N

MAKE_BASE=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPBIAS

NC_FW0_TPAP

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_FW2_TPAN

FW_P2_TPA_P

FW_P0_TPA_N

FW_P2_TPBIAS

FW_P0_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

NC_FW2_TPAP

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_P1_TPBIAS

MIN_NECK_WIDTH=0.2 MM

PPVP_FW_CPS

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=10V

MAKE_BASE=TRUE

37

37

37

93

35

93

35

93

93

37

93

93

93

93

37

37

37

37

36

7

35

35

8

8

35

7

35

7

35

7

8

35

35

35

35

8

8

35

36

37

37

37

35

35

35

35

7

7

7

35

35

35

35

7

37

35

Preliminary

OUT

IN

SYM_VER-1

SYM_VER-1

OUT

OUT

IN

IN

D

SG

D

SG

SGD

SYM_VER-1

SYM_VER-1

OUT

OUT

IN

IN

NC

NC
NC

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

516S0350

SATA HDD Port

SATA ODD Port

Indicates disc presence

516S0617

ensure the drive is unpowered in S3/S5.

NOTE: 3.3V must be S0 if 5V is S3 or S5 to

ODD Power Control

7

41

33K

MF-LF

1/16W

5%

402

R4590

1

2

55560-0168

M-ST-SM-LF

CRITICAL

J4500

1

10

1112

1314

1516

2

34

56

78

9

21

CRITICAL

90-OHM-100MA

DLP11S

PLACEMENT_NOTE=Place FL4520 close to J4500

FL4520

12

3 4

CRITICAL

DLP11S

90-OHM-100MA

PLACEMENT_NOTE=Place FL4525 close to J4500

FL4525

1 2

34

20 90

20 90

20 90

20 90

SOT563

SSM6N15FEAPE

Q4596

3

5

4

5%
1/16W
MF-LF

100K

402

R4597

1

2

SOT563

SSM6N15FEAPE

Q4596

6

2

1

5%

1/16W

100K

402

MF-LF

R4596

1

2

402

100K

5%
1/16W
MF-LF

R4595

1 2

10%

402

CERM

0.068UF

10V

C4595

1

2

16V

10%

CERM

402

0.01UF

C4596

1 2

SOT-6

FDC606P_G

CRITICAL

Q4590

1 2 5 6

3

4

402

0.01UF

16V10%

CERM

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

C4521

1 2

402

CERM

10% 16V

0.01UF

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

C4520

1 2

402

CERM

10% 16V

0.01UF

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

C4526

1 2

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

0.01UF

16V10%

CERM

402

C4525

1 2

0603

CRITICAL

FERR-70-OHM-4A

L4500

1 2

10V
CERM

20%

402

0.1UF

C4501

1

2

DLP11S

90-OHM-100MA

CRITICAL

FL4501

12

3 4

402

10V

0.1UF

20%

CERM

C4502

1

2

90-OHM-100MA

CRITICAL

DLP11S

FL4502

1 2

34

20 90

20 90

20 90

20 90

10% 16V

0.01UF

402

CERM

C4516

1 2

0.01UF

16V10%

CERM

402

C4510

1 2

402

CERM

10% 16V

0.01UF

C4511

1 2

0.01UF

16V10%

CERM

402

C4515

1 2

QT500166-L020

M-ST-SM

CRITICAL

J4501

1

10
11 12
13 14
15 16

2

3 4
5 6
7 8
9

SYNC_DATE=05/01/2008

SYNC_MASTER=M98_MLB

SATA Connectors

45

123

31

051-7656

=PP3V3_S0_ODD

=PP5V_S0_ODD

=PP5V_S0_HDD

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_UF_N

SATA_HDD_R2D_UF_P

SATA_HDD_R2D_C_P

SATA_HDD_R2D_UF_N

SATA_HDD_R2D_C_N

SATA_HDD_D2R_C_P

SATA_HDD_D2R_C_N

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SATA_HDD_R2D_P

SATA_HDD_R2D_N

PP5V_S0_HDD_FLT

SMC_ODD_DETECT

=PP3V3_S0_ODD

VOLTAGE=5V

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm

PP5V_SW_ODD

ODD_PWR_EN

ODD_PWR_EN_LS5V_L

SATA_ODD_R2D_N

SATA_ODD_D2R_N

ODD_PWR_SS

SATA_ODD_R2D_UF_P

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_UF_N

SATA_ODD_D2R_UF_P

ODD_PWR_EN_L

SATA_ODD_R2D_P

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_P

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

PLACEMENT_NOTE=Place FL4501 close to J4501

PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

PLACEMENT_NOTE=Place C4516 close to J4501

PLACEMENT_NOTE=Place C4510 close to MCP79

PLACEMENT_NOTE=Place C4511 next to C4510

PLACEMENT_NOTE=Place C4515 next to C4516

38

90

90

90

90

38

90

90

90

90

8

8

8

96

96

96

96

7

7

7

7

7

8

7

7

96

96

96

7

96

7

7

Preliminary

OUT

BI

BI

SYM_VER-1

IN
OUT

IN

SYM_VER-1

BI

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

OUT2

TPAD

GND

OUT1

OC1*

EN2

EN1
OC2*

IN

VCC

GND

SELOE*

D+
D-

Y+
Y-

M+
M-

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

SEL=0 Choose SMC

Left USB Port A

Left USB Port B

USB/SMC Debug Mux

Port Power Switch

SEL=1 Choose USB

We can add protection to 5V if we want, but leaving NC for now

Place L4600 and L4605 at connector pin

0603

FERR-220-OHM-2.5A

CRITICAL

L4605

1 2

CASE-B2-SM

POLY-TANT

100UF

20%

CRITICAL

6.3V

C4696

1

2

10UF

20%

603

X5R

6.3V

C4695

1

2

0.1UF

402

CERM

10V

20%

C4691

1

2

20

20 91

20 91

CERM

402

10V

0.1UF

SMC_DEBUG_YES

20%

C4650

1

2

1/16W
MF-LF

5%

10K

402

R4650

1

2

DLP11S

CRITICAL

90-OHM-100MA

L4600

1 2

34

7

41 42 43

7

41 42 43

41

402

5%

0

MF-LF

1/16W

SMC_DEBUG_NO

R4651

1 2

SMC_DEBUG_NO

0

402

5%
1/16W
MF-LF

R4652

1 2

16V
402

0.01uF

CERM

20%

C4605

1

2

402

CERM

16V

0.01uF

20%

C4615

1

2

CRITICAL

0603

FERR-220-OHM-2.5A

L4615

1 2

90-OHM-100MA

CRITICAL

DLP11S

L4610

1 2

34

6.3V
X5R

10UF

603

20%

C4617

1

2

CASE-B2-SM

6.3V
POLY-TANT

100UF

CRITICAL

20%

C4616

1

2

20 91

20 91

20

RCLAMP0502N

CRITICAL

SLP1210N6

D4600

1

5 42 3

6

SLP1210N6

RCLAMP0502N

CRITICAL

D4610

1

5 42 3

6

603

10UF

X5R

20%

6.3V

C4690

1

2

OMIT

USB

CRITICAL

F-RT-TH-M97-3

J4600

1

2

3

4

5

6

7

8

OMIT

F-RT-TH-M97-3

USB

CRITICAL

J4610

1

2

3

4

5

6

7

8

CRITICAL

MSOP

TPS2064DGN

Q4690

3

4

1

2

8

5

7

6

9

402

1/16W

5.1K

MF-LF

5%

R4690

1

2

10%
10V

402

X5R

0.47UF

C4692

1

2

TQFN

SMC_DEBUG_YES

CRITICAL

SIGNAL_MODEL=USB_MUX

PI3USB102ZLE

U4650

6

7

3

4

5

8

10

9

2

1

SYNC_MASTER=M98_MLB

External USB Connectors

051-7656

31

123

46

SYNC_DATE=07/14/2008

2

J4600, J4610

CONN,RCPT,USB,HB,4P

514-0638 CRITICAL

USB_EXTB_N

USB2_EXTA_MUXED_P

USB_LT2_P

USB_LT2_N

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

USB2_EXTA_MUXED_N

=PP5V_S3_RTUSB

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm

PP5V_S3_RTUSB_B_F

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB2_LT1_N

USB2_LT1_P

USB_EXTB_OC_L

USB_EXTA_N

USB_EXTA_P

SMC_RX_L
SMC_TX_L

=PP3V42_G3H_SMCUSBMUX

USB_PWR_EN

PM_SLP_S4_L

USB_EXTB_P

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB_EXTA_OC_L

USB_DEBUGPRT_EN_L

67 42

96

96

98

96

96

41

96

7

7

96

8

7

7

7

7

8

21

Preliminary

BI
BI

VCC

P1.0/D+
P1.1/D­P1.2/VREG
P1.3/SSEL
P1.4/SCLK

P1.5/SMOSI

P1.6/SMISO

P0.0

P0.1
INT0/P0.2
INT1/P0.3

TIO1/P0.6

NC

TIO0/P0.5

INT2/P0.4

VSSPAD

THRML

IN

NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

20 91

20 91

402-1

1UF

10%
10V
X5R

C4803

1

2

QFN

CRITICAL

OMIT

CY7C63803-LQXC

U4800

5
4
3

8

9
10
20
21
22
23
24

7
6

12
13
15
16
17
18
19

25

2
1

14

11

0.1UF

402

16V

10%

X7R-CERM

C4801

1

2

CERM

0.001UF

50V

402

10%

C4804

1

2

402

1/16W

100

5%

MF-LF

R4800

1 2

7

40

F-RT-SM

CRITICAL

FF18-6A-R11AD-B-3H

J4800

1
2
3
4
5
6

PLACE C4805 NEAR J4800

16V

402

0.1UF

X7R-CERM

10%

C4805

1

2

PLACE C4806 NEAR J4800

402

0.1UF

16V

10%

X7R-CERM

C4806

1

2

PLACE C4807 NEAR J4800

402

CERM

0.001UF

50V

10%

C4807

1

2

5%

10

402

1/16W

MF-LF

PLACE R4805 NEAR J4800

R4805

1 2

10

5%

402

1/16W

MF-LF

PLACE R4806 NEAR J4800

R4806

1 2

PLACE C4808 NEAR J4800

402

CERM

0.001UF

50V

10%

C4808

1

2

402

MF-LF

1/16W

100

5%

PLACE R4807 NEAR J4800

R4807

1 2

PLACE R4808 NEAR J4800

5%

1/16W

MF-LF

402

4.7

R4808

1 2

R4801

402

21
NONE
NONE

NONE

SHORT

Front Flex Support

051-7656

31

123

48

SYNC_DATE=07/18/2008

SYNC_MASTER=CHANG_K20

SYS_LED_ANODE

SMC_LID

=PP5V_S3_IR

SYS_LED_ANODE_R

=PP3V42_G3H_LIDSWITCH

PP3V42_G3H_LIDSWITCH_R

IR_RX_OUT

SMC_LID_R

PP5V_S3_IR_R

USB_IR_P

DIFFERENTIAL_PAIR=USB2_IR

IR_VREF_FILTER

IR_RX_OUT

IR_RX_OUT_RC

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_N

=PP5V_S3_IR

PP5V_S3_IR_USB

P/N 338S0633

518S0692

49

42

42

40

40

40

7

41

8

7

8

7

7

7

7

8

Preliminary

IN

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN
IN
IN
IN
IN
IN
IN
IN

IN

IN

OUT

IN

OUT

BI

IN

IN

OUT

BI
OUT

IN

IN

OUT

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN

IN
IN

IN

IN

IN
IN

IN

IN

IN

IN

OUT

IN

IN

BI
BI
BI
BI
BI
BI

OUT
OUT

OUT

IN

IN

OUT

IN

IN

BI

BI

OUT

IN

OUT

OUT

P13
P14
P15
P16 P66

P10
P11
P12

P17

P20
P21
P22
P23
P24
P25
P26
P27

P30
P31
P32
P33
P34

P36
P37

P40
P41
P42
P43
P44
P45
P46
P47

P50
P51
P52

P60
P61
P62
P63
P64
P65

P67

P70
P71
P72
P73
P74
P75
P76
P77

P80
P81

P84
P85
P86

P90
P91
P92
P93
P94
P95
P96
P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0
PA1
PA2
PA3

PA6
PA7

PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7

PE0
PE1
PE2
PE3
PE4
PF0

PF1
PF2
PF3
PF4
PF5
PF6
PF7

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7

PH0
PH1
PH2
PH3
PH4
PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

NC

OUT

OUT

OUT

NC

NC
NC
NC

NC

NC

NC

NC
NC

NC
NC
NC

NC

NC

NC

NC

NC

NC
NC

NC
NC

NC

NC
NC

IN

OUT

OUT

OUT

OUT

BI
BI
BI
BI

IN
IN
IN

OUT

BI

IN
IN
IN
IN

BI

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(OC)

(OC)

NOTE: P94 and P95 are shorted, P95 could be spare.

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

pins designed as outputs can be left floating,

(OC)

(OC)

(OC)

(OC)
(OC)

(OC)
(OC)

(OC)

(OC)

(OC)

NOTE: Unused pins have "SMC_Pxx" names. Unused

(See below)

SMC_PB3:

SMC_IG_THROTTLE_L for MG systems.
Otherwise, TP/NC okay (was ISENSE_CAL_EN)

those designated as inputs require pull-ups.

(OC)

(OC)

(OC)

(OC)

(DEBUG_SW_1)
(DEBUG_SW_2)

22UF

805

CERM

20%

6.3V

C4902

1

2

7

19 43

7

42 43

7

42 49

10%

402

CERM-X5R

0.47UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

6.3V

C4907

1

2

10V
402

0.1UF

CERM

20%

C4903

1

2

10V

402

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

0.1UF

CERM

20%

C4920

1

2

402

MF-LF

5%

1/16W

4.7

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

R4999

1 2

10V
402

0.1UF

CERM

20%

C4904

1

2

SM

XW4900

12

21

61

10V
402

0.1UF

CERM

20%

C4905

1

2

21

67

25 67 84

42

10V
402

0.1UF

CERM

20%

C4906

1

2

45

45

46

45

45

45

45

42

7

42 59

42 59

7

39 41 42 43

7

39 41 42 43

67

44

402

1/16W

5%

MF-LF

10K

R4909

1

2

7

43

7

43

402

1/16W

5%

10K

MF-LF

R4901

1

2

402

10K

MF-LF

5%
1/16W

R4902

1

2

402

1/16W

5%

MF-LF

0

NO STUFF

R4903

1

2

402

1/16W

5%

MF-LF

10K

R4998

1

2

39

42 59

21

7

38

31 42

21

42

48

48

42

42

42

42

48

48

51

51

42

51

42

42

42

7

42 43

42

7

42 43

7

42 43

7

42 43

40 42 49

44

44

44

44

44

44

42

42

42

42

7

39 41 42 43

7

39 41 42 43

42

75

7

19 43

21 27 28

7

25

7

43

21

7

19 43

LGA-HF

OMIT

HS82117

U4900

B12

A13
A12

B13

D11
C13

C12

D10

D13

E11

D12
F11

E13

E12
F13

E10

A9

D9
C8

B7
A8

D8

D7
D6

D4

A5

B4
A1

C2
B2

C1

C3

G2
F3

E4

L13

K12
K11

J12

K13
J10

J11

H12

N10

M11

L10
N11

N12

M13
N13

L12

A7

B6
C7

D5
A6

B5

C6

J4
G3

H2

G1
H4

G4
F4

F1

HS82117

OMIT

LGA-HF

U4900

N3

N1

M3
M2

N2

L1
K3

L2

B8

C9
B9

A10
C10

B10

C11
A11

G11

G13

F12
H13

G10
G12

H11

J13

M10

N9

K10

L8
M9

N8

K9
L7

K1

J3

K2
J1

K4

K5

N5
M6

L5

M5
N4

L4
M4

M8

N7

K8
K7

K6

N6
M7

L6

E2
F2

J2

A4
B3

C4

HS82117

LGA-HF

OMIT

U4900

M12

L11

L9

H3

A2

D1
H1

E5

E3

D3

B1M1H10

E1

D2

L3

F10

B11

C5

A3

75

51

21 33 36 42

42

42

42

9

31

7

19 43 84 91

7

19 43 84 91

7

19 43 84 91

7

19 43 84 91

7

19 43 84 91

25

25 91

50

44

7

21 33 36 67 82 84

21 39 42 67

42

25 91

44

44

42

SYNC_DATE=06/06/2008

SYNC_MASTER=T18_MLB

051-7656

31

123

49

SMC

LPC_FRAME_L

SMB_MGMT_DATA

SMC_RX_L
SMB_0_S0_CLK

SMC_RUNTIME_SCI_L

SMB_B_S0_CLK

SMC_PROCHOT

SMC_MCP_SAFE_MODE

=SMC_SMS_INT

SMB_BSA_CLK

SMC_THRMTRIP

SMC_SYS_LED

SMC_CASE_OPEN

SMC_P24

SMC_TX_L

SMB_BSA_DATA

SMB_A_S3_CLK

ALS_GAIN

SMC_LID

SMC_CPU_ISENSE

SMC_ADAPTER_EN

LPC_AD<0>

PM_PWRBTN_L

PM_RSMRST_L

SMC_TDO

SMC_P26

SMC_TCK

SMC_TMS

PM_CLK32K_SUSCLK

PM_SLP_S3_L

SMC_BS_ALRT_L

SMC_CPU_VSENSE

SMC_PM_G2_EN

SMB_B_S0_DATA

SMB_A_S3_DATA

SMC_TDI

SMC_XTAL
SMC_EXTAL

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM

SMC_TRST_L

SMC_MD1

SMC_KBC_MDE

SMC_VCL

SMC_NMI

SMC_RESET_L

=PP3V3_S5_SMC

PP3V3_S5_AVREF_SMC

SMB_0_S0_DATA

PM_SLP_S4_L

ALS_RIGHT

GND_SMC_AVSS

SMC_BIL_BUTTON_L

SMC_PROCHOT_3_3_L

SMC_WAKE_SCI_L

SMC_NB_MISC_ISENSE

SMC_BATT_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

SMC_GPU_ISENSE
SMC_GPU_VSENSE

PM_CLKRUN_L

SMC_BC_ACOK

PM_SLP_S5_L

SMC_ONOFF_L

SMB_MGMT_CLK

SMC_RX_L

LPC_PWRDWN_L

SMC_PH2

SMC_EXCARD_PWR_EN

LPC_CLK33M_SMC

SMC_P41

SMC_GFX_OVERTEMP_L

SMC_FAN_3_CTL
SMC_FAN_0_TACH

SMS_Y_AXIS
SMS_Z_AXIS
SMC_ANALOG_ID
SMC_NB_CORE_ISENSE

ALS_LEFT

SMC_NB_DDR_ISENSE

SMS_X_AXIS

SMC_FAN_3_TACH

SMC_FAN_2_TACH

SMC_FAN_1_TACH

SMC_FAN_2_CTL

SMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_EXCARD_OC_L

SMC_EXCARD_CP

SMC_PB3

SMC_ODD_DETECT

PM_BATLOW_L

SYS_ONEWIRE

SMC_PA5

MEM_EVENT_L

USB_DEBUGPRT_EN_L

SMC_PA1

LPC_AD<1>

PM_SYSRST_L

SMC_PA0

LPC_SERIRQ

LPC_AD<3>

ESTARLDO_EN

SMC_RSTGATE_L

SMC_SYS_KBDLED

SMC_TX_L

SMC_GFX_THROTTLE_L

SMS_ONOFF_L

SMC_LRESET_L

LPC_AD<2>

IMVP_VR_ON

RSMRST_PWRGD

ALL_SYS_PWRGD

51

46

42

42

45

42

42

42

42

8

7

42

42

42

42

42

42

42

Preliminary

D

S G

CD

GND

NC

OUT

IN

OUT

IN

OUT

BI

OUT

IN

D

S G

GND

OUT

IN

OUT

IN

IN

OUT

02

D

SG

D

SG

NC

NC

NC

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

System (Sleep) LED Circuit

SMC AVREF Supply

SMC Crystal Circuit

TO CPU

TO SMC

SMC FSB to 3.3V Level Shifting

Debug Power "Button"

PLACE R5015,R5001 ON BOTTOM SIDE

SMC Reset "Button" / Brownout Detect

402

CERM

20%

0.1uF

10V

C5000

1

2

SOT563

SSM6N15FEAPE

Q5059

3

5

4

6.3V

402

10%

0.47UF

CERM-X5R

C5020

1

2

16V

10%

402

0.01UF

CERM

C5026

1

2

603

20%

6.3V

10uF

X5R

C5025

1

2

MF-LF

5%

402

1/16W

0

R5095

1 2

402

MF-LF

5%

1/16W

10K

R5070

1 2

402

1/16W5%MF-LF

100K

R5071

1 2

402

1/16W MF-LF

5%

10K

R5072

1 2

MF-LF

5%

1/16W

402

10K

R5073

1 2

5%

MF-LF1/16W

402

100K

R5074

1 2

2.0K

MF-LF

5%

1/16W

402

ONEWIRE_PU

R5075

1 2

MF-LF

5%

1/16W

100K

402

R5076

1 2

MF-LF

5%

1/16W

10K

402

R5077

1 2

10K

1/16W5%MF-LF

402

R5078

1 2

10K

5%

1/16W MF-LF

402

R5079

1 2

10K

5%

402

MF-LF1/16W

R5080

1 2

402

MF-LF1/16W

5%

10K

R5085

1 2

5%

402

MF-LF1/16W

10K

R5086

1 2

5%

1/16W

10K

402

MF-LF

R5088

1 2

SOT23-5-HF

CRITICAL

NCP303LSN

U5000

5

3

2

4

1

5%

100K

402

MF-LF1/16W

R5090

1 2

7

41 43

41

10 14 88

SILK_PART=SMC_RST

603

MF-LF

0

5%
1/10W

OMIT

R5001

1

2

1/10W

0

MF-LF

5%

OMIT

603

SILK_PART=PWR_BTN

R5015

1

2

SOT563-HF

BC847BV-X-F

Q5060

2

6

1

MF-LF

1/16W

5%

402

3.3K

R5061

1

2

1/16W

402

3.3K

5%

MF-LF

R5062

1 2

470

402

MF-LF

1/16W

5%

R5060

1

2

10 14 61 88

41

41

SOT563

SSM6N15FEAPE

Q5059

6

2

1

100K

1/16W5%MF-LF

402

R5091

1 2

100K

MF-LF

5%

1/16W

402

R5092

1 2

REF3333

SOT23-3

CRITICAL

VR5020

3

1 2

41 20 31

1/16W

5%

1K

402

MF-LF

R5000

1

2

1/16W MF-LF

402

10K

5%

R5089

1 2

41

1%

1/16W

402

MF-LF

1.47K

R5032

1

2

1%

20

402

MF-LF

1/16W

R5030

1

2

1%

402

1/16W

523

MF-LF

R5031

1

2

SOD

2SA2154MFV-YAE

CRITICAL

Q5030

1

3

2

7

40

1/16W MF-LF

402

5%

10K

R5081

1 2

5%

0

402

MF-LF

1/16W

R5010

1 2

5X3.2-SM

20.00MHZ

CRITICAL

Y5010

1

2

402

5%

50V

CERM

15pF

C5011

1 2

402

50V

CERM

5%

15pF

C5010

1 2

SOT563-HF

BC847BV-X-F

Q5060

5

3

4

5%

1/16W

402

MF-LF

470K

R5087

1 2

SN74LVC1G02

SOT553-5

U5001

1

2

3

5

4

SOT563

SSM6N15FEAPE

Q5032

3

5

4

SSM6N15FEAPE

SOT563

Q5032

6

2

1

SOT-553

74LVC1G17DRL

U5050

2

3 1

5

4

402

25V
X7R

10%

0.01UF

C5051

1

2

402

X5R

16V

10%

0.1UF

C5050

1

2

MF-LF

5%

402

1/16W

10K

R5051

1 2

7

41 42 49

10%
16V

CERM

402

0.01UF

C5001

1

2

31

123

50

SYNC_DATE=05/01/2008

051-7656

SMC Support

SYNC_MASTER=M98_MLB

353S1912 Intersil ISL60002-33

ALL

353S1381

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_FAN_3_CTL

SMC_FAN_2_CTL

SMC_FAN_2_TACH

SMC_FAN_3_TACH

ESTARLDO_EN

SMC_BC_ACOK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

CPU_PROCHOT_L

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

SMC_CPU_FSB_ISENSE

MAKE_BASE=TRUE

SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

SMC_NB_DDR_ISENSE

SMC_NB_MISC_ISENSE

=PP3V3_S5_SMC

SMC_P24

SMC_P26

SMC_P41

ALS_GAIN

SMC_PB3

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

=PP5V_S3_SYSLED

SYS_LED_L_VDIV

SMC_SYS_LED

SYS_LED_L

SMC_TPAD_RST

=CHGR_ACOK

PP3V42_G3H

SMC_BIL_BUTTON_DB_L

SMC_TPAD_RST_L

SMC_ONOFF_L

SMC_ANALOG_ID

NC_ESTARLDO_EN

MAKE_BASE=TRUE

SMC_PA1

=PP1V05_S0_SMC_LS

=PP3V3_S0_SMC

PM_SLP_S4_L

SMC_PA0

SMC_ONOFF_L

SMC_LID

SMC_THRMTRIP

CPU_PROCHOT_L_R

SMC_PROCHOT_3_3_L

CPU_PROCHOT_BUF

SMC_PROCHOT

SMC_CASE_OPEN

SMC_EXCARD_CP

=PP3V3_S5_SMC

SMC_ADAPTER_EN

=PP3V3_S0_SMC

SYS_LED_ILIM

SYS_LED_ANODE

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

ALS_LEFT

MAKE_BASE=TRUE

SMC_MCP_VSENSE

ALS_RIGHT

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

NC_ALS_GAIN

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

SMC_EXTAL

=SMC_SMS_INT

SMC_ONOFF_L

SMC_XTAL_R

SMC_BIL_BUTTON_L

SMC_XTAL

VOLTAGE=3.3V

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

PM_THRMTRIP_L

EXCARD_OC_L

SMC_NB_CORE_ISENSE

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

SMC_PA5

PM_SLP_S5_L

SMC_RX_L

SMC_TX_L

SMC_PH2

SYS_ONEWIRE
SMC_BS_ALRT_L

SMC_TMS
SMC_TDO

SMC_TDI

SMC_TCK
SMC_BIL_BUTTON_L

SMC_BC_ACOK

SMC_RSTGATE_L

SMC_EXCARD_OC_L

SMS_INT_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL

SMC_RESET_L

SMC_MANUAL_RST_L

=PP3V3_S5_SMC

MIN_NECK_WIDTH=0.2 mm

GND_SMC_AVSS

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

=PPVIN_S5_SMCVREF

51

49

67

49

51

41

43

43

51

59

42

42

41

42

49

42

36

41

41

59

43

43

43

43

59

42

46

42

41

8

59

41

42

39

41

41

41

41

33

42

42

41

39

39

59

41

41

41

41

41

42

42

41

45

7

41

41

41

41

41

41

7

46

46

46

41

41

8

41

41

41

41

41

45

7

8

60

7

7

49

7

41

7

41

8

8

21

41

7

40

41

31

8

21

8

7

41 45

41 45

21

7

41

41

41

41

7

41 46

41

41

7

7

41

41

7

7

7

7

7

41

41

41

51

7

8

41

8

Preliminary

IN

OUT

IN

IN

OUT

IN

OUT

VCC

GND

SEL OE*

D+
D-

Y+
Y-

M+
M-

VCC

GND

SEL OE*

D+
D-

Y+
Y-

M+
M-

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

GS

D

IN

OUT

IN

OUT

OUT

IN

OUT

IN

BI

BI

OUT

IN

OUT

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

OUT

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MCP79 Internal SPI MUX Support

LPC+SPI Connector

NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON

MCP SPI Override Options

MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX

To Frank Card

From Frank Card

516S0573

Pull-up on debug card

Alternate SPI ROM Support

SPI MUX BYPASS

SEL HIGH OUTPUTS TO D (ON BOARD ROM)
SEL LOW OUTPUTS TO M (FRANKCARD ROM)

MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP

43 52

LPCPLUS_NOT

402

0

MF-LF

5%

1/16W

R5157

1 2

PLACEMENT_NOTE=PLACE NEXT TO U1400

5%

MF-LF

1/16W

0

402

MCP_CS1_YES&LPCPLUS_NOT

R5146

1 2

21 43 91

21 43 91

21 43 91

21 43 91

21 91

MF-LF

5%

1/16W

10K

402

R5190

1

2

43 52

LPCPLUS

PI3USB102ZLE

CRITICAL

TQFN

U5120

6

7

3

4

5

8

10

9

2

1

LPCPLUS

0.1UF

10V
402

CERM

20%

C5124

1

2

MCP_CS1_NO

0

5%

MF-LF

1/16W

402

R5127

1 2

MCP_CS1_NO

0

5%

1/16W

MF-LF

402

R5126

1 2

CRITICAL

PI3USB102ZLE

LPCPLUS

TQFN

U5110

6

7

3

4

5

8

10

9

2

1

0.1UF

CERM

20%
10V

402

LPCPLUS

C5114

1

2

43 52

43 52

43 52

7

43

7

43

MCP_CS1_NO

5%

MF-LF

1/16W

20K

402

R5144

1

2

52

43 52

7

43

7

43

7

39 41 42

21 43 91

7

41

MCP_CS1_YES

PLACEMENT_NOTE=PLACE NEXT TO U5120

402

5%

0

MF-LF

1/16W

R5147

1 2

7

18

7

39 41 42

7

41

MCP_CS1_NO

0

402

1/16W

5%

PLACEMENT_NOTE=Place near J5100

MF-LF

R5142

1 2

1/16W

5%

402

MF-LF

100K

R5140

1

2

MCP_CS1_YES

SOD-VESM-HF

SSM3J16FV

Q5140

3

1

2

MCP_CS1_YES

MF-LF

402

5%

1/16W

470

R5141

1

2

7

41

1/16W
MF-LF

5%

10K

402

R5191

1

2

7

41 42

7

19 41

7

19 41 84 91

7

43

7

43

7

19 41 84 91

7

19 41 84 91

55909-0374

CRITICAL

LPCPLUS

M-ST-SM

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

7

41 42

21 43 91

7

41 42

7

41 42

7

19 41

7

19 41

7

43

7

43

7

43

7

19 41 84 91

7

19 41 84 91

7

25 91

LPCPLUS_NOT

402

1/16W

5%

MF-LF

0

R5158

1 2

19

9

21

LPCPLUS_NOT

402

1/16W

5%

MF-LF

0

R5156

1 2

LPC+SPI Debug Connector

31

123

51

051-7656

SYNC_DATE=05/28/2008

SYNC_MASTER=CHANG_K20

SPI_CLK_R

SPI_MOSI_R

=PP3V3_S5_ROM

SPI_MOSI_MUX

SPI_MISO_MUX

SPI_CLK_MUX

SPI_MISO

SPI_CLK_R

SPI_MOSI_R

SPI_CS0_R_L

SPI_MISO

=PP3V3_S5_LPCPLUS

=PP3V3_S5_LPCPLUS

SPI_ALT_CS_L_MUX

SPI_MLB_CS_L_MUX

SPI_ALT_MISO

SPI_ALT_CLK
SPI_ALT_MOSI

SPI_MOSI_MUX

SPI_CLK_MUX

SPI_MISO_MUX

SPI_MLB_CS_L

=PP3V3_S5_ROM

SPI_ALT_CS_L

SMC_MD1
SMC_TX_L

=PP5V_S0_LPCPLUS

LPCPLUS_GPIO

SMC_NMI
SMC_RX_L

SPIROM_USE_MLB

MAKE_BASE=TRUE

SPI_CS1_R_L_USE_MLB

=PP3V3_S5_LPCPLUS

=PP3V3_S0_LPCPLUS

LPC_FRAME_R_L

LPC_FRAME_PU

SMC_TMS
DEBUG_RESET_L

SMC_TRST_L

SMC_TDO

LPC_AD<1>

LPC_AD<0>

SPI_ALT_MOSI

PM_CLKRUN_L

LPC_FRAME_L

SPI_ALT_MISO

=PP3V3_S5_LPCPLUS

SMC_RESET_L

LPC_AD<2>

LPC_CLK33M_LPCPLUS

LPC_AD<3>

SPIROM_USE_MLB
SPI_ALT_CLK
SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK

=SPI_CS1_R_L_USE_MLB

SPIROM_USE_MLB

52

52

43

43

43

43

43

43

43

43

8

8

8

8

8

7

8

8

8

7

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(Write: 0xA2 Read: 0xA3)

MCP79 SMBus "0" Connections

EMC1043-2: U5500

(WRITE: 0X9A READ: 0X9B)

SMC "B" SMBus Connections

MCP Temp

Battery Charger Temp

TMP102: U5540

(Write: 0x92 Read: 0x93)

SMC "0" SMBus Connections

MCP79 SMBus "1" Connections

U6800

(WRITE: 0X72 READ: 0X73)

Mikey

MCP79

The bus formerly known as "Battery B"

(Write: 0xA0 Read: 0xA1)

Battery Temp - (Write: 0x90 Read: 0x91)

SO-DIMM "A"

(MASTER)

J6955

Battery

(See Table)

EMC1043-1: U5570

(Write: 0x98 Read: 0x99)

CPU Temp

EMC1043-1: U5550

(Write: 0x98 Read: 0x99)

J3401

ALS

SMC

J3100

SMC

U4900

(MASTER)

U4900

GPU Temp (Ext)

HDCP ROM

U2690 or U2695

(Write: 0xA0-0xAE,

Read: 0xA1-0xAF)

J3200

SO-DIMM "B"

U4900

Battery LED Driver - (Write: 0x36 Read: 0x37)

Battery Manager - (Write: 0x16 Read: 0x17)

(MASTER)

(Write: 0x30 Read: 0x31)

(Write: 0x98 Read: 0x99)

Margin Control

U2900

Vref DACs

SMC

U4900

U2901

(MASTER)

TRACKPAD

(Write: 0x90 Read: 0x91)

J5800

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "A" SMBus Connections

U4900

(MASTER)

SMC

G96: U8000

GPU Temp (Int)

(Write: 0x70 Read: 0x71)

U5930

SMS

(Write: 0x9E Read: 0x9F) (Write: 0x72 Read: 0x73)

(MASTER?)

U1400

(MASTER)

U1400

J3500

ISL6258 - U7000

(Write: 0x12 Read: 0x13)

Battery Charger

SMC "Battery A" SMBus Connections

ExpressCard Slot

SMC

SMC "Management" SMBus Connections

Battery

MCP79

MF-LF

402

1/16W

5%

4.7K

1

2

R5200

1/16W

5%

MF-LF
402

4.7K

R5201

1

2

5%

4.7K

1/16W
MF-LF
402

R5291

1

2

1/16W

4.7K

402

5%

MF-LF

R5290

1

2

3.3K

402

MF-LF

5%
1/16W

R5261

1

2

5%

3.3K

1/16W
MF-LF

402

R5260

1

2

402

1/16W

4.7K

5%

MF-LF

R5251

1

2

MF-LF

4.7K

5%

402

1/16W

R5250

1

2

1K

402

MF-LF

1/16W

5%

R5280

1

2

1K

402

MF-LF

1/16W

5%

R5281

1

2

1K

5%
1/16W
MF-LF

402

R5270

1

2

1K

402

MF-LF

1/16W

5%

R5271

1

2

402

1.5K

5%
1/16W
MF-LF

R5230

1

2

MF-LF

1.5K

402

1/16W

5%

R5231

1

2

051-7656

123

52

31

SYNC_DATE=07/22/2008

SYNC_MASTER=BEN_K20

K20 SMBUS CONNECTIONS

=PP3V42_G3H_SMBUS_SMC_BSA

SMB_BSA_DATA

SMB_BSA_CLK

=SMBUS_CHGR_SDA

SMB_MGMT_CLK

SMB_MGMT_DATA

=I2C_VREFDACS_SCL

SMBUS_SMC_BSA_SDA

MAKE_BASE=TRUE

=SMBUS_EXCARD_SCL

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

=I2C_SODIMMB_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

=GPU_I2CS_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SCL

=PP3V3_S3_SMBUS_SMC_MGMT

=SMBUS_GPUTHMSNS_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

=SMBUS_BATT_SCL

SMB_B_S0_DATA

=PP3V3_S0_SMBUS_MCP_1

=I2C_HDCPROM_SDA

=I2C_SMS_SDA

=I2C_SMS_SCL

=I2C_TPAD_SDA

=I2C_TPAD_SCL

=I2C_PCA9557D_SDA

SMB_B_S0_CLK

=PP3V3_GPU_SMBUS_SMC_0_S0

=SMBUS_GPUTHMSNS_SCL

=I2C_HDCPROM_SCL

SMB_0_S0_CLK

SMB_0_S0_DATA

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

=I2C_SODIMMB_SCL

I2C_ALS_SCL

=GPU_I2CS_SDA

=SMBUS_BATT_SDA

=PP3V3_S0_SMBUS_MCP_0

SMB_A_S3_DATA

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

=PP3V3_S3_SMBUS_SMC_A_S3

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMB_A_S3_CLK

=I2C_MIKEY_SDA

=I2C_MIKEY_SCL

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

MAKE_BASE=TRUE

SMBUS_MCP_1_CLK

=PP3V3_S0_SMBUS_SMC_B_S0

=SMBUS_TMPSNSR_SDA

=SMBUS_TMPSNSR_SCL

=SMBUS_MCPTHMSNS_SDA

=SMBUS_MCPTHMSNS_SCL

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

I2C_ALS_SDA

=I2C_CPUTHMSNS_SDA

=I2C_CPUTHMSNS_SCLSMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

=SMBUS_CHGR_SCL

=SMBUS_EXCARD_SDA

MAKE_BASE=TRUE

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

MAKE_BASE=TRUE

91

91

21

21

91

91

13

13

8

41

41

60

41

41

26

31

28

94

76

94

94

26

26

8

47

94

59

41

8

24

51

51

50

50

26

41

8

47

24

41

41

27

27

28 30

76

59

8

41

8

41

58

58

21

21

8

47

47

47

47

94

30

47

47

94

60

31

7

7

Preliminary

OUT

N-CHN

S

D

G

P-CHN

G

D

S

IN

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

OUT

OUT

IN

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

OUT

IN-

IN+ REF

V+

GND

OUT

OUT

IN

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

U5303 only senses current up to 6.6A

REGULATOR SIDE:

Monitors battery discharge

INA214 has gain of 100V/V

current from battery to PBUS

LOAD SIDE:

MCP Voltage Sense / Filter

CPU Voltage Sense / Filter

GPU Voltage Sense / Filter

Place RC close to SMC

CPU VCore High Side Current Sensor

Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388

Place RC close to SMC

Place RC close to SMC

Place RC close to SMC

Place RC close to SMC

Place RC close to SMC

DCIN Current Sense Filter

Enables PBUS VSense divider when high.

Place short near U1000 center

CPU VCore Load Side Current Sense / Filter

Place RC close to SMC

Place short near U8000 center

Rthevenin = 4504 ohms

PBUS Voltage Sense & Filter

BMON Current Sense - Entire circuit must be near SMC (U4900)

100K

402

MF-LF

1/16W

5%

R5315

1

2

41

1%
1/16W
MF-LF

402

12.7K

R5385

1

2

20%

X5R
402

0.22UF

6.3V

C5385

1

2

6.98K

402

MF-LF

1/16W

1%

R5386

1

2

FDG6332CG

SC70-6

Q5315

6

2

1

FDG6332CG

SC70-6

Q5315

3

5

4

6.19K

1%
1/16W
MF-LF

402

R5331

1 2

61

100K

402

MF-LF

1/16W

5%

R5316

1

2

X5R
402

20%

6.3V

0.22UF

C5399

1

2

SM

PLACEMENT_NOTE=Place near U1400 center

XW5399

1 2

1/16W

402

1%

MF-LF

4.53K

R5399

1 2

42

402

17.4K

1%
1/16W
MF-LF

R5332

1

2

INA210

SC70

U5388

2

5

4

6

1

3

MF

0.001

1%
1W

1206

R5388

123

4

42

X5R

0.22UF

402

6.3V

20%

C5335

1

2

1%

402

1/16W
MF-LF

4.53K

R5335

1 2

8

8

0.1UF

CERM

10V

20%

402

C5388

1

2

BMON_ENG

0.1uF

20%
10V

402

CERM

C5369

1

2

41

0.22UF

X5R

20%

6.3V

402

C5390

1

2

42

4.53K

MF-LF

1/16W

402

1%

R5391

1 2

BMON_ENG

402

1/16W
MF-LF

100K

5%

R5371

1

2

NC7SB3157P6XG

BMON_ENG

SC70

U5313

43

1

2

6

5

BMON_PROD

0

1/16W
MF-LF

5%

402

R5330

12

60

402

10V

20%
CERM

0.1uF

BMON_ENG

C5318

1

2

60 96

60 96

SC70

INA214

BMON_ENG

U5303

2

5

4

6

1

3

41

402

0.22UF

X5R

20%

6.3V

C5359

1

2

4.53K

1%
1/16W
MF-LF

402

R5359

1 2

41

6.3V
X5R

20%

402

0.22UF

C5380

1

2

1%

MF-LF

402

1/16W

4.53K

R5380

1 2

60

41

0.22UF

402

20%

X5R

6.3V

C5330

1

2

SM

XW5359

1 2

41

4.53K

1%

402

1/16W
MF-LF

R5309

1 2

402

X5R

20%

0.22UF

6.3V

C5309

1

2

SM

XW5309

1 2

Current & Voltage Sensing

SYNC_MASTER=YWU_K20

SYNC_DATE=08/20/2008

53

123

31

051-7656

=PP3V42_G3H_BMON_ISNS

BMON_INA_OUT

CHGR_BMON

GND_SMC_AVSS

MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm

PPBUS_G3H_VSENSE

VOLTAGE=18.5V

SMC_CPU_VSENSE

BMON_AMUX_OUT

SMC_GPU_VSENSE

SMC_MCP_VSENSE

SMC_CPU_ISENSE

=PPVCORE_S0_CPU

=PPVIN_S5_CPU_IMVP_ISNS

=PPVIN_S5_CPU_IMVP_ISNS_R

GPUVSENSE_IN

CPUVCORE_HISIDE_IOUT

CHGR_AMON

SMC_DCIN_ISENSE

GND_SMC_AVSS

PPBUS_G3H

SMC_CPU_HI_ISENSE

GND_SMC_AVSS

PBUSVSENS_EN_L

ISNS_CPU_N

PBUSVSENS_EN_DIV

SMC_PBUS_VSENSE

GND_SMC_AVSS

GND_SMC_AVSS

GND_SMC_AVSS

ISNS_CPU_P

CPUVSENSE_IN

=PBUSVSENS_EN

GND_SMC_AVSS

IMVP6_IMON

=PPVCORE_GPU_REG

SMC_BATT_ISENSE

SMC_BMON_MUX_SEL

=PPVCORE_S0_MCP

=PP3V42_G3H_CPUCOREISNS

MCPVSENSE_IN

GND_SMC_AVSS

CHGR_CSO_R_N

CHGR_CSO_R_P

46

46

46

46

46

46

46

46

45

12

45

45

45

45

45

45

23

45

42

11

42

8

42

42

42

42

42

77

22

42

8

41

8

41

7

41

96

41

41

41

96

67

41

8

8

8

41

Preliminary

V+
V-

THRM

V+
V-

THRM

V+
V-

THRM

IN

IN

IN

OUT

OUT

OUT

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

OUT

IN

OUT

OUT

IN

V+
V-

THRM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Place RC close to SMC

MCP MEM VDD Current Sense Filter

MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share

MCP MEM VDD Current Sense

Gain: 274x

Place RC close to SMC

GPU VCore Current Sense

Place RC close to SMC

Gain: 274x

MCP VCore Current Sense Filter

GPU VCore Current Sense Filter

dual package opamp U5410

NC

NC

NC

NC

NC

NC

Place RC close to SMC

GPU 1.8V Current Sense Filter

1.05V CPU Current Sense Filter

OPA2333s for proto are placeholders for OPA2330

dual package opamp U5440

CPU FSB 1.05V Current Sense

GPU 1.8V Current Sense

Gain: 274x

Place RC close to SMC

MCP VCore Current Sense

GPU VCore Current Sense and GPU 1.8V Current Sense share

Gain: 1.4x

4.53K

402

1%
1/16W
MF-LF

R5475

1 2

OPA2333

DFN

U5410

5

6

7

9

4

8

OPA2333

DFN

U5440

3

2

1

9

4

8

OPA2333

DFN

U5440

5

6

7

9

4

8

64 96

64 96

65 96

42

0.22UF

20%

402

X5R

6.3V

C5490

1

2

MF-LF

1%

4.53K

402

1/16W

R5440

1 2

42

0.22UF

X5R

20%

6.3V

402

C5470

1

2

4.53K

1/16W

1%

MF-LF

402

R5470

1 2

42

0.22UF

402

X5R

20%

6.3V

C5435

1

2

4.53K

402

1%
1/16W
MF-LF

R5495

1 2

SC70

INA213

U5420

2

5

4

6

1

3

CERM

0.1UF

20%

402

10V

C5420

1

2

21

R5493

402

MF-LF

1/16W

1%

2.87K

10K

402

1%
1/16W
MF-LF

R5491

1 2

21

R5498

402

1/16W
MF-LF

1%

4.02K

6.3V

402

X5R

20%

0.22UF

C5465

1

2

470PF

CERM

10%
50V

402

C5498

1 2

77

42

3.65K

1%

402

MF-LF

1/16W

R5415

1 2

4.53K

1%

MF-LF

402

1/16W

R5465

1 2

0.002

CRITICAL

1206

1/4W

MF

1%

R5413

123

4

402

1M

MF-LF

1/16W

1%

SIGNAL_MODEL=EMPTY

R5411

1 2

402

50V

470PF

CERM

10%

SIGNAL_MODEL=EMPTY

C5411

1 2

0.1UF

20%

CERM

10V

402

C5410

1

2

1%

1M

1/16W
MF-LF
402

SIGNAL_MODEL=EMPTY

R5412

1

2

1/16W
MF-LF

3.65K

402

1%

R5414

1 2

470PF

402

10%
50V

CERM

SIGNAL_MODEL=EMPTY

C5412

1

2

8

8

402

10V
CERM

20%

0.1UF

C5440

1

2

402

CERM

10%
50V

SIGNAL_MODEL=EMPTY

470PF

C5441

1 2

SIGNAL_MODEL=EMPTY

MF-LF

1/16W

402

1%

1M

R5441

1 2

1/16W

1M

1%

SIGNAL_MODEL=EMPTY

MF-LF
402

R5442

1

2

402

CERM

470PF

50V

10%

SIGNAL_MODEL=EMPTY

C5442

1

2

8

MF

CRITICAL

1206

0.002

1%

1/4W

R5445

123

4

8

MF-LF

402

1/16W

1%

3.65K

R5444

1 2

41

1/16W

402

MF-LF

1%

3.65K

R5443

1 2

402

50V

470PF

10%

CERM

SIGNAL_MODEL=EMPTY

C5432

1 2

402

MF-LF

1/16W

1%

1M

SIGNAL_MODEL=EMPTY

R5432

1 2

402

MF-LF

1%

3.65K

1/16W

R5431

1 2

402

1%

MF-LF

1/16W

3.65K

R5436

1 2

1M

1%

MF-LF

1/16W

SIGNAL_MODEL=EMPTY

402

R5437

1

2

20%

0.22UF

6.3V
X5R
402

C5475

1

2

SIGNAL_MODEL=EMPTY

470PF

10%
50V

CERM

402

C5472

1

2

65 96

OPA2333

DFN

U5410

3

2

1

9

4

8

051-7656

31

123

54

SYNC_MASTER=YWU_K20

Current Sensing

SYNC_DATE=08/12/2008

GPUISENS_N

MCPDDR_IOUT

=PP3V3_S0_MCPCOREISNS

=PP3V3_S0_MCPDDRISNS

MCPCOREISNS_N

DDRISNS_N

=PPMCPDDR_ISNS

1V05CPUISNS_R_P

=PP1V8_S0GPU_ISNS_R

DDRISNS_R_N

1V05CPU_N

=PP3V3_S0_GPU1V8ISNS

SMC_GPU_1V8_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

SMC_GPU_ISENSE

SMC_CPU_FSB_ISENSE

SMC_MCP_CORE_ISENSE

MCPCORE_IOUT

GND_SMC_AVSS

GND_SMC_AVSS

GND_SMC_AVSS

P1V8_S0GPU_IOUT

P1V8GPU_P

P1V8GPU_N

P1V8GPUISNS_R_P

SMC_MCP_DDR_ISENSE

DDRISNS_P

CPU1V05_S0_IOUT

P1V8GPUISNS_R_N

DDRISNS_R_P

=PP1V8_S0GPU_ISNS

MCPCOREISNS_P

1V05CPUISNS_R_N

=PPMCPDDR_ISNS_R

1V05CPU_P

GPUISENS_P

GFXIMVP6_IMON

GPUVCORE_IOUT

46

46

46

46

46

45

45

45

45

45

42

42

42

42

42

96

8

8

96

96

96

8

41

41

41

41

41

96

96

96

96

96

96

96

96

Preliminary

BI

BI

BI

BI

BI

BI

GND

V+

ADD0

ALERT

SCL

SDA

DN1

DP1

GND

SMCLK

SMDATA

VDD

THERM*

DP2/DN3

DN2/DP3

ALERT*

THRM_PAD

DN1

DP1

GND

SMCLK

SMDATA

VDD

THERM*

DP2/DN3

DN2/DP3

ALERT*

THRM_PAD

BI

BI

DN1

DP1

GND

SMCLK

SMDATA

VDD

THERM*

DP2/DN3

DN2/DP3

ALERT*

THRM_PAD

BI

BI

BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Placement note:

Place U5500 near MCP

NOTE: U5500 Changed to EMC1403-2. Write Address: 0x9A

to IC pins as possible

Keep 2 caps as close

Placement note:

MCP Proximity/MCP Die/Right Heat Pipe

518S0519

Detect MCP Die Temperature

Detect Right Heat Pipe Temperature

CPU Proximity/CPU Die/Right Fin Stack

Placement note:

Place U5550 near GPU

Placement note:

Keep 2 caps as close
to IC pins as possible

Detect CPU Die Temperature

and close to left fin stack

Place U5570 under CPU

Placement note:

Detect Right Fin Stack Temperature

Place Q5501 on bottom side

Placement note:

Place U5540 near battery

close to right fin stack

TEMP SENSOR HAS ADDRESS WRITE:0X92, READ: 0X93

Note: EMC1403 can perform Beta

Compensation for External Diode 1 only

Placement note:

Place on top side under left heat pipe near CPU

Detect Left Heat Pipe Temperature

Battery Charger Proximity

charger circuit

Detect GPU Die Temperature

Placement note:

GPU Proximity/GPU Die/Left Heat Pipe

402

MF-LF

1/16W

5%

10K

R5572

1

2

1/16W

10K

MF-LF

5%

402

R5571

1

2

10V
CERM

0.1uF

20%

402

C5540

1

2

SOT732-3

BC846BMXXH

Q5501

1

3

2

10 96

10 96

44

44

5%

402

10K

1/16W
MF-LF

R5551

1

2

MF-LF

10K

1/16W

402

5%

R5552

1

2

CERM

10V

20%

0.1uF

402

C5550

1

2

47

1/16W

5%

MF-LF

402

R5550

1 2

0.0022uF

50V

402

CERM

10%

SIGNAL_MODEL=EMPTY

C5551

1

2

10%
50V

402

CERM

0.0022uF

SIGNAL_MODEL=EMPTY

C5552

1

2

75 96

75 96

SOT732-3

BC846BMXXH

Q5503

1

3

2

HPA00330AI

SOT563

U5540

4

3

2

1

6

5

DFN

EMC1403-1

CRITICAL

U5570

83

5

2

4

6

10

9

7

11

1

DFN

EMC1403-1

CRITICAL

U5550

83

5

2

4

6

10

9

7

11

1

M-RT-SM

78171-0002

J5502

3

4

1

2

21 96

21 96

1/16W
MF-LF

402

47

5%

R5500

1 2

0.0022uF

CERM

402

50V

10%

SIGNAL_MODEL=EMPTY

C5521

1

2

SIGNAL_MODEL=EMPTY

0.0022uF

CERM

10%
50V

402

C5511

1

2

DFN

EMC1403-2

CRITICAL

U5500

83

5

2

4

6

10

9

7

11

1

402

20%
10V
CERM

0.1uF

C5500

1

2

44

44

402

MF-LF

1/16W

10K

5%

R5501

1

2

402

1/16W

5%

10K

MF-LF

R5502

1

2

44

44

402

CERM

10V

20%

0.1uF

C5570

1

2

47

5%

402

1/16W
MF-LF

R5570

1 2

CERM

50V

10%

0.0022uF

402

SIGNAL_MODEL=EMPTY

C5590

1

2

402

50V

CERM

0.0022UF

10%

SIGNAL_MODEL=EMPTY

C5580

1

2

SYNC_MASTER=YWU_K20

SYNC_DATE=05/28/2008

55

123

31

051-7656

Thermal Sensors

=PP3V3_S0_BATTCHARGERTMPSNSR

=SMBUS_TMPSNSR_SCL

=SMBUS_TMPSNSR_SDA

CPU_THERMD_N

CPUTHMSNS_ALERT_L

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

CPUTHMSNS_THM_L

CPU_THERMD_P

PP3V3_S0_CPUTHMSNS_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

VOLTAGE=3.3V

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_GPUTHMSNS

GPU_TDIODE_N

GPUTHMSNS_D_P

GPUTHMSNS_D_N

GPU_TDIODE_P

=SMBUS_GPUTHMSNS_SDA

=SMBUS_GPUTHMSNS_SCL

GPUTHMSNS_ALERT_L

GPUTHMSNS_THM_L

VOLTAGE=3.3V

PP3V3_S0_GPUTHMSNS_R

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N

MCPTHMSNS_D_P

MCP_THMDIODE_N

=PP3V3_S0_REMTHMSNS

MCPTHMSNS_D_N

MCP_THMDIODE_P

=SMBUS_MCPTHMSNS_SDA

REMTHMSNS_THM_L

REMTHMSNS_ALERT_L

=SMBUS_MCPTHMSNS_SCL

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP3V3_S0_REMTHMSNS_R

VOLTAGE=3.3V

96

96

8

44

44

8

8

96

96

96

96

7

8

7

Preliminary

G

S D

G

S D

IN

OUT OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0521 518S0521

Left Fan

Right Fan

1/16W

47K

402

5%

MF-LF

R5650

1

2

1/16W

5%

MF-LF

402

47K

R5655

1 2

402

MF-LF

47K

5%

1/16W

R5660

1

2

402

47K

MF-LF

1/16W

5%

R5665

1 2

402

MF-LF

5%

1/16W

100K

R5651

1

2

2N7002DW-X-G

SOT-363

Q5660

3

5

4

100K

5%

MF-LF

402

1/16W

R5661

1

2

2N7002DW-X-G

SOT-363

Q5660

6

2

1

M-RT-SM

CRITICAL

78171-0004

J5650

5

6

1
2
3
4

78171-0004

CRITICAL

M-RT-SM

J5660

5

6

1
2
3
4

41

41 41

41

Fan Connectors

31

051-7656

123

56

SYNC_MASTER=M98_MLB

SYNC_DATE=04/01/2008

SMC_FAN_0_TACH

=PP3V3_S0_FAN_LT

=PP5V_S0_FAN_LT

FAN_LT_TACH

=PP3V3_S0_FAN_RT

FAN_RT_TACH

=PP5V_S0_FAN_RT

FAN_RT_PWM

SMC_FAN_0_CTL

SMC_FAN_1_TACH

SMC_FAN_1_CTL

FAN_LT_PWM

8 8 7

7

8

7

8

7 7

Preliminary

D

G S

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

Y

C

B

A

IN

OUT

Y

B

A

Y

B

A

Y

B

A

NC

NC

NC

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ISSP SDATA/I2C SDA

APN 518S0430

4MA (MAX)

4.7 OHM

CURRENT

75.2E-6 W

ISSP DATA

PSOC PROGRAMMING CONNECTOR

TEST POINTS ARE FOR ON BOARD PROGRAMMING

ISOLATION CIRCUIT

PSOC USB CONTROLLER

VDD PIN 49

CLOSE TO U5701

VDD PIN 22

CLOSE TO U5701

PLACE C5701, C5702 & C5703

TO MLB CONNECTOR

TRACKPAD PICK BUTTONS

VOUT

KEYBOARD SCANNER

APN 337S2983

APN 311S0406

USB INTERFACES TO MLB

PLACE THESE COMPONENTS CLOSE TO J5800

U5701 CHIP DECOUPLING

TMP102

THE TPAD BUTTONS WILL BE DISABLE

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V

LID CLOSE => SMC_LID_LC < 0.50V

APN 518S0637

96E-6 W

0.72E-3 W

36E-3 W

16.32E-6 W

0.255E-6 W

0.0255 V

0.6 V

0.012 V

0.012 V

0.021 V

POWERV_SNS

1.5 OHM

0.2 OHM

10 OHM

10UA
80UA
60MA MAX
60MA MAX

8MA (TYP)

14MA (MAX)

VIN

VDD

VDD

V+

IC

3V3 LDO

PSOC

18V BOOSTER

ISSP CLOCK

ISSP SCLK/I2C SCL

PLACE C5704, C5705 & C5706

SPI HOST TO Z2

0.0188 V

294E-6 W

0.204 V

R_SNS

TPAD BUTTONS DISABLE

SMC_MANUAL_RESET LOGIC

KEYBOARD CONNECTOR

2.55 KOHM

PIN NAME

SOD-VESM-HF

SSM3K15FV

Q5701

3

1

2

402

10%
16V

0.1UF

X7R-CERM

C5758

1

2

33K

402

1/16W
MF-LF

5%

R5771

1

2

33K

402

1/16W

5%

MF-LF

R5770

1

2

33K

1/16W

5%

402

MF-LF

R5769

1

2

603

X5R

6.3V

20%

4.7UF

C5706

1

2

10%
16V
X7R-CERM

0.1UF

402

C5705

1

2

402

CERM

50V

100PF

5%

C5704

1

2

16V
X7R-CERM

10%

0.1UF

402

C5703

1

2

402

CERM

50V

5%

100PF

C5702

1

2

6.3V

603

X5R

4.7UF

20%

C5701

1

2

MF-LF

1/16W

5%

402

24

R5702

1 2

OMIT

CY8C24794

MLF

CRITICAL

U5701

20

21

45544653475248

51

25182617271628

15

41

2

42

1

435644

55

3310

34

9

35

8

36

7

37

6

38

5

39

4

40

3

2914

3013

3112

3211

24

235722 49

19

50

402

MF-LF

5%

24

1/16W

R5701

1 2

SC70

SN74LVC1G10

CRITICAL

U5703

2

1
3
6

4

5

402

1/16W

1.5

5%

MF-LF

R5704

1 2

40 41 42

CERM

PLACEMENT_NOTE=NEAR J5713

20%

0.1UF

10V

402

C5710

1

2

402

MF-LF

1/16W

5%

1K

R5710

1 2

470

1/16W

402

MF-LF

1%

R5714

1 2

1/16W
MF-LF

10K

402

1%

R5715

1 2

TPAD_DEBUG

CRITICAL

FH19C-4S-0.5SH25

F-RT-SM1

J5702

5

6

1
2
3
4

CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

J5713

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

TC7SZ08AFEAPE

SOT665

CRITICAL

U5726

2

1

3

5

4

SOT665

TC7SZ08AFEAPE

CRITICAL

U5727

2

1

3

5

4

CRITICAL

TC7SZ08AFEAPE

SOT665

U5725

2

1

3

5

4

402

10V

20%

CERM

0.1UF

C5725

12

20%
10V

CERM

402

0.1UF

C5726

12

0.1UF

10V

20%

402

CERM

C5727

12

WELLSPRING 1

SYNC_DATE=05/19/2008

31

051-7656

123

57

SYNC_MASTER=YMA_K20

=PP3V3_S3_TPAD

=PP3V42_G3H_TPAD

=PP3V3_S3_TPAD

BUTTON_DISABLE

=PP3V42_G3H_TPAD

ISSP_SCLK_P1_1

Z2_RESET
PSOC_MISO

PSOC_SCLK
Z2_MISO

TP_P4_5

WS_KBD18

WS_KBD16N

WS_KBD7

Z2_KEY_ACT_L

WS_KBD19

WS_CONTROL_KEY

WS_KBD13

TP_PSOC_P1_3

WS_KBD20

WS_KBD3

WS_KBD9

WS_KBD10

WS_KBD12

WS_KBD14

WS_KBD15_C

Z2_CS_L

WS_KBD22

WS_KBD11

Z2_SCLK

WS_KBD8

WS_KBD7

WS_CONTROL_KBD

WS_LEFT_OPTION_KBD

WS_KBD_ONOFF_L

=PP3V42_G3H_TPAD

WS_LEFT_SHIFT_KBD

WS_KBD23

WS_KBD22

WS_KBD19
WS_KBD20
WS_KBD21

WS_KBD9
WS_KBD10
WS_KBD11

WS_KBD13
WS_KBD14

WS_KBD17
WS_KBD18

WS_KBD6

WS_KBD5

WS_KBD4

WS_KBD3

WS_KBD2

WS_KBD1

WS_KBD8

WS_LEFT_SHIFT_KEY

WS_KBD16N

WS_KBD17

SMC_LID

WS_CONTROL_KBD

PSOC_MOSI

PSOC_F_CS_L

WS_KBD12

WS_KBD15_C

BUTTON_DISABLE

WS_KBD23

WS_KBD21

Z2_MOSI

SMC_TPAD_RST_L

WS_LEFT_OPTION_KBD

PP3V3_S3_PSOC

WS_LEFT_SHIFT_KBD

WS_LEFT_SHIFT_KEY

USB_TPAD_P

DIFFERENTIAL_PAIR=USB2_TPAD

WS_KBD16_NUM

WS_KBD15_CAP

SMC_ONOFF_L

PP3V3_S3_PSOC

USB_TPAD_R_P

DIFFERENTIAL_PAIR=USB2_TPAD
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D

WS_KBD1

WS_CONTROL_KEY

WS_LEFT_SHIFT_KBD

Z2_CLKIN

WS_KBD2

WS_LEFT_OPTION_KBD

WS_CONTROL_KBD

=PP3V42_G3H_TPAD

USB_TPAD_N

DIFFERENTIAL_PAIR=USB2_TPAD

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP3V3_S3_PSOC

=PP3V3_S3_TPAD

=PP3V3_S3_TPAD

ISSP_SDATA_P1_0

=PP3V42_G3H_TPAD

=PP3V3_S3_TPAD

=PP3V3_S3_TPAD

ISSP_SCLK_P1_1

WS_LEFT_OPTION_KEY

TP_P7_7

ISSP_SDATA_P1_0

WS_KBD6

WS_KBD5

WS_KBD4

USB_TPAD_R_N

DIFFERENTIAL_PAIR=USB2_TPAD
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D

TP_PSOC_SDA

TP_PSOC_SCL

Z2_DEBUG3

WS_LEFT_OPTION_KEY

Z2_HOST_INTN

PICKB_L

Z2_BOOT_CFG1

42

49

49

49

49

49

50

50

50

50

49

49

50

49

49

49

49

49

49

49

49

50

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

49

50

50

49

49

49

49

49

91

41

49

49

50

49

49

49

49

91

49

49

49

49

49

49

49

49

49

49

49

50

50

50

8

8

8

49

8

7

7

7

7

7

7

49

7

7

7

49

7

7

7

7

7

7

7

7

49

7

7

7

50

7

7

7

7

7

8

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

49

49

7

7

7

7

7

49

49

7

7

50

42

7

49

7

49

20

7

7

7

49

7

49

7

7

7

7

7

8

20

49

8

8

7

8

8

8

7

49

7

7

7

7

7

49

50

7

7

Preliminary

VDD

VOUT

GND

CE

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

SYM_VER-1

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- RIPPLE TO MEET ERS

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

- R5812,R5813,C5818 MODIFIED

BOOSTER DESIGN CONSIDERATION:

BOOSTER +18.5VDC FOR SENSORS

HIGH= keyboard backlight not present

APN 518S0691

Keyboard LED Driver

HF APN 152s0898

APN 353S1401

To detect Keyboard backlight, SMC will

LOW = keyboard backlight present

APN 353S1364

3V3 LDO FOR IPD

J5815 pin 1 is grounded
on keyboard backlight flex

IPD FLEX CONNECTOR

APN 516S0689

BOM OPTION: KBDLED_YES

tristate SMC_SYS_KBDLED:

R5853 ALWAYS PRESENT

APN 371S0313

- POWER CONSUMPTION

- DROOP LINE REGULATION

APN 152S0504

KBD BACKLIGHT CONNECTOR

CRITICAL

55560-0228

M-ST-SM

J5800

1

10

1112
1314
1516
1718
19

2

20

2122

34
56
78
9

2.2UF

X5R

10%

603

16V

C5853

1

2

MM3243DRRE

MLF

CRITICAL

VR5802

1

4

2

3

1/6W

402-HF

MF

1%

0.2

R5836

1

2

10%

16V

402

X7R-CERM

0.1UF

C5838

1

2

4.7UF

603

X5R

6.3V

20%

C5854

1

2

1/16W

402

10

1%

MF-LF

R5873

1 2

41

1/16W
MF-LF

5%

4.7K

402

R5854

1

2

MF-LF

1/16W

5%

470K

402

R5853

1

2

LT3491

DFN

CRITICAL

U5850

4

6

2

5

3

7

1

5%

MF-LF

402

1/16W

10K

NO STUFF

R5852

1

2

1/16W

MF-LF

402

10

1%

R5855

1

2

1UF

10%
35V

603

X5R

C5855

1

2

CRITICAL

F-RT-SM

FF18-4A-R11AD-B-3H

J5815

1

2

3

4

1/10W

603

5%

0

MF-LF

PLACEMENT_NOTE=under L5800 on top side

R5800

1 2

0

603

5%

MF-LF

R5801

1 2

PLACEMENT_NOTE=under L5800 on top side

1/10W

PLACEMENT_NOTE=NEAR J5800

NO STUFF

CRITICAL

SM-HF

0.01H-0.3A-80V

L5800

1

2 3

4

CERM
402

10V

20%

0.1UF

PLACEMENT_NOTE=NEAR J5800

C5800

1

2

1/16W
MF-LF

0

5%

402

R5806

1 2

1/16W
MF-LF

1M

1%

402

R5812

1

2

5%
50V
CERM

39PF

402

C5818

1

2

SOD-323

B0520WSXG

D5802

1 2

603-1

10%
25V
X5R

1UF

C5819

1

2

1/16W
MF-LF

1%

71.5K

402

R5813

1

2

402

1/16W

1%

MF-LF

100K

R5811

1

2

21

VLF3010AT-SM-HF

3.3UH-870MA

CRITICAL

L5801

0

5%

1/16W

MF-LF

402

R5805

1 2

CRITICAL

TPS61045

QFN

U5805

53

4

6

1

7

8

9

2

16V
X5R
603

10%

2.2UF

C5817

1

2

402

10%

X7R-CERM

16V

0.1UF

C5816

1

2

10UH-0.58A-0.35OHM

1098AS-SM

CRITICAL

L5850

1 2

X5R

16V

1UF

10%

603

C5850

1

2

31

051-7656

58

123

SYNC_DATE=09/24/2008

SYNC_MASTER=K20_MLB

WELLSPRING 2

SMC_KDBLED_PRESENT_L

PP5V_S3_TPAD_F

Z2_BOOST_EN

Z2_MISO

Z2_MOSI

Z2_DEBUG3

TPAD_GND_F

0.50MM

0.20MM

Z2_KEY_ACT_L

PSOC_F_CS_L

=I2C_TPAD_SDA

PP18V5_S3

0.50MM

0.20MM

=I2C_TPAD_SCL

PSOC_SCLK

PSOC_MOSI

PSOC_MISO

PICKB_L

Z2_CS_L

Z2_BOOST_EN
Z2_HOST_INTN

Z2_BOOT_CFG1
Z2_CLKIN

0.50MM

0.20MM

PP3V3_S3_LDO

Z2_RESET

Z2_SCLK

KBDLED_CAP

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP3V3_S3_LDO

PP5V_S3_VR

PP3V3_S3_LDO_R

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

PP5V_S3_TPAD_F

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP18V5_S3

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP5V_S3_BOOSTER

TPAD_GND_F

TPAD_GND_F

SMC_SYS_KBDLED

=PPVIN_S0_KBDLED

=PP3V3_S0_TPAD

KBDLED_ANODE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

SMC_KDBLED_PRESENT_L

KBDLED_SW

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.3 MM

SWITCH_NODE=TRUE

=PP5V_S3_TPAD

MIN_NECK_WIDTH=0.20MM

VOLTAGE=0V

TPAD_GND_F

MIN_LINE_WIDTH=0.50MM

VOLTAGE=5V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

PP5V_S3_TPAD_F

INPUT_SW

0.50MM

0.20MM

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

VOLTAGE=18.5V

PP18V5_S3_SW

BOOST_FB

MIN_LINE_WIDTH=0.50MM

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.20MM

BOOST_SW

50

50

49

49

50

49

49

50

49

49

49

49

49

50

49

49

50

49

50

50

50

50

50

50

7

50

7

7

49

7

7

7

7

44

7

44

7

7

7

7

7

7

49

7

7

7

7

49

7

50

7

7

7

8

8

7

7

8

7

50

Preliminary

OUT

FS
PD
ST

RES
RES

GND

NC

NC
NC

NC

NC
NC

VOUTX

VOUTY

VOUTZ

VDD

IN

VDDIO

SDI

SDO

VDD

GND

INT

SCK

RESERVED

CSB

NC

OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

Pull-up required if SMS_INT_L not used.

Stuff R5931 AND NoStuff R5932 to use U5930
NoStuff R5931 AND Stuff R5932 if U5930 is not used

Analog SMS

NC

NC

NC

NC

NC

NC

NC

Digital SMS

+Z (up)

+Y

+X

Front of system

placed on board top-side:

Desired orientation when

in correct orientation

Circle indicates pin 1 location when placed

+Y

+X

+Z (up)

NC

NC

Front of system

placed on board top-side:

Desired orientation when

in correct orientation

Circle indicates pin 1 location when placed

NC

NC

41

CERM

10%
16V

402

0.01UF

C5925

1

2

402

16V
CERM

10%

0.01UF

C5924

1

2

402

0.01UF

CERM

10%
16V

C5923

1

2

402

MF-LF

1/16W

5%

10K

R5921

1

2

AP344ALH

LGA

CRITICAL

U5920

1

7

3
6
9

11
13
16

5

15

4

2

14

12

10

8

1/16W

10K

402

MF-LF

5%

R5922

1

2

41

ENG_DIGSMS

402

X5R

16V

10%

0.1UF

C5932

1

2

ENG_DIGSMS

0.022UF

10%
CERM-X5R

402

16V

C5931

1

2

CRITICAL

273141043

ENG_DIGSMS

LGA

U5930

5

3

4

11

12

1

10

6

8

7

2

9

MF-LF

1/16W
402

10K

5%

ENG_DIGSMS

R5931

1

2

402

5%

PROD_DIGSMS

MF-LF

1/16W

10K

R5932

1

2

42

X5R

4V

10UF

20%

603

C5926

1

2

0.1UF

10%
16V
X5R
402

C5922

1

2

41

41

SYNC_MASTER=YWU_K20

59

123

31

051-7656

Sudden Motion Sensor (SMS)

SYNC_DATE=06/17/2008

=PP3V3_S3_SMS

=PP3V3_S3_SMS

=I2C_SMS_SCL

=PP3V3_S5_SMC

=I2C_SMS_SDA

SMS_INT_L

SMS_Z_AXIS

SMS_X_AXIS

SMS_Y_AXIS

SMS_PWRDN

MAKE_BASE=TRUE

SMS_SELFTEST

SMS_ONOFF_L

42

51

51

41

8

8

44

8

44

Preliminary

IN

OUT

ININ

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

42 MHz

1 MHz

25 MHz

31 MHz

1

0

1

0

1

0

1

0

MCP79 SPI Frequency Select

Frequency

SPI_MOSI

SPI_CLK

43

10K

1/16W

5%
MF-LF

402

NO STUFF

R6191

1

2

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6105

1 2

43

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6152

1 2

43 43

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6150

1 2

MF-LF

5%

1/16W

10K

402

NO STUFF

R6190

1

2

32MBIT

MX25L3205DM2I-12G

CRITICAL

OMIT

SOP

U6100

1

4

7

6

5

2

8

3

5%

3.3K

1/16W
MF-LF

402

R6100

1

2

402

MF-LF

3.3K

5%
1/16W

R6101

1

2

20%

402

CERM

10V

0.1UF

C6100

1

2

61

123

31

051-7656

SPI ROM

SYNC_MASTER=M98_MLB

SYNC_DATE=05/01/2008

SPI_MOSI_MUX

SPI_MISO_MUX

SPI_MOSI

SPI_MISO_R

=PP3V3_S5_ROM

SPI_HOLD_L

SPI_WP_L

SPI_MLB_CS_L

SPI_CLK

SPI_CLK_MUX

25MHz is selected with R5190 and R5191

with R6190, R6191, R5190 and R5191

Any of the 4 frequencies can be selected

43

91

91

8

91

Preliminary

OUTS

OUT

SELB

SELA

BP

IN

GNDENPAD

THRML

EN

IN

NC

NR/FB

OUT

GND

IN

OUT

OUT

OUT

IN

OUT

OUT

OUT

IN

SYNC

CD-R

PORT-F-VREFO

PORT-E-VREFO
PORT-B-VREFO

PORT-C-VREFO

PORT-B-R

PORT-B-L

PORT-E-R

PORT-E-L

PORT-H-R

PORT-H-L

PORT-G-R

PORT-G-L

JDREF

VREF

PORT-D-R

PORT-D-L

PORT-C-R

PORT-C-L

SPDIFO

PORT-F-R

PORT-F-L

PORT-A-VREFO/DCVOL

DVSS

CD-GND

BEEP

AVSS2

AVDD2

AVDD1

SDATA_OUT
SDATA_IN

CD-L

SENSE_A
SENSE_B

AVSS1

GPIO1/DMIC-L

BCLK

NC

SPDIFI/EAPD/MIDI-I/DMIC-R

PORT-A-L
PORT-A-R

RESET*

GPIO0/DMIC-CLK

PORT-B-VREFO2

DVDD

DVDD_IO

REV B3

IN

IN

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT

IN
IN

IN

IN

IN

IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

APPLE P/N 353S1860APPLE P/N 353S1897

AUDIO 4.6 V REGULATOR MIKEY 3.3 V REGULATOR

APPLE P/N 353S1527

AUDIO CODEC

0402

FERR-220-OHM

L6200

1 2

402

MF-LF

1/16W

5%

1K

R6220

1 2

0.1UF

X5R
402

10%
16V

C6210

1

2

0.001UF

10%
CERM

402

50V

C6209

1

2

SM

XW6200

1 2

MAX8902A

TDFN

U6201

7

3

2

1

8
6

4

5

9

25V

0.015UF

X7R

10%

402

CRITICAL

C6211

12

SM

XW6203

1 2

MF-LF

1/16W

402

5%

10K

R6221

1

2

25V

0.1UF

402

X5R

10%

C6212

1

2

4.7UF

CRITICAL

805

10%
10V
X5R

C6208

1

2

X5R-CERM

10UF

0805

16V

CRITICAL

10%

C6213

1

2

SON

CRITICAL

TPS71733

U6202

4

2

6

5

3

1

10%

0.1UF

16V
X5R
402

C6250

1

2

10V

CRITICAL

X5R

10%

402

1UF

C6253

1

2

0.01UF

402

CERM

10%
16V

C6252

1

2

1K

5%

402

MF-LF

1/16W

R6252

1 2

16V

0.1UF

10%

402

X5R

C6251

1

2

402

MF-LF

1/16W

5%

10K

R6253

1

2

21 91

55

56

55

56

55

21 91

21 91

402

MF-LF

1/16W

22

5%

R6204

1 2

100K

5%

MF-LF
402

1/16W

R6205

1

2

402

5%
1/16W
MF-LF

NOSTUFF

0

R6201

1

2

10%

0.1UF

402

X5R

16V

C6220

1

2

ALC885-VB3-GR

LQFP

CRITICAL

U6200

25

38

26

42

6

12

19

18

20

1

9

4

7

2

3

40

37

39

41

33

21
22

28

32

23

24

29

35
36 14

15
31

16
17

30

43

44

45
46

11

8

5

13

34

47

48

10

27

402

MF-LF

1/16W

33

5%

R6250

1 2

21 91

9

0402

FERR-220-OHM

L6201

1 2

NOSTUFF

MF-LF

20K

5%

1/16W

402

R6251

1

2

4V
X5R
402

20%

4.7UF

C6200

1

2

CERM

50V
402

10%

0.001UF

C6201

1

2

0.001UF

402

10%
CERM

50V

C6203

1

2

MF-LF

1/16W

20.0K

1%

402

R6206

1

2

CRITICAL

3.3UF

16V

TANT

SMA-HF1

10%

C6221

1

2

0.001UF

CERM
402

10%
50V

C6222

1

2

MF-LF

100K

402

5%
1/16W

R6207

1

2

MF-LF

402

33

1/16W

5%

R6203

1 2

56

56

56

56

58

58

54

58

58

58

54

54

58

58

57

57

CRITICAL

100UF

20%

6.3V
TANT

CASE-AL1

C6204

1

2

0.001UF

10%

402

CERM

50V

C6206

1

2

CASE-AL1

TANT

6.3V

100UF

20%

CRITICAL

C6205

1

2

FERR-220-OHM

0402

L6202

1 2

20%
50V

0.001UF

CERM
402

C6207

1

2

SYNC_MASTER=AUDIO_K20

AUDIO:CODEC

123

62

31

051-7656

SYNC_DATE=09/29/2008

PP4V6_AUDIO_ANALOG

GND_AUDIO_CODEC

AVDD_ADC_DAC

MIN_NECK_WIDTH=0.20MM

VOLTAGE=4.6V

MIN_LINE_WIDTH=0.20MM

MIN_NECK_WIDTH=0.20MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.20MM

CODEC_DVDD

AUD_SPDIF_OUT

AUD_BI_PORT_B_R

AUD_BI_PORT_B_L

AUD_BI_PORT_E_L

AUD_BI_PORT_F_R

AUD_BI_PORT_H_R

AUD_CODEC_VREF

AUD_VREF_PORT_B

AUD_BI_PORT_E_R

AUD_BI_PORT_A_R

AUD_BI_PORT_A_L

AUD_SENSE_B

AUD_VREF_PORT_F

AUD_SPDIF_O

AUD_BI_PORT_F_L

AUD_VREF_PORT_A

AUD_SENSE_A

MIN_NECK_WIDTH=0.20 MM

GND_AUDIO_CODEC

VOLTAGE=0V

MIN_LINE_WIDTH=0.30 MM

AUD_SPDIF_IN

NC_AUD_VREF_PORT_C

NO_TEST

NC_AUD_VREF_PORT_E

NO_TEST

NO_TEST

NC_AUD_VREF_PORT_B2

NO_TEST

NC_AUD_BI_PORT_G_R

NO_TEST

NC_AUD_BI_PORT_H_L

AUD_CODEC_JDREF

NO_TEST

NC_AUD_BI_PORT_G_L

NC_VRP

NO_TEST

=PP3V3_S0_AUDIO

HDA_SYNC
HDA_SDOUT

HDA_BITCLK

NO_TEST

NC_BAL_IN_R

NO_TEST

NC_BAL_IN_COM

NO_TEST

NC_BAL_IN_L

AUD_GPIO_0_R

CODEC_SDATA_IN

BEEP

AUD_BI_PORT_D_L

AUD_BI_PORT_C_L

AUD_GPIO_1

AUD_BI_PORT_D_R

AUD_BI_PORT_C_R

HDA_RST_L

AUD_GPIO_0

HDA_SDIN0

PP4V6_AUDIO_ANALOG

VOLTAGE=4.6V

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.30MM

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 MM

AUD_4V6_REG_IN

VOLTAGE=5V

4V6_REG_SENSE

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM
VOLTAGE=3.3V

PP3V3_MIKEY_ANALOG

MIKEY_REG_SHDN_L

GND_AUDIO_CODEC

3V3_REG_FB

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

AUD_REG_SHDN_L

=PP3V3_S0_AUDIO

PP5V_S3_AUDIO

4V6_REG_BP

PP4V6_AUDIO_ANALOG

58

58

58

58

56

56

58

56

58

56

58

58

55

55

57

58

55

57

55

57

58

54

54

54

53

54

54

53

54

53

55

54

53

53

53

8

53

58

53

8

53

8

9

53

Preliminary

V-

V+

V-

V+

IN

OUT

OUT

IN

IN

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

GAIN = -5.4 DB AV = 0.52

Pseudo-Diff Line-In Filter

FC = 1.89 HZ

MF-LF

402

1/16W

1%

13.3K

R6312

1 2

402

1/16W

1%

25.5K

MF-LF

R6310

1 2

1/16W

402

1%

MF-LF

13.3K

R6313

1 2

CRITICAL
MAX4253EUB

UMAX-HF

U6300

7

8

9

6

10

4

CRITICAL

50V

CERM

0.001UF

402

10%

C6300

1

2

1/16W

1%

MF-LF

13.3K

402

R6322

1 2

MAX4253EUB

CRITICAL

UMAX-HF

U6300

3

2

1

5

10

4

402

1%

MF-LF

1/16W

13.3K

R6323

1 2

MF-LF

402

1%

25.5K

1/16W

R6311

1 2

1/16W

402

25.5K

1%

MF-LF

R6320

1 2

MF-LF

402

1%

1/16W

25.5K

R6321

1 2

402

1%

MF-LF

1/16W

27.4K

R6302

1

2

27.4K

MF-LF

402

1%

1/16W

R6303

1

2

58

53

53

57

57

1/16W
MF-LF

10

5%

402

R6301

1 2

57

1%

MF-LF

165

1/16W

402

R6300

1 2

53

CRITICAL

10%

X5R

16V
603

2.2UF

C6312

1 2

CRITICAL

X5R

10%
16V

2.2UF

603

C6322

1 2

FERR-220-OHM

0402

L6300

1 2

10%

402

CRITICAL

50V

CERM

0.001UF

C6303

1

2

402

CRITICAL

X5R-CERM

20%

6.3V

4.7UF

C6301

1

2

CRITICAL

100UF

6.3V
TANT
CASE-AL1

20%

C6302

1

2

10%
16V

TANT

SMA-HF1

3.3UF

CRITICAL

C6310

12

10%
16V

TANT

SMA-HF1

3.3UF

CRITICAL

C6311

12

10%
16V

TANT

SMA-HF1

3.3UF

CRITICAL

C6320

12

10%
16V

TANT

SMA-HF1

3.3UF

CRITICAL

C6321

12

SYNC_DATE=09/29/2008

AUDIO: LINE IN

31

63

123

051-7656

SYNC_MASTER=AUDIO_K20

GND_AUDIO_CODEC

AUD_LI_INR_C

AUD_LI_INR

AUD_LIFILT_RT_R

AUD_LI_GND

VOLTAGE=0V

AUD_LIFILT_LT_R

AUD_LI_INL_C

AUD_LI_INL

AUD_LI_INR_R

AUD_VREF_PORT_A

PP4V6_AUDIO_ANALOG

AUD_LI_INL_R

AUD_LIFILT_SHUTDOWN_L

AUD_CODEC_INREF

GND_AUDIO_CODEC

AUD_BI_PORT_A_L

PP4V6_AUDIO_LINE_IN

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.20MM

AUD_LIFILT_LT

AUD_BI_PORT_A_R

AUD_PORTA_R

AUD_LIFILT_RT

AUD_PORTA_L

58

58

56

56

55

55

54

58

54

53

53

53

Preliminary

IN
IN

IN

IN

IN

IN

SVSS

INL

SHDN*

INR

VDD

PVSS

PGND

SGND

THRM

OUTR

OUTL

C1P
C1N

PAD

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

HP:3.52 HZ

1st Order DAC Filter

LP:34 KHZ

VOLTAGE GAIN:1.53

APN:353S1637

Headphone Amplifier (MAX9724A)

55

55

53

53

53

10%
50V

0.001UF

402

CERM

C6501

1

2

SM

XW6500

1 2

FERR-1000-OHM

0402

L6501

1 2

57

SM

XW6501

1 2

MAX9724A

TQFN

CRITICAL

U6500

3

1

6
8

11
10

247

5

9

13

12

10UF

16V

0805

10%

CRITICAL

X5R-CERM

C6500

1

2

10%
16V

10UF

X5R-CERM

0805

CRITICAL

C6502

1

2

CRITICAL

3.3UF

SMA-HF1

TANT

16V

10%

C6510

1 2

X5R

10%
10V

1UF

402

CRITICAL

C6503

1

2

CRITICAL

3.3UF

SMA-HF1

TANT

16V

10%

C6520

1 2

X5R

10V

402

10%

CRITICAL

1UF

C6504

1

2

MF-LF

402

1/16W

5%

10K

R6500

1

2

0402

FERR-120-OHM-1.5A

L6500

1 2

MF-LF

1/16W

1%

402

2.21K

R6514

1

2

MF-LF
402

2.21K

1%
1/16W

R6524

1

2

MF-LF

402

1/16W

1%

21K

R6511

1 2

CRITICAL

25V

5%

402

CERM

220PF

C6511

12

CRITICAL

25V

5%

402

CERM

220PF

C6521

12

21K

MF-LF

402

1%

1/16W

R6521

1 2

1%

MF-LF

13.7K

1/16W

402

R6510

1 2

402

13.7K

MF-LF

1%

1/16W

R6520

1 2

55 57

55 57

31

051-7656

65

123

SYNC_DATE=09/29/2008

SYNC_MASTER=AUDIO_K20

AUDIO: HEADPHONE AMP

AUD_HPAMP_OUTR

AUD_HPAMP_OUTL

AUD_GPIO_0

PP5V_S3_AUDIO

MAX9724_C1P

MAX9724_C1N

VOLTAGE=5V

PP5V_AUDIO_HPAMP_PVDD_F

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.20 MM

AUD_HPAMP_OUTL

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.20 MM

AUD_HPAMP_OUTR

AUD_LO_GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

AUD_HPAMP_MUTE_L

AUD_HPAMP_INL_M

MAX9724_PVSS

MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.10 mm

GND_AUDIO_HPAMP_PGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

AUD_HPAMP_INR_M

GND_AUDIO_CODEC

AUD_HPAMP_INL_M

AUD_HPAMP_INR_M

AUD_CODEC_OUTL_C

AUD_BI_PORT_D_L

AUD_CODEC_OUTR_C

AUD_BI_PORT_D_R

58 56

57

57

53

54

55

55

9

53

55

55

Preliminary

IN

IN

OUT

OUT

OUT

IN

OUT

IN

OUT

OUT

IN

OUT

OUT

IN

OUT

OUT

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

GND

PGND

VDD

PVDD

IN-

IN+

SYNC

OUT-

OUT+

SHDN*

THRML

PAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE C6625 CLOSE TO VDD PIN

PLACE C6645 CLOSE TO VDD PIN

PLACE C6635 CLOSE TO VDD PIN

PLACE C6655 CLOSE TO VDD PIN

4X MONO SPEAKER AMPLIFIERS (MAX9705)

GAIN = 12 DB

APN: 353S1595

PLACE C6621/C6622 CLOSE TO PVDD PIN

PLACE C6611/C6612 CLOSE TO PVDD PIN

SPEAKER CHECKPOINTS

PLACE C6641/C6642 CLOSE TO PVDD PIN

PLACE C6631/C6632 CLOSE TO PVDD PIN

FC (SPEAKERS L2/R2/LFE) = ~97 HZ

FC (SPEAKERS L1/R1) = ~796 HZ

PLACE C6615 CLOSE TO VDD PIN

PLACE CLOSE TO U6610 PIN 9

PLACE CLOSE TO U6620 PIN 9

PLACE CLOSE TO U6630 PIN 9

PLACE CLOSE TO U6640 PIN 9

PLACE C6651/C6652 CLOSE TO PVDD PIN

1/16W
MF-LF

100K

5%

402

R6600

1

2

FERR-1000-OHM

0402

L6601

1 2

53

53

0402

FERR-1000-OHM

L6610

1 2

7

56 57 96

7

56 57 96

7

56 57 96

NOSTUFF

33

5%
1/16W
MF-LF
402

R6602

1

2

50V
CERM
402

CRITICAL

0.001UF

10%

C6611

1

2

CERM
402

10%

0.001UF

50V

CRITICAL

C6621

1

2

0402

FERR-1000-OHM

L6620

1 2

53

NOSTUFF

402

MF-LF

5%

0

1/16W

SIGNAL_MODEL=EMPTY

R6620

1

2

7

56 57 96

NOSTUFF

402

MF-LF

1/16W

5%

0

SIGNAL_MODEL=EMPTY

R6610

1

2

5%

0

402

1/16W
MF-LF

R6603

1

2

5%
MF-LF

402

1/16W

0

R6605

1

2

10%

402

0.001UF

CERM

50V

CRITICAL

C6631

1

2

0402

FERR-1000-OHM

L6630

1 2

53

33

402

MF-LF

1/16W

5%

NOSTUFF

R6604

1

2

7

56 57 96

7

56 57 96

MF-LF

NOSTUFF

0

5%

1/16W

402

SIGNAL_MODEL=EMPTY

R6630

1

2

402

50V

10%
CERM

0.001UF

CRITICAL

C6641

1

2

MF-LF

33

5%
1/16W

402

NOSTUFF

R6606

1

2

1/16W
MF-LF

5%

0

402

R6607

1

2

0402

FERR-1000-OHM

L6640

1 2

53

0

1/16W

5%

NOSTUFF

MF-LF

402

SIGNAL_MODEL=EMPTY

R6640

1

2

7

56 57 96

7

56 57 96

CRITICAL

100UF

20%

6.3V
TANT

CASE-AL1

C6612

1

2

20%

TANT

6.3V

CRITICAL

CASE-AL1

100UF

C6622

1

2

100UF

6.3V
TANT

CRITICAL

20%

CASE-AL1

C6632

1

2

20%

CASE-AL1

TANT

6.3V

CRITICAL

100UF

C6642

1

2

6.3V

20%

CASE-AL1

TANT

100UF

CRITICAL

C6652

1

2

50V

10%
CERM

402

CRITICAL

0.001UF

C6651

1

2

5%
MF-LF

1/16W
402

0

R6609

1

2

402

1/16W

5%

33

MF-LF

NOSTUFF

R6608

1

2

0402

FERR-1000-OHM

L6650

1 2

53

7

56 57 96

7

56 57 96

1/16W

5%

0

NOSTUFF

402

MF-LF

SIGNAL_MODEL=EMPTY

R6650

1

2

MAX9705

CRITICAL

TDFN1

U6610

4

3

2

9

8

7

10

5

6

11

1

MAX9705

TDFN1

CRITICAL

U6620

4

3

2

9

8

7

10

5

6

11

1

TDFN1

MAX9705

CRITICAL

U6630

4

3

2

9

8

7

10

5

6

11

1

MAX9705

TDFN1

CRITICAL

U6640

4

3

2

9

8

7

10

5

6

11

1

MAX9705

TDFN1

CRITICAL

U6650

4

3

2

9

8

7

10

5

6

11

1

1UF

10%
10V
X5R
402

C6615

1

2

1UF

10V
X5R

10%

402

C6625

1

2

10V

1UF

402

10%
X5R

C6635

1

2

402

X5R

10V

10%

1UF

C6645

1

2

1UF

10V

10%

402

X5R

C6655

1

2

10%
16V

CERM-X7R

402

CRITICAL

0.082UF

C6623

1 2

10%
16V

CERM-X7R

0.082UF

CRITICAL

402

C6624

1 2

CRITICAL

CERM-X7R

402

0.082UF

16V

10%

C6643

1 2

10%
16V

0.082UF

CRITICAL

CERM-X7R

402

C6644

1 2

16V
402

0.01UF

10%

CERM

CRITICAL

C6613

1 2

CERM

402

16V

10%

0.01UF

CRITICAL

C6614

1 2

10%
16V

CERM

402

0.01UF

CRITICAL

C6633

1 2

10%
16V

CERM

402

0.01UF

CRITICAL

C6634

1 2

CRITICAL

0.082UF

402

CERM-X7R

16V

10%

C6653

1 2

CRITICAL

0.082UF

402

CERM-X7R

16V

10%

C6654

1 2

AUDIO:SPEAKER AMP

SYNC_DATE=09/29/2008

66

123

SYNC_MASTER=AUDIO_K20

31

051-7656

SPKRAMP_LFE_OUT_P
SPKRAMP_LFE_OUT_N

PP5V_S3_AUDIO_AMP

SPKRAMP_R2_OUT_P

SPKRAMP_SYNC2

AUD_SPKRAMP_SHUTDOWN_L

SPKRAMP_SYNC3

AUD_SPKRAMP_SHUTDOWN_L

SPKRAMP_SYNC4

SPKRAMP_R1_OUT_P

PP5V_S3_AUDIO_AMP

MAX9705L1_PIN

SPKRAMP_R2_OUT_N

SPKRAMP_R1_OUT_N

SPKRAMP_SYNC2

SPKRAMP_L2_OUT_N

SPKRAMP_L2_OUT_P

SPKRAMP_L1_OUT_P

MAX9705L1_NIN

MAX9705L2_NIN

MAX9705R1_PIN

AUD_SPKRAMP_SHUTDOWN_L

MAX9705C_NIN

MAX9705C_PIN

AUD_SPKRAMP_SHUTDOWN_L

GND_AUDIO_CODEC

AUD_SPKRAMP_INC_R

MAX9705R2_NIN

MAX9705R1_NIN

PP5V_S3_AUDIO_AMP

MAX9705L2_PIN

PP5V_S3_AUDIO_AMP

AUD_SPKRAMP_SHUTDOWN_L

GND_AUDIO_CODEC

AUD_SPKRAMP_INR2_L

GND_AUDIO_CODEC

AUD_SPKRAMP_INR1_L

AUD_SPKRAMP_INL2_L

AUD_SPKRAMP_INL1_L

SPKRAMP_SYNC3

SPKRAMP_SYNC1

SPKRAMP_SYNC1

AUD_BI_PORT_H_R

MIN_LINE_WIDTH=0.30 MM

MIN_NECK_WIDTH=0.20 MM

SPKRAMP_LFE_OUT_P

MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 MM

SPKRAMP_LFE_OUT_N

AUD_BI_PORT_B_R

AUD_BI_PORT_C_R

AUD_BI_PORT_B_L

AUD_VREF_PORT_B

MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R2_OUT_P

MIN_LINE_WIDTH=0.30 MM

SPKRAMP_R2_OUT_N

MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.30 MM

SPKRAMP_SYNC4

GND_AUDIO_CODEC

GND_AUDIO_CODEC

MAX9705R2_PIN

AUD_BI_PORT_C_L

SPKRAMP_L1_OUT_N

PP5V_S3_AUDIO_AMP

SPKRAMP_L2_OUT_P

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L2_OUT_N

SPKRAMP_R1_OUT_N

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R1_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L1_OUT_N

MIN_LINE_WIDTH=0.30 mm

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L1_OUT_P

58

58

58

58

58

96

96

96

96

96

96

96

96

96

56

56

56

56

56 96

57

57

57

57

57

57

57

57

57

55

55

55

55

55 57

56

56

56

56

56

56

56

56

56

56

56

54

56

56

54

54

54

54 56

56

7

7

9

7

56

56

56

56

56

7

9

7

7

56

7

7

7

56

56

53

9

9

56

53

53

56

56

56

56

53

53

7

9

Preliminary

IN
IN

IN
IN

OUT

OUT
OUT
OUT

IN

IN

IN
IN

OUT

OUT

IN
IN

OPERATING VOLTAGE 3.3

B - VCC

AUDIO

A - VIN

C - GND

PINS

SHELL

SHIELD

POF

OPERATING VOLTAGE 3.3

C - VOUT

B - GND

A - VDD

POF

SHIELD

SHELL

PINS

AUDIO

OUT

BI

BI

OUT

IN

BI

BI

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AUDIO JACK 2 LINE IN JACK, SPDIF RX

SPEAKER CONNECTORS

APN: 518S0520

MIC CONNECTOR

APN: 518S0521

AUDIO JACK 1 LO/HP JACK, SPDIF TX

RETURN FOR HF NOISE

APN: 518S0672

APN: 514-0632

APN: 514-0633

7

56 96

7

56 96

7

56 96

7

56 96

SM

XW6701

1 2

10

5%

1/16W

402

MF-LF

R6749

1 2

16V
X5R
402

10%

0.1UF

C6750

1

2

0402

FERR-220-OHM

L6751

1 2

402

6.8V-100PF

CRITICAL

DZ6703

1

2

6.8V-100PF

CRITICAL

402

DZ6754

1

2

CRITICAL

402

6.8V-100PF

DZ6755

1

2

0402

FERR-220-OHM

L6758

1 2

CRITICAL

402

6.8V-100PF

DZ6704

1

2

402

6.8V-100PF

CRITICAL

DZ6701

1

2

CRITICAL

6.8V-100PF

402

DZ6702

1

2

6.8V-100PF

CRITICAL

402

DZ6752

1

2

6.8V-100PF

CRITICAL

402

DZ6753

1

2

55

FERR-1000-OHM

0402

L6702

1 2

0402

FERR-1000-OHM

L6703

1 2

6.8V-100PF

CRITICAL

402

DZ6700

1

2

7

58

7

58

7

58

0402

FERR-1000-OHM

L6705

1 2

0402

FERR-1000-OHM

L6752

1 2

16V

402

X5R

0.1UF

10%

C6700

1

2

CRITICAL

78171-0003

M-RT-SM

J6780

4

5

1

2

3

7

56 96

7

56 96

20%

2.2UF

402-LF

6.3V
CERM

C6701

1

2

402

5%
1/16W
MF-LF

0

R6713

1 2

402

MF-LF

5%
1/16W

0

R6714

1 2

MF-LF

402

5%

1/16W

0

R6715

1 2

1/16W
MF-LF

402

5%

0

R6716

1 2

402

MF-LF

0

1/16W

5%

R6710

1 2

5%

603

MF-LF

0

1/10W

R6711

1 2

1/16W

0

5%

MF-LF

402

R6761

1 2

5%

0

1/16W

402

MF-LF

R6762

1 2

0

1/16W

402

MF-LF

5%

R6764

1 2

1/16W

0

402

MF-LF

5%

R6766

1 2

5%

402

MF-LF

1/16W

0

R6768

1 2

5%
1/16W
MF-LF

0

402

R6701

1 2

FERR-1000-OHM

0402

L6754

1 2

100PF

NOSTUFF

402

50V

5%
CERM

C6786

1

2

50V

100PF

CERM

5%

402

NOSTUFF

C6785

1

2

402

5%
CERM

100PF

50V

NOSTUFF

C6788

1

2

402

CERM

5%

50V

100PF

NOSTUFF

C6787

1

2

78171-0004

M-RT-SM

CRITICAL

J6781

5

6

1
2
3
4

0402

FERR-1000-OHM

L6756

1 2

7

56 96

7

56 96

58

58

CERM

NOSTUFF

100PF

50V
402

5%

C6781

1

2

NOSTUFF

100PF

50V
CERM
402

5%

C6782

1

2

50V

NOSTUFF

CERM

100PF

5%

402

C6783

1

2

NOSTUFF

100PF

5%

402

CERM

50V

C6784

1

2

NOSTUFF

5%

100PF

402

CERM

50V

C6710

1

2

NOSTUFF

5%

100PF

402

CERM

50V

C6711

1

2

402

CERM

50V

5%

100PF

C6713

1

2

5%

402

50V

CERM

NOSTUFF

100PF

C6715

1

2

100PF

NOSTUFF

5%
CERM

402

50V

C6712

1

2

5%

100PF

CERM

50V

NOSTUFF

402

C6714

1

2

NOSTUFF

100PF

5%

402

CERM

50V

C6761

1

2

50V

CERM

402

100PF

5%

C6762

1

2

NOSTUFF

CERM

50V
402

5%

100PF

C6763

1

2

NOSTUFF

100PF

50V
402

5%

CERM

C6764

1

2

7

56 96

7

56 96

NOSTUFF

100PF

50V

CERM

402

5%

C6789

1

2

NOSTUFF

100PF

50V
CERM
402

5%

C6790

1

2

CRITICAL

M-RT-SM

78171-6006

J6782

7

8

1
2
3
4
5
6

CRITICAL

F-RT-TH

SPDIF-TX-K20

J6700

1

10
11
12
13

2

3
4

5

6

7
8
9

CRITICAL

F-RT-TH

SPDIF-RX-K20

J6750

1

10
11
12

2

3
4

5

9

6
7
8

NOSTUFF

402

5%

100PF

50V
CERM

C6765

1

2

53

54

54

58

53

55

55

FERR-220-OHM-2.5A

0603

CRITICAL

L6701

1 2

0402

CRITICAL

FERR-220-OHM

L6704

1 2

0402

CRITICAL

FERR-220-OHM

L6706

1 2

58

58

402

5%

10K

MF-LF

1/16W

R6700

1 2

31

051-7656

123

67

SYNC_DATE=09/29/2008

AUDIO: JACKS

SYNC_MASTER=AUDIO_K20

AUD_CONNJ2_SLEEVE

AUD_J2_OPT_OUT

AUD_CONNJ2_SLEEVEDET

=PP3V3_S0_AUDIO

AUD_CONNJ2_RING

AUD_CONNJ2_TIP

AUD_CONNJ2_TIPDET

GND_CHASSIS_AUDIO_JACK

AUD_CONNJ1_TIPDET

MIN_NECK_WIDTH=0.15 MM

AUD_CONNJ1_RING

MIN_LINE_WIDTH=0.20 MM

AUD_CONNJ1_SLEEVE

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.40 MM

AUD_SPDIF_OUT

=PP3V3_S0_AUDIO

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_SLEEVE2

AUD_CONNJ1_TIP

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.20 MM

GND_CHASSIS_AUDIO_JACK

AUD_CONNJ1_SLEEVEDET_F

BI_MIC_SHIELD

BI_MIC_LO

BI_MIC_HI

SPKRAMP_L1_OUT_P

SPKRAMP_R2_OUT_P

AUD_LI_INL

SPKRAMP_LFE_OUT_N

SPKRAMP_LFE_OUT_P

SPKRAMP_R1_OUT_P
SPKRAMP_R1_OUT_N

SPKRAMP_R2_OUT_N

AUD_CONNJ1_SLEEVE2_F

AUD_CONNJ1_SLEEVE_F

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.20 MM

MIN_NECK_WIDTH=0.15 MM

MIN_LINE_WIDTH=0.20 MM

AUD_CONNJ1_TIP_F

GND_CHASSIS_AUDIO_JACK

AUD_CONNJ2_RING_F

AUD_LI_INR

AUD_CONNJ2_TIPDET_F

AUD_J2_TIPDET_R

AUD_LI_GND

AUD_J1_SLEEVEDET_R

AUD_HPAMP_OUTL

AUD_CONNJ1_TIPDET_F

AUD_J1_TIPDET_R

MIN_LINE_WIDTH=0.20 MM

AUD_CONNJ1_RING_F

MIN_NECK_WIDTH=0.15 MM

AUD_HPAMP_OUTR

AUD_LO_GND

HS_MIC_LO

HS_MIC_HI

AUD_J2_COM

SPKRAMP_L2_OUT_P

SPKRAMP_L1_OUT_N

SPKRAMP_L2_OUT_N

AUD_CONNJ2_SLEEVE_F

AUD_SPDIF_IN

AUD_CONNJ2_SLEEVEDET_F

AUD_CONNJ2_TIP_F

58

58

57

57

53

53

8

57

8

57

57

54

Preliminary

OUT

IN

OUT

IN

IN

D

SG

D

SG

D

SG

D

SG

D

G S

OUT

IN

OUT

OUT

IN

IN

IN

D

SG

D

SG

OUT

IN

IN

BI

OUT

IN

IN

OUT

OUT

GND THM

ENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASS

INT*

SCL

IN

VDD

GND

MR*

RST*

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

VREF_B (100%)

VREF_B (100%)

PORT F (BUILT-IN MIC)

PIN COMPLEX

DET ASSIGNMENT

PORT G DETECT

(SPDIF DELEGATE)

HEADSET MIC

LINE_IN AMP SHUTDOWN CONTROL

0X0F (15)

0X23 (35)

MIXER(OUTPUT)

0X18 (24,B)

0x1E (SPDIF OUT)

N/A

KEEP DET TRACE AS SHORT AS POSS

NC

SPEAKERS L1/R1

FUNCTION
HP/LINE OUT

0X0C (12)

0X14 (20,D) 0X14 (20,D)

N/A

DET ASSIGNMENT

VREF_B (100%)

MUTE CONTROL

GPIO_0

NC

PORT A DETECT (Line-in)

PLACE L6800/C6800 CLOSE TO Q6800/01/02

NC

PORT D DETECT (Line-out)

VOLUME
0X0C (12)

0x1F (SPDIF IN)

MIKEY

0X15 (21,A)

MIKEY

N/AN/A

VREF

VREF_F (100%)

0X1B (27,E)

0X19 (25,F)

0X07 (7)

MIXER(INPUT)

0X24 (36)

0X24 (36)

N/A

FUNCTION
LINE IN
SPDIF IN

N/A

0X16 (22,G)

N/A

N/A
N/A

0X07 (7)

0X0A (10)

0X08 (8)

CODEC INPUT SIGNAL PATHS

0X0E (14)

0X04 (4)

0X0E (14)

0X17 (23,H)

CONVERTER

0X03 (3)

0X0D (13)

0X1A (26,C)

0X0D (13)

SPDIF OUT

MIC

0X02 (2)

CODEC OUTPUT SIGNAL PATHS

CONVERTER

0X05 (5)
SPEAKERS L2/R2
SPEAKER LFE

N/A

0X15 (21,A)

VREF_A (50%)

PIN COMPLEX

0X06 (6)

0X0F (15)

TIPDET DEBOUNCE CIRCUIT

402

10V

CERM

20%

0.1UF

C6801

1

2

1/16W
MF-LF

402

47K

5%

R6802

1 2

1/16W

5%

MF-LF

220K

402

R6801

1

2

53 58

57 58

0.1UF

X5R
402

10%
16V

C6800

1

2

FERR-1000-OHM

0402

L6800

1 2

1%

MF-LF
402

1/16W

1

2

R6806

5.11K

402

MF-LF

5%

100K

1/16W

R6803

1 2

402

MF-LF

220K

1/16W

5%

R6804

1

2

0.01UF

402

16V

10%
CERM

C6802

1

2

53

57 58

402

39.2K

1/16W

1%

MF-LF

R6813

1

2

0.1UF

10V

20%

402

CERM

C6811

1

2

1/16W

5%

402

MF-LF

270K

R6811

1

2

1/16W

5%

402

MF-LF

47K

R6812

1 2

57

R6805

1

402

MF-LF

1%

10K

1/16W

2

SSM6N15FEAPE

SOT563

Q6800

3

5

4

SOT563

SSM6N15FEAPE

Q6800

6

2

1

SOT563

SSM6N15FEAPE

Q6801

3

5

4

6

2

1

Q6801

SSM6N15FEAPE

SOT563

SOD-VESM-HF

SSM3K15FV

Q6802

3

1

2

53 58

402

5%
1/16W
MF-LF

2.2K

R6850

1 2

2.2K

5%

1/16W

402

MF-LF

R6855

1 2

0.001UF

CERM

402

10%

50V

C6851

1

2

CRITICAL

0.1UF

25V
X5R

10%

402

C6850

1 2

402

15PF

50V

5%

CERM

1

2

C6852

5%
1/16W
MF-LF
402

100K

1

2

R6852

SM

XW6850

1 2

SM

XW6851

1 2

53

53

53

7

57

7

57

7

57

2012-LLP

20%
16V

CRITICAL

10UF

TANT-POLY

C6853

1

2

1/16W

402

100K

5%
MF-LF

R6815

1

2

SSM6N15FEAPE

SOT563

Q6803

6

2

1

MF-LF
402

5%
1/16W

100K

R6814

1

2

SSM6N15FEAPE

SOT563

Q6803

3

5

4

54

0402

FERR-1000-OHM

L6851

1 2

FERR-1000-OHM

0402

L6850

1 2

0

402

MF-LF

1/16W

R6851

1

2

5%

402

25V

10%

0.01UF

X7R

C6881

1

2

0402

FERR-1000-OHM

NOSTUFF

L6880

1 2

X5R

6.3V

CRITICAL

10UF

20%

603

C6880

1

2

1/16W

0

402

5%

MF-LF

R6890

1 2

5%

402

0

MF-LF

1/16W

R6891

1 2

402

0

5%

MF-LF

1/16W

R6892

1 2

5%

MF-LF

402

0

1/16W

R6893

1 2

5%
MF-LF

402

1/16W

100K

R6880

1

2

MF-LF

1/16W
402

5%

2.2K

R6882

1

2

TANT
603-HF

20%

6.3V

4.7UF

CRITICAL

C6882

1

2

44

9

19

44

21

16V

0.1UF

10%

CRITICAL

C6883

1 2

402

X7R-CERM

15PF

CERM
402

5%
50V

C6884

1

2

5%
1/16W
MF-LF

100K

402

1

2

R6883

SM

XW6800

1 2

57

57

53

53

CERM
402

10%

0.001UF

50V

C6886

1

2

FERR-1000-OHM

0402

L6882

1 2

402

0

MF-LF

1/16W

5%

NOSTUFF

R6884

1

2

CD3275

DRC

CRITICAL

U6800

3

10

2

8

9

4

7

1

6

5

11

2.2K

402

1/16W

21

MF-LF

5%

R6885

50V
CERM
402

5%

100PF

C6887

1

2

1/16W

1K

5%

402

MF-LF

R6881

1

2

0.0082UF

X7R

25V

2

1

C6885

402

10%

57 58

TPDT_DEBOUNCE

MF-LF

1/16W

402

0

5%

R6860

1 2

10%

0.1UF

402

X5R

NOSTUFF

16V

1

2

C6860

402

NOSTUFF

1/16W
MF-LF

R6861

1

2

5%

100K

TPDT_DEBOUNCE

16V
X5R
402

0.1UF

10%

C6861

1

2

TPDT_DEBOUNCE

TPS3801E18DCK

CRITICAL

SC-70-1

U6860

1 2

5 3

4

TPDT_DEBOUNCE

R6862

MF-LF

5%

0

402

1/16W

1 2

1/16W

100K

5%
MF-LF

402

R6863

1

2

1/16W
MF-LF

402

0

5%

R6864

1 2

TPDT_BYPASS

5%

0

402

1/16W
MF-LF

R6865

1 2

17

SYNC_DATE=09/29/2008

31

123

68

051-7656

SYNC_MASTER=AUDIO_K20

AUDIO: JACK TRANSLATORS

AUD_J1_TIPDET_R

AUD_IP_PERIPHERAL_DET_R

AUD_LIN_SHUTDOWN

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

AUD_IP_PERPH_DET_R

AUD_SENSE_B

AUD_J2_DET_RC

AUD_SENSE_A

AUD_OUTJACK_INSERT_L

AUD_LIFILT_SHUTDOWN_L

=I2C_MIKEY_SDA

BI_MIC_BIAS

GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R

AUD_BI_PORT_F_R

AUD_VREF_PORT_F

BI_MIC_SHIELD

BI_MIC_HI

BI_MIC_LO

GND_CHASSIS_AUDIO_MIC

AUD_BI_PORT_F_L

MAKE_BASE=TRUE

BI_MIC_LO_F

BI_MIC_HI_F

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_J1_SLEEVEDET_R

PP3V3_S0_AUDIO_F

AUD_J2_TIPDET_R

PP3V3_S0_AUDIO_F

PP3V3_S0_AUDIO_F

GND_AUDIO_CODEC

PP3V3_S0_AUDIO_F

=PP3V3_S0_AUDIO

AUD_J1_DET_RC

AUD_J1_TIPDET_R

AUD_PORTD_DET_L

AUD_J1_SLEEVEDET_INV

AUD_SENSE_A

AUD_INJACK_INSERT_L

MIN_NECK_WIDTH=0.10MM
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.15MM

PP3V3_S0_HS_RX

PP3V3_MIKEY_ANALOG

=PP3V3_S0_AUDIO

=I2C_MIKEY_SCL

AUD_I2C_INT_L

GND_AUDIO_CODEC

HS_SCL

HS_RST_L

HS_INT_L

AUD_BI_PORT_E_R

AUD_PORTG_DET_L

HS_SDA

AUD_IPHS_SWITCH_EN

HS_RX_BP

HS_MIC_BIAS

HS_SW_DET

PP4V6_AUDIO_ANALOG

AUD_IP_PERPH_DET_DB

AUD_IP_PERIPHERAL_DET

GND_AUDIO_CODEC

MAKE_BASE=TRUE

AUD_BI_PORT_E_L

HS_MIC_LO

HS_MIC_HI_R

HS_MIC_HI

58

58

58

58

58

58

58

58

56

58

56

56

56

56

56

58

58

56

56

55

57

55

55

55

55

55

57

57

55

55

54

53

54

54

58

54

54

54

53

53

54

54

54

53

8

53

53

57

53

53

58

58

58

53

58

8

53

8

53

53

53

Preliminary

BI

V-

V+

BI

D

S G

D

S G

IN

OUT

D

S G

D

SG

G

D S

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

NC

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0599

BIL Connector

MagSafe DC Power Jack

send transients onto ADAPTER_SENSE when AC is

Voltage divider from DCIN ensures Q6901
Vgs is met when SYS_ONEWIRE is high or low.
Q6920 used as bilateral switch to ensure

<Vth>

Vout = 3.425

200mA max output

(Switcher limit)

<Rb>

<Ra>

Vout = 1.25V * (1 + Ra / Rb)

SIG

PWR

adapter detects system and enables 16.5V output.

If ADAPTER_SENSE > Vth

<Rb>

PWR

GND

GND

Q6910 restricts system load to 10K-70K window until

<Ra>

SYS_ONEWIRE doesn’t drive unpowered U6990

then turn off FET

Vgs = 7.63V @ 13V DCIN

Vgs = 11.750V @ 20V DCIN

Vgs(max) = 20V

1-Wire OverVoltage Protection

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

518S0694

Battery Connector

connected.

The chassis ground will otherwise float and can

Vth = Vdcin / 2

Vth = Vdcin * (Rb / (Ra + Rb))

44 59

MF-LF

402

470K

5%

1/16W

R6911

1

2

402

CERM

50V

10%

0.001UF

C6910

1

2

402

270K

1/16W

5%

MF-LF

R6917

1

2

402

MF-LF

270K

5%

1/16W

R6915

1

2

402

25V

10%
X5R

0.1UF

C6915

1

2

100K

402

1/16W
MF-LF

5%

R6913

1

2

1206-1

6AMP-24V

CRITICAL

F6905

1 2

330K

1/16W

5%

MF-LF

402

R6912

1

2

MF-LF

402

270K

5%

1/16W

R6918

1

2

CERM
402

50V

10%

0.001UF

C6917

1

2

LM397

SOT23-5-HF

CRITICAL

U6915

2

4

1

3

5

1

24.3K

MF-LF
402

1/16W

1%

R6920

2

0.01UF

50V
CERM

20%

603

PLACEMENT_NOTE=Place near L6900

C6905

1

2

402

1/16W
MF-LF

100K

5%

R6914

1

2

41 42

SSM6N15FEAPE

CRITICAL

SOT563

Q6920

3

5

4

CRITICAL

SOT563

SSM6N15FEAPE

Q6920

6

2

1

1/16W

402

1K

MF-LF

5%

R6910

1 2

41 42

MF-LF

1/16W

402

270K

5%

R6916

1

2

1/3W

1%

R6905

47

805

MF

1 2

25V

10%

X5R
805

10UF

C6990

1

2

CDPH4D19FHF-SM

33UH

CRITICAL

L6995

1 2

22pF

CERM

50V

5%

402

C6995

1

2

1/16W

200K

MF-LF
402

1%

R6996

1

2

348K

MF-LF

1%
1/16W

402

R6995

1

2

603

22UF

20%

6.3V
X5R-CERM

C6999

1

2

402

X5R

20%

0.22UF

6.3V

C6994

1

2

7

42

50V

402

0.001UF

CERM

10%

C6954

1

2

50V

CERM

5%

47PF

402

C6953

1

2

CERM

5%

47PF

50V

402

C6952

1

2

0.001UF

50V
CERM
402

10%

C6955

1

2

CRITICAL

M-RT-SM

78048-0573

J6900

1

2

3

4

5

SSM6N15FEAPE

SOT563

Q6915

6

2

1

SSM6N15FEAPE

CRITICAL

SOT563

Q6915

3

5

4

CRITICAL

BSS84V

SOT-563

Q6910

6

2

1

LTC3470A

DFN

CRITICAL

U6990

2

3

1

5

7

8 4

9

6

CRITICAL

BAT30CWFILM

SOT-323

D6905

1

2

3

SC-75

RCLAMP2402B

CRITICAL

D6900

3

1

2

CRITICAL

GS731301047E7H

M-RT-SM

J6950

14

15

1

10
11
12
13

2
3
4
5
6
7
8
9

CRITICAL

SC-75

RCLAMP2402B

D6950

3

1

2

FF18-5A-R11A-3H

CRITICAL

F-RT-SM-HF

J6995

1
2
3
4
5

0.001UF

50V
CERM
402

10%

C6950

1

2

50V

CERM

0.001UF

10%

C6951

1

2

402

2

SHORT-1206

XW6950

1

1 2

SHORT-1206

XW6951

21

XW6952

SHORT-1206

SHORT-1206

XW6953

44 59

SYNC_DATE=05/21/2008

SYNC_MASTER=RXU_K20

31

051-7656

123

69

DC-In & Battery Connectors

ADAPTER_SENSE

PPVBAT_G3H_CONN_F

VOLTAGE=8.6V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CONN

GND_BATT_CHGND

=SMBUS_BATT_SCL=SMBUS_BATT_SCL

GND_BATT_CHGND

=SMBUS_BATT_SDA

=PP18V5_DCIN_CONN

MIN_LINE_WIDTH=0.5 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

P3V42G3H_SW

P3V42G3H_BOOST

=PP3V42_G3H_REG

P3V42G3H_FB

=PP18V5_DCIN_CONN

ONEWIRE_PWR_EN_L_DIV

SMC_BC_ACOK_RC

ONEWIRE_PWR_EN_L

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20mm

PP18V5_DCIN_FUSE

MIN_LINE_WIDTH=1mm

SYS_ONEWIRE

SMC_BC_ACOK

SYS_ONEWIRE_BILAT

ONEWIRE_DCIN_DIV

ONEWIRE_ESD

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

PPVIN_G3H_P3V42G3H

=PPVBAT_G3H_P3V42G3H

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

PPDCIN_S5_P3V42G3H

ONEWIRE_OVERVOLT

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=0.25mm

PP18V5_DCIN_ONEWIRE

ONEWIRE_EN

SMC_BS_ALRT_L

SMC_BIL_BUTTON_DB_L

=SMBUS_BATT_SDA

=PP3V42_G3H_BATT

60

60

42

59

59

59

59

59

59

41

7

7

60

9

44

9

44

8

8

8

7

8

7

8

Preliminary

G

S

D

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF
ACIN

SDA

VHST
SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON
BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

NC

OUT

OUT

IN
BI

OUT

GND

VCC

D

S G

D

S G

D

G

S

D1D3D4

S3

S2

GATE

S1

D2

D1

D3

D4

S3

S2

GATE

S1

D2

D

G

S

G

S

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

152S0542

(CHGR_AGATE)

FROM ADAPTER

M99 differences from last sync on 12/02/07 to T18 MLB:

4. Q7060 and Q7065 changed to 376S0667.

3. U7000 Thermal Pad is now connected to GND, not through XW.

Inrush Limiter

(OD)

30mA max load

152S0542

(CHGR_DCIN)

is 3.2V, +/- 50mV

Divider sets ACIN
threshold at 13.07V

sparkitecture requirements

VREF = 3.2V, < 300uA

not powered to counter TL331 bias current.

R7075 clamps CHGR_AMON when charger is

2S Battery Default

(CHGR_CSO_P)
(CHGR_CSO_N)

3S Battery Default

ACIN pin threshold

2. Added Q7056, C7058,R7055,R7056..

1. L7030 changed from T18 MLB inductor to 152S0542.

Input impedance of ~40K meets

5. Q7055 and Q7056 changed to 376S0666.

f = 400 kHz

Max Current = 8.5A
(L7030 limit)

Reverse-Current Protection

152S0542

32V/V

20V/V

(OD)

TO SYSTEM

(PPVBAT_G3H_CHGR_R)

152S0542

1%

MF-LF

1/16W

402

9.31K

R7011

1

2

16V
X5R

0.033UF

10%

402

C7042

1

2

402

CERM

50V

10%

470PF

C7016

1

2

402

1/16W

1%

MF-LF

3.01K

R7016

1

2

402

CERM

0.001UF

50V

10%

C7015

1

2

402

MF-LF

1/16W

1%

56.2K

R7015

1

2

402

1UF

X5R

10%
10V

C7002

1

2

X5R

10%

402

1UF

10V

C7000

1

2

4.7

402

1/16W

5%

MF-LF

R7001

1 2

1/16W

402

30.1K

MF-LF

1%

R7010

1

2

10%
25V

0.1UF

X5R
402

C7060

1

2

MF-LF

1/16W

402

470K

1%

R7060

1

2

MF-LF

1.82K

1%

402

1/16W

R7071

1

2

MF-LF

1%

402

1/16W

57.6K

R7070

1

2

10%

CERM

402

0.01uF

16V

C7057

1

2

X5R
402

0.1UF

10%
16V

C7056

1

2

LFPAK-SM

HAT1127H

CRITICAL

Q7055

5

4

1

2

3

SM

XW7000

1 2

QFN

OMIT

ISL6258A

CRITICAL

U7000

3

14

1

6

26

9

16

15

25

27

28

17

18

2

5

21

22

23

11

10

29

13

24

7

19

20

12

8

4

10V
402

1UF

X5R

10%

C7001

1

2

C7021

402

0.1UF

10%
25V
X5R

1

2

0.1UF

10%

402

X5R

25V

C7022

1

2

10%

SIGNAL_MODEL=EMPTY

CERM
402

10V

0.047UF

C7020

1

2

0.22UF

10V
CERM
402

10%

C7035

1

2

CRITICAL

RJK0305DPB

LFPAK-HF

Q7035

5

4

1 2 3

2

10

R7022

1/16W

402

MF-LF

5%

1

R7021

1/16W
MF-LF

5%

10

402

1 2

5

LFPAK-HF

CRITICAL

RJK0305DPB

Q7030

4

1 2 3

CASE-D2-SM

25V

20%

22UF

POLY-TANT

CRITICAL

C7030

2

1

CRITICAL

22UF

20%
25V
POLY-TANT
CASE-D2-SM

C7031

1

2

25V

603-1

10%

1UF

X5R

C7032

1

2

POLY-TANT

16V

33UF

20%

CASED2E-SM

CRITICAL

C7040

1

2

CRITICAL

1206

8AMP-24V

F7040

1

2

10

1/16W
MF-LF

5%

402

R7051

1 2

402

5%

MF-LF

1/16W

10

R7052

1 2

X5R

10%

603-1

25V

C7033

1

2

1UF

62K

402

1/16W

5%

MF-LF

R7066

1

2

402

1/16W
MF-LF

5%

100K

R7065

1

2

1UF

X5R

25V

603-1

10%

C7055

1

2

1%
1/16W

332K

MF-LF
402

R7061

1

2

0.1UF

25V

402

X5R

10%

C7005

1

2

45

45
60

44

44

402

CERM

0.01UF

10%
16V

C7011

1

2

X5R

10%

0.1uF

402

16V

C7070

1

2

402

10%
16V
X5R

0.1uF

SIGNAL_MODEL=EMPTY

C7050

1

2

50V

10%
CERM

402

0.001UF

C7026

1

2

42

0.005

MF

0612

1W

1%

CRITICAL

R7050

2 1
4 3

0.02

432

1

R7020

0612

MF

0.5%
1W

CRITICAL

SOT23-5

TL331

U7070

1

3

4

5

2

SOT563

SSM6N15FEAPE

Q7074

3

5

4

402

1M

5%

MF-LF

1/16W

R7074

1

2

SSM6N15FEAPE

SOT563

Q7074

6

2

1

0.001UF

10%
50V
X7R
402

C7034

1

2

50V

0.001UF

10%
X7R

402

C7041

1

2

402-1

1UF

10V
X5R

10%

C7058

1

2

LFPAK-SM

HAT1127H

CRITICAL

Q7056

5

4

1 2 3

5%

402

1/16W

MF-LF

20K

R7057

1 2

1/16W

402

5%
MF-LF

1M

R7056

1 2

CRITICAL

RJK0305DPB

LFPAK-HF

Q7036

5

4

1 2 3

CRITICAL

LFPAK-HF

RJK0305DPB

Q7031

5

4

1 2 3

HAT1128R01

SOI

CRITICAL

Q7060

567

8

4

123

SOI

HAT1128R01

CRITICAL

Q7065

567

8

4

123

CRITICAL

25V

22UF

20%
POLY-TANT

CASE-D2-SM

C7036

1

2

CRITICAL

SM

2.2UH-20A-5.5M-OHM

L7030

1 2

POLY-TANT

20%

33UF

16V

CASED2E-SM

CRITICAL

C7043

1

2

CRITICAL

CASE-D2-SM

POLY-TANT

20%

22UF

25V

C7037

1

2

SM

2.2UH-20A-5.5M-OHM

CRITICAL

L7031

1 2

BAT30CWFILM

SOT-323

CRITICAL

D7005

1

2

3

CRITICAL

1206

8AMP-24V

F7041

1

2

NO STUFF

MF-LF

603

5%

10

1/10W

R7099

1

2

402

X7R

10%

0.001UF

50V

C7099

1

2

LFPAK-SM

HAT1127H

CRITICAL

Q7058

5

4

1 2 3

CRITICAL

LFPAK-SM

HAT1127H

Q7057

5

4

1

2

3

SYNC_DATE=05/21/2008

SYNC_MASTER=RXU_K20

051-7656

31

123

70

PBus Supply & Battery Charger

353S1832

IC,ISL6258A,BAT CHARGER,4X4MM,QFN28

CRITICAL

1

U7000

ISL6258A

IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L

U7000

CRITICAL

1

ISL6258

353S1938

VOLTAGE=12.6V

PPVBAT_G3H_FET

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

BATT_POS_GATE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

PPVBAT_G3H_CHGR_R

CHGR_BGATE

MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm

PPVBAT_G3H_CHGR_REG

=PPBUS_G3H

CHGR_VNEG
CHGR_CSO_P

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

PP5V1_CHGR_VDD

CHGR_CSO_N

CHGR_ICOMP

CHGR_CSI_P

CHGR_LGATE

CHGR_UGATE

=CHGR_ACOK

CHGR_BMON

=SMBUS_CHGR_SDA

CHGR_ACIN

CHGR_VCOMP

=SMBUS_CHGR_SCL

CHGR_VNEG_R

=PP3V42_G3H_CHGR

CHGR_VCOMP_R

TP_CHGR_TRKL

CHGR_SGATE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_AMON

PP5V1_CHGR_VDD

AMON_CLAMP

SGATE_P0V1_VREF

CHGR_AMON

=PP3V42_G3H_CHGR

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

PP5V1_CHGR_VDDP

CHGR_BOOT

CHGR_PHASE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

GND_CHGR_AGND

MIN_NECK_WIDTH=0.3 mm

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_SGATE_DIV

PPDCIN_S5_INRUSH

VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

CHGR_DCIN

PPVBAT_G3H_CHGR_REG_L

MIN_NECK_WIDTH=0.4 mm

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm

CHGR_PHASE_RC

GND_BATT_CHGND

CHGR_CSO_R_N

CHGR_CSO_R_P

GND_CHGR_AGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm

PPDCIN_S5_CHGR_R

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

CHGR_AGATE

CHGR_CSI_N

CHGR_CSI_R_N

=PPDCIN_S5_CHGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

PPDCIN_S5_FET_CHGR

VOLTAGE=18.5V

CHGR_CSI_R_P

60

60

60

59

96

96

8

94

60

94

94

8

60

45

8

60

9

45

45

60

59

94

96

8

96

Preliminary

IN

IN

IN

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

OUT
OUT

IN

IN

OUT

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT*
NTC

VR_ON
PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3
VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1
BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DPRSTP*

1

Operation

Place R7131 Between L7100,L7101 and CPU

(IMVP6_VW)

1

2-Phase

DCM

0 DCM

44A MAX CURRENT

1-Phase

1

(GND_IMVP6_SGND)

Place R7126 in hot

(IMVP6_PHASE2)

(IMVP6_ISEN1)

spot of reg circuit.

0
1

(IMVP6_VO)

ModePSI*

(GND)

(ISL9504A)

DPRSLPVR

CCM

1

0
0

0

0

(GND)

(IMVP6_COMP)

These caps are for Q7102

(IMVP6_NTC)

CCM

1-Phase

(PGD_IN)

(IMVP6_PHASE1)

(GND_IMVP6_SGND)

(IMVP6_ISEN2)

(IMVP6_VSUM)

(IMVP6_VO)

LAYOUT NOTE:

1 1-Phase

These caps are for Q7100

(IMVP6_FB)

1/16W
MF-LF

402

10K

1%

R7100

1 2

10%

0.22UF

10V

CERM

402

C7103

1 2

SM

XW7104

12

25V

603

X5R

20%

0.22UF

C7115

1

2

9

10 14 88

21 88

10

9

61

25

SM

XW7102

12

10K

1/16W
MF-LF

402

1%

R7105

1 2

402

0.22UF

10V

10%

CERM

C7104

1 2

0.22UF

25V

603

20%
X5R

C7127

1

2

MF-LF

10

1/16W

402

1%

R7120

1 2

MF-LF

402

10

1/16W

1%

R7112

1 2

X5R
402

10V

10%

1UF

C7126

1

2

1/16W
MF-LF

402

1%

10

R7121

1 2

X5R
402

10%

0.1uF

16V

C7130

1

2

499

1/16W

402

1%

MF-LF

R7119

1 2

402

CERM

50V

10%

0.001UF

C7107

1

2

6.81K

1%
1/16W
MF-LF
402

R7110

1

2

4.7UF

6.3V
X5R-CERM

20%

402

C7135

1

2

CERM

402

0.01uF

16V

10%

C7110

1

2

402

1%

1K

1/16W
MF-LF

R7113

1

2

MF-LF

1/16W

2

402

1%

1K

R7109

1

2

1

C7113

10%

402

50V

CERM

390PF

97.6K

402

1/16W
MF-LF

1

2

R7114

1%

402

MF-LF

1/16W

5%

1

R7104

1

2

1/16W

402

MF-LF

1

5%

R7107

1

2

CERM

50V

10%

NO STUFF

0.001uF

402

C7116

1

2

3.92K

1/16W
MF-LF

402

1%

R7117

1 2

CERM

50V

402

5%

180pF

C7129

1

2

1K

1%
1/16W

402

MF-LF

R7118

1

2

1%
1/16W
MF-LF

402

2.61K

R7130

1

2

402

MF-LF

1/16W

1%

11K

R7115

1

2

0.22UF

CERM-X5R

10%

402

6.3V

C7128

1

2

0.068UF

CERM

10V
402

10%

C7134

1

2

402

0

MF-LF

5%

1/16W

R7122

1 2

SIGNAL_MODEL=EMPTY

0.001UF

50V

402

CERM

10%

C7131

1

2

0.001UF

50V

10%

402

CERM

C7132

1

2

5%

1/16W

402

MF-LF

0

R7123

1 2

10%
50V

0.001UF

402

CERM

C7143

1

2

0.22UF

6.3V

20%

402

X5R

C7121

1

2

SM

XW7100

1 2

1/10W

3.65K

MF-LF
603

1%

R7101

1

2

3.65K

1/10W

1%

603

MF-LF

R7106

1

2

CRITICAL

0.36UH-30A-1.05MOHM

PCMC104T-SM

L7100

1 2

0.36UH-30A-1.05MOHM

PCMC104T-SM

CRITICAL

L7101

1 2

0.1UF

X5R
402

10%
16V

C7196

1

2

9

88

9

88

9

88

9

88

9

88

9

88

9

88

0.001UF

50V

402

CERM

10%

C7106

1

2

CERM
402

50V

10%

470PF

C7114

1

2

402

MF-LF

1%

1/16W

255

R7111

1

2

10%

402

16V

0.015UF

X7R

C7105

1

2

1%
MF-LF

1/16W

402

13.3K

R7116

1

2

10%

1UF

25V
X5R
603-1

C7109

1

2

CRITICAL

0603-LF

10KOHM-5%

R7131

1

2

1/16W

147K

402

MF-LF

1%

R7108

1

2

402

MF-LF

4.02K

1/16W

1%

R7127

1

2

MF-LF

1/16W

5%

10K

402

R7197

1

2

SM

XW7103

1 2

SM

XW7101

1 2

61

61

11 88

11 88

402

CRITICAL

470K

R7126

1

2

402

5%

MF-LF

0

1/16W

R7198

1 2

10 14 42 88

68

MF-LF
402

1/16W

5%

R7199

1

2

CRITICAL

ISL9504BCRZ

QFN

U7100

48

36

26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

LFPAK-HF

RJK0305DPB

CRITICAL

Q7100

5

4

1 2 3

CRITICAL

RJK0328DPB

LFPAK-HF

Q7103

5

4

1 2 3

LFPAK-HF

RJK0305DPB

CRITICAL

Q7102

5

4

1 2 3

CRITICAL

RJK0328DPB

LFPAK-HF

Q7101

5

4

1 2 3

603-1

1UF

X5R

10%
25V

C7154

1

2

45

I848I849

5%

1/16W

0

MF-LF

402

R7160

1 2

50V

0.001UF

10%

402

X7R

C7108

1

2

50V

0.001UF

10%
X7R

402

C7152

1

2

50V

0.001UF

10%

402

X7R

C7156

1

2

50V

0.001UF

X7R
402

10%

C7157

1

2

20%

16V

68UF

TANTD

SM

CRITICAL

C7117

1

2

25V

603-1

1UF

10%
X5R

C7118

1

2

25V

10%
X5R

1UF

603-1

C7158

1

2

POLY-TANT

33UF

CRITICAL

20%

16V

CASED2E-SM

C7155

1

2

TANTD

68UF

16V

20%

CRITICAL

SM

C7133

1

2

0

5%

1/10W

603

MF-LF

R7189

1 2

1/10W

603

5%

MF-LF

0

R7188

1 2

16V

20%

CRITICAL

33UF

POLY-TANT

CASED2E-SM

C7153

1

2

IMVP6 CPU VCore Regulator

SYNC_MASTER=RXU_K20

051-7656

31

71

123

SYNC_DATE=05/21/2008

IMVP6_VDIFF_RC

IMVP6_VDIFF

IMVP6_COMP_RC

IMVP6_COMP

IMVP6_FB

IMVP6_VW

IMVP6_RBIAS

IMVP_DPRSLPVR

=PPVIN_S5_CPU_IMVP

IMVP6_BOOT1

IMVP6_BOOT1_R

IMVP6_UGATE1

IMVP6_PHASE1

IMVP6_LGATE1

IMVP6_PHASE2

IMVP6_UGATE2

IMVP6_LGATE2

IMVP6_VSUM
IMVP6_OCSET

CPU_VCCSENSE_P

IMVP6_ISEN2

IMVP6_DROOP

VR_PWRGD_CLKEN_L

IMVP6_IMON

CPU_PSI_L

IMVP6_DFB

IMVP6_VR_TT_L
IMVP6_NTC

VR_PWRGOOD_DELAY

=PPVCORE_S0_CPU_REG

IMVP6_VID<6>

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_DROOP

IMVP6_FB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VO_R

IMVP6_VSUM2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_SOFT

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_COMP

PM_DPRSLPVR

MIN_LINE_WIDTH=1.5 MM

IMVP6_PHASE2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_BOOT2

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM

IMVP6_UGATE2

CPU_VCCSENSE_N

IMVP6_VO1

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VSUM2

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM

IMVP6_LGATE1

IMVP6_BOOT1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=1.5 MM

IMVP6_PHASE1

IMVP6_FB2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VDIFF

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_RBIAS

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DFB

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VO

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_OCSET

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VSUM1

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM

IMVP6_UGATE1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_VSEN_P

IMVP_VR_ON_R

IMVP_VR_ON

IMVP6_VO2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_VSEN_N

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VO2

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_ISEN2

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM

IMVP6_LGATE2

IMVP6_VW

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_NTC_R

IMVP_VR_ON_R

CPU_DPRSTP_L

IMVP6_VID<1>
IMVP6_VID<0>

IMVP6_VID<2>

IMVP6_VID<4>

VOLTAGE=3.3V

PP3V3_S0_IMVP6_3V3

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

=PP1V05_S0_CPU

=PP3V3_S0_IMVP

IMVP6_VSUM1

IMVP6_FB2

IMVP6_VID<3>

IMVP6_VID<5>

CPU_PROCHOT_L

IMVP6_SOFT

VOLTAGE=0V

MIN_LINE_WIDTH=0.50 MM

GND_IMVP6_SGND

MIN_NECK_WIDTH=0.20 MM

MIN_NECK_WIDTH=0.25 MM

IMVP6_VO1

MIN_LINE_WIDTH=0.25 MM

IMVP6_ISEN1

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_ISEN1

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM

VOLTAGE=5V

PP5V_S0_IMVP6_VDD

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

=PP5V_S0_CPU_IMVP

IMVP6_BOOT2

IMVP6_BOOT2_R

IMVP6_VSEN_N

IMVP6_VSEN_P

IMVP6_VO

13 12 11 10

88 88

8

88

88

61

61

61

61

61

88

8

61

61

61

61

61

61

61

61

61

61

8

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61

61 41

61

61

61

61

61

61

6

8

61

61

61

61

61

61

8

61

61

61

Preliminary

OUT

Q1

Q2

SW

VREG3

COMP1 COMP2

CSN1 CSN2

CSP1 CSP2

DRVH1 DRVH2

FUNC

GND

PGOOD1 PGOOD2

RF

SW1 SW2

THRM_PAD

TRIP

VFB1 VFB2

VIN

VREF2

VREG5

VBST1 VBST2

V5SW

DRVL1

SKIPSEL2

SKIPSEL1

DRVL2

EN1 EN2

EN

S

D

G

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 5.0V

F=400KHZ

.

(Q7220 limit)

7A MAX OUTPUT

F=400KHZ

6A MAX OUTPUT

Vout = 3.3V

(L7260 limit)

One master PGOOD for both 5V and 3V3

10%
25V

1UF

C7200

1

2

X5R

603-1

IHLP2525CZ-SM1

2.2UH-14A

CRITICAL

L7260

1 2

10%

X5R

1UF

25V

603-1

C7241

1

2

603-1

X7R

50V

0.1UF

10%

C7264

1

2

X5R
603

10UF

20%

6.3V

C7290

1

2

50V
X7R
603-1

0.1UF

10%

C7224

1

2

POLY-TANT

330UF

CASE-D3L-SM1

20%

6.3V

CRITICAL

C7252

1

2

805

X5R

20%
10V

10UF

C7250

1

2

603-1

10%

X5R

1UF

25V

C7281

1

2

1 2

SM-IHLP

1.0UH-22A-10M-OHM

L7220

CRITICAL

10%

402

CERM

6.3V

1UF

C7203

1

2

10UF

20%

X5R
603

6.3V

C7205

1

2

1/16W

1%

MF-LF
402

249K

R7206

1

2

67

SM

XW7261

1

2

MLP

FDMS9600S

CRITICAL

Q7260

2349

1

8

56

7

10

10V

10%

402

CERM

0.22UF

C7201

1

2

23.2K

1%

MF-LF
402

PATH=I621

1/16W

R7260

1

2

10K

1/16W

402

MF-LF

1%

R7261

1

2

PATH=I623

1/16W
MF-LF
402

40.2K

1%

R7220

1

2

1%
1/16W

402

MF-LF

10K

R7221

1

2

RJK0305DPB

LFPAK-HF

CRITICAL

Q7220

5

4

123

33UF

20%

16V

POLY-TANT

CASED2E-SM

CRITICAL

C7280

1

2

CASED2E-SM

16V

20%

33UF

POLY-TANT

CRITICAL

C7240

1

2

LLP

TPS51220

CRITICAL

U7201

10

15

8

17

7

18

1

24

30

27

12

4

21

11

28

5

20

3

19

32

25

33

14

2

31

26

9

16

23

13

22

29

6

PLACEMENT_NOTE=Place XW7200 between pins U7200.28 and 33.

SM

XW7200

1 2

1/16W
MF-LF
402

1%

3.83K

R7216

1

2

402

X5R

10%

25V

0.1UF

C7288

1

2

1/16W1%MF-LF

402

1.18K

R7246

1

2

SM

PLACEMENT_NOTE=PLACE XW7260 AND XW7261 NEXT TO L7260 .

XW7260

1

2

402

10%

X5R

16V

0.1UF

C7218

1

2

MF-LF1%1/16W

402

1.54K

R7247

1

2

1/16W

1%

402

MF-LF

2.74K

R7256

1

2

SM

XW7220

1

2

SM

XW7221

1

2

PLACEMENT_NOTE=PLACE XW7220 AND XW7221 NEXT TO L7220.

MF-LF

1%
1/16W

402

10K

R7236

1

2

MF-LF

1/16W

402

1%

20.0K

R7237

1

2

10%

402

470PF

CERM

50V

C7236

1

2

100PF

CERM

402

5%

50V

C7237

1

2

PLACEMENT_NOTE=PLACE XW7262 NEXT TO L7260.

SM

XW7262

1

2

PLACEMENT_NOTE=PLACE XW7222 NEXT TO L7220.

SM

XW7222

1

2

PWRPK-1212-8-HF

CRITICAL

SI7110DN

Q7225

5

4

123

POLY-TANT

330UF

CASE-D3L-SM1

20%

6.3V

CRITICAL

C7292

1

2

402

1%

20.0K

MF-LF

1/16W

R7239

1

2

50V

100PF

5%

402

CERM

C7239

1

2

402

1/16W
MF-LF

1%

10K

R7238

1

2

402

10%

470PF

CERM

50V

C7238

1

2

67 67

402

1/16W

MF-LF

5%

0

NO STUFF

R7248

1

2

MF-LF

1/16W

402

0

5%

R7249

1

2

50V

10%

402

0.0033UF

CERM

C7299

1

2

MF-LF

5%

1/10W

603

1

R7299

1

2

NO STUFF

10%

402

X7R

0.001UF

50V

C7298

1

2

10

5%

1/10W

603

MF-LF

NO STUFF

R7298

1

2

10%

402

X7R

0.001UF

50V

C7272

1

2

10%

402

X7R

0.001UF

50V

C7273

1

2

10%

402

X7R

0.001UF

50V

C7270

1

2

0.001UF

10%
50V
X7R
402

C7271

1

2

5V / 3.3V Power Supply

SYNC_MASTER=RXU_K20

72

123

31

051-7656

SYNC_DATE=05/21/2008

P5VS3_CSP1-R

P5VS3_VBST

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

P5VP3V3_VREF2

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

P5VS3_DRVH

GATE_NODE=TRUE

P5VS3_CSP1

P3V3S5_EN

P5V3V3_PGOOD

P5VP3V3_VREF2

SWITCH_NODE=TRUE

P5VS3_LL

P5VS3_CSN1

P5VS3_VFB1

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_P5VP3V3_SGND

P3V3S5_VFB2

P3V3S5_CSN2

P3V3S5_CSP2_R

P3V3S5_RF

P3V3S5_COMP2

P3V3S5_CSP2

P5VP3V3_VREG3

P5VP3V3_VREG5

MIN_NECK_WIDTH=0.2 mm

P3V3S5_VBST

MIN_LINE_WIDTH=0.6 mm

P3V3S5_LL_RC

P3V3S5_VFB2_R

P5VS3_LL_RC

P5VS3_VFB1-R

P3V3S5_COMP2_R

P5VP3V3_VREF2

P5VS3_COMP1_R

=PP5V_S3_REG

GATE_NODE=TRUE

P5VS3_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

P5VP3V3_VREG3

P5VS3_FUNC

P5VS3_COMP1

=P5VS3_EN

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

P3V3S5_DRVL

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

P3V3S5_LL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

P3V3S5_DRVH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

=PP3V3_S5_REG

=PP5V_S3_REG

=PPVIN_S5_P5VP3V3

62

62

62

62

62

62

8

62

8 8

8

Preliminary

MODE

VDDQSNS

COMP

NC0
NC1

VTTSNS

VTT

VTTREF

PGOOD

S3
S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN
IN
OUT

NC
NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = VTTREF

(DDRREG_DRVL)

VTT Enable

(DDRREG_VBST)

Vout = 0.75V * (1 + Ra / Rb)

<Ra>

(Q7335 limit)

(DDRREG_CSGND)

<Rb>

VDDQ/VTTREF Enable

VDDQ PGOOD

10mA max load

(DDRREG_VDDQSNS)

Vout = VDDQSNS/2

(DDRREG_LL)

(DDRREG_FB)

Vout = 1.50V or 1.80V

f = 400 kHz

(DDRREG_DRVH)

18A MAX OUTPUT

0.1UF

10%

X7R

50V

603-1

C7325

1 2

402

1%
1/16W

15.0K

MF-LF

R7320

1

2

1/16W
MF-LF

1%

402

15.0K

R7321

1

2

603-1

10%

1UF

X5R

25V

C7332

1

2

50V

5%

100PF

CERM

402

NO STUFF

C7320

1

2

CRITICAL

TPS51116

QFN

U7300

6

16

17

21

19

3

20

4

7

12

18

13

10

11

25

14

15

22

9

8

23

24

1

5

2

10%
X5R

10V

1UF

402

C7305

1

2

MF-LF

1/16W

5%

4.7

402

R7305

1 2

6.3V

20%

22UF

CRITICAL

X5R-CERM
603

C7361

1

2

X5R-CERM

6.3V

20%

603

22UF

CRITICAL

C7360

1

2

PLACEMENT_NOTE=Place next to C7361

SM

XW7360

1 2

PLACEMENT_NOTE=Place next to Q7335

SM

XW7335

1 2

0.033UF

10%
X5R

16V

402

C7350

1

2

9

68

603

4.7UF

CERM

20%

6.3V

C7300

1

2

67

8.06K

1/16W

402

MF-LF

1%

R7310

1

2

67

RJK0305DPB

CRITICAL

LFPAK-HF

Q7330

5

4

1 2 3

IHLP4040DZ11-SM

CRITICAL

1.0UH-20A

L7330

1 2

LFPAK-HF

RJK0328DPB

CRITICAL

Q7335

5

4

1 2 3

PLACEMENT_NOTE=Place next to L7330

SM

XW7345

1

2

20%

603

6.3V
X5R

10UF

C7355

1

2

SM

PLACEMENT_NOTE=Place next to U7300.3

XW7300

1

2

2.5V

20%

330UF

CASE-C2-SM

POLY-TANT

CRITICAL

C7341

1

2

CRITICAL

2.5V
CASE-C2-SM

20%

330UF

POLY-TANT

C7340

1

2

6.3V

20%
X5R

10UF

603

C7345

1

2

50V

0.001UF

10%

402

X7R

C7333

1

2

50V

0.001UF

10%

402

X7R

C7346

1

2

SM

TANTD

68UF

CRITICAL

20%

16V

C7330

1

2

SM

16V

20%

CRITICAL

68UF

TANTD

C7331

1

2

SYNC_DATE=05/21/2008

SYNC_MASTER=RXU_K20

31

123

73

051-7656

1.5V DDR3 Supply

DDRREG_VTTSNS

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=2 mm

=PPVTT_S0_DDR_LDO

=PPVTT_S3_DDR_BUF

DDRREG_PGOOD

=PPVIN_S3_DDRREG

PP5V_S3_DDRREG_V5FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

DDRREG_VDDQSNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

DDRREG_DRVH

=PPDDR_S3_REG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

DDRREG_LL

=PPVIN_S0_DDRREG_LDO

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

DDRREG_DRVL

GATE_NODE=TRUE

=DDRREG_EN

=DDRVTT_EN

DDRREG_CS

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

DDRREG_CSGND

DDRREG_FB

DDRREG_VBST

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

=PP5V_S3_DDRREG

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

GND_DDRREG_SGND

26 8 8

8

8

8

8

Preliminary

IN

IN

OUT

IN
IN
IN

S

D

G

S

D

G

IN

IN

LDOREFIN

LDO

PGND

GND

TONSEL

EN_LDO
V5DRV1

VBST1

DRVL1

VSW

EN1

LL1

DRVH1

VOUT1

TRIP1
SKIPSEL

VBST2
DRVH2

LL2
DRVL2
VOUT2

EN2

THRM_PAD

VIN

VFB1

TRIP2

REFIN2

PGOOD2

PGOOD1

VREF2

V5DRV

VREF3

V5FILT

D

SG

D

SG

D

SG

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

(P5VRTS0_UGATE)

(MCPCORES0_LGATE)

Max load 100mA

(=P5V_RTS0_EN)

Vout = 0.7V * (1 + Ra / Rb)

3.5A MAX OUTPUT
(Q7510 limit?)

(=PPMCPCORE_S0_REG)

Vout = 2.0V * Req / (Ra + Req)

(=PP5V_RTS0_REG)

(P5VRTS0_BOOT)

(SGND)

<Rb>

Max load 50uA

<Ra>

<Rd>

<Ra>

Req = Rb || Rc || Rd || Re

<Rb>

MCP79 Rev A01 requires higher core & analog voltage

(P5VRTS0_PHASE)

(Q7560 Limit)

Vout = See below

<Re>

MAX CURRENT: 11A

<Rc>

111 +0.876V +0.719V +0.70V

110 +0.913V +0.752V +0.75V

100 +0.995V +0.830V +0.85V

011 +1.049V +0.885V +0.90V

010 +1.101V +0.937V +0.95V

001 +1.159V +0.994V +1.00V

000 +1.224V +1.060V +1.05V

VID<2:0> Voltage Voltage MCP Target

Rev A01 Production

Vout = 5.03V

(MCPCORES0_PHASE)

(P5VRTS0_LGATE)

f = 200 kHz F = 300 KHZ

101 +0.952V +0.789V +0.80V

from PVCC to VCC)

(Internal 10-ohm path

(MCPCORES0_UGATE)

67

NO STUFF

402

CERM

50V

100PF

5%

C7520

1

2

CRITICAL

POLY-TANT

16V

CASED2E-SM

20%

C7510

1

2

33UF

603-1

X5R

25V

1UF

10%

C7511

1

2

0.22UF

603

16V
X7R

10%

C7514

1

2

RJK0305DPB

LFPAK-HF

CRITICAL

Q7560

5

4

1 2 3

CRITICAL

321

5

Q7565

LFPAK-HF

4

RJK0328DPB

C7567

2

1

603

10UF

X5R

20%
4V

67

67

21

21

21

0.01UF

16V

10%

CERM
402

C7590

1

2

SWITCH_NODE=TRUE

21

L7560

CRITICAL

1.0UH-20A

IHLP4040DZ11-SM

C7568

2

1

CRITICAL

CASE-C2-SM

POLY-TANT

2.5V

20%

330UF

C7563

0.001UF

50V
X7R

10%

402

1

2

C7569

50V

0.001UF

402

10%
X7R

1

2

PWRPK-1212-8-HF

SI7108DN

CRITICAL

Q7511

5

4

123

2

1

C7515

CRITICAL

POLY-TANT

6.3V

330UF

20%

CASE-D3L-SM1

2

1

C7516

805

X5R

10V

10UF

20%

L7510

IHLP2525CZ-SM1

21

CRITICAL

2.2UH-14A

SI7110DN

PWRPK-1212-8-HF

Q7510

CRITICAL

5

4

123

21

XW7510

SM

R7500

4.7

402

MF-LF

5%

1/16W

1

2

X5R

1UF

10V

10%

1

2

402-1

C7504

20%

402

CERM

50V

0.001UF

C7512

1

2

MCPCORES0_PHASE_L

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

R7505

CRITICAL

4 3

2 1

MF

1%

0612

1W

0.001

46 96

46 96

NO STUFF

1.00

1%

1/6W

MF

1

402

R7598

2

NO STUFF

C7598

0.001UF

10%

402

X7R

50V

1

2

NO STUFF

1.00

1

2

402

R7599

1%

1/6W

MF

NO STUFF

1

C7599

0.001UF

2

402

10%
50V
X7R

U7500

CRITICAL

QFN

3519

1
13
28

32
31

11

6

33

27

30

23

25

26

24

29

12

10

15
16

14

9

18

17

20

4

2

21

22

7
8

SN0802043

C7562

2

1

CRITICAL

CASE-C2-SM

POLY-TANT

2.5V

20%

330UF

SM

XW7500

1 2

20%
10V
CERM
402

0.1UF

C7530

1

2

R7564

1%

100K

402

1/16W
MF-LF

1

2

402

MCP_PROD

54.9K

1/16W

MF

0.1%

R7571

1

2

402

1/16W

48.7K

MF

0.1%

1

2

R7570

MCP_PROD

10V

CERM-X7R

C7564

603

5%

0.22UF

1

2

1

805

10%
X5R

25V

10UF

2

C7500

C7501

10%
X5R

402-1

10V

1UF

1

2

X5R

10V

10%

402-1

1UF

C7503

1

2

4.7UF

C7502

20%

6.3V
X5R-CERM
402

1

2

C7561

25V

10%

603-1

X5R

1UF

1

2

C7565

CASE-C2-SM

2.5V

20%

330UF

POLY-TANT

CRITICAL

1

2

C7566

603

X5R

20%

10UF

4V

1

2

402

100K

1/16W

1%

MF-LF

R7514

1

2

C7560

20%
16V

TANTD

68UF

SM

CRITICAL

1

2

SOT563

SSM6N15FEAPE

Q7580

3

5

4

402

1/16W

MCP_PROD

MF

475K

0.1%

R7580

1

2

SSM6N15FEAPE

SOT563

Q7580

6

2

1

MCP_PROD

402

1/16W
MF

237K

0.1%

R7581

1

2

SOT563

SSM6N15FEAPE

Q7582

3

5

4

MCP_PROD

402

1/16W
MF

110K

0.1%

R7582

1

2

402

1/16W

5%

0

MF-LF

R7521

1

2

NO STUFF

1%

402

MF-LF

61.9K

1/16W

R7520

1

2

PLACEMENT_NOTE=Place next to C7516

SM

XW7516

1

2

67

RES,MTL FILM,1/16W,48.7K,1,0402,SMD,LF

114S0382

R7570

1

MCP_A01

1

MCP_A01

114S0400

RES,MTL FILM,1/16W,76.8K,1,0402,SMD,LF

R7571

114S0422

1

R7582

MCP_A01

RES,MTL FILM,1/16W,130K,1,0402,SMD,LF

R7580

1

MCP_A01

114S0482

RES,MTL FILM,1/16W,523K,1,0402,SMD,LF

MCP_A01Q

R7581

1

RES,MTL FILM,1/16W,237K,1,0402,SMD,LF

114S0447

R7571

MCP_A01Q

1

114S0404

RES,MTL FILM,1/16W,84.5K,1,0402,SMD,LF

114S0453

1

R7581

MCP_A01

RES,MTL FILM,1/16W,267K,1,0402,SMD,LF

MCP_A01Q

114S0373

1

R7570

RES,MTL FILM,1/16W,40.2K,1,0402,SMD,LF

R7580

MCP_A01Q

114S0458

1

RES,MTL FILM,1/16W,301K,1,0402,SMD,LF

MCP_A01Q

R7582

1

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

114S0411

SYNC_DATE=05/21/2008

75

123

31

051-7656

SYNC_MASTER=RXU_K20

5V_S0 / MCP CORE REGULATOR

=PPVIN_S0_P5VRTS0_MCPCORE

PP5V_S0_MCPREG_VCC

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

=P5V_RTS0_EN

MCP_VID<0>

P5V_RTS0_ILIM

P5VRTS0_VSNS

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GATE_NODE=TRUE

P5VRTS0_LGATE

=PPMCPCORE_S0_REG

=PP5V_S0_REG

P5VRTS0_PHASE

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP5VRTS0_LL_RC
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

PPMCPCORE_LL_RC

MCPCOREISNS_N

MCPCOREISNS_P

MCP_VID0_L MCP_VID1_L MCP_VID2_L

MCP_VID<2>

MCP_VID<1>

PP3V3_S0_MCP_VREF

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

P5V_RTS0_PGOOD

MCPCORES0_PGOOD

=MCPCORES0_EN

P5V_RTS0_FB

P5VRTS0_BOOT

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

PP5V_S0_MCPREG_LDO

VOLTAGE=5V

PMCPCORE_VSNS

MCPCORES0_REFIN

VOLTAGE=2V

PP2V_S0_MCPREG_REF

MCPCORES0_ILIM

MCPCORES0_BOOT
MCPCORES0_UGATE

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE

GND_MCPREG_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE

MCPCORES0_PHASE
MCPCORES0_LGATE

MIN_LINE_WIDTH=0.5 MM

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 MM

P5VRTS0_UGATE

MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

PVIN_P5VRTS0_MCPCORE

8

8 8

Preliminary

BST

V5V

FB

TON

VLDO

FBL

EN/PSV

DL

ILIM

LX4

LX3

LX2

LX0

DH

VIN2

VIN1

PGOOD

ENL

LX5

LX1

VIN0

VIN3
VIN4VOUT

PGNDAGND

IN

IN

NC

NC

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

NC

MAX CURRENT = 6A

PWM FREQ = 400KHZ

MF-LF

1%

402

1/16W

130K

R7651

1

2

CRITICAL

33UF

16V

20%

POLY-TANT

CASED2E-SM

C7650

1

2

X5R
603-1

1

2

C7651

1UF

10%
25V

402

1UF

X5R

10V

10%

C7657

1

2

MLPQ

SC417

CRITICAL

U7600

4

30

34

8

12

14

29

32

1

2

27

13
23
24
25
28
33

15161718192021

22

26

31

3

6
9
10
11
35

7

5

SM

XW7660

1 2

1%

402

MF-LF

1/16W

7.15K

R7654

1 2

10%
CERM

10V
402

0.22UF

C7653

12

CRITICAL

IHLP2525CZ-SM1

2.2UH-14A

L7650

1 2

POLY-TANT

150UF

20%

6.3V
CASE-B2-SM

CRITICAL

C7654

1

2

11K

1/16W

1%

MF-LF
402

CRITICAL

R7656

1

2

10%
16V
CERM
402

0.01UF

C7655

1

2

1/16W
MF-LF

402

1%

CRITICAL

12.1K

R7655

1

2

NO STUFF

CERM

50V

5%

180PF

402

C7656

1

2

5%

402

MF-LF

1/16W

10

R7699

1 2

20%

0.001UF

402

CERM

50V

C7658

1

2

1%

56.2K

1/16W
MF-LF

402

R7630

1 2

SM

XW7661

1 2

SM

XW7662

1 2

402

1%

1

2

R7631

10K

MF-LF

1/16W

NO STUFF

10%

0.01UF

402

CERM

16V

C7630

1

2

NO STUFF

10%

330PF

50V
CERM
402

C7631

1

2

NO STUFF

67

67

50V

0.001UF

X7R
402

10%

C7698

1

2

603

1/10W
MF-LF

5%

1

2

R7698

1

CRITICAL

0.002

1206

MF

1%

1/4W

R7650

1 2
3 4

46 96

46 96

CPU VTT Power Supply

76

123

051-7656

SYNC_MASTER=RXU_K20

SYNC_DATE=05/21/2008

31

CPUVTTS0_LL

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

=PPCPUVTT_S0_REG

=PPVIN_S0_CPUVTTS0

1V05CPU_N

PPCPUVTT_S0_REG_XW

CPUVTTS0_ILIM

CPUVTTS0_TONE

CPUVTTS0_PGOOD

=CPUVTTS0_EN

CPUVTTS0_VBST

1V05CPU_P

CPUVTTS0_LL_XW

PP5V_S0_CPUVTTS0_R

VOLTAGE=5V
MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm

CPUVTTS0_FB

=PP5V_S0_CPUVTTS0

PPCPUVTT_ISNS_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

CPUVTTS0_LL_RC

GND_CPUVTTS0_SGND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=0V

CPUVTTS0_FB_C

8

8

8

Preliminary

VIN

SW1

SW2

GND

RUN2

RUN1

VFB1
VFB2

PAD

THRML

VI

SW

EN

FB

GND

OUT

IN

S

D

G

S

D

G

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD
COMP

FSET

ISEN

FB
VO

BOOT

VIN

THRML

PAD

VCC

G

D

S

GND

VIN

VFB

ITH/RUN SENSE-

NGATE

GND

BIAS

OUT

ADJ

IN

SHDN*

PAD

THRML

THRM_PAD

PVINAVIN

PG

MODE

OVT FB

AGND PGND

SWEN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

<Ra>

<Rb>

Vout = 0.6V * (1 + Ra / Rb)

(GND)

(=PP1V05_S5_REG)

(P1V05S5_VFB)

VOUT = 1.804V

Vout = 1.001V

<Rb>

<Ra>

<Rb>

?MA MAX OUTPUT

VOUT = 10V

F=550KHZ?

<Ra>

<Rb>

FW BOOST POWER

VOUT = 0.8V * (1 + RA / RB)

MAX CURRENT = 300MA

INPUT RAIL IS 3.3V S0

FREQ = 1Mhz

Vout = 1.052V

MAX CURRENT = 300MA

<Ra>

<Rb>

Vout = 1.5V

<Ra>

Vout = 0.6V * (1 + Ra/Rb)

MAX Current = 1.2A

(L7770 limit)

5A max output

f = 400 kHz

Vout = 1.052V

VOUT = 0.6V * (1 + Ra / Rb)

MCP 1.05V AUXC Supply

F = 2.25 MHZ

(Switcher limit)

0.3A max output

S5 power required for output discharge feature

<Rb>

EXPRESSCARD 1.5V_S0 SUPPLY

1.8V S0 Switcher

f = 2.25 MHz

<Ra>

300mA max output
(Switcher limit)

1.8V S0 Switcher / 1.0VFW SWITCHER

MCP79 PLL VLDO

LTC3547

DFN-HF

5

2
7

4
6

9

1

8

3

U7700

CRITICAL

CERM

402

5%

10PF

50V

C7701

1

2

603

X5R

6.3V

20%

10uF

C7760

1

2

TPS62202

SOT23-5

CRITICAL

U7760

3

4

2

5

1

10UH-0.55A-330MOHM

PCAA031B-SM

CRITICAL

L7760

1 2

10uF

6.3V
X5R

20%

603

C7762

1

2

1/16W

1%

MF-LF
402

38.3K

1

2

R7752

67

67

4.7

5%

R7751

1 2

1/16W
MF-LF

402

SM

XW7750

1

2

4.7UF

603

6.3V

20%

CERM

C7751

1

2

16V
X5R

2.2UF

603

C7750

1

2

10%

402

10%
10V

CERM

0.22UF

C7770

1

2

1/16W

402

MF-LF

2.0K

1%

R7779

1

2

603-1

10%
X5R

1UF

25V

C7775

1

2

4.42K

MF-LF

1%
1/16W

402

R7781

1

2

402

MF-LF

1%

3.74K

1/16W

R7780

1

2

SM

PLACEMENT_NOTE=Place XW7775 next to C7775

XW7775

1

2

CRITICAL

B2-SM

2.0V

POLY-TANT

330UF

20%

C7771

1

2

CRITICAL

2.2UH-8.0A

PCMB065T-SM

L7770

1 2

402

4V

4.7UF

20%

X5R

C7776

1

2

CRITICAL

SI7110DN

PWRPK-1212-8-HF

Q7770

5

4

1 2 3

PWRPK-1212-8-HF

SI7108DN

CRITICAL

Q7771

5

4

1 2 3

QFN

ISL6269

CRITICAL

U7750

13

5

4

6

3

7

9

11

10

16

15

12

17

14

2

1

8

2

1

R7753

1/16W

402

MF-LF

1%

100K

10%

402

CERM

50V

470PF

C7754

1

2

2

1

C7755

5%

402

CERM

50V

22PF

10%

402

CERM

16V

0.01UF

C7753

1

2

10%

1UF

X5R

25V

603-1

1

2

C7752

CRITICAL

4.7UH-10A

PCMC063T-SM

L7795

1 2

10%
16V

1UF

402

X5R

C7794

1

2

1%

1206

MF-LF

1/4W

1.00M

R7795

1

2

402

5%

50V

CERM

33PF

C7795

1

2

1/16W
MF-LF
402

1%

86.6K

R7796

1

2

10UF

16V

10%

X5R

1206

C7790

1

2

16V
POLY-TANT

33UF

20%

CASED2E-SM

C7799

1

2

CRITICAL

SUPERSOT-6

FDC796NG

Q7790

7

4

12356

0612

MF

0.5%

0.02

1W

R7790

1 2
3 4

1%

402

MF-LF

1/16W

38.3K

R7797

1

2

402

50V

CERM

0.0012UF

10%

C7797

1

2

CRITICAL

SOT23-6

LTC1872

U7790

2

1

6

4

3

5

CASED2E-SM

20%

33UF

POLY-TANT

16V

C7798

1

2

CRITICAL

STPS1L30MF

DO222-SM

D7790

1 2

C7741

1UF

CERM

402

10%

6.3V

1

2

6.3V

1UF

10%

CERM

1

2

402

C7742

5

7

4

DFN

6

1

3

2

CRITICAL

LTC3025

U7740

402

1%

66.5K

1/16W
MF-LF

1

2

R7740

MF-LF

40.2K

402

1/16W

1%

1

2

R7741

2

1

R7742

0

5%

NO STUFF

1/16W
MF-LF
402

16V
402

X5R

10%

0.1UF

C7711

1

2

TPS62510

BQA

CRITICAL

U7710

3

9

6

4

7

5

8

2

10

1

11

CRITICAL

2.2UH-1.2A

PCAA031B-SM

P1V5EXPS0_SW

L7710

1 2

5%

1

402

MF-LF

1/16W

R7712

1

2

CERM
805

20%

22UF

6.3V

CRITICAL

C7710

1

2

402

MF-LF

1/16W

1%

100K

R7711

1

2

SM

XW7710

1 2

22PF

402

CERM

5%
50V

C7712

1

2

402

1%
MF-LF

1/16W

150K

R7710

1

2

805

CERM

6.3V

20%

CRITICAL

22UF

C7713

1

2

402

5%

1

1/16W
MF-LF

2

100

R7743

2

1

402

C7740

1UF

CERM

10%

6.3V

402

MF-LF

1/16W

1%

280K

R7783

1

2

10PF

CERM

5%

50V
402

C7782

1

2

1%

187K

1/16W
MF-LF
402

R7782

1

2

2.2UH-1.2A

CRITICAL

PCAA031B-SM

L7780

1 2

402

4.7UF

20%
4V
X5R

C7785

1

2

67

6.3V

402-LF

20%

CERM

2.2UF

C7700

1

2

MF-LF

280K

1%

402

1/16W

R7701

1

2

PCAA031B-SM

2.2UH-1.2A

CRITICAL

L7700

1 2

4.7UF

20%

X5R

4V

402

C7705

1

2

562K

MF-LF

1%

402

1/16W

R7700

1

2

77

123

31

051-7656

SYNC_DATE=05/21/2008

SYNC_MASTER=RXU_K20

Misc Power Supplies

PP3V3_S0_MCP_PLL_VLDO_BIAS

=PP3V3_S0_MCP_PLL_VLDO

=PP1V8_S0_MCP_PLL_VLDO

=PP1V0_FW_REG

P5V_P1V05S5_V5FILT

P1V05S5_ISEN

GATE_NODE=TRUE

P1V05S5_DRVL

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

P1V5EXPS0_FB

P1V0FW_VFB

=PP1V8_S0_REG

TP_P1V5_EXP_S0_PGOOD

=PP3V3_S3_P1V5EXPS0

P1V5EXPS0_AVIN

P1V5EXPS0_SGND

=PP1V05_S5_MCP

P1V05S5_VSNS

=P1V5_EXP_S0_EN

=PP1V05_S0_FET

=PP1V5_EXP_S0

=PP1V05_S0_MCP_PLL_UF

P1V05_S0_MCP_PLL_UF_ADJ

P1V8GPU_SW

=P1V8FB_EN

=PP3V3_GPU_P1V8S0

=PP1V8_GPUIFPX_REG

PFWBOOST_ITH_R

PFWBOOST_NGATE

PFWBOOST_ITH

PFWBOOST_SW

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

=PPVIN_PFWBOOST

PFWBOOST_BOOST

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PFWBOOST_FB

=PFWBOOST_REG

PFWBOOST_SENSE

P1V8S0_LX

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

=PP3V3_S3_P1V8S0

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

P1V0FW_SW

MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V05S5_DRVH

GATE_NODE=TRUE

P1V05_S5_PGOOD

=P1V05S5_EN

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5V_P1V05S5

VOLTAGE=5V

=PPVIN_S0_P1V05S5

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

GND_P1V05S5_SGND

MIN_NECK_WIDTH=0.2 mm

P1V05S5_VFB

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

SWITCH_NODE=TRUE

P1V05S5_LL

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V05S5_VBST

P1V8S0_VFB

=PP3V3_FW_P1V0FW

=P1V8S0_EN

=PPVIN_S0_P1V05S5

P1V05_S5_COMP

P1V05S5_COMP_R

P1V05_S5_FSET

84

68

23

83

66

66

8

8

8

8

8

8

9

8

8

8

67

8

8

8

8

8

8

8

8

Preliminary

OUT

IN

OUT

OUT

OUT

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

OUT

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

IN

OUT

OUT

OUT

OUT

IN

IN

OUT

SENSE

CT

VDD

GND

RESET*

MR*

ADJ1

SEL

ADJ2

REF

VCC

TMR

GND

THRM_PAD

RST*

OUT

OUT

OUT

OUT

Y

B

A

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

NC

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1.1V GPU ENABLE

SMC_PM_G2_ENABLE

Sleep (S3)

Other S0 RAILS

IG high
EG PM_ALL_GPU_PGOOD

PM_ALL_GFX_PGOOD

(PM_SLP_S3_L)

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

3.3V 1,05V S5 ENABLE

Run (S0)

State

Soft-Off (S5)

Battery Off (G3Hot)

1

1

1

0

1

0

1

PM_SLP_S4_L

0 0

0

1

PM_SLP_S3_L

0

place XW0402 if needed to save trace space for pin 7,8

3.3V,5V S3 ENABLE

TPS3808 MR* HAS INTERNAL PULLUP

1.5V 1.05V COMPARED TO 0.5V

(PM_S4_STATE_L)

TIE TMR TO GND
TRST = 200MS

S5 rail PWRGD

Unused PGOOD signal

S0 ENABLE

EXT GPU PWRGD Pullup

Graphic MEM ENABLE

LTC2909 THRESHOLD IS 3.136V

V4MON THRESHOLD IS 0.6V

4) GDDR3 1.8V
BOMOPTION: EG

3) GPUVcore

V3MON THRESHOLD IS 0.6V

2) GPU_3.3V

1) 1.1V

up in the following order:

V2MON THRESHOLD IS 2.866V

G96 GPU requires rails to come

GPUVCORE ENABLE

U7871 IS TO REPLACE U7870

NC

83 84

16V

NO STUFF

0.022UF

20%

CERM

PLACEMENT_NOTE=near U9500

402

C7850

1

2

EG_PWRSEQ_HW

1/16W

402

MF-LF

0

5%

PLACEMENT_NOTE=near U9500

R7852

12

EG_PWRSEQ_HW

5%

1/16W

MF-LF

402

10K

R7851

1 2

100K

EG_PWRSEQ_HW

5%

MF-LF

1/16W

402

R7850

1 2

84

1/16W

100K

MF-LF

5%

402

R7853

1

2

1/16W

10K

MF-LF

5%

402

R7892

1

2

77 84

PLACEMENT_NOTE=near U8900

10%

0.01UF

CERM

16V

402

EG_PWRSEQ_HW

C7861

1

2

PLACEMENT_NOTE=near U8900

1/16W

5%

MF-LF

402

0

EG_PWRSEQ_HW

R7864

1 2

EG_PWRSEQ_HW

402

1/16W

5%

MF-LF

100K

R7863

1 2

68

63

100K

5%

MF-LF

402

PLACEMENT_NOTE=near U1400

1/16W

R7810

1

2

21 39 41 42

66 83 84

NO STUFF

PLACEMENT_NOTE=near U7880

5%

0

402

MF-LF

1/16W

R7891

1 2

64

SOT563

SSM6N15FEAPE

EG_PWRSEQ_HW

Q7850

6

2

1

EG_PWRSEQ_HW

SOT563

SSM6N15FEAPE

Q7850

3

5

4

EG_PWRSEQ_HW

SSM6N15FEAPE

SOT563

Q7861

6

2

1

SOT563

SSM6N15FEAPE

EG_PWRSEQ_HW

Q7861

3

5

4

62

66

65

6.3V

10%

0.47UF

402

CERM-X5R

PLACEMENT_NOTE=near U7750

C7801

1

2

402

5%
1/16W
MF-LF

100

R7802

12

PLACEMENT_NOTE=near U7201

NO STUFF

0.068UF

10%

402

10V
CERM

C7802

1

2

5%

MF-LF

402

1/16W

PLACEMENT_NOTE=near U7750

5.1K

R7801

12

100K

MF-LF

PLACEMENT_NOTE=near U4900

402

1/16W

5%

R7858

1

2

41

64

68

45

68

64

68

65

66

402

5%

MF-LF

1/16W

PLACEMENT_NOTE=nearU7951

0

R7884

1

2

64

62

NO STUFF

PLACEMENT_NOTE=nearU7951

402

CERM-X5R

6.3V

10%

0.47UF

C7884

1

2

5%
1/16W

10K

MF-LF

402

PLACEMENT_NOTE=nearU7700

R7883

1

2

1/16W

5%

402

PLACEMENT_NOTE=nearQ7971

MF-LF

0

R7882

1

2

PLACEMENT_NOTE=nearU7600

5%

MF-LF

402

1/16W

33K

R7881

1

2

402

5%

PLACEMENT_NOTE=nearU7500

1/16W
MF-LF

22K

R7880

1

2

402

100K

5%
1/16W
MF-LF

R7890

1

2

MF-LF

PLACEMENT_NOTE=near U1400

1/16W

402

5%

100K

R7879

1

2

7

21 33 36 41 82 84

PLACEMENT_NOTE=nearU7700

402

10%

6.3V

0.47UF

CERM-X5R

C7883

1

2

PLACEMENT_NOTE=nearQ7971

10%

402

CERM-X5R

6.3V

0.47UF

NO STUFF

C7882

1

2

PLACEMENT_NOTE=nearQ7600

0.47UF

10%

CERM-X5R

6.3V

402

C7881

1

2

CERM-X5R

PLACEMENT_NOTE=nearU7500

10%

402

6.3V

0.47UF

C7880

1

2

62

PLACEMENT_NOTE=near U7300

5%

1/16W

5.1K

402

MF-LF

R7811

1

2

PLACEMENT_NOTE=near U7300

0.47UF

CERM-X5R
402

10%

6.3V

C7810

1

2

PLACEMENT_NOTE=near U7201

402

1/16W

5%

0

MF-LF

R7812

1

2

PLACEMENT_NOTE=near U7201

0.47UF

6.3V

402

CERM-X5R

10%

NO STUFF

C7812

1

2

MF-LF

1/16W

402

5%

PLACEMENT_NOTE=near U7880

0

R7894

1

2

100K

402

MF-LF

1/16W

5%

R7840

1

2

0.1uF

20%
10V

CERM

402

C7840

1

2

SOT23-6

TPS3808G33DBVRG4

U7840

4

2

3

15

6

0.001UF

20%
50V

CERM

402

C7841

1

2

CLOSE TO U7870 & U7871

20%

402

CERM

10V

0.1uF

C7870

1

2

NO STUFF

6

7

LTC2909

DFN

U7870

8

5

4

1

9

2

3

EG_PWRSEQ_HW

402

5%

100K

MF-LF

1/16W

PLACEMENT_NOTE=near U7972

R7889

1

2

9

67

68 84

402

5%
1/16W

10K

MF-LF

PLACEMENT_NOTE=nearU9900

R7885

1

2

5.1K

5%

MF-LF

402

PLACEMENT_NOTE=nearU9900

1/16W

R7886

1

2

10%

6.3V

402

CERM-X5R

0.47UF

PLACEMENT_NOTE=nearU9900

C7885

1

2

CERM-X5R
402

10%

6.3V

0.47UF

PLACEMENT_NOTE=nearU9900

C7886

1

2

87

87

5%01/16W

MF-LF

402

EG_PWRSEQ_HW

R7888

1 2

402

5%

100

1/16W
MF-LF

R7878

1 2

SOT665

TC7SZ08AFEAPE

U7880

2

1

3

5

4

ISL88042IRTEZ

1

4

TDFN

U7871

8

9

3
5
6

2

7

25 41 84

CERM

402

16V

20%

PLACEMENT_NOTE=near U9500

0.022UF

NO STUFF

C7869

1

2

CERM
402

0.1UF

10V

20%

C7889

1

2

1/16W

5%

402

0

EG_PWRSEQ_HW

PLACEMENT_NOTE=near U9500

MF-LF

R7869

1 2

MF-LF

5%

1/16W

402

100K

EG_PWRSEQ_HW

R7868

1 2

SYNC_DATE=09/09/2008

123

78

31

051-7656

SYNC_MASTER=YMA_K20

Power Control

=PP1V05_S0_VMON

=PP1V5_S0_VMON

P3V3S5_EN

=PP3V3_GPU_PWRCTL

P1V8_S0GPU_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

GPU_S0_EN_L

EXTGPU_PWR_EN

=PP3V3_S0_PWRCTL

P1V1_GPU_EN_RC

=PP3V3_S5_PWRCTL

SMC_PM_G2_EN

=P1V8FB_EN

=PP3V3_S0_VMON

=PP3V3_S0_VMON

=PP1V5_S0_VMON

=PP1V05_S0_VMON

MAKE_BASE=TRUE

MCPCORES0_EN

MAKE_BASE=TRUE

P1V2_S0_EN

=PP3V3_S0_VMON

S0PGOOD_PWROK

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

P1V8FB_PGOOD

=PP3V3_S0_PWRCTL

=P1V8S0_EN

P1V05S0_EN

=P2V5S0_EN

S0_PWR_PGOOD

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

DDRREG_PGOOD

CPUVTTS0_PGOOD

CPUVTTS0_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

MCPDDR_EN

P2V5S0_EN

MAKE_BASE=TRUE

=MCPDDR_EN

PM_SLP_S3_L

=P1V1GPU_EN

MCPCORES0_PGOOD

P1V8S0_PGOOD

GPUVCORE_EN_RC_L

S0PGOOD_PWROK

PM_SLP_S4_L

MAKE_BASE=TRUE

GPUVCORE_EN_RC_L

=P5VS3_EN

=DDRREG_EN

=P3V3S3_EN

P1V05_S5_PGOOD

RSMRST_PWRGD

CT

=PP3V3_GPU_PWRCTL

=PP3V42_G3H_PWRCTL

S0PGOOD_PWROK

PM_ALL_GPU_PGOOD

=GPUVCORE_EN

=PP3V3_S5_PWRCTL

=PP3V3_S0_PWRCTL

=P5V_RTS0_EN

=P3V3S0_EN

=PBUSVSENS_EN

=P1V2S0_EN

=CPUVTTS0_EN

=MCPCORES0_EN

=PP3V3_S0_PWRCTL

P5V3V3_PGOOD

P5V_RTS0_PGOOD

=PP3V3_S5_PWRCTL

ALL_SYS_PWRGD

MAKE_BASE=TRUE

P5VS3_EN

GPUVCORE_PGOOD

ALL_GFX_PGOOD_R

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

P1V1_GPU_EN

P1V8_S0GPU_EN_RC

MAKE_BASE=TRUE

GPUVCORE_EN

P1V1GPU_PGOOD

P3V3GPU_EN

MAKE_BASE=TRUE

PM_SLP_S3_L_R

MAKE_BASE=TRUE

PM_G2_P1V05S5_EN

=P1V05S5_EN

MAKE_BASE=TRUE

DDRREG_EN

GPUVCORE_EN_RC

67

67

67

67

67

67

67

67

67

67

67

67

67

67

67

67

67

8

8

8

8

8

8

8

8

8

8

67

83

8

63

67

67

67

66

41

8

8

67

9

8

8

8

8

77

83

Preliminary

IN

D

SG

D

SG

IN

D

SG

D

SG

IN

IN

IN

D

SG

D

SG

D

SG

D

SG

IN

S

D

G

D

G S

SGD

SGD

S

D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.3V S3 FET

0.087 A (EDP)

CHANNEL

1.5V S0 FET

RDS(ON)

1.5V S0 FET

26 mOhm @4.5V

In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low
before rail is turned off, and remains low until after rail turns back on or DIMMs
will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp
on VTT rail, which pulls all CKE signals low through VTT termination resistors.

MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep.

MCP79 DDR FETs

81mW max power

90mA max load @ 0.9V

LOADING

RDS(ON)

P-TYPE

3.3V S0 FET

RDS(ON)

CHANNEL

LOADING

RDS(ON)

CHANNEL

MOSFET

3.3V GPU FET

LOADING 1.1 A (EDP)

MOSFET

FDC638P

P-TYPE

MOSFET

3.3V S0 FET

2.9 A (EDP)

26 mOhm @4.5V

P-TYPE

FDC606P

FDC606P

APN 376S0651

LOADING

CHANNEL

MOSFET

N-TYPE

SI7108DN

5.4 A (EDP)

5 mOhm @4.5V

SI7108DN

LOADING

APN 376S0651

5 mOhm @4.5V

1.05V S0 FET

48 mOhm @4.5V

N-TYPE

CHANNEL

3.3V GPU FET

RDS(ON)

MOSFET

5.1 A (EDP)

1.05V S0 FET

3.3V S3 FET

9

63

SOT563

SSM6N15FEAPE

Q7975

3

5

4

1/16W

5%

100K

MF-LF

402

R7976

1

2

0.001UF

402

CERM

20%
50V

NO STUFF

C7976

1

2

SOT563

SSM6N15FEAPE

Q7975

6

2

1

10

5%

402

1/16W
MF-LF

R7975

1

2

X5R

1UF

10V

10%

402

C7971

1

2

0.01UF

CERM

402

16V

10%

C7970

1 2

1/16W

1K

MF-LF

5%

402

R7970

1 2

5%

51K

MF-LF

402

1/16W

R7972

1

2

67 84

10V

CERM

402

20%

0.1UF

C7902

1

2

402

0.068UF

CERM

10%
10V

C7903

1

2

SOT563

SSM6N15FEAPE

Q7971

6

2

1

402

5%

47K

MF-LF

1/16W

R7971

1 2

5%

10K

MF-LF

1/16W

402

R7901

1 2

MF-LF

1/16W

402

100K

5%

R7903

1

2

SOT563

SSM6N15FEAPE

Q7971

3

5

4

67

0.01UF

10%

402

CERM

16V

C7910

1 2

0.033UF

402

10%

X5R

16V

C7911

1

2

MF-LF

402

5%

1/16W

47K

R7910

1 2

MF-LF

10K

402

5%

1/16W

R7912

1

2

10%

402

CERM

16V

0.01UF

C7930

1 2

16V

0.033UF

10%

X5R
402

C7931

1

2

47K

5%
1/16W
MF-LF

402

R7930

1 2

MF-LF

100K

402

1/16W

5%

R7932

1

2

67

67

SOT563

SSM6N15FEAPE

Q7912

6

2

1

SOT563

SSM6N15FEAPE

Q7912

3

5

4

SM

FDC638P_G

CRITICAL

Q7910

1

2

5

6

3

4

10V
CERM
402

10%

0.068UF

C7953

1

2

220K

402

1/16W
MF-LF

5%

R7952

1 2

SSM6N15FEAPE

SOT563

Q7951

6

2

1

100K

MF-LF

1/16W

5%

402

R7951

1 2

MF-LF

1/16W

402

5%

10K

R7953

1

2

SOT563

SSM6N15FEAPE

Q7951

3

5

4

67

CRITICAL

PWRPK-1212-8-HF

SI7108DN

Q7901

5

4

1 2 3

SSM3K15FV

SOD-VESM-HF

Q7972

3

1

2

SOT-6

CRITICAL

FDC606P_G

Q7930

1 2 5 6

3

4

SOT-6

CRITICAL

FDC606P_G

Q7970

1 2 5 6

3

4

SI7108DN

PWRPK-1212-8-HF

CRITICAL

Q7953

5

4

1 2 3

31

SYNC_MASTER=YMA_K20

SYNC_DATE=05/19/2008

Power FETs

79

051-7656

123

P3V3S3_SS

=PP3V3_S3_FET

P1V05S0_SS

=PP1V8R1V5_S0_FET

=PP3V3_S0GPU_FET

VTTCLAMP_L

P3V3S3_EN_L

=PP5V_S3_P1V05S0FET

=PP1V05_S0_FET

=PP1V05_S5_P1V05S0FET

=PP3V3_S5_P1V05FET

P1V05_EN_L_RC

=PP3V3_S0_P3V3S0FET

P3V3S0_SS

P3V3GPU_SS

=PP3V3_GPU_P3V3GPUFET

P3V3GPU_EN_L

=PP3V3_S3_P3V3S3FET

P3V3S0_EN_L

MCPDDR_EN_L_RC

MCPDDR_SS

=PP1V8R1V5_S0_MCP_FET

=PP5V_S3_MCPDDRFET

MCPDDR_EN_L

P1V05S0_EN

P1V05_EN_L

=P3V3S0_EN

=P3V3S3_EN

=PP5V_S3_VTTCLAMP

VTTCLAMP_EN

=DDRVTT_EN

=PPVTT_S0_VTTCLAMP

=MCPDDR_EN

=PP3V3_S0_FET

P3V3GPU_EN

66

8

8

8

8

8

8

8

8

8

8

8

8

8

8

8

Preliminary

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

GND_SENSE

VDD_SENSE

PEX_IOVDDQ23

PEX_IOVDDQ25

PEX_IOVDD5

PEX_IOVDDQ1
PEX_IOVDDQ2

PEX_PLLVDD

PEX_IOVDDQ22

PEX_IOVDDQ6

PEX_IOVDD2
PEX_IOVDD3
PEX_IOVDD4

PEX_IOVDDQ9

PEX_IOVDDQ15
PEX_IOVDDQ16
PEX_IOVDDQ17

PEX_IOVDDQ19
PEX_IOVDDQ20
PEX_IOVDDQ21

PEX_IOVDD1

PEX_IOVDDQ14

PEX_IOVDDQ13

PEX_IOVDDQ12

PEX_IOVDDQ8

PEX_IOVDDQ7

PEX_IOVDDQ5

PEX_IOVDDQ4

PEX_IOVDDQ11

PEX_IOVDDQ24

PEX_IOVDDQ18

PEX_IOVDDQ3

PEX_IOVDDQ10

NC

SYMBOL 2 OF 9

PEX_RFU2

PEX_TX2

PEX_TX3

PEX_TX3*

PEX_TX4

PEX_TX4*

PEX_TX5*

PEX_TX6*

PEX_RFU1

PEX_RX5

PEX_RX3*

PEX_RX4

PEX_RX0

PEX_RX1

PEX_RX0*

PEX_RX9
PEX_RX9*

PEX_RX4*

PEX_RX5*

PEX_RX10

PEX_TX13*

PEX_TX1

PEX_TX7

PEX_TX10

PEX_TX10*

PEX_TX11

PEX_TX11*

PEX_TX12

PEX_TX12*

PEX_TX13

PEX_TX14

PEX_TX14*

PEX_TX15*

PEX_TX9*

PEX_TX8*

PEX_TX2*

PEX_TX1*

PEX_TX0*

PEX_RX15*

PEX_RX12*

PEX_RX11*

PEX_RX10*

PEX_RX8*

PEX_RX7*

PEX_RX6*

PEX_RX2*

PEX_TX0

PEX_TX9

PEX_TX5

PEX_TX6

PEX_TX8

PEX_TX15

PEX_RX3

PEX_RX6

PEX_RX7

PEX_RX8

PEX_RX11

PEX_RX12

PEX_RX2

PEX_RX1*

PEX_RX15

PEX_RX14*

PEX_RX14

PEX_RX13
PEX_RX13*

PEX_TSTCLK_OUT*

PEX_TSTCLK_OUT

PEX_TERMP

PEX_CLKREQ*

PEX_RST*

PEX_REFCLK*

PEX_REFCLK

PEX_TX7*

SYMBOL 1 OF 9

NC

NC
NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

1500mA

(NONE)

(NONE)

180mA

250mA

PEX 1.1V Current = 2A

BOM options provided by this page:

- =PP1V2_GPU_PEX_PLLXVDD

Signal aliases required by this page:

- =PP1V2_GPU_PEX_IOVDD

- =PP1V2_GPU_PEX_IOVDDQ

9

90

40216V X5R10%

0.1uF

C8081

1 2

40216V X5R10%

0.1uF

C8082

1 2

9

90

9

90

40216V X5R10%

0.1uF

C8079

1 2

40216V X5R10%

0.1uF

C8080

1 2

9

90

9

90

40216V X5R10%

0.1uF

C8077

1 2

40216V X5R10%

0.1uF

C8078

1 2

9

90

9

90

40216V X5R10%

0.1uF

C8075

1 2

40216V X5R10%

0.1uF

C8076

1 2

9

90

9

90

402X5R16V10%

0.1uF

C8073

1 2

402X5R16V10%

0.1uF

C8074

1 2

9

90

0.1uF

402X5R16V10%

C8020

1 2

9

90

402X5R16V10%

0.1uF

C8071

1 2

402X5R16V10%

0.1uF

C8072

1 2

9

90

9

90

40216V X5R10%

0.1uF

C8069

1 2

40216V X5R10%

0.1uF

C8070

1 2

9

90

9

90

40216V X5R10%

0.1uF

C8067

1 2

16V10%

0.1uF

402X5R

C8021

1 2

40216V X5R10%

0.1uF

C8068

1 2

9

90

9

90

402X5R16V10%

0.1uF

C8065

1 2

40216V X5R10%

0.1uF

C8066

1 2

9

90

9

90

402X5R16V10%

0.1uF

C8063

1 2

402X5R16V10%

0.1uF

C8064

1 2

9

90

16V10% 402X5R

0.1uF

C8050

1 2

9

90

402X5R16V10%

0.1uF

C8061

1 2

402X5R16V

0.1uF

10%

C8062

1 2

9

90

9

90

40216V X5R10%

0.1uF

C8059

1 2

40216V X5R10%

0.1uF

C8060

1 2

9

90

9

90

40216V X5R10%

0.1uF

C8057

1 2

0.1uF

16V 402X5R10%

C8051

1 2

40216V X5R10%

0.1uF

C8058

1 2

16V10% 402X5R

0.1uF

C8048

1 2

16V10% 402X5R

0.1uF

C8049

1 2

16V10% 402X5R

0.1uF

C8046

1 2

4.7UF

20%

6.3V

603

CERM

C8001

1

2

1UF

10%

402

CERM

6.3V

C8003

1

2

CERM

20%

402

10V

0.1UF

C8004

1

2

16V10% 402X5R

0.1uF

C8047

1 2

0.1UF

CERM
402

20%
10V

C8005

1

2

4.7UF

20%
CERM

6.3V

603

C8016

1

2

603

20%

4.7UF

CERM

6.3V

C8015

1

2

CERM-X5R

22UF

6.3V

805

20%

C8000

1

2

16V 402X5R10%

0.1uF

C8044

1 2

402

CERM

6.3V

10%

1UF

C8002

1

2

6.3V

20%

805

CERM-X5R

22UF

C8006

1

2

603

6.3V

4.7UF

CERM

20%

C8007

1

2

6.3V

10%

402

CERM

1UF

C8008

1

2

1UF

10%

6.3V
CERM
402

C8009

1

2

10V

20%

0.1UF

CERM
402

C8010

1

2

10V
CERM
402

0.1UF

20%

C8011

1

2

0.1UF

402

CERM

10V

20%

C8017

1

2

10% X5R 40216V

0.1uF

C8045

1 2

0603

10NH-600MA

L8015

1 2

16V10% 402X5R

0.1uF

C8042

1 2

OMIT

BGA

NB9P-GS

U8000

AD19

H32

AD6

AF6
AG6

AJ5

D35

AK15

AL7

E7

E35

F7

M7

A2

P6

P7
R7

U7

V6

AB7

AK16

AK17
AK21

AK24
AK27

AG11

AG24
AG25

AG26

AJ14
AJ15

AJ19

AJ21
AJ22

AJ24
AJ25

AG12

AJ27

AK18
AK20

AK23

AK26
AL16

AG13

AG15

AG16
AG17

AG18
AG22

AG23

AG14

AD20

OMIT

NB9P-GS

BGA

U8000

AR13

AR16

AR17

AG19
AG20

AM16

AP17

AN17

AN19

AP19

AN28

AP28

AR28
AR29

AP29
AN29

AN31
AP31

AR31

AR32

AR34

AP34

AR19

AR20

AP20

AN20

AN22
AP22

AR22
AR23

AP23
AN23

AN25

AP25

AR25

AR26

AP26

AN26

AG21

AJ17

AJ18

AL17

AM17

AM18

AM19

AM27

AM28

AL28
AK28

AK29
AL29

AM29
AM30

AM31

AM32

AN32

AP32

AL19

AK19

AL20

AM20

AM21
AM22

AL22
AK22

AL23
AM23

AM24

AM25

AL25

AK25

AL26

AM26

2.49K

MF-LF

402

1%

1/16W

R8050

1 2

1/16W

1%

402

MF-LF

200

R8060

1 2

1/16W
MF-LF

402

0

5%

R8020

1 2

16V10% 402X5R

0.1uF

C8043

1 2

10% 16V 402X5R

0.1uF

C8040

1 2

0.1uF

16V10% 402X5R

C8041

1 2

16V10% 402

0.1uF

X5R

C8038

1 2

X5R16V10% 402

0.1uF

C8039

1 2

16V10% 402X5R

0.1uF

C8036

1 2

402X5R

0.1uF

16V10%

C8037

1 2

16V10% 402X5R

0.1uF

C8034

1 2

0.1uF

16V10% 402X5R

C8035

1 2

16V10% 402X5R

0.1uF

C8032

1 2

16V10% 402X5R

0.1uF

C8033

1 2

16V10% 402X5R

0.1uF

C8030

1 2

16V10% 402X5R

0.1uF

C8031

1 2

16V10% 402X5R

0.1uF

C8028

1 2

16V10% 402X5R

0.1uF

C8029

1 2

16V10% 402X5R

0.1uF

C8026

1 2

16V10% 402X5R

0.1uF

C8027

1 2

16V10% 402X5R

0.1uF

C8024

1 2

16V10% 402X5R

0.1uF

C8025

1 2

0.1uF

16V10% X5R 402

C8022

1 2

16V10% 402X5R

0.1uF

C8023

1 2

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

17 90

17 90

9

16V X5R 40210%

0.1uF

C8055

1 2

16V X5R 40210%

0.1uF

C8056

1 2

9

90

9

90

9

90

9

90

402X5R16V10%

0.1uF

C8085

1 2

402X5R16V10%

0.1uF

C8086

1 2

9

90

9

90

40216V X5R10%

0.1uF

C8083

1 2

402X5R16V10%

0.1uF

C8084

1 2

9

90

31

051-7656

SYNC_DATE=04/01/2008

80

123

NV G96 PCI-E

SYNC_MASTER=M98_MLB

PEG_D2R_C_P<14>
PEG_D2R_C_N<14>

PEG_D2R_C_P<15>
PEG_D2R_C_N<15>

PEX_TSTCLK_P
PEX_TSTCLK_N

PEG_R2D_C_P<10>

GPU_RESET_R_L

GPU_RESET_L

PEG_R2D_N<12>

PEG_R2D_P<13>
PEG_R2D_N<13>

PEG_R2D_N<14>

=PP1V1_GPU_PEX_IOVDDQ
=PP1V1_GPU_PEX_IOVDD

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 mm

PP1V1_GPU_PEX_PLLVDD_F

MIN_NECK_WIDTH=0.25 mm

PEG_R2D_C_P<3>

PEG_R2D_N<7>

PEG_R2D_N<10>

PEG_R2D_N<11>

PEG_R2D_C_P<12>

PEG_R2D_N<15>

PEG_R2D_C_P<6>

PEG_R2D_P<11>

GPU_GND_SENSE

PEG_R2D_N<0>

PEG_R2D_N<1>

PEG_R2D_P<1>

PEG_R2D_P<0>

PEG_R2D_C_N<13>

PEG_R2D_C_N<8>

PEG_R2D_C_P<8>

PEG_R2D_C_P<7>

PEG_R2D_C_N<6>

PEG_R2D_C_P<5>

PEG_R2D_C_N<4>

PEG_R2D_C_N<3>

PEG_R2D_C_N<2>

PEG_R2D_C_P<2>

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_N<1>

PEG_D2R_P<1>

PEG_D2R_N<2>

PEG_D2R_P<2>

PEG_D2R_N<3>

PEG_D2R_P<3>

PEG_D2R_N<4>

PEG_D2R_P<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_N<8>

PEG_D2R_P<9>

PEG_D2R_N<6>

PEG_D2R_P<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<9>

PEG_D2R_N<14>

PEG_D2R_P<13>

PEG_D2R_N<12>

PEG_D2R_N<10>

PEG_D2R_N<11>

PEG_D2R_P<11>

PEG_D2R_P<12>

PEG_D2R_P<14>

PEG_D2R_N<13>

PEG_D2R_P<15>

PEG_D2R_N<15>

PEG_R2D_P<2>
PEG_R2D_N<2>

PEG_R2D_C_P<4>

PEG_D2R_C_N<5>

PEG_D2R_C_N<6>

PEG_R2D_N<3>

PEG_R2D_P<4>

PEG_R2D_N<9>

PEG_R2D_P<10>

PEG_D2R_C_P<1>

PEG_D2R_C_P<7>
PEG_D2R_C_N<7>

PEG_D2R_C_P<10>

PEG_D2R_C_P<11>
PEG_D2R_C_N<11>

PEG_D2R_C_P<12>
PEG_D2R_C_N<12>

PEG_D2R_C_N<9>

PEG_D2R_C_N<8>

PEG_R2D_N<8>

PEG_R2D_N<6>

PEG_D2R_C_P<9>

PEG_D2R_C_P<5>

PEG_D2R_C_P<6>

PEG_D2R_C_P<8>

PEG_R2D_P<3>

PEG_R2D_P<6>

PEG_R2D_P<7>

PEG_R2D_P<8>

PEG_R2D_P<15>

PEG_R2D_P<14>

NO_TEST=TRUE

NC_GPU_DFM

PEG_R2D_C_N<5>

PEG_R2D_C_N<7>

PEG_R2D_C_N<1>

PEG_R2D_N<5>

PEG_R2D_P<5>

PEG_R2D_N<4>

PEG_R2D_P<9>

PEG_R2D_C_N<10>

PEG_R2D_C_N<9>

PEG_R2D_C_P<11>

PEG_R2D_C_N<12>

PEG_R2D_P<12>

PEG_D2R_C_N<4>

PEG_D2R_C_P<4>

PEG_D2R_C_N<3>

PEG_D2R_C_P<3>

PEG_D2R_C_N<2>

PEG_D2R_C_P<2>

PEG_D2R_C_N<1>

PEG_D2R_C_N<0>

PEG_D2R_C_P<0>

GPU_VDD_SENSE

PEG_D2R_C_N<10>

PEG_D2R_P<10>

PEG_D2R_C_N<13>

PEG_D2R_C_P<13>

PEX_TERMP_PD

PEG_R2D_C_P<13>

TP_PEX_CLKREQ_L

PEG_R2D_C_N<11>

PEG_R2D_C_P<9>

PEG_R2D_C_P<1>

PEG_R2D_C_N<0>

PEG_R2D_C_P<0>

PEG_R2D_C_P<15>

PEG_R2D_C_P<14>

PEG_R2D_C_N<14>

PEG_R2D_C_N<15>

PEG_CLK100M_N

PEG_CLK100M_P

=PP1V1_GPU_PEX_PLLXVDD

90

90

90

90

90

90

90

90

8

8

90

90

90

90

90

77

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90 90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

90

77

90

90

90

7

8

Preliminary

SYMBOL 7 OF 9

FBVDDQ FBVDDQ

SYMBOL 8 OF 9

GNDGND

VDD VDD

SYMBOL 9 OF 9

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Signal aliases required by this page:

???A @ ???MHz 1.8V GDDR3

Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF

BOM options provided by this page:

- =PP1V8_GPU_FBVDDQ

(NONE)

(NONE)

- =PPVCORE_GPU

Power aliases required by this page:

???A @ ???/???MHz Core/Mem Clk for VDD

4.7UF

20%

X5R-CERM
402

6.3V

C8101

1

2

4.7UF

20%

X5R-CERM

6.3V

402

C8100

1

2

4.7UF

20%

X5R-CERM

6.3V

402

C8102

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8107

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8112

1

2

20%
10V

402

CERM

0.1UF

C8117

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8106

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8105

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8110

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8111

1

2

CERM

20%

402

0.1UF

10V

C8116

1

2

10V

0.1UF

20%

402

CERM

C8115

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8104

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8109

1

2

20%
10V

402

CERM

0.1UF

C8114

1

2

0.1UF

20%
10V
CERM
402

C8113

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8108

1

2

6.3V

0.47UF

10%

CERM-X5R
402

C8103

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C8160

1

2

10%

6.3V

0.47UF

402

CERM-X5R

C8166

1

2

0.1UF

20%
10V

402

CERM

C8159

1

2

6.3V
CERM

20%

603

4.7UF

C8151

1

2

0.1UF

20%
10V

402

CERM

C8158

1

2

10V

20%

0.1UF

402

CERM

C8165

1

2

10V

20%

0.1UF

402

CERM

C8164

1

2

CERM

6.3V

20%

603

4.7UF

C8150

1

2

20%

0.1UF

10V

402

CERM

C8157

1

2

0.1UF

20%
10V

CERM

402

C8163

1

2

10V

20%

CERM

0.1UF

402

C8162

1

2

10V

0.1UF

20%

402

CERM

C8156

1

2

0.1UF

402

CERM

20%
10V

C8122

1

2

CERM

0.1UF

402

20%
10V

C8121

1

2

0.1UF

402

CERM

20%
10V

C8120

1

2

402

CERM

10V

0.1UF

20%

C8119

1

2

CERM
402

20%
10V

0.1UF

C8118

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C8161

1

2

CERM-X5R

10%

6.3V

402

0.47UF

C8167

1

2

402

6.3V

10%

CERM-X5R

0.47UF

C8169

1

2

402

6.3V

10%

0.47UF

CERM-X5R

C8168

1

2

402

6.3V

10%

CERM-X5R

0.47UF

C8171

1

2

402

6.3V

10%

CERM-X5R

0.47UF

C8170

1

2

BGA

OMIT

NB9P-GS

U8000

B18

E21

G8
G9

G17

G18
G22

H29
J14

J15

J16

J17

J20

J21

J22
J23

J24
J29

N27

P27
R27

T27

U27

U29
V27

V29

V34
W27

Y27
AA27

AA29

AA31

AB27

AB29
AC27

AD27

AE27
AJ28

BGA

NB9P-GS

U8000

B3

B33

V24
V31

Y11
Y13

Y15

Y17
Y19

Y21

Y23
Y25

C2

AA2

AA5
AA11

AA12
AA13

AA14

AA15
AA16

AA17

AA18

C34

AA19

AA20

AA21
AA22

AA23
AA24

AA25

AA34

AB12
AB14

E6

AB16
AB18

AB20

AB22
AB24

AC9
AD2

AD5

AD11
AD13

E9

AD15

AD17
AD21

AD23

AD25
AD31

AD34
AE11

AE12

AE13

E12

AE14

AE15

AE16
AE17

AE18

AE19
AE20

AE21
AE22

AE23

E15

AE24
AE25

AG2

AG5
AG31

AG34

AK2
AK5

AP33
AK31

E18

AK34

AL6
AL9

AL12

AL15
AL18

AL21

AL24
AL27

AL30

E24

AN2

AN34

AP3
AP6

AP9

AP12
AP15

AP18

AP21
AP24

E27

AP27
AP30

B6

E30

F2

F5

F31
F34

J2

J5
J31

J34

L9

B9

M2

M5
M11

M13

M15
M17

M19

M21
M23

M25

B12

M31

M34

N11
N12

N13

N14
N15

N16

N17
N18

B15

N19
N20

N21

N22
N23

N24

N25
P12

P14

P16

B21

P18

P20
P22

P24

R2

R5

R31

R34
T11

T13

B24

T15
T17

T19
T21

T23

T25
U11

U12

U13
U14

B27

U15

U16
U17

U18
U19

U20

U21
U22

U23

U24

B30

U25

V2

V5

V9

V12
V14

V16

V18
V20

V22

OMIT

BGA

NB9P-GS

U8000

L11

L20

AC20
AC21

AC22

AC23
AC24

AC25
AD12

AD14

AD16
AD18

L21

AD22

W20

L22

L23

L24
L25

M12
M14

M16

M18

L12

M20

M22

M24
P11

P13

P15
P17

P19
P21

P23

L13

P25
R11

R12

R13
R14

R15

R16
R17

R18
R19

L14

R20

R21
R22

R23

R24
R25

T12

T14
T16

T18

L15

T20

T22

T24
V11

V13

V15
V17

V19

V21

V23

L16

V25

W11
W12

W13

W14
W15

W16

W17
W18

W19

L17

AD24
W21

W22
W23

W24

W25
Y12

Y14

Y16
Y18

L18

Y20

Y22
Y24

AB11
AB13

AB15

AB17
AB19

AB21

AB23

L19

AB25

AC11

AC12
AC13

AC14
AC15

AC16

AC17
AC18

AC19

NV G96 CORE/FB POWER

SYNC_MASTER=M98_MLB

81

123

051-7656

31

SYNC_DATE=04/01/2008

=PPVCORE_GPU

=PP1V8_GPU_FBVDDQ

8

8

Preliminary

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT

OUT
OUT

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI
BI

BI

BI
BI

BI
BI

BI
BI

BI

BI
BI

BI

BI

BI

BI
BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT

OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN
IN
IN
IN

IN

IN

OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT

OUT

OUT

OUT

OUT

BI

BI

BI

BI

BI

BI

BI

BI

IN
IN
IN
IN
IN
IN
IN
IN

OUT
OUT
OUT

OUT

OUT

OUT
OUT
OUT

D

SG

IN

OUT OUT

OUT

OUT

OUT

OUT

FBC_D8

FBC_CMD2
FBC_CMD3

FBC_RFU0
FBC_RFU1*

FBC_RFU7*

FBC_RFU6

FBC_RFU5*

FBC_RFU4

FBC_RFU3*

FBC_RFU2

FBC_D63

FBC_D62

FBC_D21

FBC_D24
FBC_D25
FBC_D26

FBC_D0

FBC_D2

FBC_CMD1

FBC_CMD0

FBC_D5

FBC_D3
FBC_D4

FBC_D6
FBC_D7

FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20

FBC_D23

FBC_D28

FBC_D31

FBC_D34

FBC_D32
FBC_D33

FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55

FBC_CMD26

FBC_CMD25

FBC_CMD24

FBC_CMD23

FBC_CMD22

FBC_CMD20

FBC_CMD19

FBC_CMD17

FBC_CMD16

FBC_CMD14

FBC_CMD13

FBC_CMD11

FBC_CMD10

FBC_CMD9

FBC_CMD8

FBC_CMD7

FBC_CMD6

FBC_CMD5

FBC_CMD4

FBC_CMD21

FBC_CMD18

FBC_CMD15

FBC_CMD12

FBC_D1

FBC_D58

FBC_D57

FBC_D56

FBC_D27

FBC_D29
FBC_D30

FBC_D35

FBC_D22

FBC_CLK0*

FBC_CLK0

FBC_CLK1

FBC_CLK1*

FBC_DQM0
FBC_DQM1
FBC_DQM2
FBC_DQM3
FBC_DQM4
FBC_DQM5
FBC_DQM6
FBC_DQM7

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_DQS_WP1

FBC_DQS_WP0

FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FB_DLLAVDD1

FBC_DEBUG

FB_PLLAVDD1

FB_VREF

FBC_CMD28

FBC_CMD27

FBC_CMD30

FBC_CMD29

FBC_D61

FBC_D60

FBC_D59

SYMBOL 4 OF 9

FBA_D62

FBA_D60

FBA_D59

FBA_D57

FBA_D55

FBA_D52

FBA_D48

FBA_D43

FBA_D39

FBA_D36

FBA_D34

FBA_D32

FBA_D30

FBA_D28

FBA_D27

FBA_D26

FBA_D25

FBA_CMD0

FBA_CMD7

FBA_CMD9

FBA_D5

FBA_CMD1

FBA_D0
FBA_D1

FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6

FBA_CMD8

FBA_CMD10
FBA_CMD11

FBA_CMD15

FBA_CMD14

FBA_CMD13

FBA_CMD12

FBA_D14
FBA_D15

FBA_D17

FBA_D20

FBA_D23
FBA_D24

FBA_D33

FBA_D35

FBA_D38

FBA_D40
FBA_D41
FBA_D42

FBA_D44
FBA_D45
FBA_D46
FBA_D47

FBA_D49
FBA_D50
FBA_D51

FBA_D53
FBA_D54

FBA_D56

FBA_CMD24

FBA_CMD23

FBA_CMD22

FBA_CMD21

FBA_CMD20

FBA_CMD19

FBA_CMD18

FBA_CMD17

FBA_CMD16

FBA_D22

FBA_D19

FBA_D16

FBA_CMD25

FBA_D31

FBA_D18

FBA_D3

FBA_D11

FBA_D10

FBA_D9

FBA_D8

FBA_D7

FBA_D6

FBA_D4

FBA_D2

FBA_D37

FBA_D21

FBA_D29

FBA_DQM5
FBA_DQM6

FBA_DQS_RN0

FBA_DQM7

FBA_DQS_RN2

FBA_DQS_RN1

FBA_DQS_RN4

FBA_DQS_RN3

FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1

FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6

FB_DLLAVDD0

FBA_DQS_WP7

FBA_DEBUG

FB_PLLAVDD0

FB_CAL_PU_GND

FB_CAL_PD_VDDQ

FB_CAL_TERM_GND

FBA_CLK1*

FBA_DQM1
FBA_DQM2
FBA_DQM3
FBA_DQM4

FBA_CLK0*

FBA_CLK1

FBA_CLK0

FBA_CMD30

FBA_DQM0

FBA_DQS_WP3

FBA_DQS_WP2

FBA_D58

FBA_D63

FBA_D61

FBA_RFU7*

FBA_RFU1*

FBA_RFU3*
FBA_RFU4
FBA_RFU5*
FBA_RFU6

FBA_RFU2

FBA_RFU0

FBA_D13

FBA_D12

FBA_CMD29

FBA_CMD28

FBA_CMD27

FBA_CMD26

SYMBOL 3 OF 9

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC
NC
NC
NC
NC
NC
NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

Signal aliases required by this page:
(NONE)

BOM options provided by this page:

- =PP1V2_GPU_FBPLLAVDD

(NONE)

- =PP1V8_GPU_FBIO

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

7

72 79 95

72 79 95

72 79 95

79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

7

73 80 95

72 95

72 79 95

72 79 95

72 79 95

72 79 95

CERM

10V

0.1UF

20%

402

C8201

1

2

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

73 80 95

73 80 95

73 80 95

7

73 80 95

73 80 95

73 80 95

73 80 95

80 95

7

73 95

7

73 80 95

7

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

402

MF-LF

5%

10K

1/16W

R8200

1

2

73 80 95

5%
1/16W
MF-LF
402

10K

R8250

1

2

1/16W
MF-LF

33.2

402

1%

PLACEMENT_NOTE=Place close to U8000.

R8291

1

2

NO STUFF

16V

0.1uF

10%

X5R
402

C8296

1

2

1.07K

MF-LF

402

1/16W

1%

R8295

1

2

FERR-220-OHM

0402

CRITICAL

L8200

1 2

48.7

402

MF-LF

1/16W

1%

PLACEMENT_NOTE=Place close to U8000.

R8290

1

2

6.3V
CERM

1UF

10%

402

C8200

1

2

10K

MF-LF

1/16W

5%

402

R8201

1

2

5%
1/16W
MF-LF
402

10K

R8251

1

2

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

72 79 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

73 80 95

NO STUFF

SSM6N15FEAPE

SOT563

Q8295

6

2

1

402

MF-LF

1/16W

1%

2.49K

R8296

1

2

NO STUFF

1.02K

1%
1/16W
MF-LF

402

R8297

1

2

72 73 75

72 79 95 73 80 95

72 79 95

75

73 80 95

75

BGA

NB9P-GS

OMIT

U8000

J19
J18

J27

E17
D17

D23
E23

C17

B19

F19
F23

A22

C22
B17

F24

C25
E22

C20

B22

D18

A19

D22
D20

E19

D19
F18

C19

F22
C23

B20

F21

A20

A23

D21
B23

E20

G21
F20

D11

E11

A11

B8

A8

C8
C11

C10

D12
E13

F17

F15

F10

F16

E16
F14

F13

D13
A13

B13

A14
C16

A17

D8

B16
D16

D24
D26

E25

F25
F27

E28

F28
D29

F8

A25

B25
D25

C26
C28

B28

A28
A29

E29

F29

F9

D30

E31

C33
D33

F32
E32

B29

C29
B31

C31

E8

B32
C32

B34

B35

F12

B11
C13

G19

F11
D10

D15

A16
D27

D28

D34
A34

D9

B10

E14
B14

F26

A26
D31

A31

E10

A10
D14

C14

E26
B26

D32

A32

G11
G12

G14
G15

G24

G25
G27

G28

1/16W

402

MF-LF

1%

40.2

PLACEMENT_NOTE=Place close to U8000.

R8292

1

2

0.1UF

20%
10V
CERM
402

C8202

1

2

20%

0.1UF

10V
CERM
402

C8291

1

2

20%

0.1UF

10V
CERM
402

C8290

1

2

60.4

1%
1/16W
MF-LF

402

R8293

1

2

402

1%

1/16W

60.4

MF-LF

R8294

1

2

NB9P-GS

BGA

OMIT

U8000

K27

L27
M27

AG27
AF27

T32
T31

AC31
AC30

V32

W31

T35
AB31

Y30

Y34
W32

AA30

AA32
Y33

U32

Y31

U31

U34

Y35
W34

V30

U35
U30

U33

AB30
AB33

T33

Y32

W29

AB35

AB34
W35

W33

W30
T34

R30

R32

N35
P35

N34

L33
L32

N33

K31
K30

G30

K32

P31

G32

H30
F30

G31

H33
K35

K33

G34
K34

E33

N30

E34
G33

AG30
AH31

AG32

AF31
AF30

AD30

AC32
AE30

L31

AE32

AF33
AF34

AE35
AE33

AE34

AC35
AB32

AN33

AK32

M32

AL33

AM33

AL31
AK30

AJ30
AH30

AM35

AH33
AH35

AH32

M30

AH34
AM34

AL35

AJ33

L30

P33
P34

T30

P30
P32

J30

H34
AF32

AF35

AL32
AL34

N32

L35

H31
G35

AD32

AC34
AJ31

AJ35

N31

L34
J32

H35

AE31
AC33

AJ32

AJ34

P29
R29

L29
M29

AD29

AE29
AG29

AH29

NV G96 FRAME BUFFER I/F

SYNC_DATE=09/24/2008

82

123

051-7656

31

SYNC_MASTER=K20_MLB

FB_B_DQ<55>

=PP1V1_GPU_FBPLLAVDD

GPU_FB_VREF_UNTERM_L

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

GPU_FB_VREF

FBA_DEBUG

FBCAL_PD_VDDQ

=PP1V8_GPU_FBIO

FB_B_DQ<61>

FB_A_DQ<3>

FB_A_DQ<4>

FB_A_CAS_L

FB_A_MA<11>

FB_A_CS0_L

FB_A_CS1_L

FB_B_DQ<0>

FB_B_DQ<10>
FB_B_DQ<11>

FB_B_DQ<12>

FB_B_DQ<15>

FB_A_DQ<11>

FB_A_DQ<62>

FB_A_DQ<59>

FB_A_DQ<55>

FB_A_DQ<52>

FB_A_DQ<48>

FB_A_DQ<39>

FB_A_DQ<36>

FB_A_DQ<34>

FB_A_DQ<32>

FB_A_DQ<30>

FB_A_DQ<28>

FB_A_DQ<27>

FB_A_DQ<26>

FB_A_DQ<25>

FB_A_LMA<4>

FB_A_DQ<5>

FB_A_RAS_L

FB_A_DQ<0>

FB_A_DQ<1>

FB_A_LMA<5>

FB_A_BA<1>

FB_A_UMA<4>

FB_A_UMA<3>

FB_A_WE_L

FB_A_DQ<14>

FB_A_DQ<15>

FB_A_DQ<17>

FB_A_DQ<20>

FB_A_DQ<23>
FB_A_DQ<24>

FB_A_DQ<33>

FB_A_DQ<35>

FB_A_DQ<38>

FB_A_DQ<40>
FB_A_DQ<41>

FB_A_DQ<42>

FB_A_DQ<44>

FB_A_DQ<45>
FB_A_DQ<46>

FB_A_DQ<47>

FB_A_DQ<49>

FB_A_DQ<50>

FB_A_DQ<51>

FB_A_DQ<53>

FB_A_DQ<54>

FB_A_LMA<3>

FB_A_MA<8>

FB_A_LMA<2>

FB_A_MA<6>

FB_A_MA<9>

FB_A_MA<0>

FB_A_CKE

FB_A_MA<7>

FB_A_DQ<22>

FB_A_DQ<19>

FB_A_DQ<16>

FB_A_DQ<31>

FB_A_DQ<18>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<8>

FB_A_DQ<7>

FB_A_DQ<6>

FB_A_DQ<21>

FB_A_DQ<29>

FB_A_DQM_L<5>
FB_A_DQM_L<6>

FB_A_RDQS<0>

FB_A_DQM_L<7>

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A_RDQS<3>

FB_A_RDQS<5>

FB_A_RDQS<6>

FB_A_RDQS<7>

FB_A_WDQS<0>

FB_A_WDQS<1>

FB_A_WDQS<4>

FB_A_WDQS<5>

FB_A_WDQS<6>

MIN_NECK_WIDTH=0.2 MM

PP1V1_GPU_FBPLLAVDD_F

VOLTAGE=1.1V

MIN_LINE_WIDTH=0.2 MM

FB_A_WDQS<7>

FBCAL_PU_GND

FBCAL_TERM_GND

FB_A_CLK_N<1>

FB_A_DQM_L<1>

FB_A_DQM_L<2>
FB_A_DQM_L<3>

FB_A_CLK_N<0>

FB_A_CLK_P<0>

TP_FBA_CMD30

FB_A_DQM_L<0>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_DQ<61>

FB_A_DQ<13>

FB_A_DQ<12>

TP_FBA_CMD29

TP_FBA_CMD28

FB_A_BA<2>

FB_A_MA<13>

FB_B_CKE

FB_B_CLK_P<0>

FB_B_CLK_N<1>

FB_B_WDQS<7>

FBC_DEBUG

FB_B_MA<8>

FB_B_DQ<26>

FB_B_DQ<5>

FB_B_DQ<3>

FB_B_DQ<4>

FB_B_DQ<6>

FB_B_DQ<7>

FB_B_DQ<9>

FB_B_DQ<8>

FB_B_DQ<13>

FB_B_DQ<14>

FB_B_DQ<16>

FB_B_DQ<17>

FB_B_DQ<18>
FB_B_DQ<19>

FB_B_DQ<20>

FB_B_DQ<21>
FB_B_DQ<22>

FB_B_DQ<23>
FB_B_DQ<24>

FB_B_DQ<27>

FB_B_DQ<28>

FB_B_DQ<29>

FB_B_DQ<34>

FB_B_DQ<33>

FB_B_DQ<37>

FB_B_DQ<43>

FB_B_DQ<58>

FB_B_BA<2>

FB_B_MA<13>

FB_B_MA<1>

FB_B_LMA<3>

FB_B_LMA<2>

FB_B_MA<10>

FB_B_MA<7>

FB_B_MA<12>

FB_B_UMA<5>

FB_B_WE_L

FB_B_CAS_L

FB_B_MA<11>

FB_B_CS0_L

FB_B_CS1_L

FB_B_UMA<3>

FB_B_UMA<4>

FB_B_UMA<2>

FB_B_BA<1>

FB_B_LMA<5>

FB_B_DRAM_RST

FB_B_BA<0>

FB_B_DQ<1>
FB_B_DQ<2>

FB_B_RAS_L

FB_B_LMA<4>

FB_B_DQ<62>

FB_B_DQ<59>

FB_B_DQ<57>

FB_B_DQ<52>

FB_VREF_UNTERM

FB_B_DQ<63>

FB_B_DQ<36>

FB_B_DQ<60>

FB_B_DQ<53>

FB_B_DQ<30>

FB_B_DQ<31>

FB_B_DQ<32>

FB_B_DQ<45>

FB_B_DQ<44>

FB_B_DQ<42>

FB_B_CLK_N<0>

FB_B_CLK_P<1>

FB_B_DQM_L<5>

FB_B_RDQS<0>

FB_B_RDQS<1>
FB_B_RDQS<2>

FB_B_RDQS<3>

FB_B_RDQS<4>

FB_B_RDQS<6>

FB_B_RDQS<7>

FB_B_WDQS<0>

FB_B_WDQS<2>

FB_B_WDQS<4>

FB_B_WDQS<3>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_DQ<25>

TP_FBC_CMD28

TP_FBC_CMD29
TP_FBC_CMD30

FB_B_MA<6>

FB_B_MA<9>

FB_B_MA<0>

FB_B_WDQS<1>

FB_B_RDQS<5>

FB_B_DQ<47>

FB_B_DQ<46>

FB_B_DQM_L<7>

FB_B_DQM_L<6>

FB_B_DQ<50>

FB_B_DQ<35>

=PP1V8_GPU_FBIO

FB_B_DQM_L<4>

FB_B_DQM_L<3>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_DQM_L<0>

FB_B_DQ<48>
FB_B_DQ<49>

FB_B_DQ<54>

FB_B_DQ<41>

FB_B_DQ<40>

FB_B_DQ<39>

FB_B_DQ<38>

FB_B_DQ<56>

FB_B_DQ<51>

=PP1V1_GPU_FBPLLAVDD

FB_A_DQ<63>

FB_A_DQ<60>

FB_A_DQ<58>

FB_A_DQ<57>

FB_A_DQ<56>

FB_A_DQ<43>

FB_A_DQ<37>

FB_A_UMA<2>

FB_A_DQ<2>

FB_A_BA<0>
FB_A_UMA<5>

FB_A_MA<12>

FB_A_DRAM_RST

FB_A_DQM_L<4>

FB_A_RDQS<4>

FB_A_CLK_P<1>

FB_A_MA<1>

FB_A_MA<10>

71

71

71

71

8

8

75

75

75 75

75

75

8

8

Preliminary

IN

IN

IN

IN

BI

BI
BI

BI

BI

BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI
BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN
IN

OUT
OUT

OUT
OUT

IN

IN

IN

IN
IN

IN

IN

OUT

OUT
OUT

OUT

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

BI

IN
IN

BI

BI

IN
IN

IN IN

D

SG

D

SG

D

SG

D

SG

IN IN

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ7

DQ10
DQ11
DQ12
DQ13

DQ15
DQ16

DQ18
DQ19

DQ21

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

A3
A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5
A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

MFHIGH

(1 OF 2)

MFHIGH

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ7

DQ10
DQ11
DQ12
DQ13

DQ15
DQ16

DQ18
DQ19

DQ21

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

A3
A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5
A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

MFHIGH

(1 OF 2)

MFHIGH

VDD0
VDD1

VDD4

VDD3

VDD2

VSS6
VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0
VSSA1

VDDA0
VDDA1

VDD7

VDD6

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VSSQ0

VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

VREF0
VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0
VDD1

VDD4

VDD3

VDD2

VSS6
VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0
VSSA1

VDDA0
VDDA1

VDD7

VDD6

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VSSQ0

VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

VREF0
VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

BI

BI

BI

BI
BI

BI

BI

BI

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =PP1V8_S0_FB_VREFA

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

Signal aliases required by this page:

VRAM4

U8400.J12

U8400.J1U8400.J1

(NONE)

BOM options provided by this page:

Connect to designated pin, then GND

U8400.J12

Connect to designated pin, then GND

549

1%

402

MF-LF

1/16W

R8430

1

2

1.33K

1%
1/16W
MF-LF

402

R8431

1

2

16V

402

X5R

0.1uF

10%

C8403

1

2

16V

10%

X5R
402

0.1uF

C8402

1

2

10%

402

X5R

16V

0.1uF

C8404

1

2

16V

402

X5R

0.1uF

10%

C8401

1

2

402

X5R

16V

0.1uF

10%

C8422

1

2

0.1uF

10%
16V
X5R
402

C8423

1

2

X5R

10%
16V

0.1uF

402

C8424

1

2

10%

0.1uF

16V

402

X5R

C8425

1

2

16V

10%

X5R

0.1uF

402

C8426

1

2

5%
1/16W

402

100

MF-LF

R8449

1

2

1/16W

1%

402

243

MF-LF

R8448

1

2

1%

121

402

1/16W
MF-LF

VRAM4

R8445

1

2

243

MF-LF

402

1%

1/16W

R8446

1

2

402

X5R

16V

10%

0.1uF

C8421

1

2

16V

10%

402

X5R

0.1uF

C8415

1

2

0.1uF

10%
16V

402

X5R

C8410

1

2

5%

1K

402

1/16W
MF-LF

R8440

1

2

402

1%

MF-LF

243

1/16W

R8447

1

2

1%

121

MF-LF

402

1/16W

VRAM4

R8444

1

2

402

121

1%

MF-LF

VRAM4

1/16W

R8443

1

2

1%

121

MF-LF

402

1/16W

VRAM4

R8442

1

2

71 79 95

71 79 95

71 79 95

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 95

71 79 95

71 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 72 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 95

71 72 79 95

71 79 95

71 72 79 95

71 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 79 95

71 79 95

71 79 95

71 79 95

71 72 79 95

71 72 79 95

MF-LF

402

1/16W

1K

5%

R8490

1

2

402

1%

121

1/16W

VRAM4

MF-LF

R8492

1

2

10%

0.1uF

X5R

16V

402

C8471

1

2

0.1uF

X5R
402

10%
16V

C8472

1

2

243

MF-LF

402

1%

1/16W

R8498

1

2

100

MF-LF
402

1/16W

5%

R8499

1

2

1/16W

402

MF-LF

121

1%

VRAM4

R8493

1

2

MF-LF

1%

402

1/16W

121

VRAM4

R8495

1

2

VRAM4

1%

121

402

1/16W
MF-LF

R8494

1

2

243

1/16W

402

1%

MF-LF

R8497

1

2

243

1/16W

1%

402

MF-LF

R8496

1

2

0.1uF

X5R
402

10%
16V

C8473

1

2

0.1uF

X5R
402

10%
16V

C8474

1

2

0.1uF

X5R
402

16V

10%

C8475

1

2

0.1uF

X5R
402

10%
16V

C8476

1

2

0.1uF

402

10%
16V
X5R

C8451

1

2

X5R

0.1uF

10%
16V

402

C8452

1

2

X5R
402

10%
16V

0.1uF

C8460

1

2

402

X5R

0.1uF

10%
16V

C8453

1

2

0.1uF

X5R
402

10%
16V

C8465

1

2

0.1uF

X5R
402

10%
16V

C8454

1

2

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

71 79 95

71 79 95

7

71 79 95

7

71 79 95

71 79 95

71 79 95

X5R

6.3V

603

20%

10UF

C8400

1

2

6.3V

20%

10UF

603

X5R

C8420

1

2

20%

6.3V
X5R
603

10UF

C8450

1

2

20%

6.3V
X5R
603

10UF

C8470

1

2

16V

10%

402

0.01UF

CERM

C8446

1

2

CERM

10%
16V

402

0.01UF

C8496

1

2

931

1/16W
MF-LF

402

1%

R8432

1

2

CERM
402

0.01uF

10%
16V

C8481

1

2

402

MF-LF

1%

1/16W

931

R8482

1

2

1/16W

1%

MF-LF

402

549

R8480

1

2

402

1/16W
MF-LF

1%

1.33K

R8481

1

2

71 72 73
75

71 72 73
75

SSM6N15FEAPE

SOT563

Q8400

6

2

1

SSM6N15FEAPE

SOT563

Q8450

6

2

1

1/16W

1%

MF-LF

931

402

R8435

1

2

549

1/16W

402

MF-LF

1%

R8433

1

2

1.33K

1/16W

402

1%

MF-LF

R8434

1

2

CERM
402

0.01UF

16V

10%

C8431

1

2

SSM6N15FEAPE

SOT563

Q8400

3

5

4

402

10%
16V

0.01uF

CERM

C8482

1

2

1/16W
MF-LF

402

1%

931

R8485

1

2

1/16W

1%

402

MF-LF

549

R8483

1

2

MF-LF

402

1/16W

1%

1.33K

R8484

1

2

SSM6N15FEAPE

SOT563

Q8450

3

5

4

71 72 79 95 71 72 79 95

OMIT

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFH

CRITICAL

U8450

K9

H11

K11

L9

J3

K10

M9

K4
H2

K3
L4

K2

M4

G9
G4

H3

F9

J11

J10

H9

F4

E3

E10
N10

N3

B2
B3

C11

C10
E11

F10

F11
G10

M11

L10
N11

M10

C2

R11
R10

T11
T10

M2

L3
N2

M3

R2
R3

C3

T2

T3

E2

F3

F2
G3

B11

B10

A9

H10

D3

D10
P10

P3

V9

J2

V4

D2
D11

P11

P2

H4

A4

OMIT

CRITICAL

32MX32-900MHZ-MFH

BGA

K4J10324QD-HC11

U8400

K9

H11

K11

L9

J3

K10

M9

K4
H2

K3
L4

K2

M4

G9
G4

H3

F9

J11

J10

H9

F4

E3

E10
N10

N3

B2
B3

C11

C10
E11

F10

F11
G10

M11

L10
N11

M10

C2

R11
R10

T11
T10

M2

L3
N2

M3

R2
R3

C3

T2

T3

E2

F3

F2
G3

B11

B10

A9

H10

D3

D10
P10

P3

V9

J2

V4

D2
D11

P11

P2

H4

A4

OMIT

CRITICAL

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFH

U8400

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1

N4

N9

N12

R1
R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4
E9

E12

H1

H12

A3
A10

G1

G12
L1

L12
V3

V10

J1
J12

B1

B4

L2

L11
P1

P4

P9
P12

T1
T4

T9

T12

B9
B12

D1
D4

D9

D12
G2

G11

CRITICAL

BGA

OMIT

32MX32-900MHZ-MFH

K4J10324QD-HC11

U8450

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1

N4

N9

N12

R1
R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4
E9

E12

H1

H12

A3
A10

G1

G12
L1

L12
V3

V10

J1
J12

B1

B4

L2

L11
P1

P4

P9
P12

T1
T4

T9

T12

B9
B12

D1
D4

D9

D12
G2

G11

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

7

71 79 95

16V
CERM
402

10%

0.01UF

C8432

1

2

31

123

84

SYNC_MASTER=M98_MLB

SYNC_DATE=04/01/2008

051-7656

GDDR3 Frame Buffer A (Bottom)

FB_A_BA<0>

FB_A0_MF

FB_A_CAS_L

FB_A_DRAM_RST

FB_A_CS0_L

FB_A_MA<12>

FB_A_CKE

=PP1V8_GPU_FB_VDDQ

FB_A_MA<8>

=PP1V8_GPU_FB_VDD

FB_A_CS0_L

FB_A_WE_L
FB_A_CAS_L

FB_A1_ZQ

FB_A_DQ<49>

FB_A_DQ<51>

FB_A_DQ<52>

FB_A_DQ<53>

FB_A_DQ<48>

FB_A_DQ<50>

FB_A_DQ<55>

FB_A_DQ<42>

FB_A_DQ<45>

FB_A_DQ<46>

FB_A_DQ<54>

FB_A_DQ<41>

FB_A_DQ<43>

FB_A_DQ<5>

FB_A_DQ<31>

FB_VREF_UNTERM

FB_A_DQM_L<7>

FB_A_RDQS<5>

FB_A_DQ<35>

FB_A_RDQS<4>

FB_A_RDQS<6>

FB_A_WDQS<7>

FB_A_WDQS<5>

FB_A3_VREF_UNTERM_L
FB_A1_VREF_UNTERM_L

FB_A_CLK0_TERM

VOLTAGE=0.9V

FB_A0_VREF

FB_A2_VREF_UNTERM_L

FB_A_BA<1>

FB_A1_VREF

=PP1V8_GPU_FB_VREF_A

FB_A_CLK1_TERM

VOLTAGE=0.9V

FB_A3_VREFFB_A2_VREF

FB_A1_SEN

FB_A_RDQS<7>

FB_A_DRAM_RST

FB_A_DQM_L<5>

FB_A_DQM_L<6>
FB_A_DQM_L<4>

FB_A0_VREF_UNTERM_L

=PP1V8_GPU_FB_VREF_A

=PP1V8_GPU_FB_VDD

FB_VREF_UNTERM

FB_A_DQ<30>

FB_A_DQ<29>

FB_A_DQ<24>

FB_A_MA<1>

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<1>

FB_A_DQ<12>

FB_A_DQ<1>

FB_A_DQ<18>

FB_A_DQ<23>

FB_A_DQ<13>

FB_A_DQM_L<0>

FB_A_DQ<2>

FB_A_DQ<3>

FB_A_DQ<0>

FB_A_DQ<15>

FB_A_DQ<4>

FB_A_DQ<14>

FB_A_DQ<10>

FB_A_DQ<9>

FB_A_DQ<11>

FB_A_DQ<8>

FB_A_DQ<7>

FB_A_DQ<6>

FB_A_DQ<17>

FB_A_DQ<27>

FB_A_DQ<25>

FB_A_DQ<26>
FB_A_DQ<20>

FB_A_DQ<22>

FB_A_DQ<21>

FB_A_DQ<19>

FB_A_DQ<16>

=PP1V8_GPU_FB_VDDQ

FB_A_DQ<34>

FB_A_DQ<39>

FB_A_DQ<38>

FB_A_DQ<37>

FB_A_DQ<36>

FB_A_DQ<32>

FB_A_DQ<33>

FB_A_DQ<47>

FB_A_DQ<44>

FB_A_DQ<62>
FB_A_DQ<40>

FB_A_DQ<61>

FB_A_DQ<63>

FB_A_DQ<58>

FB_A_DQ<59>

FB_A_DQ<56>

FB_A_DQ<57>

FB_A_DQ<60>

FB_A_MA<7>

FB_A_CKE

FB_A_MA<12>

FB_A_CLK_P<1>
FB_A_CLK_N<1>

FB_A_RAS_L

FB_A_WDQS<6>

FB_A_WDQS<4>

FB_A_BA<0>

FB_A_BA<2>FB_A_BA<2>

FB_A_BA<1>

FB_A0_SEN

FB_A0_ZQ

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_WDQS<2>

FB_A_WDQS<3>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_RAS_L

FB_A_WE_L

FB_A_MA<11>

FB_A_MA<10>

FB_A_MA<9>

FB_A_MA<7>

FB_A_MA<0>

FB_A_LMA<2>
FB_A_LMA<3>

FB_A_CLK_P<0>

FB_A_LMA<4>

FB_A_CLK_N<0>

FB_A_LMA<5>
FB_A_MA<6>

FB_A_DQ<28>

FB_A_MA<10>
FB_A_MA<11>

FB_A_MA<9>

FB_A_MA<8>

FB_A_MA<6>

FB_A_UMA<3>

FB_A_MA<1>

FB_A_UMA<5>

FB_A_MA<0>

FB_A_UMA<4>

FB_A_UMA<2>

FB_A1_MF

80 80 79

80 80

79 73

79 79

73 72

73 73

72

9

72

72 72

72

9 8

8

79 79

9

79 79

9

8

8

Preliminary

IN

IN
IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

BI

BI
BI

BI

BI

BI

BI
BI

BI

BI

BI

BI
BI
BI
BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN
IN

IN

IN

OUT

OUT
OUT

OUT

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI
BI
BI
BI

BI
BI

BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

BI

IN
IN

BI

BI

IN
IN

IN IN

D

SG

D

SG

D

SG

D

SG

ININ

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ7

DQ10
DQ11
DQ12
DQ13

DQ15
DQ16

DQ18
DQ19

DQ21

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

A3
A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5
A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

MFHIGH

(1 OF 2)

MFHIGH

CK*

DQ17

CKE

A8/AP

RFU

DQ9

A11

CK

CS0*

DM2

BA2

BA1

BA0

WDQS1

WDQS3

WDQS2

WDQS0

RDQS3

RDQS2

SEN

DQ24

DQ20

DQ1

DQ0

DQ2
DQ3

DQ5
DQ6

DQ4

DQ7

DQ10
DQ11
DQ12
DQ13

DQ15
DQ16

DQ18
DQ19

DQ21

DQ23

DQ22

DQ25
DQ26
DQ27

DQ29

DQ28

DQ30
DQ31

A3
A4

DM3

DM1

DM0

CAS*

WE*

MF

ZQ

RAS*

A5
A6

A9

DQ8

RDQS1

RDQS0

RESET

A10

A7

A2

A1

A0

A12/CS1*

DQ14

MFHIGH

MFHIGH

(1 OF 2)

MFHIGH

VDD0
VDD1

VDD4

VDD3

VDD2

VSS6
VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0
VSSA1

VDDA0
VDDA1

VDD7

VDD6

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VSSQ0

VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

VREF0
VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0
VDD1

VDD4

VDD3

VDD2

VSS6
VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0
VSSA1

VDDA0
VDDA1

VDD7

VDD6

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VSSQ0

VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

VREF0
VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

BI

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Connect to designated pin, then GND

VRAM4

U8500.J12

U8500.J1

U8500.J12

(NONE)

U8500.J1

Connect to designated pin, then GND

BOM options provided by this page:

Signal aliases required by this page:

- =PP1V8_S0_FB_VDD

Power aliases required by this page:

Page Notes

- =PP1V8_S0_FB_VREF_B

402

X5R

10%
16V

0.1uF

C8503

1

2

0.1uF

X5R
402

10%
16V

C8502

1

2

10%

X5R
402

16V

0.1uF

C8504

1

2

X5R

10%
16V

402

0.1uF

C8501

1

2

0.1uF

X5R
402

10%
16V

C8522

1

2

0.1uF

X5R
402

10%
16V

C8523

1

2

0.1uF

X5R
402

10%
16V

C8524

1

2

0.1uF

X5R
402

10%
16V

C8525

1

2

16V

402

0.1uF

X5R

10%

C8526

1

2

100

MF-LF
402

5%
1/16W

R8549

1

2

243

MF-LF

402

1%

1/16W

R8548

1

2

0.1uF

X5R

10%
16V

402

C8521

1

2

0.1uF

X5R
402

10%
16V

C8515

1

2

0.1uF

X5R
402

10%
16V

C8510

1

2

71 80 95

71 80 95

71 80 95

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80

95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

71 73 80 95

7

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

7

71 73 80 95

71 73 80 95

7

71 73 95

71 80 95

71 80 95

71 73 80 95

7

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 73 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 73 80 95

7

71 73 80 95

71 73 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 73 80 95

71 73 80 95

7

71 73 80 95

7

71 73 95

71 73 80 95

71 80 95

71 73 80 95

71 80 95

7

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 80 95

71 80 95

71 80 95

71 80 95

71 73 80 95

71 73 80 95

0.1uF

16V

10%

402

X5R

C8571

1

2

0.1uF

16V

10%

402

X5R

C8572

1

2

1/16W

402

MF-LF

243

1%

R8598

1

2

5%

MF-LF

1/16W

402

100

R8599

1

2

0.1uF

16V
X5R
402

10%

C8573

1

2

0.1uF

X5R
402

10%
16V

C8574

1

2

0.1uF

10%

402

X5R

16V

C8575

1

2

0.1uF

16V

10%

402

X5R

C8576

1

2

16V

10%

402

X5R

0.1uF

C8551

1

2

16V

10%

402

X5R

0.1uF

C8552

1

2

0.1uF

X5R
402

10%
16V

C8560

1

2

0.1uF

X5R
402

10%
16V

C8553

1

2

0.1uF

X5R
402

10%
16V

C8565

1

2

16V

10%

402

X5R

0.1uF

C8554

1

2

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

7

71 80 95

71 80 95

71 80 95

7

71 80 95

7

71 80 95

71 80 95

71 80 95

20%

6.3V
X5R
603

10UF

C8500

1

2

20%

6.3V
X5R
603

10UF

C8520

1

2

X5R

6.3V

20%

603

10UF

C8550

1

2

20%

6.3V
X5R
603

10UF

C8570

1

2

243

1%

402

1/16W
MF-LF

R8546

1

2

243

1%

MF-LF
402

1/16W

R8547

1

2

402

MF-LF

1%

1/16W

VRAM4

121

R8544

1

2

121

1/16W

1%

402

MF-LF

VRAM4

R8545

1

2

1/16W

1%

121

MF-LF

402

VRAM4

R8542

1

2

1K

1/16W
MF-LF

5%

402

R8540

1

2

1/16W

402

121

1%

MF-LF

VRAM4

R8543

1

2

243

MF-LF

402

1/16W

1%

R8596

1

2

243

1%

MF-LF
402

1/16W

R8597

1

2

1/16W

1%

121

MF-LF

VRAM4

402

R8595

1

2

1/16W
MF-LF

121

1%

402

VRAM4

R8594

1

2

1/16W
MF-LF

1%

VRAM4

121

402

R8592

1

2

402

121

1/16W

VRAM4

1%

MF-LF

R8593

1

2

MF-LF

5%

1K

1/16W

402

R8590

1

2

CERM

0.01UF

402

10%
16V

C8596

1

2

16V

10%

402

CERM

0.01UF

C8546

1

2

1.33K

MF-LF

1%

1/16W

402

R8531

1

2

931

1/16W
MF-LF

402

1%

R8532

1

2

0.01uF

CERM
402

16V

10%

C8531

1

2

549

MF-LF

402

1%

1/16W

R8530

1

2

1.33K

402

1/16W

1%

MF-LF

R8581

1

2

931

402

MF-LF

1%

1/16W

R8582

1

2

MF-LF

549

1%

1/16W

402

R8580

1

2

16V

0.01uF

CERM
402

10%

C8581

1

2

71 72 73
75

71 72 73
75

SOT563

SSM6N15FEAPE

Q8500

6

2

1

SOT563

SSM6N15FEAPE

Q8550

6

2

1

402

CERM

16V

10%

0.01uF

C8532

1

2

931

MF-LF

402

1%

1/16W

R8535

1

2

549

1/16W

1%

402

MF-LF

R8533

1

2

1.33K

402

MF-LF

1/16W

1%

R8534

1

2

SOT563

SSM6N15FEAPE

Q8500

3

5

4

10%

402

CERM

0.01uF

16V

C8582

1

2

1/16W

931

MF-LF

402

1%

R8585

1

2

549

MF-LF

402

1%

1/16W

R8583

1

2

1.33K

402

1/16W

1%

MF-LF

R8584

1

2

SOT563

SSM6N15FEAPE

Q8550

3

5

4

71 73 80 95 71 73 80 95

K4J10324QD-HC11

32MX32-900MHZ-MFH

BGA

OMIT

CRITICAL

U8550

K9

H11

K11

L9

J3

K10

M9

K4
H2

K3
L4

K2

M4

G9
G4

H3

F9

J11

J10

H9

F4

E3

E10
N10

N3

B2
B3

C11

C10
E11

F10

F11
G10

M11

L10
N11

M10

C2

R11
R10

T11
T10

M2

L3
N2

M3

R2
R3

C3

T2

T3

E2

F3

F2
G3

B11

B10

A9

H10

D3

D10
P10

P3

V9

J2

V4

D2
D11

P11

P2

H4

A4

CRITICAL

BGA

OMIT

32MX32-900MHZ-MFH

K4J10324QD-HC11

U8500

K9

H11

K11

L9

J3

K10

M9

K4
H2

K3
L4

K2

M4

G9
G4

H3

F9

J11

J10

H9

F4

E3

E10
N10

N3

B2
B3

C11

C10
E11

F10

F11
G10

M11

L10
N11

M10

C2

R11
R10

T11
T10

M2

L3
N2

M3

R2
R3

C3

T2

T3

E2

F3

F2
G3

B11

B10

A9

H10

D3

D10
P10

P3

V9

J2

V4

D2
D11

P11

P2

H4

A4

OMIT

CRITICAL

BGA

32MX32-900MHZ-MFH

K4J10324QD-HC11

U8500

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1

N4

N9

N12

R1
R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4
E9

E12

H1

H12

A3
A10

G1

G12
L1

L12
V3

V10

J1
J12

B1

B4

L2

L11
P1

P4

P9
P12

T1
T4

T9

T12

B9
B12

D1
D4

D9

D12
G2

G11

OMIT

CRITICAL

K4J10324QD-HC11

32MX32-900MHZ-MFH

BGA

U8550

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1

N4

N9

N12

R1
R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4
E9

E12

H1

H12

A3
A10

G1

G12
L1

L12
V3

V10

J1
J12

B1

B4

L2

L11
P1

P4

P9
P12

T1
T4

T9

T12

B9
B12

D1
D4

D9

D12
G2

G11

7

71 80 95

GDDR3 Frame Buffer B (Bottom)

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

051-7656

31

123

85

FB_B_DRAM_RST

FB_B1_SEN

FB_B1_MF

FB_B1_ZQ

FB_B_RAS_L

FB_B_CAS_L

FB_B_WE_L

FB_B_CS0_L

FB_B_MA<12>

FB_B_CKE

FB_B_DQ<6>

FB_B_DQ<3>

FB_B_DQ<2>
FB_B_DQ<1>

FB_B_DQ<7>

FB_B_LMA<2>

FB_B_MA<1>

FB_B_MA<0>

FB_B_DQM_L<0>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_DQM_L<3>

FB_B_DQ<12>

FB_B_DQ<8>

FB_B_DQ<11>
FB_B_DQ<10>

FB_B_DQ<15>

FB_B_DQ<14>

FB_B_DQ<9>

FB_B_DQ<4>

FB_B_DQ<5>

FB_B_UMA<5>
FB_B_MA<6>

FB_B_UMA<4>

FB_B_UMA<3>

FB_B_UMA<2>

FB_B_MA<1>

FB_B_MA<0>

FB_VREF_UNTERM

FB_B3_VREF_UNTERM_L

FB_B1_VREF

FB_B1_VREF_UNTERM_LFB_B0_VREF_UNTERM_L

FB_B0_ZQ

FB_B0_MF

FB_B0_SEN

FB_B_WE_L

FB_B_CS0_L

FB_B2_VREF_UNTERM_L

FB_B_DQ<63>
FB_B_DQ<59>

FB_B_DQ<57>

FB_B_DQ<36>

FB_B_DQ<32>

FB_B_MA<11>

FB_B_BA<1>

FB_B_MA<10>

FB_B_MA<9>

FB_B_WDQS<5>

FB_B_WDQS<7>

FB_B_BA<2>

FB_B_WDQS<4>

FB_B_RDQS<6>

FB_B_RDQS<5>

FB_B_RDQS<4>
FB_B_RDQS<7>

FB_B_WDQS<6>

FB_B_BA<1>

FB_B_DQ<51>

FB_B_DQM_L<5>

FB_B_DQM_L<7>

FB_B_DQ<49>

FB_B_DQ<50>

FB_B_DQM_L<6>

FB_B_BA<0>

FB_B_MA<10>

FB_B0_VREF

FB_B3_VREFFB_B2_VREF

VOLTAGE=0.9V

FB_B_CLK1_TERMFB_B_CLK0_TERM

VOLTAGE=0.9V

FB_B_DQ<48>

FB_B_DQM_L<4>

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FB_VREF_B =PP1V8_GPU_FB_VREF_B

FB_VREF_UNTERM

FB_B_MA<8>

FB_B_MA<7>

FB_B_MA<6>

FB_B_MA<9>

FB_B_LMA<4>

FB_B_LMA<5>

FB_B_LMA<3>

FB_B_CAS_L

FB_B_MA<11>

FB_B_DQ<19>

FB_B_DQ<16>

FB_B_DQ<21>

FB_B_RDQS<0>

FB_B_DQ<0>

FB_B_DQ<13>

FB_B_DQ<17>

FB_B_DQ<23>

FB_B_DQ<18>

FB_B_DQ<20>

FB_B_DQ<22>

FB_B_DQ<24>

FB_B_DQ<29>

FB_B_DQ<30>

FB_B_DQ<25>

FB_B_DQ<26>
FB_B_DQ<27>

FB_B_DQ<31>
FB_B_DQ<28>

FB_B_BA<2>

FB_B_WDQS<2>

FB_B_WDQS<1>

FB_B_RDQS<1>

FB_B_RAS_L

FB_B_DQ<34>

FB_B_DQ<35>

FB_B_DQ<33>

FB_B_DQ<46>

FB_B_DQ<43>

FB_B_DQ<45>

FB_B_DQ<44>

FB_B_DQ<47>

FB_B_DQ<42>

FB_B_DQ<41>

FB_B_DQ<52>

FB_B_DQ<53>
FB_B_DQ<55>

FB_B_DQ<54>

FB_B_DQ<40>

FB_B_MA<7>

FB_B_MA<8>

FB_B_DQ<37>

FB_B_DQ<38>
FB_B_DQ<39>

FB_B_DQ<56>

FB_B_DQ<60>

FB_B_DQ<61>

FB_B_DQ<62>

FB_B_DQ<58>

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FB_VDD=PP1V8_GPU_FB_VDD

FB_B_BA<0>

FB_B_WDQS<3>

FB_B_WDQS<0>

FB_B_RDQS<3>

FB_B_RDQS<2>

FB_B_DRAM_RST

FB_B_MA<12>

FB_B_CKE

FB_B_CLK_P<0>
FB_B_CLK_N<0>

FB_B_CLK_P<1>
FB_B_CLK_N<1>

80 80 79 79

80 80

73 73

79 79

72 72

73 73

9

73 73

9

72 72

80 80

80 80

8

9 9

8

8 8

Preliminary

HDA_BCLK

HDA_SYNC

HDA_SDO

HDA_RST*

SPDIF

BUFRST*

JTAG_TMS

MIOA_CLKIN

MIOA_CLKOUT

JTAG_TCK

GPIO20

GPIO23

HDA_SDI

MIOA_D8

MIOA_D10

MIOA_D9

JTAG_TDI

GPIO2

GPIO11

GPIO7

GPIO5

GPIO4

GPIO3

GPIO1

GPIO0

MIOB_VDDQ_4

MIOB_VDDQ_2

GPIO21

GPIO18

GPIO15
GPIO16
GPIO17

GPIO9

GPIO10

GPIO12
GPIO13
GPIO14

GPIO19

JTAG_TDO

JTAG_TRST*

MIOA_CTL3

MIOA_D7

MIOA_D6

MIOA_D5

MIOA_D4

MIOA_D3

MIOA_D2

MIOA_D1

MIOA_DE

MIOB_CAL_PD_VDDQ

GPIO6

GPIO8

MIOA_D11
MIOA_D12
MIOA_D13

MIOB_D9

MIOB_D8

MIOB_D7

MIOB_D5
MIOB_D6

MIOB_D3

MIOB_D0

MIOB_DE

MIOB_CLKOUT*

MIOB_CTL3

MIOB_CLKOUT

MIOB_CLKIN

MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14

MIOB_D16
MIOB_D17

MIOB_D15

MIOB_HSYNC
MIOB_VSYNC

THERMDP
THERMDN

PGOOD_OUT*

XTAL_IN
XTAL_OUT

XTAL_OUTBUFF

MIOB_D10

MIOB_D4

MIOB_D2

MIOB_D1

MIOA_VSYNC

MIOA_HSYNC

MIOA_D14

MIOA_CLKOUT*

MIOA_D0

MIOB_CAL_PU_GND

MIOB_VDDQ_3

MIOA_VDDQ_3
MIOA_VDDQ_4

MIOA_VDDQ_2

GPIO22

RFU1

ROM_CS*

ROM_SCLK

ROM_SO

STRAP_REF_3V3
STRAP_REF_MIOB

VDD33_5

VDD33_1
VDD33_2
VDD33_3
VDD33_4

RFU1_GND

RFU0

RFU0_GND

ROM_SI

MIOA_VDDQ_1

MIOB_VDDQ_1

MIOA_CAL_PU_GND

MIOA_CAL_PD_VDDQ

MIOA_VREF
MIOB_VREF

TESTMODE

SP_PLLVDD

PLLVDD

VID_PLLVDD

XTAL_SSIN

SYMBOL 6 OF 9

BI
BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI
BI

OUT
OUT
OUT
OUT
OUT

OUT

OUT

IN
IN

IN
IN

IN

IN

IN

OUT

IN

OUT

OUT

OUT

IN

IN

NC
NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Typically <??mA

Signal aliases required by this page:

Power aliases required by this page:

50mA

25mA

65mA

110mA

- =PP1V2_GPU_VID_PLLVDD

- =PP1V2_GPU_PLLVDD

Page Notes

- =PP3V3_GPU_VDD33

- =PP3V3_GPI_MIO

- =PP1V2_GPU_H_PLLVDD

(NONE)

BOM options provided by this page:

(NONE)

(IPD)

40.2K

1%
1/16W
MF-LF
402

R8697

1

2

0.47UF

6.3V
CERM-X5R

10%

402

C8601

1

2

6.3V

402

CERM-X5R

10%

0.47UF

C8602

1

2

10%

X5R

16V

402

0.1uF

C8636

1

2

CERM

4.7UF

603

6.3V

20%

C8635

1

2

0402

FERR-220-OHM

CRITICAL

L8635

1 2

FERR-220-OHM

0402

CRITICAL

L8640

1 2

0.1uF

10%

402

X5R

16V

C8617

1

2

402

5%

10K

1/16W
MF-LF

R8616

1

2

5%

10K

402

1/16W
MF-LF

R8617

1

2

1/16W

402

1%

49.9

MF-LF

R8620

1

2

1/16W

49.9

1%

402

MF-LF

R8622

1

2

1%

MF-LF

49.9

1/16W

402

R8621

1

2

0.1uF

10%

402

X5R

16V

C8619

1

2

10K

5%

MF-LF
402

1/16W

R8618

1

2

5%

10K

1/16W
MF-LF
402

R8619

1

2

CERM

10%

1UF

402

6.3V

C8611

1

2

402

6.3V

1UF

10%

CERM

C8610

1

2

1/16W

1%

MF-LF
402

49.9

R8623

1

2

10%

X5R
402

16V

0.1uF

C8631

1

2

4.7UF

603

CERM

6.3V

20%

C8630

1

2

FERR-220-OHM

0402

CRITICAL

L8630

1 2

4.7UF

603

CERM

6.3V

20%

C8633

1

2

0.1uF

10%

X5R

16V

402

C8641

1

2

CERM

603

6.3V

20%

4.7UF

C8640

1

2

603

20%

6.3V
CERM

4.7UF

C8643

1

2

6.3V
CERM

603

4.7UF

20%

C8637

1

2

CERM-X5R

0.47UF

6.3V

10%

402

C8600

1

2

BGA

OMIT

NB9P-GS

U8000

A4

K1

K2

K4
K5

H7

J4
J6

L1
L2

L4

M4
L7

K3

L5

K6
L6

M6

H3

H2
H1

H4

H5
H6

J7

D7
D6

C7

B7
A7

AP14
AN14

AN16
AR14

AP16

U5

T5

N4

R4
T4

P5

N1

P4

U2
U3

R6

T6
N6

P1
P2

P3
T3

T2

T1
U4

U1

N2

N3

P9

R9
T9

U9

N5

L3

AA7

AA6

AE1

V4

W4
W3

Y1
Y2

AE3

AE2
U6

W6
Y6

W5

W7
V7

Y3
AB3

AB2

AB1
AC4

AC1

AC2
AC3

Y5

W1

AA9

AB9

W9
Y9

AF1

W2

C5

AE9

J25

AK14

J26

K9

C3

D4

D3
C4

AF9

A5

N9

M9

AP35

B4

B5

J9

J10

J11
J12

J13

AD9

B1

B2

D1

D2

40.2K

1%
1/16W
MF-LF
402

R8696

1

2

5%

10K

402

MF-LF

1/16W

R8660

1

2

16V
CERM-X5R
402

0.022UF

10%

C8691

1

2

402

0.022UF

10%
16V
CERM-X5R

C8693

1

2

402

20%
10V
CERM

0.1UF

C8695

1

2

402

16V

10%

CERM-X5R

0.022UF

C8690

1

2

402

16V

10%

CERM-X5R

0.022UF

C8692

1

2

0.1UF

20%
10V

402

CERM

C8694

1

2

402

CERM-X5R

6.3V

10%

0.47UF

C8697

1

2

402

CERM-X5R

6.3V

10%

0.47UF

C8696

1

2

10%

6.3V

1UF

CERM
402

C8698

1

2

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

7

6

6

6

6

6

75

75

75

75

75

7

75

75

75

75

NV G96 GPIO/MIO/MISC

123

31

SYNC_DATE=09/24/2008

051-7656

86

SYNC_MASTER=K20_MLB

GPU_JTAG_TMS

GPU_JTAG_TRST_L

=PP3V3_GPU_VDD33

GPU_ROM_CS_L

GPU_ROM_SCLK
GPU_ROM_SI

GPU_ROM_SO

GPU_STRAP_REF_3V3_PD
GPU_STRAP_REF_MIOB_PD

=PP3V3_GPU_MIO

GPU_XTALIN

GPU_XTALOUTBUFF

GPU_XTALSSIN

GPU_XTALOUT

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.2V

PP1V1_GPU_VID_PLLVDD_F

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm

PP1V1_GPU_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm

VOLTAGE=1.2V

MIN_NECK_WIDTH=0.2 mm

PP1V1_GPU_H_PLLVDD_F

GPU_MIOB_VSYNC

GPU_MIOB_HSYNC

GPU_MIOB_D<14>

GPU_STRAP<1>

GPU_THERMD_P

GPU_THERMD_N

TP_GPU_PGOOD_OUT_L

GPU_GPIO_19

GPU_GPIO_20
GPU_GPIO_21

GPU_GPIO_22

GPU_GPIO_23

GPU_HDA_BCLK

GPU_SPDIF

GPU_GPIO_12
GPU_GPIO_13

GPU_GPIO_14

GPU_GPIO_15

GPU_GPIO_18

GPU_JTAG_TDO

GPU_MIOA_CTL3

GPU_MIOA_D<1>

GPU_MIOA_D<9>

GPU_MIOA_D<7>

GPU_MIOB_D<10>

GPU_MIOB_D<13>

GPU_MIOB_PU_GND

GPU_MIOB_PD_VDDQ

GPU_MIOA_PU_GND

GPU_MIOA_PD_VDDQ

GPU_TESTMODE_PD

GPU_MIOB_D<11>

GPU_MIOB_D<12>

GPU_STRAP<0>

GPU_STRAP<2>

GPU_MIOB_CLKIN

GPU_MIOA_CLKIN

GPU_JTAG_TDI

GPU_JTAG_TCK

GPU_GPIO_17

GPU_HDA_SDI
GPU_HDA_SDO

TP_GPU_BUFRST_L

GPU_HDA_RST_L

GPU_HDA_SYNC

GPU_MIOB_CLKOUT_N

GPU_MIOB_CTL3

GPU_MIOB_DE
GPU_MIOB_D<0>

GPU_MIOB_D<1>

GPU_MIOB_D<2>
GPU_MIOB_D<3>

GPU_MIOB_D<4>
GPU_MIOB_D<5>

GPU_MIOB_D<6>

GPU_MIOB_D<7>
GPU_MIOB_D<8>

GPU_MIOB_D<9>

GPU_MIOB_CLKOUT_P

GPU_MIOA_DE

GPU_MIOA_D<0>

GPU_MIOA_D<2>

GPU_MIOA_D<3>

GPU_MIOA_D<6>

GPU_MIOA_CLKOUT_N

GPU_MIOA_D<4>
GPU_MIOA_D<5>

GPU_MIOA_D<8>

GPU_MIOA_D<10>

GPU_MIOA_D<11>

GPU_MIOA_D<12>
GPU_MIOA_D<13>

GPU_MIOA_D<14>

GPU_MIOA_HSYNC
GPU_MIOA_VSYNC

GPU_MIOA_CLKOUT_P

GPU_GPIO_16

GPU_GPIO_2

GPU_GPIO_3

GPU_GPIO_4
GPU_GPIO_5

GPU_GPIO_6
GPU_GPIO_7

GPU_GPIO_8

GPU_GPIO_9
GPU_GPIO_10

GPU_GPIO_11

GPU_GPIO_0

GPU_GPIO_1

GPU_MIOA_VREF

GPU_MIOB_PD_VDDQ

=PP1V1_GPU_VID_PLLVDD

GPU_MIOB_VREF

GPU_MIOA_PD_VDDQ

GPU_MIOA_PU_GND
GPU_MIOB_PU_GND

=PP3V3_GPU_MIO

=PP3V3_GPU_VDD33

=PP1V1_GPU_H_PLLVDD

=PP1V1_GPU_PLLVDD

75

75

74

75

75

74

8

74

74

8

6

75

75

75

75

8

74

74

74

74

74

8

74

74

74

8

6

8

8

Preliminary

OUT

OUT

OUT

IN

NC

NC

D

GS

IN

IN

IN

IN

BI

BI

BI

BI

BI

OUT

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

STRAP 0

STRAP 1

STRAP 2

ROM_SI

(I2CS requires pullups even if not used)

I2CS ties into SMBus connection page

HPDF

ROM_SCLK

GPU 27MHz Crystal

E 1110 PU 35k

DVI_MODE1

A 1010 PU 15k
B 1011 PU 20k
C 1100 PU 25k

TVMODE[1]

LCD0_BL_PWM

VID0

VID2/MEM_VID

Native Func

4 0100 PD 25k

7 0111 PD 45k

Config Straps

RAMCFG[3]

USER[3]

Strap S1/S2 Bit[3:0] PU/PD Rval

F 1111 PU 45k

2 0010 PD 15k

RAMCFG[2]

D 1101 PU 30k

9 1001 PU 10k

XCLK_277

GP

HPDE

GP

Unused Clocks

Unused signals

DVI_MODE0

G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.

GPIOs

SWAPRDY_A

Isolation FETs for DP MUX inputs

PWR_CTL1

HPDD

HDMI_DETECT1

HDMI_DETECT0

PEX_PLLEN_TERM100

RAMCFG[0]

PCI_DEVID[0]

3GIO_PADCFG[0]

USER[0]

TVMODE[0]

Strapping Bit 0

PCI_DEVID[1]

SLOT_CLK_CFG

Strapping Bit 1

USER[1]

HPDC

Renamed signals

Unused I2C Buses

PWR_CTL0

AC_DET

FAN_PWM

VID1

3 0011 PD 20k

0 0000 PD 5k

Physical

Native Func

3GIO_PADCFG[3]

PCI_DEVID[3]

8 1000 PU 5k

USER[2]

3GIO_PADCFG[2]

PCI_DEVID[4]

SLI_SYNC

MEM_VREF

GPIOs

PCI_DEVID[2]

SUB_VENDOR

TVMODE[2]

Strapping Bit 3

1 0001 PD 10k

Strapping Pin

Strapping Bit 2

RAMCFG[1]

3GIO_PADCFG[1]

Strap S1/S2 Bit[3:0] PU/PD Rval

6 0110 PD 35k

5 0101 PD 30k

LCD0_BL_EN

LCD0_VDD

THERM

ROM_SO

2

1

R8781

1/16W
MF-LF

GPU_SS_INT

10K

5%

402

2

1

R8780

MF-LF

1/16W

5%

402

10K

77

77

74 75

75 95

21

R8783

5%

402

1/16W
MF-LF

0

21

C8780

50V

402

CERM

5%

12pF

21

C8781

CERM

402

5%

12pF

50V

31

42

Y8780

27MHZ

SM-2

CRITICAL

2

1

R8782

NO STUFF

MF-LF

402

10M

5%

1/16W

2

1

R8708

1%

1/16W

45.3K

OMIT

402

MF-LF

2

1

R8710

2.0K

402

MF-LF

1/16W

5%

2

1

R8712

402

1/16W
MF-LF

15.0K

1%

2

1

R8702

402

1/16W

2.0K

NO STUFF

MF-LF

5%

2

1

R8707

OMIT

MF-LF

402

5%

2.0K

1/16W

2

1

R8709

NO STUFF

1/16W

402

1%

MF-LF

4.99K

2

1

R8711

MF-LF

4.99K

NO STUFF

1%

402

1/16W

2

1

R8704

MF-LF

10K

402

1%

1/16W

2

1

R8706

45.3K

1/16W

1%

MF-LF

402

2

1

R8701

402

1%

MF-LF

45.3K

1/16W

2

1

R8703

402

NO STUFF

10K

1%

MF-LF

1/16W

2

1

R8705

MF-LF

402

1/16W

10K

1%

NO STUFF

2

1

3

Q8742

DP_CA_DET_EG_FET

SOD-VESM-HF

SSM3K15FV

2

1

R8742

100K

1%
1/16W
MF-LF

402

DP_CA_DET_EG_FET

81 82 84

81

2

1

R8750

MF-LF

5%

402

4.7K

1/16W

2

1

1/16W

402

5%

MF-LF

R8751

4.7K

2

1

R8752

402

MF-LF

1/16W

5%

4.7K

2

1

R8753

4.7K

1/16W
MF-LF

402

5%

75 81

9

81

75 81

9

81

74

74

74

74

74

74

21

R8743

DP_CA_DET_EG_PLD

402

0

MF-LF

1/16W

5%

84

21

MF-LF

402

5%01/16W

R8798

21

MF-LF

402

5%01/16W

R8799

41

41

77

2

1

R8797

402

MF-LF

1/16W

2.2K

5%

2

1

R8796

402

1/16W

2.2K

5%

MF-LF

75 84

75 84

75 83

71 72 73 75

10K

1

5%

MF-LF

1/16W

NO STUFF

402

R8795

2

5%

MF-LF

402

1

2

10K

1/16W

R8794

2

1

R8793

402

MF-LF

5%

1/16W

10K

2

1

R8792

402

MF-LF

1/16W

5%

10K

R8707

114S0361

RES,MTL FILM,1/16W,30.1K,1,0402,SMD,LF

VRAM_1024_QIMONDA

1

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF

1

R8708

VRAM_512_SAMSUNG

114S0378

RES,MTL FILM,1/16W,30.1K,1,0402,SMD,LF

R8708

1

114S0361

VRAM_512_QIMONDA

VRAM_256_SAMSUNG

R8708

114S0343

1

RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF

R8708

114S0331

1

VRAM_256_HYNIX

RES,MTL FILM,1/16W,15.0K,1,0402,SMD,LF

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF

114S0378

VRAM_1024_SAMSUNG

R8707

1

G96 GPIOs & Straps

SYNC_MASTER=M98_MLB

31

051-7656

SYNC_DATE=05/12/2008

123

87

GPU_XTALOUT

=PP3V3_GPU_VDD33

SMC_GFX_OVERTEMP_R_L

SMC_GFX_THROTTLE_R_L

EG_BKLT_EN

GPIO7_FBVDD_ALTVO

FB_VREF_UNTERM

GPU_GPIO_18

GPU_GPIO_12

GPU_GPIO_11

GPU_GPIO_10

GPU_GPIO_1

GPU_GPIO_2

GPU_GPIO_5

GPU_GPIO_7

GPU_GPIO_8

=PP3V3_GPU_VDD33

DP_IG_DDC_CLK

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

FB_VREF_UNTERM

GPU_ROM_SI

SMC_GFX_THROTTLE_L

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_0

NO_TEST=TRUE

MAKE_BASE=TRUE

DP_EG_HPD

TP_LVDS_EG_BKL_PWM

MAKE_BASE=TRUE

EG_LCD_PWR_EN

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

TP_GPU_GSTATE<0>

MAKE_BASE=TRUE

GPU_ROM_SO

GPU_GPIO_15

DP_IG_DDC_DATA

MAKE_BASE=TRUE

GPIO7_FBVDD_ALTVO

SMC_GFX_OVERTEMP_L

GPU_GPIO_13

GPU_GPIO_14

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUE

=PP3V3_GPU_MIO

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CC_SCL

GPU_I2CC_SCL

GPU_I2CB_SDA

GPU_I2CA_SDA

GPU_I2CA_SCL

GPU_THERMD_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_HDA_SDI

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBA_CMD28

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBC_CMD28

NC_FBA_CMD29

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_LVDS_EG_B_CLK_N

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_22

NO_TEST=TRUE

DP_CA_DET_EG

DP_CA_DET

GPU_STRAP<0>

MAKE_BASE=TRUE

NC_GPU_GPIO_15

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_N<3>

MAKE_BASE=TRUE

NC_FBC_CMD29

NO_TEST=TRUE

GPU_I2CD_SCL

GPU_I2CB_SCL

MAKE_BASE=TRUE

DP_EG_DDC_CLK

GPU_CLK27M

GPU_I2CC_SDA

LVDS_EG_B_DATA_N<3>

LVDS_EG_B_DATA_P<3>

LVDS_EG_B_CLK_N

FB_A_MA<13>

FB_B_MA<13>

TP_FBC_CMD30

LVDS_EG_A_DATA_P<3>

TP_FBA_CMD29

TP_FBC_CMD29

TP_FBA_CMD30

GPU_I2CD_SDA

LVDS_EG_A_DATA_N<3>

GPU_HDA_SDI

NO_TEST=TRUE

NC_GPU_SPDIF

MAKE_BASE=TRUE

GPU_SPDIF

MAKE_BASE=TRUE

NC_FBA_CMD30

NO_TEST=TRUE

GPU_HDA_RST_L

GPU_HDA_BCLK

GPU_HDA_SYNC

GPU_HDA_SDO

TP_FBC_CMD28

TP_FBA_CMD28

NC_FBA_MA<13>

MAKE_BASE=TRUE

NO_TEST=TRUE

GPU_MIOA_VSYNC

GPU_MIOA_HSYNC

GPU_MIOA_DE

GPU_MIOA_CTL3

GPU_MIOA_CLKOUT_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_CLKOUT_P

GPU_MIOA_CLKOUT_P

GPU_MIOA_CLKIN

GPU_MIOA_D<14..10>

GPU_MIOA_D<9..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CD_SDA

GPU_MIOB_CLKIN

GPU_MIOB_CTL3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_DE

GPU_MIOB_DE

GPU_MIOB_CLKOUT_N

GPU_MIOB_CLKOUT_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_HSYNC

GPU_MIOB_HSYNC

GPU_MIOB_VSYNC

GPU_MIOB_D<14..0>

GPU_XTALSSIN

GPU_THERMD_N

GPU_CLK27M_XTALOUT_R

GPU_XTALOUTBUFF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_CTL3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CD_SCL

DP_EG_DDC_CLK

DP_EG_DDC_DATA

=PP3V3_GPU_MIO

GPU_STRAP<2>

GPU_STRAP<1>

GPU_GPIO_6

GPU_GPIO_4

GPU_ROM_CS_L

NC_LVDS_EG_B_DATA_P<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_EG_A_DATA_N<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBB_MA<13>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_HDA_RST_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CPU_HDA_BCLK

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_HDA_SYNC

NC_CPU_HDA_SD0

NO_TEST=TRUE

MAKE_BASE=TRUE

GPU_GPIO_0

GPU_GPIO_3

GPU_GPIO_9

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_GPU_VCORE_VID3

GPU_ROM_SCLK

TP_LVDS_EG_B_CLK_P

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_CS_L

NO_TEST=TRUE

NO_TEST=TRUE

NC_FBC_CMD30

MAKE_BASE=TRUE

LVDS_EG_B_CLK_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOA_D<14..10>

MAKE_BASE=TRUE

NC_GPU_GPIO_21

NO_TEST=TRUE

NC_GPU_GPIO_23

MAKE_BASE=TRUE

NO_TEST=TRUE

GPU_GPIO_16

GPU_GPIO_17

GPU_GPIO_22

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_VSYNC

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOB_D<14..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKOUT_N

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKOUT_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKIN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CLKIN

MAKE_BASE=TRUE

TP_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CTL3

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_MIOA_CLKOUT_N

GPU_GPIO_21

GPU_GPIO_20

GPU_GPIO_19

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GPIO_17

EG_DP_CA_DET

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CC_SDA

GPU_I2CE_SCL

GPU_I2CE_SDA

GPU_I2CH_SDA

GPU_I2CH_SCL

MAKE_BASE=TRUE

DP_EG_DDC_DATA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CE_SCL

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CE_SDA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CH_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CH_SCL

MAKE_BASE=TRUE

LVDS_EG_DDC_DATA

MAKE_BASE=TRUE

GPU_CLK27M_SS

MAKE_BASE=TRUE

GPU_CLK27M

MAKE_BASE=TRUE

GPU_XTALOUT GPU_XTALOUT

GPU_XTALIN

GPU_XTALSSIN

MAKE_BASE=TRUE

GPU_TDIODE_P

MAKE_BASE=TRUE

GPU_TDIODE_N

MAKE_BASE=TRUE

LVDS_EG_DDC_CLK

GPU_GPIO_23

NC_GPU_GPIO_20

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_19

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_18

NO_TEST=TRUE

=PP3V3_S0_DDC_LCD

EG_LCD_PWR_EN

=PP3V3_GPU_VDD33

EG_DP_CA_DET

75

75

75

75

74

74

73

75

75

78

74

8

8

72

84

84

83

74

81

75

74

81

95

75 75

75

96

96

8

8

6

75

75

74

74

74

74

74

74

74

74

74

6

71

7

7

75

75

7

74

75

74

74

75

75

8

76

76

76

76

74

7

76

76 75

76

76

76

76

71

71

71

76

71

71

71

76

76

74

74

74

74

74

74

71

71

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

74

8

74

74

74

74

74

74

7

7

76

74

74

74

7

7

74

74

74

75

76

76

76

76

75

81

95

75

74 74

74

74

47

47

81

74

7

6

75

Preliminary

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

IFPB_TXC*

I2CD_SDA

I2CB_SCL

I2CS_SDA

I2CS_SCL

I2CC_SCL
I2CC_SDA

IFPEF_RSET

I2CA_SDA

DACB_RSET

DACC_VSYNC

DACC_HSYNC

DACC_BLUE

DACC_GREEN

DACC_RED

DACB_CSYNC

DACB_BLUE

DACB_GREEN

DACB_RED

DACA_VSYNC

DACA_RED

IFPF_L0*

IFPF_L0

IFPF_AUX*

IFPF_AUX

IFPE_L3*

IFPE_L3

IFPE_L2*

IFPE_L2

IFPE_L1*

IFPE_L1

IFPE_L0*

IFPE_L0

IFPE_AUX

IFPD_L3*

IFPD_L3

IFPD_L2*

IFPD_L2

IFPD_L0*

IFPD_AUX*

IFPC_L3*

IFPC_L2*

IFPC_L0*

IFPC_AUX*

IFPB_TXD7*

IFPB_TXD7

IFPB_TXD6*

IFPB_TXD5

IFPB_TXD4*

IFPA_TXD2*

IFPA_TXD2

DACC_VREF
DACC_RSET

DACC_VDD

DACB_VDD

DACA_VDD

DACA_VREF
DACA_RSET

DACA_HSYNC

DACA_GREEN

DACA_BLUE

IFPF_L1

IFPF_L1*

IFPF_L2

IFPF_L3

IFPF_L2*

IFPF_L3*

IFPE_AUX*

IFPD_L0

IFPD_L1

IFPD_L1*

IFPC_L3

IFPC_L2

IFPC_L1

IFPC_L0

IFPB_TXD6

IFPB_TXD4

IFPB_TXC

IFPA_TXD3*

IFPA_TXD3

IFPA_TXD1

IFPA_TXD1*

IFPA_TXD0

IFPA_TXD0*

IFPA_TXC*

IFPA_TXC

I2CA_SCL

IFPCD_RSET

IFPC_AUX

I2CE_SDA

I2CE_SCL

I2CD_SCL

I2CB_SDA

I2CH_SCL

IFPC_L1*

I2CH_SDA

IFPD_AUX

IFPB_TXD5*

IFPEF_PLLVDD

IFPAB_PLLVDD
IFPAB_RSET

IFPF_IOVDD

IFPE_IOVDD

IFPD_IOVDD

IFPC_IOVDD

IFPB_IOVDD

IFPA_IOVDD

DACB_VREF

IFPCD_PLLVDD

SYMBOL 5 OF 9

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC

NC
NC

NC
NC
NC

NC

NC
NC
NC

NC
NCNC

NC

NC

NC

NC

NC

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

OUT
OUT

OUT
OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Power inputs must be pulled down if not used

Place at AG10

I2CS must be pulled up if not used

I2CS must be pulled up if not used.

Sum of peak currents: 240mA

Power aliases required by this page:

Signal aliases required by this page:

- =PP3V3_GPU_IFPCD_IOVDD

I2CS addr fixed at 0x9E,0x9F

BOM options provided by this page:

(NONE)

- =PP1V8_GPU_IFPX

Place at AK8

I2CS addr fixed at 0x9E,0x9F

Place at AG9

?mA peak per diff pair

?mA peak for all pairs

?mA peak per diff pair

(NONE)

160mA peak

Place at AJ8

80mA peak

?mA peak for all pairs

Page Notes

402

1%

1K

1/16W
MF-LF

R8850

1

2

0402

FERR-220-OHM

CRITICAL

L8805

1 2

402

10V

CERM

0.1UF

20%

C8806

1

2

FERR-220-OHM

0402

CRITICAL

L8815

1 2

75

75

84 95

84 95

84 95

84 95

84 95

84 95

84 95

84 95

84 95

84 95

84 95

84 95

84 95

7

84 95

603

6.3V
CERM

20%

4.7UF

C8805

1

2

MF-LF
402

10K

5%
1/16W

R8852

1

2

402

MF-LF

10K

5%
1/16W

R8853

1

2

MF-LF
402

10K

1/16W

5%

R8854

1

2

6.3V
CERM

603

20%

4.7UF

C8815

1

2

CERM

402

10V

0.1UF

20%

C8801

1

2

603

6.3V
CERM

20%

4.7UF

C8800

1

2

0402

FERR-220-OHM

CRITICAL

L8800

1 2

402

CERM

10V

20%

0.1UF

C8803

1

2

402

0.1UF

CERM

10V

20%

C8813

1

2

20%
10V

402

CERM

0.1UF

C8811

1

2

4.7UF

20%

CERM

603

6.3V

C8810

1

2

0402

FERR-220-OHM

CRITICAL

L8810

1 2

20%
10V

402

0.1UF

CERM

C8816

1

2

BGA

NB9P-GS

OMIT

U8000

AL14

AM14

AM13

AM15

AK13

AJ12

AK12

AL13

Y4

AB5

AB4

AA4

AB6

AC6

AC5

AJ4

AL4

AM1

AK4

AH7

AG7

AK6

AM2

G1

G4

G3
G2

E3

E4

F4
G5

D5

E5

F6

G6

E2

E1

AG9

AM11

AM12

AM8
AL8

AM10

AM9
AK10

AL10

AK11
AL11

AK9

AJ11

AG10

AP13

AN13

AN8
AP8

AP10

AN10
AR11

AR10

AN11
AP11

AP2

AN3

AJ8

AM7
AM6

AL5

AM5
AM3

AM4

AP1
AR2

AJ9
AK7

AP4

AN4

AK8

AR8
AR7

AP7

AN7
AN5

AP5

AR5
AR4

AE4

AD4

AE7

AH6
AH5

AH4

AG4
AF4

AF5

AE6
AE5

AJ6

AL1

AF3

AF2

AD7

AL2
AL3

AJ3

AJ2
AJ1

AH1

AH2
AH3

402

1K

1%
1/16W
MF-LF

R8855

1

2

81 95

81 95

81 95

81 95

81 95

81 95

81 95

81 95

81 95

81 95

1/16W
MF-LF

10K

5%

402

R8857

1

2

402

1/16W

10K

MF-LF

5%

R8856

1

2

75

75

75

75

75

75

75

75

75

75

75

75

44

44

75

75

75

75

1K

NO STUFF

MF-LF
402

1/16W

5%

R8860

1

2

1/16W
MF-LF
402

5%

1K

R8861

1

2

402

1K

1%
1/16W
MF-LF

R8851

1

2

SYNC_DATE=09/24/2008

88

123

051-7656

31

SYNC_MASTER=K20_MLB

NV G96 Video Interfaces

=PP1V8_GPU_IFPX

GPU_IFPCD_RSET

GPU_IFPEF_RSET

GPU_I2CA_SCL

=GPU_I2CS_SCL

GPU_I2CH_SDA

GPU_I2CA_SDA

LVDS_EG_B_CLK_N

LVDS_EG_B_DATA_N<0>

MIN_LINE_WIDTH=0.4 mm

PP1V1_GPU_IFPCD_IOVDD_F

VOLTAGE=1.1V

MIN_NECK_WIDTH=0.1 mm

GPU_DACC_VDD

DP_EG_ML_N<3>

LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>

DP_EG_ML_P<0>

DP_EG_ML_N<0>

LVDS_EG_B_DATA_P<0>

LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>

PP1V1_GPU_IFPCD_IOVDD_F

GPU_I2CE_SCL

GPU_I2CE_SDA

GPU_I2CD_SCL

GPU_I2CD_SDA

GPU_I2CB_SCL

GPU_I2CB_SDA

GPU_I2CH_SCL

GPU_I2CC_SDA

=GPU_I2CS_SDA

LVDS_EG_B_CLK_P

LVDS_EG_A_DATA_P<2>

LVDS_EG_A_DATA_P<3>

LVDS_EG_A_DATA_N<3>

LVDS_EG_A_DATA_N<0>

LVDS_EG_A_DATA_P<0>

LVDS_EG_A_CLK_N

GPU_IFPAB_RSET

GPU_IFPEF_RSET

GPU_IFPCD_RSET

PP1V8_GPU_IFPCD_PLLVDD_F

DP_EG_ML_P<2>

LVDS_EG_A_DATA_N<2>

LVDS_EG_A_CLK_P

GPU_IFPAB_RSET

DP_EG_ML_P<1>
DP_EG_ML_N<1>

DP_EG_ML_P<3>

DP_EG_ML_N<2>

LVDS_EG_B_DATA_N<3>

LVDS_EG_B_DATA_P<3>

LVDS_EG_B_DATA_N<2>

LVDS_EG_B_DATA_P<2>

GPU_DACA_VDD

GPU_DACB_VDD

PP1V1_GPU_IFPEF_IOVDD_F

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_IFPAB_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm

GPU_I2CC_SCL

PP1V8_GPU_IFPEF_PLLVDD_F

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V8_GPU_IFPAB_IOVDD_F

DP_EG_AUX_CH_N

DP_EG_AUX_CH_P

PP1V1_GPU_IFPEF_IOVDD_F

PP1V8_GPU_IFPEF_PLLVDD_F

PP1V8_GPU_IFPCD_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

=PP1V1_GPU_IFPCD_IOVDD

8

76

76

76

76

76

76

76

76

76

76

76

76

76

76

8

Preliminary

PVCC

THRM_PAD

FDE

PGOOD

AF_EN

VR_ON

IMON

VID4

VID3

VID2

VID1

VID0

LGATE

PGND

PHASE

UGATE

BOOT

VSS

VIN

ISP

VO

ISN

ICOMP

RTN

VSEN

VDIFF

FB

COMP

VW

OCSET

SOFT

VDD

RBIAS

OUT

IN

IN

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

(GFXIMVP6_AGND)

1

1
1

VID2

1 10

1

1
1

VID11VID0

0

1

-

-

Max Batt Balanced

-

Max perf

-

-

(PPVCORE_GPU_REG)

PLACE C8965,C8966,C8967 AND C8968 ON THE BACK SIDE OF GPU

Vout = 1.05V - 0.96V

(L8920 limit)

12A max output

Other VID states may not be valid

1.00425V

0.92700V

0.90125V

Voltage

GPU VCore Setpoints

X

X

X

VID3

Default Vcore Setpoints

GPU VCore Regulator

2

1

R8951

1/16W

1%

402

MF-LF

4.99K

2

1

R8950

402

1%
1/16W

374K

MF-LF

21

R8908

MF-LF

402

20

1/16W

5%

PLACEMENT_NOTE=Place R8920 at U8900

21

R8920

PLACEMENT_NOTE=Place R8908 at U8900

402

1/16W

5%

MF-LF

20

2

1

R8907

1/16W

5%

402

MF-LF

10K

2

1

R8910

MF-LF

1/16W

10K

5%

402

21

C8951

CERM

10%
50V

402

560PF

2

1

R8953

MF-LF

2.21K

402

1%
1/16W

2

1

C8952

50V

402-1

CERM

68PF

5%

2 1

C8950

402

180PF

CERM

50V

5%

2

1

C8920

10%
50V

402

0.001UF

CERM

4

15

8

29

12

14

27

26

25

24

23

7

16

18

33

2

9

1

22

19

31

20

3

21

13
11

28

10

32

6

5

17

30

U8900

CRITICAL

ISL6263C

QFN

21

XW8900

SM

2

1

C8953

50V
CERM
402

10%

680pF

2

1

R8909

4.99K

1/16W
MF-LF

402

1%

2

1

C8922

X7R

10%

402

0.001UF

50V

2

1

C8923

0.001UF

50V

402

CERM

10%

67

2

1

C8921

50V

402

CERM

10%

0.001UF

21

R8904

MF-LF

402

1%

10

1/16W

12

R8905

150K

1/16W
MF-LF

402

1%

2 1

C8904

0.033UF

10%

402

X5R

16V

2

1

C8901

10%

402

X5R

10V

1uF

21

R8911

5%

1/16W

402

MF-LF

1

2

1

C8902

6.3V

4.7UF

20%

X5R-CERM

402

2

1

C8903

10%

0.01uF

16V
CERM
402

2

1

C8972

16V

10%
X5R

0.1uF

402

C8971

21

68PF

402-1

5%

50V

CERM

1

2

R8902

9.76K

402

MF-LF

1/16W

1%

2

1

R8901

5.11K

1/16W

402

MF-LF

1%

7.15K

1/16W

402

MF-LF

1%

R8900

1 2

321

4

5

Q8951

CRITICAL

LFPAK-HF

RJK0328DPB

2

1

C8956

603

10%

0.22UF

16V
X7R

0.68UH-25A-5.5MOHM

PCMC063T-SM

CRITICAL

L8920

1 2

2

1

C8965

20%

603

6.3V
X5R

10UF

2

1

C8966

10UF

6.3V

603

X5R

20%

3 2

1

C8943

D2T-SM2

20%

POLY-TANT

2.0V

330UF

CRITICAL

2

1

R8930

MF-LF

1/16W

1K

402

5%

321

4

5

Q8950

RJK0305DPB

CRITICAL

LFPAK-HF

2

1

C8930

CRITICAL

POLY-TANT

20%
16V

33UF

CASED2E-SM

2

1

C8932

X5R

1UF

10%

603-1

25V

2

1

C8933

1UF

10%
X5R

25V

603-1

2

1

R8903

MF-LF

402

1/16W

1%

1K

2

1

C8906

330PF

5%

COG
402

50V

32

1

C8942

D2T-SM2

330UF

20%

2.0V

POLY-TANT

CRITICAL

2

1

C8968

10UF

20%
X5R

6.3V

603

2

1

C8967

X5R

20%

6.3V

10UF

603

2

1

C8931

CRITICAL

33UF

16V

POLY-TANT

CASED2E-SM

20%

84 67

43

21

R8940

0.001

1W

1%

MF

0612

2

1

C8934

X7R

10%

402

0.001UF

50V

2

1

C8969

X7R
402

10%

0.001UF

50V

2 1

R8986

1/16W
MF-LF

402

0

5%

2

1

R8980

5%
1/16W
MF-LF

0

402

2

1

R8982

MF-LF

GPUVID2_1

5%

402

1/16W

2.2K

2

1

R8988

402

MF-LF

0

5%
1/16W

2

1

R8984

5%

1/16W

402

MF-LF

2.2K

GPUVID1_1

2

1

R8987

1/16W

402

MF-LF

5%

2.2K

GPUVID0_1

2

1

R8983

GPUVID2_0

MF-LF

5%

1/16W

2.2K

402

2

1

R8985

MF-LF

5%

GPUVID1_0

2.2K

402

1/16W

21

R8990

402

5%

0

1/16W
MF-LF

75

75

21

R8994

5%
1/16W
MF-LF

0

402

75

31

123

89

SYNC_DATE=05/21/2008

SYNC_MASTER=RXU_K20

051-7656

GPU (G96) CORE SUPPLY

GPUVID_1P00V

GPUVID2_0,GPUVID1_1,GPUVID0_1

GPUVID_0P90V

GPUVID2_1,GPUVID1_1,GPUVID0_1

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_DFB

GFXIMVP6_VSUM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM

=PPVCORE_GPU_REG

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_PHASE_VSUM

=GPUVCORE_EN

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

GND_GFXIMVP6_AGND

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_DROOP

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

PP5V_S5_GFXIMVP6_VDD

GFXIMVP6_VID1

GFXIMVP6_LGATE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_IMON

GFXIMVP6_FDE

GPUVCORE_PGOOD

GFXIMVP6_AF_EN

GFXIMVP6_VID4

GFXIMVP6_VID2

GFXIMVP6_VID0

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_PHASE

GFXIMVP6_VSEN_N

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSEN_P

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF

GFXIMVP6_RBIAS

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GPU_VDD_SENSE

MIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.25V

MIN_NECK_WIDTH=0.20 mm

GFXIMVP6_VDIFF_RC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.3MM

PPVCORE_GPU_REG_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

=PP5V_S3_GPUVCORE

=PPVIN_GPU_GPUVCORE

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.3MM

GFXIMVP6_COMP_RC

GPU_GND_SENSE

MIN_LINE_WIDTH=0.25 mm
VOLTAGE=0V

MIN_NECK_WIDTH=0.20 mm

GFXIMVP6_VID3
GFXIMVP6_VID4

GPU_VCORE_VID0

GPU_VCORE_VID1

GPU_VCORE_VID2

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_SOFT

GFXIMVP6_VID3

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_COMP

MIN_NECK_WIDTH=0.2MM

=PP3V3_GPU_VCORELOGIC

GFXIMVP6_VW

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_FB

GFXIMVP6_VIN

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_BOOT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_UGATE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP5V_S5_GFXIMVP6_PVCC

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_OCSET

=PP3V3_GPU_VCORELOGIC

GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2

45

77

77

8

77

46

77

77

77

69

8

8

69

77

77

77

8

8

77

77

77

Preliminary

D

G S

IN

SYM_VER-1

SYM_VER-1

NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LCD (LVDS) INTERFACE

518S0651

Place close to the connector

Place close to the connector

Panel has 2K pull-ups

no-panel case (development).

100K pull-ups are for

50V

0.001UF

X7R

10%

402

C9010

1

2

10%

0.1UF

X5R

16V

402

C9001

1

2

CRITICAL

FERR-250-OHM

SM

L9000

1 2

CERM

10%
50V

402

0.0022uF

C9000

1 2

1/16W
MF-LF

5%

100K

402

R9001

1 2

R9000

100K

MF-LF

402

1/16W

5%

1

2

SSM3K15FV

SOD-VESM-HF

Q9001

3

1

2

MF-LF

1/16W

100K

402

5%

R9011

1

2

100K

1/16W

402

MF-LF

5%

R9010

1

2

84

CRITICAL

DLP11S

90-OHM-100MA

L9010

1 2

34

CRITICAL

DLP11S

90-OHM-100MA

L9011

1 2

34

CRITICAL

F-RT-SM

20474-040E-11

J9000

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

5

6

7

8

9

50V

0.001UF

10%

X7R
402

C9002

1

2

SM

FDC638P_G

CRITICAL

Q9000

125

6

3

4

051-7656

31

123

90

SYNC_MASTER=M98_MLB

SYNC_DATE=07/14/2008

LVDS Display Connector

LCD_PWR_EN

LVDS_CONN_A_CLK_F_P

LED_RETURN_4

LED_RETURN_5

LVDS_CONN_B_CLK_F_P

LVDS_CONN_A_CLK_F_N

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5 mm

PP3V3_SW_LCD

MIN_NECK_WIDTH=0.25 mm

LVDS_CONN_A_CLK_N

LVDS_CONN_B_CLK_N

LVDS_CONN_B_CLK_P

LVDS_CONN_A_CLK_P

PPVOUT_S0_LCDBKLT

LED_RETURN_6

LED_RETURN_3

LED_RETURN_2

LED_RETURN_1

LVDS_CONN_B_DATA_N<1>

LVDS_CONN_B_DATA_N<2>

LVDS_CONN_B_DATA_P<2>

BKL_SYNC

LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_A_DATA_P<2>

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_CLK_F_N

LCD_PWREN_L_RC

=PP3V3_S0_LCD

LVDS_DDC_DATA

LVDS_DDC_CLK

=PP3V3_S0_DDC_LCD

PP3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

LCD_PWREN_L

95

95

95

95

95

95

95

95

95

95

95

95

75

95

85

85

95

95

95

95

95

95

85

85

85

85

85

81

81

81

85

81

81

81

81

81

81

81

81

81

95

81

81

8

7

7

7

7

7

7

81

81

81

81

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

8

7

7

7

Preliminary

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN
IN

IN

IN

OUT

OUT
OUT

OUT

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

BI

IN
IN

BI

BI

IN
IN

IN
IN IN

IN

IN IN

DQ13

DM0
DM1

DM3

A1

A0

A2

A4

A3

DQ31

DQ30

DQ28
DQ29

DQ27

DQ26

DQ25

DQ22
DQ23

DQ21

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ7

DQ4

DQ6

DQ5

DQ3

DQ2

DQ0
DQ1

DQ8
DQ9

DQ20

DQ24

A5

A9

A8/AP

ZQ
MF
SEN

RESET

RDQS0

RDQS2

RDQS1

RDQS3

WDQS0

WDQS2
WDQS3

WDQS1

BA0
BA1
BA2

RFU

A7

A6

DM2

RAS*

CAS*

WE*

CK*
CS0*

CK

A10
A11
CKE

A12/CS1*

MFLOW

MFLOW

MFLOW

(1 OF 2)

DQ13

DM0
DM1

DM3

A1

A0

A2

A4

A3

DQ31

DQ30

DQ28
DQ29

DQ27

DQ26

DQ25

DQ22
DQ23

DQ21

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ7

DQ4

DQ6

DQ5

DQ3

DQ2

DQ0
DQ1

DQ8
DQ9

DQ20

DQ24

A5

A9

A8/AP

ZQ
MF
SEN

RESET

RDQS0

RDQS2

RDQS1

RDQS3

WDQS0

WDQS2
WDQS3

WDQS1

BA0
BA1
BA2

RFU

A7

A6

DM2

RAS*

CAS*

WE*

CK*
CS0*

CK

A10
A11
CKE

A12/CS1*

MFLOW

MFLOW

MFLOW

(1 OF 2)

VDD0
VDD1

VDD4

VDD3

VDD2

VSS6
VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0
VSSA1

VDDA0
VDDA1

VDD7

VDD6

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VSSQ0

VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

VREF0
VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0
VDD1

VDD4

VDD3

VDD2

VSS6
VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0
VSSA1

VDDA0
VDDA1

VDD7

VDD6

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VSSQ0

VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

VREF0
VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

NCNC

IN

IN

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

VRAM8

Page Notes

Connect to designated pin, then GNDConnect to designated pin, then GND

U8400.J1

U8400.J12

U8400.J1

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

U8400.J12

X5R
402

10%
16V

VRAM8

0.1uF

C9103

1

2

VRAM8

402

X5R

10%
16V

0.1uF

C9102

1

2

0.1uF

X5R
402

10%
16V

VRAM8

C9104

1

2

10%

X5R

0.1uF

16V

VRAM8

402

C9101

1

2

0.1uF

402

16V

10%

X5R

VRAM8

C9122

1

2

X5R

16V

10%

402

0.1uF

VRAM8

C9123

1

2

10%

VRAM8

0.1uF

16V

402

X5R

C9124

1

2

VRAM8

0.1uF

X5R
402

10%
16V

C9125

1

2

X5R
402

10%
16V

0.1uF

VRAM8

C9126

1

2

VRAM8

100

1/16W

5%

402

MF-LF

R9149

1

2

VRAM8

243

1%

MF-LF

402

1/16W

R9148

1

2

0.1uF

16V

10%

X5R
402

VRAM8

C9121

1

2

402

X5R

0.1uF

10%
16V

VRAM8

C9115

1

2

VRAM8

10%

0.1uF

X5R

16V

402

C9110

1

2

1K

5%

MF-LF

402

1/16W

VRAM8

R9140

1

2

71 72 95

71 72 95

71 72 95

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 79 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 79 95

71 72 79 95

71 72 79 95

71 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 79 95

71 72 95

71 72 95

71 72 95

71 72 95

71 72 79 95

71 72 79 95

402

5%

1K

1/16W
MF-LF

VRAM8

R9190

1

2

16V

402

X5R

0.1uF

10%

VRAM8

C9171

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9172

1

2

402

1/16W

1%

MF-LF

243

VRAM8

R9198

1

2

MF-LF

1/16W

5%

100

VRAM8

402

R9199

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9173

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9174

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9175

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9176

1

2

16V

10%

402

0.1uF

X5R

VRAM8

C9151

1

2

16V

10%

X5R

0.1uF

402

VRAM8

C9152

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9160

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9153

1

2

0.1uF

16V

10%

402

X5R

VRAM8

C9165

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9154

1

2

7

71 72

95
7

71 72

95
7

71 72

95
7

71 72

95

7

71 72 95

7

71 72

95
7

71 72

95
7

71 72

95
7

71 72

95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

7

71 72 95

71 72 95

71 72 95

7

71 72 95

7

71 72 95

71 72 95

71 72 95

10UF

603

X5R

6.3V

20%

VRAM8

C9100

1

2

X5R

10UF

603

20%

6.3V

VRAM8

C9120

1

2

10UF

603

X5R

20%

6.3V

VRAM8

C9150

1

2

603

X5R

20%

6.3V

VRAM8

10UF

C9170

1

2

72

72 72

72

71 72 79 95 71 72 79 95

32MX32-900MHZ-MFL

CRITICAL

OMIT

BGA

K4J10324QD-HC11

U9150

K4

H2

K2

L4

J3

K3

M4

K9
H11

K10

L9

K11

M9

G4

G9

H10

F4

J11

J10

H4

F9

E3

E10
N10

N3

B2
B3

C11

C10
E11

F10

F11
G10

M11

L10
N11

M10

C2

R11
R10

T11
T10

M2

L3
N2

M3

R2
R3

C3

T2

T3

E2

F3

F2
G3

B11

B10

A9

H3

D3

D10
P10

P3

V9

J2

V4

D2
D11

P11

P2

H9

A4

32MX32-900MHZ-MFL

K4J10324QD-HC11

BGA

OMIT

CRITICAL

U9100

K4

H2

K2

L4

J3

K3

M4

K9
H11

K10

L9

K11

M9

G4
G9

H10

F4

J11

J10

H4

F9

E3

E10
N10

N3

B2
B3

C11

C10
E11

F10

F11
G10

M11

L10
N11

M10

C2

R11
R10

T11
T10

M2

L3
N2

M3

R2
R3

C3

T2

T3

E2

F3

F2
G3

B11

B10

A9

H3

D3

D10
P10

P3

V9

J2

V4

D2
D11

P11

P2

H9

A4

K4J10324QD-HC11

BGA

OMIT

CRITICAL

32MX32-900MHZ-MFL

U9100

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1

N4

N9

N12

R1
R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4
E9

E12

H1

H12

A3
A10

G1

G12
L1

L12
V3

V10

J1
J12

B1

B4

L2

L11
P1

P4

P9
P12

T1
T4

T9

T12

B9
B12

D1
D4

D9

D12
G2

G11

CRITICAL

OMIT

K4J10324QD-HC11

BGA

32MX32-900MHZ-MFL

U9150

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1

N4

N9

N12

R1
R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4
E9

E12

H1

H12

A3
A10

G1

G12
L1

L12
V3

V10

J1
J12

B1

B4

L2

L11
P1

P4

P9
P12

T1
T4

T9

T12

B9
B12

D1
D4

D9

D12
G2

G11

71 72 95

71 72 95

71 72 95

71 72 95

GDDR3 Frame Buffer A (Top)

123

051-7656

31

91

SYNC_MASTER=M99_MLB

SYNC_DATE=04/04/2008

FB_A_DQ<55>

FB_A_DQM_L<6>

FB_A_DQ<2>

FB_A_DQ<7>

FB_A_DQ<6>

FB_A_DQ<4>

FB_A_DQ<5>

FB_A_DQ<8>

FB_A_DQ<9>

FB_A_DQ<10>

FB_A_DQ<12>

FB_A_DQ<14>

FB_A_DQ<16>

FB_A_DQ<18>

FB_A_DQ<23>

FB_A_DQ<19>

FB_A_DQ<17>
FB_A_DQ<24>

FB_A_DQ<29>
FB_A_DQ<31>

FB_A_DQ<30>

FB_A_DQ<28>

FB_A_DQ<27>
FB_A_DQ<25>

FB_A_DQ<26>
FB_A_DQ<13>

FB_A_DQ<3>
FB_A_DQ<1>

FB_A_DQ<0>

FB_A_DQ<11>

FB_A_DQM_L<4>

FB_A_DQM_L<7>

FB_A_DQM_L<5>

FB_A0_VREF

FB_A2_VREF

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FB_VDD

=PP1V8_GPU_FB_VDDQ

FB_A_DQ<22>

FB_A_DQ<21>

FB_A_DQM_L<3>

FB_A2_SEN

FB_A_DQ<15>

FB_A3_MF

FB_A3_SEN

FB_A_DQ<36>

FB_A_DQ<37>

FB_A_DQ<32>
FB_A_DQ<38>

FB_A_DQ<39>

FB_A_DQ<34>
FB_A_DQ<33>

FB_A_DQ<53>
FB_A_DQ<52>

FB_A_DQ<49>

FB_A_DQ<51>
FB_A_DQ<50>

FB_A_DQ<48>

FB_A_DQ<54>

FB_A_DQ<35>

FB_A_DQ<62>

FB_A_DQ<58>

FB_A_DQ<63>

FB_A_DQ<57>

FB_A_DQ<61>

FB_A_DQ<56>

FB_A_DQ<60>

FB_A_DQ<59>

FB_A_DQ<41>

FB_A_DQ<40>

FB_A_DQ<47>

FB_A_DQ<46>
FB_A_DQ<45>

FB_A_DQ<43>

FB_A_DQ<44>

FB_A_DQ<42>

FB_A3_ZQ

FB_A_DQM_L<1>
FB_A_DQM_L<0>

FB_A_DQ<20>

FB_A_DQM_L<2>

FB_A2_ZQ

FB_A2_MF

FB_A_MA<1>

FB_A_MA<0>

FB_A_UMA<3>

FB_A_UMA<2>

FB_A_UMA<4>

FB_A_UMA<5>
FB_A_MA<6>

FB_A_MA<8>

FB_A_MA<7>

FB_A_MA<9>

FB_A_MA<10>
FB_A_MA<11>

FB_A_CKE

FB_A_MA<12>

FB_A_CS1_L

FB_A_CAS_L

FB_A_WE_L

FB_A_RAS_L

FB_A_RDQS<7>

FB_A_RDQS<5>

FB_A_DRAM_RST

FB_A_RDQS<4>
FB_A_RDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<7>
FB_A_WDQS<4>

FB_A_BA<0>

FB_A_WDQS<6>

FB_A_BA<1>
FB_A_BA<2>

FB_A_MA<0>

FB_A_MA<1>

FB_A_LMA<3>

FB_A_LMA<2>

FB_A_MA<6>

FB_A_LMA<4>

FB_A_LMA<5>

FB_A_MA<8>

FB_A_MA<7>

FB_A_MA<11>

FB_A_MA<9>

FB_A_MA<10>

FB_A_CKE

FB_A_MA<12>

FB_A_CLK_N<0>

FB_A_CLK_P<0>

FB_A_CAS_L

FB_A_CS1_L

FB_A_WE_L

FB_A_RAS_L

FB_A_DRAM_RST

FB_A_RDQS<2>

FB_A_RDQS<3>

FB_A_RDQS<1>
FB_A_RDQS<0>

FB_A_WDQS<1>

FB_A_WDQS<2>

FB_A_WDQS<3>

FB_A_BA<0>

FB_A_WDQS<0>

FB_A_BA<1>
FB_A_BA<2>

FB_A_CLK_N<1>

FB_A_CLK_P<1>

=PP1V8_GPU_FB_VDD

FB_A1_VREF

FB_A3_VREF

80 80 79

80

79

80

73

79

73

79

72

73

72

73

9

72

9

72

8

8

8

8

Preliminary

IN

IN

IN

IN

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

IN

IN

IN

IN
IN

IN

IN

OUT

OUT
OUT

OUT

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI
BI
BI
BI
BI

BI

BI
BI
BI
BI

BI

IN
IN

BI

BI

IN
IN

IN
IN IN

IN

IN IN

DQ13

DM0
DM1

DM3

A1

A0

A2

A4

A3

DQ31

DQ30

DQ28
DQ29

DQ27

DQ26

DQ25

DQ22
DQ23

DQ21

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ7

DQ4

DQ6

DQ5

DQ3

DQ2

DQ0
DQ1

DQ8
DQ9

DQ20

DQ24

A5

A9

A8/AP

ZQ
MF
SEN

RESET

RDQS0

RDQS2

RDQS1

RDQS3

WDQS0

WDQS2
WDQS3

WDQS1

BA0
BA1
BA2

RFU

A7

A6

DM2

RAS*

CAS*

WE*

CK*
CS0*

CK

A10
A11
CKE

A12/CS1*

MFLOW

MFLOW

MFLOW

(1 OF 2)

DQ13

DM0
DM1

DM3

A1

A0

A2

A4

A3

DQ31

DQ30

DQ28
DQ29

DQ27

DQ26

DQ25

DQ22
DQ23

DQ21

DQ19

DQ18

DQ17

DQ16

DQ15

DQ14

DQ12

DQ11

DQ10

DQ7

DQ4

DQ6

DQ5

DQ3

DQ2

DQ0
DQ1

DQ8
DQ9

DQ20

DQ24

A5

A9

A8/AP

ZQ
MF
SEN

RESET

RDQS0

RDQS2

RDQS1

RDQS3

WDQS0

WDQS2
WDQS3

WDQS1

BA0
BA1
BA2

RFU

A7

A6

DM2

RAS*

CAS*

WE*

CK*
CS0*

CK

A10
A11
CKE

A12/CS1*

MFLOW

MFLOW

MFLOW

(1 OF 2)

VDD0
VDD1

VDD4

VDD3

VDD2

VSS6
VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0
VSSA1

VDDA0
VDDA1

VDD7

VDD6

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VSSQ0

VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

VREF0
VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

VDD0
VDD1

VDD4

VDD3

VDD2

VSS6
VSS7

VSS3

VSS5

VSS2

VSS1

VSS0

VSS4

VSSA0
VSSA1

VDDA0
VDDA1

VDD7

VDD6

VDDQ0
VDDQ1
VDDQ2
VDDQ3
VDDQ4
VDDQ5
VDDQ6
VDDQ7
VDDQ8
VDDQ9
VDDQ10
VDDQ11
VDDQ12
VDDQ13
VDDQ14
VDDQ15
VDDQ16
VDDQ17
VDDQ18
VDDQ19
VDDQ20
VDDQ21

VSSQ0

VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

VREF0
VREF1

VSSQ2

VSSQ1

VDD5

(2 OF 2)

NC NC

IN

IN IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Connect to designated pin, then GND

U8500.J12

U8500.J1

U8500.J12

U8500.J1

Connect to designated pin, then GND

- =PP1V8_S0_FB_VDDQ

- =PP1V8_S0_FB_VDD

Power aliases required by this page:

Page Notes

VRAM8

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

16V

10%

X5R
402

0.1uF

VRAM8

C9203

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9202

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9204

1

2

402

16V

10%

X5R

0.1uF

VRAM8

C9201

1

2

402

10%

VRAM8

0.1uF

X5R

16V

C9222

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9223

1

2

VRAM8

16V
X5R

10%

0.1uF

402

C9224

1

2

VRAM8

16V

402

X5R

0.1uF

10%

C9225

1

2

VRAM8

10%

X5R

0.1uF

16V

402

C9226

1

2

VRAM8

100

MF-LF
402

5%
1/16W

R9249

1

2

VRAM8

243

MF-LF

402

1%

1/16W

R9248

1

2

VRAM8

10%

402

16V
X5R

0.1uF

C9221

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9215

1

2

X5R

VRAM8

16V

10%

402

0.1uF

C9210

1

2

71 73 95

71 73 95

71 73 95

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

71 73 80 95

7

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

7

71 73 80 95

71 73 80 95

71 80 95

71 73 80 95

7

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 80 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 80 95

7

71 73 80 95

71 73 80 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 80 95

71 73 80 95

7

71 73 80 95

71 80 95

71 73 80 95

71 73 80 95

7

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 80 95

71 73 95

71 73 95

71 73 95

71 73 95

71 73 80 95

71 73 80 95

VRAM8

X5R
402

10%
16V

0.1uF

C9271

1

2

VRAM8

X5R
402

10%
16V

0.1uF

C9272

1

2

VRAM8

1/16W

402

MF-LF

243

1%

R9298

1

2

VRAM8

1/16W

402

MF-LF

5%

100

R9299

1

2

VRAM8

10%

402

X5R

16V

0.1uF

C9273

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9274

1

2

402

VRAM8

X5R

10%
16V

0.1uF

C9275

1

2

VRAM8

X5R
402

10%
16V

0.1uF

C9276

1

2

VRAM8

0.1uF

X5R
402

10%
16V

C9251

1

2

VRAM8

0.1uF

X5R
402

10%
16V

C9252

1

2

VRAM8

16V

10%

X5R

0.1uF

402

C9260

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9253

1

2

VRAM8

10%

402

X5R

0.1uF

16V

C9265

1

2

VRAM8

0.1uF

X5R
402

10%
16V

C9254

1

2

7

71 73

95
7

71 73

95
7

71 73

95
7

71 73

95

7

71 73 95

7

71 73

95
7

71 73

95
7

71 73

95
7

71 73

95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

7

71 73 95

71 73 95

71 73 95

7

71 73 95

7

71 73 95

71 73 95

71 73 95

VRAM8

10UF

603

X5R

6.3V

20%

C9200

1

2

10UF

VRAM8

603

X5R

6.3V

20%

C9220

1

2

VRAM8

10UF

603

X5R

6.3V

20%

C9250

1

2

10UF

VRAM8

603

X5R

6.3V

20%

C9270

1

2

VRAM8

5%

MF-LF

402

1/16W

1K

R9240

1

2

MF-LF

402

1/16W

1K

5%

VRAM8

R9290

1

2

73

73 73

73

71 73 80 95 71 73 80 95

32MX32-900MHZ-MFL

K4J10324QD-HC11

CRITICAL

OMIT

BGA

U9200

K4

H2

K2

L4

J3

K3

M4

K9
H11

K10

L9

K11

M9

G4
G9

H10

F4

J11

J10

H4

F9

E3

E10
N10

N3

B2
B3

C11

C10
E11

F10

F11
G10

M11

L10
N11

M10

C2

R11
R10

T11
T10

M2

L3
N2

M3

R2
R3

C3

T2

T3

E2

F3

F2
G3

B11

B10

A9

H3

D3

D10
P10

P3

V9

J2

V4

D2
D11

P11

P2

H9

A4

CRITICAL

OMIT

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFL

U9250

K4

H2

K2

L4

J3

K3

M4

K9
H11

K10

L9

K11

M9

G4

G9

H10

F4

J11

J10

H4

F9

E3

E10
N10

N3

B2
B3

C11

C10
E11

F10

F11
G10

M11

L10
N11

M10

C2

R11
R10

T11
T10

M2

L3
N2

M3

R2
R3

C3

T2

T3

E2

F3

F2
G3

B11

B10

A9

H3

D3

D10
P10

P3

V9

J2

V4

D2
D11

P11

P2

H9

A4

CRITICAL

OMIT

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFL

U9200

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1

N4

N9

N12

R1
R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4
E9

E12

H1

H12

A3
A10

G1

G12
L1

L12
V3

V10

J1
J12

B1

B4

L2

L11
P1

P4

P9
P12

T1
T4

T9

T12

B9
B12

D1
D4

D9

D12
G2

G11

CRITICAL

OMIT

BGA

K4J10324QD-HC11

32MX32-900MHZ-MFL

U9250

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4
J9
N1

N4

N9

N12

R1
R4

R9

R12

C1

V1

V12

C4

C9

C12

E1

E4
E9

E12

H1

H12

A3
A10

G1

G12
L1

L12
V3

V10

J1
J12

B1

B4

L2

L11
P1

P4

P9
P12

T1
T4

T9

T12

B9
B12

D1
D4

D9

D12
G2

G11

71 73 95

71 73 95 71 73 95

71 73 95

92

123

31

051-7656

SYNC_MASTER=M88_MLB

SYNC_DATE=11/01/2007

GDDR3 Frame Buffer B (Top)

FB_B_DQ<24>

FB_B_DQ<28>

FB_B2_MF

FB_B2_ZQ

FB_B_DQ<16>

FB_B3_MF

FB_B3_ZQ

FB_B_DQ<59>

FB_B_DQ<62>

FB_B_DQ<60>

FB_B_DQ<35>

FB_B_DQ<56>

FB_B_DQ<57>

FB_B_DQ<63>

FB_B_DQ<58>

FB_B_DQ<33>
FB_B_DQ<32>

FB_B_DQ<38>

FB_B_DQ<51>

FB_B_DQ<48>

FB_B_DQ<50>

FB_B_DQ<49>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<40>

FB_B_DQ<44>

FB_B_DQ<46>

FB_B_DQ<4>

FB_B_DQ<0>

FB_B_DQ<12>

FB_B_DQ<8>

FB_B_DQ<13>

FB_B_DQ<26>

FB_B_DQ<27>

FB_B_DQ<31>

FB_B_DQ<25>
FB_B_DQ<29>

FB_B_DQ<30>

FB_B_DQ<21>

=PP1V8_GPU_FB_VDD

=PP1V8_GPU_FB_VDDQ

FB_B3_VREF

FB_B1_VREF

FB_B2_VREF

FB_B0_VREF

FB_B_DQ<55>

FB_B_DQM_L<5>

FB_B_DQM_L<6>

FB_B_DQM_L<4>

FB_B_DQ<36>

FB_B_DQ<39>

FB_B_DQ<37>

FB_B_DQ<61>

FB_B_DQ<52>

FB_B_DQ<54>

FB_B_DQ<53>

FB_B_DQ<43>

FB_B_DQ<45>

FB_B_DQ<47>

FB_B_DQ<34>

FB_B_DQM_L<7>

FB_B_DQ<15>

FB_B_DQM_L<0>

FB_B_DQM_L<2>

FB_B_DQ<17>

FB_B_DQ<19>

FB_B_DQ<9>

FB_B_DQ<14>

FB_B_DQ<10>

FB_B_DQ<11>

FB_B_DQ<7>

FB_B_DQ<6>

FB_B_DQ<5>

FB_B_DQ<20>

FB_B_DQ<18>

FB_B_DQ<23>

FB_B3_SEN

FB_B_DQ<22>

FB_B_DQ<3>

FB_B_DQM_L<3>

FB_B_DQM_L<1>

FB_B2_SEN

=PP1V8_GPU_FB_VDDQ

=PP1V8_GPU_FB_VDD

FB_B_MA<1>

FB_B_MA<0>

FB_B_UMA<3>

FB_B_UMA<2>

FB_B_UMA<4>

FB_B_UMA<5>
FB_B_MA<6>

FB_B_MA<8>

FB_B_MA<7>

FB_B_MA<9>

FB_B_MA<10>
FB_B_MA<11>

FB_B_CKE

FB_B_MA<12>

FB_B_CS1_L

FB_B_CAS_L

FB_B_WE_L

FB_B_RAS_L

FB_B_RDQS<6>

FB_B_RDQS<5>

FB_B_DRAM_RST

FB_B_RDQS<7>
FB_B_RDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>
FB_B_WDQS<7>

FB_B_BA<0>

FB_B_WDQS<4>

FB_B_BA<1>
FB_B_BA<2>

FB_B_MA<0>

FB_B_MA<1>

FB_B_LMA<3>

FB_B_LMA<4>

FB_B_LMA<5>

FB_B_MA<7>

FB_B_MA<11>

FB_B_MA<9>

FB_B_MA<12>

FB_B_CAS_L

FB_B_CS1_L

FB_B_WE_L

FB_B_RAS_L

FB_B_DRAM_RST

FB_B_RDQS<0>

FB_B_RDQS<1>

FB_B_RDQS<3>
FB_B_RDQS<2>

FB_B_WDQS<3>

FB_B_WDQS<0>

FB_B_WDQS<1>

FB_B_BA<0>

FB_B_WDQS<2>

FB_B_BA<1>
FB_B_BA<2>

FB_B_CKE

FB_B_MA<10>

FB_B_MA<8>

FB_B_LMA<2>

FB_B_CLK_P<0>
FB_B_CLK_N<0>

FB_B_DQ<1>

FB_B_DQ<2>

FB_B_MA<6>

FB_B_CLK_P<1>
FB_B_CLK_N<1>

80 80

80

79 79

80 79

73 73

79 73

72 72

73 72

9 9

72

8

8 8

8

Preliminary

IN
IN

IN

IN

IN

IN

IN

IN

BI

IN

OUT

OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

BI

BI

IN

BI

BI

IN

IN

IN

IN

IN

IN

IN
IN

BI
BI

IN

OUT

BI

IN

IN

XSD*

HPD_1

DIN1_0-

DIN1_1+

DIN1_2-

DAUX1+

DIN1_3+

DDC_DAT2

DAUX2-

DDC_CLK2

HPD_2

GPU_SEL

TST0

DIN1_2+

DIN1_1-

DOUT_0-

DOUT_1+
DDC_CLK1
DDC_DAT1

DOUT_2+

DOUT_2-

DOUT_3+

DOUT_3-

DIN2_1+

DDC_AUX_SEL

DIN2_1-

AUX+
AUX-

HPDIN

DIN2_2+
DIN2_2-

DIN2_3+
DIN2_3-

DAUX2+

DIN2_0-

DIN2_0+

DIN1_0+

DAUX1-

DOUT_1-

DOUT_0+
DIN1_3-

VDD

GND

OUT

OUT

VCC

C1

C2

C3

C4

A1
B1

A2
B2

A3
B3

A4
B4

GND

THRM

IN

IN

OUT

IN

IN

BI

BI
BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LVDS DDC MUX

LVDS Transmitter Termination

All emulated LVDS outputs require this termination

LO=PORT1
HI=PORT2

DisplayPort Mux

HI=DDC

LO=AUX_CH

(All 24 resistors)

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

90

9

75

9

75

9

82 95

82 95

82 95

82 95

95 82

82 95

82 95

82 95

82 95

82 95

75 82 84

0.1uF

X5R 40210% 16V

C9330

1 2

0.1uF

X5R 40210% 16V

C9331

1 2

18 90

18 90

MUXGFX

10V

20%

402

CERM

0.1UF

C9320

1

2

76 95

76 95

76 95

76 95

76 95

76 95

0.1uF

X5R 40210% 16V

C9335

1 2

X5R10% 402

0.1uF

16V

C9336

1 2

76 95

76 95

76 95

76 95

75

75

75

82

84

MUXGFX

10V

20%

402

CERM

0.1UF

C9321

1

2

A1

SIGNAL_MODEL=DPMUX

D2

CRITICAL

BGA

CBTL06141EE

U9320

H1

H2

J9

H9

J6

H6

C2

H8

H5

J8

J5

A4

B4

A5

B5

A6

B6

A9

A8

B9

B8

D9

D8

E9

E8

F9

F8

B1

B2

D1

E1

E2

F1

F2

B3C8G8H4H7

J2

H3

J1

G2

A2

J4

B7

MUXGFX

84

18

QFN1

SN74LV4066A

U9370

1

4

8

11

2

3

9

10

13

5

6

12

7

15

14

84

84

7

78

75

18

75

18

7

78

20%

0.1UF

402

CERM

10V

C9370

1

2

20K

402

MF-LF

1/16W

5%

R9373

1

2

5%

1/16W

402

MF-LF

20K

R9372

1

2

84

1%

10K

MF-LF

402

1/16W

DPMUX_EN_S0&DPMUX_EN_PLD

R9302

1

2

5%

0

MF-LF

402

1/16W

DPMUX_EN_PLD

R9303

1 2

DPMUX_EN_HPD

1%

10K

1/16W

402

MF-LF

R9301

1

2

84 95

84 95

84 95

84 95

7

84 95

7

84 95

84 95

7

84 95

84 95

84 95

84 95

84 95

7

84 95

PLACEMENT_NOTE=Place at U9600

1%

MF-LF

402

1 2

1/16W

270

R9357

OMIT

PLACEMENT_NOTE=Place at U9600

1%

R9356

GMUX_2V5

133

402

1/16W
MF-LF

SIGNAL_MODEL=EMPTY

1

2

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

R9352

1 2

OMIT

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

1 2

OMIT

R9355

PLACEMENT_NOTE=Place at U9600

133

402

1/16W
MF-LF

1%

SIGNAL_MODEL=EMPTY

R9351

1

2

GMUX_2V5

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

R9350

1 2

OMIT

PLACEMENT_NOTE=Place at U9600

R9347

270

1%

402

MF-LF

1/16W

1 2

OMIT

PLACEMENT_NOTE=Place at U9600

1%

GMUX_2V5
133

402

1/16W
MF-LF

SIGNAL_MODEL=EMPTY

R9346

1

2

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

R9342

1 2

OMIT

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

R9345

1 2

OMIT

PLACEMENT_NOTE=Place at U9600

133

402

1/16W
MF-LF

1%

R9341

1

2

SIGNAL_MODEL=EMPTY

GMUX_2V5

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

R9340

1 2

OMIT

PLACEMENT_NOTE=Place at U9600

270

1%

402

MF-LF

1/16W

1 2

R9337

OMIT

PLACEMENT_NOTE=Place at U9600

133

402

1/16W
MF-LF

1%

SIGNAL_MODEL=EMPTY

R9336

1

2

GMUX_2V5

PLACEMENT_NOTE=Place at U9600

270

1%
1/16W
MF-LF

402

2

OMIT

1

R9332

PLACEMENT_NOTE=Place at U9600

270

1%

1/16W

1 2

R9335

MF-LF

402

OMIT

PLACEMENT_NOTE=Place at U9600

133

402

1/16W
MF-LF

1%

SIGNAL_MODEL=EMPTY

R9331

1

2

GMUX_2V5

PLACEMENT_NOTE=Place at U9600

270

1%
1/16W
MF-LF

402

21

R9330

OMIT

PLACEMENT_NOTE=Place at U9600

270

1%
1/16W
MF-LF

402

R9327

1 2

OMIT

PLACEMENT_NOTE=Place at U9600

133

1/16W
MF-LF
402

1%

SIGNAL_MODEL=EMPTY

R9326

1

2

GMUX_2V5

7

84 95

84 95

84 95

OMIT

PLACEMENT_NOTE=Place at U9600

MF-LF

402

2

270

1/16W

1%

R9322

1

PLACEMENT_NOTE=Place at U9600

270

402

1/16W
MF-LF

1%

R9325

1 2

OMIT

PLACEMENT_NOTE=Place at U9600

133

1/16W
MF-LF

1%

402

SIGNAL_MODEL=EMPTY

R9321

1

2

GMUX_2V5

PLACEMENT_NOTE=Place at U9600

402

MF-LF

1/16W

R9320

21

1%

270

OMIT

DPMUX_EN_HPD

402

CERM-X5R

6.3V

10%

1UF

C9301

1

2

78 95

78 95

7

78 95

7

78 95

7

78 95

7

78 95

7

78 95

7

78 95

78 95

78 95

7

78 95

7

78 95

7

78 95

7

78 95

7

78 95

7

78 95

5%

100K

1/16W

402

MF-LF

R9305

1

2

5%

100K

1/16W

402

MF-LF

R9304

1

2

MF-LF

402

1/16W

1K

5%

R9306

1

2

PLACEMENT_NOTE=Place at U9320

1K

5%

MF-LF

402

1/16W

MUXGFX

R9307

1 2

R9371

5%

MF-LF

1/16W

402

20K

1

2

5%

20K

MF-LF

402

1/16W

R9370

1

2

16

114S0517

R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357

GMUX_2V5

RES,MTL FILM,270 OHM,1%,1/16W,0402,SMD,L

16

R9320,R9322,R9325,R9327,R9330,R9332,R9335,R9337,R9340,R9342,R9345,R9347,R9350,R9352,R9355,R9357

GMUX_1V8114S0174

RES,MTL FILM,1/16W,357 OHM,1,0402,SMD,LF

Muxed Graphics Support

SYNC_DATE=05/01/2008

051-7656

31

123

93

SYNC_MASTER=M98_MLB

LVDS_B_DATA_N<2>

LVDS_A_DATA_P<1>

LVDS_B_CLK_P

LVDS_CONN_A_CLK_P

DP_EG_HPD

LVDS_B_DATA_P<2>

DP_EG_AUX_CH_P
DP_EG_AUX_CH_N

DP_MUX_SEL_EG

=PP3V3_S0_DPMUX

DP_MUX_EN

DP_MUX_XSD_L

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_A_DATA_P<1>

DP_IG_ML_N<3>

DP_IG_ML_P<3>

DP_EG_ML_P<1>

DP_IG_CA_DET

DP_HOTPLUG_DET

MAKE_BASE=TRUE

LVDS_EG_DDC_DATA

LVDS_DDC_DATA

LVDS_DDC_SEL_IG

LVDS_A_DATA_N<1>

LVDS_B_DATA_N<1>

LVDS_A_CLK_N

DP_EG_AUX_CH_C_P

DP_IG_AUX_CH_C_P

DP_ML_N<0>

DP_ML_P<1>
DP_ML_N<1>

DP_EG_ML_P<0>
DP_EG_ML_N<0>

=PP3V3_S0_LVDSDDCMUX

LVDS_EG_DDC_CLK

LVDS_IG_DDC_CLK

LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_A_DATA_P<2>

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<2>

LVDS_DDC_SEL_EG

LVDS_IG_DDC_DATA

LVDS_DDC_CLK

LVDS_A_CLK_P

=PP3V3_GPU_LVDS_DDC

DP_ML_P<0>

DP_HPD_R

DP_IG_ML_P<0>

DP_IG_ML_P<1>

DP_IG_ML_P<2>

=PP3V3_S0_DPMUX

DP_HPD

DP_EG_ML_N<2>

DP_EG_ML_N<1>

DP_IG_DDC_CLK

DP_IG_AUX_CH_C_N

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_B_CLK_P

LVDS_CONN_B_CLK_N

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_N<1>

LVDS_CONN_B_DATA_P<2>

LVDS_B_DATA_P<1>

LVDS_B_DATA_N<0>

LVDS_B_DATA_P<0>

LVDS_B_CLK_N

LVDS_A_DATA_N<2>

LVDS_A_DATA_P<2>

LVDS_A_DATA_N<0>

LVDS_A_DATA_P<0>

LVDS_CONN_A_CLK_N

DP_ML_P<3>

DP_ML_N<2>

DP_ML_N<3>

DP_AUX_CH_C_P
DP_AUX_CH_C_N

MAKE_BASE=TRUE

DP_CA_DET

DP_EG_ML_P<3>

DP_IG_ML_N<2>

DP_IG_ML_N<1>

DP_IG_ML_N<0>

DP_ML_P<2>

DP_EG_DDC_DATA

DP_EG_DDC_CLK

DP_EG_AUX_CH_C_N

DP_EG_ML_N<3>

DP_EG_ML_P<2>

DP_IG_HPD

DP_IG_DDC_DATA

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

81

81

8

95

96

8

8

8

96

95

Preliminary

BI

IN

IN

IO
NC NC

IO

GND

OUT

IO
NC NC

IO

GND

IO
NC NC

IO

GND

IO
NC NC

IO

GND

IN

IN

IN

IN

IN

IN

G

D

S

G

D

S

SYM_VER-2

SYM_VER-2

SYM_VER-2

SYM_VER-2

OUT

G

D

S

G

D

S

BI

IN

OC*

OUT

EN

GND

IN

GND

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

GND

DP_PWR

ML_LANE2P

AUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P

ML_LANE3N

ML_LANE2N

CONFIG1
CONFIG2

TOP ROW

TH PINS

BOT ROW

SM PINS

SHIELD PINS

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Port Power Switch

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

pull-up to DP_PWR.

(CA) has 100k

Cable Adapter

DP to DVI/HDMI

to 100K (DPv1.1a).

greater than or equal

down HPD input with

DP Source must pull

95 81

95 81

95 81

2

1

R9421

MF-LF

100K

1/16W

5%

402

10

9

12

3

D9411

RCLAMP0524P

CRITICAL

SLP2510P8

DP_ESD

21

C9415

40216V

0.1uF

X5R10%

21

C9414

40216V

0.1uF

X5R10%

84 81 75

21

C9411

0.1uF

X5R 40216V10%

21

C9410

0.1uF

X5R 40210% 16V

2

1

R9420

100K

402

1/16W

5%

MF-LF

76

45

3

D9410

RCLAMP0524P

CRITICAL

DP_ESD

SLP2510P8

52

6

4

3

1

D9400

DP_ESD

SC70-6-1

CRITICAL

RCLAMP0504F

76

45

3

D9411

RCLAMP0524P

SLP2510P8

DP_ESD

CRITICAL

2

1

R9425

5%

402

1/16W

1M

MF-LF

10

9

12

3

D9410

DP_ESD

CRITICAL

SLP2510P8

RCLAMP0524P

21

C9417

X5R 40210% 16V

0.1uF

21

C9416

0.1uF

X5R 40210% 16V

21

C9413

0.1uF

X5R 40210% 16V

21

C9412

X5R 40210% 16V

0.1uF

95 81

95 81

95 81

95 81

2

1

C9400

0.01UF

CERM
603

50V

20%

21

L9400

0603

FERR-120-OHM-3A

95 81

95 81

4

5

3

Q9440

SOT-363

2N7002DW-X-G

1

2

6

Q9440

SOT-363

2N7002DW-X-G

2

1

R9443

100K

MF-LF

402

1/16W

5%

2

1

R9442

MF-LF

100K

402

1/16W

5%

4

3 2

1

FL9403

12-OHM-100MA

TCM1210-4SM

CRITICAL

4

32

1

FL9402

TCM1210-4SM

12-OHM-100MA

CRITICAL

4

32

1

FL9401

12-OHM-100MA

TCM1210-4SM

CRITICAL

4

32

1

FL9400

TCM1210-4SM

12-OHM-100MA

CRITICAL

21

R9403

0

1/16W

5%

402

MF-LF

NO STUFF

21

R9413

NO STUFF

1/16W

5%

402

MF-LF

0

21

R9402

0

1/16W

5%

402

MF-LF

NO STUFF

21

R9432

0

1/16W

5%

402

MF-LF

NO STUFF

21

R9401

MF-LF

5%

0

402

1/16W

NO STUFF

21

R9431

NO STUFF

5%

0

MF-LF

402

1/16W

21

R9400

0

1/16W

5%

402

MF-LF

NO STUFF

21

R9430

NO STUFF

MF-LF

402

5%

1/16W

0

81

1

2

6

Q9441

2N7002DW-X-G

SOT-363

4

5

3

Q9441

2N7002DW-X-G

SOT-363

2

1

R9422

5%

MF-LF

402

1/16W

1M

2

1

R9445

10K

MF-LF

402

1/16W

5%

2

1

R9444

10K

MF-LF

5%

402

1/16W

2

1

R9423

5%

MF-LF

1/16W

402

100K

2

1

C9480

6.3V

20%
X5R

10UF

603

2

1

C9481

0.1UF

402

CERM

10V

20%

95 81

2

1

603

6.3V
X5R-CERM

20%

CRITICAL

C9486

22UF

2

1

C9485

402

10V

20%

CERM

0.1UF

1

3

5

2

4

U9480

TPS2051B

SOT23

CRITICAL

84 67 41 36 33 21

7

DSPLYPRT-M97

J9400

CRITICAL

F-RT-THSM

6

4

17

12

10

18

2

19

16 15

20

21

14

8

11
13

9

3
5
7

1

22

OMIT

1

CRITICAL514-0637

CONN,RCP,MDP,HB,20P,P=0.6

J9400

94

123

31

051-7656

SYNC_DATE=09/24/2008

SYNC_MASTER=K20_MLB

DisplayPort Connector

DP_ML_CONN_N<0>

DP_ML_CONN_P<0>

DP_ML_CONN_P<1>

DP_ML_CONN_N<1>

DP_ML_CONN_P<2>

DP_AUX_CH_C_P

DP_AUX_CH_C_N

DP_ML_CONN_P<3>

DP_ML_CONN_N<3>

DP_ML_CONN_N<2>

DP_CA_DET_Q

HDMI_CEC

TP_DPPWR_OC_L

DP_HPD

DP_HPD_L_Q

DP_ML_C_P<1>

DP_ML_C_P<0>

DP_ML_C_N<0>

DP_ML_C_N<1>

DP_ML_C_P<2>

DP_ML_C_N<2>

DP_ML_P<3>

DP_ML_N<2>

DP_ML_P<2>

DP_ML_N<1>

DP_ML_P<1>

DP_ML_N<0>

DP_ML_P<0>

=PP3V3_S0_DPCONN

DP_CA_DET_L_Q

DP_CA_DET

DP_ML_N<3>

DP_ML_C_P<3>

=PP3V3_S0_DPCONN

=PP3V3_S5_DP_PORT_PWR

PM_SLP_S3_L

DP_ML_C_N<3>

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.38 MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

DP_HPD_Q

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.38 MM

PP3V3_S0_DPILIM

82

82

95

95

95

95

95

95

95

95

95

95

95

95

95

95

8

95

8

8

95

Preliminary

IN
OUT

IN

OUT

BOOT1
UGATE1
PHASE1
LGATE1
OUT1

VCC

REFIN2

ILIM2

OUT2

SKIP*

POK2

EN2

UGATE2
PHASE2

BOOT2

LGATE2

PGND

GND

SECFB

PVCC

EN1

ILIM1

FB1

BYP

LDOREFIN

LDO

VIN

VREF3

EN_LDO

TON

REF

POK1

THRM_PAD

D

GS

NC

S

D

G

S

D

G

S

D

G

S

D

G

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

<Rb>

8A MAX OUTPUT

3.5A MAX OUTPUT

Vout = 1.103V

Vout = 1.8V

<Ra>

(SGND)

(=PP1V8FB_S0_REG)

<Ra>

f = 400 kHz

(Q9510 limit?)

(Rb should be between 10K and 100K)

<Rb>

(Q9560 limit?)

Vout = 0.7V * (1 + Ra / Rb)

F = 500 KHZ

Vout = 2(Req/(Ra+Req))

1

1.553V

0

1.8V

GPIO7

FBVDDQ

from PVCC to VCC)

(Internal 10-ohm path

6.3V
X5R

10UF

20%

603

C9565

1

2

603-1

X5R

1UF

10%
25V

C9595

1

2

0.1UF

603-1

10%
50V
X7R

C9530

1

2

603-1

X5R

25V

10%

1UF

C9545

1

2

MF-LF
402

1%
1/16W

5.76K

R9520

1

2

10K

1/16W

1%

MF-LF
402

R9521

1

2

X5R
603

6.3V

20%

10UF

C9515

1

2

1%

402

1/16W
MF-LF

75K

R9535

1

2

1%

130K

402

1/16W
MF-LF

R9585

1

2

PCMB065T-SM

2.2UH-8.0A

CRITICAL

L9510

1 2

330UF

2.0V

20%

CRITICAL

B2-SM

POLY-TANT

C9510

1

2

CRITICAL

220UF

POLY-TANT

CASE-B2-SM2

20%

2.5V

C9560

1

2

67 84

67

66 67 84

67

PCMB065T-SM

1.0UH-13A-5.6MOHM

CRITICAL

L9560

1 2

X7R
603-1

10%
50V

0.1UF

C9580

1

2

20%
16V

CASED2E-SM

33UF

POLY-TANT

CRITICAL

C9540

1

2

CASED2E-SM

POLY-TANT

CRITICAL

20%
16V

33UF

C9590

1

2

PLACEMENT_NOTE=Place next to C7665

SM

XW9565

12

NO STUFF

100PF

5%

50V

CERM

402

C9520

1

2

SM

PLACEMENT_NOTE=Place XW9515 next to C7615

XW9515

1 2

QFN

CRITICAL

ISL6236

OMIT

U9500

17 24

9

14 27

4

11

21

12 31

7
8

18 23
10 30

22

16 25

13

28

19

1

32

20

29

33

2

15 26

365

10UF

X5R
805

10%
25V

C9500

1

2

SM

XW9500

1 2

0.1UF

CERM
402

20%
10V

C9585

1

2

402

1/16W

1%

MF-LF

127K

R9564

1

2

14.0K

MF-LF

1/16W

1%

402

R9563

1

2

X5R

402-1

10%

1UF

10V

C9503

1

2

10V

2

1

C9501

1UF

402-1

X5R

10%

78.7K

MF-LF
402

1%
1/16W

R9562

1

2

SOD-VESM-HF

SSM3K15FV

Q9565

3

1

2

16V

0.01UF

10%

402

CERM

C9561

1

2

1/16W

4.7

5%

402

MF-LF

R9500

12

10%
10V

1UF

X5R

402-1

C9504

1

2

CRITICAL

SI7110DN

PWRPK-1212-8-HF

Q9560

5

4

1 2 3

PWRPK-1212-8-HF

SI7108DN

CRITICAL

Q9561

5

4

1 2 3

CRITICAL

SI7110DN

PWRPK-1212-8-HF

Q9510

5

4

123

PWRPK-1212-8-HF

CRITICAL

SI7108DN

Q9515

5

4

123

75

1

CRITICAL

IC,ISL6236,DUAL PWM CNTRL,QFN32

U9500

353S2312

SYNC_DATE=05/21/2008

1.1V / 1V8 FB Power Supply

SYNC_MASTER=RXU_K20

051-7656

31

123

95

=PP5V_S0GPU_P1V1P1V8_GPU

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP5V_S0GPU_P1V1P1V8_VCC

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

GND_P1V1P1V8_SGND

GPIO7_FBVDD_ALTVO

P1V8_GPU_VSNS

P1V8FB_TRIP

P1V1GPU_VBST

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

VOLTAGE=2V

PP2V_S0GPU_P1V8_REF

P1V1GPU_TRIP

P1V8FB_PGOOD

P1V1GPU_PGOOD

=P1V1GPU_EN

PVIN_S0GPU_P1V1

MIN_LINE_WIDTH=0.6MM

P1V8FB_VBST

MIN_NECK_WIDTH=0.2MM

=PP1V8_GPU_REG

PP5V_S0GPU_VREF

VOLTAGE=5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

P1V1S0_VSNS

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

P1V8FB_DRVL

=PP1V1_S0GPU_REG

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

P1V1GPU_DRVH

MIN_NECK_WIDTH=0.2MM

P1V1GPU_LL

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

GPU_P1V8_REFIN

MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

P1V1GPU_DRVL

MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

MIN_LINE_WIDTH=0.6MM

P1V8FB_DRVH

MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

P1V8FB_LL

MIN_LINE_WIDTH=0.6MM

=P1V8FB_EN

GPUFB_VID_L

=PPVIN_S0GPU_P1V8P1V1

P1V1GPU_VFB

8

8

8

8

Preliminary

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

D

S G

IN

IN
IN

IN

OUT

OUT

OUT

OUT

OUT

IN

IN
OUT

D

SG

D

SG

IN

IN

D

S G

IN
IN

IN

IN

IN

IN
IN

IN

IN

IN

IN

PT17B

PT17A

PT16B

PT16A

PT15A

PT14B

PT4B

PT4A

PT3B

PT3A

PR10B

PR10A

PT32A

PT20B

PT19B

PT19A

PB15B
PB16A
PB16B

PR11B
PR12A

PR13B

PR14B
PR15A
PR15B
PR16A
PR16B

CFG0

GND

GNDIO0

GNDIO1

GNDIO2

GNDIO3

GNDIO4

GNDIO5

GNDIO6

GNDIO7

LRC_GNDPLL

LRC_VCCPLL

PB2A
PB2B
PB14A
PB14B
PB15A

PB17A
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B

PL2A
PL2B
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL18A
PL18B
PL19A
PL19B
PL32A
PL32B

PR2A
PR2B

PR11A

PR12B
PR13A

PR14A

PR18A
PR18B
PR30A
PR30B

PT2A
PT2B

PT14A

PT15B

PT18B

PT20A

PT32B

TCK
TDI
TDO
TMS
TOE

ULC_GNDPLL

ULC_VCCPLL

VCCAUX

VCCIO0

VCCIO1

VCCIO2

VCCIO3

VCCIO4

VCCIO5

VCCIO6

VCCIO7

VCCJ

PT18A

VCC

IN

IN
OUT

IN

BI
BI

BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

BANK1

GMUX_JTAG_TCK Inversion

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

BANK3

GMUX CPLD

The MAKE BASE properties for these signals are on the POWER CONTROL page.

Required Pulldowns

Required Pullups

BANK0

(OD)

BANK5

LVDS Receiver Termination

PM_SLP_S3_L Isolation

(All 14 resistors)

BANK2

(OD)

BANK4 BANK6BANK7

82 67

41 36 33 21

7

95 84 76

81

82 81 75

95 81

95 81

95 81

95 81

95 81

7

95 81

7

95 81

4V
X5R
402

20%

4.7UF

C9600

1

2

95 81

7

95 81

95 81

84

84

95 81

95 81

95 81

95 81

95 81

7

R9670

2

1

MF-LF

1/16W

1%

10K

402

7

95 81

5

4

3

SSM6N15FEAPE

SOT563

Q9670

17

100K

5%

MF-LF

402

1/16W

R9693

1 2

20K

1/16W

402

5%

MF-LF

R9692

1 2

NO STUFF

100K

1/16W

5%

402

MF-LF

R9691

1 2

R9683

5%

1/16W MF-LF

10K

402

1 2

R9682

MF-LF

402

5%

10K

1/16W

1 2

9

5%

4.7K

402

MF-LF1/16W

R9690

1 2

R9681

10K

5%

402

MF-LF1/16W

1 2

R9680

21

1K

1/16W MF-LF

402

5%

0.1UF

CERM

10V

20%

402

C9630

1

2

0.1UF

CERM

10V

402

20%

C9631

1

2

PLACEMENT_NOTE=Place at U9600

SIGNAL_MODEL=EMPTY

100

402

1%

MF-LF1/16W

R9666

1 2

PLACEMENT_NOTE=Place at U9600

100

402

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9665

1 2

PLACEMENT_NOTE=Place at U9600

402

100

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9664

1 2

PLACEMENT_NOTE=Place at U9600

1/16W MF-LF

100

402

1%

SIGNAL_MODEL=EMPTY

R9663

1 2

84

PLACEMENT_NOTE=Place at U9600

100

402

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9656

1 2

PLACEMENT_NOTE=Place at U9600

100

402

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9662

1 2

PLACEMENT_NOTE=Place at U9600

100

402

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9661

1 2

PLACEMENT_NOTE=Place at U9600

1%

1/16W MF-LF

402

100

SIGNAL_MODEL=EMPTY

R9660

1 2

PLACEMENT_NOTE=Place at U9600

100

402

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9655

1 2

PLACEMENT_NOTE=Place at U9600

100

402

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9651

1 2

PLACEMENT_NOTE=Place at U9600

1/16W

100

402

MF-LF

1%

SIGNAL_MODEL=EMPTY

R9652

1 2

PLACEMENT_NOTE=Place at U9600

100

402

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9653

1 2

PLACEMENT_NOTE=Place at U9600

1%

100

402

MF-LF1/16W

SIGNAL_MODEL=EMPTY

R9654

1 2

PLACEMENT_NOTE=Place at U9600

100

402

MF-LF1/16W

1%

SIGNAL_MODEL=EMPTY

R9650

1 2

84

5%

402

1/16W

10K

MF-LF

R9695

1 2

PLACEMENT_NOTE=Place on top side at U9600

R9679

SILK_PART=GMUX_RST

1/16W

10K

1%

MF-LF

402

1

2

NO STUFF

67

68 67

83 67

77 67

83 67 66

25

NO STUFF

10V
CERM
402

0.1UF

20%

1

2

C9694

NO STUFF

10V
CERM
402

20%

0.1UF

1

2

C9693

EG_PWRSEQ_HW

1/16W MF-LF0402

5%

R9630

1 2

EG_PWRSEQ_GMUX

402

1/16W MF-LF

5%

0

R9631

1 2

EG_PWRSEQ_GMUX

MF-LF

402

0

5%

1/16W

R9632

1 2

2

1

CERM

10V

20%

402

0.1UF

NO STUFF

C9692

NO STUFF

10V
CERM

0.1UF

402

20%

1

2

C9691

EG_PWRSEQ_GMUX

0

MF-LF

402

5%

1/16W

R9634

1 2

EG_PWRSEQ_GMUX

MF-LF

402

0

5%

1/16W

R9633

1 2

90 84 18

100K

1/16W MF-LF

402

5%

R9694

1 2

R9674

402

MF-LF

1/16W

5%

4.7K

EG_PWRSEQ_GMUX

1

2

R9673

402

MF-LF

1/16W

5%

4.7K

EG_PWRSEQ_GMUX

1

2

R9672

EG_PWRSEQ_GMUX

402

MF-LF

1/16W

5%

4.7K

1

2

R9671

EG_PWRSEQ_GMUX

4.7K

402

1/16W
MF-LF

5%

1

2

0402

FERR-220-OHM

L9621

1 2

0402

FERR-220-OHM

L9620

1 2

9

SSM6N15FEAPE

Q9607

SOT563

2

1

6

4

Q9607

SSM6N15FEAPE

SOT563

5

3

10%

6.3V

2

1

402

CERM

C9695

1UF

NO STUFF

R9676

100K

MF-LF

1/16W

5%

402

2

1

5%

0

402

2

1

1/16W
MF-LF

R9675

NO STUFF

R9677

10K

1 2

1%
1/16W
MF-LF

402

NO STUFF

90 84 18

R9678

4.7K

2

1

1/16W

5%

MF-LF

402

1/16W

402

R9684

5%

0

1 2

MF-LF

67 41 25

SSM6N15FEAPE

SOT563

6

2

1

Q9670

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

90 84 18

B4

M11

M14

E14

P14

CRITICAL

OMIT

CSBGA-HF

XP28

U9600

K1

J1B8C6

C12

C13

E13

N10

N6P3M2C1E2

P11

P4

N4

N3
M4

P5

M5
P6

M6
P7

M7

N7
N8

P9

N9

P2

N2

P10

M10

P12
P13

N12

C2

D3
D1

E1

D2
E3

F1
G1

F3

G2
H2

G3

H1
H3

L1

L3
K3

L2

B1
B2

P1

D12

D13
D14

E12
F12

F14
G14

G12

G13
H13

H12

H14

L14

M13

A14
B14

B6

C7
A6

A7
C8

C9

A8
B9

A9

C10
B10

A10

A11
B12

A2

A3

B13
A13

A1

B3

C5
A5

K14

L13

K13
L12

K2

A4

B11C4J3

J13

N11P8C11J2J14M8B5B7A12

C14

F13

M12M9M3N5M1C3F2

K12

N1

J12

N13

N14

90 84 18

25

84

9

91 25 19

91 43 41 19

7

91 43 41 19

7

91 43 41 19

7

91 43 41 19

7

MF-LF

1/16W

1%

10K

402

NO STUFF

R9647

1

2

91 43 41 19

7

84 78

75

84

9

84

84

84

84

84

9

84 81

81

402

CERM

10V

20%

0.1UF

C9604

1

2

1

C9605

0.1UF

10V

20%

CERM
402

2

84 81

84 81

85 84

7

9

9 6

9 6

9 6

NO STUFF

402

10K

1%
1/16W
MF-LF

R9641

1

2

402

10V
CERM

20%

0.1UF

C9606

1

2

10V
CERM

0.1UF

20%

402

C9607

1

2

20%

CERM

10V

0.1UF

402

C9608

1

2

C9609

CERM

10V

0.1UF

20%

402

1

2

0.1UF

CERM

20%
10V

402

C9610

1

2

10V

402

20%

CERM

0.1UF

C9611

1

2

10V

20%

402

CERM

0.1UF

C9621

1

2

C9622

10V
CERM

20%

402

0.1UF

1

2

0.1UF

20%

402

10V
CERM

C9612

1

2

402

CERM

10V

20%

0.1UF

C9613

1

2

NO STUFF

402

10K

1%
1/16W
MF-LF

R9646

1

2

C9623

0.1UF

402

20%

CERM

10V

1

2

20%

402

CERM

10V

0.1UF

C9624

1

2

CERM
402

0.1UF

20%
10V

C9614

1

2

20%
10V
CERM
402

0.1UF

C9625

1

2

0.1UF

10V

20%

402

CERM

C9615

1

2

0.1UF

20%
10V

402

CERM

C9616

1

2

C9626

402

CERM

0.1UF

20%
10V

1

2

20%

0.1UF

CERM

10V

402

C9627

1

2

0.1UF

CERM
402

20%
10V

C9617

1

2

402

1%

MF-LF

1/16W

10K

R9640

1

2

CERM
402

0.1UF

20%

C9628

1

2

10V

402

10V

20%

0.1UF

C9629

1

2

CERM

75

9

75

9

95 84 76

95 84 76

95 84 76

1%

402

MF-LF

1/16W

10K

R9645

1

2

95 84 76

95 84 76

95 84 76

95 84 76

95 84 76

95 84 76

7

95 84 76

95 84 76

95 84 76

95 84 76

U9600

1

CRITICAL

GMUX_PROG

341S2354 IC,CPLD,LATTICE,132CSBGA,K20

IC,XP2-8,HF,CPLD,BLANK

336S0027

U9600

CRITICAL1GMUX_8K_BLANK

96

123

31

051-7656

SYNC_DATE=02/13/2008

Graphics MUX (GMUX)

SYNC_MASTER=T18_MXMGMUX

EG_RAIL2_EN

EG_RESET_L

GMUX_INT

EG_CLKREQ_IN_L

EXTGPU_PWR_EN

TP_GMUX_PL18B_VSYNC

LVDS_IG_B_DATA_P<0>

PM_SLP_S3_L

TP_GMUX_PL10A

LVDS_IG_A_DATA_N<2>

LVDS_MUX_SEL_EG

TP_GMUX_PL10B
LVDS_IG_A_DATA_P<0>

=GMUX_PCIE_RESET_L

LPC_FRAME_L

LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>

LPC_AD<3>

LPC_AD<2>

LPC_AD<0>

LCD_PWR_EN

LVDS_DDC_SEL_EG

EG_PWRSEQ_EN

EG_PWRSEQ_EN

GMUX_PM_SLP_S3_L

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_P<2> LVDS_IG_A_DATA_N<2>

LVDS_IG_B_DATA_P<0> LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<2>

LVDS_EG_A_CLK_P LVDS_EG_A_CLK_N

LVDS_EG_B_DATA_P<1> LVDS_EG_B_DATA_N<1>

LVDS_EG_B_DATA_P<0> LVDS_EG_B_DATA_N<0>

LVDS_EG_A_DATA_P<0>

DP_CA_DET_EG

JTAG_GMUX_TCK

GMUX_PM_SLP_S3_L

LVDS_IG_B_DATA_N<2>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_CLK_N

LVDS_IG_B_DATA_N<1>

LVDS_IG_A_DATA_N<0>

EG_CLKREQ_IN_L

ALL_EG_PGOOD

JTAG_GMUX_TMS

JTAG_GMUX_TDO

JTAG_GMUX_TDI

LCD_BKLT_PWM

LCD_BKLT_EN

DP_MUX_SEL_EG

GMUX_DEBUG_RESET_L

LVDS_EG_B_DATA_P<2>

JTAG_GMUX_TCK

EG_CLKREQ_OUT_L

=PP3V3_S0_GMUX

LVDS_EG_A_DATA_P<2>

LVDS_EG_A_DATA_P<1>

LVDS_EG_A_DATA_P<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<0>

LVDS_B_CLK_N

DP_MUX_EN

DP_HOTPLUG_DET

LVDS_A_DATA_N<1>

LVDS_A_DATA_P<1>

LVDS_DDC_SEL_EG

=P1V8FB_EN

=GPUVCORE_EN

P3V3GPU_EN

=P1V1GPU_EN

EG_RAIL4_EN

EG_RAIL2_EN

LCD_BKLT_PWM

EG_RESET_L

TP_GMUX_PT20B

TP_GMUX_PT20A

LVDS_A_DATA_N<2>

LVDS_A_DATA_P<2>

LVDS_A_CLK_N

LVDS_A_CLK_P

EG_RAIL1_EN

LVDS_IG_B_DATA_N<0>

GMUX_JTAG_TCK_L

=PP3V3_S0_GMUX

LVDS_B_CLK_P

TP_GMUX_PT32A

LVDS_A_DATA_P<0>

GMUX_DEBUG_RESET_L

TP_GMUX_PT32B

=PP3V3_S3_GMUX

LVDS_EG_A_DATA_P<1>

GMUX_S3_PD_EN

EG_BKLT_EN

LVDS_EG_B_DATA_P<2>

LVDS_EG_B_DATA_N<1>

=PP3V3_S0_GMUX

LVDS_DDC_SEL_IG

LVDS_EG_A_DATA_N<2>

LVDS_EG_A_DATA_P<2>

LPC_CLK33M_GMUX

LPC_RESET_L

EG_RAIL3_EN

LVDS_EG_A_DATA_N<1>

LCD_PWR_EN

LVDS_EG_A_DATA_N<0>

LVDS_EG_A_CLK_N

LVDS_EG_A_CLK_P

LVDS_EG_B_DATA_N<2>

LVDS_EG_B_DATA_P<1>

LVDS_EG_B_DATA_N<0>

LVDS_EG_B_DATA_P<0>

LVDS_IG_A_CLK_N

LVDS_IG_A_CLK_P

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_P<1>

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

PP3V3_S0_GMUX_LRC_VCCPLL

=PP3V3_S0_GMUX

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_N<0>

GMUX_INT

EG_CLKREQ_OUT_L

EG_RAIL4_EN

GMUX_CFG0

GMUX_TOE

IG_BKLT_EN

EG_LCD_PWR_EN

IG_LCD_PWR_EN

ALL_SYS_PWRGD

=PP2V5_S0_GMUX

LPC_AD<1>

GMUX_S0_PD_DIS_RC

=PP3V3_S0_GMUX

PP3V3_S0_GMUX_ULC_VCCPLL

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm

JTAG_GMUX_TCK

DP_CA_DET

LVDS_A_DATA_N<0>

LVDS_EG_B_DATA_N<2>

LVDS_EG_A_DATA_N<2>

LVDS_EG_A_DATA_N<1>

LVDS_EG_A_DATA_N<0>

LVDS_IG_A_CLK_P

LVDS_DDC_SEL_IG

LVDS_B_DATA_N<0>
LVDS_B_DATA_P<1>
LVDS_B_DATA_N<1>

DP_MUX_SEL_EG

EG_RAIL3_EN

EG_RAIL1_EN

=PP1V2_S0_GMUX

GMUX_S3_PD_GND

95

90

90

90

90 90

90 90

90

95 95

95 95

95 95

90

90

90

90

90

95

95

95

95

85

95

84

95

95

90

84

84

84

84

84 84

84 84

84

84 84

84 84

84 84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

84

76

84

84

84

84

84

9

84

84

84

18

18

18

18 18

18 18

18

76 76

76 76

76 76

6

18

18

18

18

18

84

76

9

8

76

76

76

81

84

84

7

9

84

8

8

8

84

78

8

8

8

6

76

7

76

76

18

81

81

8

Preliminary

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

G

P-CHN

S

D

G

D

S

N-CHN

IN

VREF

DIM

ENA

VSYNC

SSTCMP

ISEN4

ISEN5

ISEN3

VSEN

VIN

THRM_PAD

LRT

LPF

ISWSEN

ISET

ISEN6

ISEN2

ISEN1

GNDA

DRV

RT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

50.4*R9724/(R9723+R9724)=2.4V

*R9702 AND R9715 PIN 1 SHOULD BE PLACED NEAR C9709 PIN 2

*BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

*Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER.

THRESHOLD=2.5V

*R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT

7

78

7

78

7

78

7

78

7

78

7

78

7

78 85

RB160M-60G

1 2

SOD-123

CRITICAL

D9701

PLACEMENT_NOTE=D9701 PLACE NEAR Q9701

85 86

SM

XW9702

1 2

PLACEMENT_NOTE=R9702 PLACE NEAR C9709 AND Q9701

MF

402

1/6W

1%

0.4

R9702

1 2

NO STUFF

402

47PF

CERM

5%
50V

C9712

1

2

PLACEMENT_NOTE=R9715 PLACE NEAR C9709 AND Q9701

402

1%

MF

1/6W

0.4

R9715

1 2

PLACEMENT_NOTE=L9701 PLACE NEAR Q9701

IHLP2525CZ-SM

22UH-2.5A

L9701

1 2

CRITICAL

1%

402

1/16W
MF-LF

R9731

1 2

187K

21

R9701

402

1%
MF-LF

1/16W

49.9

402

0.1UF

10%
25V
X5R

1

2

C9713

2

X5R

0.1UF

25V

C9702

1

10%

402

R9707

2.67K

21

1%
1/16W
MF-LF
402

PLACEMENT_NOTE=R9707 AWAY FROM Q9701

R9713

0

1/16W
MF-LF

PLACEMENT_NOTE=R9713 AWAY FROM Q9701

BKLT_PLL_NOT

402

5%

1 2

78

7

BKLT_PLL

1/16W

0

5%

MF-LF

402

R9734

12

1/16W

10.2

402

TF

0.1%

R9718

1 2

402

TF

0.1%

1/16W

10.2

R9719

1 2

402

0.1%

10.2

TF

1/16W

R9720

1 2

1/16W

10.2

402

TF

0.1%

R9721

1 2

1/16W

0.1%

TF

402

10.2

R9722

1 2

Q9701

21 3

4

5

CRITICAL

PWRPK-1212-8

SI7308DN

4.02K

1/16W

1%

402

MF-LF

R9710

1 2

8.06K

1/16W

1%

402

MF-LF

R9711

1 2

SOT-963

CRITICAL

Q9702

3

5

4

NTUD3127CXXG

NTUD3127CXXG

CRITICAL

SOT-963

Q9702

6

2

1

10K

402

MF-LF

1%

1/16W

R9700

1 2

7

84

2

1

C9714

1UF

10%

402

X5R

10V

R9733

2

4.7K

402

MF-LF

5%
1/16W

1

C9706

0.0022UF

402

50V
CERM

10%

1

2

R9703

2.0M

NO STUFF

21

MF-LF

5%

1/16W

402

17

1

2

U9700

CRITICAL

QFN

APP001

4

20

5

7 14

15

12

9

3

21

18

19

8

16

11

10

13

6

OMIT

402

1/16W

1%

100

MF-LF

R9704

1 2

PLACEMENT_NOTE=R9708 AWAY FROM Q9701

1/16W

100K

1%
MF-LF

402

R9708

1 2

1K

1/16W

PLACEMENT_NOTE=R9709 AWAY FROM Q9701

R9709

1%

MF-LF

402

1 2

C9705

10V

0.1UF

402

CERM

20%

1

2

402-LF

2.2UF

BKLT_PLL

CERM

6.3V

20%

C9707

1

2

PLACEMENT_NOTE=R9714 AWAY FROM Q9701

BKLT_PLL

1/16W
MF-LF

402

5%

10K

R9714

1 2

C9708

402

0.1UF

10%

X5R

25V

BKLT_PLL

1

2

10.2

402

TF

0.1%

1/16W

R9717

1 2

CRITICAL

1210

2.2UF

10%
100V

PLACEMENT_NOTE=C9709 PLACE NEAR C9710

X7R

C9709

1

2

CRITICAL

PLACEMENT_NOTE=C9710 PLACE NEAR J9000

2.2UF

10%

1210

X7R

100V

C9710

1

2

1.2M

MF-LF

603

1%

1/10W

R9723

1 2

1/16W
MF-LF

1%

60.4K

402

R9724

1 2

10V

C9703

1UF

10%

X5R
402

1

2

R9705

1%

402

MF-LF

1/16W

100K

1 2

402

21

R9706

MF-LF

10K

5%
1/16W

PLACEMENT_NOTE=XW9701 PLACE NEAR C9701

XW9701

1 2

SM

PLACEMENT_NOTE=C9701 PLACE NEAR L9701

CRITICAL

X5R

10UF

25V

805

10%

1

2

C9701

75K

MF-LF

PLACEMENT_NOTE=R9727 AWAY FROM Q9701

1%

1/16W
402

R9727

1 2

MF-LF

0

5%
1/10W

603

R9730

12

U9700

IC,APP001A,WHT LED BKLGHT CTR,SCRN,QFN20

353S2413 CRITICAL

1

SYNC_MASTER=KIRAN_K20

LCD BACKLIGHT DRIVER

SYNC_DATE=12/03/2008

123

31

051-7656

97

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

VOLTAGE=50V

BOOST_SINK

MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM

BOOST_SINK_R

BOOST_FET_CNTL

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.20MM

BKL_ISET

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE

VOLTAGE=50V

PPVOUT_S0_LCDBKLT_SW

MIN_LINE_WIDTH=0.5MM

VOLTAGE=6V
MIN_NECK_WIDTH=0.375MM

PPVIN_S0_LCDBKLT_BUF

BKL_PWR_EN_L

BKL_VREF_IN_4V9

BKLT_PWM_RC

BKL_DIM

BKL_SYNC

BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

BKL_ISEN5

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN3

GND_BKL_PWRGND

LED_RETURN_6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

PPVOUT_S0_LCDBKLT

BKL_VREF_4V9

GND_BKL_PWRGND

BKL_LRT_RC

LED_RETURN_3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_4

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

PPBUS_S0_LCDBKLT_PWR

MIN_LINE_WIDTH=0.5MM

GND_BKL_PWRGND

MIN_NECK_WIDTH=0.20MM

GND_BKL_PWRGND_X

MIN_LINE_WIDTH=0.5MM

MIN_NECK_WIDTH=0.20MM

BKL_VREF_4V9

PPBUS_S0_LCDBKLT_PWR

VOLTAGE=6V

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.375 MM

BKL_ISEN1

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

GND_BKL_PWRGND

BKL_VIN

BKL_VSEN

BKL_VSYNC

BKLT_EN

BKL_LPF

BKL_LRT

BKL_VREF_4V9

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN4

BKL_SSTCMP_RC

BKL_SSTCMP

LCD_BKLT_PWM

BKL_RT

85 78

86

85

7

85

85

85

85

85

7

85

Preliminary

D

SG

D

SG

IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

.

FDC638APZ

43 mOhm @4.5V

0.4 A (EDP)

P-TYPE

PPBUS S0 LCDBkLT FET

MOSFET

RDS(ON)

LOADING

CHANNEL

3AMP-32V-467

603-HF

F9800

1 2

1/16W
MF-LF

1%

301K

402

R9808

1

2

MF-LF

1/16W

402

147K

1%

R9809

1

2

X5R
402

10%
16V

0.1UF

C9802

1

2

SSOT6-HF

CRITICAL

FDC638APZ_SBMS001

Q9806

1 2 5 6

3

4

SOT563

SSM6N15FEAPE

Q9807

6

2

1

SOT563

SSM6N15FEAPE

Q9807

3

5

4

9

25

402

1/16W

5%

4.7K

MF-LF

R9840

1

2

051-7656

31

123

98

LCD Backlight Support

SYNC_MASTER=YLEE_K20 SYNC_DATE=07/18/2008

BKLT_PLT_RST_L

=PPBUS_S0_LCDBKLT

LVDS_BKL_ON

VOLTAGE=6V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_S0_LCDBKLT_FUSED

PPBUS_S0_LCDBKLT_EN_DIV

VOLTAGE=6V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPBUS_S0_LCDBKLT_PWR

BKLT_EN_L

PPBUS_S0_LCDBKLT_EN_L

8

85

Preliminary

IN

VIN

SW1

SW2

GND

RUN2

RUN1

VFB1
VFB2

PAD

THRML

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

(Switcher limit)
f = 2.25 MHz

0.3A max output

<Ra>

<Ra>

(Switcher limit)

<Rb>

<Rb>

Vout = 0.6V * (1 + Ra/Rb)

f = 2.25 MHz

300mA max output

Vout = 2.5V

Vout = 1.2V

GMUX 1.8V/1.2V S0 Switcher

67

CRITICAL

LTC3547

DFN-HF

U9900

5

2

7

4

6

9

1

8

3

PCAA031B-SM

2.2UH-1.2A

CRITICAL

L9900

1 2

2.2UF

20%

6.3V
CERM

402-LF

C9900

1

2

2.2UH-1.2A

PCAA031B-SM

CRITICAL

L9980

1 2

2

1

R9901

150K

402

MF-LF

1%
1/16W

OMIT

CERM

402

5%

10PF

50V

C9901

1

2

2

1

R9900

475K

402

1/16W

1%

MF-LF

402

1%
1/16W

280K

MF-LF

R9983

1

2

402

50V

CERM

10PF

5%

C9982

1

2

280K

1/16W

1%

402

R9982

2

1

MF-LF

4.7UF

402

20%
4V
X5R

C9985

1

2

X5R

4V

402

1

2

C9905

20%

4.7UF

SYNC_DATE=05/07/2008

SYNC_MASTER=RXU_K20

Misc Power Supplies

051-7656

31

123

99

1

GMUX_1V8114S0447

RES,MTL FILM,1/16W,237K,1,0402,SMD,LF

R9901

1

GMUX_2V5114S0428

RES,MTL FILM,1/16W,150K,1,0402,SMD,LF

R9901

P2V5S0_VFB

=PP1V2_S0_REG

=P1V2S0_EN

=P2V5S0_EN

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P2V5S0_SW

MIN_NECK_WIDTH=0.2 mm

=PP3V3_S0_P1V2P2V5

P1V2S0_VFB

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

P1V2S0_SW

SWITCH_NODE=TRUE

=PP2V5_S0_REG

8

67

8

8

Preliminary

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

Some signals require 27.4-ohm single-ended impedance.

FSB Clock Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SR DG recommends at least 25 mils, >50 mils preferred

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

PHYSICAL

FSB 2X

FSB 4X Signal Groups

ELECTRICAL_CONSTRAINT_SET

FSB 1X Signals

SPACING

NET_TYPE

Signals

(See above)

(FSB_CPURST_L)

(CPU_VCCSENSE)

(CPU_VCCSENSE)

CPU / FSB Net PropertiesFSB (Front-Side Bus) Constraints

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 4X signals / groups shown in signal table on right.
Signals within each 4x group should be matched within 5 ps of strobe.

FSB 2X signals / groups shown in signal table on right.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.

=50_OHM_SE

MCP_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE

*

=STANDARD =STANDARD

*

CPU_VCCSENSE

?

25 MIL

=3x_DIELECTRIC

?

CLK_FSB

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

CLK_FSB_100D

8 MIL

* ?

MCP_FSB_COMP

25 MIL

CPU_GTLREF

* ?

CPU_ITP

* ?

=2:1_SPACING

?

CPU_COMP

*

25 MIL

8 MIL

CPU_8MIL

?*

CPU_AGTL

?*

=STANDARD

=27P4_OHM_SE

=27P4_OHM_SE

*

=27P4_OHM_SE =27P4_OHM_SE

7 MIL7 MIL

CPU_27P4S

*

=STANDARD =STANDARD

CPU_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE =50_OHM_SE

=4x_DIELECTRICCLK_FSB

?

TOP,BOTTOM

TOP,BOTTOM

FSB_ADSTB

?

=4x_DIELECTRIC

=50_OHM_SE

*

=STANDARD

FSB_50S

=50_OHM_SE =50_OHM_SE

=STANDARD

=50_OHM_SE

TOP,BOTTOM

?

FSB_DATA

=4x_DIELECTRIC

CPU_AGTL

?

TOP,BOTTOM

=2x_DIELECTRIC

100 123

31

051-7656

CPU/FSB Constraints

SYNC_MASTER=M98_MLB

SYNC_DATE=04/01/2008

=50_OHM_SE=50_OHM_SE=50_OHM_SE

=50_OHM_SE

FSB_DSTB_50S

=1:1_DIFFPAIR=1:1_DIFFPAIR

*

TOP,BOTTOM

FSB_DSTB

?

=5x_DIELECTRIC

FSB_ADDR

TOP,BOTTOM

?

=3x_DIELECTRIC

FSB_1X

TOP,BOTTOM

?

=3x_DIELECTRIC

FSB_DATA

* ?

=2x_DIELECTRIC

?

FSB_DSTB

*

=3x_DIELECTRIC

=STANDARD

*

FSB_ADDR

?

=STANDARDFSB_1X

?*

FSB_ADSTB

?*

=2x_DIELECTRIC

FSB_DATA

FSB_D_L<15..0>

FSB_50S

FSB_DATA_GROUP0

FSB_DSTB_L_P<0>

FSB_DSTB0

FSB_DSTB

FSB_DSTB_50S

FSB_DSTB_L_N<0>

FSB_DSTB

FSB_DSTB0

FSB_DSTB_50S

FSB_DATA

FSB_D_L<31..16>

FSB_DATA_GROUP1

FSB_50S

FSB_DATA

FSB_DINV_L<1>

FSB_DATA_GROUP1

FSB_50S

FSB_DSTB_L_P<1>

FSB_DSTB

FSB_DSTB1

FSB_DSTB_50S

FSB_DATA

FSB_DINV_L<2>

FSB_DATA_GROUP2

FSB_50S

FSB_DSTB2

FSB_DSTB

FSB_DSTB_L_P<2>

FSB_DSTB_50S

FSB_DSTB_L_N<2>

FSB_DSTB2

FSB_DSTB

FSB_DSTB_50S

FSB_DATA

FSB_DATA_GROUP3

FSB_D_L<63..48>

FSB_50S

FSB_DATA

FSB_DINV_L<3>

FSB_DATA_GROUP3

FSB_50S

FSB_DSTB3

FSB_DSTB

FSB_DSTB_L_P<3>

FSB_DSTB_50S

FSB_DSTB_L_N<3>

FSB_DSTB3

FSB_DSTB

FSB_DSTB_50S

FSB_50S

FSB_A_L<16..3>

FSB_ADDR_GROUP0

FSB_ADDR

FSB_50S

FSB_ADDR

FSB_REQ_L<4..0>

FSB_ADDR_GROUP0

FSB_A_L<35..17>

FSB_ADDR

FSB_ADDR_GROUP1

FSB_50S

FSB_50S

FSB_ADSTB

FSB_ADSTB1

FSB_ADSTB_L<1>

FSB_ADS_L

FSB_1XFSB_1X

FSB_50S

FSB_1X

FSB_BREQ0_L

FSB_BREQ0_L

FSB_50S

FSB_1X

FSB_BREQ1_L

FSB_BREQ1_L

FSB_50S

FSB_BNR_L

FSB_1XFSB_1X

FSB_50S

FSB_BPRI_L

FSB_1XFSB_1X

FSB_50S

FSB_1X

FSB_DBSY_L

FSB_1X

FSB_50S

FSB_1X

FSB_DEFER_L

FSB_1X

FSB_50S

FSB_1X

FSB_DRDY_L

FSB_1X

FSB_50S

FSB_1X

FSB_HIT_L

FSB_1X

FSB_50S

FSB_HITM_L

FSB_1XFSB_1X

FSB_50S

FSB_1X

FSB_CPURST_L

FSB_CPURST_L

FSB_50S

FSB_1X

FSB_RS_L<2..0>

FSB_1X

FSB_50S

FSB_1X

FSB_TRDY_L

FSB_1X

FSB_50S

CPU_AGTL

CPU_BSEL<2..0>

CPU_BSEL

CPU_50S

CPU_8MIL

CPU_FERR_L

CPU_FERR_L

CPU_50S

CPU_AGTL

CPU_IGNNE_L

CPU_ASYNC

CPU_50S

CPU_AGTL

CPU_INIT_L

CPU_INIT_L

CPU_50S

CPU_AGTL

CPU_INTR

CPU_ASYNC_R

CPU_50S

CPU_AGTL

CPU_NMI

CPU_ASYNC_R

CPU_50S

CPU_AGTL

CPU_PROCHOT_L

CPU_PROCHOT_L

CPU_50S

CPU_AGTL

CPU_PWRGD

CPU_PWRGD

CPU_50S

CPU_AGTL

CPU_SMI_L

CPU_ASYNC

CPU_50S

CPU_AGTL

CPU_STPCLK_L

CPU_ASYNC

CPU_50S

CPU_8MIL

PM_THRMTRIP_L

PM_THRMTRIP_L

CPU_50S

CPU_AGTL

FSB_CPUSLP_L

FSB_CPUSLP_L

CPU_50S

CPU_AGTL

CPU_DPSLP_L

CPU_FROM_SB

CPU_50S

CPU_AGTL

CPU_DPRSTP_L

CPU_DPRSTP_L

CPU_50S

CPU_AGTL

FSB_DPWR_L

CPU_ASYNC

CPU_50S
MCP_50S

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP MCP_FSB_COMP

MCP_50S

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP MCP_FSB_COMP

MCP_50S

MCP_CPU_COMP_VCC

MCP_CPU_COMP MCP_FSB_COMP

MCP_50S

MCP_CPU_COMP_GND

MCP_CPU_COMP MCP_FSB_COMP

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_P

FSB_CLK_CPU

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_N

FSB_CLK_CPU

FSB_CLK_ITP_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP

FSB_CLK_ITP_N

CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP

FSB_CLK_MCP_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_MCP

FSB_CLK_MCP_N

CLK_FSB_100D

CLK_FSB

FSB_CLK_MCP

CPU_IERR_L

CPU_50S

CPU_IERR_L

PM_DPRSLPVR

CPU_AGTL

PM_DPRSLPVR

CPU_50S

IMVP_DPRSLPVR

CPU_AGTL

CPU_50S

CPU_GTLREF

CPU_50S

CPU_GTLREF

CPU_GTLREF

CPU_COMP

CPU_COMP<3>

CPU_50S

CPU_COMP

CPU_COMP

CPU_27P4S

CPU_COMP<2>

CPU_COMP

CPU_COMP

CPU_50S

CPU_COMP<1>

CPU_COMP

CPU_COMP<0>

CPU_27P4S

CPU_COMPCPU_COMP

XDP_TDI

CPU_ITPCPU_50SXDP_TDI

XDP_TDO

CPU_ITPCPU_50SXDP_TDO

XDP_TMS

CPU_ITPCPU_50SXDP_TMS

XDP_TCK

CPU_ITPCPU_50SXDP_TCK

XDP_TRST_L

CPU_ITPCPU_50S

XDP_TRST_L

CPU_ITP

XDP_BPM_L<4..0>

CPU_50S

XDP_BPM_L

XDP_BPM_L<5>

CPU_ITPCPU_50S

XDP_BPM_L5

CPU_50S CPU_ITP

XDP_CPURST_L

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

IMVP6_VSEN_N

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S

CPU_8MIL

IMVP6_VID<6..0>

CPU_50S

CPU_8MIL

CPU_50S

CPU_VID<6..0>

FSB_ADSTB0

FSB_ADSTB_L<0>

FSB_50S

FSB_ADSTB

FSB_DSTB1

FSB_DSTB

FSB_DSTB_50S

FSB_DSTB_L_N<1>

FSB_D_L<47..32>

FSB_DATA_GROUP2

FSB_DATA

FSB_50S

CPU_AGTL

CPU_A20M_L

CPU_ASYNC

CPU_50S

FSB_LOCK_L

FSB_1XFSB_1X

FSB_50S

FSB_DATA

FSB_DINV_L<0>

FSB_50S

FSB_DATA_GROUP0

14

61

61

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

14

13

14

14

42

14

42

14

13

13

13

13

14

14

14

14

14

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

10

14

14

10

14

10

10

10

10

14

14

10

14

14

14

10

10

14

13

14

14

14

14

14

10

14

14

14

14

14

61

26

10

10

10

10

10

13

13

61

61

61

11

10

10

10

14

10

10

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

9

14

10

10

7

10

7

7

7

9

10

10

9

10

10

10

9

9

10

10

10

10

10

10

10

9

10

14

14

14

14

10

10

13

13

14

14

10

21

61

10

10

10

10

10

6

6

6

6

6

10

10

13

11

11

61

61

9

9

7

7

7

10

7

7

Preliminary

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Memory Net Properties

DQ signals should be matched within 20 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

Memory Bus Constraints

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Spacing Group Assignments

Need to support MEM_*-style wildcards!

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

MCP MEM COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DDR3:

DDR2:

?*

=2:1_SPACING

MEM_CTRL2CTRL

?*

MEM_CMD2CMD

=1.5:1_SPACING

=40_OHM_SE

=STANDARD

*

=STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE

MEM_40S_VDD

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE

=STANDARD

*

=STANDARD

MEM_40S

MEM_70D_VDD

=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF =70_OHM_DIFF

*

=70_OHM_DIFF =70_OHM_DIFF

MEM_70D

=70_OHM_DIFF=70_OHM_DIFF

*

=70_OHM_DIFF=70_OHM_DIFF

=70_OHM_DIFF

=70_OHM_DIFF

*

MEM_DQS2MEM

MEM_DQS MEM_CMD

MEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

MEM_DQS

MEM_DQS2MEM

*

MEM_CLK

051-7656

31

123101

Memory Constraints

SYNC_MASTER=M98_MLB

SYNC_DATE=04/01/2008

=3:1_SPACING

?*

MEM_CMD2MEM

?*

=3:1_SPACINGMEM_DATA2MEM

?*

MEM_2OTHER

25 MIL

*

MEM_DQS2MEM

=3:1_SPACING

?

MEM_CLK

MEM_CMD2MEM

*

MEM_CMD

=4:1_SPACING

?*

MEM_CLK2MEM

=2.5:1_SPACING

?*

MEM_CTRL2MEM

=1.5:1_SPACING

?*

MEM_DATA2DATA

MEM_CTRL

MEM_CMD2MEM

MEM_CMD

*

MEM_CMD2CMD

MEM_CMDMEM_CMD

*

MEM_DATA

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

MEM_CLK

MEM_DATA

MEM_DATA2MEM

*

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

*

MEM_CLK2MEM

MEM_CTRL

MEM_CLK

*

MEM_CLK2MEM

MEM_CLKMEM_CLK

**

MEM_DATA

MEM_2OTHER

* *

MEM_CMD

MEM_2OTHER

* *

MEM_DQS

MEM_2OTHER

**

MEM_CTRL

MEM_2OTHER

* *

MEM_CLK

MEM_2OTHER

MEM_CMD

*

MEM_DATA

MEM_DATA2MEM

*

MEM_DATA

MEM_DATA2DATA

MEM_DATA

MEM_DQS

*

MEM_DATA

MEM_DATA2MEM

*

MEM_CLK

MEM_CTRL2MEM

MEM_CTRL

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_DQS

MEM_CTRL

MEM_DATA2MEM

*

MEM_DATA

MEM_CTRL

MEM_CTRL2MEM

*

MEM_CMD

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

MEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS MEM_DQS

=STANDARD=STANDARD

*

MCP_MEM_COMP

Y

7 MIL 7 MIL

=STANDARD

?*

8 MIL

MCP_MEM_COMP

MEM_B_CKE<3..0>

MEM_B_CNTL

MEM_CTRL

MEM_40S_VDD

MEM_70D_VDD

MEM_A_CLK_P<5..0>

MEM_A_CLK

MEM_CLK

MEM_A_CKE<3..0>

MEM_CTRL

MEM_A_CNTL

MEM_40S_VDD

MEM_70D_VDD

MEM_A_CLK_N<5..0>

MEM_A_CLK

MEM_CLK

MEM_CTRL

MEM_A_ODT<3..0>

MEM_A_CNTL

MEM_40S_VDD

MEM_CTRL

MEM_A_CS_L<3..0>

MEM_A_CNTL

MEM_40S_VDD

MEM_A_DM<2>

MEM_DATA

MEM_A_DQ_BYTE2 MEM_40S

MEM_DATA

MEM_A_DM<3>

MEM_A_DQ_BYTE3 MEM_40S

MEM_A_DM<4>

MEM_DATA

MEM_A_DQ_BYTE4 MEM_40S

MEM_A_DM<5>

MEM_DATA

MEM_A_DQ_BYTE5 MEM_40S

MEM_DATA

MEM_A_DM<6>

MEM_A_DQ_BYTE6 MEM_40S

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_DQSMEM_70D

MEM_DATA

MEM_A_DM<1>

MEM_A_DQ_BYTE1 MEM_40S

MEM_A_DQS0

MEM_A_DQS_N<0>

MEM_DQSMEM_70D

MEM_A_DQS1

MEM_A_DQS_N<1>

MEM_DQSMEM_70D

MEM_70D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQS

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_DQSMEM_70D

MEM_70D

MEM_A_DQS2

MEM_A_DQS_N<2>

MEM_DQS

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_DQSMEM_70D

MEM_A_DQS3

MEM_A_DQS_N<3>

MEM_DQSMEM_70D

MEM_A_DQS5

MEM_A_DQS_N<5>

MEM_DQSMEM_70D

MEM_70D

MEM_A_DQS4

MEM_A_DQS_N<4>

MEM_DQS

MEM_70D

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_DQS

MEM_70D

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_DQS

MEM_A_BA<2..0>

MEM_A_CMD

MEM_CMD

MEM_40S_VDD

MEM_DATA

MEM_A_DM<0>

MEM_A_DQ_BYTE0 MEM_40S

MEM_DATA

MEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_40S

MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_DATA

MEM_40S

MEM_A_CAS_L

MEM_CMD

MEM_A_CMD

MEM_40S_VDD

MEM_DATA

MEM_A_DQ<31..24>

MEM_A_DQ_BYTE3 MEM_40S

MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_40S_VDD

MEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_DATA

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_40S

MEM_A_CMD

MEM_A_RAS_L

MEM_CMD

MEM_40S_VDD

MEM_A_DQ<39..32>

MEM_DATA

MEM_A_DQ_BYTE4 MEM_40S

MEM_A_DQ<47..40>

MEM_DATA

MEM_A_DQ_BYTE5 MEM_40S

MEM_B_DQ_BYTE5

MEM_B_DQ<47..40>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE4 MEM_40S

MEM_B_DQ<39..32>

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_40S

MEM_DATA

MEM_B_CMD

MEM_B_WE_L

MEM_CMD

MEM_40S_VDD

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_B_DM<0>

MEM_40S

MEM_DATA

MEM_B_CMD

MEM_B_BA<2..0>

MEM_CMD

MEM_40S_VDD

MEM_B_DQS6

MEM_B_DQS_N<6>

MEM_70D MEM_DQS

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_70D MEM_DQS

MEM_B_DQ_BYTE7

MEM_B_DM<7>

MEM_40S

MEM_DATA

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_70D MEM_DQS

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_70D MEM_DQS

MEM_B_DQS4

MEM_70D

MEM_B_DQS_N<4>

MEM_DQS

MEM_B_DQS5

MEM_B_DQS_N<5>

MEM_70D MEM_DQS

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_70D MEM_DQS

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_70D MEM_DQS

MEM_B_DQS2

MEM_B_DQS_N<2>

MEM_70D MEM_DQS

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_70D MEM_DQS

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_70D MEM_DQS

MEM_B_DQS1

MEM_B_DQS_N<1>

MEM_70D MEM_DQS

MEM_B_DQS0

MEM_B_DQS_N<0>

MEM_70D MEM_DQS

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_70D MEM_DQS

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_70D MEM_DQS

MEM_B_DQ_BYTE6

MEM_B_DM<6>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DM<5>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DM<3>

MEM_40S

MEM_DATA

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_70D MEM_DQS

MEM_B_DQ_BYTE4

MEM_B_DM<4>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DM<2>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DM<1>

MEM_40S

MEM_DATA

MEM_B_ODT<3..0>

MEM_B_CNTL

MEM_CTRL

MEM_40S_VDD

MEM_B_CS_L<3..0>

MEM_B_CNTL

MEM_CTRL

MEM_40S_VDD

MEM_70D_VDD

MEM_CLK

MEM_B_CLK_N<5..0>

MEM_B_CLK

MEM_70D_VDD

MEM_B_CLK_P<5..0>

MEM_CLK

MEM_B_CLK

MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP

MCP_MEM_COMP_VDD

MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP

MCP_MEM_COMP_GND

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_DQSMEM_70D

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_DQSMEM_70D

MEM_B_CMD

MEM_B_CAS_L

MEM_CMD

MEM_40S_VDD

MEM_B_CMD

MEM_B_RAS_L

MEM_CMD

MEM_40S_VDD

MEM_B_CMD

MEM_CMD

MEM_B_A<14..0>

MEM_40S_VDD

MEM_A_CMD

MEM_CMD

MEM_A_A<14..0>

MEM_40S_VDD

MEM_DATA

MEM_A_DM<7>

MEM_A_DQ_BYTE7 MEM_40S

MEM_A_DQS0

MEM_DQSMEM_70D

MEM_A_DQS_P<0>

MEM_70D

MEM_A_DQS6

MEM_A_DQS_N<6>

MEM_DQS

28

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

27

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

28

27

27

28

28

28

27

27

27

27

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

15

16

16

15

15

15

15

15

15

15

15

15

Preliminary

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

PCI-Express

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

Analog Video Signal Constraints

R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

- 75-ohm from output of three-pole filter to connector (if possible).

SATA Interface Constraints

- 37.5-ohm from MCP to first termination resistor.

CRT signal single-ended impedence varies by location:

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

- 50-ohm from first to second termination resistor.

Digital Video Signal Constraints

=4X_DIELECTRIC

TOP,BOTTOM

?

PCIE

* ?

CLK_PCIE

20 MIL

MCP Constraints 1

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

051-7656

31

123102

=90_OHM_DIFF

=90_OHM_DIFF

*

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

PCIE_90D

* ?

MCP_PEX_COMP

8 MIL

* ?

=3X_DIELECTRIC

PCIE

=STANDARD

CRT_2CRT

?*

=4:1_SPACING

CRT

* ?

?

LVDS

=4x_DIELECTRIC

TOP,BOTTOM

TOP,BOTTOM

=4x_DIELECTRIC

?

DISPLAYPORT

?*

CRT_2CLK

50 MIL

=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFFCLK_PCIE_100D

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

*

=100_OHM_DIFF

DP_100D

=100_OHM_DIFF=100_OHM_DIFF

SATA

?

TOP,BOTTOM

=3x_DIELECTRIC

SATA_100D

=100_OHM_DIFF

=100_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

* ?

SATA_TERMP

8 MIL

CRT_2CRT

*

CRTCRT

CRT_50S

=50_OHM_SE

=STANDARD

*

=STANDARD

=50_OHM_SE=50_OHM_SE =50_OHM_SE

?*

LVDS

=3x_DIELECTRIC

=3x_DIELECTRIC

* ?

DISPLAYPORT

?

=4x_DIELECTRIC

SATA

*

* ?

CRT_2SWITCHER

250 MIL

CRT_SYNC

?*

16 MIL

MCP_DAC_COMP

* ?

=2:1_SPACING

*

Y 20 MIL 20 MIL =STANDARD

=STANDARD =STANDARD

MCP_DV_COMP

DP_IG_AUX_CH_N

DP_100D

DP_AUX_CH

DISPLAYPORT

DP_100D

DP_ML

DP_IG_ML_N<3..0>

DISPLAYPORT

TMDS_IG_TXD

DP_100D

DISPLAYPORT

TMDS_IG_TXD_P<2..0>

PCIE

PCIE_EXCARD_R2D_C_N

PCIE_90D

PCIE_EXCARD_R2D_C_P

PCIE_90D

PCIE

PCIE_EXCARD_R2D

PCIE

PCIE_EXCARD_D2R_N

PCIE_90D

CLK_PCIE

MCP_PE0_REFCLK

CLK_PCIE_100D

PEG_CLK100M_P

CLK_PCIE_100D

PEG_CLK100M_N

CLK_PCIE

MCP_IFPAB_RSET

MCP_IFPAB_RSET

MCP_DV_COMP

MCP_IFPAB_VPROBE

MCP_IFPAB_VPROBE

SATA_100D

SATA

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SATA

SATA_100D

SATA_HDD_R2D

SATA_100D

SATA

SATA_HDD_R2D_N

SATA_HDD_R2D_P

SATA_100D

SATA

SATA_100D

SATA

SATA_HDD_D2R_P

SATA_HDD_D2R

SATA_100D

SATA

SATA_HDD_D2R_C_P

SATA_100D

SATA

SATA_HDD_D2R_N

SATA_100D

SATA

SATA_ODD_R2D_C_P

SATA_ODD_R2D

SATA_100D

SATA

SATA_HDD_D2R_C_N

SATA_100D

SATA

SATA_ODD_R2D_C_N

SATA

SATA_ODD_R2D_N

SATA_100D

SATA

SATA_ODD_R2D_P

SATA_100D

SATA

SATA_ODD_D2R_N

SATA_100D

SATA_ODD_D2R_P

SATA

SATA_100D

SATA_ODD_D2R

SATA

SATA_ODD_D2R_C_P

SATA_100D

SATA_100D

SATA

SATA_ODD_D2R_C_N

MCP_SATA_TERMP

SATA_TERMP

MCP_SATA_TERMP

DISPLAYPORT

DP_100D

DP_AUX_CH

DP_IG_AUX_CH_P

LVDS_IG_B_CLK_N

LVDS

LVDS_100D

LVDS_IG_B_CLK

LVDS

LVDS_100D

LVDS_IG_B_DATA3

LVDS_IG_B_DATA_P<3>

LVDS

LVDS_100D

LVDS_IG_B_DATA3

LVDS_IG_B_DATA_N<3>

LVDS

LVDS_100D

LVDS_IG_A_DATA3

LVDS_IG_A_DATA_P<3>

LVDS

LVDS_100D

LVDS_IG_A_DATA3

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA

LVDS_100D

LVDS

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_A_DATA

LVDS_100D

LVDS

LVDS_IG_A_DATA_P<2..0>

LVDS_100D

LVDS_IG_B_DATA

LVDS

LVDS_IG_B_DATA_N<2..0>

LVDS

LVDS_100D

LVDS_IG_B_DATA

LVDS_IG_B_DATA_P<2..0>

LVDS_IG_B_CLK_P

LVDS

LVDS_100D

LVDS_IG_B_CLK

CLK_PCIE_100D

PCIE_CLK100M_MINI_N

CLK_PCIE

PCIE

PCIE_90D

PCIE_FW_R2D_C_N

PCIE

PCIE_90D

PEG_D2R_C_N<15..0>

MCP_DV_COMP

MCP_HDMI_VPROBE

MCP_HDMI_VPROBE

CRT_SYNC

CRT_IG_HSYNC

CRT_50S

CRT_SYNC

PCIE

PCIE_90D

PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P

PCIE

PCIE_MINI_R2D

PCIE_90D

LVDS

LVDS_100D

LVDS_IG_A_CLK

LVDS_IG_A_CLK_N

MCP_HDMI_RSET

MCP_DV_COMP

MCP_HDMI_RSET

DP_100D

DP_ML

DISPLAYPORT

DP_IG_ML_P<3..0>

TMDS_IG_TXD

TMDS_IG_TXD_N<2..0>

DISPLAYPORT

DP_100D

MCP_DAC_VREF MCP_DAC_COMP

MCP_TV_DAC_VREF

MCP_DAC_RSET MCP_DAC_COMP

MCP_TV_DAC_RSET

CRT_SYNC

CRT_50S

CRT_SYNC

CRT_IG_VSYNC

CRT_50S

CRT

CRT_BLUE

CRT_IG_B_COMP_PB

CRT

CRT_IG_G_Y_Y

CRT_50S

CRT_GREEN

CRT_50S

CRT

CRT_IG_R_C_PR

CRT_RED

PCIE

PCIE_MINI_R2D_C_N

PCIE_90D

PCIE_FW_R2D_P

PCIE

PCIE_90D

PCIE_FW_D2R_C_P

PCIE

PCIE_90D

PCIE_CLK100M_MINI_P

CLK_PCIE

MCP_PE1_REFCLK

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_FW_P

MCP_PE2_REFCLK

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_FW_N

PCIE

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R

PCIE_90D

PCIE_FW_D2R_C_N

PCIE

PCIE_90D

PCIE_FW_D2R_N

PCIE

PCIE_90D

PCIE_FW_D2R

PCIE_FW_D2R_P

PCIE

PCIE_90D

PCIE_FW_R2D

PCIE_FW_R2D_C_P

PCIE

PCIE_90D

PCIE_FW_R2D_N

PCIE

PCIE_90D

PEG_R2D_N<15..0>

PCIE

PCIE_90D

PEG_D2R

PCIE

PCIE_90D

PEG_D2R_P<15..0>

PCIE

PCIE_90D

PEG_D2R_C_P<15..0>

PCIE

PEG_R2D

PCIE_90D

PEG_R2D_C_P<15..0>

PCIE

PCIE_90D

PCIE_MINI_R2D_P

PEG_R2D_C_N<15..0>

PCIE

PCIE_90D

PCIE

PCIE_MINI_D2R_P

PCIE_MINI_D2R

PCIE_90D

PCIE

PCIE_90D

PCIE_MINI_D2R_N

PEG_D2R_N<15..0>

PCIE

PCIE_90D

PEG_R2D_P<15..0>

PCIE

PCIE_90D

PCIE_EXCARD_R2D_N

PCIE_90D

PCIE

PCIE

PCIE_90D

PCIE_EXCARD_R2D_P

PCIE_CLK100M_EXCARD_P

MCP_PE3_REFCLK

CLK_PCIE_100D

CLK_PCIE

MCP_PEX_CLK_COMP

MCP_PEX_COMP

MCP_PEX_CLK_COMP

TMDS_IG_TXC DISPLAYPORT

DP_100D

TMDS_IG_TXC_N

LVDS

LVDS_100D

LVDS_IG_A_CLK

LVDS_IG_A_CLK_P

TMDS_IG_TXC

DP_100D

DISPLAYPORT

TMDS_IG_TXC_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_EXCARD_N

31

31

30

30

81

81

31

31

17

69

69

24

24

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

38

81

18

18

18

18

18

84

84

84

84

18

30

35

24

24

30

30

84

24

81

24

24

24

24

24

24

30

30

35

35

17

35

35

35

69

69

30

69

17

17

69

31

31

31

84

31

18

9

17

17

7

17

17

18

18

20

20

7

7

20

7

20

20

7

20

7

7

20

20

7

7

20

18

9

9

9

9

9

18

18

18

18

9

17

17

69

18

18

7

17

18

18

9

18

18

18

18

18

18

17

35

35

17

17

17

7

35

17

17

17

35

69

9

69

9

7

9

7

7

9

69

7

7

17

17

18

17

Preliminary

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

PCI Bus Constraints

LPC Bus Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

USB 2.0 Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

SPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

SPI Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SIO Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

HD Audio Interface Constraints

SMBus Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

=STANDARD

=55_OHM_SE

*

CLK_PCI_55S

=STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

CLK_LPC_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD=STANDARD

6 MIL

LPC

?*

CLK_LPC

8 MIL

* ?

MCP Constraints 2

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

103 123

31

051-7656

=55_OHM_SE

SPI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

*

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

HDA_55S

=STANDARD =STANDARD

*

*

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

CLK_SLOW_55S

=STANDARD=STANDARD

=55_OHM_SE

PCI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD

*

=STANDARD

8 MIL

CLK_PCI

?*

=STANDARDPCI

?*

SMB

* ?

=2x_DIELECTRIC

=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

LPC_55S

*

=STANDARD

=4x_DIELECTRIC

TOP,BOTTOM

?

USB

8 MIL

?

CLK_SLOW

*

MCP_HDA_COMP

8 MIL

* ?

?*

HDA

=2x_DIELECTRIC

=55_OHM_SE=55_OHM_SE=55_OHM_SE

SMB_55S

=STANDARD=STANDARD

*

=55_OHM_SE

=90_OHM_DIFF

*

=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

USB_90D

*

=STANDARD=STANDARD

=STANDARD =STANDARD

8 MIL8 MIL

MCP_USB_RBIAS

=2x_DIELECTRIC

USB

?*

8 MIL

?

SPI

*

SMB_55S

SMB

SMBUS_MCP_1_DATA

SMBUS_MCP_1_DATA

SMB_55S

SMB

SMBUS_MCP_1_CLK

SMBUS_MCP_1_CLK

MCP_HDA_PULLDN_COMP

MCP_HDA_PULLDN_COMP

MCP_HDA_COMP

HDA_55S

HDA

HDA_SDOUT_R

PCI_55S

PCI_AD<24>

PCI

PCI_AD24

PCI_C_BE_L

PCI_55S

PCI_C_BE_L<3..0>

PCI

PCI_55S

PCI_PAR

PCI_AD

PCI

PCI_55S

PCI_IRDY_L

PCI

PCI_CNTL

PCI_55S

PCI_PERR_L

PCI

PCI_CNTL

PCI_STOP_L

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_SERR_L

PCI

PCI_CNTL

PCI_TRDY_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI_REQ0_L

PCI

PCI_REQ0_L

PCI_55S

PCI_FRAME_L

PCI_CNTL

PCI

PCI_55S

PCI_REQ1_L

PCI_REQ1_L

PCI

PCI_GNT0_L

PCI_55S

PCI_GNT0_L

PCI

PCI_55S

PCI_GNT1_L

PCI_GNT1_L

PCI

PCI_INTX_L

PCI_55S

PCI_INTX_L

PCI

PCI_55S

PCI_INTW_L

PCI

PCI_INTW_L

PCI_55S

PCI_INTZ_L

PCI

PCI_INTZ_L

PCI

PCI_55S

PCI_INTY_L

PCI_INTY_L

CLK_PCI

CLK_PCI_55S

PCI_CLK33M_MCP

CLK_PCI

CLK_PCI_55S

PCI_CLK33M_MCP_R

MCP_PCI_CLK2

LPC_FRAME_L

LPC_FRAME_L

LPC

LPC_55S

LPC_AD<3..0>

LPC

LPC_AD

LPC_55S

LPC_RESET_L

LPC

LPC_RESET_L

LPC_55S

CLK_LPC

CLK_LPC_55S

LPC_CLK33M_SMC_R

MCP_LPC_CLK0

CLK_LPC

CLK_LPC_55S

LPC_CLK33M_SMC

USB_EXTA

USB

USB_90D

USB_EXTA_P

CLK_LPC

CLK_LPC_55S

LPC_CLK33M_LPCPLUS

USB

USB_EXTA_N

USB_90D

USB

USB_90D

USB_EXTA_MUXED_P

USB_90D

USB

USB_EXTA_MUXED_N

USB

USB_90D

USB_MINI

USB_MINI_P
USB_MINI_N

USB

USB_90D

USB_EXTD

USB

USB_EXTD_P

USB_90D

USB

USB_EXTD_N

USB_90D
USB_90D

USB_CAMERA

USB

USB_CAMERA_P

USB

USB_90D

USB_CAMERA_N

USB

USB_90D

USB_BT

USB_BT_P

USB

USB_90D

USB_BT_N

USB

USB_90D

USB_TPAD_P

USB_TPAD

USB

USB_90D

USB_TPAD_N
USB_IR_P

USB

USB_90D

USB_IR

USB

USB_90D

USB_IR_N

USB_90D

USB

USB_EXTB

USB_EXTB_P

USB_90D

USB

USB_EXTB_N

USB_90D

USB

USB_EXCARD

USB_EXCARD_P

HDA_55S

HDA_SYNC

HDA

HDA_SYNC

HDA_55S

HDA

HDA_BIT_CLK_R

HDA_RST_L

HDA_55S

HDA

HDA_RST_R_L

HDA_55S

HDA

HDA_SYNC_R

HDA_55S

HDA

HDA_SDIN_CODEC

PCI_55S

PCI

MCP_DEBUG

MCP_DEBUG<7..0>

PCI_55S

PCI

PCI_AD

PCI_AD<23..8>

PCI_DEVSEL_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_AD<31..25>

PCI_AD

SPI_55SSPI_CLK

SPI

SPI_CLK_R

SPI_55S

SPI_CLK

SPI

PM_CLK32K_SUSCLK_R

CLK_SLOW

CLK_SLOW_55S

MCP_SUS_CLK

SMB_55S

SMBUS_MCP_0_CLK

SMBUS_MCP_0_CLK

SMB

HDA_55S

HDA

HDA_BIT_CLK

HDA_BIT_CLK

SMB_55S

SMBUS_MCP_0_DATA

SMBUS_MCP_0_DATA

SMB

MCP_USB_RBIAS MCP_USB_RBIAS

MCP_USB_RBIAS_GND

USB_90D

USB

USB_EXCARD_N

HDA_55S

HDA_SDOUT

HDA

HDA_SDOUT

HDA_55S

HDA

HDA_SDIN0

HDA_SDIN0

HDA_55S

HDA

HDA_RST_L

SPI_CS0_L

SPI_55S

SPI

USB

USB_EXTC_N

USB_90D

USB_90D

USB

USB_EXTC

USB_EXTC_P

SPI_CS0_R_L

SPI_CS0 SPI_55S

SPI

SPI_MISO_R

SPI_55S

SPI

SPI_MISO

SPI_55S

SPI_MISO

SPI

SPI_55S

SPI

SPI_MOSI

SPI_55S

SPI

SPI_MOSI

SPI_MOSI_R

PM_CLK32K_SUSCLK

CLK_SLOW_55S

CLK_SLOW

84

84

43

43

44

44

41

41

84

43

21

21

98

98

44

44

19

19

25

25

41

39

25

39

20

20

20

20

30

30

30

30

49

49

40

40

39

39

31

53

19

43

25

13

21

13

31

53

53

53

96

96

43

43

43

41

21

21

21

21

19

19

19

19

7

7

19

19

25

20

7

20

9

9

9

9

20

20

20

20

20

20

20

20

20

20

20

21

21

21

21

13

21

52

21

7

9

7

20

20

21

21

21

20

20

21

52

21

52

21

25

Preliminary

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

88E1116R (Ethernet PHY) Constraints

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

MCP RGMII (Ethernet) Constraints

SPACING

25 MIL

?*

ENET_MDI

ENET_MDI_100D

=100_OHM_DIFF

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=55_OHM_SE

ENET_MII_55S

=STANDARD =STANDARD

*

7.5 MIL

=STANDARD

=STANDARD =STANDARD

7.5 MIL

=STANDARD

*

MCP_MII_COMP

=3:1_SPACING

* ?

MCP_BUF0_CLK

?*

ENET_MII

12 MIL

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

Ethernet Constraints

104 123

31

051-7656

MCP_MII_COMP

MCP_MII_COMP_VDD

MCP_MII_COMP

ENET_RXD_R<3..0>

ENET_MII_55S

ENET_MII

ENET_CLK125M_RXCLK

ENET_MII_55S

ENET_MII

ENET_RXCLK

ENET_CLK125M_RXCLK_R

ENET_MII

ENET_MII_55S

MCP_CLK25M_BUF0

MCP_CLK25M_BUF0_R

MCP_BUF0_CLKENET_MII_55S

MCP_MII_COMP

MCP_MII_COMP_GND

MCP_MII_COMP

ENET_RXD

ENET_RX_CTRL

ENET_MII_55S

ENET_MII

ENET_CLK125M_TXCLK

ENET_MII_55S

ENET_MII

ENET_TXCLK

ENET_TXD<3..1>

ENET_MII

ENET_MII_55S

ENET_TXD

ENET_TXD<0>

ENET_MII_55S

ENET_MII

ENET_TXD0

ENET_MII

ENET_MII_55S

ENET_RESET_L

ENET_MII_55S

ENET_MII

ENET_TX_CTRL

ENET_TXD

ENET_MDI

ENET_MDI_N<3..0>

ENET_MDI_100D

ENET_MDI

ENET_MDI_P<3..0>

ENET_MDI_100D

ENET_MDI

ENET_RXD_STRAP

ENET_RXD<3..1>

ENET_MII_55S

ENET_MII

ENET_RXD

ENET_RXD<0>

ENET_MII_55S

ENET_MII

ENET_MII

ENET_MDIO

ENET_MDIO

ENET_MII_55S

ENET_PWRDWN_L

ENET_PWRDWN_L

ENET_MII_55S

ENET_MII

ENET_MDC

ENET_MDC ENET_MII

ENET_MII_55S

ENET_INTR_L

ENET_MII_55S

ENET_INTR_L

ENET_MII

RTL8211_CLK25M_CKXTAL1

MCP_BUF0_CLKENET_MII_55S

32

33

32

32

32

32

32

32

34

34

32

32

32

32

33

18

32

18

32

18

18

18

18

18

18

18

18

32

32

18

18

18

18

32

Preliminary

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Port 2 Not Used

PHYSICAL

FireWire Interface Constraints

NET_TYPE

SPACING

FireWire Net Properties

ELECTRICAL_CONSTRAINT_SET

=110_OHM_DIFF=110_OHM_DIFF

FW_110D

=110_OHM_DIFF=110_OHM_DIFF

=110_OHM_DIFF

*

=110_OHM_DIFF

*

=3:1_SPACING

?

FW_TP

051-7656

31

123105

FireWire Constraints

SYNC_MASTER=M98_MLB

SYNC_DATE=04/01/2008

FW_P0_TPA

FW_P0_TPA_P

FW_110D

FW_TP

FW_P0_TPA

FW_P0_TPA_N

FW_TP

FW_110D

FW_P0_TPB

FW_P0_TPB_P

FW_TP

FW_110D

FW_P0_TPB

FW_P0_TPB_N

FW_TP

FW_110D

FW_P1_TPB

FW_TP

FW_110D

FW_P1_TPB_N

FW_P1_TPB

FW_TP

FW_110D

FW_P1_TPB_P

FW_P1_TPA

FW_TP

FW_110D

FW_P1_TPA_N

FW_P1_TPA

FW_TP

FW_110D

FW_P1_TPA_P

37

37

37

37

37

37

37

37

35

35

35

35

35

35

35

35

Preliminary

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

=STANDARD =STANDARD

0.1 MM 0.1 MM

*

=STANDARD=STANDARD

1TO1_DIFFPAIR

051-7656

31

123106

SMC Constraints

SYNC_MASTER=M98_MLB

SYNC_DATE=04/01/2008

CHGR_CSO_N

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSI_N

1TO1_DIFFPAIR

SMB_55S

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SCL

SMB

SMB_55S

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SDA

SMB

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SDA

SMB

SMB_55S

SMB

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMB_55S

SMBUS_SMC_MGMT_SCL

SMB

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SCL

SMB_55S

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SDA

SMB

SMB_55S

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SCL

SMB

SMB_55S

SMB

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SDA

SMB_55S

SMB

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SCL

SMB_55S

44

44

44

44

60

60

60

60

7

7

7

44

44

7

44

44

44

44

Preliminary

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SPACING

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

GDDR3 Frame Buffer Signal Constraints

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

MUXGFX Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

GDDR3 FB A/B Net Properties

NET_TYPE

PHYSICAL

SPACING

NET_TYPE

SPACING

Digital Video Signal Constraints

From T18 MXM:

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

GDDR3 FB C/D Net Properties

PHYSICAL

(CK505_DOT96)

G96 Net Properties

ELECTRICAL_CONSTRAINT_SET

I138

I139

I142

I143

I144

I145

I148

I149

I152

I153

I155

I157

I158

I159

I160

I161

I182

I183

I184

I185

I190

I191

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I203

I204 I205

?

TOP,BOTTOM

DISPLAYPORT

=4x_DIELECTRIC

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF

DP_100D

=100_OHM_DIFF

=3x_DIELECTRIC

LVDS

* ?

=2.5:1_SPACING

*

GDDR3_DQS

?

*

GDDR3_CMD

?

=2.5:1_SPACING

GDDR3_CLK

?

*

=2.5:1_SPACING

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF

DISPLAYPORT

?*

=3x_DIELECTRIC

TOP,BOTTOM

?

LVDS

=4x_DIELECTRIC

GPU (G96) Constraints

SYNC_MASTER=M98_MLB

051-7656

31

123107

SYNC_DATE=05/01/2008

=80_OHM_DIFF=80_OHM_DIFF

*

=80_OHM_DIFF

GDDR3_80D

=80_OHM_DIFF

=80_OHM_DIFF

0.095 MM

=STANDARD=STANDARD

*

GDDR3_40SE =40_OHM_SE

=40_OHM_SE

=40_OHM_SE

0.095 MM

12.7 MM

=40_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

GDDR3_40R55SE

*

0.095 MM

GDDR3_DATA

*

?

=2.5:1_SPACING

GDDR3_DATA

FB_B_DQM_L<1>

FB_C_DQM1

GDDR3_40SE

FB_B_WDQS<5>

GDDR3_DQS

FB_D_WDQS1 GDDR3_40SE

FB_B_CS1_L

FB_CD_CS1 GDDR3_CMD

GDDR3_40R55SE

GDDR3_40R55SE

FB_CD_CS0 GDDR3_CMD

FB_B_CS0_L

FB_A_DQ_BYTE0

GDDR3_DATA

FB_A_DQ<7..0>

GDDR3_40SE

FB_A_DQ_BYTE3

GDDR3_DATA

FB_A_DQ<31..24>

GDDR3_40SE

FB_A_DQM1

FB_A_DQM_L<1>

GDDR3_DATAGDDR3_40SE

FB_A_WDQS<4>

FB_B_WDQS0

GDDR3_DQS

GDDR3_40SE

GDDR3_DQS

FB_B_WDQS1

FB_A_WDQS<5>

GDDR3_40SE

FB_B_WDQS2

GDDR3_DQS

FB_A_WDQS<6>

GDDR3_40SE

FB_B_WDQS3

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS<7>

FB_B_RDQS0 GDDR3_40SE

FB_A_RDQS<4>

GDDR3_DQS

FB_B_RDQS1

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS<5>

FB_B_DQM2

GDDR3_DATA

FB_A_DQM_L<6>

GDDR3_40SE

GDDR3_DATAGDDR3_40SE

FB_B_DQM3

FB_A_DQM_L<7>

FB_A_CS1_L

FB_AB_CS1

GDDR3_40R55SE

GDDR3_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_A_CS0_L

FB_AB_CS0

FB_A_DQ<55..48>

FB_B_DQ_BYTE2

GDDR3_40SE GDDR3_DATA

FB_B_DQM0

GDDR3_DATA

FB_A_DQM_L<4>

GDDR3_40SE

GDDR3_40R55SE

FB_AB_CMD_PD

FB_A_DRAM_RST

GDDR3_CMD

FB_A_LMA<5..2>

FB_A_CMD

GDDR3_40SE

GDDR3_CMD

GDDR3_CMDFB_CD_CMD_PD

FB_B_DRAM_RST

GDDR3_40R55SE

GDDR3_CMD

FB_C_CMD

FB_B_LMA<5..2>

GDDR3_40SE

FB_B_UMA<5..2>

FB_D_CMD

GDDR3_CMD

GDDR3_40SE

FB_B_WDQS<0>

GDDR3_DQS

FB_C_WDQS0 GDDR3_40SE

FB_B_WDQS<1>

GDDR3_DQS

FB_C_WDQS1 GDDR3_40SE

FB_B_WDQS<2>

GDDR3_DQS

FB_C_WDQS2 GDDR3_40SE

FB_B_WDQS<3>

GDDR3_DQS

FB_C_WDQS3 GDDR3_40SE

FB_B_RDQS<0>

GDDR3_DQS

FB_C_RDQS0 GDDR3_40SE

GDDR3_DQS

FB_C_RDQS1

FB_B_RDQS<1>

GDDR3_40SE

GDDR3_DQS

FB_C_RDQS2

FB_B_RDQS<2>

GDDR3_40SE

FB_C_DQ_BYTE0

FB_B_DQ<7..0>

GDDR3_DATAGDDR3_40SE

GDDR3_DATA

FB_C_DQ_BYTE2

FB_B_DQ<23..16>

GDDR3_40SE

GDDR3_DATA

FB_C_DQ_BYTE3

FB_B_DQ<31..24>

GDDR3_40SE

GDDR3_DATA

FB_C_DQM2

FB_B_DQM_L<2>

GDDR3_40SE

GDDR3_DATA

FB_C_DQM3

FB_B_DQM_L<3>

GDDR3_40SE

FB_B_WDQS<4>

GDDR3_DQS

FB_D_WDQS0 GDDR3_40SE

FB_B_WDQS<6>

GDDR3_DQS

FB_D_WDQS2 GDDR3_40SE

FB_B_WDQS<7>

GDDR3_DQS

FB_D_WDQS3 GDDR3_40SE

GDDR3_DQS

FB_B_RDQS<5>

FB_D_RDQS1 GDDR3_40SE

FB_B_RDQS<6>

GDDR3_DQS

FB_D_RDQS2 GDDR3_40SE

FB_D_RDQS3

FB_B_RDQS<7>

GDDR3_DQS

GDDR3_40SE

FB_D_DQ_BYTE0

GDDR3_DATA

FB_B_DQ<39..32>

GDDR3_40SE

GDDR3_DATA

FB_B_DQ<47..40>

FB_D_DQ_BYTE1

GDDR3_40SE

FB_D_DQM0

FB_B_DQM_L<4>

GDDR3_40SE GDDR3_DATA

GDDR3_DATA

FB_B_DQM_L<5>

GDDR3_40SE

FB_D_DQM1

GDDR3_DATAGDDR3_40SE

FB_B_DQM_L<6>

FB_D_DQM2

GDDR3_DATA

FB_B_DQM_L<7>

GDDR3_40SE

FB_D_DQM3

DP_100D

DISPLAYPORT

DP_EG_ML_P<3..0>DP_EG_ML_P<3..0>

DP_ML

DISPLAYPORT

DP_EG_ML_N<3..0>

DP_ML

DP_100D

DP_EG_ML_N<3..0>

DP_100D

DP_EG_AUX_CH_P

DISPLAYPORT

DP_AUX_CH

DISPLAYPORT

DP_AUX_CH

DP_100D

DP_EG_AUX_CH_N

DISPLAYPORT

DP_100D

DP_EG_AUX_CH_C_P

DISPLAYPORT

DP_100D

DP_EG_AUX_CH_C_N

LVDS_EG_B_DATA_N<2..0>

LVDS

LVDS_100D

LVDS_EG_B_DATA

LVDS_EG_B_DATA_P<2..0>

LVDS

LVDS_100D

LVDS_EG_B_DATA

FB_B_DQM1

GDDR3_40SE GDDR3_DATA

FB_A_DQM_L<5>

FB_B_DQ_BYTE1

FB_A_DQ<47..40>

GDDR3_DATAGDDR3_40SE

FB_B_DQ_BYTE0

GDDR3_DATA

FB_A_DQ<39..32>

GDDR3_40SE

GDDR3_40SE

FB_A_DQM2

FB_A_DQM_L<2>

GDDR3_DATA

FB_A_DQM0

GDDR3_DATAGDDR3_40SE

FB_A_DQM_L<0>

GDDR3_DATA

FB_A_DQ_BYTE2

GDDR3_40SE

FB_A_DQ<23..16>

GDDR3_DATA

FB_A_DQ<15..8>

GDDR3_40SE

FB_A_DQ_BYTE1

FB_A_RDQS<3>

FB_A_RDQS3

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS3 GDDR3_40SE

GDDR3_DQS

FB_A_WDQS<3>

FB_A_WDQS2

FB_A_WDQS<2>

GDDR3_DQS

GDDR3_40SE

FB_A_WDQS1 GDDR3_40SE

GDDR3_DQS

FB_A_WDQS<1>

FB_B_CMD

FB_A_UMA<5..2>

GDDR3_40SE

GDDR3_CMD

FB_AB_CMD_PD GDDR3_CMD

GDDR3_40R55SE

FB_A_CKE

LVDS_B_DATA

LVDS_B_DATA_P<2..0>

LVDS

LVDS_100D

LVDS_CONN_B_CLK_F_P

LVDS_100D

LVDS

LVDS_CONN_A_DATA_N<2..0>

LVDS

LVDS_100D

LVDS_CONN_B_CLK_P

LVDS

LVDS_100D

LVDS_CONN_B_CLK_F_N

LVDS

LVDS_100D

LVDS_CONN_A_DATA_P<2..0>

LVDS

LVDS_100D

LVDS_CONN_B_CLK_N

LVDS

LVDS_100D

DP_ML_N<3..0>

DP_100D

DISPLAYPORT

DP_ML_N<3..0>

DP_100D

DISPLAYPORT

DP_ML_CONN_N<3..0>

DP_100D

DISPLAYPORT

DP_ML

DP_ML_CONN_P<3..0>

DP_ML_C_P<3..0>

DP_100D

DISPLAYPORT

DP_ML

DP_ML_C_N<3..0>

DP_100D

DISPLAYPORT

DP_ML_P<3..0>DP_ML_P<3..0>

DISPLAYPORT

DP_ML

DP_100D

LVDS_CONN_B_DATA_P<2..0>

LVDS

LVDS_100D

LVDS_CONN_B_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_CONN_A_CLK_N

LVDS_100D

LVDS

LVDS_CONN_A_CLK_P

LVDS

LVDS_100D

LVDS_CONN_A_CLK_F_P

LVDS

LVDS_100D

LVDS_CONN_A_CLK_F_N

LVDS

LVDS_100D

DP_100D

DP_AUX_CH

DISPLAYPORT

DP_AUX_CH_C_N

DISPLAYPORT

DP_AUX_CH

DP_100D

DP_AUX_CH_C_P

CLK_SLOW

CK505_CLK27MSS

CLK_SLOW_55S

GPU_CLK27M_SS

LVDS

LVDS_EG_A_CLK_P

LVDS_EG_A_CLK

LVDS_100D

LVDS

LVDS_EG_A_CLK_N

LVDS_EG_A_CLK

LVDS_100D

CLK_SLOW_55S

GPU_CLK27M

CLK_SLOW

GDDR3_DQS

FB_A_RDQS<7>

GDDR3_40SEFB_B_RDQS3

FB_B_RDQS2

GDDR3_DQS

FB_A_RDQS<6>

GDDR3_40SE

GDDR3_80D

FB_C_CLK_P

FB_B_CLK_P<0>

GDDR3_CLK

FB_B_RDQS<3>

FB_C_RDQS3

GDDR3_DQS

GDDR3_40SE

FB_B_RDQS<4>

GDDR3_DQS

FB_D_RDQS0 GDDR3_40SE

FB_A_RDQS<2>

FB_A_RDQS2

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS1

GDDR3_DQS

GDDR3_40SE

FB_A_RDQS<1>

FB_A_RDQS0

FB_A_RDQS<0>

GDDR3_DQS

GDDR3_40SE

FB_AB_CMD

FB_A_WE_L

GDDR3_40R55SE

GDDR3_CMD

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_A_RAS_L

GDDR3_CMDFB_AB_CMD

GDDR3_40R55SE

FB_A_BA<2..0>

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_A_MA<12..6>

FB_A_CLK_P

GDDR3_80D GDDR3_CLK

FB_A_CLK_P<0>

GDDR3_CLKGDDR3_80D

FB_A_CLK_N<0>

FB_A_WDQS0 GDDR3_40SE

FB_A_WDQS<0>

GDDR3_DQS

GDDR3_80D

FB_B_CLK_N<0>

GDDR3_CLK

GDDR3_80D

FB_D_CLK_P

FB_B_CLK_P<1>

GDDR3_CLK

GDDR3_80D

FB_B_CLK_N<1>

GDDR3_CLK

GDDR3_40R55SE

FB_CD_CMD

FB_B_MA<1..0>

GDDR3_CMD

GDDR3_40R55SE

FB_CD_CMD

FB_B_BA<2..0>

GDDR3_CMD

FB_B_MA<12..6>

GDDR3_40R55SE

FB_CD_CMD GDDR3_CMD

GDDR3_40R55SE

FB_CD_CMD

FB_B_RAS_L

GDDR3_CMD

GDDR3_40R55SE

FB_CD_CMD

FB_B_WE_L

GDDR3_CMD

GDDR3_40R55SE

FB_CD_CMD

FB_B_CAS_L

GDDR3_CMD

FB_CD_CMD_PD

GDDR3_40R55SE

FB_B_CKE

GDDR3_CMD

GDDR3_DATA

FB_C_DQ_BYTE1

FB_B_DQ<15..8>

GDDR3_40SE

GDDR3_DATA

FB_B_DQM_L<0>

FB_C_DQM0

GDDR3_40SE

GDDR3_40SE GDDR3_DATA

FB_B_DQ<63..56>

FB_D_DQ_BYTE3

GDDR3_40SE GDDR3_DATA

FB_B_DQ<55..48>

FB_D_DQ_BYTE2

GDDR3_CLK

FB_B_CLK_P

GDDR3_80D

FB_A_CLK_P<1>

FB_A_MA<1..0>

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMD

GDDR3_80D

FB_A_CLK_N<1>

GDDR3_CLK

FB_A_CAS_L

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMD

LVDS_100D

LVDS_A_CLK_P

LVDS

LVDS_A_CLK

LVDS

LVDS_B_CLK_N

LVDS_100D

LVDS_B_CLK

LVDS_100D

LVDS_B_DATA

LVDS_B_DATA_N<2..0>

LVDS

LVDS

LVDS_100D

LVDS_A_DATA

LVDS_A_DATA_N<2..0>

LVDS_100D

LVDSLVDS_A_DATA

LVDS_A_DATA_P<2..0>

LVDS

LVDS_A_CLK_N

LVDS_A_CLK

LVDS_100D

LVDS_100D

LVDS

LVDS_B_CLK

LVDS_B_CLK_P

LVDS_EG_A_DATA_N<2..0>

LVDS

LVDS_100D

LVDS_EG_A_DATA

LVDS_EG_A_DATA_P<2..0>

LVDS

LVDS_100D

LVDS_EG_A_DATA

FB_B_DQ_BYTE3

FB_A_DQ<63..56>

GDDR3_40SE GDDR3_DATA

GDDR3_40SE

FB_A_DQM3

GDDR3_DATA

FB_A_DQM_L<3>

79

79

79

80

80

80

80

80 79

79

79

79

80

80

80

80

80

80

79

80

80

73

72

72

79

79

79

79

79

79

79

79

79

72

79

79

79

80

80

80

80

80

80

80

80

80

80

73

73

73

80

80

80

80

80

80

80

80

73

73

80

80

80

80

79

72

72

79

79

72

72

79

79

79

79

79

79

84

81

81

81

81

79

79

80

80

80

79

79

79

79

79

79

79

79

79

79

80

80

80

80

73

73

80

80

73

80

73

80

73

73

79

79

79

79

84

84

84

84

84

72

79

73

73

80

71

71

71

72

72

72

72

72

72

72

72

72

79

72

71

72

72

72

73

73

73

73

73

73

73

73

73

73

71

71

71

73

73

73

73

73

73

73

73

71

71

73

73

73

73

81

81

81

81

84

84

72

71

71

72

72

71

71

72

72

72

72

72

72

81

78

78

81

78

78

81

82

82

78

78

81

81

78

78

82

82

84

84

72

72

73

73

73

72

72

72

72

72

72

72

72

72

72

73

73

73

73

71

71

73

73

71

73

71

73

71

71

72

72

72

72

84

84

81

81

81

84

81

76

84

71

72

71

71

71

7

7

7

71

71

71

71

71

71

71

71

71

71

71

7

71

71

71

71

71

71

71

71

71

71

71

71

71

7

7

7

71

71

71

71

71

71

71

71

7

7

71

71

71

71

76

76

76

76

81

81

76

76

71

7

7

71

71

7

7

71

71

71

71

71

71

7

7

7

78

7

7

78

81

82

82

82

82

81

7

7

78

78

7

7

81

81

75

76

76

75

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

71

7

7

71

71

7

71

7

71

7

7

71

71

71

71

81

81

7

7

7

81

7

7

76

7

71

Preliminary

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

ELECTRICAL_CONSTRAINT_SET

M99 Specific Net Properties

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

Memory Constraint Relaxations

(USB_EXTA)

PHYSICAL

NET_TYPE

SPACINGSPACING

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

M99 Specific Net Properties

(USB_CAMERA)

(USB_CAMERA)

(USB_EXTD)

(USB_EXTD)

(USB_EXTA)

(USB_EXTA)

(USB_EXTA)

Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island.
Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes).

Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

FLASH MEMORY BUS CONSTRAINTS

I124

I125

I126

I127

I128

I129

I130

I131

I132

I133

I134

I135

I136

I137

I138

I139

I140

I141

I142

I143

I144

I145

I146

I147

I148

I149

I150

I151

I152

I153

I154

I155

I156

I157

I158

I159

I160

I165

I166

I167

I168

I169

I170

I171

I172

I173

I174

I175

I176

I177

I178

I179

I180

I181

I182

I183

I184

I185

I186

I187

I188

I189

I190

I191

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I202

I206

I207

I209

I210

I211

I212

I223

I224

I225

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235

I236

I237

I238

I239

I240

I241

I242

I243

I244

I245

I246

I247

I248

MEM_70D_VDD

N

ISL3,ISL10

*

GND

GND_P2MM

MEM_CMD

*

GND

GND_P2MM

CPU_VCCSENSE

GND_P2MM

*

GND

ENET_MDI

FSB_DSTB GND_P2MM

*

FSB_DSTB

FLSH_55S

=55_OHM_SE

*

=55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE

=STANDARD

BGA

SATA_100D

100_DIFF_BGA

100_DIFF_BGA

BGA

DP_100D

BGA

100_DIFF_BGA

LVDS_100D

0.20 MM

GND_P2MM

*

1000

GND

*

CLK_FSB

GND_P2MM

GND_P2MMCLK_PCIE

GND

*

PCIE

GND

GND_P2MM

*

GND

LVDS

GND_P2MM

*

6.35 MMMEM_70D

0.127 MM

BOTTOM

*

SB_POWER PWR_P2MM

SATA

PWR_P2MMCLK_PCIE

*

SB_POWER

GND

*

USB

GND_P2MM

GND_P2MM

SATA

GND

*

25 MILS

ENETCONN

?

*

051-7656

31

123108

SYNC_MASTER=M98_MLB

SYNC_DATE=04/01/2008

Project Specific Constraints

=55_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE

=1:1_DIFFPAIR

SENSE_1TO1_55S

GND

CPU_GTLREF

*

GND_P2MM

GND

GND_P2MMCPU_COMP

*

250 MIL0.25 MM

*

MCP_DV_COMP

0.20 MM

PWR_P2MM

1000

*

=55_OHM_SE =55_OHM_SE

=1:1_DIFFPAIR=1:1_DIFFPAIR

THERM_1TO1_55S

*

=55_OHM_SE

=1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR

*

DIFFPAIR

=2:1_SPACING

SENSE

?

*

=2:1_SPACING

AUDIO

?

*

=2:1_SPACING

*

THERM

?

=STANDARD

*

?

GND

*

GND

GND_P2MM

MEM_CLK

GND

*

GND_P2MMMEM_CTRL

*

GND

GND_P2MMMEM_DATA

GND

*

MEM_DQS

GND_P2MM

100 MIL

BOTTOM

0.23 MM

CPU_27P4S

SB_POWER

*

USB

PWR_P2MM

=STANDARD

?

*

PP1V8_MEM

0.09 MM 100 MIL

*

MEM_40S

MEM_40S_VDD

*

0.09 MM 100 MIL

100 MIL0.09 MMMEM_70D

*

100 MIL0.09 MM

MEM_70D_VDD

*

100 MIL

*

0.09 MM

PCIE_90D

500 MILUSB_90D

TOP 0.1 MM

500 MIL

MCP_DV_COMP

TOP 0.1 MM

500 MIL

MCP_MEM_COMP

TOP 0.1 MM

500 MIL

MCP_MII_COMP

TOP 0.1 MM

500 MIL

TOP

MCP_USB_RBIAS

0.1 MM

ISL4,ISL9

MEM_70D

ISL3,ISL10

N

MEM_40S_VDD

MEM_40S

ISL4,ISL9

GND

GND

MCP_PE4_REFCLK

CLK_PCIE_100D

PCIE_CLK100M_FC_P

CLK_PCIE

PCIE_CLK100M_FC_N

CLK_PCIE_100D

CLK_PCIE

PCIE_FC_R2D

PCIE_FC_R2D_C_P

PCIEPCIE_90D

PCIE_FC_R2D_C_N

PCIEPCIE_90D

PCIE_90D PCIE

PCIE_FC_D2R

PCIE_FC_D2R_P

DIFFPAIR

AUDIO

SPKRAMP_L1_OUT_N

DIFFPAIR

AUDIO

SPKRAMP_L2_OUT_N

USB

USB_90D

USB_LT3_P

NF_CLE

FLSH_55S

ASIC_CNTRLMEM2

NF_ALE

FLSH_55S

ASIC_CNTRLMEM2

NF_CE0_L

FLSH_55S

ASIC_CNTRLMEM2

NF_RE0_L

FLSH_55S

ASIC_CNTRLMEM2

NF_WE0_L

ASIC_CNTRLMEM2

FLSH_55S

USB

USB_LT3_N

USB_90D

DIFFPAIR

SPKRAMP_R1_OUT_N

AUDIO

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_EXCARD_CONN_N

PCIEPCIE_90D

PCIE_FC_R2D_N

PCIE

PCIE_FC_R2D_P

PCIE_90D

DIFFPAIR

AUDIO

SPKRAMP_R1_OUT_P

SPK_OUT

1TO1_DIFFPAIR

CHGR_CSO_R_P

1TO1_DIFFPAIR

CHGR_CSO_R_N

USB2_EXTA_MUXED_P

USB

USB_90D

USB

USB2_LT1_P

USB_90D

USB2_LT1_N

USB

USB_90D

USB_CAMERA_CONN_P

USB

USB_90D

USB_90D

USB

USB_CAMERA_CONN_N

USB_90D

USB

CONN_USB2_BT_P

USB

USB_90D

USB2_EXCARD_CONN_P

USB_90D

USB

USB2_EXCARD_CONN_N

DP_IG_AUX_CH_C_P

DP_100D

DISPLAYPORT

DP_IG_AUX_CH_C_N

DISPLAYPORT

DP_100D

CONN_TPAD_USB_P

USB

USB_90D

CONN_TPAD_USB_N

USB

USB_90D

USB

USB_90D

CONN_USB2_BT_N

ASIC_CNTRLMEM2

FLSH_55S

NF_WE0_L_R

ASIC_CNTRLMEM2

FLSH_55S

NF_RE0_L_R

FLSH_55S

NF_CE1_L_R

ASIC_CNTRLMEM2

DIFFPAIR

AUDIO

SPKRAMP_R2_OUT_N

DIFFPAIR

SPK_OUT

AUDIO

SPKRAMP_R2_OUT_P

SENSE

DDRISNS_P

SENSE_DIFFPAIR SENSE_1TO1_55S

DDRISNS_N

SENSE

SENSE_1TO1_55S

P1V8GPU_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

P1V8GPU_N
ISNS_CPU_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

DDRISNS_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

GPUISENS_N

SENSE

SENSE_1TO1_55S

USB2_EXTA_MUXED_N

USB

USB_90D

USB

USB_90D

USB_LT2_P

SENSE_1TO1_55S

DDRISNS_R_N

SENSE

SENSE

ISNS_CPU_N

SENSE_1TO1_55S

1TO1_DIFFPAIR

CHGR_CSI_R_P

1TO1_DIFFPAIR

CHGR_CSI_R_N

SENSE_1TO1_55S

GPUISENS_P

SENSE

SENSE_DIFFPAIR

CLK_PCIE_100D

PCIE_CLK100M_MINI_CONN_P

CLK_PCIE

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_CONN_N

CPU_THERMD_N

THERM

THERM_1TO1_55S

1V05CPU_N

SENSE

SENSE_1TO1_55S

SENSE_1TO1_55S

1V05CPUISNS_R_N

SENSE

THERM_1TO1_55S

THERM

MCPTHMSNS_D_N

MCPTHMSNS_D_DP

THERM

THERM_1TO1_55S

MCPTHMSNS_D_P

SENSE_1TO1_55S

P1V8GPUISNS_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

P1V8GPUISNS_N

SENSE

SENSE_DIFFPAIR

P1V8GPUISNS_P

SENSE_1TO1_55S

SENSE

SB_POWER

PP1V5_S0

PP3V3_S0

SB_POWER

NF_RE0_L

FLSH_55S

ASIC_CNTRLMEM3

NF_CE1_L

FLSH_55S

ASIC_CNTRLMEM2

FLSH_55S

NF_CE0_L_R

ASIC_CNTRLMEM2

ASIC_CNTRLMEM2

FLSH_55S

NF_CLE_R

ASIC_CNTRLMEM3

NF_ALE

FLSH_55S

ASIC_CNTRLMEM3

NF_CE0_L

FLSH_55S

ASIC_CNTRLMEM3

NF_CE1_L

FLSH_55S

FLSH_55S

NF_CLE_R

ASIC_CNTRLMEM1

FLSH_55S

NF_ALE_R

ASIC_CNTRLMEM1

FLSH_55S

NF_CE0_L_R

ASIC_CNTRLMEM1

NF_CE1_L_R

FLSH_55S

ASIC_CNTRLMEM1

FLSH_55S

NF_RE0_L_R

ASIC_CNTRLMEM1

FLSH_55S

NF_WE0_L_R

ASIC_CNTRLMEM1

SENSE_1TO1_55S

P1V8GPUISNS_R_N

SENSE

SENSE_DIFFPAIR

1V05CPUISNS_R_P

SENSE_1TO1_55S

SENSE

THERM_1TO1_55S

THERM

MCP_THERMD_DP

MCP_THMDIODE_P

THERM

MCP_THMDIODE_N

THERM_1TO1_55S

FLSH_55S

NF_WE0_L

ASIC_CNTRLMEM3

ASIC_CNTRLMEM3

NF_CLE

FLSH_55S

ASIC_CNTRLMEM2

FLSH_55S

NF_ALE_R

SENSE_1TO1_55S

SENSE

1V05CPU_P

SENSE_DIFFPAIR

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_EXCARD_CONN_P

PCIE_90D PCIE

PCIE_FC_D2R_N

USB

USB_90D

USB_LT2_N

DIFFPAIR

SPK_OUT

AUDIO

SPKRAMP_L1_OUT_P

DIFFPAIR

SPK_OUT

AUDIO

SPKRAMP_L2_OUT_P

SB_POWER

PP3V3_S5

SATA_100D

SATA_ODD_R2D_UF_P

SATA

SATA_100D

SATA_HDD_R2D_UF_N

SATA

GPUTHMSNS_D_N

THERM_1TO1_55S

THERM

GPU_THERMD_DP

THERM_1TO1_55S

GPU_TDIODE_P

THERM

GPUTHMSNS_D_P

THERM_1TO1_55S

THERM

GPUTHMSNS_D_DP

CPU_THERMD_P

CPU_THERMD_DP

THERM

THERM_1TO1_55S

CPUTHMSNS_D2_N

THERM_1TO1_55S

THERM

MCPCOREISNS_N

SENSE_1TO1_55S

SENSE

SATA_100D

SATA_HDD_R2D_UF_P

SATA

SATA_HDD_D2R_UF_N

SATA_100D

SATA

SATA

SATA_100D

SATA_HDD_D2R_UF_P

SATA_ODD_D2R_UF_N

SATA

SATA_100D

SATA

SATA_100D

SATA_ODD_D2R_UF_P

SATA_100D

SATA_ODD_R2D_UF_N

SATA

ENETCONN

ENET_MDI_100D

ENETCONN_P<3..0>

ENET_MDI_100D

ENETCONN_N<3..0>

ENETCONN

MCPCOREISNS_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

THERM_1TO1_55S

GPU_TDIODE_N

THERM

CPUTHMSNS_D2_DP

CPUTHMSNS_D2_P

THERM_1TO1_55S

THERM

USB

USB_EXTC_P

USB_90D

DIFFPAIR

AUDIO

SPKRAMP_LFE_OUT_N

DIFFPAIR

AUDIO

SPK_OUT

SPKRAMP_LFE_OUT_P

USB_90D

USB

USB_EXTC_N

57

57

57

57

57

57

9

57

57

98

57

57

98

56

56

98

98

56

31

56

60

60

39

39

30

30

30

31

31

30

56

56

39

30

30

47

65

47

47

8

47

47

65

31

39

56

56

8

75

47

64

64

75

91

56

56

91

7

7

7

96

96

96

96

96

7

7

7

7

45

45

39

7

7

7

7

7

7

7

81

81

7

96

96

96

7

7

46

46

46

46

45

46

46

39

7

46

45

60

60

46

7

7

10

46

46

7

7

46

7

96

96

96

96

96

96

96

96

96

96

96

96

96

46

46

21

21

96

96

96

46

7

7

7

7

7

38

38

47

47

47

10

47

46

38

38

38

38

38

38

34

34

46

47

47

20

7

7

20

Preliminary

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE
ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE

ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

M99 Board-Specific Spacing & Physical Constraints

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

NOTE:From T18 MLB, changed to reflect M99 stackup.

0.15 MM

*

?

1.5:1_SPACING

2X_DIELECTRIC

* ?

0.140 MM

=STANDARD

1:1_DIFFPAIR

* Y

0.1 MM0.1 MM

=STANDARD=STANDARD

0.095 MM

70_OHM_DIFF

Y

TOP,BOTTOM

0.150 MM0.150 MM

0.170 MM

0.170 MM

ISL2,ISL11

70_OHM_DIFF

Y

0.170 MM

0.150 MM 0.150 MM

=STANDARD

=STANDARD

N

70_OHM_DIFF

*

=STANDARD

=STANDARD

=STANDARD

40_OHM_SE

Y

0.165 MM

TOP,BOTTOM

0.095 MM

0.110 MM 0.095 MM

50_OHM_SE

TOP,BOTTOM

Y

*

?

0.18 MM

1.8:1_SPACING

Y

55_OHM_SE

=STANDARD

*

=STANDARD

=STANDARD

0.076 MM 0.076 MM

10 MM

Y

STANDARD

=DEFAULT=DEFAULT

*

=DEFAULT =DEFAULT

?

=DEFAULT

*

STANDARD

*

BGA_P1MM

?

=DEFAULT

?

BGA_P2MM =DEFAULT

*

0.220 MM

Y

90_OHM_DIFF

ISL9,ISL10

0.220 MM

0.102 MM0.102 MM

0.230 MM0.230 MM

0.115 MM

Y

ISL2,ISL11

90_OHM_DIFF

0.115 MM

0.095 MM

0.230 MM 0.230 MM

Y

TOP,BOTTOM

90_OHM_DIFF

0.115 MM

=STANDARD

=STANDARD =STANDARD

N*

100_OHM_DIFF

=STANDARD=STANDARD

0.080 MM

0.200 MM 0.200 MM

100_OHM_DIFF

ISL3,ISL4

Y

0.080 MM

0.080 MM

ISL9,ISL10

100_OHM_DIFF

Y

0.200 MM

0.080 MM

0.200 MM

4:1_SPACING

0.4 MM

*

?

ISL9,ISL10

0.330 MM

110_OHM_DIFF

0.077 MM

Y

0.330 MM

0.077 MM

0.077 MM

0.330 MM0.330 MM

Y

110_OHM_DIFF

ISL2,ISL11

0.077 MM

0.330 MM0.330 MM

0.077 MM0.077 MM

TOP,BOTTOM

110_OHM_DIFF

Y

100_DIFF_BGA

0.075 MM

ISL9,ISL10

Y

0.125 MM0.125 MM

0.075 MM

100_DIFF_BGA

0.075 MM

Y

ISL3,ISL4

0.125 MM0.125 MM

0.075 MM

100_DIFF_BGA

=100_OHM_DIFF

=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

BGA_P2MM

*

CLK_PCIE

BGA

90_OHM_DIFF

* N

=STANDARD

=STANDARD =STANDARD =STANDARD

=STANDARD

0.220 MM0.220 MM

0.102 MM

Y

90_OHM_DIFF

ISL3,ISL4

0.102 MM

**

BGA_P1MM

BGA

BGA

FSB_DSTB BGA_P3MMFSB_DSTB

BGA

BGA_P2MM

*

CLK_SLOW

MEM_CLK

BGA_P2MM

*

BGA

?

DEFAULT

*

0.1 MM

BGA_P3MM

?

*

=DEFAULT

*

0.2 MM

?

2:1_SPACING

0.25 MM

*

?

2.5:1_SPACING

0.3 MM

3:1_SPACING

*

?

CLK_FSB

*

BGA_P2MM

BGA

0.089 MM

0.220 MM0.220 MM

ISL2,ISL11

100_OHM_DIFF

Y

0.089 MM

0.220 MM 0.220 MM

Y

100_OHM_DIFF

TOP,BOTTOM

0.089 MM0.089 MM

Y

0.330 MM

110_OHM_DIFF

0.077 MM

ISL3,ISL4

0.077 MM

0.330 MM

N

=STANDARD

=STANDARD

*

110_OHM_DIFF

=STANDARD=STANDARD

=STANDARD

TOP,BOTTOM

Y

27P4_OHM_SE

0.310 MM 0.095 MM

=STANDARD

* Y

27P4_OHM_SE

=STANDARD

0.250 MM 0.250 MM

=STANDARD

?*

3X_DIELECTRIC

0.210 MM

?

4X_DIELECTRIC

*

0.280 MM

?*

0.350 MM

5X_DIELECTRIC

ISL9,ISL10

70_OHM_DIFF

Y

0.175 MM0.175 MM

0.160 MM 0.160 MM

Y

40_OHM_SE

*

=STANDARD

=STANDARD

0.135 MM

=STANDARD

0.135 MM

80_OHM_DIFF

ISL3,ISL4

Y

0.125 MM 0.125 MM

0.180 MM 0.180 MM

ISL9,ISL10

Y

80_OHM_DIFF

0.125 MM 0.125 MM

0.180 MM0.180 MM

Y

ISL2,ISL11

80_OHM_DIFF

0.140 MM

0.190 MM 0.190 MM

0.140 MM

0.095 MM

Y

TOP,BOTTOM

80_OHM_DIFF

0.140 MM

0.190 MM0.190 MM

=STANDARD

=STANDARD

=STANDARD

*

80_OHM_DIFF

=STANDARD

N

=STANDARD

ISL3,ISL4

70_OHM_DIFF

Y

0.175 MM 0.175 MM

0.160 MM 0.160 MM

0.090 MM

=STANDARD50_OHM_SE

Y*

0.090 MM

=STANDARD =STANDARD

0.090 MM

Y

TOP,BOTTOM

55_OHM_SE

0.090 MM

10 MM

=50_OHM_SE

0 MM

DEFAULT

0 MM

* Y

=50_OHM_SE

NO_TYPE,BGA

MM

15.5.1

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

PCB Rule Definitions

SYNC_DATE=04/01/2008

SYNC_MASTER=M98_MLB

051-7656

31

123109

Preliminary

OUT

BI

SYM_VER-1

BI

IOIONC

GND

VBUS

NC

TPAD

OUT1

GND

OC*

EN*

IN2

IN1

OUT2

OUT3

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LEFT USB PORT C

ENABLE TIED LOW SO INPUT POWER SOURCE MUST BE S3!!!

PLACE LC320 AND LC325 AT CONNECTOR PIN

Port Power Switch

6.3V

20%
X5R

10UF

603

CC380

1

2

0.1UF

20%
10V
CERM
402

CC381

1

2

20

20%

603

X5R

6.3V

10UF

CC385

1

2

CASE-B2-SM

6.3V
POLY-TANT

100UF

20%

CRITICAL

CC386

1

2

20 91 96

CRITICAL

DLP11S

90-OHM-100MA

LC320

1 2

34

16V
402

CERM

0.01uF

20%

CC325

1

2

20 91 96

CRITICAL

0603

FERR-220-OHM-2.5A

LC325

1 2

SLP1210N6

RCLAMP0502N

CRITICAL

DC320

1

5 42 3

6

OMIT

6

USB

CRITICAL

F-RT-TH-M97-3

JC320

1

2

3

4

5

7

8

TPS2068

MSOP

CRITICAL

UC380

4

1

2

3

5

6

7

8

9

JC320

1

CONN,RCPT,USB,HB,4P

514-0638 CRITICAL

PROJECT SPECIFIC CONNS

123 123

31

051-7656

SYNC_MASTER=N/A

SYNC_DATE=N/A

USB_EXTC_N

PP5V_S3_RTUSB_C_ILIM

VOLTAGE=5V

MIN_NECK_WIDTH=0.375 mm

MIN_LINE_WIDTH=0.5 mm

=PP5V_S3_RTUSB

USB_EXTC_P

USB_EXTC_OC_L

PP5V_S3_RTUSB_C_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB_LT3_P

USB_LT3_N

39

96

96

8

7

7

7

Preliminary