Texas Instruments CD74HCT4094M96, CD74HCT4094E, CD74HC4094PWR, CD74HC4094PW, CD74HC4094NSR Datasheet
...
CD74HC4094,
/
j
[ /Title
(CD74H
C4094,
CD74H
CT4094
)
Sub-
ect
(High
Speed
CMOS
Logic 8-
Data sheet acquired from Harris Semiconductor
SCHS211
November 1997
8-Stage Shift and Store Bus Register, Three-State
Features
• Buffered Inputs
• Separate Serial Outputs Synchronous to Both
Positive and Negative Clock Edges For Cascading
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
at VCC = 5V
o
CD74HCT4094
High Speed CMOS Logic
C to 125oC
CC
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
≤ 1µA at VOL, V
l
Pinout
CD74HC4094, CD74HCT4094
(PDIP, SOIC)
TOP VIEW
STROBE
DAT A
CP
Q
Q
Q
Q
GND
1
2
3
4
0
5
1
6
2
7
3
8
16
15
14
13
12
11
10
9
V
OE
Q
Q
Q
Q
QS
QS
OH
CC
4
5
6
7
2
1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number 1779.1
CD74HC4094, CD74HCT4094
Description
The Harris CD74HC4094 and CD74HCT4094 are 8-stage
serial shift registers having a storage latch associated with
each stage for strobing data from the serial input to parallel
buffered three-state outputs. The parallel outputs may be
connected directly to common bus lines. Data is shifted on
positive clock transitions. The data in each shift register
stage is transferred to the storage register when the Strobe
input is high. Data in the storage register appears at the
outputs whenever the Output-Enable signal is high.
Two serial outputs are available for cascading a number of
these devices. Data is available at the QS
serial output
1
terminal on positive clock edges to allow for high-speed
operation in cascaded system in which the clock rise time is
fast. The same serial information, available at the QS
terminal on the next negative clock edge, provides a means
Functional Diagram
2
3
8-STAGE
SHIFT
REGISTER
DAT A
CP
for cascading these devices when the clock rise time is slow.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC4094E -55 to 125 16 Ld PDIP E16.3
CD74HCT4094E -55 to 125 16 Ld PDIP E16.3
CD74HC4094M -55 to 125 16 Ld SOIC M16.15
CD74HCT4094M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering,use the entire part number. Add the suffix 96 to
2
obtain the variant in the tape and reel.
2. Waferordie for thispartnumber is availablewhich meets allelectrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
9
QS
1
10
QS
2
PKG.
NO.
STROBE
OE
1
15
8-BIT
STORAGE
REGISTER
THREE-
STATE
OUTPUT
4
Q
0
5
Q
1
6
Q
2
7
Q
3
14
Q
4
13
Q
5
12
Q
GND = 8
6
11
V
= 16
Q
CC
7
TRUTH TABLE
INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS
CP OE STR D Q
0
Q
n
QS1 (NOTE 4) QS
2
↑ L X X Z Z Q’6 NC
↓ LXXZZNCQ
7
↑H L X NC NC Q’6 NC
↑ HHLLQ
-1 Q’6 NC
n
2
CD74HC4094, CD74HCT4094
TRUTH TABLE
INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS
CP OE STR D Q
↑ HHHHQ
↓ H H H NCNCNCQ
NOTES:
3. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, NC = No charge, Z = High Impedance Off-state,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
4. At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS1 output.
0
Q
n
-1 Q’6 NC
n
QS1 (NOTE 4) QS
2
7
3
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