Texas Instruments CD74HCT4094M96, CD74HCT4094E, CD74HC4094PWR, CD74HC4094PW, CD74HC4094NSR Datasheet

CD74HC4094,

/
j

[ /Title
(CD74H
C4094,
CD74H
CT4094
)

Sub-

ect
(High
Speed
CMOS
Logic 8-

Data sheet acquired from Harris Semiconductor
SCHS211

November 1997

8-Stage Shift and Store Bus Register, Three-State

Features

• Buffered Inputs

• Separate Serial Outputs Synchronous to Both
Positive and Negative Clock Edges For Cascading

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

o

CD74HCT4094

High Speed CMOS Logic

C to 125oC

CC

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

Pinout

CD74HC4094, CD74HCT4094

(PDIP, SOIC)

TOP VIEW

STROBE

DAT A

CP

Q
Q
Q
Q

GND

1
2
3
4

0

5

1

6

2

7

3

8

16
15
14
13
12
11
10

9

V
OE
Q
Q
Q
Q
QS
QS

OH

CC

4
5
6
7

2
1

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1779.1

CD74HC4094, CD74HCT4094

Description

The Harris CD74HC4094 and CD74HCT4094 are 8-stage
serial shift registers having a storage latch associated with
each stage for strobing data from the serial input to parallel
buffered three-state outputs. The parallel outputs may be
connected directly to common bus lines. Data is shifted on
positive clock transitions. The data in each shift register
stage is transferred to the storage register when the Strobe
input is high. Data in the storage register appears at the
outputs whenever the Output-Enable signal is high.

Two serial outputs are available for cascading a number of
these devices. Data is available at the QS

serial output

1

terminal on positive clock edges to allow for high-speed
operation in cascaded system in which the clock rise time is
fast. The same serial information, available at the QS
terminal on the next negative clock edge, provides a means

Functional Diagram

2

3

8-STAGE

SHIFT

REGISTER

DAT A

CP

for cascading these devices when the clock rise time is slow.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC4094E -55 to 125 16 Ld PDIP E16.3
CD74HCT4094E -55 to 125 16 Ld PDIP E16.3
CD74HC4094M -55 to 125 16 Ld SOIC M16.15
CD74HCT4094M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering,use the entire part number. Add the suffix 96 to

2

obtain the variant in the tape and reel.

2. Waferordie for thispartnumber is availablewhich meets allelec­trical specifications. Please contact your local sales office or
Harris customer service for ordering information.

9

QS

1

10

QS

2

PKG.

NO.

STROBE

OE

1

15

8-BIT

STORAGE

REGISTER

THREE-

STATE

OUTPUT

4

Q

0

5

Q

1

6

Q

2

7

Q

3

14

Q

4

13

Q

5

12

Q

GND = 8

6

11

V

= 16

Q

CC

7

TRUTH TABLE

INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS

CP OE STR D Q

0

Q

n

QS1 (NOTE 4) QS

2

↑ L X X Z Z Q’6 NC
↓ LXXZZNCQ

7

↑H L X NC NC Q’6 NC
↑ HHLLQ

-1 Q’6 NC

n

2

CD74HC4094, CD74HCT4094

TRUTH TABLE

INPUTS PARALLEL OUTPUTS SERIAL OUTPUTS

CP OE STR D Q

↑ HHHHQ
↓ H H H NCNCNCQ

NOTES:

3. H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, NC = No charge, Z = High Impedance Off-state,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.

4. At the positive clock edge the information in the seventh register stage is transferred to the 8th register stage and QS1 output.

0

Q

n

-1 Q’6 NC

n

QS1 (NOTE 4) QS

2

7

3

Logic Diagram

CD74HC4094, CD74HCT4094

FF

FF

FF

FF

FF

9

1

QS

8

L

10

2

QS

7

Q

11

7

L

CP CPQD

6

Q

7

6

5

4

3

6

L

5

L

4

L

3

L

2

L

12

5

Q

13

4

Q

14

3

Q

7

2

Q

6

2

FF

1

FF

O

FF

DQ

2

DAT A

CPCP

1

Q

5

1

L

0

Q

4

Q

O

L

OE OE

STR STR

3

CP

1

STR

15

OE

4

CD74HC4094, CD74HCT4094

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

5. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

5

CD74HC4094, CD74HCT4094

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

(Note)

Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

D 0.4

CP, OE 1.5

STR 1.0

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

Prerequisite for Switching Specifications

CHARACTERISTIC SYMBOL VCC (V)

HC TYPES

CP Pulse Width t

STR Pulse Width t

W

WH

2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
6 14 - 17 - 20 - ns
2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
6 14 - 17 - 20 - ns

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSMIN MAX MIN MAX MIN MAX

6

CD74HC4094, CD74HCT4094

Prerequisite for Switching Specifications (Continued)

25

CHARACTERISTIC SYMBOL V

Data Set-up Time t

SU

Data Hold Time t

STR Set-up Time t

SU

STR Hold Time t

Maximum CP Frequency f

CL (MAX)

HCT TYPES

CP Pulse Width t
STR Pulse Width t
Data Set-up Time t

W

WH

SU

Data Hold Time t
STR Set-up Time t

SU

STR Hold Time t
Maximum CP Frequency f

CL (MAX)

H

H

H

H

(V)

CC

2 50 - 65 - 75 - ns

4.5 10 - 13 - 15 - ns
6 9 -11-13-ns
2 3-3-3-ns

4.5 3 - 3 - 3 - ns
6 3-3-3-ns
2 100 - 125 - 150 - ns

4.5 20 - 25 - 30 - ns
6 17 - 21 - 26 - ns
2 0-0-0-ns

4.5 0 - 0 - 0 - ns
6 0-0-0-ns
2 6-5-4-MHz

4.5 30 - 24 - 20 - MHz
6 35 - 28 - 24 - MHz

4.5 16 - 20 - 24 - ns

4.5 16 - 20 - 24 - ns

4.5 10 - 13 - 15 - ns

4.5 4 - 4 - 4 - ns

4.5 20 - 25 - 30 - ns

4.5 0 - 0 - 0 - ns

4.5 30 - 24 - 20 - MHz

o

C -40oC TO 85oC -55oC TO 125oC

UNITSMIN MAX MIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay Time
(Figure 1)

CP to QS

CP to QS

CP to Q

STR to Q

1

2

n

n

t

PLH,

t

PHL

t

PLH,

t

PHL

t

PLH,

t

PHL

t

PLH,

t

PHL

, tf = 6ns

r

o

C -40oC TO 85oC -55oCTO125oC

TEST

CONDITIONS

V

CC

(V)

25

CL= 50pF 2 - - 150 - 190 - 225 ns

4.5 - - 30 - 38 - 45 ns

C

=15pF 5 - 12 - - - - - ns

L

C

= 50pF 6 - - 26 - 33 - 38 ns

L

CL= 50pF 2 - - 135 - 170 - 205 ns

4.5 - - 27 - 34 - 41 ns

C

=15pF 5 - 11 - - - - - ns

L

C

= 50pF 6 - - 23 - 29 - 35 ns

L

CL= 50pF 2 - - 195 - 245 - 295 ns

4.5 - - 39 - 49 - 59 ns
5 - 16 - - - - - ns
6 - - 33 - 42 - 50 ns

CL= 50pF 2 - - 180 - 225 - 270 ns

4.5 - - 36 - 45 - 54 ns
6 - - 31 - 38 - 46 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

7

Switching Specifications Input t

PARAMETER SYMBOL

Output Enable to Q

Output Disable to Q

n

n

Output Transition Time t

Output Disabling Time t
Maximum CP Frequency f
Input Capacitance C
Power Dissipation Capacitance

(Notes 6, 7)
Three-State Output

Capacitance

HCT TYPES

Propagation Delay Time
(Figure 1)

CP to QS
CP to QS

CP to Q

STR to Q

Output Enable to Q
Output Disable to Q

1
2

n

n

n

n

Output Transition Time t
Output Disabling Time t
Maximum CP Frequency f
Input Capacitance C
Power Dissipation Capacitance

(Notes 6, 7)
Three-State Output

Capacitance

NOTES:

6. C

is used to determine the dynamic power consumption, per register.

PD

7. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

t

PZH,tPZLCL

t

PHZ,tPLZCL

TLH,tTHLCL

PHZ,tPLZCL

MAX

C

C

t

PLH,

t

PHL

t

PLH,

t

PHL

t

PLH,

t

PHL

t

PLH,

t

PHL

t

PZH,tPZLCL

t

PHZ,tPLZCL
TLH,tTHLCL
PHZ,tPLZCL

MAX

C

C

, tf = 6ns (Continued)

r

o

C -40oC TO 85oC -55oCTO125oC

TEST

CONDITIONS

V

CC

(V)

25

= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns
6 - - 30 - 37 - 45 ns

= 50pF 2 - - 125 - 155 - 190 ns

4.5 - - 25 - 31 - 38 ns
6 - - 21 - 26 - 32 ns

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

=15pF 5 - 10 - - - - - ns
CL=15pF 5 - 60 - - - - - MHz
CL= 50pF - - - 10 - 10 - 10 pF

IN

CL=15pF 5 - 90 - - - - - pF

PD

CL= 50pF - - - 15 - 15 - 15 pF

O

CL= 50pF 4.5 - - 39 - - - - ns

CL=15pF 5 - 16 - - - - - ns
CL= 50pF 4.5 - - 36 - - - - ns
C

=15pF 5 - 15 - - - - - ns

L

CL= 50pF 4.5 - - 43 - - - - ns
C

=15pF 5 - 18 - - - - - ns

L

CL= 50pF 4.5 - - 39 - - - - ns

= 50pF 4.5 - - 35 - - - - ns

= 50pF 4.5 - - 35 - - - - ns

= 50pF 4.5 - - 15 - - - - ns

=15pF 5 - 14 - - - - - ns
CL=15pF 5 - 60 - - - - - MHz
CL= 50pF - - - 10 - 10 - 10 pF

IN

CL=15pF 5 - 110 - - - - - pF

PD

CL= 50pF - - - 15 - 15 - 15 pF

O

UNITSMIN TYP MAX MIN MAX MIN MAX

8

Test Circuits and Waveforms

6ns 6ns

CLOCK

t

SU

CD74HC4094, CD74HCT4094

90%

V

S

10%

t

H

t

W

V

S

t

W

INPUT LEVEL

GND

INPUT LEVEL

SERIAL IN

CLOCK

STROBE

Q

n

SERIAL IN

, QS

Q

n

QS

t

PLH,tPHL

t

PLH

V

S

1

2

t

PLH

V

S

t

PHL

FIGURE 1. DATA PROPAGATION DELAYS, SET-UP AND HOLD TIMES

INPUT LEVEL

GND

t

V

S

SU

t

H

INPUT LEVEL

V

S

GND

t

W

V

S

V

S

V

OH

V

OL

V

OH

V

OL

= 6ns

t

r

OE 90%

t

PLZ

OUTPUT

LOW TO OFF

t

PHZ

OUTPUT

HIGH TO OFF

OUTPUTS

CONNECTED

GND

V

OH

V

OL

t

PHL

V

OH

V

OL

10%

90%

OUTPUTS

DISCONNECTED

t

= 6ns

f

V

t

t

S

10%

PZL

V

S

PZH

V

S

OUTPUTS
CONNECTED

FIGURE 2. STROBE PROPAGATIONDELAYS AND SET-UP

AND HOLD TIMES

FIGURE 3. ENABLE AND DISABLE TIMES

9

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