Texas Instruments CD74HCT4060M96, CD74HCT4060M, CD74HCT4060E, CD74HC4060M96, CD74HC4060M Datasheet

CD74HC4060,

/
j

[ /Title
(CD74
HC406
0,
CD74
HCT40

60)
Sub­ect

(High
Speed
CMOS

Data sheet acquired from Harris Semiconductor
SCHS207

February 1998

Features

• Onboard Oscillator

• Common Reset

• Negative Edge Clocking

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

= 50MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

o

CD74HCT4060

High Speed CMOS Logic

14-Stage Binary Counter with Oscillator

C to 125oC

CC

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

Pinout

CD74HC4060, CD74HCT4060

(PDIP, SOIC)

TOP VIEW

Q12
Q13
Q14

Q6
Q5
Q7
Q4

GND

1
2
3
4
5
6
7
8

16
15
14
13
12
11
10

9

V

CC

Q10
Q8
Q9
MR

φI
φO
φO

OH

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1654.1

CD74HC4060, CD74HCT4060

Description

The Harris CD74HC4060 and CD74HCT4060 each consist
of an oscillator section and 14 ripple-carry binary counter
stages. The oscillator configuration allows design of either
RC or crystal oscillator circuits. A Master Reset input is
provided which resets the counter to the all-0’s state and
disables the oscillator. A high level on the MR line
accomplishes the reset function. All counter stages are
master-slave flip-flops. The state of the counter is advanced
one step in binary order on the negative transition of φI (and
φO). All inputs and outputs are buffered. Schmitt trigger
action on the input-pulse-line permits unlimited rise and fall
times.

In order to achieve a symmetrical waveform in the oscillator
section the HCT4060 input pulse switch points are the same
as in the HC4060; only the MR input in the HCT4060 has

Functional Diagram

12

MR

14-STAGE

COUNTER

11

φI

OSCILLATOR

TTL switching levels.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC4060E -55 to 125 16 Ld PDIP E16.3
CD74HCT4060E -55 to 125 16 Ld PDIP E16.3
CD74HC4060M -55 to 125 16 Ld SOIC M16.15
CD74HCT4060M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

7

Q4

5

Q5

4

Q6

6

Q7

14

RIPPLE

AND

Q8

13

Q9

15

Q10

1

Q12

2

Q13

3

Q14

PKG.

NO.

φO
φO

9

10

GND = 8

V

= 16

CC

2

øO
øO

ø1

MR

CD74HC4060, CD74HCT4060

9

ø1Q1

10
11

FF1

ø1 Q1

R

12

FIGURE 1. LOGIC BLOCK DIAGRAM

TRUTH TABLE

ø4Q4

FF4

ø4 Q4

R

Q13

ø14 Q14

FF14

ø14 Q14

R

Q14

ø5 Q13

FF5 - FF13

ø5 Q13

R

723

5, 4, 6, 14, 13, 15, 1

Q4

Q5 - Q10, Q12

øI MR OUTPUT STATE

↑ L No Change
↓ L Advance to Next State

X H All Outputs are Low

3

CD74HC4060, CD74HCT4060

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage Q Outputs
CMOS Loads

High Level Output
Voltage Q Outputs
TTL Loads

Low Level Output
Voltage Q Outputs
CMOS Loads

Low Level Output
Voltage Q Outputs
TTL Loads

High-Level Output
Voltage

φO Output
(Pin 10)
CMOS Loads

V

IH

V

IL

V

OH

V

OL

V

OH

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - -V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

GND

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

4

CD74HC4060, CD74HCT4060

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

High-Level Output
Voltage φO Output
(Pin 10)
TTL Loads
Note 6

Low-Level Output
Voltage

φO Output
(Pin 10)
CMOS Loads

Low-Level Output
Voltage

φO Output
(Pin 10)
TTL Loads

High-Level Output
Voltage φO Output
(Pin 9)
TTL Loads

Low-Level Output
Voltage φO Output
(Pin 9)
TTL Loads

Input Leakage
Current

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage Q Outputs
CMOS Loads

High Level Output
Voltage Q Outputs
TTL Loads

Low Level Output
Voltage Q Outputs
CMOS Loads

Low Level Output
Voltage Q Outputs
TTL Loads

High-Level Output
Voltage

φO Output
(Pin 10)
CMOS Loads

High-Level Output
Voltage

φO Output
(Pin 10)
TTL Loads Note 6

Low-Level Output
Voltage

φO Output
(Pin 10)
CMOS Loads

V

OH

V

OL

V

OL

V

OH

V

OL

I

I

I

CC

V

IH

V

IL

V

OH

V

OL

V

OH

V

OH

V

OL

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

GND

VCC or

GND

VCC or

GND

VILor V

IH

VILor V

IH

VCC or

GND

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

Note 5

VIHor V

IL

Note 5

VCC or

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

GND

VCC or

GND

VCC or

GND

o

C -40oC TO 85oC -55oCTO125oC

V

CC

(V)

25

UNITSV

-2.6 4.5 3.98 - - 3.84 - 3.7 - V

-3.3 6 5.48 - - 5.34 - 5.2 - V

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

2.6 4.5 - - 0.26 - 0.33 - 0.4 V

3.3 6 - - 0.26 - 0.33 - 0.4 V

-3.2 4.5 3.98 - - 3.84 - 3.7 - V

-4.2 6 5.48 - - 5.34 - 5.2 - V

-2.6 4.5 - - 0.26 - 0.33 - 0.4 V

-3.3 6 - - 0.26 - 0.33 - 0.4 V

-6--±0.1 - ±1-±1µA

0 6 - - 8 - 80 - 160 µA

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

-2.6 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

5

CD74HC4060, CD74HCT4060

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Low-Level Output
Voltage φO Output

V

OL

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

2.6 4.5 - - 0.26 - 0.33 - 0.4 V

GND
(Pin 10)
TTL Loads

High-Level Output
Voltage φO Output

V

OH

VILor V

-3.2 4.5 3.98 - - 3.84 - 3.7 - V

IH

(Pin 9)
TTL Loads

Low-Level Output
Voltage φO Output

V

OL

VIHor V

3.2 4.5 - 0.26 - 0.33 - 0.4 V

IL

Note 5
(Pin 9)
TTL Loads

Input Leakage
Current

I

I

Any

0 5.5 - ±0.1 - ±1-±1µA

Voltage
Between
VCCand

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

∆I

CC

(Note 4)

VCC or

GND

V

CC

-2.1

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

Input Pin: 1 Unit Load

NOTES:

4. For dual-supply systems theoretical worst case (V

5. For pin 11 VIH = 3.15V, VIL = 0.9V.

6. Limits not valid when pin 12 (instead of pin 11) is used as control input.

V

CC

(V)

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- 100 360 - 450 - 490 µA

HCT Input Loading Table

INPUT UNIT LOADS

MR 0.35

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions Table, e.g. 360µA max at 25oC.

Prerequisite for Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

HC TYPES

Maximum Input Pulse
Frequency

Input Pulse Width t

Reset Removal Time t

t

MAX

REM

2 6 - - 5 - - 4 - - MHz

4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz

W

2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614- -17- -20--ns
2 100 - - 125 - - 150 - - ns

4.5 20 - - 25 - - 30 - - ns
617- -21- -26--ns

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

6

CD74HC4060, CD74HCT4060

Prerequisite for Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL V

Reset Pulse Width t

HCT TYPES

Maximum Input,
Pulse Frequency

Input Pulse Width t
Reset Removal Time t
Reset Pulse Width t

t

MAX

REM

W

W

W

(V)

CC

2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614- -17- -20--ns

4.5 30 - - 25 - - 20 - - MHz

4.5 16 - - 20 - - 24 - - ns

4.5 26 - - 33 - - 39 - - ns

4.5 25 - - 31 - - 38 - - ns

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Switching Specifications Input t

PARAMETER SYMBOL

, tf= 6ns

r

TEST

CONDITIONS VCC(V)

25oC

-40oC TO
85oC

-55oC TO
125oC

HC TYPES

Propagation Delay

t

PLH

, t

PHL

CL = 50pF

2 - - 300 - 375 - 450 ns

φI to Q4 4.5 - - 60 - 75 - 90 ns

C

= 15pF 5 - 25 - - - - - ns

L

CL = 50pF 6 - - 51 - 64 - 78 ns

Qn to Q

n+1

t

PLH

, t

CL = 50pF 2 - - 80 - 100 - 120 ns

PHL

4.5 - - 16 - 20 - 24 ns
CL = 15pF 5 - 6 - - - - - ns
CL = 50pF 6 - - 14 - 17 - 20 ns

MR to Q

n

t

PHL

CL = 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns
CL = 15pF 5 - 14 - - - - - ns
CL = 50pF 6 - - 30 - 37 - 45 ns

Output Transition Time t

THL

, t

CL = 50pF 2 - - 75 - 95 - 110 ns

TLH

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance C

I

(TBD)

Propagation Dissipation

C

PD

- - -40- - - - - pF

Capacitance

HCT TYPES

Propagation Delay

t

PLH

, t

PHL

CL = 50pF

2

- - - - - - - -ns

φI to Q4 4.5 - - 66 - 83 - 100 ns

= 15pF 5 - 25 - - - - - -ns

C

L

CL = 50pF 6 - - - - - - - -ns

UNITSMIN TYP MAX MIN MAX MIN MAX

7

CD74HC4060, CD74HCT4060

Switching Specifications Input t

, tf= 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Qn to Q

n+1

t

PLH

CONDITIONS VCC(V)

, t

CL = 50pF 2 - - - - - - - ns

PHL

4.5 - - 16 - 20 - 24 ns
CL = 15pF 5 - 6 - - - - - ns
CL = 50pF 6 - - - - - - - ns

MR to Q

n

t

PHL

CL = 50pF 2 - - - - - - - ns

4.5 - - 44 - 55 - 66 ns
CL = 15pF 5 - 17 - - - - - ns
CL = 50pF 6 - - - - - - - ns

Output Transition Time t

THL

, t

CL = 50pF 2 - - - - - - - ns

TLH

4.5 - - 15 - 19 - 22 ns

6-------ns

Input Capacitance C

I

(TBD)

Propagation Dissipation

C

PD

- - -40- - - - - pF

Capacitance

NOTES:

7. CPD is used to determine the dynamic power consumption, per package.

8. PD = CPD V

CC

2

fi∑(CL V

2

fi/M) where M = 21, 22, 23, ...214, fi = input frequency, CL = output load capacitance.

CC

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

TYPICAL LIMIT VALUES FOR RX AND C

X

TYPICAL

PARAMETER

TEST

CONDITIONS VOLTAGE

MAXIMUM

LIMITS

RX Minimum CX > 1000pF 2 1KΩ

CX > 10pF 4.5
CX > 10pF 6

RX Maximum CX > 10pF 2 20MΩ

CX > 10pF 4.5
CX > 10pF 6

CX Minimum RX > 10KΩ 2 10pF

RX > 10KΩ 4.5
RX > 10KΩ 6
RX = 1KΩ 2 1000pF
RX = 1KΩ 4.5 10pF
RX = 1KΩ 6 10pF

Maximum
Astable Oscillator
Frequency

CX = 1000pF,
RX = 1KΩ

CX = 100pF,
RX = 1KΩ

CX = 100pF,
RX = 1KΩ

2 0.5MHz

(Note 9)

4.5 3MHz
(Note 9)

6 3MHz

(Note 9)

NOTE:

9. At very high frequencies f = 1/2.2 RXCXno longer gives an
yaccurate approximation.

2

10

10

1

-1

10

(µF)

X

-2

C

10

-3

10

-4

10

-5

10

-1

0

10

10

10

OSCILLATOR FREQUENCY (Hz)

10

NOTE: OSC Frequency≈ 1/2.2 RXC

3

2

10

X

10

TA = 25oC
RX = 1KΩ
10KΩ
100KΩ
1MΩ
10MΩ

4

10510

For 1MΩ > RX > 1KΩ, CX > 10pF, f < 1MHz

FIGURE 2. FREQUENCY OF ON-BOARD OSCILLATOR AS A

FUNCTION OF CX AND R

X

6

8

Typical Performance Curves

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

WL

L

tWL+ tWH=

50%

t

WH

fC

50%

I

L

V

CC

GND

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 3. HC CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

1.3V

I

fC

L

3V

GND

t

rCL

CLOCK

= 6ns

0.3V

2.7V

1.3V

0.3V

t

fCL

t

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 4. HCT CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

10%

90%

1.3V

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

FIGURE 5. HC AND HCT TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 6. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

9

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