Texas Instruments CD74HCT253M96, CD74HCT253E, CD74HC253M, CD74HC253E, CD74HCT253M Datasheet

1

Data sheet acquired from Harris Semiconductor
SCHS170

Features

• Common Select Inputs

• Separate Output-Enable Inputs

• Three-State Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

o

C to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

= 30%, NIH = 30% of V

CC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

IL

= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, I

l

≤ 1µA at VOL, V

OH

Description

The Harris CD74HC253 and CD74HCT253 are dual 4-to-1
line selector/multiplexers having three-state outputs. One of
four sources for each section is selected by the common
select inputs, S0 and S1. When the output enable (

1OE,

2OE) is HIGH, the output is in the high-impedance state.

Pinout

CD74HC253, CD74HCT253

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

PKG.

NO.

14

15

16

9

13
12
11
10

1
2
3
4
5

7

6

8

1OE

S1

1I

3

1I

2

1I

1

1I

0

GND

1Y

V

CC

S0
2I

3

2I

2

2I

1

2I

0

2Y

2OE

November 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

File Number 1673.1

CD74HC253,

CD74HCT253

High Speed CMOS Logic

Dual 4-Input Multiplexer

[ /Title
(CD74
HC253
,
CD74
HCT25

3)
/

Sub-

j

ect
(High
Speed
CMOS
Logic
Dual
4-Input
Multi­plexer)

2

Functional DiagramS

TRUTH TABLE

SELECT INPUTS DATA INPUTS

OUTPUT
ENABLE OUTPUT

S1 S0 I

0

I

1

I

2

I

3

OE Y

XXXXXXHZ
LLLXXXLL
LLHXXXLH
LHXLXXLL
LHXHXXLH
HLXXLXLL
HLXXHXLH
HHXXXLLL
HHXXXHLH

NOTE:
Select inputs S1 and S0 are common to both sections.
H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Impedance (Off).

2OE

2I

3

2I

2

2I

1

2I

0

S

0

S

1

1I

0

1I

1

1I

2

1I

3

1OE

15 13 12 11 10 14 2 6 5 4 3 1

2OE

2OE

1OE

1OE

PN PN

2OE 2OE

9

2Y

1OE

1OE

7

1Y

16

8

V

CC

GND

CD74HC253, CD74HCT253

3

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

CC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C -40oC TO 85oC -55oC TO 125oC

UNITSV

I

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input
Voltage

V

IH

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

Low Level Input
Voltage

V

IL

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

High Level Output
Voltage
CMOS Loads

V

OH

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output
Voltage
TTL Loads

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

Low Level Output
Voltage
CMOS Loads

V

OL

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output
Voltage
TTL Loads

- - ---- - - - V

-6 4.5 - - 0.26 - 0.33 - 0.4 V

-7.8 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage
Current

I

I

VCC or

GND

-6--±0.1 - ±1-±1 µA

CD74HC253, CD74HCT253

4

Quiescent Device
Current

I

CC

VCC or

GND

0 6 - - 8 - 80 - 160 µA

HCT TYPES

High Level Input
Voltage

V

IH

- - 4.5 to

5.5

2--2- 2 - V

Low Level Input
Voltage

V

IL

- - 4.5 to

5.5

- - 0.8 - 0.8 - 0.8 V

High Level Output
Voltage
CMOS Loads

V

OH

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output
Voltage
TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output
Voltage
CMOS Loads

V

OL

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output
Voltage
TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage
Current

I

I

VCCand

GND

0 5.5 - - ±0.1 - ±1-±1 µA

Quiescent Device
Current

I

CC

VCC or

GND

0 5.5 - - 8 - 80 - 160 µA

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load

∆I

CC

(Note)

V

CC

-2.1

- 4.5 to

5.5

- 100 360 - 450 - 490 µA

Three-State Leakage
Current

I

OZ

VILor VIHVO =

VCC or

GND

5.5 - - ±0.5 - ±5-±10 µA

NOTE: For dual-supply systems theoretical worst case (V

I

= 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C -40oC TO 85oC -55oC TO 125oC

UNITSV

I

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

1IO - 1I3, 2IO-2l

3

0.4

1EO, 2EO, S0, S

1

1

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

Switching Specifications Input t

r

, tf = 6ns

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay t

PLH,

t

PHL

CL= 50pF 2 - - 175 - 220 - 265 ns

Select to Outputs 4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - - ns
C

L

= 50pF 6 - - 30 - 37 - 45 ns

CD74HC253, CD74HCT253

5

Data to Outputs t

PLH,

t

PHL

CL= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns
CL=15pF 5 - 14 - - - - - ns
C

L

= 50pF 6 - - 30 - 37 - 45 ns

Disable Delay Times t

PHZ,tPLZCL

= 50pF 2 - - 150 - 190 - 225 ns

C

L

= 50pF 4.5 - - 30 - 38 - 45 ns
CL = 15pF 5 - 12 - - - - - ns
C

L

= 50pF 6 - - 26 - 33 - 38 ns

Enable Delay Times t

PZH

,

t

PZL

CL= 50pF 2 - - 110 - 140 - 165 ns
CL = 50pF 4.5 - - 22 - 28 - 33 ns
CL = 15pF 5 - 9 - - - - - ns
CL = 50pF 6 - - 19 - 24 - 28 ns

Output Transition Times t

TLH,tTHLCL

= 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns
6 - - 10 - 13 - 15 ns

Input Capacitance C

I

- - - - 10 - 10 - 10 pF

Three-State Output Capacitance C

O

- - - - 20 - 20 - 20 pF

Power Dissipation Capacitance
(Notes 4, 5)

C

PD

-5-46-----pF

HCT TYPES

Propagation Delay t

PLH

,

t

PHL

Select to Outputs CL= 50pF 4.5 - - 40 - 50 - 60 ns

C

L

=15pF 5 - 16 - - - - ns

Data to Outputs t

PLH

,

t

PHL

CL= 50pF 4.5 - - 38 - 48 - 57 ns
C

L

=15pF 5 - 16 - - - - - ns

Disable Delay Times t

PLH

,

t

PHL

CL= 50pF 4.5 - 30 - 38 - 45 ns
C

L

=15pF 5 - 12 - - - - - ns

Enable Delay Times t

PZH

,

t

PZL

CL= 50pF 4.5 - - 30 - 38 - 45 ns
C

L

=15pF 5 - 12 - - - - - ns

Output Transition Time t

TLH,tTHLCL

= 50pF 4.5 - - 12 - 15 - 18 ns

Input Capacitance C

IN

- - - - 10 - 10 - 10 pF

Three-State Output Capacitance C

O

- - - - 20 - 20 - 20 pF

Power Dissipation Capacitance
(Notes 4, 5)

C

PD

-5-52-----pF

NOTES:

4. C

PD

is used to determine the dynamic power consumption, per multiplexer.

5. PD = V

CC

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Specifications Input t

r

, tf = 6ns (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD74HC253, CD74HCT253

6

Test Circuits and Waveforms

FIGURE 1. HC AND HCT TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

NOTE: Opendrain waveformst

PLZ

and t

PZL

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩ to

VCC, CL = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

t

PHL

t

PLH

t

THL

t

TLH

90%
50%
10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

V

CC

tr = 6ns tf = 6ns

90%

t

PHL

t

PLH

t

THL

t

TLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

3V

tr = 6ns

t

f

= 6ns

90%

50%

10%

90%

GND

V

CC

10%

90%

50%

50%

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS
ENABLED

OUTPUTS

DISABLED

OUTPUTS
ENABLED

6ns 6ns

t

PZH

t

PHZ

t

PZL

t

PLZ

0.3

2.7

GND

3V

10%

90%

1.3V

1.3V

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

OUTPUTS
ENABLED

OUTPUTS

DISABLED

OUTPUTS
ENABLED

t

r

6ns

t

PZH

t

PHZ

t

PZL

t

PLZ

6ns t

f

1.3

IC WITH

THREE-

STATE

OUTPUT

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

VCC FOR t

PLZ

AND t

PZL

GND FOR t

PHZ

AND t

PZH

OUTPUT

R

L

= 1kΩ

C

L

50pF

CD74HC253, CD74HCT253

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated