Texas Instruments CD74HCT251M96, CD74HCT251M, CD74HCT251E, CD74HC251M96, CD74HC251M Datasheet

CD74HC251,

/
j

[ /Title
(CD74
HC251
,
CD74
HCT25

1)
Sub­ect

(High
Speed
CMOS
Logic
8-Input
Multi­plexer;
Three-

Data sheet acquired from Harris Semiconductor
SCHS169

November 1997

Features

• Selects One of Eight Binary Data Inputs

• Three-State Output Capability

• True and Complement Outputs

• Typical (Data to Output) Propagation Delay of 14ns at
= 5V, CL = 15pF, TA = 25oC

V

CC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL

Logic ICs

• Alternate Source is Philips

- HC Types

- 2V to 6V Operation

- High Noise Immunity: N
at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CD74HCT251

High Speed CMOS Logic

8-Input Multiplexer; Three-State

Description

The Harris CD74HC251 and CD74HCT251 are 8-channel
digital multiplexers with three-state outputs, fabricated with
high-speed silicon-gate CMOS technology.Together with the
low power consumption of standard CMOS integrated cir­cuits, they possess the ability to drive 10 LSTTL loads. The
three-state feature makes them ideally suited for interfacing
with bus lines in a bus-oriented system.

This multiplexer features both true (Y) and complement (
outputs as well as an output enable (
be at a low logic level to enable this device. When the
input is high, both outputs are in the high-impedance state.
When enabled, address information on the data select inputs
determines which data input is routed to the Y and
puts. The CD74HCT251 logic family is speed, function, and
pin-compatible with the standard 74LS251.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CC

CD74HC251E -55 to 125 16 Ld PDIP E16.3
CD74HCT251E -55 to 125 16 Ld PDIP E16.3
CD74HC251M -55 to 125 16 Ld SOIC M16.15
CD74HCT251M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer ordie for thispart number isavailable which meetsallelec­trical specifications. Please contact your local sales office or
Harris customer service for ordering information.

OE) input. The OE must

Y)

OE

Y out-

PKG.

NO.

Pinout

CD74HC251, CD74HCT251

(PDIP, SOIC)

TOP VIEW

16

1

I

3

2

I

2

3

I

1

4

I

0

5

Y

6

Y

7

OE

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

V

CC

15

I

4

14

I

5

13

I

6

12

I

7

11

S0
S1

10

S2

9

File Number 1489.1

Functional Diagram

CD74HC251, CD74HCT251

CHANNEL

SELECT

OE

INPUTS

DAT A

SELECT

I

0

I

1

I

2

I

3

15

I

4

14

I

5

13

I

6

12

I

7

11

S

0

10

S

1

S

2

7

4
3
2

1

5

Y

OUTPUTS

6

Y

9

TRUTH TABLE

INPUTS OUTPUT

OUTPUT

CONTROL OE Y YS2 S1 S0

XXX H ZZ
LLL L I
LLH L I
LHL L I
LHH L I
HLL L I
HLH L I
HHL L I
HHH L I

0

1

2

3

4

5

6

7

I

0

I

1

I

2

I

3

I

4

I

5

I

6

I

7

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, Z = High Imped­ance (Off), I0, I1...I7 = the level of the respective input.

2

CD74HC251, CD74HCT251

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

IK

OK

O

O

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

V

IH

V

IL

V

OH

V

OL

TEST

CONDITIONS

- - 2 1.5 - - 1.5 - 1.5 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

V

CC

(V)

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

25oC -40oC TO 85oC -55oCTO125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC251, CD74HCT251

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

I

I

CC

-VILor VIHVO =

V

IH

V

V

OH

V

OL

I

I

CC

-VILor VIHVO =

∆I

CC

VCC or

I

IL

I

GND

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

V

CC

-2.1

0 6 - - 8 - 80 - 160 µA

VCC or

GND

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1µA

0 5.5 - - 8 - 80 - 160 µA

VCC or

GND

- 4.5 to

V

CC

(V)

-6--±0.1 - ±1-±1µA

6--±0.5 - ±5.0 - ±10 µA

5.5

5.5

6--±0.5 - ±5.0 - ±10 µA

5.5

25oC -40oC TO 85oC -55oCTO125oC

2--2- 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

S0, S1, S2 0.55

I0 - I7 0.5

OE 2.65

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

4

CD74HC251, CD74HCT251

Switching Specifications Input t

PARAMETER SYMBOL

, tf = 6ns

r

TEST

CONDITIONS VCC(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

HC TYPES

Propagation Delay t

PLH,tPHLCL

= 50pF 2 - - 245 - 305 - 370 ns

Select to Outputs 4.5 - - 49 - 61 - 74 ns

C

=15pF 5 - 21 - - - - - ns

L

C

= 50pF 6 - - 42 - 52 - 63 ns

L

Data to Outputs t

PLH,tPHLCL

= 50pF 2 - - 175 - 220 - 265 ns

4.5 - -35-44-53ns

C

=15pF 5 - 12 - - - - - ns

L

C

= 50pF 6 - - 30 - 37 - 45 ns

L

Enable to High Z and Enable
from High Z

Output Transition Time t

t

PLH,tPHLCL

, t

TLH

THLCL

= 50pF 2 - - 140 - 175 - 210 ns

4.5 - -28-35-42ns

C

=15pF 5 - 11 - - - - - ns

L

C

= 50pF 6 - - 24 - 30 - 36 ns

L

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - -15-19-22ns
6 - -13-16-19ns

Input Capacitance C
Three-State Output

IN

CO - - - -15-15-15pF

- - - -10-10-10pF

Capacitance
Power Dissipation Capacitance

C

PD

- 5 -60- - - - -pF

(Notes 4, 5)

HCT TYPES

Propagation Delay t

PLH

, t

PHL

Select to Outputs CL= 50pF 4.5 - - 42 - 53 - 63 ns

C

=15pF 5 - 18 - - - - ns

L

Data to Outputs t

Enable to High Z and Enable
from High Z

Output Transition Time t
Input Capacitance C
Power Dissipation Capacitance

(Notes 4, 5)

PLH

t

PLH

TLH

, t

, t

, t

IN

C

PD

PHLCL

C

PHLCL

C

THLCL

= 50pF 4.5 - - 35 - 44 - 53 ns
=15pF 5 - 12 - - - - - ns

L

= 50pF 4.5 - 30 - 38 - 45 ns
=15pF 5 - 12 - - - - - ns

L

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - -10-10-10pF

- 5 60-----pF

NOTES:

4. C

is used to determine the dynamic power consumption, per package.

PD

5. PD = V

2

fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

UNITSMIN TYP MAX MIN MAX MIN MAX

5

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

CD74HC251, CD74HCT251

tr = 6ns

V

CC

GND

INPUT

2.7V

1.3V

0.3V

= 6ns

t

f

3V

GND

INVERTING

OUTPUT

t

THL

t

PHL

t

PLH

50%

10%

t

90%

TLH

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

V

GND

OUTPUTS

ENABLED

CC

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

0.3

t

t

6ns

PZL

1.3V

PZH

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS

ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GND

NOTE: Opendrain waveforms t
VCC, CL = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

TIED HIGH

and t

PLZ

OTHER

INPUTS

OR LOW

OUTPUT

DISABLE

PZL

IC WITH

THREE-

STATE

OUTPUT

OUTPUT

= 1kΩ

R

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

6

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