The Harris CD74HC251 and CD74HCT251 are 8-channel
digital multiplexers with three-state outputs, fabricated with
high-speed silicon-gate CMOS technology.Together with the
low power consumption of standard CMOS integrated circuits, they possess the ability to drive 10 LSTTL loads. The
three-state feature makes them ideally suited for interfacing
with bus lines in a bus-oriented system.
This multiplexer features both true (Y) and complement (
outputs as well as an output enable (
be at a low logic level to enable this device. When the
input is high, both outputs are in the high-impedance state.
When enabled, address information on the data select inputs
determines which data input is routed to the Y and
puts. The CD74HCT251 logic family is speed, function, and
pin-compatible with the standard 74LS251.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CC
CD74HC251E-55 to 12516 Ld PDIPE16.3
CD74HCT251E-55 to 12516 Ld PDIPE16.3
CD74HC251M-55 to 12516 Ld SOICM16.15
CD74HCT251M-55 to 12516 Ld SOICM16.15
NOTES:
1. When ordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer ordie for thispart number isavailable which meetsallelectrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
OE) input. The OE must
Y)
OE
Y out-
PKG.
NO.
Pinout
CD74HC251, CD74HCT251
(PDIP, SOIC)
TOP VIEW
16
1
I
3
2
I
2
3
I
1
4
I
0
5
Y
6
Y
7
OE
8
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETERSYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
V
IH
V
IL
V
OH
V
OL
TEST
CONDITIONS
--21.5--1.5-1.5-V
--2--0.5-0.5-0.5V
VIHor VIL-0.0221.9--1.9-1.9-V
-0.024.54.4--4.4 -4.4-V
-0.0265.9--5.9-5.9-V
- - ---- - - - V
-44.53.98--3.84-3.7-V
-5.265.48--5.34-5.2-V
VIHor VIL0.022--0.1-0.1-0.1V
0.024.5--0.1-0.1-0.1V
0.026--0.1-0.1-0.1V
- - ---- - - - V
44.5--0.26-0.33-0.4V
5.26--0.26-0.33-0.4V
V
CC
(V)
4.53.15--3.15 -3.15-V
64.2--4.2-4.2-V
4.5--1.35-1.35-1.35V
6--1.8-1.8-1.8V
25oC-40oC TO 85oC -55oCTO125oC
UNITSVI(V)IO(mA)MINTYPMAXMINMAXMINMAX
3
CD74HC251, CD74HCT251
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETERSYMBOL
Input Leakage
Current
Quiescent Device
Current
Three-State Leakage
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Three-State Leakage
Current
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
I
I
CC
-VILor VIHVO =
V
IH
V
V
OH
V
OL
I
I
CC
-VILor VIHVO =
∆I
CC
VCC or
I
IL
I
GND
VCC or
GND
--4.5 to
--4.5 to
VIHor VIL-0.024.54.4--4.4-4.4-V
VIHor VIL0.024.5--0.1-0.1-0.1V
VCCand
GND
VCC or
GND
V
CC
-2.1
06--8-80-160µA
VCC or
GND
-44.53.98--3.84-3.7-V
44.5--0.26-0.33-0.4V
05.5-±0.1-±1-±1µA
05.5--8-80-160µA
VCC or
GND
-4.5 to
V
CC
(V)
-6--±0.1-±1-±1µA
6--±0.5-±5.0-±10µA
5.5
5.5
6--±0.5-±5.0-±10µA
5.5
25oC-40oC TO 85oC -55oCTO125oC
2--2- 2 - V
--0.8-0.8-0.8V
-100360-450-490µA
UNITSVI(V)IO(mA)MINTYPMAXMINMAXMINMAX
HCT Input Loading Table
INPUTUNIT LOADS
S0, S1, S20.55
I0 - I70.5
OE2.65
NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.
4
CD74HC251, CD74HCT251
Switching Specifications Input t
PARAMETERSYMBOL
, tf = 6ns
r
TEST
CONDITIONS VCC(V)
25
o
C
-40oC TO
85oC
-55oC TO
125oC
HC TYPES
Propagation Delayt
PLH,tPHLCL
= 50pF2--245-305-370ns
Select to Outputs4.5--49-61-74ns
C
=15pF5-21-----ns
L
C
= 50pF6--42-52-63ns
L
Data to Outputst
PLH,tPHLCL
= 50pF2--175-220-265ns
4.5 - -35-44-53ns
C
=15pF5-12-----ns
L
C
= 50pF6--30-37-45ns
L
Enable to High Z and Enable
from High Z
Output Transition Timet
t
PLH,tPHLCL
, t
TLH
THLCL
= 50pF2--140-175-210ns
4.5 - -28-35-42ns
C
=15pF5-11-----ns
L
C
= 50pF6--24-30-36ns
L
= 50pF2--75-95-110ns
4.5 - -15-19-22ns
6 - -13-16-19ns
Input CapacitanceC
Three-State Output
IN
CO-- - -15-15-15pF
-- - -10-10-10pF
Capacitance
Power Dissipation Capacitance
C
PD
-5 -60- - - - -pF
(Notes 4, 5)
HCT TYPES
Propagation Delayt
PLH
, t
PHL
Select to OutputsCL= 50pF4.5--42-53-63ns
C
=15pF5-18----ns
L
Data to Outputst
Enable to High Z and Enable
from High Z
Output Transition Timet
Input CapacitanceC
Power Dissipation Capacitance
(Notes 4, 5)
PLH
t
PLH
TLH
, t
, t
, t
IN
C
PD
PHLCL
C
PHLCL
C
THLCL
= 50pF4.5--35-44-53ns
=15pF5-12-----ns
L
= 50pF4.5-30-38-45ns
=15pF5-12-----ns
L
= 50pF4.5--15-19-22ns
-- - -10-10-10pF
-560-----pF
NOTES:
4. C
is used to determine the dynamic power consumption, per package.
PD
5. PD = V
2
fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
CC
UNITSMINTYPMAXMINMAXMINMAX
5
Test Circuits and Waveforms
tr = 6nstf = 6ns
INPUT
90%
50%
10%
CD74HC251, CD74HCT251
tr = 6ns
V
CC
GND
INPUT
2.7V
1.3V
0.3V
= 6ns
t
f
3V
GND
INVERTING
OUTPUT
t
THL
t
PHL
t
PLH
50%
10%
t
90%
TLH
FIGURE 1. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns6ns
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
50%
t
t
OUTPUTS
ENABLED
PLZ
PHZ
10%
90%
90%
10%
t
PZL
t
PZH
OUTPUTS
DISABLED
50%
50%
FIGURE 3. HC THREE-STATE PROPAGATION DELAY
WAVEFORM
V
GND
OUTPUTS
ENABLED
CC
t
INVERTING
OUTPUT
THL
t
PHL
t
PLH
1.3V
10%
90%
t
TLH
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
0.3
t
t
6ns
PZL
1.3V
PZH
1.3V
OUTPUTS
ENABLED
t
r
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
t
t
OUTPUTS
ENABLED
6nst
PLZ
PHZ
10%
90%
f
2.7
1.3
OUTPUTS
DISABLED
FIGURE 4. HCT THREE-STATE PROPAGATION DELAY
WAVEFORM
3V
GND
NOTE: Opendrain waveforms t
VCC, CL = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
TIED HIGH
and t
PLZ
OTHER
INPUTS
OR LOW
OUTPUT
DISABLE
PZL
IC WITH
THREE-
STATE
OUTPUT
OUTPUT
= 1kΩ
R
L
C
L
50pF
VCC FOR t
GND FOR t
PLZ
PHZ
AND t
AND t
PZL
PZH
are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto
6
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1999, Texas Instruments Incorporated
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