NEC UPD75116GF-XXX-3BE, UPD75116GF-A-XXX-3BE, UPD75116CW-XXX, UPD75116CW-A-XXX, UPD75112GF-A-XXX-3BE Datasheet

μPD75112(A), 75116(A)

4-Bit Single Chip-Microcomputer

Data Sheet

Description

The μPD75116(A) is one of the 4-bit single-chip microcomputer 75X series.

The μPD75116(A) is a product with the extended ROM capacity of the μPD75108(A). In addition of high-speed operations, it can manipulate data in units of 1, 4 and 8 bits. In particular, the I/O operation of the μPD75116 have been improved by a wide variety of bit control instructions. The μPD75116 is provided with interface inputs/outputs with peripheral circuits having different power voltages, and analog inputs and suitable for controlling automobile electrical equipment, etc. For the μPD75116(A), an on-chip pin-compatible one-time PROM product (μPD75P116) is separately available for system development evaluation.

Functions are described in detail in the following User’s Manual, which should be read when carrying out design work.

μPD751×× Series User’s Manual: IEM-992

		Ordering Code	Package	Qualty Grade
	μ	×××	64-pin plastic shrink DIP	Special
		PD75112CW(A)-	(750 mil)
	μPD75112GF(A)-×××-3BE			Special
			64-pin plastic QFP
	μPD75116CW(A)-×××		(14 × 20 mm)	Special
			64-pin plastic shrink DIP	Special
			(750 mil)
	μPD75116GF(A)-×××-3BE
			64-pin plastic QFP
			(14 × 20 mm)

Remarks: ××× is a ROM code number.

Please refer to "Quality Grade on NEC Semiconductor Devices" (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

Unless there are any particular functional differences, the μPD75116(A) is described in this document as a representative product.

Features

∙Higher reliability than μPD75116

∙Architecture "75X" equivalent to 8-bit microcomputer

∙Minimum instruction execution time (high-speed operation): 0.95 μs (when operated at 4.19 MHz and 5 V)

∙Instruction executionvariable function: 0.95μs/1.91μs/ 15.3 μs (when operated at 4.19 MHz)

∙Many input/output ports: 58

∙3-channel on-chip 8-bit timers

∙8-bit on-chip serial interface

∙Multi-interruptible vector interrupt function

Applications

Automobile electrical equipment, etc.

	The information in this document is subject to change without notice.
	The mark shows major revised points.
Document No. IC-2811A
(O. D. No. IC-8261A)
Date Published March 1994 P	©NEC Corporation 1990
Printed in Japan

μPD75112(A), 75116(A)

Defferences between μPD75112(A), 75116(A) and μPD75112, 75116

	Product Name	μ	μ
Item
		PD75112(A), 75116(A)	PD75112, 75116
Quality grade		Special	Standard
Electrical specifications	Absolute maximum ratings	Different high-level output current and low-level output current
	DC characteristics	Different low-level output voltage
Direct LED drive		Not possible	Possible

Outline of Functions

Item				Description
No. of basic instruction			43
Min. instruction execution time			0.95 μs/1.91 μs/15.3 μs (when operated at 4.19 MHz), switchable at 3 levels
On-chip memory		ROM	12160 × 8 (μPD75112(A)), 16256 × 8 (μPD75116(A))
		RAM	512 × 4
General register			4 bits × 8 × 4 banks (memory mapping)
Accumulator			Three accumulated in compliance with controlled date lengths
			∙1-bit accumulator (CY), 4-bit accumulator (A), 8-bit accumulator (XA)
Input/output port			58 in total
			∙	CMOS input pin	:	10
			∙	CMOS input/output pin (LED direct drive enable) :		32
			∙	Intermediate withstand voltage N-ch open drain :		12
			∙	input/output pin (bit-wise pull-up resistor inscorporation possible)
				Comparator input pin (4-bit accuracy)	:	4
Timer/counter			∙	8-bit timer/event counter × 2
			∙	8-bit basic interval timer (applicable to watchdog timer)
Serial interface			∙	8-bits
			∙	First LSB/first MSB switchable
			∙	Two transfer modes (transmit and receiver/receive dedicated mode)
Vector interrupt			External : 3, Internal : 4
Test input			External : 2
Standby			∙	STOP/HALT mode
Operating temperature range			-40 to +85°C
Operating voltage			2.7 to 6.0 V
Others			∙	On-chip power-on reset circuit (mask option)
			∙	On-chip bit contol memory (bit sequential buffer)
Package			∙	64-pin plastic shrink DIP (750 mil)
			∙	64-pin plastic QFP (14 × 20 mm)

2

					μ PD75112(A), 75116(A)
		CONTENTS
1.	Pin Configuration (Top View)...............................................................................................				4
2.	Block Diagram.........................................................................................................................				6
3.	Pin Functions.........................................................................................................................				7
	3.1	Port Pins......................................................................................................................................................			7
	3.2	Non-Port Pins...............................................................................................................................................			8
	3.3	Pin Input/Output Circuits............................................................................................................................			9
	3.4	Recommended Connection of Unused Pins.............................................................................................			10
	3.5	Caution Relating to Use of P00/INT4 Pin and	RESET	Pin	........................................................................ 10
4.	Memory Configuration.............................................................................................................				11
5.	Peripheral Hardware Functions..............................................................................................				14
	5.1	Digital Input/Output Port.........................................................................................................................			14
	5.2	Clock Generator.........................................................................................................................................			14
	5.3	Clock Output Circuit..................................................................................................................................			16
	5.4	Basic Interval Timer....................................................................................................................................			16
	5.5	Timer/Event Counter.................................................................................................................................			17
	5.6	Serial Interface............................................................................................................................................			19
	5.7	Programmable Threshold Port (Analog Input Port)...............................................................................			21
	5.8	Bit Sequential Buffer...................................................................................................................................			22
	5.9	Power-On Flag (Mask Option)....................................................................................................................			22
6.	Interrupt Functions..................................................................................................................				23
7.	Standby Functions ...............................................................................................................				25
8.	Reset Functions.....................................................................................................................				26
9.	Instruction Set.......................................................................................................................				29
10. Mask Option Selection..........................................................................................................					37
11. Electrical Specifications........................................................................................................					38
12. Package Information ............................................................................................................					48
13. Recommended Soldering Conditions .................................................................................					51
APPENDIX A. Diffeences between μPD751××(A) Series Products
		and Related PROM Products..............................................................................			52
APPENDIX B. Development Tools ............................................................................................					53
APPENDIX C. Related Documentations ...................................................................................					54

3

μPD75112(A), 75116(A)

1. Pin Configuration (Top View)

64-Pin Plastic Shrink DIP (750 mil)

P13/INT3 1

P12/INT2 2

P11/INT1 3

P10/INT0 4

PTH03 5

PTH02 6

PTH01 7

PTH00 8

TI0 9

TI1 10

P23 11

P22/PCL 12

P21/PTO1 13

P20/PTO0 14

P03/SI 15

P02/SO 16

P01/SCK 17

P00/INT4 18

P123 19

P122 20

P121 21

P120 22

P133 23

P132 24

P131 25

P130 26

P143 27

P142 28

P141 29

P140 30

NC 31

VDD 32

×××-PD75112CW(A)μ ×××-PD75116CW(A)μ

64	VSS
63	P90
62	P91
61	P92
60	P93
59	P80
58	P81
57	P82
56	P83
55	P70
54	P71
53	P72
52	P73
51	P60
50	P61
49	P62
48	P63
47	X1
46	X2
45	RESET
44	P50
43	P51
42	P52
41	P53
40	P40
39	P41
38	P42
37	P43
36	P30
35	P31
34	P32
33	P33

4

μPD75112(A), 75116(A)

64-Pin Plastic QFP (14 × 20 mm)

P42

P43

P30

P31

P32

P33

VDD

NC

P140

P141

P142

P143

P130

P41 1

P40 2

P53 3

P52 4

P51 5

P50 6 RESET 7 X2 8 X1 9

P63 10

P62 11

P61 12

P60 13

P73 14

P72 15

P71 16

P70 17

P83 18

P82 19

64 63 62 61 60 59 58 57 56 55 54 53 52

PD75116GF(A)μ	PD75112GF(A)μ
3BE-×××-	3BE-×××-

20 21 22 23 24 25 26 27 28 29 30 31 32

51	P131
50	P132
49	P133
48	P120
47	P121
46	P122
45	P123
44	P00/INT4
43	P01/SCK
42	P02/SO
41	P03/SI
40	P20/PTO0
39	P21/PTO1
38	P22/PCL
37	P23
36	T11
35	T10
34	PTH00
33	PTH01

P81

P80

P93

P92

P91

P90

VSS

P13/INT3

P12/INT2

P11/INT1

P10/INT0

PTH03

PTH02

Pin Name

P00-P03	: Port0	SCK	: Serial Clock
P10-P13	: Port1	SO	: Serial Output
P20-P23	: Port2	SI	: Serial Input
P30-P33	: Port3	PTO0, PTO1	: Programmable Timer Output
P40-P43	: Port4	PCL	: Programmable Clock
P50-P53	: Port5	PTH00-PTH03	: Programmable Threshold Input
P60-P63	: Port6	INT0, INT1, INT4	: External Vectored Interrupt Input
P70-P73	: Port7	INT2, INT3	: External Test Input
P80-P83	: Port8	TI0, TI1	: Timer Input
P90-P93	: Port9	X1, X2	: Clock Oscillation
P120-P123	: Port12	RESET	: Reset
P130-P133	: Port13	NC	: No Connection
P140-P143	: Port14	VDD	: Positive Power Supply
		VSS	: Ground

5

6

BIT SEQ.

DiagramBlock2.

PD75112(A),μ

BASIC

BUFFER(16)

INTERVAL

TIMER

PORT0

4

P00-P03

INTBT

PROGRAM

ALU

CY

SP (8)

75116(A)

COUNTER (14)

PORT1

4

P10-P13

TIMER/EVENT

TI0

COUNTER

PTO0/P20

# 0

BANK

PORT2

4

P20-P23

INTT0

TI1

TIMER/EVENT

ROM

PORT3

4

P30-P33

PTO1/P21

COUNTER

GENERAL REG.

# 1

PROGRAM

PORT4

4

P40-P43

INTT1

MEMORY

PORT5

4

P50-P53

SI/P03

DECODE

SERIAL

12160 × 8 BITS

RAM

SI/P02

AND

INTERFACE

(μPD75112(A))

PORT6

4

P60-P63

SCK/P01

DATA MEMORY

CONTROL

16256 × 8 BITS

512 × 4 BIT

INTSIO

(μPD75116(A))

PORT7

4

P70-P73

INT0/P10

PORT8

4

P80-P83

INT1/P11

INTERRUPT

INT2/P12

CONTROL

PORT9

4

P90-P93

INT3/P13

fX/2N

INT4/P00

CLOCK

CLOCK

CLOCK

STAND BY

CPU CLOCK

PORT12

4

P120-P123

PROGRAMMABLE

OUTPUT

Φ

DIVIDER

GENERATOR

CONTROL

PTH00-PTH03

4

THRESHOLD

CONTROL

PORT13

4

P130-P133

PORT

# 0

PCL/P22

X1

X2

VDD

VSS

RESET

PORT14

4

P140-P143

μPD75112(A), 75116(A)

3.

Pin Functions

3.1

Port Pins

Pin Name

Input/ Output

Dual

Function

8-Bit I/O

At Reset

I/O Circuit

Function Pin

Type *1

P00

Input

INT4

4-bit input port (PORT0)

×

Input

B

P01

Input/output

SCK

F

P02

Input/output

SO

E

P03

Input

SI

B

P10

Input

INT0

4-bit input port (PORT1)

Input

B

P11

INT1

P12

INT2

P13

INT3

P20

Input/output

PTO0

4-bit input/output port (PORT2)

×

Input

E

P21

PTO1

P22

PCL

P23

P30 to P33

Input/output

Programmable 4-bit input/output port (PORT3)

Input

E

Bit-wise input/output setting enable

P40 to P43

Input/output

4-bit input/output port (PORT4)

●

Input

E

P50 to P53

Input/output

4-bit input/output port (PORT5)

Input

E

P60 to P63

Input/output

Programmable 4-bit input/output port (PORT6)

●

Input

E

Bit-wise input/output setting enable

P70 to P73

Input/output

4-bit input/output port (PORT7)

Input

E

P80 to P83

Input/output

4-bit input/output port (PORT8)

●

Input

E

E

P90 to P93

Input/output

4-bit input/output port (PORT9)

Input

P120 to P123

Input/output

N-ch open drain 4-bit input/ output port (PORT12)

●

Input*2

M

Bit-wise pull-up resistor incorporation enable

(mask option)

2 V withstand for open drain

P130 to P133

Input/output

N-ch open drain 4-bit input/ output port (PORT13)

Input*2

M

Bit-wise pull-up resistor incorporation enable

(mask option)

12 V withstand for open drain

P140 to P143

Input/output

N-ch open drain 4-bit input/output port (PORT14)

Input*2

M

Bit-wise pull-up resistor incorporation enable

(mask option)

12 V withstand for open drain

*1: Circles indicate Schmitt trigger inputs.

2: High impedance for open drain

High level for on-chip pull-up resistors

7

μPD75112(A), 75116(A)

3.2 Non-Port Pins

Input/Output

Dual

Function

At Reset

I/O

Function

Circuit

Pin

Type*1

PTH00 to PTH03

Input

Threshold voltage ariable 4-bit analogy input port.

N

TI0

Input

External event pulse input for the timer/event counter or edge

B

detect vector interrupt input. 1-bit input enable.

TI1

PTO0

Input/output

P20

Timer/event counter output.

Input

E

PTO1

P21

Input/output

P01

Serial clock input/output.

Input

F

SCK

SO

Input/output

P02

Serial data output.

Input

E

SI

Input

P03

Serial data input.

Input

B

INT4

Input

P00

Edge detect vector interrupt input (for detecting both rising and

Input

B

falling edges).

INT0

Input

P10

Edge detect vector interrupt input (detected edge selectable).

Input

B

P11

INT1

INT2

Input

P12

Edge detect testable input (for rising edge detection).

Input

B

INT3

P13

PCL

Input/output

P22

Clock output.

Input

E

X1, X2

Crystal/ceramic connect pin (system clock oscillation).

In case with the external clock, input a signal to X1 and the

antiphase to X2.

B

RESET

Input

System reset input (low level active).

NC*2

No Connection

VDD

Positive power supply.

VSS

GND potential.

*1: Circles indicate Schmitt trigger inputs.

2: When the PWB is shared with the μPD75P116, connect the NC pin to VDD directly.

8

μPD75112(A), 75116(A)

3.3 Pin Input/Output Circuits

μPD75116(A) pin input/output crcuit are shown in schematic form.

Figure 3-1 Pin Input/Output Circuits

Type A	VDD

P-ch

IN

N-ch

CMOS specified input buffer

Type B

IN

Schmitt triggered-input with hysteresis characteristics

Type D

VDD

data

P-ch

OUT

output	N-ch
disable

Push-pull output which can be set at output high impedance (with both P-ch an N-ch set to OFF)

Type E

data	IN/OUT
output	Type D
disable
	Type A

Input/output circuit consisting of a Type D push-pull output and a Type A input buffer

Type F

data	IN/OUT
output	Type D
disable
	Type B

Input/output circuit consisting of a Type D push-pull output and a Type B Schmitt-triggered input.

Type M

VDD

Pull-Up Register (Mask Option)

IN/OUT

data	N-ch (+6 V
	Withstand)
output
disable

Middle-High Voltage Input Buffer (+6 V Withstand)

Type N

Comparator

IN +

–

VREF (Threshold Voltage)

9

μPD75112(A), 75116(A)

3.4 Recommended Connection of Unused Pins

		Pin	Recommended Connecting Method
	PTH00 to PTH03		Connect to VSS or VDD
	TI0
	TI1
	P00		Connect to VSS
	P01 to P03		Connect to VSS or VDD
	P10 to P13		Connect to VSS
	P20 to P23		Input state : Connect to VSS or VDD
			Output state : Leave open
	P30 to P33
	P40 to P43
	P50 to P53
	P60 to P63
	P70 to P73
	P80 to P83
	P90 to P93
	P120 to P123
	P130 to P133
	P140 to P143
	RESET		Connect to VDD*1
	NC		Leave open or connect to VDD*2

*1: Only when a power-on reset generator is built in by mask option, connect t VDD.

2: When the PWB is shared with the μPD75P116, connect the NC pin to VDD directly.

3.5 Caution Relating to Use of P00/INT4 Pin and RESET Pin

In addition to the functions described in sections 3.1 and 3.2, the P00/INT4 pin and the RESET pin have the function to set the IC test mode for testing the μPD75116(A) internal operations.

When a voltage larger than VDD is applied to one of these two pins, the test mode is set. Thus, if noise exceeding VDD is applied even during normal operations, the test mode is set and normal operations may be discontinued.

For example, if a cable from the P00/INT4 or RESET pin is too long, inter-wiring noise may be applied to the pin, the pin voltage may become larger than VDD, causing malfunctioning.

Thus, carry out wiring to minimize inter-wiring noise. If the noise cannot be suppressed completely, carry out the following countermeasure against noise using an externally mounted component.

o Connect a diode with low VF (max 0.3 V)between VDDs

VDD

Diode with low VF

VDD

P00/INT4, RESET

o Connect acapacitor between VDDs

VDD

VDD

P00/INT4, RESET

10

μPD75112(A), 75116(A)

4.Memory Configuration

∙Program Memory (ROM)

12160 × 8 bits (0000H to 2F7FH): μPD75112(A)

16256 × 8 bits (0000H to 3F7FH): μPD75116(A)

∙0000H to 0001H: Vector table for writing the program start address by reset

∙0002H to 000BH: Vector table for writing the program start address by interrupt

∙0020H to 007FH: Table area to be referred to by the GETI instruction

∙Data Memory

∙Data area

512 × 4 bits (000H to 1FFH)

∙Peripheral hardware area 128 × 4 bits (F80H to FFFH)

	Figure 4-1 Program Memory Map (μPD75112(A))
	Address			0
		7	6
	0000H	MBE RBE Internal Reset Start Address		(High-Order 6 Bits)
			Internal Reset Start Address	(Low-Order 8 Bits)
	0002H	MBE RBE INTBT/INT4 Start Address		(High-Order 6 Bits)
			INTBT/INT4 Start Address	(Low-Order 8 Bits)
	0004H	MBE RBE INT0/INT1 Start Address		(High-Order 6 Bits)
			INT0/INT1 Start Address	(Low-Order 8 Bits)
	0006H	MBE RBE INTSIO Start Address		(High-Order 6 Bits)
			INTSIO Start Address	(Low-Order 8 Bits)		CALL !addr
	0008H	MBE RBE INTT0 Start Address		(High-Order 6 Bits)	CALLF	Instruction
						Subroutin
					! faddr
						Entry
			INTT0 Start Address	(Low-Order 8 Bits)	Instruction
						Address
					Entry
	000AH	MBE RBE INTT1 Start Address		(High-Order 6 Bits)
					Address
			INTT1 Start Address	(Low-Order 8 Bits)		BR !addr
						Instruction
		≈		≈		Branch
					BRCB	Address
					! caddr
					Instruction
					Branch
					Address	BR $addr
	0020H					Instruction
						Relative
			GETI Instruction Reference Table			Branch Address
						(-15 to +16)
	007FH	≈		≈
	0080H					Branch Address
	07FFH					Subroutine Entry
	0800H	≈		≈		Address by GETI
						Instruction
	0FFFH
	1000H	≈		≈
					BRCB !caddr Instruction
					Branch Address
	1FFFH
	2000H	≈		≈
					BRCB !caddr Instruction
					Branch Address
	2F7FH

Remarks: In all other cases, the program can be branched by the BR PCDE and BR PCXA

instructions to an address with only the lower 8 bits of PC changed.

11

	μPD75112(A), 75116(A)
	Figure 4-2 Program Memory Map (μPD75116(A))
	Address
		7	6	0
	0000H	MBE RBE Internal Reset Start Address		(High-Order 6 Bits)
			Internal Reset Start Address	(Low-Order 8 Bits)
	0002H	MBE RBE INTBT/INT4 Start Address		(High-Order 6 Bits)
			INTBT/INT4 Start Address	(Low-Order 8 Bits)
	0004H	MBE RBE INT0/INT1 Start Address		(High-Order 6 Bits)
			INT0/INT1 Start Address	(Low-Order 8 Bits)
	0006H	MBE RBE INTSIO Start Address		(High-Order 6 Bits)
			INTSIO Start Address	(Low-Order 8 Bits)		CALL !addr
	0008H	MBE RBE INTT0 Start Address		(High-Order 6 Bits)	CALLF	Instruction
						Subroutin
					! faddr
						Entry
			INTT0 Start Address	(High-Order 6 Bits)	Instruction
						Address
					Entry
	000AH	MBE RBE INTT1 Start Address		(High-Order 6 Bits)
					Address
			INTT1 Start Address	(Low-Order 8 Bits)		BR !addr
		≈		≈		Instruction
						Branch
					BRCB	Address
					! caddr
					Instruction
	0020H				Branch
			GETI Instruction Reference Table		Address	BR $addr
						Instruction
						Relative
	007FH					Branch Address
	0080H ≈			≈		(-15 to –1
						+2 to +16)
	07FFH
	0800H ≈			≈		Branch Address
	0FFFH					Subroutine Entry
						Address by GETI
	1000H
		≈		≈		Instruction
					BRCB !caddr Instrucion
					Branch Address
	1FFFH			≈
	2000H	≈			BRCB !caddr Instrucion
					Branch Address
	2FFFH
	3000H	≈		≈
					BRCB !caddr Instruction
					Branch Address
	3F7FH

Remarks: In all other cases, the program can be branched by the BR PCDE and BR PCXA instructions to an address with only the lower 8 bits of PC changed.

12

μPD75112(A), 75116(A)

Figure 4-3 Data Memory Map

							Data Memory	Memory Bank
				General		000H
						(32 × 4)
				Regoster Area
						01FH
								Bank 0
		Stack Area				256 × 4
Data Area
Static RAM
(512 × 4)

			0FFH
			100H
			256 × 4			Bank 1
			1FFH
				Not Incorporated
			F80H
Peripheral Hardware				128	× 4	Bank 15
Area
			FFFH

13

μPD75112(A), 75116(A)

5. Peripheral Hardware Functions

5.1 Digital Input/Output Port

The digital input/output port has the following tree types.

	∙ CMOS input (PORT0, 1)			:	8
	∙ CMOS input/output (PORT 2 to PORT 9)			: 32
	∙ N-ch open-drain input/output (PORT 12 to PORT 14):				12
			Total		52
Table 5-1 Functions of Digital Ports
Port (Code)		Functions	Operations and Features					Remarks
PORT0			Read or test always enable irrespectively of the operating mode
		4-bit input					Share the pins with SI, SO, SCK and
PORT1			of dual-function pins.				INT0 to 4.
PORT3		4-bit input/	Can be set bit-wise to the input or output mode.
PORT6		output
PORT2
			Can be set in 4-bit units to the input or output mode.				Port 2 shares the pin with PTO0,
PORT4			Ports 4 and 5, 6 and 7, 8 and 9 can form pairs and data can be				PTO1 and PCL.
PORT5			input/output in 8-bit units.
PORT7
PORT8
PORT9
PORT12		4-bit input/	Can be set in 4-bit units the input or output mode.				On-chip pull-up registers can be
PORT13		output	Ports 12 and 13 can form a pair and data can be input/output in 8-				specified bit-wise by mask option.
PORT14		(N-ch open-	bit units.
		drain, 12 V
		withstand
		voltage)

5.2 Clock Generator

The clock generator is a circuit which supplies the CPU and peripheral hardware with various clocks and controls the CPU operating mode.

The instruction execution time can be changed.

∙ 0.95 μs/1.91 μs/15.3 μs (at 4.19 MHz operation)

14

						μPD75112(A), 75116(A)
Figure 5-1 Block Diagram of Clock Generator
						ì
						· Basic Interval Timer (BT)
						ï
						· Clock Generator
						ï
						· Timer/Event Counter
						í
						ï· Serial Interface
						îï· Clock Output Circuit
					1/8 to 1/4096
		System	fxx or		Frequency Divider
		Clock
			fx
		Oscillator
				1/2	1/16
		Oscillation Stop				Frequency
						Divider
					Selec-	1/4	Φ
					tor
						ì	• CPU
	PCC					îí	• Clock Output Circuit
	PCC0
Inter-	PCC1
	4				HALT F/F
nal
Bus	PCC2				S
	HALT*
	PCC3
	STOP*				R	Q
	PCC2,
	PCC3	STOP F/F				Wait Release Signal from BT
	Crear
		Q	S			RES(Internal Reset) Signal
			R			Standby Release Signal from
						the Interrupt Control Circuit

Remarks 1: fXX=crystal/ceramic oscillator frequency. 2: fX=external clock frequency.

3: Φ=CPU clock

4: *indicates instruction execution.

5: PCC (processor clock control register)

6: 1 clock cycle (tCY) of Φ is 1 michine cycle of the instruction. For tCY, see the AC characteristics in the 11."Electrical Specifications".

15

μPD75112(A), 75116(A)

5.3 Clock Output Circuit

The clock output circuit is a circuit to generate clock pulses from the P22/PCL pin. It is used to supply the peripheral LSIs with clock pulses.

∙Clock output (PCL):Φ, 524 kHz, 262 kHz (at 4.19 MHz operation)

The clock output cicuit configuration is shown as the following.

Figure 5-2 Clock Output Circuit Configuration

	From the Clock
	Generator
	Φ
	fxx/2 3		Selector			Output Buffer
						P22/PCL
	fxx/2 4
					PORT2.2	PMGB Bit 2
					P22	Port 2 Input/
	CLOM3	0	CLOM1 CLOM0	CLOM		Output Mode
					Output Latch
						Specification Bit
			4
					Internal Bus

5.4 Basic Interval Timer

The basic interval timer has the following functions;

∙Interval timer operation to generate reference time interrupts

∙Watchdog timer application to detect program overrun

∙Wait time selection and count when the standby mode is released

∙Count content read

16

μPD75112(A), 75116(A)

Figure 5-3 Basic Interval Timer Configuration

From
the Clock
Generator					Clear		Clear
fxx/2 5
fxx/2 7					Basic Interval Timer	Set	BT Interrupt
			MPX
					(8-Bit Frequency Divider)		Request Flag
fxx/2	9							Vector
								Interrupt
						BT	IRQBT	Request
fxx/2 12								Signal
			3			Wait Release Signal
			3
						When the Standby Mode
						is Released
BTM3		BTM2	BTM1	BTM0	BTM

*SET1	4	8
		Internal Bus

Remark: * indicates instruction execution.

5.5 Timer/Event Counter

The μPD75116(A) has a two-channel on-chip timer/ event counters.

Channels 0 and 1 of the timer/event counter have the same configuration and functions. They differ only in the selectable count pulse (CP) and the function of supplying clocks to the serial interface.

The timer/event counter has the following functions:

∙Programmable interval timer operation

∙Output of square wave having any selected frequency to PTOn pin

∙Event counter operation

∙Use of TIn pin as an external interrupt input pin

∙Output of TIn pin input divided by N to PTOn pin (frequency divider operation)

∙Serial shift clock supply to the serial interface circuit (channel 0 only)

∙Count status read function

17