NEC UPD45128841G5-A10-9JF, UPD45128841G5-A10B-9JF, UPD45128441G5-A80-9JF, UPD45128841G5-A80-9JF, UPD45128841G5-A75-9JF Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD45128441, 45128841, 45128163

128M-bit Synchronous DRAM

4-bank, LVTTL

Description

The μPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.

The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

All inputs and outputs are synchronized with the positive edge of the clock.

The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).

These products are packaged in 54-pin TSOP (II).

Features

∙Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

∙Pulsed interface

∙Possible to assert random column address in every cycle

∙Quad internal banks controlled by BA0(A13) and BA1(A12)

∙Byte control (×16) by LDQM and UDQM

∙Programmable Wrap sequence (Sequential / Interleave)

∙Programmable burst length (1, 2, 4, 8 and full page)

∙Programmable /CAS latency (2 and 3)

∙Automatic precharge and controlled precharge

∙CBR (Auto) refresh and self refresh

∙×4, ×8, ×16 organization

∙Single 3.3 V ± 0.3 V power supply

∙LVTTL compatible inputs and outputs

∙4,096 refresh cycles / 64 ms

∙Burst termination by Burst stop command and Precharge command

The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

Document No. M12650EJBV0DS00 (11th edition)	The mark • shows major revised points.	©		1997

Date Published April 2000 NS CP (K)

Printed in Japan

μPD45128441, 45128841, 45128163

Ordering Information

	Part number	Organization	Clock frequency	Package
		(word × bit × bank)	MHz (MAX.)
	μPD45128441G5-A75-9JF	8M × 4 × 4	133	54-pin Plastic TSOP (II)
	μPD45128441G5-A80-9JF		125	(10.16mm (400))
	μPD45128441G5-A10-9JF		100
	μPD45128441G5-A10B-9JF		100
	μPD45128841G5-A75-9JF	4M × 8 × 4	133
	μPD45128841G5-A80-9JF		125
	μPD45128841G5-A10-9JF		100
	μPD45128841G5-A10B-9JF		100
	μPD45128163G5-A75-9JF	2M × 16 × 4	133
	μPD45128163G5-A80-9JF		125
	μPD45128163G5-A10-9JF		100
	μPD45128163G5-A10B-9JF		100

2	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

Part Number

[ x4, x8 ]

μPD45128841G5 - A75

NEC Memory

Synchronous DRAM

Memory density

128 : 128M bits

Organization

4 : x4

8 : x8

Number of banks

4 : 4 banks

Interface

1 : LVTTL

[ x16 ]	163

Organization

16 : x16

Number of banks and Interface

3 : 4 banks, LVTTL

Minimum cycle time

75 : 7.5 ns (133 MHz)

80 : 8 ns (125 MHz)

10 : 10 ns (100 MHz) 10B: 10 ns (100 MHz)

Low voltage

A : 3.3 V ± 0.3 V

Package

G5 : TSOP (II)

Data Sheet M12650EJBV0DS00

3

μPD45128441, 45128841, 45128163

Pin Configurations

/xxx indicates active low signal.

[μPD45128441]

54-pin Plastic TSOP (II) (10.16mm (400))

8M words × 4 bits × 4 banks

VCC	1	54	Vss
NC	2	53	NC
VCCQ	3	52	VssQ
NC	4	51	NC
DQ0	5	50	DQ3
VSSQ	6	49	VccQ
NC	7	48	NC
NC	8	47	NC
VCCQ	9	46	VssQ
NC	10	45	NC
DQ1	11	44	DQ2
VSSQ	12	43	VccQ
NC	13	42	NC
VCC	14	41	Vss
NC	15	40	NC
/WE	16	39	DQM
/CAS	17	38	CLK
/RAS	18	37	CKE
/CS	19	36	NC
BA0(A13)	20	35	A11
BA1(A12)	21	34	A9
A10	22	33	A8
A0	23	32	A7
A1	24	31	A6
A2	25	30	A5
A3	26	29	A4
VCC	27	28	Vss

A0 to A11 Note	: Address inputs
BA0(A13), BA1(A12): Bank select
DQ0 to DQ3	: Data inputs / outputs
CLK	: Clock input
CKE	: Clock enable
/CS	: Chip select
/RAS	: Row address strobe
/CAS	: Column address strobe
/WE	: Write enable
DQM	: DQ mask enable
VCC	: Supply voltage
VSS	: Ground
VCCQ	: Supply voltage for DQ	Note A0 to A11	: Row address inputs
VSSQ	: Ground for DQ	A0 to A9, A11 : Column address inputs
NC	: No connection

4	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

[μPD45128841]

54-pin Plastic TSOP (II) (10.16mm (400))

4M words × 8 bits × 4 banks

VCC	1	54	Vss
DQ0	2	53	DQ7
VCCQ	3	52	VssQ
NC	4	51	NC
DQ1	5	50	DQ6
VSSQ	6	49	VccQ
NC	7	48	NC
DQ2	8	47	DQ5
VCCQ	9	46	VssQ
NC	10	45	NC
DQ3	11	44	DQ4
VSSQ	12	43	VccQ
NC	13	42	NC
VCC	14	41	Vss
NC	15	40	NC
/WE	16	39	DQM
/CAS	17	38	CLK
/RAS	18	37	CKE
/CS	19	36	NC
BA0(A13)	20	35	A11
BA1(A12)	21	34	A9
A10	22	33	A8
A0	23	32	A7
A1	24	31	A6
A2	25	30	A5
A3	26	29	A4
VCC	27	28	Vss

A0 to A11 Note	: Address inputs
BA0(A13), BA1(A12): Bank select
DQ0 to DQ7	: Data inputs / outputs
CLK	: Clock input
CKE	: Clock enable
/CS	: Chip select
/RAS	: Row address strobe
/CAS	: Column address strobe
/WE	: Write enable
DQM	: DQ mask enable
VCC	: Supply voltage
VSS	: Ground	Note A0 to A11 : Row address inputs
VCCQ	: Supply voltage for DQ	A0 to A9 : Column address inputs
VSSQ	: Ground for DQ
NC	: No connection

Data Sheet M12650EJBV0DS00

5

μPD45128441, 45128841, 45128163

[μPD45128163]

54-pin Plastic TSOP (II) (10.16mm (400))

2M words × 16 bits × 4 banks

VCC	1	54	Vss
DQ0	2	53	DQ15
VCCQ	3	52	VssQ
DQ1	4	51	DQ14
DQ2	5	50	DQ13
VSSQ	6	49	VccQ
DQ3	7	48	DQ12
DQ4	8	47	DQ11
VCCQ	9	46	VssQ
DQ5	10	45	DQ10
DQ6	11	44	DQ9
VSSQ	12	43	VccQ
DQ7	13	42	DQ8
VCC	14	41	Vss
LDQM	15	40	NC
/WE	16	39	UDQM
/CAS	17	38	CLK
/RAS	18	37	CKE
/CS	19	36	NC
BA0(A13)	20	35	A11
BA1(A12)	21	34	A9
A10	22	33	A8
A0	23	32	A7
A1	24	31	A6
A2	25	30	A5
A3	26	29	A4
VCC	27	28	Vss

A0 to A11 Note	: Address inputs
BA0(A13), BA1(A12): Bank select
DQ0 to DQ15	: Data inputs / outputs
CLK	: Clock input
CKE	: Clock enable
/CS	: Chip select
/RAS	: Row address strobe
/CAS	: Column address strobe
/WE	: Write enable
LDQM	: Lower DQ mask enable
UDQM	: Upper DQ mask enable
VCC	: Supply voltage
VSS	: Ground	Note A0 to A11 : Row address inputs
VCCQ	: Supply voltage for DQ	A0 to A8 : Column address inputs
VSSQ	: Ground for DQ
NC	: No connection

6	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

Block Diagram
CLK	Clock
CKE	Generator
						Bank D
						Bank C
				Row		Bank B
Address
				Address
					Decoder	Bank A
				Refresh
				Buffer
			Mode	&
			Register	Counter	Row
/RAS		Decoder	Logic	Address		Sense Amplifier
/CS				Column		Column Decoder &
						Latch Circuit
		Command	Control				Output&Input	Buffer
				Buffer		CircuitLatch
/CAS				&
/WE				Burst		Data Control Circuit
				Counter

DQM

DQ

Data Sheet M12650EJBV0DS00

7

		μPD45128441, 45128841, 45128163
		CONTENTS
1.	Input / Output Pin Function ............................................................................................................		10
2.	Commands .......................................................................................................................................		11
3.	Simplified State Diagram ................................................................................................................		14
4.	Truth Table .......................................................................................................................................		15
	4.1	Command Truth Table.............................................................................................................................	15
	4.2	DQM Truth Table ......................................................................................................................................	15
	4.3	CKE Truth Table.......................................................................................................................................	15
	4.4	Operative Command Table ....................................................................................................................	16
	4.5 Command Truth Table for CKE .............................................................................................................		19
5.	Initialization ......................................................................................................................................		20
6.	Programming the Mode Register ...................................................................................................		21
7.	Mode Register ..................................................................................................................................		22
	7.1 Burst Length and Sequence ..................................................................................................................		23
8.	Address Bits of Bank-Select and Precharge ................................................................................		24
9.	Precharge .........................................................................................................................................		25
10.	Auto Precharge ................................................................................................................................		26
	10.1	Read with Auto Precharge ..................................................................................................................	26
	10.2	Write with Auto Precharge ..................................................................................................................	27
11. Read / Write Command Interval .....................................................................................................			28
	11.1	Read to Read Command Interval ........................................................................................................	28
	11.2	Write to Write Command Interval .......................................................................................................	28
	11.3	Write to Read Command Interval ........................................................................................................	29
	11.4	Read to Write Command Interval ........................................................................................................	30
12.	Burst Termination ...........................................................................................................................		31
	12.1	Burst Stop Command ..........................................................................................................................	31
	12.2	Precharge Termination ........................................................................................................................	32
		12.2.1 Precharge Termination in READ Cycle ....................................................................................	32
		12.2.2 Precharge Termination in WRITE Cycle ..................................................................................	33

8	Data Sheet M12650EJBV0DS00

		μPD45128441, 45128841, 45128163
13.	Electrical Specifications .................................................................................................................		34
	13.1	AC Parameters for Read Timing .........................................................................................................	39
	13.2	AC Parameters for Write Timing .........................................................................................................	41
	13.3	Relationship between Frequency and Latency .................................................................................	42
	13.4	Mode Register Set ................................................................................................................................	43
	13.5	Power on Sequence and CBR (Auto) Refresh ...................................................................................	44
	13.6	/CS Function .........................................................................................................................................	45
	13.7	Clock Suspension during Burst Read (using CKE Function) ..........................................................	46
	13.8	Clock Suspension during Burst Write (using CKE Function) ..........................................................	48
	13.9	Power Down Mode and Clock Mask ...................................................................................................	50
	13.10	CBR (Auto) Refresh .............................................................................................................................	51
	13.11	Self Refresh (Entry and Exit) ...............................................................................................................	52
	13.12	Random Column Read (Page with Same Bank) ................................................................................	53
	13.13	Random Column Write (Page with Same Bank) ................................................................................	55
	13.14	Random Row Read (Ping-Pong Banks) .............................................................................................	57
	13.15	Random Row Write (Ping-Pong Banks) .............................................................................................	59
	13.16	Read and Write .....................................................................................................................................	61
	13.17	Interleaved Column Read Cycle ..........................................................................................................	63
	13.18	Interleaved Column Write Cycle .........................................................................................................	65
	13.19	Auto Precharge after Read Burst ........................................................................................................	67
	13.20	Auto Precharge after Write Burst .......................................................................................................	69
	13.21	Full Page Read Cycle ...........................................................................................................................	71
	13.22	Full Page Write Cycle ...........................................................................................................................	73
	13.23	Byte Write Operation ............................................................................................................................	75
	13.24	Burst Read and Single Write (Option) ................................................................................................	77
	13.25	Full Page Random Column Read ........................................................................................................	79
	13.26	Full Page Random Column Write .......................................................................................................	81
	13.27	PRE (Precharge) Termination of Burst ...............................................................................................	83
14.	Package Drawing .............................................................................................................................		85
15.	Recommended Soldering Conditions ...........................................................................................		86
16.	Revision History ..............................................................................................................................		87

Data Sheet M12650EJBV0DS00

9

			μPD45128441, 45128841, 45128163
	1. Input / Output Pin Function
	Pin name	Input / Output	Function
	CLK	Input	CLK is the master clock input. Other inputs signals are referenced to the CLK rising
			edge.
	CKE	Input	CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge
			is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not
			issued and the μPD45128xxx suspends operation.
			When the μPD45128xxx is not in burst mode and CKE is negated, the device enters
			power down mode. During power down mode, CKE must remain low.
	/CS	Input	/CS low starts the command input cycle. When /CS is high, commands are ignored but
			operations continue.
	/RAS, /CAS, /WE	Input	/RAS, /CAS and /WE have the same symbols on conventional DRAM but different
			functions. For details, refer to the command table.
	A0 - A11	Input	Row Address is determined by A0 - A11 at the CLK (clock) rising edge in the active
			command cycle. It does not depend on the bit organization.
			Column Address is determined by A0 - A9, A11 at the CLK rising edge in the read or
			write command cycle. It depends on the bit organization: A0 - A9, A11 for ×4 device, A0
			- A9 for ×8 device, A0 - A8 for ×16 device.
			A10 defines the precharge mode. When A10 is high in the precharge command cycle,
			all banks are precharged; when A10 is low, only the bank selected by BA0(A13) and
			BA1(A12) is precharged.
			When A10 is high in read or write command cycle, the precharge starts automatically
			after the burst access.
	BA0, BA1	Input	BA0(A13) and BA1(A12) are the bank select signal. In command cycle, BA0(A13) and
			BA1(A12) low select bank A, BA0(A13) high and BA1(A12) low select bank B, BA0(A13)
			low and BA1(A12) high select bank C and then BA0(A13) and BA1(A12) high select
			bank D.
	DQM, UDQM, LDQM	Input	DQM controls I/O buffers. In ×16 products, UDQM and LDQM control upper byte and
			lower byte I/O buffers, respectively.
			In read mode, DQM controls the output buffers like a conventional /OE pin.
			DQM high and DQM low turn the output buffers off and on, respectively.
			The DQM latency for the read is two clocks.
			In write mode, DQM controls the word mask. Input data is written to the memory cell if
			DQM is low but not if DQM is high.
			The DQM latency for the write is zero.
	DQ0 - DQ15	Input / Output	DQ pins have the same function as I/O pins on a conventional DRAM.
	VCC, VSS, VCCQ, VSSQ	(Power supply)	VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power
			supply pins for the output buffers.

10	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

2. Commands

Mode register set command

(/CS, /RAS, /CAS, /WE = Low)

The μPD45128xxx has a mode register that defines how the device operates. In this command, A0 through A11, BA0(A13) and BA1(A12) are the data input pins. After power on, the mode register set command must be executed to initialize the device.

The mode register can be set only when all banks are in idle state. During 2 CLK (tRSC) following this command, the μPD45128xxx

cannot accept any other commands.

Activate command

(/CS, /RAS = Low, /CAS, /WE = High)

The μPD45128xxx has four banks, each with 4,096 rows. This command activates the bank selected by BA0(A13) and

BA1(A12) and a row address selected by A0 through A11.

This command corresponds to a conventional DRAM’s /RAS falling.

Fig.1 Mode register set command

CLK CKE H /CS /RAS /CAS /WE

BA0(A13), BA1(A12)

A10

Add

Fig.2 Row address strobe and bank activate command

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0(A13), BA1(A12)

A10 Row

Add Row

Precharge command

(/CS, /RAS, /WE = Low, /CAS = High)

This command begins precharge operation of the bank selected by BA0(A13) and BA1(A12). When A10 is High, all banks are precharged, regardless of BA0(A13) and BA1(A12). When A10 is Low, only the bank selected by BA0(A13) and BA1(A12) is precharged.

After this command, the μPD45128xxx can’t accept the activate command to the precharging bank during tRP (precharge to activate command period).

This command corresponds to a conventional DRAM’s /RAS rising.

Fig.3 Precharge command

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0(A13), BA1(A12)

A10

(Precharge select)

Add

Data Sheet M12650EJBV0DS00

11

μPD45128441, 45128841, 45128163

Write command	Fig.4 Column address and write command
(/CS, /CAS, /WE = Low, /RAS = High)	CLK
	CKE	H

If the mode register is in the burst write mode, this command sets the burst start address given by the column address to begin the burst write operation. The first write data in burst mode can input with this command with subsequent data on following clocks.

/CS

/RAS

/CAS

/WE

BA0(A13), BA1(A12)

A10

Add Col.

Read command

(/CS, /CAS = Low, /RAS, /WE = High)

Read data is available after /CAS latency requirements have been met. This command sets the burst start address given by the column address.

Fig.5 Column address and read command

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0(A13), BA1(A12)

A10

Add Col.

CBR (auto) refresh command

(/CS, /RAS, /CAS = Low, /WE, CKE = High)

This command is a request to begin the CBR (auto) refresh operation. The refresh address is generated internally.

Before executing CBR (auto) refresh, all banks must be precharged. After this cycle, all banks will be in the idle (precharged) state and

ready for a row activate command.

During tRC period (from refresh command to refresh or activate command), the μPD45128xxx cannot accept any other command.

Fig.6 CBR (auto) refresh command

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0(A13), BA1(A12)

A10

Add

12	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

Self refresh entry command

(/CS, /RAS, /CAS, CKE = Low, /WE = High)

After the command execution, self refresh operation continues while CKE remains low. When CKE goes high, the μPD45128xxx exits the self refresh mode.

During self refresh mode, refresh interval and refresh operation are performed internally, so there is no need for external control.

Before executing self refresh, all banks must be precharged.

Burst stop command

(/CS, /WE = Low, /RAS, /CAS = High)

This command can stop the current burst operation.

Fig.7 Self refresh entry command

CLK

CKE

/CS

/RAS

/CAS

/WE

BA0(A13), BA1(A12)

A10

Add

Fig.8 Burst stop command in Full Page

Mode

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0(A13), BA1(A12)

A10

Add

No operation

(/CS = Low, /RAS, /CAS, /WE = High)

This command is not an execution command. No operations begin or terminate by this command.

Fig.9 No operation

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0(A13), BA1(A12)

A10

Add

Data Sheet M12650EJBV0DS00

13

μPD45128441, 45128841, 45128163

3. Simplified State Diagram

Self

Refresh

SELF

exit

Mode

MRS

SELF

IDLE

REF

CBR (Auto)

Register

Refresh

Set

CKE

ACT

CKE

Power

Down

CKE

Active

ROW

Power

ACTIVE

CKE

Down

BST

BST

Read

Write

Write

precharge

Auto

Read

with

Read

Write

precharge

PRE

with

Auto

CKE

Read

CKE

WRITE

WRITE

READ

READ

SUSPEND

SUSPEND

Write

CKE

CKE

CKE

termination)

CKE

READA

WRITEA

WRITEA

PRE

READA

SUSPEND

SUSPEND

CKE

CKE

(Precharge

termination)

(Precharge

PRE

POWER

Precharge

Precharge

ON

Automatic sequence

Manual input

14	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

4. Truth Table

4.1 Command Truth Table

Function

Symbol

CKE

/CS

/RAS

/CAS

/WE

BA1,

A10

A11,

n – 1

n

BA0

A9 - A0

Device deselect

DESL

H

×

H

×

×

×

×

×

×

No operation

NOP

H

×

L

H

H

H

×

×

×

Burst stop

BST

H

×

L

H

H

L

×

×

×

Read

READ

H

×

L

H

L

H

V

L

V

Read with auto precharge

READA

H

×

L

H

L

H

V

H

V

Write

WRIT

H

×

L

H

L

L

V

L

V

Write with auto precharge

WRITA

H

×

L

H

L

L

V

H

V

Bank activate

ACT

H

×

L

L

H

H

V

V

V

Precharge select bank

PRE

H

×

L

L

H

L

V

L

×

Precharge all banks

PALL

H

×

L

L

H

L

×

H

×

Mode register set

MRS

H

×

L

L

L

L

L

L

V

Remark H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input

4.2 DQM Truth Table

Function

Symbol

CKE

DQM

n – 1

n

U

L

Data write / output enable

ENB

H

×

L

Data mask / output disable

MASK

H

×

H

Upper byte write enable / output enable

ENBU

H

×

L

×

Lower byte write enable / output enable

ENBL

H

×

×

L

Upper byte write inhibit / output disable

MASKU

H

×

H

×

Lower byte write inhibit / output disable

MASKL

H

×

×

H

Remark H = High level, L = Low level, × = High or Low level (Don't care)

4.3 CKE Truth Table

Current state

Function

Symbol

CKE

/CS

/RAS

/CAS

/WE

Address

n – 1

n

Activating

Clock suspend mode entry

H

L

×

×

×

×

×

Any

Clock suspend mode

L

L

×

×

×

×

×

Clock suspend

Clock suspend mode exit

L

H

×

×

×

×

×

Idle

CBR (auto) refresh command

REF

H

H

L

L

L

H

×

Idle

Self refresh entry

SELF

H

L

L

L

L

H

×

Self refresh

Self refresh exit

L

H

L

H

H

H

×

L

H

H

×

×

×

×

Idle

Power down entry

H

L

×

×

×

×

×

Power down

Power down exit

L

H

H

×

×

×

×

L

H

L

H

H

H

×

Remark H = High level, L = Low level, × = High or Low level (Don't care)

Data Sheet M12650EJBV0DS00

15

μPD45128441, 45128841, 45128163

4.4 Operative Command Table Note1								(1/3)
Current state	/CS	/RAS	/CAS	/WE	Address	Command	Action	Notes
Idle	H	×	×	×	×	DESL	Nop or power down	2
	L	H	H	×	×	NOP or BST	Nop or power down	2
	L	H	L	H	BA, CA, A10	READ/READA	ILLEGAL	3
	L	H	L	L	BA, CA, A10	WRIT/WRITA	ILLEGAL	3
	L	L	H	H	BA, RA	ACT	Row activating
	L	L	H	L	BA, A10	PRE/PALL	Nop
	L	L	L	H	×	REF/SELF	CBR (auto) refresh or self refresh	4
	L	L	L	L	Op-Code	MRS	Mode register accessing
Row active	H	×	×	×	×	DESL	Nop
	L	H	H	×	×	NOP or BST	Nop
	L	H	L	H	BA, CA, A10	READ/READA	Begin read : Determine AP	5
	L	H	L	L	BA, CA, A10	WRIT/WRITA	Begin write : Determine AP	5
	L	L	H	H	BA, RA	ACT	ILLEGAL	3
	L	L	H	L	BA, A10	PRE/PALL	Precharge	6
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL
Read	H	×	×	×	×	DESL	Continue burst to end → Row active
	L	H	H	H	×	NOP	Continue burst to end → Row active
	L	H	H	L	×	BST	Burst stop → Row active
	L	H	L	H	BA, CA, A10	READ/READA	Terminate burst, new read : Determine AP	7
	L	H	L	L	BA, CA, A10	WRIT/WRITA	Terminate burst, start write : Determine AP	7, 8
	L	L	H	H	BA, RA	ACT	ILLEGAL	3
	L	L	H	L	BA, A10	PRE/PALL	Terminate burst, precharging
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL
Write	H	×	×	×	×	DESL	Continue burst to end → Write recovering
	L	H	H	H	×	NOP	Continue burst to end → Write recovering
	L	H	H	L	×	BST	Burst stop → Row active
	L	H	L	H	BA, CA, A10	READ/READA	Terminate burst, start read : Determine AP	7, 8
	L	H	L	L	BA, CA, A10	WRIT/WRITA	Terminate burst, new write : Determine AP	7
	L	L	H	H	BA, RA	ACT	ILLEGAL	3
	L	L	H	L	BA, A10	PRE/PALL	Terminate burst, precharging	9
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL

16	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

								(2/3)
Current state	/CS	/RAS	/CAS	/WE	Address	Command	Action	Notes
Read with auto	H	×	×	×	×	DESL	Continue burst to end → Precharging
precharge	L	H	H	H	×	NOP	Continue burst to end → Precharging
	L	H	H	L	×	BST	ILLEGAL
	L	H	L	H	BA, CA, A10	READ/READA	ILLEGAL	3
	L	H	L	L	BA, CA, A10	WRIT/WRITA	ILLEGAL	3
	L	L	H	H	BA, RA	ACT	ILLEGAL	3
	L	L	H	L	BA, A10	PRE/PALL	ILLEGAL	3
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL
Write with auto	H	×	×	×	×	DESL	Continue burst to end → Write
precharge							recovering with auto precharge
	L	H	H	H	×	NOP	Continue burst to end → Write
							recovering with auto precharge
	L	H	H	L	×	BST	ILLEGAL
	L	H	L	H	BA, CA, A10	READ/READA	ILLEGAL	3
	L	H	L	L	BA, CA, A10	WRIT/WRITA	ILLEGAL	3
	L	L	H	H	BA, RA	ACT	ILLEGAL	3
	L	L	H	L	BA, A10	PRE/PALL	ILLEGAL	3
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL
Precharging	H	×	×	×	×	DESL	Nop → Enter idle after tRP
	L	H	H	H	×	NOP	Nop → Enter idle after tRP
	L	H	H	L	×	BST	ILLEGAL
	L	H	L	H	BA, CA, A10	READ/READA	ILLEGAL	3
	L	H	L	L	BA, CA, A10	WRIT/WRITA	ILLEGAL	3
	L	L	H	H	BA, RA	ACT	ILLEGAL	3
	L	L	H	L	BA, A10	PRE/PALL	Nop → Enter idle after tRP
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL
Row activating	H	×	×	×	×	DESL	Nop → Enter bank active after tRCD
	L	H	H	H	×	NOP	Nop → Enter bank active after tRCD
	L	H	H	L	×	BST	ILLEGAL
	L	H	L	H	BA, CA, A10	READ/READA	ILLEGAL	3
	L	H	L	L	BA, CA, A10	WRIT/WRITA	ILLEGAL	3
	L	L	H	H	BA, RA	ACT	ILLEGAL	3, 10
	L	L	H	L	BA, A10	PRE/PALL	ILLEGAL	3
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL

Data Sheet M12650EJBV0DS00

17

μPD45128441, 45128841, 45128163

								(3/3)
Current state	/CS	/RAS	/CAS	/WE	Address	Command	Action	Notes
Write recovering	H	×	×	×	×	DESL	Nop → Enter row active after tDPL
	L	H	H	H	×	NOP	Nop → Enter row active after tDPL
	L	H	H	L	×	BST	Nop → Enter row active after tDPL
	L	H	L	H	BA, CA, A10	READ/READA	Start read, Determine AP	8
	L	H	L	L	BA, CA, A10	WRIT/WRITA	New write, Determine AP
	L	L	H	H	BA, RA	ACT	ILLEGAL	3
	L	L	H	L	BA, A10	PRE/PALL	ILLEGAL	3
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL
Write recovering	H	×	×	×	×	DESL	Nop → Enter precharge after tDPL
with auto precharge	L	H	H	H	×	NOP	Nop → Enter precharge after tDPL
	L	H	H	L	×	BST	Nop → Enter precharge after tDPL
	L	H	L	H	BA, CA, A10	READ/READA	ILLEGAL	3, 8
	L	H	L	L	BA, CA, A10	WRIT/WRITA	ILLEGAL	3
	L	L	H	H	BA, RA	ACT	ILLEGAL	3
	L	L	H	L	BA, A10	PRE/PALL	ILLEGAL
	L	L	L	H	×	REF/SELF	ILLEGAL
	L	L	L	L	Op-Code	MRS	ILLEGAL
Refreshing	H	×	×	×	×	DESL	Nop → Enter idle after tRC
	L	H	H	×	×	NOP/BST	Nop → Enter idle after tRC
	L	H	L	×	×	READ/WRIT	ILLEGAL
	L	L	H	×	×	ACT/PRE/PALL	ILLEGAL
	L	L	L	×	×	REF/SELF/MRS	ILLEGAL
Mode register	H	×	×	×	×	DESL	Nop → Enter idle after tRSC
accessing	L	H	H	H	×	NOP	Nop → Enter idle after tRSC
	L	H	H	L	×	BST	ILLEGAL
	L	H	L	×	×	READ/WRIT	ILLEGAL
	L	L	×	×	×	ACT/PRE/PALL/	ILLEGAL
						REF/SELF/MRS

Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle.

2.If all banks are idle, and CKE is inactive (Low level), μPD45128xxx will enter Power down mode. All input buffers except CKE will be disabled.

3.Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank.

4.If all banks are idle, and CKE is inactive (Low level), μPD45128xxx will enter Self refresh mode. All input buffers except CKE will be disabled.

5.Illegal if tRCD is not satisfied.

6.Illegal if tRAS is not satisfied.

7.Must satisfy burst interrupt condition.

8.Must satisfy bus contention, bus turn around, and/or write recovery requirements.

9.Must mask preceding data which don't satisfy tDPL.

10.Illegal if tRRD is not satisfied.

Remark H = High level, L = Low level, × = High or Low level (Don’t care), V = Valid data

18	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

4.5 Command Truth Table for CKE

Current State		CKE		/CS	/RAS	/CAS	/WE	Address	Action	Notes
	n – 1		n
Self refresh	H		×	×	×	×	×	×	INVALID, CLK (n – 1) would exit self refresh
	L		H	H	×	×	×	×	Self refresh recovery
	L		H	L	H	H	×	×	Self refresh recovery
	L		H	L	H	L	×	×	ILLEGAL
	L		H	L	L	×	×	×	ILLEGAL
	L		L	×	×	×	×	×	Maintain self refresh
Self refresh recovery	H		H	H	×	×	×	×	Idle after tRC
	H		H	L	H	H	×	×	Idle after tRC
	H		H	L	H	L	×	×	ILLEGAL
	H		H	L	L	×	×	×	ILLEGAL
	H		L	H	×	×	×	×	ILLEGAL
	H		L	L	H	H	×	×	ILLEGAL
	H		L	L	H	L	×	×	ILLEGAL
	H		L	L	L	×	×	×	ILLEGAL
Power down	H		×	×	×	×	×		INVALID, CLK (n – 1) would exit power down
	L		H	H	×	×	×	×	EXIT power down → Idle
	L		H	L	H	H	H	×	EXIT power down → Idle
	L		L	×	×	×	×	×	Maintain power down mode
All banks idle	H		H	H	×	×	×		Refer to operations in Operative Command Table
	H		H	L	H	×	×		Refer to operations in Operative Command Table
	H		H	L	L	H	×		Refer to operations in Operative Command Table
	H		H	L	L	L	H	×	CBR (auto) Refresh
	H		H	L	L	L	L	Op-Code	Refer to operations in Operative Command Table
	H		L	H	×	×	×		Refer to operations in Operative Command Table
	H		L	L	H	×	×		Refer to operations in Operative Command Table
	H		L	L	L	H	×		Refer to operations in Operative Command Table
	H		L	L	L	L	H	×	Self refresh	1
	H		L	L	L	L	L	Op-Code	Refer to operations in Operative Command Table
	L		×	×	×	×	×	×	Power down	1
Row active	H		×	×	×	×	×	×	Refer to operations in Operative Command Table
	L		×	×	×	×	×	×	Power down	1
Any state other than	H		H	×	×	×	×		Refer to operations in Operative Command Table
listed above	H		L	×	×	×	×	×	Begin clock suspend next cycle	2
	L		H	×	×	×	×	×	Exit clock suspend next cycle
	L		L	×	×	×	×	×	Maintain clock suspend

Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all banks idle or row active state.

2. Must be legal command as defined in Operative Command Table.

Remark H = High level, L = Low level, × = High or Low level (Don't care)

Data Sheet M12650EJBV0DS00

19

μPD45128441, 45128841, 45128163

5. Initialization

The synchronous DRAM is initialized in the power-on sequence according to the following.

(1)To stabilize internal circuits, when power is applied, a 100 μs or longer pause must precede any signal toggling.

(2)After the pause, all banks must be precharged using the Precharge command (The Precharge all banks command is convenient).

(3)Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed. After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.

(4)Two or more CBR (Auto) refresh must be performed.

Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.

2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.

20	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

6. Programming the Mode Register

The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0(A13) and BA1(A12) as data inputs. The register retains data until it is reprogrammed or the device loses power.

The mode register has four fields;

Options	: A11 through A7, BA0(A13), BA1(A12)
/CAS latency	: A6 through A4
Wrap type	:	A3
Burst length	:	A2 through A0

Following mode register programming, no command can be issued before at least 2 CLK have elapsed.

/CAS Latency

/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse before the data will be available.

The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of

the device.

Burst Length

Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is completed, the output bus will become Hi-Z.

The burst length is programmable as 1, 2, 4, 8 or full page.

Wrap Type (Burst Sequence)

The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either “Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.

Some microprocessor cache systems are optimized for sequential addressing and others for interleaved addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them. Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.

Data Sheet M12650EJBV0DS00

21

μPD45128441, 45128841, 45128163

7. Mode Register

BA0

BA1

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

(A13) (A12)

0

0

0

0

0

1

JEDEC Standard Test Set (refresh counter test)

0

BA0

BA1

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

(A13) (A12)

x

x

x

x

LTMODE

WT

BL

Burst Read and Single Write

1

0

0

BA0

BA1

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

(for Write Through Cache)

(A13) (A12)

Use in future

1

0

BA0

BA1

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

(A13) (A12)

x

x

x

x

x

V

V

V

V

V

V

V

Vender Specific

1

1

BA0

BA1

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

V = Valid

(A13) (A12)

x = Don’t care

0

0

0

0

0

0

0

LTMODE

WT

BL

Mode Register Set

Bits2-0

WT = 0

WT = 1

000

1

1

001

2

2

010

4

4

Burst length

011

8

8

100

R

R

101

R

R

110

R

R

111

Full page

R

Wrap type

0

Sequential

1

Interleave

Bits6-4

/CAS latency

000

R

001

R

010

2

Latency

011

3

mode

100

R

101

R

110

R

111

R

Remark R : Reserved

Mode Register Set Timing

CLK

CKE

/CS

/RAS

/CAS

/WE

A0 - A11,

BA0(13), BA1(A12)

Mode Register Set

22	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

7.1 Burst Length and Sequence

[Burst of Two]

Starting address	Sequential addressing sequence	Interleave addressing sequence
(column address A0, binary)	(decimal)	(decimal)
0	0, 1	0, 1
1	1, 0	1, 0

[Burst of Four]

Starting address	Sequential addressing sequence	Interleave addressing sequence
(column address A1 - A0, binary)	(decimal)	(decimal)
00	0, 1, 2, 3	0, 1, 2, 3
01	1, 2, 3, 0	1, 0, 3, 2
10	2, 3, 0, 1	2, 3, 0, 1
11	3, 0, 1, 2	3, 2, 1, 0

[Burst of Eight]

Starting address	Sequential addressing sequence	Interleave addressing sequence
(column address A2 - A0, binary)	(decimal)	(decimal)
000	0, 1, 2, 3, 4, 5, 6, 7	0, 1, 2, 3, 4, 5, 6, 7
001	1, 2, 3, 4, 5, 6, 7, 0	1, 0, 3, 2, 5, 4, 7, 6
010	2, 3, 4, 5, 6, 7, 0, 1	2, 3, 0, 1, 6, 7, 4, 5
011	3, 4, 5, 6, 7, 0, 1, 2	3, 2, 1, 0, 7, 6, 5, 4
100	4, 5, 6, 7, 0, 1, 2, 3	4, 5, 6, 7, 0, 1, 2, 3
101	5, 6, 7, 0, 1, 2, 3, 4	5, 4, 7, 6, 1, 0, 3, 2
110	6, 7, 0, 1, 2, 3, 4, 5	6, 7, 4, 5, 2, 3, 0, 1
111	7, 0, 1, 2, 3, 4, 5, 6	7, 6, 5, 4, 3, 2, 1, 0

Full page burst is an extension of the above tables of sequential addressing, with the length being 2,048 (for 32M ×4 device), 1,024 (for 16M ×8 device), and 512 (for 8M ×16 device).

Data Sheet M12650EJBV0DS00

23

μPD45128441, 45128841, 45128163

8. Address Bits of Bank-Select and Precharge

Row

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

BA1

BA0

BA1(A12)

BA0(A13)

Result

(A12)

(A13)

0

0

Select Bank A

(Activate command)

“Activate” command

0

1

Select Bank B

“Activate” command

1

0

Select Bank C

“Activate” command

1

1

Select Bank D

“Activate” command

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

BA1

BA0

(A12)

(A13)

(Precharge command)

A10

BA1(A12)

BA0(A13)

Result

0

0

0

Precharge Bank A

0

0

1

Precharge Bank B

0

1

0

Precharge Bank C

0

1

1

Precharge Bank D

1

x

x

Precharge All Banks

x : Don’t care

0

disables Auto-Precharge

(End of Burst)

enables Auto-Precharge

Col.

A0

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

x

BA1

BA0

1

(End of Burst)

(A12)

(A13)

(/CAS strobes)

Result

BA1(A12)

BA0(A13)

0

0

enables Read/Write

commands for Bank A

0

1

enables Read/Write

commands for Bank B

1

0

enables Read/Write

commands for Bank C

1

1

enables Read/Write

commands for Bank D

24	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

9. Precharge

The precharge command can be issued anytime after tRAS (MIN.) is satisfied.

Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters

the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge.

The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is

as follows.

It is depending on the /CAS latency and clock cycle time.

								Burst length=4
T0	T1	T2	T3	T4	T5	T6	T7	T8
CLK
/CAS latency = 2
Command	READ				PRE
DQ			Q1	Q2	Q3	Q4		Hi-Z
/CAS latency = 3
Command	READ				PRE
DQ				Q1	Q2	Q3	Q4	Hi-Z

(tRAS must be satisfied)

In order to write all data to the memory cell correctly, the asynchronous parameter “tDPL” must be satisfied. The tDPL

(MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is calculated by dividing tDPL (MIN.) with clock cycle time.

In summary, the precharge command can be issued relative to reference clock that indicates the last data word is

valid. In the following table, minus means clocks before the reference; plus means time after the reference.

/CAS latency	Read	Write
2	–1	+tDPL (MIN.)
3	–2	+tDPL (MIN.)

Data Sheet M12650EJBV0DS00

25

μPD45128441, 45128841, 45128163

10. Auto Precharge

During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is selected and begins automatically.

The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the next activate command to the bank being precharged cannot be executed until the precharge cycle ends.

In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been satisfied.

In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged. The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode

register and whether read or write cycle.

10.1 Read with Auto Precharge

During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS latency of 3) the last data word output.

								Burst length = 4
T0	T1	T2	T3	T4	T5	T6	T7	T8	T9
CLK
/CAS latency = 2
Command	READA B			Auto precharge starts
DQ			QB1	QB2	QB3	QB4			Hi-Z
/CAS latency = 3
Command	READA B			Auto precharge starts
DQ				QB1	QB2	QB3	QB4		Hi-Z

(tRAS must be satisfied)

Remark READA means Read with Auto precharge

26	Data Sheet M12650EJBV0DS00

μPD45128441, 45128841, 45128163

10.2 Write with Auto Precharge

During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (MIN.) after the last

data word input to the device.

							Burst length = 4
T0	T1	T2	T3	T4	T5	T6	T7	T8
CLK
/CAS latency = 2				Auto precharge starts
Command	WRITA B
DQ	DB1	DB2	DB3	DB4			Hi-Z
				tDPL(MIN.)
/CAS latency = 3
Command	WRITA B			Auto precharge starts
DQ	DB1	DB2	DB3	DB4			Hi-Z

tDPL(MIN.)

(tRAS must be satisfied)

Remark WRITA means Write with Auto Precharge

In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid. In the table below, minus means clocks before the reference; plus means after the reference.

/CAS latency	Read	Write
2	–1	+tDPL (MIN.)
3	–2	+tDPL (MIN.)

Data Sheet M12650EJBV0DS00

27

μPD45128441, 45128841, 45128163

11. Read / Write Command Interval

11.1 Read to Read Command Interval

During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous read operation does not completed. READ will be interrupted by another READ.

The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock without any restriction.

Burst length = 4, /CAS latency = 2

T0

T1

T2

T3

T4

T5

T6

T7

T8

T9

CLK

Command

READ A READ B

Hi-Z

DQ

QA1

QB1

QB2

QB3

QB4

1cycle

11.2 Write to Write Command Interval

During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will begin with a new Write command. WRITE will be interrupted by another WRITE.

The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock without any restriction.

						Burst length = 4, /CAS latency = 2
T0	T1	T2	T3	T4	T5	T6	T7	T8

CLK

Command	WRITE A	WRITE B
					Hi-Z
DQ	DA1	DB1	DB2	DB3	DB4

1cycle

28	Data Sheet M12650EJBV0DS00