Loading...NEC uPD78F4218AYGF-3BA, uPD78F4218AGF-3BA, uPD78F4218AYGC-8EU, uPD78F4218AGC-8EU, uPD78F4216AYGF-3BA Datasheet
...
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
16-BIT SINGLE-CHIP MICROCONTROLLERS
DESCRIPTION
The μPD78F4216A/78F4218A and 78F4216AY/78F4218AY are products of μPD784216A/784218A,
784216AY/784218AY Subseries in the 78K/IV Series.
The μPD78F4216A/78F4218A have flash memory in place of the internal ROM of the μPD784216A/784218A. The
incorporation of flash memory allows a program to be written or erased while mounted on the target board.
The μPD78F4216AY/78F4218AY are based on the μPD78F4216A/78F4218A Subseries with the addition of a multimaster-supporting I2C bus interface.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
μPD784216A, 784216AY Subseries User’s Manual Hardware: U13570E
μPD784218A, 784218AY Subseries User’s Manual Hardware: U12970E
78K/IV Series User’s Manual Instructions: |
U10905E |
FEATURES
∙Pin compatible with the mask ROM products
∙Flash memory: 128 KB (μPD78F4216A/78F4216AY)
256 KB (μPD78F4218A/78F4218AY)
∙ Internal RAM: 8,192 bytes (μPD78F4216A/78F4216AY) 12,800 bytes (μPD78F4218A/78F4218AY)
∙ Supply voltage: VDD = 1.9 to 5.5 V
APPLICATIONS
Cellular phones, PHS, cordless telephones, CD-ROM, AV equipment
Unless otherwise specified, references in this document to the μPD78F4218AY refer to the μPD78F4216A,
78F4218A, 78F4216AY, and 78F4218AY.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U14125EJ1V0DS00 (1st edition) |
|
2000 |
|
Date Published November 2000 N CP(K)
Printed in Japan
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
ORDERING INFORMATION
Part Number |
Package |
Internal ROM (Bytes) |
Internal RAM (Bytes) |
μPD78F4216AGC-8EU |
100-pin plastic LQFP |
128 K |
8,192 |
|
(fine pitch) (14 × 14) |
|
|
μPD78F4216AGF-3BA |
100-pin plastic QFP |
128 K |
8,192 |
|
(14 × 20) |
|
|
μPD78F4218AGC-8EU |
100-pin plastic LQFP |
256 K |
12,800 |
|
(fine pitch) (14 × 14) |
|
|
μPD78F4218AGF-3BA |
100-pin plastic QFP |
256 K |
12,800 |
|
(14 × 20) |
|
|
μPD78F4216AYGC-8EU |
100-pin plastic LQFP |
128 K |
8,192 |
|
(fine pitch) (14 × 14) |
|
|
μPD78F4216AYGF-3BA |
100-pin plastic QFP |
128 K |
8,192 |
|
(14 × 20) |
|
|
μPD78F4218AYGC-8EU |
100-pin plastic LQFP |
256 K |
12,800 |
|
(fine pitch) (14 × 14) |
|
|
μPD78F4218AYGF-3BA |
100-pin plastic QFP |
256 K |
12,800 |
|
(14 × 20) |
|
|
2 |
Data Sheet U14125EJ1V0DS00 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
78K/IV SERIES LINEUP
: Products in mass-production
: Products under development
Standard models
PD784026
Enhanced A/D converter,
16-bit timer, and power management
ASSP models
PD784956A
For DC inverter control
PD784908
On-chip IEBusTM controller
PD784915
Software servo control
On-chip analog circuit for VCRs Enhanced timer
PD784976
On-chip VFD controller/driver
Supports I2C bus
PD784038Y
PD784038
Enhanced internal memory capacity Pin-compatible with the PD784026
Supports multimaster I2C bus
PD784216AY
PD784216A
100-pin, enhanced I/O and internal memory capacity
PD784054
PD784046
On-chip 10-bit A/D converter
PD784938A
Enhanced functions of thePD784908, enhanced internal memory capacity, ROM correction added.
Supports multimaster I2C bus
PD784928Y
PD784928
Enhanced functions of the PD784915
Supports multimaster I2C bus
PD784225Y
PD784225
80-pin, ROM correction added
Supports multimaster I2C bus
PD784218AY
PD784218A
Enhanced internal memory capacity, ROM correction added
PD784967
Enhanced functions of thePD784938A, enhanced I/O and internal memory capacity.
Data Sheet U14125EJ1V0DS00 |
3 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
OVERVIEW OF FUNCTIONS (1/2)
|
|
Part Number |
|
μPD78F4216A, |
|
μPD78F4218A, |
|
Item |
|
|
μPD78F4216AY |
|
μPD78F4218AY |
||
|
|
|
|
|
|
|
|
Number of basic instructions (mnemonics) |
113 |
|
|
|
|||
|
|
|
|
||||
General-purpose registers |
8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory |
||||||
|
|
|
mapping) |
|
|
|
|
|
|
|
|
|
|||
Minimum instruction execution time |
∙ |
160 ns/320 ns/640 ns/1,280 ns/2,560 ns (@fXX = 12.5 MHz operation with |
|||||
|
|
|
|
main system clock) |
|
|
|
|
|
|
∙ |
61 μs (@fXT = 32.768 kHz operation with subsystem clock) |
|||
|
|
|
|
|
|
|
|
Internal |
Flash memory |
128 KB |
|
256 KB |
|
||
memory |
|
|
|
|
|
|
|
RAM |
8,192 bytes |
|
12,800 bytes |
||||
|
|
|
|||||
|
|
|
|
|
|
||
Memory space |
|
1 MB with program and data spaces combined |
|
||||
|
|
|
|
|
|
|
|
I/O ports |
Total |
86 |
|
|
|
||
|
|
|
|
|
|
|
|
|
|
CMOS input |
8 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CMOS I/O |
72 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
N-ch open-drain I/O |
6 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Pins with |
Pins with pull-up resistor |
70 |
|
|
|
|
|
additional |
|
|
|
|
|
|
|
LED direct drive output |
22 |
|
|
|
||
|
functionsNote 1 |
|
|
|
|||
|
|
|
|
|
|
|
|
|
Middle-voltage pin |
6 |
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
Real-time output port |
4 bits × 2 or 8 bits × 1 |
|
|
|
|||
|
|
|
|
||||
Timer/event counter |
Timer/event counter: |
Timer counter × 1 |
Pulse output |
||||
|
|
|
(16-bit) |
Capture/compare register × 2 |
∙ PPG output |
||
|
|
|
|
|
|
|
∙ Square wave output |
|
|
|
|
|
|
|
∙ One-shot pulse output |
|
|
|
|
|
|||
|
|
|
Timer/event counter 1: Timer counter × 1 |
Pulse output |
|||
|
|
|
(8-bit) |
Compare register × 1 |
∙ PWM output |
||
|
|
|
|
|
|
|
∙ Square wave output |
|
|
|
|
|
|||
|
|
|
Timer/event counter 2: Timer counter × 1 |
Pulse output |
|||
|
|
|
(8-bit) |
Compare register × 1 |
∙ PWM output |
||
|
|
|
|
|
|
|
∙ Square wave output |
|
|
|
|
|
|||
|
|
|
Timer/event counter 5: Timer counter × 1 |
Pulse output |
|||
|
|
|
(8-bit) |
Compare register × 1 |
∙ PWM output |
||
|
|
|
|
|
|
|
∙ Square wave output |
|
|
|
|
|
|||
|
|
|
Timer/event counter 6: Timer counter × 1 |
Pulse output |
|||
|
|
|
(8-bit) |
Compare register × 1 |
∙ PWM output |
||
|
|
|
|
|
|
|
∙ Square wave output |
|
|
|
|
|
|||
|
|
|
Timer/event counter 7: Timer counter × 1 |
Pulse output |
|||
|
|
|
(8-bit) |
Compare register × 1 |
∙ PWM output |
||
|
|
|
|
|
|
|
∙ Square wave output |
|
|
|
|
|
|||
|
|
|
Timer/event counter 8: Timer counter × 1 |
Pulse output |
|||
|
|
|
(8-bit) |
Compare register × 1 |
∙ PWM output |
||
|
|
|
|
|
|
|
∙ Square wave output |
|
|
|
|
||||
Serial interface |
|
∙ |
UART/IOE (3-wire serial I/O): 2 channels (on-chip baud rate generator) |
||||
|
|
|
∙ CSI (3-wire serial I/O, multimaster supporting I2C busNote 2): 1 channel |
||||
A/D converter |
|
8-bit resolution × 8 channels |
|
||||
|
|
|
|
||||
D/A converter |
|
8-bit resolution × 2 channels |
|
||||
|
|
|
|
|
|
|
|
Notes 1. Pins with additional functions are included with the I/O pins.
2. μPD78F4216AY, 78F4218AY only
4 |
Data Sheet U14125EJ1V0DS00 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
OVERVIEW OF FUNCTIONS (2/2)
|
Part Number |
|
μPD78F4216A, |
|
μPD78F4218A, |
Item |
|
|
μPD78F4216AY |
|
μPD78F4218AY |
|
|
|
|
||
Clock output |
|
Selectable from fXX, fXX/2, fXX/22, fXX/23, fXX/24, fXX/25, fXX/26, fXX/27, fXT |
|||
Buzzer output |
|
Selectable from fXX/210, fXX/211, fXX/212, fXX/213 |
|
||
Watch timer |
|
1 channel |
|
||
|
|
|
|
||
Watchdog timer |
|
1 channel |
|
||
|
|
|
|
|
|
Standby |
|
∙ |
HALT/STOP/IDLE modes |
|
|
|
|
∙ |
In low power consumption mode (with subsystem clock): HALT/IDLE modes |
||
|
|
|
|
||
Interrupt |
Hardware sources |
29 (internal: 20, external: 9) |
|
||
|
|
|
|
||
|
Software sources |
BRK instruction, BRKCS instruction, operand error |
|
||
|
|
|
|
||
|
Non-maskable |
Internal: 1, external: 1 |
|
||
|
|
|
|
||
|
Maskable |
Internal: 19, external: 8 |
|
||
|
|
|
|
|
|
|
|
∙ |
4 programmable priority levels |
|
|
|
|
∙ |
3 service modes: Vectored interrupt/macro service/context switching |
||
|
|
|
|
||
Supply voltage |
|
VDD = 1.9 to 5.5 V |
|
||
|
|
|
|
||
Package |
|
100-pin plastic LQFP (fine pitch) (14 × 14) |
|
||
|
|
100-pin plastic QFP (14 × 20) |
|
||
|
|
|
|
|
|
Data Sheet U14125EJ1V0DS00 |
5 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
CONTENTS
1.DIFFERENCES AMONG MODELS IN μPD784216A/784216AY, 784218A/784218AY
|
SUBSERIES ............................................................................................................................................. |
7 |
|
2. |
PIN CONFIGURATION (TOP VIEW) ................................................................................................... |
8 |
|
3. |
BLOCK DIAGRAM ............................................................................................................................... |
11 |
|
4. |
PIN FUNCTIONS .................................................................................................................................. |
12 |
|
|
4.1 |
Port Pins ..................................................................................................................................... |
12 |
|
4.2 |
Non-Port Pins ............................................................................................................................. |
14 |
|
4.3 |
Pin I/O Circuits and Recommended Connections of Unused Pins ....................................... |
16 |
5. |
INTERNAL MEMORY SIZE SWITCHING REGISTER (IMS) ................................................................ |
20 |
|
6. |
PROGRAMMING FLASH MEMORY..................................................................................................... |
22 |
|
|
6.1 |
Selecting Communication Mode .............................................................................................. |
22 |
|
6.2 |
Flash Memory Programming Function .................................................................................... |
23 |
|
6.3 |
Connecting Flashpro ll and Flashpro lll ................................................................................... |
24 |
7. |
ELECTRICAL SPECIFICATIONS ........................................................................................................ |
25 |
|
8. |
PACKAGE DRAWINGS ....................................................................................................................... |
47 |
|
9. |
RECOMMENDED SOLDERING CONDITIONS .................................................................................. |
49 |
|
APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ |
50 |
||
APPENDIX B. RELATED DOCUMENTS ................................................................................................ |
53 |
||
6 |
Data Sheet U14125EJ1V0DS00 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
1. DIFFERENCES AMONG MODELS IN μPD784216A/784216AY, 784218A/784218AY SUBSERIES
The only difference among the μPD784214A, 784215A, 784216A, 784217A, and 784218A lies in the internal memory capacity.
The μPD784214AY, 784215AY, 784216AY, 784217AY, and 784218AY are models with the addition of an I2C bus control function.
The μPD78F4216A, 78F4216AY, 78F4218A, and 78F4218AY are provided with a 128 KB/256 KB flash memory instead of the mask ROM of the above models.
These differences are summarized in Table 1-1.
Table 1-1. Differences Among Models in μPD784216A/784216AY, 784218A/784218AY Subseries
Part Number |
μPD784214A, |
μPD784215A, |
μPD784216A, |
μPD784217A, |
μPD784218A, |
μPD78F4216A, |
μPD78F4218A, |
Item |
μPD784214AY |
μPD784215AY |
μPD784216AY |
μPD784217AY |
μPD784218AY |
μPD78F4216AY |
μPD78F4218AY |
|
|
|
|
|
|
|
|
Internal ROM |
96 KB |
128 KB (Mask ROM) |
192 KB |
256 KB |
128 KB |
256 KB |
|
|
(Mask |
|
|
(Mask |
(Mask |
(Flash |
(Flash |
|
ROM) |
|
|
ROM) |
ROM) |
memory) |
memory) |
|
|
|
|
|
|
|
|
Internal RAM |
3,584 bytes |
5,120 bytes |
8,192 bytes |
12,800 bytes |
|
8,192 |
12,800 |
|
|
|
|
|
|
bytes |
bytes |
|
|
|
|
|
|
|
|
Internal memory size |
Not provided |
|
|
|
|
ProvidedNote |
|
switching register |
|
|
|
|
|
|
|
(IMS) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ROM correction |
Not provided |
|
|
Provided |
|
Not |
Provided |
|
|
|
|
|
|
provided |
|
|
|
|
|
|
|
|
|
External access status |
Not provided |
|
|
Provided |
|
Not |
Provided |
function |
|
|
|
|
|
provided |
|
|
|
|
|
|
|
|
|
Supply voltage |
VDD = 1.8 to 5.5 V |
|
|
|
VDD = 1.9 to 5.5 V |
||
|
|
|
|
|
|
||
Electrical |
Refer to the data sheet for each device. |
|
|
|
|
||
specifications |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Recommended |
|
|
|
|
|
|
|
soldering conditions |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
EXA pin |
Not provided |
|
|
Provided |
|
Not |
Provided |
|
|
|
|
|
|
provided |
|
|
|
|
|
|
|
|
|
TEST pin |
Provided |
|
|
|
|
Not provided |
|
|
|
|
|
|
|
|
|
VPP pin |
Not provided |
|
|
|
|
Provided |
|
|
|
|
|
|
|
|
|
Note The internal flash memory capacity and internal RAM capacity can be changed using the internal memory
size switching register (IMS).
Caution There are differences in noise immunity and noise radiation between the flash memory and mask ROM versions. When pre-producing an application set with the flash memory version and then mass-producing it with the mask ROM version, be sure to conduct sufficient evaluations on the commercial samples (not engineering samples) of the mask ROM version.
Data Sheet U14125EJ1V0DS00 |
7 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
2.PIN CONFIGURATION (TOP VIEW)
∙100-pin plastic LQFP (fine pitch) (14 × 14)
μPD78F4216AGC-8EU, μPD78F4218AGC-8EU, μPD78F4216AYGC-8EU, μPD78F4218AYGC-8EU
|
P95 |
P94 P93 P92 P91 |
P90 |
VPP |
P37/EXA |
P36/TI01 P35/TI00 P34/TI2 |
P33/TI1 P32/TO2 P31/TO1 P30/TO0 P103/TI8/TO8 P102/TI7/TO7 |
P101/TI6/TO6 P100/TI5/TO5 |
VDD |
P67/ASTB |
P66/WAIT |
P65/WR |
P64/RD |
P63/A19 |
|
|
|
|
|
5 Note |
|
|
|
|
|
|
|
|
|
|
|
|
|
Note1 |
|
|
|
|
|
|
|
|
|
|
|
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 |
|||||||||||||
P120/RTP0 |
1 |
|
|
|
|
|
|
|
|
|
|
|
|
75 |
P121/RTP1 |
2 |
|
|
|
|
|
|
|
|
|
|
|
|
74 |
P122/RTP2 |
3 |
|
|
|
|
|
|
|
|
|
|
|
|
73 |
P123/RTP3 |
4 |
|
|
|
|
|
|
|
|
|
|
|
|
72 |
P124/RTP4 |
5 |
|
|
|
|
|
|
|
|
|
|
|
|
71 |
P125/RTP5 |
6 |
|
|
|
|
|
|
|
|
|
|
|
|
70 |
P126/RTP6 |
7 |
|
|
|
|
|
|
|
|
|
|
|
|
69 |
P127/RTP7 |
8 |
|
|
|
|
|
|
|
|
|
|
|
|
68 |
VDD |
9 |
|
|
|
|
|
|
|
|
|
|
|
|
67 |
X2 |
10 |
|
|
|
|
|
|
|
|
|
|
|
|
66 |
X1 |
11 |
|
|
|
|
|
|
|
|
|
|
|
|
65 |
VSS |
12 |
|
|
|
|
|
|
|
|
|
|
|
|
64 |
XT2 |
13 |
|
|
|
|
|
|
|
|
|
|
|
|
63 |
XT1 |
14 |
|
|
|
|
|
|
|
|
|
|
|
|
62 |
RESET |
15 |
|
|
|
|
|
|
|
|
|
|
|
|
61 |
P00/INTP0 |
16 |
|
|
|
|
|
|
|
|
|
|
|
|
60 |
P01/INTP1 |
17 |
|
|
|
|
|
|
|
|
|
|
|
|
59 |
P02/INTP2/NMI |
18 |
|
|
|
|
|
|
|
|
|
|
|
|
58 |
P03/INTP3 |
19 |
|
|
|
|
|
|
|
|
|
|
|
|
57 |
P04/INTP4 |
20 |
|
|
|
|
|
|
|
|
|
|
|
|
56 |
P05/INTP5 |
21 |
|
|
|
|
|
|
|
|
|
|
|
|
55 |
P06/INTP6 |
22 |
|
|
|
|
|
|
|
|
|
|
|
|
54 |
AVDDNote 2 |
23 |
|
|
|
|
|
|
|
|
|
|
|
|
53 |
AVREF0 |
24 |
|
|
|
|
|
|
|
|
|
|
|
|
52 |
P10/ANI0 |
25 |
|
|
|
|
|
|
|
|
|
|
|
|
51 |
|
26 |
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
||||||||||||
|
P11/ANI1 |
P12/ANI2 P13/ANI3 P14/ANI4 P15/ANI5 |
P16/ANI6 |
P17/ANI7 |
AVSS |
P130/ANO0 P131/ANO1 AVREF1 |
P70/RxD2/SI2 P71/TxD2/SO2 P72/ASCK2/SCK2 P20/RxD1/SI1 P21/TxD1/SO1 P22/ASCK1/SCK1 |
P23/PCL P24/BUZ |
P25/SI0/SDA0 |
P26/SO0 |
P27/SCK0/SCL0 |
P80/A0 |
P81/A1 |
P82/A2 |
|
|
|
|
|
Note3 |
|
|
|
Note4 |
|
Note4 |
|
|
|
P62/A18
P61/A17
P60/A16
VSS
P57/A15
P56/A14
P55/A13
P54/A12
P53/A11
P52/A10
P51/A9
P50/A8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P43/AD3
P42/AD2
P41/AD1
P40/AD0
P87/A7
P86/A6
P85/A5
P84/A4
P83/A3
Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ.
2.Connect the AVDD pin to VDD.
3.Connect the AVSS pin to VSS.
4.The SCL0 and SDA0 pins are available in the μPD78F4216AY, 78F4218AY only.
5.The EXA pin is available in the μPD78F4218A, 78F4218AY only.
8 |
Data Sheet U14125EJ1V0DS00 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
∙100-pin plastic QFP (14 × 20)
μPD78F4216AGF-3BA, μPD78F4218AGF-3BA, μPD78F4216AYGF-3BA, μPD78F4218AYGF-3BA
|
VSS |
P57/A15 P56/A14 |
P55/A13 |
P54/A12 P53/A11 P52/A10 P51/A9 P50/A8 P47/AD7 P46/AD6 P45/AD5 P44/AD4 |
P43/AD3 |
P42/AD2 P41/AD1 P40/AD0 P87/A7 P86/A6 |
P85/A5 |
|
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 |
||||||
P60/A16 |
1 |
|
|
|
|
|
80 |
P61/A17 |
2 |
|
|
|
|
|
79 |
P62/A18 |
3 |
|
|
|
|
|
78 |
P63/A19 |
4 |
|
|
|
|
|
77 |
P64/RD |
5 |
|
|
|
|
|
76 |
P65/WR |
6 |
|
|
|
|
|
75 |
P66/WAIT |
7 |
|
|
|
|
|
74 |
P67/ASTB |
8 |
|
|
|
|
|
73 |
VDD |
9 |
|
|
|
|
|
72 |
P100/TI5/TO5 |
10 |
|
|
|
|
|
71 |
P101/TI6/TO6 |
11 |
|
|
|
|
|
70 |
P102/TI7/TO7 |
12 |
|
|
|
|
|
69 |
P103/TI8/TO8 |
13 |
|
|
|
|
|
68 |
P30/TO0 |
14 |
|
|
|
|
|
67 |
P31/TO1 |
15 |
|
|
|
|
|
66 |
P32/TO2 |
16 |
|
|
|
|
|
65 |
P33/TI1 |
17 |
|
|
|
|
|
64 |
P34/TI2 |
18 |
|
|
|
|
|
63 |
P35/TI00 |
19 |
|
|
|
|
|
62 |
P36/TI01 |
20 |
|
|
|
|
|
61 |
P37/EXANote 5 |
21 |
|
|
|
|
|
60 |
VPPNote 1 |
22 |
|
|
|
|
|
59 |
P90 |
23 |
|
|
|
|
|
58 |
P91 |
24 |
|
|
|
|
|
57 |
P92 |
25 |
|
|
|
|
|
56 |
P93 |
26 |
|
|
|
|
|
55 |
P94 |
27 |
|
|
|
|
|
54 |
P95 |
28 |
|
|
|
|
|
53 |
P120/RTP0 |
29 |
|
|
|
|
|
52 |
P121/RTP1 |
30 |
|
|
|
|
|
51 |
|
31 |
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 |
|||||
|
P122/RTP2 |
P123/RTP3 P124/RTP4 |
P125/RTP5 |
P126/RTP6 P127/RTP7 VDD X2 X1 VSS XT2 XT1 RESET |
P00/INTP0 |
P01/INTP1 P02/INTP2/NMI P03/INTP3 P04/INTP4 P05/INTP5 |
P06/INTP6 |
P84/A4
P83/A3
P82/A2
P81/A1
P80/A0
P27/SCK0/SCL0Note 4
P26/SO0
P25/SI0/SDA0Note 4
P24/BUZ
P23/PCL
P22/ASCK1/SCK1
P21/TxD1/SO1
P20/RxD1/SI1
P72/ASCK2/SCK2
P71/TxD2/SO2
P70/RxD2/SI2
AVREF1
P131/ANO1
P130/ANO0
AVSSNote 3
P17/ANI7
P16/ANI6
P15/ANI5
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
AVREF0
AVDDNote 2
Notes 1. Connect the VPP pin to VSS directly or via a pull-down resistor in normal operation mode. Connect the VPP pin to VSS via a pull-down resistor in a system in which the on-chip flash memory is written while mounted on the target board. For the pull-down connection, it is recommended to use a resistor with a resistance ranging from 470 Ω to 10 kΩ.
2.Connect the AVDD pin to VDD.
3.Connect the AVSS pin to VSS.
4.The SCL0 and SDA0 pins are available in the μPD78F4216AY, 78F4218AY only.
5.The EXA pin is available in the μPD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00 |
9 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
A0 to A19: |
Address Bus |
P120 to P127: |
Port 12 |
|||||||
AD0 to AD7: |
Address/Data Bus |
P130, P131: |
Port 13 |
|||||||
ANI0 to ANI7: |
Analog Input |
PCL: |
Programmable Clock |
|||||||
ANO0, ANO1: |
Analog Output |
|
|
|
|
|
|
|
|
Read Strobe |
RD: |
||||||||||
ASCK1, ASCK2: |
Asynchronous Serial Clock |
|
|
|
|
|
|
|
Reset |
|
RESET: |
||||||||||
ASTB: |
Address Strobe |
RTP0 to RTP7: |
Real-time Output Port |
|||||||
AVDD: |
Analog Power Supply |
RxD1, RxD2: |
Receive Data |
|||||||
AVREF0, AVREF1: |
Analog Reference Voltage |
|
|
|
to |
|
|
Serial Clock |
||
SCK0 |
SCK2: |
|||||||||
AVSS: |
Analog Ground |
SCL0Note 1: |
Serial Clock |
|||||||
BUZ: |
Buzzer Clock |
SDA0Note 1: |
Serial Data |
|||||||
EXANote 2: |
External Access Status Output |
SI0 to SI2: |
Serial Input |
|||||||
INTP0 to INTP6: |
Interrupt from Peripherals |
SO0 to SO2: |
Serial Output |
|||||||
NMI: |
Non-maskable Interrupt |
TI00, TI01, |
|
|||||||
P00 to P06: |
Port 0 |
TI1, TI2, TI5 to TI8: |
Timer Input |
|||||||
P10 to P17: |
Port 1 |
TO0 to TO2, TO5 to TO8: Timer Output |
||||||||
P20 to P27: |
Port 2 |
TxD1, TxD2: |
Transmit Data |
|||||||
P30 to P37: |
Port 3 |
VDD: |
Power Supply |
|||||||
P40 to P47: |
Port 4 |
VPP: |
Programming Power Supply |
|||||||
P50 to P57: |
Port 5 |
VSS: |
Ground |
|||||||
P60 to P67: |
Port 6 |
|
|
|
Wait |
|||||
WAIT: |
||||||||||
P70 to P72: |
Port 7 |
|
|
Write Strobe |
||||||
WR: |
||||||||||
P80 to P87: |
Port 8 |
X1, X2: |
Crystal (Main System Clock) |
|||||||
P90 to P95: |
Port 9 |
XT1, XT2: |
Crystal (Subsystem Clock) |
|||||||
P100 to P103: |
Port 10 |
|
|
|
|
|
|
|
|
|
Notes 1. The SCL0 and SDA0 pins are available in the μPD78F4216AY, 78F4218AY only.
2. The EXA pin is available in the μPD78F4218A, 78F4218AY only.
10 |
Data Sheet U14125EJ1V0DS00 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
3. BLOCK DIAGRAM
INTP2/NMI |
|
|
|
Programmable |
|
|
|||
INTP0, INTP1, |
interrupt |
|||
INTP3 to INTP6 |
controller |
|||
|
|
|
||
TI00 |
|
|
|
Timer/event |
|
|
|||
TI01 |
|
|
|
counter |
|
|
|||
TO0 |
|
|
(16 bits) |
|
|
|
|||
|
|
|
|
|
|
|
|
|
Timer/event |
TI1 |
counter 1 |
|||
TO1 |
|
|
||
|
(8 bits) |
|||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Timer/event |
TI2 |
counter 2 |
|||
TO2 |
|
|
||
|
(8 bits) |
|||
|
|
|
|
|
Timer/event TI5/TO5 
counter 5
(8 bits)
Timer/event TI6/TO6 
counter 6
(8 bits)
Timer/event TI7/TO7 
counter 7
(8 bits)
Timer/event TI8/TO8 
counter 8
(8 bits)
|
|
|
Watch timer |
|
|
|
|
|
|
|
|
|
|
|
Watchdog timer |
RTP0 to RTP7 |
|
||
|
|||
Real-time |
|||
NMI/INTP2 |
|
|
output port |
|
|||
|
|
|
|
ANO0 |
|
|
ANO1 |
D/A |
|
AVREF1 |
||
converter |
||
AVSS |
||
|
||
P03/INTP3 |
|
|
ANI0 to ANI7 |
A/D |
|
AVREF0 |
||
converter |
||
AVDD |
||
AVSS |
|
|
PCL |
Clock output |
|
control |
||
|
||
BUZ |
Buzzer output |
78K/IV |
|
Flash |
CPU core |
|
memory |
|
|
|
RAM
UART/IOE1
Baud-rate generator
UART/IOE2
Baud-rate generator
Clocked serial interface
Bus I/F
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
Port 8
Port 9
Port 10
Port 12
Port 13
System control
RxD1/SI1
TxD1/SO1
ASCK1/SCK1
RxD2/SI2
TxD2/SO2
ASCK2/SCK2
SI0/SDA0Note 1
SO0
SCK0/SCL0Note 1
AD0 to AD7
A0 to A7
A8 to A15
A16 to A19
RD
WR
WAIT
ASTB
EXANote 2
P00 to P06
P10 to P17
P20 to P27
P30 to P37
P40 to P47
P50 to P57
P60 to P67
P70 to P72
P80 to P87
P90 to P95
P100 to P103
P120 to P127 
P130, P131
RESET
X1
X2
XT1
XT2
VDD
VSS
VPP
Notes 1. This function supports the I2C bus interface and is available in the μPD78F4216AY, 78F4218AY only.
2. The EXA pin is available in the μPD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00 |
11 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4. |
PIN FUNCTIONS |
|
|
|
|
||
4.1 |
Port Pins (1/2) |
|
|
|
|
||
|
|
|
|
|
|
|
|
|
Pin Name |
|
I/O |
Alternate Function |
Function |
||
|
|
|
|
|
|
|
|
P00 |
|
I/O |
INTP0 |
Port 0 (P0): |
|||
|
|
|
|
|
|
|
∙ 7-bit I/O port |
P01 |
|
|
INTP1 |
||||
|
|
∙ Input/output can be specified in 1-bit units. |
|||||
|
|
|
|
|
|
|
|
P02 |
|
|
INTP2/NMI |
||||
|
|
∙ Whether specifying input mode or output mode, an on-chip pull-up |
|||||
|
|
|
|
|
|
|
|
P03 |
|
|
INTP3 |
resistor can be specified in 1-bit units by means of software. |
|||
|
|
|
|
|
|
|
|
P04 |
|
|
INTP4 |
|
|||
|
|
|
|
|
|
|
|
P05 |
|
|
INTP5 |
|
|||
|
|
|
|
|
|
|
|
P06 |
|
|
INTP6 |
|
|||
|
|
|
|
|
|
|
|
P10 to P17 |
|
Input |
ANI0 to ANI7 |
Port 1 (P1): |
|||
|
|
|
|
|
|
|
∙ 8-bit input only port |
|
|
|
|
|
|
|
|
P20 |
|
I/O |
RxD1/SI1 |
Port 2 (P2): |
|||
|
|
|
|
|
|
|
∙ 8-bit I/O port |
P21 |
|
|
TxD1/SO1 |
||||
|
|
∙ Input/output can be specified in 1-bit units. |
|||||
|
|
|
|
|
|
|
|
P22 |
|
|
|
|
|
||
|
|
ASCK1/SCK1 |
|
∙ Whether specifying input mode or output mode, an on-chip pull-up |
|||
|
|
|
|
|
|
|
|
P23 |
|
|
PCL |
resistor can be specified in 1-bit units by means of software. |
|||
|
|
|
|
|
|
|
|
P24 |
|
|
BUZ |
|
|||
|
|
|
|
|
|
|
|
P25 |
|
|
SI0/SDA0Note 1 |
|
|||
|
|
|
|
|
|
|
|
P26 |
|
|
SO0 |
|
|||
|
|
|
|
|
|
|
|
P27 |
|
|
SCK0/SCL0Note 1 |
|
|||
P30 |
|
I/O |
TO0 |
Port 3 (P3): |
|||
|
|
|
|
|
|
|
∙ 8-bit I/O port |
P31 |
|
|
TO1 |
||||
|
|
∙ Input/output can be specified in 1-bit units. |
|||||
|
|
|
|
|
|
|
|
P32 |
|
|
TO2 |
||||
|
|
∙ Whether specifying input mode or output mode, an on-chip pull-up |
|||||
|
|
|
|
|
|
|
|
P33 |
|
|
TI1 |
resistor can be specified in 1-bit units by means of software. |
|||
|
|
|
|
|
|
|
|
P34 |
|
|
TI2 |
|
|||
|
|
|
|
|
|
|
|
P35 |
|
|
TI00 |
|
|||
|
|
|
|
|
|
|
|
P36 |
|
|
TI01 |
|
|||
|
|
|
|
|
|
|
|
P37 |
|
|
EXANote 2 |
|
|||
P40 to P47 |
|
I/O |
AD0 to AD7 |
Port 4 (P4): |
|||
|
|
|
|
|
|
|
∙ 8-bit I/O port |
|
|
|
|
|
|
|
∙ Input/output can be specified in 1-bit units. |
|
|
|
|
|
|
|
∙ When used as an input port, an on-chip pull-up resistor can be |
|
|
|
|
|
|
|
specified by means of software. |
|
|
|
|
|
|
|
∙ LEDs can be driven directly. |
|
|
|
|
|
|
|
|
P50 to P57 |
|
I/O |
A8 to A15 |
Port 5 (P5): |
|||
|
|
|
|
|
|
|
∙ 8-bit I/O port |
|
|
|
|
|
|
|
∙ Input/output can be specified in 1-bit units. |
|
|
|
|
|
|
|
∙ When used as an input port, an on-chip pull-up resistor can be |
|
|
|
|
|
|
|
specified by means of software. |
|
|
|
|
|
|
|
∙ LEDs can be driven directly. |
|
|
|
|
|
|
|
|
Notes 1. |
This SDA0 and SCL0 are available in the μPD78F4216AY, 78F4218AY only. |
||||||
2.This function is available in the μPD78F4218A, 784218AY only.
12 |
Data Sheet U14125EJ1V0DS00 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.1 Port Pins (2/2)
Pin Name |
I/O |
|
|
Alternate Function |
Function |
||||
|
|
|
|
|
|
|
|
|
|
P60 |
I/O |
|
A16 |
Port 6 (P6): |
|||||
|
|
|
|
|
|
|
|
|
∙ 8-bit I/O port |
P61 |
|
|
A17 |
||||||
|
|
∙ Input/output can be specified in 1-bit units. |
|||||||
|
|
|
|
|
|
|
|
|
|
P62 |
|
|
A18 |
||||||
|
|
∙ When used as an input port, an on-chip pull-up resistor can be |
|||||||
|
|
|
|
|
|
|
|
|
|
P63 |
|
|
A19 |
specified by means of software. |
|||||
|
|
|
|
|
|
|
|
|
|
P64 |
|
|
|
|
|
|
|
|
|
|
|
RD |
|
||||||
|
|
|
|
|
|
|
|
|
|
P65 |
|
|
|
|
|
|
|
||
|
|
WR |
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
P66 |
|
|
|
|
|
|
|||
|
|
WAIT |
|
|
|
|
|||
|
|
|
|
|
|
|
|
|
|
P67 |
|
|
ASTB |
|
|||||
|
|
|
|
|
|
|
|
|
|
P70 |
I/O |
|
RxD2/SI2 |
Port 7 (P7): |
|||||
|
|
|
|
|
|
|
|
|
∙ 3-bit I/O port |
P71 |
|
|
TxD2/SO2 |
||||||
|
|
∙ Input/output can be specified in 1-bit units. |
|||||||
|
|
|
|
|
|
|
|
|
|
P72 |
|
|
|
|
|
|
|
|
|
|
|
ASCK2/SCK2 |
|
∙ Whether specifying input mode or output mode, an on-chip pull-up |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
resistor can be specified in 1-bit units by means of software. |
|
|
|
|
|
|
|
|
|
|
P80 to P87 |
I/O |
|
A0 to A7 |
Port 8 (P8): |
|||||
|
|
|
|
|
|
|
|
|
∙ 8-bit I/O port |
|
|
|
|
|
|
|
|
|
∙ Input/output can be specified in 1-bit units. |
|
|
|
|
|
|
|
|
|
∙ Whether specifying input mode or output mode, an on-chip pull-up |
|
|
|
|
|
|
|
|
|
resistor can be specified in 1-bit units by means of software. |
|
|
|
|
|
|
|
|
|
∙ The interrupt control flag (KRIF) is set to 1 when a falling edge is |
|
|
|
|
|
|
|
|
|
detected at a pin of this port. |
|
|
|
|
|
|
|
|
|
|
P90 to P95 |
I/O |
|
|
|
|
|
− |
Port 9 (P9): |
|
|
|
|
|
|
|
|
|
|
∙ N-ch open-drain middle-voltage I/O port |
|
|
|
|
|
|
|
|
|
∙ 6-bit I/O port |
|
|
|
|
|
|
|
|
|
∙ Input/output can be specified in 1-bit units. |
|
|
|
|
|
|
|
|
|
∙ LEDs can be driven directly. |
|
|
|
|
|
|
|
|
|
|
P100 |
I/O |
|
TI5/TO5 |
Port 10 (P10): |
|||||
|
|
|
|
|
|
|
|
|
∙ 4-bit I/O port |
P101 |
|
|
TI6/TO6 |
||||||
|
|
∙ Input/output can be specified in 1-bit units. |
|||||||
|
|
|
|
|
|
|
|
|
|
P102 |
|
|
TI7/TO7 |
||||||
|
|
∙ Whether specifying input mode or output mode, an on-chip pull-up |
|||||||
|
|
|
|
|
|
|
|
|
|
P103 |
|
|
TI8/TO8 |
resistor can be specified in 1-bit units by means of software. |
|||||
|
|
|
|
|
|
|
|
|
|
P120 to P127 |
I/O |
|
RTP0 to RTP7 |
Port 12 (P12): |
|||||
|
|
|
|
|
|
|
|
|
∙ 8-bit I/O port |
|
|
|
|
|
|
|
|
|
∙ Input/output can be specified in 1-bit units. |
|
|
|
|
|
|
|
|
|
∙ Whether specifying input mode or output mode, an on-chip pull-up |
|
|
|
|
|
|
|
|
|
resistor can be specified in 1-bit units by means of software. |
|
|
|
|
|
|
|
|
|
|
P130, P131 |
I/O |
|
ANO0, ANO1 |
Port 13 (P13): |
|||||
|
|
|
|
|
|
|
|
|
∙ 2-bit I/O port |
|
|
|
|
|
|
|
|
|
∙ Input/output can be specified in 1-bit units. |
|
|
|
|
|
|
|
|
|
|
Data Sheet U14125EJ1V0DS00 |
13 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.2 Non-Port Pins (1/2)
Pin Name |
I/O |
Alternate Function |
Function |
|
|
|
|
TI00 |
Input |
P35 |
External count clock input to 16-bit timer counter |
|
|
|
|
TI01 |
|
P36 |
Capture trigger signal input to capture/compare register 00 |
|
|
|
|
TI1 |
|
P33 |
External count clock input to 8-bit timer counter 1 |
|
|
|
|
TI2 |
|
P34 |
External count clock input to 8-bit timer counter 2 |
|
|
|
|
TI5 |
|
P100/TO5 |
External count clock input to 8-bit timer counter 5 |
|
|
|
|
TI6 |
|
P101/TO6 |
External count clock input to 8-bit timer counter 6 |
|
|
|
|
TI7 |
|
P102/TO7 |
External count clock input to 8-bit timer counter 7 |
|
|
|
|
TI8 |
|
P103/TO8 |
External count clock input to 8-bit timer counter 8 |
|
|
|
|
TO0 |
Output |
P30 |
16-bit timer output (shared by 14-bit PWM output) |
|
|
|
|
TO1 |
|
P31 |
8-bit timer output (shared by 8-bit PWM output) |
|
|
|
|
TO2 |
|
P32 |
|
|
|
|
|
TO5 |
|
P100/TI5 |
|
|
|
|
|
TO6 |
|
P101/TI6 |
|
|
|
|
|
TO7 |
|
P102/TI7 |
|
|
|
|
|
TO8 |
|
P103/TI8 |
|
|
|
|
|
RxD1 |
Input |
P20/SI1 |
Serial data input (UART1) |
|
|
|
|
RxD2 |
|
P70/SI2 |
Serial data input (UART2) |
|
|
|
|
TxD1 |
Output |
P21/SO1 |
Serial data output (UART1) |
|
|
|
|
TxD2 |
|
P71/SO2 |
Serial data output (UART2) |
|
|
|
|
ASCK1 |
Input |
P22/SCK1 |
Baud rate clock input (UART1) |
|
|
|
|
ASCK2 |
|
P72/SCK2 |
Baud rate clock input (UART2) |
|
|
|
|
SI0 |
Input |
P25/SDA0Note |
Serial data input (3-wire serial I/O 0) |
SI1 |
|
P20/RxD1 |
Serial data input (3-wire serial I/O 1) |
|
|
|
|
SI2 |
|
P70/RxD2 |
Serial data input (3-wire serial I/O 2) |
|
|
|
|
SO0 |
Output |
P26 |
Serial data output (3-wire serial I/O 0) |
|
|
|
|
SO1 |
|
P21/TxD1 |
Serial data output (3-wire serial I/O 1) |
|
|
|
|
SO2 |
|
P71/TxD2 |
Serial data output (3-wire serial I/O 2) |
|
|
|
|
SDA0Note |
I/O |
P25/SI0 |
Serial data input/output (I2C bus) |
SCK0 |
|
P27/SCL0Note |
Serial clock input/output (3-wire serial I/O 0) |
SCK1 |
|
P22/ASCK1 |
Serial clock input/output (3-wire serial I/O 1) |
|
|
|
|
SCK2 |
|
P72/ASCK2 |
Serial clock input/output (3-wire serial I/O 2) |
|
|
|
|
SCL0 Note |
|
P27/SCK0 |
Serial clock input/output (I2C bus) |
NMI |
Input |
P02/INTP2 |
Non-maskable interrupt request input |
|
|
|
|
INTP0 |
|
P00 |
External interrupt request input |
|
|
|
|
INTP1 |
|
P01 |
|
|
|
|
|
INTP2 |
|
P02/NMI |
|
|
|
|
|
INTP3 |
|
P03 |
|
|
|
|
|
INTP4 |
|
P04 |
|
|
|
|
|
INTP5 |
|
P05 |
|
|
|
|
|
INTP6 |
|
P06 |
|
|
|
|
|
Note This function is available in the μPD78F4216AY, 78F4218AY only.
14 |
Data Sheet U14125EJ1V0DS00 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.2 Non-Port Pins (2/2)
|
|
|
Pin Name |
I/O |
Alternate Function |
Function |
|||
|
|
|
|
|
|
|
|
|
|
|
PCL |
Output |
P23 |
Clock output (for trimming main system clock and subsystem clock) |
|||||
|
|
|
|
|
|
|
|
|
|
|
BUZ |
Output |
P24 |
Buzzer output |
|||||
|
|
|
|
|
|
|
|
|
|
|
RTP0 to RTP7 |
Output |
P120 to P127 |
Real-time output port that outputs data in synchronization with |
|||||
|
|
|
|
|
|
|
|
|
trigger |
|
|
|
|
|
|
|
|
|
|
|
AD0 to AD7 |
I/O |
P40 to P47 |
Lower address/data bus for expanding memory externally |
|||||
|
|
|
|
|
|
|
|
|
|
|
A0 to A7 |
Output |
P80 to P87 |
Lower address bus for expanding memory externally |
|||||
|
|
|
|
|
|
|
|
|
|
|
A8 to A15 |
|
P50 to P57 |
Middle address bus for expanding memory externally |
|||||
|
|
|
|
|
|
|
|
|
|
|
A16 to A19 |
|
P60 to P63 |
Higher address bus for expanding memory externally |
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output |
P64 |
Strobe signal output for reading from external memory |
RD |
|||||||||
|
|
|
|
|
|
P65 |
Strobe signal output for writing to external memory |
||
|
WR |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Input |
P66 |
Wait insertion at external memory access |
|||
|
WAIT |
||||||||
|
|
|
|
|
|
|
|
|
|
|
ASTB |
Output |
P67 |
Strobe output that externally latches address information output to |
|||||
|
|
|
|
|
|
|
|
|
ports 4 through 6 and 8 to access external memory |
|
|
|
|
|
|
|
|
|
|
|
EXANote |
Output |
P37 |
Status signal output at external memory access |
|||||
|
|
Input |
− |
System reset input |
|||||
|
|
RESET |
|
||||||
|
|
|
|
|
|
|
|
|
|
|
X1 |
Input |
− |
Connecting crystal resonator for main system clock oscillation |
|||||
|
|
|
|
|
|
|
|
|
|
|
X2 |
− |
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
XT1 |
Input |
− |
Connecting crystal resonator for subsystem clock oscillation |
|||||
|
|
|
|
|
|
|
|
|
|
|
XT2 |
− |
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
ANI0 to ANI7 |
Input |
P10 to P17 |
A/D converter analog input |
|||||
|
|
|
|
|
|
|
|
|
|
|
ANO0, ANO1 |
Output |
P130, P131 |
D/A converter analog output |
|||||
|
|
|
|
|
|
|
|
|
|
|
AVREF0 |
− |
− |
A/D converter reference voltage input |
|||||
|
|
|
|
|
|
|
|
|
|
|
AVREF1 |
|
|
D/A converter reference voltage input |
|||||
|
|
|
|
|
|
|
|
|
|
|
AVDD |
|
|
A/D converter positive power supply. Connect to VDD. |
|||||
|
|
|
|
|
|
|
|
|
|
|
AVSS |
|
|
GND for A/D converter and D/A converter. Connect to VSS. |
|||||
|
|
|
|
|
|
|
|
|
|
|
VDD |
|
|
Positive power supply |
|||||
|
|
|
|
|
|
|
|
|
|
|
VSS |
|
|
GND |
|||||
|
|
|
|
|
|
|
|
|
|
|
VPP |
|
|
Flash memory programming mode setting. |
|||||
|
|
|
|
|
|
|
|
|
Applying high-voltage for program write/verify. Connect this pin to |
|
|
|
|
|
|
|
|
|
VSS directly or via a pull-down resistor in normal operation mode. |
|
|
|
|
|
|
|
|
|
Connect the VPP pin to VSS via a pull-down resistor in a system in |
|
|
|
|
|
|
|
|
|
which the on-chip flash memory is written while mounted on the |
|
|
|
|
|
|
|
|
|
target board. For the pull-down connection, it is recommended to |
|
|
|
|
|
|
|
|
|
use a resistor with a resistance ranging from 470 Ω to 10 kΩ. |
|
|
|
|
|
|
|
|
|
|
Note The EXA pin is available in the μPD78F4218A, 78F4218AY only.
Data Sheet U14125EJ1V0DS00 |
15 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
4.3 Pin I/O Circuits and Recommended Connections of Unused Pins
The I/O circuit type of each pin and recommended connections of unused pins are shown in Table 4-1. For each type of input/output circuit, refer to Figure 4-1.
Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (1/2)
Pin Name |
I/O Circuit Type |
I/O |
|
Recommended Connection of Unused Pins |
|
|
|
|
|
P00/INTP0 |
8-N |
I/O |
Input: |
Independently connect to VSS via a resistor |
|
|
|
Output: Leave open |
|
P01/INTP1 |
|
|
||
|
|
|
|
|
|
|
|
|
|
P02/INTP2/NMI |
|
|
|
|
|
|
|
|
|
P03/INTP3 to P06/INTP6 |
|
|
|
|
|
|
|
|
|
P10/ANI0 to P17/ANI7 |
9 |
Input |
Connect to VSS or VDD |
|
|
|
|
|
|
P20/RxD1/SI1 |
10-K |
I/O |
Input: |
Independently connect to VSS via a resistor |
|
|
|
Output: Leave open |
|
P21/TxD1/SO1 |
10-L |
|
||
|
|
|
||
|
|
|
|
|
P22/ASCK1/SCK1 |
10-K |
|
|
|
|
|
|
|
|
P23/PCL |
10-L |
|
|
|
|
|
|
|
|
P24/BUZ |
|
|
|
|
|
|
|
|
|
P25/SI0/SDA0Note 1 |
10-K |
|
|
|
|
|
|
|
|
P26/SO0 |
10-L |
|
|
|
|
|
|
|
|
P27/SCK0/SCL0Note 1 |
10-K |
|
|
|
|
|
|
|
|
P30/TO0 to P32/TO2 |
12-E |
|
|
|
|
|
|
|
|
P33/TI1, P34/TI2 |
8-N |
|
|
|
|
|
|
|
|
P35/TI00, P36/TI01 |
10-M |
|
|
|
|
|
|
|
|
P37/EXANote 2 |
12-E |
|
|
|
|
|
|
|
|
P40/AD0 to P47/AD7 |
5-A |
|
|
|
|
|
|
|
|
P50/A8 to P57/A15 |
|
|
|
|
|
|
|
|
|
P60/A16 to P63/A19 |
|
|
|
|
|
|
|
|
|
P64/RD |
|
|
|
|
|
|
|
|
|
P65/WR |
|
|
|
|
|
|
|
|
|
P66/WAIT |
|
|
|
|
|
|
|
|
|
P67/ASTB |
|
|
|
|
|
|
|
|
|
P70/RxD2/SI2 |
8-N |
|
|
|
|
|
|
|
|
P71/TxD2/SO2 |
10-M |
|
|
|
|
|
|
|
|
P72/ASCK2/SCK2 |
8-N |
|
|
|
|
|
|
|
|
P80/A0 to P87/A7 |
12-E |
|
|
|
|
|
|
|
|
P90 to P95 |
13-D |
|
|
|
|
|
|
|
|
P100/TI5/TO5 |
8-N |
|
|
|
|
|
|
|
|
P101/TI6/TO6 |
|
|
|
|
|
|
|
|
|
P102/TI7/TO7 |
|
|
|
|
|
|
|
|
|
P103/TI8/TO8 |
|
|
|
|
|
|
|
|
|
P120/RTP0 to P127/RTP7 |
12-E |
|
|
|
|
|
|
|
|
P130/ANO0, P131/ANO1 |
12-F |
|
|
|
|
|
|
|
|
Notes 1. The SDA0 and SCL0 pins are available in the μPD78F4216AY, 78F4218AY only. 2. The EXA pin is available in the μPD78F4218A, 78F4218AY only.
16 |
Data Sheet U14125EJ1V0DS00 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Table 4-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2)
|
|
Pin Name |
I/O Circuit Type |
I/O |
Recommended Connection of Unused Pins |
|
|
|
|
|
|
|
|
2-G |
Input |
− |
|
|
RESET |
|
|||
|
|
|
|
|
|
|
XT1 |
16 |
|
Connect to VSS |
|
|
|
|
|
|
|
|
XT2 |
|
− |
Leave open |
|
|
|
|
|
|
|
|
AVREF0 |
− |
|
Connect to VSS |
|
|
|
|
|
|
|
|
AVREF1 |
|
|
Connect to VDD |
|
|
|
|
|
|
|
|
AVDD |
|
|
|
|
|
|
|
|
|
|
|
AVSS |
|
|
Connect to VSS |
|
|
|
|
|
|
|
|
VPP |
|
|
Connect this pin to VSS directly or via a pull-down resist in normal |
|
|
|
|
|
|
operation mode. Connect the VPP pin to VSS via a pull-down |
|
|
|
|
|
resistor in a system in which the on-chip flash memory is written |
|
|
|
|
|
while mounted on the target board. |
|
|
|
|
|
For the pull-down connection, it is recommended to use a resistor |
|
|
|
|
|
with a resistance ranging from 470 Ω to 10 kΩ. |
|
|
|
|
|
|
Remark Because the circuit type numbers are standardized among the 78K Series products, they are not
sequential in some models (i.e., some circuits are not provided).
Data Sheet U14125EJ1V0DS00 |
17 |
μPD78F4216A, 78F4218A, 78F4216AY, 78F4218AY
Figure 4-1. Types of Pin I/O Circuits (1/2)
Type 2-G |
|
Type 10-K |
VDD |
|
|
|
|
|
|
|
|
Pullup |
|
P-ch |
|
|
enable |
|
|
|
|
|
|
|
IN |
|
|
|
VDD |
|
|
|
|
|
|
|
Data |
|
P-ch |
|
|
|
|
|
|
|
|
|
IN/OUT |
|
|
Open drain |
|
N-ch |
|
|
Output disable |
|
|
Schmitt-triggered input with hysteresis characteristics |
|
|
|
|
Type 5-A |
VDD |
Type 10-L |
VDD |
|
|
|
|
|
|
Pullup |
P-ch |
Pullup |
|
P-ch |
enable |
|
|||
|
enable |
|
||
|
|
|
|
|
|
VDD |
|
|
VDD |
Data |
P-ch |
Data |
|
P-ch |
|
|
|
|
|
|
IN/OUT |
|
|
IN/OUT |
Output |
|
|
|
|
N-ch |
Open drain |
|
N-ch |
|
disable |
Output disable |
|
||
|
|
|||
|
|
|
|
VSS |
Input |
|
|
|
|
enable |
|
|
|
|
Type 8-N |
VDD |
Type 10-M |
VDD |
|
|
|
|
||
Pullup |
P-ch |
Pullup |
|
P-ch |
enable |
|
|||
enable |
|
|||
|
|
|
||
|
|
|
|
|
|
VDD |
|
|
VDD |
Data |
P-ch |
Data |
|
P-ch |
|
IN/OUT |
|
|
IN/OUT |
Output |
N-ch |
Output disable |
|
N-ch |
disable |
|
|
|
VSS |
|
|
|
|
|
Type 9 |
|
Type 12-E |
|
VDD |
|
|
Pullup |
|
P-ch |
|
|
enable |
|
|
|
Comparator |
|
|
|
P-ch |
|
|
VDD |
|
+ |
|
|
||
IN |
Data |
|
|
|
N-ch |
– |
|
P-ch |
|
|
VREF |
|
|
IN/OUT |
|
|
|
|
|
|
(Threshold voltage) |
Output |
|
N-ch |
|
disable |
|
|
|
|
|
|
|
|
|
Input |
Input |
|
P-ch |
|
enable |
enable |
Analog output |
|
|
|
|
|
|
|
|
|
voltage |
N-ch |
|
|
|
|
|
18 |
Data Sheet U14125EJ1V0DS00 |
Loading...