NEC UPD75068GB-XXX-3B4, UPD75068GB-A-XXX-3B4, UPD75068CU-A-XXX, UPD75068CU-XXX, UPD75066GB-XXX-3B4 Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD75064, 75066, 75068,

75064(A), 75066(A), 75068(A)

4-BIT SINGLE-CHIP MICROCOMPUTER

The μPD75068 is a member of the 75X series of 4-bit single-chip microcomputers.

The minimum instruction execution time of the μPD75068's CPU is 0.95 μs. In addition to this high-speed capability, the chip contains an A/D converter and furnishes high-performance functions such as the serial bus interface (SBI) function compliant with the NEC standard format, providing powerful features and high cost performance. The μPD75068(A) is a high-reliability version of the μPD75068.

NEC also provides PROM versions suitable for small-scale production or evaluation samples in system development. The μPD75P068 is the PROM version for the μPD75064, 75066, 75068, and the μPD75P068(A) is that for the μPD75064(A), 75066(A), 75068(A).

The detailed function descriptions are described in the document below. Please make sure to read this document before starting design.

μPD75068 User's Manual: IEU-1366

FEATURES

•Variable instruction execution time advantageous to high-speed operation and power-saving:

•0.95 μs, 1.91 μs, or 15.3 μs (at 4.19 MHz with the main system clock selected)

•122 μs (at 32.768 kHz with the subsystem clock selected)

•A/D converter (8-bit resolution, successive approximation): 8 channels

•Capable of low-voltage operation: VDD = 2.7 to 6.0 V

•Timer function: 3 channels

•On-chip NEC standard serial bus interface (SBI)

•Very low-power watch operation enabled (5 μA TYP. at 3 V)

•Pull-up resistor option allowed for 27 I/O lines

•The μPD75P068 and 75P068(A) (PROM versions) available: Capable of low-voltage operation (VDD = 2.7 to 6.0 V)

APPLICATIONS

•	μPD75064, 75066, 75068
	Home electronic appliances, air conditioners, cameras, and electronic measuring instruments
•	μPD75064(A), 75066(A), 75068(A)
	Automotive electronics

		The information in this document is subject to change without notice.
	Document No. IC-3140B	The mark shows revised points.
	( O.D. No. IC-8629B)
	Date Published December 1994 P	NEC CORPORATION 1993
	Printed in Japan

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

The μPD75064, 75066, 75068 and μPD75064(A), 75066(A), 75068(A) differ only in their quality grade. Unless otherwise specified, this data sheet describes the μPD75068 as the representative product.

For products with the suffix (A) attached, please make the following substitutions when reading:

μPD75064 —> μPD75064(A)

μPD75066 —> μPD75066(A)

μPD75068 —> μPD75068(A)

ORDERING INFORMATION

		Part number	Package	Quality Grade
		μPD75064CU-xxx	42-pin plastic shrink DIP (600 mil)	Standard
		μPD75064GB-xxx-3B4	44-pin plastic QFP (10x10 mm)	Standard
		μPD75066CU-xxx	42-pin plastic shrink DIP (600 mil)	Standard
		μPD75066GB-xxx-3B4	44-pin plastic QFP (10x10 mm)	Standard
		μPD75068CU-xxx	42-pin plastic shrink DIP (600 mil)	Standard
		μPD75068GB-xxx-3B4	44-pin plastic QFP (10x10 mm)	Standard
		μPD75064CU(A)-xxx	42-pin plastic shrink DIP (600 mil)	Special
		μPD75064GB(A)-xxx-3B4	44-pin plastic QFP (10x10 mm)	Special
		μPD75066CU(A)-xxx	42-pin plastic shrink DIP (600 mil)	Special
		μPD75066GB(A)-xxx-3B4	44-pin plastic QFP (10x10 mm)	Special
		μPD75068CU(A)-xxx	42-pin plastic shrink DIP (600 mil)	Special
		μPD75068GB(A)-xxx-3B4	44-pin plastic QFP (10x10 mm)	Special

Remark xxx : ROM code suffix

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published

by NEC Corporation to know the specification of quality grade on the devices and its recommended

applications.

DIFFERENCE BETWEEN μPD7506x SUBSERIES AND μPD7506x(A) SUBSERIES

Part number	μPD75064		μPD75064(A)
	μPD75066		μPD75066(A)
Parameter	μPD75068		μPD75068(A)
Quality grade	Standard		Special

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

FUNCTION OVERVIEW

Item						Function
Instruction execution time		• Main system clock : 0.95 μs, 1.91 μs, 15.3 μs (at 4.19 MHz)
		• Subsystem clock : 122 μs (at 32.768 kHz)
Internal memory	ROM	• μPD75064: 4096 × 8 bits
		• μPD75066 : 6016 × 8 bits
		• μPD75068 : 8064 × 8 bits
	RAM	512 × 4 bits
General register		• When operating in 4 bits: 8
		• When operating in 8 bits: 4
I/O port		32	12	CMOS input		Of these, seven with software-specifiable on-chip
						pull-up resistors
			12	CMOS I/O		Software-specifiable on-chip pull-up resistors
						Four pins can directly drive LEDs.
			8	N-ch open-drain I/O		Breakdown voltage: 10 V
						Mask-option-specifiable on-chip pull-up resistors
						Can directly drive LEDs.
Timer		3 chs.		• Timer/event counter
				• Basic interval timer : Applicable to watchdog timer
				• Watch timer : Capable of buzzer output
Serial interface		• 3-wire serial I/O mode
		• 2-wire serial I/O mode
		• SBI mode
Bit sequencial buffer		16 bits
Clock output function		Φ ,	fx/23, fx/24, fx/26 (Main system clock: at 4.19 MHz operation)
A/D converter		• 8-bit resolution x 8 channels
		• Low-power operation possible : VDD = 2.7 to 6.0 V
Vectored interrupt		External : 3 , Internal : 3
Test input		External : 1, Internal : 1
System clock oscillator		• Ceramic/crystal oscillator for main system clock
		• Crystal oscillator for subsystem clock
Standby function		STOP / HALT mode
Operating ambient		–40 to +85 °C
temperature
Operating supply		2.7 to 6.0 V
voltage
Package		• 42-pin plastic shrink DIP (600 mil)
		• 44-pin plastic QFP (10 x 10 mm)

3

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

				CONTENTS
1.	PIN CONFIGURATION (TOP VIEW) ··························································································					5
2.	BLOCK DIAGRAM························································································································					7
3.	PIN FUNCTIONS ··························································································································					8
3.1		Port Pins ···············································································································································				8
3.2		Non-Port Pins ·······································································································································				9
3.3		Pin Input/Output Circuits···················································································································				10
3.4		Mask Option Selection ························································································································				12
3.5		Handling Unused Pins ·························································································································				13
4.	MEMORY CONFIGURATION ·····································································································					14
5.	PERIPHERAL HARDWARE FUNCTIONS ···················································································					18
5.1		Ports ······················································································································································				18
5.2		Clock Generator ···································································································································				19
5.3		Clock Output Circuit ····························································································································				20
5.4		Basic Interval Timer ·····························································································································				21
5.5		Watch Timer ·········································································································································				22
5.6		Timer/Event Counter···························································································································				23
5.7		Serial Interface ·····································································································································				24
5.8		A/D Converter ······································································································································				25
5.9		Bit Sequential Buffer ···························································································································				26
6.	INTERRUPT FUNCTIONS ···········································································································					27
7.	STANDBY FUNCTION ················································································································					29
8.	RESET OPERATION····················································································································					30
9.	INSTRUCTION SET ····················································································································					32
10.	ELECTRICAL SPECIFICATIONS ·································································································					40
11.	CHARACTERISTIC CURVES (FOR REFERENCE ONLY) ···························································					54
12.	PACKAGE DRAWINGS···············································································································					60
13.	RECOMMENDED SOLDERING CONDITIONS···········································································					62
APPENDIX A.			DEVELOPMENT TOOLS ························································································			64
APPENDIX B.			RELATED DOCUMENTS ························································································			65

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

1. PIN CONFIGURATION (TOP VIEW)

• 42-pin plastic shrink DIP

XT1 1

XT2 2

RESET 3

X1 4

X2 5

P33 6

P32 7

P31 8

P30 9

AVSS 10 AN7/KR3/P63 11 AN6/KR2/P62 12 AN5/KR1/P61 13 AN4/KR0/P60 14

AN3/P113 15 AN2/P112 16 AN1/P111 17 AN0/P110 18 AVREF 19 IC 20 VDD 21

PD75066CUμ PD75068CUμ	PD75064CUμ
×××-×××-	×××-

42	VSS
41	P40
40	P41
39	P42
38	P43
37	P50
36	P51
35	P52
34	P53
33	P00/INT4
32	P01/SCK
31	P02/SO/SB0
30	P03/SI/SB1
29	P10/INT0
28	P11/INT1
27	P12/INT2
26	P13/TI0
25	P20/PTO0
24	P21
23	P22/PCL
22	P23/BUZ

• 44-pin plastic QFP

P13/TI0

P20/PTO0

P21

P22/PCL

P23/BUZ

VDD

IC

AVREF

P110/AN0

P111/AN1

NC

		44 43 42 41 40 39 38 37 36 35 34
	INT2/P12	1		33	P112/AN2
	INT1/P11	2		32	P113/AN3
	INT0/P10	3		31	P60/KR0/AN4
	SB1/SI/P03	4	μ	30	P61/KR1/AN5
	SB0/SO/P02	5	PD75064GB-×××-3B4	29	P62/KR2/AN6
			μPD75066GB-×××-3B4
	SCK/P01	6		28	P63/KR3/AN7
			μPD75068GB-×××-3B4
	INT4/P00	7		27	AVSS
	P53	8		26	P30
	P52	9		25	P31
	P51	10		24	P32
	P50	11		23	P33
		12 13 14 15 16 17 18 19 20 21 22

NC

P43

P42

P41

P40

VSS

XT1

XT2

RESET

X1

X2

IC : Internally Connected (This pin should be directly connected to VDD)

5

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

PIN IDENTIFICATIONS

P00 - 03			:	Port 0
P10 - 13			:	Port 1
P20 - 23			:	Port 2
P30 - 33			:	Port 3
P40 - 43			:	Port 4
P50 - 53			:	Port 5
P60 - 63			:	Port 6
P110 - 113 :				Port 11
KR0 - 3			:	Key Return
SCK			:	Serial Clock
SI			:	Serial Input
SO			:	Serial Output
SB0, 1			:	Serial Bus 0, 1
			:	Reset Input
RESET
TI0			:	Timer Input 0
PTO0			:	Programmable Timer Output 0
BUZ			:	Buzzer Clock
PCL			:	Programmable Clock
INT0, 1, 4			:	External Vectored Interrupt 0, 1, 4
INT2			:	External Test Input 2
X1, 2			:	Main System Clock Oscillation 1, 2
XT1, 2			:	Subsystem Clock Oscillation 1, 2
AN0 - 7			:	Analog Input 0 - 7
AVREF			:	Analog Reference
AVSS			:	Analog VSS
VDD			:	Positive Power Supply
VSS			:	Ground

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

2.BLOCK DIAGRAM

TI0/P13 PTO0/P20

SI/SB1/P03 SO/SB0/P02 SCK/P01

INT0/P10 INT1/P11 INT2/P12 INT4/P00

KR0 - KR3

4

/ P60 - P63

BUZ/P23

BASIC INTERVAL TIMER

INTBT

TIMER/ COUNTER

#0

INTT0

SERIAL INTERFACE

INTCSI

INTERRUPT CONTROL

WATCH

TIMER

INTW

AVREF

AVSS

A/D

AN0 - AN3 CONVERTER

/P110 - P113 8 AN4 - AN7

/P60 - P63

PROGRAM Note SP

COUNTER

CY ALU

BANK

						GENERAL
	ROM					REGISTER
	PROGRAM
	MEMORY
4096 × 8 BITS				DECODE
(	μ	PD75064)
				AND
6016 × 8 BITS
				CONTROL
(μPD75066)
8064 × 8 BITS						RAM
(μPD75068)						DATA
						MEMORY
						512 × 4 BITS

fX /2N

CPU CLOCK

Φ

CLOCK

CLOCK

CLOCK GENERATOR

STAND BY

OUTPUT

CONTROL

DIVIDER

SUB

MAIN

CONTROL

PCL/P22

XT1 XT2

X1 X2

VDD VSS RESET

BIT SEQ.

BUFFER

PORT 0	4	P00 - P03
	4	P10 - P13
PORT 1
		P20 - P23
PORT 2	4
		P30 - P33
PORT 3	4
		P40 - P43
PORT 4	4
		P50 - P53
PORT 5	4
		P60 - P63
PORT 6	4
		P110 - P113
PORT 11	4

Note The μPD75064 uses the program counter of a 12-bit configuration, the μPD75066 and μPD75068

use that of a 13-bit configuration.

7

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

3.PIN FUNCTIONS

3.1 Port Pins

Pin name	Input/	Shared				Function	8-bit	When reset		I/O circuit
	output		with				I/O			typeNote 1
P00	Input	INT4			4-bit input port (PORT0).		×	Input		B
					For P01 to P03, pull-up resistors can be
P01	I/O		SCK							F -A
					provided by software in units of 3 bits.
P02	I/O	SO/SB0								F -B
P03	I/O	SI/SB1								M -C
P10	Input	INT0				With noise elimination function	×	Input		B -C
P11		INT1			4-bit input port (PORT1).
					Pull-up resistors can be provided by soft-
P12		INT2
					ware in units of 4 bits.
P13			TI0
P20	I/O	PTO0			4-bit I/O port (PORT2).		×	Input		E-B
P21			–		Pull-up resistors can be provided by soft-
					ware in units of 4 bits.
P22			PCL
P23			BUZ
P30Note 2	I/O		–		Programmable 4-bit I/O port (PORT3).		×	Input		E-B
P31Note 2			–		I/O can be specified bit by bit. Pull-up
P32Note 2			–		resistors can be provided by software in
					units of 4 bits.
P33Note 2			–
P40 - P43Note 2	I/O		–		N-ch open-drain 4-bit I/O port (PORT4).			High level		M
					A pull-up resistor can be provided for			(when pull-
					each bit (mask option). Breakdown volt-			up resistors
					age is 10 V in open-drain mode.			are provided)
								or high
								impedance
P50 - P53Note 2	I/O		–		N-ch open-drain 4-bit I/O port (PORT5).			High level		M
					A pull-up resistor can be provided for			(when pull-
					each bit (mask option). Breakdown volt-			up resistors
					age is 10 V in open-drain mode.			are provided)
								or high
								impedance
P60	I/O	KR0/AN4			Programmable 4-bit I/O port (PORT6).		×	Input		Y -D
					I/O can be specified bit by bit. Pull-up
P61		KR1/AN5
					resistors can be provided by software in
P62		KR2/AN6
					units of 4 bits.
P63		KR3/AN7
P110	Input		AN0		4-bit input port (PORT11).		×	Input		Y-A
P111			AN1
P112			AN2
P113			AN3

Notes 1. The circle ( ) indicates the Schmitt trigger input.

2. Can directly drive LEDs.

8

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

3.2Non-Port Pins

Pin name

Input/

Shared

Function

When reset

I/O circuit

output

with

typeNote 1

TI0

Input

P13

Input for receiving external event pulse signal for

–

B -C

timer/event counter

PTO0

I/O

P20

Timer/event counter output

Input

E-B

PCL

I/O

P22

Clock output

Input

E-B

BUZ

I/O

P23

Output frequency selectable

Input

E-B

(for buzzer output or system clock trimming)

I/O

P01

Serial clock I/O

Input

F -A

SCK

SO/SB0

I/O

P02

Serial data output

Input

F -B

Serial bus I/O

SI/SB1

I/O

P03

Serial data input

Input

M -C

Serial bus I/O

INT4

Input

P00

Edge-detective vectored interrupt input

–

B

(both rising and falling edges enabled)

INT0

Input

P10

Edge-detective vectored interrupt input

Note 2

–

B -C

(detection edge selectable)

INT1

P11

Note 3

INT2

Input

P12

Edge-detective testable input

Note 3

–

B -C

(rising edge detection)

KR0 - KR3

I/O

P60 - P63/

Parallel falling edge detection testable input

Input

Y -D

AN4 - AN7

AN0 - AN3

Input

P110 - P113

For A /D converter only

8-bit analog input

Input

Y-A

AN4 - AN7

I/O

P60 - P63/

Y -D

KR0 - KR3

AVREF

Input

–

Reference voltage input

–

Z

AVSS

–

–

GND potential

–

Z

X1, X2

Input

–

Crystal/ceramic connection for main system clock

–

–

generation. When external clock signal is used,

the signal should be applied to X1, and its reverse

phase signal to X2.

XT1, XT2

Input

–

Crystal connection for subsystem clock genera-

–

–

tion. When external clock signal is used, the

signal should be applied to XT1, and its reverse

phase signal to XT2. XT1 can be used as a 1-bit

input (test).

RESET

Input

–

System reset input

–

B

IC

–

–

Internally connected.

–

–

(Connect this pin directly to VDD)

VDD

–

–

Positive power supply

–

–

VSS

–

–

GND potential

–

–

Notes 1. The circle ( ) indicates the Schmitt trigger input.

2.Clock synchronous

3.Asynchronous

9

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

3.3Pin Input/Output Circuits

The input/output circuit of each μPD75068 pin is shown below in a simplified manner.

(1/3)

Type A (For type E-B)

Type D (For type E-B, F-A)

VDD

VDD

Data

P-ch

P-ch

IN

OUT

Output

N-ch

N-ch

disable

	CMOS input buffer	Push-pull output which can be set to high impedance output
		(off for both P-ch and N-ch)
Type B		Type E-B
			VDD
			P.U.R.
		P.U.R.	P-ch
		enable
IN		Data	IN/OUT
		Type D
		Output
		disable
		Type A
Schmitt trigger input with hysteresis		P.U.R.: Pull-Up Resistor
Type B-C
VDD
	P.U.R.
P-ch	P.U.R.
	enable
IN
	P.U.R.: Pull-Up Resistor
10

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

(2/3)

Type F-A	Type M-C

		VDD			VDD
		P.U.R.			P.U.R.
	P.U.R.			P.U.R.	P-ch
		P-ch		enable
	enable
Data					IN/OUT
		IN/OUT
Output		Type D	Data		N-ch
disable			Output
			disable
		Type B

P.U.R.: Pull-Up Resistor					P.U.R.: Pull-Up Resistor
Type F-B					Type Y (For type Y-A , Y-D)
		VDD

		P.U.R.
	P.U.R.				VDD
		P-ch
	enable
Output		IN	P-ch		+
		VDD	N-ch
disable				Sampl-
(P)		P-ch	VDD	ing C	–
Data		IN/OUT
					AVSS
			AVSS
Output		N-ch			Reference voltage
disable
					(from voltage tap of
	Output
				Input	serial resistor string)
	disable
	(N)			enable

P.U.R.: Pull-Up Resistor

Type M

VDD

Type Y-A

P.U.R.

enable

IN/OUT

IN instruction

(Mask option)

Data

Type

A

N-ch

(Can

Input buffer

Output

withstand

+10 V)

disable

IN

Type Y

Middle-voltage input buffer (Can withstand +10 V)

P.U.R.: Pull-Up Resistor

11

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

(3/3)

Type Y-D		VDD		Type Z

P.U.R. AVREF

	P.U.R.	P-ch
	enable

Data

IN/OUT Type D

Output disable

Reference voltage

Type B

Type Y

AVSS

P.U.R.: Pull-Up Resistor

3.4Mask Option Selection

The following mask options are available for selection for each pin.

	Pin name		Mask option
P40	- P43,	1	Pull-up resistor enabled	2	Pull-up resistor disabled
P50	- P53		(specifiable bit by bit)		(specifiable bit by bit)
XT1, XT2		1	Feedback resistor enabled	2	Feedback resistor disabled
			(if a subsystem clock is used)		(if a subsystem clock is not used)

12

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

3.5Handling Unused Pins

Table 3-1. Handling Unused Pins

		Pin	Recommended connection
P00/INT4			Connect to VSS.
			Connect to VSS or VDD.
P01/SCK
P02/SO/SB0
P03/SI/SB1
P10/INT0-P12/INT2			Connect to VSS.
P13/TI0
P20/PTO0			Input state: Connect to VSS or VDD.
P21			Output state: Open
P22/PCL
P23/BUZ
P30-P33
P40-P43
P50-53
P60/KR0/AN4-P63/KR3/AN7
P110/AN0-P113/AN3			Connect to VSS or VDD.
AVREF			Connect to VSS.
AVSS
XT1			Connect to VSS or VDD.
XT2			Open
IC			Directly connect to VDD.

13

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

4.MEMORY CONFIGURATION

•Program memory (ROM) ..... 4096 × 8 bits (0000H to 0FFFH) : μPD75064

..... 6016 × 8 bits (0000H to 177FH) : μPD75066

..... 8064 × 8 bits (0000H to 1F7FH) : μPD75068

•0000H to 0001H : Vector table in which the program start address by reset is stored

•0002H to 000BH : Vector table in which the program start address by interrupt is stored

•0020H to 007FH : Table area to be referenced by GETI instruction

•Data memory

• Data area	..... 512 × 4 bits	(000H to 1FFH)
• Peripheral hardware area	..... 128 × 4 bits	(F80H to FFFH)

Figure 4-1. Program Memory Map

(a) μPD75064

Address	7	6	5	4		0
0000H	MBE	0	0	0	Internal reset start address (high-order 4 bits)
					Internal reset start address (low-order 8 bits)
0002H	MBE	0	0	0	INTBT/INT4 start address	(high-order 4 bits)
					INTBT/INT4 start address	(low-order 8 bits)
0004H	MBE	0	0	0	INT0 start address	(high-order 4 bits)
					INT0 start address	(low-order 8 bits)
0006H	MBE	0	0	0	INT1 start address	(high-order 4 bits)
					INT1 start address	(low-order 8 bits)
0008H	MBE	0	0	0	INTCSI start address	(high-order 4 bits)
					INTCSI start address	(low-order 8 bits)
000AH	MBE	0	0	0	INTT0 start address	(high-order 4 bits)
					INTT0 start address	(low-order 8 bits)
0020H
				GETI instruction reference table
007FH
0080H
07FFH
0800H

		CALL !		addr
		instruction
CALLF		subroutine entry
! faddr		address
instruction
entry
address
		BR $addr
		instruction
		relative branch
		address
		(–15 to –1,
		+2 to +16)

BRCB ! caddr

instruction branch address

Branch destination address specified by GETI instruction, Subroutine entry address

0FFFH

14

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

(b) μPD75066

Address	7	6	5		0
0000H	MBE	0	0	Internal reset start address	(high-order 5 bits)
				Internal reset start address	(low-order 8 bits)
0002H	MBE	0	0	INTBT/INT4 start address	(high-order 5 bits)
				INTBT/INT4 start address	(low-order 8 bits)
0004H	MBE	0	0	INT0 start address	(high-order 5 bits)
				INT0 start address	(low-order 8 bits)
0006H	MBE	0	0	INT1 start address	(high-order 5 bits)
				INT1 start address	(low-order 8 bits)
0008H	MBE	0	0	INTCSI start address	(high-order 5 bits)
				INTCSI start address	(low-order 8 bits)
000AH	MBE	0	0	INTT0 start address	(high-order 5 bits)
				INTT0 start address	(low-order 8 bits)

0020H

GETI instruction reference table

007FH

0080H

07FFH

0800H

0FFFH

1000H

177FH

		CALL !		addr
		instruction
CALLF		subroutine entry
! faddr		address
instruction
entry
address
		BR ! addr
		instruction brach
		address
		BR $addr
		instruction
		relative branch
		address
		(–15 to –1,
		+2 to +16)

BRCB ! caddr

instruction branch address

Branch destination address specified by GETI instruction, Subroutine entry address

BRCB ! caddr

instruction branch address

15

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

(c) μPD75068

Address	7	6	5		0
0000H	MBE	0	0	Internal reset start address	(high-order 5 bits)
				Internal reset start address	(low-order 8 bits)
0002H	MBE	0	0	INTBT/INT4 start address	(high-order 5 bits)
				INTBT/INT4 start address	(low-order 8 bits)
0004H	MBE	0	0	INT0 start address	(high-order 5 bits)
				INT0 start address	(low-order 8 bits)
0006H	MBE	0	0	INT1 start address	(high-order 5 bits)
				INT1 start address	(low-order 8 bits)
0008H	MBE	0	0	INTCSI start address	(high-order 5 bits)
				INTCSI start address	(low-order 8 bits)
000AH	MBE	0	0	INTT0 start address	(high-order 5 bits)
				INTT0 start address	(low-order 8 bits)

0020H

GETI instruction reference table

007FH

0080H

07FFH

0800H

0FFFH

1000H

1F7FH

		CALL !		addr
		instruction
CALLF		subroutine entry
! faddr		address
instruction
entry
address
		BR ! addr
		instruction brach
		address
		BR $addr
		instruction
		relative branch
		address
		(–15 to –1,
		+2 to +16)

BRCB ! caddr

instruction branch address

Branch destination address specified by GETI instruction, Subroutine entry address

BRCB ! caddr

instruction branch address

16

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

Figure 4-2. Data Memory Map

							Data memory
			General		000H
			register		(8 × 4)
			area		007H
					008H
					256 × 4
	Stack
									Bank		0
	area

Static RAM (512 × 4)

0FFH

100H

256 × 4

Bank

1

				1FFH
						Not contained
				F80H
Peripheral						128	× 4
									Bank		15
hardware			area
				FFFH

17

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 Ports

The following three types of I/O port are provided:
	• CMOS input ports (PORT0, 1, 11)	: 12
	• CMOS input/output ports (PORT2, 3, 6)	:	12
	• N-ch open-drain input/output ports (PORT4, 5)	:	8
	Total		32

Table 5-1. Functions of Port

Port (Symbol)	Function	Operation/features	Remarks
PORT0	4-bit input	Can be read or tested regard-	Shared with the SO/SB0, SI/SB1,	SCK,
PORT1		less of the operation mode of	INT0-2, 4, and TI0 pins.
		the dual function pin.
PORT3Note	4-bit I/O	Can be specified for input/	Port 6 is shared with pins KR0 to KR3 and
PORT6		output in bit units.	pins AN4 to AN7.
PORT2		Can be specified for input/	Port 2 is shared with PTO0, PCL, and BUZ
		output in 4-bit units.	pins.
PORT4Note	4-bit I/O	Can be specified for input/	Whether or not the internal pull-up
PORT5Note	(N-ch open-drain,	output in 4-bit units.	resistor is provided can be specified for
	can withstand 10 V)	Ports 4 and 5 can be paired to	each bit by mask option.
		input/output data in 8-bit units.
PORT11	4-bit input	4-bit port dedicated to input	Port 11 is shared with pins AN0 to AN3.

Note Can directly drive LEDs.

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

5.2Clock Generator

The clock generator operates according to the statuses of the processor clock control register (PCC) and the system clock control register (SCC). Two types of clock are provided: main system clock and subsystem clock, and the instruction execution time can be changed.

•0.95 μs / 1.91 μs / 15.3 μs (operated with main system clock at 4.19 MHz)

•122 μs (operated with subsystem clock at 32.768 kHz)

Figure 5-1. Clock Generator Block Diagram

• Basic interval timer (BT)

XT1

• Timer/event counter

• Serial interface

• Watch timer

Subsystem

fXT

• A/D converter

clock generator

Watch timer

XT2

(successive approximation type)

• INT0 noise eliminator

X1

• Clock output circuit

fX

1/2 to 1/4096

Main system

clock generator

Frequency divider

	X2			1/2 1/16
		Oscillator		Selec-
	WM.3			tor
		disable
	SCC				Frequency
		signal
	SCC3				divider
				Selec-
				tor	1/4	Φ
	SCC0				• CPU
					• INT0 noise
bus						eliminator
	PCC				• Clock output
Internal	PCC0					circuit
	PCC1
	4			HALT F/F
	PCC2			S
	HALTNote
	PCC3
	STOPNote			R	Q
	PCC2, PCC3
	clear signal	STOP F/F			Wait release signal from BT
		Q	S
					RESET signal
			R		Standby release signal from
					interrupt control circuit

Note Instruction execution

Remarks 1. fX = Main system clock frequency

2.fXT = Subsystem clock frequency

3.Φ = CPU clock

4.PCC: Processor clock control register

5.SCC: System clock control register

6.One clock cycle (tCY) at Φ is equal to one machine cycle of an instruction. For tCY, refer to AC Characteristics in 10. ELECTRICAL SPECIFICATIONS.

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

5.3Clock Output Circuit

The clock output circuit outputs clock pulses from the P22/PCL pin, and is used to supply clock pulses to remote unit controller and peripheral LSIs.

• Clock output (PCL): Φ, 524 kHz, 262 kHz, 65.5 kHz (fX = at 4.19 MHz)

Figure 5-2. Clock Output Circuit Configuration

From the clock generator

Φ

Output

fX / 23

Selector

buffer

fX / 24

P22/PCL

fX / 26

PORT2.2

Bit 2 of PMGB

CLOM3

0

CLOM1

CLOM0

CLOM

P22

output

Port 2 input/

output mode

latch

specification bit

4

Internal bus

Remark Measures

are taken to prevent outputting a narrow pulse

when selecting clock output

enable/disable.

μPD75064, 75066, 75068, 75064(A), 75066(A), 75068(A)

5.4Basic Interval Timer

The basic interval timer has these functions:

•Interval timer operation which generates a reference timer interrupt

•Watchdog timer application which detects a program runaway

•Selection of wait time for releasing the standby mode and counting the wait time

•Reading out the count value

Figure 5-3. Basic Interval Timer Configuration

From the clock
generator				Clear signal		Clear signal
fX/25
fX/27					Set
			MPX	Basic interval timer	signal	BT interrupt
				(8-bit frequency divider circuit)		request flag
fX/2	9						Vectored
							interrupt
							request
fX/2	12				BT	IRQBT	signal
			3		Wait release
					signal for standby
					release

	BTM3	BTM2 BTM1 BTM0	BTM
			8
SET1 Note		4

Internal bus

Note Instruction execution