NEC UPD75108GF-XXX-3BE, UPD75108GF-A-XXX-3BE, UPD75108G-XXX-1B, UPD75108CW-XXX, UPD75108CW-A-XXX Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD75104, 75106, 75108

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

μPD75108 is a 4-bit single-chip microcomputer integrating timer/event counters, serial interface, and vector interrupt function, in addition to a CPU, ROM, RAM, and I/O ports, on a single chip. Operating at high speeds, the microcomputer allows data to be manipulated in units of 1, 4, or 8 bits. In addition, various bit manipulation instructions are provided to reinforce I/O manipulation capability. Equipped with I/Os for interfacing with peripheral circuits operating on a different supply voltage, outputs that can directly drive LEDs, and analog inputs, μPD75108 is suitable for controlling such systems as VTRs, acoustic products, button telephones, radio communications equipment, and printers. A pin-compatible EPROM model is also available for evaluation of system development and small-scale production of application systems.

Detailed functions are described in the following user’s manual. Be sure to read it for designing.

μPD751XX Series User’s Manual: IEM-922

FEATURES

∙Internal memory

•Program memory (ROM)

:8068 × 8 bits (μPD75108)

:6016 × 8 bits (μPD75106)

:4096 × 8 bits (μPD75104)

•Data memory (RAM)

:512 × 4 bits (μPD75108)

:320 × 4 bits (μPD75106, 75104)

∙New architecture “75X series” rivaling 8-bit microcomputers

∙43 systematically organized instructions

•A wealth of bit manipulation instructions

•8-bit data transfer, compare, operation, increment, and decrement instructions

•1-byte relative branch instructions

•GETI instruction executing 2-/3-byte instruction with one byte

∙High speed. Minimum instruction execution time: 0.95 μs (at 4.19 MHz), 5 V

∙Power-saving, instruction time change function: 0.95 μs/1.91 μs/15.3 μs (at 4.19 MHz)

∙I/O port pins as many as 58

∙Three channels of 8-bit timers

∙8-bit serial interface

∙Multiplexed vector interrupt function

∙Model with PROM is available: μPD75P108B (One-time PROM, EPROM)

Unless there are differences among μPD75104, 75106, and 75108 functions, μPD75108 is treated as the representative model throughout this manual.

The information in this document is subject to change without notice.

Document No.	IC-2520B	The mark shows major revised points.
(O. D. No.	IC-6906B)
Date Published	January 1994 P	ã NEC Corporation 1989
Printed in Japan

μPD75104, 75106, 75108

ORDERING INFORMATION

Part Number	Package	Quality Grade
μPD75104CW-xxx	64-pin plastic shrink DIP (750 mil)	Standard
μPD75104GF-xxx-3BE	64-pin plastic QFP (14 × 20 mm)	Standard
μPD75106CW-xxx	64-pin plastic shrink DIP (750 mil)	Standard
μPD75106GF-xxx-3BE	64-pin plastic QFP (14 × 20 mm)	Standard
μPD75108CW-xxx	64-pin plastic shrink DIP (750 mil)	Standard
μPD75108GF-xxx-3BE	64-pin plastic QFP (14 × 20 mm)	Standard
Remarks: xxx is ROM code number.

Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

2

			μPD75104, 75106, 75108
FUNCTIONAL OUTLINE
	Item		Specifications
	Number of Basic Instructions		43
	Minimum Instruction		Changeable in three steps: 0.95 μs, 1.91 μs, and 15.3 μs at 4.19 MHz
	Execution Time
		ROM	8064 × 8 bits (μPD75108), 6016 × 8 bits (μPD75106), 4096 × 8 bits (μPD75104)
	Internal Memory
		RAM	512 × 4 bits (μPD75108), 320 × 4 bits (μPD75106, 75104)
	General-Purpose Register		4 bits × 8 × 4 banks (memory mapped)
	Accumulator		Three accumulators selectable according to the bit length of manipulated data:
			• 1-bit accumulator (CY), 4-bit accumulator (A), and 8-bit accumulator (XA)
			58 port pins
			• CMOS input pins: 10
	I/O Port		• CMOS I/O pins (can directly drive LEDs): 32
			• Medium voltage N-ch open-drain I/O pins: 12
			(can directly drive LEDs. Pull-up resistor can be connected to each bit)
			• Comparator input pins (4-bit accuracy): 4
	Timer/Counter		• 8-bit timer/event counter × 2
			• 8-bit basic interval timer (can be used as watchdog timer)
			• 8 bits
	Serial Interface		• LSB first/MSB first mode selectable
			• Two transfer modes (transfer/reception and reception only modes)
	Vector Interrupt		External: 3, Internal: 4
	Test Input		External: 2
	Standby		• STOP and HALT modes
			• Various bit manipulation instructions (set, reset, test, Boolean operation)
	Instruction Set		• 8-bit data transfer, compare, operation, increment, and decrement
			• 1-byte relative branch instructions
			• GETI instruction constituting 2 or 3-byte instruction with 1 byte
	Others		• Power-ON reset circuit (mask option)
			• Bit manipulation memory (bit sequential buffer: 16 bits)
	Package		• 64-pin plastic shrink DIP (750 mil)
			• 64-pin plastic QFP (14 × 20 mm)

3

μPD75104, 75106, 75108

CONTENTS

1.	PIN CONFIGURATION (TOP VIEW) ...............................................................................................				6
2.	BLOCK DIAGRAM ...........................................................................................................................				8
3.	PIN FUNCTIONS..............................................................................................................................				9
	3.1	PORT PINS.............................................................................................................................................			9
	3.2	PINS OTHER THAN PORTS .................................................................................................................			10
	3.3	PIN INPUT/OUTPUT CIRCUITS ...........................................................................................................			11
	3.4	RECOMMENDED PROCESSING OF UNUSED PINS ..........................................................................			12
	3.5	NOTES ON USING THE P00/INT4, AND	RESET	......................................................................PINS	13
4.	MEMORY CONFIGURATION ..........................................................................................................				14
5.	PERIPHERAL HARDWARE FUNCTIONS ........................................................................................				20
	5.1	PORTS ....................................................................................................................................................			20
	5.2	CLOCK GENERATOR CIRCUIT ............................................................................................................			21
	5.3	CLOCK OUTPUT CIRCUIT ....................................................................................................................			22
	5.4	BASIC INTERVAL TIMER .....................................................................................................................			23
	5.5	TIMER/EVENT COUNTER .....................................................................................................................			23
	5.6	SERIAL INTERFACE ..............................................................................................................................			25
	5.7	PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) ....................................................			27
	5.8	BIT SEQUENTIAL BUFFER .... 16 BITS ...............................................................................................			28
	5.9	POWER-ON FLAG (MASK OPTION) ....................................................................................................			28
6.	INTERRUPT FUNCTIONS................................................................................................................				28
7.	STANDBY FUNCTIONS ..................................................................................................................				30
8.	RESET FUNCTION...........................................................................................................................				31
9.	INSTRUCTION SET .........................................................................................................................				34

4

			μPD75104, 75106, 75108
10.	APPLICATION EXAMPLES..............................................................................................................			43
	10.1	VTR SYSTEM CONTROLLER ...............................................................................................................		43
	10.2	VTR CAMERA ........................................................................................................................................		43
	10.3	COMPACT DISC PLAYER .....................................................................................................................		44
	10.4	AUTOMOBILE APPLICATIONS (TRIP COMPUTER)............................................................................		44
	10.5	PUSHBUTTON TELEPHONE ................................................................................................................		45
	10.6	DISPLAY PAGER ...................................................................................................................................		45
	10.7	PLAIN PAPER COPIER (PPC) ...............................................................................................................		46
	10.8	PRINTER CONTROLLER .......................................................................................................................		46
11.	MASK OPTION SELECTION ...........................................................................................................			47
12.	ELECTRICAL SPECIFICATIONS ......................................................................................................			48
13.	CHARACTERISTIC DATA ................................................................................................................			57
14.	PACKAGE DRAWINGS ...................................................................................................................			62
15.	RECOMMENDED SOLDERING CONDITIONS ...............................................................................			65
APPENDIX A. FUNCTIONAL DIFFERENCES AMONG PRODUCTS IN μPD751XX SERIES .........				66
APPENDIX B.			DEVELOPMENT TOOLS ..............................................................................................	67
APPENDIX C.			RELATED DOCUMENTS ..............................................................................................	68

5

μPD75104, 75106, 75108

1.PIN CONFIGURATION (Top View)

•64-Pin Plastic Shrink DIP (750 mil)

P13/INT3 1 P12/INT2 2 P11/INT1 3 P10/INT0 4 PTH03 5 PTH02 6 PTH01 7 PTH00 8 TI0 9 TI1 10 P23 11

P22/PCL 12 P21 PTO1 13 P20 PTO0 14 P03/SI 15 P02/SO 16 P01/SCK 17 P00/INT4 18 P123 19 P122 20 P121 21 P120 22 P133 23 P132 24 P131 25 P130 26 P143 27 P142 28 P141 29 P140 30 NC 31 V DD 32

××× -PD75104CW μ ××× -PD75106CW μ ××× -PD75108CW μ

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

VSS

P90

P91

P92

P93

P80

P81

P82

P83

P70

P71

P72

P73

P60

P61

P62

P63

X1

X2

RESET

P50

P51

P52

P53

P40

P41

P42

P43

P30

P31

P32 P33

• 64-Pin Plastic QFP (14 × 20 mm)

P42 P43 P30 P31 P32 P33 VDD

NC P140 P141 P142 P143 P130

P41

P40

P53

P52

P51

P50 RESET X2 X1 P63 P62 P61 P60 P73 P72 P71 P70 P83 P82

	1	64 63 62 61 60 59 58 57 56 55 54 53 52	51
	2		50
	3		49
	4		48
	5		47
	6	μ μ μ	46
		PD75104GF PD75106GF PD75108GF
	10		42
	7		45
	8		44
	9		43
	11	- - -	41
		××× ××× ×××
	12		40
	13	- - -	39
		3BE 3BE 3BE
	14		38
	15		37
	16		36
	17		35
	18		34
	19	20 21 22 23 24 25 26 27 28 29 30 31 32	33

P131

P132

P133

P120

P121

P122

P123 P00/INT4

P01/SCK

P02/SO

P03/SI

P20/PTO0

P21/PTO1

P22/PCL

P23

TI1

TI0

PTH00

PTH01

P81 P80 P93 P92 P91 P90 V SS

P13/INT3 P12/INT2 P11/INT1 P10/INT0 PTH03 PTH02

6

					μPD75104, 75106, 75108
Pin names
P00-P03	: Port 0	SCK			: Serial Clock Input/Output
P10-P13	: Port 1	SO			: Serial Output
P20-P23	: Port 2	SI			: Serial Input
P30-P33	: Port 3	PTO0, PTO1			: Timer Output
P40-P43	: Port 4	PCL			: Clock Output
P50-P53	: Port 5	PTH00-PTH03			: Comparator Input
P60-P63	: Port 6	INT0, INT1, INT4			: External Vector Interrupt Input
P70-P73	: Port 7	INT2, INT3			: External Test Input
P80-P83	: Port 8	TI0, TI1			: Timer Input
P90-P93	: Port 9	X1, X2			: Clock Oscillation Pin
P120-P123	: Port 12	RESET			: Reset Input
P130-P133	: Port 13	NC			: No Connection
P140-P143	: Port 14

7

8

			BASIC
			INTERVAL
			TIMER
			INTBT
	TI0		TIMER/EVENT
			COUNTER
	PTO0/P20		#0
			INTT0
	TI1		TIMER/EVENT
			COUNTER
	PTO1/P21		#1
			INTT1
	SI/P03		SERIAL
	SO/P02
			INTERFACE
	SCK/P01
			INTSIO
	INT0/P10
	INT1/P11		INTERRUPT
	INT2/P12
			CONTROL
	INT3/P13
	INT4/P00
			PROGRAM-
	PTH00-PTH03	4	MABLE
			THRESHOLD
			PORT #0

PROGRAM

COUNTER*

ROM

PROGRAM MEMORY 8064 × 8BITS

:μPD75108 6016 × 8BITS

:μPD75106 4096 × 8BITS

:μPD75104

f XX /2N

ALU

DECODE

AND

CONTROL

	CY			SP (8)

BANK

GENERAL REG.

RAM

DATA MEMORY 512 × 4BITS

:μPD75108 320 × 4BITS

:μPD75106, 75104

	CLOCK	CLOCK	CLOCK		STAND BY	CPU CLOCK
	OUTPUT					Φ
		DIVIDER	GENERATOR		CONTROL
	CONTROL
	PCL/P22		X1	X2		V DD V SS RESET

*: 13 bits: μPD75106, 75108 12 bits: μPD75104

BIT SEQ.

BUFFER (16)

PORT 0	4	P00 - P03
PORT 1	4	P10 - P13
PORT 2	4	P20 - P23
		P30 - P33
PORT 3	4
		P40 - P43
PORT 4	4
		P50 - P53
PORT 5	4
		P60 - P63
PORT 6	4
PORT 7	4	P70 - P73
PORT 8	4	P80 - P83
PORT 9	4	P90 - P93
PORT 12	4	P120 - P123
PORT 13	4	P130 - P133
PORT 14	4	P140 - P143

DIAGRAM BLOCK .2

75108 75106, PD75104,μ

μPD75104, 75106, 75108

3.PIN FUNCTIONS

3.1PORT PINS

							8-Bit			I/O
	Pin Name	I/O	Shared with:			Function		At Reset		Circuit
							I/O
										TYPE*1
	P00	Input	INT4							B
	P01	I/O								F
				SCK		4-bit input port (PORT 0)		Input
	P02	I/O		SO						E
	P03	Input		SI			x			B
	P10		INT0
	P11	Input	INT1			4-bit input port (PORT 1)		Input		B
	P12		INT2
	P13		INT3
	P20*3		PTO0
	P21*3	I/O	PTO1			4-bit I/O port (PORT 2)		Input		E
	P22*3		PCL				x
	P23*3			—
	P30-P33*3	I/O		—		4-bit programmable I/O port (PORT 3)		Input		E
						Can be specified for input or output bitwise.
	P40-P43*3	I/O		—		4-bit I/O port (PORT 4)	o	Input		E
	P50-P53*3	I/O		—		4-bit I/O port (PORT 5)		Input		E
	P60-P63*3	I/O		—		4-bit programmable I/O port (PORT 6)		Input		E
						Can be specified for input or output bitwise.	o
	P70-P73*3	I/O				4-bit I/O port (PORT 7)		Input		E
	P80-P83*3	I/O		—		4-bit I/O port (PORT 8)	o	Input		E
	P90-P93*3	I/O		—		4-bit I/O port (PORT 9)		Input		E
						4-bit N-ch open-drain I/O port (PORT 12)
	P120-P123*3	I/O		—		Built-in pull-up resistors can be specified in bit		Input*2		M
						units by mask option.
						Open-drain withstanding voltage: 12 V	o
						4-bit N-ch open-drain I/O port (PORT 13)
	P130-P133*3	I/O		—		Built-in pull-up resistors can be specified in bit		Input*2		M
						units by mask option.
						Open-drain withstanding voltage: 12 V
						4-bit N-ch open-drain I/O port (PORT 14)
	P140-P143*3	I/O		—		Built-in pull-up resistors can be specified in bit	–	Input*2		M
						units by mask option.
						Open-drain withstanding voltage: 12 V

*1: Circles indicate Schmitt trigger input pins.

2:With drain open: high impedance

With pull-up resistor connected: high level

3:Can directly drive LEDs.

9

μPD75104, 75106, 75108

3.2PINS OTHER THAN PORTS

									I/O
Pin Name					I/O	Shared with:	Function	At Reset	Circuit
									TYPE*1
PTH00-PTH03					Input	—	4-bit variable threshold voltage analog input port	—	N
		TI0					External event pulse inputs for timer/event counter.
					Input	—	Also serves as edge-detected vector interrupt input.	—	B
		TI1
							1-bit input also possible.
	PTO0				I/O	P20	Outputs for timer/event counter	Input	E
	PTO1					P21
									F
	SCK				I/O	P01	Serial clock I/O	Input
		SO			I/O	P02	Serial data output	Input	E
		SI			Input	P03	Serial data input	Input	B
	INT4				Input	P00	Edge-detected vectored interrupt input (both rising and	Input	B
							falling edges detected)
	INT0				Input	P10	Edge-detected vectored interrupt inputs (valid	Input	B
	INT1					P11	edge selectable)
	INT2				Input	P12	Edge-detected testable inputs (rising edge detected)	Input	B
	INT3					P13
		PCL			I/O	P22	Clock output	Input	E
							Crystal/ceramic system clock oscillator connections.
X1, X2					—	—	Input external clock to X1, and signal in reverse phase	—	—
							with X1 to X2.
									B
RESET					Input	—	System reset input (low level active type)	—
	NC*2				—	—	No Connection	—	—
		VDD			—	—	Positive power supply	—	—
		VSS			—	—	GND	—	—

*1: Circles indicate Schmitt trigger input pins.

2: Connect the NC pin directly to the VDD pin when μPD75P108B and a printed circuit board are shared.

10

μPD75104, 75106, 75108

3.3PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the μPD75108.

TYPE A

TYPE E

VDD

data

P–ch

IN/OUT

IN

Type D

output

N–ch

disable

Type A

Input buffer of CMOS standard

I/O circuit consisting of Type D push-pull output circuit

and Type A input buffer

TYPE B

TYPE F

IN

data

IN/OUT

Type D

output

disable

Type B

Schmitt trigger input with hysteresis characteristics

I/O circuit consisting of Type D push-pull output and Type

B Schmitt trigger input

TYPE D

TYPE M

V DD

P.U.R.

(mask option)

VDD

IN/OUT

data

P-ch

data

N-ch

OUT

(+12 V

output

withstand)

output

N-ch

disable

disable

Push – pull output that can be set in a output

Medium-voltage input

high– impedance state (both P –ch and N –ch are off)

buffer (+12 V withstand)

P.U.R.: Pull-Up Resistor

11

	μPD75104, 75106, 75108
TYPE N
	Comparator
IN	+
	–
	V REF (threshold voltage)

3.4RECOMMENDED PROCESSING OF UNUSED PINS

	Pin		Recommended connections
PTH00-PTH03
TI0			Connect to VSS or VDD
TI1
P00			Connect to VSS
P01-P03			Connect to VSS or VDD
P10-P13			Connect to VSS
P20-P23
P30-P33
P40-P43
P50-P53
P60-P63			Input: Connect to VSS or VDD
P70-P73
P80-P83			Output: Open
P90-P93
P120-P123
P130-P133
P140-P143
			Connect to VDD
	RESET*	1
NC*2			Open

*1: Connect this pin to the VDD pin only when a power-ON reset circuit is provided as a mask option.

2:Connect the NC pin to the VDD pin when μPD75P108 and a printed circuit board are shared.

12

μPD75104, 75106, 75108

3.5NOTES ON USING THE P00/INT4, AND RESET PINS

In addition to the functions described in Sections 3.1 and 3.2, an exclusive function for setting the test mode, in which the internal fuctions of the μPD75108 are tested (solely used for IC tests), is provided to the P00/INT4

and RESET pins.

If a voltage exceeding VDD is applied to either of these pins, the μPD75108 is put into test mode. Therefore, even when the μPD75108 is in normal operation, if noise exceeding the VDD is input into any of these pins, the

μPD75108 will enter the test mode, and this will cause problems for normal operation.

As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up

and the above montioned problem may occur.

Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot

be avoided, suppress the noise using a capacitor or diode as shown in the figure below.

∙ Connect a diode across P00/INT4 and

∙ Connect a capacitor across P00/INT4 and

RESET , and VDD.

RESET , and VDD.

VDD

VDD

VDD

VDD

P00/INT4,

RESET

P00/INT4,

RESET

13

μPD75104, 75106, 75108

4.MEMORY CONFIGURATION

∙Program memory (ROM) ... 8064 × 8 bits (0000H-1F7FH) : μPD75108

... 6016 × 8 bits (0000H-177FH) : μPD75106

... 4096 × 8 bits (0000H-0FFFH) : μPD75104

• 0000H, 0001H : Vector table to which address from which program is started is written after reset

•0002H-000BH: Vector table to which address from which program is started is written after interrupt

•0020H-007FH : Table area referenced by GETI instruction

∙Data memory (RAM)

•Data area ....512 × 4 bits (000H–1FFH): μPD75108

320× 4 bits (000H-13FH) : μPD75106, 75104

•Peripheral hardware area .... 128 × 4 bits (F80H–FFFH)

14

μPD75104, 75106, 75108

				(a) μ PD75108
Address	7	6	5
0000H	MBE	RBE	0	Internal reset start address (upper 5 bits)
				Internal reset start address (lower 8 bits)
0002H	MBE	RBE	0	INTBT/INT4 start address (upper 5 bits)
				INTBT/INT4 start address (lower 8 bits)
0004H				INT0/INT1 start address (upper 5 bits)
	MBE	RBE	0
				INT0/INT1 start address (lower 8 bits)
0006H				INTSIO start address (upper 5 bits)
	MBE	RBE	0
				INTSIO start address (lower 8 bits)
0008H	MBE	RBE	0	INTT0 start address (upper 5 bits)
				INTT0 start address (lower 8 bits)
000AH				INTT1 start address (upper 5 bits)
	MBE	RBE	0
				INTT1 start address (lower 8 bits)

0020H

GETI instruction reference table

007FH

0080H

07FFH

0800H

0FFFH

1000H

1F7FH

0

CALLF
! faddr
instruction				CALL ! addr
entry				instruction
address				subroutine
				entry address
		BRCB
	! caddr			BR ! addr
	instruction
		branch		instruction
	address			branch address
				BR $addr
				instruction
				relational
				branch address
				(–15 to –1,
				+2 to +16)
					Branch destination
					address and
					subroutine entry
					address for
					GETI instruction

BRCB ! caddr instruction branch address

Fig. 4-1 Program Memory Map (1/3)

Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.

15

μPD75104, 75106, 75108

				(b) μ PD75106
Address	7	6	5
0000H	MBE	RBE	0	Internal reset start address (upper 5 bits)
				Internal reset start address (lower 8 bits)
0002H	MBE	RBE	0	INTBT/INT4 start address (upper 5 bits)
				INTBT/INT4 start address (lower 8 bits)
0004H				INT0/INT1 start address (upper 5 bits)
	MBE	RBE	0
				INT0/INT1 start address (lower 8 bits)
0006H				INTSIO start address (upper 5 bits)
	MBE	RBE	0
				INTSIO start address (lower 8 bits)
0008H	MBE	RBE	0	INTT0 start address (upper 5 bits)
				INTT0 start address (lower 8 bits)
000AH				INTT1 start address (upper 5 bits)
	MBE	RBE	0
				INTT1 start address (lower 8 bits)

0020H

GETI instruction reference table

007FH

0080H

07FFH

0800H

0FFFH

1000H

177FH

0

CALLF
! faddr
instruction				CALL ! addr
entry				instruction
address				subroutine
				entry address
		BRCB
	! caddr			BR ! addr
	instruction
		branch		instruction
	address			branch address
				BR $addr
				instruction
				relational
				branch address
				(–15 to +16)
					Branch destination
					address and
					subroutine entry
					address for
					GETI instruction

BRCB ! caddr instruction branch address

Fig. 4-1 Program Memory Map (2/3)

Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.

16

μPD75104, 75106, 75108

					(c) μ PD75106
Address	7	6	5	4
000H	MBE	RBE	0	0	Internal reset start address (upper 4 bits)
					Internal reset start address (lower 8 bits)
002H	MBE	RBE	0	0	INTBT/INT4 start address (upper 4 bits)
					INTBT/INT4 start address (lower 8 bits)
004H					INT0/INT1 start address (upper 4 bits)
	MBE	RBE	0	0
					INT0/INT1 start address (lower 8 bits)
006H					INTSIO start address (upper 4 bits)
	MBE	RBE	0	0
					INTSIO start address (lower 8 bits)
008H	MBE	RBE	0	0	INTT0 start address (upper 4 bits)
					INTT0 start address (lower 8 bits)
00AH					INTT1 start address (upper 4 bits)
	MBE	RBE	0	0
					INTT1 start address (lower 8 bits)

020H

GETI instruction reference table

07FH

080H

7FFH

800H

FFFH

0

	CALLF
	! faddr
	instruction		BRCB ! caddr
	entry
			instruction
	address				Branch destination
			branch address
					address and
					subroutine entry
					address for
			CALL ! addr		GETI instruction
			instruction
			subroutine
			entry address		BR $addr
					instruction
					relational
					branch address
					(–15 to +16)

Fig. 4-1 Program Memory Map (3/3)

Remarks: In addition to the above addresses, program can be branched to addresses specified by the PC with the contents of its lower 8 bits changed by BR PCDE or BR PCXA instruction.

17

μPD75104, 75106, 75108

(a) μ PD75108

Data memory

Memory bank

General-purpose

000H

(32 × 4)

register area

01FH

Bank

0

Stack

area

256× 4

0FFH

Data memory

Static RAM

100H

(512 × 4)

256× 4

Bank

1

1FFH

Not provided

F80H

128× 4

Peripheral hardware area

Bank

15

FFFH

Fig. 4-2 Data Memory Map(1/2)

18

μPD75104, 75106, 75108

(b) μ PD75106, 75104

Data memory

Memory bank

General-purpose

000H

(32 × 4)

register area

01FH

Stack

area

Bank

0

General-

256× 4

purpose

Static RAM

(320 × 4)

0FFH

100H

64 × 4

Bank

1

13FH

Not provided

F80H

128× 4

Peripheral hardware area

Bank

15

FFFH

Fig. 4-2 Data Memory Map(2/2)

19

μPD75104, 75106, 75108

5.PERIPHERAL HARDWARE FUNCTIONS

5.1PORTS

I/O ports are classified into the following 3 kinds:

∙ CMOS input (PORT0, 1)

: 8

∙CMOS input/output (PORT2, 3, 4, 5, 6, 7, 8, 9) : 32

∙N-ch open-drain input/output (PORT12, 13, 14) : 12

Total

: 52

Table 5-1 Port Function

	Port	Function	Operation and Features	Remarks
	(Symbol)
	PORT0			Shared with SI, SO,		and
		4-bit input	Can always be read or tested regardless of opera-		SCK,
			tion mode of shared pin	INT0 to 4 pins
	PORT1
	PORT3		Can be set in input or output mode bitwise	—
	PORT6
	PORT2
	PORT4	4-bit I/O*
	PORT5		Can be set in input or output mode in units of 4 bits.	Port 2 pins are shared with
	PORT7		Ports 4 and 5, 6 and 7, 8 and 9 can be used in pairs	PTO0, PTO1, and PCL pins
			to input or output 8-bit data
	PORT8
	PORT9
	PORT12	4-bit I/O*	Can be set in input or output mode in units of 4 bits.	Each bit can be connected to
	PORT13	(N-ch opendrain.	Ports 12 and 13 can be used in pairs to input or	pull-up resistor by mask option
		12V)	output 8-bit data
	PORT14
	*: Can directly drive LED.

20

μPD75104, 75106, 75108

5.2CLOCK GENERATOR CIRCUIT

The clock generator circuit generates clocks to control CPU operation modes by supplying clocks to the CPU and peripheral hardware. In addition, this circuit can change the instruction execution time.

• 0.95 μs/1.91 μs/15.3 μs (operating at 4.19 MHz)

						· Basic interval timer (BT)
						· Clock output circuit
						· Timer/event counter
						· Serial interface
		X1			1/8 to 1/4096
		System clock
				f XX	or
		generator		f X	Frequency civider
		circuit
		X2			1/2 1/16
		Oscillation				Frequency
		stops
					Selector	divider
						1/4	Φ
							· CPU
	PCC						· Clock output
							circuit
	PCC0
bus	PCC1
Internal	PCC2
	4				HALT F/F
	HALT*				S
	PCC3
	STOP*				R	Q
	Clears
	PCC2,	STOP F/F				Wait release signal from BT
	PCC3
		Q	S
						RES (internal reset) signal
			R			Standby release signal from
						interrupt control circuit

*: Execution of the instruction

Remarks 1: fXX = Crystal/ceramic oscillator

2:fX = External clock frequency

3:PCC: Processor clock control register

4: One clock cycle (tCY) of Φ is one machine cycle of an instruction. For tCY, refer to AC
characteristics in 12. ELECTRICAL SPECIFICATIONS.

Fig. 5-1 Clock Generator Block Diagram

21