NEC UPD753208GT-XXX-T2, UPD753208GT-XXX-T1, UPD753208GT-XXX-E2, UPD753208GT-XXX-E1, UPD753208GT-XXX Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD753204, 753206, 753208

4-BIT SINGLE-CHIP MICROCONTROLLERS

The μPD753208 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing capability comparable to that of an 8-bit microcontroller.

The μPD753208 has an on-chip LCD controller/driver and is based on the μPD75308B of the 75X Series. However, the μPD75308B is supplied in an 80-pin package, whereas the μPD753208 is supplied in a 48pin package (375 mils, 0.65-mm pitch) and therefore is suitable for small-scale application systems. In addition, the μPD753208 features expanded CPU functions and performs high-speed operations at a low voltage of 1.8 V.

Detailed information about functions can be found in the following user’s manual. Be sure to read it before designing. μPD753208 User’s Manual: U10158E

Features

•Low-voltage operation: VDD = 1.8 to 5.5 V

–Can be driven by two 1.5-V batteries

•Internal memory

–Program memory (ROM):

4096 × 8 bits (μPD753204)

6144 × 8 bits (μPD753206)

8192 × 8 bits (μPD753208)

– Data memory (RAM): 512 × 4 bits

•Variable instruction execution time for high-speed operation and power saving operation

–0.95, 1.91, 3.81, 15.3 μs (@ 4.19-MHz operation)

–0.67, 1.33, 2.67, 10.7 μs (@ 6.0-MHz operation)

•Internal programmable LCD controller/driver

•Small package:

48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

•One-time PROM version: μPD75P3216

Applications

Remote controllers, Cameras, Sphygnomamometers, Compact-disc radio cassette player compo systems, gas meters, etc.

Ordering Information

Part number	Package	ROM (× 8 bits)
μPD753204GT-×××	48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)	4096
μPD753206GT-×××	48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)	6144
μPD753208GT-×××	48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)	8192

Remark ××× indicates ROM code suffix.

Unless otherwise specified, references in this data sheet to the μPD753208 mean the

μPD753204 and the μPD753206.

The information in this document is subject to change without notice.

	Document No. U10166EJ2V0DS00 (2nd edition)	The mark shows major revised points.
	Date Published March 1997 N
	Printed in Japan

© 1996

μPD753204, 753206, 753208

Function Outline

Parameter

Function

Instruction execution time

•

0.95, 1.91, 3.81, 15.3 μs (@ 4.19-MHz operation with system clock)

•

0.67, 1.33, 2.67, 10.7 μs (@ 6.0-MHz operation with system clock)

Internal memory

ROM

4096 × 8 bits (μPD753204)

6144 × 8 bits (μPD753206)

8192 × 8 bits (μPD753208)

RAM

512 × 4 bits

General-purpose register

•

4-bit operation:

8 × 4 banks

•

8-bit operation:

4 × 4 banks

Input/

CMOS input

6

Connecting on-chip pull-up resistors can be specified by software:

5

output

CMOS input/output

20

Connecting on-chip pull-up resistors can be specified by software:

20

port

Also used for segment pins: 8

N-ch open-drain

4

On-chip pull-up resistors can be specified by mask option

input/output

13-V withstand voltage

Total

30

LCD controller/driver

•

Segment selection:

4/8/12 segments (can be changed to CMOS input/

output port in 4-time units; max. 8)

•

Display mode selection:

Static

1/2 duty (1/2 bias)

1/3 duty (1/2 bias)

1/3 duty (1/3 bias)

1/4 duty (1/3 bias)

•

On-chip split resistor for LCD drive can be specified by mask option

Timer

5 channels

•

8-bit timer/event counter:

1 channel

•

8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier

generator, and timer with gate)

•

Basic interval timer/watchdog timer: 1 channel

•

Watch timer: 1 channel

Serial interface

•

3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit

•

2-wire serial I/O mode

•

SBI mode

Bit sequential buffer (BSB)

16 bits

Clock output (PCL)

•

Φ, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)

•

Φ, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)

Buzzer output (BUZ)

•

2, 4, 32 kHz (@ 4.19-MHz operation with system clock)

•

2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)

Vectored interrupts

External: 2, Internal: 5

Test input

External: 1, Internal: 1

System clock oscillator

Ceramic or crystal oscillator for system clock oscillation

Standby function

STOP/HALT mode

Power supply voltage

VDD = 1.8 to 5.5 V

Package

48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)

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		μPD753204, 753206, 753208
		CONTENTS
1.	PIN CONFIGURATION (TOP VIEW) ....................................................................................................		5
2.	BLOCK DIAGRAM ................................................................................................................................		6
3.	PIN FUNCTIONS ....................................................................................................................................		7
	3.1	Port Pins ......................................................................................................................................	7
	3.2	Non-Port Pins ..............................................................................................................................	9
	3.3	Pin Input/Output Circuits .........................................................................................................	11
	3.4	Recommended Connections for Unused Pins .......................................................................	13
4.	SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................		14
	4.1	Difference Between Mk I and Mk II Modes ..............................................................................	14
	4.2	Setting Method of Stack Bank Select Register (SBS) ...........................................................	15
5.	MEMORY CONFIGURATION .............................................................................................................		16
6.	PERIPHERAL HARDWARE FUNCTION ...........................................................................................		21
	6.1	Digital I/O Port ...........................................................................................................................	21
	6.2	Clock Generator ........................................................................................................................	22
	6.3	Clock Output Circuit .................................................................................................................	23
	6.4	Basic Interval Timer/Watchdog Timer .....................................................................................	24
	6.5	Watch Timer ..............................................................................................................................	25
	6.6	Timer/Event Counter .................................................................................................................	26
	6.7	Serial Interface ..........................................................................................................................	30
	6.8	LCD Controller/Driver ...............................................................................................................	32
	6.9	Bit Sequential Buffer ................................................................................................................	34
7.	INTERRUPT FUNCTION AND TEST FUNCTION ..............................................................................		35
8.	STANDBY FUNCTION ........................................................................................................................		37
9.	RESET FUNCTION .............................................................................................................................		38
10.	MASK OPTION ...................................................................................................................................		41
11.	INSTRUCTION SET ............................................................................................................................		42
12.	ELECTRICAL SPECIFICATIONS .......................................................................................................		56
13. CHARACTERISTIC CURVES (REFERENCE VALUES) ...................................................................			68
14. PACKAGE DRAWINGS .....................................................................................................................			70
15. RECOMMENDED SOLDERING CONDITIONS .................................................................................			71

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	μPD753204, 753206, 753208
APPENDIX A	μPD753108, 753208, AND 75P3216 FUNCTIONAL LIST .............................................	72
APPENDIX B	DEVELOPMENT TOOLS .................................................................................................	74
APPENDIX C	RELATED DOCUMENTS ................................................................................................	77

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μPD753204, 753206, 753208

1. PIN CONFIGURATION (TOP VIEW)

•48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) μPD753204GT-×××, μPD753206GT-×××, μPD753208GT-×××

COM0	1	48	S12
COM1	2	47	S13
COM2	3	46	S14
COM3	4	45	S15
BIAS	5	44	P93/S16
VLC0	6	43	P92/S17
VLC1	7	42	P91/S18
VLC2	8	41	P90/S19
P30/LCDCL	9	40	P83/S20
P31/SYNC	10	39	P82/S21
P32	11	38	P81/S22
P33	12	37	P80/S23
VSS	13	36	P23/BUZ
P50	14	35	P22/PCL/PTO2
P51	15	34	P21/PTO1
P52	16	33	P20/PTO0
P53	17	32	P13/TI0
P60/KR0	18	31	P10/INT0
P61/KR1	19	30	P03/SI/SB1
P62/KR2	20	29	P02/SO/SB0
P63/KR3	21	28	P01/SCK
VDD	22	27	P00/INT4
X1	23	26	RESET
X2	24	25	IC Note

Note Connect IC (Internally Connected) pin directly to VDD.

Pin Identification

P00 to P03		: Port0	S12 to S23		: Segment Output 12 to 23
P10, P13		: Port1	VLC0 to VLC2		: LCD Power Supply 0 to 2
P20 to P23		: Port2	BIAS		: LCD Power Supply Bias Control
P30 to P33		: Port3	LCDCL		: LCD Clock
P50 to P53		: Port5	SYNC		: LCD Synchronization
P60 to P63		: Port6	TI0		: Timer Input 0
P80 to P83		: Port8	PTO0 to PTO2		: Programmable Timer Output 0 to 2
P90 to P93		: Port9	BUZ		: Buzzer Clock
KR0 to KR3		: Key Return 0 to 3	PCL		: Programmable Clock
COM0 to COM3		: Common Output 0 to 3	INT0, INT4		: External Vectored Interrupt 0, 4
		: Serial Clock	X1, X2		: System Clock Oscillation 1, 2
SCK
SI		: Serial Input			: Reset
			RESET
SO		: Serial Output	IC		: Internally Connected
SB0, SB1		: Serial Data Bus 0, 1	VDD		: Positive Power Supply
			VSS		: Ground

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μPD753204, 753206, 753208

2. BLOCK DIAGRAM

BUZ/P23

WATCH

TIMER

PORT0

4

P00 to P03

INTW

fLCD

BASIC

PORT1

2

P10,P13

INTERVAL

TIMER/

PORT2

4

P20 to P23

WATCHDOG

PROGRAM

SP (8)

TIMER

INTBT

COUNTER

CY

PORT3

4

P30 to P33

ALU

SBS

TI0/P13

8-BIT

PORT5

4

P50 to P53

TIMER/EVENT

TPO0/P20

BANK

COUNTER #0

INTT0

TOUT

PORT6

4

P60 to P63

INTT1

PORT8

4

P80 to P83

8-BIT

GENERAL REG.

TIMER

CASCADED

PORT9

4

PTO1/P21

COUNTER #1 16-BIT

PROGRAM

DECODE

P90 to P93

8-BIT

TIMER

TOUT

MEMORY

Note

AND

TIMER

COUNTER

PTO2/PCL/P22

COUNTER #2

(ROM)

CONTROL

DATA

4

S12 to S15

MEMORY

INTT2

(RAM)

S16/P93 to

512 × 4 BITS

4

SI/SB1/P03

CLOCKED

S19/P90

SO/SB0/P02

SERIAL

4

S20/P83 to

SCK/P01

INTERFACE

S23/P80

LCD

INTCSI TOUT

4

CONTROLLER/

COM0 to COM3

INT0/P10

DRIVER

VLC0

CPU CLOCK

fX/2

N

VLC1

INT4/P00

INTERRUPT

Φ

fLCD

KR0/P60 to

CONTROL

CLOCK

CLOCK

SYSTEM

STANDBY

VLC2

4

BIAS

OUTPUT

CLOCK

KR3/P63

DIVIDER

CONTROL

LCDCL/P30

CONTROL

GENERATOR

SYNC/P31

BIT SEQ

PCL/PTO2/P22

BUFFER (16)

X1 X2

IC VDD VSS RESET

Note The ROM capacity depends on the product.

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μPD753204, 753206, 753208

3. PIN FUNCTION

3.1	Port Pins (1/2)
Pin Name		Input/Output		Alternate			Function	8-bit	After Reset	I/O Circuit
				Function				I/O		TYPE Note 1
P00		Input		INT4			4-bit input port (PORT0).	No	Input	(B)
							For P01 to P03, on-chip pull-up resistors can
P01		Input/Output		SCK						(F)-A
							be specified by software in 3-bit units.
P02		Input/Output		SO/SB0						(F)-B
P03		Input/Output		SI/SB1						(M)-C
P10		Input		INT0			Input port in 1 bit unit (PORT1).	No	Input	(B)-C
							On-chip pull-up resistors can be specified by
							software in 2-bit units.
P13					TI0		Noise elimination circuit can be specified with
							P10/INT0.
P20		Input/Output		PTO0			4-bit input/output port (PORT2).	No	Input	E-B
							On-chip pull-up resistors can be specified by
P21				PTO1
							software in 4-bit units.
P22				PCL/PTO2
P23				BUZ
P30		Input/Output		LCDCL			Programmable 4-bit input/output port (PORT3).	No	Input	E-B
							This port can be specified input/output bit-
P31				SYNC
							wise. On-chip pull-up resistor can be speci-
P32					–
							fied by software in 4-bit units.
P33					–
P50	to	Input/Output			–		N-ch open-drain 4-bit input/output port (PORT5).	No	High level	M-D
P53 Note 2							A pull-up resistor can be contained bit-wise		(when pull-
							(mask option).		up resistors
									are
							Withstand voltage is 13 V in open-drain mode.		provided) or
									high-
									impedance

Notes 1. Characters in parentheses indicate the Schmitt-trigger input.

2.If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port), low level input leakage current increases when input or bit manipulation instruction is executed.

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μPD753204, 753206, 753208

3.1 Port Pins (2/2)

Pin Name	Input/Output	Alternate	Function	8-bit	After Reset	I/O Circuit
		Function		I/O		TYPE Note 1
P60	Input/Output	KR0	Programmable 4-bit input/output port (PORT6).	No	Input	(F)-A
			This port can be specified for input/output bit-
P61		KR1
			wise.
P62		KR2	On-chip pull-up resistors can be specified by
			software in 4-bit units.
P63		KR3
P80	Input/Output	S23	4-bit input/output port (PORT8).	Yes	Input	H
			On-chip pull-up resistors can be specified by
P81		S22
			software in 4-bit units. Note 2
P82		S21
P83		S20
P90	Input/Output	S19	4-bit input/output port (PORT9).		Input	H
			On-chip pull-up resistors can be specified by
P91		S18
			software in 4-bit units. Note 2
P92		S17
P93		S16

Notes 1. Characters in parentheses indicate the Schmitt-trigger input.

2.Do not connect on-chip pull-up resistors specified by software when using as segment signal output pins.

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μPD753204, 753206, 753208

3.2 Non-Port Pins (1/2)

	Pin Name		Input/Output		Alternate	Function			After Reset	I/O Circuit
					Function					TYPE Note 1
	TI0		Input		P13	Inputs external event pulses to the timer/event			Input	(B)-C
						counter.
	PTO0		Output		P20	Timer/event counter output			Input	E-B
	PTO1				P21	Timer counter output
	PTO2				P22/PCL
	PCL				P22/PTO2	Clock output
	BUZ				P23	Optional frequency output (for buzzer output
						or system clock trimming)
	SCK		Input/Output		P01	Serial clock input/output			Input	(F)-A
	SO/SB0				P02	Serial data output				(F)-B
						Serial data bus input/output
	SI/SB1				P03	Serial data input				(M)-C
						Serial data bus input/output
	INT4		Input		P00	Edge detection vectored interrupt input (both			Input	(B)
						rising edge and falling edge detection)
	INT0		Input		P10	Edge detection vectored		With clock elimination	Input	(B)-C
						interrupt input (detection		circuit/asynchronous
						edge can be selected).		selectable
						Noise elimination circuit
						can be specified.
	KR0 to KR3		Input/Output		P60 to P63	Falling edge detection testable input			Input	(F)-A
	S12 to S15		Output		–	Segment signal output			Note 2	G-A
	S16 to S19		Output		P93 to P90	Segment signal output			Input	H
	S20 to S23		Output		P83 to P80	Segment signal output			Input	H
	COM0 to COM3		Output		–	Common signal output			Note 2	G-B
VLC0 to VLC2			–		–	LCD drive power			–	–
						On-chip split resistor is enable (mask option).
	BIAS		Output		–	Output for external split resistor disconnect			Note 3	–
	LCDCL Note 4		Input/Output		P30	Clock output for externally expanded driver			Input	E-B
	SYNC Note 4		Input/Output		P31	Clock output for externally expanded driver sync			Input	E-B

Notes 1. Characters in parentheses indicate the Schmitt trigger input.

2.Each display output selects the following VLCX as input source. S12 to S15: VLC1, COM0 to COM2: VLC2, COM3: VLC0.

3.When a split resistor is contained ....... Low level

When no split resistor is contained ......High-impedance

4.These pins are provided for future system expansion.

At present, these pins are used only as pins P30 and P31.

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μPD753204, 753206, 753208

3.2 Non-Port Pins (2/2)

	Pin Name		Input/Output	Alternate	Function	After Reset	I/O Circuit
				Function			TYPE Note 1
	X1		Input	–	Crystal/ceramic connection pin for the system	–	–
					clock oscillator. When inputting the external
					clock, input the external clock to pin X1, and
	X2		–		the reverse phase of the external clock to pin
					X2.
			Input	–	System reset input (low-level active)	–	(B)
	RESET
	IC		–	–	Internally connected. Connect directly to VDD.	–	–
	VDD		–	–	Positive power supply	–	–
	VSS		–	–	Ground potential	–	–

Note Characters in parentheses indicate the Schmitt-trigger input.

10

μPD753204, 753206, 753208

3.3 Pin Input/Output Circuits

The μPD753208 pin input/output circuits are shown schematically.

(1/2)

TYPE A

TYPE D

VDD

VDD

data

P-ch

IN

P-ch

OUT

output

N-ch

N-ch

disable

Push-pull output that can be placed in output

CMOS specification input buffer.

high-impedance (both P-ch, N-ch off).

TYPE B

TYPE E-B

				VDD
				P.U.R.
			P.U.R.	P-ch
			enable
	IN
			data	IN/OUT
			Type D
			output
			disable
	Schmitt trigger input having hysteresis characteristic.		Type A
			P.U.R. : Pull-Up Resistor
	TYPE B-C		TYPE F-A
				VDD
	VDD			P.U.R.
		P.U.R.	P.U.R.	P-ch
			enable
	P-ch	P.U.R.	data
		enable		IN/OUT
			Type D
			output
			disable
	IN
			Type B
	P.U.R. : Pull-Up Resistor		P.U.R. : Pull-Up Resistor

11

μPD753204, 753206, 753208

(2/2)

TYPE F-B

VDD

		P.U.R
	P.U.R	P-ch
	enable
output		VDD
disable
(P)		P-ch
data		IN/OUT
output		N-ch
disable
	output
	disable
	(N)

TYPE H

SEG			TYPE G-A					P-ch IN/OUT
data
								N-ch

data

TYPE E-B

output disable

P.U.R : Pull-Up Resistor

TYPE G-A

TYPE M-C

P-ch

VDD

VLC0

P.U.R

N-ch

VLC1	P-ch			P.U.R.	P-ch
	N-ch
				enable
	P-ch	N-ch			IN/OUT
			data		N-ch
			OUT
SEG			output
		N-ch	disable
data

P-ch

VLC2

N-ch

N-ch

P.U.R : Pull-Up Resistor

TYPE G-B		TYPE M-D

						VDD
VLC0	P-ch				P.U.R.
	N-ch				(Mask Option)
						IN/OUT
				data		N-ch
VLC1						(+13-V
	P-ch	N-ch		output	VDD	withstand)
				disable
				input	P-ch
				instruction
			OUT
COM					P.U.R.Note	Voltage
						control
data
	N-ch P-ch					circuit
VLC2	P-ch				P.U.R. : Pull-Up Resistor
	N-ch
	N-ch			Note Pull-up resistor that only operates upon the execution
				of an input instruction when the pull-up resistor is not
				connected via the mask option (it is available during
				low-voltage).

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μPD753204, 753206, 753208

3.4 Recommended Connections for Unused Pins

Table 3-1. List of Recommended Connections for Unused Pins

		Pin		Recommended Connection
P00/INT4			Connect to VSS or VDD
			Connect individually to VSS or VDD via a resistor
P01/SCK
P02/SO/SB0
P03/SI/SB1			Connect to VSS
P10/INT0			Connect to VSS or VDD
P13/TI0
P20/PTO0			Input state: Connect individually to VSS or VDD via a resistor
P21/PTO1			Output state: No connection
P22/PCL/PTO2
P23/BUZ
P30/LCDCL
P31/SYNC
P32
P33
P50 to P53			Input state	: Connect to VSS
			Output state	: Connect to VSS (Do not connect pull-up
				resistor in the mask option)
P60/KR0 to P63/KR3			Input state	: Connect individually to VSS or VDD via a
				resistor
			Output state	: No connection
S0 to S15			No connection
COM0 to COM3
S16/P93 to S19/P90			Input state: Connect individually to VSS or VDD via a resistor
S20/P83 to S23/P80			Output state: No connection
VLC0 to VLC2			Connect to VSS
BIAS			Only if all of VLC0 to VLC2 are unused, connect to VSS.
			In other cases, no connection.
IC			Connect to VDD directly

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μPD753204, 753206, 753208

4 SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE

4.1 Difference Between Mk I and Mk II Modes

The CPU of the μPD753208 has the following two modes: Mk I and Mk II, either of which can be selected. The mode can be switched by bit 3 of the Stack Bank Select register (SBS).

• Mk I mode: Upward compatible with the μPD75308B. Can be used in the 75XL CPU with a ROM capacity of up to 16 Kbytes.

• Mk II mode: Incompatible with μPD75308B. Can be used in all the 75XL CPU including those products whose ROM capacity is more than 16 Kbytes.

Table 4-1. Differences between Mk I Mode and Mk II Mode

	Mk I mode	Mk II mode
Number of stack bytes	2 bytes	3 bytes
for subroutine instructions
BRA ! addr1 instruction	Not available	Available
CALLA ! addr1 instruction
CALL ! addr instruction	3 machine cycles	4 machine cycles
CALLF ! faddr instruction	2 machine cycles	3 machine cycles

Caution The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series. Software compatibility with products whose program memory exceeds 16 Kbytes can be raised by using this mode.

When the MkII mode is selected, the number of stack bytes increases by one byte per stack during subroutine call instruction execution compared with the MkI mode. When the !faddr instruction is used, the length of each machine cycle increases by 1 machine cycle. Therefore, if RAM efficiency or processing speed is emphasized over software compatibility, use of the MkI mode is recommended.

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μPD753204, 753206, 753208

4.2 Setting Method of Stack Bank Select Register (SBS)

Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format. The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be initialized to 100×B Note at the beginning of a program. When using the Mk II mode, it must be initialized to 000×BNote.

Note The desired numbers must be set in the × positions.

Figure 4-1. Stack Bank Select Register Format

Address	3	2	1		0		Symbol
F84H	SBS3	SBS2	SBS1		SBS0		SBS

Stack area specification

	0		0	Memory bank 0
	0		1	Memory bank 1
	Other	than		Setting prohibited
	above

0 0 must be set in the bit 2 position.

Mode switching specification

0 Mk II mode

1 Mk I mode

Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode. When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode.

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μPD753204, 753206, 753208

5. MEMORY CONFIGURATION

• Program Memory (ROM) ....	4096 × 8 bits (μPD753204)
....	6144 × 8 bits (μPD753206)
....	8192 × 8 bits (μPD753208)

–Addresses 0000H and 0001H

Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET signal is generated are written. Reset and start are possible at an arbitrary address.

–Addresses 0002H to 000DH

Vector table wherein the program start address and values set for the RBE and MBE by the vectored interrupts are written. Interrupt execution can be started at an arbitrary address.

–Addresses 0020H to 007FH

Table area referenced by the GETI instruction Note.

Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte instruction, or two 1-byte instructions. It is used to decrease the program steps.

•Data Memory (RAM)

–Data area ... 512 words × 4 bits (000H to 1FFH)

–Peripheral hardware area ... 128 words × 4 bits (F80H to FFFH)

16

μPD753204, 753206, 753208

Figure 5-1. Program Memory Map (1/3)

(a) μPD753204

Address

7

6

5

4

0

0 0 0 H

MBE

RBE

0

0

Internal reset start address

(high-order 4 bits)

Internal reset start address

(low-order 8 bits)

0 0 2 H

MBE

RBE

0

0

INTBT/INT4

start address

(high-order 4 bits)

INTBT/INT4

start address

(low-order 8 bits)

0 0 4 H

MBE

RBE

0

0

INT0

start address

(high-order 4 bits)

CALLF

INT0

start address

(low-order 8 bits)

! faddr

instruction

0 0 6 H

entry

address

Branch address of

BR BCXA, BR BCDE,

BR !addr, BRA !addr1Note or

CALLA !addr1Note

0 0 8 H

MBE

RBE

0

0

INTCSI

start address

(high-order 4 bits)

instructions

CALL !addr instruction

INTCSI

start address

(low-order 8 bits)

subroutine entry address

0 0 A H

MBE

RBE

0

0

INTT0

start address

(high-order 4 bits)

BR $addr instruction

INTT0

start address

(low-order 8 bits)

relative branch address

–15 to –1,

0 0 C H

MBE

RBE

0

0

INTT1/INTT2

start address

(high-order 4 bits)

+2 to +16

INTT1/INTT2

start address

(low-order 8 bits)

BRCB

! caddr instruction

branch address

0 2 0 H

GETI instruction reference table

0 7 F H

0 8 0 H

		Branch destination
		address and
		subroutine entry
		address when GETI
7 F F H		instruction is executed
8 0 0 H

F F F H

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction.

17

μPD753204, 753206, 753208

Figure 5-1. Program Memory Map (2/3)

						(b)	μPD753206
Address		7	6	5			0
0 0 0 0	H	MBE	RBE	0	Internal reset start address		(high-order 5 bits)
					Internal reset start address		(low-order 8 bits)
0 0 0 2	H	MBE	RBE	0	INTBT/INT4	start address	(high-order 5 bits)
					INTBT/INT4	start address	(low-order 8 bits)
0 0 0 4	H	MBE	RBE	0	INT0	start address	(high-order 5 bits)
					INT0	start address	(low-order 8 bits)
0 0 0 6	H
0 0 0 8	H	MBE	RBE	0	INTCSI	start address	(high-order 5 bits)
					INTCSI	start address	(low-order 8 bits)
0 0 0 A H		MBE	RBE	0	INTT0	start address	(high-order 5 bits)
					INTT0	start address	(low-order 8 bits)
0 0 0 C H		MBE	RBE	0	INTT1/INTT2	start address	(high-order 5 bits)
					INTT1/INTT2	start address	(low-order 8 bits)

0 0 2 0 H

GETI instruction reference table

0 0 7 F H

0 0 8 0 H

0 7 F F H

0 8 0 0 H

0 F F F H

1 0 0 0 H

			Branch address
			of BR BCXA, BR
	CALLF
			BCDE, BR ! addr,
	! faddr
			BRA ! addr1Note or
	instruction		CALLA ! addr1Note
	entry		instructions
	address
			CALL ! addr
			instruction
			subroutine entry
			address
			BR $ addr
			instruction relative
			branch address
			–15 to –1,
			+2 to +16

BRCB ! caddr instruction branch address

Branch destination address and subroutine entry address when GETI instruction is executed

BRCB ! caddr instruction branch address

1 7 F F H

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction.

18

μPD753204, 753206, 753208

Figure 5-1. Program Memory Map (3/3)

						(c) μPD753208
Address		7	6	5			0
0 0 0 0	H	MBE	RBE	0	Internal reset start address		(high-order 5 bits)
					Internal reset start address		(low-order 8 bits)
0 0 0 2	H	MBE	RBE	0	INTBT/INT4	start address	(high-order 5 bits)
					INTBT/INT4	start address	(low-order 8 bits)
0 0 0 4	H	MBE	RBE	0	INT0	start address	(high-order 5 bits)
					INT0	start address	(low-order 8 bits)
0 0 0 6	H
0 0 0 8	H	MBE	RBE	0	INTCSI	start address	(high-order 5 bits)
					INTCSI	start address	(low-order 8 bits)
0 0 0 A H		MBE	RBE	0	INTT0	start address	(high-order 5 bits)
					INTT0	start address	(low-order 8 bits)
0 0 0 C H		MBE	RBE	0	INTT1/INTT2	start address	(high-order 5 bits)
					INTT1/INTT2	start address	(low-order 8 bits)

0 0 2 0 H

GETI instruction reference table

0 0 7 F H

0 0 8 0 H

0 7 F F H

0 8 0 0 H

0 F F F H

1 0 0 0 H

			Branch address
	CALLF		of BR BCXA, BR
			BCDE, BR ! addr,
	! faddr
			BRA ! addr1Note or
	instruction		CALLA ! addr1Note
	entry		instructions
	address
			CALL ! addr
			instruction
			subroutine entry
			address
			BR $ addr
			instruction relative
			branch address
			–15 to –1,
			+2 to +16

BRCB ! caddr instruction branch address

Branch destination address and subroutine entry address when GETI instruction is executed

BRCB ! caddr instruction branch address

1 F F F H

Note Can be used only in the Mk II mode.

Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order eight bits of PC by executing the BR PCDE or BR PCXA instruction.

19

μPD753204, 753206, 753208

Figure 5-2. Data Memory Map

0 0 0 H

General-purpose register area

0 1 F H

0 2 0 H

		Stack area Note
	Data area	0 F F H
	static RAM	1 0 0 H
	(512×4)

1 E B H

1 E C H Display data

memory area

1 F 7 H

1 F 8 H

1 F F H

Data memory	Memory bank

(32 × 4)

0

256 × 4

(224 × 4)

256 × 4

(236 × 4)

1

(12 × 4)

(8 × 4)

					Not incorporated
			F 8 0 H
			128 × 4
Peripheral hardware area								15

F F F H

Note As a stack area, either memory bank 0 or 1 can be selected.

20

			μPD753204, 753206, 753208
6. PERIPHERAL HARDWARE FUNCTION
6.1 Digital I/O Port
There are three kinds of I/O ports.
	• CMOS input ports (Ports 0, 1)	:	6
	• CMOS input/output ports (Ports 2, 3, 6, 8, 9)	:	20
	• N-ch open-drain input/output ports (Port 5)	:	4
	Total		30

Table 6-1. Types and Features of Digital Ports

Port	Function	Operation and features		Remarks
PORT0	4-bit input	The alternate function pins have an output function		Also used for the INT4, SCK,
		with operation mode when using the serial interface		SO/SB0, and SI/SB1 pins.
		function.
PORT1	1-bit input	2-bit input dedicated port		Also used for the INT0 and
				TI0.
PORT2	4-bit I/O	Can be set to input mode or output mode in 4-bit		Also used for the PTO0 to
		units.		PTO2, PCL, and BUZ pins.
PORT3		Can be set to input mode or output mode bit-wise.		Also used for the LCDCL
				and SYNC pins.
PORT5	4-bit I/O (N-	Can be set to input mode or output mode in 4-bit		—
	channel open-	units. On-chip pull-up resistor can be specified
	drain, 13-V	by mask option bit-wise.
	withstand)
PORT6	4-bit I/O	Can be set to input mode or output mode bit-wise.		Also used for the KR0 to
				KR3 pins.
PORT8		Can be set to input mode	Ports 8 and 9 are paired	Also used for the S20 to
		or output mode in 4-bit	and data can be input/	S23 pins.
		units.	output in 8-bit units.
PORT9				Also used for the S16 to
				S19 pins.

21

μPD753204, 753206, 753208

6.2 Clock Generator

The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is shown in Figure 6-1.

The operation of the clock generator is determined by the Processor Clock Control Register (PCC). The instruction execution time can also be changed.

•0.95, 1.91, 3.81, 15.3 μs (system clock: @ 4.19-MHz operation)

•0.67, 1.33, 2.67, 10.7 μs (system clock: @ 6.0-MHz operation)

Figure 6-1. Clock Generator Block Diagram

	þ	· Basic interval timer (BT)
		· Timer/event counter 0
	ï
	ï	· Timer counter 1, 2
	ï	· Watch timer
	ý	· LCD controller/driver
	ï
		· Serial interface
	ï
		· INT0 noise eliminator
	ï
		· Clock output circuit
	ü

X1

VDD

					System clock	fX	1/1 to 1/4096
					oscillator		Divider
				X2		1/2	1/4 1/16
					Oscillation stop
								Divider
							Selector	1/4		F
								þ	· CPU
									· INT0 noise eliminator
				PCC				ý
				PCC0				ü	· Clock output circuit
bus				PCC1
Internal							HALT	F/F
	4
	HALT	Note		PCC2			S
	STOP		Note	PCC3			R	Q
				PCC2,	STOP	F/F		Wait release signal from BT
				PCC3
					Q	S
				Clear

RESET Signal

R							Standby release signal from
							interrupt control circuit

Note Instruction execution

22

μPD753204, 753206, 753208

Remarks 1. fX = System clock frequency

2.Φ = CPU clock

3.PCC: Processor Clock Control Register

4.One clock cycle (tCY) of the CPU clock is equal to one machine cycle of the instruction.

6.3Clock Output Circuit

The clock output circuit is provided to output the clock pulses from the PCL pin (also functions as P22 or PTO2) to the remote control wave outputs and peripheral LSIs.

• Clock Output (PCL) : Φ, 524, 262, 65.5 kHz (system clock: @ 4.19-MHz operation)

Φ, 750, 375, 93.8 kHz (system clock: @ 6.0-MHz operation)

Figure 6-2. Clock Output Circuit Block Diagram

From clock generator

Φ

fX/23

Selector

fX/24

fX/26

From timer counter (channel 2)

Selector

									PORT2.2
									P22
CLOM3		0	CLOM1		CLOM0		CLOM
									output latch

Output buffer

PCL/PTO2/P22

Bit 2 of PMGB

Port 2 I/O mode specification bit

4

Internal bus

Remark Special care has been taken in designing the chip so that small-width pulses may not be output when

switching clock output enable/disable.

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μPD753204, 753206, 753208

6.4 Basic Interval Timer/Watchdog Timer

The basic interval timer/watchdog timer has the following functions.

•Interval timer operation to generate a reference time interrupt

•Watchdog timer operation to detect program runaway and reset the CPU

•Selects and counts the wait time when the standby mode is released

•Reads the contents of counting

Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram

From clock
generator
fX/25		Clear			Clear
fX/27	MPX	Basic interval timer		Set	BT
		(8-bit frequency divider)			interrupt
fX/29					request flag	Vectored
			BT			interrupt
fX/212					IRQBT	request signal
	3		Wait release signal		Internal reset
			when standby is
					signal
			released.
BTM3 BTM2 BTM1 BTM0		BTM		WDTM
				SET1Note
SET1Note	4	8		1

Internal bus

Note Instruction execution

24