NEC UPD753208GT-XXX-T2, UPD753208GT-XXX-T1, UPD753208GT-XXX-E2, UPD753208GT-XXX-E1, UPD753208GT-XXX Datasheet
...
©
1996
DATA SHEET
4-BIT SINGLE-CHIP MICROCONTROLLERS
The µPD753208 is one of the 75XL Series 4-bit single-chip microcontrollers and has a data processing
capability comparable to that of an 8-bit microcontroller.
The
µ
PD753208 has an on-chip LCD controller/driver and is based on the µPD75308B of the 75X Series.
However, the
µ
PD75308B is supplied in an 80-pin package, whereas the µPD753208 is supplied in a 48pin package (375 mils, 0.65-mm pitch) and therefore is suitable for small-scale application systems. In
addition, the
µ
PD753208 features expanded CPU functions and performs high-speed operations at a low
voltage of 1.8 V.
Detailed information about functions can be found in the following user’s manual. Be sure to read it
before designing.
µ
PD753208 User’s Manual: U10158E
Document No. U10166EJ2V0DS00 (2nd edition)
Date Published March 1997 N
Printed in Japan
MOS INTEGRATED CIRCUIT
µ
PD753204, 753206, 753208
The information in this document is subject to change without notice.
The mark shows major revised points.
Features
• Low-voltage operation: VDD = 1.8 to 5.5 V
– Can be driven by two 1.5-V batteries
• Internal memory
– Program memory (ROM):
4096 × 8 bits (
µ
PD753204)
6144 × 8 bits (
µ
PD753206)
8192 × 8 bits (
µ
PD753208)
– Data memory (RAM):
512 × 4 bits
• Variable instruction execution time for high-speed
operation and power saving operation
– 0.95, 1.91, 3.81, 15.3
µ
s (@ 4.19-MHz operation)
– 0.67, 1.33, 2.67, 10.7
µ
s (@ 6.0-MHz operation)
• Internal programmable LCD controller/driver
• Small package:
48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
• One-time PROM version:
µ
PD75P3216
Applications
Remote controllers, Cameras, Sphygnomamometers, Compact-disc radio cassette player compo systems,
gas meters, etc.
Ordering Information
Part number Package ROM (× 8 bits)
µ
PD753204GT-××× 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 4096
µ
PD753206GT-××× 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 6144
µ
PD753208GT-××× 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch) 8192
Remark ××× indicates ROM code suffix.
Unless otherwise specified, references in this data sheet to the
µ
PD753208 mean the
µ
PD753204 and the µPD753206.
2
µ
PD753204, 753206, 753208
Function Outline
Parameter Function
Instruction execution time • 0.95, 1.91, 3.81, 15.3 µs (@ 4.19-MHz operation with system clock)
• 0.67, 1.33, 2.67, 10.7 µs (@ 6.0-MHz operation with system clock)
Internal memory ROM 4096 × 8 bits (
µ
PD753204)
6144 × 8 bits (µPD753206)
8192 × 8 bits (
µ
PD753208)
RAM 512 × 4 bits
General-purpose register • 4-bit operation: 8 × 4 banks
• 8-bit operation: 4 × 4 banks
Input/ CMOS input 6 Connecting on-chip pull-up resistors can be specified by software: 5
output
CMOS input/output 20 Connecting on-chip pull-up resistors can be specified by software: 20
port
Also used for segment pins: 8
N-ch open-drain 4 On-chip pull-up resistors can be specified by mask option
input/output 13-V withstand voltage
Total 30
LCD controller/driver • Segment selection: 4/8/12 segments (can be changed to CMOS input/
output port in 4-time units; max. 8)
• Display mode selection: Static
1/2 duty (1/2 bias)
1/3 duty (1/2 bias)
1/3 duty (1/3 bias)
1/4 duty (1/3 bias)
• On-chip split resistor for LCD drive can be specified by mask option
Timer 5 channels
• 8-bit timer/event counter: 1 channel
• 8-bit timer counter: 2 channels (can be used as the 16-bit timer counter, carrier
generator, and timer with gate)
• Basic interval timer/watchdog timer: 1 channel
• Watch timer: 1 channel
Serial interface • 3-wire serial I/O mode ... MSB or LSB can be selected for transferring first bit
• 2-wire serial I/O mode
• SBI mode
Bit sequential buffer (BSB) 16 bits
Clock output (PCL) • Φ, 524, 262, 65.5 kHz (@ 4.19-MHz operation with system clock)
• Φ, 750, 375, 93.8 kHz (@ 6.0-MHz operation with system clock)
Buzzer output (BUZ) • 2, 4, 32 kHz (@ 4.19-MHz operation with system clock)
• 2.93, 5.86, 46.9 kHz (@ 6.0-MHz with system clock)
Vectored interrupts External: 2, Internal: 5
Test input External: 1, Internal: 1
System clock oscillator Ceramic or crystal oscillator for system clock oscillation
Standby function STOP/HALT mode
Power supply voltage V
DD = 1.8 to 5.5 V
Package 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
3
µ
PD753204, 753206, 753208
CONTENTS
1. PIN CONFIGURATION (TOP VIEW) ....................................................................................................5
2. BLOCK DIAGRAM................................................................................................................................6
3. PIN FUNCTIONS ....................................................................................................................................7
3.1 Port Pins ......................................................................................................................................7
3.2 Non-Port Pins ..............................................................................................................................9
3.3 Pin Input/Output Circuits .........................................................................................................11
3.4 Recommended Connections for Unused Pins .......................................................................13
4. SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE ................................................14
4.1 Difference Between Mk I and Mk II Modes ..............................................................................14
4.2 Setting Method of Stack Bank Select Register (SBS) ...........................................................15
5. MEMORY CONFIGURATION .............................................................................................................16
6. PERIPHERAL HARDWARE FUNCTION ........................................................................................... 21
6.1 Digital I/O Port ...........................................................................................................................21
6.2 Clock Generator ........................................................................................................................22
6.3 Clock Output Circuit .................................................................................................................23
6.4 Basic Interval Timer/Watchdog Timer.....................................................................................24
6.5 Watch Timer ..............................................................................................................................25
6.6 Timer/Event Counter.................................................................................................................26
6.7 Serial Interface ..........................................................................................................................30
6.8 LCD Controller/Driver ...............................................................................................................32
6.9 Bit Sequential Buffer ................................................................................................................34
7. INTERRUPT FUNCTION AND TEST FUNCTION ..............................................................................35
8. STANDBY FUNCTION........................................................................................................................37
9. RESET FUNCTION .............................................................................................................................38
10. MASK OPTION ...................................................................................................................................41
11. INSTRUCTION SET ............................................................................................................................42
12. ELECTRICAL SPECIFICATIONS.......................................................................................................56
13. CHARACTERISTIC CURVES (REFERENCE VALUES) ...................................................................68
14. PACKAGE DRAWINGS .....................................................................................................................70
15. RECOMMENDED SOLDERING CONDITIONS .................................................................................71
4
µ
PD753204, 753206, 753208
APPENDIX A µPD753108, 753208, AND 75P3216 FUNCTIONAL LIST .............................................72
APPENDIX B DEVELOPMENT TOOLS.................................................................................................74
APPENDIX C RELATED DOCUMENTS ................................................................................................77
5
µ
PD753204, 753206, 753208
1. PIN CONFIGURATION (TOP VIEW)
• 48-pin plastic shrink SOP (375 mils, 0.65-mm pitch)
µ
PD753204GT-×××, µPD753206GT-×××,
µ
PD753208GT-×××
Note Connect IC (Internally Connected) pin directly to V
DD.
Pin Identification
P00 to P03 : Port0 S12 to S23 : Segment Output 12 to 23
P10, P13 : Port1 V
LC0 to VLC2 : LCD Power Supply 0 to 2
P20 to P23 : Port2 BIAS : LCD Power Supply Bias Control
P30 to P33 : Port3 LCDCL : LCD Clock
P50 to P53 : Port5 SYNC : LCD Synchronization
P60 to P63 : Port6 TI0 : Timer Input 0
P80 to P83 : Port8 PTO0 to PTO2: Programmable Timer Output 0 to 2
P90 to P93 : Port9 BUZ : Buzzer Clock
KR0 to KR3 : Key Return 0 to 3 PCL : Programmable Clock
COM0 to COM3 : Common Output 0 to 3 INT0, INT4 : External Vectored Interrupt 0, 4
SCK : Serial Clock X1, X2 : System Clock Oscillation 1, 2
SI : Serial Input RESET : Reset
SO : Serial Output IC : Internally Connected
SB0, SB1 : Serial Data Bus 0, 1 V
DD : Positive Power Supply
V
SS : Ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
COM0
COM1
COM2
COM3
BIAS
V
LC0
VLC1
VLC2
P30/LCDCL
P31/SYNC
P32
P33
V
SS
P50
P51
P52
P53
P60/KR0
P61/KR1
P62/KR2
P63/KR3
V
DD
X1
X2
S12
S13
S14
S15
P93/S16
P92/S17
P91/S18
P90/S19
P83/S20
P82/S21
P81/S22
P80/S23
P23/BUZ
P22/PCL/PTO2
P21/PTO1
P20/PTO0
P13/TI0
P10/INT0
P03/SI/SB1
P02/SO/SB0
P01/SCK
P00/INT4
RESET
IC
Note
6
µ
PD753204, 753206, 753208
2. BLOCK DIAGRAM
Note The ROM capacity depends on the product.
PORT0
PORT1
PORT2
PORT3
PORT5
PORT6
PORT8
PORT9
4
2
4
4
4
4
4
4
P00 to P03
P10,P13
P20 to P23
P30 to P33
P50 to P53
P60 to P63
P80 to P83
P90 to P93
S12 to S15
4
4
4
4
S16/P93 to
S19/P90
S20/P83 to
S23/P80
COM0 to COM3
VLC0
VLC1
VLC2
BIAS
LCDCL/P30
SYNC/P31
f
LCD
LCD
CONTROLLER/
DRIVER
INT0/P10
4
INTW
CPU CLOCK
Φ
IC V
DD VSS
RESET
STANDBY
CONTROL
SYSTEM
CLOCK
GENERATOR
X1 X2
CLOCK
DIVIDER
CLOCK
OUTPUT
CONTROL
PCL/PTO2/P22
f
X/2
N
INTERRUPT
CONTROL
BIT SEQ
BUFFER (16)
INTCSI TOUT
INTT2
CLOCKED
SERIAL
INTERFACE
8-BIT
TIMER
COUNTER #1
8-BIT
TIMER
COUNTER #2
CASCADED
16-BIT
TIMER
COUNTER
PTO1/P21
TOUT
PTO2/PCL/P22
SP (8)
SBS
BANK
GENERAL REG.
DATA
MEMORY
(RAM)
512 × 4 BITS
CY
ALU
PROGRAM
COUNTER
PROGRAM
MEMORY
Note
(ROM)
f
LCD
WATCH
TIMER
BASIC
INTERVAL
TIMER/
WATCHDOG
TIMER
BUZ/P23
TI0/P13
TPO0/P20
8-BIT
TIMER/EVENT
COUNTER #0
INTT1
INTT0 TOUT
SI/SB1/P03
SO/SB0/P02
SCK/P01
INT4/P00
KR0/P60 to
KR3/P63
DECODE
AND
CONTROL
INTBT
7
µ
PD753204, 753206, 753208
3. PIN FUNCTION
3.1 Port Pins (1/2)
Pin Name Input/Output
Alternate
Function
8-bit
After Reset
I/O Circuit
Function I/O TYPE
Note 1
P00 Input INT4 No Input (B)
P01 Input/Output SCK (F)-A
P02 Input/Output SO/SB0 (F)-B
P03 Input/Output SI/SB1 (M)-C
P10 Input INT0 No Input (B)-C
P13 TI0
P20 Input/Output PTO0 No Input E-B
P21 PTO1
P22 PCL/PTO2
P23 BUZ
P30 Input/Output LCDCL No Input E-B
P31 SYNC
P32 –
P33 –
P50 to Input/Output – No M-D
P53
Note 2
Notes 1. Characters in parentheses indicate the Schmitt-trigger input.
2. If on-chip pull-up resistors are not specified by mask option (when used as N-ch open-drain input port),
low level input leakage current increases when input or bit manipulation instruction is executed.
4-bit input port (PORT0).
For P01 to P03, on-chip pull-up resistors can
be specified by software in 3-bit units.
High level
(when pullup resistors
are
provided) or
highimpedance
Input port in 1 bit unit (PORT1).
On-chip pull-up resistors can be specified by
software in 2-bit units.
Noise elimination circuit can be specified with
P10/INT0.
4-bit input/output port (PORT2).
On-chip pull-up resistors can be specified by
software in 4-bit units.
Programmable 4-bit input/output port (PORT3).
This port can be specified input/output bitwise. On-chip pull-up resistor can be specified by software in 4-bit units.
N-ch open-drain 4-bit input/output port (PORT5).
A pull-up resistor can be contained bit-wise
(mask option).
Withstand voltage is 13 V in open-drain mode.
8
µ
PD753204, 753206, 753208
3.1 Port Pins (2/2)
Pin Name Input/Output
Alternate
Function
8-bit
After Reset
I/O Circuit
Function I/O TYPE
Note 1
P60 Input/Output KR0 No Input (F)-A
P61 KR1
P62 KR2
P63 KR3
P80 Input/Output S23 Yes Input H
P81 S22
P82 S21
P83 S20
P90 Input/Output S19 Input H
P91 S18
P92 S17
P93 S16
Notes 1. Characters in parentheses indicate the Schmitt-trigger input.
2. Do not connect on-chip pull-up resistors specified by software when using as segment signal output
pins.
Programmable 4-bit input/output port (PORT6).
This port can be specified for input/output bitwise.
On-chip pull-up resistors can be specified by
software in 4-bit units.
4-bit input/output port (PORT8).
On-chip pull-up resistors can be specified by
software in 4-bit units.
Note 2
4-bit input/output port (PORT9).
On-chip pull-up resistors can be specified by
software in 4-bit units.
Note 2
9
µ
PD753204, 753206, 753208
3.2 Non-Port Pins (1/2)
Pin Name Input/Output
Alternate
Function After Reset
I/O Circuit
Function TYPE
Note 1
TI0 Input P13 Inputs external event pulses to the timer/event Input (B)-C
counter.
PTO0 Output P20 Timer/event counter output Input E-B
PTO1 P21 Timer counter output
PTO2 P22/PCL
PCL P22/PTO2 Clock output
BUZ P23 Optional frequency output (for buzzer output
or system clock trimming)
SCK Input/Output P01 Serial clock input/output Input (F)-A
SO/SB0 P02 Serial data output (F)-B
Serial data bus input/output
SI/SB1 P03 Serial data input (M)-C
Serial data bus input/output
INT4 Input P00 Edge detection vectored interrupt input (both Input (B)
rising edge and falling edge detection)
INT0 Input P10 Input (B)-C
KR0 to KR3 Input/Output P60 to P63 Falling edge detection testable input Input (F)-A
S12 to S15 Output – Segment signal output Note 2 G-A
S16 to S19 Output P93 to P90 Segment signal output Input H
S20 to S23 Output P83 to P80 Segment signal output Input H
COM0 to COM3
Output – Common signal output Note 2 G-B
V
LC0 to VLC2 – – LCD drive power – –
On-chip split resistor is enable (mask option).
BIAS Output – Output for external split resistor disconnect Note 3 –
LCDCL
Note 4
Input/Output P30 Clock output for externally expanded driver Input E-B
SYNC
Note 4
Input/Output P31 Clock output for externally expanded driver sync Input E-B
Notes 1. Characters in parentheses indicate the Schmitt trigger input.
2. Each display output selects the following VLCX as input source.
S12 to S15: V
LC1, COM0 to COM2: VLC2, COM3: VLC0.
3. When a split resistor is contained ....... Low level
When no split resistor is contained ...... High-impedance
4. These pins are provided for future system expansion.
At present, these pins are used only as pins P30 and P31.
Edge detection vectored With clock elimination
interrupt input (detection circuit/asynchronous
edge can be selected). selectable
Noise elimination circuit
can be specified.
10
µ
PD753204, 753206, 753208
3.2 Non-Port Pins (2/2)
Pin Name Input/Output
Alternate
Function After Reset
I/O Circuit
Function TYPE
Note 1
X1 Input – Crystal/ceramic connection pin for the system – –
clock oscillator. When inputting the external
clock, input the external clock to pin X1, and
X2 – the reverse phase of the external clock to pin
X2.
RESET Input – System reset input (low-level active) – (B)
IC – – Internally connected. Connect directly to V
DD.– –
V
DD – – Positive power supply – –
VSS – – Ground potential – –
Note Characters in parentheses indicate the Schmitt-trigger input.
11
µ
PD753204, 753206, 753208
3.3 Pin Input/Output Circuits
The
µ
PD753208 pin input/output circuits are shown schematically.
TYPE A
TYPE B
TYPE D
TYPE E-B
TYPE B-C
TYPE F-A
V
DD
IN
P-ch
N-ch
data
output
disable
N-ch
P-ch
IN
OUT
V
DD
P-ch
output
disable
data
P.U.R.
enable
Type D
Type A
IN/OUT
V
DD
P.U.R.
enable
P.U.R.
P-ch
IN
V
DD
P.U.R.
P.U.R.
enable
P-ch
IN/OUT
Type D
Type B
output
disable
data
P.U.R. : Pull-Up Resistor P.U.R. : Pull-Up Resistor
P.U.R. : Pull-Up Resistor
Schmitt trigger input having hysteresis characteristic.
CMOS specification input buffer.
Push-pull output that can be placed in output
high-impedance (both P-ch, N-ch off).
P.U.R.
V
DD
(1/2)
12
µ
PD753204, 753206, 753208
TYPE F-B TYPE H
TYPE G-A
TYPE M-D
TYPE M-C
V
DD
P.U.R
enable
P.U.R
P-ch
P-ch
V
DD
N-ch
output
disable
(P)
data
output
disable
output
disable
(N)
IN/OUT
P.U.R : Pull-Up Resistor
data
output
disable
P.U.R.
enable
P.U.R
V
DD
P-ch
IN/OUT
N-ch
P.U.R : Pull-Up Resistor
V
LC1
P-ch N-ch
OUT
N-ch
V
LC2
N-ch
COM
data
P-ch
IN/OUT
N-ch
(+13-V
withstand)
V
DD
data
output
disable
P.U.R.
(Mask Option)
P.U.R. : Pull-Up Resistor
Voltage
control
circuit
Pull-up resistor that only operates upon the execution
of an input instruction when the pull-up resistor is not
connected via the mask option (it is available during
low-voltage).
Note
V
DD
P-ch
P.U.R.
Note
input
instruction
TYPE G-B
V
LC0
V
LC1
SEG
data
V
LC2
N-ch
SEG
data
data
output
disable
TYPE G-A
TYPE E-B
IN/OUT
(2/2)
P-ch
N-ch
V
LC0
P-ch
N-ch
P-ch
N-ch
P-ch N-ch
OUT
N-ch
P-ch
N-ch
P-ch
N-ch
P-ch
N-ch
13
µ
PD753204, 753206, 753208
3.4 Recommended Connections for Unused Pins
Table 3-1. List of Recommended Connections for Unused Pins
Pin Recommended Connection
P00/INT4 Connect to VSS or VDD
P01/SCK Connect individually to VSS or VDD via a resistor
P02/SO/SB0
P03/SI/SB1 Connect to VSS
P10/INT0 Connect to VSS or VDD
P13/TI0
P20/PTO0 Input state: Connect individually to VSS or V DD via a resistor
P21/PTO1 Output state: No connection
P22/PCL/PTO2
P23/BUZ
P30/LCDCL
P31/SYNC
P32
P33
P50 to P53 Input state : Connect to V
SS
Output state : Connect to VSS (Do not connect pull-up
resistor in the mask option)
P60/KR0 to P63/KR3 Input state : Connect individually to VSS or VDD via a
resistor
Output state : No connection
S0 to S15 No connection
COM0 to COM3
S16/P93 to S19/P90 Input state: Connect individually to VSS or VDD via a resistor
S20/P83 to S23/P80 Output state: No connection
VLC0 to VLC2 Connect to VSS
BIAS Only if all of VLC0 to VLC2 are unused, connect to VSS.
In other cases, no connection.
IC Connect to VDD directly
14
µ
PD753204, 753206, 753208
4 SWITCHING FUNCTION BETWEEN Mk I MODE AND Mk II MODE
4.1 Difference Between Mk I and Mk II Modes
The CPU of the
µ
PD753208 has the following two modes: Mk I and Mk II, either of which can be selected.
The mode can be switched by bit 3 of the Stack Bank Select register (SBS).
• Mk I mode: Upward compatible with the
µ
PD75308B. Can be used in the 75XL CPU with a ROM
capacity of up to 16 Kbytes.
• Mk II mode: Incompatible with
µ
PD75308B. Can be used in all the 75XL CPU including those products
whose ROM capacity is more than 16 Kbytes.
Table 4-1. Differences between Mk I Mode and Mk II Mode
Mk I mode Mk II mode
Number of stack bytes 2 bytes 3 bytes
for subroutine instructions
BRA ! addr1 instruction Not available Available
CALLA ! addr1 instruction
CALL ! addr instruction 3 machine cycles 4 machine cycles
CALLF ! faddr instruction 2 machine cycles 3 machine cycles
Caution The MkII mode supports a program area exceeding 16 Kbytes for the 75X and 75XL Series.
Software compatibility with products whose program memory exceeds 16 Kbytes can be raised
by using this mode.
When the MkII mode is selected, the number of stack bytes increases by one byte per stack
during subroutine call instruction execution compared with the MkI mode. When the !faddr
instruction is used, the length of each machine cycle increases by 1 machine cycle. Therefore,
if RAM efficiency or processing speed is emphasized over software compatibility, use of the MkI
mode is recommended.
15
µ
PD753204, 753206, 753208
Caution Since SBS. 3 is set to “1” after a RESET signal is generated, the CPU operates in the Mk I mode.
When executing an instruction in the Mk II mode, set SBS. 3 to “0” to select the Mk II mode.
4.2 Setting Method of Stack Bank Select Register (SBS)
Switching between the Mk I mode and Mk II mode can be done by the SBS. Figure 4-1 shows the format.
The SBS is set by a 4-bit memory manipulation instruction. When using the Mk I mode, the SBS must be
initialized to 100×B
Note
at the beginning of a program. When using the Mk II mode, it must be initialized to 000×B
Note
.
Note The desired numbers must be set in the × positions.
Figure 4-1. Stack Bank Select Register Format
SBS3 SBS2 SBS1 SBS0
3210
Symbol
SBS
Address
F84H
00
01
0
1
0
Memory bank 0
Memory bank 1
Other than
above
0 must be set in the bit 2 position.
Stack area specification
Mk II mode
Mk I mode
Mode switching specification
Setting prohibited
16
µ
PD753204, 753206, 753208
5. MEMORY CONFIGURATION
• Program Memory (ROM) .... 4096 × 8 bits (
µ
PD753204)
.... 6144 × 8 bits (
µ
PD753206)
.... 8192 × 8 bits (
µ
PD753208)
– Addresses 0000H and 0001H
Vector table wherein the program start address and the values set for the RBE and MBE at the time a RESET
signal is generated are written. Reset and start are possible at an arbitrary address.
– Addresses 0002H to 000DH
Vector table wherein the program start address and values set for the RBE and MBE by the vectored
interrupts are written. Interrupt execution can be started at an arbitrary address.
– Addresses 0020H to 007FH
Table area referenced by the GETI instruction
Note
.
Note The GETI instruction realizes a 1-byte instruction on behalf of an arbitrary 2-byte instruction, 3-byte
instruction, or two 1-byte instructions. It is used to decrease the program steps.
• Data Memory (RAM)
– Data area ... 512 words × 4 bits (000H to 1FFH)
– Peripheral hardware area ... 128 words × 4 bits (F80H to FFFH)
17
µ
PD753204, 753206, 753208
Figure 5-1. Program Memory Map (1/3)
(a)
µ
PD753204
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
000H
Address
7654
MBE RBE 0 0 Internal reset start address (high-order 4 bits)
0
002H MBE RBE 0 0 INTBT/INT4 (high-order 4 bits)start address
004H MBE RBE 0 0 INT0 (high-order 4 bits)start address
006H
008H MBE RBE 0 0 INTCSI (high-order 4 bits)start address
00AH MBE RBE 0 0 INTT0 (high-order 4 bits)start address
00CH MBE RBE 0 0 INTT1/INTT2 (high-order 4 bits)start address
020H
07FH
080H
7FFH
800H
FFFH
GETI instruction reference table
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
BRCB
! caddr instruction
branch address
CALL !addr instruction
subroutine entry address
BR $addr instruction
relative branch address
–15 to –1,
+2 to +16
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
Internal reset start address
INTBT/INT4 start address
INT0 start address
INTCSI start address
INTT0 start address
INTT1/INTT2 start address
Branch address of
BR BCXA, BR BCDE,
BR !addr, BRA !addr1
Note
or
CALLA !addr1
Note
instructions
CALLF
! faddr
instruction
entry
address
18
µ
PD753204, 753206, 753208
Figure 5-1. Program Memory Map (2/3)
(b)
µ
PD753206
0000H
Address
0002H MBE RBE 0 INTBT/INT4 (high-order 5 bits)start address
0004H MBE RBE 0 INT0 (high-order 5 bits)start address
0006H
0008H MBE RBE 0 INTCSI (high-order 5 bits)start address
000AH MBE RBE 0 INTT0 (high-order 5 bits)start address
0020H
007FH
0080H
07FFH
0800H
MBE RBE 0
Internal reset start address (high-order 5 bits)
0FFFH
1000H
17FFH
GETI instruction reference table
000CH MBE RBE 0 INTT1/INTT2 (high-order 5 bits)start address
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
CALLF
! faddr
instruction
entry
address
BRCB ! caddr
instruction
branch
address
Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1
Note
or
CALLA ! addr1
Note
instructions
CALL ! addr
instruction
subroutine entry
address
BR $ addr
instruction relative
branch address
–15 to –1,
+2 to +16
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
BRCB ! caddr
instruction
branch
address
765 0
Internal reset start address
INTBT/INT4
INT0
INTCSI
INTT0
INTT1/INTT2
start address
start address
start address
start address
start address
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
19
µ
PD753204, 753206, 753208
Figure 5-1. Program Memory Map (3/3)
(c)
µ
PD753208
0000H
Address
0002H MBE RBE 0 INTBT/INT4 (high-order 5 bits)start address
0004H MBE RBE 0 INT0 (high-order 5 bits)start address
0006H
0008H MBE RBE 0 INTCSI (high-order 5 bits)start address
000AH MBE RBE 0 INTT0 (high-order 5 bits)start address
0020H
007FH
0080H
07FFH
0800H
MBE RBE 0
Internal reset start address (high-order 5 bits)
0FFFH
1000H
1FFFH
GETI instruction reference table
000CH MBE RBE 0 INTT1/INTT2 (high-order 5 bits)start address
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
(low-order 8 bits)
CALLF
! faddr
instruction
entry
address
BRCB ! caddr
instruction
branch
address
Branch address
of BR BCXA, BR
BCDE, BR ! addr,
BRA ! addr1
Note
or
CALLA ! addr1
Note
instructions
CALL ! addr
instruction
subroutine entry
address
BR $ addr
instruction relative
branch address
–15 to –1,
+2 to +16
Branch destination
address and
subroutine entry
address when GETI
instruction is executed
BRCB ! caddr
instruction
branch
address
765 0
Internal reset start address
INTBT/INT4
INT0
INTCSI
INTT0
INTT1/INTT2
start address
start address
start address
start address
start address
Note Can be used only in the Mk II mode.
Remark In addition to the above, a branch can be taken to the address indicated by changing only the low-order
eight bits of PC by executing the BR PCDE or BR PCXA instruction.
20
µ
PD753204, 753206, 753208
Figure 5-2. Data Memory Map
Note As a stack area, either memory bank 0 or 1 can be selected.
Data area
static RAM
(512×4)
Stack area
Note
General-purpose
register area
000H
01FH
0FFH
100H
1EBH
1ECH
1F7H
1F8H
1FFH
F80H
FFFH
Display data
memory area
Peripheral hardware area
Data memory Memory bank
0
(32 × 4)
256 × 4
(224 × 4)
256 × 4
(236 × 4)
(12 × 4)
(8 × 4)
Not incorporated
128 × 4
15
1
020H
21
µ
PD753204, 753206, 753208
6. PERIPHERAL HARDWARE FUNCTION
6.1 Digital I/O Port
There are three kinds of I/O ports.
• CMOS input ports (Ports 0, 1) : 6
• CMOS input/output ports (Ports 2, 3, 6, 8, 9) : 20
• N-ch open-drain input/output ports (Port 5) : 4
Total 30
Table 6-1. Types and Features of Digital Ports
Port Function Operation and features Remarks
PORT0 4-bit input The alternate function pins have an output function Also used for the INT4, SCK,
with operation mode when using the serial interface SO/SB0, and SI/SB1 pins.
function.
PORT1 1-bit input 2-bit input dedicated port Also used for the INT0 and
TI0.
PORT2 4-bit I/O Can be set to input mode or output mode in 4-bit Also used for the PTO0 to
units. PTO2, PCL, and BUZ pins.
PORT3 Can be set to input mode or output mode bit-wise. Also used for the LCDCL
and SYNC pins.
PORT5 4-bit I/O (N- Can be set to input mode or output mode in 4-bit —
channel open- units. On-chip pull-up resistor can be specified
drain, 13-V by mask option bit-wise.
withstand)
PORT6 4-bit I/O Can be set to input mode or output mode bit-wise. Also used for the KR0 to
KR3 pins.
PORT8 Can be set to input mode Ports 8 and 9 are paired Also used for the S20 to
or output mode in 4-bit and data can be input/ S23 pins.
units. output in 8-bit units.
PORT9 Also used for the S16 to
S19 pins.
22
µ
PD753204, 753206, 753208
6.2 Clock Generator
The clock generator provides the clock signals to the CPU and peripheral hardware and its configuration is
shown in Figure 6-1.
The operation of the clock generator is determined by the Processor Clock Control Register (PCC).
The instruction execution time can also be changed.
• 0.95, 1.91, 3.81, 15.3
µ
s (system clock: @ 4.19-MHz operation)
• 0.67, 1.33, 2.67, 10.7
µ
s (system clock: @ 6.0-MHz operation)
Figure 6-1. Clock Generator Block Diagram
Note Instruction execution
4
Φ
VDD
X2
X1
f
X
Oscillation stop
System clock
oscillator
1/2 1/4 1/16
1/1 to 1/4096
Divider
Selector
Divider
1/4
· CPU
· INT0 noise eliminator
· Clock output circuit
HALT F/F
S
RQ
Wait release signal from BT
RESET Signal
Standby release signal from
interrupt control circuit
S
R
Q
F/FSTOP
PCC2,
PCC3
Clear
STOP
Note
PCC2
PCC3
PCC1
PCC0
PCC
HALT
Note
Internal bus
· Basic interval timer (BT)
· Timer/event counter 0
· Timer counter 1, 2
· Watch timer
· LCD controller/driver
· Serial interface
· INT0 noise eliminator
· Clock output circuit
23
µ
PD753204, 753206, 753208
From clock
generator
Φ
f
X/2
3
fX/2
4
fX/2
6
Selector
CLOM3 0 CLOM1 CLOM04CLOM
P22
output latch
Port 2 I/O mode
specification bit
PORT2.2 Bit 2 of PMGB
Internal bus
Output buffer
PCL/PTO2/P22
From timer counter
(channel 2)
Selector
Remarks 1. f X = System clock frequency
2. Φ = CPU clock
3. PCC: Processor Clock Control Register
4. One clock cycle (t
CY) of the CPU clock is equal to one machine cycle of the instruction.
6.3 Clock Output Circuit
The clock output circuit is provided to output the clock pulses from the PCL pin (also functions as P22 or PTO2)
to the remote control wave outputs and peripheral LSIs.
• Clock Output (PCL) : Φ, 524, 262, 65.5 kHz (system clock: @ 4.19-MHz operation)
Φ, 750, 375, 93.8 kHz (system clock: @ 6.0-MHz operation)
Figure 6-2. Clock Output Circuit Block Diagram
Remark Special care has been taken in designing the chip so that small-width pulses may not be output when
switching clock output enable/disable.
24
µ
PD753204, 753206, 753208
From clock
generator
f
X/2
5
fX/2
7
fX/2
9
fX/2
12
MPX
BTM3 BTM2 BTM1 BTM0 BTM
4
SET1
Note
Internal bus
81
Basic interval timer
(8-bit frequency divider)
Clear
BT
Wait release signal
when standby is
released.
Set
Clear
3
WDTM
SET1
Note
Internal reset
signal
Vectored
interrupt
request signal
BT
interrupt
request flag
IRQBT
6.4 Basic Interval Timer/Watchdog Timer
The basic interval timer/watchdog timer has the following functions.
• Interval timer operation to generate a reference time interrupt
• Watchdog timer operation to detect program runaway and reset the CPU
• Selects and counts the wait time when the standby mode is released
• Reads the contents of counting
Figure 6-3. Basic Interval Timer/Watchdog Timer Block Diagram
Note Instruction execution
Loading...