NEC UPD75008GB-A-XXX-3B4, UPD75008GB-XXX-3B4, UPD75008CU-XXX, UPD75008CU-A-XXX, UPD75006GB-XXX-3B4 Datasheet

DATA SHEET

MOS INTEGRATED CIRCUIT

μPD75004, 75006, 75008

4-BIT SINGLE-CHIP MICROCOMPUTER

DESCRIPTION

The μPD75008 is one of the 75X Series 4-bit single-chip microcomputer.

In addition to high-speed operation with 0.95 μs minimum instruction execution time for the CPU, the

μPD75008 employs a serial bus interface with standard NEC format, the μPD75004 is a powerful product with a high cost/performance ratio.

The μPD75P008 with PROM, which is provided with μPD75008, is applicable for evaluating systems under development, or for small-scale production of developed systems.

Detailed functions are described in the following user’s manual. Be sure to read it for designing.

μPD7500X Series User’s Manual: IEM-5033

FEATURES

∙Capable of high-speed operation and variable instruction execution time to power save

•0.95 μs, 1.91 μs, 15.3 μs (Main system clock: operating at 4.19 MHz)

•122 μs (Subsystem clock: operating at 32.768 kHz)

∙75X architecture comparable to that for an 8-bit microcomputer is employed

∙Built-in NEC standard serial bus interface (SBI)

∙Clock operation at reduced power dissipation (5 μA TYP. : operating at 3 V)

∙Enhanced timer function (3 channels)

∙Interrupt functions especially enhanced for applications, such as remote control receiver

APPLICATIONS

VCRs, CD players, telephones, cameras, blood pressure gauges, etc.

Unless otherwise specified, μPD75008 is treated as the representative model throughout this manual.

The information in this document is subject to change without notice.

Document No.	IC-2633C	The mark shows major revised points.
(O. D. No.	IC-7673E)
Date Published	November 1993 P	ã NEC Corporation 1990
Printed in Japan

μPD75004, 75006, 75008

ORDERING INFORMATION

Part Number	Package	Quality Grade
μPD75004CU-xxx	42-pin plastic shrink DIP (600 mil)	Standard
μPD75004GB-xxx-3B4	44-pin plastic QFP (■10 mm)	Standard
μPD75006CU-xxx	42-pin plastic shrink DIP (600 mil)	Standard
μPD75006GB-xxx-3B4	44-pin plastic QFP (■10 mm)	Standard
μPD75008CU-xxx	42-pin plastic shrink DIP (600 mil)	Standard
μPD75008GB-xxx-3B4	44-pin plastic QFP (■10 mm)	Standard
Remarks: xxx is ROM code number.

Please refer to “Quality Grade on NEC Semiconductor Devices” (Document Number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

2

								μPD75004, 75006, 75008
FUNCTIONAL OUTLINE
	Item						Function
	Instruction			0.95, 1.91, and 15.3 μs, (Main system clock: operating at 4.19 MHz)
	Execution Time			122 μs (Subsystem clock: operating at 32.768 kHz)
				4096 × 8-bit (μPD75004)
	Internal		ROM	6016 × 8-bit (μPD75006)
	Memory
				8064 × 8-bit (μPD75008)
			RAM	512 × 4-bit
	General-Purpose			• 4-bit manipulation: 8
	Registers			• 8-bit manipulation: 4
					8		CMOS Input pins	Internal pull-up resistor
								specification by software
					18		CMOS input/output pins	is possible. : 25
	I/O Port			34			Can directly drive LED: 4
					8		N-ch open-drain	Withstand voltage: 10V
							input/output	Internal pull-up resistor
							Can directly drive LED: 8	specification by mask option
								is possible.
					Timer/event counter
	Timer			3 chs	Basic interval timer: Also serves as watchdog timer
					Watch timer: Buzzer output possible
	Serial			3-line serial I/O mode
	Interface			2-line serial I/O mode
				SBI mode
	Bit Sequential			16 bits
	Buffer
	Clock Output Function			Φ, fx/23, fx/24, fx/26
	Vector Interrupt			External: 3, Internal: 3
	Test Input			External: 1, Internal: 1
	System Clock			Main system clock oscillation ceramic/crystal oscillator
	Oscillator			Subsystem clock oscillation crysal ocillator
	Standby Function			STOP/HALT mode
	Operating			–40 to +85°C
	Temperature Range
	Operating Supply			2.7 to 6.0 V
	Voltage
	Package			42-pin plastic shrink DIP (600 mil)
				44-pin plastic QFP (■10 mm)

3

μPD75004, 75006, 75008

CONTENTS

1.	PIN CONFIGURATION (TOP VIEW) ...............................................................................................				6
2.	BLOCK DIAGRAM ...........................................................................................................................				8
3.	PIN FUNCTIONS..............................................................................................................................				9
	3.1	PORT PINS.............................................................................................................................................			9
	3.2	NON PORT PINS ...................................................................................................................................			11
	3.3	PIN INPUT/OUTPUT CIRCUITS ...........................................................................................................			12
	3.4	SELECTION OF MASK OPTION ..........................................................................................................			14
	3.5	RECOMMENDED PROCESSING OF UNUSED PINS ..........................................................................			14
	3.6	NOTES ON USING THE P00/INT4, AND RESET PINS ......................................................................			15
4.	MEMORY CONFIGURATION ..........................................................................................................				16
5.	PERIPHERAL HARDWARE FUNCTIONS ........................................................................................				20
	5.1	PORTS ....................................................................................................................................................			20
	5.2	CLOCK GENERATOR CIRCUIT ............................................................................................................			21
	5.3	CLOCK OUTPUT CIRCUIT ....................................................................................................................			22
	5.4	BASIC INTERVAL TIMER .....................................................................................................................			23
	5.5	WATCH TIMER ......................................................................................................................................			24
	5.6	TIMER/EVENT COUNTER .....................................................................................................................			24
	5.7	SERIAL INTERFACE ..............................................................................................................................			26
	5.8	BIT SEQUENTIAL BUFFER ...................................................................................................................			28
6.	INTERRUPT FUNCTIONS................................................................................................................				28
7.	STANDBY FUNCTIONS ..................................................................................................................				30
8.	RESET FUNCTION...........................................................................................................................				31
9.	INSTRUCTION SET .........................................................................................................................				33
10.	ELECTRICAL SPECIFICATIONS ......................................................................................................				40
11.	CHARACTERISTIC CURVES ...........................................................................................................				53

4

		μPD75004, 75006, 75008
12.	PACKAGE DRAWINGS ...................................................................................................................	58
13.	RECOMMENDED SOLDERING CONDITIONS ...............................................................................	61
APPENDIX A. DEVELOPMENT TOOLS ..............................................................................................		62
APPENDIX B. RELATED DOCUMENTS ..............................................................................................		63

5

μPD75004, 75006, 75008

1.PIN CONFIGURATION (Top View)

•42-pin plastic shrink DIP (600 mil)

XT1 1

XT2 2

RESET 3

X1 4

X2 5

P33 6

P32 7

P31 8

P30 9

P81 10

P80 11

SI/SB1/P03 12

SO/SB0/P02 13

SCK/P01 14

INT4/P00 15

TI0/P13 16

INT2/P12 17

INT1/P11 18

INT0/P10 19

NC 20

VDD 21

• 44-pin plastic QFP (■ 10 mm)

xxx-PD75008CUμ

xxx-PD75006CUμ

xxx-PD75004CUμ

42 VSS

41 P40

40 P41

39 P42

38 P43

37 P50

36 P51

35 P52

34 P53

33 P60/KR0

32 P61/KR1

31 P62/KR2

30 P63/KR3

29 P70/KR4

28 P71/KR5

27 P72/KR6

26 P73/KR7

25 P20/PTO0

24 P21

23 P22/PCL

22 P23/BUZ

	P73/KR7	P20/PTO0 P21 P22/PCL P23/BUZ VDD NC P10/INT0 P11/INT1	P12/INT2	NC
	44 43 42 41 40 39 38 37 36 35 34				P03/TI0
P72/KR6	1			33
P71/KR5	2			32	P00/INT4
P70/KR4	3			31	P01/SCK
P63/KR3	4	μ PD75004GB–xxx–3B4		30	P02/SO/SB0
P62/KR2	5			29	P03/SI/SB1
P61/KR1	6	μ PD75006GB–xxx–3B4		28	P80
P60/KR0	7	μ PD75008GB–xxx–3B4		27	P81
P53	8			26	P30
P52	9			25	P31
P51	10			24	P32
P50	11			23	P33
	12 13 14 15 16 17 18 19 20 21 22
	NC	P43 P42 P41 P40 V XT1 XT2 RESET	X1	X2
		SS

6

						μPD75004, 75006, 75008
Pin names
	P00-P03		: Port 0	SO		: Serial Output
	P10-P13		: Port 1	SB0,SB1		: Serial Bus 0,1
	P20-P23		: Port 2	RESET		: Reset Input
	P30-P33		: Port 3	TI0		: Timer Input 0
	P40-P43		: Port 4	PTO0		: Programmable Timer Output 0
	P50-P53		: Port 5	BUZ		: Buzzer Clock
	P60-P63		: Port 6	PCL		: Programmable Clock
	P70-P73		: Port 7	INT0, 1, 4		: External Test Interrupt 0,1,4
	P80-P81		: Port 8	INT2		: External Test Input 2
	KR0-KR7		: Key Return	X1, 2		: Main System Clock Oscillation 1,2
	SCK		: Serial Clock	XT1, 2		: Subsystem Clock Oscillation 1,2
	SI		: Serial Input	NC		: No Connection

7

8

	BASIC
	INTERVAL
	TIMER
	INTBT	PROGRAM	SP (8)
		COUNTER *
TI0/P13	TIMER/EVENT		CY
			ALU
PTO0/P20	COUNTER
	#0

	INTT0	BANK
BUZ/P23	WATCH
	TIMER

		PROGRAM					GENERAL REG.
	INTW
		MEMORY
		(ROM)
		4096 ×	8 BITS
SI/SB1/P03		μ			DECODE
	CLOCKED	( PD75004)
SO/SB0/P02		6016 ×	8 BITS		AND
	SERIAL	μ
		( PD75006)			CONTROL		DATA
SCK/P01	INTERFACE	8064 ×	8 BITS
		μ					MEMORY
		( PD75008)					(RAM)
	INTCSI						512	×	4 BITS
INT0/P10
INT1/P11
INT2/P12	INTERRUPT
	CONTROL
INT4/P00
KR0/P60
–KR7/P73				fX /2 N
		CLOCK			SYSTEM CLOCK
				CLOCK	GENERATOR	STAND BY	CPU
	BIT SEQ.	OUTPUT
				DIVIDER		CONTROL	CLOCK
	BUFFER (16)	CONTROL
					SUB MAIN
		PCL/P22			XT1 XT2 X1	X2	V DD		V SS RESET

*: For μPD75004, 12 bits. For μPD75006 and μPD75008, 13 bits.

PORT 0	4	P00-P03
		P10-P13
PORT 1	4
PORT 2	4	P20-P23
		P30-P33
PORT 3	4
PORT 4	4	P40-P43
PORT 5	4	P50-P53
PORT 6	4	P60-P63
PORT 7	4	P70-P73
PORT 8	2	P80-P81

DIAGRAM BLOCK .2

75008 75006, PD75004,μ

μPD75004, 75006, 75008

3.PIN FUNCTIONS

3.1	PORT PINS (1/2)
				Also Served							Input/
Pin Name			Input/Output					Function	8-Bit I/O	When Reset	Output
				As							Circuit
											TYPE*1
	P00		Input	INT4							B
			Input/								F -A
	P01				SCK		4-bit input port (PORT0)
			Output
							Pull-up resistors can be specified in 3-bit		X	Input
	P02		Input/	SO/SB0			units for the P01 to P03 pins by software.				F -B
			Output
	P03		Input/	SO/SB1							M -C
			Output
	P10			INT0				With noise elimination function
	P11		Input	INT1			4-bit input port (PORT1)		X	Input	B -C
	P12			INT2			Internal pull-up resistors can be
							specified in 4-bit units by software.
	P13				TI0
	P20			PTO0
							4-bit input/output port (PORT2)
	P21		Input/		—
							Internal pull-up resistors can be		X	Input	E-B
	P22		Output		PCL		specified in 4-bit units by software.
	P23				BUZ
P30*2					—		Programmable 4-bit input/output port
							(PORT3)
P31*2					—
			Input/				This port can be specified for input/		X	Input	E-B
P32*2			Output		—		output in bit units.
							Internal pull-up resistors can be
P33*2					—		specified in 4-bit units by software.
							N-ch open-drain 4-bit input/output port			High level
							(PORT4)
			Input/							(with internal
P40-43*2					—		Internal pull-up resistors can be				M
										pull-up
			Output
							specified in bit units. (mask option)			resistor) or
							Resistive voltage is 10 V in the open-
										high imped-
							drain mode.
										ance
									●
							N-ch open-drain 4-bit input/output port			High level
			Input/				(PORT5)			(with internal
P50-53*2					—		Internal pull-up resistors can be			pull-up	M
			Output
							specified in bit units. (mask option)			resistor) or
							Resistive voltage is 10 V in the open-			high imped-
							drain mode.			ance

*1: Circles indicate Schmitt trigger inputs.

2: Can directly drive LED.

9

μPD75004, 75006, 75008

3.1	PORT PINS (2/2)
										Input/
Pin Name		Input/Output			Also Served		Function	8-Bit I/O	When Reset	Output
					As					Circuit
										TYPE*1
P60						KR0	Programmable 4-bit input/output port
							(PORT6)
P61						KR1
			Input/				This port can be specified for input/		Input	F -A
P62			Output			KR2	output in bit units.
							Internal pull-up resistors can be
								●
P63						KR3	specified in 4-bit units by software.
P70						KR4
							4-bit input/output port (PORT7)
P71			Input/			KR5
							Internal pull-up resistors can be		Input	F -A
			Output			KR6
P72							specified in 4-bit units by software.
P73						KR7
P80			Input/			—	2-bit input/output port (PORT8)		Input
							Internal pull-up resistors can be	X		E-B
P81			Output			—
							specified in 2-bit units by software.

*1: Circles indicate Schmitt trigger inputs.

2: Can directly drive LED.

10

μPD75004, 75006, 75008

3.2NON PORT PINS

Also Served

Input/

Pin Name

Input/Output

Functon

When Reset

Output

As

Circuit

TYPE*1

TI0

Input

P13

Timer/event counter external event pulse Input

Input

B -C

PTO0

Input/

P20

Timer/event counter output

Input

E-B

Output

PCL

Input/

P22

Clock output

Input

E-B

Output

BUZ

Input/

P23

Fixed frequency output (for buzzer or for trim-

Input

E-B

Output

ming the system clock)

Input/

Serial clock input/output

SCK

P01

Input

F -A

Output

SO/SB0

Input/

P02

Serial data output

Input

F -B

Output

Serial bus input/output

SI/SB1

Input/

P03

Serial data input

Input

M -C

Output

Serial bus input/output

INT4

Input

P00

Edge detection vector interrupt input (both

Input

B

rising and falling edge detection are effective)

INT0

Input

P10

Edge detection vector

Clock synchronous

interrupt input (detection

Input

B -C

INT1

P11

edge can be selected)

Asynchronous

INT2

Input

P12

Edge detection testable

Asynchronous

Input

B -C

input (rising edge detection)

KR0-KR3

Input/

P60-P63

Parallel falling edge detection testable input

Input

F -A

Output

KR4-KR7

Input/

P70-P73

Parallel falling edge detection testable input

Input

F -A

Output

To connect the crystal/ceramic oscillator to the

X1, X2

Input

—

main system clock generator. When inputting the

Input

—

external clock, input the external clock to pin X1,

and the reverse phase of the external clock to pin

X2.

XT1

Input

To connect the crystal oscillator to the subsystem

Input

clock generator.

—

—

When the external clock is used, pin XT1 inputs

XT2

—

the external clock. In this case, pin XT2 must be

—

left open.

Input

—

—

RESET

System reset input

B

NC *2

—

—

No connection

—

—

VDD

—

—

Positive power supply

—

—

VSS

—

—

GND

—

—

*1: Circles indicate Schmitt trigger inputs.

2:When sharing the printed circut board with the μPD75P008, the NC pin must be directly connected to VDD.

11

μPD75004, 75006, 75008

3.3PIN INPUT/OUTPUT CIRCUITS

The following shows a simplified input/output circuit diagram for each pin of the μPD75008.

	TYPE A (for TYPE E–B)		TYPE D (for TYPE E–B, F–A)
	VDD			VDD
			data
		P–ch		OUT
	IN
		N–ch	output
			disable
	Input buffer of CMOS standard		Push–pull output that can be set in a output
			high–impedance state (both P–ch and N–ch are off)
	TYPE B		TYPE E–B	VDD
				P.U.R.
			P.U.R.	P–ch
			enable
	IN		data
				IN/OUT
			Type D
			output
			disable
			Type A
	Schmitt trigger input with hysteresis characteristics		P.U.R. : Pull–Up Resistor
	TYPE B–C		TYPE F–A	VDD
	VDD			P.U.R.
	P.U.R.		P.U.R.	P–ch
			enable
	P–ch	P.U.R.	data
		enable		IN/OUT
			Type D
			output
	IN		disable
			Type B
	P.U.R. : Pull–Up Resistor		P.U.R. : Pull–Up Resistor

12

				μPD75004, 75006, 75008
TYPE F–B			TYPE M–C
			VDD
			P.U.R.		VDD
	P.U.R.				P.U.R.
			P–ch
output	enable
		VDD		P.U.R.	P–ch
disable				enable
(P)
		P-ch	IN/OUT		IN/OUT
data
			data
output		N-ch			N-ch
disable
output			output
disable
			disable
	(N)
P.U.R. : Pull–Up Resistor
			P.U.R. : Pull–Up Resistor
TYPE M	VDD
	P.U.R.
	enable		IN/OUT
	(Mask option)
data		N-ch
		(withstand
output		voltage:
		+10 V)
disable
	Middle voltage input buffer
	(withstand voltage: +10 V)
P.U.R. : Pull–Up Resistor

13

μPD75004, 75006, 75008

3.4SELECTION OF MASK OPTION

The following mask operations are available and can be specified for each pin.

Table 3-1 Mask Option Selection

	Pin		Mask Option
	P40-P43,	•	With pull-up resistor	• Without pull-up resistor
	P50-P53

*: Mask option can be specified in bit units.

3.5 RECOMMENDED PROCESSING OF UNUSED PINS

			Table 3-2	Processing of Unused Pins
			Pin	Recommended Connections
	P00/INT4			Connect to VSS
	P01/SCK
	P02/SO/SB0			Connect to VSS or VDD
	P03/SI/SB1
	P10/INT0-P12/INT2			Connect to VSS
	P13/TI0
	P20/PTO0
	P21
	P22/PCL
	P23/BUZ
	P30-P33			Input : Connect to VSS or VDD
	P40-P43			Output: Open
	P50-P53
	P60-P63
	P70-P73
	P80-P81
	XT1			Connect to VSS or VDD
	XT2			Open

14

μPD75004, 75006, 75008

3.6 NOTES ON USING THE P00/INT4, AND RESET PINS

In addition to the functions described in Sections 3.1 PORT PINS and 3.2 NON PORT PINS, an exclusive function for setting the test mode, in which the internal fuctions of the μPD75008 are tested (solely used for

IC tests), is provided to the P00/INT4 and RESET pins.

If a voltage exceeding VDD is applied to either of these pins, the μPD75008 is put into test mode. Therefore, even when the μPD75008 is in normal operation, if noise exceeding the VDD is input into any of these pins, the

μPD75008 will enter the test mode, and this will cause problems for normal operation.

As an example, if the wiring to the P00/INT4 pin or the RESET pin is long, stray noise may be picked up and the above montioned problem may occur.

Therefore, all wiring to these pins must be made short enough to not pick up stray noise. If noise cannot be avoided, suppress the noise using a capacitor or diode as shown in the figure below.

∙Connect a diode having a low VF across P00/INT4 and RESET, and VDD. (0.3 V max.)

VDD

Low VF		VDD
diode

∙Connect a capacitor across P00/INT4 and RESET, and VDD.

VDD

VDD

P00/INT4, RESET

P00/INT4, RESET

15

μPD75004, 75006, 75008

4.MEMORY CONFIGURATION

∙Program memory (ROM) ... 4096 × 8 bits (0000H-0FFFH) : μPD75004

... 6016 × 8 bits (0000H-177FH) : μPD75006

... 8064 × 8 bits (0000H-1F7FH) : μPD75008

•0000H-0001H : Vector table to which address from which program is started is written after reset

•0002H-000BH: Vector table to which address from which program is started is written after interrupt

•0020H-007FH : Table area referenced by GETI instruction

∙Data memory (RAM)

•Data area .... 512 × 4 bits (000H–1FFH)

•Peripheral hardware area .... 128 × 4 bits (F80H–FFFH)

Address	7	6	5	4
000H	MBE		0		0		Internal reset start address (upper 4 bits)
		0
							Internal reset start address (lower 8 bits)
002H	MBE						INTBT/INT4 start address (upper 4 bits)
		0	0		0
							INTBT/INT4 start address (lower 8 bits)
004H	MBE						INT0 start address (upper 4 bits)
		0	0		0
							INT0 start address (lower 8 bits)
006H	MBE						INT1 start address (upper 4 bits)
		0	0		0
							INT1 start address (lower 8 bits)
008H	MBE						INTCSI start address (upper 4 bits)
		0	0		0
							INTCSI start address (lower 8 bits)
00AH	MBE						INTT0 start address (upper 4 bits)
		0	0		0
							INTT0 start address (lower 8 bits)

020H

GETI instruction reference table

07FH

080H

7FFH

800H

FFFH

0

CALLF
!faddr
instruction			CALL ! addr
entry			instruction
address			subroutine
			entry address
			BRCD ! caddr
			instruction
			branch address
			BR $addr
			instruction
			relational
			branch address
			(–15 to –1,
			+2 to +16)
				Branch destination
				address and
				subroutine entry
				address for
				GETI instruction

Fig. 4-1 Program Memory Map (μPD75004)

16

μPD75004, 75006, 75008

Address	7	6	5
0000H	MBE		0		Internal reset start address (upper 5 bits)
		0
					Internal reset start address (lower 8 bits)
0002H	MBE				INTBT/INT4 start address (upper 5 bits)
		0	0
					INTBT/INT4 start address (lower 8 bits)
0004H	MBE				INT0 start address (upper 5 bits)
		0	0
					INT0 start address (lower 8 bits)
0006H	MBE				INT1 start address (upper 5 bits)
		0	0
					INT1 start address (lower 8 bits)
0008H	MBE				INTCSI start address (upper 5 bits)
		0	0
					INTCSI start address (lower 8 bits)
000AH	MBE				INTT0 start address (upper 5 bits)
		0	0
					INTT0 start address (lower 8 bits)

0020H

GETI instruction reference table

007FH

0080H

07FFH

0800H

0FFFH

1000H

177FH

0

CALLF
! faddr
instruction				CALL ! addr
entry				instruction
address				subroutine
				entry address
		BRCB
	! caddr			BR ! addr
	instruction
		branch		instruction
	address			branch address
				BR $addr
				instruction
				relational
				branch address
				(–15 to –1,
				+2 to +16)
					Branch destination
					address and
					subroutine entry
					address for
					GETI instruction

BRCB ! caddr instruction branch address

Fig. 4-2 Program Memory Map (μPD75006)

17

μPD75004, 75006, 75008

Address	7	6	5
0000H	MBE		0		Internal reset start address (upper 5 bits)
		0
					Internal reset start address (lower 8 bits)
0002H	MBE				INTBT/INT4 start address (upper 5 bits)
		0	0
					INTBT/INT4 start address (lower 8 bits)
0004H	MBE				INT0 start address (upper 5 bits)
		0	0
					INT0 start address (lower 8 bits)
0006H	MBE				INT1 start address (upper 5 bits)
		0	0
					INT1 start address (lower 8 bits)
0008H	MBE				INTCSI start address (upper 5 bits)
		0	0
					INTCSI start address (lower 8 bits)
000AH	MBE				INTT0 start address (upper 5 bits)
		0	0
					INTT0 start address (lower 8 bits)

0020H

GETI instruction reference table

007FH

0080H

07FFH

0800H

0FFFH

1000H

1F7FH

0

CALLF
! faddr
instruction				CALL ! addr
entry				instruction
address				subroutine
				entry address
		BRCB
	! caddr			BR ! addr
	instruction
		branch		instruction
	address			branch address
				BR $addr
				instruction
				relational
				branch address
				(–15 to –1,
				+2 to +16)
					Branch destination
					address and
					subroutine entry
					address for
					GETI instruction

BRCB ! caddr instruction branch address

Fig. 4-3 Program Memory Map (μPD75008)

18

μPD75004, 75006, 75008

Data memory

Memory bank

General-purpose

000H

(8 × 4)

register area

007H

008H

Stack

area

256× 4

0

(248 × 4)

0FFH

Data area

Static RAM

100H

(512 × 4)

256× 4

1

1FFH

Not provided

F80H

128× 4

Peripheral hardware area

15

FFFH

Fig. 4-4 Data Memory Map

19

μPD75004, 75006, 75008

5.PERIPHERAL HARDWARE FUNCTIONS

5.1PORTS

I/O ports are classified into the following 3 kinds:
∙	CMOS input (PORT0, 1)	:	8
∙	CMOS input/output (PORT2, 3, 6, 7, and 8)	: 18
∙	N-ch open-drain input/output (PORT4, 5)	:	8

Total

: 34

Table 5-1 Port Function

Port Name	Function		Operation and Feature			Remarks
(Symbol)
PORT0			Can be always read or tested regardless of opera-			Multiplexed with SO/SB0,
	4-bit input					SI/SB1, SCK, INT0-2, 4,
PORT1			tion mode of multiplexed pin.
						and TIO
PORT3*			Can be set in input or output mode in 1-bit units.			Port 6 is multiplexed with
PORT6						KR0 to KR3.
	4-bit input/output					Port 2 is multiplexed with
PORT2			Can be set in input or output mode in 4-bit units.			PTO0, PCL, and BUZ.
PORT7			Ports 6 and 7 are used in pairs to input/output data			Port 7 is multiplexed with
			in 8-bit units.
						KR4-KR7.
PORT4*	4-bit input/output		Can be set in input or output mode in 4-bit units.			Can be connected to a
						pull-up resistor in 1-bit
PORT5*	(N-ch open-drain,		Ports 4 and 5 are used in pairs to input/output data			units by using mask
	10 V)		in 8-bit units.
						option.
PORT8	2-bit input/output		Can be set input or output mode in 2-bit units.			—

*: Can directly drive LED.

20