Loading...NEC UPD70216HLP-20, UPD70216HLP-16, UPD70208HLP-10, UPD70208HLP-12, UPD70208HGK-20-9EU Datasheet
...
DATA SHEET
MOS INTEGRATED CIRCUIT
μPD70208H, 70216H
V40HLTM, V50HLTM
16/8, 16-BIT MICROPROCESSOR
DESCRIPTION
The μPD70208H (V40HL) is a high-speed, low-power 16-/8-bit microprocessor based on the μPD70208 (V40TM) with 16-bit architecture, 8-bit data bus, and general-purpose peripheral functions.
The μPD70216H (V50HL) is a high-speed, low-power 16-bit microprocessor based on the μPD70216 (V50TM) with 16bit architecture, 16-bit data bus, and general-purpose peripheral functions.
The V40HL and V50HL offer 20 MHz operation, and in addition to the conventional standby functions, also allows the clock to be stopped by the use of fully static internal circuitry, thus achieving greatly reduced power consumption. It is also capable of 3 V operation in addition to the previous 5 V operation, making it ideally suited to battery driven systems.
Details are given in the following manuals. Be sure to read when carrying out design work.
•V40HL, V50HL User’s Manual – Hardware (U11610E)
•16-bit V seriesTM User’s Manual – Instruction (U11301J: Japanese version)
FEATURES
•High-speed, low-power version of V40 and V50
•High-performance CPU (V20TM/V30TM software compatible)
• Minimum instruction execution time: |
100 ns (20 MHz, 5 V) |
|
200 ns (10 MHz, 3 V) |
0.95 to 2.8 μs (20 MHz, 5 V)
1.9to 5.6 μs (10 MHz, 3 V)
•Maskable (ICU) & non-maskable (NMI) interrupt inputs
•μPD8080AF emulation function
•Standby functions, clock stoppage capability
•Standard peripheral LSI functions on chip
•Clock generator (CG)
•Programmable wait control unit (WCU)
•Refresh control unit (REFU)
• |
Timer/counter unit (TCU) |
··· |
μPD71054 subset |
• Serial control unit (SCU) |
··· |
μPD71051 subset |
|
• Interrupt control unit (ICU) |
··· |
μPD71059 subset |
|
• |
DMA control unit (DMAU) |
··· |
μPD71071/71037 subset (functions of either selectable) |
• Operating frequency: 10/12.5/16/20 MHz (at 5 V, with 20/25/32/40 MHz supplied externally) 5/6.25/8/10 MHz (at 3 V, with 10/12.5/16/20 MHz supplied externally)
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. U13225EJ4V0DS00 (4th edition) Date Published April 1999 N CP(K)
Printed in Japan
The mark 
shows the the major revised points.
© 
1995
|
|
|
μPD70208H, 70216H |
|
ORDERING INFORMATION |
|
|
|
|
(1) |
V40HL |
|
|
|
|
|
|
Max. Operating |
|
|
Part Number |
Package |
Frequency (MHz) |
|
|
|
|
|
|
|
μPD70208HGF-10-3B9 |
80-pin plastic QFP (14 × 20 mm) |
10 |
|
|
|
(Resin thickness 2.7 mm) |
|
|
|
μPD70208HGF-12-3B9 |
80-pin plastic QFP (14 × 20 mm) |
12.5 |
|
|
|
(Resin thickness 2.7 mm) |
|
|
|
μPD70208HGF-16-3B9 |
80-pin plastic QFP (14 × 20 mm) |
16 |
|
|
|
(Resin thickness 2.7 mm) |
|
|
|
μPD70208HGF-20-3B9 |
80-pin plastic QFP (14 × 20 mm) |
20 |
|
|
|
(Resin thickness 2.7 mm) |
|
|
|
μPD70208HGK-10-9EU |
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) |
10 |
|
|
|
(Resin thickness 1.0 mm) |
|
|
|
μPD70208HGK-12-9EU |
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) |
12.5 |
|
|
|
(Resin thickness 1.0 mm) |
|
|
|
μPD70208HGK-16-9EU |
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) |
16 |
|
|
|
(Resin thickness 1.0 mm) |
|
|
|
μPD70208HGK-20-9EU |
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) |
20 |
|
|
|
(Resin thickness 1.0 mm) |
|
|
|
μPD70208HLP-10 |
68-pin plastic QFJ (950 × 950 mil) |
10 |
|
|
μPD70208HLP-12 |
68-pin plastic QFJ (950 × 950 mil) |
12.5 |
|
|
μPD70208HLP-16 |
68-pin plastic QFJ (950 × 950 mil) |
16 |
|
|
μPD70208HLP-20 |
68-pin plastic QFJ (950 × 950 mil) |
20 |
|
(2) |
V50HL |
|
|
|
|
|
|
Max. Operating |
|
|
Part Number |
Package |
Frequency (MHz) |
|
|
|
|
|
|
|
μPD70216HGF-10-3B9 |
80-pin plastic QFP (14 × 20 mm) |
10 |
|
|
|
(Resin thickness 2.7 mm) |
|
|
|
μPD70216HGF-12-3B9 |
80-pin plastic QFP (14 × 20 mm) |
12.5 |
|
|
|
(Resin thickness 2.7 mm) |
|
|
|
μPD70216HGF-16-3B9 |
80-pin plastic QFP (14 × 20 mm) |
16 |
|
|
|
(Resin thickness 2.7 mm) |
|
|
|
μPD70216HGF-20-3B9 |
80-pin plastic QFP (14 × 20 mm) |
20 |
|
|
|
(Resin thickness 2.7 mm) |
|
|
|
μPD70216HGK-10-9EU |
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) |
10 |
|
|
|
(Resin thickness 1.0 mm) |
|
|
|
μPD70216HGK-12-9EU |
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) |
12.5 |
|
|
|
(Resin thickness 1.0 mm) |
|
|
|
μPD70216HGK-16-9EU |
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) |
16 |
|
|
|
(Resin thickness 1.0 mm) |
|
|
|
μPD70216HGK-20-9EU |
80-pin plastic TQFP (Fine pitch) (12 × 12 mm) |
20 |
|
|
|
(Resin thickness 1.0 mm) |
|
|
|
μPD70216HLP-10 |
68-pin plastic QFJ (950 × 950 mil) |
10 |
|
|
μPD70216HLP-12 |
68-pin plastic QFJ (950 × 950 mil) |
12.5 |
|
|
μPD70216HLP-16 |
68-pin plastic QFJ (950 × 950 mil) |
16 |
|
|
μPD70216HLP-20 |
68-pin plastic QFJ (950 × 950 mil) |
20 |
|
2 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
PIN CONFIGURATION (Top View)
(1)V40HL
• 80-pin Plastic QFP (14 × 20 mm)
μPD70208HGF-10-3B9
μPD70208HGF-12-3B9
μPD70208HGF-16-3B9
μPD70208HGF-20-3B9
A17/PS1 |
A18/PS2 |
A19/PS3 |
|
REFRQ |
HLDRQ |
HLDAK |
RESOUT |
VDD |
VDD |
|
RESET |
READY |
NMI |
BS2 |
BS1 |
BS0 |
|
MRD |
|
|
|
||||||||||||||||
|
|
|||||||||||||||||
|
||||||||||||||||||
|
|
|
|
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 |
||||||
A16/PS0 |
1 |
|
|
|
|
|
64 |
NC |
2 |
|
|
|
|
|
63 |
A15 |
3 |
|
|
|
|
|
62 |
A14 |
4 |
|
|
|
|
|
61 |
A13 |
5 |
|
|
|
|
|
60 |
A12 |
6 |
|
|
|
|
|
59 |
A11 |
7 |
|
|
|
|
|
58 |
A10 |
8 |
|
|
|
|
|
57 |
A9 |
9 |
|
|
|
|
|
56 |
A8 |
10 |
|
|
|
|
|
55 |
GND |
11 |
|
|
|
|
|
54 |
NC |
12 |
|
|
|
|
|
53 |
GND |
13 |
|
|
|
|
|
52 |
AD7 |
14 |
|
|
|
|
|
51 |
AD6 |
15 |
|
|
|
|
|
50 |
AD5 |
16 |
|
|
|
|
|
49 |
AD4 |
17 |
|
|
|
|
|
48 |
AD3 |
18 |
|
|
|
|
|
47 |
AD2 |
19 |
|
|
|
|
|
46 |
AD1 |
20 |
|
|
|
|
|
45 |
AD0 |
21 |
|
|
|
|
|
44 |
NC |
22 |
|
|
|
|
|
43 |
NC |
23 |
|
|
|
|
|
42 |
END/TC |
24 |
|
|
|
|
|
41 |
|
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 |
||||||
|
DMARQ0 |
DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD IC INTAK/SRDY/TOUT1 VDD |
INTP1 |
INTP2 |
INTP3 |
INTP4 |
INTP5 |
Caution Leave IC pin open.
IORD
NC
MWR
IOWR BUSLOCK
BUFR/W
BUFEN CLKOUT X1
X2
GND
NC
GND
High
ASTB
QS0
QS1
POLL
TCTL2
TOUT2
TCLK
NC
INTP7
INTP6
Data Sheet U13225EJ4V0DS00 |
3 |
μPD70208H, 70216H
• 80-pin Plastic TQFP (Fine pitch) (12 × 12 mm)
μPD70208HGK-10-9EU
μPD70208HGK-12-9EU
μPD70208HGK-16-9EU
μPD70208HGK-20-9EU
|
NC |
A16/PS0 A17/PS1 A18/PS2 A19/PS3 REFRQ HLDRQ HLDAK RESOUT VDD |
VDD RESET READY NMI BS2 BS1 BS0 |
MRD |
IORD |
NC |
|
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 |
|||||
A15 |
1 |
|
|
|
|
60 |
NC |
2 |
|
|
|
|
59 |
A14 |
3 |
|
|
|
|
58 |
A13 |
4 |
|
|
|
|
57 |
A12 |
5 |
|
|
|
|
56 |
A11 |
6 |
|
|
|
|
55 |
A10 |
7 |
|
|
|
|
54 |
A9 |
8 |
|
|
|
|
53 |
A8 |
9 |
|
|
|
|
52 |
GND |
10 |
|
|
|
|
51 |
GND |
11 |
|
|
|
|
50 |
AD7 |
12 |
|
|
|
|
49 |
AD6 |
13 |
|
|
|
|
48 |
AD5 |
14 |
|
|
|
|
47 |
AD4 |
15 |
|
|
|
|
46 |
AD3 |
16 |
|
|
|
|
45 |
AD2 |
17 |
|
|
|
|
44 |
AD1 |
18 |
|
|
|
|
43 |
AD0 |
19 |
|
|
|
|
42 |
NC |
20 |
|
|
|
|
41 |
|
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 |
|||||
|
NC |
END/TC DMARQ0 DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD |
INTAK/SRDY/TOUT1 VDD INTP1 INTP2 INTP3 INTP4 INTP5 |
INTP6 |
INTP7 |
NC |
NC
MWR
IOWR
BUSLOCK
BUFR/W
BUFEN CLKOUT X1
X2
GND
GND
High
ASTB
QS0
QS1
POLL
TCTL2
TOUT2
TCLK
NC
4 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
• 68-pin Plastic QFJ (950 × 950 mil)
μPD70208HLP-10
μPD70208HLP-12
μPD70208HLP-16
μPD70208HLP-20
|
|
A16/PS0 |
A17/PS1 |
A18/PS2 |
A19/PS3 |
REFRQ |
HLDRQ |
HLDAK |
RESOUT |
VDD |
RESET |
READY NMI BS2 |
BS1 |
BS0 |
MRD |
IORD |
|
A15 |
|
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
68 67 66 65 64 63 62 61 |
|
|||||
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
60 |
MWR |
|
A14 |
11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
59 |
IOWR |
A13 |
12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
58 |
BUSLOCK |
A12 |
13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
57 |
BUFR/W |
A11 |
14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
56 |
BUFEN |
A10 |
15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
55 |
CLKOUT |
A9 |
16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
54 |
X1 |
A8 |
17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
53 |
X2 |
GND |
18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
52 |
GND |
AD7 |
19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
51 |
High |
AD6 |
20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
50 |
ASTB |
AD5 |
21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
49 |
QS0 |
AD4 |
22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
48 |
QS1 |
AD3 |
23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
47 |
POLL |
AD2 |
24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
46 |
TCTL2 |
AD1 |
25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
45 |
TOUT2 |
AD0 |
26 |
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4344 |
TCLK |
||||||||||||||
|
|||||||||||||||||
|
|
END/TC |
DMARQ0 |
DMAAK0 |
DMARQ1 |
DMAAK1 |
DMARQ2 |
DMAAK2 |
DMARQ3/RXD |
DMAAK3/TXD |
INTAK/SRDY/TOUT1 |
INTP1 INTP2 INTP3 |
INTP4 |
INTP5 |
INTP6 |
INTP7 |
|
Data Sheet U13225EJ4V0DS00 |
5 |
μPD70208H, 70216H
(2)V50HL
• 80-pin Plastic QFP (14 × 20 mm)
μPD70216HGF-10-3B9
μPD70216HGF-12-3B9
μPD70216HGF-16-3B9
μPD70216HGF-20-3B9
A17/PS1 |
A18/PS2 |
A19/PS3 |
|
REFRQ |
HLDRQ |
HLDAK |
RESOUT |
VDD |
VDD |
|
RESET |
READY |
NMI |
BS2 |
BS1 |
BS0 |
|
MRD |
|
|
|
||||||||||||||||
|
|
|||||||||||||||||
|
|
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 |
||||||
A16/PS0 |
1 |
|
|
|
|
|
64 |
NC |
2 |
|
|
|
|
|
63 |
AD15 |
3 |
|
|
|
|
|
62 |
AD14 |
4 |
|
|
|
|
|
61 |
AD13 |
5 |
|
|
|
|
|
60 |
AD12 |
6 |
|
|
|
|
|
59 |
AD11 |
7 |
|
|
|
|
|
58 |
AD10 |
8 |
|
|
|
|
|
57 |
AD9 |
9 |
|
|
|
|
|
56 |
AD8 |
10 |
|
|
|
|
|
55 |
GND |
11 |
|
|
|
|
|
54 |
NC |
12 |
|
|
|
|
|
53 |
GND |
13 |
|
|
|
|
|
52 |
AD7 |
14 |
|
|
|
|
|
51 |
AD6 |
15 |
|
|
|
|
|
50 |
AD5 |
16 |
|
|
|
|
|
49 |
AD4 |
17 |
|
|
|
|
|
48 |
AD3 |
18 |
|
|
|
|
|
47 |
AD2 |
19 |
|
|
|
|
|
46 |
AD1 |
20 |
|
|
|
|
|
45 |
AD0 |
21 |
|
|
|
|
|
44 |
NC |
22 |
|
|
|
|
|
43 |
NC |
23 |
|
|
|
|
|
42 |
END/TC |
24 |
|
|
|
|
|
41 |
|
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 |
||||||
|
DMARQ0 |
DMAAK0 DMARQ1 DMAAK1 DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD IC INTAK/SRDY/TOUT1 VDD |
INTP1 |
INTP2 |
INTP3 |
INTP4 |
INTP5 |
Caution Leave IC pin open.
IORD
NC
MWR
IOWR
BUSLOCK BUFR/W BUFEN CLKOUT X1
X2
GND
NC
GND
UBE
ASTB
QS0
QS1
POLL
TCTL2
TOUT2
TCLK
NC
INTP7
INTP6
6 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
• 80-pin Plastic TQFP (Fine pitch) (12 × 12 mm)
μPD70216HGK-10-9EU
μPD70216HGK-12-9EU
μPD70216HGK-16-9EU
μPD70216HGK-20-9EU
|
NC |
A16/PS0 |
A17/PS1 A18/PS2 A19/PS3 REFRQ |
HLDRQ HLDAK RESOUT VDD |
VDD |
RESET |
READY |
NMI |
BS2 BS1 |
BS0 MRD |
IORD |
NC |
|
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 |
|||||||||||
AD15 |
1 |
|
|
|
|
|
|
|
|
|
|
60 |
NC |
2 |
|
|
|
|
|
|
|
|
|
|
59 |
AD14 |
3 |
|
|
|
|
|
|
|
|
|
|
58 |
AD13 |
4 |
|
|
|
|
|
|
|
|
|
|
57 |
AD12 |
5 |
|
|
|
|
|
|
|
|
|
|
56 |
AD11 |
6 |
|
|
|
|
|
|
|
|
|
|
55 |
AD10 |
7 |
|
|
|
|
|
|
|
|
|
|
54 |
AD9 |
8 |
|
|
|
|
|
|
|
|
|
|
53 |
AD8 |
9 |
|
|
|
|
|
|
|
|
|
|
52 |
GND |
10 |
|
|
|
|
|
|
|
|
|
|
51 |
GND |
11 |
|
|
|
|
|
|
|
|
|
|
50 |
AD7 |
12 |
|
|
|
|
|
|
|
|
|
|
49 |
AD6 |
13 |
|
|
|
|
|
|
|
|
|
|
48 |
AD5 |
14 |
|
|
|
|
|
|
|
|
|
|
47 |
AD4 |
15 |
|
|
|
|
|
|
|
|
|
|
46 |
AD3 |
16 |
|
|
|
|
|
|
|
|
|
|
45 |
AD2 |
17 |
|
|
|
|
|
|
|
|
|
|
44 |
AD1 |
18 |
|
|
|
|
|
|
|
|
|
|
43 |
AD0 |
19 |
|
|
|
|
|
|
|
|
|
|
42 |
NC |
20 |
|
|
|
|
|
|
|
|
|
|
41 |
|
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 |
|||||||||||
|
NC |
END/TC |
DMARQ0 DMAAK0 DMARQ1 DMAAK1 |
DMARQ2 DMAAK2 DMARQ3/RXD DMAAK3/TXD |
INTAK/SRDY/TOUT1 |
VDD |
INTP1 |
INTP2 |
INTP3 INTP4 |
INTP5 INTP6 |
INTP7 |
NC |
NC
MWR
IOWR
BUSLOCK
BUFR/W
BUFEN CLKOUT X1
X2
GND
GND
UBE
ASTB
QS0
QS1
POLL
TCTL2
TOUT2
TCLK
NC
Data Sheet U13225EJ4V0DS00 |
7 |
μPD70208H, 70216H
• 68-pin Plastic QFJ (950 × 950 mil)
μPD70216HLP-10
μPD70216HLP-12
μPD70216HLP-16
μPD70216HLP-20
|
|
A16/PS0 |
A17/PS1 |
A18/PS2 |
A19/PS3 |
REFRQ |
HLDRQ |
HLDAK |
RESOUT |
VDD |
RESET |
READY |
NMI |
BS2 |
BS1 |
BS0 |
MRD |
IORD |
|
AD15 |
|
9 |
8 |
7 |
6 |
5 |
4 |
3 |
2 |
1 |
68 67 66 65 64 63 62 61 |
|
|||||||
10 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
60 |
MWR |
|
AD14 |
11 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
59 |
IOWR |
AD13 |
12 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
58 |
BUSLOCK |
AD12 |
13 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
57 |
BUFR/W |
AD11 |
14 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
56 |
BUFEN |
AD10 |
15 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
55 |
CLKOUT |
AD9 |
16 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
54 |
X1 |
AD8 |
17 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
53 |
X2 |
GND |
18 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
52 |
GND |
AD7 |
19 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
51 |
UBE |
AD6 |
20 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
50 |
ASTB |
AD5 |
21 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
49 |
QS0 |
AD4 |
22 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
48 |
QS1 |
AD3 |
23 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
47 |
POLL |
AD2 |
24 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
46 |
TCTL2 |
AD1 |
25 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
45 |
TOUT2 |
AD0 |
26 |
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 4344 |
TCLK |
||||||||||||||||
|
|||||||||||||||||||
|
|
END/TC |
DMARQ0 |
DMAAK0 |
DMARQ1 |
DMAAK1 |
DMARQ2 |
DMAAK2 |
DMARQ3/RXD |
DMAAK3/TXD |
INTAK/SRDY/TOUT1 |
INTP1 |
INTP2 |
INTP3 |
INTP4 |
INTP5 |
INTP6 |
INTP7 |
|
8 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
PIN NAMES
A8-A15 |
: |
Address Bus |
|||||||||||||||||||
A16/PS0-A19/PS3 |
: |
Address/Processor Status |
|||||||||||||||||||
AD0-AD15 |
: |
Address Bus/Data Bus |
|||||||||||||||||||
ASTB |
: |
Address Strobe |
|||||||||||||||||||
BS0-BS2 |
: |
Bus Status |
|||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
BUFEN |
: |
Buffer Enable |
|||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
: |
Buffer Read/Write |
||||||
BUFR/W |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
: |
Bus Lock |
|||||
BUSLOCK |
|
|
|
||||||||||||||||||
CLKOUT |
: |
Clock Output |
|||||||||||||||||||
|
|
|
|
|
|
|
: |
DMA Acknowledge |
|||||||||||||
DMAAK0-DMAAK2 |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
||||||||||||
DMAAK3/TXD |
: |
DMA Acknowledge/Transmit Data |
|||||||||||||||||||
DMARQ0-DMARQ2 |
: |
DMA Request |
|||||||||||||||||||
DMARQ3/RXD |
: |
DMA Request/Receive Data |
|||||||||||||||||||
|
|
|
|
: |
End/Terminal Count |
||||||||||||||||
END/TC |
|||||||||||||||||||||
GND |
: |
Ground |
|||||||||||||||||||
High |
: |
High Level Output |
|||||||||||||||||||
HLDAK |
: |
Hold Acknowledge |
|||||||||||||||||||
HLDRQ |
: |
Hold Request |
|||||||||||||||||||
IC |
: |
Internally Connected |
|||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
||||||||||
INTAK/SRDY/TOUT1 |
: Interrupt Acknowledge/Serial Ready/Timer Output 1 |
||||||||||||||||||||
INTP1-INTP7 |
: Interrupt Request from Peripherals |
||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
: |
I/O Read |
|
IORD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
: |
I/O Write |
||||
IOWR |
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
: |
Memory Read |
||
MRD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
: |
Memory Write |
|||
MWR |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||
NC |
: |
No Connection |
|||||||||||||||||||
NMI |
: |
Non-Maskable Interrupt Request |
|||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||
POLL |
: |
Poll |
|||||||||||||||||||
QS0, QS1 |
: |
Queue Status |
|||||||||||||||||||
READY |
: |
Ready |
|||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
REFRQ |
: |
Refresh Request |
|||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESET |
: |
Reset |
|||||||||||||||||||
RESOUT |
: |
Reset Output |
|||||||||||||||||||
TCLK |
: |
Timer Clock |
|||||||||||||||||||
TCTL2 |
: |
Timer Control 2 |
|||||||||||||||||||
TOUT2 |
: |
Timer Output 2 |
|||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||
UBE |
: |
Upper Byte Enable |
|||||||||||||||||||
VDD |
: |
Power Supply |
|||||||||||||||||||
X1, X2 |
: |
Crystal |
|||||||||||||||||||
Data Sheet U13225EJ4V0DS00 |
9 |
μPD70208H, 70216H
BLOCK DIAGRAM |
|
|
|
|
|
|
A19/PS3 |
|
|
|
|
|
|
|
(1) |
V40HL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
A16/PS0- |
|
|
AD0-AD7 |
BS0-BS2 |
|
|
||
|
|
|
TXD |
SRDY |
RXD |
|
|
|
A8-A15 |
QS1 |
QS0 |
|||
|
TOUT2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TOUT1 |
TCU |
|
SCU |
|
|
|
|
|
|
BIU |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
TCTL2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TCLK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP7 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP6 |
|
|
|
|
|
|
|
|
|
WCU |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP5 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP4 |
ICU |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP3 |
|
|
|
|
CPU |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
INTP2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTAK |
|
|
|
|
|
|
|
|
|
|
BAU |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
NMI |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
X2 |
CG |
|
|
|
|
DMAU |
|
|
|
|
|
REFU |
|
|
|
|
|
|
|
|
|
|
|
|
||||
|
X1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKOUT |
DMARQ0 |
DMAAK0 |
DMARQ1 |
DMAAK1 |
DMARQ2 |
DMAAK2 |
DMARQ3 |
DMAAK3 |
END/TC |
|
REFRQ |
|
POLL
BUSLOCK
BUFEN
BUFR/W
High
ASTB
IOWR
IORD
MWR
MRD
READY
RESOUT
RESET
HLDAK
HLDRQ
CPU : |
Central Processing Unit |
REFU |
: |
Reflesh Control Unit |
|
CG |
: |
Clock Generator |
TCU |
: |
Timer/Count Unit |
BIU |
: |
Bus Interface Unit |
SCU |
: |
Serial Control Unit |
BAU |
: |
Bus Arbitration Unit |
ICU |
: |
Interrupt Control Unit |
WCU : |
Wait Control Unit |
DMAU : |
DMA Control Unit |
||
10 |
Data Sheet U13225EJ4V0DS00 |
|
|
|
|
|
|
|
|
|
|
|
|
|
μPD70208H, 70216H |
(2) |
V50HL |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TXD |
SRDY |
RXD |
|
|
|
A16/PS0-A19/PS3 |
AD0-AD15 |
BS0-BS2 |
QS1 |
QS0 |
|
TOUT2 |
|
|
|
|
|
|
|
|
|
|
|
POLL |
|
TOUT1 |
TCU |
|
SCU |
|
|
|
|
|
|
BIU |
|
BUSLOCK |
|
|
|
|
|
|
|
|
|
|
|
|||
|
TCTL2 |
|
|
|
|
|
|
|
|
|
|
|
BUFEN |
|
TCLK |
|
|
|
|
|
|
|
|
|
|
|
BUFR/W |
|
|
|
|
|
|
|
|
|
|
|
|
|
UBE |
|
|
|
|
|
|
|
|
|
|
|
|
|
ASTB |
|
|
|
|
|
|
|
|
|
|
|
|
|
IOWR |
|
INTP7 |
|
|
|
|
|
|
|
|
|
|
|
IORD |
|
|
|
|
|
|
|
|
|
|
|
|
MWR |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP6 |
|
|
|
|
|
|
|
|
|
WCU |
|
MRD |
|
|
|
|
|
|
|
|
|
|
|
|
||
|
INTP5 |
|
|
|
|
|
|
|
|
|
|
|
READY |
|
|
ICU |
|
|
|
|
|
|
|
|
|
|
|
|
INTP4 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESOUT |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP3 |
|
|
|
|
CPU |
|
|
|
|
|
RESET |
|
|
|
|
|
|
|
|
|
|
|
|
|||
|
INTP2 |
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
INTAK |
|
|
|
|
|
|
|
|
|
|
BAU |
HLDAK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
NMI |
|
|
|
|
|
|
|
|
|
|
|
HLDRQ |
|
X2 |
CG |
|
|
|
|
DMAU |
|
|
|
|
|
REFU |
|
|
|
|
|
|
|
|
|
|
|
|||
|
X1 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKOUT |
DMARQ0 |
DMAAK0 |
DMARQ1 |
DMAAK1 |
DMARQ2 |
DMAAK2 |
DMARQ3 |
DMAAK3 |
END/TC |
|
REFRQ |
Data Sheet U13225EJ4V0DS00 |
11 |
|
|
|
|
|
|
|
|
μPD70208H, 70216H |
|
|
DIFFERENCES FROM V40 AND V50 |
|
|
|
|
||||
|
|
|
|
|
|
|
|
|
|
|
Item |
|
|
V40HL, V50HL |
|
|
V40, V50 |
|
|
|
|
|
|
|
|
|
|
|
|
|
Operating supply voltage |
|
3 V, 5 V |
5 V |
|
||||
|
|
|
|
|
|
|
|
|
|
|
O p e r a t i n g |
VDD = 5 V |
|
MAX. : 10, 12.5, 16, 20 MHz |
MAX. : 8, 10 MHz |
|
|||
|
frequency |
|
|
MIN. : DC |
MIN. : 2 MHz |
|
|||
|
|
|
|
|
|
|
|
|
|
|
|
VDD = 3 V |
|
MAX. : 5, 6.25, 8, 10 MHz |
No operation |
|
|||
|
|
|
|
MIN. : DC |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Clock generator |
|
Variable scaling factor |
Fixed scaling factor |
|
||||
|
(CG) |
|
|
|
|
|
|
|
|
|
|
Variable instruction cycle time |
Fixed instruction cycle time |
|
|||||
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Maximum input frequency: 40 MHz |
Maximum input frequency: 20 MHz |
|
|||
|
|
|
|
|
|
|
|
|
|
|
Internal I/O relocation |
|
Switchable 8-bit boundary or 16-bit boundary |
V40: Relocation possible on 8-bit boundary |
|
||||
|
function |
|
relocation function |
V50: Relocation possible on 16-bit boundary |
|
||||
|
|
|
|
|
|
|
|
|
|
|
Wait control unit (WCU) |
|
Memory space: 5 divisionsNote 1 |
Memory space: 3 divisions |
|
||||
|
|
|
|
I/O space: 3 divisionsNote 2 |
I/O space: Not divided |
|
|||
|
Refresh control unit |
|
Refresh address: 16 bits |
Refresh address: 9 bits |
|
||||
|
(REFU) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
REFRQ extended timing supported |
No REFRQ extended timing |
|
|||||
|
|
|
|
|
|||||
|
|
|
|
|
|
|
|
|
|
|
Serial control unit (SCU) |
|
Dedicated baud rate generator incorporated |
No dedicated baund rate generator |
|
||||
|
|
|
|
|
|
incorporated |
|
||
|
|
|
|
|
|
|
|
|
|
|
DMA control unit (DMAU) |
|
μPD71071/71037 subset (either function |
μPD71071 subset |
|
||||
|
|
|
|
selectable) |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Standby functions |
|
HALT mode, STOP mode |
HALT mode only |
|
||||
|
|
|
|
|
|
|
|
|
|
Notes 1. Divided into 3 when a reset is performed.
2. Not divided when a reset is performed.
12 |
Data Sheet U13225EJ4V0DS00 |
|
|
|
μPD70208H, 70216H |
|
|
CONTENTS |
|
1. |
PIN FUNCTIONS ................................................................................................................................... |
15 |
|
|
1.1 |
LIST OF PIN FUNCTIONS ........................................................................................................................... |
15 |
|
1.2 |
PROCESSING OF UNUSED PINS .............................................................................................................. |
17 |
2. |
MEMORY AND I/O CONFIGURATION ................................................................................................ |
19 |
|
|
2.1 |
MEMORY SPACE ......................................................................................................................................... |
19 |
|
2.2 |
I/O SPACE .................................................................................................................................................... |
21 |
3. |
CPU |
........................................................................................................................................................ |
22 |
4. |
CG (CLOCK .................................................................................................................GENERATOR) |
24 |
|
5. |
BIU (BUS ..............................................................................................................INTERFACE UNIT) |
24 |
|
6. |
BAU ........................................................................................................(BUS ARBITRATION UNIT) |
25 |
|
7. WCU (WAIT ................................................................................................................CONTROL UNIT) |
27 |
||
|
7.1 ................................................................................................................................................... |
FEATURES |
27 |
|
7.2 ........................................................................................ |
RELATION BETWEEN WCU AND READY PIN |
28 |
8. |
REFU ....................................................................................................(REFRESH CONTROL UNIT) |
29 |
|
|
8.1 ................................................................................................................................................... |
FEATURES |
29 |
|
8.2 ............................................................................................................................ |
REFRESH OPERATIONS |
29 |
9. |
TCU ............................................................................................................(TIMER/COUNTER UNIT) |
30 |
|
|
9.1 ................................................................................................................................................... |
FEATURES |
30 |
|
9.2 ........................................................................................................... |
TCU INTERNAL BLOCK DIAGRAM |
30 |
10. SCU ..........................................................................................................(SERIAL CONTROL UNIT) |
31 |
||
|
10.1 ................................................................................................................................................... |
FEATURES |
31 |
|
10.2 ........................................................................................................... |
SCU INTERNAL BLOCK DIAGRAM |
31 |
11. ICU (INTERRUPT ....................................................................................................CONTROL UNIT) |
32 |
||
|
11.1 ................................................................................................................................................... |
FEATURES |
32 |
|
11.2 ............................................................................................................ |
ICU INTERNAL BLOCK DIAGRAM |
32 |
12. DMAU ............................................................................................................(DMA CONTROL UNIT) |
33 |
||
|
12.1 ................................................................................................................................................... |
FEATURES |
33 |
|
12.2 ....................................................................................................... |
DMAU INTERNAL BLOCK DIAGRAM |
33 |
13. STANDBY ........................................................................................................................FUNCTIONS |
34 |
||
14. RESET .............................................................................................................................OPERATION |
34 |
||
15. INSTRUCTION ...............................................................................................................................SET |
35 |
||
Data Sheet U13225EJ4V0DS00 |
13 |
|
|
|
μPD70208H, 70216H |
16. |
ELECTRICAL SPECIFICATIONS ......................................................................................................... |
66 |
|
|
16.1 |
AT 5 V OPERATION .................................................................................................................................... |
66 |
|
16.2 |
AT 3 V OPERATION .................................................................................................................................... |
75 |
17. |
PACKAGE DRAWINGS ........................................................................................................................ |
100 |
|
18. |
RECOMMENDED SOLDERING CONDITIONS ................................................................................... |
103 |
|
14 |
Data Sheet U13225EJ4V0DS00 |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
μPD70208H, 70216H |
|
|
1. PIN FUNCTIONS |
|
|
|
||||||||||||||||||
|
1.1 LIST OF PIN FUNCTIONS |
|
|
|
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin Name |
|
Input/Output |
Function |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD0 to AD15Note 1, 3 |
|
3-state I/O |
Time-division address/data bus |
|
||||||||||||||||
|
|
AD0 to AD7Note 2, 3 |
|
3-state I/O |
Time-division address/data bus |
|
||||||||||||||||
|
|
A8 to A15Note 2, 3 |
|
3-state output |
Address bus |
|
||||||||||||||||
|
|
A16/PS0 to A19/PS3Note 3 |
|
3-state output |
Time-division address/processor status |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output |
Refresh request |
|
|
|
|
REFRQ |
|
|
|
|
|
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HLDRQ |
|
Input |
Bus hold request |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HLDAK |
|
Output |
Bus hold acknowledge |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESET |
|
Input |
Reset |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESOUT |
|
Output |
System reset output |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
READY |
|
Input |
Bus cycle end |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
NMI |
|
Input |
Non-maskable interrupt |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note 3 |
|
3-state output |
Memory read strobe |
|
||||||||||
|
|
MRD |
|
|
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note 3 |
|
|
|
|
|||||||||
|
|
MWR |
|
3-state output |
Memory read strobe |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note 3 |
|
|
|
|
|||||||||||||||
|
|
IORD |
|
3-state output |
I/O read strobe |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note 3 |
|
|
|
|
||||||||
|
|
IOWR |
|
3-state output |
I/O write strobe |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ASTB |
|
Output |
Address strobe |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note 1, 3 |
|
|
|
|
|||||||||||
|
|
UBE |
|
3-state output |
Data bus upper byte enable |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HighNote 2 |
|
3-state output |
High level output |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
Note 3 |
|
|
|
|
||||||||
|
|
BUSLOCK |
|
3-state output |
Bus lock |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Input |
Floating-point operation processor polling |
|
|||||||||
|
|
POLL |
|
|
|
|
|
|
|
|||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3-state output |
Buffer read/write |
|
||||||||||
|
|
BUFR/WNote 3 |
|
|
||||||||||||||||||
|
|
|
|
|
|
|
|
Note 3 |
|
3-state output |
Buffer enable |
|
||||||||||
|
|
BUFEN |
|
|
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
X1 |
|
Input |
Crystal/external clock |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
X2 |
|
— |
|
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKOUT |
|
Output |
Clock output |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BS0 to BS2 Note 3 |
|
3-state output |
Bus status |
|
||||||||||||||||
|
|
QS0, QS1 |
|
Output |
Queue status |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TOUT2 |
|
Output |
Timer 2 output |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TCTL2 |
|
Input |
Timer 2 control |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TCLK |
|
Input |
Timer clock |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP1 to INTP7 |
|
Input |
Maskable interrupts |
|
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output |
Interrupt acknowledge/serial reception ready/timer 1 output |
|
||||||||||||
|
|
INTAK/SRDY/TOUT1 |
|
|
||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Notes 1. V50HL only
2.V40HL only
3.These pins are provided with a latch. Therefore, when they go into a high-impedance state, they hold the status before the high-impedance state until driven by an external device. It is not necessary to pull up or down the data bus. To invert the level of the pin that goes into a high-impedance state by an external device, a drive current higher than the latch invert current (IILH, IILL) is necessary.
Data Sheet U13225EJ4V0DS00 |
15 |
|
|
|
|
|
|
|
|
|
|
|
μPD70208H, 70216H |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin Name |
Input/Output |
Function |
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
XD |
Output |
DMA acknowledge 3/serial transmit data |
|
||
|
|
DMAAK3/T |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DMARQ3/RXD |
Input |
DMA request 3/serial receive data |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DMAAK0 to DMAAK2 |
Output |
DMA acknowledge |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DMARQ0 to DMARQ2 |
Input |
DMA request |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I/O |
DMA service forcible termination/DMA service completion |
|
||||
|
|
END/TC |
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
VDD |
— |
Positive power supply pin |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
GND |
— |
Ground potential pin |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
IC |
— |
Internal connection pin (External connection impossible) |
|
|||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
16 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
1.2 PROCESSING OF UNUSED PINS
Table 1-1 shows the processing (recommended connection) of the unused pins. Use of a resistor with a resistance of 1 to 10 kΩ is recommended to connect these pins to VDD or GND via resistor.
Table 1-1. Processing of Unused Pins
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Pin Name |
Input/Output |
Recommended Connection |
||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
AD0 to AD15Note 1 |
3-state I/O |
Open |
|||||||||||||||||||||
|
AD0 to AD7Note 2 |
3-state I/O |
|
|||||||||||||||||||||
|
A8 to A15Note 2 |
3-state output |
|
|||||||||||||||||||||
|
A16/PS0 to A19/PS3 |
3-state output |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output |
|
|
|
REFRQ |
|
|
|
|
|
|
|
|
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HLDRQ |
Input |
Connect to GND via resistor |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HLDAK |
Output |
Open |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
RESOUT |
Output |
Open |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
READY |
Input |
Connect to VDD via resistor |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
NMI |
Input |
Connect to GND via resistor |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3-state output |
Open |
||
|
MRD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3-state output |
|
||||
|
MWR |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3-state output |
|
|||
|
IORD |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
IOWR |
3-state output |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
ASTB |
Output |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Note 1 |
3-state output |
|
||||||||||||||||
|
UBE |
|
||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
HighNote 2 |
Output |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||||||
|
BUSLOCK |
3-state output |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Input |
Connect to GND via resistor |
|||||||||
|
|
POLL |
|
|
|
|
|
|
|
|
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3-state output |
Open |
||||||||||
|
BUFR/W |
|||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
3-state output |
|
||||||||||
|
|
BUFEN |
|
|
|
|
|
|
|
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CLKOUT |
Output |
Open |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
BS0 to BS2 |
3-state output |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
QS0, QS1 |
Output |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TOUT2 |
Output |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TCTL2 |
Input |
Connect to GND via resistor |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TCLK |
Input |
|
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
INTP1 to INTP7 |
Input |
Open |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output |
|
||||||||||||
|
INTAK/SRDY/TOUT1 |
|
||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Output |
|
|||||||||||||||
|
DMAAK3/TxD |
|
||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DMARQ3/RxD |
Input |
Connect to GND via resistor |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|||||||||||||||||
|
|
|
DMAAK0 |
to |
DMAAK2 |
|
Output |
Open |
||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
DMARQ0 to DMARQ2 |
Input |
Connect to GND via resistor |
|||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
I/O |
Individually connect to VDD via resistor |
||||||||||||||||||
|
END/TC |
|||||||||||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Notes 1. V50HL only
2. V40HL only
Data Sheet U13225EJ4V0DS00 |
17 |
μPD70208H, 70216H
Remark The circuit configuration of the latch is as illustrated below. To invert the level of the pin with a latch, a drive
current higher than the latch invert current is necessary.
(1) Output pin
|
Output buffer |
Latch |
|
|
|
|
|
Output pin |
|
|
address bus, |
Hi-Z |
|
control bus |
control |
|
|
(2) I/O pin
Output buffer |
Latch |
|
|
|
I/O pin |
|
(data bus) |
Hi-Z |
|
control |
|
Input buffer |
|
18 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
2. MEMORY AND I/O CONFIGURATION
2.1MEMORY SPACE
The V40HL and V50HL can access a 1M-byte (512K-word) memory space.
Figure 2-1. Memory Map
FFFFFH
Reserved
FFFFCH
FFFFBH
Dedicated
FFFF0H
FFFEFH
General Use
00400H
003FFH
Interrupt Vector Table
00000H
Figure 2-2. Interface with Memory (1/2)
(a) V40HL
A0-A19 |
Address Bus (20) |
Memory
1M Byte
8
D0-D7 |
Data Bus (8) |
Data Sheet U13225EJ4V0DS00 |
19 |
μPD70208H, 70216H
A1-A19
A0
UBE
D0-D15
Figure 2-2. Interface with Memory (2/2)
(b) |
V50HL |
Address Bus (19) |
|
19 |
19 |
BSEL |
BSEL |
Memory |
Memory |
Upper Bank |
Lower Bank |
512K Byte |
512K Byte |
8 D8-D15 |
8 D0-D7 |
Data Bus (16)
20 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
2.2 I/O SPACE
In the V40HL and V50HL, I/Os up to 64K bytes (32K words) can be accessed in an area independent of the memory. The various on-chip peripheral LSIs are set by accessing the system I/O area.
Extended functions added to those of the V40 and V50 are mapped onto unused V40 and V50 registers and the reserved area.
The I/O map is shown in Figure 2-3.
Figure 2-3. I/O Map
FFFFH
System I/O Area
FFE0H
FFDFH
Reserved Area
FF00H
FEFFH
DMAU
ICU
256 Bytes
TCU
SCU
Area used for setting of I/O boundary, WCU, REFU, baud rate generator, etc., and DMAU, ICU, TCU and SCU allocation.
The DMAU, ICU, TCU and SCU are allocated within any 256 bytes.
Internal I/O Area
External I/O Area
0000H
Data Sheet U13225EJ4V0DS00 |
21 |
μPD70208H, 70216H
3. CPU
The CPU has the same functions as the V20HLTM and V30HLTM. In hardware terms, there are some changes regarding the use of the bus with on-chip peripherals, but in software terms the CPU is fully compatible.
The internal block diagram of the CPU is shown in Figure 3-1.
Figure 3-1. Internal Block Diagram of CPU (1/2)
(a) V40HL
Internal Address/Data Bus (20)
To BIU
ADM
PS
SS
DS0
DS1
PFP
DP
TEMP
Q0 Q1
Q2 Q3
LC
PC
AW
BW
CW
DW
IX
IY
BP
SP
TC
TA SHIFTER
TB
ALU
PSW
Sub Data Bus
(16)
T-STATE
CONTROL
CYCLE |
INTERRUPT |
|
NMI |
|
|||
DECISION |
CONTROL |
|
INT |
|
|||
|
|
|
|
|
|
|
(From ICU) |
QUEUE |
STANDBY |
|
CLOCK |
|
|||
CONTROL |
CONTROL |
|
(From CG) |
|
|
BCU |
|
|
|
EXU |
|
EFFECTIVE ADDRESS
GENERATOR
(8)Bus |
ADDRESSμ REGISTER |
μINSTRUCTION |
|
|
|
|
|
29 Micro Data Bus |
|
|
ROM |
Data |
|
μSEQUENCE |
Queue |
|
|
|
CONTROL |
|
|
|
INSTRUCTION DECODER
Main Data Bus
(16)
22 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
Figure 3-1. Internal Block Diagram of CPU (2/2)
(b) V50HL
Internal Address/Data Bus (20)
To BIU
ADM
|
PS |
|
SS |
|
DS0 |
|
DS1 |
|
PFP |
|
DP |
|
TEMP |
Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
LC
PC
AW
BW
CW
DW
IX
IY
BP
SP
TC
TA
SHIFTER
TB
ALU
PSW
Sub Data Bus
(16)
T-STATE
CONTROL
CYCLE |
INTERRUPT |
|
NMI |
|
|||
DECISION |
CONTROL |
|
INT |
|
|||
|
|
|
|
|
|
|
(From ICU) |
QUEUE |
STANDBY |
|
CLOCK |
|
|||
CONTROL |
CONTROL |
|
(From CG) |
|
|
BCU |
|
|
|
EXU |
|
EFFECTIVE ADDRESS
GENERATOR
(8)Bus |
ADDRESSμ REGISTER |
μINSTRUCTION |
|
|
|
|
|
29 Micro Data Bus |
|
|
ROM |
Data |
|
μSEQUENCE |
Queue |
|
|
|
CONTROL |
|
|
|
INSTRUCTION DECODER
Main Data Bus
(16)
Data Sheet U13225EJ4V0DS00 |
23 |
μPD70208H, 70216H
4. CG (CLOCK GENERATOR)
The CG generates a clock at a frequency of 1/2, 1/4, 1/8 or 1/16 that of the crystal and oscillator connected to the X1 and X2 pins, supplies it as the CPU operating clock and outputs it externally as the CLKOUT pin output.
The interrupt cycle time can be changed according to the oscillator scaling factor. The scaling factor can be set by a system I/O area register.
Figure 4-1. Internal Block Diagram of CG
X1 |
fXX |
Divide-by-2 |
Divide-by-1-to-8 |
fX |
|
||||
|
Oscillator |
Scaler |
Scaler |
|
X2 |
|
|
||
|
|
|
|
|
|
|
|
Divide-by-2-to-16 |
|
|
|
|
Scaler |
|
CPU, DMAU, REFU, SCU
CLKOUT
Baud Rate Counter (BRC)
TCU
5. BIU (BUS INTERFACE UNIT)
The BIU controls the data bus, address bus and control bus pins. These buses are used by the CPU, DMAU (DMA control unit) and REFU (refresh control unit).
The BIU synchronizes the RESET input signal and READY input signal using the CLOCK signal generated by the clock generator (CG). In addition to being supplied to the inside of the V40HL and V50HL, the synchronized reset signal is also output externally from the RESOUT pin. The synchronized READY signal is supplied to the internal CPU, DMAU and REFU.
Figure 5-1. RESET and READY Signal Synchronization
|
|
|
CLOCK |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CK ↓ |
|
|
|
|
|
|
|
|
RESET |
|
|
|
|
|
|
|
|
|
|
|
||||||
|
|
|
|
|
D |
|
Q |
|
|
|
|
RESOUT |
|||||
|
|
|
|
|
|
|
|
|
|||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
To Internal Units |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
CK − |
|
|
CK ↓ |
|
|
|
|
|
||||
READY |
|
|
D |
|
Q |
|
D |
|
Q |
|
|
|
To Internal Units |
||||
|
|
|
|
|
|
|
|||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
24 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
6. BAU (BUS ARBITRATION UNIT)
The BAU performs bus arbitration among bus masters.
A list of bus masters (units which can acquire the bus) is shown below.
Table 6-1. Bus Masters
Bus Master |
Bus Cycle |
|
|
CPU |
Program fetch, data read/write |
|
|
DMAU |
DMA cycle |
|
|
REFU |
Refresh cycle |
|
|
External bus master |
Bus cycle driven by external device |
(HLDRQ pin input) |
|
|
|
The relative priorities of the bus masters are shown below.
High |
CPU (when BUSLOCK prefix is used) |
|
|
|
REFU (highest priority: when given number of requests are reached) |
|
|
|
|
|
DMAU |
|
|
HLDRQ pin |
|
|
CPU (normal CPU cycle) |
|
|
|
Low |
REFU (lowest priority: cycle steal) |
|
BAU bus arbitration is performed as follows.
A bus master such as the CPU, DMAU, REFU, etc., incorporated in the V40HL and V50HL normally release the bus at the end of the bus cycle currently being executed, as shown in Figure 6-1. However, in the case of a bus master connected to the HLDRQ pin, or cascaded external DMA controllers, for instance, the situation is as shown in Figure 6-2. The V40HL and V50HL request return of the bus by inactivating the acknowledge signal (HLDAK), and on receiving this request, the external bus master holding the bus should release the bus by dropping the bus hold request signal (HLDRQ). The V40HL and V50HL-internal bus master with the highest priority is kept waiting until the bus hold request signal is dropped. This is called a bus wait operation.
Data Sheet U13225EJ4V0DS00 |
25 |
μPD70208H, 70216H
Figure 6-1. Internal Bus Cycles
Bus Cycle |
|
CPU |
CPU |
DMA |
Refresh |
Refresh |
Refresh |
|
|
|
|
|
|
|
|
|
|
Internal DMA Request
Internal Refresh Request
(Highest Priority)
Figure 6-2. Bus Wait Operation
Bus Cycle
HLDRQ Pin
HLDAK Pin
|
Bus Wait |
Bus Release Note |
Refresh |
Internal Refresh Request
(Highest Priority)
Note The period in which the external bus master which has been given the bus after its release by the V40HL and
V50HL can use the bus.
26 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
7. WCU (WAIT CONTROL UNIT)
The WCU has the function of automatically inserting a wait state (TW) of 0 to 3 clock cycles in a CPU, DMAU or REFU
bus cycle.
7.1FEATURES
•Automatic setting of 0 to 3 waits for a CPU memory bus cycle
•1M-byte memory space can be divided into 5
•64K-byte I/O space can be divided into 3
•Automatic setting of 0 to 3 waits for an external I/O cycle
•Automatic setting of 0 to 3 waits for a DMA cycle
•Automatic setting of 0 to 3 waits for a refresh cycle
•Same as V40 and V50 directly after a reset (memory space divided into 3, no division of I/O space)
Figure 7-1. Example of Memory Space Division
|
|
|
|
|
|
Upper Sub |
|
|
|
FFFFFH |
|
|
Memory Block |
|
|
|
|
Upper Memory Block |
|
|
|
|
|
|
|
|
|
1 M- |
Byte |
Middle Memory Block |
|
|
||
Memory Area |
|
|
||||
|
|
|
|
Lower Memory Block |
|
|
|
|
|
00000H |
|
|
Lower Sub |
|
|
|
|
|
Memory Block |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
Remark The division specification and the size of each block are set by means of a system I/O area register.
Data Sheet U13225EJ4V0DS00 |
27 |
μPD70208H, 70216H
Figure 7-2. Example of I/O Space Division
FFFFH
Upper I/O Block
64K- |
Byte I/O Area |
Middle I/O Block |
Lower I/O Block
0000H
Remark The division specification and the size of each block are set by means of a system I/O area register.
7.2RELATION BETWEEN WCU AND READY PIN
When wait cycles exceeding 3 clock cycles are necessary, the WCU and the READY signal pin can be used in combination. The number of wait cycles specified by the WCU set value or the number of wait cycles under READY control, whichever is larger, is inserted.
Figure 7-3. WCU and READY Control
V40HL/V50HL
WCU
Bus Control
READY 
28 |
Data Sheet U13225EJ4V0DS00 |
μPD70208H, 70216H
8. REFU (REFRESH CONTROL UNIT)
The REFU generates refresh cycles required for refreshing of external DRAM. Refresh enabling/disabling and the refresh interval can be set programmably.
8.1FEATURES
•Lowest-priority refreshing/highest-priority refreshing
•7-refresh queue
•16-bit refresh address
•REFRQ extended timing supported (REFRQ active from T1 state)
8.2REFRESH OPERATIONS
The REFU has two priorities. Normally, it has the lowest priority, and a refresh cycle cannot be started unless the bus is completely idle. However, if there are 7 or more pending refresh requests, it is given the highest priority, and it requests the bus master holding the bus to relinquish it. (See 6. BAU.)
The refresh address is output on A0 to A15. Every refresh cycle the refresh address is incremented by 1 (for the V40HL) or by 2 (for the V50HL), and the next refresh address is generated.
In a refresh cycle, a low-level signal is output on the low address pins (A16 to A19).
This refresh address is not affected by a reset. When the device is powered on, the refresh address is undefined.
Data Sheet U13225EJ4V0DS00 |
29 |
μPD70208H, 70216H
9. TCU (TIMER/COUNTER UNIT)
The TCU incorporates 3 counters, and can be used as a timer, event counter, rate generator, etc. Functionally it is a subset of the μPD71054.
9.1FEATURES
•3 × 16-bit counters
•Six programmable count modes
•Binary/BCD count
•Multiple latch command
•Choice of two input clocks: internal/external
9.2TCU INTERNAL BLOCK DIAGRAM
|
|
|
|
TCU |
TCLK |
CLOCK |
|
|
|
|
TCTL1=High |
||||||||||
|
|
|
|
(External) |
TCTL0=High |
TOUT1 |
(External) TCTL2 (External) |
||||||||||||||
|
|
|
|
|
|
|
|
||||||||||||||
|
|
|
Note 2 Selection |
|
|
|
|
||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
TOUT2 (External) |
||||||
|
|
|
|
|
|
|
|
TOUT0 (To INTL0) |
|
|
|
|
|
|
|
||||||
IORD IOWR Note 1 |
Signal |
|
Prescaler |
|
|
To INTL2/SCU |
|||||||||||||||
|
|
|
|
|
|
|
|||||||||||||||
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
SW |
|
|
|
SW |
|
|
|
|
|
SW |
|
|||
|
TCT #0 |
|
|
|
|
Read/Write Control |
|
|
|
|
|
|
|
Control Logic |
|
|
|
|
Status |
Down Counter (16) |
TCT #1 |
TCT #2 |
|
|
Register |
||||
|
|
|
|
|
|
TMD |
(8) |
(16) |
(16) |
|
|
|
|
|
|
|
|
(Mode |
Status |
H(8) L(8) |
H(8) L(8) |
|
|
Register) |
Count |
Count |
|
|
|
Latch |
|
|
|||
Register |
Latch |
|
|
||
|
(8) |
(8) |
(8) |
|
|
Internal Data Bus
Notes 1. A0 or A1 (Set by a system I/O area register)
2. A1 or A2 (Set by a system I/O area register)
30 |
Data Sheet U13225EJ4V0DS00 |
Loading...