NEC UPD75117HGK-XXX-8A8, UPD75117HGC-XXX-AB8, UPD75116HGK-XXX-8A8, UPD75116HGC-XXX-AB8 Datasheet

DESCRIPTION

The µPD75117H is a 75X Series 4-bit single-chip microcomputer. The

µ

PD75117H is a product which has the same functions as those of the µPD751××F, with the minimum operating voltage reduced from the previous 2.7 V to 1.8 V, and achieving 1.91 µs operation at 1.8 V. Therefore, it facilitates low-voltage operation for a set requiring high-speed operation.

Functions are described in detail in the following User’s Manual, which should be read when carrying out

design work.

µ

PD75117H User’s Manual : IEU-799

FEATURES

• Memory capacity

ROM : 24448 × 8 bits (

µ

PD75117H)

: 16256 × 8 bits (

µ

PD75116H)

RAM : 768 × 4 bits

• High-speed low voltage operation

Minimum instruction execution time : 1.91

µ

s (VDD = 1.8 V)

0.95

µ

s (VDD = 2.7 V)

• Operating voltage range : 1.8 to 5.5 V (Ta = –40 to +60 °C)

• Input/output ports : 58

• Timer/counter : 3 channels

• Timer/event counter × 2 channels

• Basic interval timer × 1 channel

• 8-bit serial interface on chip

• Programmable threshold port : 4-bit resolution × 4 channels

• On-chip PROM product available :

µ

PD75P117H (One-time PROM)

APPLICATIONS

Cordless telephone subsets, portable radio equipment, pager, etc.

4-BIT SINGLE-CHIP MICROCOMPUTER

MOS INTEGRATED CIRCUIT

µ

PD75116H,75117H

DATA SHEET

Document No. IC-3120 (O.D.No. IC-8502) Date Published May 1994P Printed in Japan

The mark ★ shows major revised points.

"Unless there are any particular functional differences, the µPD75117H is described in this document as a representative product."

The information in this document is subject to change without notice.

★

2

µ

PD75116H,75117H

ORDERING INFORMATION

Ordering Code Package Quality Grade

µ

PD75116HGC-×××-AB8 64-pin plastic QFP ( 14 mm) Standard

µ

PD75116HGK-×××-8A8 64-pin plastic QFP ( 12 mm) Standard

µ

PD75117HGC-×××-AB8 64-pin plastic QFP ( 14 mm) Standard

µ

PD75117HGK-×××-8A8 64-pin plastic QFP ( 12 mm) Standard

Remarks ×××: ROM code number

OVERVIEW OF FUNCTIONS

Contents

43

0.95 µs, 1.91 µs, 15.3 µs (4.19 MHz operation) 3-stage switching capability

24448 × 8 bits (µPD75117H), 16256 × 8 bits (µPD75116H) 768 × 4 bits 4 bits × 8 × 4 banks (memory mapping)

Total 58

• CMOS input pins : 10

• CMOS input/output pins : 32 (pins with LED direct drive

capability*1)

• N-ch open-drain input/output pins : 12 (pins with LED direct drive

capability*2)

(A pull-up resistor can be incorporated bit-wise.)

• Comparator input pins (4-bit precision) : 4

• 8-bit timer/event counter × 2

• 8-bit basic interval timer (watchdog timer applicable)

• 8 bits

• LSB-first/MSB-first switchable

• 2 transfer modes (transmission/reception and dedicated reception modes)

• External : 3

• Internal : 4

• External : 2

• STOP/HALT mode

• Various bit manipulation instructions (set, reset, test, Boolean operation)

• 8-bit data transfer, comparison, operation, increment/decrement instructions

• 1-byte relative branch instruction

• GETI instruction that can implement arbitrary 2-byte/3-byte instructions with 1 byte

• Bit manipulation memory (bit sequential buffer: 16 bits) on chip

• 64-pin plastic QFP ( 14 mm)

• 64-pin plastic QFP ( 12 mm)

Item

Basic instructions

Instruction cycle

On-chip memory

General register

Input/output port

Timer/counter

Serial interface

Vectored interrupt

Test input

Standby

Instruction set

Others

Package

ROM

RAM

*1. When VDD = 5 V, IOL = 15 mA.

2. When V

DD = 5 V, IOL = 10 mA.

★

★ ★

3

µ

PD75116H,75117H

DIFFERENCES BETWEEN µPD75116H AND µPD75117H

µ

PD75116H

µ

PD75117H

16256 × 8 bits 24448 × 8 bits

(Mask ROM) (Mask ROM)

768 × 4 bits

No Yes

Memory bank 0 Memory banks 0, 1, 2

2-byte stack 3-byte stack

3 machine cycles 4 machine cycles

2 machine cycles 3 machine cycles

Undefined operation Normal operation

SBS register

Stack area

Item

ROM

RAM

Stack

Stack operation when subroutine call instruction is executed

CALL instruction machine cycle

CALLF instruction machine cycle

BRA instruction CALLA instruction MOVT XA, BCDE MOVT XA, BCXA BR BCDE BR BCXA

★

4

µ

PD75116H,75117H

CONTENTS

1. PIN CONFIGURATION (TOP VIEW) ...................................................................................................... 6

2. BLOCK DIAGRAM ................................................................................................................................... 8

3. PIN FUNCTIONS ..................................................................................................................................... 9

3.1 PORT PINS ....................................................................................................................................................... 9

3.2 OTHER PINS ..................................................................................................................................................... 10

3.3 PIN INPUT/OUTPUT CIRCUITS ..................................................................................................................... 11

3.4 RECOMMENDED CONNECTION OF UNUSED PINS ................................................................................... 12

4. MEMORY CONFIGURATION ................................................................................................................. 13

5. PERIPHERAL HARDWARE FUNCTIONS ............................................................................................... 18

5.1 PORT ................................................................................................................................................................. 18

5.2 CLOCK GENERATOR ....................................................................................................................................... 19

5.3 CLOCK OUTPUT CIRCUIT ............................................................................................................................... 20

5.4 BASIC INTERVAL TIMER ................................................................................................................................ 21

5.5 TIMER/EVENT COUNTER ............................................................................................................................... 21

5.6 SERIAL INTERFACE ......................................................................................................................................... 23

5.7 PROGRAMMABLE THRESHOLD PORT (ANALOG INPUT PORT) .............................................................. 25

5.8 BIT SEQUENTIAL BUFFER ............................................................................................................................. 26

6. INTERRUPT FUNCTION ........................................................................................................................ 27

7. STANDBY FUNCTION ............................................................................................................................ 29

8. RESET FUNCTION .................................................................................................................................. 30

9. INSTRUCTION SET ................................................................................................................................. 33

10. APPLICATION EXAMPLE ....................................................................................................................... 43

10.1 CORDLESS TELEPHONE (SUBSET) .............................................................................................................. 43

10.2 DISPLAY PAGER .............................................................................................................................................. 44

11. MASK OPTION SELECTION................................................................................................................... 45

12. ELECTRICAL SPECIFICATIONS ............................................................................................................. 46

13. PACKAGE INFORMATION ..................................................................................................................... 57

14. RECOMMENDED SOLDERING CONDITIONS ...................................................................................... 59

APPENDIX A. FUNCTIONAL DIFFERENCES AMONG µPD751×× SERIES PRODUCTS ......................... 60

5

µ

PD75116H,75117H

APPENDIX B. DEVELOPMENT TOOLS ........................................................................................................ 62

APPENDIX C. RELATED DOCUMENTS........................................................................................................ 63

6

µ

PD75116H,75117H

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

P41

P42

P43

P30

P31

P32

P33

V

DD

IC*

P140

P141

P142

P143

P130

P131

P132

P90

V

SS

P83

P82

P81

P80

P93

P92

P91

P13/INT3

P12/INT2

P11/INT1

P10/INT0

PTH03

PTH02

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P70

P71

P72

P73

P60

P61

P62

P63X1X2

RESET

P50

P51

P52

P53

P40

PTH00

TI0

TI1

P23

P22/PCL

P21/PTO1

P20/PTO0

P03/SI

P02/SO

P01/SCK

P00/INT4

P123

P122

P121

P120

P133

PTH01

1. PIN CONFIGURATION (TOP VIEW)

* Connect the IC (Internally Connected ) pin to VDD directly.

µ

PD75116HGC-×××-AB8

µ

PD75116HGK-×××-8A8

µ

PD75117HGC-×××-AB8

µ

PD75117HGK-×××-8A8

7

µ

PD75116H,75117H

Pin Name

P00-P03 : Port 0 PCL : Programmable Clock Output P10-P13 : Port 1 SCK : Serial Clock P20-P23 : Port 2 SO : Serial Data Output P30-P33 : Port 3 SI : Serial Data Input P40-P43 : Port 4 PTH00-PTH03 : Programmable Treshold Input P50-P53 : Port 5 INT0, INT1, INT4 : External Vectored Interrupt Input 0, 1, 4 P60-P63 : Port 6 INT2, INT3 : External Test Input 2, 3 P70-P73 : Port 7 X1, X2 : System Clock Oscillation 1, 2 P80-P83 : Port 8 RESET : Reset P90-P93 : Port 9 V

DD : Positive Power Supply

P120-P123 : Port 12 V

SS : Ground

P130-P133 : Port 13 IC : Internally Connected P140-P143 : Port 14 TI0, TI1 : Timer Input 0, 1 PTO0, PTO1 : Programmable Timer

Output 0, 1

8

µ

PD75116H,75117H

2. BLOCK DIAGRAM

*1. The µPD75116H program counter is composed of 14 bits.

2. The

µ

PD75117H incorporates the SBS register.

PORT 0

PORT 1

44P00-P03

P10-P13

PORT 3

PORT 4

PORT 5

PORT 6

4

PORT 2

4 P20-P23

P30-P33

P40-P43

P50-P53

P60-P63

PORT 7 4

P70-P73

SP(8)

BANK

GENERAL REG.

 RAM DATA

MEMORY

768 × 4 BITS

DECODE

AND

CONTROL

CY

ALU

PROGRAM

COUNTER (15) *1

ROM

PROGRAM

MEMORY

16256 × 8 BITS

: PD75116H

24448 × 8 BITS

: PD75117H

RESET

V

SS

STAND BY CONTROL

V

DD

CPU CLOCK 

CLOCK

GENERATOR

CLOCK

DIVIDER

CLOCK

OUTPUT

CONTROL

X2X1PCL/P22

f

X

/ 2

N

BASIC

INTERVAL

TIMER

INTER-

RUPT 

CONTROL

INTT1

INTBT

PORT 14 4

P140-P143

PORT 12 4

P120-P123

TIMER/EVENT

COUNTER 

#0

INTT0

TI0

PTO0/P20

TIMER/EVENT

COUNTER 

#1

TI1

PTO1/P21



SERIAL

INTERFACE

INTSIO

SCK/P01

SO/P02

SI/P03

PROGRAM-

MABLE

THRESHOLD

PORT #0

PTH00-PTH03

INT4/P00

INT2/P12

INT1/P11

INT0/P10

INT3/P13

PORT 13 4

P130-P133

PORT 9 4

P90-P93

PORT 8 4

P80-P83

BIT SEQ. BUFFER (16)

SBS(2) *2

4

Φ

µ µ

9

µ

PD75116H,75117H

3. PIN FUNCTIONS

3.1 PORT PINS

Dual-

Function Pin

INT4

SCK

SO

SI

INT0

INT1

INT2

INT3

PTO0

PTO1

PCL

—

I/O Circuit

Type *1

B

F

E

B

E

M

*1. : Schmitt trigger input

2. Direct LED drive capability (When V

DD = 5 V, IOL = 15 mA).

3. Direct LED drive capability (When VDD = 5 V, IOL = 10 mA).

4. Open-drain … high impedance

On-chip pull-up resistor … high level

*3

*2

*3

★ ★

Pin Name

P00

P01

P02

P03

P10

P11

P12

P13

P20

P21

P22

P23

P30 to P33

P40 to P43

P50 to P53

P60 to P63

P70 to P73

P80 to P83

P90 to P93

P120 to P123

P130 to P133

P140 to P143

Input/Output

Input

Input/output

Input

Input/output

Function

4-bit input port (PORT 0).

4-bit input port (PORT 1).

4-bit input/output port (PORT 2).

Programmable 4-bit input/output port (PORT 3). Input/output can be specified bit-wise.

4-bit input/output port (PORT 4).

4-bit input/output port (PORT 5).

Programmable 4-bit input/output port (PORT 6). Input/output can be specified bit-wise.

4-bit input/output port (PORT 7).

4-bit input/output port (PORT 8).

4-bit input/output port (PORT 9).

N-ch open-drain 4-bit input/output port (PORT

12). On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: +6 V withstand voltage

N-ch open-drain 4-bit input/output port (PORT

13). On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: +6 V withstand voltage

N-ch open-drain 4-bit input/output port (PORT

14). On-chip pull-up resistor can be specified bitwise (mask option). Open-drain: +6 V withstand voltage

8-bit I/O

×

—

Reset

Input

Input *4

10

µ

PD75116H,75117H

3.2 OTHER PINS

Dual-

Function Pin

—

P20

P21

P01

P02

P03

P00

P10

P11

P12

P13

P22

—

I/O Circuit

Type *1

N

B

E

F

E

B

E

B

* : Schmitt trigger input

Pin Name

PTH00 to PTH03

TI0

TI1

PTO0

PTO1

SCK

SO

SI

INT4

INT0

INT1

INT2

INT3

PCL

X1, X2

RESET

IC

V

DD

VSS

Input/Output

Input

Input/output

Input

Input/output

Input

—

Function

Variable threshold voltage 4-bit analog input port.

External event pulse input to timer/event counter. Or edge detection vectored interrupt input, or 1-bit input is also possible.

Timer/event counter output.

Serial clock input/output.

Serial data output.

Serial data input.

Edge detection vector interrupt input (detection of both rising and falling edges)

Edge detection vector interrupt input (detection edge selectable)

Edge detection test input (rising edge detection)

Clock output

System clock oscillation crystal/ceramic connection pin. When an external clock is used, the clock is input to X1 and the inverted clock is input to X2.

System reset input (low-level active).

Internally Connected. IC pin should be connected to V

DD

directly.

Positive power supply.

GND potential.

Reset

Input

11

µ

PD75116H,75117H

3.3 PIN INPUT/OUTPUT CIRCUITS

The input/output circuits of each pin of the

µ

PD75117H are shown by in abbreviated form.

Fig. 3-1 Pin Input/Output Circuit List

Type A

Type F

Type B

Type D

Type E

Type M

Type N

IN/OUT

data

output disable

Type D

P-ch

V

DD

IN

N-ch

IN

Pull-Up Resistor

V

DD

IN/OUT

N-ch (+6 V  Withstand  Voltage)

data

output disable

(Mask Option)

Middle-High Voltage Input Buffer

(+6 V Withstand Voltage)

IN/OUT

data

output disable

Type D

Type A

P-ch

V

DD

OUT

N-ch

data

output disable

+

–

V

REF

(Threshold Voltage)

CMOS standard input buffer

This is an input/output circuit made up of a Type D  push-pull output and Type B Schmitt-triggered input.

Schmitt-trigger input with hysteresis characteristic

Push-pull output that can be made high- impedance output (P-ch and N-ch OFF)

This is an input/output circuit made up of a Type D push-pull output and Type A input buffer.

Comparator

Type B

12

µ

PD75116H,75117H

3.4 RECOMMENDED CONNECTION OF UNUSED PINS

PTH00 to PTH03

TI0

TI1

P00

P01 to P03

P10 to P13

P20 to P23

P30 to P33

P40 to P43

P50 to P53

P60 to P63

P70 to P73

P80 to P83

P90 to P93

P120 to P123

P130 to P133

P140 to P143

IC

Recommended Connection

Connect to VSS or VDD.

Connect to VSS.

Connect to VSS or VDD.

Connect to VSS.

Input status : Connect to VSS or VDD.

Output status : Leave open.

Connect to VDD directly.

13

µ

PD75116H,75117H

4. MEMORY CONFIGURATION

• Program memory (ROM) : 24448 × 8 bits (0000H to 5F7FH) :µPD75117H 16256 × 8 bits (0000H to 3F7FH) :µPD75116H

• 0000H, 0001H : Vector table in which a program start address after reset is written.

• 0002H to 000BH : Vector table in which program start addresses after interruption are written.

• 0020H to 007FH : Table area referred by GETI instruction

• Data memory

• Data area : 768 × 4 bits (000H to 2FFH)

• Peripheral hardware area : 128 × 4 bits (F80H to FFFH)

14

µ

PD75116H,75117H

Note Since the above interrupt vector start address is a 14-bit address, set it in a 16K space (0000H to

3FFFH).

Remarks Apart from the above instructions, branching is possible to an address at which only the PC low-

order 8 bits have been changed by the BR PCDE or BR PCXA instruction.

Fig. 4-1 Program Memory Map (1/2)

(a)

µ

PD75117H

≈ ≈

≈

≈ ≈

MBE0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH 0080H

07FFH 0800H

0FFFH 1000H

7 6 0

Address

Internal Reset Start Address (High-Order 6 Bits)

Internal Reset Start Address (Low-Order 8 Bits)

INTBT/INT4 Start Address (High-Order 6 Bits)

INT0/INT1 Start Address (High-Order 6 Bits)

INTBT/INT4 Start Address (Low-Order 8 Bits)

INT0/INT1 Start Address (Low-Order 8 Bits)

INTSIO Start Address (High-Order 6 Bits)

INTSIO Start Address (Low-Order 8 Bits)

INTT0 Start Address (High-Order 6 Bits)

INTT0 Start Address (Low-Order 8 Bits)

INTT1 Start Address (High-Order 6 Bits)

INTT1 Start Address (Low-Order 8 Bits)

GETI Instruction Reference Table

CALLF ! faddr Instruction Entry Address

BRCB ! caddr Instruction Branch  Address

BR !addr Instruction Branch Address

≈

RBE

MBE RBE

1FFFH 2000H

2FFFH 3000H

3FFFH 4000H

4FFFH 5000H

5F7FH

≈

CALL !addr Instruction Branch Address

Branch/Call  Address by GETI

BR BCDE BR BCXA Branch Address

BRA !addr1 Instruction Branch Address

CALLA !addr1 Instruction Branch Address

BR $addr1 Instruction  Relative Branch  Address (-15 to -1, +2 to +16)

BRCB !caddr Instruction Branch Address

15

µ

PD75116H,75117H

Fig. 4-1 Program Memory Map (2/2)

(b)

µ

PD75116H

MBE0000H

0002H

0004H

0006H

0008H

000AH

0020H

007FH 0080H

07FFH 0800H

0FFFH 1000H

76 0

Address

Internal Reset Start Address (High-Order 6 Bits)

Internal Reset Start Address (Low-Order 8 Bits)

INTBT/INT4 Start Address (High-Order 6 Bits)

INT0/INT1 Start Address (High-Order 6 Bits)

INTBT/INT4 Start Address (Low-Order 8 Bits)

INT0/INT1 Start Address (Low-Order 8 Bits)

INTSIO Start Address (High-Order 6 Bits)

INTSIO Start Address (Low-Order 8 Bits)

INTT0 Start Address (High-Order 6 Bits)

INTT0 Start Address (Low-Order 8 Bits)

INTT1 Start Address (High-Order 6 Bits)

INTT1 Start Address (Low-Order 8 Bits)

GETI Instruction Reference Table

CALLF ! faddr Instruction Entry Address

BRCB ! caddr Instruction Branch  Address

BR ! addr Instruction Branch Address

RBE

MBE RBE

1FFFH 2000H

2FFFH 3000H

3F7FH

CALL ! addr Instruction Subroutine  Entry Address

BR $ addr Instruction Relative Branch Address –15 to –1, +2 to +16

Branch Destination Address and Subroutine Entry Address by GETI  Instruction

BRCB !caddr Instruction Branch Address

Remarks Apart from the above instructions, branching is possible to an address at which only the PC low-

order 8 bits have been changed by the BR PCDE or BR PCXA instruction.

16

µ

PD75116H,75117H

Fig. 4-2 Data Memory Map (1/2)

(a)

µ

PD75117H

256 × 4

256 × 4



256 × 4



128 × 4

(32 × 4)

Bank 0

Bank 1

Bank 15

000H

01FH 020H

0FFH 100H

1FFH 200H

2FFH

F80H

FFFH

General Register Area

Stack Area

Data Area Static RAM (768 × 4)

Peripheral Hardware Area

Data Memory Memory Bank

Not On-Chip

Bank 2

17

µ

PD75116H,75117H

Fig. 4-2 Data Memory Map (2/2)

(b)

µ

PD75116H

256 × 4

256 × 4



256 × 4



128 × 4

(32 × 4)

Bank 0

Bank 1

Bank 15

000H

01FH 020H

0FFH 100H

1FFH 200H

2FFH

F80H

FFFH

General Register Area

Stack Area

Data Area Static RAM (768 × 4)

Peripheral Hardware Area

Data Memory Memory Bank

Not On-Chip

Bank 2

18

µ

PD75116H,75117H

5. PERIPHERAL HARDWARE FUNCTIONS

5.1 PORT

There are the following three digital input/output ports.

• CMOS input (PORT0, PORT1) : 8

• CMOS input/output (PORT2 to PORT9) : 32

• N-ch open-drain input/output (PORT12 to PORT14) : 12

Total : 52

Table 5-1 Port Function

Port Name Function Operation/Features Remarks

4-bit input

4-bit input/output

4-bit input/output (N-ch open-drain +6 V withstand voltage)

Regardless of the operating mode of the shared pin, reading or test is always possible.

Can be set in the input or output bit-wise.

Can be set in the input or output mode as a 4bit unit. Ports 4 and 5, 6 and 7, and 8 and 9 are paired and data input/output is possible as an 8-bit unit.

Can be set to input or output mode as a 4-bit unit. Ports 12 and 13 are paired and data input/ output is possible as an 8-bit unit.

These pins are shared with SI, SO, SCK, INT0 to INT4.

Port 2, PTO0, PTO1, and PCL share the same pins.

On-chip pull-up resistor specifiable bit-wise by mask option.

PORT 0

PORT 1

PORT 3 *1

PORT 6 *1

PORT 2 *1

PORT 4 *1

PORT 5 *1

PORT 7 *1

PORT 8 *1

PORT 9 *1

PORT12 *2

PORT13 *2

PORT14 *2

*1. When VDD = 5 V, IOL = 15 mA.

2. When VDD = 5 V, IOL = 10 mA.

★ ★

19

µ

PD75116H,75117H

5.2 CLOCK GENERATOR

The clock generator operation is determined by the processor clock control register (PCC). This circuit can also change the instruction execution time.

• 0.95

µ

s/1.91 µs/15.3 µs (4.19 MHz operation)

Fig. 5-1 Clock Generator Block Diagram

* Instruction execution

Remarks 1. fXX = Crystal/ceramic oscillator frequency

2. fX = External clock frequency

3.Φ = CPU Clock

4. PCC : Processor clock control register

5. One Φ clock cycle (tCY) is one machine cycle. See "AC CHARACTERISTICS" in 12. "ELECTRICAL SPECIFICATIONS" for tCY.

★

X1

f

XX

or f

X

• Basic Interval Timer (BT)

• Clock Output Circuit

• Timer/Event Counter

• Serial Interface 

Frequency Divider

1/2

Selector

HALT F/F

Wait Release Signal from BT

RESET Signal (Internal Reset)

Standby Release Signal from Interrupt Control Circuit

STOP F/F

S

R

Q

PCC2, PCC3 Clear

Oscillation Stop

PCC

4

Internal Bus

System Clock  Oscillation  Circuit

S

R

Q

HALT *

STOP *

Frequency Divider

1/4

• CPU

• Clock Output Circuit

Φ

1/16

X2



1/8 to 1/4096

PCC0

PCC1

PCC2

PCC3

20

µ

PD75116H,75117H

5.3 CLOCK OUTPUT CIRCUIT

The clock output circuit is a circuit which outputs a clock pulse from P22/PCL and is used to supply clock pulses

to remote control outputs or peripheral LSI’s.

• Clock output (PCL) :

Φ

, 524 kHz, 262 kHz (4.19 MHz operation)

Fig. 5-2 Configuration of Clock Output Circuit

CLOM3

CLOM1

CLOM0

4

Internal Bus

CLOM

P22 Output Latch

PORT2.2 Bit 2 of PMGB

Bit Specified in Port 2 Input/Output Mode

Output Buffer

PCL/P22

f

XX

/2

3

fXX/2

4

Selector

Φ

From Clock Generator

CLOM2