National Semiconductor 54173, DM54173, DM74173 Technical data

54173

June 1989

54173/DM54173/DM74173 TRI-STATEÉ Quad D Registers

General Description

These four-bit registers contain D-type flip-flops with totempole TRI-STATE outputs, capable of driving highly capacitive or low-impedance loads. The high-impedance state and increased high-logic-level drive provide these flip-flops with the capability of driving the bus lines in a bus-organized system without need for interface or pull-up components.

Gated enable inputs are provided for controlling the entry of data into the flip-flops. When both data-enable inputs are low, data at the D inputs are loaded into their respective flipflops on the next positive transition of the buffered clock input. Gate output control inputs are also provided. When both are low, the normal logic states of the four outputs are available for driving the loads or bus lines. The outputs are disabled independently from the level of the clock by a high logic level at either output control input. The outputs then present a high impedance and neither load nor drive the bus line. Detailed operation is given in the function table.

To minimize the possibility that two outputs will attempt to take a common bus to opposite logic levels, the output control circuitry is designed so that the average output disable times are shorter than the average output enable times.

Features

YTRI-STATE outputs interface directly with system bus

YGated output control lines for enabling or disabling the outputs

YFully independent clock elminates restrictions for operating in one of two modes:

Parallel load

Do nothing (hold)

YFor application as bus buffer registers

YTypical propagation delay 18 ns

YTypical frequency 30 MHz

YTypical power dissipation 250 mW

YAlternate Military/Aerospace device (54173) is available. Contact a National Semiconductor Sales Office/ Distributor for specifications.

Connection Diagram	Function Table
Dual-In-Line Package
				Inputs
							Output
				Data Enable		Data
	Clear		Clock				Q
				G1	G2	D
	H		X	X	X	X	L
	L		L	X	X	X	Q0
	L		u	H	X	X	Q0
	L		u	X	H	X	Q0
	L		u	L	L	L	L
	L		u	L	L	H	H
	When either M or N (or both) is (are) high the output is disabled to the
	high-impedance state; however, sequential operation of the flip-flops is
	not affected.
	H e high level (steady state)
	L e low level (steady state)
	u e low-to-high level transition
	X e don't care (any input including transitions)
	Q0 e the level of Q before the indicated steady state input conditions were
	established
TL/F/6556 ± 1
Order Number 54173DMQB, 54173FMQB,
DM54173J, DM54173W or DM74173N
See NS Package Number J16A, N16E or W16A

TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.

Registers D Quad STATE-TRI 54173/DM54173/DM74173

C1995 National Semiconductor Corporation

TL/F/6556

RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Note)

If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/Distributors for availability and specifications.

Supply Voltage	7V
Input Voltage	5.5V
Operating Free Air Temperature Range	b55§C to a125§C
DM54 and 54
DM74	0§C to a70§C
Storage Temperature Range	b65§C to a150§C

Note: The ``Absolute Maximum Ratings'' are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the ``Electrical Characteristics'' table are not guaranteed at the absolute maximum ratings. The ``Recommended Operating Conditions'' table will define the conditions for actual device operation.

Recommended Operating Conditions

Symbol		Parameter			DM54173			DM74173		Units
				Min	Nom	Max	Min	Nom	Max
VCC	Supply Voltage			4.5	5	5.5	4.75	5	5.25	V
VIH	High Level Input Voltage			2			2			V
VIL	Low Level Input Voltage					0.8			0.8	V
IOH	High Level Output Current					b2			b5.2	mA
IOL	Low Level Output Current					16			16	mA
fCLK	Clock Frequency (Note 4)			0		25	0		25	MHz
tW	Pulse Width		Clock	20			20			ns
	(Note 4)		Clear	20			20
tSU	Setup Time		Enable	17			17			ns
	(Note 4)		Data	10			10
tH	Hold Time		Enable	2			2			ns
	(Note 4)		Data	10			10
tREL	Clear Release Time (Note 4)			10			10			ns
TA	Free Air Operating Temperature			b55		125	0		70	§C

Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)

Symbol	Parameter	Conditions			Min	Typ	Max	Units
						(Note 1)
VI	Input Clamp Voltage	VCC e Min, II e b12 mA					b1.5	V
VOH	High Level Output	VCC e Min, IOH e Max			2.4			V
	Voltage	VIL e Max, VIH e Min
VOL	Low Level Output	VCC e Min, IOL e Max					0.4	V
	Voltage	VIH e Min, VIL e Max
II	Input Current @ Max	VCC e Max, VI e 5.5V					1	mA
	Input Voltage
IIH	High Level Input Current	VCC e Max, VI e 2.4V					40	mA
IIL	Low Level Input Current	VCC e Max, VI e 0.4V					b1.6	mA
IOZH	Off-State Output Current with High	VCC e Max, VO e 2.4V					40	mA
	Level Output Voltage Applied	VIH e Min, VIL e Max
IOZL	Off-State Output Current with Low	VCC e Max, VO e 0.4V					b40	mA
	Level Output Voltage Applied	VIH e Min, VIL e Max
IOS	Short Circuit	VCC e Max		DM54	b30		b70	mA
	Output Current	(Note 2)		DM74	b30		b70
ICC	Supply Current	VCC e Max (Note 3)				50	72	mA
Note 1: All typicals are at VCC e 5V, TA e 25§C.

Note 2: Not more than one output should be shorted at a time.

Note 3: ICC is measured with all outputs open, CLEAR grounded after a momentary connection to 4.5V: N, G1, G2 and all DATA inputs grounded: and the CLOCK input and M input at 4.5V.

Note 4: TA e 25§C and VCC e 5V.

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