Motorola SN54LS174J, SN74LS174N, SN74LS174D Datasheet

5-1

FAST AND LS TTL DATA

HEX D FLIP-FLOP

The LSTTL /MSI SN54 /74LS174 is a high speed Hex D Flip-Flop. The
device is used primarily as a 6-bit edge-triggered storage register. The
information on the D inputs is transferred to storage during the LOW to HIGH
clock transition. The device has a Master Reset to simultaneously clear all
flip-flops. The LS174 is fabricated with the Schottky barrier diode process for
high speed and is completely compatible with all Motorola TTL families.

• Edge-Triggered D-Type Inputs

• Buffered-Positive Edge-Triggered Clock

• Asynchronous Common Reset

• Input Clamp Diodes Limit High Speed Termination Effects

NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.

CONNECTION DIAGRAM DIP (TOP VIEW)

14 13 12 11 10 9

1 2 3 4 5 6

7

16 15

8

V

CC

MR

Q5D5D4Q

4

Q

3

D

3

CP

Q0D0D1Q1D2Q2GND

PIN NAMES LOADING (Note a)

HIGH

LOW

D0–D

5

CP
MR
Q0–Q

5

Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)

0.5 U.L.

0.5 U.L.

0.5 U.L.
10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 (2.5) U.L.

NOTES:
a. 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b. The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)

b. Temperature Ranges.

LOGIC DIAGRAM

D Q
CP

C

D

Q

5

Q

4

Q

3

Q

2

Q

1

Q

0

CP D

5

D

4

D

3

D

2

D

1

D

0

MR

14

2

6

7

3

4

5

9 11

12

10

13

15

D Q
CP

C

D

D Q
CP

C

D

D Q
CP

C

D

D Q
CP

C

D

D Q
CP

C

D

1

VCC = PIN 16
GND = PIN 8

= PIN NUMBERS

SN54/74LS174

HEX D FLIP-FLOP

LOW POWER SCHOTTKY

J SUFFIX

CERAMIC

CASE 620-09

N SUFFIX

PLASTIC

CASE 648-08

16

1

16

1

ORDERING INFORMATION

SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC

16

1

D SUFFIX

SOIC

CASE 751B-03

LOGIC SYMBOL

VCC = PIN 16
GND = PIN 8

D5D4D3D2D1D

0

9
1

3 4 6 11 13 14

CP
MR

Q2Q1Q

0

Q3Q4Q

5

2 5 7 10 12 15

5-2

FAST AND LS TTL DATA

SN54/74LS174

FUNCTIONAL DESCRIPTION

The LS174 consists of six edge-triggered D flip-flops with
individual D inputs and Q outputs. The Clock (CP) and Master
Reset (MR) are common to all flip-flops.

Each D input’s state is transferred to the corresponding flip­flop’s output following the LOW to HIGH Clock (CP) transition.

A LOW input to the Master Reset (MR

) will force all outputs
LOW independent of Clock or Data inputs. The LS174 is
useful for applications where the true output only is required
and the Clock and Master Reset are common to all storage
elements.

TRUTH TABLE

Inputs (t = n, MR = H) Outputs (t = n+1) Note 1

D Q
H H

L L

Note 1: t = n + 1 indicates conditions after next clock.

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit

V

CC

Supply Voltage 54

74

4.5

4.75

5.0

5.0

5.5

5.25

V

T

A

Operating Ambient Temperature Range 54

74

–55

0

25
25

125

70

°C

I

OH

Output Current — High 54, 74 –0.4 mA

I

OL

Output Current — Low 54

74

4.0

8.0

mA

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)

Limits

Symbol

Parameter

Min Typ Max

Unit

Test Conditions

V

IH

Input HIGH Voltage 2.0 V

Guaranteed Input HIGH Voltage for
All Inputs

54 0.7

VILInput LOW Voltage

74 0.8

V

Guaranteed Input LOW Voltage for
All Inputs

V

IK

Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA

54 2.5 3.5 V

CC

= MIN, IOH = MAX, VIN = V

IH

VOHOutput HIGH Voltage

74 2.7 3.5 V

VCC = MIN, IOH = MAX, VIN = V

IH

or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA

VOLOutput LOW Voltage

74 0.35 0.5 V IOL = 8.0 mA

VIN = VIL or V

IH

per Truth Table

20 µA VCC = MAX, VIN = 2.7 V

IIHInput HIGH Current

0.1 mA VCC = MAX, VIN = 7.0 V

I

IL

Input LOW Current –0.4 mA VCC = MAX, VIN = 0.4 V

I

OS

Short Circuit Current (Note 1) –20 –100 mA VCC = MAX

I

CC

Power Supply Current 26 mA VCC = MAX

Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

Guaranteed Input LOW Voltage for

V

VCC = VCC MIN,