Motorola MC10E195FN, MC100E195FN Datasheet

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SEMICONDUCTOR TECHNICAL DATA

2–1

REV 2

 Motorola, Inc. 1996

12/93

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The MC10E/100E195 is a programmable delay chip (PDC) designed primarily for clock de-skewing and timing adjustment. It provides variable delay of a differential ECL input transition.

The delay section consists of a chain of gates organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E195 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6], which are latched on chip by a high signal on the latch enable (LEN) control.

Because the delay programmability of the E195 is achieved by purely differential ECL gate delays the device will operate at frequencies of >1.0 GHz while maintaining over 600 mV of output swing.

The E195 thus offers very fine resolution, at very high frequencies, that is selectable entirely from a digital input allowing for very accurate system clock timing.

An eighth latched input, D7, is provided for cascading multiple PDC’s for increased programmable range. The cascade logic allows full control of multiple PDC’s, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.

• 2.0ns Worst Case Delay Range

• ≈20ps/Delay Step Resolution

• >1.0GHz Bandwidth

• On Chip Cascade Circuitry

• Extended 100E V

Range of –4.2 to –5.46V

• 75KΩ Input Pulldown Resistors

PIN NAMES

Pin Function

IN/IN EN D[0:7] Q/Q LEN SET MIN SET MAX CASCADE

Signal Input Input Enable Mux Select Inputs Signal Output Latch Enable Min Delay Set Max Delay Set Cascade Signal

LOGIC DIAGRAM – SIMPLIFIED

IN IN

LEN

SET MIN

SET MAX

110

1 1 1

101

Q Q

CASCADE

7 BIT LATCH

LEN Q

LATCH

4 GATES 8 GATES 16 GATES

* 1.25

* 1.5

D0 D1 D2 D3 D4 D5 D6 D7

* DELAYS ARE 25% OR 50% LONGER THAN

* STANDARD (STANDARD

≈

80 PS)

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PROGRAMMABLE

DELAY CHIP

FN SUFFIX

PLASTIC PACKAGE

CASE 776-02

D3 D4 D5 D6 D7 NC

NC NC EN

SET MIN

SET MAX

CASCADE

CCO

Q Q

CCO

D0 LEN

IN IN V

25 24 23 22 21 20 19

26 27 28

1 2 3 4

18 17

16 15

14 13 12

5 6 7 8 9 10 11

Pinout:

28-Lead PLCC

(Top View)

MC10E195 MC100E195

MOTOROLA ECLinPS and ECLinPS Lite

DL140 — Rev 4

2–2

DC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V

CCO

= GND)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Condition

Input HIGH Current 150 150 150 µA

Power Supply Current

10E 100E

130 130

156 156

130 130

156 156

130 150

156 179

AC CHARACTERISTICS (VEE = VEE(min) to VEE(max); VCC = V

CCO

= GND)

0°C 25°C 85°C

Symbol Characteristic Min Typ Max Min Typ Max Min Typ Max Unit Notes

PLH

PHL

Propagation Delay

IN to Q; Tap = 0 IN to Q; Tap = 127 EN

to Q; Tap = 0

D7 to CASCADE

1210 3320 1250

300

1360 3570 1450

450

1510 3820 1650

700

1240 3380 1275

300

1390 3630 1475

450

1540 3880 1675

700

1440 3920 1350

300

1590 4270 1650

450

1765 4720 1950

700

RANGE

Programmable Range

tPD (max) – tPD (min)

2000 2175 2050 2240 2375 2580

∆t Step Delay

D0 High D1 High D2 High D3 High D4 High D5 High D6 High

55 115 250 505

1000

17 34

68 136 272 544

1088

105 180 325 620

1190

55 115 250 515

1030

17.5 35 70

140 280 560

1120

105 180 325 620

1220

65 140 305 620

1240

21 42

84 168 336 672

1344

120 205 380 740

1450

ps 6

Lin Linearity D1 D0 D1 D0 D1 D0 7 t

SKEW

Duty Cycle Skew

PHL–tPLH

±30 ±30 ±30

Setup Time

D to LEN D to IN EN

to IN

200 800 200

0 200

800 200

0 200

800 200

2 3

Hold Time

LEN to D IN to EN

5000250 5000250 5000250

Release Time

to IN SET MAX to LEN SET MIN to LEN

300 800 800

jit

Jitter <5.0 <5.0 <5.0 ps 8

Output Rise/Fall Time

20–80% (Q) 20–80% (CASCADE)

125 300

225 450

325 650

125 300

225 450

325 650

125 300

225 450

325 650

1. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output.

2. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set.

3. This setup time is the minimum time that EN

must be asserted prior to the next transition of IN/IN to prevent an output response greater than

±75 mV to that IN/IN

transition.

4. This hold time is the minimum time that EN

must remain asserted after a negative going IN or positive going IN to prevent an output response

greater than ±75 mV to that IN/IN transition.

5. This release time is the minimum time that EN

must be deasserted prior to the next IN/IN transition to ensure an output response that meets

the specified IN to Q propagation delay and transition times.

6. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range.

7. The linearity specification guarantees to which delay control input the programmable steps will be monotonic (i.e. increasing delay steps for increasing binary counts on the control inputs Dn). T ypically the device will be monotonic to the D0 input, however under worst case conditions and process variation, delays could decrease slightly with increasing binary counts when the D0 input is the LSB. With the D1 input as the LSB the device is guaranteed to be monotonic over all specified environmental conditions and process variation.

8. The jitter of the device is less than what can be measured without resorting to very tedious and specialized measurement techniques.

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