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μPD78083 SUBSERIES

8-BIT SINGLE-CHIP MICROCONTROLLER

μPD78081 μPD78081(A) μPD78082 μPD78082(A)

μPD78P083 μPD78P083(A) μPD78P081(A2)

 

 

 

Document No. U12176EJ2V0UM00 (2nd edition)

 

 

 

(O. D. No. IEU-886)

 

 

 

Date Published May 1997 N

©

 

4

Printed in Japan

 

 

1992

 

NOTES FOR CMOS DEVICES

1PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

FIP, IEBus, and QTOP are trademarks of NEC Corporation.

MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United States and/or other countries.

IBM DOS, PC/AT and PC DOS are trademarks of International Business Machines Corporation. HP9000 Series 300, HP9000 Series 700, and HP-UX are trademarks of Hewlett-Packard Company. SPARCstation is a trademark of SPARC International, Inc.

Sun OS is a trademark of Sun Microsystems, Inc.

Ethernet is a trademark of XEROX Corporation.

NEWS and NEWS-OS are trademarks of SONY Corporation.

OSF/Motif is a trademark of Open Software Foundation, Inc.

TRON is an abbreviation of The Realtime Operating system Nucleus.

ITRON is an abbreviation of Industrial TRON.

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these products may be prohibited without governmental license. To export or re-export some or all of these products from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales representative.

License not needed: μPD78P083DU

The customer must judge the need for license:

μPD78081CU-×××, 78081GB-×××-3B4, 78081GB-×××-3BS-MTX μPD78081GB(A)-×××-3B4, 78081GB(A2)-×××-3B4 μPD78082CU-×××, 78082GB-×××-3B4, 78082GB-×××-3BS-MTX μPD78082GB(A)-×××-3B4

μPD78P083CU, 78P083GB-3B4, 78P083GB-3BS-MTX μPD78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated “quality assurance program“ for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M7 96.5

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC product in your application, please contact the NEC office in your country to obtain a list of authorized representatives and distributors. They will verify:

Device availability

Ordering information

Product release schedule

Availability of related technical literature

Development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, AC supply voltages, and so forth)

Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country.

NEC Electronics Inc. (U.S.)

NEC Electronics (Germany) GmbH

NEC Electronics Hong Kong Ltd.

Santa Clara, California

Benelux Office

Hong Kong

Tel: 800-366-9782

Eindhoven, The Netherlands

Tel: 2886-9318

Fax: 800-729-9288

Tel: 040-2445845

Fax: 2886-9022/9044

NEC Electronics (Germany) GmbH

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

 

Duesseldorf, Germany

NEC Electronics (France) S.A.

Seoul Branch

Tel: 0211-65 03 02

Velizy-Villacoublay, France

Seoul, Korea

Fax: 0211-65 03 490

Tel: 01-30-67 58 00

Tel: 02-528-0303

NEC Electronics (UK) Ltd.

Fax: 01-30-67 58 99

Fax: 02-528-4411

 

NEC Electronics Singapore Pte. Ltd.

Milton Keynes, UK

NEC Electronics (France) S.A.

Tel: 01908-691-133

Spain Office

United Square, Singapore 1130

Fax: 01908-670-290

Madrid, Spain

Tel: 253-8311

NEC Electronics Italiana s.r.1.

Tel: 01-504-2787

Fax: 250-3583

Fax: 01-504-2860

NEC Electronics Taiwan Ltd.

Milano, Italy

 

Tel: 02-66 75 41

NEC Electronics (Germany) GmbH

Taipei, Taiwan

Fax: 02-66 75 42 99

Scandinavia Office

Tel: 02-719-2377

 

Taeby, Sweden

Fax: 02-719-5951

 

Tel: 08-63 80 820

NEC do Brasil S.A.

 

Fax: 08-63 80 388

 

 

Sao Paulo-SP, Brasil

 

 

Tel: 011-889-1680

 

 

Fax: 011-889-1689

J96. 8

 

Major Revision in This Edition

 

 

Page

Description

 

 

Throughout

The following products have been already developed

 

μPD78081CU-×××, 78081GB-×××-3B4, 78082CU-×××, 78082GB-×××-3B4, 78P083CU, 78P083DU,

 

78P083GB-3B4

 

 

 

The following products have been added

 

μPD78081GB-×××-3BS-MTX, 78082GB-×××-3BS-MTX, 78P083GB-3BS-MTX, 78081GB(A)-×××-3B4,

 

78082GB(A)-×××-3B4, 78P083CU(A), 78P083GB(A)-3B4, 78P083GB(A)-3BS-MTX, 78081GB(A2)-×××-3B4

 

 

 

Changes supply voltage to VDD = 1.8 to 5.5V.

 

 

p. 9

1.6 78K/0 Series Development has been changed.

 

 

p. 13

1.9 Differences between the μPD78081, 78082, and 78P083, the μPD78081(A), 78082(A), and

 

78P083(A), and the μPD78081(A2) has been added.

 

 

p. 19

Cautions regarding the use of functions in common with 2.2.5 (2) (d) ASCK has been added.

 

 

p. 72

Cautions concerning the Write to OSMS Command has been added to 5.3 (2) Oscillation mode select

 

register (OSMS).

 

 

p. 73

Cautions concerning external clock input in 5.4.1 Main system clock oscillator has been changed.

 

 

p. 108

Figure 7-3. Watchdog Timer Mode Register Format, notes and cautions have been added.

 

 

p. 110

Description of 7.4.2 Interval timer operation has been changed.

 

 

p. 113

Cautions with regard to rewriting TCL0 to other than same data has been added to 8.3 (1) Timer clock

 

select register 0 (TCL0).

 

 

p. 120

The HSC bit has been added to the A/D Converter Mode

 

Register in Figure10-1. A/D Converter Block Diagram.

 

 

p. 122, 193

10.3 (1) A/D converter mode register (ADM), 13.1.1 Standby function, and Cautions have been added.

 

 

p. 137

Figure 11-1. Serial Interface Channel 2 Block Diagram has been corrected.

 

 

p. 146, 155

11.3 (4) (a), 11.4.2 (1) (d) (i) Generation of baud rate transmit/receive clock by means of main system

 

clock have been added.

 

76800 bps has been added to baud rate generated from the main system clock.

 

 

p. 161

Figure 11-10. Receive Error Timing has been corrected.

 

 

p. 165

11.4.3 (1) (c) Baud rate generator control register (BRGC) has been added.

 

 

p. 168

11.4.3 (3) MSB/LSB switching as start bit has been added.

 

 

p. 206

15.1 Memory Size Switching Register has been changed from W to R/W.

 

 

p. 205

Items and cautions have been added to Table 15-1. Differences between the μPD78P083 and Mask ROM

 

Versions.

 

 

p. 214

A description of the QTOP microcontroller has been added to 15.5 Screening of One-Time PROM

 

Versions.

 

 

p. 232

Figure A-1. Development Tool Configuration has been changed.

 

 

p. 231

APPENDIX A DEVELOPMENT TOOLS

 

The following Development Tools have been added:

 

IE-78000-R-A, IE-70000-98-IF-B, IE-70000-98N-IF, IE-70000-PC-IF-B, IE-78000-R-SV3, SM78K0, ID78K0

 

 

p. 239

A.4 OS for IBM PC has been added.

 

 

p. 240

Table A-2. System-Up Method from Other In-Circuit Emulator to IE-78000-R-A has been added.

 

 

p. 244

B.1 Real-time OS has been added.

 

 

p. 249

APPENDIX D REVISION HISTORY has been added.

 

 

The mark shows major revised points.

 

 

PREFACE

 

 

Readers

This manual has been prepared for user engineers who want to understand the

 

functions of the μPD78083 subseries and design and develop its application

 

systems and programs.

 

 

Caution

In the μPD78083 Subseries, the μPD78P083DU is not designed to maintain the

 

reliability required for use in customers’ mass-produced equipment.

 

Please use this device only for experimentation or for evaluation of functions.

Purpose

This manual is intended for users to understand the functions described in the

 

Organization below.

 

 

Organization

The μPD78083 subseries manual is separated into two parts: this manual and the

 

instruction edition (common to the 78K/0 Series).

 

 

 

 

 

 

 

 

μPD78083 Subseries

 

78K/0 Series

 

 

 

User’s Manual

 

User’s Manual

 

 

 

(This Manual)

 

Instruction

 

 

 

 

 

 

 

 

 

Pin functions

CPU functions

 

 

Internal block functions

Instruction set

 

 

Interrupt

Explanation of each instruction

 

 

Other on-chip peripheral functions

 

 

How to Read This Manual Before reading this manual, you should have general knowledge of electric and logic circuits and microcontrollers.

For those who will be using this as a manual for the μPD78081(A), 78082(A), 78P083(A) and 78081(A2):

The μPD78081, 78082, 78P083 are explained as being representative devices.

In case this is used as a manual for the μPD78081(A), 78082(A), 78P083(A), or 78081(A2), please reread the product names as follows.

μPD78081 → μPD78081(A) or μPD78081(A2)

μPD78082 → μPD78082(A)

μPD78P083 → μPD78P083(A)

When you want to understand the functions in general:

Read this manual in the order of the contents.

To know the μPD78083 Subseries instruction function in detail:

Refer to the 78K/0 Series User's Manual: Instructions (IEU-1372)

How to interpret the register format:

For the circled bit number, the bit name is defined as a reserved word in RA78K/0, and in CC78K/0, already defined in the header file named sfrbit.h.

To learn the function of a register whose register name is known:

Refer to Appendix C Register Index.

To know the electrical specifications of the μPD78083 Subseries:

Refer to separately available Data Sheet.

To know application examples of the functions provided in the μPD78083 Subseries:

Refer to Application Note separately provided.

Legend

Data representation weight

: High digits on the left and low digits on the right

 

Active low representations

: ××× (line over the pin and signal names)

 

Note

: Description of note in the text.

 

Caution

: Information requiring particular attention

 

Remarks

:

Additional explanatory material

 

Numeral representations

:

Binary ... ×××× or ××××B

 

 

 

Decimal ... ××××

 

 

 

Hexadecimal ... ××××H

Examples of use in this manual are prepared for “Standard” quality level devices for general electronic equipment. In the case of examples of use in this manual for devices which meet “Special” quality level requirements, please use each device only after studying each part that is actuall to be used, the circuitry and the quality level of each component before use.

Related Documents

The related documents indicated in this publication may include preliminary

 

versions. However, preliminary versions are not marked as such.

Related documents for μPD78054 subseries

 

 

 

 

 

 

 

 

Document name

Document No.

 

 

 

 

 

 

Japanese

English

 

 

 

 

μPD78083 Subseries User’s Manual

U12176J

This Manual

 

 

 

 

 

μPD78081, 78082 Data Sheet

 

 

U11415J

U11415E

 

 

 

 

 

μPD78P083 Data Sheet

 

 

U11006J

U11006E

 

 

 

 

μPD78081(A), 78082(A), 78081(A2) Data Sheet

In preparation

To be prepared

 

 

 

 

 

μPD78P083(A) Data Sheet

 

 

U12175J

U12175E

 

 

 

 

μPD78083 Subseries Special Function Register Table

IEM-5599

 

 

 

 

78K/0 Series User’s Manual—Instruction

IEU-849

IEU-1372

 

 

 

 

 

78K/0 Series Instruction Table

 

 

U10903J

 

 

 

 

 

78K/0 Series Instruction Set

 

 

U10904J

 

 

 

 

 

78K/0 Series Application Note

 

Basics (III)

IEA-767

U10182E

 

 

 

 

 

Caution: The above documents are subject to change without prior notice. Be sure to use the latest version

document when starting design.

Development Tool Documents (User’s Manuals)

Document name

 

Document No.

 

 

 

 

 

Japanese

English

 

 

 

 

RA78K Series Assembler Package

Operation

EEU-809

EEU-1399

 

 

 

 

 

Language

EEU-815

EEU-1404

 

 

 

 

RA78K Series Structured Assembler Preprocessor

 

EEU-817

EEU-1402

 

 

 

 

RA78K0 Assembler Package

Structured assembly language

U11789J

U11789E

 

 

 

 

 

Assembly language

U11801J

U11801E

 

 

 

 

 

Operation

U11802J

U11802E

 

 

 

 

CC78K Series C Compiler

Operation

EEU-656

EEU-1280

 

 

 

 

 

Language

EEU-655

EEU-1284

 

 

 

 

CC78K/0 C Compiler

Operation

U11517J

U11517E

 

 

 

 

 

Language

U11518J

U11518E

 

 

 

 

CC78K/0 C Compiler Application Note

Programming know-how

EEA-618

EEA-1208

 

 

 

 

CC78K Series Library Source File

 

EEU-777

 

 

 

 

PG-1500 PROM Programmer

 

U11940J

EEU-1335

 

 

 

 

PG-1500 Controller PC-9800 Series (MS-DOS™) Base

 

EEU-704

EEU-1291

 

 

 

 

PG-1500 Controller IBM PC Series (PC DOS™) Base

 

EEU-5008

U10540E

 

 

 

 

IE-78000-R

 

EEU-810

U11376E

 

 

 

 

IE-78000-R-A

 

U10057J

U10057E

 

 

 

 

IE-78000-R-BK

 

EEU-867

EEU-1427

 

 

 

 

IE-78078-R-EM

 

U10775J

U10775E

 

 

 

 

EP-78083

 

EEU-5003

EEU-1529

 

 

 

 

SM78K0 System Simulator Windows™ Base

Reference

U10181J

U10181E

 

 

 

 

SM78K Series System Simulator

External component user

U10092J

U10092E

 

open interface specifications

 

 

 

 

 

 

ID78K0 Integrated Debugger EWS Base

Reference

U11151J

 

 

 

 

ID78K0 Integrated Debugger PC Base

Reference

U11539J

 

 

 

 

ID78K0 Integrated Debugger Windows™ Base

Guide

U11649J

U11649E

 

 

 

 

SD78K/0 Screen Debugger

Introduction

EEU-852

U10539E

 

 

 

 

PC-9800 Series (MS-DOS) Base

Reference

U10952J

 

 

 

 

SD78K/0 Screen Debugger

Introduction

EEU-5024

EEU-1414

 

 

 

 

IBM PC/AT™ (PC DOS) Base

Reference

U11279J

U11279E

 

 

 

 

Caution: The above documents are subject to change without prior notice. Be sure to use the latest version

document when starting design.

Documents for Embedded Software (User’s Manual)

Document name

 

Document No.

 

 

 

 

 

Japanese

English

 

 

 

 

78K/0 Series Real-Time OS

Basics

U11537J

 

 

 

 

 

Installation

U11536J

 

 

 

 

 

Technicals

U11538J

 

 

 

 

OS for 78K/0 Series MX78K0

Basics

EEU-5010

 

 

 

 

Fuzzy Knowledge Data Creation Tool

 

EEU-829

EEU-1438

 

 

 

 

78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System—Translator

EEU-862

EEU-1444

 

 

 

 

78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Module

EEU-858

EEU-1441

 

 

 

 

78K/0 Series Fuzzy Inference Development Support System—Fuzzy Inference Debugger

EEU-921

EEU-1458

 

 

 

 

Other Documents

Document name

Document No.

 

 

 

Japanese

English

 

 

 

IC PACKAGE MANUAL

C10943X

 

 

 

 

Semiconductor Device Mounting Technology Manual

C10535J

C10535E

 

 

 

Quality Grade on NEC Semiconductor Devices

C11531J

C11531E

 

 

 

Reliability Quality Control on NEC Semiconductor Devices

C10983J

C10983E

 

 

 

Electric Static Discharge (ESD) Test

MEM-539

 

 

 

Semiconductor Devices Quality Assurance Guide

C11893J

C11893E

 

 

 

Microcontroller Related Product Guide—Third Party Manufacturers

U11416J

 

 

 

Caution: The above documents are subject to change without prior notice. Be sure to use the latest version

document when starting design.

CONTENTS

CHAPTER 1 OUTLINE .....................................................................................................................

1

1.1

Features .............................................................................................................................

1

1.2

Applications ......................................................................................................................

2

1.3

Ordering Information ........................................................................................................

2

1.4

Quality Grade ....................................................................................................................

3

1.5

Pin Configuration (Top View) ...........................................................................................

4

1.6

78K/0 Series Development ...............................................................................................

9

1.7

Block Diagram ...................................................................................................................

11

1.8

Outline of Function ...........................................................................................................

12

1.9Differences between the μPD78081, 78082 and 78P083, the μPD78081(A), 78082(A)

 

and 78P083(A), and the μPD78081(A2) ...........................................................................

13

CHAPTER 2

PIN FUNCTION ...........................................................................................................

15

2.1

Pin Function List ...............................................................................................................

15

 

2.1.1

 

Normal operating mode pins ...............................................................................................

15

 

2.1.2

 

PROM programming mode pins (μPD78P083 only) ............................................................

16

2.2 Description of Pin Functions ...........................................................................................

17

 

2.2.1

 

P00 to P03 (Port 0) ..............................................................................................................

17

 

2.2.2

 

P10 to P17 (Port 1) ..............................................................................................................

17

 

2.2.3

 

P30 to P37 (Port 3) ..............................................................................................................

18

 

2.2.4

 

P50 to P57 (Port 5) ..............................................................................................................

18

 

2.2.5

 

P70 to P72 (Port 7) ..............................................................................................................

19

 

2.2.6

 

P100 to P101 (Port 10) ........................................................................................................

19

 

2.2.7

 

AVREF ..................................................................................................................................

20

 

2.2.8

 

AVDD ....................................................................................................................................

20

 

2.2.9

 

AVSS ....................................................................................................................................

20

 

 

 

 

 

 

 

2.2.10

 

RESET .................................................................................................................................

20

 

2.2.11

X1 and X2 ............................................................................................................................

20

 

2.2.12

VDD ......................................................................................................................................

20

 

2.2.13

VSS ......................................................................................................................................

20

 

2.2.14

VPP (μPD78P083 only) .........................................................................................................

20

 

2.2.15

 

IC (Mask ROM version only) ................................................................................................

21

 

2.2.16

 

NC (44-pin plastic QFP versions only) .................................................................................

21

2.3 Pin Input/Output Circuits and Recommended Connection of Unused Pins ...............

22

CHAPTER 3

CPU ARCHITECTURE ................................................................................................

25

3.1

Memory Spaces.................................................................................................................

25

 

3.1.1

 

Internal program memory space ..........................................................................................

28

 

3.1.2

 

Internal data memory space ................................................................................................

29

 

3.1.3

 

Special Function Register (SFR) area .................................................................................

29

 

3.1.4

 

Data memory addressing ....................................................................................................

29

3.2

Processor Registers .........................................................................................................

33

 

3.2.1

 

Control registers ..................................................................................................................

33

 

3.2.2

 

General registers .................................................................................................................

36

– i –

 

3.2.3 Special Function Register (SFR) .........................................................................................

37

3.3

Instruction Address Addressing .....................................................................................

40

 

3.3.1

Relative Addressing .............................................................................................................

40

 

3.3.2

Immediate addressing .........................................................................................................

41

 

3.3.3

Table indirect addressing .....................................................................................................

42

 

3.3.4

Register addressing .............................................................................................................

43

3.4

Operand Address Addressing .........................................................................................

44

 

3.4.1

Implied addressing ..............................................................................................................

44

 

3.4.2

Register addressing .............................................................................................................

45

 

3.4.3

Direct addressing .................................................................................................................

46

 

3.4.4

Short direct addressing ........................................................................................................

47

 

3.4.5 Special-Function Register (SFR) addressing ......................................................................

49

 

3.4.6

Register indirect addressing ................................................................................................

50

 

3.4.7

Based addressing ................................................................................................................

51

 

3.4.8

Based indexed addressing ..................................................................................................

52

 

3.4.9

Stack addressing .................................................................................................................

52

CHAPTER 4

PORT FUNCTIONS ....................................................................................................

53

4.1

Port Functions...................................................................................................................

53

4.2

Port Configuration ............................................................................................................

55

 

4.2.1

Port 0 ...................................................................................................................................

55

 

4.2.2

Port 1 ...................................................................................................................................

57

 

4.2.3

Port 3 ...................................................................................................................................

58

 

4.2.4

Port 5 ...................................................................................................................................

59

 

4.2.5

Port 7 ...................................................................................................................................

60

 

4.2.6

Port 10 .................................................................................................................................

62

4.3

Port Function Control Registers .....................................................................................

63

4.4

Port Function Operations.................................................................................................

67

 

4.4.1 Writing to input/output port...................................................................................................

67

 

4.4.2 Reading from input/output port ............................................................................................

67

 

4.4.3 Operations on input/output port ...........................................................................................

67

CHAPTER 5

CLOCK GENERATOR ................................................................................................

69

5.1

Clock Generator Functions ..............................................................................................

69

5.2

Clock Generator Configuration .......................................................................................

69

5.3

Clock Generator Control Register ...................................................................................

71

5.4

System Clock Oscillator ...................................................................................................

73

 

5.4.1 Main system clock oscillator ................................................................................................

73

 

5.4.2

Scaler ...................................................................................................................................

75

5.5

Clock Generator Operations ............................................................................................

76

5.6

Changing CPU Clock Settings .........................................................................................

77

 

5.6.1 Time required for CPU clock switchover ..............................................................................

77

 

5.6.2 CPU clock switching procedure ...........................................................................................

78

CHAPTER 6 8-BIT TIMER/EVENT COUNTERS 5 AND 6 ..............................................................

79

6.1

8-Bit Timer/Event Counters 5 and 6 Functions ..............................................................

80

6.2

8-Bit Timer/Event Counters 5 and 6 Configurations ......................................................

82

6.3

8-Bit Timer/Event Counters 5 and 6 Control Registers .................................................

84

– ii –

6.4

8-Bit Timer/Event Counters 5 and 6 Operations ............................................................

90

 

6.4.1

Interval timer operations ......................................................................................................

90

 

6.4.2 External event counter operation .........................................................................................

93

 

6.4.3

Square-wave output ............................................................................................................

94

 

6.4.4

PWM output operations .......................................................................................................

96

6.5

Cautions on 8-Bit Timer/Event Counters 5 and 6 ..........................................................

100

CHAPTER 7

WATCHDOG TIMER ...................................................................................................

103

7.1

Watchdog Timer Functions ..............................................................................................

103

7.2

Watchdog Timer Configuration .......................................................................................

105

7.3

Watchdog Timer Control Registers .................................................................................

106

7.4

Watchdog Timer Operations ............................................................................................

109

 

7.4.1

Watchdog timer operation ....................................................................................................

109

 

7.4.2

Interval timer operation ........................................................................................................

110

CHAPTER 8 CLOCK OUTPUT CONTROL CIRCUIT .....................................................................

111

8.1

Clock Output Control Circuit Functions .........................................................................

111

8.2

Clock Output Control Circuit Configuration ...................................................................

112

8.3

Clock Output Function Control Registers ......................................................................

113

CHAPTER 9 BUZZER OUTPUT CONTROL CIRCUIT ....................................................................

115

9.1

Buzzer Output Control Circuit Functions .......................................................................

115

9.2

Buzzer Output Control Circuit Configuration .................................................................

115

9.3

Buzzer Output Function Control Registers ....................................................................

116

CHAPTER 10 A/D CONVERTER .......................................................................................................

119

10.1

A/D Converter Functions ..................................................................................................

119

10.2

A/D Converter Configuration ...........................................................................................

119

10.3

A/D Converter Control Registers .....................................................................................

122

10.4

A/D Converter Operations ................................................................................................

126

 

10.4.1 Basic operations of A/D converter .......................................................................................

126

 

10.4.2 Input voltage and conversion results ...................................................................................

128

 

10.4.3 A/D converter operating mode .............................................................................................

129

10.5

A/D Converter Cautions ...................................................................................................

131

CHAPTER 11 SERIAL INTERFACE CHANNEL 2 ............................................................................

135

11.1

Serial Interface Channel 2 Functions ..............................................................................

135

11.2

Serial Interface Channel 2 Configuration .......................................................................

136

11.3

Serial Interface Channel 2 Control Registers .................................................................

140

11.4

Serial Interface Channel 2 Operation ..............................................................................

148

 

11.4.1 Operation stop mode ...........................................................................................................

148

 

11.4.2 Asynchronous serial interface (UART) mode ......................................................................

150

 

11.4.3 3-wire serial I/O mode .........................................................................................................

163

CHAPTER 12 INTERRUPT FUNCTION ............................................................................................

171

12.1

Interrupt Function Types ..................................................................................................

171

12.2

Interrupt Sources and Configuration ..............................................................................

172

12.3

Interrupt Function Control Registers ..............................................................................

175

– iii –

12.4 Interrupt Servicing Operations ........................................................................................

181

12.4.1 Non-maskable interrupt request acknowledge operation ....................................................

181

12.4.2 Maskable interrupt request acknowledge operation ............................................................

184

12.4.3 Software interrupt request acknowledge operation .............................................................

187

12.4.4

Multiple interrupt servicing ...................................................................................................

187

12.4.5

Interrupt request reserve .....................................................................................................

191

CHAPTER 13 STANDBY FUNCTION ................................................................................................

193

13.1

Standby Function and Configuration ..............................................................................

193

 

13.1.1

Standby function ..................................................................................................................

193

 

13.1.2

Standby function control register .........................................................................................

194

13.2

Standby Function Operations ..........................................................................................

195

 

13.2.1

HALT mode ..........................................................................................................................

195

 

13.2.2

STOP mode .........................................................................................................................

198

CHAPTER 14 RESET FUNCTION .....................................................................................................

201

14.1

Reset Function ..................................................................................................................

201

CHAPTER 15 μPD78P083 .................................................................................................................

205

15.1

Memory Size Switching Register .....................................................................................

206

15.2

PROM Programming .........................................................................................................

207

 

15.2.1

Operating modes .................................................................................................................

207

 

15.2.2

PROM write procedure ........................................................................................................

209

 

15.2.3

PROM reading procedure ....................................................................................................

213

15.3

Erasure Procedure (μPD78P083DU Only) .......................................................................

214

15.4

Opaque Film Masking the Window (μPD78P083DU Only).............................................

214

15.5

Screening of One-Time PROM Versions .........................................................................

214

CHAPTER 16 INSTRUCTION SET ....................................................................................................

215

16.1

Legends Used in Operation List ......................................................................................

216

 

16.1.1

Operand identifiers and description methods ......................................................................

216

 

16.1.2

Description of “operation” column ........................................................................................

217

 

16.1.3

Description of “flag operation” column .................................................................................

217

16.2

Operation List ....................................................................................................................

218

16.3

Instructions Listed by Addressing Type .........................................................................

226

APPENDIX A DEVELOPMENT TOOLS ............................................................................................

231

A.1

Language Processing Software ......................................................................................

233

A.2

PROM Programming Tools ..............................................................................................

234

 

A.2.1

Hardware .............................................................................................................................

234

 

A.2.2

Software ...............................................................................................................................

234

A.3

Debugging Tools ...............................................................................................................

235

 

A.3.1

Hardware .............................................................................................................................

235

 

A.3.2

Software (1/3) ......................................................................................................................

236

 

A.3.2

Software (2/3) ......................................................................................................................

237

 

A.3.2

Software (3/3) ......................................................................................................................

238

A.4 OS for IBM PC ...................................................................................................................

239

– iv –

A.5

System-Upgrade Method from Other In-Circuit Emulators to 78K/0 Series

 

 

In-Circuit Emulator ............................................................................................................

240

APPENDIX B EMBEDDED SOFTWARE ..........................................................................................

243

B.1

Real-time OS ......................................................................................................................

244

B.2

Fuzzy Inference Development Support System .............................................................

245

APPENDIX C REGISTER INDEX ......................................................................................................

247

C.1

Register Index .....................................................................................................................

247

APPENDIX D REVISION HISTORY ..................................................................................................

249

– v –

FIGURE (1/4)

Fig. No.

Title

Page

2-1

Pin Input/Output Circuit of List ............................................................................................

23

3-1

Memory Map (μPD78081) ..................................................................................................

25

3-2

Memory Map (μPD78082) ..................................................................................................

26

3-3

Memory Map (μPD78P083) ................................................................................................

27

3-4

Data Memory Addressing (μPD78081) ...............................................................................

30

3-5

Data Memory Addressing (μPD78082) ...............................................................................

31

3-6

Data Memory Addressing (μPD78P083) ............................................................................

32

3-7

Program Counter Configuration .........................................................................................

33

3-8

Program Status Word Configuration...................................................................................

33

3-9

Stack Pointer Configuration ................................................................................................

35

3-10

Data to be Saved to Stack Memory ....................................................................................

35

3-11

Data to be Reset from Stack Memory ................................................................................

35

3-12

General Register Configuration ..........................................................................................

36

4-1

Port Types ..........................................................................................................................

53

4-2

P00 Block Diagram .............................................................................................................

56

4-3

P01 to P03 Block Diagram .................................................................................................

56

4-4

P10 to P17 Block Diagram .................................................................................................

57

4-5

P30 to P37 Block Diagram .................................................................................................

58

4-6

P50 to P57 Block Diagram .................................................................................................

59

4-7

P70 Block Diagram .............................................................................................................

60

4-8

P71 and P72 Block Diagram ..............................................................................................

61

4-9

P100 to P101 Block Diagram .............................................................................................

62

4-10

Port Mode Register Format ................................................................................................

65

4-11

Pull-Up Resistor Option Register Format ...........................................................................

66

5-1

Block Diagram of Clock Generator .....................................................................................

70

5-2

Processor Clock Control Register Format ..........................................................................

71

5-3

Oscillation Mode Selection Register Format ......................................................................

72

5-4

Main System Clock Waveform due to Writing to OSMS .....................................................

 

5-5

External Circuit of Main System Clock Oscillator ...............................................................

73

5-6

Examples of Oscillator with Bad Connection (1/2) .............................................................

74

5-7

CPU Clock Switching .........................................................................................................

78

6-1

8-Bit Timer/Event Counters 5 and 6 Block Diagram ...........................................................

82

6-2

Block Diagram of 8-Bit Timer/Event Counters 5 and 6 Output Control Circuit ...................

83

6-3

Timer Clock Select Register 5 Format ................................................................................

85

6-4

Timer Clock Select Register 6 Format ................................................................................

86

6-5

8-Bit Timer Mode Control Register 5 Format ......................................................................

87

6-6

8-Bit Timer Mode Control Register 6 Format ......................................................................

88

6-7

Port Mode Register 10 Format ...........................................................................................

89

6-8

8-Bit Timer Mode Control Register Settings for Interval Timer Operation ..........................

90

6-9

Interval Timer Operation Timings .......................................................................................

91

– vi –

FIGURE (2/4)

Fig. No.

Title

Page

6-10

8-Bit Timer Mode Control Register Setting for External Event Counter Operation .............

93

6-11

External Event Counter Operation Timings (with Rising Edge Specification) ....................

93

6-12

8-Bit Timer Mode Control Register Settings for Square-Wave Output Operation ..............

94

6-13

8-Bit Timer Mode Control Register Settings for PWM Output Operation ...........................

96

6-14

PWM Output Operation Timing (Active high setting) ..........................................................

97

6-15

PWM Output Operation Timings (CRn0 = 00H, active high setting) ...................................

97

6-16

PWM Output Operation Timings (CRn0 = FFH, active high setting) ..................................

98

6-17

PWM Output Operation Timings (CRn0 changing, active high setting) ..............................

99

6-18

8-Bit Timer Registers 5 and 6 Start Timing .........................................................................

100

6-19

External Event Counter Operation Timing ..........................................................................

100

6-20

Timing after Compare Register Change during Timer Count Operation ............................

101

7-1

Watchdog Timer Block Diagram .........................................................................................

105

7-2

Timer Clock Select Register 2 Format ................................................................................

107

7-3

Watchdog Timer Mode Register Format .............................................................................

108

8-1

Remote Controlled Output Application Example ................................................................

111

8-2

Clock Output Control Circuit Block Diagram.......................................................................

112

8-3

Timer Clock Select Register 0 Format ................................................................................

113

8-4

Port Mode Register 3 Format .............................................................................................

114

9-1

Buzzer Output Control Circuit Block Diagram ....................................................................

115

9-2

Timer Clock Select Register 2 Format ................................................................................

117

9-3

Port Mode Register 3 Format .............................................................................................

118

10-1

A/D Converter Block Diagram ............................................................................................

120

10-2

A/D Converter Mode Register Format ................................................................................

123

10-3

A/D Converter Input Select Register Format ......................................................................

124

10-4

External Interrupt Mode Register 1 Format ........................................................................

125

10-5

A/D Converter Basic Operation ..........................................................................................

127

10-6

Relations between Analog Input Voltage and A/D Conversion Result ................................

128

10-7

A/D Conversion by Hardware Start ....................................................................................

129

10-8

A/D Conversion by Software Start ......................................................................................

130

10-9

Example of Method of Reducing Current Dissipation in Standby Mode .............................

131

10-10

Analog Input Pin Disposition ..............................................................................................

132

10-11

A/D Conversion End Interrupt Request Generation ...........................................................

 

10-12

Handling of AVDD Pin .........................................................................................................

133

11-1

Serial Interface Channel 2 Block Diagram .........................................................................

137

11-2

Baud Rate Generator Block Diagram .................................................................................

138

11-3

Serial Operating Mode Register 2 Format ..........................................................................

140

11-4

Asynchronous Serial Interface Mode Register Format .......................................................

141

11-5

Asynchronous Serial Interface Status Register Format .....................................................

143

11-6

Baud Rate Generator Control Register Format (1/2) .........................................................

144

– vii –

FIGURE (3/4)

Fig. No.

 

 

 

 

 

 

Title

Page

11-6

Baud Rate Generator Control Register Format (2/2) .........................................................

145

11-7

Asynchronous Serial Interface Transmit/Receive Data Format ..........................................

157

11-8

Asynchronous Serial Interface Transmission Completion Interrupt Request Timing ..........

159

11-9

Asynchronous Serial Interface Reception Completion Interrupt Request Timing ...............

160

11-10

Receive Error Timing ..........................................................................................................

161

11-11

State of the Receive Buffer Register (RXB) when Reception is Interrupted, and

 

 

Generation/Non Generation of an Interrupt Request (INTSR) ...........................................

162

11-12

3-Wire serial I/O Mode Timing ............................................................................................

168

11-13

Circuit of Switching in Transfer Bit Order ...........................................................................

169

12-1

Basic Configuration of Interrupt Function (1/2) ...................................................................

173

12-1

Basic Configuration of Interrupt Function (2/2) ...................................................................

174

12-2

Interrupt Request Flag Register Format .............................................................................

176

12-3

Interrupt Mask Flag Register Format ..................................................................................

177

12-4

Priority Specify Flag Register Format .................................................................................

178

12-5

External Interrupt Mode Register 0 Format ........................................................................

179

12-6

External Interrupt Mode Register 1 Format ........................................................................

179

12-7

Program Status Word Configuration ...................................................................................

180

12-8

Flowchart from Non-Maskable Interrupt Request Generation to Acknowledgment ............

182

12-9

Non-Maskable Interrupt Request Acknowledge Timing ......................................................

182

12-10

Non-Maskable Interrupt Request Acknowledge Operation ................................................

183

12-11

Interrupt Request Acknowledge Processing Algorithm .......................................................

185

12-12

Interrupt Request Acknowledge Timing (Minimum Time) ...................................................

186

12-13

Interrupt Request Acknowledge Timing (Maximum Time) ..................................................

186

12-14

Example of Multiple Interrupt (1/2) .....................................................................................

189

12-14

Example of Multiple Interrupt (2/2) .....................................................................................

190

12-15

Interrupt Request Hold .......................................................................................................

192

13-1

Oscillation Stabilization Time Select Register Format ........................................................

194

13-2

HALT Mode Clear upon Interrupt Generation .....................................................................

196

 

 

 

 

 

 

 

 

 

13-3

HALT Mode Release by

RESET

 

 

................................................................................Input

197

13-4

STOP Mode Release by Interrupt Generation ....................................................................

199

 

 

 

 

 

13-5

Release by STOP Mode RESET Input ...............................................................................

200

14-1

Block Diagram of Reset Function .......................................................................................

201

 

 

 

 

 

 

 

14-2

Timing of Reset Input by

RESET

 

...............................................................................Input

202

14-3

Timing of Reset due to Watchdog Timer Overflow .............................................................

202

 

 

 

 

 

14-4

Timing of Reset Input in STOP Mode by

RESET

......................................................Input

202

15-1

Memory Size Switching Register Format ...........................................................................

206

15-2

Page Program Mode Flowchart ..........................................................................................

209

15-3

Page Program Mode Timing ...............................................................................................

210

15-4

Byte Program Mode Flowchart ...........................................................................................

211

15-5

Byte Program Mode Timing ................................................................................................

212

– viii –

FIGURE (4/4)

Fig. No.

 

Title

Page

15-6

PROM Read Timing ...........................................................................................................

213

A-1

Development Tool Configuration ........................................................................................

232

A-2

EV-9200G-44

Drawing (For Reference Only) .....................................................................

241

A-3

EV-9200G-44

Footprint (For Reference Only) ....................................................................

242

– ix –

TABLE (1/2)

Table. No.

Title

Page

1-1

Differences between the μPD78081, 78082 and 78P083, the μPD78081(A), 78082(A)

 

 

and 78P083(A), and the μPD78081(A2) ............................................................................

13

2-1

Type of Input/Output Circuit of Each Pin ............................................................................

22

3-1

Vector Table ........................................................................................................................

28

3-2

Special-Function Register List (1/2) ..................................................................................

38

3-2

Special-Function Register List (2/2) ...................................................................................

39

4-1

Port Functions ....................................................................................................................

54

4-2

Port Configuration ..............................................................................................................

55

4-3

Port Mode Register and Output Latch Settings when Using Dual-Fucntions .....................

64

5-1

Clock Generator Configuration ...........................................................................................

69

5-2

Maximum Time Required for CPU Clock Switchover .........................................................

77

6-1

Timer/Event Counter Types and Functions ........................................................................

79

6-2

8-Bit Timer/Event Counters 5 and 6 Interval Times ............................................................

80

6-3

8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ...................................

81

6-4

8-Bit Timer/Event Counters 5 and 6 Configurations ...........................................................

82

6-5

8-Bit Timer/Event Counters 5 and 6 Interval Times ............................................................

92

6-6

8-Bit Timer/Event Counters 5 and 6 Square-Wave Output Ranges ...................................

95

7-1

Watchdog Timer Overrun Detection Times .........................................................................

103

7-2

Interval Times .....................................................................................................................

104

7-3

Watchdog Timer Configuration ...........................................................................................

105

7-4

Watchdog Timer Overrun Detection Time ..........................................................................

109

7-5

Interval Timer Interval Time ................................................................................................

110

8-1

Clock Output Control Circuit Configuration ........................................................................

112

9-1

Buzzer Output Control Circuit Configuration ......................................................................

115

10-1

A/D Converter Configuration ..............................................................................................

119

11-1

Serial Interface Channel 2 Configuration ...........................................................................

136

11-2

Serial Interface Channel 2 Operating Mode Settings .........................................................

142

11-3

Relation between Main System Clock and Baud Rate .......................................................

146

11-4

Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)

147

11-5

Relation between Main System Clock and Baud Rate .......................................................

155

11-6

Relation between ASCK Pin Input Frequency and Baud Rate (When BRGC is set to 00H)

156

11-7

Receive Error Causes ........................................................................................................

161

– x –

TABLE (2/2)

Table. No.

Title

Page

12-1

Interrupt Source List ...........................................................................................................

172

12-2

Various Flags Corresponding to Interrupt Request Sources ..............................................

175

12-3

Times from Maskable Interrupt Request Generation to Interrupt Service ..........................

184

12-4

Interrupt Request Enabled for Multiple Interrupt during Interrupt Servicing .......................

188

13-1

HALT Mode Operating Status .............................................................................................

195

13-2

Operation after HALT Mode Release .................................................................................

197

13-3

STOP Mode Operating Status ............................................................................................

198

13-4

Operation after STOP Mode Release .................................................................................

200

14-1

Hardware Status after Reset (1/2) ......................................................................................

203

14-1

Hardware Status after Reset (2/2) ......................................................................................

204

15-1

Differences between the μPD78P083 and Mask ROM Versions .......................................

205

15-2

Examples of Memory Size Switching Register Settings .....................................................

206

15-3

PROM Programming Operating Modes .............................................................................

207

16-1

Operand Identifiers and Description Methods ....................................................................

216

A-1

System-Up Method from Other In-Circuit Emulator to IE-78000-R ....................................

240

A-2

System-Up Method from Other In-Circuit Emulator to IE-78000-R-A .................................

240

– xi –

[MEMO]

– xii –

CHAPTER 1 OUTLINE

CHAPTER 1 OUTLINE

1.1 Features

On-chip ROM and RAM

Type

Program Memory

Data Memory

 

 

Part Number

(ROM)

(Internal High-Speed RAM)

 

 

 

 

μPD78081

8 Kbytes

256 bytes

μPD78082

16 Kbytes

384 bytes

μPD78P083

24 Kbytes (Note)

512 bytes (Note)

Note The capacities of internal PROM and internal high-speed RAM can be changed by means of the memory size switching register (IMS).

Instruction execution time changeable from high speed (0.4 μs: In main system clock 5.0 MHz operation) to low speed (12.8 μs: In main system clock 5.0 MHz operation)

Instruction set suited to system control

Bit manipulation possible in all address spaces

Multiply and divide instructions

33 I/O ports

8-bit resolution A/D converter: 8 channels Serial interface: 1 channel

• 3-wire serial I/O/UART mode: 1 channel Timer: 3 channels

8-bit timer/event counter : 2 channels

Watchdog timer : 1 channel

Vectored Interrupt Source : 13

Supply voltage: VDD = 1.8 to 5.5 V

1

CHAPTER 1 OUTLINE

1.2 Applications

μPD78081, 78082, 78P083:

Airbags, CRT displays, keyboards, air conditioners, hot water dispensers, boilers, fan heaters, dashboards, etc.

μPD78081(A), 78082(A), 78P083(A), 78081(A2):

Automobile electrical control devices, gas detector cutoff devices, various safety devices, etc.

1.3 Ordering Information

Part number

Package

Internal ROM

 

 

 

μPD78081CU-×××

42-pin plastic shrink DIP (600 mil)

Mask ROM

μPD78081GB-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Mask ROM

μPD78081GB-×××-3BS-MTX

44-pin plastic QFP (10 × 10 mm)

Mask ROM

μPD78082CU-×××

42-pin plastic shrink DIP (600 mil)

Mask ROM

μPD78082GB-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Mask ROM

μPD78082GB-×××-3BS-MTX

44-pin plastic QFP (10 × 10 mm)

Mask ROM

μPD78P083CU

42-pin plastic shrink DIP (600 mil)

One-Time PROM

μPD78P083DU

42-pin ceramic shrink DIP (with window) (600 mil)

EPROM

μPD78P083GB-3B4

44-pin plastic QFP (10 × 10 mm)

One-Time PROM

μPD78P083GB-3BS-MTX

44-pin plastic QFP (10 × 10 mm)

One-Time PROM

μPD78081GB(A)-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Mask ROM

μPD78082GB(A)-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Mask ROM

μPD78P083CU(A)

42-pin plastic shrink DIP (600 mil)

One-Time PROM

μPD78P083GB(A)-3B4

44-pin plastic QFP (10 × 10 mm)

One-Time PROM

μPD78P083GB(A)-3BS-MTXNote

44-pin plastic QFP (10 × 10 mm)

One-Time PROM

μPD78081GB(A2)-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Mask ROM

Note Under development

Remark ××× indicates ROM code suffix.

2

CHAPTER 1 OUTLINE

1.4 Quality Grade

Part number

Package

Quality grade

 

 

 

μPD78081CU-×××

42-pin plastic shrink DIP (600 mil)

Standard

μPD78081GB-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Standard

μPD78081GB-×××-3BS-MTX

44-pin plastic QFP (10 × 10 mm)

Standard

μPD78082CU-×××

42-pin plastic shrink DIP (600 mil)

Standard

μPD78082GB-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Standard

μPD78082GB-×××-3BS-MTX

44-pin plastic QFP (10 × 10 mm)

Standard

μPD78P083CU

42-pin plastic shrink DIP (600 mil)

Standard

μPD78P083DU

42-pin ceramic shrink DIP (with window) (600 mil)

Not applicable

μPD78P083GB-3B4

44-pin plastic QFP (10 × 10 mm)

Standard

μPD78P083GB-3BS-MTX

44-pin plastic QFP (10 × 10 mm)

Standard

μPD78081GB(A)-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Special

μPD78082GB(A)-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Special

μPD78P083CU(A)

42-pin plastic shrink DIP (600 mil)

Special

μPD78P083GB(A)-3B4

44-pin plastic QFP (10 × 10 mm)

Special

μPD78P083GB(A)-3BS-MTXNote

44-pin plastic QFP (10 × 10 mm)

Special

μPD78081GB(A)-×××-3B4

44-pin plastic QFP (10 × 10 mm)

Special

Note Under planning

Remark ××× indicates ROM code suffix.

Please refer to “Quality grade on NEC Semiconductor Devices” (Document number C11531E) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications.

3

CHAPTER 1 OUTLINE

1.5Pin Configuration (Top View)

(1)Normal operating mode

42-pin plastic shrink DIP (600 mil)

μPD78081CU-×××, 78082CU-×××, 78P083CU, 78P083CU(A)

42-pin ceramic shrink DIP (with window) (600 mil)

μPD78P083DU

P55

1

42

VSS

P56

2

41

P54

P57

3

40

P53

P30

4

39

P52

P31

5

38

P51

P32

6

37

P50

P33

7

36

P100/TI5/TO5

P34

8

35

P101/TI6/TO6

P35/PCL

9

34

P70/RXD/SI2

P36/BUZ

10

33

P71/TXD/SO2

P37

11

32

P72/ASCK/SCK2

P00

12

31

P17/ANI7

P01/INTP1

13

30

P16/ANI6

P02/INTP2

14

29

P15/ANI5

P03/INTP3

15

28

P14/ANI4

RESET

16

27

P13/ANI3

IC (VPP)

17

26

P12/ANI2

X2

18

25

P11/ANI1

X1

19

24

P10/ANI0

VDD

20

23

AVSS

AVDD

21

22

AVREF

Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly.

2.Connect AVDD pin to VDD.

3.Connect AVSS pin to VSS.

Remark Pin connection in parentheses is intended for the μPD78P083.

4

CHAPTER 1 OUTLINE

44-pin plastic QFP (10 × 10 mm)

μPD78081GB-×××-3B4, 78081GB-×××-3BS-MTX

μPD78082GB-×××-3B4, 78082GB-×××-3BS-MTX

μPD78P083GB-3B4, 78P083GB-3BS-MTX

μPD78081GB(A)-×××-3B4, 78082GB(A)-×××-3B4 μPD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTXNote

μPD78P081GB(A2)-×××-3B4

 

P11/ANI1

P10/ANI0

AVSS

AVREF

AVDD

VDD

X1

X2

IC (VPP)

RESET

NC

 

P12/ANI2

44 43 42 41 40 39 38 37 36 35 34

P03/INTP3

1

 

 

 

 

 

 

 

 

 

33

P13/ANI3

2

 

 

 

 

 

 

 

 

 

32

P02/INTP2

P14/ANI4

3

 

 

 

 

 

 

 

 

 

31

P01/INTP1

P15/ANI5

4

 

 

 

 

 

 

 

 

 

30

P00

P16/ANI6

5

 

 

 

 

 

 

 

 

 

29

P37

P17/ANI7

6

 

 

 

 

 

 

 

 

 

28

P36/BUZ

P72/ASCK/SCK2

7

 

 

 

 

 

 

 

 

 

27

P35/PCL

P71/TxD/SO2

8

 

 

 

 

 

 

 

 

 

26

P34

P70/RxD/SI2

9

 

 

 

 

 

 

 

 

 

25

P33

P101/TI6/TO6

10

 

 

 

 

 

 

 

 

 

24

P32

P100/TI5/TO6

11

 

 

 

 

 

 

 

 

 

23

NC

 

12 13 14 15 16 17 18 19 20 21 22

 

 

P50

P51

P52

P53

P54

VSS

P55

P56

P57

P30

P31

 

Note Under development

Cautions 1. Be sure to connect IC (Internally Connected) pin to VSS directly.

2.Connect AVDD pin to VDD.

3.Connect AVSS pin to VSS.

4.Connect NC pin to VSS for noise protection (It can be left open).

Remark Pin connection in parenthesis is intended for the μPD78P083.

5

CHAPTER 1 OUTLINE

Pin Identifications

ANI0 to ANI7

:

Analog Input

P100, P101

:

Port 10

ASCK

:

Asynchronous Serial Clock

PCL

:

Programmable Clock

 

 

 

 

 

 

 

 

AVDD

:

Analog Power Supply

RESET

:

Reset

AVREF

:

Analog Reference Voltage

RxD

:

Receive Data

 

 

 

 

 

 

 

AVSS

:

Analog Ground

SCK2

:

Serial Clock

BUZ

:

Buzzer Clock

SI2

:

Serial Input

IC

:

Internally Connected

SO2

:

Serial Output

INTP1 to INTP3

:

Interrupt from Peripherals

TI5, TI6

:

Timer Input

NC

:

Non-connection

TO5 to TO6

:

Timer Output

P00 to P03

:

Port 0

TxD

:

Transmit Data

P10 to P17

:

Port 1

VDD

:

Power Supply

P30 to P37

:

Port 3

VPP

:

Programming Power Supply

P50 to P57

:

Port 5

VSS

:

Ground

P70 to P72

:

Port 7

X1, X2

:

Crystal (Main System Clock)

6

CHAPTER 1 OUTLINE

(2) PROM programming mode

42-pin plastic shrink DIP (600 mil)

μPD78P083CU, 78P083CU(A)

42-pin ceramic shrink DIP (with window) (600 mil)

μPD78P083DU

A5

1

42

VSS

A6

2

41

A4

A7

3

40

A3

OE

4

39

A2

CE

5

38

A1

PGM

6

37

A0

A8

7

36

A10

 

8

35

A11

(L)

9

34

A12

10

33

A13

 

 

11

32

A14

A9

12

31

D7

 

13

30

D6

(L)

14

29

D5

 

15

28

D4

RESET

16

27

D3

VPP

17

26

D2

Open

18

25

D1

(L)

19

24

D0

VDD

20

23

VSS

VDD

21

22

VSS

Cautions 1. (L) : Individually connect to VSS via a pull-down resistor.

2.VSS : Connect to the ground.

3.RESET : Set to the low level.

4.Open : Do not connect anything.

7

CHAPTER 1 OUTLINE

44-pin plastic QFP (10 × 10 mm)

μPD78P083GB-3B4, 78P083GB-3BS-MTX μPD78P083GB(A)-3B4, 78P083GB(A)-3BS-MTXNote

 

D1

D0 VSS VSS VDD VDD (L)

Open

VPP

RESET

(L)

 

D2

44 43 42 41 40 39 38 37 36 35 34

 

1

 

 

 

 

33

 

D3

2

 

 

 

 

32

(L)

D4

3

 

 

 

 

31

 

D5

4

 

 

 

 

30

A9

D6

5

 

 

 

 

29

 

D7

6

 

 

 

 

28

(L)

A14

7

 

 

 

 

27

 

 

 

 

 

A13

8

 

 

 

 

26

 

A12

9

 

 

 

 

25

A8

A11

10

 

 

 

 

24

PGM

A10

11

 

 

 

 

23

(L)

 

12 13 14 15 16 17 18 19 20 21 22

 

 

A0

A1 A2 A3 A4 VSS A5

A6

A7

OE

CE

 

Note Under development

Cautions 1. (L) : Connect individually to VSS via a pull-down resistor.

2.

 

VSS

:

Connect to the ground.

3.

 

RESET

:

Set to the low level.

4.

Open

:

Do not connect anything.

A0 to A14

:

Address Bus

RESET

: Reset

 

 

:

Chip Enable

VDD

: Power Supply

CE

D0 to D7

:

Data Bus

VPP

: Programming Power Supply

 

 

:

Output Enable

VSS

: Ground

OE

 

 

:

Program

 

 

PGM

 

 

 

8

CHAPTER 1 OUTLINE

1.6 78K/0 Series Development

The following shows the 78K/0 Series products development. Subseries names are shown inside frames.

78K/0 series

 

Control

 

 

 

100-pin

µPD78075B

µPD78075BY

100-pin

µPD78078

µPD78078Y

100-pin

µPD78070A

µPD78070AY

100-pin

µPD780018

Note

µPD780018Y

Note

80-pin

 

 

µPD780058

µPD780058Y

Note

80-pin

 

µPD78058F

µPD78058FY

80-pin

µPD78054

µPD78054Y

64-pin

µPD780034

µPD780034Y

64-pin

µPD780024

µPD780024Y

64-pin

µPD78014H

 

 

64-pin

 

 

µPD78018F

µPD78018FY

64-pin

µPD78014

µPD78014Y

64-pin

µPD780001

 

 

64-pin

 

 

µPD78002

µPD78002Y

 

42/44-pin

µPD78083

 

 

Inverter control

64-pin

µPD780964

64-pin

µPD780924

 

 

FIP® driving

100-pin

µPD780208

100-pin

µPD780228

80-pin

µPD78044H

80-pin

µPD78044F

 

LCD driving

 

100-pin

µPD780308

µPD780308Y

100-pin

µPD78064B

 

100-pin

µPD78064

µPD78064Y

Mass-produced products

Products under development

Y Subseries supports the I2C bus specifications.

Low EMI noise version of the µPD78078

Timer is added to the µPD78054 and its external interface is enhanced. ROM-less versions of the µPD78078

Serial I/O of the µPD78078 is enhanced and only selected functions are provided.

Serial I/O-enhanced versions of the µPD78054; Low EMI noise version Low EMI noise version of the µPD78054

UART and D/A converter are added to the µPD78014 and I/O is enhanced. A/D-enhanced version of the µPD780024

Serial I/O-enhanced versions of the µPD78018F; Low EMI noise version

Low EMI noise version of the µPD78018F

Low-voltage (1.8 V) operation versions of the µPD78014 with several ROM and RAM capacities available. A/D converter and 16-bit timer are added to the µPD78002.

A/D converter is added to the µPD78002.

Basic subseries for control applications

On-chip UART, and operable at low voltage (1.8 V).

A/D-enhanced version of the µPD780924

On-chip inverter control circuit and UART incorporated; Low EMI noise version

I/O and FIP C/D of the µPD78044F are enhanced. Total display outputs : 53 pins

I/O and FIP C/D of the µPD78044H are enhanced. Total display outputs : 48 pins N-ch open-drain I/O is added to the µPD78044F. Total display outputs : 34 pins

Basic subseries for FIP driving. Total display outputs: 34 pins

SIO of the µPD78064 is enhanced, and ROM and RAM are expanded. Low EMI noise version of the µPD78064

Basic subseries for driving LCDs and with on-chip UART.

 

IEBusTM supported

 

80-pin

µPD78098

IEBus controller is added to the µPD78054.

 

LV

 

64-pin

µPD78P0914

PWM output, LV digital code decoder and Hsync counter are incorporated.

Note Under planning

9

CHAPTER 1 OUTLINE

The following table shows the differences among subseries functions.

 

Function

ROM

 

Timer

 

8-bit

10-bit

8-bit

Serial interface

I/O

VDD

External

Subseries name

capacity

8-bit

16-bit Watch WDT

A/D

A/D

D/A

MIN.

expansion

 

 

value

 

 

 

 

 

 

 

 

 

 

 

 

 

Control

μPD78075B

32K to 40K

4 ch

1 ch

1 ch

1 ch

8 ch

2 ch

3 ch (UART: 1 ch)

88

1.8

V

Available

 

μPD78078

48K to 60K

 

 

 

 

 

 

 

 

 

 

 

 

 

μPD78070A

 

 

 

 

 

 

 

 

61

2.7

V

 

 

μPD780018

48K to 60K

 

 

 

 

 

 

2 ch (Time division

88

 

 

 

 

 

 

 

 

 

 

 

 

 

3-wire: 1 ch)

 

 

 

 

 

μPD780058

24K to 60K

2 ch

 

 

 

 

 

2 ch

3 ch (Time division

68

1.8

V

 

 

 

 

 

 

 

 

 

 

 

UART: 1 ch)

 

 

 

 

 

μPD78058F

48K to 60K

 

 

 

 

 

 

 

3 ch (UART: 1 ch)

69

2.7

V

 

 

μPD78054

16K to 60K

 

 

 

 

 

 

 

 

 

2.0

V

 

 

μPD780034

8K to 32K

 

 

 

 

8 ch

3 ch (UART: 1 ch, Time

51

1.8

V

 

 

μPD780024

 

 

 

 

 

8 ch

 

division 3-wire: 1 ch)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

μPD78014H

 

 

 

 

 

 

 

 

2 ch

53

 

 

 

 

μPD78018F

8K to 60K

 

 

 

 

 

 

 

 

 

 

 

 

 

μPD78014

8K to 32K

 

 

 

 

 

 

 

 

 

2.7

V

 

 

μPD780001

8K

 

 

 

 

 

1 ch

39

 

 

 

μPD78002

8K to 16K

 

 

1 ch

 

 

 

 

53

 

 

Available

 

μPD78083

 

 

 

 

8 ch

 

 

1 ch (UART: 1 ch)

33

1.8

V

Inverter

μPD780964

8K to 32K

3 ch

Note

1 ch

8 ch

2 ch (UART: 2 ch)

47

2.7

V

Available

control

μPD780924

 

 

 

 

 

8 ch

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FIP driving

μPD780208

32K to 60K

2 ch

1 ch

1 ch

1 ch

8 ch

2 ch

74

2.7

V

 

μPD780228

48K to 60K

3 ch

 

 

 

 

1 ch

72

4.5

V

 

 

μPD78044H

32K to 48K

2 ch

1 ch

1 ch

 

 

 

 

 

68

2.7

V

 

 

μPD78044F

16K to 40K

 

 

 

 

 

 

 

2 ch

 

 

 

 

LCD

μPD780308

48K to 60K

2 ch

1 ch

1 ch

1 ch

8 ch

3 ch (Time division

57

2.0

V

driving

 

 

 

 

 

 

 

 

 

UART: 1 ch)

 

 

 

 

 

μPD78064B

32K

 

 

 

 

 

 

 

2 ch (UART: 1 ch)

 

 

 

 

 

μPD78064

16K to 32K

 

 

 

 

 

 

 

 

 

 

 

 

IEBus

μPD78098

32K to 60K

2 ch

1 ch

1 ch

1 ch

8 ch

2 ch

3 ch (UART: 1 ch)

69

2.7

V

Available

supported

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LV

μPD78P0914

32K

6 ch

1 ch

8 ch

2 ch

54

4.5

V

Available

Note 10 bits timer: 1 channel

10

CHAPTER 1 OUTLINE

1.7 Block Diagram

P100/TI5/TO5

8-bit TIMER/

 

 

PORT 0

EVENT COUNTER 5

 

 

 

 

 

 

P101/TI6/TO6

8-bit TIMER/

 

 

PORT 1

EVENT COUNTER 6

 

 

 

 

 

 

WATCHDOG

78K/0

 

 

 

CPU

ROM

 

 

TIMER

PORT 3

 

 

CORE

 

 

 

 

 

SI2/RXD/P70

SERIAL

 

 

 

SO2/TXD/P71

 

 

 

INTERFACE 2

 

 

 

SCK2/ASCK/P72

 

 

PORT 5

 

 

 

ANI0/P10-

 

 

 

 

 

 

 

 

 

 

 

 

 

ANI7/P17

A/D

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AVDD

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PORT 7

 

 

 

CONVERTER

 

 

 

 

 

 

 

 

 

 

 

AVSS

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

AVREF

 

 

 

 

 

 

 

 

RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTP1/P01-

 

 

 

 

 

 

 

 

 

 

PORT 10

 

 

 

 

 

 

 

 

 

 

INTERRUPT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

INTP3/P03

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

BUZ/P36

 

BUZZER OUTPUT

 

 

 

 

 

 

 

 

 

 

 

SYSTEM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PCL/P35

 

 

 

CLOCK OUTPUT

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CONTROL

 

 

 

VDD

VSS

IC

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(VPP)

 

 

 

Remarks 1. The internal ROM and high-speed RAM capacities depend on the product.

2. Pin connection in parentheses is intended for the μPD78P083.

P00 P01-P03

P10-P17

P30-P37

P50-P57

P70-P72

P100, P101

RESET

X1

X2

11

CHAPTER 1 OUTLINE

1.8 Outline of Function

 

 

Part Number

 

 

μPD78081

 

μPD78082

μPD78083

Item

 

 

 

 

 

 

 

 

Internal memory

ROM

Mask ROM

 

 

PROM

 

 

 

8 Kbytes

 

16 Kbytes

24 KbytesNote

 

 

High-speed RAM

256 bytes

 

384 bytes

512 bytesNote

Memory space

 

64 Kbytes

 

 

 

General register

 

8 bits × 32 registers (8 bits × 8 registers × 4 banks)

 

Instruction cycle

 

Instruction execution time variable function is integrated.

 

 

 

0.4 μs/0.8 μs/1.6 μs/3.2 μs/6.4 μs/12.8 μs (@5.0-MHz operation with main system clock)

Instruction set

 

• 16-bit operation

 

 

 

 

 

 

Multiply/divide (8 bits × 8 bits, 16 bits ÷ 8 bits)

 

 

 

 

Bit manipulation (set, reset, test, Boolean operation)

 

 

 

 

• BCD adjust, etc.

 

 

 

I/O ports

 

 

Total

:

33

 

 

 

 

 

CMOS input

:

1

 

 

 

 

 

CMOS input/output

:

32

 

A/D converter

 

 

8-bit resolution × 8 channels

 

Serial interface

 

• 3-wire serial I/O/UART mode selectable: 1 channel

 

Timer

 

 

8-bit timer/event counter:

2 channels

 

 

 

 

• Watchdog timer: 1 channel

 

Timer output

 

 

2 pins (8-bit PWM output enable)

 

Clock output

 

 

19.5 kHz, 39.1 kHz, 78.1 kHz, 156 kHz, 313 kHz, 625 kHz, 1.25 MHz, 2.5 MHz,

 

 

 

and 5.0 MHz (@ 5.0-MHz operation with main system clock)

Buzzer output

 

1.2 kHz, 2.4 kHz, 4.9 kHz, and 9.8 kHz

 

 

 

 

(@ 5.0-MHz operation with main system clock)

 

Vectored

Maskable

Internal : 8 external : 3

 

 

 

interrupt

Non-maskable

Internal : 1

 

 

 

source

Software

1

 

 

 

 

 

Supply voltage

 

VDD = 1.8 to 5.5 V

 

 

 

Operating ambient temperature

TA = –40 to +85°C

 

 

 

Package

 

 

• 42-pin plastic shrink DIP (600 mil)

 

 

 

 

• 44-pin plastic QFP (10 × 10 mm)

 

 

 

 

• 42-pin ceramic shrink DIP (with window) (600 mil) (μPD78P083 only)

Note Internal PROM and high-speed RAM capacities can be changed by setting the internal memory size

switching register (IMS).

12

CHAPTER 1 OUTLINE

1.9Differences between the μPD78081, 78082 and 78P083, the μPD78081(A), 78082(A) and 78P083(A), and the μPD78081(A2)

Table 1-1 Differences between the μPD78081, 78082 and 78P083, the μPD78081(A), 78082(A) and 78P083(A), and the μPD78081(A2)

Part Number

μPD78081

μPD78081(A)

μPD78081(A2)

 

μPD78082

μPD78082(A)

 

Item

μPD78P083

μPD78P083(A)

 

 

 

 

 

Quality grade

Standard

Special

 

 

 

 

 

Supply voltage

VDD = 1.8 to 5.5 V

 

VDD = 4.5 to 5.5 V

 

 

 

 

Operating ambient temperature

TA = –40 to +85°C

 

TA = –40 to +125°C

 

 

 

Electrical specifications

Please refer to the individual data sheets.

 

 

 

 

 

13

CHAPTER 1 OUTLINE

[MEMO]

14

CHAPTER 2 PIN FUNCTION

CHAPTER 2 PIN FUNCTION

2.1 Pin Function List

2.1.1Normal operating mode pins

(1)Port pins

Pin Name

Input/Output

 

 

Function

After Reset

Alternate Function

 

 

 

 

 

 

 

 

 

 

P00

Input

Port 0

 

 

Input only

Input

 

 

 

 

 

 

 

 

 

 

P01

Input/output

4-bit input/output port

 

Input/output is specifiable

Input

INTP1

 

 

 

 

 

 

 

 

 

 

P02

 

 

 

 

bit-wise. When used as the

 

INTP2

P03

 

 

 

 

input port, it is possible to

 

INTP3

 

 

 

 

 

connect a pull-up resistor by

 

 

 

 

 

 

 

 

 

software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P10-P17

Input/output

Port 1

 

 

 

Input

ANI0-ANI7

 

 

8-bit input/output port

 

 

 

 

 

 

 

 

Input/output is specifiable bit-wise.

 

 

 

 

 

 

When used

as the input port, it is possible to connect

 

 

 

 

 

 

a pull-up resistor by software. Note

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P30-P34

Input/output

Port 3

 

 

 

Input

 

 

 

 

 

 

 

 

 

 

P35

 

8-bit input/output port

 

 

 

PCL

 

 

 

 

 

 

 

P36

 

Input/output is specifiable bit-wise.

 

BUZ

 

 

 

 

 

 

 

 

P37

 

When used

as the input port, it is possible to connect

 

 

 

 

a pull-up resistor by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P50-P57

Input/output

Port 5

 

 

 

Input

 

 

 

8-bit input/output port

 

 

 

 

 

 

 

 

A maximum of 7 out of 8 ports can drive LEDs directly.

 

 

 

 

 

 

Input/output is specifiable bit-wise.

 

 

 

 

 

 

When used

as the input port, it is possible to connect

 

 

 

 

 

 

a pull-up resistor by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P70

Input/output

Port 7

 

 

 

Input

SI2/RxD

 

 

 

 

 

 

 

 

 

P71

 

3-bit input/output port

 

 

 

SO2/TxD

 

 

 

 

 

 

 

P72

 

Input/output is specifiable bit-wise.

 

 

 

 

 

 

SCK2/ASCK

 

 

When used

as the input port, it is possible to connect

 

 

 

 

 

 

a pull-up resistor by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P100

Input/output

Port 10

 

 

 

Input

TI5/TO5

 

 

 

 

 

 

 

 

 

P101

 

2-bit input/output port

 

 

 

TI6/TO6

 

 

Input/output is specifiable bit-wise.

 

 

 

 

 

 

When used

as the input port, it is possible to connect

 

 

 

 

 

 

a pull-up resistor by software.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Note When P10/ANI0-P17/ANI7 pins are used as the analog inputs for the A/D converter, set the port 1 to

the input mode. The on-chip pull-up resistor is automatically disabled.

15

CHAPTER 2 PIN FUNCTION

(2) Pins other than port pins

 

 

Pin Name

Input/Output

Function

After Reset

Alternate Function

 

 

 

 

 

 

 

 

 

 

 

 

INTP1

Input

External interrupt request input by which the active edge

Input

P01

 

INTP2

 

(rising edge, falling edge, or both rising and falling edges)

 

P02

 

INTP3

 

can be specified.

 

P03

 

 

 

 

 

 

 

 

 

 

 

 

SI2

Input

Serial interface serial data input.

Input

P70/RxD

 

SO2

Output

Serial interface serial data output.

Input

P71/TxD

 

 

 

 

 

 

 

 

 

 

 

 

 

Input/output

Serial interface serial clock input/output.

Input

P72/ASCK

 

 

SCK2

 

 

 

 

 

 

 

 

 

 

 

 

 

RxD

Input

Asynchronous serial interface serial data input.

Input

P70/SI2

 

 

 

 

 

 

 

 

 

 

 

 

TxD

Output

Asynchronous serial interface serial data output.

Input

P71/SO2

 

 

 

 

 

 

 

 

 

 

 

 

ASCK

Input

Asynchronous serial interface serial clock input.

Input

 

 

 

 

P72/SCK2

 

 

 

 

 

 

 

 

 

 

 

 

 

TI5

Input

External count clock input to 8-bit timer (TM5).

Input

P100/TO5

 

 

 

 

 

 

 

 

 

 

 

TI6

 

External count clock input to 8-bit timer (TM6).

 

P101/TO6

 

 

 

 

 

 

 

 

 

 

 

 

TO5

Output

8-bit timer output. (also used for 8-bit PWM output)

Input

P100/TI5

 

TO6

 

 

 

P101/TI6

 

 

 

 

 

 

 

 

 

 

 

 

PCL

Output

Clock output. (for main system clock trimming)

Input

P35

 

 

 

 

 

 

 

 

 

 

 

BUZ

Output

Buzzer output.

Input

P36

 

 

 

 

 

 

 

 

 

 

 

ANI0-ANI7

Input

A/D converter analog input.

Input

P10-P17

 

 

 

 

 

 

 

 

 

AVREF

Input

A/D converter reference voltage input.

 

 

 

 

 

 

 

 

 

 

 

 

AVDD

A/D converter analog power supply. Connected to VDD.

 

 

 

 

 

 

 

 

 

 

 

 

AVSS

A/D converter ground potential. Connected to VSS.

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

Input

System reset input.

 

 

 

 

 

 

 

 

 

 

 

 

X1

Input

Main system clock oscillation crystal connection.

 

 

 

 

 

 

 

 

 

 

 

 

X2

 

 

 

 

 

 

 

 

 

 

 

 

 

VDD

Positive power supply.

 

 

 

 

 

 

 

 

 

 

 

 

VPP

High-voltage applied during program write/verification.

 

 

 

 

 

 

 

Connected directly to VSS in normal operating mode.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

VSS

Ground potential.

 

 

 

 

 

 

 

 

 

 

 

 

IC

Internal connection. Connect directly to VSS.

 

 

 

 

 

 

 

 

 

NC

Does not internally connected. Connect to VSS.

 

 

 

 

 

 

 

(It can be left open)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

2.1.2 PROM programming mode pins (μPD78P083 only)

 

 

Pin Name

Input/Output

 

 

Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET

Input

 

PROM programming mode setting.

 

 

 

 

 

 

 

 

 

When +5 V or +12.5 V is applied to the VPP pin or a low level voltage is applied to the

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

RESET pin, the PROM programming mode is set.

 

 

 

 

 

 

 

 

 

 

 

VPP

Input

 

High-voltage application for PROM programming mode setting and program write/verify.

 

 

 

 

 

 

 

 

 

 

 

A0 to A14

Input

 

Address bus

 

 

 

 

 

 

 

 

 

 

 

D0 to D7

Input/output

 

Data bus

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

CE

Input

 

PROM enable input/program pulse input

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Input

 

Read strobe input to PROM

 

 

OE

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

PGM

Input

 

Program/program inhibit input in PROM programming mode

 

 

 

 

 

 

 

 

 

 

 

VDD

 

Positive power supply

 

 

 

 

 

 

 

 

 

 

 

VSS

 

Ground potential

 

 

 

 

 

 

 

 

 

 

 

16

CHAPTER 2 PIN FUNCTION

2.2 Description of Pin Functions

2.2.1 P00 to P03 (Port 0)

These are 4-bit input/output ports. Besides serving as input/output ports, they function as an external interrupt

request input.

The following operating modes can be specified bit-wise.

(1)Port mode

P00 functions as input-only port and P01 to P03 function as input/output ports.

P01 to P03 can be specified for input or output ports bit-wise with a port mode register 0 (PM0). When they are used as input ports, on-chip pull-up resistors can be used to them by defining the pull-up resistor option register L (PUOL).

(2)Control mode

INTP1 to INTP3 function as external interrupt request input pins which are capable of specifying the valid edges (rising edge, falling edge, and both rising and falling edges).

2.2.2P10 to P17 (Port 1)

These are 8-bit input/output ports. Besides serving as input/output ports, they function as an A/D converter analog

input.

The following operating modes can be specified bit-wise.

(1)Port mode

These ports function as 8-bit input/output ports.

They can be specified bit-wise as input or output ports with a port mode register 1 (PM1). If used as input ports, on-chip pull-up resistors can be used to these ports by defining the pull-up resistor option register L (PUOL).

(2)Control mode

These ports function as A/D converter analog input pins (ANI0-ANI7). The on-chip pull-up resistor is automatically disabled when the pins specified for analog input.

17

CHAPTER 2 PIN FUNCTION

2.2.3 P30 to P37 (Port 3)

These are 8-bit input/output ports. Beside serving as input/output ports, they function as clock output and buzzer

output.

The following operating modes can be specified bit-wise.

(1)Port mode

These ports function as 8-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 3 (PM3). When they are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register L (PUOL).

(2)Control mode

These ports function as clock output, and buzzer output.

(a)PCL

Clock output pin.

(b)BUZ

Buzzer output pin.

2.2.4P50 to P57 (Port 5)

These are 8-bit input/output ports. They can be specified bit-wise as input/output ports with port mode register 5 (PM5). When they are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register L (PUOL). A maximum of 7 out of 8 ports can drive LEDs directly.

18

CHAPTER 2 PIN FUNCTION

2.2.5 P70 to P72 (Port 7)

This is a 3-bit input/output port. In addition to its use as an input/output port, it also has serial interface data input/

output and clock input/output functions.

The following operating modes can be specified bit-wise.

(1)Port mode

Port 7 functions as a 3-bit input/output port. Bit-wise specification as an input port or output port is possible by means of port mode register 7 (PM7). When used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register L (PUOL).

(2)Control mode

Port 7 functions as serial interface data input/output and clock input/output.

(a)SI2, SO2

Serial interface serial data input/output pins

(b)SCK2

Serial interface serial clock input/output pin.

(c)RxD, TxD

Asynchronous serial interface serial data input/output pins.

(d)ASCK

Asynchronous serial interface serial clock input pin.

Caution When this port is used as a serial interface, the I/O and output latches must be set according to the function the user requires.

For the setting, see the operation mode setting list in Table 11-2 “Serial Interface Channel 2 Operating Mode Settings”

2.2.6 P100 to P101 (Port 10)

These are 2-bit input/output ports. Besides serving as input/output ports, they function as timer input/output.

The following operating modes can be specified bit-wise.

(1)Port mode

These ports function as 2-bit input/output ports. They can be specified bit-wise as input or output ports with port mode register 10 (PM10). When they are used as input ports, on-chip pull-up resistors can be used by defining the pull-up resistor option register H (PUOH).

(2)Control mode

These ports function as timer input/output.

(a)TI5, TI6

Pin for external clock input to the 8-bit timer/event counter 5 and 6.

(b)TO5, TO6

Timer output pins.

19

CHAPTER 2 PIN FUNCTION

2.2.7 AVREF

A/D converter reference voltage input pin.

When A/D converter is not used, connect this pin to VSS.

2.2.8 AVDD

Analog power supply pin of A/D converter. Always use the same voltage as that of the V DD pin even when A/D converter is not used.

2.2.9 AVSS

This is a ground voltage pin of A/D converter. Always use the same voltage as that of the VSS pin even when A/ D converter is not used.

2.2.10 RESET

This is a low-level active system reset input pin.

2.2.11 X1 and X2

Crystal resonator connect pins for main system clock oscillation. For external clock supply, input it to X1 and its inverted signal to X2.

2.2.12 VDD

Positive power supply pin

2.2.13 VSS

Ground potential pin

2.2.14 VPP (μPD78P083 only)

High-voltage apply pin for PROM programming mode setting and program write/verify. Connect directly to VSS in normal operating mode.

20

CHAPTER 2 PIN FUNCTION

2.2.15 IC (Mask ROM version only)

The IC (Internally Connected) pin is provided to set the test mode to check the μPD78083 Subseries at delivery. Connect it directly to the VSS with the shortest possible wire in the normal operating mode.

When a voltage difference is produced between the IC pin and VSS pin because the wiring between those two pins is too long or an external noise is input to the IC pin, the user's program may not run normally.

Connect IC pins to VSS pins directly.

VSS IC

As short as possible

2.2.16 NC (44-pin plastic QFP versions only)

Not internally connected. Please connect to Vss (open is also possible)

21

CHAPTER 2 PIN FUNCTION

2.3Pin Input/Output Circuits and Recommended Connection of Unused Pins

Types of input/output circuits of the pins and recommeded connection of unused pins are shown in Table 2-1.

For the configuration of each type of input/output circuit, see Figure 2-1.

Table 2-1. Type of Input/Output Circuit of Each Pin

 

 

 

Pin Name

Input/Output

Input/Output

Recommended Connection for Unused Pins

 

 

 

 

 

Circuit Type

 

 

 

 

 

 

 

 

 

 

 

P00

2

Input

Connect to VSS.

 

 

 

 

 

 

 

 

P01/INTP1

8-A

Input/Output

Independently connect to VSS via a resistor.

 

 

 

 

 

 

 

 

P02/INTP2

 

 

 

 

 

 

 

 

 

 

 

P03/INTP3

 

 

 

 

 

 

 

 

 

 

 

P10/ANI0-P17/ANI7

11

Input/Output

Independently connect to VDD or VSS via

 

 

 

 

 

 

 

 

P30-P32

5-A

 

a resistor.

 

 

 

 

 

 

 

 

P33, P34

8-A

 

 

 

 

 

 

 

 

 

 

P35/PCL

5-A

 

 

 

 

 

 

 

 

 

 

P36/BUZ

 

 

 

 

 

 

 

 

 

 

 

P37

 

 

 

 

 

 

 

 

 

 

 

P50-P57

5-A

 

 

 

 

 

 

 

 

 

 

P70/SI2/RxD

8-A

 

 

 

 

 

 

 

 

 

 

P71/SO2/TxD

5-A

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

P72/SCK2/ASCK

8-A

 

 

 

 

 

 

 

 

 

 

P100/TI5/TO5

8-A

 

 

 

 

 

 

 

 

 

 

P101/TI6/TO6

 

 

 

 

 

 

 

 

 

 

 

 

RESET

2

Input

 

 

 

 

 

 

 

 

AVREF

Connect to VSS.

 

 

 

 

 

 

 

 

AVDD

 

 

Connect to VDD.

 

 

 

 

 

 

 

 

AVSS

 

 

Connect to VSS.

 

 

 

 

 

 

 

 

VPP (μPD78P083)

 

 

Connect directly to VSS.

 

 

 

 

 

 

 

 

NC (44-pin plastic QFP

 

 

Connect to VSS (can also leave open)

 

version)

 

 

 

 

 

 

 

 

 

 

 

 

IC (Mask ROM version)

 

 

Connect directly to VSS.

 

 

 

 

 

 

 

 

22

CHAPTER 2 PIN FUNCTION

Figure 2-1. Pin Input/Output Circuit of List

Type 2

 

 

Type 8-A

VDD

 

 

 

 

 

 

 

pull-up

P-ch

 

 

 

enable

 

 

 

 

IN

 

 

 

VDD

 

 

 

 

 

 

 

data

P-ch

 

 

 

 

 

Schmitt-Triggered Input with

 

 

IN/OUT

 

 

 

 

 

Hysteresis Characteristics

 

output

N-ch

 

 

 

disable

 

 

 

 

Type 5-A

 

 

Type 11

VDD

 

VDD

 

 

 

 

 

 

 

 

 

pull-up

P-ch

pull-up

 

 

enable

P-ch

 

VDD

enable

 

 

 

 

data

 

 

 

 

P-ch

 

VDD

 

 

 

 

 

IN/OUT

data

 

 

 

P-ch

 

output

N-ch

 

 

 

 

IN/OUT

disable

P-ch

 

 

 

 

 

comparator

output

 

 

N-ch

 

 

+

disable

 

 

 

 

 

 

 

N-ch

 

 

 

 

VREF (Threshold voltage)

input

 

 

input

 

enable

 

 

 

 

 

enable

 

 

 

 

 

23

CHAPTER 2 PIN FUNCTION

[MEMO]

24

CHAPTER 3 CPU ARCHITECTURE

CHAPTER 3 CPU ARCHITECTURE

3.1 Memory Spaces

Figures 3-1 to 3-3 shows memory maps.

Figure 3-1. Memory Map (μPD78081)

 

 

 

 

 

FFFFH

 

Special Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Registers (SFRs)

 

 

 

 

 

 

 

 

 

FF00H

256 × 8 bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FEFFH

General Registers

 

 

 

 

 

 

 

 

 

 

FEE0H

32 × 8 bits

 

 

 

 

 

 

 

 

 

 

FEDFH

Internal High-speed RAM

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1FFFH

 

 

 

 

 

 

 

 

256 × 8 bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program Area

 

 

 

 

 

 

 

 

 

 

1 0 0 0 H

 

 

 

 

 

 

FE00H

 

 

 

0FFFH

 

Data memory

 

 

 

 

 

 

 

 

 

FDFFH

 

 

 

 

 

 

space

 

 

 

 

 

CALLF Entry Area

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 8 0 0 H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Unusable

 

07FFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program Area

 

 

 

 

 

2 0 0 0 H

 

 

 

 

0 0 8 0 H

 

 

 

 

 

 

 

 

 

0 0 7 F H

 

 

 

 

 

 

1FFFH

 

 

 

CALLT Table Area

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Program

 

 

 

 

 

0 0 4 0 H

 

 

 

memory

 

 

Internal ROM

 

 

 

 

 

 

 

0 0 3 F H

 

 

 

space

 

 

8192 × 8 bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Vector Table Area

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

0 0 0 0 H

 

 

 

0 0 0 0 H

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

25

CHAPTER 3 CPU ARCHITECTURE

Figure 3-2. Memory Map (μPD78082)

 

 

 

 

 

FFFFH

 

Special Function

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Registers (SFRs)

 

 

 

 

 

 

 

 

FF00H

256 × 8 bits

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

FEFFH

General Registers

 

 

 

 

 

 

 

 

 

FEE0H

32 × 8 bits

 

 

 

 

 

 

 

 

 

FEDFH

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Internal High-speed RAM

 

3FFFH

 

 

 

 

 

 

 

 

384 × 8 bits

 

 

Program Area