Apple IMAC A1418 Schematic

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

www.qdzbwx.comwww.qdzbwx.com

6 5 4 3

J117 MLB

LAST_MODIFIED=Thu Sep 18 13:37:48 2014

LAST_MODIFICATION=Thu Sep 18 13:37:48 2014

2 1

ECNREV DESCRIPTION OF REVISION

CK APPD

DATE

2014-12-0900035019963 ENGINEERING RELEASED

D

www.rosefix.com

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<.CSA>

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<.CSA>

DATE

CONTENTS

J117 MLB_IG

BOM Configuration

DEBUG LEDS

Holes/PD parts CPU GFX/NCTF/RSVD

CPU Misc/JTAG/CFG/RSVD

CPU DDR3/LPDDR3 Interfaces

CPU/PCH POWER

CPU/PCH GROUNDS

CPU Decoupling

PCH Decoupling

PCH Audio/JTAG/SATA/CLK

PCH PM/PCI/GFX

PCH PCIe/USB/LPC/SPI/SMBus

PCH GPIO/MISC/LPIO

CPU/PCH Merged XDP

Chipset Support

Project Chipset Support

DDR3 Signal Aliases

DDR3 VREF MARGINING

LPDDR3 DRAM Channel A (0-31)

LPDDR3 DRAM Channel A (32-63)

LPDDR3 DRAM Channel B (0-31)

LPDDR3 DRAM Channel B (32-63)

LPDDR3 DRAM Termination

Thunderbolt Host (1 of 2)

Thunderbolt Host (2 of 2) PCH PCIe/DMI Constaints

Thunderbolt Connector A

Thunderbolt Connector B

DDC Crossbar

AIRPORT/BT

SSD Connectors

HDD Connector

ETHERNET PHY (CAESAR IV)

Ethernet Support & Connector

SD READER CONNECTOR

Camera Controller

Camera Controller Support

Internal DP Support

Internal DP MUXing

EXTERNAL USB PORTS A & B

EXTERNAL USB PORTS C & D

SMC

SMC Support

SPI and Debug Connector

SYNC

J117_Tony

J117_Rossana

J117_Andres

J117_Tony

J117_Rossana

J117_Andres

J117_Garen

J117_Andres

J94

J117_Nick

J94

J117_Rossana

J117_Nick

J117_Rossana

J117_Garen

J94

J117_Nick

07/11/2014

09/03/2014

09/12/2014

09/09/2014

06/19/2014

11/20/2014

06/11/2014

06/24/2014

07/14/2014

07/31/2014

06/26/2014

10/10/2014

11/20/2014

06/17/2014

11/18/2014

12/03/2014

07/31/2014

10/10/2014

07/31/2014

07/14/2014

06/24/2014

PAGE CONTENTS

46

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84

85

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100

104

105

110

111

112

113

114

115

116

117

118

119

120

121

123

SMBus Connections

I and V Sense

Temperature Sensors

System Fan

AUDIO: Codec (Analog)

AUDIO:CODEC, DIGITAL

AUDIO: SPEAKER AMP, LEFT CHANNEL

AUDIO: SPEAKER AMP, RIGHT CHANEL

AUDIO: JACK TRANSLATORS

AUDIO: Speaker ID

Power Connectors / VReg G3Hot

CPU VR12.6 VCC Regulator IC

CPU VR12.5 VCC Power Stage

VReg VDDQ S3 / 1.8V S3

VREG 1V05 S0 / 1V5 S0

VReg 3.3V S5/5V S4

LCD Backlight Driver (LP8561)

PM FETs/LDOs

PM Regulator Enables

PM Power Good

Power Aliases

Unused Signal Aliases

Functional / ICT Test

J70 RULE DEFINITIONS

DDR3 Constraints

CPU CONSTRAINTS

SATA/FDI/XDP Constraints

PCH and BR Constraints

USB/Ethernet/SD Constraints

SMBus/Sensor Constraints

VReg Constraints

CPU VReg Constraints

Platform VReg Constraints

TBT/DP Constraints

BLC Constraints

SYNC

J117_Tony

J117_Garen

J94

J117_Tony

J117_Garen

J117_Andres

J117_Garen

DATE

11/17/2014

06/12/2014

10/10/2014

10/28/2014

06/27/2014

06/10/2014

09/12/2014

06/17/2014

D

C

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A

DRAWING

TITLE=J16 MLB_IG

ABBREV=DRAWING

LAST_MODIFIED=Thu Sep 18 13:37:48 2014

3

DRAWING TITLE

SCHEM,MLB,J117

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

DRAWING

051-00081

REVISION

3.0.0

BRANCH

PAGE

1 OF 123

SHEET

1 OF 81

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SIZEDRAWING NUMBER

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Schematic / PCB #'s

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

www.qdzbwx.com

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

1 CRITICALSCHSCH,MLB,J117051-00081

TABLE_5_ITEM

820-00034 1 CRITICALPCBPCBF,MLB,J117

TABLE_5_ITEM

1685-00013 PCBA,MLB,J117,COMMON PARTS MLB_CMNPTSCMNPTS

Main BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

985-00016 PCBA,MLB,DEV,J117 DEVELOPMENT,J117_DEVEL

PCBA,MLB,DEV,J117,CPU_INT939-00158

639-00910 PCBA,MLB,J117,HY_8GB_29NM,HDD,1866

639-00911 PCBA,MLB,J117,EL_8GB_25NM,HDD,1866

639-00912 PCBA,MLB,J117,SA_8GB_23NM,HDD,1866

639-00913 PCBA,MLB,J117,EL_16GB_25NM,HDD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:ELPIDA_16GB_1866,SSD:N

639-00914 PCBA,MLB,J117,HY_16GB_25NM,HDD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:HYNIX_16GB_1866,SSD:N

639-00713 PCBA,MLB,J117,HY_8GB_29NM,SSD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:HYNIX_8GB_1866,SSD:Y

639-00714 PCBA,MLB,J117,EL_8GB_25NM,SSD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:ELPIDA_8GB_1866,SSD:Y

639-00715 PCBA,MLB,J117,SA_8GB_23NM,SSD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:SAMSUNG_8GB_1866,SSD:Y

PCBA,MLB,J117,EL_16GB_25NM,SSD,1866639-00716

PCBA,MLB,J117,HY_16GB_25NM,SSD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:HYNIX_16GB_1866,SSD:Y639-00717

PCBA,MLB,J117,COMMON PARTS685-00013 J117_COMMON

MLB_CMNPTS,ALTERNATE,CPU:SOCKET,DDR3:HYNIX_8GB_1866,SSD:Y

MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:HYNIX_8GB_1866,SSD:N

MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:ELPIDA_8GB_1866,SSD:N

MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:SAMSUNG_8GB_1866,SSD:N

MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:ELPIDA_16GB_1866,SSD:Y

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Alternates

PART NUMBER

377S0155377S00011

377S0184

155S0578 155S0367 ALL

197S0481 ALL197S0480

197S0399 ALL197S0392

155S0830 155S0316 ALL

377S0155

377S0057

128S0365 ALL128S0368

138S0638138S0681 ALL

197S0478 ALL197S0479

197S0478197S0486 ALL

197S0480 ALL197S0343

378S0390378S0391 ALL

341S3912 ALL341S00016

197S0544 ALL197S0542

197S0392 ALL197S0369

376S00075 ALL376S0972

132S0401 ALL132S00012

138S0771138S00012 ALL

155S0546155S00076 ALL

ALL

ALL107S0251 107S0249

ALL138S0775138S0860

ALL138S0859 138S0788

ALL138S0773138S0747

ALL197S0544197S0545

ALL376S0659376S0572

ALL138S1103 138S0719

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

USB3 diodesALL 376S1128 ALL376S1089

TABLE_ALT_ITEM

USB3 diodesALL

TABLE_ALT_ITEM

TVS377S0124

TABLE_ALT_ITEM

120OHM EMI BEAD

TABLE_ALT_ITEM

150UF AL POLY

TABLE_ALT_ITEM

Taiyo 10uf 805 alt

TABLE_ALT_ITEM

12 MHz Cam. Xtal

TABLE_ALT_ITEM

155S0694 155S0387 ALL

127S0164 127S0162

376S00074 376S0855

376S1129

376S00074

12 MHz Cam. Xtal

TABLE_ALT_ITEM

Sense resistor

TABLE_ALT_ITEM

25MHz Xtal

TABLE_ALT_ITEM

25MHz Xtal

TABLE_ALT_ITEM

Single-source 1uF 402

TABLE_ALT_ITEM

Single-source 10uF

TABLE_ALT_ITEM

Debug LEDs

TABLE_ALT_ITEM

ENET ROM,ADESTO,V1.15

TABLE_ALT_ITEM

1uF,X6S,402

TABLE_ALT_ITEM

24 MHz PCH XTal

TABLE_ALT_ITEM

24 Mhz PCH XTal

TABLE_ALT_ITEM

32 KHz PCH Xtal

TABLE_ALT_ITEM

32 KHz PCH Xtal

TABLE_ALT_ITEM

Single P-Ch FET

TABLE_ALT_ITEM

Single N-Ch FET

TABLE_ALT_ITEM

0.22uF,X7R,0402

TABLE_ALT_ITEM

1uF,X6S,0402

TABLE_ALT_ITEM

4.7uF,X5R,0402

TABLE_ALT_ITEM

FER BD,600 OHM,0.5A,0603

TABLE_ALT_ITEM

FER BD,600 OHM,300MA,402

311S0649

107S0375

107S00011

353S3814

353S4376

311S00014

311S00013

371S00019

376S00037

376S00036 ALL

138S0746 ALL

152S1757

138S00013

PART NUMBER

155S0513155S0660 ALL

ALL

376S0855

ALL

376S0855 SSD:Y ALL

ALLSSD:Y376S0855376S1129

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

Single N-Ch FET

22OHM EMI BEAD

470OHM EMI BEAD

1UF 25V TANT

Dual N-Ch FET

311S0541 ALL Single AND Gate

107S00039

107S0372

353S3812

353S3384

311S0515

311S0508

371S0463

376S1193

376S1194

138S0705

152S1821

138S0772

371S0749

ALL DDR Sense Res

ALL CPU VR Sense Res

ALL

ALL371S00017

TBT mux

HDD OOBv1 comparator

TBT JTAG ISOLATION BUFFER

Single Buffer Driver OD

Rohm Schottky Barrier Diode

30V,64A,Single N-Channel FET

30V,52A,Single N-channel FET

CAP,CER,X5R,10uF,20%,10V,402

IND,0.4uH,23A

CAP,CER,2.2UF,20%,10V,X6S,402

DIODE,SCHOTTKY,30V,1A,SOD-323

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Strategic Silicon

PART# COMMENT

337S00065 08

338S1247 02

335S00006

333S0784 07

333S0786

333S0790

333S00004 07

STRATEGIC VALUE

07

07333S0792

CPU,BDW-ULT,2+GT3

TBT,Falcon Ridge-4c

IC,SERIAL FLASH,Quad-IO

32Gb,25nm LPDDR3-1866

16Gb,29nm LPDDR3-1866

32Gb,25nm LPDDR3-1866

16Gb,25nm LPDDR3-1866

16Gb,23nm LPDDR3-1866

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

D

TABLE_STRATEGIC__ITEM

C

B

A

BOM Groups

BOM GROUP BOM OPTIONS

COMMON,ALTERNATE,J117_PROGPARTS,SMCREG:SUP,XDP,SMBUS1:ISOL,USB_OC_ISO:Y,RTCRST:Y,AUDIO_DP_SNS:NJ117_COMMON

J117_DEVEL XDP_CONN,TEMPSNSDEV,SAMCONN

CPUs

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

337S00101

998-7866

1

IC,CPU,BDW-ULT,QH3Y,ES,f0-B2,2/3,1.6,15W,.95,1168

1

INTERPOSER,BGA1168,SINGLE SIDE

U0500

ASIC Parts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

343S0616

1

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

IC,BCM57766A,CIV+,A0,8x8

1

U2800338S1247

Programmable Parts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

341S00158

335S00006

341S00110

338S1214

341S3778

335S0852

341S00154

341S3912 ENETROM:PROGCRITICALU3990

335S1025

IC,EFI,V0108,J117

1

IC,SERIAL FLASH,64MBIT,3V,8P,WSON,QE=1

IC,SMC-B1,EXTERNAL,V2.24A19,POC,J117

1

IC,SMC12-B1,40MHZ/50MIPS,MCU,157BGA

IC,CAMERA,FLASH,V7229,J16

1

IC,FLASH,SPI,1MBIT,3V3

IC,EPROM,T29,FALCON RIDGE,V27.1,J117

1

IC,FLASH,SPI,4MBIT,50MHZ335S0915

IC,ENET SPI ROM,NYMONYX,V1.15,J16/J16G/J17

1

IC,SERIAL FLASH,2MBIT,2.7V,REV F

1

U4202

U2890 TBTROM:PROG

U3990 CRITICAL

SMC:PROG,BOOTROM:PROG,CAMROM:PROG,TBTROM:PROG,ENETROM:PROGJ117_PROGPARTS

CRITICAL

CRITICALU3900

CRITICAL BOOTROM:PROGU5210

CRITICAL SMC:PROGU5000

CRITICAL SMC:BLANKU5000

CRITICAL CAMROM:BLANKU4202

CRITICAL

BOM OPTIONCRITICAL

CPU:ULT

CPU:SOCKET

BOM OPTIONCRITICAL

BOOTROM:BLANKCRITICALU5210

CAMROM:PROGCRITICAL

TBTROM:BLANKCRITICALU2890

ENETROM:BLANK

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CPU DRAM SPD Straps

BOM GROUP BOM OPTIONS

DDR3:HYNIX_8GB_1600

DDR3:HYNIX_16GB_1600

DDR3:HYNIX_8GB_1866

DDR3:HYNIX_16GB_1866

DDR3:ELPIDA_8GB_1600

DDR3:ELPIDA_16GB_1600

DDR3:ELPIDA_8GB_1866

DDR3:ELPIDA_16GB_1866

DDR3:SAMSUNG_8GB_1600

DDR3:SAMSUNG_8GB_1866

DRAM Parts

333S0783

4

4333S0784

333S0785

333S0786

4

333S0789 4

333S0790

333S0791

333S0792

4

333S00003 4

333S00004 4

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

IC,SDRAM,29nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,29nm 16Gb,LPDDR3-1866,178P FBGA

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

IC,SDRAM,25nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,25nm 16Gb,LPDDR3-1866,178P FBGA

IC,SDRAM,23nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,23nm 16Gb,LPDDR3-1866,178P FBGA

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,RAMCFG4:L,HYNIX_8GB_1600

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,RAMCFG4:L,HYNIX_16GB_1600

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,RAMCFG4:H,HYNIX_8GB_1866

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,RAMCFG4:H,HYNIX_16GB_1866

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,RAMCFG4:L,ELPIDA_8GB_1600

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,RAMCFG4:L,ELPIDA_16GB_1600

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,RAMCFG4:H,ELPIDA_8GB_1866

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,RAMCFG4:H,ELPIDA_16GB_1866

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,RAMCFG4:L,SAMSUNG_8GB_1600

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,RAMCFG4:H,SAMSUNG_8GB_1866

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

U2300,U2400,U2500,U2600

CRITICAL

HYNIX_16GB_1600

HYNIX_16GB_1866

HYNIX_8GB_1600

HYNIX_8GB_1866

ELPIDA_16GB_1600

ELPIDA_16GB_1866

ELPIDA_8GB_1600

ELPIDA_8GB_1866

SAMSUNG_8GB_1600

SAMSUNG_8GB_1866

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CPU DRAM CFG Chart

CFG 3

A

B

0

1

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

VENDOR

HYNIX

SAMSUNG

N/A

ELPIDA

SIZE

8GB

16GB 1

SPEED

1866

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

CFG 1

0

1

CFG 0

0

1

0

1

CFG 2

0

CFG 4DIE REV

01600

1

SYNC_DATE=05/05/2014SYNC_MASTER=J117_TONY

051-00081

3.0.0

2 OF 123

2 OF 81

B

A

D

8 7 5 4 2 1

36

www.qdzbwx.com

345678

2 1

VIDEO ON Led

D

=PP3V3_S5_LED

66

1

R0301

1K

5% 1/16W MF-LF 402

2

ITS_PLUGGED_IN

SILK_PART=1

A

CRITICAL

LE0301

GRN-6MCD-0.03A

0805

K

ALL_SYS_PWRGD LedS5 Led

=PP3V3_S4_LED =PP3V3_S4_LED

66 3 66 3

1

R0302

1K

5% 1/16W MF-LF 402

2

SILK_PART=2

A

CRITICAL

LE0302

GRN-6MCD-0.03A

0805

K

CORE_VOLTAGES_ON

CRITICAL

Q0302

DMN5L06VK-7

SOT563

VER 3

3

D

MEM_GOOD Led

1

R0303

1K

5% 1/16W MF-LF 402

2

SILK_PART=3

A

CRITICAL

LE0303

GRN-6MCD-0.03A

0805

K

MEMORY_GOOD

CRITICAL

Q0302

SOT563

VER 3

6

D

DMN5L06VK-7

=PP3V3_S0_LED

66

1

R0304

1K

5% 1/16W MF-LF 402

2

LCD_SHOULD_ON_RMEMORY_GOOD_RCORE_VOLTAGES_ON_R

SILK_PART=4

A

CRITICAL

LE0304

GRN-6MCD-0.03A

0805

K

VIDEO_ON_L

D

39

IN

C

65 43 17

5

G S

IN

ALL_SYS_PWRGD MEM_GOOD_LED

4

15

IN

2

G S

1

C

B

A

PAGE TITLE

DEBUG LEDS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=10/22/2013SYNC_MASTER=J70_GAREN

051-00081

3.0.0

3 OF 123

3 OF 81

A

D

345678

2 1

D

CPU HEATSINK MOUNTING FEATURES

SH0473

STDOFF-4.5OD.98H-1.1-3.40-TH

CRITICAL

1

STDOFF-4.5OD.98H-1.1-3.40-TH

SH0474

CRITICAL

1

www.qdzbwx.com

STDOFF-4.5OD.98H-1.1-3.40-TH

HEATSINK STABILITY MOUNTING FEATURES

SH0475

CRITICAL

1

SH0476

CRITICAL

STDOFF-4.5OD.98H-1.1-3.40-TH

1

WIRELESS CARD MTG HOLES

APN:998-01406 (Plated holes, 2.1mm inner diameter, 4.3mm top pad, 5.1mm bottom pad)

ZH0421

4P3R2P1-5P5B-NSP

1

ZH0422

4P3R2P1-5P5B-NSP

1

D

C

APN:860-1532

CRITICAL

SH0477

STDOFF-4.5OD.98H-1.1-3.40-TH

1

Rear Cover

CRITICAL

SH0479

STDOFF-4.5OD.98H-1.1-3.40-TH

1

C

B

APN:998-4559 (Plated holes, 4mm inner diameter, 8mm pad)

ZH0413

7P0R4P0-8P0B-NSP

1

ZH0414

7P0R4P0-8P0B-NSP

1

ZH0415

7P0R4P0-8P0B-NSP

1

ZH0416

7P0R4P0-8P0B-NSP

1

B

J117 SPRINGS

APN:870-00908 SPRING FINGER 4.2X2.5X5.3 APN:870-00909 SPRING FINGER 4.2X2.5X5.81

SH0480

2288394-4

1

SM

SH0481

2288394-5

1

SM

SH0482

2288394-5

1

SM

SSD STANDOFF

APN: 860-00198

SSD:Y

CRITICAL

NUT0413

5.5OD2.65ID-6.5H-SM

1

A

PAGE TITLE

Holes/PD parts

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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051-00081

3.0.0

4 OF 123

4 OF 81

A

D

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DDI Port Assignments:

TBT Sink 0

TBT Sink 1

(MUXed with HDMI

if necessary)

345678

2 1

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 1 OF 19

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<3>

C54 C55 B58 C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

DDI

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

DP_INT_ML_N<0>

DP_INT_ML_P<0>

DP_INT_ML_N<1>

DP_INT_ML_P<1>

DP_INT_ML_N<2>

DP_INT_ML_P<2>

DP_INT_ML_N<3>

DP_INT_ML_P<3>

DP_INT_AUX_N

DP_INT_AUX_P

MCP_EDP_RCOMP

71

NC_EDP_DISP_UTILDP_TBTSNK1_ML_C_P<3>

OUT

BI

40 80

40

40 80

eDP Port Assignment:

Internal panel

PPVCOMP_S0_CPU

1

R0530

24.9

1% 1/20W MF 201

2

PLACE_NEAR=U0500.D20:12.7mm

D

8

C

TP0531

TP0501

TP

TP-P6

TP

TP-P6

MCP Daisy-Chain Strategy:

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

NO_TEST

MCP_DC_AW2_AY2

5

MCP_DC_AW3_AY3

5

1

MCP_DC_AY60

MCP_DC_AW61_AY61

5

MCP_DC_AW62_AY62

5

MCP_DC_B2

MCP_DC_A3_B3

5

MCP_DC_A61_B61

5

MCP_DC_B62_B63

MCP_DC_C1_C2

1

AY2

AY3 AY60 AY61 AY62

B2

B3 B61 B62 B63

C1

C2

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

SYM 17 OF 19

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

Each corner of CPU has two testpoints.

Other corner test signals connected in

daisy-chain fashion. Continuity should

exist between both TP's on each corner.

NO_TEST

A3 A4

A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63

1

MCP_DC_A3_B3

MCP_DC_A4

MCP_DC_A60

MCP_DC_A61_B61

MCP_DC_A62

MCP_DC_AV1

MCP_DC_AW1

MCP_DC_AW2_AY2

MCP_DC_AW3_AY3

MCP_DC_AW61_AY61

MCP_DC_AW62_AY62

MCP_DC_AW63

C

5

1

TP

TP0500

TP-P6

1

TP

TP0510

5

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP0511

TP0520

TP0521

TP0530

B

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 18 OF 19

AT2

RSVD

AU44

NC NC

AV44

NC NC

D15

F22

H22

J21

RSVD RSVD RSVD

SPARE

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

NCNC

NC

B

A

PAGE TITLE

CPU GFX/NCTF/RSVD

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

051-00081

3.0.0

5 OF 123

5 OF 81

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www.qdzbwx.com

CRITICAL

OMIT_TABLE

345678

2 1

D

66 57 17 16 15 8

71 57 44 43

=PP1V05_S0_CPU_VCCST

CPU_PROCHOT_L

R0651

121

1%

1/20W

MF

201

R0650

200

1%

1/20W

MF

201

BI

1

2

U0500

BROADWELL-ULT

2C+GT2

BGA

D61

NC

62

5%

1/20W

MF

201

100

1%

1/20W

MF

201

1

71 44

2

1

2

R0611

56

2 1

5%

1/20W

MF

201

R0620

10K

5%

1/20W

MF

201

1

2

18

OUT

BI

OUT

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

71

CPU_PWRGD

70

CPU_SM_RCOMP<0>

70

CPU_SM_RCOMP<1>

70

CPU_SM_RCOMP<2>

NC_MEM_RESET_L

CPU_MEMVTT_PWR_EN_LSVDDQ

AU60 AV60 AU61

AV15

AV61

R0610

1

2

R0652

PROC_DETECT* PRDY*

K61

CATERR*

N62

PECI

K63

PROCHOT*

C61

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SM_DRAMRST*

SM_PG_CNTL1

SYM 2 OF 19

THERMAL

MISC

PWRDDR3

(IPU)

JTAG

(IPD)

(IPU)

PREQ*

PROC_TCK

PROC_TMS

PROC_TRST*

PROC_TDI

PROC_TDO

(IPU)

BPM0* BPM1* BPM2* BPM3* BPM4* BPM5* BPM6* BPM7*

J62 K62

E60 E61 E59

F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

XDP_CPU_TMS

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TDO

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<6>

XDP_BPM_L<7>

OUT

IN

OUT

BI

16

73 16

71 16

73 16

D

C

B

A

PLACE_NEAR=U0500.AU60:12.7mm

PLACE_NEAR=U0500.AV60:12.7mm

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

These can be placed close to J1800

and are only for debug access

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<1>

CPU_CFG<0>

NOSTUFF

R0640

1K

5%

1/20W

MF

201

NOSTUFF

1

2

1

R0639

1K

5% 1/20W MF 201

2

NOSTUFF

R0638

1K

5%

1/20W

MF

201

1

2

NOSTUFF

1

R0631

1K

5% 1/20W MF 201

2

NOSTUFF

1

R0630

1K

5% 1/20W MF 201

2

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid

issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CPU_CFG<4>

1

R0634

1K

5% 1/20W MF 201

2

73 16 6

PLACE_NEAR=U0500.AU61:12.7mm

PLACE_NEAR=U0500.C61:12.7mm

C

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 19 OF 19

NC

AC60 AC62 AC63

AA63 AA60

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

AA62

U63

AA61

U62

V63

A5

E1 D1

J20 H18 B12

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

(IPU)

CFG_RCOMP

RSVD

RSVD RSVD RSVD RSVD TD_IREF

RESERVED

RSVD_TP RSVD_TP

RSVD_B43

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

PROC_OPI_COMP

RSVD RSVD

73 16 6

73 16

73 16 6

73 16

73 16 6

73 16

73 16 6

R0680

49.9

1/20W

1%

MF

201

BI

1

2

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<2>

CPU_CFG<3>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<12>

CPU_CFG<13>

CPU_CFG<14>

CPU_CFG<15>

CPU_CFG<16>

CPU_CFG<18>

CPU_CFG<17>

CPU_CFG<19>

71

CPU_CFG_RCOMP

PCH_TD_IREF

1

R0685

8.25K

1% 1/20W MF 201

2

www.qdzbwx.com

VSS VSS

AV63 AU63

C63 C62

B43

A51 B51

L60

N60

W23 Y22

AY15

AV62 D58

P22 N21

P20 R20

NC

NC_MCP_RSVD_AV63

NC_MCP_RSVD_AU63

TP_MCP_RSVD_C63

TP_MCP_RSVD_C62

NC_MCP_RSVD_A51

NC_MCP_RSVD_B51

NC_MCP_RSVD_L60

CPU_OPI_RCOMP

71

PLACE_NEAR=U0500.AY15:12.7mm

1

R0690

49.9

1% 1/20W MF 201

2

SYNC_MASTER=J117_ANDRES SYNC_DATE=03/24/2014

PAGE TITLE

CPU Misc/JTAG/CFG/RSVD

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

6 OF 123

SHEET

6 OF 81

D

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

70 19

CRITICAL

OMIT_TABLE

BI

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

AH63 AH62 AK63 AK62 AH61 AH60 AK61

AK60 AM63 AM62

AP63

AP62 AM61 AM60

AP61

AP60

AP58

AR58 AM57

AK57

AL58 AK58 AR57 AN57 AP55 AR55

AM54

AK54

AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42

AM43 AM45

AK45 AK43

AM40 AM42 AM46

AK46

AM49

AK49

AM48

AK48

AM51

AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 3 OF 19

MEMORY CHANNEL A

LPDDR3

CAB3

CAB2

CAB1

CAB4

CAB6

CAA5

CAB9

CAB8

CAB5

RSVD1

RSVD2

CAA0

CAA2

CAA4

CAA3

CAA1

CAB7

CAA7

CAA6

CAB0

CAA9

CAA8

SM_VREF_CA

SM_VREF_DQ0

SM_VREF_DQ1

SA_CLK0*

SA_CLK0

SA_CLK1*

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS0* SA_CS1*

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49

AR51

AP51

MEM_A_CLK_N<0>MEM_A_DQ<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CAB<1>

MEM_A_CAB<4>

MEM_A_CAB<6>

MEM_A_CAA<5>

MEM_A_CAB<9>

MEM_A_CAB<8> MEM_A_CAB<5>

NC_MEM_A_RSVD1

NC_MEM_A_RSVD2

MEM_A_CAA<0>

MEM_A_CAA<2>

MEM_A_CAA<4>

MEM_A_CAA<3>

MEM_A_CAA<1>

MEM_A_CAB<7>

MEM_A_CAA<7>

MEM_A_CAA<6>

MEM_A_CAB<0>

MEM_A_CAA<9>

MEM_A_CAA<8>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1>

MEM_A_DQS_N<2>

MEM_A_DQS_N<3>

MEM_A_DQS_N<4>

MEM_A_DQS_N<5>

MEM_A_DQS_N<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<0>

MEM_A_DQS_P<1>

MEM_A_DQS_P<2>

MEM_A_DQS_P<3>

MEM_A_DQS_P<4>

MEM_A_DQS_P<5>

MEM_A_DQS_P<6>

MEM_A_DQS_P<7>

CPU_DDR_VREFCA

CPU_DDR_A_VREFDQ

CPU_DDR_B_VREFDQ

OUT

BI

OUT

20

70 25 21

70 25 22

70 25 21

70 25 22

70 25 22 21

70 25 22

70 25 21

70 25 22

70 25 21

70 25 22

70 25 21

70 25 22

70 25 21

70 19

BI

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<9>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<14>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36> MEM_B_CAB<0>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<46>

MEM_B_DQ<48>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

AY31

AW31

AY29

AW29

AV31 AU31 AV29 AU29 AY27

AW27

AY25

AW25

AV27 AU27 AV25 AU25

AM29

AK29

AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26

AM26

AK25

AL25 AY23

AW23

AY21

AW21

AV23 AU23 AV21 AU21 AY19

AW19

AY17

AW17

AV19 AU19 AV17 AU17 AR21 AR22

AL21

AM22

AN22 AP21 AK21 AK22 AN20 AR20 AK18

AL18 AK20

AM20

AR18 AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4

SB_DQ9

SB_DQ12

SB_DQ14

SB_DQ18

SB_DQ22

SB_DQ36

SB_DQ39

SB_DQ48

SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 4 OF 19

MEMORY CHANNEL B

LPDDR3

CAB3

CAB2

CAB1

CAB4

CAB6

CAA5

CAB9

CAB8

CAB5

RSVD3

RSVD4

CAA0

CAA2

CAA4

CAA3

CAA1

CAB7

CAA7

CAA6

CAB0

CAA9

CAA8

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

SB_CKE0SB_DQ5 SB_CKE1SB_DQ6 SB_CKE2SB_DQ7 SB_CKE3SB_DQ8

SB_CS0*SB_DQ10 SB_CS1*SB_DQ11

SB_ODT0SB_DQ13

SB_RAS*SB_DQ15

SB_WE*SB_DQ16

SB_CAS*SB_DQ17

SB_BA0SB_DQ19 SB_BA1SB_DQ20 SB_BA2SB_DQ21

SB_MA0SB_DQ23 SB_MA1SB_DQ24 SB_MA2SB_DQ25 SB_MA3SB_DQ26 SB_MA4SB_DQ27 SB_MA5SB_DQ28 SB_MA6SB_DQ29 SB_MA7SB_DQ30 SB_MA8SB_DQ31

SB_MA9SB_DQ32 SB_MA10SB_DQ33 SB_MA11SB_DQ34 SB_MA12SB_DQ35 SB_MA13 SB_MA14SB_DQ37 SB_MA15SB_DQ38

SB_DQSN0SB_DQ40 SB_DQSN1SB_DQ41 SB_DQSN2SB_DQ42 SB_DQSN3SB_DQ43 SB_DQSN4SB_DQ44 SB_DQSN5SB_DQ45 SB_DQSN6SB_DQ46 SB_DQSN7SB_DQ47

SB_DQSP0SB_DQ49 SB_DQSP1SB_DQ50 SB_DQSP2SB_DQ51 SB_DQSP3SB_DQ52 SB_DQSP4SB_DQ53 SB_DQSP5SB_DQ54 SB_DQSP6SB_DQ55 SB_DQSP7SB_DQ56

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<0>MEM_B_DQ<5>

MEM_B_CKE<1>

MEM_B_CKE<2>MEM_B_DQ<7>

MEM_B_CKE<3>MEM_B_DQ<8>

MEM_B_CS_L<0>MEM_B_DQ<10>

MEM_B_CS_L<1>

MEM_B_ODT<0>MEM_B_DQ<13>

MEM_B_CAB<3>MEM_B_DQ<15>

MEM_B_CAB<2>MEM_B_DQ<16>

MEM_B_CAB<1>MEM_B_DQ<17>

MEM_B_CAB<4>

MEM_B_CAB<6>

MEM_B_CAA<5>

MEM_B_CAB<9>MEM_B_DQ<23>

MEM_B_CAB<8>MEM_B_DQ<24>

MEM_B_CAB<5>MEM_B_DQ<25>

NC_MEM_B_RSVD3

NC_MEM_B_RSVD4

MEM_B_CAA<0>

MEM_B_CAA<2>

MEM_B_CAA<4>

MEM_B_CAA<3>

MEM_B_CAA<1>

MEM_B_CAB<7>

MEM_B_CAA<7>

MEM_B_CAA<6>

MEM_B_CAA<9>MEM_B_DQ<37>

MEM_B_CAA<8>MEM_B_DQ<38>

MEM_B_DQS_N<0>

MEM_B_DQS_N<1>MEM_B_DQ<41>

MEM_B_DQS_N<2>MEM_B_DQ<42>

MEM_B_DQS_N<3>MEM_B_DQ<43>

MEM_B_DQS_N<4>MEM_B_DQ<44>

MEM_B_DQS_N<5>MEM_B_DQ<45>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>MEM_B_DQ<47>

MEM_B_DQS_P<0>MEM_B_DQ<49>

MEM_B_DQS_P<1>MEM_B_DQ<50>

MEM_B_DQS_P<2>MEM_B_DQ<51>

MEM_B_DQS_P<3>

MEM_B_DQS_P<4>

MEM_B_DQS_P<5>

MEM_B_DQS_P<6>

MEM_B_DQS_P<7>MEM_B_DQ<56>

OUT

BI

70 25 23

70 25 24

70 25 23

70 25 24

70 25 24 23

70 25 24

70 25 23

70 25 24

70 25 23

70 25 24

70 25 23

70 25 24

70 25 23

70 19

D

C

B

A

PAGE TITLE

CPU DDR3/LPDDR3 Interfaces

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

051-00081

3.0.0

7 OF 123

7 OF 81

A

D

C

B

BDW-ULT current estimates from Broadwell Mobile ULT Processor EDS vol 1, doc #514405, v1.5.

WPT-LP current estimates from Wildcat Point-LP PCH EDS, doc #515621, v1.0.

Numbers may not be accurate values as of 08/26/2014

66 11

1838mA Max

66

29mA Max[1]

14 11

=PP1V05_S0_PCH_VCCHSIO

=PP1V05_S0_PCH_VCCIO_HSIO

PP1V05_S0_PCH_VCCUSB3PLL

K9

VCCHSIO

L10

VCCHSIO VCCHSIO

N8

VCC1_05

P9

VCC1_05

B18

VCCUSB3PLL

BROADWELL-ULT

SYM 13 OF 19

41mA Max

12 11

PP1V05_S0_PCH_VCCSATA3PLL

B11

VCCSATA3PLL

42mA Max

66 57 17 16 15 8 6

78 57

IN

78 57

OUT

78 57

CRITICAL

OMIT_TABLE

U0500

2C+GT2

BGA

RTCSPICORE

=PP1V05_S0_CPU_VCCST

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

BI

VCCSUS3_3

VCCRTC

DCPRTC

VCCSPI

VCCASW VCCASW

AH11

AG10M9

AE7

Y8

AG14 AG13

75

1%

1/20W

MF

201

1

2

R0810

1/20W

R0800

R0811

0

21

5%

1/20W

MF

0201

=PP3V3_SUS_PCH_VCCSUS_RTC

0.3mA Max[1]

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

=PP3V3_SUS_PCH_VCC_SPI

18mA Max

=PP1V05_S0_PCH_VCCASW

185mA Max[1]

R0812

1/20W

0201

43

5%

MF

201

0

5%

MF

345678

2 1

CRITICAL

OMIT_TABLE

L59

NC

66 10

=PPVMEMIO_S0_CPU

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35

66 10 8

=PPVCC_S0_CPU

AY40 AY44 AY50

100

5%

1/20W

MF

201

1

NC

AC58

2

NC

AB23

NC

AD23

NC

AA23

NC

AE59

R0860

PLACE_NEAR=U0500.C50:50.8mm

78 57

1

R0802

130

1% 1/20W MF 201

2

21

Max load: 300mA

16

OUT

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

PPVCOMP_S0_CPU

5

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

CPU_VCCSENSE_P

MAKE_BASE=TRUE

NOTE: Aliases not used on CPU supply outputs

to avoid any extraneous connections.

NC

CPU_VIDALERT_R_L

78

CPU_VIDSCLK_R

78

CPU_VIDSOUT_R

78

R0802.2:

21

R0810.2:

R0800.2:

PLACE_NEAR=U0500.L63:6.35mm

PLACE_NEAR=U0500.L62:38.1mm

PLACE_NEAR=R0810.1:2.54mm

71 17 16

57

16

IN

OUT

IN

CPU_VCCST_PWRGD

CPU_VR_EN

CPU_VR_READY

CPU_PWR_DEBUG

NC_CPU_RSVD_P60

NC_CPU_RSVD_P61

NC_CPU_RSVD_N59

TP_CPU_RSVD_N61

NC

AD60

NC

AD59

NC

AA59

NC

AE60

NC

AC59

NC

AG58

NC

66 57 17 16 15 8 6

66 11

=PPVRTC_G3_PCH

=PP1V05_S0_CPU_VCCST

???mA Max

66 13 12

AC22 AE22 AE23

BYPASS=U0500.AE7::6.35mm

66 14 11

66 11 8

1

C0895

0.1UF

10%

6.3V

2

CERM-X5R 0201

C0892

0.1UF

20% 10V

CERM

402

1

2

C0891

0.1UF

20% 10V

CERM

402

BYPASS=U0500.AG10::6.35mm

1

2

BYPASS=U0500.AG10::6.35mm

1

C0890

1UF

10%

6.3V

2

CERM 402

BYPASS=U0500.AG10::6.35mm

AB57

AD57 AG57

RSVD

J58

RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

F59

VCC

N58

RSVD RSVD

E63

VCC_SENSE

RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT RSVD RSVD RSVD

L62

VIDALERT*

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG*

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

U59

RSVD

V59

RSVD

VCCST VCCST VCCST

VCC VCC VCC

C24

VCC

C28

VCC

C32

VCC

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 12 OF 19

HSW ULT POWER

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

=PPVCC_S0_CPU

66 10 8

32A Max

D

C

B

11

66 17 11

66 11

11

WF: RSVD on Sawtooth Peak rev 1.0

PP1V05_S0_PCH_VCCAPLL_OPI

57mA Max

=PP1V5_S0_PCH_VCCSUSHDA

11mA Max

=PP3V3_SUS_PCH_VCCSUS_GPIO

59mA Max[1]

=PP3V3_S5_PCH_VCCDSW

114mA Max

=PP3V3_S0_PCH_VCC3_3_GPIO

40mA Max[1]

PP1V05_S0_PCH_VCC_ICC

VCCCLK: 200mA Max

NC

Y20

AA21

W21

J13

AH14

AH13

AC9 AA9

AH10

V8

W9

J18

K19

VCCAPLL VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

VRM/USB2/AZALIA

DCPSUS2

VCCSUS3_3 VCCSUS3_3

VCCDSW3_3

VCC3_3 VCC3_3

VCCCLK VCCCLK

AZALIA/HDA

USB3 OPI HSIO

THERMAL SENSOR

VCC1P05 VCC1P05 VCC1P05 VCC1P05 VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

J11 H11 H15 AE8 AF22

AG19 AG20

AE9 AF9 AG8

AD10 AD8

J15

K14 K16

=PP1V05_S0_PCH_VCC

1499mA Max[1]

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

=PP1V05_S0_PCH_VCCASW

473mA Max[1]

NC

=PP1V5_S0_PCH_VCCTS

3mA Max

=PP3V3_S0_PCH_VCCTS

1mA Max[1]

66 11

Powered in DeepSx

66

66 11

PLACE_NEAR=U0500.AG19:2.54mm

R0899

5.11

1/20W MF-LF

66 11 8

1%

201

21

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

1

C0899

1UF

10%

6.3V

2

CERM 402

BYPASS=U0500.AG19::2.54mm

A

12 11

PP1V05_S0_PCH_VCCACLKPLL

31mA Max

66 11

=PP1V05_S0_PCH_VCCCLK

VCCCLK: 200mA Max

WF: RSVD on Sawtooth Peak rev 1.0

NC

A20

J17 R21 T21 K18

M20

V21

VCCACLKPLL

VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD

SERIAL IO

SUS OSCILLATOR

ICC GPIO/LCC

VCCSDIO VCCSDIO

DCPSUS4

RSVD

U8 T9

AB8

AC20

=PP3V3_S0_PCH_VCCSDIO

17mA Max

NC

WF: RSVD on Sawtooth Peak rev 1.0

NC

66 11

PAGE TITLE

CPU/PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

=PP3V3_SUS_PCH_VCCSUS_ICC

66

3.3mA Max[1]

AE20 AE21

VCCSUS3_3 VCCSUS3_3

LPT LP POWER

USB2

VCC1_05 VCC1_05

8 7 5 4 2 1

AG16 AG17

=PP1V05_S0_PCH_VCCIO_USB2

213mA Max[1]

66 11

www.qdzbwx.com

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

36

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

8 OF 123

SHEET

8 OF 81

A

345678

2 1

D

C

B

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63 AE10

AE5

AE58

AF11 AF12 AF14 AF15 AF17 AF18

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 14 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57

AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5

AR52

AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1

AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59

AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 15 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D5 D50 D51 D53 D54 D55 D57 D59 D62

D8 E11 E17

F20 F26 F30 F34 F38 F42 F46 F50 F54 F58

F61 G18 G22

G3 G5 G6 G8

H13

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 16 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS_SENSE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

CPU_VCCSENSE_N

1

R0960

2

100

5% 1/20W MF 201

PLACE_NEAR=U0500.E62:50.8mm

OUT

D

C

78 57

B

A

PAGE TITLE

CPU/PCH GROUNDS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

051-00081

3.0.0

9 OF 123

9 OF 81

A

D

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

CPU VCC Decoupling

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff

Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

=PPVCC_S0_CPU

66 8

J70 implementation : 18x 10uF 0402 mirrored stuff, 32x 10uF single sided no stuff

345678

2 1

D

CRITICAL

1

C105A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C108A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1076

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C105B

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C108C

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1077

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C105D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C108D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107C

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1060

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107B

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1061

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C105E

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C104A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1062

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C105F

2

10UF

20%

6.3V CERM 0402

CRITICAL

1

C104B

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1063

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C106A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C104C

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C104D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C104E

10UF

20%

6.3V

2

CERM 0402

1

2

These caps are on the top side.

CRITICAL

1

C106B

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C106C

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C106D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

C104F

10UF

20%

6.3V CERM 0402

CRITICAL

1

C106E

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1030

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1070

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1085

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C105C

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1071

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1086

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1072

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1087

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1078

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1091

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1079

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1092

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1080

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1093

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1081

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1094

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1082

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1095

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1083

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1096

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1084

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1097

1UF

10% 10V

2

X6S-CERM 0402

D

C

CRITICAL

1

C107E

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107F

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C108B

10UF

20%

6.3V

2

CERM 0402

1

2

These caps are mirrored top and bottom.

CPU VDDQ DECOUPLING

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603

Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 6x 10uF no stuff, 1x 270 uF Bulk

CRITICAL

C1064

10UF

20%

6.3V CERM 0402

CRITICAL

1

C1065

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1066

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1067

10UF

20%

6.3V

2

CERM 0402

These caps are beneath the CPU.

C

These caps are on the bottom side.

B

=PPVMEMIO_S0_CPU

66 8

CRITICAL

1

C1040

2.2UF

20% 10V

2

X6S-CERM 0402

CRITICAL

1

C1042

2.2UF

20% 10V

2

X6S-CERM 0402

CRITICAL

1

C1043

2.2UF

20% 10V

2

X6S-CERM 0402

These caps are on the bottom side.

CRITICAL

1

C1041

2.2UF

20% 10V

2

X6S-CERM 0402

These caps are on the top side.

CRITICAL

1

C1050

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1051

10UF

20% 4V

2

X6S 0402

CRITICAL NO STUFF

1

C109A

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1054

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1055

10UF

20% 4V

2

X6S 0402

NO STUFF CRITICAL

1

C109E

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF CRITICAL

1

C109D

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1053

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF CRITICAL

1

C109C

10UF

20%

6.3V

2

CERM-X5R 0402-1

These caps are on the bottom side.

NO STUFF CRITICAL

1

C109F

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF CRITICAL

1

C109B

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1052

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF CRITICAL

1

C1099

10UF

20%

6.3V

2

CERM-X5R 0402-1

These caps are on the top side.

B

A

CRITICAL

1

C1056

270UF-0.006OHM

20% 2V

2

TANT CASE-D2

www.qdzbwx.com

These caps are mirrored top and bottom.

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

10 OF 123

SHEET

10 OF 81

A

8 7 5 4 2 1

36

D

C

66 8

66 14 8

66 8

PCH VCCDSW3_3 BYPASS

(PCH 3.3V DSW PWR)

=PP3V3_S5_PCH_VCCDSW

PCH VCCSPI BYPASS

(PCH 3.3V SPI PWR)

=PP3V3_SUS_PCH_VCC_SPI

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SUSPEND PWR)

=PP3V3_SUS_PCH_VCCSUS_GPIO

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SUSPEND RTC PWR)

=PP3V3_SUS_PCH_VCCSUS_RTC

NO STUFF

1UF

10%

6.3V CERM

402

1

2

C1200

BYPASS=U0500.AH10::6.35mm

NO STUFF

20% 10V

CERM

402

22UF

20%

6.3V

603

1UF

10%

6.3V CERM

402

1

2

1

2

1

2

C1202

0.1UF

BYPASS=U0500.Y8::6.35mm

C1204

X5R-CERM-1

BYPASS=U0500.AC9::12.7mm

C1206

BYPASS=U0500.AH11::6.35mm

345678

2 1

PCH VCCASW BYPASS

PCH VCC3_3 BYPASS

(PCH 3.3V GPIO/LPC PWR)

=PP3V3_S0_PCH_VCC3_3_GPIO =PP1V05_S0_PCH_VCCIO_USB2

66 8 66 8

(PCH 1.05V ME CORE PWR)

=PP1V05_S0_PCH_VCCASW

66 8

PCH VCCIO BYPASS

(PCH 1.05V USB2 PWR)

NO STUFF

1

C1251

1UF

10%

6.3V

2

CERM 402

20%

6.3V

603

1

2

C1212

22UF

X5R-CERM-1

BYPASS=U0500.V8::12.7mm

20%

6.3V

603

1

2

C1250

22UF

X5R-CERM-1

BYPASS=U0500.AE9::12.7mm

BYPASS=U0500.AE9::6.35mm

PCH VCC3_3 BYPASS

(PCH 3.3V THERMAL PWR)

=PP3V3_S0_PCH_VCCTS

66 8

20% 10V

CERM

402

1

2

C1214

0.1UF

BYPASS=U0500.K14::6.35mm

PCH VCC BYPASS

(PCH 1.05V CORE PWR)

=PP1V05_S0_PCH_VCC

66 8

20%

6.3V

1

2

C1255

10UF

CERM-X5R

0402-1

BYPASS=U0500.J11::12.7mm

BYPASS=U0500.J11::6.35mm

1

C1256

1UF

10%

6.3V

2

CERM 402

BYPASS=U0500.AE8::6.35mm

1

C1257

1UF

10%

6.3V

2

CERM 402

PCH VCCCLK BYPASS

(PCH 1.05V CLK PWR)

=PP1V05_S0_PCH_VCCCLK

66 8

BYPASS=U0500.J17::6.35mm

PCH VCCHSIO BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

=PP1V05_S0_PCH_VCCHSIO

66 8

C1260

BYPASS=U0500.K9::6.35mm

1

1UF

10%

6.3V

2

CERM

402

BYPASS=U0500.L10::6.35mm

C1261

BYPASS=U0500.M9::6.35mm

1UF

10%

6.3V CERM

402

1

2

1

C1262

10UF

20%

6.3V

2

CERM-X5R 0402-1

BYPASS=U0500.AG16::6.35mm

C1266

1

1UF

10%

6.3V

2

CERM

402

BYPASS=U0500.R21::6.35mm

C1264

1UF

10%

6.3V CERM

402

C1267

1UF

10%

6.3V CERM

402

1

2

D

1

2

C

B

66 8

66 17 8

PCH VCCSDIO BYPASS

(PCH 3.3V SDIO PWR)

=PP3V3_S0_PCH_VCCSDIO

PCH VCCSUSHDA BYPASS

(PCH 1.5V HDA PWR)

=PP1V5_S0_PCH_VCCSUSHDA

1UF

10%

6.3V CERM

402

1UF

10%

6.3V CERM

402

1

2

1

2

C1208

BYPASS=U0500.U8::6.35mm

C1210

BYPASS=U0500.AH14::6.35mm

=PP1V05_S0_PCH_PLLFILTERS

66

R1270

0

21

PP1V05_S0_PCH_VCCACLKPLL_R

5% 1/16W MF-LF

402

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

R1275

0

21

PP1V05_S0_PCH_VCC_ICC_R

5% 1/16W MF-LF

402

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

R1280

0

21

5% 1/16W MF-LF

402

CRITICAL

NO STUFF

L1280

2.2UH-240MA-0.221OHM

0603

CRITICAL

L1270

2.2UH-240MA-0.221OHM

21

0603

C1270

CERM-X5R

0805-1

BYPASS=U0500.A20::12.7mm

1

47UF

20%

4V

2

BYPASS=U0500.A20::12.7mm

CRITICAL

L1275

2.2UH-240MA-0.221OHM

21

0603

C1275

CERM-X5R

0805-1

BYPASS=U0500.J18::12.7mm

PCH OPI VCCAPLL FILTER/BYPASS

1

47UF

20%

4V

2

BYPASS=U0500.J18::12.7mm

47UF

20%

4V

47UF

20%

4V

1

2

1

2

C1271

CERM-X5R

0805-1

BYPASS=U0500.A20::6.35mm

C1276

CERM-X5R

0805-1

BYPASS=U0500.J18::6.35mm

PCH VCCACLKPLL FILTER/BYPASS

(PCH 1.05V ACLK PLL PWR)

PP1V05_S0_PCH_VCCACLKPLL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

1

C1272

1UF

10% 10V

2

X5R 402-1

PCH VCCCLK FILTER/BYPASS

(PCH 1.05V VCCCLK PWR)

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

1

C1277

1UF

10% 10V

2

X5R 402-1

12 8

31mA Max

8

??mA Max

B

(PCH 1.05V OPI PLL PWR)

PP1V05_S0_PCH_VCCAPLL_OPI

21

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

57mA Max

8

=PP1V05_S0_PCH_VCCPLL_HSIO

66

83mA Max

NO STUFF

C1280

47UF

20%

4V

CERM-X5R

0805-1

BYPASS=U0500.AA21::12.7mm

CRITICAL

L1290

2.2UH-240MA-0.221OHM

21

0603

C1290

47UF

20%

4V

CERM-X5R

0805-1

BYPASS=U0500.B11::12.7mm

NO STUFF

20%

4V

1

2

1

C1281

47UF

2

BYPASS=U0500.AA21::6.35mm

CERM-X5R

0805-1

NO STUFF

20%

4V

1

2

1

C1291

47UF

2

BYPASS=U0500.B11::12.7mm

CERM-X5R

0805-1

BYPASS=U0500.B11::6.35mm

1

C1282

1UF

10% 10V

2

X5R 402-1

PCH VCCSATA3PLL FILTER/BYPASS

(PCH 1.05V SATA3 PLL PWR)

PP1V05_S0_PCH_VCCSATA3PLL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

1

C1292

1UF

10% 10V

2

X5R 402-1

12 8

42mA Max

A

WPT-LP current estimates from Wildcat Point-LP PCH EDS, doc #515621, v1.0

These numbers may not be accurate as of 08/26/2014

8 7 5 4 2 1

www.qdzbwx.com

CRITICAL

L1295

2.2UH-240MA-0.221OHM

0603

BYPASS=U0500.B18::12.7mm

21

C1295

47UF

20%

4V

CERM-X5R

0805-1

NO STUFF

20%

4V

1

2

1

C1296

47UF

2

BYPASS=U0500.B18::6.35mm

CERM-X5R

0805-1

PCH VCCUSB3PLL FILTER/BYPASS

(PCH 1.05V USB3 PLL PWR)

PP1V05_S0_PCH_VCCUSB3PLL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

1

C1297

1UF

10% 10V

2

X5R 402-1

41mA Max

SYNC_MASTER=J117_ANDRES

PAGE TITLE

14 8

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

PCH Decoupling

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2014

051-00081

3.0.0

12 OF 123

11 OF 81

A

D

36

345678

2 1

D

C

66 13 8

=PPVRTC_G3_PCH

44

IN

R1300

20K

5%

1/20W

MF

201

C1300

1UF

10% 10V X5R

402-1

RTC_RESET_L

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 5 OF 19

RTCJTAG

AUDIO

SATA

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

(IPU)

SATA_IREF

RSVD

SATA_RCOMP

SATALED*RSVD

J5 H5

B15 A15

J8 H8

A17 B17

J6 H6

B14 C15

F5 E5

C17 D17

V1 U1 V6 AC1

A12

L11

K10

C12

U3

NC

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

NC

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<1>

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D_P<0>

SSD_XDP_PCIE3_SEL_L

SSD_XDP_PCIE2_SEL_L

SSD_XDP_PCIE1_SEL_L

SSD_XDP_PCIE0_SEL_L

73

PCH_SATA_RCOMP

PCH_SATALED_L

12

Port assignments:

IN

OUT

73 33

Primary HDD (SATA)

SSD Lane 2 (PCIe, unused)

IN

OUT

IN

OUT

73 32

16 12

SSD Lane 1 (PCIe)

SSD Lane 0 (PCIe)

PCIE = GND

SATA = 100K PU (3V3S0)

PP1V05_S0_PCH_VCCSATA3PLL

1

R1370

3.01K

1% 1/20W MF 201

2

PLACE_NEAR=U0500.C12:2.54mm

D

11 8

C

330K

5%

1/20W

MF

201

74 51

1

2

OUT

1

R1301

1M

5% 1/20W MF 201

2

PCH_INTRUDER_L

PCH_INTVRMEN

PCH_SRTCRST_L

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

R1310

R1311

R1312

R1313

33

100

33

74 17

74 51

IN

OUT

21

5% 201MF

PLACE_NEAR=U0500.AW8:6.35mm

21

PLACE_NEAR=U0500.AV11:6.35mm

21

PLACE_NEAR=U0500.AU8:6.35mm

IN

21

5% MF

PLACE_NEAR=U0500.AU11:6.35mm

PCH_CLK32K_RTCX1

PCH_CLK32K_RTCX2

HDA_BIT_CLK_R

74

1/20W

74

HDA_SYNC_R

74

HDA_RST_R_L

HDA_SDIN0

TP_HDA_SDIN1

67

HDA_SDOUT_R

74 17

1/20W 201

NC_PCH_I2S1_TXD

NC_PCH_I2S1_SFRM

NC_PCH_I2S1_SCLK

16

73 16

16

IN

OUT

IN

BI

XDP_PCH_TRST_L

XDP_PCH_TCK

XDP_PCH_TDI

XDP_PCH_TDO

XDP_PCH_TMS

PCH_JTAGX

AW5

AW8

AV11

201MF5% 1/20W

AY10 AU12

AU11

AW10

AV10

AU62

AE62

AD61

AE61

AD62

AL11

NC

AE63

NC

RTCX1

AY5

RTCX2

AU6

INTRUDER*

AV7

INTVRMEN

AV6

SRTCRST*

AU7

RTCRST*

HDA_BCLK/I2S0_SCLK

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST*/I2S_MCLK

(IPD-PLTRST#)

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

(IPD-PLTRST#)

HDA_DOCK_EN*/I2S1_TXD HDA_DOCK_RST*/I2S1_SFRM

AY8

I2S1_SCLK

PCH_TRST*

PCH_TCK

PCH_TDI

(IPD)

(IPU)

PCH_TDO

PCH_TMS

(IPU)

RSVD

AC4

RSVD

JTAGX

AV2

(IPD)

1

2

1

2

1

R1303

20K

5% 1/20W MF 201

2

1

C1303

1UF

10% 10V

2

X5R 402-1

R1302

B

NOTE: Haswell ULT requires that CLQREQ_n be mapped to ROOT_PORT_n+1

to properly support CLKREQs for PCIE devices.

72 31

31 12

72 34

34 12

OUT

IN

OUT

IN

TP_PCIE_CLK100M_FWN

67

TP_PCIE_CLK100M_FWP

67

PCIE_CLKREQ0_L

12

TP_PCIE_CLK100M_CAMERAN

67

TP_PCIE_CLK100M_CAMERAP

67

PCIE_CLKREQ1_L

12

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP_P

AP_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

ENETSD_CLKREQ_L

C43 C42

U2

B41 A41

Y5

C41 B42

AD1

B38 C37

N1

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

SYM 6 OF 19

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

PCIECLKRQ3*/GPIO21

BGA

XTAL24_IN

XTAL24_OUT

CLOCK SIGNALS

DIFFCLK_BIASREF

TESTLOW TESTLOW TESTLOW TESTLOW

RSVD RSVD

A25 B25

K21 M21

C26

C35 C34 AK8 AL8

NC

PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT

PCH_DIFFCLK_BIASREF

PCH_TESTLOW_C35

PCH_TESTLOW_C34

PCH_TESTLOW_AK8

PCH_TESTLOW_AL8

IN

OUT

74 17

PP1V05_S0_PCH_VCCACLKPLL

1

R1380

3.01K

1% 1/20W MF 201

2

PLACE_NEAR=U0500.C26:2.54mm

R1390 R1391 R1392 R1393

10K

11 8

B

21

5%

21

5%

21

5%

1/20W MF 201

MF1/20W5% 201

MF 2011/20W

201MF1/20W

A

=PP3V3_S0_PCH_GPIO

R1320 R1321 R1322 R1323 R1324 R1325 R1326 R1327 R1328 R1329 R1330

100K

1K

66 27 16 15 13

21

5% 2011/20W

21

5% 1/20W 201

21

5% 1/20W MF 201

21

1/20W 201MF5%

MF1/20W

MF

1/20W5% 201

1/20W

MF

MF1/20W 2015%

MF5% 201

MF1/20W5% 201

PCH_SATALED_L

ENETSD_CLKREQ_L

2015%

PCIE_CLKREQ1_L

2015% 1/20W

AP_CLKREQ_L

PCIE_CLKREQ0_L

TBT_CLKREQ_L

SSD_CLKREQ_L

SSD_XDP_PCIE3_SEL_L

SSD_XDP_PCIE2_SEL_L

SSD_XDP_PCIE1_SEL_L

2015% MF1/20W

SSD_XDP_PCIE0_SEL_L

12

72 26

26 12

72 32

32 12

34 12

31 12

26 12

32 12

16 12

OUT

IN

OUT

IN

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

PCIE_CLK100M_SSD_N

PCIE_CLK100M_SSD_P

SSD_CLKREQ_L

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4*/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5*/GPIO23

CLKOUT_LPC_0

CLKOUT_LPC_1

(IPD-PWROK)

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

AN15

AP15

B35 A35

LPC_CLK24M_SMC_R

TP_LPC_CLK24M_LPCPLUS

CKPLUS_WAIVE=NO_TEST

NC_ITPXDP_CLK100MN

NC_ITPXDP_CLK100MP

OUT

74 17

SYNC_MASTER=J117_TONY

PAGE TITLE

SYNC_DATE=05/05/2014

A

PCH Audio/JTAG/SATA/CLK

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

13 OF 123

SHEET

12 OF 81

D

8 7 5 4 2 1

36

345678

2 1

D

44

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

R1402

IN

SMC_PCH_SUSACK_L

0

1 2

5%

1/20W

MF

0201

NOSTUFF

43

OUT

R1400/2 kept for debug purposes.

PCH_SUSACK_L

PM_SYSRST_L

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PM_PCH_APWROK

PLT_RESET_L

PM_RSMRST_PCH_L

R1400

0

5%

1/20W

MF

0201

43 17

65 44 16

1

65 16

2

71 18

65 16 13

16 15

65

IN

OUT

IN

PCH_SUSWARN_L

43 16 13

IN

PM_PWRBTN_L

PCH_GPIO31

13

PM_BATLOW_L

13 13

AK2

AC3

AG2

AY7

AB5

AG7

AW6

AV4

AL7

AJ8

AN4

SYSTEM POWER MANAGEMENT

SUSACK*

(IPU)

SYS_RESET*

SYS_PWROK

PCH_PWROK

APWROK

PLTRST*

RSMRST*

SUSWARN*/SUSPWRDNACK/GPIO30

PWRBTN*

ACPRESENT/GPIO31

(IPU)

(IPD-DeepSx)

BATLOW*/GPIO72

SYM 8 OF 19

(IPD-DeepSx)

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

AW7

AV5

AJ5

V5

AG4

AE6

AP5

AJ6

AT4

AL5

AP4

PCH_DSWVRMEN

PM_RSMRST_PCH_L

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

NC_PM_SLP_A_L

PM_SLP_SUS_L

IN

BI

OUT

35 31 18 13

43 13

43

74 44

64 43 31 13

64 43 13

65 64 44 43 35 13

=PPVRTC_G3_PCH

1

R1450

330K

5% 1/20W MF 201

2

IN

1

R1451

100K

5% 1/20W MF 201

2

66 12 8

D

65 16 13

C

27 13

76 43 13

NC_PM_SLP_S0_L

NC_PCH_SLP_WLAN_L

AM5

SLP_S0*

SLP_WLAN*/GPIO29

SLP_LAN*

AJ7AF3

NC_PCH_SLP_LAN_L

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 9 OF 19

NC_EDP_BKLT_PWM

EDP_BKLT_EN

13

EDP_PANEL_PWR

13

IN

TBT_PWR_REQ_L

SMC_RUNTIME_SCI_L

PCH_GPIO79

13

PCH_GPIO80

13

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA*/GPIO77

P4

PIRQB*/GPIO78

N4

PIRQC*/GPIO79

N2

PIRQD*/GPIO80

eDP

SIDEBAND

DISPLAY

DDPB_CTRLCLK

DDPB_CTRLDATA

(IPD-PLTRST#)

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPB_AUXN DDPC_AUXN

DDPB_AUXP

NC_PCI_PME_L

AD4

PME*

(IPU)

PCI

DDPC_AUXP

B9 C9

D9 D11

C5 B6

B5 A6

DP_TBTSNK0_DDC_CLK

DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_CLK

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_P

OUT

BI

OUT

BI

80 30

80 26

C

B

=PP3V3_S5_PCH_GPIO

R1405 R1410 R1452

R1453

1K

10K

100K

1 2

66 50 15

1/20W

U7

L1 L3

R5

L4

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

DDPB_HPD

DDPC_HPD

EDP_HPD

C8

A8

D6

DP_TBTSNK0_HPD_BUF

DP_TBTSNK1_HPD_BUF

DP_INT_HPD

18

IN

18

IN

40

IN

36 34 13

13

50 40 13

OUT

13

PCH_GPIO55

DP_TBT_SEL

ENET_LOW_PWR

BRD_ID

AP_PCIE_DEV_WAKE

B

MF 2015%

MF5% 2011/20W

PM_BATLOW_L

PCIE_WAKE_L

PCH_GPIO31

PM_PWRBTN_L

MF1/20W5%

201

43 16 13

13

35 31 18 13

13

A

=PP3V3_S0_PCH_GPIO

R1455

R1440 R1441 R1442 R1443

R1448

R1460 R1461 R1462 R1464 R1430 R1431 R1445 R1446 R1447 R1449

10K

100K

10K

100K

1 2

1

1 2

66 27 16 15 12

1/20W5% MF

1/20W

1/20W MF

1/20W

5% 2011/20W MF

2

5% 2011/20W MF

2

5% 2011/20W MF

MF 2015%

MF1/20W 2015%

MF 2015%

MF1/20W 2015%

MF1/20W5% 201

PM_CLKRUN_L

201

TBT_PWR_REQ_L

SMC_RUNTIME_SCI_L

PCH_GPIO79

PCH_GPIO80

2015%

BRD_ID

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

PM_SLP_SUS_L

EDP_BKLT_EN

EDP_PANEL_PWR

PCH_GPIO55

DP_TBT_SEL

ENET_LOW_PWR

AP_PCIE_DEV_WAKE

43 13

27 13

76 43 13

13

64 43 31 13

64 43 13

65 64 44 43 35 13

13

50 40 13

36 34 13

13

www.qdzbwx.com

SYNC_MASTER=J117_ANDRES SYNC_DATE=03/24/2014

PAGE TITLE

PCH PM/PCI/GFX

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

14 OF 123

SHEET

13 OF 81

D

A

8 7 5 4 2 1

36

PCIe Port Assignments:

CRITICAL

OMIT_TABLE

345678

2 1

USB Port Assignments:

D

C

Thunderbolt lane 0

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

AirPort

Ethernet

USB3 Port Assignments:

Ext C (SS)

Ext D (SS)

72 26

72 31

72 34

75 42

PP1V05_S0_PCH_VCCUSB3PLL

11 8

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

72

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_P<3>

PCIE_AP_D2R_N

PCIE_AP_D2R_P

PCIE_AP_R2D_C_N

PCIE_AP_R2D_C_P

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

USB3_EXTC_D2R_N

USB3_EXTC_D2R_P

USB3_EXTC_R2D_CF_N

USB3_EXTC_R2D_CF_P

USB3_EXTD_D2R_N

USB3_EXTD_D2R_P

USB3_EXTD_R2D_CF_N

USB3_EXTD_R2D_CF_P

PCH_PCIE_RCOMP

R1500

PLACE_NEAR=U0500.A27:6.35mm

3.01K

1%

1/20W

MF

201

F10 E10

C23 C22

F8 E8

B23 A23

PERN5_L0 PERP5_L0

PETN5_L0 PETP5_L0

PERN5_L1 PERP5_L1

PETN5_L1 PETP5_L1

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 11 OF 19

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

H10

PERN5_L2

G10

B21

C21

E6 F6

B22 A21

PERP5_L2

PETN5_L2 PETP5_L2

PERN5_L3 PERP5_L3

PETN5_L3 PETP5_L3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7

G11

F11

C29

B30

PERN3 PERP3

PETN3 PETP3

PCI-E

USB

USB2P7

(IPD)

USB3RN1

USB3RP1

F13

G13

B29 A29

PERN4 PERP4

PETN4 PETP4

USB3TN1 USB3TP1

USB3RN2

USB3RP2

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

NC

1

2

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27 AV3

PCIE_IREF

USB3TN2 USB3TP2

USBRBIAS*

USBRBIAS

RSVD RSVD

OC0*/GPIO40 OC1*/GPIO41 OC2*/GPIO42 OC3*/GPIO43

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11

AN10 AM10

AL3 AT1 AH2

NC

USB_EXTA_N

USB_EXTA_P

USB_EXTB_N

USB_EXTB_P

USB_EXTC_N

USB_EXTC_P

USB_EXTD_N

USB_EXTD_P

USB_CAMERA_N

USB_CAMERA_P

USB_BT_N

USB_BT_P

NC

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_CF_N

USB3_EXTA_R2D_CF_P

USB3_EXTB_D2R_N

USB3_EXTB_D2R_P

USB3_EXTB_R2D_CF_N

USB3_EXTB_R2D_CF_P

75

PCH_USB_RBIAS

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

BI

IN

OUT

IN

OUT

IN

75 41

75 42

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

Ext C (LS/FS/HS)

D

75 42

75 37

75 31

75 41

16 14

Ext D (LS/FS/HS)

Camera

BT

USB3 Port Assignments:

Ext A (SS)

Ext B (SS)

PLACE_NEAR=U0500.AJ10:6.35mm

1

R1570

22.6

1% 1/20W MF 201

2

C

CRITICAL

OMIT_TABLE

B

74 43

BI

OUT

LPC_AD<0>

LPC_AD<1>

LPC_AD<2>

LPC_AD<3>

LPC_FRAME_L

R1540 R1541 R1542 R1543

R1544

100

21

5% 1/20W 201MF

21

5% 1/20W 201MF

21

1/20W5% 201MF

201MF5% 1/20W

MF5% 1/20W 201

74 45

45 14

45

OUT

BI

74

LPC_AD_R<0>

74

LPC_AD_R<1>

74

LPC_AD_R<2>

LPC_AD_R<3>

74

LPC_FRAME_R_L

74

SPI_CLK_R

SPI_CS0_R_L

NC_SPI_CS1_L

NC_SPI_CS2_L

SPI_MOSI_R

SPI_MISO_R

SPI_IO_R<2>

SPI_IO_R<3>

AU14

AW12

AY12

AW11

AV12

AA3

Y7

Y4

AC2

AA2

AA4

Y6

AF1

(IPU)

LAD1 LAD2 LAD3

LFRAME*

SPI_CLK

(IPU)

SPI_CS0*

(IPU)

SPI_CS1*

(IPU)

SPI_CS2*

(IPU)

SPI_MOSI

(IPU/IPD)

SPI_MISO

(IPU)

SPI_IO2

(IPU)

SPI_IO3

(IPU)

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 7 OF 19

LPC

SMBUS

SML1ALERT*/PCHHOT*/GPIO73

SPI

(IPU/IPD)

C-LINK

SMBALERT*/GPIO11LAD0

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1DATA/GPIO74

(IPU/IPD)

CL_CLK

CL_DATA

CL_RST*

AN2

AP2 AH1

AL2

AN1 AK1

AU4

AU3 AH3

AF2

AD2

AF4

PCH_SMBALERT_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

WOL_EN

SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L

SML_PCH_1_CLK

SML_PCH_1_DATA

NC_CLINK_CLK

NC_CLINK_DATA

NC_CLINK_RESET_L

14

OUT

BI

OUT

BI

OUT

BI

46

76 46

35 14

76 46

B

A

=PP3V3_SUS_PCH_GPIO

R1579 R1580 R1581 R1582 R1583 R1590

100K

=PP3V3_SUS_PCH_VCC_SPI

R1548 R1549

R1591

100K

1K

21

5% MF1/20W 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5%

21

1/20W MF

5% 201

1/20W MF 2015%

MF 2011/20W5%

MF1/20W

66

PCH_SML1ALERT_L

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

201MF1/20W

PCH_SMBALERT_L

2015%

66 11 8

SPI_IO_R<2>

SPI_IO_R<3>

WOL_EN

14

16 14

14

45 14

www.qdzbwx.com

35 14

SYNC_MASTER=J117_ANDRES

PAGE TITLE

PCH PCIe/USB/LPC/SPI/SMBus

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=03/24/2014

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

15 OF 123

SHEET

14 OF 81

A

8 7 5 4 2 1

36

345678

2 1

D

C

71 18 16 15 13

GPIO12:

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

Required JTAG pullups are on the XDP connector page.

66 57 17 16 8 6

CRITICAL

OMIT_TABLE

IN

PLT_RESET_L

36

OUT

R1603

26

OUT

32

OUT

100K

5%

1/20W

MF

201

1

2

R1606

100K

5%

1/20W

MF

201

1

2

R1604

1/20W

201

1K

5%

MF

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 10 OF 19

16 15

16 15 15 3

16 15

BI

26

BI

IN OUT

IN

MLB_RAMCFG4

MLB_RAMCFG0

HDMITBTMUX_SEL_TBT

NC_MEM_VDD_SEL_1V5_L

XDP_LPCPLUS_GPIO

XDP_PCH_GPIO17

NO_TEST=1

ENET_SD_RESET_L

76 43 15

75 34 15

63 15

IN

OUT

SMC_WAKE_SCI_L

TPAD_SPI_INT_L

15

ENET_MEDIA_SENSE

SSD_PWR_EN

PCH_TBT_PCIE_RESET_L

63 15

16 15

26 15

18 16

18 16 15

18 15

1

16 15

2

74 45 15

15

OUT

BI

OUT

BI

HDD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

SD_PWR_EN

15

TBT_PWR_EN

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

JTAG_TBT_TMS_PCH

PCH_HSIO_PWR_EN

15

TPAD_SPI_IF_EN

15

MLB_RAMCFG3

SPIROM_USE_MLB

SSD_RESET_L

32 15

16 15

OUT

BI

SSD_SR_EN_L

MLB_RAMCFG1

MLB_RAMCFG2

PCH_GPIO33

15

P1

AU2

AM7

AD6

Y1

T3

AD5

AN5

AD7

AN3

AG6

AP1

AL4

AT5

AK4

AB6

U4

Y3

P3

Y2

AT3

AH4

AM4

AG5

AG3

AM3

AM2

P2

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

(IPD-RSMRST#)

GPIO16

GPIO17

GPIO24

GPIO27

(IPD-DeepSx)

GPIO28

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO44

GPIO47

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO14

GPIO25

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0/GPIO33

(IPD)

(IPD-PLTRST#)

(IPD)

LPIO

GPIO

CPU/MISC

GSPI0_MISO/GPIO85

GSPI0_MOSI/GPIO86

GSPI1_MISO/GPIO89

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

THERMTRIP*

RCIN*/GPIO82

SERIRQ

PCH_OPI_COMP

RSVD RSVD

GSPI0_CS*/GPIO83

GSPI0_CLK/GPIO84

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI_MOSI/GPIO90

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST*/GPIO2

UART1_CTS*/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

D60

V4

T4

AW15

AF20 AB21

R6

L6

N6

L8

R7

L5

N7

K2

J1

K3

J2

G1

K4

G2

J3

J4

F2

F3

G4

F1

E3

F4

=PP1V05_S0_CPU_VCCST

PM_THRMTRIP_L

TBT_CIO_PLUG_EVENT_L

LPC_SERIRQ

PCH_OPI_COMP

NC

MEM_GOOD_LED

PCH_CAM_RESET_L

PCH_CAM_EXT_BOOT

AUD_SPI_MOSI

PCH_GSPI1_CS_L

SDCONN_OC_L

PCH_GSPI1_MISO

PCH_GSPI1_MOSI

AP_S0IX_WAKE_L

HDMITBTMUX_FLAG_L

PCH_BT_UART_RTS_L

PCH_BT_UART_CTS_L

PCH_UART1_RXD

PCH_UART1_TXD

JTAG_ISP_TDO

PCH_UART1_CTS_L

PCH_GPIO4

AP_RESET_L

PCH_I2C1_SDA

PCH_I2C1_SCL

TBT_POC_RESET_L

BT_PWR_RST_L

R1600

1K

5%

1/20W

MF

201

1

2

OUT

IN

BI

71 44

26 15

43 15

Pull-up/down on chipset support page (depends on TBT controller)

Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.

Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

D

PLACE_NEAR=U0500.AW15:12.7mm

1

R1601

49.9

1% 1/20W MF 201

2

27

38 15

36 15

PLT_RESET_L

1

R1602

18 15

100K

5% 1/20W MF 201

2

IN

OUT

31

71 18 16 15 13

C

Pull-up on TBT page

OUT

15

IN

15

IN

15

OUT

15

B

A

66 27 16 15 13 12

=PP3V3_S5_PCH_GPIO

=PP3V3_S4_PCH_GPIO

=PP3V3_S0_PCH_GPIO

R1628

R1624 R1634

R1609

R1611 R1618 R1621 R1625 R1630 R1632 R1633 R1635 R1637

R1617

R1629 R1615 R1619 R1620 R1614 R1613

R1616 R1612 R1622

R1623 R1626

R1631 R1636 R1638

100K

10K

100K

1

1 2

1

1 2

1

1 2

1

1 2

1

1 2

2

5%

2

5% 201MF1/20W

21

5%

2

5% MF1/20W 201

21

2

5% 201MF

2

5%

2

5% MF 201

5% 1/20W 201

5% 1/20W MF

5% 2011/20W MF

2

5% 1/20W 201MF

5% 201MF

5%

1/20W5%

1/20W

1/20W 201

1/20W5% MF 201

1/20W 201MF

1/20W5% MF

1/20W MF

1/20W 201MF5%

1/20W

1/20W 201MF5%

1/20W

1/20W 201MF

MF5%

MF1/20W 2015%

MF5%

MF5% 1/20W

MF

MF1/20W5% 201

MF1/20W 201

OUT

C4

SDIO_POWER_EN/GPIO70 SDIO_D0/GPIO66

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

(IPD-PLTRST#)

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D3/GPIO69

RAM Configuration Straps

For chip-down RAM systems

66 27 16 15 13 12

MLB_RAMCFG0

MLB_RAMCFG1

MLB_RAMCFG2

MLB_RAMCFG3

MLB_RAMCFG4

=PP3V3_S0_PCH_GPIO

RAMCFG4:H

R1688

100K

5%

1/20W

MF

201

RAMCFG4:L

R1689

10K

5%

1/20W

MF

201

RAMCFG3:H

1

2

RAMCFG3:L

1

2

R1680

100K

5%

1/20W

MF

201

R1684

10K

5%

1/20W

MF

201

1

2

1

2

RAMCFG2:H

RAMCFG2:L

AP_S0IX_WAKE_SEL

15

PCH_GPIO38

15

PCH_GPIO39

R1605

1K

2

1/20W

66 50 13

66 42 41 18

66 27 16 15 13 12

PCH_GPIO38

201MF

JTAG_TBT_TMS_PCH

201MF

JTAG_ISP_TDO

TBT_CIO_PLUG_EVENT_L

XDP_LPCPLUS_GPIO

HDD_PWR_EN

TBT_PWR_EN

PCH_HSIO_PWR_EN

PCH_GPIO33

201MF1/20W5%

PCH_GPIO39

201

LPC_SERIRQ

BT_PWR_RST_L

2015%

LCD_IRQ_L

SSD_PWR_EN

SSD_SR_EN_L

2011/20W MF

TPAD_SPI_INT_L

201

XDP_SDCONN_STATE_CHANGE_L

SD_PWR_EN

201

SMC_WAKE_SCI_L

SPIROM_USE_MLB

201

PCH_GPIO67

XDP_PCH_GPIO17

XDP_JTAG_ISP_TCK

2015% 1/20W MF

XDP_JTAG_ISP_TDI

TPAD_SPI_IF_EN

AP_S0IX_WAKE_SEL

ENET_MEDIA_SENSE

LCD_PSR_EN

5%

MF

201

1

15

PCH_TCO_TIMER_DISABLE=PP3V3_S0_PCH_GPIO

18 15

TBTLC for CR, S0 for RR

18 15

26 15

16 15

63 15

26 15

43 15

63 15

32 15

16 15

76 43 15

74 45 15

16 15

18 16 15

75 34 15

16 15

D3

E4

C3

E2

R1681

100K

5%

1/20W

MF

201

R1685

10K

5%

1/20W

MF

201

RAMCFG1:H

1

2

RAMCFG1:L

1

2

PCH_STRP_TOPBLK_SWP_L

PCH_GPIO67

LCD_IRQ_L

LCD_PSR_EN

RAMCFG0:H

R1682

100K

5%

1/20W

MF

201

1

2

R1683

100K

1/20W

201

RAMCFG0:L

10K

5%

1/20W

MF

201

1

R1687

10K

1/20W

2

201

R1686

5%

MF

5%

MF

44

IN

15

1

2

1

Requires connection to SMC via 1K series R

AP_S0IX_WAKE_L

15

HDMITBTMUX_FLAG_L

15

PCH_I2C1_SDA

15

PCH_I2C1_SCL

15

PCH_UART1_TXD

15

PCH_GSPI1_CS_L

15

PCH_GSPI1_MOSI

15

PCH_GPIO4

15

36 15

38 15

SDCONN_OC_L

AUD_SPI_MOSI

15

MEM_GOOD_LED

15 3

PCH_CAM_RESET_L

PCH_CAM_EXT_BOOT

PCH_BT_UART_RTS_L

15

PCH_BT_UART_CTS_L

15

PCH_UART1_RXD

15

PCH_UART1_CTS_L

15

PCH_GSPI1_MISO

15

PAGE TITLE

NOSTUFF

R1658 R1659

R1666 R1667

R1661 R1654 R1653 R1664 R1651

R1657 R1650 R1668 R1669

R1670 R1671 R1660 R1663 R1652

66 27 16 15 13 12

100K

47K

100K

47K

1 2

1

=PP3V3_S0_PCH_GPIO

1/20W

1/20W5%

5% MF1/20W 201

1/20W5%

1/20W MF5% 201

5% 1/20W MF 201

5% MF1/20W 201

2

5% MF

1/20W

1/20W 201

MF5% 201

MF 2011/20W5%

MF5%

MF5% 201

MF 201

MF1/20W5% 201

MF5% 1/20W

MF5% 1/20W 201

MF1/20W5%

MF5% 201

2011/20W

201MF

201

201MF1/20W5%

201

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

B

A

PCH GPIO/MISC/LPIO

2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

16 OF 123

SHEET

15 OF 81

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

Extra BPM Testpoints

73 6

71 17 8

43 13

65 44 13

73 16 6

16 12

IN

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<6>

XDP_BPM_L<7>

IN

OUT

CPU_VCCST_PWRGD

PM_PWRBTN_L

PM_PCH_SYS_PWROK

XDP_CPU_TCK

PCH_JTAGX

1

TP-P6

1

TP-P6

1

TP-P6

1

TP-P6

1

TP-P6

1

TP-P6

TP

TP1802

TP1803

TP1804

TP1805

TP1806

TP1807

PLACE_NEAR=U0500.C61:12.7mm

R1800

R1802

PLACE_NEAR=U5000.J3:12.7mm

R1804

R1835

1K

0

220

0

XDP

21

5% 2011/20W MF

21

5%

1/20W MF

21

5%

21

PLACE_NEAR=J1800.58:28mm

1/20W 0201

5% MF

PCH XDP Signals

These signals do not connect to XDP connector in this architecture, only accessible

via Top-Side Probe. Nets are listed here to show XDP associations and to make clear

what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

Non-XDP Signals

USB_EXTA_OC_L

USB_EXTB_OC_L

USB_EXTC_OC_L

USB_EXTD_OC_L

MLB_RAMCFG0

MLB_RAMCFG1

MLB_RAMCFG2

MLB_RAMCFG3

MLB_RAMCFG4

SDCONN_STATE_CHANGE_L

16 14

16 15

OUT

IN

16

OUT

PCH/XDP Signals

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTD_OC_L

MAKE_BASE=TRUE

XDP_MLB_RAMCFG0

MAKE_BASE=TRUE

XDP_MLB_RAMCFG1

MAKE_BASE=TRUE

XDP_MLB_RAMCFG2

MAKE_BASE=TRUE

XDP_MLB_RAMCFG3

MAKE_BASE=TRUE

XDP_MLB_RAMCFG4

MAKE_BASE=TRUE

XDP_SDCONN_STATE_CHANGE_L

MAKE_BASE=TRUE

MLB_RAMCFGx GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

0201

MF-LF1/16W 402

PCH_JTAGX_R

IN

BI

IN

=PP1V05_S0_XDP

66 16

XDP_CPU_PREQ_L CPU_CFG<17>

BI

XDP_CPU_PRDY_L

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<2>

CPU_CFG<3>

XDP_BPM_L<0>

XDP_BPM_L<1>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7> CPU_CFG<15>

71

XDP_CPU_VCCST_PWRGD

16

XDP_CPU_PWRBTN_L

CPU_PWR_DEBUG

73 6

71 6

73 6

8

6

IN

OUT

XDP_SYS_PWROK

46 16

BI

IN

=SMBUS_XDP_SDA

=SMBUS_XDP_SCL

TP_XDP_TCK1

PLACE_NEAR=J1800.48:28mm

1

TP

TP1888

TP-P6

41

42

15

36

65 13

16 15

IN

73 16 12

www.qdzbwx.com

XDP

C1804

0.1UF

10%

6.3V

CERM-X5R

0201

16 14

OUT

46 16

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

XDP_SDCONN_STATE_CHANGE_L

XDP_MLB_RAMCFG1

16

XDP_MLB_RAMCFG2

16

XDP_MLB_RAMCFG3

16

PM_RSMRST_PCH_L

XDP_CPU_PWRBTN_L

16

=SMBUS_XDP_SDA

=SMBUS_XDP_SCL

XDP_PCH_TCK

PPVCCIO_S0_CPU

8

1

2

PLACE_NEAR=U0500.AA63:50mm

XDP

1

2

1

R1831

1K

5% 1/16W MF-LF 402

2

XDP_CPU_PRESENT_L

R1883

1K

1/20W

R1832

150

5% 1/16W MF-LF 402

XDP_CPU_OBSAB

=PP3V3_S5_XDP

66

12

MF5% 201

OMIT

1

XW1800

SHORT

402

2

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_B0

OBSDATA_B1

OBSDATA_B2

OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

1

XW1850

SHORT

402

2

XDP_PM_RSMRST_PCH_L

XDP_PCH_OBSAB

HOOK1

HOOK2

HOOK3

SDA

SCL

TCK1

TCK0

XDP

10%

6.3V

0201

1

2

C1800

0.1UF

CERM-X5R

OMIT

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_B0

OBSDATA_B1

OBSDATA_B2

OBSDATA_B3

VCC_OBS_AB

C1850

CERM-X5R

CPU Micro2-XDP

CRITICAL

XDP_CONN

J1800

DF40RC-60DP-0.4V

M-ST-SM1

62

2 1

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

30 29

32 31

34 33

36 35

38 37

40 39

42 41

44 43

46 45

48 47

50 49

52 51

54 53

56 55

58 57

60 59

64 63

518S0847

61

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0

OBSFN_D1

OBSDATA_D0

OBSDATA_D1

OBSDATA_D2

OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

TDO

TRSTn

TDI

TMS

XDP_PRESENT#

XDP

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R 0201

PCH Micro2-XDP

CRITICAL

XDP_CONN

J1850

DF40RC-60DP-0.4V

M-ST-SM1

62

2 1

NC

HOOK0 HOOK4

HOOK1

HOOK2

HOOK3

NC

SDA

SCL

TCK1

NC

TCK0

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

30 29

32 31

34 33

36 35

38 37

40 39

42 41

44 43

46 45

48 47

50 49

52 51

54 53

56 55

58 57

60 59

XDP

0.1UF

10%

6.3V

0201

1

2

64 63

61

NC

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0

OBSFN_D1

OBSDATA_D0

OBSDATA_D1

OBSDATA_D2

OBSDATA_D3

HOOK5

VCC_OBS_CD

HOOK6

HOOK7

TDO

TRSTn

TDI

TMS

XDP

1

C1851

0.1UF

10%

6.3V

2

CERM-X5R 0201

NOTE: This is not the standard XDP pinout.

Use with 921-0133 Adapter Flex to

support chipset debug.

OMIT

1

XW1801

SHORT

402

2

IN

CPU_CFG<16>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<19>

CPU_CFG<18>

CPU_CFG<12>

CPU_CFG<13>

CPU_CFG<14>

IN

NC

XDP_CPU_OBSCD

XDP_CPURST_L

XDP_DBRESET_L

OUT

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

XDP_CPU_TDO

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

XDP

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R 0201

PLACE_NEAR=J1800.47:28mm

IN

OUT

66 65 64 63 17

XDP_MLB_RAMCFG0

XDP_JTAG_ISP_TCK

SSD_XDP_PCIE3_SEL_L

SSD_XDP_PCIE2_SEL_L

SSD_XDP_PCIE1_SEL_L

SSD_XDP_PCIE0_SEL_L

XDP_LPCPLUS_GPIO

XDP_PCH_GPIO17

XDP_MLB_RAMCFG4

XDP_JTAG_ISP_TDI

=PP1V05_S0_XDP

=PP3V3_S0_PCH_GPIO

66 27 15 13 12

XDP_PM_PCH_PWROK

XDP_DBRESET_L

XDP_PCH_TDO

XDP_PCH_TRST_L_R

XDP_PCH_TDI

XDP_PCH_TMS

PLACE_NEAR=J1850.47:28mm

XDP

1

C1852

0.1UF

10%

6.3V

2

CERM-X5R 0201

73 6

66 57 17 15 8 6

=PP1V05_S0_CPU_VCCST

D

XDP

73 6

73 16 6

XDP_CPU_TDO

R1810

PLACE_NEAR=J1800.51:28mm

51

21

MF 2015% 1/20W

XDP

73 6

73 16 6

XDP_CPU_TRST_L

XDP_CPU_TCK

TDI and TMS are terminated in CPU.

R1811

PLACE_NEAR=U0500.E59:28mm

R1813

PLACE_NEAR=U0500.E60:28mm MF1/20W 2015%

51

XDP

51

12

MF1/20W 2015%

12

XDP

R1805

17 16

73 16 6

73 6

1K

21

PLT_RESET_L

5% 2011/20W MF

PLACE_NEAR=U0500.AG7:12.7mm

IN

71 18 15 13

C

1.05V S5 LDO

Power to the JTAG debug lines

=PP3V3_S5_PWRCTL

U1830

TPS720105

SON

BIAS

CRITICAL

XDP

1

IN

EN

GND

5

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500

PLACE_NEAR=U0500.AE62:28mm

PLACE_NEAR=U0500.AU62:28mm

65 13

16 12

CPU/PCH Merged XDP

Apple Inc.

R

OUT

THRM

PAD

7

R1896

R1897

2

NC

1

R1890

51

1% 1/20W MF 201

2

XDP

51

NC

1

R1891

51

1% 1/20W MF 201

2

XDP

NOSTUFF

PP1V05_S5

1

C1831

2.2UF

10%

6.3V

2

X5R 402

XDP

1

R1892

51

1% 1/20W MF 201

2

XDP

12

5% MF

12

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

77 16

NOSTUFF

1

R1899

1K

1% 1/20W MF 201

2

1/20W 201

1/20W5% 201MF

SYNC_DATE=03/24/2014

051-00081

3.0.0

18 OF 123

16 OF 81

B

A

D

16

12

15

16

IN

OUT

IN

OUT

XDP

1

C1830

0.1UF

10% 16V

2

X7R-CERM 0402

1

R1833

150

5% 1/16W MF-LF 402

2

PM_EN_REG_P1V05_S5

4

6

3

XDP

1

C1832

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V05_S5

77 16

18 15

73 16 12

16 12

15

18 15

66 16

73 16 12

XDP_PCH_TCK

XDP_PCH_TRST_L

16 12

XDP_PCH_TDO

XDP_PCH_TDI

XDP_PCH_TMS

PCH_JTAGX

R1881

1K

17 16

5%

73 16 12

1/20W

R1882

0

5%

73 16 12

1/20W

12

MF

NOSTUFF

MF

201

0201

PM_PCH_PWROK

XDP_PCH_TRST_L

SYNC_MASTER=J117_ANDRES

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8 7 5 4 2 1

36

345678

2 1

D

PPVBATT_G3_RTC

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

2 1

Coin-Cell Holder

R1902

1K

5% 1/16W MF-LF

402

RTC Power Sources

=PP3V3_G3H_RTC_D

66

PPVBATT_G3_RTC_R

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

D1900

BAT54DW-X-G

SOT-363

PP3V3_G3_RTC_SW

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

OMIT

NC NC

TP1900

1.97X2.02MM-NSP

SMT-PAD

1

OMIT

1

4

5

NC NC

6

3

2

TP1901

1.97X2.02MM-NSP

SMT-PAD

1

Place TP1901 on bottom side

SMC_ASSERT_RTCRST

44

RTCRST:Y

R1930

10K

1 2

5% 1/16W MF-LF

402

SMC_ASSERT_RTCRST_R

OMIT_TABLE

20%

10V

CERM

402

1

2

C1931

0.1UF

CRITICAL

Q1930

NTR4101P

SOT-23-HF

2

S D

G

1

3

C1930

0.1UF

20%

10V

CERM

402

ALL_SYS_PWRGD/CPU_VCCST_PWRGD Level-Shifter

=PP3V3_S5_PWRCTL

16 63 64 65 66

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

1

66

6

VCC

U1972

74AUP1G07GF

SOT891

4

YA

5

NCNC

10% 16V

0201

1

2

NC NC

1

C1972

0.1UF

X5R-CERM

3 43 65

IN

ALL_SYS_PWRGD

GND

2

3

=PP1V05_S0_CPU_VCCST

1

R1972

10K

5% 1/20W MF 201

2

CPU_VCCST_PWRGD

6 8 15 16 57 66

8 16 71

OUT

D

C

1

J1900

BAT-HLDR-RCPT-J94-J95

SM

2

APN:998-6925

12 74

IN

12 74

OUT

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PART# DESCRIPTIONQTY

CAP,0.1 UF,402 C1931132S1059 1 RTCRST:Y

PCH RTC Crystal

R1910

0

R1911

10M

5%

1/20W

MF1 201

1 2

5%

1

2

1/20W

MF

0201

PCH_CLK32K_RTCX2_R

74

32.768K-20PPM-12.5PF

CRITICAL

Y1910

2012-1

C1931RES,10K OHM,4021116S0090 RTCRST:N

PLACE_NEAR=Y1910.2:2MM

C1910

20PF

1 2

5%

25V

2

1

PLACE_NEAR=Y1910.1:2MM

C0G

0201

C1911

20PF

1 2

5% 25V C0G

0201

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

=PP5V_S0_PCH_STRAP

TABLE_5_ITEM

PCH ME Disable Strap

=PP1V5_S0_PCH_VCCSUSHDA

8 11 66

43

IN

SPI_DESCRIPTOR_OVERRIDE_L

Q1920

DMN5L06VK-7

SOT563

D

3

DMN5L06VK-7

Q1920

SOT563

VER 3

2

5

GS

4

G S

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE

6

D

1

66

1

R1920

100K

5% 1/20W MF 201

2

1

R1921

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

IPD = 9-50k

OUT

C

12 74

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

B

PCH 24MHz Crystal

C1915

2.2PF

1 2

+/-0.05PF

25V

C0G-CERM

0201

NC

PCH_CLK24M_XTALOUT_R

74

CRITICAL

13

NC

24

NC

Y1915

3.20X2.50MM-SM1

24.000MHZ-20PPM-6PF

C1916

2.2PF

1

2

+/-0.05PF

25V

C0G-CERM

0201

TBT 25MHz Crystal

R1915

0

1 2

5%

1/20W

MF

0201

PCH_CLK24M_XTALOUT

1

R1916

1M

5% 1/20W MF 201

2

PCH_CLK24M_XTALIN

IN

OUT

12 74

Ethernet 25MHz Crystal

16

PCH Reset Button

=PP3V3_S0_PCH

66

1

R1995

4.7K

5%

2

1/16W MF-LF 402

OMIT

1

R1997

0

5% 1/16W MF-LF 402

2

XDP

R1996

0

XDP_DBRESET_L PM_SYSRST_L

1 2

5% 1/16W MF-LF

402

13 43

OUTIN

B

A

C1917

10PF

21

5%

25V

C0G-NPO

0201

C1918

10PF

21

5%

25V

C0G-NPO

0201

TBT_CLK25M_OUT_R

74

1 3

NC

2 4

CRITICAL

25.000MHZ-20PPM-12PF-85C

NOTE: 30 PPM crystal required

Y1916

3.2X2.5MM-SM

R1917

0

1 2

5%

1/20W

MF

0201

TBT_CLK25M_OUT

NOSTUFF

1

R1918

1M

5% 1/20W MF 201

2

TBT_CLK25M_IN

26 74

C1919

18PF

1 2

5% 50V C0G

NC

0402

NC

C1920

18PF

2

1

5% 50V C0G

0402

www.qdzbwx.com

ENET_XTAL_OUT_R

74

1 3

2 4

CRITICAL

Y1917

25.000MHZ-20PPM-12PF-85C

3.2X2.5MM-SM

NOTE: 30 PPM crystal required

R1919

0

1 2

5% 1/16W MF-LF

402

ENET_XTAL_OUT

NOSTUFF

1

R1922

1M

5% 1/16W MF-LF 402

2

ENET_XTAL_IN

34 74

Clock series termination

R1955

IN OUT

LPC_CLK24M_SMC_R LPC_CLK24M_SMC

PLACE_NEAR=U0500.AN15:10MM

22

1 2

5%

1/20W

MF

201

PAGE TITLE

Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=02/25/2014SYNC_MASTER=J70_NICK

DRAWING NUMBER SIZE

051-00081

REVISION

3.0.0

BRANCH

PAGE

19 OF 123

SHEET

17 OF 81

43 74 12 74

A

D

8 7 5 4 2 1

36

Platform Reset Connections

345678

2 1

D

From RR

From PCH

79 27 26

26

IN

15

IN

Falcon Ridge JTAG Isolation

TBTLC can be on when S0 is off, and vice-versa

PP3V3_TBTLC

R2021

JTAG_TBT_TDO

JTAG_TBT_TMS_PCH

S0 pull-up on PCH page

Isolation ensures no leakage to RR or PCH

1

R2022

100K

5% 1/20W MF 201

2

S0 pull-up on PCH page

JTAG_ISP_TDO

JTAG_TBT_TMS

100K

5%

1/20W

MF

201

1

2

1

C2020

0.1UF

20%

10V

2

CERM 402

1

3

52

VCC

U2020

74LVC2G07

SOT891

6

1Y1A

4

2Y2A

GND

OUT

15

26

To PCH

To RR

R2055

33

5%

1/20W

MF

201

21

71 16 15 13 76 43

PLT_RESET_L

IN OUT

MAKE_BASE=TRUE

Unbuffered

SMC_LRESET_L

MAKE_BASE=TRUE

R2096

100

1 2

5%

1/20W

MF

201

DP_HPD_RESET_L

18

D

C

NOTE: Solution shown is for WPT-LP. Other PCH's may require isolation on TCK

and TDI as well for PCH glitch-prevention.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for

Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs

different isolation techniques will likely be necessary.

Multi-router designs also require different circuitry.

16 15

IN

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

JTAG_TBT_TCK_S

MAKE_BASE=TRUE

JTAG_TBT_TDI_S

MAKE_BASE=TRUE

Falcon Ridge HPD Isolation

SHORT

OMIT

XW2000

XW2001

OMIT

21

402

21

402

JTAG_TBT_TCK

JTAG_TBT_TDI

OUT

26

=PP3V3_S4_PCH_GPIO

CRITICAL

Q2010

1

SSM3K15AMFVAP

G

35 31 13 26

PCIE_WAKE_L TBT_WAKE_L

3

D

SOD

S

2

1

R2010

10K

5% 1/16W MF-LF 402

2

66 42 41 15

C

B

NOTE: PLT_RESET_L used as the other input to the AND gate so that HPD

is only driven high to the PCH in S0.

66 64 29 28 27 26 18

26

IN

DP_TBTSNK0_HPD

DP_HPD_RESET_L

18

=PP3V3_S4_TBT

2

1

A

U2030

B

TC7SZ08FEAPE

5

SOT665

CRITICAL

4

Y

3

1

C2030

0.1UF

20%

10V

2

CERM 402

DP_TBTSNK0_HPD_BUF

1

R2030

100K

5% 1/20W MF 201

2

OUT

13

=PP1V2_S3_MEM_VTTPWRCTL

66

CPU_MEMVTT_PWR_EN_LSVDDQ

6

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

=PP3V3_S0_MEM_VTTPWRCTL

1

R2040

100K

5% 1/20W MF 201

2

TPS51916 I(leak) = +/- 1uA,

Vih(min) = 1.8V

PM_EN_LDO_S3_DDRVTT

C2040

0.1UF

10% 16V

X5R-CERM

0201

1

6

VCC

2

U2040

74AUP1G07GF

SOT891

4

YA

66

B

59

A

66 64 29 28 27 26 18

26

IN

DP_TBTSNK1_HPD

DP_HPD_RESET_L

18

=PP3V3_S4_TBT

2

1

A

U2031

B

TC7SZ08FEAPE

5

SOT665

CRITICAL

4

Y

3

1

C2031

0.1UF

20%

10V

2

CERM 402

DP_TBTSNK1_HPD_BUF

1

R2031

100K

5% 1/20W MF 201

2

OUT

13

1

5

NCNC

GND

3

SYNC_MASTER=J70_NICK SYNC_DATE=11/20/2013

PAGE TITLE

A

Project Chipset Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

20 OF 123

18 OF 81

D

Memory Bit/Byte Swizzle

345678

2 1

D

C

B

=MEM_A_DQ<0>

21

=MEM_A_DQ<1>

21

=MEM_A_DQ<2>

21

=MEM_A_DQ<3>

21

=MEM_A_DQ<6>

21

=MEM_A_DQ<5>

21

=MEM_A_DQ<7>

21

=MEM_A_DQ<4>

21

=MEM_A_DQ<17>

21

=MEM_A_DQ<18>

21

=MEM_A_DQ<19>

21

=MEM_A_DQ<23>

21

=MEM_A_DQ<21>

21

=MEM_A_DQ<16>

21

=MEM_A_DQ<22>

21

=MEM_A_DQ<20>

21

=MEM_A_DQ<8>

21

=MEM_A_DQ<12>

21

=MEM_A_DQ<11>

21

=MEM_A_DQ<14>

21

=MEM_A_DQ<9>

21

=MEM_A_DQ<13>

21

=MEM_A_DQ<15>

21

=MEM_A_DQ<10>

21

=MEM_A_DQ<28>

21

=MEM_A_DQ<25>

21

=MEM_A_DQ<24>

21

=MEM_A_DQ<27>

21

=MEM_A_DQ<26>

21

=MEM_A_DQ<31>

21

=MEM_A_DQ<30>

21

=MEM_A_DQ<29>

21

=MEM_A_DQ<32>

22

=MEM_A_DQ<33>

22

=MEM_A_DQ<39>

22

=MEM_A_DQ<38>

22

=MEM_A_DQ<37>

22

=MEM_A_DQ<36>

22

=MEM_A_DQ<35>

22

=MEM_A_DQ<34>

22

=MEM_A_DQ<55>

22

=MEM_A_DQ<51>

22

=MEM_A_DQ<53>

22

=MEM_A_DQ<49>

22

=MEM_A_DQ<50>

22

=MEM_A_DQ<54>

22

=MEM_A_DQ<48>

22

=MEM_A_DQ<52>

22

=MEM_A_DQ<47>

22

=MEM_A_DQ<46>

22

=MEM_A_DQ<40>

22

=MEM_A_DQ<42>

22

=MEM_A_DQ<43>

22

=MEM_A_DQ<41>

22

=MEM_A_DQ<45>

22

=MEM_A_DQ<44>

22

=MEM_A_DQ<60>

22

=MEM_A_DQ<61>

22

=MEM_A_DQ<58>

22

=MEM_A_DQ<59>

22

=MEM_A_DQ<56>

22

=MEM_A_DQ<57>

22

=MEM_A_DQ<62>

22

=MEM_A_DQ<63>

22

MAKE_BASE

TRUE

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MAKE_BASE

70 7

70 7 70 7

=MEM_B_DQ<7>

23

=MEM_B_DQ<3>

23

=MEM_B_DQ<1>

23

=MEM_B_DQ<5>

23

=MEM_B_DQ<6>

23

=MEM_B_DQ<2>

23

=MEM_B_DQ<0>

23

=MEM_B_DQ<4>

23

=MEM_B_DQ<8>

23

=MEM_B_DQ<9>

23

=MEM_B_DQ<14>

23

=MEM_B_DQ<15>

23

=MEM_B_DQ<10>

23

=MEM_B_DQ<13>

23

=MEM_B_DQ<12>

23

=MEM_B_DQ<11>

23

=MEM_B_DQ<22>

23

=MEM_B_DQ<18>

23

=MEM_B_DQ<16>

23

=MEM_B_DQ<20>

23

=MEM_B_DQ<23>

23

=MEM_B_DQ<19>

23

=MEM_B_DQ<17>

23

=MEM_B_DQ<21>

23

=MEM_B_DQ<29>

23

=MEM_B_DQ<25>

23

=MEM_B_DQ<24>

23

=MEM_B_DQ<28>

23

=MEM_B_DQ<30>

23

=MEM_B_DQ<26>

23

=MEM_B_DQ<31>

23

=MEM_B_DQ<27>

23

=MEM_B_DQ<34>

24

=MEM_B_DQ<37>

24

=MEM_B_DQ<39>

24

=MEM_B_DQ<35>

24

=MEM_B_DQ<33>

24

=MEM_B_DQ<32>

24

=MEM_B_DQ<38>

24

=MEM_B_DQ<36>

24

=MEM_B_DQ<42>

24

=MEM_B_DQ<43>

24

=MEM_B_DQ<40>

24

=MEM_B_DQ<41>

24

=MEM_B_DQ<45>

24

=MEM_B_DQ<47>

24

=MEM_B_DQ<44>

24

=MEM_B_DQ<46>

24

=MEM_B_DQ<51>

24

=MEM_B_DQ<48>

24

=MEM_B_DQ<54>

24

=MEM_B_DQ<50>

24

=MEM_B_DQ<49>

24

=MEM_B_DQ<55>

24

=MEM_B_DQ<52>

24

=MEM_B_DQ<53>

24

=MEM_B_DQ<56>

24

=MEM_B_DQ<58>

24

=MEM_B_DQ<62>

24

=MEM_B_DQ<60>

24

=MEM_B_DQ<63>

24

=MEM_B_DQ<61>

24

=MEM_B_DQ<59>

24

=MEM_B_DQ<57>

24

TRUE

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

70 7

D

C

B

A

=MEM_A_DQS_P<0>

21

=MEM_A_DQS_N<0>

21

=MEM_A_DQS_P<2>

21

=MEM_A_DQS_N<2>

21

=MEM_A_DQS_P<1>

21

=MEM_A_DQS_N<1>

21

=MEM_A_DQS_P<3>

21

=MEM_A_DQS_N<3>

21

=MEM_A_DQS_P<4>

22

=MEM_A_DQS_N<4>

22

=MEM_A_DQS_P<6>

22

=MEM_A_DQS_N<6>

22

=MEM_A_DQS_P<5>

22

=MEM_A_DQS_N<5>

22

=MEM_A_DQS_P<7>

22

=MEM_A_DQS_N<7>

22

TRUE

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

70 7

=MEM_B_DQS_P<0>

23

=MEM_B_DQS_N<0>

23

=MEM_B_DQS_P<1>

23

=MEM_B_DQS_N<1>

23

=MEM_B_DQS_P<2>

23

=MEM_B_DQS_N<2>

23

=MEM_B_DQS_P<3>

23

=MEM_B_DQS_N<3>

23

=MEM_B_DQS_P<4>

24

=MEM_B_DQS_N<4>

24

=MEM_B_DQS_P<5>

24

=MEM_B_DQS_N<5>

24

=MEM_B_DQS_P<6>

24

=MEM_B_DQS_N<6>

24

=MEM_B_DQS_P<7>

24

=MEM_B_DQS_N<7>

24

TRUE

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

70 7

SYNC_MASTER=MASTER SYNC_DATE=MASTER

PAGE TITLE

A

DDR3 Signal Aliases

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

21 OF 123

19 OF 81

D

345678

2 1

D

C

B

D

VRef Dividers

R2223

10

1%

1/20W

MF

201

10

1%

1/20W

MF

201

1%

201

21

PLACE_NEAR=R2221.2:1mm

8.2K

1%

1/20W

MF

201

1

2

R2222

R2220

24.9

1/20W

21

PLACE_NEAR=R2241.2:1mm

1%

MF

201

R2242

21

8.2K

1%

1/20W

MF

201

1

2

R2240

24.9

1/20W

21

PLACE_NEAR=R2261.2:1mm

1%

MF

201

R2262

21

8.2K

1%

1/20W

MF

201

1

2

R2260

24.9

1/20W

1%

MF

201

21

7

IN

CPU_DDR_A_VREFDQ

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM 0201

DDR_VREFDQ_A_RC

R2243

7

IN

CPU_DDR_B_VREFDQ

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM 0201

DDR_VREFDQ_B_RC

R2263

7

IN

CPU_DDR_VREFCA

5.11

1/20W MF-LF

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM 0201

DDR_VREFCA_A_RC

=PP1V2_S3_DDR_MEMVREF

1

R2221

8.2K

1% 1/20W MF 201

2

PP0V6_S3_DDR_VREFDQ_A

VOLTAGE=0.6V

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000

1

R2241

8.2K

1% 1/20W MF 201

2

PP0V6_S3_DDR_VREFDQ_B

VOLTAGE=0.6V

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000

1

R2261

8.2K

1% 1/20W MF 201

2

PP0V6_S3_DDR_VREFCA

VOLTAGE=0.6V

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000

66

22 21

C

24 23

24 23 22 21

B

A

SYNC_MASTER=J117_ANDRES SYNC_DATE=02/27/2014

PAGE TITLE

DDR3 VREF MARGINING

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

22 OF 123

20 OF 81

A

D

LPDDR3 CHANNEL A (0-31)

345678

2 1

D

C

B

R2300

243

1%

1/20W

MF

201

U2300

LPDDR3-1600-32GB

EDFB232A1MA

70 25 7

70 25 22 7

IN

MEM_A_CAA<0>

MEM_A_CAA<1>

MEM_A_CAA<2>

MEM_A_CAA<3>

MEM_A_CAA<4>

MEM_A_CAA<5>

MEM_A_CAA<6>

MEM_A_CAA<7>

MEM_A_CAA<8>

MEM_A_CAA<9>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<0>

MEM_A_ZQ<1>

1

2

R2301

243

1%

1/20W

MF

201

1

2

C2340

0.047UF

10%

6.3V X5R 201

1

2

24 23 22 20

22 20

1

C2341

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_DDR_VREFCA

PP0V6_S3_DDR_VREFDQ_A

NC

R2

P2 N2 N3

M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8

D8

J8

B3

B4

H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1

U2

U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

FBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC

=MEM_A_DQ<0>

=MEM_A_DQ<1>

=MEM_A_DQ<2>

=MEM_A_DQ<3>

=MEM_A_DQ<4>

=MEM_A_DQ<5>

=MEM_A_DQ<6>

=MEM_A_DQ<7>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<12>

=MEM_A_DQ<13>

=MEM_A_DQ<14>

=MEM_A_DQ<15>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<20>

=MEM_A_DQ<21>

=MEM_A_DQ<22>

=MEM_A_DQ<23>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<26>

=MEM_A_DQ<27>

=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

=MEM_A_DQS_P<0>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<3>

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

66 24 23 22 21

=PP1V8_S3_DDR

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2

H3

L2

M2

A11 C12

E8

E12 G12

H8 H9

H11

J9

J10

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2300

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

K8

K11

L12

66 24 23 22 21

=PP1V2_S3_DDR_VDDQ

1

C2300

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2301

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2302

1UF

10% 10V

2

X5R 402-1

1

C2303

1UF

10% 10V

2

X5R 402-1

1

C2304

10UF

20%

6.3V

2

CERM 0402

1

C2305

1UF

10% 10V

2

X5R 402-1

1

C2306

1UF

10% 10V

2

X5R 402-1

1

C2307

10UF

20%

6.3V

2

CERM 0402

N8

N12 R12 U11

A

66 24 23 22 21

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V8_S3_DDR

1

C2320

1UF

10% 10V

2

X5R 402-1

1

C2310

1UF

10% 10V

2

X5R 402-1

1

C2330

1UF

10% 10V

www.qdzbwx.com

2

X5R 402-1

1

C2321

1UF

10% 10V

2

X5R 402-1

1

C2311

1UF

10% 10V

2

X5R 402-1

1

C2331

1UF

10% 10V

2

X5R 402-1

1

C2322

1UF

10% 10V

2

X5R 402-1

1

C2313

1UF

10% 10V

2

X5R 402-1

1

C2334

1UF

10% 10V

2

X5R 402-1

1

C2325

1UF

10% 10V

2

X5R 402-1

1

C2314

1UF

10% 10V

2

X5R 402-1

1

C2335

1UF

10% 10V

2

X5R 402-1

1

C2326

1UF

10% 10V

2

X5R 402-1

1

C2315

1UF

10% 10V

2

X5R 402-1

1

C2332

10UF

20%

6.3V

2

CERM 0402

1

C2327

1UF

10% 10V

2

X5R 402-1

1

C2312

1UF

10% 10V

2

X5R 402-1

1

C2333

10UF

20%

6.3V

2

CERM 0402

1

C2323

1UF

10% 10V

2

X5R 402-1

1

C2336

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C2324

10UF

20%

6.3V

2

CERM 0402

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

Distribute evenly.

SYNC_MASTER=J41_MLB SYNC_DATE=09/03/2013

PAGE TITLE

LPDDR3 DRAM Channel A (0-31)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

23 OF 123

SHEET

21 OF 81

D

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL A (32-63)

345678

2 1

D

C

B

R2400

243

1%

1/20W

MF

201

U2400

LPDDR3-1600-32GB

EDFB232A1MA

70 25 7

70 25 21 7

IN

MEM_A_CAB<0>

MEM_A_CAB<1>

MEM_A_CAB<2>

MEM_A_CAB<3>

MEM_A_CAB<4>

MEM_A_CAB<5>

MEM_A_CAB<6>

MEM_A_CAB<7>

MEM_A_CAB<8>

MEM_A_CAB<9>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<2>

MEM_A_ZQ<3>

243

1%

1/20W

MF

201

1

2

C2440

0.047UF

10%

6.3V X5R 201

1

2

24 23 21 20

21 20

1

C2441

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_DDR_VREFCA

PP0V6_S3_DDR_VREFDQ_A

NC

1

2

R2401

NC

R2

P2 N2 N3 M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8

D8

J8

B3

B4

H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1

U2

U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

FBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC

=MEM_A_DQ<32>

=MEM_A_DQ<33>

=MEM_A_DQ<34>

=MEM_A_DQ<35>

=MEM_A_DQ<36>

=MEM_A_DQ<37>

=MEM_A_DQ<38>

=MEM_A_DQ<39>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<42>

=MEM_A_DQ<43>

=MEM_A_DQ<44>

=MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<48>

=MEM_A_DQ<49>

=MEM_A_DQ<50>

=MEM_A_DQ<51>

=MEM_A_DQ<52>

=MEM_A_DQ<53>

=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<58>

=MEM_A_DQ<59>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQ<62>

=MEM_A_DQ<63>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<4>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<6>

=MEM_A_DQS_P<7>

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

66 24 23 22 21

=PP1V8_S3_DDR

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3

L2

M2

A11 C12

E8

E12

G12

H8 H9

H11

J9

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

J10

U2400

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

K8

K11

66 24 23 22 21

=PP1V2_S3_DDR_VDDQ

1

C2400

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2401

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2402

1UF

10% 10V

2

X5R 402-1

1

C2403

1UF

10% 10V

2

X5R 402-1

1

C2404

1UF

10% 10V

2

X5R 402-1

1

C2405

1UF

10% 10V

2

X5R 402-1

1

C2406

10UF

20%

6.3V

2

CERM 0402

L12

N8

N12 R12 U11

A

66 24 23 22 21

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V8_S3_DDR

1

C2420

1UF

10% 10V

2

X5R 402-1

1

C2410

1UF

10% 10V

2

X5R 402-1

1

C2430

1UF

10% 10V

www.qdzbwx.com

2

X5R 402-1

1

C2421

10UF

20%

6.3V

2

CERM 0402

1

C2411

1UF

10% 10V

2

X5R 402-1

1

C2431

1UF

10% 10V

2

X5R 402-1

1

C2422

10UF

20%

6.3V

2

CERM 0402

1

C2413

1UF

10% 10V

2

X5R 402-1

1

C2433

1UF

10% 10V

2

X5R 402-1

1

C2424

1UF

10% 10V

2

X5R 402-1

1

C2414

1UF

10% 10V

2

X5R 402-1

1

C2434

1UF

10% 10V

2

X5R 402-1

1

C2425

1UF

10% 10V

2

X5R 402-1

1

C2415

1UF

10% 10V

2

X5R 402-1

1

C2432

10UF

20%

6.3V

2

CERM 0402

1

C2426

1UF

10% 10V

2

X5R 402-1

1

C2412

10UF

20%

6.3V

2

CERM 0402

1

C2435

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C2423

1UF

10% 10V

2

X5R 402-1

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

Distribute evenly.

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=09/03/2013SYNC_MASTER=J41_MLB

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

24 OF 123

SHEET

22 OF 81

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (0-31)

345678

2 1

D

C

B

R2500

243

1%

1/20W

MF

201

U2500

LPDDR3-1600-32GB

EDFB232A1MA

70 25 7 19

70 25 7

70 25 24 7

IN BI

IN

MEM_B_CAA<0>

MEM_B_CAA<1>

MEM_B_CAA<2>

MEM_B_CAA<3>

MEM_B_CAA<4>

MEM_B_CAA<5>

MEM_B_CAA<6>

MEM_B_CAA<7>

MEM_B_CAA<8>

MEM_B_CAA<9>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<0>

MEM_B_ZQ<1>

1

2

R2501

243

1%

1/20W

MF

201

1

2

C2540

0.047UF

10%

6.3V X5R 201

1

2

24 22 21 20

1

C2541

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_DDR_VREFCA

PP0V6_S3_DDR_VREFDQ_B

24 20

NC

R2

P2 N2 N3

M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8 D8

J8

B3

B4

H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1 U2

U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

FBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC

=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQ<6>

=MEM_B_DQ<7>

=MEM_B_DQ<8>

=MEM_B_DQ<9>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<12>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<16>

=MEM_B_DQ<17>

=MEM_B_DQ<18>

=MEM_B_DQ<19>

=MEM_B_DQ<20>

=MEM_B_DQ<21>

=MEM_B_DQ<22>

=MEM_B_DQ<23>

=MEM_B_DQ<24>

=MEM_B_DQ<25>

=MEM_B_DQ<26>

=MEM_B_DQ<27>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<0>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<3>

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

66 24 23 22 21

=PP1V8_S3_DDR

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2 H3

L2

M2

A11 C12

E8

E12 G12

H8 H9

H11

J9

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

J10

U2500

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

K8

66 24 23 22 21

=PP1V2_S3_DDR_VDDQ

K11

L12

1

C2500

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2501

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2502

1UF

10% 10V

2

X5R 402-1

1

C2503

1UF

10% 10V

2

X5R 402-1

1

C2504

1UF

10% 10V

2

X5R 402-1

1

C2505

10UF

20%

6.3V

2

CERM 0402

1

C2506

10UF

20%

6.3V

2

CERM 0402

N8 N12 R12 U11

A

66 24 23 22 21

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V8_S3_DDR

1

C2520

1UF

10% 10V

2

X5R 402-1

1

C2510

1UF

10% 10V

2

X5R 402-1

1

C2530

1UF

10% 10V

2

X5R 402-1

1

C2521

1UF

10% 10V

2

X5R 402-1

1

C2511

10UF

20%

6.3V

2

CERM 0402

1

C2531

1UF

10% 10V

2

X5R 402-1

1

C2522

1UF

10% 10V

2

X5R 402-1

1

C2512

1UF

10% 10V

2

X5R 402-1

1

C2533

1UF

10% 10V

2

X5R 402-1

1

C2524

1UF

10% 10V

2

X5R 402-1

1

C2534

1UF

10% 10V

2

X5R 402-1

1

C2525

1UF

10% 10V

2

X5R 402-1

1

C2526

1UF

10% 10V

2

X5R 402-1

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

Distribute evenly.

1

C2532

10UF

20%

6.3V

2

CERM 0402

1

C2535

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C2523

10UF

20%

6.3V

2

CERM 0402

PAGE TITLE

LPDDR3 DRAM Channel B (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=09/03/2013SYNC_MASTER=J41_MLB

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

25 OF 123

SHEET

23 OF 81

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (32-63)

345678

2 1

D

C

B

R2600

243

1%

1/20W

MF

201

U2600

LPDDR3-1600-32GB

EDFB232A1MA

70 25 7

70 25 23 7

IN

MEM_B_CAB<0>

MEM_B_CAB<1>

MEM_B_CAB<2>

MEM_B_CAB<3>

MEM_B_CAB<4>

MEM_B_CAB<5>

MEM_B_CAB<6>

MEM_B_CAB<7>

MEM_B_CAB<8>

MEM_B_CAB<9>

MEM_B_CKE<2>

MEM_B_CKE<3>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<2>

MEM_B_ZQ<3>

1

2

R2601

243

1%

1/20W

MF

201

1

2

C2640

0.047UF

10%

6.3V X5R 201

1

2

23 22 21 20

1

C2641

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_DDR_VREFCA

PP0V6_S3_DDR_VREFDQ_B

23 20

NC

R2 P2 N2 N3

M3

F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8

G8

P8 D8

J8

B3 B4

H4

J11

A1 A2

A12 A13

B1

B13

T1

T13

U1 U2

U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

FBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC

=MEM_B_DQ<32>

=MEM_B_DQ<33>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<36>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQ<39>

=MEM_B_DQ<40>

=MEM_B_DQ<41>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<44>

=MEM_B_DQ<45>

=MEM_B_DQ<46>

=MEM_B_DQ<47>

=MEM_B_DQ<48>

=MEM_B_DQ<49>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<52>

=MEM_B_DQ<53>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

=MEM_B_DQ<58>

=MEM_B_DQ<59>

=MEM_B_DQ<60>

=MEM_B_DQ<61>

=MEM_B_DQ<62>

=MEM_B_DQ<63>

=MEM_B_DQS_N<4>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<4>

=MEM_B_DQS_P<5>

=MEM_B_DQS_P<6>

=MEM_B_DQS_P<7>

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

66 24 23 22 21

=PP1V8_S3_DDR

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2

H3

L2

M2

A11 C12

E8

E12

G12

H8 H9

H11

J9

J10

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2600

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

K8

K11

66 24 23 22 21

=PP1V2_S3_DDR_VDDQ

1

C2600

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2601

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2602

1UF

10% 10V

2

X5R 402-1

1

C2603

10UF

20%

6.3V

2

CERM 0402

1

C2604

1UF

10% 10V

2

X5R 402-1

1

C2605

10UF

20%

6.3V

2

CERM 0402

1

C2607

1UF

10% 10V

2

X5R 402-1

1

C2606

10UF

20%

6.3V

2

CERM 0402

L12

N8

N12 R12 U11

A

66 24 23 22 21

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V8_S3_DDR

1

C2620

1UF

10% 10V

2

X5R 402-1

1

C2610

1UF

10% 10V

2

X5R 402-1

1

C2630

1UF

10% 10V

2

X5R 402-1

1

C2621

1UF

10% 10V

2

X5R 402-1

1

C2611

1UF

10% 10V

2

X5R 402-1

1

C2631

1UF

10% 10V

2

X5R 402-1

1

C2622

1UF

10% 10V

2

X5R 402-1

1

C2612

1UF

10% 10V

2

X5R 402-1

1

C2633

1UF

10% 10V

2

X5R 402-1

1

C2624

1UF

10% 10V

2

X5R 402-1

1

C2613

1UF

10% 10V

2

X5R 402-1

1

C2634

1UF

10% 10V

2

X5R 402-1

1

C2625

1UF

10% 10V

2

X5R 402-1

1

C2614

1UF

10% 10V

2

X5R 402-1

1

C2632

10UF

20%

6.3V

2

CERM 0402

1

C2626

1UF

10% 10V

2

X5R 402-1

1

C2615

1UF

10% 10V

2

X5R 402-1

1

C2635

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C2627

1UF

10% 10V

2

X5R 402-1

1

C2623

10UF

20%

6.3V

2

CERM 0402

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

Distribute evenly.

SYNC_MASTER=J41_MLB SYNC_DATE=09/03/2013

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

26 OF 123

SHEET

24 OF 81

D

A

8 7 5 4 2 1

36

345678

2 1

D

C

70 21 7

70 22 7

70 22 21 7

Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

=PP0V6_S3_DDRVTT_A

66 66

IN

MEM_A_CAA<9>

MEM_A_CAA<8>

MEM_A_CAA<6>

MEM_A_CAA<7>

MEM_A_CAA<5>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_A_CAA<4>

MEM_A_CAA<3>

MEM_A_CAA<2>

MEM_A_CAA<1>

MEM_A_CAA<0>

MEM_A_CAB<9>

MEM_A_CAB<8>

MEM_A_CAB<6>

MEM_A_CAB<7>

MEM_A_CAB<5>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CAB<4>

MEM_A_CAB<2>

MEM_A_CAB<3>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

RP2701 RP2701 RP2701

RP2701 R2700 R2701 R2702 R2703 R2704 R2705 R2706

RP2703

RP2703 R2725

RP2707

RP2707 R2707 R2708 R2709 R2720 R2721

RP2704

RP2704 R2722 R2723 R2724

56

39

82

56

39

82

56 56

56

82

54

1/32W

5%

63

1/32W

5%

72

81

21

54

63

72

21

54

63

72

81

21

54

63

72

81

21

1/32W5%

1/20W5% 201 MF

5% 2011/20W MF

5% MF201

1/20W

5% MF1/20W 201

5%561/20W MF201

5%

1/32W

5%

1/32W

5% 1/32W

5%561/20W MF201

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5% MF1/20W 201

5%391/20W MF201

5%

5% 1/20W

5%

1/32W5%

1/32W

5%

5%561/32W

1/32W

5%

5%821/20W 201 MF

5%

4X0201-HF

2015% 1/20W MF

4X0201-HF

201 MF1/20W

4X0201-HF

Spare

RP2703

56

5%

1/32W

4X0201-HF

81

PLACE_NEAR=RP2701.5:4mm

D

=PP0V6_S3_DDRVTT_B

1

C2700

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2701

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2703

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2705

0.47UF

20% 4V

2

CERM-X5R-1 201

MF2011/20W

MF201

1

C2707

0.47UF

20% 4V

2

CERM-X5R-1 201

MF1/20W 201

1

MF1/20W 201

C2709

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2702

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2704

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2706

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2708

0.47UF

20% 4V

2

CERM-X5R-1 201

70 23 7

70 24 7

70 24 23 7

IN

MEM_B_CAA<9>

MEM_B_CAA<8>

MEM_B_CAA<7>

MEM_B_CAA<6>

MEM_B_CAA<5>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_B_CAA<4>

MEM_B_CAA<2>

MEM_B_CAA<3>

MEM_B_CAA<1>

MEM_B_CAA<0>

MEM_B_CAB<9>

MEM_B_CAB<8>

MEM_B_CAB<7>

MEM_B_CAB<6>

MEM_B_CAB<5>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<2>

MEM_B_CKE<3>

MEM_B_CAB<4>

MEM_B_CAB<2>

MEM_B_CAB<3>

MEM_B_CAB<1>

MEM_B_CAB<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

RP2712 RP2712 RP2712

RP2712 R2710 R2711 R2712 R2713 R2714 R2715 R2716

RP2713

RP2713 R2735

RP2717

RP2717 R2717 R2718 R2719 R2730 R2731

RP2714

RP2714 R2732 R2733 R2734

Spare

56

39

82

56

56 56

56

39

82

56 56

56

82

RP2713

56

81

5%

1

C2720

22UF

20%

6.3V

2

X5R-CERM-1 603

CRITICAL

NC NCNCNC

1/32W

4X0201-HF

54

63

72

81

21

54

63

72

21

54

63

72

81

21

54

63

72

81

21

1/32W5%

5%

1/32W

5%

1/32W

5%

1/32W

5%

5% 1/20W MF

5% MF1/20W 201

5%

5%561/20W MF201

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

5% 1/20W MF

5%

5% 1/32W

1/32W

5%

5%561/32W

1/32W

5%

5% 1/20W MF201

4X0201-HF

MF1/20W 201

201

MF1/20W 201

4X0201-HF

2011/20W MF

4X0201-HF

MF1/20W 201

201

MF1/20W 201

201 MF1/20W

4X0201-HF

MF1/20W 201

PLACE_NEAR=RP2714.8:4.5mm

1

C2710

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2711

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2713

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2715

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2717

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2719

0.47UF

20% 4V

2

CERM-X5R-1 201

CRITICAL

1

C2740

22UF

20%

6.3V

2

X5R-CERM-1 603

1

C2712

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2714

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2716

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2718

0.47UF

20% 4V

2

CERM-X5R-1 201

C

B

A

PAGE TITLE

LPDDR3 DRAM Termination

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/03/2013SYNC_MASTER=J41_MLB

051-00081

3.0.0

27 OF 123

25 OF 81

A

D

Apple IMAC A1418 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual