Apple IMAC A1418 Schematic

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

7

www.qdzbwx.comwww.qdzbwx.com

6 5 4 3

J117 MLB

LAST_MODIFIED=Thu Sep 18 13:37:48 2014

LAST_MODIFICATION=Thu Sep 18 13:37:48 2014

2 1

ECNREV DESCRIPTION OF REVISION

CK APPD

DATE

2014-12-0900035019963 ENGINEERING RELEASED

D

www.rosefix.com

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<.CSA>

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<.CSA>

DATE

CONTENTS

J117 MLB_IG

BOM Configuration

DEBUG LEDS

Holes/PD parts CPU GFX/NCTF/RSVD

CPU Misc/JTAG/CFG/RSVD

CPU DDR3/LPDDR3 Interfaces

CPU/PCH POWER

CPU/PCH GROUNDS

CPU Decoupling

PCH Decoupling

PCH Audio/JTAG/SATA/CLK

PCH PM/PCI/GFX

PCH PCIe/USB/LPC/SPI/SMBus

PCH GPIO/MISC/LPIO

CPU/PCH Merged XDP

Chipset Support

Project Chipset Support

DDR3 Signal Aliases

DDR3 VREF MARGINING

LPDDR3 DRAM Channel A (0-31)

LPDDR3 DRAM Channel A (32-63)

LPDDR3 DRAM Channel B (0-31)

LPDDR3 DRAM Channel B (32-63)

LPDDR3 DRAM Termination

Thunderbolt Host (1 of 2)

Thunderbolt Host (2 of 2) PCH PCIe/DMI Constaints

Thunderbolt Connector A

Thunderbolt Connector B

DDC Crossbar

AIRPORT/BT

SSD Connectors

HDD Connector

ETHERNET PHY (CAESAR IV)

Ethernet Support & Connector

SD READER CONNECTOR

Camera Controller

Camera Controller Support

Internal DP Support

Internal DP MUXing

EXTERNAL USB PORTS A & B

EXTERNAL USB PORTS C & D

SMC

SMC Support

SPI and Debug Connector

SYNC

J117_Tony

J117_Rossana

J117_Andres

J117_Tony

J117_Rossana

J117_Andres

J117_Garen

J117_Andres

J94

J117_Nick

J94

J117_Rossana

J117_Nick

J117_Rossana

J117_Garen

J94

J117_Nick

07/11/2014

09/03/2014

09/12/2014

09/09/2014

06/19/2014

11/20/2014

06/11/2014

06/24/2014

07/14/2014

07/31/2014

06/26/2014

10/10/2014

11/20/2014

06/17/2014

11/18/2014

12/03/2014

07/31/2014

10/10/2014

07/31/2014

07/14/2014

06/24/2014

PAGE CONTENTS

46

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84

85

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100

104

105

110

111

112

113

114

115

116

117

118

119

120

121

123

SMBus Connections

I and V Sense

Temperature Sensors

System Fan

AUDIO: Codec (Analog)

AUDIO:CODEC, DIGITAL

AUDIO: SPEAKER AMP, LEFT CHANNEL

AUDIO: SPEAKER AMP, RIGHT CHANEL

AUDIO: JACK TRANSLATORS

AUDIO: Speaker ID

Power Connectors / VReg G3Hot

CPU VR12.6 VCC Regulator IC

CPU VR12.5 VCC Power Stage

VReg VDDQ S3 / 1.8V S3

VREG 1V05 S0 / 1V5 S0

VReg 3.3V S5/5V S4

LCD Backlight Driver (LP8561)

PM FETs/LDOs

PM Regulator Enables

PM Power Good

Power Aliases

Unused Signal Aliases

Functional / ICT Test

J70 RULE DEFINITIONS

DDR3 Constraints

CPU CONSTRAINTS

SATA/FDI/XDP Constraints

PCH and BR Constraints

USB/Ethernet/SD Constraints

SMBus/Sensor Constraints

VReg Constraints

CPU VReg Constraints

Platform VReg Constraints

TBT/DP Constraints

BLC Constraints

SYNC

J117_Tony

J117_Garen

J94

J117_Tony

J117_Garen

J117_Andres

J117_Garen

DATE

11/17/2014

06/12/2014

10/10/2014

10/28/2014

06/27/2014

06/10/2014

09/12/2014

06/17/2014

D

C

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A

DRAWING

TITLE=J16 MLB_IG

ABBREV=DRAWING

LAST_MODIFIED=Thu Sep 18 13:37:48 2014

3

DRAWING TITLE

SCHEM,MLB,J117

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

DRAWING

051-00081

REVISION

3.0.0

BRANCH

PAGE

1 OF 123

SHEET

1 OF 81

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SIZEDRAWING NUMBER

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Schematic / PCB #'s

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

www.qdzbwx.com

TABLE_5_HEAD

BOM OPTIONCRITICAL

TABLE_5_ITEM

1 CRITICALSCHSCH,MLB,J117051-00081

TABLE_5_ITEM

820-00034 1 CRITICALPCBPCBF,MLB,J117

TABLE_5_ITEM

1685-00013 PCBA,MLB,J117,COMMON PARTS MLB_CMNPTSCMNPTS

Main BOM Variants

BOM NUMBER BOM NAME BOM OPTIONS

985-00016 PCBA,MLB,DEV,J117 DEVELOPMENT,J117_DEVEL

PCBA,MLB,DEV,J117,CPU_INT939-00158

639-00910 PCBA,MLB,J117,HY_8GB_29NM,HDD,1866

639-00911 PCBA,MLB,J117,EL_8GB_25NM,HDD,1866

639-00912 PCBA,MLB,J117,SA_8GB_23NM,HDD,1866

639-00913 PCBA,MLB,J117,EL_16GB_25NM,HDD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:ELPIDA_16GB_1866,SSD:N

639-00914 PCBA,MLB,J117,HY_16GB_25NM,HDD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:HYNIX_16GB_1866,SSD:N

639-00713 PCBA,MLB,J117,HY_8GB_29NM,SSD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:HYNIX_8GB_1866,SSD:Y

639-00714 PCBA,MLB,J117,EL_8GB_25NM,SSD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:ELPIDA_8GB_1866,SSD:Y

639-00715 PCBA,MLB,J117,SA_8GB_23NM,SSD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:SAMSUNG_8GB_1866,SSD:Y

PCBA,MLB,J117,EL_16GB_25NM,SSD,1866639-00716

PCBA,MLB,J117,HY_16GB_25NM,SSD,1866 MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:HYNIX_16GB_1866,SSD:Y639-00717

PCBA,MLB,J117,COMMON PARTS685-00013 J117_COMMON

MLB_CMNPTS,ALTERNATE,CPU:SOCKET,DDR3:HYNIX_8GB_1866,SSD:Y

MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:HYNIX_8GB_1866,SSD:N

MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:ELPIDA_8GB_1866,SSD:N

MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:SAMSUNG_8GB_1866,SSD:N

MLB_CMNPTS,ALTERNATE,CPU:ULT,DDR3:ELPIDA_16GB_1866,SSD:Y

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

Alternates

PART NUMBER

377S0155377S00011

377S0184

155S0578 155S0367 ALL

197S0481 ALL197S0480

197S0399 ALL197S0392

155S0830 155S0316 ALL

377S0155

377S0057

128S0365 ALL128S0368

138S0638138S0681 ALL

197S0478 ALL197S0479

197S0478197S0486 ALL

197S0480 ALL197S0343

378S0390378S0391 ALL

341S3912 ALL341S00016

197S0544 ALL197S0542

197S0392 ALL197S0369

376S00075 ALL376S0972

132S0401 ALL132S00012

138S0771138S00012 ALL

155S0546155S00076 ALL

ALL

ALL107S0251 107S0249

ALL138S0775138S0860

ALL138S0859 138S0788

ALL138S0773138S0747

ALL197S0544197S0545

ALL376S0659376S0572

ALL138S1103 138S0719

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

USB3 diodesALL 376S1128 ALL376S1089

TABLE_ALT_ITEM

USB3 diodesALL

TABLE_ALT_ITEM

TVS377S0124

TABLE_ALT_ITEM

120OHM EMI BEAD

TABLE_ALT_ITEM

150UF AL POLY

TABLE_ALT_ITEM

Taiyo 10uf 805 alt

TABLE_ALT_ITEM

12 MHz Cam. Xtal

TABLE_ALT_ITEM

155S0694 155S0387 ALL

127S0164 127S0162

376S00074 376S0855

376S1129

376S00074

12 MHz Cam. Xtal

TABLE_ALT_ITEM

Sense resistor

TABLE_ALT_ITEM

25MHz Xtal

TABLE_ALT_ITEM

25MHz Xtal

TABLE_ALT_ITEM

Single-source 1uF 402

TABLE_ALT_ITEM

Single-source 10uF

TABLE_ALT_ITEM

Debug LEDs

TABLE_ALT_ITEM

ENET ROM,ADESTO,V1.15

TABLE_ALT_ITEM

1uF,X6S,402

TABLE_ALT_ITEM

24 MHz PCH XTal

TABLE_ALT_ITEM

24 Mhz PCH XTal

TABLE_ALT_ITEM

32 KHz PCH Xtal

TABLE_ALT_ITEM

32 KHz PCH Xtal

TABLE_ALT_ITEM

Single P-Ch FET

TABLE_ALT_ITEM

Single N-Ch FET

TABLE_ALT_ITEM

0.22uF,X7R,0402

TABLE_ALT_ITEM

1uF,X6S,0402

TABLE_ALT_ITEM

4.7uF,X5R,0402

TABLE_ALT_ITEM

FER BD,600 OHM,0.5A,0603

TABLE_ALT_ITEM

FER BD,600 OHM,300MA,402

311S0649

107S0375

107S00011

353S3814

353S4376

311S00014

311S00013

371S00019

376S00037

376S00036 ALL

138S0746 ALL

152S1757

138S00013

PART NUMBER

155S0513155S0660 ALL

ALL

376S0855

ALL

376S0855 SSD:Y ALL

ALLSSD:Y376S0855376S1129

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

Single N-Ch FET

22OHM EMI BEAD

470OHM EMI BEAD

1UF 25V TANT

Dual N-Ch FET

311S0541 ALL Single AND Gate

107S00039

107S0372

353S3812

353S3384

311S0515

311S0508

371S0463

376S1193

376S1194

138S0705

152S1821

138S0772

371S0749

ALL DDR Sense Res

ALL CPU VR Sense Res

ALL

ALL371S00017

TBT mux

HDD OOBv1 comparator

TBT JTAG ISOLATION BUFFER

Single Buffer Driver OD

Rohm Schottky Barrier Diode

30V,64A,Single N-Channel FET

30V,52A,Single N-channel FET

CAP,CER,X5R,10uF,20%,10V,402

IND,0.4uH,23A

CAP,CER,2.2UF,20%,10V,X6S,402

DIODE,SCHOTTKY,30V,1A,SOD-323

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Strategic Silicon

PART# COMMENT

337S00065 08

338S1247 02

335S00006

333S0784 07

333S0786

333S0790

333S00004 07

STRATEGIC VALUE

07

07333S0792

CPU,BDW-ULT,2+GT3

TBT,Falcon Ridge-4c

IC,SERIAL FLASH,Quad-IO

32Gb,25nm LPDDR3-1866

16Gb,29nm LPDDR3-1866

32Gb,25nm LPDDR3-1866

16Gb,25nm LPDDR3-1866

16Gb,23nm LPDDR3-1866

TABLE_STRATEGIC_HEAD

TABLE_STRATEGIC__ITEM

D

TABLE_STRATEGIC__ITEM

C

B

A

BOM Groups

BOM GROUP BOM OPTIONS

COMMON,ALTERNATE,J117_PROGPARTS,SMCREG:SUP,XDP,SMBUS1:ISOL,USB_OC_ISO:Y,RTCRST:Y,AUDIO_DP_SNS:NJ117_COMMON

J117_DEVEL XDP_CONN,TEMPSNSDEV,SAMCONN

CPUs

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

337S00101

998-7866

1

IC,CPU,BDW-ULT,QH3Y,ES,f0-B2,2/3,1.6,15W,.95,1168

1

INTERPOSER,BGA1168,SINGLE SIDE

U0500

ASIC Parts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

343S0616

1

IC,TBT,FR-4C,A0,PRQ,CIO,SR1JC,FCBGA288

IC,BCM57766A,CIV+,A0,8x8

1

U2800338S1247

Programmable Parts

REFERENCE DESIGNATOR(S)QTY DESCRIPTIONPART#

341S00158

335S00006

341S00110

338S1214

341S3778

335S0852

341S00154

341S3912 ENETROM:PROGCRITICALU3990

335S1025

IC,EFI,V0108,J117

1

IC,SERIAL FLASH,64MBIT,3V,8P,WSON,QE=1

IC,SMC-B1,EXTERNAL,V2.24A19,POC,J117

1

IC,SMC12-B1,40MHZ/50MIPS,MCU,157BGA

IC,CAMERA,FLASH,V7229,J16

1

IC,FLASH,SPI,1MBIT,3V3

IC,EPROM,T29,FALCON RIDGE,V27.1,J117

1

IC,FLASH,SPI,4MBIT,50MHZ335S0915

IC,ENET SPI ROM,NYMONYX,V1.15,J16/J16G/J17

1

IC,SERIAL FLASH,2MBIT,2.7V,REV F

1

U4202

U2890 TBTROM:PROG

U3990 CRITICAL

SMC:PROG,BOOTROM:PROG,CAMROM:PROG,TBTROM:PROG,ENETROM:PROGJ117_PROGPARTS

CRITICAL

CRITICALU3900

CRITICAL BOOTROM:PROGU5210

CRITICAL SMC:PROGU5000

CRITICAL SMC:BLANKU5000

CRITICAL CAMROM:BLANKU4202

CRITICAL

BOM OPTIONCRITICAL

CPU:ULT

CPU:SOCKET

BOM OPTIONCRITICAL

BOOTROM:BLANKCRITICALU5210

CAMROM:PROGCRITICAL

TBTROM:BLANKCRITICALU2890

ENETROM:BLANK

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CPU DRAM SPD Straps

BOM GROUP BOM OPTIONS

DDR3:HYNIX_8GB_1600

DDR3:HYNIX_16GB_1600

DDR3:HYNIX_8GB_1866

DDR3:HYNIX_16GB_1866

DDR3:ELPIDA_8GB_1600

DDR3:ELPIDA_16GB_1600

DDR3:ELPIDA_8GB_1866

DDR3:ELPIDA_16GB_1866

DDR3:SAMSUNG_8GB_1600

DDR3:SAMSUNG_8GB_1866

DRAM Parts

333S0783

4

4333S0784

333S0785

333S0786

4

333S0789 4

333S0790

333S0791

333S0792

4

333S00003 4

333S00004 4

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

IC,SDRAM,29nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,29nm 16Gb,LPDDR3-1866,178P FBGA

IC,SDRAM,25nm 32Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,25nm 32Gb,LPDDR3-1866,178P FBGA

IC,SDRAM,25nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,25nm 16Gb,LPDDR3-1866,178P FBGA

IC,SDRAM,23nm 16Gb,LPDDR3-1600,178P FBGA

IC,SDRAM,23nm 16Gb,LPDDR3-1866,178P FBGA

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,RAMCFG4:L,HYNIX_8GB_1600

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,RAMCFG4:L,HYNIX_16GB_1600

RAMCFG0:L,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,RAMCFG4:H,HYNIX_8GB_1866

RAMCFG0:L,RAMCFG1:L,RAMCFG2:H,RAMCFG3:L,RAMCFG4:H,HYNIX_16GB_1866

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,RAMCFG4:L,ELPIDA_8GB_1600

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,RAMCFG4:L,ELPIDA_16GB_1600

RAMCFG0:H,RAMCFG1:H,RAMCFG2:L,RAMCFG3:L,RAMCFG4:H,ELPIDA_8GB_1866

RAMCFG0:H,RAMCFG1:H,RAMCFG2:H,RAMCFG3:L,RAMCFG4:H,ELPIDA_16GB_1866

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,RAMCFG4:L,SAMSUNG_8GB_1600

RAMCFG0:H,RAMCFG1:L,RAMCFG2:L,RAMCFG3:L,RAMCFG4:H,SAMSUNG_8GB_1866

CRITICALPART NUMBER QTY BOM OPTIONREFERENCE DESDESCRIPTION

U2300,U2400,U2500,U2600

CRITICAL

HYNIX_16GB_1600

HYNIX_16GB_1866

HYNIX_8GB_1600

HYNIX_8GB_1866

ELPIDA_16GB_1600

ELPIDA_16GB_1866

ELPIDA_8GB_1600

ELPIDA_8GB_1866

SAMSUNG_8GB_1600

SAMSUNG_8GB_1866

PAGE TITLE

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

CPU DRAM CFG Chart

CFG 3

A

B

0

1

BOM Configuration

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

VENDOR

HYNIX

SAMSUNG

N/A

ELPIDA

SIZE

8GB

16GB 1

SPEED

1866

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

CFG 1

0

1

CFG 0

0

1

0

1

CFG 2

0

CFG 4DIE REV

01600

1

SYNC_DATE=05/05/2014SYNC_MASTER=J117_TONY

051-00081

3.0.0

2 OF 123

2 OF 81

B

A

D

8 7 5 4 2 1

36

www.qdzbwx.com

345678

2 1

VIDEO ON Led

D

=PP3V3_S5_LED

66

1

R0301

1K

5% 1/16W MF-LF 402

2

ITS_PLUGGED_IN

SILK_PART=1

A

CRITICAL

LE0301

GRN-6MCD-0.03A

0805

K

ALL_SYS_PWRGD LedS5 Led

=PP3V3_S4_LED =PP3V3_S4_LED

66 3 66 3

1

R0302

1K

5% 1/16W MF-LF 402

2

SILK_PART=2

A

CRITICAL

LE0302

GRN-6MCD-0.03A

0805

K

CORE_VOLTAGES_ON

CRITICAL

Q0302

DMN5L06VK-7

SOT563

VER 3

3

D

MEM_GOOD Led

1

R0303

1K

5% 1/16W MF-LF 402

2

SILK_PART=3

A

CRITICAL

LE0303

GRN-6MCD-0.03A

0805

K

MEMORY_GOOD

CRITICAL

Q0302

SOT563

VER 3

6

D

DMN5L06VK-7

=PP3V3_S0_LED

66

1

R0304

1K

5% 1/16W MF-LF 402

2

LCD_SHOULD_ON_RMEMORY_GOOD_RCORE_VOLTAGES_ON_R

SILK_PART=4

A

CRITICAL

LE0304

GRN-6MCD-0.03A

0805

K

VIDEO_ON_L

D

39

IN

C

65 43 17

5

G S

IN

ALL_SYS_PWRGD MEM_GOOD_LED

4

15

IN

2

G S

1

C

B

A

PAGE TITLE

DEBUG LEDS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=10/22/2013SYNC_MASTER=J70_GAREN

051-00081

3.0.0

3 OF 123

3 OF 81

A

D

345678

2 1

D

CPU HEATSINK MOUNTING FEATURES

SH0473

STDOFF-4.5OD.98H-1.1-3.40-TH

CRITICAL

1

STDOFF-4.5OD.98H-1.1-3.40-TH

SH0474

CRITICAL

1

www.qdzbwx.com

STDOFF-4.5OD.98H-1.1-3.40-TH

HEATSINK STABILITY MOUNTING FEATURES

SH0475

CRITICAL

1

SH0476

CRITICAL

STDOFF-4.5OD.98H-1.1-3.40-TH

1

WIRELESS CARD MTG HOLES

APN:998-01406 (Plated holes, 2.1mm inner diameter, 4.3mm top pad, 5.1mm bottom pad)

ZH0421

4P3R2P1-5P5B-NSP

1

ZH0422

4P3R2P1-5P5B-NSP

1

D

C

APN:860-1532

CRITICAL

SH0477

STDOFF-4.5OD.98H-1.1-3.40-TH

1

Rear Cover

CRITICAL

SH0479

STDOFF-4.5OD.98H-1.1-3.40-TH

1

C

B

APN:998-4559 (Plated holes, 4mm inner diameter, 8mm pad)

ZH0413

7P0R4P0-8P0B-NSP

1

ZH0414

7P0R4P0-8P0B-NSP

1

ZH0415

7P0R4P0-8P0B-NSP

1

ZH0416

7P0R4P0-8P0B-NSP

1

B

J117 SPRINGS

APN:870-00908 SPRING FINGER 4.2X2.5X5.3 APN:870-00909 SPRING FINGER 4.2X2.5X5.81

SH0480

2288394-4

1

SM

SH0481

2288394-5

1

SM

SH0482

2288394-5

1

SM

SSD STANDOFF

APN: 860-00198

SSD:Y

CRITICAL

NUT0413

5.5OD2.65ID-6.5H-SM

1

A

PAGE TITLE

Holes/PD parts

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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051-00081

3.0.0

4 OF 123

4 OF 81

A

D

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DDI Port Assignments:

TBT Sink 0

TBT Sink 1

(MUXed with HDMI

if necessary)

345678

2 1

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 1 OF 19

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

26 80

OUT

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<3>

C54 C55 B58 C58 B55 A55 A57 B57

C51 C50 C53 B54 C49 B50 A53 B53

DDI1_TXN0 DDI1_TXP0 DDI1_TXN1 DDI1_TXP1 DDI1_TXN2 DDI1_TXP2 DDI1_TXN3 DDI1_TXP3

DDI2_TXN0 DDI2_TXP0 DDI2_TXN1 DDI2_TXP1 DDI2_TXN2 DDI2_TXP2 DDI2_TXN3 DDI2_TXP3

DDI

EDP_TXN0 EDP_TXP0 EDP_TXN1 EDP_TXP1

EDP_TXN2 EDP_TXP2 EDP_TXN3 EDP_TXP3

EDP

EDP_AUXN EDP_AUXP

EDP_RCOMP

EDP_DISP_UTIL

C45 B46 A47 B47

C47 C46 A49 B49

A45 B45

D20 A43

DP_INT_ML_N<0>

DP_INT_ML_P<0>

DP_INT_ML_N<1>

DP_INT_ML_P<1>

DP_INT_ML_N<2>

DP_INT_ML_P<2>

DP_INT_ML_N<3>

DP_INT_ML_P<3>

DP_INT_AUX_N

DP_INT_AUX_P

MCP_EDP_RCOMP

71

NC_EDP_DISP_UTILDP_TBTSNK1_ML_C_P<3>

OUT

BI

40 80

40

40 80

eDP Port Assignment:

Internal panel

PPVCOMP_S0_CPU

1

R0530

24.9

1% 1/20W MF 201

2

PLACE_NEAR=U0500.D20:12.7mm

D

8

C

TP0531

TP0501

TP

TP-P6

TP

TP-P6

MCP Daisy-Chain Strategy:

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

NO_TEST

MCP_DC_AW2_AY2

5

MCP_DC_AW3_AY3

5

1

MCP_DC_AY60

MCP_DC_AW61_AY61

5

MCP_DC_AW62_AY62

5

MCP_DC_B2

MCP_DC_A3_B3

5

MCP_DC_A61_B61

5

MCP_DC_B62_B63

MCP_DC_C1_C2

1

AY2

AY3 AY60 AY61 AY62

B2

B3 B61 B62 B63

C1

C2

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

SYM 17 OF 19

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF DAISY_CHAIN_NCTF

Each corner of CPU has two testpoints.

Other corner test signals connected in

daisy-chain fashion. Continuity should

exist between both TP's on each corner.

NO_TEST

A3 A4

A60 A61 A62 AV1 AW1 AW2 AW3 AW61 AW62 AW63

1

MCP_DC_A3_B3

MCP_DC_A4

MCP_DC_A60

MCP_DC_A61_B61

MCP_DC_A62

MCP_DC_AV1

MCP_DC_AW1

MCP_DC_AW2_AY2

MCP_DC_AW3_AY3

MCP_DC_AW61_AY61

MCP_DC_AW62_AY62

MCP_DC_AW63

C

5

1

TP

TP0500

TP-P6

1

TP

TP0510

5

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

1

TP

TP-P6

TP0511

TP0520

TP0521

TP0530

B

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 18 OF 19

AT2

RSVD

AU44

NC NC

AV44

NC NC

D15

F22

H22

J21

RSVD RSVD RSVD

SPARE

RSVD RSVD RSVD RSVD

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

N23 R23 T23 U10

AL1 AM11 AP7 AU10 AU15 AW14 AY14

NCNC

NC

B

A

PAGE TITLE

CPU GFX/NCTF/RSVD

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

051-00081

3.0.0

5 OF 123

5 OF 81

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www.qdzbwx.com

CRITICAL

OMIT_TABLE

345678

2 1

D

66 57 17 16 15 8

71 57 44 43

=PP1V05_S0_CPU_VCCST

CPU_PROCHOT_L

R0651

121

1%

1/20W

MF

201

R0650

200

1%

1/20W

MF

201

BI

1

2

U0500

BROADWELL-ULT

2C+GT2

BGA

D61

NC

62

5%

1/20W

MF

201

100

1%

1/20W

MF

201

1

71 44

2

1

2

R0611

56

2 1

5%

1/20W

MF

201

R0620

10K

5%

1/20W

MF

201

1

2

18

OUT

BI

OUT

CPU_CATERR_L

CPU_PECI

CPU_PROCHOT_R_L

71

CPU_PWRGD

70

CPU_SM_RCOMP<0>

70

CPU_SM_RCOMP<1>

70

CPU_SM_RCOMP<2>

NC_MEM_RESET_L

CPU_MEMVTT_PWR_EN_LSVDDQ

AU60 AV60 AU61

AV15

AV61

R0610

1

2

R0652

PROC_DETECT* PRDY*

K61

CATERR*

N62

PECI

K63

PROCHOT*

C61

PROCPWRGD

SM_RCOMP0 SM_RCOMP1 SM_RCOMP2

SM_DRAMRST*

SM_PG_CNTL1

SYM 2 OF 19

THERMAL

MISC

PWRDDR3

(IPU)

JTAG

(IPD)

(IPU)

PREQ*

PROC_TCK

PROC_TMS

PROC_TRST*

PROC_TDI

PROC_TDO

(IPU)

BPM0* BPM1* BPM2* BPM3* BPM4* BPM5* BPM6* BPM7*

J62 K62

E60 E61 E59

F63 F62

J60 H60 H61 H62 K59 H63 K60 J61

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L

XDP_CPU_TCK

XDP_CPU_TMS

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TDO

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<6>

XDP_BPM_L<7>

OUT

IN

OUT

BI

16

73 16

71 16

73 16

D

C

B

A

PLACE_NEAR=U0500.AU60:12.7mm

PLACE_NEAR=U0500.AV60:12.7mm

CFG<10>:SAFE MODE BOOT 1 = NORMAL OPERATION 0 = POWER FEATURES NOT ACTIVE

CFG<9> :NO SVID-CAPABLE VR 1 = VR SUPPORTS SVID 0 = VR DOES NOT SUPPORT SVID

CFG<8> :ALLOW NOA ON LOCKED UNITS 1 = NORMAL OPERATION 0 = NOA ALWAYS UNLOCKED

CFG<4> :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

CFG<1> :PCH-LESS MODE 1 = NORMAL OPERATION 0 = PCH-LESS MODE

CFG<0> :RESET SEQUENCE STALL 1 = NORMAL OPERATION 0 = STALL AFTER PCU PLL LOCK

These can be placed close to J1800

and are only for debug access

CPU_CFG<10>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<1>

CPU_CFG<0>

NOSTUFF

R0640

1K

5%

1/20W

MF

201

NOSTUFF

1

2

1

R0639

1K

5% 1/20W MF 201

2

NOSTUFF

R0638

1K

5%

1/20W

MF

201

1

2

NOSTUFF

1

R0631

1K

5% 1/20W MF 201

2

NOSTUFF

1

R0630

1K

5% 1/20W MF 201

2

NOTE: Pre-ES2 CPUs have issue with Sx cycling, must set CFG<9> low to avoid

issue, but this locks CPU VR at 1.7V Vboot (CPU Sighting #4391569).

CPU_CFG<4>

1

R0634

1K

5% 1/20W MF 201

2

73 16 6

PLACE_NEAR=U0500.AU61:12.7mm

PLACE_NEAR=U0500.C61:12.7mm

C

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 19 OF 19

NC

AC60 AC62 AC63

AA63 AA60

Y62 Y61 Y60 V62 V61 V60 U60 T63 T62 T61 T60

AA62

U63

AA61

U62

V63

A5

E1 D1

J20 H18 B12

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15

CFG16 CFG18 CFG17 CFG19

(IPU)

CFG_RCOMP

RSVD

RSVD RSVD RSVD RSVD TD_IREF

RESERVED

RSVD_TP RSVD_TP

RSVD_B43

RSVD_TP RSVD_TP

RSVD_TP

RSVD

RSVD RSVD

PROC_OPI_COMP

RSVD RSVD

73 16 6

73 16

73 16 6

73 16

73 16 6

73 16

73 16 6

R0680

49.9

1/20W

1%

MF

201

BI

1

2

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<2>

CPU_CFG<3>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<12>

CPU_CFG<13>

CPU_CFG<14>

CPU_CFG<15>

CPU_CFG<16>

CPU_CFG<18>

CPU_CFG<17>

CPU_CFG<19>

71

CPU_CFG_RCOMP

PCH_TD_IREF

1

R0685

8.25K

1% 1/20W MF 201

2

www.qdzbwx.com

VSS VSS

AV63 AU63

C63 C62

B43

A51 B51

L60

N60

W23 Y22

AY15

AV62 D58

P22 N21

P20 R20

NC

NC_MCP_RSVD_AV63

NC_MCP_RSVD_AU63

TP_MCP_RSVD_C63

TP_MCP_RSVD_C62

NC_MCP_RSVD_A51

NC_MCP_RSVD_B51

NC_MCP_RSVD_L60

CPU_OPI_RCOMP

71

PLACE_NEAR=U0500.AY15:12.7mm

1

R0690

49.9

1% 1/20W MF 201

2

SYNC_MASTER=J117_ANDRES SYNC_DATE=03/24/2014

PAGE TITLE

CPU Misc/JTAG/CFG/RSVD

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

6 OF 123

SHEET

6 OF 81

D

B

A

8 7 5 4 2 1

36

345678

2 1

D

C

B

70 19

CRITICAL

OMIT_TABLE

BI

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

AH63 AH62 AK63 AK62 AH61 AH60 AK61

AK60 AM63 AM62

AP63

AP62 AM61 AM60

AP61

AP60

AP58

AR58 AM57

AK57

AL58 AK58 AR57 AN57 AP55 AR55

AM54

AK54

AL55 AK55 AR54 AN54 AY58

AW58

AY56

AW56

AV58 AU58 AV56 AU56 AY54

AW54

AY52

AW52

AV54 AU54 AV52 AU52 AK40 AK42

AM43 AM45

AK45 AK43

AM40 AM42 AM46

AK46

AM49

AK49

AM48

AK48

AM51

AK51

SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 3 OF 19

MEMORY CHANNEL A

LPDDR3

CAB3

CAB2

CAB1

CAB4

CAB6

CAA5

CAB9

CAB8

CAB5

RSVD1

RSVD2

CAA0

CAA2

CAA4

CAA3

CAA1

CAB7

CAA7

CAA6

CAB0

CAA9

CAA8

SM_VREF_CA

SM_VREF_DQ0

SM_VREF_DQ1

SA_CLK0*

SA_CLK0

SA_CLK1*

SA_CLK1

SA_CKE0 SA_CKE1 SA_CKE2 SA_CKE3

SA_CS0* SA_CS1*

SA_ODT0

SA_RAS*

SA_WE*

SA_CAS*

SA_BA0 SA_BA1 SA_BA2

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8

SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15

SA_DQSN0 SA_DQSN1 SA_DQSN2 SA_DQSN3 SA_DQSN4 SA_DQSN5 SA_DQSN6 SA_DQSN7

SA_DQSP0 SA_DQSP1 SA_DQSP2 SA_DQSP3 SA_DQSP4 SA_DQSP5 SA_DQSP6 SA_DQSP7

AU37 AV37 AW36 AY36

AU43 AW43 AY42 AY43

AP33 AR32

AP32

AY34 AW34 AU34

AU35 AV35 AY41

AU36 AY37 AR38 AP36 AU39 AR36 AV40 AW39 AY39 AU40 AP35 AW41 AU41 AR35 AV42 AU42

AJ61 AN62 AM58 AM55 AV57 AV53 AL43 AL48

AJ62 AN61 AN58 AN55 AW57 AW53 AL42 AL49

AP49

AR51

AP51

MEM_A_CLK_N<0>MEM_A_DQ<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_CAB<3>

MEM_A_CAB<2>

MEM_A_CAB<1>

MEM_A_CAB<4>

MEM_A_CAB<6>

MEM_A_CAA<5>

MEM_A_CAB<9>

MEM_A_CAB<8> MEM_A_CAB<5>

NC_MEM_A_RSVD1

NC_MEM_A_RSVD2

MEM_A_CAA<0>

MEM_A_CAA<2>

MEM_A_CAA<4>

MEM_A_CAA<3>

MEM_A_CAA<1>

MEM_A_CAB<7>

MEM_A_CAA<7>

MEM_A_CAA<6>

MEM_A_CAB<0>

MEM_A_CAA<9>

MEM_A_CAA<8>

MEM_A_DQS_N<0>

MEM_A_DQS_N<1>

MEM_A_DQS_N<2>

MEM_A_DQS_N<3>

MEM_A_DQS_N<4>

MEM_A_DQS_N<5>

MEM_A_DQS_N<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<0>

MEM_A_DQS_P<1>

MEM_A_DQS_P<2>

MEM_A_DQS_P<3>

MEM_A_DQS_P<4>

MEM_A_DQS_P<5>

MEM_A_DQS_P<6>

MEM_A_DQS_P<7>

CPU_DDR_VREFCA

CPU_DDR_A_VREFDQ

CPU_DDR_B_VREFDQ

OUT

BI

OUT

20

70 25 21

70 25 22

70 25 21

70 25 22

70 25 22 21

70 25 22

70 25 21

70 25 22

70 25 21

70 25 22

70 25 21

70 25 22

70 25 21

70 19

BI

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<6>

MEM_B_DQ<9>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<14>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36> MEM_B_CAB<0>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<46>

MEM_B_DQ<48>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

AY31

AW31

AY29

AW29

AV31 AU31 AV29 AU29 AY27

AW27

AY25

AW25

AV27 AU27 AV25 AU25

AM29

AK29

AL28 AK28 AR29 AN29 AR28 AP28 AN26 AR26 AR25 AP25 AK26

AM26

AK25

AL25 AY23

AW23

AY21

AW21

AV23 AU23 AV21 AU21 AY19

AW19

AY17

AW17

AV19 AU19 AV17 AU17 AR21 AR22

AL21

AM22

AN22 AP21 AK21 AK22 AN20 AR20 AK18

AL18 AK20

AM20

AR18 AP18

SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4

SB_DQ9

SB_DQ12

SB_DQ14

SB_DQ18

SB_DQ22

SB_DQ36

SB_DQ39

SB_DQ48

SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 4 OF 19

MEMORY CHANNEL B

LPDDR3

CAB3

CAB2

CAB1

CAB4

CAB6

CAA5

CAB9

CAB8

CAB5

RSVD3

RSVD4

CAA0

CAA2

CAA4

CAA3

CAA1

CAB7

CAA7

CAA6

CAB0

CAA9

CAA8

SB_CK0*

SB_CK0

SB_CK1*

SB_CK1

SB_CKE0SB_DQ5 SB_CKE1SB_DQ6 SB_CKE2SB_DQ7 SB_CKE3SB_DQ8

SB_CS0*SB_DQ10 SB_CS1*SB_DQ11

SB_ODT0SB_DQ13

SB_RAS*SB_DQ15

SB_WE*SB_DQ16

SB_CAS*SB_DQ17

SB_BA0SB_DQ19 SB_BA1SB_DQ20 SB_BA2SB_DQ21

SB_MA0SB_DQ23 SB_MA1SB_DQ24 SB_MA2SB_DQ25 SB_MA3SB_DQ26 SB_MA4SB_DQ27 SB_MA5SB_DQ28 SB_MA6SB_DQ29 SB_MA7SB_DQ30 SB_MA8SB_DQ31

SB_MA9SB_DQ32 SB_MA10SB_DQ33 SB_MA11SB_DQ34 SB_MA12SB_DQ35 SB_MA13 SB_MA14SB_DQ37 SB_MA15SB_DQ38

SB_DQSN0SB_DQ40 SB_DQSN1SB_DQ41 SB_DQSN2SB_DQ42 SB_DQSN3SB_DQ43 SB_DQSN4SB_DQ44 SB_DQSN5SB_DQ45 SB_DQSN6SB_DQ46 SB_DQSN7SB_DQ47

SB_DQSP0SB_DQ49 SB_DQSP1SB_DQ50 SB_DQSP2SB_DQ51 SB_DQSP3SB_DQ52 SB_DQSP4SB_DQ53 SB_DQSP5SB_DQ54 SB_DQSP6SB_DQ55 SB_DQSP7SB_DQ56

AM38 AN38 AK38 AL38

AY49 AU50 AW49 AV50

AM32 AK32

AL32

AM35 AK35 AM33

AL35 AM36 AU49

AP40 AR40 AP42 AR42 AR45 AP45 AW46 AY46 AY47 AU46 AK36 AV47 AU47 AK33 AR46 AP46

AW30 AV26 AN28 AN25 AW22 AV18 AN21 AN18

AV30 AW26 AM28 AM25 AV22 AW18 AM21 AM18

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<0>MEM_B_DQ<5>

MEM_B_CKE<1>

MEM_B_CKE<2>MEM_B_DQ<7>

MEM_B_CKE<3>MEM_B_DQ<8>

MEM_B_CS_L<0>MEM_B_DQ<10>

MEM_B_CS_L<1>

MEM_B_ODT<0>MEM_B_DQ<13>

MEM_B_CAB<3>MEM_B_DQ<15>

MEM_B_CAB<2>MEM_B_DQ<16>

MEM_B_CAB<1>MEM_B_DQ<17>

MEM_B_CAB<4>

MEM_B_CAB<6>

MEM_B_CAA<5>

MEM_B_CAB<9>MEM_B_DQ<23>

MEM_B_CAB<8>MEM_B_DQ<24>

MEM_B_CAB<5>MEM_B_DQ<25>

NC_MEM_B_RSVD3

NC_MEM_B_RSVD4

MEM_B_CAA<0>

MEM_B_CAA<2>

MEM_B_CAA<4>

MEM_B_CAA<3>

MEM_B_CAA<1>

MEM_B_CAB<7>

MEM_B_CAA<7>

MEM_B_CAA<6>

MEM_B_CAA<9>MEM_B_DQ<37>

MEM_B_CAA<8>MEM_B_DQ<38>

MEM_B_DQS_N<0>

MEM_B_DQS_N<1>MEM_B_DQ<41>

MEM_B_DQS_N<2>MEM_B_DQ<42>

MEM_B_DQS_N<3>MEM_B_DQ<43>

MEM_B_DQS_N<4>MEM_B_DQ<44>

MEM_B_DQS_N<5>MEM_B_DQ<45>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>MEM_B_DQ<47>

MEM_B_DQS_P<0>MEM_B_DQ<49>

MEM_B_DQS_P<1>MEM_B_DQ<50>

MEM_B_DQS_P<2>MEM_B_DQ<51>

MEM_B_DQS_P<3>

MEM_B_DQS_P<4>

MEM_B_DQS_P<5>

MEM_B_DQS_P<6>

MEM_B_DQS_P<7>MEM_B_DQ<56>

OUT

BI

70 25 23

70 25 24

70 25 23

70 25 24

70 25 24 23

70 25 24

70 25 23

70 25 24

70 25 23

70 25 24

70 25 23

70 25 24

70 25 23

70 19

D

C

B

A

PAGE TITLE

CPU DDR3/LPDDR3 Interfaces

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

051-00081

3.0.0

7 OF 123

7 OF 81

A

D

C

B

BDW-ULT current estimates from Broadwell Mobile ULT Processor EDS vol 1, doc #514405, v1.5.

WPT-LP current estimates from Wildcat Point-LP PCH EDS, doc #515621, v1.0.

Numbers may not be accurate values as of 08/26/2014

66 11

1838mA Max

66

29mA Max[1]

14 11

=PP1V05_S0_PCH_VCCHSIO

=PP1V05_S0_PCH_VCCIO_HSIO

PP1V05_S0_PCH_VCCUSB3PLL

K9

VCCHSIO

L10

VCCHSIO VCCHSIO

N8

VCC1_05

P9

VCC1_05

B18

VCCUSB3PLL

BROADWELL-ULT

SYM 13 OF 19

41mA Max

12 11

PP1V05_S0_PCH_VCCSATA3PLL

B11

VCCSATA3PLL

42mA Max

66 57 17 16 15 8 6

78 57

IN

78 57

OUT

78 57

CRITICAL

OMIT_TABLE

U0500

2C+GT2

BGA

RTCSPICORE

=PP1V05_S0_CPU_VCCST

CPU_VIDALERT_L

CPU_VIDSCLK

CPU_VIDSOUT

BI

VCCSUS3_3

VCCRTC

DCPRTC

VCCSPI

VCCASW VCCASW

AH11

AG10M9

AE7

Y8

AG14 AG13

75

1%

1/20W

MF

201

1

2

R0810

1/20W

R0800

R0811

0

21

5%

1/20W

MF

0201

=PP3V3_SUS_PCH_VCCSUS_RTC

0.3mA Max[1]

PPVOUT_S0_PCH_DCPRTC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

=PP3V3_SUS_PCH_VCC_SPI

18mA Max

=PP1V05_S0_PCH_VCCASW

185mA Max[1]

R0812

1/20W

0201

43

5%

MF

201

0

5%

MF

345678

2 1

CRITICAL

OMIT_TABLE

L59

NC

66 10

=PPVMEMIO_S0_CPU

1.4A Max (DDR3: 1.5-1.35V)

1.1A Max (LPDDR3: 1.2V)

AH26

AJ31 AJ33

AJ37 AN33 AP43 AR48 AY35

66 10 8

=PPVCC_S0_CPU

AY40 AY44 AY50

100

5%

1/20W

MF

201

1

NC

AC58

2

NC

AB23

NC

AD23

NC

AA23

NC

AE59

R0860

PLACE_NEAR=U0500.C50:50.8mm

78 57

1

R0802

130

1% 1/20W MF 201

2

21

Max load: 300mA

16

OUT

PPVCCIO_S0_CPU

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

PPVCOMP_S0_CPU

5

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

CPU_VCCSENSE_P

MAKE_BASE=TRUE

NOTE: Aliases not used on CPU supply outputs

to avoid any extraneous connections.

NC

CPU_VIDALERT_R_L

78

CPU_VIDSCLK_R

78

CPU_VIDSOUT_R

78

R0802.2:

21

R0810.2:

R0800.2:

PLACE_NEAR=U0500.L63:6.35mm

PLACE_NEAR=U0500.L62:38.1mm

PLACE_NEAR=R0810.1:2.54mm

71 17 16

57

16

IN

OUT

IN

CPU_VCCST_PWRGD

CPU_VR_EN

CPU_VR_READY

CPU_PWR_DEBUG

NC_CPU_RSVD_P60

NC_CPU_RSVD_P61

NC_CPU_RSVD_N59

TP_CPU_RSVD_N61

NC

AD60

NC

AD59

NC

AA59

NC

AE60

NC

AC59

NC

AG58

NC

66 57 17 16 15 8 6

66 11

=PPVRTC_G3_PCH

=PP1V05_S0_CPU_VCCST

???mA Max

66 13 12

AC22 AE22 AE23

BYPASS=U0500.AE7::6.35mm

66 14 11

66 11 8

1

C0895

0.1UF

10%

6.3V

2

CERM-X5R 0201

C0892

0.1UF

20% 10V

CERM

402

1

2

C0891

0.1UF

20% 10V

CERM

402

BYPASS=U0500.AG10::6.35mm

1

2

BYPASS=U0500.AG10::6.35mm

1

C0890

1UF

10%

6.3V

2

CERM 402

BYPASS=U0500.AG10::6.35mm

AB57

AD57 AG57

RSVD

J58

RSVD

VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ

F59

VCC

N58

RSVD RSVD

E63

VCC_SENSE

RSVD

A59

VCCIO_OUT

E20

VCCIOA_OUT RSVD RSVD RSVD

L62

VIDALERT*

N63

VIDSCLK

L63

VIDSOUT

B59

VCCST_PWRGD

F60

VR_EN

C59

VR_READY

D63

VSS

H59

PWR_DEBUG*

P62

VSS

P60

RSVD_TP

P61

RSVD_TP

N59

RSVD_TP

N61

RSVD_TP

T59

RSVD RSVD RSVD RSVD RSVD RSVD RSVD

U59

RSVD

V59

RSVD

VCCST VCCST VCCST

VCC VCC VCC

C24

VCC

C28

VCC

C32

VCC

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 12 OF 19

HSW ULT POWER

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

C36 C40 C44 C48 C52 C56 E23 E25 E27 E29 E31 E33 E35 E37 E39 E41 E43 E45 E47 E49 E51 E53 E55 E57 F24 F28 F32 F36 F40 F44 F48 F52 F56 G23 G25 G27 G29 G31 G33 G35 G37 G39 G41 G43 G45 G47 G49 G51 G53 G55 G57 H23 J23 K23 K57 L22 M23 M57 P57 U57 W57

=PPVCC_S0_CPU

66 10 8

32A Max

D

C

B

11

66 17 11

66 11

11

WF: RSVD on Sawtooth Peak rev 1.0

PP1V05_S0_PCH_VCCAPLL_OPI

57mA Max

=PP1V5_S0_PCH_VCCSUSHDA

11mA Max

=PP3V3_SUS_PCH_VCCSUS_GPIO

59mA Max[1]

=PP3V3_S5_PCH_VCCDSW

114mA Max

=PP3V3_S0_PCH_VCC3_3_GPIO

40mA Max[1]

PP1V05_S0_PCH_VCC_ICC

VCCCLK: 200mA Max

NC

Y20

AA21

W21

J13

AH14

AH13

AC9 AA9

AH10

V8

W9

J18

K19

VCCAPLL VCCAPLL VCCAPLL

DCPSUS3

VCCHDA

VRM/USB2/AZALIA

DCPSUS2

VCCSUS3_3 VCCSUS3_3

VCCDSW3_3

VCC3_3 VCC3_3

VCCCLK VCCCLK

AZALIA/HDA

USB3 OPI HSIO

THERMAL SENSOR

VCC1P05 VCC1P05 VCC1P05 VCC1P05 VCC1P05

DCPSUSBYP DCPSUSBYP

VCCASW VCCASW VCCASW

DCPSUS1 DCPSUS1

VCCTS1_5

VCC3_3 VCC3_3

J11 H11 H15 AE8 AF22

AG19 AG20

AE9 AF9 AG8

AD10 AD8

J15

K14 K16

=PP1V05_S0_PCH_VCC

1499mA Max[1]

PPVOUT_S5_PCH_DCPSUSBYP_R

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

=PP1V05_S0_PCH_VCCASW

473mA Max[1]

NC

=PP1V5_S0_PCH_VCCTS

3mA Max

=PP3V3_S0_PCH_VCCTS

1mA Max[1]

66 11

Powered in DeepSx

66

66 11

PLACE_NEAR=U0500.AG19:2.54mm

R0899

5.11

1/20W MF-LF

66 11 8

1%

201

21

PPVOUT_S5_PCH_DCPSUSBYP

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

1

C0899

1UF

10%

6.3V

2

CERM 402

BYPASS=U0500.AG19::2.54mm

A

12 11

PP1V05_S0_PCH_VCCACLKPLL

31mA Max

66 11

=PP1V05_S0_PCH_VCCCLK

VCCCLK: 200mA Max

WF: RSVD on Sawtooth Peak rev 1.0

NC

A20

J17 R21 T21 K18

M20

V21

VCCACLKPLL

VCCCLK VCCCLK VCCCLK RSVD RSVD RSVD

SERIAL IO

SUS OSCILLATOR

ICC GPIO/LCC

VCCSDIO VCCSDIO

DCPSUS4

RSVD

U8 T9

AB8

AC20

=PP3V3_S0_PCH_VCCSDIO

17mA Max

NC

WF: RSVD on Sawtooth Peak rev 1.0

NC

66 11

PAGE TITLE

CPU/PCH POWER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

=PP3V3_SUS_PCH_VCCSUS_ICC

66

3.3mA Max[1]

AE20 AE21

VCCSUS3_3 VCCSUS3_3

LPT LP POWER

USB2

VCC1_05 VCC1_05

8 7 5 4 2 1

AG16 AG17

=PP1V05_S0_PCH_VCCIO_USB2

213mA Max[1]

66 11

www.qdzbwx.com

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

36

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

8 OF 123

SHEET

8 OF 81

A

345678

2 1

D

C

B

A11 A14 A18 A24 A28 A32 A36 A40 A44 A48 A52 A56

AA1 AA58 AB10 AB20 AB22

AB7 AC61 AD21

AD3 AD63 AE10

AE5

AE58

AF11 AF12 AF14 AF15 AF17 AF18

AG1 AG11 AG21 AG23 AG60 AG61 AG62 AG63 AH17 AH19 AH20 AH22 AH24 AH28 AH30 AH32 AH34 AH36 AH38 AH40 AH42 AH44 AH49 AH51 AH53 AH55 AH57

AJ13 AJ14 AJ23 AJ25 AJ27 AJ29

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 14 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AJ35 AJ39 AJ41 AJ43 AJ45 AJ47 AJ50 AJ52 AJ54 AJ56 AJ58 AJ60 AJ63 AK23 AK3 AK52 AL10 AL13 AL17 AL20 AL22 AL23 AL26 AL29 AL31 AL33 AL36 AL39 AL40 AL45 AL46 AL51 AL52 AL54 AL57 AL60 AL61 AM1 AM17 AM23 AM31 AM52 AN17 AN23 AN31 AN32 AN35 AN36 AN39 AN40 AN42 AN43 AN45 AN46 AN48 AN49 AN51 AN52 AN60 AN63 AN7 AP10 AP17 AP20

AP22 AP23 AP26 AP29

AP3 AP31 AP38 AP39 AP48 AP52 AP54 AP57

AR11 AR15 AR17 AR23 AR31 AR33 AR39 AR43 AR49

AR5

AR52

AT13 AT35 AT37 AT40 AT42 AT43 AT46 AT49 AT61 AT62 AT63

AU1

AU16 AU18 AU20 AU22 AU24 AU26 AU28 AU30 AU33 AU51 AU53 AU55 AU57 AU59

AV14 AV16 AV20 AV24 AV28 AV33 AV34 AV36 AV39 AV41 AV43 AV46 AV49 AV51 AV55

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 15 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AV59 AV8 AW16 AW24 AW33 AW35 AW37 AW4 AW40 AW42 AW44 AW47 AW50 AW51 AW59 AW60 AY11 AY16 AY18 AY22 AY24 AY26 AY30 AY33 AY4 AY51 AY53 AY57 AY59 AY6 B20 B24 B26 B28 B32 B36 B4 B40 B44 B48 B52 B56 B60 C11 C14 C18 C20 C25 C27 C38 C39 C57 D12 D14 D18 D2 D21 D23 D25 D26 D27 D29 D30 D31

D33 D34 D35 D37 D38 D39 D41 D42 D43 D45 D46 D47 D49

D5 D50 D51 D53 D54 D55 D57 D59 D62

D8 E11 E17

F20 F26 F30 F34 F38 F42 F46 F50 F54 F58

F61 G18 G22

G3 G5 G6 G8

H13

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 16 OF 19

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS_SENSE

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS

VSS

H17 H57 J10 J22 J59 J63 K1 K12 L13 L15 L17 L18 L20 L58 L61 L7 M22 N10 N3 P59 P63 R10 R22 R8 T1 T58 U20 U22 U61 U9 V10 V3 V7 W20 W22 Y10 Y59 Y63

V58 AH46 V23 E62 AH16

CPU_VCCSENSE_N

1

R0960

2

100

5% 1/20W MF 201

PLACE_NEAR=U0500.E62:50.8mm

OUT

D

C

78 57

B

A

PAGE TITLE

CPU/PCH GROUNDS

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

051-00081

3.0.0

9 OF 123

9 OF 81

A

D

All Intel recommendations from Intel doc #503160 Shark Bay Ultrabook Platform Power Delivery Design Guide Rev 1.0 unless stated otherwise

CPU VCC Decoupling

Intel recommendation (Table 5-1): 23x 22uF 0805 stuff, 7x 22uF 0805 nostuff

Apple implementation : 18x 10uF 0402 mirrored stuff, 1x 470uF stuff, 50x 10uF mirrored no stuff, 50x 10uF single sided no stuff

=PPVCC_S0_CPU

66 8

J70 implementation : 18x 10uF 0402 mirrored stuff, 32x 10uF single sided no stuff

345678

2 1

D

CRITICAL

1

C105A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C108A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1076

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C105B

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C108C

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1077

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C105D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C108D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107C

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1060

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107B

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1061

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C105E

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C104A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1062

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C105F

2

10UF

20%

6.3V CERM 0402

CRITICAL

1

C104B

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1063

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C106A

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C104C

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C104D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C104E

10UF

20%

6.3V

2

CERM 0402

1

2

These caps are on the top side.

CRITICAL

1

C106B

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C106C

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C106D

10UF

20%

6.3V

2

CERM 0402

CRITICAL

C104F

10UF

20%

6.3V CERM 0402

CRITICAL

1

C106E

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1030

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1070

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1085

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C105C

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1071

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1086

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1072

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1087

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1078

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1091

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1079

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1092

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1080

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1093

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1081

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1094

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1082

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1095

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1083

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1096

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1084

1UF

10% 10V

2

X6S-CERM 0402

CRITICAL

1

C1097

1UF

10% 10V

2

X6S-CERM 0402

D

C

CRITICAL

1

C107E

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C107F

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C108B

10UF

20%

6.3V

2

CERM 0402

1

2

These caps are mirrored top and bottom.

CPU VDDQ DECOUPLING

Intel recommendation (Table 5-4): 4x 2.2uF 0402, 6x 10uF 0603

Apple implementation : 4x 2.2uF 0402, 6x 10uF 0402, 6x 10uF no stuff, 1x 270 uF Bulk

CRITICAL

C1064

10UF

20%

6.3V CERM 0402

CRITICAL

1

C1065

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1066

10UF

20%

6.3V

2

CERM 0402

CRITICAL

1

C1067

10UF

20%

6.3V

2

CERM 0402

These caps are beneath the CPU.

C

These caps are on the bottom side.

B

=PPVMEMIO_S0_CPU

66 8

CRITICAL

1

C1040

2.2UF

20% 10V

2

X6S-CERM 0402

CRITICAL

1

C1042

2.2UF

20% 10V

2

X6S-CERM 0402

CRITICAL

1

C1043

2.2UF

20% 10V

2

X6S-CERM 0402

These caps are on the bottom side.

CRITICAL

1

C1041

2.2UF

20% 10V

2

X6S-CERM 0402

These caps are on the top side.

CRITICAL

1

C1050

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1051

10UF

20% 4V

2

X6S 0402

CRITICAL NO STUFF

1

C109A

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1054

10UF

20% 4V

2

X6S 0402

CRITICAL

1

C1055

10UF

20% 4V

2

X6S 0402

NO STUFF CRITICAL

1

C109E

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF CRITICAL

1

C109D

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1053

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF CRITICAL

1

C109C

10UF

20%

6.3V

2

CERM-X5R 0402-1

These caps are on the bottom side.

NO STUFF CRITICAL

1

C109F

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF CRITICAL

1

C109B

10UF

20%

6.3V

2

CERM-X5R 0402-1

CRITICAL

1

C1052

10UF

20%

6.3V

2

CERM-X5R 0402-1

NO STUFF CRITICAL

1

C1099

10UF

20%

6.3V

2

CERM-X5R 0402-1

These caps are on the top side.

B

A

CRITICAL

1

C1056

270UF-0.006OHM

20% 2V

2

TANT CASE-D2

www.qdzbwx.com

These caps are mirrored top and bottom.

PAGE TITLE

CPU Decoupling

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

10 OF 123

SHEET

10 OF 81

A

8 7 5 4 2 1

36

D

C

66 8

66 14 8

66 8

PCH VCCDSW3_3 BYPASS

(PCH 3.3V DSW PWR)

=PP3V3_S5_PCH_VCCDSW

PCH VCCSPI BYPASS

(PCH 3.3V SPI PWR)

=PP3V3_SUS_PCH_VCC_SPI

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SUSPEND PWR)

=PP3V3_SUS_PCH_VCCSUS_GPIO

PCH VCCSUS3_3 BYPASS

(PCH 3.3V SUSPEND RTC PWR)

=PP3V3_SUS_PCH_VCCSUS_RTC

NO STUFF

1UF

10%

6.3V CERM

402

1

2

C1200

BYPASS=U0500.AH10::6.35mm

NO STUFF

20% 10V

CERM

402

22UF

20%

6.3V

603

1UF

10%

6.3V CERM

402

1

2

1

2

1

2

C1202

0.1UF

BYPASS=U0500.Y8::6.35mm

C1204

X5R-CERM-1

BYPASS=U0500.AC9::12.7mm

C1206

BYPASS=U0500.AH11::6.35mm

345678

2 1

PCH VCCASW BYPASS

PCH VCC3_3 BYPASS

(PCH 3.3V GPIO/LPC PWR)

=PP3V3_S0_PCH_VCC3_3_GPIO =PP1V05_S0_PCH_VCCIO_USB2

66 8 66 8

(PCH 1.05V ME CORE PWR)

=PP1V05_S0_PCH_VCCASW

66 8

PCH VCCIO BYPASS

(PCH 1.05V USB2 PWR)

NO STUFF

1

C1251

1UF

10%

6.3V

2

CERM 402

20%

6.3V

603

1

2

C1212

22UF

X5R-CERM-1

BYPASS=U0500.V8::12.7mm

20%

6.3V

603

1

2

C1250

22UF

X5R-CERM-1

BYPASS=U0500.AE9::12.7mm

BYPASS=U0500.AE9::6.35mm

PCH VCC3_3 BYPASS

(PCH 3.3V THERMAL PWR)

=PP3V3_S0_PCH_VCCTS

66 8

20% 10V

CERM

402

1

2

C1214

0.1UF

BYPASS=U0500.K14::6.35mm

PCH VCC BYPASS

(PCH 1.05V CORE PWR)

=PP1V05_S0_PCH_VCC

66 8

20%

6.3V

1

2

C1255

10UF

CERM-X5R

0402-1

BYPASS=U0500.J11::12.7mm

BYPASS=U0500.J11::6.35mm

1

C1256

1UF

10%

6.3V

2

CERM 402

BYPASS=U0500.AE8::6.35mm

1

C1257

1UF

10%

6.3V

2

CERM 402

PCH VCCCLK BYPASS

(PCH 1.05V CLK PWR)

=PP1V05_S0_PCH_VCCCLK

66 8

BYPASS=U0500.J17::6.35mm

PCH VCCHSIO BYPASS

(PCH 1.05V PCIe/SATA/USB3 PWR)

=PP1V05_S0_PCH_VCCHSIO

66 8

C1260

BYPASS=U0500.K9::6.35mm

1

1UF

10%

6.3V

2

CERM

402

BYPASS=U0500.L10::6.35mm

C1261

BYPASS=U0500.M9::6.35mm

1UF

10%

6.3V CERM

402

1

2

1

C1262

10UF

20%

6.3V

2

CERM-X5R 0402-1

BYPASS=U0500.AG16::6.35mm

C1266

1

1UF

10%

6.3V

2

CERM

402

BYPASS=U0500.R21::6.35mm

C1264

1UF

10%

6.3V CERM

402

C1267

1UF

10%

6.3V CERM

402

1

2

D

1

2

C

B

66 8

66 17 8

PCH VCCSDIO BYPASS

(PCH 3.3V SDIO PWR)

=PP3V3_S0_PCH_VCCSDIO

PCH VCCSUSHDA BYPASS

(PCH 1.5V HDA PWR)

=PP1V5_S0_PCH_VCCSUSHDA

1UF

10%

6.3V CERM

402

1UF

10%

6.3V CERM

402

1

2

1

2

C1208

BYPASS=U0500.U8::6.35mm

C1210

BYPASS=U0500.AH14::6.35mm

=PP1V05_S0_PCH_PLLFILTERS

66

R1270

0

21

PP1V05_S0_PCH_VCCACLKPLL_R

5% 1/16W MF-LF

402

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

R1275

0

21

PP1V05_S0_PCH_VCC_ICC_R

5% 1/16W MF-LF

402

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

R1280

0

21

5% 1/16W MF-LF

402

CRITICAL

NO STUFF

L1280

2.2UH-240MA-0.221OHM

0603

CRITICAL

L1270

2.2UH-240MA-0.221OHM

21

0603

C1270

CERM-X5R

0805-1

BYPASS=U0500.A20::12.7mm

1

47UF

20%

4V

2

BYPASS=U0500.A20::12.7mm

CRITICAL

L1275

2.2UH-240MA-0.221OHM

21

0603

C1275

CERM-X5R

0805-1

BYPASS=U0500.J18::12.7mm

PCH OPI VCCAPLL FILTER/BYPASS

1

47UF

20%

4V

2

BYPASS=U0500.J18::12.7mm

47UF

20%

4V

47UF

20%

4V

1

2

1

2

C1271

CERM-X5R

0805-1

BYPASS=U0500.A20::6.35mm

C1276

CERM-X5R

0805-1

BYPASS=U0500.J18::6.35mm

PCH VCCACLKPLL FILTER/BYPASS

(PCH 1.05V ACLK PLL PWR)

PP1V05_S0_PCH_VCCACLKPLL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

1

C1272

1UF

10% 10V

2

X5R 402-1

PCH VCCCLK FILTER/BYPASS

(PCH 1.05V VCCCLK PWR)

PP1V05_S0_PCH_VCC_ICC

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

1

C1277

1UF

10% 10V

2

X5R 402-1

12 8

31mA Max

8

??mA Max

B

(PCH 1.05V OPI PLL PWR)

PP1V05_S0_PCH_VCCAPLL_OPI

21

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

57mA Max

8

=PP1V05_S0_PCH_VCCPLL_HSIO

66

83mA Max

NO STUFF

C1280

47UF

20%

4V

CERM-X5R

0805-1

BYPASS=U0500.AA21::12.7mm

CRITICAL

L1290

2.2UH-240MA-0.221OHM

21

0603

C1290

47UF

20%

4V

CERM-X5R

0805-1

BYPASS=U0500.B11::12.7mm

NO STUFF

20%

4V

1

2

1

C1281

47UF

2

BYPASS=U0500.AA21::6.35mm

CERM-X5R

0805-1

NO STUFF

20%

4V

1

2

1

C1291

47UF

2

BYPASS=U0500.B11::12.7mm

CERM-X5R

0805-1

BYPASS=U0500.B11::6.35mm

1

C1282

1UF

10% 10V

2

X5R 402-1

PCH VCCSATA3PLL FILTER/BYPASS

(PCH 1.05V SATA3 PLL PWR)

PP1V05_S0_PCH_VCCSATA3PLL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

1

C1292

1UF

10% 10V

2

X5R 402-1

12 8

42mA Max

A

WPT-LP current estimates from Wildcat Point-LP PCH EDS, doc #515621, v1.0

These numbers may not be accurate as of 08/26/2014

8 7 5 4 2 1

www.qdzbwx.com

CRITICAL

L1295

2.2UH-240MA-0.221OHM

0603

BYPASS=U0500.B18::12.7mm

21

C1295

47UF

20%

4V

CERM-X5R

0805-1

NO STUFF

20%

4V

1

2

1

C1296

47UF

2

BYPASS=U0500.B18::6.35mm

CERM-X5R

0805-1

PCH VCCUSB3PLL FILTER/BYPASS

(PCH 1.05V USB3 PLL PWR)

PP1V05_S0_PCH_VCCUSB3PLL

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0750 VOLTAGE=1.05V

1

C1297

1UF

10% 10V

2

X5R 402-1

41mA Max

SYNC_MASTER=J117_ANDRES

PAGE TITLE

14 8

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

PCH Decoupling

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2014

051-00081

3.0.0

12 OF 123

11 OF 81

A

D

36

345678

2 1

D

C

66 13 8

=PPVRTC_G3_PCH

44

IN

R1300

20K

5%

1/20W

MF

201

C1300

1UF

10% 10V X5R

402-1

RTC_RESET_L

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 5 OF 19

RTCJTAG

AUDIO

SATA

SATA_RN0/PERN6_L3

SATA_RP0/PERP6_L3

SATA_TN0/PETN6_L3

SATA_TP0/PETP6_L3

SATA_RN1/PERN6_L2

SATA_RP1/PERP6_L2

SATA_TN1/PETN6_L2

SATA_TP1/PETP6_L2

SATA_RN2/PERN6_L1

SATA_RP2/PERP6_L1

SATA_TN2/PETN6_L1

SATA_TP2/PETP6_L1

SATA_RN3/PERN6_L0

SATA_RP3/PERP6_L0

SATA_TN3/PETN6_L0

SATA_TP3/PETP6_L0

SATA0GP/GPIO34 SATA1GP/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37

(IPU)

SATA_IREF

RSVD

SATA_RCOMP

SATALED*RSVD

J5 H5

B15 A15

J8 H8

A17 B17

J6 H6

B14 C15

F5 E5

C17 D17

V1 U1 V6 AC1

A12

L11

K10

C12

U3

NC

SATA_HDD_D2R_N

SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

NC

PCIE_SSD_D2R_N<1>

PCIE_SSD_D2R_P<1>

PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<1>

PCIE_SSD_D2R_N<0>

PCIE_SSD_D2R_P<0>

PCIE_SSD_R2D_N<0>

PCIE_SSD_R2D_P<0>

SSD_XDP_PCIE3_SEL_L

SSD_XDP_PCIE2_SEL_L

SSD_XDP_PCIE1_SEL_L

SSD_XDP_PCIE0_SEL_L

73

PCH_SATA_RCOMP

PCH_SATALED_L

12

Port assignments:

IN

OUT

73 33

Primary HDD (SATA)

SSD Lane 2 (PCIe, unused)

IN

OUT

IN

OUT

73 32

16 12

SSD Lane 1 (PCIe)

SSD Lane 0 (PCIe)

PCIE = GND

SATA = 100K PU (3V3S0)

PP1V05_S0_PCH_VCCSATA3PLL

1

R1370

3.01K

1% 1/20W MF 201

2

PLACE_NEAR=U0500.C12:2.54mm

D

11 8

C

330K

5%

1/20W

MF

201

74 51

1

2

OUT

1

R1301

1M

5% 1/20W MF 201

2

PCH_INTRUDER_L

PCH_INTVRMEN

PCH_SRTCRST_L

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDOUT

R1310

R1311

R1312

R1313

33

100

33

74 17

74 51

IN

OUT

21

5% 201MF

PLACE_NEAR=U0500.AW8:6.35mm

21

PLACE_NEAR=U0500.AV11:6.35mm

21

PLACE_NEAR=U0500.AU8:6.35mm

IN

21

5% MF

PLACE_NEAR=U0500.AU11:6.35mm

PCH_CLK32K_RTCX1

PCH_CLK32K_RTCX2

HDA_BIT_CLK_R

74

1/20W

74

HDA_SYNC_R

74

HDA_RST_R_L

HDA_SDIN0

TP_HDA_SDIN1

67

HDA_SDOUT_R

74 17

1/20W 201

NC_PCH_I2S1_TXD

NC_PCH_I2S1_SFRM

NC_PCH_I2S1_SCLK

16

73 16

16

IN

OUT

IN

BI

XDP_PCH_TRST_L

XDP_PCH_TCK

XDP_PCH_TDI

XDP_PCH_TDO

XDP_PCH_TMS

PCH_JTAGX

AW5

AW8

AV11

201MF5% 1/20W

AY10 AU12

AU11

AW10

AV10

AU62

AE62

AD61

AE61

AD62

AL11

NC

AE63

NC

RTCX1

AY5

RTCX2

AU6

INTRUDER*

AV7

INTVRMEN

AV6

SRTCRST*

AU7

RTCRST*

HDA_BCLK/I2S0_SCLK

HDA_SYNC/I2S0_SFRM

AU8

HDA_RST*/I2S_MCLK

(IPD-PLTRST#)

HDA_SDI0/I2S0_RXD HDA_SDI1/I2S1_RXD

HDA_SDO/I2S0_TXD

(IPD-PLTRST#)

HDA_DOCK_EN*/I2S1_TXD HDA_DOCK_RST*/I2S1_SFRM

AY8

I2S1_SCLK

PCH_TRST*

PCH_TCK

PCH_TDI

(IPD)

(IPU)

PCH_TDO

PCH_TMS

(IPU)

RSVD

AC4

RSVD

JTAGX

AV2

(IPD)

1

2

1

2

1

R1303

20K

5% 1/20W MF 201

2

1

C1303

1UF

10% 10V

2

X5R 402-1

R1302

B

NOTE: Haswell ULT requires that CLQREQ_n be mapped to ROOT_PORT_n+1

to properly support CLKREQs for PCIE devices.

72 31

31 12

72 34

34 12

OUT

IN

OUT

IN

TP_PCIE_CLK100M_FWN

67

TP_PCIE_CLK100M_FWP

67

PCIE_CLKREQ0_L

12

TP_PCIE_CLK100M_CAMERAN

67

TP_PCIE_CLK100M_CAMERAP

67

PCIE_CLKREQ1_L

12

PCIE_CLK100M_AP_N

PCIE_CLK100M_AP_P

AP_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

ENETSD_CLKREQ_L

C43 C42

U2

B41 A41

Y5

C41 B42

AD1

B38 C37

N1

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

SYM 6 OF 19

CLKOUT_PCIE_N0 CLKOUT_PCIE_P0

PCIECLKRQ0*/GPIO18

CLKOUT_PCIE_N1 CLKOUT_PCIE_P1

PCIECLKRQ1*/GPIO19

CLKOUT_PCIE_N2 CLKOUT_PCIE_P2

PCIECLKRQ2*/GPIO20

CLKOUT_PCIE_N3 CLKOUT_PCIE_P3

PCIECLKRQ3*/GPIO21

BGA

XTAL24_IN

XTAL24_OUT

CLOCK SIGNALS

DIFFCLK_BIASREF

TESTLOW TESTLOW TESTLOW TESTLOW

RSVD RSVD

A25 B25

K21 M21

C26

C35 C34 AK8 AL8

NC

PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT

PCH_DIFFCLK_BIASREF

PCH_TESTLOW_C35

PCH_TESTLOW_C34

PCH_TESTLOW_AK8

PCH_TESTLOW_AL8

IN

OUT

74 17

PP1V05_S0_PCH_VCCACLKPLL

1

R1380

3.01K

1% 1/20W MF 201

2

PLACE_NEAR=U0500.C26:2.54mm

R1390 R1391 R1392 R1393

10K

11 8

B

21

5%

21

5%

21

5%

1/20W MF 201

MF1/20W5% 201

MF 2011/20W

201MF1/20W

A

=PP3V3_S0_PCH_GPIO

R1320 R1321 R1322 R1323 R1324 R1325 R1326 R1327 R1328 R1329 R1330

100K

1K

66 27 16 15 13

21

5% 2011/20W

21

5% 1/20W 201

21

5% 1/20W MF 201

21

1/20W 201MF5%

MF1/20W

MF

1/20W5% 201

1/20W

MF

MF1/20W 2015%

MF5% 201

MF1/20W5% 201

PCH_SATALED_L

ENETSD_CLKREQ_L

2015%

PCIE_CLKREQ1_L

2015% 1/20W

AP_CLKREQ_L

PCIE_CLKREQ0_L

TBT_CLKREQ_L

SSD_CLKREQ_L

SSD_XDP_PCIE3_SEL_L

SSD_XDP_PCIE2_SEL_L

SSD_XDP_PCIE1_SEL_L

2015% MF1/20W

SSD_XDP_PCIE0_SEL_L

12

72 26

26 12

72 32

32 12

34 12

31 12

26 12

32 12

16 12

OUT

IN

OUT

IN

PCIE_CLK100M_TBT_N

PCIE_CLK100M_TBT_P

TBT_CLKREQ_L

PCIE_CLK100M_SSD_N

PCIE_CLK100M_SSD_P

SSD_CLKREQ_L

A39

CLKOUT_PCIE_N4

B39

CLKOUT_PCIE_P4

U5

PCIECLKRQ4*/GPIO22

B37

CLKOUT_PCIE_N5

A37

CLKOUT_PCIE_P5

T2

PCIECLKRQ5*/GPIO23

CLKOUT_LPC_0

CLKOUT_LPC_1

(IPD-PWROK)

CLKOUT_ITPXDP_N CLKOUT_ITPXDP_P

AN15

AP15

B35 A35

LPC_CLK24M_SMC_R

TP_LPC_CLK24M_LPCPLUS

CKPLUS_WAIVE=NO_TEST

NC_ITPXDP_CLK100MN

NC_ITPXDP_CLK100MP

OUT

74 17

SYNC_MASTER=J117_TONY

PAGE TITLE

SYNC_DATE=05/05/2014

A

PCH Audio/JTAG/SATA/CLK

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

13 OF 123

SHEET

12 OF 81

D

8 7 5 4 2 1

36

345678

2 1

D

44

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

R1402

IN

SMC_PCH_SUSACK_L

0

1 2

5%

1/20W

MF

0201

NOSTUFF

43

OUT

R1400/2 kept for debug purposes.

PCH_SUSACK_L

PM_SYSRST_L

PM_PCH_SYS_PWROK

PM_PCH_PWROK

PM_PCH_APWROK

PLT_RESET_L

PM_RSMRST_PCH_L

R1400

0

5%

1/20W

MF

0201

43 17

65 44 16

1

65 16

2

71 18

65 16 13

16 15

65

IN

OUT

IN

PCH_SUSWARN_L

43 16 13

IN

PM_PWRBTN_L

PCH_GPIO31

13

PM_BATLOW_L

13 13

AK2

AC3

AG2

AY7

AB5

AG7

AW6

AV4

AL7

AJ8

AN4

SYSTEM POWER MANAGEMENT

SUSACK*

(IPU)

SYS_RESET*

SYS_PWROK

PCH_PWROK

APWROK

PLTRST*

RSMRST*

SUSWARN*/SUSPWRDNACK/GPIO30

PWRBTN*

ACPRESENT/GPIO31

(IPU)

(IPD-DeepSx)

BATLOW*/GPIO72

SYM 8 OF 19

(IPD-DeepSx)

DSWVRMEN

DPWROK

WAKE*

CLKRUN*/GPIO32

SUS_STAT*/GPIO61

SUSCLK/GPIO62

SLP_S5*/GPIO63

SLP_S4*

SLP_S3*

SLP_A*

SLP_SUS*

AW7

AV5

AJ5

V5

AG4

AE6

AP5

AJ6

AT4

AL5

AP4

PCH_DSWVRMEN

PM_RSMRST_PCH_L

PCIE_WAKE_L

PM_CLKRUN_L

LPC_PWRDWN_L

PM_CLK32K_SUSCLK_R

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

NC_PM_SLP_A_L

PM_SLP_SUS_L

IN

BI

OUT

35 31 18 13

43 13

43

74 44

64 43 31 13

64 43 13

65 64 44 43 35 13

=PPVRTC_G3_PCH

1

R1450

330K

5% 1/20W MF 201

2

IN

1

R1451

100K

5% 1/20W MF 201

2

66 12 8

D

65 16 13

C

27 13

76 43 13

NC_PM_SLP_S0_L

NC_PCH_SLP_WLAN_L

AM5

SLP_S0*

SLP_WLAN*/GPIO29

SLP_LAN*

AJ7AF3

NC_PCH_SLP_LAN_L

CRITICAL

OMIT_TABLE

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 9 OF 19

NC_EDP_BKLT_PWM

EDP_BKLT_EN

13

EDP_PANEL_PWR

13

IN

TBT_PWR_REQ_L

SMC_RUNTIME_SCI_L

PCH_GPIO79

13

PCH_GPIO80

13

B8

EDP_BKLCTL

A9

EDP_BKLEN

C6

EDP_VDDEN

U6

PIRQA*/GPIO77

P4

PIRQB*/GPIO78

N4

PIRQC*/GPIO79

N2

PIRQD*/GPIO80

eDP

SIDEBAND

DISPLAY

DDPB_CTRLCLK

DDPB_CTRLDATA

(IPD-PLTRST#)

DDPC_CTRLCLK

DDPC_CTRLDATA

(IPD-PLTRST#)

DDPB_AUXN DDPC_AUXN

DDPB_AUXP

NC_PCI_PME_L

AD4

PME*

(IPU)

PCI

DDPC_AUXP

B9 C9

D9 D11

C5 B6

B5 A6

DP_TBTSNK0_DDC_CLK

DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_CLK

DP_TBTSNK1_DDC_DATA

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_P

OUT

BI

OUT

BI

80 30

80 26

C

B

=PP3V3_S5_PCH_GPIO

R1405 R1410 R1452

R1453

1K

10K

100K

1 2

66 50 15

1/20W

U7

L1 L3

R5

L4

GPIO55 GPIO52 GPIO54 GPIO51 GPIO53

DDPB_HPD

DDPC_HPD

EDP_HPD

C8

A8

D6

DP_TBTSNK0_HPD_BUF

DP_TBTSNK1_HPD_BUF

DP_INT_HPD

18

IN

18

IN

40

IN

36 34 13

13

50 40 13

OUT

13

PCH_GPIO55

DP_TBT_SEL

ENET_LOW_PWR

BRD_ID

AP_PCIE_DEV_WAKE

B

MF 2015%

MF5% 2011/20W

PM_BATLOW_L

PCIE_WAKE_L

PCH_GPIO31

PM_PWRBTN_L

MF1/20W5%

201

43 16 13

13

35 31 18 13

13

A

=PP3V3_S0_PCH_GPIO

R1455

R1440 R1441 R1442 R1443

R1448

R1460 R1461 R1462 R1464 R1430 R1431 R1445 R1446 R1447 R1449

10K

100K

10K

100K

1 2

1

1 2

66 27 16 15 12

1/20W5% MF

1/20W

1/20W MF

1/20W

5% 2011/20W MF

2

5% 2011/20W MF

2

5% 2011/20W MF

MF 2015%

MF1/20W 2015%

MF 2015%

MF1/20W 2015%

MF1/20W5% 201

PM_CLKRUN_L

201

TBT_PWR_REQ_L

SMC_RUNTIME_SCI_L

PCH_GPIO79

PCH_GPIO80

2015%

BRD_ID

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

PM_SLP_SUS_L

EDP_BKLT_EN

EDP_PANEL_PWR

PCH_GPIO55

DP_TBT_SEL

ENET_LOW_PWR

AP_PCIE_DEV_WAKE

43 13

27 13

76 43 13

13

64 43 31 13

64 43 13

65 64 44 43 35 13

13

50 40 13

36 34 13

13

www.qdzbwx.com

SYNC_MASTER=J117_ANDRES SYNC_DATE=03/24/2014

PAGE TITLE

PCH PM/PCI/GFX

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

14 OF 123

SHEET

13 OF 81

D

A

8 7 5 4 2 1

36

PCIe Port Assignments:

CRITICAL

OMIT_TABLE

345678

2 1

USB Port Assignments:

D

C

Thunderbolt lane 0

Thunderbolt lane 1

Thunderbolt lane 2

Thunderbolt lane 3

AirPort

Ethernet

USB3 Port Assignments:

Ext C (SS)

Ext D (SS)

72 26

72 31

72 34

75 42

PP1V05_S0_PCH_VCCUSB3PLL

11 8

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

72

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_P<3>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_P<3>

PCIE_AP_D2R_N

PCIE_AP_D2R_P

PCIE_AP_R2D_C_N

PCIE_AP_R2D_C_P

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

USB3_EXTC_D2R_N

USB3_EXTC_D2R_P

USB3_EXTC_R2D_CF_N

USB3_EXTC_R2D_CF_P

USB3_EXTD_D2R_N

USB3_EXTD_D2R_P

USB3_EXTD_R2D_CF_N

USB3_EXTD_R2D_CF_P

PCH_PCIE_RCOMP

R1500

PLACE_NEAR=U0500.A27:6.35mm

3.01K

1%

1/20W

MF

201

F10 E10

C23 C22

F8 E8

B23 A23

PERN5_L0 PERP5_L0

PETN5_L0 PETP5_L0

PERN5_L1 PERP5_L1

PETN5_L1 PETP5_L1

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 11 OF 19

USB2N0 USB2P0

USB2N1 USB2P1

USB2N2 USB2P2

USB2N3 USB2P3

H10

PERN5_L2

G10

B21

C21

E6 F6

B22 A21

PERP5_L2

PETN5_L2 PETP5_L2

PERN5_L3 PERP5_L3

PETN5_L3 PETP5_L3

USB2N4 USB2P4

USB2N5 USB2P5

USB2N6 USB2P6

USB2N7

G11

F11

C29

B30

PERN3 PERP3

PETN3 PETP3

PCI-E

USB

USB2P7

(IPD)

USB3RN1

USB3RP1

F13

G13

B29 A29

PERN4 PERP4

PETN4 PETP4

USB3TN1 USB3TP1

USB3RN2

USB3RP2

G17

PERN1/USB3RN3

F17

PERP1/USB3RP3

C30

PETN1/USB3TN3

C31

PETP1/USB3TP3

F15

PERN2/USB3RN4

G15

PERP2/USB3RP4

B31

PETN2/USB3TN4

A31

PETP2/USB3TP4

E15

NC

1

2

RSVD

E13

RSVD

A27

PCIE_RCOMP

B27 AV3

PCIE_IREF

USB3TN2 USB3TP2

USBRBIAS*

USBRBIAS

RSVD RSVD

OC0*/GPIO40 OC1*/GPIO41 OC2*/GPIO42 OC3*/GPIO43

AN8 AM8

AR7 AT7

AR8 AP8

AR10 AT10

AM15 AL15

AM13 AN13

AP11 AN11

AR13 AP13

G20 H20

C33 B34

E18 F18

B33 A33

AJ10 AJ11

AN10 AM10

AL3 AT1 AH2

NC

USB_EXTA_N

USB_EXTA_P

USB_EXTB_N

USB_EXTB_P

USB_EXTC_N

USB_EXTC_P

USB_EXTD_N

USB_EXTD_P

USB_CAMERA_N

USB_CAMERA_P

USB_BT_N

USB_BT_P

NC

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_CF_N

USB3_EXTA_R2D_CF_P

USB3_EXTB_D2R_N

USB3_EXTB_D2R_P

USB3_EXTB_R2D_CF_N

USB3_EXTB_R2D_CF_P

75

PCH_USB_RBIAS

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

BI

IN

OUT

IN

OUT

IN

75 41

75 42

Ext A (LS/FS/HS)

Ext B (LS/FS/HS)

Ext C (LS/FS/HS)

D

75 42

75 37

75 31

75 41

16 14

Ext D (LS/FS/HS)

Camera

BT

USB3 Port Assignments:

Ext A (SS)

Ext B (SS)

PLACE_NEAR=U0500.AJ10:6.35mm

1

R1570

22.6

1% 1/20W MF 201

2

C

CRITICAL

OMIT_TABLE

B

74 43

BI

OUT

LPC_AD<0>

LPC_AD<1>

LPC_AD<2>

LPC_AD<3>

LPC_FRAME_L

R1540 R1541 R1542 R1543

R1544

100

21

5% 1/20W 201MF

21

5% 1/20W 201MF

21

1/20W5% 201MF

201MF5% 1/20W

MF5% 1/20W 201

74 45

45 14

45

OUT

BI

74

LPC_AD_R<0>

74

LPC_AD_R<1>

74

LPC_AD_R<2>

LPC_AD_R<3>

74

LPC_FRAME_R_L

74

SPI_CLK_R

SPI_CS0_R_L

NC_SPI_CS1_L

NC_SPI_CS2_L

SPI_MOSI_R

SPI_MISO_R

SPI_IO_R<2>

SPI_IO_R<3>

AU14

AW12

AY12

AW11

AV12

AA3

Y7

Y4

AC2

AA2

AA4

Y6

AF1

(IPU)

LAD1 LAD2 LAD3

LFRAME*

SPI_CLK

(IPU)

SPI_CS0*

(IPU)

SPI_CS1*

(IPU)

SPI_CS2*

(IPU)

SPI_MOSI

(IPU/IPD)

SPI_MISO

(IPU)

SPI_IO2

(IPU)

SPI_IO3

(IPU)

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 7 OF 19

LPC

SMBUS

SML1ALERT*/PCHHOT*/GPIO73

SPI

(IPU/IPD)

C-LINK

SMBALERT*/GPIO11LAD0

SMBCLK

SMBDATA

SML0ALERT*/GPIO60

SML0CLK

SML0DATA

SML1CLK_GPIO75

SML1DATA/GPIO74

(IPU/IPD)

CL_CLK

CL_DATA

CL_RST*

AN2

AP2 AH1

AL2

AN1 AK1

AU4

AU3 AH3

AF2

AD2

AF4

PCH_SMBALERT_L

SMBUS_PCH_CLK

SMBUS_PCH_DATA

WOL_EN

SML_PCH_0_CLK

SML_PCH_0_DATA

PCH_SML1ALERT_L

SML_PCH_1_CLK

SML_PCH_1_DATA

NC_CLINK_CLK

NC_CLINK_DATA

NC_CLINK_RESET_L

14

OUT

BI

OUT

BI

OUT

BI

46

76 46

35 14

76 46

B

A

=PP3V3_SUS_PCH_GPIO

R1579 R1580 R1581 R1582 R1583 R1590

100K

=PP3V3_SUS_PCH_VCC_SPI

R1548 R1549

R1591

100K

1K

21

5% MF1/20W 201

21

5% 1/20W MF 201

21

5% 1/20W MF 201

21

5%

21

1/20W MF

5% 201

1/20W MF 2015%

MF 2011/20W5%

MF1/20W

66

PCH_SML1ALERT_L

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

201MF1/20W

PCH_SMBALERT_L

2015%

66 11 8

SPI_IO_R<2>

SPI_IO_R<3>

WOL_EN

14

16 14

14

45 14

www.qdzbwx.com

35 14

SYNC_MASTER=J117_ANDRES

PAGE TITLE

PCH PCIe/USB/LPC/SPI/SMBus

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=03/24/2014

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

15 OF 123

SHEET

14 OF 81

A

8 7 5 4 2 1

36

345678

2 1

D

C

71 18 16 15 13

GPIO12:

CR: TBT_GO2SX_BIDIR, requires 100k pull-up to SUS

RR/FR: DPHDMIMUX_SEL_TBT, requires 100k pull-up to TBTLC

Required JTAG pullups are on the XDP connector page.

66 57 17 16 8 6

CRITICAL

OMIT_TABLE

IN

PLT_RESET_L

36

OUT

R1603

26

OUT

32

OUT

100K

5%

1/20W

MF

201

1

2

R1606

100K

5%

1/20W

MF

201

1

2

R1604

1/20W

201

1K

5%

MF

U0500

BROADWELL-ULT

2C+GT2

BGA

SYM 10 OF 19

16 15

16 15 15 3

16 15

BI

26

BI

IN OUT

IN

MLB_RAMCFG4

MLB_RAMCFG0

HDMITBTMUX_SEL_TBT

NC_MEM_VDD_SEL_1V5_L

XDP_LPCPLUS_GPIO

XDP_PCH_GPIO17

NO_TEST=1

ENET_SD_RESET_L

76 43 15

75 34 15

63 15

IN

OUT

SMC_WAKE_SCI_L

TPAD_SPI_INT_L

15

ENET_MEDIA_SENSE

SSD_PWR_EN

PCH_TBT_PCIE_RESET_L

63 15

16 15

26 15

18 16

18 16 15

18 15

1

16 15

2

74 45 15

15

OUT

BI

OUT

BI

HDD_PWR_EN

XDP_SDCONN_STATE_CHANGE_L

SD_PWR_EN

15

TBT_PWR_EN

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

JTAG_TBT_TMS_PCH

PCH_HSIO_PWR_EN

15

TPAD_SPI_IF_EN

15

MLB_RAMCFG3

SPIROM_USE_MLB

SSD_RESET_L

32 15

16 15

OUT

BI

SSD_SR_EN_L

MLB_RAMCFG1

MLB_RAMCFG2

PCH_GPIO33

15

P1

AU2

AM7

AD6

Y1

T3

AD5

AN5

AD7

AN3

AG6

AP1

AL4

AT5

AK4

AB6

U4

Y3

P3

Y2

AT3

AH4

AM4

AG5

AG3

AM3

AM2

P2

BMBUSY*/GPIO76

GPIO8

LAN_PHY_PWR_CTRL/GPIO12

GPIO15

(IPD-RSMRST#)

GPIO16

GPIO17

GPIO24

GPIO27

(IPD-DeepSx)

GPIO28

GPIO26

GPIO56

GPIO57

GPIO58

GPIO59

GPIO44

GPIO47

GPIO48

GPIO49

GPIO50

HSIOPC/GPIO71

GPIO13

GPIO14

GPIO25

GPIO45

GPIO46

GPIO9

GPIO10

DEVSLP0/GPIO33

(IPD)

(IPD-PLTRST#)

(IPD)

LPIO

GPIO

CPU/MISC

GSPI0_MISO/GPIO85

GSPI0_MOSI/GPIO86

GSPI1_MISO/GPIO89

UART0_RXD/GPIO91

UART0_TXD/GPIO92

UART0_RTS*/GPIO93

UART0_CTS*/GPIO94

THERMTRIP*

RCIN*/GPIO82

SERIRQ

PCH_OPI_COMP

RSVD RSVD

GSPI0_CS*/GPIO83

GSPI0_CLK/GPIO84

GSPI1_CS*/GPIO87

GSPI1_CLK/GPIO88

GSPI_MOSI/GPIO90

UART1_RXD/GPIO0

UART1_TXD/GPIO1

UART1_RST*/GPIO2

UART1_CTS*/GPIO3

I2C0_SDA/GPIO4

I2C0_SCL/GPIO5

I2C1_SDA/GPIO6

I2C1_SCL/GPIO7

SDIO_CLK/GPIO64

SDIO_CMD/GPIO65

D60

V4

T4

AW15

AF20 AB21

R6

L6

N6

L8

R7

L5

N7

K2

J1

K3

J2

G1

K4

G2

J3

J4

F2

F3

G4

F1

E3

F4

=PP1V05_S0_CPU_VCCST

PM_THRMTRIP_L

TBT_CIO_PLUG_EVENT_L

LPC_SERIRQ

PCH_OPI_COMP

NC

MEM_GOOD_LED

PCH_CAM_RESET_L

PCH_CAM_EXT_BOOT

AUD_SPI_MOSI

PCH_GSPI1_CS_L

SDCONN_OC_L

PCH_GSPI1_MISO

PCH_GSPI1_MOSI

AP_S0IX_WAKE_L

HDMITBTMUX_FLAG_L

PCH_BT_UART_RTS_L

PCH_BT_UART_CTS_L

PCH_UART1_RXD

PCH_UART1_TXD

JTAG_ISP_TDO

PCH_UART1_CTS_L

PCH_GPIO4

AP_RESET_L

PCH_I2C1_SDA

PCH_I2C1_SCL

TBT_POC_RESET_L

BT_PWR_RST_L

R1600

1K

5%

1/20W

MF

201

1

2

OUT

IN

BI

71 44

26 15

43 15

Pull-up/down on chipset support page (depends on TBT controller)

Cactus Ridge: Alias to TBT_CIO_PLUG_EVENT, requires pull-down.

Redwood Ridge: Alias to TBT_CIO_PLUG_EVENT_L, requires pull-up (S0).

D

PLACE_NEAR=U0500.AW15:12.7mm

1

R1601

49.9

1% 1/20W MF 201

2

27

38 15

36 15

PLT_RESET_L

1

R1602

18 15

100K

5% 1/20W MF 201

2

IN

OUT

31

71 18 16 15 13

C

Pull-up on TBT page

OUT

15

IN

15

IN

15

OUT

15

B

A

66 27 16 15 13 12

=PP3V3_S5_PCH_GPIO

=PP3V3_S4_PCH_GPIO

=PP3V3_S0_PCH_GPIO

R1628

R1624 R1634

R1609

R1611 R1618 R1621 R1625 R1630 R1632 R1633 R1635 R1637

R1617

R1629 R1615 R1619 R1620 R1614 R1613

R1616 R1612 R1622

R1623 R1626

R1631 R1636 R1638

100K

10K

100K

1

1 2

1

1 2

1

1 2

1

1 2

1

1 2

2

5%

2

5% 201MF1/20W

21

5%

2

5% MF1/20W 201

21

2

5% 201MF

2

5%

2

5% MF 201

5% 1/20W 201

5% 1/20W MF

5% 2011/20W MF

2

5% 1/20W 201MF

5% 201MF

5%

1/20W5%

1/20W

1/20W 201

1/20W5% MF 201

1/20W 201MF

1/20W5% MF

1/20W MF

1/20W 201MF5%

1/20W

1/20W 201MF5%

1/20W

1/20W 201MF

MF5%

MF1/20W 2015%

MF5%

MF5% 1/20W

MF

MF1/20W5% 201

MF1/20W 201

OUT

C4

SDIO_POWER_EN/GPIO70 SDIO_D0/GPIO66

L2

DEVSLP1/GPIO38

N5

DEVSLP2/GPIO39

V2

SPKR/GPIO81

(IPD-PLTRST#)

SDIO_D1/GPIO67

SDIO_D2/GPIO68

SDIO_D3/GPIO69

RAM Configuration Straps

For chip-down RAM systems

66 27 16 15 13 12

MLB_RAMCFG0

MLB_RAMCFG1

MLB_RAMCFG2

MLB_RAMCFG3

MLB_RAMCFG4

=PP3V3_S0_PCH_GPIO

RAMCFG4:H

R1688

100K

5%

1/20W

MF

201

RAMCFG4:L

R1689

10K

5%

1/20W

MF

201

RAMCFG3:H

1

2

RAMCFG3:L

1

2

R1680

100K

5%

1/20W

MF

201

R1684

10K

5%

1/20W

MF

201

1

2

1

2

RAMCFG2:H

RAMCFG2:L

AP_S0IX_WAKE_SEL

15

PCH_GPIO38

15

PCH_GPIO39

R1605

1K

2

1/20W

66 50 13

66 42 41 18

66 27 16 15 13 12

PCH_GPIO38

201MF

JTAG_TBT_TMS_PCH

201MF

JTAG_ISP_TDO

TBT_CIO_PLUG_EVENT_L

XDP_LPCPLUS_GPIO

HDD_PWR_EN

TBT_PWR_EN

PCH_HSIO_PWR_EN

PCH_GPIO33

201MF1/20W5%

PCH_GPIO39

201

LPC_SERIRQ

BT_PWR_RST_L

2015%

LCD_IRQ_L

SSD_PWR_EN

SSD_SR_EN_L

2011/20W MF

TPAD_SPI_INT_L

201

XDP_SDCONN_STATE_CHANGE_L

SD_PWR_EN

201

SMC_WAKE_SCI_L

SPIROM_USE_MLB

201

PCH_GPIO67

XDP_PCH_GPIO17

XDP_JTAG_ISP_TCK

2015% 1/20W MF

XDP_JTAG_ISP_TDI

TPAD_SPI_IF_EN

AP_S0IX_WAKE_SEL

ENET_MEDIA_SENSE

LCD_PSR_EN

5%

MF

201

1

15

PCH_TCO_TIMER_DISABLE=PP3V3_S0_PCH_GPIO

18 15

TBTLC for CR, S0 for RR

18 15

26 15

16 15

63 15

26 15

43 15

63 15

32 15

16 15

76 43 15

74 45 15

16 15

18 16 15

75 34 15

16 15

D3

E4

C3

E2

R1681

100K

5%

1/20W

MF

201

R1685

10K

5%

1/20W

MF

201

RAMCFG1:H

1

2

RAMCFG1:L

1

2

PCH_STRP_TOPBLK_SWP_L

PCH_GPIO67

LCD_IRQ_L

LCD_PSR_EN

RAMCFG0:H

R1682

100K

5%

1/20W

MF

201

1

2

R1683

100K

1/20W

201

RAMCFG0:L

10K

5%

1/20W

MF

201

1

R1687

10K

1/20W

2

201

R1686

5%

MF

5%

MF

44

IN

15

1

2

1

Requires connection to SMC via 1K series R

AP_S0IX_WAKE_L

15

HDMITBTMUX_FLAG_L

15

PCH_I2C1_SDA

15

PCH_I2C1_SCL

15

PCH_UART1_TXD

15

PCH_GSPI1_CS_L

15

PCH_GSPI1_MOSI

15

PCH_GPIO4

15

36 15

38 15

SDCONN_OC_L

AUD_SPI_MOSI

15

MEM_GOOD_LED

15 3

PCH_CAM_RESET_L

PCH_CAM_EXT_BOOT

PCH_BT_UART_RTS_L

15

PCH_BT_UART_CTS_L

15

PCH_UART1_RXD

15

PCH_UART1_CTS_L

15

PCH_GSPI1_MISO

15

PAGE TITLE

NOSTUFF

R1658 R1659

R1666 R1667

R1661 R1654 R1653 R1664 R1651

R1657 R1650 R1668 R1669

R1670 R1671 R1660 R1663 R1652

66 27 16 15 13 12

100K

47K

100K

47K

1 2

1

=PP3V3_S0_PCH_GPIO

1/20W

1/20W5%

5% MF1/20W 201

1/20W5%

1/20W MF5% 201

5% 1/20W MF 201

5% MF1/20W 201

2

5% MF

1/20W

1/20W 201

MF5% 201

MF 2011/20W5%

MF5%

MF5% 201

MF 201

MF1/20W5% 201

MF5% 1/20W

MF5% 1/20W 201

MF1/20W5%

MF5% 201

2011/20W

201MF

201

201MF1/20W5%

201

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

B

A

PCH GPIO/MISC/LPIO

2

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

16 OF 123

SHEET

15 OF 81

8 7 5 4 2 1

36

345678

2 1

D

C

B

A

Extra BPM Testpoints

73 6

71 17 8

43 13

65 44 13

73 16 6

16 12

IN

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_BPM_L<6>

XDP_BPM_L<7>

IN

OUT

CPU_VCCST_PWRGD

PM_PWRBTN_L

PM_PCH_SYS_PWROK

XDP_CPU_TCK

PCH_JTAGX

1

TP-P6

1

TP-P6

1

TP-P6

1

TP-P6

1

TP-P6

1

TP-P6

TP

TP1802

TP1803

TP1804

TP1805

TP1806

TP1807

PLACE_NEAR=U0500.C61:12.7mm

R1800

R1802

PLACE_NEAR=U5000.J3:12.7mm

R1804

R1835

1K

0

220

0

XDP

21

5% 2011/20W MF

21

5%

1/20W MF

21

5%

21

PLACE_NEAR=J1800.58:28mm

1/20W 0201

5% MF

PCH XDP Signals

These signals do not connect to XDP connector in this architecture, only accessible

via Top-Side Probe. Nets are listed here to show XDP associations and to make clear

what restrictions exist on PCH GPIOs when Top-Side Probe is used for PCH debug.

Non-XDP Signals

USB_EXTA_OC_L

USB_EXTB_OC_L

USB_EXTC_OC_L

USB_EXTD_OC_L

MLB_RAMCFG0

MLB_RAMCFG1

MLB_RAMCFG2

MLB_RAMCFG3

MLB_RAMCFG4

SDCONN_STATE_CHANGE_L

16 14

16 15

OUT

IN

16

OUT

PCH/XDP Signals

XDP_USB_EXTA_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTB_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTC_OC_L

MAKE_BASE=TRUE

XDP_USB_EXTD_OC_L

MAKE_BASE=TRUE

XDP_MLB_RAMCFG0

MAKE_BASE=TRUE

XDP_MLB_RAMCFG1

MAKE_BASE=TRUE

XDP_MLB_RAMCFG2

MAKE_BASE=TRUE

XDP_MLB_RAMCFG3

MAKE_BASE=TRUE

XDP_MLB_RAMCFG4

MAKE_BASE=TRUE

XDP_SDCONN_STATE_CHANGE_L

MAKE_BASE=TRUE

MLB_RAMCFGx GPIOs have TPs.

USB Overcurrents are aliased, do not cause USB OC# events during PCH debug.

SDCONN_STATE_CHANGE_L is aliased, do not plug/unplug SD Cards during PCH debug.

JTAG_ISP (non-TMS) nets are aliased, do not attempt bit-banged JTAG during PCH debug.

NOTE: Should force PCH GPIO47 high to ensure TBT router powered to avoid leakage/clamping of signals.

LPCPLUS_GPIO is aliased, do not attempt use during PCH debug.

0201

MF-LF1/16W 402

PCH_JTAGX_R

IN

BI

IN

=PP1V05_S0_XDP

66 16

XDP_CPU_PREQ_L CPU_CFG<17>

BI

XDP_CPU_PRDY_L

CPU_CFG<0>

CPU_CFG<1>

CPU_CFG<2>

CPU_CFG<3>

XDP_BPM_L<0>

XDP_BPM_L<1>

CPU_CFG<4>

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7> CPU_CFG<15>

71

XDP_CPU_VCCST_PWRGD

16

XDP_CPU_PWRBTN_L

CPU_PWR_DEBUG

73 6

71 6

73 6

8

6

IN

OUT

XDP_SYS_PWROK

46 16

BI

IN

=SMBUS_XDP_SDA

=SMBUS_XDP_SCL

TP_XDP_TCK1

PLACE_NEAR=J1800.48:28mm

1

TP

TP1888

TP-P6

41

42

15

36

65 13

16 15

IN

73 16 12

www.qdzbwx.com

XDP

C1804

0.1UF

10%

6.3V

CERM-X5R

0201

16 14

OUT

46 16

XDP_USB_EXTA_OC_L

XDP_USB_EXTB_OC_L

XDP_USB_EXTC_OC_L

XDP_USB_EXTD_OC_L

XDP_SDCONN_STATE_CHANGE_L

XDP_MLB_RAMCFG1

16

XDP_MLB_RAMCFG2

16

XDP_MLB_RAMCFG3

16

PM_RSMRST_PCH_L

XDP_CPU_PWRBTN_L

16

=SMBUS_XDP_SDA

=SMBUS_XDP_SCL

XDP_PCH_TCK

PPVCCIO_S0_CPU

8

1

2

PLACE_NEAR=U0500.AA63:50mm

XDP

1

2

1

R1831

1K

5% 1/16W MF-LF 402

2

XDP_CPU_PRESENT_L

R1883

1K

1/20W

R1832

150

5% 1/16W MF-LF 402

XDP_CPU_OBSAB

=PP3V3_S5_XDP

66

12

MF5% 201

OMIT

1

XW1800

SHORT

402

2

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_B0

OBSDATA_B1

OBSDATA_B2

OBSDATA_B3

PWRGD/HOOK0

VCC_OBS_AB

1

XW1850

SHORT

402

2

XDP_PM_RSMRST_PCH_L

XDP_PCH_OBSAB

HOOK1

HOOK2

HOOK3

SDA

SCL

TCK1

TCK0

XDP

10%

6.3V

0201

1

2

C1800

0.1UF

CERM-X5R

OMIT

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_A1

OBSDATA_A2

OBSDATA_A3

OBSFN_B0

OBSFN_B1

OBSDATA_B0

OBSDATA_B1

OBSDATA_B2

OBSDATA_B3

VCC_OBS_AB

C1850

CERM-X5R

CPU Micro2-XDP

CRITICAL

XDP_CONN

J1800

DF40RC-60DP-0.4V

M-ST-SM1

62

2 1

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

30 29

32 31

34 33

36 35

38 37

40 39

42 41

44 43

46 45

48 47

50 49

52 51

54 53

56 55

58 57

60 59

64 63

518S0847

61

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0

OBSFN_D1

OBSDATA_D0

OBSDATA_D1

OBSDATA_D2

OBSDATA_D3

ITPCLK/HOOK4

ITPCLK#/HOOK5

VCC_OBS_CD

RESET#/HOOK6

DBR#/HOOK7

TDO

TRSTn

TDI

TMS

XDP_PRESENT#

XDP

1

C1801

0.1UF

10%

6.3V

2

CERM-X5R 0201

PCH Micro2-XDP

CRITICAL

XDP_CONN

J1850

DF40RC-60DP-0.4V

M-ST-SM1

62

2 1

NC

HOOK0 HOOK4

HOOK1

HOOK2

HOOK3

NC

SDA

SCL

TCK1

NC

TCK0

4 3

6 5

8 7

10 9

12 11

14 13

16 15

18 17

20 19

22 21

24 23

26 25

28 27

30 29

32 31

34 33

36 35

38 37

40 39

42 41

44 43

46 45

48 47

50 49

52 51

54 53

56 55

58 57

60 59

XDP

0.1UF

10%

6.3V

0201

1

2

64 63

61

NC

OBSFN_C0

OBSFN_C1

OBSDATA_C0

OBSDATA_C1

OBSDATA_C2

OBSDATA_C3

OBSFN_D0

OBSFN_D1

OBSDATA_D0

OBSDATA_D1

OBSDATA_D2

OBSDATA_D3

HOOK5

VCC_OBS_CD

HOOK6

HOOK7

TDO

TRSTn

TDI

TMS

XDP

1

C1851

0.1UF

10%

6.3V

2

CERM-X5R 0201

NOTE: This is not the standard XDP pinout.

Use with 921-0133 Adapter Flex to

support chipset debug.

OMIT

1

XW1801

SHORT

402

2

IN

CPU_CFG<16>

CPU_CFG<8>

CPU_CFG<9>

CPU_CFG<10>

CPU_CFG<11>

CPU_CFG<19>

CPU_CFG<18>

CPU_CFG<12>

CPU_CFG<13>

CPU_CFG<14>

IN

NC

XDP_CPU_OBSCD

XDP_CPURST_L

XDP_DBRESET_L

OUT

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

XDP_CPU_TDO

XDP_CPU_TRST_L

XDP_CPU_TDI

XDP_CPU_TMS

XDP

1

C1806

0.1UF

10%

6.3V

2

CERM-X5R 0201

PLACE_NEAR=J1800.47:28mm

IN

OUT

66 65 64 63 17

XDP_MLB_RAMCFG0

XDP_JTAG_ISP_TCK

SSD_XDP_PCIE3_SEL_L

SSD_XDP_PCIE2_SEL_L

SSD_XDP_PCIE1_SEL_L

SSD_XDP_PCIE0_SEL_L

XDP_LPCPLUS_GPIO

XDP_PCH_GPIO17

XDP_MLB_RAMCFG4

XDP_JTAG_ISP_TDI

=PP1V05_S0_XDP

=PP3V3_S0_PCH_GPIO

66 27 15 13 12

XDP_PM_PCH_PWROK

XDP_DBRESET_L

XDP_PCH_TDO

XDP_PCH_TRST_L_R

XDP_PCH_TDI

XDP_PCH_TMS

PLACE_NEAR=J1850.47:28mm

XDP

1

C1852

0.1UF

10%

6.3V

2

CERM-X5R 0201

73 6

66 57 17 15 8 6

=PP1V05_S0_CPU_VCCST

D

XDP

73 6

73 16 6

XDP_CPU_TDO

R1810

PLACE_NEAR=J1800.51:28mm

51

21

MF 2015% 1/20W

XDP

73 6

73 16 6

XDP_CPU_TRST_L

XDP_CPU_TCK

TDI and TMS are terminated in CPU.

R1811

PLACE_NEAR=U0500.E59:28mm

R1813

PLACE_NEAR=U0500.E60:28mm MF1/20W 2015%

51

XDP

51

12

MF1/20W 2015%

12

XDP

R1805

17 16

73 16 6

73 6

1K

21

PLT_RESET_L

5% 2011/20W MF

PLACE_NEAR=U0500.AG7:12.7mm

IN

71 18 15 13

C

1.05V S5 LDO

Power to the JTAG debug lines

=PP3V3_S5_PWRCTL

U1830

TPS720105

SON

BIAS

CRITICAL

XDP

1

IN

EN

GND

5

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.1500

PLACE_NEAR=U0500.AE62:28mm

PLACE_NEAR=U0500.AU62:28mm

65 13

16 12

CPU/PCH Merged XDP

Apple Inc.

R

OUT

THRM

PAD

7

R1896

R1897

2

NC

1

R1890

51

1% 1/20W MF 201

2

XDP

51

NC

1

R1891

51

1% 1/20W MF 201

2

XDP

NOSTUFF

PP1V05_S5

1

C1831

2.2UF

10%

6.3V

2

X5R 402

XDP

1

R1892

51

1% 1/20W MF 201

2

XDP

12

5% MF

12

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

77 16

NOSTUFF

1

R1899

1K

1% 1/20W MF 201

2

1/20W 201

1/20W5% 201MF

SYNC_DATE=03/24/2014

051-00081

3.0.0

18 OF 123

16 OF 81

B

A

D

16

12

15

16

IN

OUT

IN

OUT

XDP

1

C1830

0.1UF

10% 16V

2

X7R-CERM 0402

1

R1833

150

5% 1/16W MF-LF 402

2

PM_EN_REG_P1V05_S5

4

6

3

XDP

1

C1832

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V05_S5

77 16

18 15

73 16 12

16 12

15

18 15

66 16

73 16 12

XDP_PCH_TCK

XDP_PCH_TRST_L

16 12

XDP_PCH_TDO

XDP_PCH_TDI

XDP_PCH_TMS

PCH_JTAGX

R1881

1K

17 16

5%

73 16 12

1/20W

R1882

0

5%

73 16 12

1/20W

12

MF

NOSTUFF

MF

201

0201

PM_PCH_PWROK

XDP_PCH_TRST_L

SYNC_MASTER=J117_ANDRES

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8 7 5 4 2 1

36

345678

2 1

D

PPVBATT_G3_RTC

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

2 1

Coin-Cell Holder

R1902

1K

5% 1/16W MF-LF

402

RTC Power Sources

=PP3V3_G3H_RTC_D

66

PPVBATT_G3_RTC_R

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

VOLTAGE=3.3V

D1900

BAT54DW-X-G

SOT-363

PP3V3_G3_RTC_SW

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

OMIT

NC NC

TP1900

1.97X2.02MM-NSP

SMT-PAD

1

OMIT

1

4

5

NC NC

6

3

2

TP1901

1.97X2.02MM-NSP

SMT-PAD

1

Place TP1901 on bottom side

SMC_ASSERT_RTCRST

44

RTCRST:Y

R1930

10K

1 2

5% 1/16W MF-LF

402

SMC_ASSERT_RTCRST_R

OMIT_TABLE

20%

10V

CERM

402

1

2

C1931

0.1UF

CRITICAL

Q1930

NTR4101P

SOT-23-HF

2

S D

G

1

3

C1930

0.1UF

20%

10V

CERM

402

ALL_SYS_PWRGD/CPU_VCCST_PWRGD Level-Shifter

=PP3V3_S5_PWRCTL

16 63 64 65 66

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

1

66

6

VCC

U1972

74AUP1G07GF

SOT891

4

YA

5

NCNC

10% 16V

0201

1

2

NC NC

1

C1972

0.1UF

X5R-CERM

3 43 65

IN

ALL_SYS_PWRGD

GND

2

3

=PP1V05_S0_CPU_VCCST

1

R1972

10K

5% 1/20W MF 201

2

CPU_VCCST_PWRGD

6 8 15 16 57 66

8 16 71

OUT

D

C

1

J1900

BAT-HLDR-RCPT-J94-J95

SM

2

APN:998-6925

12 74

IN

12 74

OUT

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX1

PART# DESCRIPTIONQTY

CAP,0.1 UF,402 C1931132S1059 1 RTCRST:Y

PCH RTC Crystal

R1910

0

R1911

10M

5%

1/20W

MF1 201

1 2

5%

1

2

1/20W

MF

0201

PCH_CLK32K_RTCX2_R

74

32.768K-20PPM-12.5PF

CRITICAL

Y1910

2012-1

C1931RES,10K OHM,4021116S0090 RTCRST:N

PLACE_NEAR=Y1910.2:2MM

C1910

20PF

1 2

5%

25V

2

1

PLACE_NEAR=Y1910.1:2MM

C0G

0201

C1911

20PF

1 2

5% 25V C0G

0201

TABLE_5_HEAD

BOM OPTIONREFERENCE DESIGNATOR(S)

TABLE_5_ITEM

=PP5V_S0_PCH_STRAP

TABLE_5_ITEM

PCH ME Disable Strap

=PP1V5_S0_PCH_VCCSUSHDA

8 11 66

43

IN

SPI_DESCRIPTOR_OVERRIDE_L

Q1920

DMN5L06VK-7

SOT563

D

3

DMN5L06VK-7

Q1920

SOT563

VER 3

2

5

GS

4

G S

SPI_DESCRIPTOR_OVERRIDE_LS5V

SPI_DESCRIPTOR_OVERRIDE

6

D

1

66

1

R1920

100K

5% 1/20W MF 201

2

1

R1921

1K

5% 1/20W MF 201

2

HDA_SDOUT_R

IPD = 9-50k

OUT

C

12 74

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

If high, ME is disabled. This allows for full re-flashing of SPI ROM. SMC controls strap enable to allow in-field control of strap setting. Q1920 & 5V pull-up allows circuit to work regardless of HDA voltage.

B

PCH 24MHz Crystal

C1915

2.2PF

1 2

+/-0.05PF

25V

C0G-CERM

0201

NC

PCH_CLK24M_XTALOUT_R

74

CRITICAL

13

NC

24

NC

Y1915

3.20X2.50MM-SM1

24.000MHZ-20PPM-6PF

C1916

2.2PF

1

2

+/-0.05PF

25V

C0G-CERM

0201

TBT 25MHz Crystal

R1915

0

1 2

5%

1/20W

MF

0201

PCH_CLK24M_XTALOUT

1

R1916

1M

5% 1/20W MF 201

2

PCH_CLK24M_XTALIN

IN

OUT

12 74

Ethernet 25MHz Crystal

16

PCH Reset Button

=PP3V3_S0_PCH

66

1

R1995

4.7K

5%

2

1/16W MF-LF 402

OMIT

1

R1997

0

5% 1/16W MF-LF 402

2

XDP

R1996

0

XDP_DBRESET_L PM_SYSRST_L

1 2

5% 1/16W MF-LF

402

13 43

OUTIN

B

A

C1917

10PF

21

5%

25V

C0G-NPO

0201

C1918

10PF

21

5%

25V

C0G-NPO

0201

TBT_CLK25M_OUT_R

74

1 3

NC

2 4

CRITICAL

25.000MHZ-20PPM-12PF-85C

NOTE: 30 PPM crystal required

Y1916

3.2X2.5MM-SM

R1917

0

1 2

5%

1/20W

MF

0201

TBT_CLK25M_OUT

NOSTUFF

1

R1918

1M

5% 1/20W MF 201

2

TBT_CLK25M_IN

26 74

C1919

18PF

1 2

5% 50V C0G

NC

0402

NC

C1920

18PF

2

1

5% 50V C0G

0402

www.qdzbwx.com

ENET_XTAL_OUT_R

74

1 3

2 4

CRITICAL

Y1917

25.000MHZ-20PPM-12PF-85C

3.2X2.5MM-SM

NOTE: 30 PPM crystal required

R1919

0

1 2

5% 1/16W MF-LF

402

ENET_XTAL_OUT

NOSTUFF

1

R1922

1M

5% 1/16W MF-LF 402

2

ENET_XTAL_IN

34 74

Clock series termination

R1955

IN OUT

LPC_CLK24M_SMC_R LPC_CLK24M_SMC

PLACE_NEAR=U0500.AN15:10MM

22

1 2

5%

1/20W

MF

201

PAGE TITLE

Chipset Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=02/25/2014SYNC_MASTER=J70_NICK

DRAWING NUMBER SIZE

051-00081

REVISION

3.0.0

BRANCH

PAGE

19 OF 123

SHEET

17 OF 81

43 74 12 74

A

D

8 7 5 4 2 1

36

Platform Reset Connections

345678

2 1

D

From RR

From PCH

79 27 26

26

IN

15

IN

Falcon Ridge JTAG Isolation

TBTLC can be on when S0 is off, and vice-versa

PP3V3_TBTLC

R2021

JTAG_TBT_TDO

JTAG_TBT_TMS_PCH

S0 pull-up on PCH page

Isolation ensures no leakage to RR or PCH

1

R2022

100K

5% 1/20W MF 201

2

S0 pull-up on PCH page

JTAG_ISP_TDO

JTAG_TBT_TMS

100K

5%

1/20W

MF

201

1

2

1

C2020

0.1UF

20%

10V

2

CERM 402

1

3

52

VCC

U2020

74LVC2G07

SOT891

6

1Y1A

4

2Y2A

GND

OUT

15

26

To PCH

To RR

R2055

33

5%

1/20W

MF

201

21

71 16 15 13 76 43

PLT_RESET_L

IN OUT

MAKE_BASE=TRUE

Unbuffered

SMC_LRESET_L

MAKE_BASE=TRUE

R2096

100

1 2

5%

1/20W

MF

201

DP_HPD_RESET_L

18

D

C

NOTE: Solution shown is for WPT-LP. Other PCH's may require isolation on TCK

and TDI as well for PCH glitch-prevention.

NOTE: This reference schematic assumes PCH JTAG GPIOs are only used for

Thunderbolt. If other ASIC JTAG signals are wired into these GPIOs

different isolation techniques will likely be necessary.

Multi-router designs also require different circuitry.

16 15

IN

XDP_JTAG_ISP_TCK

XDP_JTAG_ISP_TDI

JTAG_TBT_TCK_S

MAKE_BASE=TRUE

JTAG_TBT_TDI_S

MAKE_BASE=TRUE

Falcon Ridge HPD Isolation

SHORT

OMIT

XW2000

XW2001

OMIT

21

402

21

402

JTAG_TBT_TCK

JTAG_TBT_TDI

OUT

26

=PP3V3_S4_PCH_GPIO

CRITICAL

Q2010

1

SSM3K15AMFVAP

G

35 31 13 26

PCIE_WAKE_L TBT_WAKE_L

3

D

SOD

S

2

1

R2010

10K

5% 1/16W MF-LF 402

2

66 42 41 15

C

B

NOTE: PLT_RESET_L used as the other input to the AND gate so that HPD

is only driven high to the PCH in S0.

66 64 29 28 27 26 18

26

IN

DP_TBTSNK0_HPD

DP_HPD_RESET_L

18

=PP3V3_S4_TBT

2

1

A

U2030

B

TC7SZ08FEAPE

5

SOT665

CRITICAL

4

Y

3

1

C2030

0.1UF

20%

10V

2

CERM 402

DP_TBTSNK0_HPD_BUF

1

R2030

100K

5% 1/20W MF 201

2

OUT

13

=PP1V2_S3_MEM_VTTPWRCTL

66

CPU_MEMVTT_PWR_EN_LSVDDQ

6

Memory VTT Enable Level-Shifter

CPU output is on VDDQ rail (1.2V), TPS51916 has 1.8V Vih(min).

=PP3V3_S0_MEM_VTTPWRCTL

1

R2040

100K

5% 1/20W MF 201

2

TPS51916 I(leak) = +/- 1uA,

Vih(min) = 1.8V

PM_EN_LDO_S3_DDRVTT

C2040

0.1UF

10% 16V

X5R-CERM

0201

1

6

VCC

2

U2040

74AUP1G07GF

SOT891

4

YA

66

B

59

A

66 64 29 28 27 26 18

26

IN

DP_TBTSNK1_HPD

DP_HPD_RESET_L

18

=PP3V3_S4_TBT

2

1

A

U2031

B

TC7SZ08FEAPE

5

SOT665

CRITICAL

4

Y

3

1

C2031

0.1UF

20%

10V

2

CERM 402

DP_TBTSNK1_HPD_BUF

1

R2031

100K

5% 1/20W MF 201

2

OUT

13

1

5

NCNC

GND

3

SYNC_MASTER=J70_NICK SYNC_DATE=11/20/2013

PAGE TITLE

A

Project Chipset Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

20 OF 123

18 OF 81

D

Memory Bit/Byte Swizzle

345678

2 1

D

C

B

=MEM_A_DQ<0>

21

=MEM_A_DQ<1>

21

=MEM_A_DQ<2>

21

=MEM_A_DQ<3>

21

=MEM_A_DQ<6>

21

=MEM_A_DQ<5>

21

=MEM_A_DQ<7>

21

=MEM_A_DQ<4>

21

=MEM_A_DQ<17>

21

=MEM_A_DQ<18>

21

=MEM_A_DQ<19>

21

=MEM_A_DQ<23>

21

=MEM_A_DQ<21>

21

=MEM_A_DQ<16>

21

=MEM_A_DQ<22>

21

=MEM_A_DQ<20>

21

=MEM_A_DQ<8>

21

=MEM_A_DQ<12>

21

=MEM_A_DQ<11>

21

=MEM_A_DQ<14>

21

=MEM_A_DQ<9>

21

=MEM_A_DQ<13>

21

=MEM_A_DQ<15>

21

=MEM_A_DQ<10>

21

=MEM_A_DQ<28>

21

=MEM_A_DQ<25>

21

=MEM_A_DQ<24>

21

=MEM_A_DQ<27>

21

=MEM_A_DQ<26>

21

=MEM_A_DQ<31>

21

=MEM_A_DQ<30>

21

=MEM_A_DQ<29>

21

=MEM_A_DQ<32>

22

=MEM_A_DQ<33>

22

=MEM_A_DQ<39>

22

=MEM_A_DQ<38>

22

=MEM_A_DQ<37>

22

=MEM_A_DQ<36>

22

=MEM_A_DQ<35>

22

=MEM_A_DQ<34>

22

=MEM_A_DQ<55>

22

=MEM_A_DQ<51>

22

=MEM_A_DQ<53>

22

=MEM_A_DQ<49>

22

=MEM_A_DQ<50>

22

=MEM_A_DQ<54>

22

=MEM_A_DQ<48>

22

=MEM_A_DQ<52>

22

=MEM_A_DQ<47>

22

=MEM_A_DQ<46>

22

=MEM_A_DQ<40>

22

=MEM_A_DQ<42>

22

=MEM_A_DQ<43>

22

=MEM_A_DQ<41>

22

=MEM_A_DQ<45>

22

=MEM_A_DQ<44>

22

=MEM_A_DQ<60>

22

=MEM_A_DQ<61>

22

=MEM_A_DQ<58>

22

=MEM_A_DQ<59>

22

=MEM_A_DQ<56>

22

=MEM_A_DQ<57>

22

=MEM_A_DQ<62>

22

=MEM_A_DQ<63>

22

MAKE_BASE

TRUE

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MAKE_BASE

70 7

70 7 70 7

=MEM_B_DQ<7>

23

=MEM_B_DQ<3>

23

=MEM_B_DQ<1>

23

=MEM_B_DQ<5>

23

=MEM_B_DQ<6>

23

=MEM_B_DQ<2>

23

=MEM_B_DQ<0>

23

=MEM_B_DQ<4>

23

=MEM_B_DQ<8>

23

=MEM_B_DQ<9>

23

=MEM_B_DQ<14>

23

=MEM_B_DQ<15>

23

=MEM_B_DQ<10>

23

=MEM_B_DQ<13>

23

=MEM_B_DQ<12>

23

=MEM_B_DQ<11>

23

=MEM_B_DQ<22>

23

=MEM_B_DQ<18>

23

=MEM_B_DQ<16>

23

=MEM_B_DQ<20>

23

=MEM_B_DQ<23>

23

=MEM_B_DQ<19>

23

=MEM_B_DQ<17>

23

=MEM_B_DQ<21>

23

=MEM_B_DQ<29>

23

=MEM_B_DQ<25>

23

=MEM_B_DQ<24>

23

=MEM_B_DQ<28>

23

=MEM_B_DQ<30>

23

=MEM_B_DQ<26>

23

=MEM_B_DQ<31>

23

=MEM_B_DQ<27>

23

=MEM_B_DQ<34>

24

=MEM_B_DQ<37>

24

=MEM_B_DQ<39>

24

=MEM_B_DQ<35>

24

=MEM_B_DQ<33>

24

=MEM_B_DQ<32>

24

=MEM_B_DQ<38>

24

=MEM_B_DQ<36>

24

=MEM_B_DQ<42>

24

=MEM_B_DQ<43>

24

=MEM_B_DQ<40>

24

=MEM_B_DQ<41>

24

=MEM_B_DQ<45>

24

=MEM_B_DQ<47>

24

=MEM_B_DQ<44>

24

=MEM_B_DQ<46>

24

=MEM_B_DQ<51>

24

=MEM_B_DQ<48>

24

=MEM_B_DQ<54>

24

=MEM_B_DQ<50>

24

=MEM_B_DQ<49>

24

=MEM_B_DQ<55>

24

=MEM_B_DQ<52>

24

=MEM_B_DQ<53>

24

=MEM_B_DQ<56>

24

=MEM_B_DQ<58>

24

=MEM_B_DQ<62>

24

=MEM_B_DQ<60>

24

=MEM_B_DQ<63>

24

=MEM_B_DQ<61>

24

=MEM_B_DQ<59>

24

=MEM_B_DQ<57>

24

TRUE

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

70 7

D

C

B

A

=MEM_A_DQS_P<0>

21

=MEM_A_DQS_N<0>

21

=MEM_A_DQS_P<2>

21

=MEM_A_DQS_N<2>

21

=MEM_A_DQS_P<1>

21

=MEM_A_DQS_N<1>

21

=MEM_A_DQS_P<3>

21

=MEM_A_DQS_N<3>

21

=MEM_A_DQS_P<4>

22

=MEM_A_DQS_N<4>

22

=MEM_A_DQS_P<6>

22

=MEM_A_DQS_N<6>

22

=MEM_A_DQS_P<5>

22

=MEM_A_DQS_N<5>

22

=MEM_A_DQS_P<7>

22

=MEM_A_DQS_N<7>

22

TRUE

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

70 7

=MEM_B_DQS_P<0>

23

=MEM_B_DQS_N<0>

23

=MEM_B_DQS_P<1>

23

=MEM_B_DQS_N<1>

23

=MEM_B_DQS_P<2>

23

=MEM_B_DQS_N<2>

23

=MEM_B_DQS_P<3>

23

=MEM_B_DQS_N<3>

23

=MEM_B_DQS_P<4>

24

=MEM_B_DQS_N<4>

24

=MEM_B_DQS_P<5>

24

=MEM_B_DQS_N<5>

24

=MEM_B_DQS_P<6>

24

=MEM_B_DQS_N<6>

24

=MEM_B_DQS_P<7>

24

=MEM_B_DQS_N<7>

24

TRUE

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

70 7

SYNC_MASTER=MASTER SYNC_DATE=MASTER

PAGE TITLE

A

DDR3 Signal Aliases

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

21 OF 123

19 OF 81

D

345678

2 1

D

C

B

D

VRef Dividers

R2223

10

1%

1/20W

MF

201

10

1%

1/20W

MF

201

1%

201

21

PLACE_NEAR=R2221.2:1mm

8.2K

1%

1/20W

MF

201

1

2

R2222

R2220

24.9

1/20W

21

PLACE_NEAR=R2241.2:1mm

1%

MF

201

R2242

21

8.2K

1%

1/20W

MF

201

1

2

R2240

24.9

1/20W

21

PLACE_NEAR=R2261.2:1mm

1%

MF

201

R2262

21

8.2K

1%

1/20W

MF

201

1

2

R2260

24.9

1/20W

1%

MF

201

21

7

IN

CPU_DDR_A_VREFDQ

1

C2220

0.022UF

10%

6.3V

2

X5R-CERM 0201

DDR_VREFDQ_A_RC

R2243

7

IN

CPU_DDR_B_VREFDQ

1

C2240

0.022UF

10%

6.3V

2

X5R-CERM 0201

DDR_VREFDQ_B_RC

R2263

7

IN

CPU_DDR_VREFCA

5.11

1/20W MF-LF

1

C2260

0.022UF

10%

6.3V

2

X5R-CERM 0201

DDR_VREFCA_A_RC

=PP1V2_S3_DDR_MEMVREF

1

R2221

8.2K

1% 1/20W MF 201

2

PP0V6_S3_DDR_VREFDQ_A

VOLTAGE=0.6V

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000

1

R2241

8.2K

1% 1/20W MF 201

2

PP0V6_S3_DDR_VREFDQ_B

VOLTAGE=0.6V

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000

1

R2261

8.2K

1% 1/20W MF 201

2

PP0V6_S3_DDR_VREFCA

VOLTAGE=0.6V

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.2000

66

22 21

C

24 23

24 23 22 21

B

A

SYNC_MASTER=J117_ANDRES SYNC_DATE=02/27/2014

PAGE TITLE

DDR3 VREF MARGINING

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

22 OF 123

20 OF 81

A

D

LPDDR3 CHANNEL A (0-31)

345678

2 1

D

C

B

R2300

243

1%

1/20W

MF

201

U2300

LPDDR3-1600-32GB

EDFB232A1MA

70 25 7

70 25 22 7

IN

MEM_A_CAA<0>

MEM_A_CAA<1>

MEM_A_CAA<2>

MEM_A_CAA<3>

MEM_A_CAA<4>

MEM_A_CAA<5>

MEM_A_CAA<6>

MEM_A_CAA<7>

MEM_A_CAA<8>

MEM_A_CAA<9>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<0>

MEM_A_ZQ<1>

1

2

R2301

243

1%

1/20W

MF

201

1

2

C2340

0.047UF

10%

6.3V X5R 201

1

2

24 23 22 20

22 20

1

C2341

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_DDR_VREFCA

PP0V6_S3_DDR_VREFDQ_A

NC

R2

P2 N2 N3

M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8

D8

J8

B3

B4

H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1

U2

U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

FBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC

=MEM_A_DQ<0>

=MEM_A_DQ<1>

=MEM_A_DQ<2>

=MEM_A_DQ<3>

=MEM_A_DQ<4>

=MEM_A_DQ<5>

=MEM_A_DQ<6>

=MEM_A_DQ<7>

=MEM_A_DQ<8>

=MEM_A_DQ<9>

=MEM_A_DQ<10>

=MEM_A_DQ<11>

=MEM_A_DQ<12>

=MEM_A_DQ<13>

=MEM_A_DQ<14>

=MEM_A_DQ<15>

=MEM_A_DQ<16>

=MEM_A_DQ<17>

=MEM_A_DQ<18>

=MEM_A_DQ<19>

=MEM_A_DQ<20>

=MEM_A_DQ<21>

=MEM_A_DQ<22>

=MEM_A_DQ<23>

=MEM_A_DQ<24>

=MEM_A_DQ<25>

=MEM_A_DQ<26>

=MEM_A_DQ<27>

=MEM_A_DQ<28>

=MEM_A_DQ<29>

=MEM_A_DQ<30>

=MEM_A_DQ<31>

=MEM_A_DQS_N<0>

=MEM_A_DQS_N<1>

=MEM_A_DQS_N<2>

=MEM_A_DQS_N<3>

=MEM_A_DQS_P<0>

=MEM_A_DQS_P<1>

=MEM_A_DQS_P<2>

=MEM_A_DQS_P<3>

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

66 24 23 22 21

=PP1V8_S3_DDR

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2

H3

L2

M2

A11 C12

E8

E12 G12

H8 H9

H11

J9

J10

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2300

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

K8

K11

L12

66 24 23 22 21

=PP1V2_S3_DDR_VDDQ

1

C2300

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2301

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2302

1UF

10% 10V

2

X5R 402-1

1

C2303

1UF

10% 10V

2

X5R 402-1

1

C2304

10UF

20%

6.3V

2

CERM 0402

1

C2305

1UF

10% 10V

2

X5R 402-1

1

C2306

1UF

10% 10V

2

X5R 402-1

1

C2307

10UF

20%

6.3V

2

CERM 0402

N8

N12 R12 U11

A

66 24 23 22 21

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V8_S3_DDR

1

C2320

1UF

10% 10V

2

X5R 402-1

1

C2310

1UF

10% 10V

2

X5R 402-1

1

C2330

1UF

10% 10V

www.qdzbwx.com

2

X5R 402-1

1

C2321

1UF

10% 10V

2

X5R 402-1

1

C2311

1UF

10% 10V

2

X5R 402-1

1

C2331

1UF

10% 10V

2

X5R 402-1

1

C2322

1UF

10% 10V

2

X5R 402-1

1

C2313

1UF

10% 10V

2

X5R 402-1

1

C2334

1UF

10% 10V

2

X5R 402-1

1

C2325

1UF

10% 10V

2

X5R 402-1

1

C2314

1UF

10% 10V

2

X5R 402-1

1

C2335

1UF

10% 10V

2

X5R 402-1

1

C2326

1UF

10% 10V

2

X5R 402-1

1

C2315

1UF

10% 10V

2

X5R 402-1

1

C2332

10UF

20%

6.3V

2

CERM 0402

1

C2327

1UF

10% 10V

2

X5R 402-1

1

C2312

1UF

10% 10V

2

X5R 402-1

1

C2333

10UF

20%

6.3V

2

CERM 0402

1

C2323

1UF

10% 10V

2

X5R 402-1

1

C2336

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C2324

10UF

20%

6.3V

2

CERM 0402

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

Distribute evenly.

SYNC_MASTER=J41_MLB SYNC_DATE=09/03/2013

PAGE TITLE

LPDDR3 DRAM Channel A (0-31)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

23 OF 123

SHEET

21 OF 81

D

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL A (32-63)

345678

2 1

D

C

B

R2400

243

1%

1/20W

MF

201

U2400

LPDDR3-1600-32GB

EDFB232A1MA

70 25 7

70 25 21 7

IN

MEM_A_CAB<0>

MEM_A_CAB<1>

MEM_A_CAB<2>

MEM_A_CAB<3>

MEM_A_CAB<4>

MEM_A_CAB<5>

MEM_A_CAB<6>

MEM_A_CAB<7>

MEM_A_CAB<8>

MEM_A_CAB<9>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

MEM_A_ZQ<2>

MEM_A_ZQ<3>

243

1%

1/20W

MF

201

1

2

C2440

0.047UF

10%

6.3V X5R 201

1

2

24 23 21 20

21 20

1

C2441

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_DDR_VREFCA

PP0V6_S3_DDR_VREFDQ_A

NC

1

2

R2401

NC

R2

P2 N2 N3 M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8

D8

J8

B3

B4

H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1

U2

U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

FBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC

=MEM_A_DQ<32>

=MEM_A_DQ<33>

=MEM_A_DQ<34>

=MEM_A_DQ<35>

=MEM_A_DQ<36>

=MEM_A_DQ<37>

=MEM_A_DQ<38>

=MEM_A_DQ<39>

=MEM_A_DQ<40>

=MEM_A_DQ<41>

=MEM_A_DQ<42>

=MEM_A_DQ<43>

=MEM_A_DQ<44>

=MEM_A_DQ<45>

=MEM_A_DQ<46>

=MEM_A_DQ<47>

=MEM_A_DQ<48>

=MEM_A_DQ<49>

=MEM_A_DQ<50>

=MEM_A_DQ<51>

=MEM_A_DQ<52>

=MEM_A_DQ<53>

=MEM_A_DQ<54>

=MEM_A_DQ<55>

=MEM_A_DQ<56>

=MEM_A_DQ<57>

=MEM_A_DQ<58>

=MEM_A_DQ<59>

=MEM_A_DQ<60>

=MEM_A_DQ<61>

=MEM_A_DQ<62>

=MEM_A_DQ<63>

=MEM_A_DQS_N<4>

=MEM_A_DQS_N<5>

=MEM_A_DQS_N<6>

=MEM_A_DQS_N<7>

=MEM_A_DQS_P<4>

=MEM_A_DQS_P<5>

=MEM_A_DQS_P<6>

=MEM_A_DQS_P<7>

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

66 24 23 22 21

=PP1V8_S3_DDR

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8 A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6 U8 U9

F2 G2 H3

L2

M2

A11 C12

E8

E12

G12

H8 H9

H11

J9

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

J10

U2400

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

K8

K11

66 24 23 22 21

=PP1V2_S3_DDR_VDDQ

1

C2400

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2401

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2402

1UF

10% 10V

2

X5R 402-1

1

C2403

1UF

10% 10V

2

X5R 402-1

1

C2404

1UF

10% 10V

2

X5R 402-1

1

C2405

1UF

10% 10V

2

X5R 402-1

1

C2406

10UF

20%

6.3V

2

CERM 0402

L12

N8

N12 R12 U11

A

66 24 23 22 21

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V8_S3_DDR

1

C2420

1UF

10% 10V

2

X5R 402-1

1

C2410

1UF

10% 10V

2

X5R 402-1

1

C2430

1UF

10% 10V

www.qdzbwx.com

2

X5R 402-1

1

C2421

10UF

20%

6.3V

2

CERM 0402

1

C2411

1UF

10% 10V

2

X5R 402-1

1

C2431

1UF

10% 10V

2

X5R 402-1

1

C2422

10UF

20%

6.3V

2

CERM 0402

1

C2413

1UF

10% 10V

2

X5R 402-1

1

C2433

1UF

10% 10V

2

X5R 402-1

1

C2424

1UF

10% 10V

2

X5R 402-1

1

C2414

1UF

10% 10V

2

X5R 402-1

1

C2434

1UF

10% 10V

2

X5R 402-1

1

C2425

1UF

10% 10V

2

X5R 402-1

1

C2415

1UF

10% 10V

2

X5R 402-1

1

C2432

10UF

20%

6.3V

2

CERM 0402

1

C2426

1UF

10% 10V

2

X5R 402-1

1

C2412

10UF

20%

6.3V

2

CERM 0402

1

C2435

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C2423

1UF

10% 10V

2

X5R 402-1

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

Distribute evenly.

PAGE TITLE

LPDDR3 DRAM Channel A (32-63)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=09/03/2013SYNC_MASTER=J41_MLB

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

24 OF 123

SHEET

22 OF 81

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (0-31)

345678

2 1

D

C

B

R2500

243

1%

1/20W

MF

201

U2500

LPDDR3-1600-32GB

EDFB232A1MA

70 25 7 19

70 25 7

70 25 24 7

IN BI

IN

MEM_B_CAA<0>

MEM_B_CAA<1>

MEM_B_CAA<2>

MEM_B_CAA<3>

MEM_B_CAA<4>

MEM_B_CAA<5>

MEM_B_CAA<6>

MEM_B_CAA<7>

MEM_B_CAA<8>

MEM_B_CAA<9>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<0>

MEM_B_ZQ<1>

1

2

R2501

243

1%

1/20W

MF

201

1

2

C2540

0.047UF

10%

6.3V X5R 201

1

2

24 22 21 20

1

C2541

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_DDR_VREFCA

PP0V6_S3_DDR_VREFDQ_B

24 20

NC

R2

P2 N2 N3

M3

F3

E3

E2 D2 C2

K3

K4

J3 J2

L3 L4

L8

G8

P8 D8

J8

B3

B4

H4

J11

A1

A2

A12 A13

B1

B13

T1

T13

U1 U2

U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

FBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC

=MEM_B_DQ<0>

=MEM_B_DQ<1>

=MEM_B_DQ<2>

=MEM_B_DQ<3>

=MEM_B_DQ<4>

=MEM_B_DQ<5>

=MEM_B_DQ<6>

=MEM_B_DQ<7>

=MEM_B_DQ<8>

=MEM_B_DQ<9>

=MEM_B_DQ<10>

=MEM_B_DQ<11>

=MEM_B_DQ<12>

=MEM_B_DQ<13>

=MEM_B_DQ<14>

=MEM_B_DQ<15>

=MEM_B_DQ<16>

=MEM_B_DQ<17>

=MEM_B_DQ<18>

=MEM_B_DQ<19>

=MEM_B_DQ<20>

=MEM_B_DQ<21>

=MEM_B_DQ<22>

=MEM_B_DQ<23>

=MEM_B_DQ<24>

=MEM_B_DQ<25>

=MEM_B_DQ<26>

=MEM_B_DQ<27>

=MEM_B_DQ<28>

=MEM_B_DQ<29>

=MEM_B_DQ<30>

=MEM_B_DQ<31>

=MEM_B_DQS_N<0>

=MEM_B_DQS_N<1>

=MEM_B_DQS_N<2>

=MEM_B_DQS_N<3>

=MEM_B_DQS_P<0>

=MEM_B_DQS_P<1>

=MEM_B_DQS_P<2>

=MEM_B_DQS_P<3>

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

66 24 23 22 21

=PP1V8_S3_DDR

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2 H3

L2

M2

A11 C12

E8

E12 G12

H8 H9

H11

J9

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

J10

U2500

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

K8

66 24 23 22 21

=PP1V2_S3_DDR_VDDQ

K11

L12

1

C2500

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2501

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2502

1UF

10% 10V

2

X5R 402-1

1

C2503

1UF

10% 10V

2

X5R 402-1

1

C2504

1UF

10% 10V

2

X5R 402-1

1

C2505

10UF

20%

6.3V

2

CERM 0402

1

C2506

10UF

20%

6.3V

2

CERM 0402

N8 N12 R12 U11

A

66 24 23 22 21

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V8_S3_DDR

1

C2520

1UF

10% 10V

2

X5R 402-1

1

C2510

1UF

10% 10V

2

X5R 402-1

1

C2530

1UF

10% 10V

2

X5R 402-1

1

C2521

1UF

10% 10V

2

X5R 402-1

1

C2511

10UF

20%

6.3V

2

CERM 0402

1

C2531

1UF

10% 10V

2

X5R 402-1

1

C2522

1UF

10% 10V

2

X5R 402-1

1

C2512

1UF

10% 10V

2

X5R 402-1

1

C2533

1UF

10% 10V

2

X5R 402-1

1

C2524

1UF

10% 10V

2

X5R 402-1

1

C2534

1UF

10% 10V

2

X5R 402-1

1

C2525

1UF

10% 10V

2

X5R 402-1

1

C2526

1UF

10% 10V

2

X5R 402-1

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

Distribute evenly.

1

C2532

10UF

20%

6.3V

2

CERM 0402

1

C2535

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C2523

10UF

20%

6.3V

2

CERM 0402

PAGE TITLE

LPDDR3 DRAM Channel B (0-31)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=09/03/2013SYNC_MASTER=J41_MLB

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

25 OF 123

SHEET

23 OF 81

A

8 7 5 4 2 1

36

D

LPDDR3 CHANNEL B (32-63)

345678

2 1

D

C

B

R2600

243

1%

1/20W

MF

201

U2600

LPDDR3-1600-32GB

EDFB232A1MA

70 25 7

70 25 23 7

IN

MEM_B_CAB<0>

MEM_B_CAB<1>

MEM_B_CAB<2>

MEM_B_CAB<3>

MEM_B_CAB<4>

MEM_B_CAB<5>

MEM_B_CAB<6>

MEM_B_CAB<7>

MEM_B_CAB<8>

MEM_B_CAB<9>

MEM_B_CKE<2>

MEM_B_CKE<3>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

MEM_B_ZQ<2>

MEM_B_ZQ<3>

1

2

R2601

243

1%

1/20W

MF

201

1

2

C2640

0.047UF

10%

6.3V X5R 201

1

2

23 22 21 20

1

C2641

0.047UF

10%

6.3V

2

X5R 201

PP0V6_S3_DDR_VREFCA

PP0V6_S3_DDR_VREFDQ_B

23 20

NC

R2 P2 N2 N3

M3

F3 E3 E2 D2 C2

K3 K4

J3 J2

L3 L4

L8

G8

P8 D8

J8

B3 B4

H4

J11

A1 A2

A12 A13

B1

B13

T1

T13

U1 U2

U12 U13

CA0 CA1 CA2 CA3 CA4 CA5 CA6 CA7 CA8 CA9

CKE0 CKE1

CK_T CK_C

CS0* CS1*

DM0 DM1 DM2 DM3

ODT

ZQ0 ZQ1

VREFCA VREFDQ

NU

FBGA

SYM 1 OF 2

OMIT_TABLE

CRITICAL

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31

DQS0_C DQS1_C DQS2_C DQS3_C

DQS0_T DQS1_T DQS2_T DQS3_T

NC

P9 N9 N10 N11 M8 M9 M10 M11 F11 F10 F9 F8 E11 E10 E9 D9 T8 T9 T10 T11 R8 R9 R10 R11 C11 C10 C9 C8 B11 B10 B9 B8

L11 G11 P11 D11

L10 G10 P10 D10

C4 K9 R3

NC

=MEM_B_DQ<32>

=MEM_B_DQ<33>

=MEM_B_DQ<34>

=MEM_B_DQ<35>

=MEM_B_DQ<36>

=MEM_B_DQ<37>

=MEM_B_DQ<38>

=MEM_B_DQ<39>

=MEM_B_DQ<40>

=MEM_B_DQ<41>

=MEM_B_DQ<42>

=MEM_B_DQ<43>

=MEM_B_DQ<44>

=MEM_B_DQ<45>

=MEM_B_DQ<46>

=MEM_B_DQ<47>

=MEM_B_DQ<48>

=MEM_B_DQ<49>

=MEM_B_DQ<50>

=MEM_B_DQ<51>

=MEM_B_DQ<52>

=MEM_B_DQ<53>

=MEM_B_DQ<54>

=MEM_B_DQ<55>

=MEM_B_DQ<56>

=MEM_B_DQ<57>

=MEM_B_DQ<58>

=MEM_B_DQ<59>

=MEM_B_DQ<60>

=MEM_B_DQ<61>

=MEM_B_DQ<62>

=MEM_B_DQ<63>

=MEM_B_DQS_N<4>

=MEM_B_DQS_N<5>

=MEM_B_DQS_N<6>

=MEM_B_DQS_N<7>

=MEM_B_DQS_P<4>

=MEM_B_DQS_P<5>

=MEM_B_DQS_P<6>

=MEM_B_DQS_P<7>

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

19

BI

66 24 23 22 21

=PP1V8_S3_DDR

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

A3 A4 A5 A6

A10

U3 U4 U5 U6

U10

A8

A9 D4 D5 D6 G5 H5 H6

H12

J5

J6 K5 K6

K12

L5 P4 P5 P6

U8 U9

F2

G2

H3

L2

M2

A11 C12

E8

E12

G12

H8 H9

H11

J9

J10

LPDDR3-1600-32GB

VDD1

VDD2

VDDCA

VDDQ

U2600

EDFB232A1MA

FBGA

SYM 2 OF 2

OMIT_TABLE

CRITICAL

VSS

VSSCA

VSSQ

B2 B5 C5 E4 E5 F5 J12 K2 L6 M5 N4 N5 R4 R5 T2 T3 T4 T5 H2

C3 D3 F4 G3 G4 P3 M4 J4

B6 B12 C6 D12 E6 F6 F12 G6 G9 H10 K10 L9 M6 M12 N6 P12 R6 T6 T12

C

B

K8

K11

66 24 23 22 21

=PP1V2_S3_DDR_VDDQ

1

C2600

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2601

0.1UF

10% 16V

2

X5R-CERM 0201

1

C2602

1UF

10% 10V

2

X5R 402-1

1

C2603

10UF

20%

6.3V

2

CERM 0402

1

C2604

1UF

10% 10V

2

X5R 402-1

1

C2605

10UF

20%

6.3V

2

CERM 0402

1

C2607

1UF

10% 10V

2

X5R 402-1

1

C2606

10UF

20%

6.3V

2

CERM 0402

L12

N8

N12 R12 U11

A

66 24 23 22 21

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V8_S3_DDR

1

C2620

1UF

10% 10V

2

X5R 402-1

1

C2610

1UF

10% 10V

2

X5R 402-1

1

C2630

1UF

10% 10V

2

X5R 402-1

1

C2621

1UF

10% 10V

2

X5R 402-1

1

C2611

1UF

10% 10V

2

X5R 402-1

1

C2631

1UF

10% 10V

2

X5R 402-1

1

C2622

1UF

10% 10V

2

X5R 402-1

1

C2612

1UF

10% 10V

2

X5R 402-1

1

C2633

1UF

10% 10V

2

X5R 402-1

1

C2624

1UF

10% 10V

2

X5R 402-1

1

C2613

1UF

10% 10V

2

X5R 402-1

1

C2634

1UF

10% 10V

2

X5R 402-1

1

C2625

1UF

10% 10V

2

X5R 402-1

1

C2614

1UF

10% 10V

2

X5R 402-1

1

C2632

10UF

20%

6.3V

2

CERM 0402

1

C2626

1UF

10% 10V

2

X5R 402-1

1

C2615

1UF

10% 10V

2

X5R 402-1

1

C2635

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C2627

1UF

10% 10V

2

X5R 402-1

1

C2623

10UF

20%

6.3V

2

CERM 0402

PLACEMENT_NOTE:

10uF caps are shared between DRAM.

Distribute evenly.

SYNC_MASTER=J41_MLB SYNC_DATE=09/03/2013

PAGE TITLE

LPDDR3 DRAM Channel B (32-63)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

26 OF 123

SHEET

24 OF 81

D

A

8 7 5 4 2 1

36

345678

2 1

D

C

70 21 7

70 22 7

70 22 21 7

Intel reccomends 55 Ohm for CMD/ADDR, 80 Ohm for CTRL/CKE, 38 Ohm for CLK

=PP0V6_S3_DDRVTT_A

66 66

IN

MEM_A_CAA<9>

MEM_A_CAA<8>

MEM_A_CAA<6>

MEM_A_CAA<7>

MEM_A_CAA<5>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_A_CAA<4>

MEM_A_CAA<3>

MEM_A_CAA<2>

MEM_A_CAA<1>

MEM_A_CAA<0>

MEM_A_CAB<9>

MEM_A_CAB<8>

MEM_A_CAB<6>

MEM_A_CAB<7>

MEM_A_CAB<5>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CKE<2>

MEM_A_CKE<3>

MEM_A_CAB<4>

MEM_A_CAB<2>

MEM_A_CAB<3>

MEM_A_CAB<1>

MEM_A_CAB<0>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

RP2701 RP2701 RP2701

RP2701 R2700 R2701 R2702 R2703 R2704 R2705 R2706

RP2703

RP2703 R2725

RP2707

RP2707 R2707 R2708 R2709 R2720 R2721

RP2704

RP2704 R2722 R2723 R2724

56

39

82

56

39

82

56 56

56

82

54

1/32W

5%

63

1/32W

5%

72

81

21

54

63

72

21

54

63

72

81

21

54

63

72

81

21

1/32W5%

1/20W5% 201 MF

5% 2011/20W MF

5% MF201

1/20W

5% MF1/20W 201

5%561/20W MF201

5%

1/32W

5%

1/32W

5% 1/32W

5%561/20W MF201

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5% MF1/20W 201

5%391/20W MF201

5%

5% 1/20W

5%

1/32W5%

1/32W

5%

5%561/32W

1/32W

5%

5%821/20W 201 MF

5%

4X0201-HF

2015% 1/20W MF

4X0201-HF

201 MF1/20W

4X0201-HF

Spare

RP2703

56

5%

1/32W

4X0201-HF

81

PLACE_NEAR=RP2701.5:4mm

D

=PP0V6_S3_DDRVTT_B

1

C2700

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2701

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2703

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2705

0.47UF

20% 4V

2

CERM-X5R-1 201

MF2011/20W

MF201

1

C2707

0.47UF

20% 4V

2

CERM-X5R-1 201

MF1/20W 201

1

MF1/20W 201

C2709

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2702

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2704

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2706

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2708

0.47UF

20% 4V

2

CERM-X5R-1 201

70 23 7

70 24 7

70 24 23 7

IN

MEM_B_CAA<9>

MEM_B_CAA<8>

MEM_B_CAA<7>

MEM_B_CAA<6>

MEM_B_CAA<5>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_B_CAA<4>

MEM_B_CAA<2>

MEM_B_CAA<3>

MEM_B_CAA<1>

MEM_B_CAA<0>

MEM_B_CAB<9>

MEM_B_CAB<8>

MEM_B_CAB<7>

MEM_B_CAB<6>

MEM_B_CAB<5>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<2>

MEM_B_CKE<3>

MEM_B_CAB<4>

MEM_B_CAB<2>

MEM_B_CAB<3>

MEM_B_CAB<1>

MEM_B_CAB<0>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

RP2712 RP2712 RP2712

RP2712 R2710 R2711 R2712 R2713 R2714 R2715 R2716

RP2713

RP2713 R2735

RP2717

RP2717 R2717 R2718 R2719 R2730 R2731

RP2714

RP2714 R2732 R2733 R2734

Spare

56

39

82

56

56 56

56

39

82

56 56

56

82

RP2713

56

81

5%

1

C2720

22UF

20%

6.3V

2

X5R-CERM-1 603

CRITICAL

NC NCNCNC

1/32W

4X0201-HF

54

63

72

81

21

54

63

72

21

54

63

72

81

21

54

63

72

81

21

1/32W5%

5%

1/32W

5%

1/32W

5%

1/32W

5%

5% 1/20W MF

5% MF1/20W 201

5%

5%561/20W MF201

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

1/32W

5%

5% 1/20W MF

5%

5% 1/32W

1/32W

5%

5%561/32W

1/32W

5%

5% 1/20W MF201

4X0201-HF

MF1/20W 201

201

MF1/20W 201

4X0201-HF

2011/20W MF

4X0201-HF

MF1/20W 201

201

MF1/20W 201

201 MF1/20W

4X0201-HF

MF1/20W 201

PLACE_NEAR=RP2714.8:4.5mm

1

C2710

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2711

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2713

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2715

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2717

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2719

0.47UF

20% 4V

2

CERM-X5R-1 201

CRITICAL

1

C2740

22UF

20%

6.3V

2

X5R-CERM-1 603

1

C2712

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2714

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2716

0.47UF

20% 4V

2

CERM-X5R-1 201

1

C2718

0.47UF

20% 4V

2

CERM-X5R-1 201

C

B

A

PAGE TITLE

LPDDR3 DRAM Termination

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/03/2013SYNC_MASTER=J41_MLB

051-00081

3.0.0

27 OF 123

25 OF 81

A

D

CRITICAL

OMIT_TABLE

345678

2 1

D

C

B

A

R2890

80 5

80 13

80 5

80 13

3.3K

5%

1/20W

MF

201

IN

BI

IN

BI

www.qdzbwx.com

BYPASS=U2890.8::2mm

1

2

1

R2891

3.3K

5% 1/20W MF 201

2

TBT_SPI_MOSI_R

TBT_SPI_CLK_R

(TBT_SPI_CS_L)

TBTROM_WP_L

TBTROM_HOLD_L

DP_TBTSNK0_ML_C_P<0>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_AUXCH_C_N

C2890

201 5%

1

1UF

10%

6.3V

2

CERM

402

R2894

33

PIN SWAPPED

CRITICAL

8

OMIT_TABLE

VCC

DI/IO0

DO/IO1

U2890

6

1

3

7

CLK

CS*

WP*

HOLD*

4MBIT

W25X40CLXIG

USON

THRM_PADGND

4

21

1/20W MF

9

R2895

SNK0 AC Coupling

C2820

0.1UF

C2821

0.1UF

C2822

0.1UF

C2823

0.1UF

C2824

0.1UF

C2825

0.1UF

C2826

0.1UF

C2827

0.1UF

C2828

0.1UF

C2829

0.1UF

SNK1 AC Coupling

C2830

0.1UF

C2831

0.1UF

C2832

0.1UF

C2833

0.1UF

C2834

0.1UF

C2835

0.1UF

C2836

0.1UF

C2837

0.1UF

C2838

0.1UF

C2839

0.1UF

25

33

21

X5R-CERM

21

X5R-CERM

21

10% 16V X5R-CERM

21

X5R-CERM

21

10% 16V X5R-CERM

21

X5R-CERM

21

10% 16V X5R-CERM

21

X5R-CERM

21

10% 16V X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

21

X5R-CERM

72 14

IN

TBT_SPI_MISO_R

21

1/20W MF5%201

DP_TBTSNK0_ML_P<0>

0201

16V10%

DP_TBTSNK0_ML_N<0>

0201

16V10%

DP_TBTSNK0_ML_P<1>

0201

DP_TBTSNK0_ML_N<1>

16V10%

0201

DP_TBTSNK0_ML_P<2>

0201

DP_TBTSNK0_ML_N<2>

16V10%

0201

DP_TBTSNK0_ML_P<3>

0201

DP_TBTSNK0_ML_N<3>

16V10%

0201

DP_TBTSNK0_AUXCH_P

0201

DP_TBTSNK0_AUXCH_N

16V10%

0201

DP_TBTSNK1_ML_P<0>

16V10%

0201

DP_TBTSNK1_ML_N<0>

16V10%

0201

DP_TBTSNK1_ML_P<1>

16V10%

0201

DP_TBTSNK1_ML_N<1>

16V10%

0201

DP_TBTSNK1_ML_P<2>

0201

16V10%

DP_TBTSNK1_ML_N<2>

16V10%

0201

DP_TBTSNK1_ML_P<3>

16V10%

0201

DP_TBTSNK1_ML_N<3>

16V10%

0201

DP_TBTSNK1_AUXCH_P

16V10%

0201

DP_TBTSNK1_AUXCH_N

0201

16V10%

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_N<0>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_N<1>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_P<3>

79 27 26 18

R2892

3.3K

5%

1/20W

MF

201

1

2

PP3V3_TBTLC

1

R2893

3.3K

5% 1/20W MF 201

2

C2800

C2801

C2802

C2803

C2804

C2805

C2806

C2807

80 26

0.1UF

R2829

10K

5%

1/20W

MF

201

1

2

21

16V X5R-CERM

21

16V X5R-CERM

21

16V X5R-CERM 020110%

21

16V X5R-CERM

21

16V X5R-CERM

10% 0201

21

16V X5R-CERM 020110%

21

16V X5R-CERM 020110%

21

16V X5R-CERM 020110%

OMIT

NONE NONE NONE 0201

1

2

R2815

NOSTUFF

R2896

5%0201 MF1/20W

1

R2825

100

5% 1/20W MF 201

2

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

72

020110%

15

27

IN

PCIE_TBT_R2D_P<0>

72

PCIE_TBT_R2D_N<0>

72

PCIE_TBT_R2D_P<1>

72

PCIE_TBT_R2D_N<1>

72

PCIE_TBT_R2D_P<2>

72

PCIE_TBT_R2D_N<2>

72

PCIE_TBT_R2D_P<3>

72

PCIE_TBT_R2D_N<3>

PCH_TBT_PCIE_RESET_L

TBT_PWR_ON_POC_RST_L

NC_TBT_MONDC0

NC_TBT_MONDC1

DEBUG: For monitoring current/voltage

TBT_MONOBSP

TBT_MONOBSN

DEBUG: For monitoring clock

48

OUT

0

21

18

IN

18

IN

18

IN

18

OUT

TBT_THERM_DP

Use AA8 GND ball for THERM_DN

80

TBT_SPI_MOSI

80

TBT_SPI_MISO

80

TBT_SPI_CS_L

TBT_SPI_CLK

80

JTAG_TBT_TDI

JTAG_TBT_TMS

JTAG_TBT_TCK

JTAG_TBT_TDO

TBT_TEST_EN

TBT_TEST_PWR_GOOD

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_ML_N<3>

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_P<1>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK0_AUXCH_P

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_HPD

OUT

DP_TBTSNK1_ML_P<3>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_HPD

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_N<0>

TBT_A_D2R_P<0>

TBT_A_D2R_N<0>

TBT_A_CONFIG1_BUF

TBT_A_CONFIG2_RC

TBT_A_R2D_C_P<1>

TBT_A_R2D_C_N<1>

TBT_A_D2R_P<1>

TBT_A_D2R_N<1>

TBT_A_LSTX

TBT_A_LSRX

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_N<3> DP_TBTPB_ML_C_N<3>

DP_TBTPA_AUXCH_C_P

DP_TBTPA_AUXCH_C_N

DP_TBTPA_HPD

TBT_A_HV_EN

TBT_A_CIO_SEL

TBT_A_DP_PWRDN

18

80 28

28

80 28

28

80 28

28

28 26

28

28 26

80 26

18

80 26

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

OUT

AB9

AA10

AA12 AB13

AB15 AA16

AA18 AB19

P5

R4

AD23 AC24

W18 W16

AB7

AA2

Y3

T5

U8

W2 AB1 AA6

U6 R6

W8

E14 D13

E16 D15

E18 D17

E20 D19

G4 G2

AB5

E6 D5

E8 D7

E10

D9

E12 D11

H3 H1

U4

G24 E24

G22 E22

P1 K5

L24

J24

L22

J22

N8

J6

A16 B17

A18 B19

L4 L2

M3

PERP_0 PERN_0

FALCON RIDGE

PERP_1 PERN_1

PERP_2 PERN_2

PERP_3 PERN_3

PERST_OD_N

PWR_ON_POC_RSTN

MONDC0 MONDC1

MONOBSP MONOBSN

THERMDA

EE_DI EE_DO EE_CS_N EE_CLK

TDI TMS TCK TDO TEST_EN TEST_PWR_GOOD

DPSNK0_3_P DPSNK0_3_N

DPSNK0_2_P DPSNK0_2_N

DPSNK0_1_P DPSNK0_1_N

DPSNK0_0_P DPSNK0_0_N

DPSNK0_AUX_P DPSNK0_AUX_N

DPSNK0_HPD

DPSNK1_3_P DPSNK1_3_N

DPSNK1_2_P DPSNK1_2_N

DPSNK1_1_P DPSNK1_1_N

DPSNK1_0_P DPSNK1_0_N

DPSNK1_AUX_P DPSNK1_AUX_N

DPSNK1_HPD

PA_CIO0_TX_P/DPSRC_0_P PA_CIO0_TX_N/DPSRC_0_N

PA_CIO0_RX_P PA_CIO0_RX_N

PA_CONFIG1/CIO_0_LSEO PA_CONFIG2/CIO_0_LSOE

PA_CIO1_TX_P/DPSRC_2_P PA_CIO1_TX_N/DPSRC_2_N

PA_CIO1_RX_P PA_CIO1_RX_N

PA_LSTX/CIO_1_LSEO PA_LSRX/CIO_1_LSOE

PA_DPSRC_1_P PA_DPSRC_1_N

PA_DPSRC_3_P PA_DPSRC_3_N

PA_AUX_P PA_AUX_N

PA_DPSRC_HPD

GPIO_0/PA_HV_EN/BYP0 GPIO_10/PA_CIO_SEL/BYP1 GPIO_12/PA_DP_PWRDN/BYP2

U2800

PETP_0

PETN_0

FCBGA

SYM 1 OF 2

PETP_1

PETN_1

PETP_2

PETN_2

PCIE GEN2

PETP_3

PETN_3

RSENSE

RBIAS

RSVD_GND

GPIO_16/DEVICE_PCIE_RST_N

GPIO_17

MISC

PCIE_CLKREQ_OD_N

REFCLK_100_IN_P REFCLK_100_IN_N

DISPLAY PORT

DPSRC_HPD_OD

GPIO_2/TMU_CLK_IN/AC_PRESENT

GPIO_3/FORCE_PWR

GPIO_4/WAKE_OD_N

GPIO_5/CIO_PLUG_EVENT_N/HV_OK_OD

GPIO_6_OD/CIO_SDA_OD

GPIO_7_OD/CIO_SCL_OD

GPIO_8/EN_CIO_PWR_N_OD

GPIO_9/SX_CTRL_OD*

PB_CIO2_TX_P/DPSRC_0_P

PB_CIO2_TX_N/DPSRC_0_N

PB_CONFIG1/CIO_2_LSEO PB_CONFIG2/CIO_2_LSOE

PB_CIO3_TX_P/DPSRC_2_P

PB_CIO3_TX_N/DPSRC_2_N

PB_LSTX/CIO_3_LSEO

PB_LSRX/CIO_3_LSOE

PB_DPSRC_1_P PB_DPSRC_1_N

PORTS

GPIO_1/PB_HV_EN/BYP0

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

PB_DPSRC_3_P PB_DPSRC_3_N

PB_DPSRC_HPD

GPIO_18 GPIO_19

XTAL_25_IN

XTAL_25_OUT

TMU_CLK_OUT

DPSRC_3_P DPSRC_3_N

DPSRC_2_P DPSRC_2_N

DPSRC_1_P DPSRC_1_N

DPSRC_0_P DPSRC_0_N

DPSRC_AUX_P DPSRC_AUX_N

GPIO_14 GPIO_15

PB_CIO2_RX_P

PB_CIO2_RX_N

PB_CIO3_RX_P

PB_CIO3_RX_N

PB_AUX_P PB_AUX_N

AD5 AD7

AD9 AD11

AD13 AD15

AD17 AD19

U20

W20

AD1 L8

W6 AB3 AD3 V1

V3

AB21 AD21

AA24 AB23

AA4

A14 B15

A12 B13

A10 B11

A8 B9

J4 J2

AC2

U2 L6 H5 Y7 Y1 T7 V7 M7 T1 T3

R24 N24

R22 N22

D3 M1

W24 U24

W22 U22

M5 P7

A20 B21

A22 B23

K3 K1

N6

F1R8 R2N2 F3P3

72

PCIE_TBT_D2R_C_P<0>

72

PCIE_TBT_D2R_C_N<0>

72

PCIE_TBT_D2R_C_P<1>

72

PCIE_TBT_D2R_C_N<1>

72

PCIE_TBT_D2R_C_P<2>

72

PCIE_TBT_D2R_C_N<2>

PCIE_TBT_D2R_C_P<3>

72

PCIE_TBT_D2R_C_N<3>

TBT_RSENSE

TBT_RBIAS

Used for straps in host mode

TP_TBT_PCIE_RESET0_L

TBT_DFT_STRAP_1

TBT_ROM_SECURITY_XOR

TBT_DFT_STRAP_3

TBT_CLKREQ_L

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

TBT_CLK25M_IN

TBT_CLK25M_OUT

TBT_TMU_CLK_OUT

DP_TBTSRC_ML_P<3>

DP_TBTSRC_ML_N<3>

DP_TBTSRC_ML_P<2>

DP_TBTSRC_ML_N<2>

DP_TBTSRC_ML_P<1>

DP_TBTSRC_ML_N<1>

DP_TBTSRC_ML_P<0>

DP_TBTSRC_ML_N<0>

DP_TBTSRC_AUX_P

DP_TBTSRC_AUX_N

DP_TBTSRC_HPD

TBT_GPIO2

TBT_PWR_EN

TBT_WAKE_L

TBT_CIO_PLUG_EVENT_L

HDMITBTMUX_SEL_TBT

TBT_GPIO7

TBT_EN_CIO_PWR_L

TBT_BATLOW_L

TBTDP_AUXIO_EN

TBT_DDC_XBAR_EN_L

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_N<0>

TBT_B_D2R_P<0>

TBT_B_D2R_N<0>

TBT_B_CONFIG1_BUF

TBT_B_CONFIG2_RC

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_N<1>

TBT_B_D2R_P<1>

TBT_B_D2R_N<1>

TBT_B_LSTX

TBT_B_LSRX

DP_TBTPB_ML_C_P<1>

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_P<3>

DP_TBTPB_AUXCH_C_P

DP_TBTPB_AUXCH_C_N

DP_TBTPB_HPD

TBT_B_HV_EN

TBT_B_CIO_SEL

TBT_B_DP_PWRDN

C2840

C2841

C2842

C2843

C2844

C2845

C2846

C2847

1

R2855

1K

1% 1/20W MF 201

2

67

OUT

IN

OUT

BI

IN

OUT

26 15

OUT

26

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

IN

OUT

0.1UF

12

72 12

74 17

40

80 40

40 26

15

18

15

27 26

30 26

80 29

29

80 29

29

80 29

29

29 26

29

29 26

21

PCIE_TBT_D2R_P<0>

16V10% X5R-CERM

21

PCIE_TBT_D2R_N<0>

16V10% X5R-CERM

21

PCIE_TBT_D2R_N<1>

21

PCIE_TBT_D2R_P<1>

16V10% X5R-CERM

21

PCIE_TBT_D2R_N<2>

16V10%

X5R-CERM 0201

21

PCIE_TBT_D2R_P<2>

10% 16V X5R-CERM

21

PCIE_TBT_D2R_P<3>

21

PCIE_TBT_D2R_N<3>

10% 16V

X5R-CERM 0201

Security strap setting is XORed with

bit in the flash, so the active-level

depends on the code in the flash.

If strap != bit then security is enabled?

0201

020116V10% X5R-CERM

0201

0201X5R-CERM10% 16V

OUT

72 14

PIN SWAPPED

72 14

PIN SWAPPED

72 14

79 27 26 18

PP3V3_TBTLC

1

R2861

10K

5% 1/20W MF 201

2

NO STUFF

1

R2867

10K

5% 1/20W MF 201

2

1

R2862

10K

5% 1/20W MF 201

2

1

R2863

10K

5% 1/20W MF 201

2

D

C

79 27 26 18

66 64 29 28 27 26 18

NO STUFF

10K

5%

1/20W

MF

201

1

2

27 26

30 26

26 15

29 28 26

40 26

TBT_EN_CIO_PWR_L

TBT_DDC_XBAR_EN_L

HDMITBTMUX_SEL_TBT

TBTDP_AUXIO_EN

DP_TBTSRC_HPD

R2899

PP3V3_TBTLC

80 40

29 28 26

R2878

100K

5%

1/20W

MF

201

1

2

1

R2879

100K

5% 1/20W MF 201

2

66 64 29 28 27 26 18

28 26

29 26

28 26

29 26

www.qdzbwx.com

NOTE: The following pins require testpoints:

0 - GPIO_13

1 - GPIO_1

2 - GPIO_2

3 - GPIO_3

4 - GPIO_5

5 - PCIE_RST_1_N

6 - PCIE_RST_2_N

7 - PCIE_RST_3_N 15 - PB_LSRX

SYNC_MASTER=J117_NICK

PAGE TITLE

80 29

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

PP3V3_TBTLC

=PP3V3_S4_TBT

100K

5%

1/20W

MF

201

1

2

R2880

R2881

79 27 26 18

R2832

100K

5%

1/20W

MF

201

100K

5%

1/20W

MF

201

1

2

1

2

=PP3V3_S4_TBT

NO STUFF

10K

5%

1/20W

MF

201

1

2

TBT_BATLOW_L

26

R2884

100K

5%

1/20W

MF

201

1

2

R2885

TBT_A_DP_PWRDN

TBT_B_DP_PWRDN

TBT_A_HV_EN

TBT_B_HV_EN

10K

5%

1/20W

MF

201

1

2

R2888

8 - GPIO_15

9 - GPIO_11

10 - GPIO_14

11 - GPIO_0

12 - GPIO_12

13 - GPIO_10

14 - PB_LSTX

Thunderbolt Host (1 of 2)

DRAWING NUMBER SIZE

Apple Inc.

R

051-00081

REVISION

BRANCH

PAGE

28 OF 123

SHEET

1

R2882

100K

5% 1/20W MF 201

2

1

R2883

100K

5% 1/20W MF 201

2

NO STUFF

1

R2886

10K

5% 1/20W MF 201

2

1

R2887

10K

5% 1/20W MF 201

2

SYNC_DATE=01/27/2014

D

3.0.0

26 OF 81

B

A

8 7 5 4 2 1

36

D

C

B

A

PP1V05_TBTRDV

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

1

2

20%

6.3V X5R

1

2

C2900

1.0UF

0201-1

PP1V05_TBT

27

MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.05V

C2901

1.0UF

20%

6.3V X5R

0201-1

20%

6.3V X5R

1

C2903

1.0UF

2

0201-1

1

C2902

1.0UF

2

0201-1

20%

6.3V X5R

1

C2904

1.0UF

2

0201-1

20%

6.3V X5R

1

C2905

1.0UF

2

0201-1

20%

6.3V X5R

1

2

C2906

1.0UF

20%

6.3V X5R

0201-1

C2910

1.0UF

0201-1

CRITICAL

L2920

680NH-30%-3.6A-35MOHM

C2923

10UF

20%

6.3V

CERM-X5R

0402-1

1900 mA EDP

1

2

C2922

10UF

20%

6.3V

CERM-X5R

0402-1

SM

10UF

20%

6.3V

1

C2920

10UF

2

CERM-X5R

0402-1

1

2

C2921

CERM-X5R

0402-1

20%

6.3V

1

CRITICAL

2

21

D2920

SOD-323

P1V05TBT_SW

MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2000 DIDT=TRUE SWITCH_NODE=TRUE

K

NSR1020MW2T1G

A

A2, B1, and C2 are the ground current pins for A4, A6, and B3. They should be routed as a shape to the annode of D2920.

www.qdzbwx.com

EDP current / power consumption figures copied from R68 schematic (Rev 2, dated October 28, 2012, not available on IBL).

700 mA EDP

1

20%

6.3V

2

X5R

C2911

1.0UF

20%

6.3V X5R

0201-1

345678

2 1

U2950

Part SLG5AP304V

Type

R(on)

@ 1.05V

Load Switch

7.8 mOhm Typ

9.6 mOhm Max

1.05V TBT "CIO" Switch

Internal switch not functional on RR.

66 64 29 28 27 26 18

Max Current = 4A (85C)

PP1V05_TBT

27

G10 G12 G14 G16 G18

H19

H9

J18 K15 K17 K19

K7

L16

M19

P19 T19

U2800

FALCON RIDGE

FCBGA

SYM 2 OF 2

VCC1P0_CIO

VCC1P0_RDV_DECAP

J10 J12 K11 L10 M11 N10 N14 P11 P15 R10 R14 T11 T15 U10 U14 V11

C2930

1.0UF

20%

6.3V X5R

0201-1

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000

1

C2931

1.0UF

2

0201-1

20%

6.3V X5R

1

2

C2932

1.0UF

20%

6.3V X5R

0201-1

VOLTAGE=1.05V

1

1200 mA EDP

2

U18

V15

V17 W12 W14

VCC

VCC3P3

D1 E2 H11 N4

SVR input to RR - 1100 mA EDP

POC input to RR - 150 mA EDP

Isolated to reduce noise from SVR

V5

J8

K9

1

2

L14 M15 M17

VCC3P3_LC

SVR_VCC1P0

P17 V19

VCC3P3_RDV_DECAP

NC

A4 A6 B3

B5

SVR_AMON

SVR_IND

A2

A24 AA14 AA20 AA22

AA8 AB11 AB17

AC10 AC12 AC14 AC16 AC18

GND

AC20 AC22

AC4

AC6

AC8

B1 B7

VSS

C10 C12 C14 C16 C18

C2 C20 C22 C24

C4

C6

C8 D21 D23

E4

F11 F13 F15 F17 F19 F21 F23

F5

F7

F9

W4

Y5

H13 H15 H17 H7 L18 N18 R18 W10

G20 G6 G8 H21 H23 J14 J16 J20 K13 K21 K23 L12 L20 M13 M21 M23 M9 N12 N16 N20 P13 P21 P23 P9 R12 R16 R20 T13 T17 T21 T23 T9 U12 U16 V13 V21 V23 V9 Y11 Y13 Y15 Y17 Y19 Y21 Y23

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1500 VOLTAGE=3.3V

100 mA EDP

20%

6.3V X5R

1

2

C2970

1.0UF

0201-1

PP3V3_TBTRDV PP3V3_S4_TBT_F

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000

PP3V3_TBTLC

VOLTAGE=3.3V

25 mA EDP

65 44 43

66 27 16 15 13 12

15

1

C2980

1.0UF

20%

6.3V

2

X5R 0201-1

IN

SMC_DELAYED_PWRGD

=PP3V3_S0_PCH_GPIO

IN OUT

1

C2981

1.0UF

20%

6.3V

2

X5R 0201-1

66 64 29 28 27 26 18

R2995

100K

5%

1/20W

MF

201

=PP3V3_S4_TBT

1

GS

2

Y9

=PP3V3_S4_TBT

3 7

5 2

66 27 16 15 13 12

20%

6.3V

20%

6.3V X5R

1

2

1

2

C2950

10UF

CERM-X5R

0402-1

C2960

1.0UF

0201-1

Q2995

DMN32D2LFB4

DFN1006H4-3

SYM_VER_3

C2995

330PF

U2940

SLG5AP304V

D

3

10% 16V X7R

0201

CRITICAL

C2951

CERM-X5R

C2961

1

2

1

C2940

1

VDD

TDFN

GND

8

CAP

ONS

1.0UF

20%

6.3V

2

X5R 0201-1

TBT_CIO_FET_CAP

TBT_EN_CIO_PWR

C2941

0.0022UF

10% 50V

CERM

402

1

2

PP3V3_TBTLC

1

R2945

100K

5% 1/20W MF 201

2

6

D

1

VER 3

2

GS

Q2945

DMN5L06VK-7

SOT563

=PP3V3_S0_PCH_GPIO

5

13

OUT

TBT_PWR_REQ_L

Pull-up (S0) on PCH page

GS

4

VER 3

D

3

TBT_EN_CIO_PWR_L

Q2945

DMN5L06VK-7

SOT563

=PP3V3_S4_TBT

3.1 W (Dual-Port)

2.4 W (Single-Port)

10UF

20%

6.3V

0402-1

1.0UF

20%

6.3V X5R

0201-1

1

2

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

1

2

C2952

10UF

20%

6.3V

CERM-X5R

0402-1

1

C2953

10UF

2

CERM-X5R

0402-1

20%

6.3V

1

2

EDP: 1.25 A

PLACE_NEAR=C2952.1:3mm

2

XW2960

SM

1

TBT "POC" Power-up Reset

1

CRITICAL

1

3

SENSE

100K

5%

1/20W

MF

201

1

2

1

R2990

100K

5% 1/20W MF 201

2

R2992

TBTPOCRST_MR_LTBT_POC_RESET_L

TBTPOCRST_SENSE TBTPOCRST_CT

1

R2991

24.9K

1% 1/20W MF 201

2

6

VCC

U2990

TPS3895ADRY

USON

SENSE_OUTENABLE

GND

2

CT

4

5

Vth = 2.508V nominal

SYNC_MASTER=J70_NICK SYNC_DATE=01/12/2014

PAGE TITLE

C2990

0.1UF

10% 25V

2

X5R 402

Push-pull output

TBT_PWR_ON_POC_RST_L

Delay = 4.04ms nominal

Thunderbolt Host (2 of 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

79 27 26 18

D

26

IN

66 64 29 28 27 26 18 79 27 26 18

C

B

26

10% 50V

0402

1

2

C2991

0.001UF

X7R-CERM

A

DRAWING NUMBER SIZE

051-00081

REVISION

3.0.0

BRANCH

PAGE

29 OF 123

SHEET

27 OF 81

D

8 7 5 4 2 1

36

345678

2 1

D

V3P3 must be S4 to support

wake from Thunderbolt devices.

=PP3V3_S4_TBTAPWRSW

66

CRITICAL

C3287

100UF

20%

6.3V

POLY-TANT

CASE-B2-SM

=PPHV_SW_TBTAPWRSW

66

1

2

CRITICAL

C3280

22UF

20%

6.3V

X5R-CERM-1

603

18.9V Max

10% 25V

0603

IN

1

2

=TBTAPWRSW_EN

TBT_A_HV_EN

=TBT_S0_EN

C3215

4.7UF

X5R-CERM

64

26

64 29

1

2

1

C3210

0.1UF

10% 50V

2

X7R 603-1

1

C3281

0.1UF

20% 10V

2

CERM 402

3.3V/HV Power MUX

For 12V systems:

I(min) = 38429/R - 0.0161A I(max) = 41571/R + 0.0161A

Min Max

IV3P3 1040mA 1155mA

IHVS0/S3 1060mA 1180mA (12W minimum)

PAD

21

18

12 14

416

8

1011

9

NC

TBTAPWRSW_ISET_V3P3

TBTAPWRSW_ISET_S0

TBTAPWRSW_ISET_S3

19 20

6 7

5

17

V3P3

VHV

CRITICAL

U3210

CD3211A1RGP

QFN

ENHVU

EN

HV_EN

S0

GND THRM

3

2

1

13

V3P3OUT

OUT

FAULTZ

ISET_V3P3

ISET_S0

ISET_S3

15

R3210

35.7K

1%

1/20W

MF

201

PPHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=15V

1

C3211

0.1UF

10% 50V

2

X7R 603-1

1

2

1

R3211

35.7K

1% 1/20W MF 201

2

PART NUMBER

1

R3212

36.5K

1% 1/16W MF-LF 402

2

TABLE_ALT_HEAD

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

3.3V INPUT CAP128S0220128S0398 ALL

C3277

80 26

OUT

TBT_A_D2R_P<1>

TBT_A_D2R_N<1>

C3276

66 64 29 27 26 18

GND_VOID=TRUE

(Both C's)

0.47UF

80 26

BI

DP_TBTPA_AUXCH_C_N

DP_TBTPA_AUXCH_C_P

C3230

0.1UF

C3231

0.1UF

21

20% X5R

21

20% X5R

80 26

IN

DP_TBTPA_ML_C_P<1>

DP_TBTPA_ML_C_N<1>

C3232

0.22UF

C3233

0.22UF

=PP3V3_S4_TBT

21

20%

4V

CERM-X5R-1

21

CERM-X5R-1 201

21

10% CERM-X5R

21

10% CERM-X5R

6.3V 0201

4V20%

6.3V

201

0201

30 80

80 30

26

POLARITY SWAPPED

80

TBT_A_D2R_C_N<1>

80

TBT_A_D2R_C_P<1>

DP_TBTPA_AUXCH_N

80

BI

IN

OUT

IN

OUT

DP_TBTPA_DDC_DATA

DP_TBTPA_DDC_CLK

TBT_A_CONFIG1_BUF

DP_TBTPA_ML_P<1>

80

DP_TBTPA_ML_N<1>

80

TBT_A_LSTX

TBT_A_LSRX

DP_TBTPA_HPD

C3220

0.1UF

10%

6.3V

CERM-X5R

0201

10%

6.3V

0201

1

2

3

VDD

1

C3221

0.1UF

2

CERM-X5R

CRITICAL

U3220

CBTL05024

GND_VOID=TRUE

7 15 8

1 2

4 5

16 18

11 10

14 13

12 17

HVQFN24-COMBO

TB- TB_ENA TB+

AUXIO_EN

DP_PD AUXAUX+

AUXIO-

AUXIO+ DDC_DAT DDC_CLK

CA_DETOUT

CA_DET

DP+ DP-

LSTX

DPMLO+

DPMLO-

LSRX

HPDOUT

HPD

24 6

GND_VOID=TRUE

23 22

GND_VOID=TRUE

19 20

TBT_A_CIO_SEL

TBTDP_AUXIO_EN

TBT_A_DP_PWRDN

TBT_A_D2R1_AUXDDC_NDP_TBTPA_AUXCH_P

TBT_A_D2R1_AUXDDC_P

TBT: RX_1

TBT_A_CONFIG1_RC

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_A_HPD

28

26

IN

29 26

26

80 28

D

GND THMPAD

9

21

25

C

B

80 26

POLARITY SWAPPED

OUT

IN

TBT_A_D2R_N<0>

TBT_A_D2R_P<0>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_N<3>

C3274

0.47UF

C3275

0.47UF

26

GND_VOID=TRUE

(Both C's)

C3278

0.22UF

C3279

0.22UF

TBT_A_HPD

28

TBT_A_CONFIG1_RC

28

OUT

TBT_A_CONFIG2_RC

21

4V

20% CERM-X5R-1

21

4V

20% CERM-X5R-1

21

X5R

21

X5R

201

6.3V20% 0201

R3252

1M

5%

1/20W

MF

201

TBT_A_D2R_C_P<0>

80

TBT_A_D2R_C_N<0>

80

DP_TBTPA_ML_P<3>

80

DP_TBTPA_ML_N<3>

TBT: Terminated

1

2

1

R3251

1M

5% 1/20W MF 201

2

GND_VOID=TRUE

1/20W

10% 16V X7R

0201

1K

5%

MF

201

1

2

1

2

R3294

NO_XNET_CONNECTION=1

C3294

330PF

GND_VOID=TRUE

1

R3295

1K

5% 1/20W MF 201

2

NO_XNET_CONNECTION=1

R3278

R3279

1

C3295

330PF

10% 16V

2

X7R 0201

1

R3241

100K

5% 1/20W MF 201

2

470K

80 28

10% 50V

0402

5% MF

1

2

1/20W5%

1/20W

201MF

201

C3200

0.01UF

X7R-CERM

21

TBT_A_D2R1_AUXDDC_P

TBT_A_D2R1_AUXDDC_N

10% 25V

0201

1

2

C3202

0.01UF

X5R-CERM

L3200

FERR-120-OHM-3A

21

0603

1

C3201

0.01UF

10% 50V

2

X7R-CERM 0402

PP3V3RHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=15V

TBTACONN_20_RC

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=18.9V

TBT: RX_0

DP: Lane 3

TBT: RX_1

DP Source must pull

down HPD input with

greater than or equal

to 100K (DPv1.1a).

Sink HPD range:

High: 2.0 - 5.0V

Low: 0 - 0.8V

R3201

12

5%

1/20W

MF

201

Thunderbolt Connector A

TBTACONN_1_C

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=18.9V

21

DP: Lane 0

CRITICAL

4645444342

SHLD

J3200

2 4 6

8 7 10 12 14 13 16 18 20

J70:514-0824 / J78:514-0831

DUAL-MDP-K70

HPD CONFIG1 CONFIG2 GND2 ML_LANE3P ML_LANE3N GND4 AUX_CHP AUX_CHN DP_PWR

F-ANG-TH

PORT A

SHLD

65525150494847

41

GND0

ML_LANE0P

ML_LANE0N

GND1

ML_LANE1P

ML_LANE1N

GND3

ML_LANE2P

ML_LANE2N

RETURN

1 3 5

9 11

15 17 19

TBTACONN_7_C

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=18.9V

DP: Lane 1

DP: Lane 2

(0-18.9V)

TBT: TX_0

(0-18.9V)

TBT: TX_1

C3205

0.01UF

21

10% 25V

X5R-CERM

0201

80

TBT_A_R2D_P<0>

TBT_A_R2D_N<0>

80

C3206

0.01UF

10% 25V

X5R-CERM

0201

TBT_A_R2D_P<1>

80

TBT_A_R2D_N<1>

C

GND_VOID=TRUE

(Both C's)

C3270

0.22UF

C3271

0.22UF

GND_VOID=TRUE

1

R3270

470K

5% 1/20W MF 201

2

21

GND_VOID=TRUE

(Both C's)

C3272

0.22UF

C3273

0.22UF

GND_VOID=TRUE

1

R3272

470K

5% 1/20W MF 201

2

470k R's for ESD protection

on AC-coupled signals.

21

6.3V

20% X5R

0201

21

6.3V

20% X5R

0201

GND_VOID=TRUE

1

R3271

470K

5% 1/20W MF 201

2

21

6.3V

20% X5R

0201

21

6.3V

20% X5R

0201

GND_VOID=TRUE

1

R3273

470K

5% 1/20W MF 201

2

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_N<0>

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

POLARITY SWAPPED

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

IN

80 26

80 28

80 26

B

A

SYNC_MASTER=J70_NICK SYNC_DATE=10/16/2013

PAGE TITLE

Thunderbolt Connector A

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

32 OF 123

28 OF 81

A

D

345678

2 1

D

V3P3 must be S4 to support

wake from Thunderbolt devices.

=PP3V3_S4_TBTBPWRSW

66

CRITICAL

C3387

100UF

20%

6.3V

POLY-TANT

CASE-B2-SM

=PPHV_SW_TBTBPWRSW

66

1

2

CRITICAL

C3380

22UF

20%

6.3V

X5R-CERM-1

603

1

2

18.9V Max

10% 25V

0603

IN

1

2

=TBTBPWRSW_EN

TBT_B_HV_EN

=TBT_S0_EN

C3315

4.7UF

X5R-CERM

64

26

64 28

1

C3310

0.1UF

10% 50V

2

X7R 603-1

1

C3381

0.1UF

20% 10V

2

CERM 402

3.3V/HV Power MUX

IV3P3 1040mA 1155mA

IHVS0/S3 1060mA 1180mA (12W minimum)

PAD

21

18

12 14

416

8

1011

9

NC

TBTBPWRSW_ISET_V3P3

TBTBPWRSW_ISET_S0

TBTBPWRSW_ISET_S3

19 20

6 7

5

17

V3P3

VHV

CRITICAL

U3310

CD3211A1RGP

QFN

ENHVU

EN

HV_EN

S0

GND THRM

3

2

1

13

V3P3OUT

OUT

FAULTZ

ISET_V3P3

ISET_S0

ISET_S3

15

For 12V systems:

I(min) = 38429/R - 0.0161A I(max) = 41571/R + 0.0161A

Min Max

PPHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=15V

1

C3311

0.1UF

10% 50V

2

X7R 603-1

R3310

35.7K

1%

1/20W

MF

201

1

2

1

2

R3311

35.7K

1% 1/20W MF 201

1

R3312

36.5K

1% 1/16W MF-LF 402

2

80 26

66 64 28 27 26 18

GND_VOID=TRUE

=PP3V3_S4_TBT

(Both C's)

C3377

0.47UF

C3376

OUT

TBT_B_D2R_P<1>

TBT_B_D2R_N<1>

0.47UF

BI

DP_TBTPB_AUXCH_C_N

DP_TBTPB_AUXCH_C_P

C3330

0.1UF

C3331

0.1UF

DP_TBTPB_ML_C_P<1> DP_TBTPB_ML_P<1>

IN

DP_TBTPB_ML_C_N<1>

IN

C3332

0.22UF

C3333

0.22UF

21

20% 4V

21

20%

4V

CERM-X5R-1

21

6.3V

10% CERM-X5R

21

10%

6.3V

CERM-X5R

21

20%

6.3V 0201

X5R

21

20%

6.3V 0201

X5R

201CERM-X5R-1

201

0201

30 80

80 30

26

POLARITY SWAPPED

TBT_B_D2R_C_N<1>

80

TBT_B_D2R_C_P<1>

DP_TBTPB_AUXCH_N

80

DP_TBTPB_AUXCH_P

BI

IN

OUT

IN

OUT

DP_TBTPB_DDC_DATA

DP_TBTPB_DDC_CLK

TBT_B_CONFIG1_BUF

80

DP_TBTPB_ML_N<1>

TBT_B_LSTX

TBT_B_LSRX

DP_TBTPB_HPD

C3320

0.1UF

10%

6.3V

CERM-X5R

0201

10%

6.3V

0201

1

2

3

VDD

1

C3321

0.1UF

2

CERM-X5R

CRITICAL

U3320

CBTL05024

GND_VOID=TRUE

7 15 8

1 2

4 5

16 18

11 10

14 13

12 17

HVQFN24-COMBO

TB- TB_ENA TB+

AUXIO_EN

DP_PD AUXAUX+

AUXIO-

AUXIO+ DDC_DAT DDC_CLK

CA_DETOUT

CA_DET

DP+ DP-

LSTX

DPMLO+

DPMLO-

LSRX

HPDOUT

HPD

GND THMPAD

9

21

25

24 6

GND_VOID=TRUE

23 22

GND_VOID=TRUE

19 20

TBT_B_CIO_SEL

TBTDP_AUXIO_EN

TBT_B_DP_PWRDN

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R1_AUXDDC_P

TBT: RX_1

TBT_B_CONFIG1_RC

DP_B_LSX_ML_P<1>

DP_B_LSX_ML_N<1>

TBT: LSX_B_R2P/P2R (P/N)

TBT_B_HPD

29

26

IN

80 29

28 26

26

80 29

D

C

B

80 26

POLARITY SWAPPED

OUT

TBT_B_D2R_N<0>

TBT_B_D2R_P<0>

POLARITY SWAPPED

IN

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_P<3>

C3374

0.47UF

C3375

0.47UF

26

GND_VOID=TRUE

(Both C's)

C3379

0.22UF

C3378

0.22UF

TBT_B_HPD

29

TBT_B_CONFIG1_RC

29

OUT

TBT_B_CONFIG2_RC

21

4V

20% CERM-X5R-1

21

CERM-X5R-1 201

201

4V20%

21

20% X5R

21

20% X5R

6.3V 0201

R3352

1M

5%

1/20W

MF

201

TBT_B_D2R_C_P<0>

80

TBT_B_D2R_C_N<0>

DP_TBTPB_ML_P<3>

80

DP_TBTPB_ML_N<3>

TBT: Terminated

1

2

1

R3351

1M

5% 1/20W MF 201

2

GND_VOID=TRUE

1/20W

10% 16V X7R

0201

1K

5%

MF

201

1

2

1

2

R3394

NO_XNET_CONNECTION=1

C3394

330PF

GND_VOID=TRUE

1

R3395

1K

5% 1/20W MF 201

2

NO_XNET_CONNECTION=1

R3378

R3379

1

C3395

330PF

10% 16V

2

X7R 0201

1

R3341

100K

5% 1/20W MF 201

2

470K

80 29

10% 50V

0402

MF

5% MF

1

2

1/20W5%

1/20W

201

C3300

0.01UF

X7R-CERM

21

TBT_B_D2R1_AUXDDC_P

TBT_B_D2R1_AUXDDC_N

10% 25V

0201

1

2

C3302

0.01UF

X5R-CERM

L3300

FERR-120-OHM-3A

21

0603

1

C3301

0.01UF

10% 50V

2

X7R-CERM 0402

PP3V3RHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=15V

TBTBCONN_20_RC

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=18.9V

TBT: RX_0

DP: Lane 3

TBT: RX_1

DP Source must pull

down HPD input with

greater than or equal

to 100K (DPv1.1a).

Sink HPD range:

High: 2.0 - 5.0V

Low: 0 - 0.8V

R3301

12

5%

1/20W

MF

201

Thunderbolt Connector B

TBTBCONN_1_C

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=18.9V

21

DP: Lane 0

CRITICAL

5857565554

SHLD

J3200

22 24 26 28 27 30 32 34 33 36 38 40

J70:514-0824 / J78:514-0831

DUAL-MDP-K70

HPD CONFIG1 CONFIG2 GND2 ML_LANE3P ML_LANE3N GND4 AUX_CHP AUX_CHN DP_PWR

F-ANG-TH

PORT B

SHLD

65

6463626160

53

GND0

ML_LANE0P

ML_LANE0N

GND1

ML_LANE1P

ML_LANE1N

GND3

ML_LANE2P

ML_LANE2N

RETURN

59

21 23 25

29 31

35 37 39

TBTBCONN_7_C

MIN_LINE_WIDTH=0.3800 MIN_NECK_WIDTH=0.2000 VOLTAGE=18.9V

DP: Lane 1

DP: Lane 2

(0-18.9V)

TBT: TX_0

(0-18.9V)

TBT: TX_1

C3305

0.01UF

21

10% 25V

X5R-CERM

0201

80

TBT_B_R2D_P<0>

80

TBT_B_R2D_N<0>

C3306

0.01UF

10% 25V

X5R-CERM

0201

TBT_B_R2D_P<1>

80

TBT_B_R2D_N<1>

C

GND_VOID=TRUE

(Both C's)

C3370

0.22UF

C3371

0.22UF

GND_VOID=TRUE

1

R3370

470K

5% 1/20W MF 201

2

21

GND_VOID=TRUE

(Both C's)

C3372

0.22UF

C3373

0.22UF

GND_VOID=TRUE

1

R3372

470K

5% 1/20W MF 201

2

470k R's for ESD protection

on AC-coupled signals.

21

6.3V

20% X5R

0201

21

6.3V

20% X5R

0201

GND_VOID=TRUE

1

R3371

470K

5% 1/20W MF 201

2

21

6.3V

20% X5R

0201

21

6.3V

20% X5R

0201

GND_VOID=TRUE

1

R3373

470K

5% 1/20W MF 201

2

TBT_B_R2D_C_P<0>

TBT_B_R2D_C_N<0>

DP_B_LSX_ML_P<1>

DP_B_LSX_ML_N<1>

POLARITY SWAPPED

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_P<1>

IN

80 26

80 29

80 26

B

A

SYNC_MASTER=J70_NICK SYNC_DATE=10/16/2013

PAGE TITLE

Thunderbolt Connector B

DRAWING NUMBER SIZE

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

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8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

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051-00081

3.0.0

33 OF 123

29 OF 81

A

D

345678

2 1

DDC Pull-Ups

2.2k pull-ups are required by PCH

to indicate active display interface.

DP++ spec violation, should remove!

NOTE: Only DDC_DATA is sensed, so DDC_CLK

pull-ups are unstuffed.

D

C

66 39

=PP3V3_S0_DP

80 28

OUT

BI

DP_TBTPA_DDC_CLK

DP_TBTPA_DDC_DATA

R3485

100K

5%

1/20W

MF

201

R3451

DDC Crossbar

Only necessary on dual-port hosts.

On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC.

NEVER SEND AUXCH THROUGH CROSSBAR!

1

2

C3480

0.1UF

20% 10V CERM 402

13

1

VCC

U3400

2

16

ENA

1

INA+

2

INA-

14

SAI

TS3DS10224

QFN

CRITICAL

OUTA1+

OUTA1-

OUTA0+

OUTA0-

SAO

20

19

18

17

15

1

2

2.2K

1% 1/20W MF 201

R3452

1

2.2K

1% 1/20W MF 201

2

R3453

1

2.2K

1% 1/20W MF 201

2

R3454

1

2.2K

1% 1/20W MF 201

2

DP_TBTSNK1_DDC_CLK

DP_TBTSNK1_DDC_DATA

C

IN

BI

80 13

80 29

OUT

BI

DP_TBTPB_DDC_CLK

DP_TBTPB_DDC_DATA

Q3400

DMN32D2LFB4

DFN1006H4-3

SYM_VER_2

1

10

ENB

TBT_DDC_XBAR_EN

12

3

INB+

4

INB-

OUTB1+

OUTB1-

OUTB0+

OUTB0-

SBI

PAD

GND

5

THRM

21

SBO

6

7

8

9

11

DP_TBTSNK0_DDC_CLK

DP_TBTSNK0_DDC_DATA

IN

BI

80 13

SAI/SBI = 1: INA == OUTA0, INB == OUTB0

SAI/SBI = 0: INA == OUTB0, INB == OUTA0

3

D

SG

2

B

26

IN

TBT_DDC_XBAR_EN_L

B

A

PAGE TITLE

DDC Crossbar

DRAWING NUMBER SIZE

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NOTICE OF PROPRIETARY PROPERTY:

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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8 7 5 4 2 1

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SYNC_DATE=09/13/2013SYNC_MASTER=J70_TONY

051-00081

3.0.0

34 OF 123

30 OF 81

A

D

345678

2 1

D

C

AP & BT Load Switch

SWITCH

AP SLEW RATE

BT SLEW RATE

Equation

TPS22966

1185 us

0.32*Ct + 13.7

IN

1

C3541

0.001UF

10% 50V

2

X7R-CERM 0402

44

66 31

66 44 31

44 31

1

C3542

0.1UF

10% 16V

2

X7R-CERM 0402

=PP3V3_G3H_BT

BT_PWR_EN

BT_PWR_RAMP

66 31

=PP3V3_G3H_BT

=PP3V3_S4_AP

IN

AP_PWR_EN

AP_PWR_RAMP

1

C3543

0.001UF

10% 50V

2

X7R-CERM 0402

12

10

1

3

4

6

5

VIN1

ON1

CT1

VBIAS

VIN2

ON2

CT2

CRITICAL

U3500

TPS22966

DPU

GND

11

PAD

THRM

15

VOUT1

VOUT2

13

8

44

PP3V3_S4_AP_FET

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

PP3V3_G3H_BT_FET

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2000

CRITICAL

L3502

FERR-220-OHM-2.5A

0603

72 14

72

14

PCIE_AP_R2D_C_P

IN

PCIE_AP_R2D_C_N

IN

CRITICAL

L3501

FERR-220-OHM-2.5A

0603

AIRPORT

BLUETOOTH

21

PP3V3_S4_AP_FLT

31

10% 16V

0402

1

0.1UF

10%

2

PLACE_NEAR=J3500.4:7mm

16V

X7R-CERM

0402

C3502 C3503

0.1UF

X7R-CERM

C3505

C3506

0201

PLACE_NEAR=J3500.5:7mm

PP3V3_G3H_BT_FLT

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2000

1

2

0.1UF

21

CERM-X5R

0.1UF

21

CERM-X5R

C3504

10UF

20%

6.3V X5R 603

6.3V0201

6.3V

1

2

44 43

10%

72 12

72

72 14

BI

12

OUT

75 31

C3507

0.1UF

10% 16V

X7R-CERM

0402

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

AP_EVENT_L

72

PCIE_AP_R2D_N PCIE_AP_R2D_P

72

PCIE_CLK100M_AP_N

IN

PCIE_CLK100M_AP_P

IN

PCIE_AP_D2R_P PCIE_AP_D2R_N

AP_WAKE_L

31

AP_RESET_CONN_L

31

AP_CLKREQ_Q_L

31

USB_BT_MUX_N USB_BT_MUX_P

20%

6.3V X5R 603

1

2

1

C3508

10UF

2

514S0335

CRITICAL

J3500

SSD-K99

F-RT-SM1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

D

POLARITY SWAPPED

C

B

A

44 43

OUT

SMC_PME_S4_WAKE_L

CRITICAL

Q3501

SSM3K15AMFVAP

SOD

Supervisor & CLKREQ# Isolation

Delay = 130 ms +/- 20%

1

R3530

100K

1% 1/16W MF-LF 402

2

PP3V3_S4_AP_FLT

1

R3531

232K

1% 1/16W MF-LF 402

2

CRITICAL

P3V3AP_VMON

31

VDD

U3530

SLG4AP041V

TDFN

2

SENSE

VREF

+

-

=PP3V3_S4_AP

1

C3530

0.1uF

20% 10V

2

CERM 402

66 44 31

B

Wake from BT in G3H circuit

DLY

AP_RESET_CONN_L

=PP3V3_G3H_BT

66 31

1

3

D

G

1

S

75 14

2

15K

1%

1/20W

MF

201

1

2

R3501

75 14

64 43 13

SWI_USB3740_DFN_USB3740_MOJO

USB_BT_N

BI

USB_BT_P

BI

USB_BT_WAKEN

NC

PM_SLP_S5_L

IN

6

7

2

1

3

4

U3501

USB3740

DP_2

DM_2

DP_1

DM_1

OE*

S

CRITICAL

5

VDD

DFN

GND

8

DP

DM

10

9

C3500

0.1UF

10% 10V

2

X5R-CERM 0201

USB_BT_MUX_N

USB_BT_MUX_P

75 31

CRITICAL

Q3570

SSM3K15AMFVAP

SOD

35 18 13 31

PCIE_WAKE_L AP_WAKE_L

3

1

G

D

S

2

31

AP_CLKREQ_Q_L

31

1

R3570

10K

5% 1/16W MF-LF 402

2

PP3V3_S4_AP_FLT

31

1

R3532

100K

1% 1/16W MF-LF 402

2

www.qdzbwx.com

4

RESET*

7

IN

PAGE TITLE

THRM

PAD

9

GND

5

MR*

EN

OUT

(OD)

3

6 8

AIRPORT/BT

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

AP_RESET_L

AP_PWR_EN

AP_CLKREQ_L

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

15

IN

OUT

44 31

12

SYNC_DATE=10/08/2013SYNC_MASTER=J70_DINI

051-00081

3.0.0

35 OF 123

31 OF 81

A

D

8 7 5 4 2 1

36

345678

2 1

D

C

PCIE TX1

(POLARITY REVERSED)

PCIE TX0

(POLARITY REVERSED)

15

12 73

73 12

12 73

66 48 47 33

GS3 SSD

DCR =0.01-ohm

SSD:Y

PLACE_NEAR=J3700.1:10MM

CRITICAL

L3700

FERR-26-OHM-6A

=PPSSD_S4_CONN

66

SSD:Y

1

C3701

0.1UF

20% 10V

2

CERM 402

IN

SSD_SR_EN_L

SSD_RESET_L

PCIE_SSD_R2D_P<1> PCIE_SSD_R2D_N<1>

PCIE_SSD_R2D_P<0> PCIE_SSD_R2D_N<0>

C3711

C3710

C3713

C3712

SSD:Y

1 2

16V10%

GND_VOID=TRUE

PLACE_NEAR=J3700.18:5MM

SSD:Y

1 2

16V X5R-CERM 020110%

GND_VOID=TRUE

PLACE_NEAR=J3700.19:5MM

SSD:Y

1 2

GND_VOID=TRUE

PLACE_NEAR=J3700.21:5MM

SSD:Y

1 2

GND_VOID=TRUE

PLACE_NEAR=J3700.22:5MM

0603

SSD:Y

R3718

1 2

5%

MF-LF

0.1UF

X5R-CERM

0.1UF

X5R-CERM 020110% 16V

0.1UF

X5R-CERM

12

C3700

0.1UF

0

1/16W

402

0201

020116V10%

SSD:Y

20% 10V

CERM

402

PPSSD_S4_CONN_FLT

32

MIN_LINE_WIDTH=0.1000 MIN_NECK_WIDTH=0.0850 VOLTAGE=3.3V

1

2

SSD_SR_EN_L_R

SSD_BFH_L

PCIE TX3

PCIE TX2

GND_VOID=TRUE

73

SSD_R2D_C_N<1>

73

GND_VOID=TRUE

73

GND_VOID=TRUE

SSD_R2D_C_P<0> SSD_R2D_C_N<0>

GND_VOID=TRUE GND_VOID=TRUE

NC

NC NC

J3700

SSD:Y

CRITICAL

SSD-J90

F-RT-SM

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16

17 18 19 20 21 22 23 24 25 26 27 28

53 52 51

50 49 48 47

46 45 44 43 42 41 40

39 38 37 36 35 34 33

32 31 30 29

NC

SMC_OOB2_R2D_L SMC_OOB2_D2R_L

SSD_V_SEL(S3X only) SSD_PD_L(S3X only)

STORAGE_LATCH(S3X only)

SSD_EN

PCIE RX3

PCIE RX2

GND_VOID=TRUE

PCIE_SSD_D2R_N<1>SSD_R2D_C_P<1> PCIE_SSD_D2R_P<1>

GND_VOID=TRUE GND_VOID=TRUE

PCIE_SSD_D2R_N<0> PCIE_SSD_D2R_P<0>

PCIE_CLK100M_SSD_N PCIE_CLK100M_SSD_P

=PP3V3_S0_SENSE

H=2.7V,L=3.3V (SSD pulls pin low for 3.3V)

1

R3713

100K

5% 1/16W MF-LF 402

2

R3712

100K

1/16W MF-LF

SSD:Y

1 2

5%

MF-LF

R3717

IN

OUT

1

5%

402

2

PPSSD_S4_CONN_FLT

1/16W

402

0

OUT

72 12

73 12

76 44

D

32

Note:Bead Probes needed

This need to be checked for S1X LPSR

PCIE RX1

PCIE RX0

C

PCIEx2 SSD requires AC coupling caps on TX side

B

12

OUT

SSD_CLKREQ_L

54 55 56 57 58 59 60 61 62 63

64

65

66 67

68

POR:514S0457 (tall)

B

A

SYNC_MASTER=J70_DINI SYNC_DATE=10/14/2013

PAGE TITLE

SSD Connectors

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

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051-00081

3.0.0

37 OF 123

32 OF 81

A

D

HDD POWER/OOB CONNECTOR

HDD Out-of-Band Temperature Sensing

345678

2 1

D

J3830

78047-0483

M-ST-SM

1

2

3

4

CRITICAL

518S0864

66 33

76

SMC_OOB1_R2D_R_L HDD_OOB1_D2R_L

76

=PP5V_S0_SATA

C3830

66 48 47 33 32

1

10UF

20%

6.3V

2

X5R 603

=PP3V3_S0_SENSE

safety isolation

R3808

523

21

1% MF-LF

1/16W

402

L3830

0402

FERR-220-OHM

SSD:N

1

R3815

0

5% 1/16W MF-LF 402

2

1

R3814

10K

5% 1/16W MF-LF 402

2

SMC_OOB1_R2D_L

IN

=PP1V5_S0_SENSE

66

76 43

1

R3802

100K

5% 1/16W MF-LF 402

2

R3803

21

HDD_OOB1_D2R_F_L

76 76

SSD:Y CRITICAL

Node is at 1.5V

3.3K

5% 1/16W MF-LF

402

Q3801

NTR1P02L

SOT23-3-HF

Notes:

Drive active: Valid signal protocol

Drive asleep: HDD drives HDD_OOB_TEMP low

Drive disconnected: Pulled high

66 48 47 33 32

1

R3800

49.9K

1% 1/16W MF-LF 402

2

1

R3801

100K

1% 1/16W MF-LF 402

2

21

HDD_OOB1_D2R_R_L

Trip is 1.0V

HDD_OOB_1V00_REF

1

C3806

0.1UF

10% 16V

2

X7R-CERM 0402

=PP3V3_S0_SENSE

1

2

CRITICAL

U3800

VCC+

GND

5

LMV331

SC70-5

2

3

1

C3807

0.1UF

10% 16V X7R-CERM 0402

4

From drive:

0.0V to 0.3V

Low:

High:

1.2V to 2.0V

=PP3V3_S0_SENSE

1

R3805

1K

5% 1/16W MF-LF 402

2

SMC_OOB1_D2R_L

OUT

66 48 47 33 32

76 43

D

C

66 48 47 33 32

=PP5V_S0_SATA

66 33

=PP3V3_S0_SENSE

VER 3

5

G S

D

SSD:Y

1

R3816

10K

5% 1/16W MF-LF 402

2

3

4

SSD:Y

CRITICAL

Q3800

DMN5L06VK-7

SOT563

2

S D

G

1

SATA_PWR_L

3

P3V3_S0_OOB

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1500 VOLTAGE=3.3V

VER 3

2

G S

C

SSD:Y

CRITICAL

6

D

1

Q3800

DMN5L06VK-7

SOT563

B

A

J3820

CRITICAL

PSA127-0747-A01-1H

GND_VOID=TRUE

M-ST-SM

8

1

2

3

4

5

6

7

9

518S0893

HDD SIGNAL CONNECTOR

SATA_HDD_R2D_P

73

SATA_HDD_R2D_N

73

SATA_HDD_D2R_C_N

73

SATA_HDD_D2R_C_P

73

402

21

X7R25V

21

0.01UF

C3821

10%

GND_VOID=TRUE

C3822

C3823

10% 25V X7R

C3824

25V10% X7R

GND_VOID=TRUE

25V10% X7R

GND_VOID=TRUE

www.qdzbwx.com

R3821

100K

2 1

R3823

100K

2 1

B

2

D3821

ESD0P2RF-02LS

TSSLP-2-1

NOSTUFF

1

2015% MF1/20W

2011/20W5% MF

2

D3823

ESD0P2RF-02LS

TSSLP-2-1

NOSTUFF

1

2

D3822

ESD0P2RF-02LS

TSSLP-2-1

NOSTUFF

1

2

D3824

ESD0P2RF-02LS

TSSLP-2-1

NOSTUFF

1

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N

SATA_HDD_D2R_N SATA_HDD_D2R_P

OUT

IN

73 12

SYNC_DATE=08/27/2013SYNC_MASTER=J16_MLB_IG

PAGE TITLE

A

HDD Connector

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

38 OF 123

SHEET

33 OF 81

D

8 7 5 4 2 1

36

66 35 34

=PP3V3_ENET_PHY

BCM57765 ENET SR pins are internal 1.2V switching regulator. See note for SR_DISABLE below.

If disabled: Okay to float VDD, VDDP & LX pin. VFB must always connect to =PP1V2_S3_ENET_PHY.

If enabled: VDD/VDDP connect to =PP3V3_S3_ENET_PHY (add bypassing), LX connects to inductor.

Special Star routing needed on these pins. Decoupling on Pg 37.

345678

=PP1V2_ENET_PHY

396mA (1000base-T, Caesar II)

2 1

35

D

281mA (1000base-T max power, Caesar IV)

CRITICAL

L3900

FERR-600-OHM-300MA-0.85OHM

21

0402

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

CRITICAL

L3905

FERR-600-OHM-300MA-0.85OHM

21

PP3V3_ENET_PHY_BIASVDDH

0402

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

CRITICAL

L3910

FERR-600-OHM-300MA-0.85OHM

21

PP3V3_ENET_PHY_AVDDH

0402

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

C3900

0.1UF

X5R-CERM

C3905

0.1UF

X5R-CERM

R3910

4.7K

5% 1/16W MF-LF

402

10% 16V

0201

10% 16V

0201

1

2

1

2

1

2

1

2

C3910

0.1UF

10% 16V X5R-CERM 0201

VDD for Card Reader I/O

=PP3V3R1V8_CR_VDDIO

34

ENET_XTALVDDH

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

1

C3911

0.1UF

10% 16V

2

X5R-CERM 0201

ENET_SR_LX

=ENET_SR_VFB

35

Internal 1.2V Switching Regulator pins.

35

PP1V2_ENET_PHY_AVDDL

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.2V

C3921

0.1UF

10% 16V

X5R-CERM

0201

1

2

1

C3920

4.7UF

20%

6.3V

2

X5R-CERM1 402

PP1V2_ENET_PHY_PCIEPLL

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.2V

C3926

0.1UF

10% 16V

X5R-CERM

0201

1

2

1

C3925

4.7UF

20%

6.3V

2

X5R-CERM1 402

PP1V2_ENET_PHY_GPHYPLL

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1500 VOLTAGE=1.2V

C3931

0.1UF

10% 16V

X5R-CERM

0201

1

2

1

C3930

4.7UF

20%

6.3V

2

X5R-CERM1 402

CRITICAL

L3920

FERR-600-OHM-300MA-0.85OHM

21

0402

CRITICAL

L3925

FERR-600-OHM-0.5A

21

SM

CRITICAL

L3930

FERR-600-OHM-300MA-0.85OHM

21

0402

D

C

B

72 14

35

OUT

IN

OUT

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

=ENET_WAKE_L

(See note)

WAKE#

Must isolate from PCIe WAKE# if PHY

is powered-down in S3/S5. Standard

N-channel FET isolation suggested.

If PHY is always powered then alias

=ENET_WAKE_L to PCIE_WAKE_L.

PHY Non-Volatile Memory

ROM contains MAC address, PCIe config

info as well as code for Bonjour proxy.

Avoids need for EFI to program at startup.

(Required ROM size 1 Mbit)

=PP3V3_S0_ENET

66

C3950

0.1UF

21

10% 16V

X5R-CERM

0201

C3955

0.1UF

21

10% 16V

X5R-CERM

0201

C3951

0.1UF

21

10% 16V

X5R-CERM

0201

C3956

0.1UF

21

10% 16V

X5R-CERM

0201

1

R3942

1K

5% 1/16W MF-LF 402

2

72 12

36 13

R3940

4.7K

1/16W MF-LF

402

Current Limiting Resistor

IN

36

IN

12

OUT

IN

75 34

74 17

5%

35

1

C3916

0.1UF

10% 16V

2

X5R-CERM 0201

42

48

17

37

BIASVDDH

XTALVDDH

7

56

20

VDDO

62

151416

SR_VDD

SR_VDDP

OMIT_TABLE

13

SR_LX

SR_VFB

45

39

AVDDL

51

32

29

36

GPHY_PLLVDDL

PCIE_PLLVDDL

35

VDDCAVDDH

61

C3936

0.1UF

10% 16V

X5R-CERM

0201

1

2

1

C3935

10UF

20%

6.3V

2

X5R 603

LR_OUT/GPIO1 is used as a 3.3V/1.8V internal LDO out for

the card reader on-chip I/O.

Connect only to U3900 pin 20.

C

20%

6.3V

402

1

2

1

2

1

R3941

4.7K

5% 1/16W MF-LF 402

2

C3915

4.7UF

X5R-CERM1

U3900

72

BI

IN

BI

OUT

IN

OUT

75

ENET_VMAIN_PRSNT

PCIE_ENET_D2R_C_N PCIE_ENET_D2R_C_P

PCIE_ENET_R2D_P PCIE_ENET_R2D_N

PCIE_CLK100M_ENET_P PCIE_CLK100M_ENET_N

ENET_RESET_L

ENETSD_CLKREQ_L

ENET_LOW_PWR

SMB_ENET_SCL SMB_ENET_SDA

ENET_SCLK ENET_MISO ENET_MOSI ENET_CS_L

ENET_TRAFFICLED_L

ENET_XTAL_IN ENET_XTAL_OUT

ENET_RDAC

1

R3965

1.24K

1% 1/16W MF-LF 402

2

NC

58

VMAIN_PRSNT

27

PCIE_TXD_N

28

PCIE_TXD_P

33

PCIE_RXD_P

34

PCIE_RXD_N

31

PCIE_REFCLK_P

30

PCIE_REFCLK_N

11

PERST*

12

CLKREQ*

3

WAKE*

4

LOW_PWR

6

SMB_CLK

10

SMB_DATA

66

SCLK_SPD1000LED*

64

SI/EEDATA

65

SO_LINKLED*

63

CS*/EECLK

2

SPD100LED*/SERIAL_DO

67

TRAFFICLED*/SERIAL_DI

18

XTALI

19

XTALO

38

RDAC

(IPD-ENET)

(IPD)

(OD)

(IPD)

(IPD-ENETM)

BCM57766C0KMLG

QFN-8X8

GPIO_0/CR_ACT_LED*

(IPD)

NOTE: "IPx" == Programmable pull-up/down

(IPx-ENET)

SD_DETECT can only be used active low due to errata.

(IPU-ENET)

(IPU)

(OD)

(IPU-ENET)

(NO IPU OR IPD-ENET)

THRM_PAD

69

CR_LED*/CR_BUS_PWR

GPIO_1/LR_OUT

GPIO_2/MEDIA_SENSE

(IPU-ENET)

SR_DISABLE

ENET 1.2V SR IS ENABLED IF FLOATING.

TRD0_P

TRD0_N

TRD1_P

TRD1_N

TRD2_P

TRD2_N

TRD3_P

TRD3_N

SD_DETECT

CR_CMD

CR_CLK

CR_DATA0 CR_DATA1 CR_DATA2 CR_DATA3 CR_DATA4 CR_DATA5 CR_DATA6 CR_DATA7

MS_INS*

CR_WP*

40 41 44 43 46 47 50 49

5

NC

8 9

1

o

26

21

25 24 23 22 52 53 54 55

59

NC

60 57 68

ENET_CR Signals

BCM requests SD CR[0:7], CMD, CLK termination.

ENET_SR_DISABLE

ENETCONN_MDI_P<0> ENETCONN_MDI_N<0> ENETCONN_MDI_P<1> ENETCONN_MDI_N<1> ENETCONN_MDI_P<2> ENETCONN_MDI_N<2> ENETCONN_MDI_P<3> ENETCONN_MDI_N<3>

75

ENET_SD_CMD

75

ENET_SD_CLK

75

ENET_CR_DATA<0>

75

ENET_CR_DATA<1> ENET_CR_DATA<2>

75

ENET_CR_DATA<3>

75

ENET_CR_DATA<4> ENET_CR_DATA<5>

75

ENET_CR_DATA<6>

75

ENET_CR_DATA<7>

No MS (Memory Stick) Insert feature needed. Control signal to light LED or control SD bus power.

ENET_CR_PWREN

ENET_SR_DISABLE

(See note)

BI

75 35

R3961 R3979 R3971

R3972 R3973 R3974 R3975 R3976 R3977 R3978

36

OUT

R3981

PP3V3R1V8_ENET_LR_OUT

MIN_LINE_WIDTH=0.3000 MIN_NECK_WIDTH=0.1500 VOLTAGE=3.3V

MAKE_BASE=TRUE

33

33 33 33 33 33 33

1K

5%

PLACEMENT_NOTE=PLACE R3961 NEAR U3900

PLACEMENT_NOTE=PLACE R3979 NEAR U3900

21

5%

1/20W

21

21 21 21 21 21 21 21 21

21

1/20W5%

1/20W5% MF

1/20W MF

5% 201

1/20W5% MF

1/20W MF

1/20W5% MF

5% 1/20W MF

402

1/16W

MF-LF

201MF

MF

MF5%331/20W 201

201

2015%

201

=PP3V3R1V8_CR_VDDIO

1

C3980

4.7UF

20%

6.3V

2

X5R-CERM1 402

ENET_MEDIA_SENSE

ENET_SD_DETECT_L

SDCONN_CMD

SDCONN_CLK

SDCONN_DATA<0> SDCONN_DATA<1> SDCONN_DATA<2> SDCONN_DATA<3> SDCONN_DATA<4> SDCONN_DATA<5> SDCONN_DATA<6> SDCONN_DATA<7>

SDCONN_WP

ENET supports both active-levels for WP.

1

C3981

0.1UF

10% 16V

2

X5R-CERM 0201

OUT

IN

OUT

BI

36

IN

75 15

75 36

1

C3982

0.1UF

10% 16V

2

X5R-CERM 0201

34

B

A

66 35 34

75 34

=PP3V3_ENET_PHY

IN

ENET_SCLK

ENET_CS_L

NOTE: Pull-down on SO plus internal pull-ups on

other 3 SPI pins configures ENET for the

Atmel AT45DB011D (1Mbit) ROM. If a different

ROM is used then the straps must change.

NOTE: ENETM requires SI pull-down instead of SO.

4

5

3

AT45DB011D

OMIT_TABLE

SCK

CS*

WP*

RESET*

6

VCC

U3990

SOIC-8S1

GND

7

SI

SO

If ENET switching regulator is

used, this pin should have

1

C3990

0.1UF

10% 16V

2

X5R-CERM 0201

12

8

ENET_MOSI

ENET_MISO

OUT

IN

75 34

a 1K pull-down to GND

NOSTUFF

1

R3990

4.7K

5% 1/16W MF-LF 402

2

1

R3997

4.7K

5% 1/16W MF-LF 402

2

www.qdzbwx.com

PLACEMENT_NOTE=PLACE R3971 NEAR U3900

PLACEMENT_NOTE=PLACE R3972 NEAR U3900

PLACEMENT_NOTE=PLACE R3973 NEAR U3900

PLACEMENT_NOTE=PLACE R3974 NEAR U3900

PLACEMENT_NOTE=PLACE R3975 NEAR U3900

PLACEMENT_NOTE=PLACE R3976 NEAR U3900

PLACEMENT_NOTE=PLACE R3977 NEAR U3900

PLACEMENT_NOTE=PLACE R3978 NEAR U3900

SYNC_MASTER=J70_GAREN

PAGE TITLE

ETHERNET PHY (CAESAR IV)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=09/19/2013

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

39 OF 123

SHEET

34 OF 81

A

8 7 5 4 2 1

36

345678

3.3V ENET FET

2 1

D

66 35 34

=PP3V3_ENET_PHY

Power decoupling

CAESAR IV 1.2V INT.VR CMPTS

4.7UH-0.8A

ENET_SR_LX

=PP1V2_ENET_PHY

1

C4010

4.7UF

20%

6.3V

2

X5R-CERM1 402

1

C4011

0.1UF

10% 16V

2

X7R-CERM 0402

35

PP1V2_ENET_INTREG

MAKE_BASE=TRUE

34

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000 VOLTAGE=1.2V

SWITCH_NODE=TRUE DIDT=TRUE

CRITICAL

L4010

PCAA031B-SM

=ENET_SR_VFB

21

C4012

10UF

20%

6.3V X5R 603

34

ENET Enable Generation

ENET is enabled when in S0 or when (S4 & WOL_EN) is present

CRITICAL

Q4020

CAESAR IV ACTIVITY LED

NTR4101P

SOT-23-HF

66 35 34

S D

2

PP1V2_ENET_INTREG

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

1

C4013

0.1UF

2

X7R-CERM

10% 16V

0402

1

Feedback loop

2

VOLTAGE=1.2V

14

65 64 44 43 13

IN

35

WOL_EN

PM_SLP_S3_L

CRITICAL

Q4021

DMN5L06VK-7

SOT563

VER 3

5

G S

1

C4020

0.033UF

10% 16V

2

X5R 402

P3V3ENET_SS

SOT563

G

1

C4021

10K

5% 1/16W MF-LF

402

6

D

1

2

R4021

100K

1/16W MF-LF

DMN5L06VK-7

21

5%

402

CRITICAL

Q4021

R4020

PM_EN_ENET_L

3

D

4

VER 3

2

G S

3

0.01UF

2 1

10% 50V

X7R-CERM

0402

PP3V3_ENET_FET=PP3V3_S4_FET_ENET

66 66

ENET_TRAFFICLED_L

34

=PP3V3_ENET_PHY

DEVELOPMENT

1

R4050

330

5% 1/16W MF-LF 402

2

ENET_ACT

A

DEVELOPMENT

LED4050

GRN-6MCD-0.03A

0805

K

D

C

B

CAESAR IV WAKE# ISOLATION

=PP3V3_ENET_PHY

CRITICAL

Q4070

1

SSM3K15AMFVAP

G

31 18 13 34

OUT IN

PCIE_WAKE_L ENET_WAKE_L

75 34

ENETCONN_MDI_P<1>

BI

ENETCONN_MDI_N<1>

BI

3

D

SOD

S

2

1

R4070

10K

5% 1/16W MF-LF 402

2

MAKE_BASE=TRUE

157S0058

CRITICAL

T4000

1

2

3

SM

TX

75

12

11

10

ENETCONN_MCT1

LFE8904CF

75

9

ENETCONN_MCT3

8

75 34

ENETCONN_MDI_P<3>

BI

4

5

34

66 35

=ENET_WAKE_L

ENETCONN_MDI_T_P<1>

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_P<3>

C

514-0822

CRITICAL

J4000

BI

75 35

BI

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_P<3>

ENETCONN_MDI_T_N<1>

ENETCONN_MDI_T_N<2>

ENETCONN_MDI_T_P<2>

ENETCONN_MDI_T_P<1>

ENETCONN_MDI_T_N<0>

ENETCONN_MDI_T_P<0>

K70-K72

F-ANG-TH

ENET_MDI

8 7 6 5 4 3 2 1

ENET_MDI_TRAN3ENET_MDI_TRAN3+ ENET_MDI_TRAN1ENET_MDI_TRAN2ENET_MDI_TRAN2+

ENET_MDI_TRAN1+

ENET_MDI_TRAN0-

ENET_MDI_TRAN0+

B

75 34

ENETCONN_MDI_N<3>

BI

ENETCONN_MDI_N<2>

BI

ENETCONN_MDI_P<2>

BI

ENETCONN_MDI_N<0>

BI

ENETCONN_MDI_P<0>

BI

76

RX

CRITICAL

T4010

1

2

3

SM

TX

75

12

11

10

ENETCONN_MCT2

ENETCONN_MDI_T_N<3>

ENETCONN_MDI_T_N<2>

ENETCONN_MDI_T_P<2>

BI

75 35

10 11 12 13 14

9

SHIELD

PINS

LFE8904CF

4

5

RX

75

9

ENETCONN_MCT0

8

76

ENETCONN_MDI_T_N<0>

ENETCONN_MDI_T_P<0>

BI

75 35

A

ENETCONN_TCT

1

C4001

0.1UF

20% 10V

2

CERM 402

1

C4002

0.1UF

20% 10V

2

CERM 402

1

C4003

0.1UF

20% 10V

2

CERM 402

1

C4004

0.1UF

20% 10V

2

CERM 402

R4000

75

5% 1/16W MF-LF 402

2

75

ENETCONN_MCT_BS

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000

NOSTUFF

1

C4000

1000PF

10% 2KV

2

CERM 1206

8 7 5 4 2 1

1

R4001

75

5% 1/16W MF-LF 402

2

1

R4002

75

5% 1/16W MF-LF 402

2

1

R4003

75

5% 1/16W MF-LF 402

2

www.qdzbwx.com

SYNC_MASTER=J16_MLB_IG SYNC_DATE=05/01/2013

PAGE TITLE

Ethernet Support & Connector

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

36

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

40 OF 123

35 OF 81

A

D

SD CARD 3.3V OVERCURRENT PROTECTION CHIP

345678

2 1

D

34

=PP3V3_S0_SDCARD

66 36

IN

ENET_CR_PWREN

C4100

22UF

20%

6.3V

X5R-CERM1

0603

353S2548

U4100

=PP3V3_S0_SW_SD_PWR

36

D

TPS2553

6

IN

EN

10% 16V

0402

1

2

1

C4101

0.1UF

2

X7R-CERM

SON

CRITICAL

GND

5

THRML

PAD

7

OUT

ILIM

FAULT*

1

2

SDCONN_ILIM

34

SDCONN_OC_L

SDCONN_ILIM_R

15

1

R4118

13K

1% 1/16W MF-LF 402

2

1

R4119

13K

1% 1/16W MF-LF 402

2

1

C4102

10UF

20%

6.3V

2

X5R 603

1

C4103

0.1UF

10% 16V

2

X7R-CERM 0402

1

R4100

47K

5% 1/16W MF-LF 402

2

PP3V3_S0_SW_SD_PWR

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 VOLTAGE=3.3V

J16:516-0249 / J17:512-0038

C

B

=PP3V3_S0_SDCARD

66 36

1

EMC

Bridge cap for SDCONN_CLK in layout

2

=PP5V_S4_SDCARD

66

C4105

0.1UF

10% 16V

X7R-CERM

0402

SDCONN DETECT DEBOUNCE. ENET_RESET AND DETECT-CHANGED PCH GPIO PULSE GENERATION.

=PP3V3_S4_SDCARD

66

1UF

10% 10V X5R

402-1

1

2

10

CRITICAL

VDD

C4110

75 34

34

BI

OUT

BI

OUT

SDCONN_DATA<3>

SDCONN_CMD

SDCONN_CLK

IN

SDCONN_DATA<0>

SDCONN_DATA<1>

SDCONN_DATA<2>

SDCONN_DATA<4>

SDCONN_DATA<5>

SDCONN_DATA<6>

SDCONN_DATA<7>

SDCONN_DETECT_L

36

SDCONN_WP

CRITICAL

NOSTUFF

1

C4171

22PF

5%

50V

2

CER-C0G

0402

=PP3V3_S0_SW_SD_PWR

36

L4102

47NH-1.3OHM

21

0402

EMC

1

C4172

100PF

5% 25V

2

C0G 0201

SDCONN_CLK_R

75

NOSTUFF

1

C4170

15PF

5% 50V

2

CERM 0402

SD CARD CONNECTOR

J4100

SD-CARD-D7

F-ANG-TH

CRITICAL

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15

16 17 18 19 20 21 22 23 24 25 26 27

CD/DAT3 CMD VSS VDD CLK VSS DAT0 DAT1 DAT2 DAT4 DAT5 DAT6 DAT7 CRD_DETECT_SWITCH WRITE_PROTECT_SWITCH

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

C

SD switch is normally connected (i.e. gnd)

B

A

15

ENET_SD_RESET_L

IN

NOSTUFF

R4110

10K

5% 1/16W MF-LF

402

U4111

SLG4AP026V

TDFN

LOW_PWR

34 13

10K

5% 1/16W MF-LF

402

36

FROM SD CONN ->

1

2

1

2

R4115

ENET_LOW_PWR

IN

SDCONN_DETECT_L

SD_DETECT_LVL

2

3

7

1

RST_IN*

DET_IN

(IPU)

DET_LVL

XOR

GND

5

RST

LOGIC

DLY

When ENET_LOW_PWR deasserts, RST_OUT# deasserts for >80ms, then asserts for 10ms regradless of RST_IN# state. Otherwise RST_OUT# follows RST_IN#

RST_OUT*

DET_CH_EN*

XOR

DET_CHNGD*

DET_OUT

THRM

PAD

11

(OD)

4

SLG_ENET_RESET_R_L

6

9

8

SDCONN_STATE_CHANGE_L

DLY block is 20ms nominal

ENET_SD_DETECT_L

R4114

0

5% 1/16W MF-LF

402

16

OUT

75 34

21

ENET_RESET_L

-> TO PCH GPIO

-> TO ENET CHIP

OUT

34

PAGE TITLE

SYNC_DATE=09/23/2013SYNC_MASTER=J70_GAREN

A

SD READER CONNECTOR

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

41 OF 123

36 OF 81

D

USB CAMERA CONTROLLER

345678

2 1

Camera/ALS/DMIC connector

J4200

20455-A20E-32

APN:518S0879

F-RT-SM

21

22

25

D

C

66 38 37

38 37

75 37

=PP3V3_S0_CAMERA

PP1V2_S0_CAMERA

SMIA_DATA_P

SMIA_DATA_N

SMIA_CLK_P

SMIA_CLK_N

1

C4214

0.1UF

10%

6.3V

2

CERM-X5R 0201

L4220

FERR-600-OHM-300MA-0.85OHM

0402

CAM_AGND

37

1

C4215

0.1UF

10%

6.3V

2

CERM-X5R 0201

21

PP3V3_S0_CAMFILT

1

2

1

C4217

0.1UF

10%

6.3V

2

CERM-X5R 0201

GPIO3, EXT/IN FIRMWARE BOOT SEL

'1'= EXT FW

'0'= INT FW

GPIO3 CAN BE CONFIGED AS

GENERAL GPIO AFTER POWER ON

TP_CAM_GPIO1

38

CAM_EXT_BOOT

IN

C4216

1.0UF

20%

6.3V X5R 0201-1

NC

1

C4213

0.1UF

10%

6.3V

2

CERM-X5R 0201

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000 VOLTAGE=3.3V

1

C4218

0.1UF

10%

6.3V

2

CERM-X5R 0201

48

GPIO0

47

GPIO1

46

GPIO3

12

GPIO9

28

MRXDATAINP

27

MRXDATAINN

30

MRXCLKINP

29

MRXCLKINN

1

2

C4220

0.1UF

10%

6.3V CERM-X5R 0201

34

16

DVDD3

DVDD4

32

43

DVDD6

23

MAVDD33

USB_VDDA0

CRITICAL

U4200

VC0359

FQFN

337S4151

40

7

OVDD1

NC

45

NC

OVDD2

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000 VOLTAGE=1.2V

PP1V2_S0_CAMFILT PP1V2_S0_F_R

19

26

VDDA_PLL

USB_VDDL0

CS_PWDB

CS_CLK

CS_RSTB

CS_SCK CS_SDA

CLKIN

CLKOUT

TEST

1

C4221

1.0UF

20%

6.3V

2

X5R 0201-1

37 38 36 41 42

9

CAM_XTAL_IN

10

CAM_XTAL_OUT

11

CAM_TEST

1

C4222

1.0UF

20%

6.3V

2

X5R 0201-1

1/20W

1

C4223

0.1UF

10%

6.3V

2

CERM-X5R 0201

TP_CS_PWD_L

TP_ISM_CLK

TP_ISM_RST_L

1

C4224

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C4228

0.1UF

10%

6.3V

2

CERM-X5R 0201

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000

R4220

10

VOLTAGE=1.2V

21

MF5%

201

CAM_PLLGND

37

PP1V8_S0_CAMERA

PP1V2_S0_CAMERA

L4210

21

0402

FERR-1000-OHM

37 38

1

R4218

1K

1% 1/20W MF 201

2

I2C_CAMSENSOR_SCL

I2C_CAMSENSOR_SDA

38 37

1

R4219

1K

1% 1/20W MF 201

2

75 37

=PP3V3_S0_AUDIO

66 50

=PP5V_S0_CAMERA

66 38

PP1V8_S0_CAMERA

38 37

=PP3V3_S0_ALS

66

SMIA_DATA_N

75 37

SMIA_DATA_P

75 37

SMIA_CLK_N

75 37

SMIA_CLK_P

75 37

L4200

FERR-1000-OHM

21

PP3V3_DMIC_CONN

0402

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.4000 VOLTAGE=3.3V

L4202

FERR-1000-OHM

21

0402

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000 VOLTAGE=5V

L4204

FERR-1000-OHM

21

0402

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000 VOLTAGE=1.8V

L4206

FERR-1000-OHM

21

0402

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000 VOLTAGE=3.3V

PP5V_S0_CAMERA_F

1

C4262

1UF

10% 16V

2

X5R 402

PP1V8_S0_CAMERA_F

1

C4264

1UF

10% 16V

2

X5R 402

PP3V3_S0_ALS_F

1

C4266

1UF

10% 16V

2

X5R 402

37

1

2

46

C4265

1UF

10% 16V X5R 402

BI

IN

I2C_CAMSENSOR_SDA

75 37

I2C_CAMSENSOR_SCL

75 37

PP5V_S0_CAMERA_F

37

SMB_ALS_F_SDA

37

SMB_ALS_F_SCL

37

PP1V8_S0_CAMERA_F

37

PP3V3_S0_ALS_F

37

IN

DMIC_SDA3

DMIC_CLK3

51

OUT

R4267

=SMB_ALS_SDA

5%

1/20W

MF

0201

21

SMB_ALS_F_SDA

1

C4267

150PF

5% 50V

2

CERM 402

NOSTUFF

0

R4268

0

5%

MF

0201

21

=SMB_ALS_SCL

1/20W

Use 100 ohms and 150pF for 10MHz filter

SMB_ALS_F_SCL

1

C4268

150PF

5% 50V

2

CERM 402

NOSTUFF

37

10

11

12

13

14

15

16

17

18

19

20

23

24

1

2

3

4

5

6

7

8

9

26

D

C

B

75 14

1

R4204

24K

1% 1/20W MF 201

2

PLACE_NEAR=U4200:5mm

CAM_AGND

37

BI

MIPI_RESISTOR

75 37

USB_CAMERA_P

USB_CAMERA_N

CAM_SF_CLK

CAM_SF_CS_L

CAM_SF_DIN

CAM_SF_DOUT

CAM_SF_WP_L

XW4202

SHORT-0201

20

USB_PADP

21

USB_PADM

33

MIPI_RESISTOR

6

SF_CLK

3

SF_CS*

5

SF_DIN

4

SF_DOUT

2

SF_WP*

21

STITCH THERMAL PAD TO INNER GROUND

DVSS4

44

35

37

CAM_AGND

DVSS6

MAVSS

31

OVSS1

8

OVSS2

39

USB_VSSA0

22

USB_VSDL0

18

VSSA_PLL

25

2

XW4203

1

USB_VRES

LED_FIXED

RST*

UART1_RX

UART1_TX

PAD

DVSS3

THRM

49

15

CAM_PLLGND

SHORT-0201

24

17

1

14 13

NC

CAM_PROC_RESET_L

CAM_RX

CAM_TX

37

PLACE_NEAR=U4200:5mm

1

R4213

8.2K

1%

38

IN

1

R4210

10K

1% 1/20W MF 201

2

1/20W MF 201

2

PLACE_NEAR=U4200:5mm

UART1_TX is strap for selection

of pos/neg edge sampling of

SPI clock during power-on.

'1' = POSITIVE EDGE

'0' = NEGATIVE EDGE

1

C4226

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

R4216

47

1% 1/20W MF 201

2

=PP3V3_S0_CAMERA

2

R4211

10K

201 MF

1

1/20W 1%

66 38 37

PLACE_NEAR=U4200:5mm

CAM_SF_CLK

75 37

66 38 37

PLACE_NEAR=U4200:5mm

CAM_SF_CS_L

75 37

CAM_SF_WP_L

75 37

CAM_SF_HOLD_L

=PP3V3_S0_CAMERACAM_USB_VRES

R4203

1%

1/20W

R4202

1%

R4207

10K

1% 1/20W MF 201

33

21

MF

201

51

21

MF

2011/20W

1

C4219

2

1

2

R4206

10K

1% 1/20W MF 201

1

75

CAM_SF_CLK_R

1

R4208

4.7K

5% 1/20W MF 201

2

6

SCLK

8

VCC

U4202

1MBIT-104MHZ

USON

SI/SIO0

5

75

MX25L1006EZUI-10G

CAM_SF_CS_R_L

1

CS*

3

WP*

7

HOLD*

335S0852

CRITICAL OMIT_TABLE

GND

4

SO/SIO1

THRM

PAD

9

2

75

CAM_SF_DIN_R CAM_SF_DIN

0.1UF

10%

6.3V

2

CERM-X5R 0201

PLACE_NEAR=U4200:5mm

33

2 1

201 1/20W

R4205

1%MF

R4209

33

21

1%

1/20W

MF

201

PLACE_NEAR=U4202:5mm

B

CAM_SF_DOUTCAM_SF_DOUT_R

75 37

SERIAL FLASH

CRYSTAL

A

R4215

CAM_XTAL_OUT

37

R4214

1M

1% 1/20W MF 201

CAM_XTAL_IN

37

21

1%

1/20W

MF

2

201

CRITICAL

Y4200

1

3.2X2.5MM-SM

12.000MHZ-30PPM-10PF-85C

CAM_XTAL_OUT_R

31

42

47

www.qdzbwx.com

8 7 5 4 2 1

36

C4227

18PF

21

5% 25V C0G

0201

C4225

18PF

21

5% 25V C0G

0201

SYNC_MASTER=J70_GAREN

PAGE TITLE

Camera Controller

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=02/05/2014

051-00081

D

3.0.0

42 OF 123

37 OF 81

A

345678

2 1

D

Camera Processor Reset

PCH_CAM_RESET_L

15

=PP3V3_S0_CAMERA

2

1

R4306

10K

5% 1/20W MF 201

2

CAM_P1V2_RST_HOLDOFF_L

6

Q4310

MMDT3904-X-G

SOT-363-LF

1

PP1V2_S0_CAMERA

38 37

66 38 37

1

R4304

1K

5% 1/20W MF 201

2

CAM_P1V2_RST_HOLDOFF

R4301

0

5% 1/16W MF-LF

402

D

66 38 37

=PP3V3_S0_CAMERA

1.8V S0 and 1.2V S0 Load Switch

1

R4300

51K

5% 1/20W MF 201

2

21

5

CAM_PROC_RESET_L

3

Q4310

MMDT3904-X-G

SOT-363-LF

4

1

C4301

2.2UF

20% 10V

2

X5R-CERM 402

OUT

37

=PP5V_S0_CAMERA

37 66

1

C4321

0.001UF

10% 50V

2

CERM 402

1

C4320

0.1UF

10% 16V

2

X7R-CERM 0402

66 38 37

IN OUT

64 63

IN

38 37

=PP1V8_S3_CAMERA_FET

PM_PGOOD_FET_P3V3_S0

FET_RAMP_P1V8_S0

=PP1V2_S3_CAMERA_FET

IN

PP1V8_S0_CAMERA

FET_RAMP_P1V2_S0

1

C4322

0.0022UF

10% 50V

2

CERM 402

Enable 1.8V camera rail when 3.3V S0 rail is on Enable 1.2V camera rail when 1.8V S0 rail is on

1

3

12

4

6

5

10

POWER SEQUENCE

3.3V => 1.8V => 1.2V

U4320

TPS22968

VIN1 VOUT1

ON1

CT1

VBIAS

VIN2

ON2

CT2

DPU

CRITICAL

THRM

GND

15

11

VOUT2

PAD

13

PP1V8_S0_CAMERA

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000 VOLTAGE=1.8V

8

PP1V2_S0_CAMERA

MIN_NECK_WIDTH=0.1500 MIN_LINE_WIDTH=0.6000 VOLTAGE=1.2V

OUTIN

38 37 66

C

Camera Processor ExtBoot Cntl

=PP3V3_S0_CAMERA

R4311

0

5% 1/16W MF-LF

402

1

R4310

10K

5% 1/20W MF 201

2

21

CAM_EXT_BOOT

OUT

37

15

PCH_CAM_EXT_BOOT

IN

66 38 37

Capacitor Values Found Using

Slew Rate(us/V) = 0.32*CT(pF) + 13.7

C

Rise Times:

1.8V S0 -- 1000 pF -- 600 us

1.2V S0 -- 2200 pF -- 861 us

B

A

PAGE TITLE

Camera Controller Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=10/24/2013SYNC_MASTER=J70_GAREN

051-00081

3.0.0

43 OF 123

38 OF 81

A

D

345678

2 1

Backlight Control

Delay applies only on a L->H transition on VIDEO_ON. This guarantees video is valid before the backlight is enabled.

On a H->L transition, output follows with standard logic propagation delay. This ensures the backlight is off immediately after loss of video

=PP3V3_S0_DP

66 30

D

C

=PP12V_S0_LCD

66

40

2AMP-32V

1 2

OUT

F4400

MIN_LINE_WIDTH=0.4000

0603

DP_INTPNL_HPD

MIN_NECK_WIDTH=0.1000

PP12V_LCD_F

R4400

1 2

L4400

FERR-120-OHM-3A

1 2

0603

Display TCon Slave

1K

5% 1/16W MF-LF

402

80 74 51

80 40

62

OUT

BI

IN

OUT

PP12V_LCD

VOLTAGE=12VVOLTAGE=12V MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000

PANEL_PGOOD

39

SMB_DP_TCON_SLA_SDA

39

SMB_DP_TCON_SLA_SCL

39

DP_INT_SPDIF_AUDIO

DP_INTPNL_HPD_R

DP_INTPNL_AUX_N

DP_INTPNL_AUX_P

DP_INTPNL_ML_P<0>

DP_INTPNL_ML_N<0>

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_N<1>

VIDEO_ON

39

BKLT_VSYNC

Internal DP Connector

518S0829

CRITICAL

J4400

1

C4420

10UF

10% 16V

2

X5R-CERM 0805

1

C4401

0.001UF

20%

50V

2

CERM 0402

20525-130E-01

NC

F-RT-SM

31

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

64 63

66 64 63 59

IN

PM_PGOOD_FET_P12V_S0

39

=PP3V3_S4_PWRCTL

1

R4451

100K

5% 1/20W MF 201

2

1

C4410

0.1UF

10%

16V

2

X7R-CERM 0402

1

C4450

0.1UF

10%

6.3V

2

CERM-X5R 0201

2 4

5

U4450

74AUP2G14GM

SOT886

1

2

U4410

74LVC1G125DBVG4

5

SOT23-5

3 1

BUF_OE_L

1

C4451

10UF

20%

6.3V

2

CERM-X5R 0402-1

D4450

SOD-523

6

A K

VIDEO_ON_L_DLY

BAT54XV2T1

R4450

41.2K

1/20W

VIDEO_ON_L

To Diag LED

1%

MF

201

21

3

OUT

R4411

100

PANEL_PGOOD_R PANEL_PGOOD

1

R4410

10K

5% 1/16W MF-LF 402

2

1 2

5% 1/16W MF-LF

402

3

39

5

U4450

74AUP2G14GM

SOT886

4

2

BKLT_ENVIDEO_ON

To BLC

OUT

62

C

B

33

34

35

36

37

38

39

40

41

32

SMBus Isolation

I2C

66 46 39

=PP3V3_S0_SMBUS_SMC_1

VER 3

2

G S

B

66 46 39

SMB_DP_TCON_SLA_SDA

SMBUS1:ISOL

6

D

CRITICAL

1

Q4411

DMN5L06VK-7

SOT563

SMBUS1:RES

1

R4412

0

5% 1/20W MF 0201

2

39

=PP3V3_S0_SMBUS_SMC_1

VER 3

5

G S

SMB_DP_TCON_SLA_SCL

SMBUS1:ISOL

3

D

CRITICAL

4

Q4411

DMN5L06VK-7

SOT563

SMBUS1:RES

1

R4413

0

5% 1/20W MF 0201

2

39

A

www.qdzbwx.com

46

BI

SMB_DP_MLB_MSR_SDA

46

SMB_DP_MLB_MSR_SCL

IN

PAGE TITLE

SYNC_DATE=08/27/2013SYNC_MASTER=J16_MLB_IG

A

Internal DP Support

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

44 OF 123

SHEET

39 OF 81

D

8 7 5 4 2 1

36

345678

2 1

D

C

26

D

NC aliases

DP_INT_HPD

40 13

DP_TBTSRC_ML_P<2>

IN

DP_TBTSRC_ML_N<2>

IN

DP_TBTSRC_ML_P<3>

IN

DP_TBTSRC_ML_N<3>

IN

5

DP_INT_ML_P<2>

IN

DP_INT_ML_N<2>

IN

DP_INT_ML_P<3>

IN

DP_INT_ML_N<3>

IN

NC_DP_TBTSRC_ML_P<2>

NO_TEST=1

MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_N<2>

NO_TEST=1

MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_P<3>

NO_TEST=1

MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_N<3>

NO_TEST=1

MAKE_BASE=TRUE

NC_DP_INT_ML_P<2>

NO_TEST=1

MAKE_BASE=TRUE

NC_DP_INT_ML_N<2>

NO_TEST=1

MAKE_BASE=TRUE

NC_DP_INT_ML_P<3>

NO_TEST=1

MAKE_BASE=TRUE

NC_DP_INT_ML_N<3>

NO_TEST=1

MAKE_BASE=TRUE

1

R4500

100K

5% 1/20W MF 201

2

80 5

40 13

80 26

50 13

26

DP_INT_ML_P<0>

IN

DP_INT_ML_N<0>

IN

DP_INT_ML_P<1>

IN

DP_INT_ML_N<1>

IN

DP_INT_AUX_P

BI

DP_INT_AUX_N

BI

DP_INT_HPD

OUT

DP_TBTSRC_ML_P<0>

80 26

DP_TBTSRC_ML_N<0>

80 26

DP_TBTSRC_ML_P<1>

80 26

DP_TBTSRC_ML_N<1>

80 26

DP_TBTSRC_AUX_P

BI

DP_TBTSRC_AUX_N

BI

DP_TBTSRC_HPD

OUT

PD is on the CR page

DP_TBT_SEL

IN

31 30

27 26

19 18

17

25 24

23 22

15 14

13

10 32 11

D0+A D0-A

D1+A D1-A

AUX+A AUX-A

HPD_A

D0+B D0-B

D1+B D1-B

AUX+B AUX-B

HPD_B

SEL AUX_SEL HPD_SEL

292016129

VDD

U4500

PI3VEDP212

TQFN

CRITICAL

3

D0+

D0-

D1+

D1-

AUX+

AUX-

HPD

1

80

2

80

4

80

5

80

6 7

8

1

C4568

0.1UF

10%

6.3V

2

CERM-X5R 0201

DP_INTPNL_ML_C_P<0>

DP_INTPNL_ML_C_N<0>

DP_INTPNL_ML_C_P<1>

DP_INTPNL_ML_C_N<1>

DP_INTPNL_AUX_C_P

DP_INTPNL_AUX_C_N

DP_INTPNL_HPD

1

C4569

0.1UF

10%

6.3V

2

CERM-X5R 0201

=PP3V3_S0_INTDPMUX

C4500

0.1UF

C4501

0.1UF

C4502

0.1UF

C4503

0.1UF

C4504

0.1UF

C4505

0.1UF

39

IN

21

0201

CERM-X5R

21

CERM-X5R 6.3V

21

0201 10%

CERM-X5R 6.3V

21

CERM-X5R 6.3V

21

0201 10%

10%

10%0201

66 40

6.3V

6.3VCERM-X5R

DP_INTPNL_ML_P<0>

DP_INTPNL_ML_N<0>

DP_INTPNL_ML_P<1>

DP_INTPNL_ML_N<1>

1

R4502

100K

5% 1/20W MF 201

2

DP_INTPNL_AUX_P

DP_INTPNL_AUX_N

1

R4503

100K

5% 1/20W MF 201

2

OUT

BI

80 39

=PP3V3_S0_INTDPMUX

C

66 40

B

THMPAD GND

28

33

21

B

A

PAGE TITLE

Internal DP MUXing

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

.

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/05/2013SYNC_MASTER=J70_TONY

051-00081

3.0.0

45 OF 123

40 OF 81

A

D

C

=PP5V_S4_USB

42 66

C4601

0.1UF

20% 10V

CERM

402

345678

2 1

L4601

FERR-120-OHM-3A

PP5V_S4_EXTA_ILIM

VOLTAGE=5V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

C4605

0.01UF

X7R-CERM

20% 16V

0402

1

2

=PP3V3_G3H_SMC_USBMUX

66

1

C4607

0.1UF

20% 10V

2

CERM 402

0603

C4606

0.1UF

9

VCC

43 44

14 75

CRITICAL

1

2

1

C4602

330UF-25MOHM

20%

6.3V

2

TANT CASE-D2E

CRITICAL

SMC_DEBUGPRT_TX_L

IN

OUT

SMC_DEBUGPRT_RX_L

CKPLUS_WAIVE=ndifpr_badterm

USB_EXTA_N

BI

USB_EXTA_P

BI

CKPLUS_WAIVE=pdifpr_badterm

5

M+

4

M-

CRITICAL

U4610

PI3USB102EZLE

7

D+

6

D-

8

OE* SEL

TQFN

GND

3

Y+

Y-

21

1

20% 10V

2

CERM

402

CKPLUS_WAIVE=ndifpr_badterm

1

2

CKPLUS_WAIVE=pdifpr_badterm

10

2

R4605

100K

5%

1/16W

MF-LF

402

75

VOLTAGE=5V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_P

SMC_DEBUGPRT_EN_L

PIN SWAPPED

U4600

TPS2561DR

SON

2

IN_0

3

IN_1

OUT1

OUT2

9 8

PP5V_S4_EXTA_F

IN

14 75

USB3_EXTA_R2D_CF_P

IN

L4602

120-OHM-90MA

DLP0NS

SYM_VER-1

4 3

CRITICAL

43

21

75

14

14 75

OUT

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

C4608

10% CERM-X5R 6.3V

C4609

2

1

21

CRITICAL

D4601

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

4

1

0.1UF

75

USB3_EXTA_R2D_F_N

0201

USB3_EXTA_R2D_F_PUSB3_EXTA_R2D_CF_N

75

020110% CERM-X5R 6.3V

CRITICAL

2

D4606

ESD0P2RF-02LS

TSSLP-2-1

1

CRITICAL

L4603

80OHM-25%-100MA

GND_VOID=TRUE

0504

L2

3

2

L1

4

1

OMIT_TABLE

CRITICAL

L4604

80OHM-25%-100MA

0504

L2

L1

GND_VOID=TRUE

2

CRITICAL

D4602

ESD0P2RF-02LS

TSSLP-2-1

1

CRITICAL

2

D4604

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

3

2

CRITICAL

D4603

ESD0P2RF-02LS

TSSLP-2-1

2

OMIT_TABLEOMIT_TABLE

USB3_EXTA_D2R_F_N

75

USB3_EXTA_D2R_F_P

75

USB3_EXTA_R2D_N

75

USB3_EXTA_R2D_P

75

CRITICAL

1

D4605

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

USB2_EXTA_N

75

USB2_EXTA_P

75

EXT PORT A

CRITICAL

J4600

USB-NO1-K70

F-ANG-TH

1

VBUS

2

D-

3

D+

4

GND

5

STDA_SSRX-

6

STDA_SSRX+

7

GND_DRAIN

8

STDA_SSTX-

9

STDA_SSTX+

10 11 12 13 14 15

SHIELD

16 17 18 19 20 21 22

514-0817

D

C

B

A

16

OUT

USB_EXTB_OC_FET_L

41

USB_EXTA_OC_FET_L

41

PM_EN_USB_PWR

42 64

10

6

4 5

FAULT1* FAULT2*

EN1 EN2

GND

1

THRM

PAD

11

ILIM

7

USB_ILIM1_R

USB OVERCURRENT ISOLATION

=PP3V3_S4_PCH_GPIO

Q4611

SSM3K15AMFVAP

SOD

USB_OC_ISO:Y

USB_EXTA_OC_L

3

1

G

D

S

2

R4612

0

21

0% 1/16W MF-LF

USB_OC_ISO:N

0402

Q4621

SSM3K15AMFVAP

SOD

USB_OC_ISO:Y

1

G

USB_EXTB_OC_L

3

D

S

2

R4622

0

21

0%

1/16W MF-LF

USB_OC_ISO:N

Circuit added to prevent PCH from misinterpreting the power on behavior of the power switch as an overcurrent event

NOSTUFF the isolation circuit if power on behavior cleaned up

0402

1

R4611

100K

5% 1/20W MF 201

2

USB_OC_ISO:Y

USB_EXTA_OC_FET_L

=PP3V3_S4_PCH_GPIO

1

R4621

100K

5% 1/20W MF 201

2

USB_OC_ISO:Y

USB_EXTB_OC_FET_L

USB_ILIM1

R4602

11.5K

1% 1/16W MF-LF

402

R4603

11.5K

1% 1/16W MF-LF

402

15 18 41 42 66

1

2

MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

1

2

41

PART# DESCRIPTIONQTY

377S0155

PP5V_S4_EXTB_ILIM

VOLTAGE=5V

20% 16V

0402

1

2

C4615

0.01UF

X7R-CERM

www.qdzbwx.com

6

USB3 diodes

6377S0155

USB3 diodes

1

C4617

0.1UF

20% 10V

2

CERM 402

L4611

FERR-120-OHM-3A

0603

14 75

BI

14 75

BI

D4601,D4602,D4603,D4604,D4605,D4606

D4611,D4612,D4613,D4614,D4615,D4616

21

USB_EXTB_P

USB_EXTB_N

BOM OPTIONREFERENCE DESIGNATOR(S)

VOLTAGE=5V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

TABLE_5_HEAD

TABLE_5_ITEM

PP5V_S4_EXTB_F

CRITICAL

120-OHM-90MA

4 3

14 75

USB3_EXTB_R2D_CF_P

IN

USB3_EXTB_R2D_CF_N

IN

L4612

DLP0NS

SYM_VER-1

CRITICAL

2

D4611

21

14 75

P and N pins swapped for cleaner routing Lane polarity inversion supported by USB3 See Section 6.4.2 of USB3 Spec

USB3_EXTB_D2R_N

BI

USB3_EXTB_D2R_P

BI

10% CERM-X5R 0201

ESD0P2RF-02LS

TSSLP-2-1

1

OMIT_TABLE

C4618

C4619

21

6.3V

21

0.1UF

75

0.1UF

75

02016.3VCERM-X5R10%

4

1

USB3_EXTB_R2D_F_N

USB3_EXTB_R2D_F_P

CRITICAL

2

D4616

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

CRITICAL

L4613

80OHM-25%-100MA

GND_VOID=TRUE

0504

L2

3

2

L1

CRITICAL

L4614

80OHM-25%-100MA

0504

L2

4

1

L1

GND_VOID=TRUE

2

CRITICAL

D4612

ESD0P2RF-02LS

TSSLP-2-1

1

2

CRITICAL

D4613

ESD0P2RF-02LS

TSSLP-2-1

1

OMIT_TABLEOMIT_TABLE

EXT PORT B

CRITICAL

J4610

USB-NO2-K70

F-ANG-TH

1

75

USB2_EXTB_N

75

USB2_EXTB_P

75

USB3_EXTB_D2R_F_N

75

USB3_EXTB_D2R_F_P

USB3_EXTB_R2D_N

75

USB3_EXTB_R2D_P

CRITICAL

2

D4614

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE OMIT_TABLE

1

3

2

SYNC_MASTER=J117_GAREN

PAGE TITLE

CRITICAL

2

D4615

ESD0P2RF-02LS

TSSLP-2-1

1

2 3 4 5 6 7 8 9

10 11 12 13 14 15 16 17 18 19 20 21 22

VBUS DD+ GND STDA_SSRXSTDA_SSRX+ GND_DRAIN STDA_SSTXSTDA_SSTX+

SHIELD

514-0825

SYNC_DATE=05/05/2014

B

A

EXTERNAL USB PORTS A & B

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

46 OF 123

SHEET

41 OF 81

D

8 7 5 4 2 1

36

PP5V_S4_EXTC_ILIM

VOLTAGE=5V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

L4701

FERR-120-OHM-3A

1 2

0603

VOLTAGE=5V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

PP5V_S4_EXTC_F

345678

2 1

D

C

=PP5V_S4_USB

41 66

C4701

0.1UF

20% 10V

CERM

402

42

USB_EXTC_OC_FET_L

42

PM_EN_USB_PWR

41 64

EXT PORT C

CRITICAL

J4700

USB-NO3-K70

F-ANG-TH

1

VBUS

2

D-

3

D+

4

GND

5

STDA_SSRX-

6

STDA_SSRX+

7

GND_DRAIN

8

STDA_SSTX-

9

STDA_SSTX+

10 11 12 13 14 15

SHIELD

16 17 18 19 20 21 22

514-0826

D

C

C4705

0.01UF

20% 16V

X7R-CERM

0402

1

2

1

C4707

0.1UF

20% 10V

2

CERM 402

BI

USB_EXTC_P

USB_EXTC_N

14 75

CRITICAL

L4702

120-OHM-90MA

DLP0NS

SYM_VER-1

1 2

34

2

CRITICAL

D4701

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

CRITICAL

2

D4706

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

2

CRITICAL

D4702

ESD0P2RF-02LS

TSSLP-2-1

1

L4703

2

CRITICAL

D4703

ESD0P2RF-02LS

TSSLP-2-1

1

OMIT_TABLEOMIT_TABLE

75

USB2_EXTC_N

75

USB2_EXTC_P

75

USB3_EXTC_D2R_F_N

75

USB3_EXTC_D2R_F_P

80OHM-25%-100MA

0504

L2

14 75

OUT

14 75

OUT

CRITICAL

1

2

1

C4702

330UF-25MOHM

20%

6.3V

2

TANT CASE-D2E

CRITICAL

USB3_EXTC_D2R_N

USB3_EXTC_D2R_P

4

1

L1

GND_VOID=TRUE

U4700

2 3

10

6

4 5

TPS2561DR

SON

IN_0 IN_1

FAULT1* FAULT2*

EN1 EN2

GND

THRM

1

OUT2

PAD

11

OUT1

ILIM

9 8

7

USB_ILIM2USB_EXTD_OC_FET_L

USB_ILIM2_R

R4702

11.5K

1% 1/16W MF-LF

402

14 75

1

2

USB3_EXTC_R2D_CF_N

IN

USB3_EXTC_R2D_CF_P

C4708

10% CERM-X5R 0201

C4709

1 2

0.1UF

6.3V

0.1UF

6.3V10%

75

0201CERM-X5R

USB3_EXTC_R2D_F_N

USB3_EXTC_R2D_F_P

3

CRITICAL

2

CRITICAL

D4704

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

CRITICAL

2

D4705

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

L4704

80OHM-25%-100MA

4

1

GND_VOID=TRUE

0504

L2

3

2

L1

75

USB3_EXTC_R2D_N

75

USB3_EXTC_R2D_P

B

A

16

OUT

1% 1/16W MF-LF

402

1

2

R4703

11.5K

USB OVERCURRENT ISOLATION

=PP3V3_S4_PCH_GPIO

Q4711

SSM3K15AMFVAP

SOD

USB_OC_ISO:Y

USB_EXTC_OC_L

3

1

G

D

S

2

R4712

0

1 2

0% 1/16W MF-LF

USB_OC_ISO:N

0402

Q4721

SSM3K15AMFVAP

SOD

USB_OC_ISO:Y

1

G

USB_EXTD_OC_L USB_EXTD_OC_FET_L

3

D

S

2

R4722

0

1 2

0% 1/16W MF-LF

USB_OC_ISO:N

Circuit added to prevent PCH from misinterpreting the power on behavior of the power switch as an overcurrent event

NOSTUFF the isolation circuit if power on behavior cleaned up

0402

1

R4711

100K

5% 1/20W MF 201

2

USB_OC_ISO:Y

USB_EXTC_OC_FET_L

=PP3V3_S4_PCH_GPIO

1

R4721

100K

5% 1/20W MF 201

2

USB_OC_ISO:Y

PP5V_S4_EXTD_ILIM

VOLTAGE=5V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

C4715

0.01UF

20% 16V

X7R-CERM

0402

15 18 41 42 66

42

15 18 41 42 66

42

PART# DESCRIPTIONQTY

377S0155

377S0155 6

6

1

2

www.qdzbwx.com

USB3 diodes

1

C4717

0.1UF

20% 10V

2

CERM 402

FERR-120-OHM-3A

1 2

D4701,D4702,D4703,D4704,D4705,D4706

D4711,D4712,D4713,D4714,D4715,D4716

L4711

0603

14 75

BI

14 75

BI

BOM OPTIONREFERENCE DESIGNATOR(S)

VOLTAGE=5V MIN_LINE_WIDTH=0.6000 MIN_NECK_WIDTH=0.2000

USB_EXTD_P

USB_EXTD_N

TABLE_5_HEAD

TABLE_5_ITEM

CRITICAL

120-OHM-90MA

1 2

14 75

USB3_EXTD_R2D_CF_N

IN

USB3_EXTD_R2D_CF_P

IN

PP5V_S4_EXTD_F

L4712

DLP0NS

SYM_VER-1

2

CRITICAL

D4712

ESD0P2RF-02LS

TSSLP-2-1

1

34

2

CRITICAL

D4711

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

CRITICAL

2

D4716

ESD0P2RF-02LS

TSSLP-2-1

1

OMIT_TABLE

CRITICAL

L4713

80OHM-25%-100MA

14 75

OUT

14 75

OUT

P and N pins swapped for cleaner routing Lane polarity inversion supported by USB3 See Section 6.4.2 of USB3 Spec

USB3_EXTD_D2R_P

USB3_EXTD_D2R_N

4

1

GND_VOID=TRUE

0504

L2

3

2

L1

CRITICAL

OMIT_TABLE

CRITICAL

2

D4714

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

2

D4713

ESD0P2RF-02LS

TSSLP-2-1

CRITICAL

1

OMIT_TABLE

75

USB3_EXTD_D2R_F_N

75

USB3_EXTD_D2R_F_P

75

USB3_EXTD_R2D_N

75

USB3_EXTD_R2D_P

CRITICAL

2

D4715

ESD0P2RF-02LS

TSSLP-2-1

OMIT_TABLE

1

75

USB2_EXTD_N

75

USB2_EXTD_P

EXT PORT D

CRITICAL

J4710

USB-NO4-K70

F-ANG-TH

1

VBUS

2

D-

3

D+

4

GND

5

STDA_SSRX-

6

STDA_SSRX+

7

GND_DRAIN

8

STDA_SSTX-

9

STDA_SSTX+

10 11 12 13 14 15

SHIELD

16 17 18 19 20 21 22

B

L4714

C4718

C4719

CERM-X5R 6.3V 0201

10%

1 2

0.1UF

75

020110% CERM-X5R 6.3V

0.1UF

75

USB3_EXTD_R2D_F_N

USB3_EXTD_R2D_F_P

80OHM-25%-100MA

4

1

GND_VOID=TRUE

0504

L2

L1

514-0827

3

2

SYNC_MASTER=J117_GAREN SYNC_DATE=05/05/2014

PAGE TITLE

A

EXTERNAL USB PORTS C & D

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

47 OF 123

SHEET

42 OF 81

D

8 7 5 4 2 1

36

345678

2 1

D

C

B

NOTE: Unused pins have "SMC_Pxx" names. Unused

pins designed as outputs can be left floating,

those designated as inputs require pull-ups.

74 14

74 17

74 14

76 18

15

13

76 13

76 15

76 46

44

76 44

76 49

49

44

71 44

44

44 31

44

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

LPC_AD<0>

BI

LPC_AD<1>

BI

LPC_AD<2>

BI

LPC_AD<3>

BI

LPC_CLK24M_SMC

LPC_FRAME_L

SMC_LRESET_L

LPC_SERIRQ

BI

PM_CLKRUN_L

LPC_PWRDWN_L

SMC_RUNTIME_SCI_L

SMC_WAKE_SCI_L

SMBUS_SMC_0_S0_SCL

BI

SMBUS_SMC_0_S0_SDA

BI

SMBUS_SMC_1_S0_SCL

BI

SMBUS_SMC_1_S0_SDA

BI

SMBUS_SMC_2_S0_SCL

BI

SMBUS_SMC_2_S0_SDA

BI

SMBUS_SMC_3_SCL

BI

SMBUS_SMC_3_SDA

BI

SMBUS_SMC_4_ASF_SCL

BI

SMBUS_SMC_4_ASF_SDA

BI

SMBUS_SMC_5_G3H_SCL

BI

SMBUS_SMC_5_G3H_SDA

BI

SMC_FAN_0_CTL

SMC_FAN_0_TACH

SMC_FAN_1_CTL

SMC_FAN_1_TACH

SMC_TOPBLK_SWP_L

SMC_PN3

SMC_PN4

SMC_PN5

SMC_G3_WAKESRC_EN

SMC_PN7

SMC_PH2

SMC_PH3

CPU_PECI_R

IN

SMC_PECI_L

SMC_PP0

SMC_DP_HPD_L

SMC_PME_S4_WAKE_L

SMC_PME_S4_DARK_L

SMC_PP4

SMC_PP5

SMC_PP6

SMC_PP7

arch

od

arch

od

arch

proj

arch

proj

arch analog

arch

proj

int

B13

LPC0AD0

A13

LPC0AD1

C12

LPC0AD2

D11

LPC0AD3

H12

LPC0CLK

D12

LPC0FRAME*

C13

LPC0RESET*

H13

LPC0SERIRQ

G11

LPC0CLKRUN*

F13

LPC0PD*

F12

LPC0SCI*

B12

PK5

E10

I2C0SCL

D13

I2C0SDA

M4

I2C1SCL

N2

I2C1SDA

N8

I2C2SCL

M8

I2C2SDA

L8

I2C3SCL

K8

I2C3SDA

N7

I2C4SCL

M7

I2C4SDA

N4

I2C5SCL

N3

I2C5SDA

H11

PM6/FAN0PWM0

L13

PM7/FAN0TACH0

C11

PK6/FAN0PWM1

A12

PK7/FAN0TACH1

G3

PN2/FAN0PWM2

D10

PN3/FAN0TACH2

L11

PN4/FAN0PWM3

N12

PN5/FAN0TACH3

N11

PN6/FAN0PWM4

M11

PN7/FAN0TACH4

J4

PH2/FAN0PWM5

J2

PH3/FAN0TACH5

C4

PECI0RX

C6

PECI0TX

M13

PP0/IRQ116

L12

PP1/IRQ117

M5

PP2/IRQ118

J12

PP3/IRQ119

J13

PP4/IRQ120

L5

PP5/IRQ121

D8

PP6/IRQ122

K6

PP7/IRQ123

U5000

LM4FSXAH5BB

BGA

(1 OF 2)

OMIT_TABLE

T3CCP1/PJ5/C2-

T3CCP0/PJ4/C2+

SSI0CLK/PA2 SSI0FSS/PA3

SSI0RX/PA4

SSI0TX/PA5

T0CCP0/PB6 T0CCP1/PB7

SSI1RX/PF0

SSI1TX/PF1 SSI1CLK/PF2 SSI1FSS/PF3

WT0CCP0/PG4 WT0CCP1/PG5

AIN00 AIN01 AIN02 AIN03 AIN04 AIN05 AIN06 AIN07 AIN08 AIN09 AIN10 AIN11 AIN12 AIN13 AIN14 AIN15 AIN16 AIN17 AIN18 AIN19 AIN20 AIN21 AIN22 AIN23

C0-

C0+

C1-

PC5/C1+

U1RX/B0

U1TX/PB1

PF4 PF5

E2 E1 F2 F1 B3 A3 B4 A4 B5 A5 B6 A6 C1 C2 B1 B2 G2 G1 H1 H2 B7 A7 B8 A8

K2 K1 L2 L1 C5 D5

M2 M3 L4 N1

F11 E11 F4 F3

M9 N9 L10 K10 L9 K9

K7 L7

proj

analog

proj analog

proj

analog

proj analog

proj

arch

analog

arch

analogarch

arch

pwm

arch

66 49 44

SMC_ADC0

SMC_ADC1

SMC_ADC2

SMC_ADC3

SMC_ADC4

SMC_ADC5

SMC_ADC6

SMC_ADC7

SMC_ADC8

SMC_ADC9

SMC_ADC10

SMC_ADC11

SMC_ADC12

SMC_ADC13

SMC_ADC14

SMC_ADC15

SMC_ADC16

SMC_ADC17

SMC_ADC18

SMC_ADC19

SMC_ADC20

SMC_ADC21

SMC_ADC22

SMC_ADC23

CPU_PROCHOT_L

SMC_VCCIO_CPU_DIV2

SMC_S5_PWRGD_VIN

SPI_DESCRIPTOR_OVERRIDE_L

SMC_CPU_CATERR_L

CPU_THRMTRIP_3V3

SMC_PM_G2_EN

PM_DSW_PWRGD

SMC_DELAYED_PWRGD

SMC_PROCHOT

SMC_DEBUGPRT_RX_L

SMC_DEBUGPRT_TX_L

SMC_SYS_LED

SMC_GFX_THROTTLE_L

SPI_SMC_MISO

SPI_SMC_MOSI

SPI_SMC_CLK

SPI_SMC_CS_L

S5_PWRGD

SMC_PM_PCH_SYS_PWROK

SMC_DEBUGPRT_EN_L

SMC_GFX_OVERTEMP

=PP3V3_G3H_SMC

C5002

1UF

20% 10V

X5R-CERM

0603-1

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

44

IN

17

OUT

44

IN

44

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

56 44

65 44

65 44 27

44

44 41

44

74 45

65

44

41

44

L5001

30-OHM-1.7A

21

PP3V3_G3H_SMC_VDDA

0402

1

2

1

C5003

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5007

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5004

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5008

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5005

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5009

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5006

0.1UF

10%

6.3V

2

CERM-X5R 0201

45 44

44 31

74 44

IN

BI

IN

76 44

SMC_RESET_L

AP_EVENT_L

NC_SMC_HIB_L

NO_TEST=1

SMC_CLK32K

NC_SMC_XOSC1

NO_TEST=1

SMC_EXTAL

SMC_XTAL

1

R5002

1M

5% 1/20W MF 201

2

(OD)

SMC_WAKE_L

RST*

B11

PK4/RTCCLK

N13

WAKE*

M12

HIB*

M10

XOSC0

N10

XOSC1

G12

OSC0

G13

OSC1

K12

VBAT

U5000

LM4FSXAH5BB

BGA

(2 OF 2)

SWCLK/TCK

SWDIO/TMS

OMIT_TABLE

D7

E6

1

C5010

1UF

10%

6.3V

2

CERM 402

1

C5011

1UF

10%

6.3V

2

CERM 402

1

C5012

1UF

10%

6.3V

2

CERM 402

E8 E9

F10

J7

VDD

J9

J10

J1 J6

K13

D6

VDDC

1

C5013

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5014

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5015

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5016

0.1UF

10%

6.3V

2

CERM-X5R 0201

1

C5017

0.1UF

10%

6.3V

2

CERM-X5R 0201

PP1V2_G3H_SMC_VDDC

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.1000 VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2500 MIN_NECK_WIDTH=0.1000 VOLTAGE=3.3V

C10G10 A10

TDI

NC

A11 B10

A2

D3

D2 D1

SWO/TDO

VDDA

VREFA+

VREFA-

C3

GNDA

E3

A1 C7 D9 E5 F9 H5

GND

H9 J5 J8 J11

K11

NC

1

C5001

0.1UF

10%

6.3V

2

CERM-X5R 0201

SMC_TCK

SMC_TMS

SMC_TDO

SMC_TDI

XW5000

SM

2 1

PLACE_NEAR=U5000.A1:4MM

45 44

44

PLACE_NEAR=U5000.D1:4mm

GND_SMC_AVSS

C5020

1.0UF

20%

6.3V X5R

0201-1

76 47 44

D

PP3V3_G3H_AVREF_SMC

PLACE_NEAR=U5000.D2:4mm

1

2

1

C5021

0.01UF

10% 10V

2

X5R-CERM 0201

44

C

71 57 44 6

B

A

13

44

65 64 44 35 13

64 13

64 31 13

44

IN

OUT

BI

PCH_SUSWARN_L

SMS_INT_L

SMC_BC_ACOK

G3_POWERON_L

PM_SLP_S3_L

PM_SLP_S4_L

PM_SLP_S5_L

SMC_ONOFF_L

SMC_RX_L

SMC_TX_L

SMC_PL7

SMC_PL6

arch

od

int

intarch

arch int

arch

int

arch

D4

PQ0/IRQ124

E4

PQ1/IRQ125

F5

PQ2/IRQ126

N5

PQ3/IRQ127

N6

PQ4/IRQ128

K5

PQ5/IRQ129

M6

PQ6/IRQ130

L6

PQ7/IRQ131

L3

U0RX

M1

U0TX

E13

USB0DM

E12

USB0DP

WT2CCP0/PH0 WT2CCP1/PH1

WT3CCP0/PH4 WT3CCP1/PH5 WT4CCP0/PH6 WT4CCP1/PH7

T1CCP0/PJ0 T1CCP1/PJ1 T2CCP0/PJ2 T2CCP1/PJ3

WT5CCP1/PM3

K3 K4

J3 H4 H3 G4

C9 B9 A9 C8

H10

arch

proj

arch

proj

arch

od

ALL_SYS_PWRGD

SMC_THRMTRIP

PM_PWRBTN_L

PM_SYSRST_L

MEM_EVENT_L

SMC_PH7

SMC_OOB1_D2R_L

SMC_OOB1_R2D_L

SMC_PJ2

SMC_PJ3

SMC_BATLOW_L

OUT

44

65 17 3

16 13

17 13

76 33

SYNC_MASTER=J70_NICK

PAGE TITLE

SYNC_DATE=09/24/2013

A

IN

SMC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

051-00081

3.0.0

50 OF 123

43 OF 81

D

ADC Channel Aliases

345678

2 1

D

C

49 44 43

66

66 49 44 43

=PP3V3_G3H_SMC

=PPVIN_G3H_SMCVREF

66

SMC_MANUAL_RST_L

10% 16V

0402

1

2

C5101

0.01UF

X7R-CERM

Note: IPU are pulled to VIN rail

Power Button

=PP3V3_G3H_SMC

DEVELOPMENT

J5120

NTC020-AK1J-B260T

SM

21

R5102

1

R5120

10K

5% 1/20W MF 201

2

47

21

5% 1/16W MF-LF

402

10%

6.3V

402

1

2

C5100

0.47UF

CERM-X5R

SMC_ONOFF_L

MAKE_BASE=TRUE

PWR_BTN

SMC Supervisor and AVREF Supply

=PP3V3_G3H_SMC

3

1

R5105

100K

5% 1/16W MF-LF 402

2

1

C5102

4.7UF

20%

6.3V

2

X5R-CERM1 402

66 49 44 43

PP3V42_G3H_SMC_SPVSR

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000 VOLTAGE=3.42V

1

V+ VIN

U5100

VREF-3.3V-VDET-3.0V

NC

OUT

6

7

4

MR1*

MR2*

DELAY

44 17

43

56

(ipu)

DFN

SN0903049

CRITICAL

GND

2

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000 VOLTAGE=0V

SMC_ASSERT_RTCRST

R5199

RESET*

REFOUT

THRM

PAD

9

SMC Controlled RTC Reset

1

10K

5% 1/16W MF-LF

402

2

5

8

C5105

1UF

20% 10V

X5R-CERM

0603-1

NOSTUFF

1

C5199

1.0UF

20%

6.3V

2

X5R-CERM 0402

1

2

PP3V3_G3H_AVREF_SMC

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000 VOLTAGE=3.3V

1

C5106

0.01UF

10% 16V

2

X7R-CERM 0402

76 47 43

RTC_RESET_L_R

G

1

SMC_RESET_L

43

NOSTUFF

5%

25V CERM 0402

1

2

C5103

1000PF

To absorb current from discharging RTC Reset CAP

R5194

330

1/16W MF-LF

3

D

CRITICAL

5%

402

21

RTC_RESET_L

Q5199

S

2

SSM3K15AMFVAP

SOD

OUT

45 43

OUT

SMC_ADC0

43

SMC_ADC1 ISNS_P12VG3H

43 76 47

SMC_ADC6

43

SMC_ADC7

43

SMC_ADC10

43

SMC_ADC11

43

SMC_ADC20

43

SMC_ADC21

43

VSNS_P12VG3H

MAKE_BASE=TRUE

VSNS_P1V2_S3_DDR

MAKE_BASE=TRUE

ISNS_P1V2_S3_DDR

MAKE_BASE=TRUE

VSNS_CPUVCC

MAKE_BASE=TRUE

ISNS_CPUVCC

MAKE_BASE=TRUE

VSNS_P3V3_SSD

MAKE_BASE=TRUE

ISNS_SSDS4

MAKE_BASE=TRUE

Unused ADC Channels

12

SMC_ADC2

43

SMC_ADC3

43

SMC_ADC4

43

SMC_ADC5 NC_ISNS_PVDDQS0

43

SMC_ADC8

43

SMC_ADC9

43

SMC_ADC12

43

SMC_ADC13

43

SMC_ADC14

43

SMC_ADC15

43

SMC_ADC16

43

SMC_ADC17

43

SMC_ADC18

43

SMC_ADC19

43

SMC_ADC22

43

SMC_ADC23

43

NC_VSNS_P12VS0_GPUCORE

MAKE_BASE=TRUE

NO_TEST=1

NC_ISNS_P12VS0_GPUCORE

MAKE_BASE=TRUE

NO_TEST=1

NC_VSNS_PVDDQS0

MAKE_BASE=TRUE

NO_TEST=1

NC_VSNS_P12VS0_FBVDDQ

MAKE_BASE=TRUE

NO_TEST=1

NC_ISNS_P12VS0_FBVDDQ

MAKE_BASE=TRUE

NO_TEST=1

NC_VSNS_GPUCORE_ALT

MAKE_BASE=TRUE

NO_TEST=1

NC_ISNS_GPUCORE_ALT

MAKE_BASE=TRUE

NO_TEST=1

NC_VSNS_HDDS0

MAKE_BASE=TRUE

NO_TEST=1

NC_ISNS_HDDS0

MAKE_BASE=TRUE

NO_TEST=1

NC_SMC_ADC16

MAKE_BASE=TRUE

NO_TEST=1

NC_SMC_ADC17

MAKE_BASE=TRUE

NO_TEST=1

NC_VSNS_P1V05S0_PCH

MAKE_BASE=TRUE

NO_TEST=1

NC_ISNS_P3V3S4_AP

MAKE_BASE=TRUE

NO_TEST=1

NC_SMC_ADC22

MAKE_BASE=TRUE

NO_TEST=1

NC_SMC_ADC23

MAKE_BASE=TRUE

NO_TEST=1

Platform Thermal Control

76 47

SMC_PN5

43

SMC_PJ3

43

76 47

TP for access if ZPB re-intstated

SMC_PJ2

43

SMC_PP0

43

SMC_PH2

43

SMC_PL6

43

SMC_PH3

SMC_PL7

43

SMC_S5_PWRGD_VIN

43

SMC_PN3

43

SMC_PN4

43

SMC_PP4

43

SMC_PN7

43

SMC_PP5

43

SMC_PP6

43

SMC_PP7

43

SMC_DP_HPD_L

43

SMC_PME_S4_DARK_L

43

SMC_PH7

43

SMBUS_SMC_4_ASF_SCL

43

SMBUS_SMC_4_ASF_SDA

43

SMBUS_SMC_5_G3H_SCL

76 43

SMBUS_SMC_5_G3H_SDA

76 43

SMC_BATLOW_L

43

SMC_GFX_THROTTLE_L

43

SMC_GFX_OVERTEMP

43

MEM_EVENT_L

43

Project-specific Aliases

ACDC_BURST_EN_L

MAKE_BASE=TRUE

SMC_OOB2_R2D_L

MAKE_BASE=TRUE

SMC_OOB2_D2R_L

MAKE_BASE=TRUE

SMC_ACDC_ID

MAKE_BASE=TRUE

SMC_ASSERT_RTCRST

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN

MAKE_BASE=TRUE

SMC_PCH_SUSACK_L

MAKE_BASE=TRUE

BT_PWR_EN

MAKE_BASE=TRUE

Unused Project-specific

NC_SMC_S5_PWRGD_VIN

MAKE_BASE=TRUE

NC_SMC_PN3

MAKE_BASE=TRUE

NC_SMC_PN4

MAKE_BASE=TRUE

NC_SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

NC_SMC_PN7

MAKE_BASE=TRUE

NC_SMC_PP5

MAKE_BASE=TRUE

NC_SMC_PP6

MAKE_BASE=TRUE

NC_SMC_PP7

MAKE_BASE=TRUE

NC_SMC_DP_HPD_L

MAKE_BASE=TRUE

NC_SMC_PME_S4_DARK_L

MAKE_BASE=TRUE

NC_SMC_PH7

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

MAKE_BASE=TRUE

NC_SMBUS_SMC_5_G3H_SCL

MAKE_BASE=TRUE

NC_SMBUS_SMC_5_G3H_SDA

MAKE_BASE=TRUE

NC_SMC_BATLOW_L

MAKE_BASE=TRUE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

NC_MEM_EVENT_L

MAKE_BASE=TRUE

NO_TEST=1

44

56

44

13 43

SMC 32KHz Clock

R5160

76 32

44 17

74 13

PM_CLK32K_SUSCLK_R

IN OUT

PLACE_NEAR=U0500.AE6:10MM

SMC Crystal

NOTE: SMC team wants 12MHz for this Xtal

51

2 1

5%

1/20W

MF

201

SMC_CLK32K

SMC_EXTAL

74 43

76 43

D

44 31

CRITICAL

Y5165

3.2X2.5MM-SM

12.000MHZ-30PPM-10PF-85C

31

SMC_XTAL_R

C5165

12PF

5% 50V C0G

0402

1

2

42

PM_PCH_SYS_PWROK

71 6

44 43 15

CPU_CATERR_L

IN OUT

SMC_TOPBLK_SWP_L

IN OUT

1

C5166

12PF

5% 50V

2

C0G 0402

R5148

0

2 1

5%

1/20W

MF

0201

R5149

0

2 1

5%

1/20W

MF

0201

R5154

1K

5%

1/20W

MF

201

21

NOSTUFF

R5166

1M

5% 1/16W MF-LF

402

1

2

R5165

0

2 1

5% 1/16W MF-LF

402

SMC_PM_PCH_SYS_PWROK

SMC_CPU_CATERR_L

PCH_STRP_TOPBLK_SWP_L

SMC_XTAL

76 43

43 65 16 13

OUTIN

43

C

Arch Pull Up/Down

B

43

Comparator Reference

=PP1V05_S0_SMC

66 44

R5130

PLACE_NEAR=U5000.K1:5MM

R5131

10K

1% 1/16W MF-LF

402

10K

1% 1/16W MF-LF

402

1

2

SMC_VCCIO_CPU_DIV2

1

2

PLACE_NEAR=U5000.K1:3.5MM

1

C5131

0.1UF

10% 16V

2

X7R-CERM 0402

OUT

43

SMC control for AirPort power

=PP3V3_S4_AP

66 31

100K

5%

1/20W

MF

201

1

2

AP_PWR_EN

MAKE_BASE=TRUE

SMC_WIFI_PWR_EN

44

R5142

OUT

31

43

SMC_PROCHOT

IN

71 43

PROCHOT Support

Level-shifter that allows SMC to drive PROCHOT

CPU_PROCHOT_L

3

D

CRITICAL

Q5125

G

1

S

SSM3K15AMFVAP

SOD

Level-shifter that allows SMC to drive PECI

Place this circuit near the Tee point to minimize reflections

SMC_PECI_L

IN

R5135

1/16W MF-LF

OMIT

R5136

NOSTUFF

NONE NONE NONE

BI

1

C5125

47PF

5% 50V

2

CER 0402

Wire OR'd with CPU

71 57 43 6

5%

402

0

66 44

1

2

1

2

PECI Support

=PP1V05_S0_SMC

G

1

SMC_PECI_L_R

3

D

S

2

CRITICAL

Q5135

SSM3K15AMFVAP

SOD

43

CPU_PECI_R

1

R5137

330

5% 1/16W MF-LF 402

2

NOSTUFF

1

C5137

2

47PF

5% 50V CER 0402

R5138

43

2 1

5% 1/16W MF-LF

402

CPU_PECI

=PP3V3_S0_SMC

66

44 43

43 31

6

BI

71

43 31

44 31

65 43 27

65 43

56 43

SMC_TOPBLK_SWP_L

G3_POWERON_L

43

SMC_BC_ACOK

43

SMC_SYS_LED

43

SMS_INT_L

43

SMC_PME_S4_WAKE_L

AP_EVENT_L

SMC_G3_WAKESRC_EN

43

BT_PWR_EN

SMC_DELAYED_PWRGD

PM_DSW_PWRGD

SMC_PM_G2_EN

NOSTUFF

R5171

R5176

R5178 R5179 R5180 R5181

R5185

R5118

R5119

R5186 R5184 R5187

1K

66 49 44 43

10K

100K 100K

10K 10K

31

10K

100K

100K 100K 100K

21

5% MF

1/20W

201

=PP3V3_G3H_SMC

21

5% MF 5% MF 5% MF 5% MF

1/20W5%

201MF

1/20W

201

1/20W

201

1/20W

201

1/20W

201

PP3V3_S4_AP_FET

21

5%

1/20W

201

MF

21

MF-LF 402

21

MF-LF

21

1/20W

5%

201

MF

5% 1/20W

201MF

1/16W5%

5% 1/16W

402

5%

1/20W

201

MF

B

Note:

A

66 44

CRITICAL

Q5140

DMN5L06VK-7

SOT563

ACDC_BURST_EN_L

44

65 64 43 35 13

=PP3V3_S5_SMC

VER 3

5

PM_SLP_S3_L

IN

R5140

10K

5%

1/20W

MF

201

G S

1

2

ACDC_BURST

3

D

4

66

AC/DC Burst Mode Enable

66 44

=PP3V3_S5_SMC

2

A

U5140

1

B

CRITICAL

TC7SZ08FEAPE

SOT665

1

C5140

0.1UF

10%

6.3V

2

CERM-X5R 0201

5

4

PM_SLP_S3_BUF_L

Y

3

=PP3V3_S4_SMC

R5141

10K

1/20W

VER 3

2

G S

5%

MF

201

Note:

1

Open-drain stage on S4 to account

case when SMC is initializing in S5,

and chip is not yet configured.

and ACDC_BURST_EN_L could be floating.

2

BURSTMODE_EN_L

CRITICAL

6

D

Q5140

DMN5L06VK-7

SOT563

1

www.qdzbwx.com

OUT

2

61 56

71 15

IN

This allows SMC to shutdown system.

43

SMC_THRMTRIP

IN

R5126

10K

5%

1/20W

MF

201

1

2

PM_THRMTRIP_L

G

1

66 44

3

D

CRITICAL

Q5123

S

2

SSM3K15AMFVAP

SOD

R5127

3.3K

2 1

5%

1/20W

MF

201

This passes CPU's TRHMTRIP to SMC so shutdown reason can be recorded.

=PP3V3_S5_SMC

CPU_TT_OC_L

R5128

10K

5%

1/20W

MF

201

1

2

CPU_THRMTRIP_3V3

3

CRITICAL

Q5127

BC846BLP

DFN1006H4-3

2

OUT

43

43 41

45 43

43

45 43

Serial/JTAG Interface Pull-ups

66 49 44 43

SMC_TX_L

SMC_RX_L

SMC_DEBUGPRT_TX_L

SMC_DEBUGPRT_RX_L

SMC_TCK

SMC_TDI

SMC_TDO

SMC_TMS

PAGE TITLE

R5190 R5191 R5192 R5193

R5195 R5196 R5197 R5198

10K

100K

20K 20K

10K 10K 10K 10K

SMC Support

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

=PP3V3_G3H_SMC

21

5%

1/20W

201

MF

21

5% 1/20W

201

MF

21

1/20W

5%

201

MF

1/20W5%

201MF

1/20W

5%

201

MF

1/20W MF5%201 5%

1/20W

201

MF 5%

1/20W

201

MF

SYNC_DATE=01/15/2014SYNC_MASTER=J70_NICK

DRAWING NUMBER SIZE

051-00081

REVISION

BRANCH

PAGE

SHEET

A

D

3.0.0

51 OF 123

44 OF 81

8 7 5 4 2 1

36

D

74 45

74 45 15

345678

2 1

SPI BootROM

Quad_IO Mode (Mode 0 & 3) supported

SPI Freq: 50MHz for PCH, 20 MHz for SMC

=PP3V3_S5_ROM

66

8

4

CRITICAL

SI/SIO0

SO/SIO1

EPAD

9

74 45

5 2

SPI_MLB_MOSI

SPI_MLB_MISO

BI

74 45

45

44 43

IN

OUT

SPI_ALT_MOSI SPI_ALT_MISO SPI_ALT_IO<2> SPI_ALT_IO<3>

SMC_RESET_L SMC_TCK

1UF

10%

6.3V CERM

402

1

VCC

2

U5210

MX25L6473EZNI-10G

64MBIT

WSON

OMIT_TABLE

GND

7

6

1

3

SCLK

CS*

SIO2

SIO3

C5210

1UF

10%

6.3V CERM

402

1

2

74 45

SPI_MLBROM_CS_L

45

IN

BI

SPI_MLB_CLK

SPI_MLB_IO<2>

SPI_MLB_IO<3>

YA

OE*

C5205

7

1

100K

5%

1/20W

MF

201

1

8

VCC

2

U5205

74LVC1G99

2

3

5

6

SOT833

B

C

D

R5212

IN

SPI_MLB_CS_L

SPIROM_USE_MLB FUNC_TEST=TRUE

GND

4

SPI+SWD SAM Connector

SAMCONN

J5200

=PP3V3_G3H_T112

66

FUNC_TEST=TRUE

DF40PC-12DP-0.4V-51

M-ST-SM

14 13

2 1

4 3

6 5

8 7

10 9

12 11

16

15

CRITICAL

516S00024

SPI_ALT_CLK

SPI_ALT_CS_L SPIROM_USE_MLB SMC_TMS

IN

BI

OUT

D

74 45

74 45 15

44 43

C

SPI Series Termination

1

R5223

43

5% 1/20W MF 201

2

1

R5224

43

5% 1/20W MF 201

2

1

R5225

43

5% 1/20W MF 201

2

1

R5226

43

5% 1/20W MF 201

2

1

R5227

43

5% 1/20W MF 201

2

1

R5228

43

5% 1/20W MF 201

2

SPI_ALT_IO<3>

SPI_ALT_IO<2>

SPI_ALT_MISO

FUNC_TEST=TRUE

SPI_ALT_MOSI

FUNC_TEST=TRUE

SPI_ALT_CLK

SPI_ALT_CS_L

PLACE_NEAR=J5200.11:5mm

45

74 45

PLACE_NEAR=J5200.11:5mm

PLACE_NEAR=J5200.9:5mm

PLACE_NEAR=J5200.12:10mm

PLACE_NEAR=J5200.14:5mm

C

SAM Card ROM slave

B

5%

MF

R5229

43

5%

1/20W

MF

201

21

SPI_MLB_CS_L

SPI_MLB_CLK

OUT

SPI_MLB_MOSI

SPI_MLB_MISO

SPI_MLB_IO<2>

SPI_MLB_IO<3>

R5220

74 14

IN

SPI_CS0_R_L

PLACE_NEAR=U0500.Y7:11MM

R5221

74 14

IN

SPI_CLK_R

PLACE_NEAR=U0500.AA3:12.5MM

R5222

74 14

BI

SPI_MOSI_R

PLACE_NEAR=U0500.AA2:18.5MM

R5235

14 74 45

BI BI

PLACE_NEAR=U0500.AA4:12.7MM

R5236

14

BI BI

SPI_IO_R<2>

PLACE_NEAR=U0500.Y6:12.5MM

R5237

14 45

BI BI

SPI_IO_R<3>

PLACE_NEAR=U0500.AF1:12.7MM

15

5%

1/20W

MF

201

15

5%

1/20W

MF

201

21

15

5%

1/20W

MF

201

21

15

5%

1/20W

MF

201

21

15

5%

1/20W

MF

201

21

15

21

5%

1/20W

MF

201

21

SPI_CS0_L

74

FUNC_TEST=TRUE

SPI_CLK

74

FUNC_TEST=TRUE

SPI_MOSI

74

SPI_MISOSPI_MISO_R

74

SPI_IO<2>

FUNC_TEST=TRUE

SPI_IO<3>

FUNC_TEST=TRUE

PLACE_NEAR=R5224.2:5mm

R5234

43

PLACE_NEAR=R5223.2:5mm

5%

1/20W

MF

201

PLACE_NEAR=R5226.2:5mm

PLACE_NEAR=R5225.2:5mm

R5233

43

21

5%

1/20W

MF

21

201

PLACE_NEAR=R5228.2:5mm

PLACE_NEAR=R5227.2:5mm

R5231

43

21

5%

R5232

43

5%

1/20W

MF

201

1/20W

MF

201

21

R5230

43

1/20W

201

74 45

B

BI

74 45

45

A

74 43

SPI_SMC_MISO

OUT

SPI_SMC_MOSI

IN

PLACE_NEAR=U5000.N9:8.5MM

74 43

SPI_SMC_CLK

IN

PLACE_NEAR=U5000.L10:15MM

74 43

SPI_SMC_CS_L

IN

PLACE_NEAR=U5000.K10:12.7MM

www.qdzbwx.com

R5250

24

5%

1/20W

MF

201

R5252

15

5%

1/20W

MF

201

21

PLACE_NEAR=U5210.2:5MM

R5251

43

21

5%

1/20W

MF

201

21

R5253

15

21

5%

1/20W

MF

201

SMC SPI Master Support

SYNC_MASTER=J117_TONY SYNC_DATE=05/05/2014

PAGE TITLE

SPI and Debug Connector

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

52 OF 123

SHEET

45 OF 81

D

A

8 7 5 4 2 1

36

345678

2 1

Line Legend

D

66 46

=PP3V3_S0_SMBUS

U0500

PCH (SMBus)

SMBUS_PCH_CLK

14 76

MAKE_BASE=TRUE

SMBUS_PCH_DATA

14 76

MAKE_BASE=TRUE

R5360

2.2K

5% 1/16W MF-LF

402

=PP3V3_S0_SMBUS_SMC_0

66

1

R5361

2.2K

5% 1/16W MF-LF

2

402

2

U5000

SMC (SMBus 0)

R5300

2.2K

5% 1/16W MF-LF

402

1

R5301

2.2K

5% 1/16W MF-LF

2

402

2

66 46

SMB_0_S0_CLK

MAKE_BASE=TRUE

SMB_0_S0_DATA

MAKE_BASE=TRUE

76 43

U5600

Temp Sensors "T1"

=SMB_SNS1_SCL

=SMB_SNS1_SDA

U5600 EMC1414 (Prod):

48

0x98 Write 0x99 Read

48

U8100

Backlight Control

=I2C_BKLT_SCL

=I2C_BKLT_SDA

0x58 Write 0x59 Read

62

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

=PP3V3_S0_SMBUS

U0500

SML_PCH_0_CLK

14 76

MAKE_BASE=TRUE

SML_PCH_0_DATA

14 76

MAKE_BASE=TRUE

Unused PCH SM Link

R5364

8.2K

5%

1/20W

MF

201

1

R5365

8.2K

5% 1/20W MF

2

201

2

Master

Slave

Mux

D

C

J1800

XDP

=SMBUS_XDP_SCL

=SMBUS_XDP_SDA

0x94 Write 0x95 Read

16

66 39

=PP3V3_S0_SMBUS_SMC_1

SMC (SMBus 1)

SMB_1_S0_CLK

MAKE_BASE=TRUE

SMB_1_S0_DATA

MAKE_BASE=TRUE

R5310

2.2K

5% 1/16W MF-LF

402

U0500

PCH (SML 1)

0x88 Write

SML_PCH_1_CLK

SML_PCH_1_DATA

1

R5311

2.2K

5% 1/16W MF-LF

2

402

2

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

U5650U5000

Temp Sensors "T2"

=SMB_SNS2_SCL

=SMB_SNS2_SDA

76 43

48

0x89 Read

14

For J70: U5650 TMP423B (Dev): 0x9A Write 0x9B Read

C

J4400

Display TCon

TMP421:

SMB_DP_MLB_MSR_SCL

0x9E Write

39

0x9F Read

B

=PP3V3_S0_SMBUS_SMC_2

66

U5000

SMC (SMBus 2)

SMB_2_S0_CLK

MAKE_BASE=TRUE

SMB_2_S0_DATA

MAKE_BASE=TRUE

R5320

2.2K

5% 1/16W MF-LF

402

SMB_DP_MLB_MSR_SDA

1

2

R5321

2.2K

5% 1/16W MF-LF 402

2

76 43

SMBUS_SMC_2_S0_SCL

76 43

SMBUS_SMC_2_S0_SDA

J4200

ALS

=SMB_ALS_SCL

=SMB_ALS_SDA

39

Panel/Vendor ID: 0x1A Write 0x1B Read

0x52 Write 0x53 Read

37

B

A

www.qdzbwx.com

=PP3V3_S0_SMBUS_SMC_3

66

U5000

SMC (SMBus 3)

SMB_3_CLK

MAKE_BASE=TRUE

SMB_3_DATA

MAKE_BASE=TRUE

SMC multi-master experiment

R5330

4.7K

5% 1/16W MF-LF

402

1

R5331

4.7K

5% 1/16W MF-LF

2

402

2

SMBUS_SMC_3_SCL

SMBUS_SMC_3_SDA

76 43

SYNC_MASTER=J70_NICK SYNC_DATE=02/14/2014

PAGE TITLE

A

SMBus Connections

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

53 OF 123

SHEET

46 OF 81

D

8 7 5 4 2 1

36

345678

2 1

D

C

12V G3H (VD2R:ADC0/ID2R:ADC1)

CRITICAL

R5400

=PP12V_G3H_SNS_R

66

0.002

1% 1W

TFT

0612

1 2 3 4

PP12V_G3H_SNS

=PP3V3_S5_SENSE

66

3

V+

66

U5400

SNS_P12VG3H_N

76

SNS_P12VG3H_P

76

353S2208

Gain: 100 V/V

Range: 0-16.5A

5

IN-

4

INA214

SC70

CRITICAL

GND

2

SSD S4 (IH1R:ADC21/VR3R:ADC20)

SSD:Y

CRITICAL

R5410

=PPSSD_S4_SNS_R

66

0.002

1% 1W

TFT

0612

12 34

PPSSD_S4_SNS

SSD:Y

66

=PP12V_S5_SNS

1

2

6

76

OUT

REFIN+

ISNS_P12VG3H_R

1

66

AC/DC lowside sense (System total)

NOTE:VSNS on S5 to avoid burning G3H Power

R5401

18.2K

C5400

0.22UF

20%

6.3V X5R 0201

1 2

1% 1/16W MF-LF

402

1

R5402

6.04K

1% 1/16W MF-LF 402

2

VSNS_P12VG3H

U5000.E2:10mm

1

C5402

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

R5405

4.53K

1

R5406

20K

5% 1/20W MF 201

2

1 2

1% 1/16W MF-LF

402

ISNS_P12VG3H

U5000.E1:10mm

1

C5405

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

I-sense / V-sense for SSD

SSD:Y

R5416

4.53K

1 2

1%

1/20W

MF

201

VSNS_P3V3_SSD

OMIT_TABLE

U5000.B7:10mm

1

C5416

0.22UF

20%

6.3V

2

X5R 0201

OUT

44 76

OUT

43 44 47 76

44 76

OUT

43 44 47 76

VDDQ S3 (VM0R:ADC6/IM0R:ADC7)

VDDQ lowside sense for DDR

CRITICAL

R5430

66

0.0005

1% 1W MF

0612-2

21 43

SNS_P1V2_S3_DDR_N ISNS_P1V2_S3_DDR_R

76

SNS_P1V2_S3_DDR_P

76

5

4

353S3498

Gain: 1000 V/V

Range: 0-6.6A

PP1V2_S3_SNS_DDR

=PP3V3_S0_SENSE

32 33 48 66

3

V+

U5430

INA212

IN-

IN+ REF

SC70

CRITICAL

GND

2

OUT

CPU Core (VC0C:ADC10/IC0C:ADC11)

Voltage sense and IMON amp (VC0C, IC0C)

R5461

4.53K

1 2

1% 1/16W MF-LF

402

VSNS_CPUVCC

U5000.B6:10mm

1

C5461

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

44 76

OUT

43 44 47 76

D

66

1

C5430

0.22UF

20%

6.3V

2

X5R 0201

R5431

4.53K

1 2

1%

1/20W

MF

201

VSNS_P1V2_S3_DDR=PP1V2_S3_SNS_DDR_R

U5000.B4:10mm

1

C5431

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

44 76

OUT

43 44 47 76

=PPCPUVCC_S0_CPU

66

R5435

6

76

1

R5436

20K

5% 1/20W MF 201

2

4.53K

1 2

1%

1/20W

MF

201

ISNS_P1V2_S3_DDR

U5000.A4:10mm

1

C5435

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

44 76

OUT

43 44 47 76

PLACE_NEAR=U5000.A6:10mm

R5465

0

57 76

CPUVR_IMON ISNS_CPUVCC

IN OUT

1 2

5% 1/16W MF-LF

402

NOSTUFF

1

C5465

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

PLACE_NEAR=U5000.A6:10mm

44 76

43 44 47 76

C

U5410

INA216A4

SNS_SSD_P

76

SNS_SSD_N

76

2

IN+

3

IN+

4

IN-

5

IN-

353S4411 Gain: 200 V/V Range: 0-8.25A

PART# DESCRIPTIONQTY

132S0304 2 CAP,0.22UF,201 SSD:Y

TQFN

CRITICAL

GND

9

OUT

10

1 6

NC

7 8

C5415,C5416

C5415,C5416117S0201 SSD:N2 RES,0 OHM,201

NC

76

ISNS_SSDS4_R

BOM OPTIONREFERENCE DESIGNATOR(S)

GND_SMC_AVSS

SSD:Y

R5415

4.53K

1 2

1%

1/20W

MF

201

TABLE_5_HEAD

TABLE_5_ITEM

ISNS_SSDS4

OMIT_TABLE

U5000.A7:12.7mm

1

C5415

0.22UF

20%

6.3V

2

X5R 0201

GND_SMC_AVSS

43 44 47 76

44 76

OUT

43 44 47 76

B

A

PAGE TITLE

I and V Sense

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/05/2013SYNC_MASTER=J70_NICK

051-00081

3.0.0

54 OF 123

47 OF 81

A

D

Temperature Sensor T1

345678

2 1

D

LPDDR3 Proximity

3

CRITICAL

1

Q5610

BC846BLP

DFN1006H4-3

2

PLACEMENT_NOTE=Place Q5610 between U2400 and U2500

CPU Proximity

3

CRITICAL

1

Q5612

BC846BLP

DFN1006H4-3

2

PLACEMENT_NOTE=Place Q5612 underneath CPU

Q5610.3:2MM

1

C5610

2.2PF

+/-0.1PF 25V

2

NP0-C0G-CERM 0201

Q5612.3:2MM

1

C5612

2.2PF

+/-0.1PF 25V

2

NP0-C0G-CERM 0201

SNS_T1_1_P

SNS_T1_1_N

SNS_T1_2_P

SNS_T1_2_N

AC/DC

Diode on supply

L5614

FERR-220-OHM

76 48

0402

76 56

IN

SNS_ACDC_P

SNS_ACDC_N

L5615

FERR-220-OHM

76 48

0402

21

L5614.2:2MM

1

C5614

0.0022UF

10% 50V

2

CERM

21

402

SNS_T1_3_P

SNS_T1_3_N

76 48

D

66 48 47 33 32

76 48

=PP3V3_S0_SENSE

CRITICAL

1

VDD

1

C5600

1UF

10% 10V

2

X5R 402-1

1

R5600

10K

5% 1/16W MF-LF 402

2

U5600

EMC1414-1-AIZL

76 48

LPDDR3 (TM0p)

CPU Prox (TC0p)

AC/DC (Tp2h)

76 48

SNS_T1_1_P

SNS_T1_1_N

SNS_T1_2_P

MAKE_BASE=TRUE

SNS_T1_2_N

MAKE_BASE=TRUE

SNS_T1_3_P

SNS_T1_3_N

NOSTUFF

U5600.4:2MM

C5604

47PF

5% 50V CER

0402

NOSTUFF

1

2

U5600.5:2MM

1

C5605

47PF

5% 50V

2

CER 0402

2

DP1

3 8

DN1

4

DP2/DN3

5

DN2/DP3

MSOP

THERM*/ADDR

ALERT*

SMDATA

SMCLK

GND 6

7

NC

SNS1_ALERT_L

9

=SMB_SNS1_SDA

10

=SMB_SNS1_SCL

I2C Address (EMC1414-1):

0x98 (Write)

0x99 (Read)

46

BI

46

IN

C

PART NUMBER

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

ALL372S0185372S0186 Alternate Temp Diode

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Temperature Sensor T2

Filter Caps: Stuff if needed for PSU sensor SI

Note:

Internal sensor of the EMC 1414

will be used as the ambient sensor.

Place U5600 at the coolest location

on the MLB.

C

B

TBT On Die

26

OUT

BLC Proximity

3

TEMPSNSDEV CRITICAL

1

Q5664

BC846BLP

DFN1006H4-3

2

PLACEMENT_NOTE=Place Q5664 near BLC controller

NO_XNET_CONNECTION=1

PLACE_NEAR=U2800.AA8:5MM

XW5660

SM

21

MAKE_BASE=TRUE

SNS_T2_1_PTBT_THERM_DP

NO_XNET_CONNECTION=1

TEMPSNSDEV

1

C5660

2.2PF

+/-0.1PF 25V

2

NP0-C0G-CERM 0201

SNS_T2_1_N

PLACE_NEAR=XW5660.2:2MM

SNS_T2_3_P

TEMPSNSDEV

PLACE_NEAR=Q5664.3:2MM

1

C5664

2.2PF

+/-0.1PF 25V

2

NP0-C0G-CERM 0201

SNS_T2_3_N

76 48

B

TBT Die 1 (TI0p)

76 48

MLB Prox 2 (Tm2p)

76 48

BLC Prox (Tb0p)

76 48

SNS_T2_1_P

SNS_T2_1_N

SNS_T2_2_P

NO_XNET_CONNECTION=1

SNS_T2_2_N

SNS_T2_3_P

NO_XNET_CONNECTION=1

SNS_T2_3_N

NO_XNET_CONNECTION=1

OMIT

U5650.4:2MM

XW5651

SM

OMIT

U5650.4:2MM

XW5652

SM

OMIT

U5650.4:2MM

XW5653

SM

21

48 47 33 32

SNS_T2_DXN

66

=PP3V3_S0_SENSE

1

DXP1

2

DXP2

3

DXP3

4

DXN

CRITICAL TEMPSNSDEV

8

V+

U5650

TMP423

SOT23-8

GND

5

SCL

SDA

TEMPSNSDEV

1

C5650

1UF

10% 10V

2

X5R 402-1

7

=SMB_SNS2_SCL

6

=SMB_SNS2_SDA

I2C Address (TMP432B):

0x9A (Write)

0x9B (Read)

46

IN

46

BI

A

MLB Misc 0

SNS_T2_2_P

TEMPSNSDEV

3

TEMPSNSDEV CRITICAL

1

Q5665

BC846BLP

DFN1006H4-3

2

PLACEMENT_NOTE=PLACE Q5665 near CPU

PLACE_NEAR=Q5665.3:2MM

1

C5662

0.0022UF

10% 50V

2

CERM 402

SNS_T2_2_N

8 7 5 4 2 1

76 48

www.qdzbwx.com

36

PAGE TITLE

Temperature Sensors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

DRAWING NUMBER SIZE

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=11/05/2013SYNC_MASTER=J70_NICK

051-00081

3.0.0

56 OF 123

48 OF 81

A

D

345678

2 1

D

C

B

Note:

The circuit for the PWM input to

the fan acts as a non-inverting

level-shifter to protect the SMC.

It is assumed there is a pull-up to

5V/12V inside the fan, otherwise

when the SMC PWM goes low and Q6010

turns on, there would be 5V/12V

present on the SMC pin! Then by

definition, the drain of Q6010 is

at common and the SMC sinks current

when Q6010 is on.

This resembles an open-drain if

there is a pull-up, going to a Hi-Z

FET input.

Otherwise, this is simply a pass-FET. See RADAR: 10565825- D7: Need scematic and PCB file of fan(All Vendors).

66 49 44 43

=PP12V_S0_FAN

66

=PP3V3_G3H_SMC

=PP3V3_S0_FAN

66 49

76 43

IN

SMC_FAN_0_CTL

SMC Fan 0 (System)

L6000

220-OHM-1.4A

1

C6000

4.7UF

10% 16V

2

X7R-CERM 1206

SEE RADAR:12960082 J16/J17 CONNECT GATE OF FAN PWM FET TO PP3V42_G3H

1

R6010

10K

5% 1/16W MF-LF 402

2

1

C6001

0.01UF

20% 16V

2

X7R-CERM 0402

CRITICAL

Q6010

SSM3K15AMFVAP

1

G

2

S

SOD

D

FAN_0_PWM_FET

3

1

C6010

100PF

5% 50V

2

C0G 0402

0603

CRITICAL

L6010

FERR-220-OHM

0402

CRITICAL

C

21

VOLTAGE=12V MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2500

518S0730

CRITICAL

J6000

53780-8604

M-RT-SM

5

MIN_LINE_WIDTH=0.5000 MIN_NECK_WIDTH=0.2500

21

FAN_0_PWM_FILT FAN_0_TACH_FILT

PP12V_S0_FAN_0_FILT

1

2

3

4

6

Tach

GND

12V DC

B

66 49 44 43

=PP3V3_G3H_SMC

66 49

K

D6020

BAS316DG

SOD323-SM

A

=PP3V3_S0_FAN

1

R6026

47K

5% 1/16W MF-LF 402

2

R6020

76 43

OUT

SMC_FAN_0_TACH

PLACE_NEAR=U5000.L13:5MM

1

C6020

1000PF

10% 16V

2

X7R-1 0201

47K

1/16W MF-LF

Add C6020 1000pF Cap, Change R6020 to 47K -- Radar 11661918 D8 Proto1 Fan Tach instability.

5%

402

21

FAN_0_TACH_FET

1

C6021

100PF

5% 50V

2

C0G 0402

L6021

FERR-220-OHM

21

0402

CRITICAL

A

SMC Fan 1 (Unused)

SYNC_MASTER=J16_MLB_IG

PAGE TITLE

System Fan

DRAWING NUMBER SIZE

43

IN

OUT

SMC_FAN_1_CTL

SMC_FAN_1_TACH

www.qdzbwx.com

8 7 5 4 2 1

NC_SMC_FAN_1_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_1_TACH

MAKE_BASE=TRUE

NO_TEST=1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

36

SYNC_DATE=08/27/2013

051-00081

D

3.0.0

60 OF 123

49 OF 81

A

D

C

B

GND_AUDIO_CODEC

50

BYPASS=U6201.A8:B10:5 mm

CRITICAL

C6222

15UF

0402

20%

4V

X5R

1

2

50

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0700

MIN_NECK_WIDTH=0.0700 MIN_LINE_WIDTH=0.2000

GND_AUDIO_CODEC

4.5V POWER SUPPLY FOR CODEC

CRITICAL

C6219

15UF

20%

4V

X5R

0402

CODEC_FLYP

CODEC_FLYN

R6206

2.21K

1/20W

1%

MF

201

21

C6220

1UF

21

10% 25V X5R 402

345678

2 1

AUDIO CODEC, ANALOG BLOCKS

APPLE P/N 353S4080

PP3V3_S0_AUDIO_ANALOG

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.1000 VOLTAGE=3.3V

BYPASS=U6201.N13:M11:7 mm

C6218

0.1UF

X7R-CERM

CRITICAL

C6215

21

TANT-POLY

0805-LLP-1

BYPASS=U6201.H12:H13:5 mm

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0700

C6227

0.1UF

10% 16V X5R-CERM 0201

21

C6228

0.1UF

10% 16V X5R-CERM 0201

21

C6226

0.1UF

10% 16V X5R-CERM 0201

AUD_HSBIAS_IN

AUD_HSBIAS

21

AUD_HSBIAS_REF

CRITICAL

1

C6221

4.7UF

20% 10V

2

X5R-CERM 0402

1

10UF

20% 16V

2

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.0700

VREF_DAC

VHP_FILTN

CODEC_LINEIN

CODEC_MICIN1

CODEC_MICIN2

AUD_HSBIAS_FILT

NC

H13

VREF_DAC

A11

VHP_FILT-

A8

FLYP

B10

FLYN

B11

FLYN

N10

LINEIN_L+

M10

LINEIN_L-

N9

LINEIN_R+

M9

LINEIN_R-

L8

MICBIAS1_L

L7

MICBIAS1_R

L5

MICBIAS2_L

L4

MICBIAS2_R

N8

MICIN1_L+

M8

MICIN1_L-

N7

MICIN1_R+

M7

MICIN1_R-

N5

MICIN2_L+

M5

MICIN2_L-

N4

MICIN2_R+

M4

MICIN2_R-

L12

HSBIAS_IN

L13

HSBIAS

M13

HSBIAS_REF

N11

HSBIAS_FILT

AGND

L6

M11

H12A1A9

VA_REF

U6201

CS4208-CRZR

VFBGA

ANALOG

SYM 1 OF 2

AGND

L9

L10

N13

VA

VA_HP

HPGND

C8

A10

VA_PLL

HPGND

D13

C10

PLLGND

HSGND

A2

1

10% 16V

2

0402

HPOUT_L

HPOUT_R

SENSE_A1 SENSE_A2

HS3

HS4 HS3_REF HS4_REF

HSIN+

HSIN-

SENSE_B1 SENSE_B2

SENSE_C SENSE_D

LINEOUT1_L+

LINEOUT1_L-

LINEOUT1_R+

LINEOUT1_R-

LINEOUT2_L+

LINEOUT2_L-

LINEOUT2_R+

LINEOUT2_R-

LINEOUT3_L+

LINEOUT3_L-

LINEOUT3_R+

LINEOUT3_R-

LINEOUT4_L+

LINEOUT4_L-

LINEOUT4_R+

LINEOUT4_R-

VCOM

VREF_ADC

A12

A13

C11

D12

C13

C12

B13

B12

N6

55

CODEC_HS_MIC_P

M6

CODEC_HS_MIC_N

55

E11

D11

M3

L3

E12

E13

F11

F12

F13

G11

G12

G13

H11

J11

J12

J13

K11

K12

K13

L11

M12

N12

C6216

0.1UF

X7R-CERM

BYPASS=U6201.H12:L10:8 mm

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000

GND_AUDIO_CODEC

AUD_TYPEDET

AUD_SENSE_D

NC

CODEC_VCOM

CODEC_VREF_ADC

CRITICAL

C6210

1UF-10OHM

0603-LLP

10% 16V

0402

20% 25V

TANT

1

2

1

2

CRITICAL

1

C6217

10UF

20% 16V

2

TANT-POLY 0805-LLP-1

50

54

IN

1

R6211

100K

1% 1/16W MF-LF 402

2

AUDIO_DP_SNS:N

GND_AUDIO_CODEC

CRITICAL

1

C6211

10UF

20% 16V

2

TANT-POLY 0805-LLP-1

GND_AUDIO_CODEC

MIN_NECK_WIDTH=0.2000MIN_LINE_WIDTH=0.4000

50

C6224

6

1

PLACE CLOSE TO CODEC

GND_AUDIO_CODEC

PP4V5_AUDIO_ANALOG

64 50

C6214

0.1UF

X7R-CERM

0402

50

C6212

0.1UF

10% 16V

X7R-CERM

0402

1UF

21

10% 25V

402

X5R

PP4V5_AUDIO_ANALOG

1

R6210

100K

1% 1/16W MF-LF 402

2

AUDIO_DP_SNS:Y

D

GND_AUDIO_CODEC

C6225

1UF

21

10% 25V X5R 402

Q6210

DMN5L06VK-7

SOT563

AUDIO_DP_SNS:Y

VER 3

2

GS

DP_TBT_SEL_L

50

10% 16V

1

2

1

BYPASS=U6201.A1:A2:5 MM

2

AUD_HP_PORT_REFUS

AUD_HP_PORT_REFCH

64 50

50

CRITICAL

1

C6213

10UF

20% 10V

2

X5R-CERM 0402-1

4.5V COMPARATOR

CRITICAL

L6201

120-OHM-25%-1.3A

21

0402

AUD_TIPDET_1

AUD_TIPDET_2

AUD_US_HS_GND

AUD_CH_HS_GND

HS_MIC_P

HS_MIC_N

=PP3V3_S5_PCH_GPIO

1

R6212

100K

1% 1/16W MF-LF 402

2

AUDIO_DP_SNS:Y

Q6210

3

4

PLACE CLOSE TO PCH

DMN5L06VK-7

D

SOT563

AUDIO_DP_SNS:Y

VER 3

5

GS

DP_TBT_SEL

55 50

=PP3V3_S0_AUDIO

GND_AUDIO_CODEC

54

IN

54

IN

55 54

55 50

HS_MIC_P

HS_MIC_N

AUD_HP_PORT_LEFT

AUD_HP_PORT_RIGHT

1%

1/20W

MF

201

IN

1

2

40 13

R6208

2.21K

66 15 13

66 37

50

OUT

1

R6209

2.21K

1% 1/20W MF 201

2

GND_AUDIO_CODEC

MIC FILTER

100K

5%

1/20W

MF

201

1

2

1

2

R6256

54

CRITICAL

C6250

3300PF

10% 10V X7R-CERM 0201

50

R6250

2.2K

5% 1/16W MF-LF

402

R6259

2.2K

5% 1/16W MF-LF

402

D

C

21

AUD_HS_MIC_P

IN

55 54

B

CRITICAL

1

C6251

27PF

5% 25V

2

C0G 0201

21

R/C6550 FILTER TO ADDRESS OUT-OF-BAND

NOISE ISSUE SEEN ON EARLY HEADSETS

(SEE RADAR # 6210118)

AUD_HS_MIC_N

IN

55 54

A

64

=PP5V_S4_AUDIO

66

IN

R6207

5%

1/16W

APPLE P/N 353S2456

L6200

FERR-22-OHM-1A-0.055OHM

21

0

21

MF-LF 402

PM_EN_REG_P4V5_S0_RPM_EN_REG_P4V5_S0

0201

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500 VOLTAGE=5V

PP5V_S4_AUDIO_FLT

NOSTUFF

1

C6200

0.1UF

20% 10V

2

X7R-CERM 0402

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

1

C6201

1UF

10% 10V

2

X5R 402-1

XW6200

6

IN

4

EN

SM

U6200

TPS71745

SON

CRITICAL

GND

2

21

OUT

NR/FB

NC

1

3

4V5_NR

5

CRITICAL

C6202

0.01UF

10% 25V

X5R-CERM

0201

PP4V5_AUDIO_ANALOG

VOLTAGE=4.5V MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

64 50

CRITICAL

1

2

1

C6203

1.0UF

20% 10V

2

X5R-CERM 0201-1

R1

R6270

GND_AUDIO_CODEC

VOLTAGE=0V MIN_LINE_WIDTH=0.5000

MIN_NECK_WIDTH=0.1500

50

PP4V5_AUDIO_ANALOG

64 50

Vref = 0.80V * (R1+R2)/R2 = 4.25V

100K

1% 1/16W MF-LF

402

R2

21

COMP_P4V5_VREF

1

R6271

23.2K

1% 1/16W MF-LF 402

2

www.qdzbwx.com

GND_AUDIO_CODEC

50

=PP5V_S4_PWRCTL

66 63

COMP_P4V5_GATE

Q6270

DMB53D0UV

SOT-563

R6272

10K

5% 1/16W MF-LF

402

5

1

PM_PGOOD_REG_P4V5_S0

2

6

D

2

G

3

S

1

4

PLACE_NEAR=U6200.2:25MM

Q6270

DMB53D0UV

SOT-563

OUT

64

PAGE TITLE

AUDIO: Codec (Analog)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=05/05/2014SYNC_MASTER=J117_GAREN

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

62 OF 123

SHEET

50 OF 81

A

8 7 5 4 2 1

36

D

C

55 52

MCLKA_SPKR_LEFT

OUT

SCLKA_SPKR_LEFT

OUT

LRCLKA_SPKR_LEFT

OUT

SDOUTA_SPKR_LEFT

OUT

R6350

33

21

1%

1/20W

MF

201

R6353

33

1%

1/20W

MF

201

=PP1V5_S0_AUDIO_DIG

66

R6351

33

21

1%

1/20W

MF

201

R6352

33

21

1%

1/20W

MF

21

201

L6300

FERR-22-OHM-1A-0.055OHM

21

0201

C6300

4.7UF

20% 4V X5R-1 402

66 54 51

55 53 52 51

=PP3V3_S0_AUDIO_DIG

CODEC_SDA

CODEC_SCL

53 52

54

74 12

OUT

SPKR_AMP_SD

SPKR_AMP_FAULT

IN

AUD_CONN_SPKR_VENDOR_ID_LEFT

AUD_CONN_SPKR_VENDOR_ID_RIGHT

DFET_OPENUS

DFET_OPENCH

HDA_BIT_CLK

IN

HDA_SYNC

IN

HDA_SDIN0

HDA_SDOUT

IN

HDA_RST_L

1

2

2 1

1

C6301

0.1UF

10% 16V

2

X7R-CERM 0402

BYPASS=U6201.J2:J1:13 mm

1

R6358

1K

1% 1/16W MF-LF 402

2

R6341

0

5%

1/20W

0201

MF

R6343

2 1

5% MF

PP1V5_S0_AUDIO_DIG_FILT

MIN_LINE_WIDTH=0.6000

MIN_NECK_WIDTH=0.0700

VOLTAGE=1.5V

1

R6359

1K

1% 1/16W MF-LF 402

2

1

R6324

100K

5% 1/20W MF 201

2

R6340

0

2 1

5%

1/20W

0201

MF

R6342

22

21

5%

1/20W

201

0

1/20W

0201

MF

1

R6325

100K

5% 1/20W MF 201

2

1

R6326

47.0K

1% 1/16W MF-LF 402

2

HDA_BIT_CLK_PORT

HDA_SYNC_PORT

CS4208_HDA_SDOUT0_R

NC_CS4208_HDA_SDOUT1

HDA_SDOUT_PORT

1

2

1

R6327

47.0K

1% 1/16W MF-LF 402

2

55

MCLKA_SPKR_LEFT_R

55

SCLKA_SPKR_LEFT_R

55

LRCLKA_SPKR_LEFT_R

55

SDOUTA_SPKR_LEFT_R

55

MCLKB_SPKR_RIGHT_R

55

SCLKB_SPKR_RIGHT_R

55

LRCLKB_SPKR_RIGHT_R

55

SDOUTB_SPKR_RIGHT_R

BYPASS=U6201.E1:F1:11 mm

C6302

0.1UF

10% 16V X7R-CERM 0402

H3

GPIO0

H2

GPIO1

H1

GPIO2

C4

GPIO3

C5

GPIO4

C7

GPIO5

C9

NC

GPO0

B9

GPO1

F2

BCLK

E2

SYNC

D1

SDI0

C1

SDI1

D2

SDO0

C2

SDO1

C3

SDO2

B1

SDO3

D3

RST*

A5

MCLK_A

B2

SCLK_A

B4

LRCK_A

A3

SDOUT_A

B3

SDIN_A

A6

MCLK_B

B6

SCLK_B

B5

LRCK_B

B8

SDOUT_B

A4

SDIN_B

AUDIO CODEC, DIGITAL BLOCKS

APPLE P/N 353S4080

BYPASS=U6201.G1:F1:12 mm

1

C6303

0.1UF

10%

6.3V

2

CERM-X5R 0201

A7

J2

VD

VL_HD

U6201

CS4208-CRZR

VFBGA

DIGITAL

SYM 2 OF 2

G1E1K1

VL_IF

VL_SP

VL_DM

SPDIF_IN

SPDIF_OUT

DMIC_SDA0

DMIC_SCL0

DMIC_SDA1

DMIC_SCL1

DMIC_SDA2

DMIC_SCL2

DMIC_SDA3

DMIC_SCL3

NC NC NC NC NC NC NC NC NC

G3

G2

N3

N2

N1

M1

M2

L1

K2

L2

F6

F7

F8

G6

G7

G8

H6

H7

H8

BYPASS=U6201.K1:K3:6 mm

1

C6304

0.1UF

10%

6.3V

2

CERM-X5R 0201

74

CS4208_SPDIF_IN

74

CS4208_SPDIF_OUT

NC

345678

C6305

10UF

20% 10V X5R-CERM 0402-1

1

2

DMIC_SDA3_R

DMIC_CLK3_R

=PP3V3_S0_AUDIO_DIG

C6306

10UF

20% 10V X5R-CERM 0402-1

R6302

0

2 1

1/20W

5%

0201

MF

R6333

2 1

5% MF

1

2

0

1/20W

0201

2 1

66 54 51

BYPASS=U6201.A7:E3:6 mm

1

C6307

0.1UF

10%

6.3V

2

CERM-X5R 0201

DP_INT_SPDIF_AUDIO

R6330

33

5% 1/16W MF-LF

402

R6332

75

21

1% 1/16W MF-LF

402

=PP3V3_S0_AUDIO_DIG

21

SPDIF_OUT_JACK

DMIC_SDA3

DMIC_CLK3

IN

OUT

66 54 51

IN

OUT

D

80 74 39

74 54

37

C

B

55 53

MCLKB_SPKR_RIGHT

OUT

SCLKB_SPKR_RIGHT

OUT

LRCLKB_SPKR_RIGHT

OUT

SDOUTB_SPKR_RIGHT

OUT

R6360

33

1%

1/20W

MF

201

R6363

33

21

1%

1/20W

MF

201

21

R6361

R6362

33

1%

1/20W

MF

201

33

1%

1/20W

MF

201

55 53 52 51

21

OUT

CODEC_SDA

CODEC_SCL

C6

B7

SDA SCL

DGND

J1

LGND

F1

E3

LGND

F3

LGND

J3

K3

LGND

B

A

PAGE TITLE

AUDIO:CODEC, DIGITAL

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=05/05/2014SYNC_MASTER=J117_GAREN

051-00081

3.0.0

63 OF 123

51 OF 81

A

D

345678

2 1

D

2X MONO SPEAKER AMPLIFIERS (TAS5758L)

=PP3V3_S0_AUDIO_SPKRAMP

53 52

66

53 52 51

55 53 52 51

55 52 51

SPKR_AMP_SD

IN

SPKR_AMP_FAULT

OUT

IN

CODEC_SCL

CODEC_SDA

SDOUTA_SPKR_LEFT

LRCLKA_SPKR_LEFT

SCLKA_SPKR_LEFT

NOSTUFF

R6404

ADDRESS 0X6C

R6405

MCLKA_SPKR_LEFT

1/16W MF-LF

22K

5%

402

5%

1/20W

MF

0201

21

C6400

1

1UF

10% 10V X5R

402-1

1

2

0

2

AUD_LAMP_LT_ADR

C6401

X7R-CERM

3

13 12

8 9

2

7

4

6 5

0.1UF

20% 10V

0402

SDZ*

ADR0 ADR1

SCL SDA

FAULTZ*

SDI

FSYNC

SBCLK MCLK

1

2

28

AVDD

GND

10

AUD_LAMP_LT_GVDD

15

14

30

11

GVDD

PVDD

DVDD

U6400

TAS5758L

QFN

PGND

GND

21

20

19

29

26

PVDD

PGND

22

APN: TBD GAIN = TBD

27

PVDD

BST_P

OUT_P OUT_P

OUT_N OUT_N

BST_N

VCOM

VREF_N

VREG

THRM_PAD

33

C6402

1.0UF

20% 10V

X5R-CERM

0201-1

23

24 25

16 17

18

32

AUD_LAMP_LT_VCOM

1

AUD_LAMP_LT_VREFN

31

AUD_LAMP_LT_VREG

21

C6406

1UF

21

10% X5R 0402

25V

C6403

0.1UF

10% 25V X5R 402

C6407

1UF

10% 25V X5R 0402

SPEAKER AMPLIFIERS - LEFT CHANNEL

66 53 52

=PP12V_S0_AUDIO_SPKRAMP

66 53 52

CRITICAL

20% 16V

POLY

SM

1

2

1

2

1

C6404

1UF

10% 25V

2

X5R 603-1

C6405

470UF

NOTE: AUD_LAMP_BOOTLT<P/N> DO NOT NEED TO BE TREATED AS DIFFERENTIAL SIGNALS AS LONG AS BOOTSTRAP CAPS C6408 AND C6409 ARE PLACED CLOSE TO U6400

C6408

AUD_LAMP_BOOTLTP

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

0.22UF

21

20% 25V X5R 603

CKPLUS_WAIVE=MISS_N_DIFFPAIR

55

CRITICAL

L6400

180OHM-3.4A

0806

CKPLUS_WAIVE=MISS_N_DIFFPAIR

21

AUD_SPKR_LTWT_OUT_PAUD_SPKR_LTWT_OUT_L_P

C6409

0.22UF

CRITICAL

L6401

180OHM-3.4A

0806

21

AUD_SPKR_LTWT_OUT_MAUD_SPKR_LTWT_OUT_L_M

20% 25V X5R 603

21

55

AUD_LAMP_BOOTLTN

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

21

=PP12V_S0_AUDIO_SPKRAMP

C6420

10UF

10% 25V X5R 805

1

2

1

C6421

10UF

10% 25V

2

X5R 805

D

OUT

55 54

C

B

=PP3V3_S0_AUDIO_SPKRAMP

53 52

66

53 52 51

55 53 52 51

55 52 51

SPKR_AMP_SD

IN

OUT

IN

NOSTUFF

R6414

22K

1/16W MF-LF

402

ADDRESS 0X6D

R6415

22K

1/16W MF-LF

402

SPKR_AMP_FAULT

CODEC_SCL

CODEC_SDA

SDOUTA_SPKR_LEFT

LRCLKA_SPKR_LEFT

SCLKA_SPKR_LEFT

MCLKA_SPKR_LEFT

C

=PP12V_S0_AUDIO_SPKRAMP

21

C6413

0.1UF

1UF

10% 10V X5R

402-1

1

C6411

0.1UF

2

X7R-CERM

5%

21

5%

C6410

20% 10V

0402

1

2

28

AVDD

AUD_LAMP_LW_GVDD

15

14

30

11

PVDD

GVDD

PVDD

DVDD

27

26

PVDD

C6412

1.0UF

21

20% 10V

X5R-CERM

0201-1

10% 25V X5R 402

1

2

1

C6414

1UF

10% 25V

2

X5R 603-1

U6410

GND

10

GND

29

TAS5758L

QFN

PGND

22

21

20

19

PGND

THRM_PAD

33

BST_P

OUT_P OUT_P

OUT_N OUT_N

BST_N

VCOM

VREF_N

VREG

23

24 25

16 17

18

32

AUD_LAMP_LW_VCOM

1

AUD_LAMP_LW_VREFN

31

AUD_LAMP_LW_VREG

C6416

1UF

21

10% X5R 0402

25V

C6417

1UF

10% X5R

21

25V

0402

AUD_LAMP_LW_ADR

3

13 12

8 9

2

7

4

6 5

SDZ*

ADR0 ADR1

SCL SDA

FAULTZ*

SDI

FSYNC

SBCLK MCLK

66 53 52

NOTE: AUD_LAMP_BOOTLW<P/N> DO NOT NEED TO BE TREATED AS DIFFERENTIAL SIGNALS AS LONG AS BOOTSTRAP CAPS C6418 AND C6419 ARE PLACED CLOSE TO U6410

C6418

AUD_LAMP_BOOTLWP

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

0.22UF

21

20% 25V X5R 603

CKPLUS_WAIVE=MISS_N_DIFFPAIR

AUD_SPKR_LWFR_OUT_L_P

55

AUD_SPKR_LWFR_OUT_L_M

C6419

0.22UF

20% 25V X5R 603

21

AUD_LAMP_BOOTLWN

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

CRITICAL

L6410

180OHM-3.4A

0806

CRITICAL

L6411

180OHM-3.4A

0806

CKPLUS_WAIVE=MISS_N_DIFFPAIR

21

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_LWFR_OUT_M

CRITICAL

1

C6430

330PF

10% 50V

2

CERM 603

CRITICAL

1

C6431

330PF

10% 50V

2

CERM 603

CRITICAL

1

C6432

330PF

10% 50V

2

CERM 603

OUT

CRITICAL

1

C6433

330PF

10% 50V

2

CERM 603

55 54

B

A

www.qdzbwx.com

55 53 52 51

55 52 51

CODEC_SCL

CODEC_SDA

SDOUTA_SPKR_LEFT

LRCLKA_SPKR_LEFT

SCLKA_SPKR_LEFT

MCLKA_SPKR_LEFT

TP6400

P3MM

SM

1

PP

PLACE_NEAR=U6400.8:5 mm

TP6401

P3MM

SM

1

PP

PLACE_NEAR=U6400.9:5 mm

TP6402

P3MM

SM

1

PP

PLACE_NEAR=U6400.7:5 mm

TP6403

P3MM

SM

1

PP

TP6404

P3MM

SM

1

PP

TP6405

P3MM

SM

1

PP

PLACE_NEAR=U6400.4:5 mm

PLACE_NEAR=U6400.6:5 mm

PLACE_NEAR=U6400.5:5 mm

PAGE TITLE

AUDIO: SPEAKER AMP, LEFT CHANNEL

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=05/05/2014SYNC_MASTER=J117_GAREN

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

64 OF 123

SHEET

52 OF 81

A

8 7 5 4 2 1

36

345678

2 1

D

C

66 53 52

55 53 52 51

2X MONO SPEAKER AMPLIFIERS (TAS5758L)

=PP3V3_S0_AUDIO_SPKRAMP

22K

5%

402

22K

5%

402

21

C6500

21

AUD_RAMP_RT_ADR

1UF

10% 10V X5R

402-1

1

2

13 12

53 52 51

55 53 51

SPKR_AMP_SD

IN

SPKR_AMP_FAULT

OUT

IN

CODEC_SCL

CODEC_SDA

SDOUTB_SPKR_RIGHT

LRCLKB_SPKR_RIGHT

SCLKB_SPKR_RIGHT

MCLKB_SPKR_RIGHT

R6504

1/16W MF-LF

ADDRESS 0X6E

NOSTUFF

R6505

1/16W MF-LF

C6501

0.1UF

X7R-CERM

3

SDZ*

ADR0 ADR1

8

SCL

9

SDA

2

FAULTZ*

7

SDI

4

FSYNC

6

SBCLK

5

MCLK

20% 10V

0402

1

2

28

AVDD

GND

10

AUD_RAMP_RT_GVDD

15

14

30

11

GVDD

PVDD

DVDD

U6500

TAS5758L

QFN

PGND

GND

21

20

19

29

26

PVDD

PGND

22

APN: TBD GAIN = TBD

27

PVDD

BST_P

OUT_P OUT_P

OUT_N OUT_N

BST_N

VCOM

VREF_N

VREG

THRM_PAD

33

C6502

1.0UF

20% 10V

X5R-CERM

0201-1

23

24 25

16 17

18

32

AUD_RAMP_RT_VCOM

1

AUD_RAMP_RT_VREFN

31

AUD_RAMP_RT_VREG

21

C6506

1UF

21

10% X5R 0402

25V

C6503

0.1UF

10% 25V X5R 402

C6507

1UF

10%

0402X5R

1

2

21

25V

1

C6504

1UF

10% 25V

2

X5R 603-1

CRITICAL

C6505

470UF

20% 16V

POLY

SM

=PP12V_S0_AUDIO_SPKRAMP

1

2

66 53 52

NOTE: AUD_LAMP_BOOTRT<P/N> DO NOT NEED TO BE TREATED AS DIFFERENTIAL SIGNALS AS LONG AS BOOTSTRAP CAPS C6508 AND C6509 ARE PLACED CLOSE TO U6500

C6508

AUD_RAMP_BOOTRTP

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

0.22UF

21

20% 25V X5R 603

CKPLUS_WAIVE=MISS_N_DIFFPAIR

55

C6509

0.22UF

20% 25V X5R 603

21

55

AUD_SPKR_RTWT_OUT_L_M

AUD_RAMP_BOOTRTN

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

SPEAKER AMPLIFIERS - RIGHT CHANNEL

=PP12V_S0_AUDIO_SPKRAMP

C6520

CRITICAL

L6500

180OHM-3.4A

0806

CRITICAL

L6501

180OHM-3.4A

0806

66 53 52

21

CKPLUS_WAIVE=MISS_N_DIFFPAIR

AUD_SPKR_RTWT_OUT_PAUD_SPKR_RTWT_OUT_L_P

AUD_SPKR_RTWT_OUT_M

10UF

10% 25V X5R 805

1

2

1

C6521

10UF

10% 25V

2

X5R 805

D

OUT

55 54

C

B

66 53 52

55 53 52 51

=PP3V3_S0_AUDIO_SPKRAMP

ADDRESS 0X6F

53 52 51

55 53 51

OUT

IN

SPKR_AMP_SD

IN

SPKR_AMP_FAULT

CODEC_SCL

CODEC_SDA

SDOUTB_SPKR_RIGHT

LRCLKB_SPKR_RIGHT

SCLKB_SPKR_RIGHT

IN

MCLKB_SPKR_RIGHT

R6514

1/20W

0201

NOSTUFF

R6515

22K

1/16W MF-LF

402

=PP12V_S0_AUDIO_SPKRAMP

1

C6514

1UF

10% 25V

2

X5R 603-1

10% 25V X5R 402

1

2

0

5%

MF

2

21

5%

C6510

1UF

10% 10V X5R

402-1

1

C6511

0.1UF

2

X7R-CERM

20% 10V

0402

1

2

28

AVDD

AUD_RAMP_RW_GVDD

15

14

30

11

GVDD

PVDD

DVDD

26

PVDD

27

PVDD

C6512

1.0UF

21

20% 10V

X5R-CERM

0201-1

C6513

0.1UF

U6510

GND

10

GND

29

TAS5758L

QFN

PGND

22

21

20

19

PGND

THRM_PAD

33

BST_P

OUT_P OUT_P

OUT_N OUT_N

BST_N

VCOM

VREF_N

VREG

23

24 25

16 17

18

32

AUD_RAMP_RW_VCOM

1

AUD_RAMP_RW_VREFN

31

AUD_RAMP_RW_VREG

C6516

1UF

10% X5R

21

25V

0402

C6517

1UF

21

10% 25V X5R

0402

55 53 52 51

AUD_RAMP_RW_ADR

3

13 12

8 9

2

7

4

6 5

SDZ*

ADR0 ADR1

SCL SDA

FAULTZ*

SDI

FSYNC

SBCLK MCLK

66 53 52

NOTE: AUD_LAMP_BOOTRW<P/N> DO NOT NEED TO BE TREATED AS DIFFERENTIAL SIGNALS AS LONG AS BOOTSTRAP CAPS C6518 AND C6519 ARE PLACED CLOSE TO U6510

C6518

AUD_RAMP_BOOTRWP

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

0.22UF

21

20% 25V X5R 603

55

AUD_SPKR_RWFR_OUT_L_P

55

AUD_SPKR_RWFR_OUT_L_M

C6519

0.22UF

20% 25V X5R 603

21

TP6500

P3MM

SM

1

PP

PLACE_NEAR=U6510.8:5 mm

AUD_RAMP_BOOTRWN

MIN_LINE_WIDTH=0.2000 MIN_NECK_WIDTH=0.1500

CODEC_SCL

CRITICAL

L6510

180OHM-3.4A

0806

CRITICAL

L6511

180OHM-3.4A

0806

CKPLUS_WAIVE=MISS_N_DIFFPAIRCKPLUS_WAIVE=MISS_N_DIFFPAIR

21

AUD_SPKR_RWFR_OUT_P

AUD_SPKR_RWFR_OUT_M

CRITICAL

1

C6530

330PF

10% 50V

2

CERM 603

CRITICAL

1

C6531

330PF

10% 50V

2

CERM 603

CRITICAL

1

C6532

330PF

10% 50V

2

CERM 603

OUT

CRITICAL

1

C6533

330PF

10% 50V

2

CERM 603

55 54

B

A

www.qdzbwx.com

55 53 52 51

55 53 51

CODEC_SDA

SDOUTB_SPKR_RIGHT

LRCLKB_SPKR_RIGHT

SCLKB_SPKR_RIGHT

MCLKB_SPKR_RIGHT

TP6501

P3MM

SM

1

PP

PLACE_NEAR=U6510.9:5 mm

TP6502

P3MM

SM

1

PP

PLACE_NEAR=U6510.7:5 mm

TP6503

P3MM

SM

1

PP

PLACE_NEAR=U6510.4:5 mm

TP6504

P3MM

SM

1

PP

TP6505

P3MM

SM

1

PP

PLACE_NEAR=U6510.6:5 mm

PLACE_NEAR=U6510.5:5 mm

PAGE TITLE

AUDIO: SPEAKER AMP, RIGHT CHANEL

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=05/05/2014SYNC_MASTER=J117_GAREN

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

65 OF 123

SHEET

53 OF 81

A

8 7 5 4 2 1

36

345678

2 1

SPEAKER CONNECTOR

D

51

55 54

IN

AUD_CONN_REFCH

AUD_CONN_CH_HS_GND

AUD_CONN_HS_MIC_P

AUD_CONN_HS_MIC_N

AUD_CONN_US_HS_GND

AUD_CONN_REFUS

DFET_OPENUS

DFET_OPENCH

J6600

54722-0204

F-ST-SM

21

43

65

87

109

1211

1413

1615

1817

2019

AUD_CONN_HP_LEFT

AUD_CONN_HP_RIGHT

SPDIF_OUT_JACK

=PP3V3_S0_AUDIO_DIG

AUD_CONN_TYPEDET

AUD_CONN_TIPDET2

AUD_CONN_TIPDET1

54

CRITICAL

J6601

504050-0691

M-RT-SM

7

55 52

51

55 52

IN

66 51

1

R6600

10K

5% 1/16W MF-LF 402

2

74 51

AUD_SPKR_LWFR_OUT_M

IN

AUD_SPKR_LWFR_OUT_P

IN

AUD_CONN_SPKR_VENDOR_ID_LEFT

IN

AUD_SPKR_LTWT_OUT_M

IN

AUD_SPKR_LTWT_OUT_P

IN

Reversed Phases 1 & 2 and 5 & 6 on J6601 and J6602 Ref J16

1

2

3

4

5

6

8

55 53

51

55 53

AUD_SPKR_RWFR_OUT_M

IN

AUD_SPKR_RWFR_OUT_P

IN

AUD_CONN_SPKR_VENDOR_ID_RIGHT

IN

AUD_SPKR_RTWT_OUT_M

IN

AUD_SPKR_RTWT_OUT_P

IN

CRITICAL

J6602

504050-0691

M-RT-SM

7

1

2

3

4

5

6

8

D

C

55 50

AUD_HP_PORT_REFUS

OUT

AUD_US_HS_GND

OUT

CRITICAL

L6613

120-OHM-25%-1.3A

21

0402

CRITICAL

L6614

120-OHM-25%-1.3A

21

0402

55 50

OUT

AUD_HP_PORT_REFCH

CRITICAL

L6611

120-OHM-25%-1.3A

21

0402

CRITICAL

AUD_CONN_REFCH_XW

55

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000

PLACE_NEAR=J6600.5:8mm

XW6600

SM

21

AUD_CONN_REFCH

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000

L6612

120-OHM-25%-1.3A

55 50

55

AUD_CONN_REFUS_XW

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000 MIN_NECK_WIDTH=0.2000

OUT

AUD_CH_HS_GND

AUD_HS_MIC_P

PLACE_NEAR=J6600.6:8mm

XW6602

SM

0402

XW6601

SM

21

AUD_CONN_CH_HS_GND

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000

AUD_CONN_HS_MIC_P

AUD_CONN_REFUS

MIN_LINE_WIDTH=0.4000

AUD_CONN_US_HS_GND

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.2000

55 54

C

55 54

B

50

AUD_TIPDET_1

OUT

AUD_HP_PORT_RIGHT

IN

AUD_TYPEDET

OUT

CRITICAL

L6607

FERR-470-OHM

21

0201

CRITICAL

L6605

120-OHM-25%-1.3A

21

0402

CRITICAL

L6606

FERR-470-OHM

21

0201

50

IN

OUT

AUD_HP_PORT_LEFT

AUD_TIPDET_2

CRITICAL

L6604

120-OHM-25%-1.3A

21

0402

CRITICAL

L6608

FERR-470-OHM

21

0201

55 50

AUD_HS_MIC_N

OUT

XW6603

SM

21

AUD_CONN_HS_MIC_N

AUD_CONN_HP_LEFT

MIN_LINE_WIDTH=0.4000 MIN_NECK_WIDTH=0.2000

AUD_CONN_TIPDET2

55 54

54

B

AUD_CONN_TIPDET1

AUD_CONN_HP_RIGHT

MIN_LINE_WIDTH=0.4000

MIN_NECK_WIDTH=0.2000

AUD_CONN_TYPEDET

54

A

C6600

100PF

5% 25V C0G

0201

2

1

2

CRITICAL

NOSTUFF

DZ6600

ESDALC5-1BM2

SOD882

CRITICAL

NOSTUFF

DZ6601

ESDALC5-1BM2

SOD882

2

1

C6601

100PF

5% 25V

2

C0G 0201

2

C6602

100PF

1

5% 25V C0G

0201

1

2

1

CRITICAL

NOSTUFF

DZ6602

ESDALC5-1BM2

SOD882

C6603

100PF

5% 25V C0G

0201

2

1

2

CRITICAL

NOSTUFF

DZ6603

ESDALC5-1BM2

SOD882

C6604

100PF

0201

5% 25V C0G

2

CRITICAL

NOSTUFF

DZ6604

ESDALC5-1BM2

SOD882

1

CRITICAL

NOSTUFF

2

DZ6605

2

ESDALC5-1BM2

SOD882

1

C6605

100PF

5% 25V

2

C0G 0201

C6606

100PF

5% 25V C0G

0201

1

2

1

CRITICAL

NOSTUFF

DZ6606

ESDALC5-1BM2

SOD882

CRITICAL

NOSTUFF

DZ6607

ESDALC5-1BM2

SOD882

1

C6607

100PF

5% 25V

2

C0G 0201

2

5% 25V C0G

0201

1

2

C6608

100PF

1

2

1

NOSTUFF

CRITICAL

DZ6608

ESDALC5-1BM2

SOD882

NOSTUFF

CRITICAL

DZ6609

ESDALC5-1BM2

SOD882

1

C6609

100PF

5% 25V

2

C0G 0201

2

5% 25V C0G

0201

1

2

C6610

100PF

1

2

NOSTUFF

CRITICAL

DZ6610

ESDALC5-1BM2

SOD882

SYNC_MASTER=J117_GAREN SYNC_DATE=05/05/2014

PAGE TITLE

A

AUDIO: JACK TRANSLATORS

DRAWING NUMBER SIZE

ESD DIODES (DZ6600 -> DZ6610) NOW NOSTUFF - MAY BE ADDED FOLLOWING ESD TESTING

www.qdzbwx.com

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

66 OF 123

SHEET

54 OF 81

D

8 7 5 4 2 1

36

.

CODEC OUTPUT SIGNAL PATHS

345678

2 1

D

FUNCTION

HP/LINE OUT PRIMARY SPKRS (WFR) SECONDARY SPKRS (TWT)

CODEC INPUT SIGNAL PATHS

FUNCTION

SPDIF IN INTERNAL MIC ARRAY

OTHER DETECT

FUNCTION

MULTIPLE SPKR VENDORS

*AUDIO_ISO

SPKROUT_ISO

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

VOLUME/MUTE

0X03 (3)

CONVERTER

0X03 (3) 0X04 (4) 0X03 (3) N/ASPDIF OUT

0X03 (3) N/A

0X08 (8)

CONVERTER PIN COMPLEX

0X07 (7)

0X06 (6)

0X05 (5)

CONVERTER

N/A

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

0.1 MM

0.2 MM*

* *AUDIO AUDIO_ISO

** SPKROUT_ISOSPKROUT

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

PIN COMPLEX

0X0A (10,D) 0X0B (11) 0X0A (10,V24) 0x10 (16)

MAC SHDN

GPIO_2 MICBIAS MICBIAS N/A N/A

ENABLE/CONTROL

0x0F (15) 0X0E (14,LEFT & RIGHT) N/A

0X12 (18,LEFT)

PIN COMPLEX

N/A

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

AUDIODIFF

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

* 0.1 MM 10 MM0.1 MM

*AUDIODIFF_2MM 0.2 MM 0.1 MM

*

* AUDIODIFFAUDIODIFF

* SPKROUTDIFFSPKROUTDIFF

ALLOW ROUTE

ON LAYER?

N/A

Lynx POINT GPIO 16EXTERNAL MIC 0X06 (6) 0X0D (13,V22,B,LEFT)

ENABLE/CONTROL

N/A

Y

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

WIN SHDN

GPIO_30X04 (4)

MINIMUM LINE WIDTH

DET ASSIGNMENT

0X0A (DET D)GPIO_2 N/A N/A 0X0D (DET B)

DET ASSIGNMENT

0X09 (DET A) N/A

Lynx POINT GPIO 5 (RCVR INT) Lynx POINT GPIO 3 (PERIPH DET)

DET ASSIGNMENT

0X0C (DET C)

10 MM

0.25 MMSPKROUTDIFF 0.6 MM

10 MM

0.1 MM

0.1 MM 0.1 MM

0.2 MM

0.1 MM

0.2 MM

D

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

C

B

ELECTRICAL_CONSTRAINT_SET

SPEAKER OUTPUTS

I205

I203

I220

I219

I333

I332

I330

I331

I337

I336

I334

I335

I341

I340

I338

I339

HEADSET MIC

I344

I345

I254

I255

I324

I325

I343

I342

I354

I355

I368

I369

I356

I357

I371

I370

I373

I372

AUDIO_DIFFPAIR AUDIODIFF AUDIO

NET_TYPE

PHYSICAL

SPKROUTDIFF SPKROUTAUDIO_DIFFPAIR

SPKROUTDIFF SPKROUT

SPKROUTDIFF SPKROUTAUDIO_DIFFPAIR

SPKROUTDIFF SPKROUT

SPKROUTDIFF SPKROUTAUDIO_DIFFPAIR

SPKROUTDIFF SPKROUT

SPKROUTDIFF SPKROUTAUDIO_DIFFPAIR

SPKROUTDIFF SPKROUT

SPACING

SPKROUTSPKROUTDIFFAUDIO_DIFFPAIR

AUDIO

AUD_SPKR_RWFR_OUT_P

AUD_SPKR_RWFR_OUT_M

AUD_SPKR_RWFR_OUT_L_P

AUD_SPKR_RWFR_OUT_L_M

AUD_SPKR_RTWT_OUT_P

AUD_SPKR_RTWT_OUT_M

AUD_SPKR_RTWT_OUT_L_P

AUD_SPKR_RTWT_OUT_L_M

AUD_SPKR_LWFR_OUT_P

AUD_SPKR_LWFR_OUT_M

AUD_SPKR_LWFR_OUT_L_P

AUD_SPKR_LWFR_OUT_L_M

AUD_SPKR_LTWT_OUT_P

AUD_SPKR_LTWT_OUT_M

AUD_SPKR_LTWT_OUT_L_P

AUD_SPKR_LTWT_OUT_L_M

AUD_CONN_HS_MIC_P

AUD_CONN_HS_MIC_N

AUD_HS_MIC_P

AUD_HS_MIC_N

HS_MIC_P

HS_MIC_N

CODEC_HS_MIC_P

CODEC_HS_MIC_N

AUD_CONN_CH_HS_GND

AUD_CONN_US_HS_GND

AUD_CH_HS_GND

AUD_US_HS_GND

AUD_CONN_REFCH

AUD_CONN_REFUS

AUD_CONN_REFCH_XW

AUD_CONN_REFUS_XW

AUD_HP_PORT_REFCH

AUD_HP_PORT_REFUS

53

52

54

50

54

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

CODEC SCL & SDA

54 53

54 52

54 50

I358

I359

TDM

I360

I361

I362

I363

I374

I375

I376

I377

I364

I365

I367

I366

I379

I378

I380

I381

PHYSICAL

SPACING

HDA

CODEC_SCL

CODEC_SDA

MCLKA_SPKR_LEFT

SCLKA_SPKR_LEFT

LRCLKA_SPKR_LEFT

SDOUTA_SPKR_LEFT

MCLKA_SPKR_LEFT_R

SCLKA_SPKR_LEFT_R

LRCLKA_SPKR_LEFT_R

SDOUTA_SPKR_LEFT_R

MCLKB_SPKR_RIGHT

SCLKB_SPKR_RIGHT

LRCLKB_SPKR_RIGHT

SDOUTB_SPKR_RIGHT

MCLKB_SPKR_RIGHT_R

SCLKB_SPKR_RIGHT_R

LRCLKB_SPKR_RIGHT_R

SDOUTB_SPKR_RIGHT_R

C

53 52 51

52 51

51

53 51

51

B

54 50

A

PAGE TITLE

AUDIO: Speaker ID

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

051-00081

3.0.0

68 OF 123

55 OF 81

A

D

3.425V "G3Hot" Regulator

345678

2 1

D

=PP12V_G3H_REG_3V42_G3H

66

SMCREG:SUP

1

R6920

0

5% 1/16W MF-LF 402

2

SUP_P12VG3H_MR_L

Switching freq: 409 kHz =

13.5 L6901

TABLE_ALT_HEAD

PART NUMBER

138S0691 C6905138S0676

SMCREG:SUP

1

C6920

0.1UF

10% 25V

2

X5R 402

CRITICAL

1

C6906

1UF

10% 25V

2

X6S-CERM 0402

CRITICAL

1

C6907

1UF

10% 25V

2

X6S-CERM 0402

CRITICAL

1

C6902

10UF

20% 16V

2

X6S-CERM 0603

C6902/C6908 are mirrored as a provision for acoustic noise

5

VCC

SMCREG:SUP

U6920

RESET*

TPS3847DBVR

4

MR*

SOT23-5

GND

2

NC

1

3

NC

NOSTUFF

1

C6908

10UF

20% 16V

2

X6S-CERM 0603

SMCREG:DIV

1

R6901

150K

1% 1/16W MF-LF 402

2

P3V42G3H_SHDN_R_L

79

SMCREG:DIV

1

R6902

49.9K

1% 1/16W MF-LF 402

2

NOSTUFF

1

C6901

1000PF

5% 25V

2

CERM 0402

R6906

0

21

5% 1/16W MF-LF

402

79

P3V42G3H_SHDN_L

NC

7

6

VIN BOOST

U6900

LT3470AED

DFN

SHDN*

NC

CRITICAL

GND

P3V42G3H_BOOST

79

1

3

48

P3V42G3H_SW

79

SW

2

BIAS

1

FB

THRM

PAD

5

9

P3V42G3H_FB

79

C6903

0.22UF

10% 16V

2

CERM 402

CRITICAL

L6901

33UH

CDPH4D19FHF-SM

21

PP3V42_G3H_REG_R

79

1

C6904

22PF

5% 50V

2

CER-C0G 0402

<Ra>

1

R6905

0

5% 1/16W MF-LF 402

2

1

R6903

348K

1% 1/16W MF-LF 402

2

1

C6905

10UF

20%

6.3V

2

CERM-X5R 0402-1

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

1

C6909

2

10UF

20%

6.3V CERM-X5R 0402-1

TABLE_ALT_ITEM

PP3V42_G3H_REG

Vout = 3.425 250mA max output (Switcher limit)

66

D

C

MLB to AC-DC Connector

CRITICAL

J6900

43650-0603

F-RT-TH

1

2

3

4

5

6

1

2

PP12V_G3H_ACDC

J6900.4:3mm

C6911

10UF

10% 16V X5R-CERM 0805

66

J6900.4:3mm

NOSTUFF

1

C6917

10UF

20% 16V

2

X6S-CERM 0603

J6900.4:3mm

NOSTUFF

1

C6918

10UF

20% 16V

2

X6S-CERM 0603

EMC

J6900.5:4mm

1

C6912

1000PF

5% 25V

2

CERM 0402

EMC

J6900.4:4mm

1

C6913

1000PF

5% 25V

2

CERM 0402

C6917/C6918 are mirrored as a provision for acoustic noise to replace C6911 if

needed

1

R6904

200K

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

1% 1/16W MF-LF 402

2

C6905/C6909 are mirrored as a provision for acoustic noise

C

B

44

OUT

61 44

PWR_BTN

C6914

BURSTMODE_EN_L

IN

1UF

10%

6.3V CERM

402

1

2

C6915

0.1UF

X7R-CERM

0402

R6911

100

1/16W MF-LF

402

10%

16V

1

2

5%

21

R6912

2

1

1K

5% 1/16W MF-LF

402

MLB to AC-DC Supplemental Signal Connector

CRITICAL

J6901

53780-8606

M-RT-SM

7

=PP3V3_S0_VRD

66

1

2

3

4

5

6

SMC_ACDC_ID

8

56 44

D6911

6.8V-100PF

402

21

2

1

76 48

56 44

D6912

6.8V-100PF

402

OUT

PWR_BTN_R

SNS_ACDC_N

SNS_ACDC_P

BURSTMODE_EN_R_L

SMC_ACDC_ID

C6916

1UF

10%

6.3V CERM

402

1

2

1

2

R6913

10K

5% 1/16W MF-LF 402

12V S5 FET

=PP12V_G3H_FET_P12V_S5

66

44 43

IN

SMC_PM_G2_EN IS PULLED DOWN ON SMC PAGE

SMC_PM_G2_EN

1

C6970

0.1UF

10% 16V

2

X7R-CERM 0402

NC

CRITICAL

Q6970

IRFH3702TRPBF

PQFN

D

5

S

1

PP12V_S5_FET

66

B

G

4

FET_EN_P12V_S5

1

VCC

U6970

SLG5AP036

GND

4

TDFN

THRM

PAD

9

G

S

PG

5

D

7

6

8

PM_PGOOD_FET_P12V_S5

OUT

64

2

ON

3

NC

C6971

0.022UF

X7R 10%

2

50V 0402

A

PAGE TITLE

Power Connectors / VReg G3Hot

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

051-00081

3.0.0

69 OF 123

56 OF 81

A

D

345678

2 1

D

C

B

66 17 16 15 8 6

=PP1V05_S0_CPU_VCCST

C7078

PLACE_NEAR=R7079.1:2mm

78 8

BI

78 8

OUT

78 8

78 58

IN

CERM-X5R

CPU_VIDSOUT

CPU_VIDALERT_L

CPU_VIDSCLK

REG_CPUVCC_ISUMP

REG_CPUVCC_ISUMN

REG_CPUVCC_ISEN1

REG_CPUVCC_ISEN2

1

0.1UF

10%

6.3V

2

0201

PLACE_NEAR=U7000.32:2mm

NO_XNET_CONNECTION=1

R7079

54.9

1%

1/20W

MF

201

1

2

C7014

220PF

X7R-CERM

1

R7080

130

1% 1/20W MF 201

2

PLACE_NEAR=U7000.30:2mm

1

10% 25V

2

201

10%

6.3V

0201

1

2

C7013

0.1UF

CERM-X5R

R7036

R7015

1%

1/20W

1

C7010

0.01UF

10% 10V

2

X7R-CERM 0201

95.3K

1/20W

845

201

D

R7001

1

5% 1/16W MF-LF

402

21

C7030

1800PF

10% 10V

X5R-CERM

201

PP5V_S0_REG_CPUVCC_VDD

1

C7001

1UF

10% 10V

2

X5R 402-1

5

NTC

4

VR_HOT*

29

SLOPE

28

PROG1

27

PROG2 PROG3

1

VR_ON

30

SDA

31

ALERT*

32

SCLK

6

COMP

13

RTN

7

FB

8

FB2

15

ISUMP

14

ISUMN

3

IMON

12

ISEN1

11

ISEN2

10

ISEN3

1

2

R7030

100K

1% 1/20W MF 201

2

PP12V_S0_REG_CPUVCC_VIN

78

17

16

VDD VIN

U7000

ISL95826AHRZ-_S2378

CRITICAL

LLP

PAD

THRM

33

FCCM

PWM3 PWM2 PWM1

78

DRSEL

PGOOD

NC NC NC NC

18

23 22 2026

25

2

9 19 21 24

10% 25V X7R

0402

1

2

C7002

0.22UF

FCCM = 1: Forced CCM

FCCM = 0: DCM

FCCM = FLOATING: PS4

REG_CPUVCC_FCCM

NC

REG_PWM_CPUVCC_2

REG_PWM_CPUVCC_1

REG_CPUVCC_DRSEL

REG_CPUVCC_PGOOD

NC

PLACE_NEAR=U7000.17:2mm

CRITICAL

=PP5V_S0_REG_CPUVCC_S0

PLACE_NEAR=U7000.16:2mm

R7035

78

REG_CPUVCC_NTC_R

1

9.31K

1

1%

1/20W

MF

201

21

(GND)

R7037

1%

MF

2

100KOHM

0201

2

1

R7023

16.9K

1% 1/20W MF 201

2

C7015

820PF

21

201

MF

REG_CPUVCC_ISUMN_RC

R7010

255

21

1%

1/20W

MF

201

1

C7011

0.01UF

10% 10V

2

X7R-CERM 0201

10% 25V X7R-CERM

78

REG_CPUVCC_COMP_RC

NO_XNET_CONNECTION=1

21

0201

1

R7022

9.31K

1% 1/20W MF 201

2

C7040

1.2NF

+/-10%

10V

CERM

0201-1

R7040

75K

1/20W

201

1

R7021

21K

1% 1/20W MF 201

2

1

R7020

6.04K

1% 1/20W MF 201

2

71 44 43 6

OUT

REG_CPUVCC_NTC

CPU_PROCHOT_L

REG_CPUVCC_SLOPE

REG_CPUVCC_PROG1

REG_CPUVCC_PROG2

REG_CPUVCC_PROG3

57 8

CPU_VR_EN

R7000

5%

1/16W

0

21

MF-LF

402

CPU_VR_EN_R

REG_CPUVCC_COMP

REG_CPUVCC_RTN

C7016

47PF

21

C0G5%

25V

1

2

1

1%

MF

2

0201

C7041

56PF

5%

25V

NP0-C0G

0201

1

2

NO_XNET_CONNECTION=1

76 47

OUT

REG_CPUVCC_FB

REG_CPUVCC_FB2

(REG_CPUVCC_ISUMP)

REG_CPUVCC_ISUMN_R

CPUVR_IMON

R7002

10

5% 1/16W MF-LF

402

21

=PP12V_S0_REG_CPUVCC_S0

NOSTUFF

OUT

78 58

1

R7025

0

5% 1/20W MF 0201

2

R7024

0

21

5%

1/20W

57

57 8

IN

REG_CPUVCC_PGOOD CPU_VR_READY

57

CPU_VR_EN

MF

0201

1

R7060

10K

5% 1/20W MF 201

2

MAKE_BASE=TRUE

66 58 66 58

C

8

OUT

B

78 8

78 9

R7041

1.37K

NO_XNET_CONNECTION=1

78

CPU_VCCSENSE_P_R

R7043

0

5%

1/20W

MF

0201

21

1

2

C7061

330PF

10% 16V X7R 0201

IN

CPU_VCCSENSE_P

CPU_VCCSENSE_N

1

C7060

330PF

10% 16V

2

X7R 0201

NO_XNET_CONNECTION=1

C7042

100PF

21

5% 25V C0G

0201

NO_XNET_CONNECTION=1

CPU_VCCSENSE_P_RC

XW7061

SM

21

1%

1/20W

MF

201

21

NOSTUFF

R7050

2K

1%

1/20W

MF

201

21

REG_CPUVCC_FB_RC

NOSTUFF

1

C7050

330PF

10% 16V

2

X7R 0201

R7042

1K

2 1

1%

1/20W

MF

201

NO_XNET_CONNECTION=1

www.qdzbwx.com

A

PAGE TITLE

CPU VR12.6 VCC Regulator IC

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

www.qdzbwx.com

8 7 5 4 2 1

36

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=09/17/2013SYNC_MASTER=J70_ROSSANA

051-00081

3.0.0

70 OF 123

57 OF 81

A

D

345678

2 1

D

66 58 57

78 57

78 58 57

66 57

=PP5V_S0_REG_CPUVCC_S0

PHASE 1

IN

REG_PWM_CPUVCC_1

REG_CPUVCC_FCCM

APN:353S3942

=PP12V_S0_REG_CPUVCC_S0

C7110

1UF

10% 16V

X6S-CERM

0402

CRITICAL

6

VCC

U7110

ISL6208D

3

PWM

7

FCCM UGATE

GND

DFN

CRITICAL

THRM

PAD

9

4

BOOT

PHASE

LGATE

C7118/C7119 ARE FOR EMC

CRITICAL

1

C7113

180UF

20%

16V

2

POLY

TH1

CRITICAL

1

C7114

180UF

2

20%

16V POLY

TH1

1

2

NOSTUFF

CRITICAL

C7115

10UF

20% 16V X6S-CERM 0603

1

2

CRITICAL

NOSTUFF

CRITICAL

C7116

10UF

20% 16V X6S-CERM 0603

CRITICAL

1

C7117

1UF

10% 16V

2

X6S-CERM 0402

C7117 and C7137 need to be mirrored.

1

2

NOSTUFF

C7137

1UF

10% 16V X6S-CERM 0402

CRITICAL

1

C7118

2

1UF

10% 16V X6S-CERM 0402

CRITICAL

1

C7119

1UF

10% 16V

2

X6S-CERM 0402

R7110

CRITICAL

1

2

78

REG_UGATE_CPUVCC_1

4

5

D

G

S

CRITICAL

Q7110

SISA18JN_GE3

PWRPAK-SM

321

78

REG_PHASE_CPUVCC_1

NOSTUFF

R7112

2.2

5% 1/10W MF-LF

603

1

2

1

5

8

5

REG_LGATE_CPUVCC_1

78

4

G

D

CRITICAL

Q7111

SISA12JN_GE3

PWRPAK-SM

L7110

0.4UH-20%-23A

PILE063T-SM

152S1821

REG_SNUBBER_CPUVCC_1

NOSTUFF

1

C7112

0.001UF

10% 50V

2

X7R-CERM 0402

21

78

PPCPUVCC_S0_SENSE_1

REG_CPUVCC_ISNS1_P

78

CKPLUS_WAIVE=MISS_N_DIFFPAIR

78

1K

1%

1/20W

MF

201

1

2

R7115

S

0.00075

1%

1W

MTL

0612

21

43

REG_CPUVCC_ISNS1_M

1

R7114

1.00

1% 1/20W MF-LF 0201

2

NO_XNET_CONNECTION=1

1

R7116

200K

1% 1/20W MF 201

2

78

REG_CPUVCC_ISUMN

REG_CPUVCC_ISEN1

REG_CPUVCC_ISUMP

OUT

D

78 58 57

78 57

78 58 57

C

78 57

78 58 57

66 58 57

IN

=PP5V_S0_REG_CPUVCC_S0

PHASE 2

REG_PWM_CPUVCC_2

REG_CPUVCC_FCCM

CRITICAL

6

VCC

U7120

ISL6208D

3

PWM

7

FCCM UGATE

DFN

CRITICAL

C7120

1UF

10% 16V

X6S-CERM

0402

BOOT

R7111

78

REG_BOOT_CPUVCC_1

2 1

C7111

0.22UF

10% 16V

CERM

402

1

2

REG_UGATE_CPUVCC_2

78

2

1

2.2

1/16W MF-LF

21

5%

402

78

REG_BOOT_CPUVCC_1_RC

5

D

4

G

S

CRITICAL

Q7120

SISA18JN_GE3

PWRPAK-SM

321

C7128/C7129 ARE FOR EMC

NOSTUFF

CRITICAL

1

C7126

10UF

20% 16V

2

X6S-CERM 0603

CRITICAL

R7120

0.00075

1%

1W

MTL

0612

1

R7124

1.00

1% 1/20W MF-LF 0201

2

NO_XNET_CONNECTION=1

1

R7126

200K

1% 1/20W MF 201

2

CRITICAL

1

C7127

1UF

10% 16V

2

X6S-CERM 0402

C7127 and C7147 need to be mirrored.

1

2

NOSTUFF

C7147

1UF

10% 16V X6S-CERM 0402

REG_CPUVCC_ISUMN

CRITICAL

1

C7128

1UF

10% 16V

2

X6S-CERM 0402

OUT

CRITICAL

1

C7129

2

78 58 57

1UF

10% 16V X6S-CERM 0402

PPCPUVCC_S0_REG

Vout = 1.85V max 32A max output f = 700kHz

C

66 58

REG_PHASE_CPUVCC_2

78

NOSTUFF

R7122

2.2

5% 1/10W MF-LF

603

CRITICAL

1

C7125

2

NOSTUFF

10UF

20% 16V X6S-CERM 0603

CRITICAL

1

C7123

180UF

20%

16V

2

POLY

TH1

CRITICAL

1

C7124

180UF

2

20%

16V POLY

TH1

L7120

0.4UH-20%-23A

21

78

PPCPUVCC_S0_SENSE_2

PILE063T-SM

152S1821

1

2

REG_SNUBBER_CPUVCC_2

NOSTUFF

1

C7122

0.001UF

10% 50V

2

X7R-CERM 0402

REG_CPUVCC_ISNS2_P REG_CPUVCC_ISNS2_M

78 78

CKPLUS_WAIVE=MISS_N_DIFFPAIR

78

R7125

1K

1%

1/20W

MF

201

2 1

4 3

1

2

5

B

APN:353S3942

GND

4

THRM

PAD

9

PHASE

LGATE

8

5

78

REG_LGATE_CPUVCC_2

4

G

R7121

2.2

78

REG_BOOT_CPUVCC_2

C7121

2 1

5% 1/16W MF-LF

402

78

REG_BOOT_CPUVCC_2_RC

D

S

CRITICAL

Q7121

SISA12JN_GE3

PWRPAK-SM

321

REG_CPUVCC_ISEN2

REG_CPUVCC_ISUMP

OUT

78 57

78 58 57

B

www.qdzbwx.com

0.22UF

21

10% 16V

CERM

402

A

CPU Output Decoupling

66 58

PPCPUVCC_S0_REG

NOSTUFF

CRITICAL

1

C7180

270UF-0.006OHM

20%

2.5V

2

TANT CASE-D2

CRITICAL

1

C7181

270UF-0.006OHM

20%

2.5V

2

TANT CASE-D2

NOSTUFF

CRITICAL

1

C7182

270UF-0.006OHM

20%

2.5V

2

TANT CASE-D2

NOSTUFF

CRITICAL

1

C7183

270UF-0.006OHM

20%

2.5V

2

TANT CASE-D2

CRITICAL

1

C7184

270UF-0.006OHM

20%

2.5V

2

TANT CASE-D2

SYNC_MASTER=J117_ANDRES

PAGE TITLE

CPU VR12.5 VCC Power Stage

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=03/24/2014

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

71 OF 123

SHEET

58 OF 81

A

8 7 5 4 2 1

36

VDDQ 1.2V S3 Regulator

345678

2 1

D

C

18

64

OC trip point:

Switching freq:

IN

PM_EN_LDO_S3_DDRVTT

PM_EN_REG_P1V2_S3

10% 16V

0402

1

2

C7330

0.1UF

X7R-CERM

30.4 A VDDQ =

3 A VTT (FIXED) 10 mA VTTREF (FIXED)

500 kHz

=PP5V_S4_REG_P1V2_S3

66

R7300

MF-LF

10% 16V X5R 603

1

2

1

R7335

1K

2

C7300

2.2UF

R7360

0

5%

1/16W

21

MF-LF

402

R7361

0

21

5%

1/16W

<Ra>

10K

1% 1/16W MF-LF

402

1

2

R7330

<Rb>

20.0K

1% 1/16W MF-LF

402

1

2

R7331

Vout = 1.8V * (Rb / (Ra + Rb))

MF-LF

402

1

C7331

0.01UF

10% 50V

2

X7R-CERM 0402

2.2

5%

1/8W

805

77

1% 1/16W MF-LF 402

R7336 0.65625

8 E5 * Rds(Q7310)

=PP1V2_S3_LDO_DDRVTT

66

1

C7301

10UF

2

20%

6.3V X5R 603

1

2

PP5V_REG_P1V2_V5IN

PM_EN_LDO_S3_DDRVTT_R

PM_EN_REG_P1V2_S3_R

77

REG_P1V2_S3_VREF

77

REG_P1V2_S3_REFIN

77

REG_P1V2_S3_MODE

REG_P1V2_S3_TRIP

77

AGND_P1V2_S3

PGND_REG_P1V2_S3

79

NOSTUFF

C7302

CERM-X5R

0402-1

R7336

60.4K

1/16W MF-LF

402

1

+

L7310 * f(switch)

17 16

6

8

19 18

NOSTUFF

C7303

10UF

6.3V

CERM-X5R

0402-1

V5IN

S3 S5

VREF

REFIN

MODE TRIP

PGND GND

1

20%

2

VLDOIN

CRITICAL

U7300

TPS51916

7

10

1

10UF

20%

6.3V

2

1

1%

2

PLACE_NEAR=U7300.10:5MM

C7302/C7303 are mirrored as a provision for acoustic noise

2

77

VBST

DRVH

SW

1512 14 13

REG_BOOT_P1V2_S3

REG_UGATE_P1V2_S3

77

REG_PHASE_P1V2_S3

QFN

77

DRVL

PGOOD

VDDQSNS

VTT

VTTSNS

VTTREF

11 20 9 3 1

5

REG_LGATE_P1V2_S3

REG_P1V2_S3_PGOOD

77

REG_P1V2_S3_VDDQSNS

PP0V6_S3_DDRVTT_LDO

77

LDO_DDRVTTS0_SNS

77

REG_P1V2_S3_VTTREF

VTT THRM

GND PAD

4

21

OMIT

2

PLACE_NEAR=U7300.21:4.5MM

77

REG_BOOT_P1V2_S3_RC

5% 1/10W MF-LF

603

1

0

2

59

R7316

C7325.1:6MM

10% 16V

CERM

402

1

2

C7327

0.22UF

1

C7316

0.1UF

10% 25V

2

X6S 0402

SM

XW7325

OMIT

CRITICAL

C7326

22UF

20%

6.3V

X5R-CERM-1

603

=PP12V_S5_REG_P1V2_S3

66

CRITICAL

C7310

180UF

20% 16V

POLY

TH1

3

4

5

66

OUT

21

1

2

CRITICAL

1

C7325

22UF

20%

6.3V

2

X5R-CERM-1 603

CRITICAL

1

2

C7311

180UF

20% 16V

POLY

TH1

CRITICAL

Q7310

CSD58889Q3D

Q3D

TG

TGR

BG

VSW

9

1

2

VIN

PGND

EMC

CRITICAL

1

C7342

1UF

10% 25V

2

X6S-CERM 0402

1

Critical:

CRITICAL

1

C7343

1UF

10% 25V

2

X6S-CERM 0402

CRITICAL

1

C7344

10UF

20% 16V

2

X6S-CERM 0603

CRITICAL

1

C7345

10UF

20% 16V

2

X6S-CERM 0603

CRITICAL

Q7310.1:3MM

1

C7346

1UF

10% 25V

2

X6S-CERM 0402

Need copper around Q7310 to sink heat

6 7 8

77

REG_PHASE_P1V2_S3_L

1.0UH-13A-7.8MOHM

CRITICAL

L7310

21

SPM6530T-SM

NOSTUFF

1

C7317

1000PF

5% 25V

2

CERM 0402

REG_SNUBBER_P1V2_S3

77

EMC CRITICAL

Q7310.1:3MM

1

C7347

1UF

10% 25V

2

X6S-CERM 0402

EMC

L7310.2:8MM

1

C7340

1000PF

5% 25V

2

CERM 0402

CRITICAL

1

C7320

270UF-0.006OHM

20% 2V

2

TANT CASE-D2

EMC

L7310.2:8MM

1

C7341

1000PF

5% 25V

2

CERM 0402

CRITICAL

1

C7321

270UF-0.006OHM

20% 2V

2

TANT CASE-D2

1

C7323

10UF

20%

6.3V

2

CERM-X5R 0402-1

PP1V2_S3_REG

NOSTUFF

1

C7324

10UF

20%

6.3V

2

CERM-X5R 0402-1

66

NOSTUFF

1

R7317

0.499

1% 1/10W MF 603

2

R7362

0

21

5% 1/16W MF-LF

402

D

C

B

A

64

OMIT

XW7326

SM

2

XW7300

SM

1

66 64 63 59 39

59

=PP3V3_S4_PWRCTL

REG_P1V2_S3_PGOOD

1

R7340

20K

5% 1/16W MF-LF 402

2

PM_PGOOD_REG_P1V2_S3

MAKE_BASE=TRUE

OUT

64

B

www.qdzbwx.com

=PP3V3_S5_REG_P1V8_S3

66

10% 16V

0201

1

2

C7350

1000PF

X7R-1

R7357

IN

PM_EN_REG_P1V8_S3

1/16W 402

0

5%

C7351 and C7356 must be mirrored.

CRITICAL

1

C7356

10UF

20%

6.3V

2

CERM-X5R 0402-1

21

MF-LF

CRITICAL

1

C7351

10UF

20%

6.3V

2

CERM-X5R 0402-1

REG_P1V8_S3_EN

REG_P1V8_S3_PGOOD

59

1

VIN

U7350

ISL8009B

DFN

2

EN

3

POR

4 5

SKIP

CRITICAL

THRM_PADGND

7

LX

VFB

RSI

9

1.8V S3 REGULATOR

APN:152S1870

L7350

2.2UH-20%-2.0A-0.108OHM

8

6

REG_SW_P1V8_S3

77

SWITCH_NODE=TRUE DIDT=TRUE

REG_FB_P1V8_S3

77

2520-SM

CRITICAL

21

R7358

0

5% 1/16W MF-LF

402

R7350

113K

1%

1/20W

MF

201

<Ra>

R7351

90.9K

1%

1/20W

MF

201

<Rb>

1

2

PP1V8_S3_REG_R

77

1

2

1

2

1

C7352

47PF

5% 25V

2

C0G 0201

Vout = 0.8V * (1 + Ra / Rb)

CRITICAL

1

C7353

22UF

20%

6.3V

2

X5R-CERM-1 603

CRITICAL

C7354

22UF

20%

6.3V

X5R-CERM-1

603

PP1V8_S3_REG

66

Vout = 1.794V Max Current = 1.8A Freq = 1 MHz

CRITICAL

1

C7355

10UF

20%

6.3V

2

CERM-X5R 0402-1

1

2

CRITICAL

1

C7357

10UF

20%

6.3V

2

CERM-X5R 0402-1

C7355 and C7357 must be mirrored.

66 64 63 59 39

REG_P1V8_S3_PGOOD

59

=PP3V3_S4_PWRCTL

1

R7356

33K

5% 1/16W MF-LF 402

2

PM_PGOOD_REG_P1V8_S3

MAKE_BASE=TRUE

OUT

64

PAGE TITLE

VReg VDDQ S3 / 1.8V S3

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=09/12/2013SYNC_MASTER=J70_ROSSANA

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

73 OF 123

SHEET

59 OF 81

A

8 7 5 4 2 1

36

PCH (1.05V) S0 REGULATOR

345678

2 1

D

C

Switching freq:

FSEL STRAP GND

VCC 100k to GND FLOAT

66 60

NO_XNET_CONNECTION=1

PP1V05_S0_REG

XW7411

R7430

R7431

SM

3.01K

1/16W MF-LF

<Rb>

2.74K

1/16W MF-LF

1%

402

1%

402

500 kHz

OC trip point:

12.4 A =

R7450 * 8.5 E-6

DCR(L7410)

SW FREQ 300 kHz

=PP12V_S0_REG_P1V05_S0

66

D

1 MHz 600 kHz

=PP5V_S0_REG_P1V05_S0

66

500 kHz

R7400

1UF

10% 16V X5R 402

77

1

2

3 12

EN

6

FB

4

SREF

8

VO

7

OCSET

9

PGOOD

2

RTN

5

FSEL

2

1

NO_XNET_CONNECTION=1

1

2

1

2

1

R7435

3.01K

1% 1/16W MF-LF 402

2

<Rb>

1

R7436

2.74K

1% 1/16W MF-LF 402

2

NO_XNET_CONNECTION=1

XW7412

SM

REG_P1V05S0_FB_RREG_P1V05S0_RTN_R

64

C7430

10PF

5%

50V CERM 0402

IN

PM_EN_REG_P1V05_S0

1

2

1

2

C7440

0.047UF

X7R-CERM

0402

C7435

10PF

5% 50V CERM 0402

10% 16V

C7400

R7482

0

5%

1/16W

1

2

77 60

21

MF-LF

402

PM_EN_REG_P1V05_S0_R

REG_P1V05S0_FB

77

REG_P1V05S0_SREF

77

REG_P1V05S0_VO

REG_P1V05S0_OCSET

REG_P1V05S0_PGOOD

60

REG_P1V05S0_RTN

77

REG_P1V05S0_FSEL

77

AGND_P1V05S0

NOSTUFF

R7460

1/16W MF-LF

402

5%

1

0

2

1

10

5%

1/8W

MF-LF

805

2

13

U7400

ISL95870

UTQFN

CRITICAL

1

14

PVCCVCC

PGNDGND

16

1

R7401

2.2

5% 1/8W MF-LF 805

2

REG_PVCC_U7400REG_VCC_U7400

BOOT

UGATE

PHASE

LGATE

1

2

11

10

15

77

C7401

2.2UF

10% 16V X5R 603

77

REG_BOOT_P1V05S0

77

REG_UGATE_P1V05S0

77

REG_PHASE_P1V05S0

77

REG_LGATE_P1V05S0

REG_BOOT_P1V05S0_RC

R7416

0

5% 1/10W MF-LF

603

1

2

1

C7416

0.1UF

10% 16V

2

X7R-CERM 0402

77

REG_UGATE_P1V05S0_R

5% 1/10W MF-LF

603

1

0

2

R7411

CRITICAL

Q7410

CSD58873Q3D

3

TG

4

TGR

5

BG

Q3D

9

VIN

VSW

PGND

1

6 7 8

REG_SNUBBER_P1V05S0

77

REG_PHASE_P1V05S0_L

EMC CRITICAL

Q7410.1:3MM

1

C7480

1UF

10% 25V

2

X6S-CERM 0402

NOSTUFF

C7417

0.001UF

10% 50V

X7R-CERM

0402

NOSTUFF

R7417

2.2

1/10W MF-LF

603

1

2

1

2

1

5%

2

CRITICAL

C7410

180UF

20% 16V POLY TH1

1

2

CRITICAL

1

C7411

10UF

20% 16V

2

X6S-CERM 0603

EMC CRITICAL

Q7410.1:3MM

C7481

1UF

10% 25V X6S-CERM 0402

CRITICAL

L7410

1.0UH-13A-7.8MOHM

SPM6530T-SM

1

OMIT

SM

XW7413

2

XW7414

1

2

21

OMIT

SM

CRITICAL

C7412

10UF

20% 16V X6S-CERM 0603

2

1

C7418

1000PF

Note:

1

5%

25V

2

CERM 0402

Regulator requires

a minimum load to

prevent noise in the

audio frequencies

1

2

R7418

200

5% 1/10W MF-LF 603

CRITICAL

1

C7420

330UF-0.009OHM

20% 2V

2

POLY CASE-D2-HF

CRITICAL

1

C7421

330UF-0.009OHM

20% 2V

2

POLY CASE-D2-HF

1

C7423

10UF

20%

6.3V

2

CERM-X5R 0402-1

PP1V05_S0_REG

CRITICAL

1

C7422

330UF-0.009OHM

20% 2V

2

POLY CASE-D2-HF

PP1V05_S0_REG

NOSTUFF

1

C7424

10UF

20%

6.3V

2

CERM-X5R 0402-1

66 60

C

66 60

B

Vout = 0.5 * (1 + Ra / Rb)

U7400.1:1MM

XW7400

SM

2

1

To regulator:

REG_P1V05S0_OCSET

77 60

REG_P1V05S0_VO

77 60

R7451

12.7K

1% 1/16W MF-LF

402

1

C7450

8200PF

10% 50V

2

CERM 603

21

R7450

12.7K

2 1

1% 1/16W MF-LF

402

PLACE_NEAR=R7450.2:3MM

77

REG_P1V05S0_PHASE_SNS_P

CKPLUS_WAIVE=MISS_N_DIFFPAIR

77

REG_P1V05S0_PHASE_SNS_M

=PP5V_S0_PWRCTL

66 64

REG_P1V05S0_PGOOD

60

1

R7480

20K

5% 1/16W MF-LF 402

2

PM_PGOOD_REG_P1V05_S0

MAKE_BASE=TRUE

OUT

64

B

www.qdzbwx.com

A

1.5V S0 REGULATOR

=PP3V3_S4_REG_P1V5_S0

66

=PP1V8_S3_REG_P1V5_S0

66

64

IN

C7490

1UF

10%

6.3V CERM

402

=PP1V8_S3_PWRCTL

66

=PP3V3_S0_PWRCTL

PP1V5_S0_REG

U7490

TPS72015

SON

4

BIAS

6

R7490

0

21

5%

1/16W

1

2

1

C7491

1UF

10%

6.3V

2

CERM 402

MF-LF

402

PM_EN_REG_P1V5_S0_RPM_EN_REG_P1V5_S0

IN

3

EN

THRM

GND

5

PAD

7

OUT

NC

1

2

NC NC NC

1

C7492

2.2UF

10%

6.3V

2

X5R 402

1

C7495

2.2UF

10%

6.3V

2

X5R 402

66

C7493

0.1UF

10% 16V

X7R-CERM

0402

1

2

1

6

VCC

U7491

74AUP1G07GF

SOT891

GND

3

4

YA

5

NCNC

1

R7491

100K

5% 1/16W MF-LF 402

2

1

C7494

0.1UF

10% 16V

2

X7R-CERM 0402

PM_PGOOD_REG_P1V5_S0

Vih = 0.65 x Vcc = 1.17V.

C7492/C7495 are mirrored as a provision for acoustic noise

66

RC Delay on 1.5V PGOOD must be longer than delay on 1.5V EN. This allows for rail voltage to complete transition from Vih min (1.17V) to

1.5V after output shifts to OD.

65

OUT

SYNC_MASTER=J117_ANDRES

PAGE TITLE

VREG 1V05 S0 / 1V5 S0

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=03/24/2014

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

74 OF 123

SHEET

60 OF 81

A

8 7 5 4 2 1

36

D

3.3V S5 Regulator

OC trip point:

Switching freq: 356 kHz =

12.5 A =

R7618 * 10 E-6

DCR(L7610)

1

170 E-12 * R7633

=PP12V_S5_REG_P3V3P5V_S5

66

345678

2 1

5V S4 Regulator

R7658 * 10 E-6

OC trip point:

Switching freq:

14.1 A = DCR(L7650)

1

356 kHz =

170 E-12 * R7673

D

C

B

A

EMC

L7610.1:8MM

66 61

C7622

10UF

20%

6.3V

CERM-X5R

0402-1

PP3V3_S5_REG

66 61

C7640

1000PF

5%

25V CERM 0402

PP3V3_S5_REG

CRITICAL

1

2

C7621

B1A-SM-1

R7690

1/16W

MF-LF

NOSTUFF

C7623

10UF

20%

6.3V

CERM-X5R

0402-1

150UF

5%

402

L7610.1:8MM

1

2

1

20%

6.3V

2

POLY

1

0

2

1

2

CRITICAL

REG_P3V3S5_PHASE_SNS_M

79

NOSTUFF

C7624

10UF

6.3V

CERM-X5R

0402-1

C7623/C7624 are mirrored as a provision for acoustic noise

This circuit toggles the Vreg between PWM and ultrasonic DCM modes based on load requirements

Vreg ModeBURSTMODE_EN_L

PWM0

1

DCM

EMC

C7641

1000PF

5%

25V CERM 0402

C7620

150UF

20%

6.3V POLY

B1A-SM-1

1

20%

2

66 63 61

56 44

1

2

1

2

61

DCR(L7610) = 11.2 MOHM (TYP) / 12.5 MOHM (MAX)

BURSTMODE_EN

=PP5V_S5_PWRCTL

BURSTMODE_EN_L

IN

Check this text note for accuracy

CRITICAL

L7610

2.2UH-20%-8A-0.0112OHM

21

1

OMIT

SM

XW7610

2

C7618

PIMB065T-SM

OMIT

SM

XW7611

2

1

0.01UF

21

X7R-CERM

0402

1

R7619

18.2K

1% 1/16W MF-LF 402

2

10% 16V

REG_SNUBBER_P3V3S5

79

REG_P3V3S5_PHASE_SNS_P

CKPLUS_WAIVE=MISS_N_DIFFPAIR

1

R7618

18.2K

1% 1/16W MF-LF 402

2

(reg_p3v3s4_isen)

(reg_p3v3s4_ocset)

(reg_p3v3s4_vout)

<Ra>

R7630

45.3K

1% 1/16W MF-LF

402

1

2

R7632

976

1% 1/16W MF-LF

402

<Rb>

R7631

10.0K

0.5%

1/16W

MF

402

1

2

C7632

1000PF

5%

25V CERM 0402

Vout = 0.6 * (1 + Ra / Rb)

NOSTUFF

Q7600

SSM6L36FEAPL

SOT563

P-CH

5

G

4

S

2

G

1

S

N-CH

3

D

REG_U7600_FCCM_R

6

61

CRITICAL

C7610

180UF

Q7610.2:3MM

NOSTUFF

C7617

0.001UF

NOSTUFF

R7617

0.499

1

2

1

2

BURSTMODE_EN

1

10% 50V

2

CERM

402

79

1

1%

1/10W

MF

603

2

REG_P3V3S5_VOUT_R

1

20% 16V

2

POLY

TH1

EMC

CRITICAL

1UF

10% 25V

0402

1

2

C7642

X6S-CERM

(reg_phase_p3v3s5)

1

C7616

0.1UF

10% 25V

2

X6S 0402

REG_BOOT_P3V3S5_RC

1

R7616

0

5% 1/10W MF-LF 603

2

79

NOSTUFF

R7600

1K

2 1

5% 1/16W MF-LF

402

NOSTUFF

R7601

10K

5% 1/16W MF-LF

402

EMC

CRITICAL

Q7610.2:3MM

C7643

1UF

10% 25V

X6S-CERM

0402

CRITICAL

FDMS3602S

REG_U7600_FCCM

=PP5V_S5_PWRCTL

1

2

1

2

Q7610

POWER56

79

CRITICAL

1

C7650

180UF

20% 16V

2

POLY TH1

www.qdzbwx.com

REG_VIN_U7600

79

PP5V_S5_LDO

1

C7601

4.7UF

20%

6.3V

2

CERM 603

REG_VCC2_U7600

1UF

10% 16V X5R 402

79

REG_VCC1_U7600

1

2

C7600

1

7

PHASE

5

6

18

LDO5

VCC1

R7602

2.2

5% 1/8W MF-LF 805

2

4

VCC2

U7600

5 4 3

61

79

1

C7633

0.01UF

10% 16V

2

X7R-CERM 0402

REG_P3V3S5_PGOOD

REG_UGATE_P3V3S5

REG_BOOT_P3V3S5

REG_PHASE_P3V3S5

REG_LGATE_P3V3S5

REG_P3V3S5_ISEN

REG_P3V3S5_OCSET

REG_P3V3S5_VOUT

REG_P3V3S5_FB

REG_P3V3S5_FSET

1

R7633

16.5K

1% 1/16W MF-LF 402

2

7

15

10

8

6

ISL62383CRTZ

PGOOD1

UGATE1

BOOT1

PHASE1

LGATE1

ISEN1

OCSET1

VOUT1

FB1

FSET1

EN1

THRM

PAD

QFN

CRITICAL

PGND

29

19

PGOOD2

UGATE2

BOOT2

PHASE2

LGATE2

OCSET2

VOUT2

OUT

1

2

VIN

FCCM

ISEN2

FB2

FSET2

EN2

66

C7602

1UF

10% 16V X5R 402

17

3

1

2214

21

2313

2016

26

2511

279

28

2

2412

79

1

R7603

1

5% 1/10W MF-LF 603

2

1

C7603

1UF

10% 16V

2

X5R 402

REG_U7600_FCCM

REG_P5VS4_PGOOD

REG_UGATE_P5VS4

REG_BOOT_P5VS4

REG_PHASE_P5VS4

REG_LGATE_P5VS4

REG_P5VS4_ISEN

REG_P5VS4_OCSET

REG_P5VS4_VOUT

REG_P5VS4_FB

REG_P5VS4_FSET

61

REG_BOOT_P5VS4_RC

79

1

R7656

0

5% 1/10W MF-LF 603

2

PM_EN_REG_P3V3_S5_R

61

1

R7692

0

5% 1/16W MF-LF 402

2

64

IN

64

IN

66 63 61

PM_EN_REG_P3V3_S5

PM_EN_REG_P5V_S4

R7693

0

21

5% 1/16W MF-LF

402

PM_EN_REG_P5V_S4_R

1

C7673

0.01UF

10% 16V

2

X7R-CERM 0402

66 61

REG_P5VS4_PGOOD

61

66 61

REG_P3V3S5_PGOOD

61

1

R7673

16.5K

1% 1/16W MF-LF 402

2

=PP3V3_S5_VRD

CRITICAL

1

C7651

180UF

20% 16V

2

POLY TH1

4

1

C7656

0.1UF

10% 25V

2

X6S 0402

CRITICAL

Q7655

FDMC0223S

MLP3.3X3.3

4

1

R7680

20K

5% 1/16W MF-LF 402

2

PM_PGOOD_REG_P5V_S4

MAKE_BASE=TRUE

1

R7640

20K

5% 1/16W MF-LF 402

2

PM_PGOOD_REG_P3V3_S5

MAKE_BASE=TRUE

EMC CRITICAL

Q7650.5:3MM

1

C7682

1UF

10% 25V

2

X6S-CERM

5

D

G

S

CRITICAL

Q7650

FDMC0225

MLP3.3X3.3

321

0402

Check this text note for accuracy

DCR(L7650) = 6.2 MOHM (TYP) / 6.9 MOHM (MAX)

EMC CRITICAL

Q7650.5:3MM

1

C7683

1UF

10% 25V

2

X6S-CERM 0402

CRITICAL

EMC

L7650.2:4MM

1

C7680

1000PF

5% 25V

2

CERM 0402

EMC

L7650.2:4MM

1

C7681

1000PF

5% 25V

2

CERM 0402

C

L7650

2.2UH-20%-0.0058OHM-16A

(reg_phase_p5vs4)

PCMB104E-SM

NOSTUFF

1

C7657

0.001UF

10% 50V

5

D

G

2

X7R-CERM 0402

REG_SNUBBER_P5VS4

NOSTUFF

1

R7657

S

321

0.499

1% 1/10W MF 603

2

1

OMIT

SM

XW7650

2

79

REG_P5VS4_PHASE_SNS_P

CKPLUS_WAIVE=MISS_N_DIFFPAIR

REG_P5VS4_PHASE_SNS_M

79

R7658

9.31K

1% 1/16W MF-LF

402

21

(reg_p5vs4_isen)

(reg_p5vs4_ocset)

21

OMIT

SM

XW7651

79

C7658

0.033UF

21

10%

16V

X5R 402

R7659

9.31K

1% 1/16W MF-LF

402

PP5V_S4_REG

CRITICAL

2

1

C7660

330UF

20%

6.3V

2

POLY-TANT CASE-D3L-SM

CRITICAL

1

C7661

330UF

20%

6.3V

2

POLY-TANT CASE-D3L-SM

1

2

PP5V_S4_REG

NOSTUFF

1

C7663

1

R7691

1

2

0

5% 1/16W MF-LF 402

2

10UF

20% 10V

2

X5R-CERM 0402-1

NOSTUFF

1

C7664

10UF

20% 10V

2

X5R-CERM 0402-1

C7663/C7664 are mirrored as a provision for acoustic noise

66 61

C7662

10UF

20% 10V X5R-CERM 0402-1

66 61

B

(reg_p5vs4_vout)

<Ra>

REG_P5VS4_VOUT_R

79

1

R7672

976

1% 1/16W MF-LF 402

2

1

C7672

1000PF

5% 25V

2

CERM 0402

1

R7670

75K

1% 1/16W MF-LF 402

2

<Rb>

1

R7671

10K

1% 1/16W MF-LF 402

2

Vout = 0.6 * (1 + Ra / Rb)

OUT

64

SYNC_MASTER=J117_ANDRES SYNC_DATE=03/24/2014

PAGE TITLE

A

VReg 3.3V S5/5V S4

DRAWING NUMBER SIZE

OUT

65

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

76 OF 123

SHEET

61 OF 81

D

8 7 5 4 2 1

36

D

C

81 62

46

IN

46

IN

LGND_BKLT

81 62

PGND_BKLT

81 62

DGND_BKLT

81 62

PP12V_S0_BKLT_PWR

81 62

PP12V_S0_BKLT_PWR

1

C8151

1UF

10% 25V

2

X7R 805

=I2C_BKLT_SCL

=I2C_BKLT_SDA

XW8103

SM

2 1

XW8104

SM

2 1

XW8105

SM

2 1

CRITICAL

D8101

SOD-323

SBR130S3

81 62

1

C8152

1UF

10% 25V

2

X7R 805

PGND_BKLT

R8100

R8101

402 5%

K

A

CRITICAL

1

C8100

10UF

10% 25V

2

X6S 0805

CRITICAL

1

C8101

10UF

10% 25V

2

X6S 0805

PP12V_S0_BKLT_PWR_R

1

C8153

1UF

10% 25V

2

X7R 805

81 62

21

0

21

1/16W MF-LF

MF-LF1/16W40205%

CRITICAL

1

C8102

10UF

10% 25V

2

X6S 0805

1

C8154

1UF

10% 25V

2

X7R 805

CRITICAL

1

C8103

10UF

10% 25V

2

X6S 0805

PGND_BKLT

PP12V_S0_BKLT_PWR PP5V_S0_BKLT_R PP3V3_S0_BKLT_VDDIO_R

BKLT_SCL

BKLT_SDA

81 62

BKLT_SHUTDOWN

62

81

BKLT_ISET

81

BKLT_FLT

BKLT_VSYNC_R

62

81 62

BKLT_SCL

BKLT_SDA

LVDS_BKLT_PWM_RC

81 62

1

C8104

0.1UF

10% 25V

2

X6S 0402

CRITICAL

R8104

0.05

7

3

20

19

10

11

2

1

C8105

0.1UF

10% 25V

2

X6S 0402

21

PP12V_S0_BKLT_PWR_R

8

MF

22

CRITICAL

U8100

LLP

LP8561B0SQ-F

1/16W04021%

SD

ISET

FILTER

VSYNC

SCLK

SDA

PWM

NOSTUFF

1

C8106

0.1UF

10% 25V

2

X6S 0402

23

VINVDDIO VLDO

GD

ISENSE

FB

OUT1

OUT2

OUT3

OUT4

OUT5

33UH-20%-10A-0.0355OHM

NOSTUFF

1

C8107

0.1UF

10% 25V

2

X6S 0402

PGND_BKLT

81 62

R8106

1/8W

MF-LF

6

81

BKLT_GATE

24

81

BKLT_SW_P

CKPLUS_WAIVE=MISS_N_DIFFPAIR

21

81

BKLT_FB

12

BKLT_ISEN1

13

BKLT_ISEN2

14

BKLT_ISEN3

16

BKLT_ISEN4

17

BKLT_ISEN5

CRITICAL

L8100

PIMB177T-SM

81

BKLT_GATE_R

1

0

5%

805

2

81 62

21

81

R8107

0

5% 1/10W MF-LF

603

NOSTUFF

1

C8126

1000PF

5% 50V

2

C0G-CERM 603

BKLT_SW_M

BKLT_PHASE

D

G

5

S

43

21

81

XW8101

SM

2 1

POWERDI5-TO277A

7621

CRITICAL

Q8100

IRF6645PBF

DIRECTFET-SJ

BKLT_SW_R

81 62

PGND_BKLT

81 62

CRITICAL

D8100

1

2

PDS5100H

NOSTUFF

1

R8109

4.7

5% 1/4W MF-LF 1206

2

81

BKLT_SNUBBER

NOSTUFF

1

C8127

100PF

5% 100V

2

C0G-CERM 0603-1

CRITICAL

1

R8108

0.05

1% 1W MF 2512

2

3

CRITICAL

1

C8108

2.2UF

10% 100V

2

X7S-CERM 1206

81

BKLT_FB_XW

1

R8124

0

5% 1/10W MF-LF 603

2

81

BKLT_FB_R

1

R8110

1M

1% 1/16W MF-LF 402

2

1

R8111

330K

1% 1/8W MF 0402

2

CRITICAL

1

C8109

2.2UF

10% 100V

2

X7S-CERM 1206

BKLT_BOOST

81 62

XW8102

SM

2 1

81 62

1

C8160

2

PART NUMBER

1

2

81 62

BKLT_BOOST

BKLT_ISEN1

33PF

5% 100V C0G-CERM 0603

CRITICAL

C8110

2.2UF

10% 100V X7S-CERM 1206

1

C8140

1000PF

10% 100V

2

X7R 0603

81 62

CRITICAL

1

C8111

2.2UF

10% 100V

2

X7S-CERM 1206

CRITICAL

1

2

1

C8120

100PF

5% 100V

2

C0G-CERM 0603

BKLT_ISEN2

BKLT_ISEN3

81 62

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

D8100371S0694371S0648 BLC Switch Diode

1

C8112

2

CRITICAL

C8141

1000PF

10% 100V X7R 0603

1

C8121

100PF

5% 100V

2

C0G-CERM 0603

81 62

CRITICAL

2.2UF

10% 100V X7S-CERM 1206

1

C8142

1000PF

10% 100V

2

X7R 0603

BKLT_ISEN4

1

2

CRITICAL

1

C8122

100PF

5% 100V

2

C0G-CERM 0603

BKLT_ISEN5

81 62

345678

CRITICAL

C8113

2.2UF

10% 100V X7S-CERM 1206

1

2

1

2

81 62

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL

1

C8114

2.2UF

10% 100V

2

X7S-CERM 1206

CRITICAL

C8143

1000PF

10% 100V X7R 0603

C8123

100PF

5% 100V C0G-CERM 0603

BKLT_ISEN6

1

C8144

1000PF

10% 100V

2

X7R 0603

1

C8124

100PF

5% 100V

2

C0G-CERM 0603

1

C8115

2.2UF

10% 100V

2

X7S-CERM 1206

CRITICAL

1

2

CRITICAL

1

C8145

1000PF

10% 100V

2

X7R 0603

PGND_BKLT

C8125

100PF

5% 100V C0G-CERM 0603

2 1

ACOUSTICS E-NOISE COMPONENTS

CRITICAL

1

C8116

2.2UF

10% 100V

2

X7S-CERM 1206

1

2

81 62

BKLT_BOOST

81 62

CRITICAL

C8117

2.2UF

10% 100V X7S-CERM 1206

1

2

1

C8195

2

CRITICAL

C8191

2.2UF

10% 100V X7S-CERM 1206

CRITICAL

2.2UF

10% 100V X7S-CERM 1206

CRITICAL

1

C8118

2.2UF

10% 100V

2

X7S-CERM 1206

1

2

1

C8196

2.2UF

10% 100V

2

X7S-CERM 1206

1

C8119

2.2UF

10% 100V

2

X7S-CERM 1206

CRITICAL

C8192

2.2UF

10% 100V X7S-CERM 1206

CRITICAL

1

C8193

2.2UF

10% 100V

2

X7S-CERM 1206

NOSTUFF

CRITICAL

1

C8198

2.2UF

10% 100V

2

X7S-CERM 1206

CRITICAL

1

C8197

2.2UF

10% 100V

2

X7S-CERM 1206

CRITICAL

1

C8194

2.2UF

10% 100V

2

X7S-CERM 1206

NOSTUFF

CRITICAL

1

C8199

2.2UF

10% 100V

2

X7S-CERM 1206

BKLT_BOOST

CRITICAL

1

C8190

2.2UF

10% 100V

2

X7S-CERM 1206

PGND_BKLT

81 62

D

C

81 62

B

A

BKLT_VSYNC

39

=PP5V_S0_BKLT

66

=PP3V3_S0_BKLT_VDDIO

66

NOSTUFF

C8128

33PF

5%

50V

C0G-CERM

0402

DGND_BKLT

81 62

BKLT_FLT_RC

81

R8152

0

402 1/16W5% MF-LF

21

BKLT_VSYNC_R

R8130

1

21

5% 1/16W MF-LF

402

C8131

1UF

10% 25V X7R

0603

1

2

81 62

PP5V_S0_BKLT_R

C8132

0.01UF

X7R-CERM

0402

R8131

1

21

5% 1/16W MF-LF

402

C8134

1UF

10% 25V X7R

0603

81 62

PP3V3_S0_BKLT_VDDIO_R

1

C8135

0.01UF

2

X7R-CERM

1

2

10% 16V

0402

10% 16V

1

R8103

270K

5% 1/16W MF-LF 402

2

1

C8129

4700PF

5% 50V

2

CERM 603

1

2

1

2

1

R8123

10K

1% 1/16W MF-LF 402

2

C8133

0.1UF

X7R-CERM

C8136

0.1UF

X7R-CERM

62

10% 16V

0402

10% 16V

0402

1

R8105

12.4K

1% 1/16W MF-LF 402

2

1

C8130

330PF

10% 50V

2

X7R-CERM 0402

DGND_BKLT

1

2

DGND_BKLT

1

2

DGND_BKLT

62 39

NOSTUFF

1

R8153

10K

1% 1/16W MF-LF 402

2

IN

BKLT_EN

BKLT_SW_M

81 62

LGND_BKLT

81 62

PGND_BKLT

81 62

DGND_BKLT

81 62

PGND_BKLT

81 62

R8150

BKLT_ISEN6_R

81 62

BKLT_ISEN5_R

81 62

BKLT_ISEN4_R

81 62

BKLT_BOOST

81 62

BKLT_ISEN3_R

81 62

BKLT_ISEN2_R

81 62

BKLT_ISEN1_R

81 62

4

EN

GND_GD

ISENSE_GND

1

GND_S

9155

OUT6

THRM

PAD

GND_L

25

PP12V_S0_BKLT_PWR

1

100K

1% 1/10W MF-LF

603

2

CRITICAL

600-OHM-25%-0.5A-0.40OHM

CRITICAL

600-OHM-25%-0.5A-0.40OHM

CRITICAL

600-OHM-25%-0.5A-0.40OHM

CRITICAL

600-OHM-25%-0.5A-0.40OHM

CRITICAL

600-OHM-25%-0.5A-0.40OHM

CRITICAL

600-OHM-25%-0.5A-0.40OHM

18

BKLT_ISEN6

FB8100

0603

FB8101

0603

FB8102

0603

FB8103

0603

FB8104

0603

FB8105

0603

FB8106

0603

FB8107

0603

CRITICAL

Q8105

SI3440DVT1GE3

TSOP

3 6

4

21

CRITICAL

21

CRITICAL

21

81 62

21

81 62

BKLT_ISEN1_R

1

2

5

BKLT_ISEN2

81 62

PART NUMBER

376S1073376S1256 ALL Short Protection FET

81

LED_RETURN_6

81

LED_RETURN_5

81

LED_RETURN_4 BKLT_BOOST_1

81

BKLT_BOOST_2

81

LED_RETURN_3

81

LED_RETURN_2 LED_RETURN_1

81

PGND_BKLT

CRITICAL

Q8106

SI3440DVT1GE3

3 6

4

TSOP

CRITICAL

J8100

504050-1091

F-RT-SM

11

1

2

3

4

5

6

7

8

9

10

12

www.qdzbwx.com

BKLT_ISEN2_R

1

2

5

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

=PP12V_S0_BKLT

66

CRITICAL

Q8107

SI3440DVT1GE3

TSOP

3 6

4

TABLE_ALT_HEAD

TABLE_ALT_ITEM

CRITICAL

F8100

6AMP-32V

0603-1

BKLT_ISEN3_R

1

2

5

21

81

PP12V_BKLT_SNS

62 39

IN

BKLT_EN

CRITICAL

R8112

0.005

1%

1/4W

MF

1206-1

CRITICAL

Q8108

SI3440DVT1GE3

3 6

4

21

TSOP

PART NUMBER

1

2

5

PP12V_BKLT_FUSED

BKLT_EN_L

3

D

G

1

S

2

BKLT_ISEN4_R

BKLT_ISEN5

81 62

CRITICAL

FB8108

FERR-600-OHM-3A

NOSTUFF

R8120

147K

1% 1/16W MF-LF

402

NOSTUFF

Q8101

SSM3K15AMFVAP

SOD

BKLT_SHUTDOWN

62

SI3440DVT1GE3

3 6

4

F8100740S0145 740S0146 BLC Fuse

21

PP12V_S0_BKLT_FILT

81

1206

21

CRITICAL

Q8109

TSOP

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

BLC Inrush FET376S1121 376S1116 Q8102155S0831 155S0797 FB8100 to FB8107ALL

NOSTUFF

1

C8171

0.1UF

10% 25V

2

X6S 0402

1

R8122

0

5% 1/16W MF-LF 402

2

TABLE_ALT_HEAD

PART NUMBER

371S0731 INPUT DIODED8101371S0748

2.2UF_CAP138S1078 138S0810 BLC 2.2uF OUTPUT CAPS

CRITICAL

COMMENTS:REF DESBOM OPTIONPART NUMBER ALTERNATE FOR

TABLE_ALT_ITEM

Q8110

BKLT_ISEN5_R

1

2

5

BKLT_ISEN6BKLT_ISEN3BKLT_ISEN1 BKLT_ISEN4

81 62 81 62 81 62 81 62

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Q8102

SI3440DVT1GE3

TSOP

3 6

4

CRITICAL

AON6407_001

DFN5X6

SYM-VER-2

PP12V_S0_BKLT_PWR

NOSTUFF

1

C8137

100PF

5% 50V

2

C0G 0402

1

R8121

71.5K

1% 1/16W MF-LF 402

2

S

3 2 1

G

4

D

5

BKLT_EN_DIV

SYNC_MASTER=J117_ANDRES SYNC_DATE=03/24/2014

PAGE TITLE

BKLT_ISEN6_R

1

2

5

81 62

LCD Backlight Driver (LP8561)

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

81 OF 123

SHEET

62 OF 81

D

B

A

8 7 5 4 2 1

36

345678

2 1

D

1

C8401

470PF

10% 50V

2

CERM 0402

=PP5V_S5_PWRCTL

66 61

1

C8400

0.1UF

10% 16V

2

X7R-CERM 0402

66 63 66

64

IN

64

IN

C8402

0.001UF

10% 50V

CERM

402

3.3V S4/S0 FET

U8400

TPS22966

DPU

CRITICAL

GND

THRM

11

15

PAD

VOUT1

VOUT2

13

8

PP3V3_S0_FET

12

10

1

3

4

6

5

VIN1

ON1

CT1

VBIAS

VIN2

ON2

CT2

=PP3V3_S5_FET_P3V3_S4 PP3V3_S4_FET

PM_EN_FET_P3V3_S4

FET_RAMP_P3V3_S4

=PP3V3_S5_FET_P3V3_S0

66

PM_EN_FET_P3V3_S0

FET_RAMP_P3V3_S0

1

2

3V3 S4 SSD

66 65 64 63 17 16

66 63

SSD:Y

10%

25V CERM 0402

1

2

4nF corresponds to

C8411

0.0047UF

P3V3_S4_SSD_FET_RAMP

15

SSD_PWR_EN

IN IN

2.2V / ms ramp rate

=PP3V3_S5_PWRCTL

1

VDD

U8410

SLG5AP304V

7 3

CAP

2 5

ON S

TDFN

CRITICAL

SSD:Y

GND

8

1

2

D

SSD:Y

C8410

0.1UF

10% 16V X7R-CERM 0402

=PP3V3_S5_FET_P3V3_S4

PP3V3_S4_SSD_FET

66

66 63

C8421

0.0047UF

10%

25V CERM 0402

66 63 50

P5V_S0_FET_RAMP

64

1

2

4nF corresponds to

PM_EN_FET_P5V_S0

2.2V / ms ramp rate

5V S0 FET

=PP5V_S4_PWRCTL

1

VDD

U8420

SLG5AP304V

7 3

CAP

2 5

ON S

TDFN

CRITICAL

GND

8

1

2

D

C8420

0.1UF

10% 16V X7R-CERM 0402

=PP5V_S4_FET_P5V_S0

PP5V_S0_FET

D

66

66 63

C

B

66 63 50

Rise Time For VD = 3.3V:

=PP5V_S4_PWRCTL

66 64 63 59 39

470 pF -- 603 us 1000 pF -- 1185 us

66 63 50

1

R8440

2.0K

5% 1/16W MF-LF 402

1

C8442

0.1UF

10% 16V

2

X7R-CERM 0402

=PP3V3_S4_PWRCTL

2

66 63

1

R8441

18K

5% 1/16W MF-LF 402

2

P5V_S0_VREF

PP5V_S0_FET

1

C8444

0.1UF

10% 16V

2

X7R-CERM 0402

=PP5V_S4_PWRCTL

Input: 0.9 * 5V = 4.5V

R8442

1

10K

1/16W MF-LF

1

2

1

2

1%

402

R8443

2.0K

5% 1/16W MF-LF 402

R8444

18K

5% 1/16W MF-LF 402

P5V_S0_FET_R

Input: 0.9 * 3.3V = 2.9V

P3V3_S0_VREF

66 63

1

R8449

3.0K

5% 1/16W MF-LF 402

2

BOMOPTION=NOSTUFF

PP3V3_S0_FET

4

-

3

+

R8448

1

R8447

15K

1/16W MF-LF

21

5%

402

5

2

1M

1% 1/16W MF-LF

402

U8441

TLV3701IDBV

SOT-23-5

1

2

66 64 63 59 39

P3V3_S0_FET_R

1

R8445

7.5K

5% 1/16W MF-LF 402

2

BOMOPTION=NOSTUFF

=PP3V3_S4_PWRCTL

1

C8443

0.1UF

10% 16V

2

X7R-CERM 0402

1

2

4

3

C8441

0.1UF

10% 16V X7R-CERM 0402

52

-

+

U8442

TLV3701IDBV

SOT-23-5

1

64 63

66 65 64 63 17 16

PM_EN_S0

IN

P5V_S0_PGD

PM_EN_S0

IN

P3V3_S0_PGD

5V / 3V3 S0 PGOODs

=PP3V3_S5_PWRCTL

1

C8440

0.1UF

10% 16V

2

CRITICAL

U8440

1

A1

2

B1

5

A2

6

B2

8

VCC

SOT833

08

74LVC2G08GT/S505

GND

4

7

Y1

3

Y2

X7R-CERM 0402

PM_PGOOD_FET_P5V_S0

PM_PGOOD_FET_P3V3_S0

OUT

64

5V HDD FET

=PP5V_S4_FET_P5V_HDD

66

1

VDD

SSD:Y

1

C8460

0.1UF

10% 16V

2

X7R-CERM 0402

C

U8460

SLG5AP304V

P5V_S0_HDD_FET_RAMP

64 38

15

SSD:Y

10%

25V CERM 0402

1

2

C8461

0.0047UF

IN

HDD_PWR_EN

7 3

CAP

2 5

ON S

FERR-33-OHM-3A-22-MOHM

=PP5V_S0_FET_P5V_HDD

66 63

TDFN

CRITICAL

SSD:Y

GND

8

L8460

1 2

0402

SSD:N

D

=PP5V_S0_FET_P5V_HDD

PP5V_S0_HDD_FET

66 63

B

PP5V_S0_HDD_FET

66 63

A

64

12V S0 FET

=PP12V_G3H_FET_P12V_S0

66

PM_EN_FET_P12V_S0

IN

1

R8451

100K

5% 1/16W MF-LF 402

2

1

C8450

0.1UF

10% 16V

2

X7R-CERM 0402

NC

R8446

1M

1 2

1% 1/16W MF-LF

402

D

5

CRITICAL

Q8450

IRFH3702TRPBF

PQFN

S

1

PP12V_S0_FET

OUT

66

G

4

FET_EN_P12V_S0

1

VCC

U8450

SLG5AP036

2

ON

3

NC

TDFN

GND

4

THRM

PAD

9

G

S

PG

5

D

7

6

8

1

C8451

0.022UF

X7R 10%

2

50V 0402

=PP3V3_S4_PWRCTL

47K

5% 1/16W MF-LF

402

1

2

PM_PGOOD_FET_P12V_S0

R8452

www.qdzbwx.com

OUT

66 64 63 59 39

SYNC_MASTER=J16_MLB_IG

PAGE TITLE

SYNC_DATE=08/27/2013

A

PM FETs/LDOs

64 39

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

84 OF 123

SHEET

63 OF 81

8 7 5 4 2 1

36

345678

2 1

D

S5 Enable

=PP12V_S5_PWRCTL

66

56

PM_PGOOD_FET_P12V_S5

IN

1

R8590

68K

5% 1/16W MF-LF 402

2

1

R8591

33K

5% 1/16W MF-LF 402

2

PM_EN_REG_P3V3_S5

MAKE_BASE=TRUE

OUT

61

65 44 43 35 13

59

S0 Enables

66 65 64 63 17 16

IN

PM_SLP_S3_L

PM_PGOOD_REG_P1V2_S3

=PP3V3_S5_PWRCTL

4

5

A

B

14

08

7 15

U8500

74LVC08A

QFN

6

Y

PM_EN_S0

R8506

330

5% 1/16W MF-LF

402

21

OUT

R8505

12K

5% 1/16W MF-LF

402

64 63

21

D8506

SM-201

KA

RB521ZS-30

PM_EN_S0_R

PM_EN_FET_P12V_S0

1

C8505

1UF

10%

6.3V

2

CERM 402

OUT

63

12V S0 EN RC delay must be >= downstream delay on 4.5V REG enable which in turn enables 1.05V S0. This allows for 12V S0 to hold as long as 1.05V S0 regulator is powered.

D

C

S4 Enables

43 31 13

IN OUT

S4 USB Enable

PM_SLP_S5_L

R8501

330

5% 1/16W MF-LF

402

R8500

100K

5% 1/16W MF-LF

402

21

D8501

SM-201

KA

RB521ZS-30

PM_SLP_S5_R_L

PM_EN_REG_P5V_S4

1

C8500

0.1UF

10% 16V

2

X5R-CERM 0201

61

~40 ms RC delay added to ensure that 5V S4 rail stays up at least as long as the S0 sequencing holds in order to keep 5V S0 powered.

63 39

66 65 64 63 17 16

PM_EN_S0

64 63

PM_PGOOD_FET_P12V_S0

IN

NOSTUFF

C8501

0.47UF

10%

6.3V

CERM-X5R

402

=PP3V3_S5_PWRCTL

1

2

1

2

A

B

14

08

7 15

U8500

74LVC08A

QFN

3

Y

PM_EN_FET_P5V_S0_R

MAKE_BASE=TRUE

R8508

330

5% 1/16W MF-LF

402

R8507

21

=TBT_S0_EN

82K

21

5% 1/16W MF-LF

402

D8508

SM-201

KA

RB521ZS-30

PM_EN_FET_P5V_S0_D

OUT

1

C8507

0.1UF

10% 16V

2

X5R-CERM 0201

29 28

PM_EN_FET_P5V_S0

5V S0 RC delay must be >= downstream delay on 4.5V REG enable to allow for 4.5V regulator to remain powered during power down sequence.

63

OUT

C

B

PM_PGOOD_REG_P5V_S4

MAKE_BASE=TRUE

63

OUT

PM_EN_FET_P3V3_S4

S4 TBT Port Enable

66 29 28 27 26 18

=PP3V3_S4_TBT

IN

R8520

0

5% 1/16W MF-LF

402

=PP5V_S0_PWRCTL

66 60

PP4V5_AUDIO_ANALOG

50

21

PM_EN_USB_PWR

OUTIN

42 41 61

Audio + PCH Sequencing Requirements:

4.5V -> 1.05V -> 3.3V -> 1.5V -> ALL SYS GOOD

NOSTUFF

1

C8520

0.47UF

10%

6.3V

2

CERM-X5R 402

=TBTAPWRSW_EN

=TBTBPWRSW_EN

OUT

28

29

63

IN OUT

PM_PGOOD_FET_P5V_S0

R8537

330

5% 1/16W MF-LF

402

66 65 64 63 17 16

=PP3V3_S5_PWRCTL

R8530

21

68K

21

5% 1/16W MF-LF

402

D8537

SM-201

KA

RB521ZS-30

PM_EN_REG_P4V5_S0_D

C8530

0.1UF

10% 16V

X5R-CERM

0201

PM_EN_REG_P4V5_S0

1

2

50

50 60

NOSTUFF resistor added in case of using 4.5V rail as the PGOOD itself directly.

PM_PGOOD_REG_P4V5_S0

IN OUT

MAKE_BASE=TRUE

NOSTUFF

1

R8535

0

5% 1/16W MF-LF 402

2

R8536

10K

5% 1/16W MF-LF

402

1

2

PM_EN_REG_P1V05_S0

B

A

S3 Enables

64 43 13

66 63 59 39

64 43 13

59

U8600

74LVC08A

QFN

11

Y

PM_EN_FET_P3V3_S0_R

R8531

47K

5% 1/16W MF-LF

402

R8533

21

PM_EN_FET_P3V3_S0

1

C8531

0.1UF

10% 16V

2

X5R-CERM 0201

63

63 38

PM_PGOOD_FET_P3V3_S0

IN OUTOUT

PAGE TITLE

R8534

330

5% 1/16W MF-LF

402

68K

5% 1/16W MF-LF

402

21

D8534

SM-201

K A

PM_EN_REG_P1V5_S0

RB521ZS-30

PM_PGOOD_FET_P3V3_S0_R

1

C8533

0.1UF

10% 16V

2

X5R-CERM 0201

60

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

A

PM Regulator Enables

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

PAGE

85 OF 123

SHEET

64 OF 81

D

A

B

14

08

7 15

66 65 64 63 17 16

=PP3V3_S5_PWRCTL

BYPASS=U8500::5MM

1

C8510

0.1UF

20% 10V

2

CERM 402

60

64 63

IN

PM_EN_S0

PM_PGOOD_REG_P1V05_S0

12

13

No bypass diode added across 3.3V S0 EN RC delay to mitigate

U8500

IN

PM_SLP_S4_L

=PP3V3_S4_PWRCTL

12

13

14

A

08

B

7 15

66 65 64 63 17 16

IN

PM_SLP_S4_L

PM_PGOOD_REG_P1V8_S3

=PP3V3_S5_PWRCTL

9

A

10

B

14

08

7 15

74LVC08A

QFN

11

Y

U8500

74LVC08A

QFN

8

Y

PM_EN_REG_P1V8_S3_R

PM_EN_REG_P1V2_S3

R8503

330

5% 1/16W MF-LF

402

OUT

R8504

68K

5% 1/16W MF-LF

402

21

59

21

D8503

SM-201

KA

PM_EN_REG_P1V8_S3

RB521ZS-30

PM_EN_REG_P1V8_S3_D

1

C8503

0.1UF

10% 16V

2

X5R-CERM 0201

OUT

59

possible glitching from PGOOD pullup to 5V S0 on 1.05V VR page competing with logic turn on time.

www.qdzbwx.com

8 7 5 4 2 1

36

D

ALL_SYS_PWRGD,PCH_PWROK & SYS_PWROK Generation

66 65 64 63 17 16

=PP3V3_S5_PWRCTL

345678

2 1

Resume Reset

Intel Doc# 29517 Maho Bay PDG, Section 22.13

Intel Doc# 29562 Panther Point EDS, Section 8.7 and 8.8

Note:

The iMac J70 design does not support Deep Sx modes so both DPWROK and

RSMRST# signals are shorted together

Requirements:

Power on:

Asserted at least 10 ms after all suspend well power is valid

Power off or loss of AC:

Transition to 0.8V or less before VccSUS3_3 drops to 2.90 V

to allow PCH to switch suspend well to battery without excessive loading

D

C

64 44 43 35 13

60

BYPASS=U8600::5MM

1

C8620

0.1UF

20% 10V

2

CERM 402

Method:

The SMC guarantees proper assertion and de-assertion of RSMRST# for

normal operation via PM_DSW_PWRGD.

RSMRST# is asserted when power good from regulator is de-asserted in the

event AC is lost. Power good de-assertion should happen quickly enough

to meet Intel spec.

U8600

14

IN

PM_SLP_S3_L

9

A

R8600

PM_PGOOD_REG_P1V5_S0

IN

100K

1/16W MF-LF

5%

402

21

B

08

7 15

74LVC08A

QFN

8

Y

PM_PGOOD_ALL

14

4

A

5

B

08

7 15

U8600

74LVC08A

QFN

610

Y

PM_PCH_SYS_PWROK_R

R8601

1M

5%

402

21

R8621

0

5% 1/16W MF-LF

402

21

PM_PGOOD_REG_P1V5_S0_R

1/16W MF-LF

PCH Power Goods

NOSTUFF

R8622

1/16W MF-LF

5%

402

0

1

2

1

R8624

10K

5% 1/16W MF-LF 402

2

R8620

1K

5% 1/16W MF-LF

402

21

PM_PCH_SYS_PWROK

PM_PCH_PWROK

MAKE_BASE=TRUE

PM_PCH_APWROK

OUT

To PCH

OUT

16 13

13

44 16 13

65 61 43

IN OUT

From SMC

44 43

IN

65 61

IN

PM_PGOOD_REG_P3V3_S5

MAKE_BASE=TRUE

66 65 64 63 17 16

PM_DSW_PWRGD

PM_PGOOD_REG_P3V3_S5

=PP3V3_S5_PWRCTL

U8600

14

1

A

2

B

08

7 15

74LVC08A

QFN

3

Y

PM_RSMRST_PCH_L_R

S5_PWRGD

To SMC

R8635

100

5%

1/20W

MF

201

21

PM_RSMRST_PCH_L

To PCH

OUT

C

16 13

B

43 17 3

44 43 27

OUT

IN

ALL_SYS_PWRGD

MAKE_BASE=TRUE

To SMC, for 99ms delay

ALL_SYS_PWRGD must remain low for

5ms minimum after all rails are valid

SMC_DELAYED_PWRGD

B

A

Rail definitions

Platform:

Uncore:

All processor non-Core and non-Graphics (5V, 3.3V, 1.5V, 1.05V for PCH/TBT/GPU)

1.8V and 1.2V for DDR3

Notes on sequencing requirements

Intel:

1. No hard specification on platform rails

2. SMC guarantees timing on PCH DPWROK and PWROK

3. VCC3_3 may power up before VCC, VCC must ramp to 0.6V within 25ms of VCC3V3 ramping to 2.6V

4. VCC1_5 may power up before VCC, VCC must ramp to 0.6V within 25ms of VCC1V5 ramping to 1.35V

5. VCC may power down before VCC3_3, VCC3_3 must ramp down to 2.6V within 35ms

6. VCC may power down before VCC1_5, VCC1_5 must ramp down to 1.35V within 35ms

8 7 5 4 2 1

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SYNC_MASTER=J117_ANDRES SYNC_DATE=03/24/2014

PAGE TITLE

A

PM Power Good

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

051-00081

REVISION

3.0.0

BRANCH

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86 OF 123

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65 OF 81

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D

345678

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G3 Rails

Always on: Keeps the PCH RTC alive

PP3V3_G3

G3H Rails

PP12V_ACDC

79

MAKE_BASE=TRUE

PP12V_G3H

79

MAKE_BASE=TRUE

PP3V42_G3H

79

MAKE_BASE=TRUE

PP3V3_G3_RTC

=PPVRTC_G3_PCH

PP12V_G3H_ACDC

=PP12V_G3H_SNS_R

PP12V_G3H_SNS

=PP12V_G3H_REG_3V42_G3H

=PP12V_G3H_FET_P12V_S5

=PP12V_G3H_FET_P12V_S0

PP3V42_G3H_REG

=PP3V3_G3H_BT

=PP3V3_G3H_SMC

=PP3V3_G3H_RTC_D

=PPVIN_G3H_SMCVREF

=PP3V3_G3H_SMC_USBMUX

=PP3V3_G3H_T112

17

56

47

56

63

56

31

17

44

41

45

S4 Rails

Enabled when system has AC and is in run or sleep

PP5V_S4

79

MAKE_BASE=TRUE

13 12 8

PP3V3_S4

79

MAKE_BASE=TRUE

49 44 43

PP5V_S4_REG

=PP5V_S4_REG_P1V2_S3

=PP5V_S4_FET_P5V_S0

=PP5V_S4_PWRCTL

=PP5V_S4_USB

=PP5V_S4_AUDIO

=PP5V_S4_FET_P5V_HDD

=PP5V_S4_SDCARD

PP3V3_S4_FET

=PP3V3_S4_FET_ENET

=PP3V3_S4_PWRCTL

=PP3V3_S4_LED

=PP3V3_S4_PCH_GPIO

=PP3V3_S4_SDCARD

=PP3V3_S4_SMC

=PP3V3_S4_TBT

=PP3V3_S4_AP

=PP3V3_S4_REG_P1V5_S0

61

59

63

63 50

42 41

50

63

36

63

35

64 63 59 39

3

42 41 18 15

36

44

64 29 28 27 26 18

44 31

60

S0 Rails

Enabled when system is in run

PP12V_S0

79 79

MAKE_BASE=TRUEMAKE_BASE=TRUE

PP5V_S0

79

MAKE_BASE=TRUE

PP12V_S0_FET

=PP12V_S0_REG_CPUVCC_S0

=PP12V_S0_REG_P1V05_S0

=PP12V_S0_AUDIO_SPKRAMP

=PP12V_S0_BKLT

=PP12V_S0_FAN

=PP12V_S0_LCD

PP5V_S0_FET

=PP5V_S0_REG_CPUVCC_S0

=PP5V_S0_REG_P1V05_S0

=PP5V_S0_BKLT

=PP5V_S0_FET_P5V_HDD

=PP5V_S0_CAMERA

=PP5V_S0_PCH_STRAP

=PP5V_S0_PWRCTL

63

60

62

49

39

63

60

62

63

17

PP1V5_S0

79

MAKE_BASE=TRUE

58 57

53 52

PP1V5_S0_REG

=PP1V5_S0_SENSE

=PP1V5_S0_PCH_VCCTS

=PP1V5_S0_AUDIO_DIG

=PP1V5_S0_PCH_VCCSUSHDA

60

33

8

51

17 11 8

D

58 57

PP1V05_S0

77

MAKE_BASE=TRUE

38 37

64 60

PP1V05_S0_REG

=PP1V05_S0_PCH_VCC

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCCLK

=PP1V05_S0_PCH_VCCIO_USB2

=PP1V05_S0_PCH_VCCHSIO

=PP1V05_S0_PCH_VCCIO_HSIO

=PP1V05_S0_PCH_PLLFILTERS

=PP1V05_S0_SMC

=PP1V05_S0_XDP

=PP1V05_S0_CPU_VCCST

=PP1V05_S0_PCH_VCCPLL_HSIO

60

8

11

44

16

57

11

11 8

17 16 15 8 6

C

B

Ground/Common

GND\G

MAKE_BASE=TRUE

Enabled when system has AC and is in S5

PP12V_S5

79

MAKE_BASE=TRUE

PP5V_S5

79

MAKE_BASE=TRUE

PP3V3_S5

79

MAKE_BASE=TRUE

I2326

PP12V_S5_FET

=PP12V_S5_REG_P3V3P5V_S5

=PP12V_S5_REG_P1V2_S3

=PPHV_SW_TBTAPWRSW

=PPHV_SW_TBTBPWRSW

=PP12V_S5_SNS

=PP12V_S5_PWRCTL

PP5V_S5_LDO

NBC

=PP5V_S5_PWRCTL

PP3V3_S5_REG

=PP3V3_S5_FET_P3V3_S4

=PP3V3_S5_FET_P3V3_S0

=PP3V3_S5_PWRCTL

=PP3V3_S5_VRD

=PP3V3_S5_LED

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_S5_PCH_VCCDSW

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_SUS_PCH_VCCSUS_RTC

=PP3V3_SUS_PCH_VCCSUS_ICC

=PP3V3_S5_ROM

=PP3V3_S5_SENSE

=PP3V3_S5_SMC

=PP3V3_S4_TBTAPWRSW

=PP3V3_S4_TBTBPWRSW

=PP3V3_SUS_PCH_GPIO

=PP3V3_S5_PCH_GPIO

=PP3V3_S5_REG_P1V8_S3

=PP3V3_S5_XDP

56

61

59

28

29

47

64

61

63

61

3

8

45

47

44

28

29

14

59

16

PP5V_S0_HDD

79

MAKE_BASE=TRUE

S3 RailsS5 Rails

Enabled when system is in run or sleep

PP3V3_ENET

79

MAKE_BASE=TRUE

PP1V8_S3

77

MAKE_BASE=TRUE

PP1V2_S3

77

63 61

65 64 63 17 16

11 8

14 11 8

11 8

50 15 13

MAKE_BASE=TRUE

PP1V2_S3_DDR

77

MAKE_BASE=TRUE

PP0V6_S3_DDRVTT

77

MAKE_BASE=TRUE

PP3V3_ENET_FET

=PP3V3_ENET_PHY

PP1V8_S3_REG

=PP1V8_S3_DDR

=PP1V8_S3_CAMERA_FET

=PP1V8_S3_PWRCTL

=PP1V8_S3_REG_P1V5_S0

PP1V2_S3_REG

=PP1V2_S3_SNS_DDR_R

PP1V2_S3_SNS_DDR

=PP1V2_S3_LDO_DDRVTT

=PP1V2_S3_DDR_MEMVREF

=PP1V2_S3_DDR_VDD2

=PP1V2_S3_DDR_VDDCA

=PP1V2_S3_DDR_VDDQ

=PP1V2_S3_MEM_VTTPWRCTL

=PPVMEMIO_S0_CPU

=PP1V2_S3_CAMERA_FET

PP0V6_S3_DDRVTT_LDO

=PP0V6_S3_DDRVTT_A

=PP0V6_S3_DDRVTT_B

35

35 34

59

24 23 22 21

38

60

59

47

59

20

24 23 22 21

18

10 8

38

59

25

PP3V3_S0

79

MAKE_BASE=TRUE

PP5V_S0_HDD_FET

=PP5V_S0_SATA

PP3V3_S0_FET

=PP3V3_S0_VRD

=PP3V3_S0_AUDIO

=PP3V3_S0_AUDIO_DIG

=PP3V3_S0_AUDIO_SPKRAMP

=PP3V3_S0_DP

=PP3V3_S0_ENET

=PP3V3_S0_FAN

=PP3V3_S0_INTDPMUX

=PP3V3_S0_LED

=PP3V3_S0_PCH

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_PCH_VCCTS

=PP3V3_S0_PCH_VCCSDIO

=PP3V3_S0_CAMPWREN

=PP3V3_S0_SDCARD

=PP3V3_S0_SENSE

=PP3V3_S0_SMBUS

=PP3V3_S0_SMBUS_SMC_0

=PP3V3_S0_SMBUS_SMC_1

=PP3V3_S0_SMBUS_SMC_2

=PP3V3_S0_SMBUS_SMC_3

=PP3V3_S0_SMC

=PP3V3_S0_BKLT_VDDIO

=PP3V3_S0_PCH_GPIO

=PP3V3_S0_CAMERA

=PP3V3_S0_ALS

=PP3V3_S0_MEM_VTTPWRCTL

=PP3V3_S0_PWRCTL

63

33

63

56

34

49

40

3

17

36

46

44

62

37

18

60

PPCPUVCC_S0_CPU

78

MAKE_BASE=TRUE

50 37

54 51

53 52

39 30

11 8

48 47 33 32

PPCPUVCC_S0_REG

=PPCPUVCC_S0_CPU

=PPVCC_S0_CPU

58

47

10 8

C

B

46 39

27 16 15 13 12

38 37

A

www.qdzbwx.com

PP3V3_S4_SSD

MAKE_BASE=TRUE

PPSSD_S4

79

MAKE_BASE=TRUE

PP3V3_S4_SSD_FET

=PPSSD_S4_SNS_R

PPSSD_S4_SNS

=PPSSD_S4_CONN

63 79

47

32

SYNC_MASTER=J16_MLB_IG

PAGE TITLE

Power Aliases

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

SYNC_DATE=08/27/2013

DRAWING NUMBER SIZE

051-00081

REVISION

D

3.0.0

BRANCH

PAGE

100 OF 123

SHEET

66 OF 81

A

8 7 5 4 2 1

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PCH Miscellaneous

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TP_HDA_SDIN1

12

TP_PCIE_CLK100M_CAMERAP

12

TP_PCIE_CLK100M_CAMERAN

12

TP_PCIE_CLK100M_FWP

12

TP_PCIE_CLK100M_FWN

12

NC_HDA_SDIN1

MAKE_BASE=TRUE

NC_PCIE_CLK100M_CAMERAP

MAKE_BASE=TRUE

NC_PCIE_CLK100M_CAMERAN

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWP

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWN

MAKE_BASE=TRUE

Unused Thunderbolt Aliases

TP_TBT_PCIE_RESET0_L

26

MAKE_BASE=TRUE

NO_TEST=1

NC_TBT_PCIE_RESET0_L

NO_TEST=1

D

C

B

A

SYNC_MASTER=J16_MLB_IG

PAGE TITLE

Unused Signal Aliases

DRAWING NUMBER SIZE

Apple Inc.

R

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NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=08/27/2013

051-00081

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67 OF 81

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C

B

A

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PAGE TITLE

Functional / ICT Test

DRAWING NUMBER SIZE

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I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

REVISION

BRANCH

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SHEET

051-00081

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105 OF 123

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D

J70 BOARD SPECIFIC PHYSICAL AND SPACING CONSTRAINTS

BOARD AREASBOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,BOTTOM 16.2MMNO_TYPE,BGA

BOARD UNITS

(MIL or MM)

ALLEGRO

VERSION

TABLE_BOARD_INFO

345678

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C

General Physical Rule Definitions

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

DEFAULT 0.1 MM

ALLOW ROUTE

ON LAYER?

Y*

Y*STANDARD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ALLOW ROUTE

ON LAYER?

ALLOW ROUTE

ON LAYER?

50_OHM_SE TOP,BOTTOM

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ALLOW ROUTE

ON LAYER?

* Y

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ALLOW ROUTE

ON LAYER?

ALLOW ROUTE

ON LAYER?

Y*

YTOP,BOTTOM

MINIMUM LINE WIDTH

=DEFAULT =DEFAULT

MINIMUM LINE WIDTH

0.175 MM 0.085 MM

MINIMUM LINE WIDTH

0.092 MM* Y50_OHM_SE

0.111 MM

MINIMUM LINE WIDTH

0.150 MM70_OHM_DIFF * Y

0.174 MM70_OHM_DIFF TOP,BOTTOM Y

MINIMUM LINE WIDTH

0.141 MM73_OHM_DIFF

0.165 MM =STANDARD73_OHM_DIFF

12.7 MM=50_OHM_SE

12.7 MM

0.076 MM0.145 MM =STANDARD40_OHM_SE * Y

=STANDARDTOP,BOTTOM40_OHM_SE Y

=STANDARD0.076 MM

=STANDARD0.085 MMY

=STANDARD0.076 MM55_OHM_SE 0.076 MM

0.085 MM0.090 MM

0.076 MM

=STANDARD55_OHM_SE TOP,BOTTOM Y

=STANDARD

0.085 MM =STANDARD

=STANDARD0.076 MM

0.085 MM

0 MM

=DEFAULT

=STANDARD

0.120 MM

0.130 MM

0 MM

=DEFAULT

=STANDARD=STANDARD

=STANDARD

0.1 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

General Spacing Definitions

Default

DEFAULT * 0.1 MM

*

Fixed and Dielectric

1:1_SPACING * 0.1 MM

BGA

*

Power and Common

GND_P2MM

PWR_P2MM * =2:1_SPACING

=DEFAULTSTANDARD

0.070 MM*1X_DIELECTRIC

=STANDARDBGA_P1MM

=STANDARDGND *

=2:1_SPACING*

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

?

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

?

1000

1100

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Board Stack-up

Finished board thickness: 1.58 mm

Top

Signal

Prepreg

2

Plane

Prepreg

3

Signal

Prepreg

4

Plane

Core

5

Plane

Prepreg

6

Signal

Prepreg

2

Plane

Prepreg

Btm Signal

1/3 OZ (CU PLATED)

0.070 MM

1/3 OZ (CU PLATED)

0.070 MM

0.5 OZ

0.435 MM

1 OZ

0.152 MM

1 OZ

0.435 MM

0.5 OZ

0.070 MM

1/3 OZ (CU PLATED)

0.070 MM

1/3 OZ (CU PLATED)

D

C

B

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

* Y80_OHM_DIFF

TOP,BOTTOM Y80_OHM_DIFF =STANDARD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

* Y85_OHM_DIFF =STANDARD

TOP,BOTTOM Y85_OHM_DIFF =STANDARD0.085 MM

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

TOP,BOTTOM 0.085 MM =STANDARD90_OHM_DIFF

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

100_OHM_DIFF *

100_OHM_DIFF =STANDARD0.085 MMYTOP,BOTTOM

ALLOW ROUTE

ON LAYER?

ALLOW ROUTE

ON LAYER?

ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

Y 0.115 MM

ALLOW ROUTE

ON LAYER?

MINIMUM LINE WIDTH

0.085 MM0.140 MM

0.108 MM 0.076 MM

0.125 MM

0.099 MM

0.076 MM

0.095 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD0.120 MM 0.076 MM

0.140 MM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

0.1 MM

BGA Area Constraints

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.150 MM

=STANDARD* Y90_OHM_DIFF

0.170 MM

0.175 MM

=STANDARDY 0.080 MM 0.076 MM

0.200 MM

0.210 MM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

0.1 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

0.1 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

0.1 MM

TABLE_PHYSICAL_RULE_ITEM

0.1 MM

* BGA_P1MM* BGA

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

B

A

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DDR3

DDR3-specific Physical Rules

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ALLOW ROUTE

ON LAYER?

*

*DDR_COMP Y 0.305 MM =STANDARD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

POWER_DDR_P4MM 0.100 MM0.400 MM 3.0 MM

ALLOW ROUTE

ON LAYER?

Y*

Physical Net Type to Rule Map

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

POWER_DDR_P4MMPOWER_DDR *

TABLE_PHYSICAL_ASSIGNMENT_ITEM

* DDR_70DDDR_CLK_PHY

TABLE_PHYSICAL_ASSIGNMENT_ITEM

DDR_40SDDR_CTRL_PHY *

TABLE_PHYSICAL_ASSIGNMENT_ITEM

* DDR_40SDDR_CMD_PHY

TABLE_PHYSICAL_ASSIGNMENT_ITEM

DDR_40S*DDR_DQ_PHY

TABLE_PHYSICAL_ASSIGNMENT_ITEM

DDR_70D*DDR_DQS_PHY

TABLE_PHYSICAL_ASSIGNMENT_ITEM

DDR_COMP_PHY DDR_COMP*

DDR3-specific Spacing Definitions

*DDR_CLK_ISO

*DDR_CTRL_ISO

*DDR_CMD2CMD

DDR_DATA_ISO * =4:1_SPACING

*

DDR_DQ2DQ * =2:1_SPACING

*DDR_DQ2DQS

DDR_COMP_ISO 0.381 MM

*

=5:1_SPACING

=3.5:1_SPACING

=2:1_SPACING*DDR_CTRL2CTRL

=3.5:1_SPACING*DDR_CMD_ISO

=2:1_SPACING

=3:1_SPACINGDDR_STROBE_ISO

=3:1_SPACING

=3:1_SPACING*DDR_BL2BL

=6.5:1_SPACINGDDR_CH2CH *

MINIMUM LINE WIDTH

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SEDDR_40S

=50_OHM_SE=50_OHM_SE=50_OHM_SE=50_OHM_SEDDR_50S *

=70_OHM_DIFF=70_OHM_DIFF=70_OHM_DIFFDDR_70D *

=73_OHM_DIFFDDR_73D * =73_OHM_DIFF =73_OHM_DIFF

=73_OHM_DIFF

=70_OHM_DIFF

0.105 MM

MINIMUM LINE WIDTH

DDR3 Power-specific Spacing Definitions

POWER_DDR =2:1_SPACING*

Main Segment Min Spacing Rules (mils) (HSW U/Y PDG, Intel Doc# 502636)

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

900

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

BDW does not have a separate power spec from HSW, so this document is still accurate

Table

6-14

6-14 13.78

6-14

Trace Design

4

(diff)

7.87

7.5

7.87

7.5

Iso

16

12

16

12

7.5

12

16

?

-

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

TABLE_PHYSICAL_RULE_ITEM

=70_OHM_DIFF=70_OHM_DIFF

=73_OHM_DIFF

=STANDARD

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=73_OHM_DIFF

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD

Minimum diff spacing is 4 mil

Table 4-5, Intel Doc# 486712

?

Design

19.69 CLK trace spacing controlled by =70_OHM_DIFF.

13.787.5

11.817.87

11.81

7.87

11.81

25.59

Comments

DQ to other signals not in the same bytelane (but not ch)

DQS to other signals of the same channel

DQ to DQ in the same bytelane of the same channel

DQ to DQS in the same bytelane of the same channel

DQ or DQS in different bytelanes of the same channel

DQ or DQS in different channels. ISO RULE NOT IN PDG

DDR3 to any other signal not DDR3

DDR3

Electrical Contraint Set

Channel A

I178

I179

I258

I259

I262

I181

I182

I180

I247

I183

I184

I188

I189

I191

I190

I192

I193

I194

I195

I196

I197

I198

I199

I200

I201

I203

I202

I204

I205

I206

I207

I208

I209

I210

I211

Channel B

I212

I213

I260

I261

I263

I215

I216

DDR_A_CLK0 DDR_CLK_PHY DDR_CLK

DDR_A_CLK1 DDR_CLK_PHY DDR_CLK

DDR_A_CS0 DDR_CTRL_PHY DDR_CTRL

DDR_A_CS1 DDR_CTRL_PHY DDR_CTRL

DDR_A_ODT DDR_CTRL_PHY DDR_CTRL

DDR_A_DQS0 DDR_DQS_PHY DDR_A_DQS0

DDR_A_DQS1 DDR_DQS_PHY DDR_A_DQS1

DDR_A_DQS2 DDR_DQS_PHY DDR_A_DQS2

DDR_A_DQS3 DDR_DQS_PHY DDR_A_DQS3

DDR_A_DQS4 DDR_DQS_PHY DDR_A_DQS4

DDR_A_DQS5 DDR_DQS_PHY DDR_A_DQS5

DDR_A_DQS6 DDR_DQS_PHY DDR_A_DQS6

DDR_A_DQS7 DDR_DQS_PHY DDR_A_DQS7

DDR_B_CLK0 DDR_CLK_PHY DDR_CLK

DDR_B_CLK1 DDR_CLK_PHY DDR_CLK

DDR_B_CS0 DDR_CTRL_PHY DDR_CTRL

DDR_B_CS1 DDR_CTRL_PHY DDR_CTRL

DDR_B_ODT DDR_CTRL_PHY DDR_CTRL

SpacingPhysical

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_ODT<0>

???

MEM_A_CKE<1..0>

MEM_A_CKE<3..2>

MEM_A_CAA<9..0>

MEM_A_CAB<9..0>

MEM_A_DQ<7..0>

MEM_A_DQ<15..8>

MEM_A_DQ<23..16>

MEM_A_DQ<31..24>

MEM_A_DQ<39..32>

MEM_A_DQ<47..40>

MEM_A_DQ<55..48>

MEM_A_DQ<63..56>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_ODT<0>

25 21 7

25 22 7

25 22 21 7

25 21 7

25 22 7

25 21 7

25 22 7

19 7

25 23 7

25 24 7

25 24 23 7

D

C

B

A

Constraints Clocks: CK[3:0], CK#[3:0]

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

Control: CS#[3:0], CKE[3:0], ODT[3:0]

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

DDR_CTRL DDR_CTRL_ISO* *

DDR_CTRLDDR_CTRL * DDR_CTRL2CTRL

Command: MA[15:0], RAS#, CAS#, WE# BS[2:0]

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

DDR_CMD DDR_CMD_ISO* *

DDR_CMDDDR_CMD DDR_CMD2CMD*

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

**DDR_COMP DDR_COMP_ISO

Data: DQS[7:0], DQS#[7:0], DQ[63:0]

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

DDR_CLK_ISO* *DDR_CLK

DDR_A_DQ_BYTE* * * DDR_DATA_ISO

DDR_STROBE_ISO*DDR_A_DQS* *

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

DDR_B_DQ_BYTE* * * DDR_DATA_ISO

DDR_STROBE_ISODDR_B_DQS* * *

=SAMEDDR_*_DQ_BYTE* * DDR_DQ2DQ

DDR_A_DQ_BYTE* DDR_A_DQS* * DDR_DQ2DQS

DDR_A_DQ_BYTE* DDR_A_DQ_BYTE* DDR_BL2BL*

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Note (1):

Deliberately set DQ to DQS spacing to 3:1 to avoid adding

complexity to contraints, even though it can be less. Only

one rule per channel is needed by trading off a little space.

Note (2):

Intel suggests 25 mil (0.65 mm) spacing for via to channel,

and via to pad to two different channels. DDR3 draws about

20 mA per trace with edge rates in the 100s of ps. The main

coupling mechanism is capacitive. A 0.65 mm spacing is used

for power nets, which draw far more current (inductive

coupling however). These rules are far too conservative.

To meet these rules, the spacing must be applied to the net.

DDR_B_DQS* DDR_DQ2DQS*DDR_B_DQ_BYTE*

DDR_BL2BLDDR_B_DQ_BYTE* DDR_B_DQ_BYTE* *

*DDR_A_* DDR_B_* DDR_CH2CH

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

See Note (3)

TABLE_SPACING_ASSIGNMENT_ITEM

See Note (1)

TABLE_SPACING_ASSIGNMENT_ITEM

See Note (3)

TABLE_SPACING_ASSIGNMENT_ITEM

See Note (1)

TABLE_SPACING_ASSIGNMENT_ITEM

See Note (2)

I214

I250

I217

I218

I222

I223

I225

I224

I226

I227

I228

I229

I230

I231

I232

I233

I234

I235

I237

I236

I238

I239

I240

I241

I242

I243

I244

I245

SM COMP

I257

DDR_B_DQS0 DDR_DQS_PHY DDR_B_DQS0

DDR_B_DQS1 DDR_DQS_PHY DDR_B_DQS1

DDR_B_DQS2 DDR_DQS_PHY DDR_B_DQS2

DDR_B_DQS3 DDR_DQS_PHY DDR_B_DQS3

DDR_B_DQS4 DDR_DQS_PHY DDR_B_DQS4

DDR_B_DQS5 DDR_DQS_PHY DDR_B_DQS5

DDR_B_DQS6 DDR_DQS_PHY DDR_B_DQS6

DDR_B_DQS7 DDR_DQS_PHY DDR_B_DQS7

???

??

MEM_B_CKE<1..0>

MEM_B_CKE<3..2>

MEM_B_CAA<9..0>

MEM_B_CAB<9..0>

MEM_B_DQ<7..0>

MEM_B_DQ<15..8>

MEM_B_DQ<23..16>

MEM_B_DQ<31..24>

MEM_B_DQ<39..32>

MEM_B_DQ<47..40>

MEM_B_DQ<55..48>

MEM_B_DQ<63..56>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

CPU_SM_RCOMP<0..2>

25 23 7

25 24 7

25 23 7

25 24 7

19 7

6

B

Note (3):

In order for the constraints DDR_*_DQ_BYTE* to =SAME to win

out over DDR_{A,B}_DQ_BYTE* to DDR_{A,B}_DQ_BYTE* so that

the small intra-bytelane spacing is used, the spacing rule

DDR_DQ2DQ must have a weight greater than DDR_BL2BL.

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PCI Express

PCIe-specific Physical Rules

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

PCIE_85D

* =90_OHM_DIFF

PCIE_COMP =STANDARD0.305 MM*

CPU_50S

* =50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SE

Physical Net Type to Rule Map

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

* PCIE_COMPCOMP_PCIE_PHY

CPU_ASYNC_PHY * CPU_50S

ALLOW ROUTE

ON LAYER?

=85_OHM_DIFF* =85_OHM_DIFF

=90_OHM_DIFFPCIE_90D

PCIE_90DCLK_PCIE_PHY *

MINIMUM LINE WIDTH

=90_OHM_DIFF =90_OHM_DIFF

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

=85_OHM_DIFF=85_OHM_DIFF

0.105 MMY

PCIe and DMI Compensation Rules (mils)

Table

4-5 50

50

DesignImp

50 504-7

Iso

15

Design

15.75

8 15.75

=85_OHM_DIFF

=90_OHM_DIFF

=STANDARD

=85_OHM_DIFF

=90_OHM_DIFF

=STANDARD

=STANDARD =STANDARD

Comments

PCIe. Impedance inferred from Table 4-7.

DMI. Numbers based on Intel stack-up.

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

CPU ASYNCHRONOUS

PCIe (CPU)

Electrical Contraint Set SpacingPhysical Physical SpacingElectrical Contraint Set

CPU OPI Compensation

I573

I574

I575

I576

I578

I577

I583

I581

I584

I585

I582

PECI

?

CPU_ASYNCCPU_ASYNC_PHY

CPU_ASYNC_MSCPU_ASYNC_PHY

CPU_ASYNCCPU_ASYNC_PHY

??

CPU_PROCHOT_R_L

CPU_PECI

SMC_PECI_L

CPU_CATERR_L

CPU_PWRGD

PM_THRMTRIP_L

CPU_VCCST_PWRGD

XDP_CPU_VCCST_PWRGD

PLT_RESET_L

XDP_BPM_L<1..0>

6

44 6

44 43

44 6

6

44 15

17 16 8

16

18 16 15 13

16 6

I570

CPU eDP Compensation

I571

I572

COMP_PCIECOMP_PCIE_PHYCPU_ASYNCCPU_ASYNC_PHY

COMP_PCIECOMP_PCIE_PHY

CPU_OPI_RCOMPCPU_PROCHOT_L

MCP_EDP_RCOMP

CPU_CFG_RCOMP

6 57 44 43 6

5

6

D

C

PCIe-specific Spacing Definitions

CLK_PCIE_ISO

COMP_PCIE_ISO =4:1_SPACING

*

CPU_MS_ISO TOP,BOTTOM =4.5:1_SPACING

CPU_MS_ISO =3:1_SPACING*

=5:1_SPACING*

=3:1_SPACING*CPU_ASYNC_ISO

Spacing Constraints

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

* *CLK_PCIE CLK_PCIE_ISO

COMP_PCIE ** COMP_PCIE_ISO

CPU_ASYNC ** CPU_ASYNC_ISO

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

C

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

CPU_MS_ISOCPU_ASYNC_MS **

B

PEG Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

ImpSection

4.2.1 8080

Iso

DesignDesign

15.7516

Comments

PCIe Gen3. Allow looser spacing for same direction on stripline per Anil

B

A

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Physical Net Type to Rule Map

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

*PCIE_PHY PCIE_85D

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PCIe (PCH)

Electrical Contraint Set

Physical

Spacing

345678

2 1

D

PCIe-specific Spacing Definitions

TOP,BOTTOM =5X_DIELECTRICPCIE_SAME_DIR

*PCIE_SAME_DIR =3.5X_DIELECTRIC

PCIE_ALT_DIR

PCIE_ISO

* =5X_DIELECTRIC

* =4:1_SPACING

TBT x4 PCIE Spacing Constraints

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

PCIE_TBT_R2D * PCIE_SAME_DIRPCIE_TBT_R2D

PCIE_TBT_D2R *PCIE_TBT_D2R PCIE_SAME_DIR

x4 Thunderbolt

I140

I141

I132

I133

I134

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

*PCIE_TBT_D2R PCIE_ALT_DIRPCIE_TBT_R2D

TABLE_SPACING_ASSIGNMENT_ITEM

I135

I179

I180

I181

I182

I183

I184

I185

I186

I136

I137

I138

I139

I187

I188

I190

I189

CLK_PCIECLK_PCIE_PHYPCIE_REF_CLK_CONN

???

??

PCIE_TBT_R2DPCIE_PHYPCIE_GEN2_R2D_RVSD

PCIE_TBT_R2DPCIE_PHY

PCIE_TBT_D2RPCIE_PHYPCIE_GEN2_D2R

PCIE_TBT_D2RPCIE_PHY

???

??

PCIE_TBT_D2RPCIE_PHYPCIE_GEN2_D2R

PCIE_TBT_D2RPCIE_PHY

PCIE_CLK100M_TBT_P

PCIE_CLK100M_TBT_N

PCIE_TBT_R2D_P<2..0>

PCIE_TBT_R2D_N<2..0>

PCIE_TBT_R2D_C_P<2..0>

PCIE_TBT_R2D_C_N<2..0>

PCIE_TBT_R2D_P<3>

PCIE_TBT_R2D_N<3>

PCIE_TBT_R2D_C_P<3>

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_D2R_P<0>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_C_P<0>

PCIE_TBT_D2R_C_N<0>

PCIE_TBT_D2R_P<2..1>

PCIE_TBT_D2R_N<2..1>

PCIE_TBT_D2R_C_P<2..1>

PCIE_TBT_D2R_C_N<2..1>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_C_P<3>

PCIE_TBT_D2R_C_N<3>

26

26 12

26 14

D

26 14

PCIE_ISO**PCIE_TBT_D2R

TABLE_SPACING_ASSIGNMENT_ITEM

** PCIE_ISOPCIE_TBT_R2D

x1 AirPort

I142

I143

I144

I146

I145

I147

PCIEPCIE_PHYPCIE_GEN2_R2D_CONN_AP

PCIEPCIE_PHY

PCIEPCIE_PHYPCIE_GEN2_D2R_CONN_AP

PCIE_AP_R2D_P

PCIE_AP_R2D_N

PCIE_AP_R2D_C_P

PCIE_AP_R2D_C_N

PCIE_AP_D2R_P

PCIE_AP_D2R_N

31

31 14

C

PCH x1 PCIE Constraints

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

*PCIE PCIE_ISO*

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

I148

I149

x1 Caesar IV

I151

I150

I152

I154

I153

I155

I156

I157

I158

I159

x2 SSD

I172

I173

PCH PCIE Compensation

I178

C

CLK_PCIECLK_PCIE_PHYPCIE_REF_CLK

PCIEPCIE_PHYPCIE_GEN2_R2D

PCIEPCIE_PHY

PCIEPCIE_PHYPCIE_GEN2_D2R

PCIEPCIE_PHY

CLK_PCIECLK_PCIE_PHYPCIE_REF_CLK

CLK_PCIECLK_PCIE_PHYPCIE_REF_CLK_CONN

COMP_PCIECOMP_PCIE_PHY

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

PCIE_ENET_R2D_P

PCIE_ENET_R2D_N

PCIE_ENET_R2D_C_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

PCIE_ENET_D2R_C_P

PCIE_ENET_D2R_C_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PCH_PCIE_RCOMP

31 12

34

34 14

34

34 12

32 12

14

B

A

PAGE TITLE

PCH PCIe/DMI Constaints

DRAWING NUMBER SIZE

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE INC. THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

8 7 5 4 2 1

36

REVISION

BRANCH

PAGE

SHEET

SYNC_DATE=10/28/2013SYNC_MASTER=J70_DINI

051-00081

3.0.0

113 OF 123

72 OF 81

A

D

PCH XDP

Spacing

DesignIso

SATA Compensation Rules (mils)

SATA

SATA-specific Physical Rules

Physical Net Type to Rule Map

Comments

SATA Gen2, SATA Gen3

Design

SATA-specific Spacing Definitions

Section

90 SATA Gen2, SATA Gen3

Constraints

20

IsoDesign

SATA Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

Imp

15

15.2.1 95 23.62

Electrical Contraint Set

All signals default are 50 Ohm SE.

Physical

SATA

Imp

Table

15.755015-3

XDP-specific Physical Rules

XDP

Physical

CPU XDP

Physical Net Type to Rule Map

Isolation is for JTAG clocks.

Comments

15.75

DesignIso

-

Imp Design

5545-65

Section

1.5

Constraints

50

XDP-specific Spacing Definitions

Desktop Debug Design Guide (Intel Doc# 430883)

PCH SATA Port 1 (SSD)

CommentsDesign

PCH SATA Port 0 (HDD)

PCH SATA Compensation

Electrical Contraint Set Spacing

XDP

73 OF 81

COMP_SATACOMP_SATA_PHY

SATASATA_PHY_90

SATASATA_PHY_90SATA_R2D

XDPXDP_PHY

CLK_JTAGXDP_PHY

XDPXDP_PHY

XDPXDP_PHYXDP_CPU_CFG1_PD

XDPXDP_PHYXDP_CPU_CFG_PD

XDPXDP_PHY

XDPXDP_PHYXDP_CPU_CFG_PD

XDPXDP_PHYXDP_CPU_CFG

SATASATA_PHY_90SATA_D2R

CLK_JTAGXDP_PHYXDP_CPU_TCK

XDPXDP_PHYXDP_CPU_TMS

XDPXDP_PHYXDP_CPU_TRST_L

114 OF 123

3.0.0

051-00081

CPU_CFG<7..5>

???

CPU_CFG<10..8>

???

CPU_CFG<19..11>

???

PCIE_SSD_D2R_N<0..1>

???

PCIE_SSD_D2R_P<0..1>

???

SSD_R2D_C_N<0..1>

???

SSD_R2D_C_P<0..1>

???

XDP_BPM_L<7..2>

???

PCIE_SSD_R2D_N<0..1>

???

PCIE_SSD_R2D_P<0..1>

???

PCH_SATA_RCOMP

SATA_HDD_D2R_C_N

SATA_HDD_D2R_C_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_N

SATA_HDD_R2D_P

XDP_CPU_TDI

XDP_CPU_TDO

XDP_PCH_TCK

XDP_PCH_TDI

XDP_PCH_TDO

XDP_PCH_TMS

CPU_CFG<1>

CPU_CFG<0>

CPU_CFG<3>

?

CPU_CFG<4>

CPU_CFG<2>

SATA_HDD_D2R_N

SATA_HDD_D2R_P

XDP_CPU_TCK

XDP_CPU_TMS

XDP_CPU_TRST_L

=50_OHM_SE*SATA_50S =50_OHM_SE=50_OHM_SE =50_OHM_SE

=STANDARD=STANDARD

=85_OHM_DIFF*

=85_OHM_DIFF=85_OHM_DIFF

=85_OHM_DIFF=85_OHM_DIFF=85_OHM_DIFFSATA_85D

SATA_85D*SATA_PHY

SATA_90DSATA_PHY_90 *

COMP_SATA_PHY * SATA_50S

*SATA_90D

=90_OHM_DIFF =90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

SATA SATA_ISO**

COMP_SATA_ISOCOMP_SATA **

COMP_SATA_ISO

?

* =4:1_SPACING

?

*SATA_ISO =6:1_SPACING

* *CLK_JTAG CLK_JTAG_ISO

XDP_55S*XDP_PHY

XDP_ISO *

?

=2:1_SPACING

CLK_JTAG_ISO *

?

=4:1_SPACING

XDP_ISOXDP * *

=STANDARD

XDP_55S =55_OHM_SE=55_OHM_SE=55_OHM_SE*

=STANDARD

=55_OHM_SE

SYNC_DATE=10/23/2013

SATA/FDI/XDP Constraints

SYNC_MASTER=J70_TONY

I98

I96

I95

I94

I93

I92

I91

I90

I89

I88

I52

I51

I50

I49

I48

I47

I46

I45

I38

I37

I124

I123

I122

I121

I120

I119

I118

I117

I116

I115

I104

I103

I102

16 6

32 12

32

16 6

32 12

12

33

33 12

33

16 6

16 12

16 6

33 12

16 6

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

LPC Clocks

LPC-specific Spacing Definitions

Spacing

PhysicalElectrical Contraint Set Spacing

Spacing

PCH RTC 32K

Electrical Contraint Set

LPC

Crystal-specific Spacing Definitions

HDA

PCH-specific Spacing Definitions

SMC 32K

Spacing

SPDIF

PCH Clocks

PCH-specific Physical Rules

Electrical Contraint Set Physical

LPC

Physical

Electrical Contraint Set

PCH

HDA

SpacingPhysical

PCH Reference Clock

25M Reference Crystal

Crystal-specific Physical Rules

SPI ROM

Physical

HDA-specific Physical Rules

HDA

HDA-specific Spacing Definitions

LPC-specific Physical Rules

Electrical Contraint Set

SPI Bootrom

Crystal

SPI-specific Spacing Definitions

SPI-specific Physical Rules

SPI

25 MHz XTALS

74 OF 81

HDA_55S

HDA HDA

CLK_XTAL XTAL

HDA HDA

CLK_LPC_55S CLK_LPC

LPC_55S LPC

CLK_XTAL XTAL

CLK_PCH_55S CLK_PCH

HDA_55S

SPI_50S SPI

CLK_XTAL XTAL

HDA HDAHDA_CLK

HDA HDAHDA_RST

HDA HDAHDA_IN

HDA HDAHDA_OUT

HDA HDAHDA_SYNC

115 OF 123

3.0.0

051-00081

LPC_AD<3..0>

??

LPC_AD_R<3..0>

??

CS4208_SPDIF_IN

?

CS4208_SPDIF_OUT

?

DP_INT_SPDIF_AUDIO

ENET_XTAL_IN

ENET_XTAL_OUT

ENET_XTAL_OUT_R

HDA_BIT_CLK_R

HDA_RST_R_L

HDA_SDOUT_R

HDA_SYNC_R

LPC_CLK24M_SMC

LPC_CLK24M_SMC_R

LPC_FRAME_L

LPC_FRAME_R_L

PCH_CLK24M_XTALIN

PCH_CLK24M_XTALOUT

PCH_CLK24M_XTALOUT_R

PCH_CLK32K_RTCX1

PCH_CLK32K_RTCX2

PCH_CLK32K_RTCX2_R

PM_CLK32K_SUSCLK_R

SMC_CLK32K

SPDIF_OUT_JACK

?

SPIROM_USE_MLB

SPI_ALT_CLK

SPI_ALT_CS_L

SPI_ALT_MISO

SPI_ALT_MOSI

SPI_CLK

SPI_CLK_R

SPI_CS0_L

SPI_CS0_R_L

SPI_MISO

SPI_MLB_CLK

SPI_MLB_CS_L

SPI_MLB_MISO

SPI_MLB_MOSI

SPI_MOSI

SPI_MOSI_R

SPI_SMC_CLK

SPI_SMC_CS_L

SPI_SMC_MISO

SPI_SMC_MOSI

TBT_CLK25M_IN

TBT_CLK25M_OUT

TBT_CLK25M_OUT_R

HDA_BIT_CLK

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

HDA_SYNC

SYNC_DATE=10/15/2013

PCH and BR Constraints

SYNC_MASTER=J70_NICK

*

?

=2x_DIELECTRICHDA_ISO

=STANDARD=STANDARD

* =55_OHM_SE=55_OHM_SECLK_LPC_55S =55_OHM_SE =55_OHM_SE

?

* =2:1_SPACINGCOMP_PCH_ISO

?

* =1.5:1_SPACINGLPC_ISO

?

=4:1_SPACING*CLK_PCH_ISO

?

* =2:1_SPACINGCLK_LPC_ISO

=55_OHM_SE

=STANDARD

=55_OHM_SE =55_OHM_SEPCH_55S =55_OHM_SE*

=STANDARD

=55_OHM_SECLK_PCH_55S *

=STANDARD=STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE* =55_OHM_SE=55_OHM_SE =55_OHM_SEHDA_55S

=STANDARD

=55_OHM_SE

=STANDARD

=55_OHM_SE*

=STANDARD

=55_OHM_SELPC_55S =55_OHM_SE

=100_OHM_DIFFCLK_XTAL * =100_OHM_DIFF =100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

?

* =2:1_SPACINGSPI_ISO

=STANDARD

*

=STANDARD

SPI_55S =55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

=STANDARD

*

=STANDARD

=50_OHM_SE =50_OHM_SE =50_OHM_SE =50_OHM_SESPI_50S

* =4X_DIELECTRIC

?

XTAL_ISO

* *SPI SPI_ISO

**XTAL XTAL_ISO

**HDA HDA_ISO

** LPC_ISOLPC

**CLK_LPC CLK_LPC_ISO

**COMP_PCH COMP_PCH_ISO

** CLK_PCH_ISOCLK_PCH

I421

I420

I419

I418

I417

I413

I412

I411

I410

I409

I408

I407

I405

I404

I403

I401

I400

I399

I397

I396

I395

I394

I393

I392

I391

I388

I386

I384

I381

I380

I379

I371

I370

I368

I367

I366

I365

I364

I363

I362

I361

I353

I352

I350

I349

I348

I347

I342

I341

I338

I337

I336

I335

43 14

14

51

80 51 39

34 17

17

12

17 12

12

43 17

17 12

43 14

14

17 12

17

17 12

17

44 13

44 43

54 51

45 15

45

45 14

45

45 14

45

45 14

45 43

26 17

17

51 12

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

Physical Net Type to Rule Map

USB 3.0 and USB 2.0 Trixies Muxing

External Port A (J4600)

Design

CIV-specific Physical Rules

2 kV isolation

External Port D (J4710)

RMH Love

Electrical Contraint Set Spacing

USB 3.0

SD

Physical

Electrical Contraint Set

Camera Processor's SMIA Interface Spacing Definitions

Spacing

CIV SPI

Spacing

Camera (J3510)

CIV-specific Spacing Definitions Ethernet Ethernet

Constraints

USB-specific Spacing Definitions

Caesar IV (Ethernet/SD)

Spacing

USB

Comments

USB 2.0

21.65

11.81

20

Iso

12

Design

90

Imp

90

8513.3.1 85

12.2.1

Section

Physical

PCH USB Compensation

Constraints

External Port C (J4700)

SD

Camera Processor's SMIA Interface Physical Rules

Camera Processor-to-Camera Sensor I/F (SMIA/MIPI)

SD

Ethernet

PhysicalElectrical Contraint Set

USB-specific Physical Rules

External Port B (J4610)

Physical

Camera Processor-Camera Sensor I/F

Electrical Contraint Set

Et tu Brute?

USB Min Spacing Rules (mils) (Maho Bay PDG, Intel Doc# 473718)

Physical Net Type to Rule Map

75 OF 81

USB2_PHY USB2USB2_CONN

USB2_PHY USB2USB2_MUXED_MOJO_CONN

USB2_PHY USB2USB2_CONN

USB2USB2_PHYUSB2_CONN

USB2_PHY USB2USB2_CONN

SPISPI_50S

ENET_TRANS

SPICIV_SPI

SDSD_PHY

SPICIV_SPI

COMP_ENETENET_COMP_PHY

SPICIV_SPI

SDSD_PHY

SMBSMB_PHY

COMP_PCHPCH_55S

SDSD_PHY

USB2USB2_PHY

USB3USB3_PHY

USB3USB3_PHYUSB3_TX_CONN_RVSD

USB3USB3_PHY

USB3USB3_PHYUSB3_TX_CONN_RVSD

USB3USB3_PHY

USB3USB3_PHYUSB3_TX_CONN

USB3USB3_PHY

SDSD_PHYSD_CLK

SDSD_PHYSD_CMD

SMIA_DIFFSMIA_DIFF_PHYSMIA_DP

USB3USB3_PHYUSB3_RX_CONN

USB3USB3_PHYUSB3_TX_CONN_RVSD

USB3USB3_PHYUSB3_RX_CONN

USB3USB3_PHYUSB3_TX_CONN_RVSD

USB3USB3_PHYUSB3_RX_CONN

USB3USB3_PHYUSB3_TX_CONN

USB3USB3_PHYUSB3_RX_CONN_RVSD

USB2USB2_PHYUSB2_MUXED_BT

USB2USB2_PHYUSB2_CONN_INT

USB3USB3_PHY

USB3USB3_PHYUSB3_TX_CONN

USB3USB3_PHY

USB2USB2_PHY

116 OF 123

3.0.0

051-00081

? ? ?

ENETCONN_MDI_N<3..0>

? ?

ENETCONN_MDI_T_N<3..0>

? ?

ENETCONN_MDI_T_P<3..0>

? ? ?

ENET_CR_DATA<7..0>

? ?

SDCONN_DATA<7..0>

? ? ?

ENETCONN_MDI_P<3..0>

USB_EXTB_P

USB_EXTA_N

USB_EXTA_P

USB_EXTB_N

USB_EXTC_N

USB_EXTC_P

USB_EXTD_N

USB_EXTD_P

CAM_SF_CLK

CAM_SF_CLK_R

CAM_SF_CS_L

CAM_SF_DIN

CAM_SF_DIN_R

CAM_SF_DOUT

CAM_SF_DOUT_R

CAM_SF_WP_L

ENETCONN_MCT0

ENETCONN_MCT1

ENETCONN_MCT2

ENETCONN_MCT3

ENETCONN_MCT_BS

ENET_CS_L

ENET_MEDIA_SENSE

ENET_MISO

ENET_MOSI

ENET_RDAC

ENET_SCLK

ENET_SD_DETECT_L

I2C_CAMSENSOR_SCL

I2C_CAMSENSOR_SDA

PCH_USB_RBIAS

SDCONN_CLK

SDCONN_CLK_R

SDCONN_CMD

USB2_EXTA_MUXED_N

USB2_EXTA_MUXED_P

USB2_EXTA_N

USB2_EXTA_P

USB2_EXTB_N

USB2_EXTB_P

USB2_EXTC_P

USB2_EXTD_N

USB2_EXTD_P

USB3_EXTA_D2R_F_N

USB3_EXTA_D2R_F_P

USB3_EXTA_R2D_CF_N

USB3_EXTA_R2D_CF_P

USB3_EXTA_R2D_F_N

USB3_EXTA_R2D_F_P

USB3_EXTA_R2D_P

USB3_EXTB_D2R_F_N

USB3_EXTB_D2R_F_P

USB3_EXTB_R2D_CF_N

USB3_EXTB_R2D_CF_P

USB3_EXTB_R2D_F_N

USB3_EXTB_R2D_F_P

USB3_EXTB_R2D_P

USB3_EXTC_D2R_F_N

USB3_EXTC_D2R_F_P

USB3_EXTC_R2D_CF_N

USB3_EXTC_R2D_CF_P

USB3_EXTC_R2D_F_N

USB3_EXTC_R2D_F_P

USB3_EXTC_R2D_P

USB3_EXTD_R2D_CF_N

ENET_SD_CLK

ENET_SD_CMD

SMIA_CLK_N

SMIA_CLK_P

SMIA_DATA_N

SMIA_DATA_P

USB3_EXTA_D2R_N

USB3_EXTA_D2R_P

USB3_EXTA_R2D_N

USB3_EXTB_D2R_N

USB3_EXTB_D2R_P

USB3_EXTB_R2D_N

USB3_EXTC_D2R_N

USB3_EXTC_D2R_P

USB3_EXTC_R2D_N

USB3_EXTD_D2R_N

USB3_EXTD_D2R_P

USB_BT_MUX_N

USB_BT_MUX_P

USB_BT_N

USB_BT_P

USB_CAMERA_N

USB_CAMERA_P

USB3_EXTD_R2D_CF_P

USB3_EXTD_R2D_F_N

USB3_EXTD_R2D_F_P

USB3_EXTD_R2D_N

USB3_EXTD_R2D_P

USB3_EXTD_D2R_F_N

USB3_EXTD_D2R_F_P

USB2_EXTC_N

=3:1_SPACING*

?

USB2_ISO

SYNC_DATE=03/24/2014

USB/Ethernet/SD Constraints

SYNC_MASTER=J117_ANDRES

=3:1_SPACING

?

TOP,BOTTOMUSB2_ISO

=100_OHM_DIFF

ENET_100D * =100_OHM_DIFF

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

* =50_OHM_SE=50_OHM_SE

=STANDARD

ENET_50S =50_OHM_SE

=STANDARD

=50_OHM_SE

=STANDARD

SD_50S * =50_OHM_SE

=STANDARD

=50_OHM_SE=50_OHM_SE =50_OHM_SE

COMP_ENET * COMP_ENET_ISO*

=3:1_SPACINGENET_DIFF2DIFF *

?

*ENET_DIFF ENET_DIFF2DIFFENET_DIFF

** ENET_TRANS_ISOENET_TRANS

ENET_TRANS ENET_TRANS ENET_DIFF2DIFF*

SD ** SD_ISO

=100_OHM_DIFF

* =100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

SMIA_100D

=6:1_SPACING

?

SMIA_DIFF_ISO * *SMIA_DIFF * SMIA_DIFF_ISO

USB3 * * USB3_ISO

ENET_DIFF_PHY * ENET_100D

SD_PHY * SD_50S

=85_OHM_DIFF =85_OHM_DIFFUSB_85D

=85_OHM_DIFF

=85_OHM_DIFF*

=85_OHM_DIFF

ENET_DIFF_ISO* *ENET_DIFF

1.27 MM*ENET_TRANS_ISO

?

=6:1_SPACING

?

*ENET_DIFF_ISO

=4:1_SPACING*COMP_ENET_ISO

?

SMIA_DIFF_PHY * SMIA_100D

=3:1_SPACING

?

*SMIA_DIFF2DIFF

CIV_SPI * SPI_55S

ENET_COMP_PHY * ENET_50S

* SMIA_DIFF2DIFFSMIA_DIFF SMIA_DIFF

=3:1_SPACING*

?

SD_ISO

* *USB2 USB2_ISO

?

TOP,BOTTOMUSB3_ISO =5.5:1_SPACING

=5.5:1_SPACINGUSB3_ISO *

?

USB3_PHY USB_85D*

USB_90D*USB2_PHY

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF*USB_90D

I523

I522

I521

I520

I519

I518

I517

I514

I513

I512

I511

I510

I509

I508

I507

I506

I505

I504

I503

I502

I501

I500

I499

I498

I497

I496

I495

I494

I493

I492

I491

I490

I489

I488

I486

I485

I484

I483

I482

I481

I480

I479

I478

I477

I476

I475

I474

I468

I466

I462

I461

I460

I459

I458

I457

I456

I455

I454

I453

I452

I450

I446

I445

I444

I443

I442

I441

I440

I439

I438

I437

I434

I433

I430

I429

I428

I427

I426

I425

I424

I423

I422

I421

I420

I419

I418

I417

I416

I415

I414

I413

I410

I409

I394

I393

I392

I391

I384

I326

I324

I321

I320

35 34

35

34

36 34

35 34

41 14

42 14

37

35

34

34 15

34

36 34

37

14

36 34

36

36 34

41

42

41

41 14

41

41 14

41

42

42 14

42

42 14

34

37

41 14

41

41 14

41

42 14

42

42 14

31

31 14

37 14

42 14

42

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_ITEM

Sensor-specific Physical Rules

Spacing

PCH

Sensor-specific Spacing Definitions

SMC Generic Control Line Spacing Definitions

Constraints

SMBus-specific Spacing Definitions

Physical Net Type to Rule Map

SMBus

SMC

Spacing

Constraints

Physical

Common

SMBus

SMC

SMC Generic Control Line Physical Rules

Physical Net Type to Rule Map

Electrical Contraint Set

Physical

Electrical Contraint Set

SSD

Physical

Current/Voltage Sense

Electrical Contraint Set Spacing

SSD Out-of-Band

Temperature Sense

Electrical Contraint Set

TMP423 (Development)

SMBus-specific Physical Rules

Physical Net Type to Rule Map

CPU Core

EMC1414-1 (Production)

Physical Spacing

Sensor

Constraints

HDD Out-of-Band

12V S5 (System Total)

VDDQ S3 (DDR)

76 OF 81

SENSE

SENSESNS_DIFF_PHY

TBT_I2CTBT_I2C_55S

SMBSMB_PHY

SENSESNS_DIFF_PHYSNS_CURRENT

SENSE

SMBSMB_PHY

SMC_CTRLSMC_GEN

XTALCLK_XTAL

SMC_CTRLSMC_GEN

XTALCLK_XTAL

SENSE

SNS_TEMP SENSESNS_DIFF_PHY

SENSESNS_DIFF_PHYSNS_CURRENT

SNS_CURRENT SENSESNS_DIFF_PHY

SNS_DIFF_PHY SENSESNS_CURRENT

SENSESNS_DIFF_PHYSNS_CURRENT

117 OF 123

3.0.0

051-00081

ISNS_SSDS4_R

?

ISNS_SSDS4

VSNS_P3V3_SSD

CPUVR_IMON

VSNS_CPUVCC

ISNS_CPUVCC

SMC_OOB2_D2R_L

SMC_OOB2_R2D_L

SMC_OOB1_R2D_R_L

SMC_OOB1_R2D_L

SMC_OOB1_D2R_L

HDD_OOB1_D2R_R_L

HDD_OOB1_D2R_F_L

HDD_OOB1_D2R_L

SNS_T1_2_N

SNS_T1_2_P

SMBUS_PCH_CLK

SMBUS_PCH_DATA

SML_PCH_0_DATA

SML_PCH_0_CLK

SMBUS_SMC_2_S0_SCL

SMBUS_SMC_2_S0_SDA

SMBUS_SMC_3_SCL

SMBUS_SMC_5_G3H_SCL

SMBUS_SMC_3_SDA

SMBUS_SMC_1_S0_SDA

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_5_G3H_SDA

SNS_SSD_N

SNS_SSD_P

ISNS_P1V2_S3_DDR_R

VSNS_P12VG3H

ISNS_P12VG3H_R

ISNS_P12VG3H

GND_SMC_AVSS

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

SMC_FAN_0_CTL

SMC_FAN_0_TACH

SMC_LRESET_L

SMC_RUNTIME_SCI_L

SMC_XTAL

SMC_WAKE_SCI_L

SMC_EXTAL

VSNS_P1V2_S3_DDR

ISNS_P1V2_S3_DDR

SNS_T2_3_N

SNS_T2_3_P

SNS_T2_2_N

SNS_T2_2_P

SNS_T2_1_N

SNS_T2_1_P

SNS_T1_1_P

SNS_T1_1_N

SNS_T1_3_P

SNS_T1_3_N

SNS_ACDC_N

SNS_ACDC_P

SNS_P12VG3H_P

SNS_P12VG3H_N

SNS_P1V2_S3_DDR_N

SNS_P1V2_S3_DDR_P

=1:1_SPACINGSMC_ISO *

?

SMB_ISO

?

* =2x_DIELECTRIC

*SMB_PHY SMB_55S

SMC_50S*SMC_GEN

=STANDARD

* =50_OHM_SE =50_OHM_SESMC_50S

=STANDARD

=50_OHM_SE =50_OHM_SE

** SENSE_ISOSENSE

POWER *SENSE PWR_P2MM

* SMB_ISOSMB *

SENSE GND_P2MM*GND

=55_OHM_SE=55_OHM_SE* =55_OHM_SE =55_OHM_SESMB_55S

=STANDARD=STANDARD

1:1_DIFFPAIR =STANDARD=STANDARD

0.085 MM0.1 MM

Y =STANDARD*

SNS_DIFF_PHY * 1:1_DIFFPAIR

*

?

SENSE_ISO =1.5:1_SPACING

SMC_ISO**SMC_CTRL

SYNC_MASTER=J70_NICK SYNC_DATE=10/15/2013

SMBus/Sensor Constraints

I94

I93

I92

I91

I90

I9

I89

I88

I87

I86

I85

I8

I78

I77

I76

I75

I74

I73

I72

I71

I70

I7

I69

I68

I67

I66

I65

I60

I6

I59

I58

I57

I54

I53

I52

I5

I46

I45

I42

I4

I36

I35

I34

I33

I32

I3

I21

I20

I2

I19

I16

I15

I14

I13

I124

I123

I12

I117

I116

I11

I10

I1

47

47 44

57 47

47 44

44 32

33

43 33

33

48

46 14

46 43

44 43

46 43

44 43

47

47 44

47

47 44

47 44 43

46 43

49 43

43 18

43 13

44 43

43 15

44 43

47 44

48

56 48

47

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_ITEM

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

Spacing Voltage

Input Bus

Physical

Input Bus

Output Bus

Local Ground

Switch

Output Bus

Switch

NO_TEST

1.8V S3

NO_TESTDIDTSpacingPhysical

DIDT

DC-DC Control

VDDQ (1.2V)/VTT (0.6V) S3

Input Bus

Local Ground

Power-specific Spacing Definitions

Input Bus

NO_TESTVoltageSpacingPhysical

Local Ground

PCH 1.05V S0

Power and Common

DC-DC

DC-DC Control

Power-specific Physical Rules

Output Bus

Sensed

Physical Spacing Voltage DIDT NO_TEST

VDDQ S3

Physical Net Type to Rule Map

DC-DC Baddies

DIDT

Output Bus

1.05V S0

DC-DC Baddies

Power and Common

Electrical Contraint Set

Voltage

Constraints

1.05V S5

77 OF 81

1.05V

VR_SWITCHVR_DIDT_PHY TRUE

POWERPOWER 5V

GNDGND 0V

VR_SWITCHVR_DIDT_PHY TRUE3.3V

VR_SWITCHVR_DIDT_PHY TRUE12V

VR_CTLVR_CTL_PHY

POWER_DDRPOWER_DDR 0.6V

VR_CTLVR_CTL_PHY

GNDGND 0V

POWERPOWER 1.05V

POWERPOWER 1.2V

POWERPOWER 5V

VR_SWITCHVR_DIDT_PHY TRUE12V

SENSE

VR_CTLVR_CTL_PHY

SENSE

VR_CTLVR_CTL_PHY

VR_SWITCHVR_DIDT_PHY TRUE12V

POWERPOWER 5V

VR_SWITCHVR_DIDT_PHY TRUE12V

VR_SWITCHVR_DIDT_PHY 12V TRUE

POWERPOWER 5V

VR_SWITCHVR_DIDT_PHY TRUE12V

POWERPOWER 1.2V

VR_CTLVR_CTL_PHY

VR_SWITCHVR_DIDT_PHY TRUE12V

POWER POWER 1.8V

VR_DIDT_PHY VR_SWITCH TRUE3.3V

POWER POWER 1.8V

SENSESNS_DIFF_PHYSNS_CURRENT

118 OF 123

3.0.0

051-00081

PP1V05_S5

REG_LGATE_P1V2_S3

PP5V_REG_P1V2_V5IN

AGND_P1V2_S3

REG_SW_P1V8_S3

REG_BOOT_P1V2_S3_RC

REG_BOOT_P1V2_S3

REG_P1V2_S3_TRIP

LDO_DDRVTTS0_SNS

PP0V6_S3_DDRVTT

REG_P1V2_S3_MODE

AGND_P1V05S0

AGND_P1V2_S3

PP1V05_S0

PP1V2_S3_DDR

PP5V_REG_P1V2_V5IN

REG_BOOT_P1V05S0

REG_BOOT_P1V05S0_RC

REG_LGATE_P1V05S0

REG_P1V05S0_FB

REG_P1V05S0_FSEL

REG_P1V05S0_OCSET

REG_P1V05S0_RTN

REG_P1V05S0_SREF

REG_P1V05S0_VO

REG_PHASE_P1V05S0

REG_PHASE_P1V05S0_L

REG_PVCC_U7400

REG_SNUBBER_P1V05S0

REG_UGATE_P1V05S0

REG_UGATE_P1V05S0_R

REG_VCC_U7400

REG_PHASE_P1V2_S3_L

REG_PHASE_P1V2_S3

PP1V2_S3

REG_P1V2_S3_VTTREF

REG_P1V2_S3_REFIN

REG_P1V2_S3_VREF

REG_P1V2_S3_VDDQSNS

REG_SNUBBER_P1V2_S3

REG_UGATE_P1V2_S3

PP1V8_S3

REG_FB_P1V8_S3

PP1V8_S3_REG_R

REG_P1V05S0_PHASE_SNS_M

REG_P1V05S0_PHASE_SNS_P

VR_VID_ISO* *VR_VID

VR_CTL_ISOVR_CTL * *

=STANDARD*

?

POWER_ISO

1000

SWNODE_ISO * =8:1_SPACING

POWER_50SVR_VID_PHY *

VR_SWITCH * BGA_P1MMBGA

GND *VR_SWITCH SWNODE_SW2GND

VR_SWITCH VR_SWITCH * SWNODE_SW2SW

0.300 MM 0.150 MM

=STANDARD

GND_P3MM

=STANDARD

Y* 12.7 MM

=STANDARD

0.150 MM* 0.600 MM

=STANDARD

YPOWER_P6MM 12.7 MM

GND * GND_P5MM

=STANDARD*

?

GND_ISO

=1:1_SPACINGSWNODE_SW2SW *

?

*GND * GND_ISO

POWER_P3MM*VR_CTL_PHY

VR_CTL_PHY STANDARDBGA

=2:1_SPACING*

?

SWNODE_SW2GND

STANDARDVR_DIDT_PHY BGA

POWER_P6MMVR_DIDT_PHY *

* =50_OHM_SEPOWER_50S =50_OHM_SE

=STANDARD

=50_OHM_SE

=STANDARD

=50_OHM_SE

=STANDARD

0.500 MM 0.150 MM

=STANDARD

* YGND_P5MM 12.7 MM

BGAPOWER POWER_P3MM

POWER_P6MMPOWER *

BGA GND_P3MMGND

12.7 MM

=STANDARD=STANDARD

0.300 MM 0.150 MMY*POWER_P3MM

=2:1_SPACING*

?

SWNODE_SW2PWR

SWNODE_ISO**VR_SWITCH

SWNODE_SW2PWRPOWERVR_SWITCH *

VR_CTL_ISO =3:1_SPACING

?

*

=4X_DIELECTRIC*VR_VID_ISO

?

SYNC_MASTER=J117_ANDRES

VReg Constraints

SYNC_DATE=03/24/2014

* POWER_ISO*POWER

I92

I9

I86

I85

I84

I83

I8

I70

I7

I69

I68

I67

I64

I62

I61

I60

I6

I59

I58

I57

I56

I55

I53

I52

I51

I5

I49

I48

I47

I46

I45

I44

I43

I4

I3

I22

I21

I20

I2

I19

I18

I14

I12

I11

I10

I1

16

59

77 59

59

66

59

60

77 59

66

77 59

60

59

66

59

66

59

60

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

Phase 1

Spacing

CPU VCC ControllerCPU VCC Phases

Electrical Contraint Set Electrical Contraint SetVoltage Voltage NO_TEST

Input Bus

Physical DIDTDIDT

Phase 2

Physical Spacing

ISL95826HRZ

Output Bus

NO_TEST

78 OF 81

VR_SWITCHVR_DIDT_PHY TRUE12V

VR_SWITCHVR_DIDT_PHY 12V TRUE

VR_SWITCHVR_DIDT_PHY TRUE12V

VR_SWITCHVR_DIDT_PHY 12V TRUE

VR_CTLVR_CTL_PHY

VR_SWITCHVR_DIDT_PHY 12V TRUE

VR_SWITCHVR_DIDT_PHY TRUE12V

VR_DIDT_PHY VR_SWITCH TRUE12V

VR_CTLVR_CTL_PHY

SENSE

VR_CTLVR_CTL_PHY

SENSE

VR_CTLVR_CTL_PHY

VR_SWITCHVR_DIDT_PHY 12V TRUE

VR_SWITCHVR_DIDT_PHY TRUE12V

VR_SWITCHVR_DIDT_PHY 12V TRUE

VR_SWITCHVR_DIDT_PHY TRUE12V

POWERPOWER 1.8V

POWERPOWER 5V

VR_VIDVR_VID_PHY

SENSE

VR_CTLVR_CTL_PHY

POWERPOWER 12V

SENSESNS_DIFF_PHYISNS_CPU_CORE

VR_VIDVR_VID_PHYCPU_VIDSOUT

VR_VIDVR_VID_PHYCPU_VIDSCLK

VR_VIDVR_VID_PHYCPU_VIDALERT_L

SENSESNS_DIFF_PHYVSNS_CPU_CORE

119 OF 123

3.0.0

051-00081

REG_UGATE_CPUVCC_2

REG_UGATE_CPUVCC_1

REG_SNUBBER_CPUVCC_2

REG_SNUBBER_CPUVCC_1

REG_PWM_CPUVCC_2

REG_PHASE_CPUVCC_2

REG_PHASE_CPUVCC_1

REG_LGATE_CPUVCC_2

REG_LGATE_CPUVCC_1

REG_CPUVCC_SLOPE

REG_CPUVCC_RTN

REG_CPUVCC_PROG3

REG_CPUVCC_PROG2

REG_CPUVCC_PROG1

REG_CPUVCC_NTC_R

REG_CPUVCC_NTC

REG_CPUVCC_ISUMP

REG_CPUVCC_ISUMN_RC

REG_CPUVCC_ISUMN_R

REG_CPUVCC_ISUMN

REG_CPUVCC_ISEN2

REG_CPUVCC_ISEN1

REG_CPUVCC_FCCM

REG_CPUVCC_FB_RC

REG_CPUVCC_FB2

REG_CPUVCC_FB

REG_CPUVCC_DRSEL

REG_CPUVCC_COMP_RC

REG_CPUVCC_COMP

REG_BOOT_CPUVCC_2_RC

REG_BOOT_CPUVCC_2

REG_BOOT_CPUVCC_1_RC

REG_BOOT_CPUVCC_1

PPCPUVCC_S0_SENSE_2

PPCPUVCC_S0_SENSE_1

PPCPUVCC_S0_CPU

PP5V_S0_REG_CPUVCC_VDD

CPU_VIDSOUT_R

CPU_VIDSCLK_R

CPU_VIDALERT_R_L

CPU_VCCSENSE_P_RC

CPU_VCCSENSE_P_R

REG_PWM_CPUVCC_1

PP12V_S0_REG_CPUVCC_VIN

REG_CPUVCC_ISNS2_P

REG_CPUVCC_ISNS2_M

REG_CPUVCC_ISNS1_P

REG_CPUVCC_ISNS1_M

CPU_VIDSOUT

CPU_VIDSCLK

CPU_VIDALERT_L

CPU_VCCSENSE_P

CPU_VCCSENSE_N

SYNC_DATE=03/24/2014SYNC_MASTER=J117_ANDRES

CPU VReg Constraints

I896

I895

I894

I893

I892

I890

I888

I887

I884

I1274

I1273

I1272

I1271

I1270

I1269

I1268

I1151

I1150

I1149

I1148

I1146

I1145

I1143

I1142

I1140

I1136

I1068

I1066

I1065

I1064

I1063

I1062

I1061

I1056

I1055

I1054

I1052

I1051

I1050

I1040

I1039

I1038

I1037

I1036

I1035

I1034

I1031

I1029

I1028

I1027

I1026

I1022

I1020

58

58 57

58

57

58 57

57

58 57

57

58

66

57

8

57

58 57

57

58

57 8

57 9

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

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SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

3.3V G3

Voltage

Physical

3.42V G3H

NO_TESTVoltagePhysical

Voltage

Physical

Ground/Common

Electrical Contraint Set

OUTPUT BUS

DIDTVoltage

5V S4

NO_TEST

Output Bus

Sensed

Common

DIDT

NO_TESTDIDTSpacingPhysical

Input Bus

3.3V S5

SpacingPhysical

NO_TESTDIDTVoltageSpacingPhysical

Input Bus

HDD S0

Physical Spacing DIDTVoltage NO_TEST

NO_TEST

FET Switched

1V5 S0

Spacing

FET Switched

DIDT

Voltage

NO_TEST

Sensed

NO_TESTDIDT

3.42V G3H

Output Bus

Spacing

3.3V S5/5V S4

Spacing

VoltageSpacing

12V

FET Switched

79 OF 81

3.3V

POWERPOWER 3.3V

VR_CTLVR_CTL_PHY

0VGNDGND

12VPOWERPOWER

12VPOWER POWER

12VPOWERPOWER

5VPOWERPOWER

1.5VPOWERPOWER

12V TRUEPOWERPOWER

TRUE12VPOWERPOWER

3.425VPOWERPOWER

VR_CTLVR_CTL_PHY

3.3VPOWERPOWER

12VPOWERPOWER

5VPOWERPOWER

TRUE12VVR_SWITCHVR_DIDT_PHY

12V TRUEVR_SWITCHVR_DIDT_PHY

TRUE12VVR_SWITCHVR_DIDT_PHY

12V TRUEVR_SWITCHVR_DIDT_PHY

VR_CTL_PHY VR_CTL

POWER POWER 3.3V

3.3VPOWER POWER

5VPOWERPOWER

VR_CTLVR_CTL_PHY

12V TRUEVR_SWITCHVR_DIDT_PHY

SNS_CURRENT SENSESNS_DIFF_PHY

VR_CTLVR_CTL_PHY

TRUE12VVR_SWITCHVR_DIDT_PHY

VR_CTLVR_CTL_PHY

3.3VPOWERPOWER

12V TRUEVR_SWITCHVR_DIDT_PHY

12VVR_SWITCHVR_DIDT_PHY TRUE

12V TRUEVR_SWITCHVR_DIDT_PHY

VR_CTLVR_CTL_PHY

VR_CTL_PHY VR_CTL

GND GND

120 OF 123

3.0.0

051-00081

? ?

PP3V3_S4_SSD

??

PPSSD_S4

PP3V3_S0

P3V42G3H_SHDN_L

PGND_REG_P1V2_S3

PP12V_S5

PP12V_ACDC

PP12V_S0

PP12V_G3H

PP5V_S0_HDD

PP1V5_S0

P3V42G3H_BOOST

P3V42G3H_SW

PP3V42_G3H_REG_R

PP3V42_G3H

P3V42G3H_SHDN_R_L

P3V42G3H_FB

PP3V3_G3

REG_VIN_U7600

REG_VCC2_U7600

REG_VCC1_U7600

REG_PHASE_P3V3S5

REG_UGATE_P3V3S5

REG_BOOT_P3V3S5

REG_BOOT_P3V3S5_RC

REG_LGATE_P3V3S5

REG_SNUBBER_P3V3S5

REG_P3V3S5_ISEN

PP3V3_S4

PP3V3_S5

PP5V_S0

PP5V_S4

PP5V_S5

REG_P5VS4_FSET

REG_P5VS4_ISEN

REG_P5VS4_OCSET

REG_P5VS4_VOUT

REG_SNUBBER_P5VS4

REG_P3V3S5_PHASE_SNS_P

REG_P3V3S5_PHASE_SNS_M

REG_P5VS4_PHASE_SNS_P

REG_P5VS4_PHASE_SNS_M

REG_P5VS4_VOUT_R

REG_P3V3S5_FSET

REG_P3V3S5_OCSET

REG_P3V3S5_VOUT

REG_LGATE_P5VS4

REG_P5VS4_FB

PP3V3_ENET

PP3V3_TBTLC

REG_UGATE_P5VS4

REG_BOOT_P5VS4_RC

REG_BOOT_P5VS4

REG_PHASE_P5VS4

REG_P3V3S5_FB

REG_P3V3S5_VOUT_R

GND\G

SYNC_DATE=03/24/2014

Platform VReg Constraints

SYNC_MASTER=J117_ANDRES

I852

I851

I850

I849

I848

I847

I843

I1506

I1505

I1504

I1503

I1486

I1485

I1484

I1477

I1476

I1460

I1454

I1453

I1452

I1451

I1449

I1448

I1447

I1446

I1445

I1444

I1443

I1382

I1255

I1254

I1236

I1233

I1219

I1218

I1153

I1151

I1149

I1148

I1147

I1146

I1145

I1144

I1143

I1142

I1141

I1140

I1139

I1138

I1137

I1136

I1082

I1078

I1077

I1072

I1071

66

56

59

66

56

66

56

66

61

66

61

66

27 26 18

61

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

SOURCE: Bill Cornelius's T29 Routing Notes

Port B

DDC

Internal DP SPDIF

Spacing

Max length of DisplayPort traces: 12 inches

Physical

Thunderbolt-specific Physical Rules

Spacing

TBT/DP Net Properties

Port A

*

DisplayPort intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

DisplayPort

DP-specific Physical Rules

Thunderbolt-specific Spacing Definitions

Thunderbolt

Internal Panel

SpacingPhysical

DisplayPort AUX channel intra-pair matching should be 5 ps. No relationship to other signals.

Pairs should be within 100 mils of clock length.

DP-specific Spacing Definitions

Physical

DisplayPort

Electrical Contraint Set

Graphics Source

Electrical Contraint SetElectrical Contraint Set

TBT IC Net Properties

*: Only used on hosts supporting T29 video-in

80 OF 81

DISPLAYPORTDP_85D

HDA

DISPLAYPORTDP_85D

TBT_I2CTBT_I2C_55S

DISPLAYPORTDP_85D

TBT_I2CTBT_I2C_55S

DISPLAYPORTDP_85D

TBT_I2CTBT_I2C_55S

DISPLAYPORTDP_85D

DP_85D DISPLAYPORT

TBT_I2CTBT_I2C_55S

TBTDPTBTDP_90D

TBT_D2R1_RVSD TBTDPTBTDP_90D

TBTDPTBTDP_90DTBT_D2R0_RVSD

TBTDPTBTDP_90D

TBT_D2R1_RVSD TBTDPTBTDP_90D

TBT_D2R0_RVSD TBTDPTBTDP_90D

TBTDPTBTDP_90D

TBT_R2D TBTDPTBTDP_90D

DP_ML1 DISPLAYPORTDP_85D

DP_ML3 DISPLAYPORTDP_85D

DP_LSX DISPLAYPORTDP_85D

DP_INTPNL_AUX_CONN DISPLAYPORTDP_85D

DP_INTPNL_IG_AUX_MUX DISPLAYPORTDP_85D

TBT_AUXCH DISPLAYPORTDP_85D

DP_ML3 DISPLAYPORTDP_85D

DP_ML1 DISPLAYPORTDP_85D

TBT_AUXCH DISPLAYPORTDP_85D

DP_ML1 DISPLAYPORTDP_85D

DP_ML3_RVSD DISPLAYPORTDP_85D

DP_ML1 DISPLAYPORTDP_85D

DP_ML3_RVSD DISPLAYPORTDP_85D

DP_TBTSNK0_AUX DISPLAYPORTDP_85D

DP_TBTSNK1_AUX DP_85D DISPLAYPORT

DP_INTPNL_TBT_AUX_MUX DISPLAYPORTDP_85D

DP_85D DISPLAYPORTDP_INTPNL_TBT_AUX_MUX

TBT_AUXDDC TBTDPTBTDP_90D

TBT_D2R1_RVSD TBTDPTBTDP_90D

TBT_D2R0_RVSD TBTDPTBTDP_90D

TBT_R2D_RVSD TBTDPTBTDP_90D

TBT_R2D TBTDPTBTDP_90D

TBT_R2D_RVSD TBTDPTBTDP_90D

TBT_AUXDDC TBTDPTBTDP_90D

TBT_D2R1_RVSD TBTDPTBTDP_90D

TBT_D2R0_RVSD TBTDPTBTDP_90D

TBT_R2D_RVSD TBTDPTBTDP_90D

TBT_R2D TBTDPTBTDP_90D

TBT_R2D_RVSD TBTDPTBTDP_90D

TBT_R2D TBTDPTBTDP_90D

TBT_SPITBT_SPI_55STBT_SPI_CLK

TBT_SPI_CS_L TBT_SPI_55S TBT_SPI

TBT_SPI_MISO TBT_SPI_55S TBT_SPI

TBT_SPI_MOSI TBT_SPITBT_SPI_55S

DP_TBTSNK1_AUX DP_85D DISPLAYPORT

121 OF 123

3.0.0

051-00081

? ? ?

DP_TBTSNK0_ML_N<3..0>

DP_TBTSNK0_ML_C_P<3..0>

? ?

DP_TBTSNK0_ML_C_N<3..0>

? ? ?

DP_INT_ML_N<1..0>

?

DP_TBTSNK1_ML_N<3..0>

? ?

DP_TBTSNK1_ML_P<3..0>

? ? ?

? ?

DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSRC_ML_C_N<1..0>

? ? ?

DP_TBTSNK0_ML_P<3..0>

? ?

DP_TBTSNK1_ML_C_P<3..0>

DP_TBTSRC_ML_P<1..0>

?? ?

DP_TBTSRC_ML_N<1..0>

? ? ?

DP_INTPNL_ML_N<1..0>

? ? ?

DP_INTPNL_ML_P<1..0>

? ? ?

DP_INTPNL_ML_C_N<1..0>

? ?

DP_INTPNL_ML_C_P<1..0>

? ?

? ? ?

DP_INT_ML_P<1..0>

DP_TBTSRC_ML_C_P<1..0>

? ? ?

DP_INT_AUX_C_N

? ?

DP_INT_AUX_C_P

? ?

DP_TBTSRC_AUX_C_N

? ?

DP_TBTSRC_AUX_C_P

? ?

DP_TBTPA_ML_P<1>

DP_INT_SPDIF_AUDIO

DP_TBTPA_AUXCH_N

DP_TBTPA_AUXCH_P

DP_TBTPA_DDC_CLK

DP_TBTPA_DDC_DATA

DP_TBTPA_ML_N<3>

DP_TBTPA_ML_N<1>

DP_TBTPA_ML_P<3>

DP_TBTPB_AUXCH_N

DP_TBTPB_AUXCH_P

DP_TBTPB_DDC_CLK

DP_TBTPB_DDC_DATA

DP_TBTPB_ML_N<1>

DP_TBTPB_ML_N<3>

DP_TBTPB_ML_P<1>

DP_TBTPB_ML_P<3>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_DDC_CLK

DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_DDC_CLK

DP_TBTSNK1_DDC_DATA

TBT_A_D2R_C_N<1>

TBT_A_D2R_C_N<0>

TBT_A_D2R_C_P<1>

TBT_A_D2R_C_P<0>

TBT_A_D2R_P<1>

TBT_A_D2R_P<0>

TBT_A_R2D_N<0>

TBT_A_R2D_N<1>

TBT_A_R2D_P<0>

TBT_A_R2D_P<1>

TBT_B_D2R_C_N<1>

TBT_B_D2R_C_N<0>

TBT_B_D2R_C_P<1>

TBT_B_D2R_C_P<0>

TBT_B_D2R_P<1>

TBT_B_D2R_P<0>

TBT_B_R2D_N<1>

TBT_B_R2D_N<0>

TBT_B_R2D_P<1>

TBT_B_R2D_P<0>

TBT_A_R2D_C_N<0>

DP_TBTPA_ML_C_N<1>

DP_TBTPA_ML_C_N<3>

DP_A_LSX_ML_P<1>

DP_A_LSX_ML_N<1>

DP_B_LSX_ML_N<1>

DP_B_LSX_ML_P<1>

DP_INTPNL_AUX_N

DP_INTPNL_AUX_P

DP_INT_AUX_N

DP_INT_AUX_P

DP_TBTPA_AUXCH_C_N

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_P<1>

DP_TBTPB_AUXCH_C_N

DP_TBTPB_AUXCH_C_P

DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

DP_TBTPB_ML_C_P<1>

DP_TBTPB_ML_C_P<3>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_AUXCH_P

DP_TBTSRC_AUX_N

DP_TBTSRC_AUX_P

TBT_A_D2R1_AUXDDC_N

TBT_A_D2R1_AUXDDC_P

TBT_A_D2R_N<1>

TBT_A_D2R_N<0>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<0>

TBT_A_R2D_C_P<1>

TBT_B_D2R1_AUXDDC_N

TBT_B_D2R1_AUXDDC_P

TBT_B_D2R_N<1>

TBT_B_D2R_N<0>

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_N<0>

TBT_B_R2D_C_P<1>

TBT_B_R2D_C_P<0>

TBT_SPI_CLK

TBT_SPI_CS_L

TBT_SPI_MISO

TBT_SPI_MOSI

DP_TBTSNK1_AUXCH_N

TBT_I2C_ISO

?

=2x_DIELECTRIC*

TBTDP_ISO =5x_DIELECTRIC

?

* TBT_I2C_ISOTBT_I2C * *

TBT_SPI_ISOTBT_SPI * *

TBTDP_ISOTBTDP * *

DP_ISODISPLAYPORT * *

=85_OHM_DIFFDP_85D * 0.08MM =85_OHM_DIFF

=85_OHM_DIFF =85_OHM_DIFF

=85_OHM_DIFF

TBTDP_ISO =7x_DIELECTRIC

?

TOP,BOTTOM

=90_OHM_DIFF

TBTDP_90D

=90_OHM_DIFF

=90_OHM_DIFF =90_OHM_DIFF* =90_OHM_DIFF

=55_OHM_SETBT_SPI_55S

=STANDARD

=55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE*

DP_ISO

?

=3:1_SPACING*

TBT_SPI_ISO * =2x_DIELECTRIC

?

=55_OHM_SETBT_I2C_55S

=STANDARD

* =55_OHM_SE=55_OHM_SE

=STANDARD

=55_OHM_SE

SYNC_MASTER=J70_NICK SYNC_DATE=10/22/2013

TBT/DP Constraints

I711

I710

I709

I708

I707

I706

I705

I704

I703

I702

I701

I700

I699

I698

I697

I696

I695

I694

I693

I692

I687

I686

I685

I684

I683

I682

I681

I680

I679

I678

I677

I676

I675

I674

I673

I671

I670

I669

I667

I666

I665

I664

I663

I662

I661

I660

I659

I658

I657

I656

I655

I654

I653

I652

I651

I650

I647

I646

I645

I644

I643

I642

I611

I610

I609

I608

I607

I606

I605

I604

I603

I602

I601

I600

I599

I596

I595

I566

I565

I564

I563

I550

I549

I548

I547

I546

I545

I544

I543

I542

I541

I538

I535

I534

I533

I530

I529

I526

I525

I524

I523

I522

I521

I520

I519

I518

I517

I516

I515

I514

I513

I512

I511

26

26 5

40 5

26

26 5

26

26 5

40 26

40 39

40

40 5

28

74 51 39

28

30 28

28

29

30 29

29

26 13

30 13

26 13

30 13

28

28 26

28

29

29 26

29

28 26

28

29

40 39

40 5

28 26

29 26

26

40 26

28

28 26

29

29 26

26

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

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PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

Spacing

BLC High Voltage Output

SPI

Electrical Contraint Set SpacingPhysical

Output Bus

Backlight

Constraints

BLC Control

BLC Baddies BLC Baddies

BLC Control

Backlight Controller

BLC-specific Physical Rules

Physical Net Type to Rule Map

BLC-specific Spacing Definitions

DIDTVoltage

Input Bus

Physical

BLC High Voltage Output

NO_TEST

Local Ground

Cello Miscellaneous

Is it chel'oh or sel'oh?

81 OF 81

BLC_HVPOWER_BLC 67V

SENSE

BLC_HV 67V

BLC_CTLBLC_CTL_PHY

BLC_PHASEBLC_CTL_PHY TRUE80V

BLC_CTLPOWER_BLC_RET

BLC_HVPOWER_BLC_RET

BLC_CTLPOWER_BLC_RET

BLC_HVPOWER_BLC_RET

BLC_CTLPOWER_BLC_RET

BLC_HVPOWER_BLC_RET

BLC_CTLPOWER_BLC_RET

BLC_HVPOWER_BLC_RET

BLC_CTLPOWER_BLC_RET

BLC_HVPOWER_BLC_RET

BLC_CTLPOWER_BLC_RET

BLC_HVPOWER_BLC_RET

BLC_CTLBLC_CTL_PHY

BLC_PHASEPOWER_BLC 80V TRUE

SMBSMB_PHY

BLC_PHASEBLC_CTL_PHY TRUE80V

SENSESNS_DIFF_PHY

BLC_PHASEBLC_CTL_PHY TRUE12V

BLC_PHASEBLC_CTL_PHY 0V

BLC_HVPOWER_BLC_RET

BLC_PHASEBLC_CTL_PHY 0V

POWERPOWER 12V

POWERPOWER 3.3V

POWERPOWER 5V

123 OF 123

3.0.0

051-00081

BKLT_BOOST

BKLT_BOOST_1

BKLT_BOOST_2

BKLT_FB

BKLT_FB_R

BKLT_FB_XW

BKLT_FLT

BKLT_FLT_RC

BKLT_GATE

BKLT_GATE_R

BKLT_ISEN1

BKLT_ISEN1_R

BKLT_ISEN2

BKLT_ISEN2_R

BKLT_ISEN3

BKLT_ISEN3_R

BKLT_ISEN4

BKLT_ISEN4_R

BKLT_ISEN5

BKLT_ISEN5_R

BKLT_ISEN6

BKLT_ISEN6_R

BKLT_ISET

BKLT_PHASE

BKLT_SCL

BKLT_SDA

BKLT_SNUBBER

BKLT_SW_M

BKLT_SW_P

BKLT_SW_R

DGND_BKLT

LED_RETURN_1

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

LGND_BKLT

PGND_BKLT

PP12V_BKLT_FUSED

PP12V_BKLT_SNS

PP12V_S0_BKLT_FILT

PP12V_S0_BKLT_PWR

PP12V_S0_BKLT_PWR_R

PP3V3_S0_BKLT_VDDIO_R

PP5V_S0_BKLT_R

BLC_PHASE GND * PHASE_SW2GND

* =3:1_SPACING

?

BLC_CTL_ISO

*BLC_HV_ISO 0.45mm

1000

PHASE_SW2GND =2:1_SPACING*

?

*BLC_HV BLC_CTL BLC_CTL_ISO

*BLC_HV BLC_CTL_ISOBLC_HV

*BLC_HV BLC_HV_ISO*

PHASE_SW2PWR =2:1_SPACING*

?

PHASE_SW2SW *

?

=1:1_SPACING

=8:1_SPACING*

2000

PHASE_ISO

** BLC_CTL_ISOBLC_CTL

PHASE_SW2SWBLC_PHASEBLC_PHASE *

PHASE_SW2PWRPOWERBLC_PHASE *

BLC_P6MMPOWER_BLC *

BLC_P3MMPOWER_BLC_RET *

BLC_P3MMBLC_CTL_PHY *

BLC_P6MM * 3.0 MMY

=STANDARD=STANDARD

0.100 MM0.600 MM

*

=STANDARD=STANDARD

BLC_P3MM 0.300 MM 3.0 MMY 0.100 MM

**BLC_PHASE PHASE_ISO

SYNC_MASTER=J117_ANDRES SYNC_DATE=03/24/2014

BLC Constraints

I802

I801

I800

I799

I798

I797

I796

I795

I794

I793

I792

I791

I790

I789

I788

I787

I786

I785

I784

I783

I782

I780

I779

I778

I777

I776

I775

I774

I773

I772

I770

I765

I764

I763

I762

I759

I757

I755

I754

I753

I752

I751

I750

I749

I564

I563

62

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

PHYSICAL_RULE_SET DIFFPAIR NECK GAPDIFFPAIR PRIMARY GAPMAXIMUM NECK LENGTHMINIMUM NECK WIDTHLAYER

ON LAYER?

ALLOW ROUTE

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

NET_PHYSICAL_TYPE AREA_TYPE PHYSICAL_RULE_SET

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

WEIGHTSPACING_RULE_SET LAYER LINE-TO-LINE SPACING

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE2NET_SPACING_TYPE1 SPACING_RULE_SETAREA_TYPE

TABLE_SPACING_ASSIGNMENT_ITEM

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

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NOTICE OF PROPRIETARY PROPERTY:

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PROPRIETARY PROPERTY OF APPLE INC.

THE INFORMATION CONTAINED HEREIN IS THE

Apple Inc.

Apple IMAC A1418 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual