Apple iMAC A1195-M50-DVT-VALLCO-051-7032 Schematic

Page 1
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
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TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD
TABLE_TABLEOFCONTENTS_ITEM
ANGLES
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.
DATE
APPD
DATE
APPD
CK
ZONE
DO NOT SCALE DRAWING
X.XXX
X.XX
XX
DIMENSIONS ARE IN MILLIMETERS
THIRD ANGLE PROJECTION
D
SIZE
APPLICABLE
NOTED AS
MATERIAL/FINISH
NONE
SCALE
DESIGNER
MFG APPD
DESIGN CK
RELEASE
QA APPD
ENG APPD
DRAFTER
METRIC
OF
SHT
DRAWING NUMBER
TITLE
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
Apple Computer Inc.
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
DESCRIPTION OF CHANGE
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
TABLE_TABLEOFCONTENTS_ITEM
04/05/06
M50 - DVT
FW: FW323-06
MASTER MASTER
4438
SYNC MASTER
DATE
CONTENTS
CSAPDF
SYNC MASTER
CONTENTS
CSA DATEPDF
System Block Diagram
MASTER
22
MASTER
FW: DECAPS
MASTER MASTER
4539
FIREWIRE CONNECTORS
MASTER MASTER
4640
USB Device Interfaces
MASTER MASTER
4741
AIRPORT CONN
MASTER MASTER
5342
SMC
M1
01/05/2006
5844
SMC & TPM SUPPORT
(MASTER) (MASTER)
5945
LPC+ CONN
M38
12/09/2005
6046
NB THERMAL
MASTER MASTER
6147
SPI BOOTROM
M38
01/05/2006
6348
Fan 0, 1 & System Temp
MASTER MASTER
6549
Fan 2 & HD Temp
MASTER MASTER
6650
TPM
M38
01/05/2006
6751
AUDIO: CODEC
AUDIO
03/30/2006
6852
AUDIO: SPEAKER AMP
AUDIO
03/30/2006
7253
AUDIO: CONNECTORS
AUDIO
03/30/2006
7354
AUDIO: POWER SUPPLIES
AUDIO
03/30/2006
7455
IMVP6 CPU VCore Regulator
MASTER MASTER
7556
CPU & SYSTEM SENSE CIRCUITRIES
(MASTER) (MASTER)
7657
PWR GOOD
(MASTER) (MASTER)
7758
3V DC/DC 2.5V
(MASTER) (MASTER)
7859
1.8V & 1.2V VREG
MASTER MASTER
7960
1.5V_S0 & 1.05V_S0 VREG
MASTER MASTER
8061
5V DC/DC
MASTER MASTER
8262
S0 AND S3 FETS
MASTER MASTER
8363
Internal Display Conns
MASTER MASTER
9464
EXTERNAL TMDS
MASTER MASTER
9565
TMDS/Inverter/ExtVGA
MASTER MASTER
9666
External Display Conns
MASTER MASTER
9767
Power Block Diagram
MASTER
33
MASTER
FUNC TEST 1 OF 2
MASTER
55
MASTER
Power Conn / Alias
MASTER
66
MASTER
CPU 1 OF 2-FSB
MASTER
77
MASTER
CPU 2 OF 2-PWR/GND
MASTER
88
MASTER
CPU DECAPS & VID<>
MASTER
99
MASTER
CPU TEMP SENSOR
MASTER
1010
MASTER
CPU ITP700FLEX DEBUG
01/05/2006
1111
M38
NB CPU Interface
01/05/2006
1212
M1
NB PEG / Video Interfaces
01/05/2006
1313
M1
NB Misc Interfaces
MASTER
1414
MASTER
NB DDR2 Interfaces
01/05/2006
1515
M1
NB Power 1
MASTER
1616
MASTER
NB Power 2
01/05/2006
1717
M40
NB Grounds
01/05/2006
1818
M1
NB (GM) Decoupling
(MASTER)
1919
(MASTER)
NB Config Straps
01/05/2006
2020
M1
SB: 1 OF 4
01/05/2006
2121
M38
SB: 2 OF 4
MASTER
2222
MASTER
SB: 3 OF 4
MASTER
2323
MASTER
SB: 4 OF 4
01/05/2006
2424
M38
SB:DECOUPLING
MASTER
2525
MASTER
SB: MISC
MASTER
2626
MASTER
SB: SMB HUB AND ALIAS
MASTER
2727
MASTER
DDR2 SO-DIMM Connector A
MASTER
2828
MASTER
DDR2 SO-DIMM Connector B
MASTER
2929
MASTER
Memory Active Termination
MASTER
3030
MASTER
Memory Vtt Supply
MASTER
3131
MASTER
CLOCKS
MASTER
3332
MASTER
CLOCKS: TERMINATIONS
MASTER
3433
MASTER
Disk Connectors
MASTER
3834
MASTER
ETHERNET CONTROLLER
MASTER
4135
MASTER
ETHERNET MISC
MASTER
4236
MASTER
ETHERNET CONNECTOR
MASTER
4337
MASTER
??
051-7032
SCHEM VALLCO
97
1
10/18/05 06/22/04
13
405954 ENGINEERING RELEASED
Table Items
MASTER
44
MASTER
PCIE PORT ALIASES
MASTER MASTER
5443
Page 2
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
3.3V/66MHZ/133MHZ
UATA/66/100
CONNECTOR
PAGE 14
J9700
MINI-DVI
SPI
U2100
DMI
PAGE 14
4-BIT
PAGE 15
U1200
PAGE 12
667MHZ
FSB
J0700
1.2V/800MHZ
CORE
MISC
CONTROL = 2.5V
SATA
MAIN MEMORY
JC900
PAGE 16-17
64-BIT
1.8V/667MHZ
DDR2 - DUAL CHAN
(1.83/2.17GHZ)
PAGE 7
PAGE 8
CORE (~1.2V)
CPU
(TMDS - VGA)
(INTERNAL)
LVDS
PAGE 94
J9402
PAGE
13
CORE (1.05V)
SB
SATA2
PAGE 38
HARD DRIVE
SATA0
PAGE 21
SATA
UATA
JC901
OPTICAL PAGE 38
CONNECTOR
UATA
PORT
#0
#2-5
PCI-E
PAGE 22
#1
MINI-PCIE
PAGE 53
AIRPORT
1.2V/1.5GHZ
X1 - 1.5GHZ
X1 - 1.5GHZ
YUKON
GIG ETHERNET
ETHERNET CONNECTOR
4 Diff pairs
JD600
PAGE 43
U4101
PAGE 41
PAGES 30
PARALLEL
TERM
J2900
J2800
DIMM
PAGE 28-29
PAGE 21
PORT PORT
2 Diff pairs
32-BIT
33MHZ
FIREWIRE A
0
FIREWIRE A CONNECTORS
PAGE 46
PAGE 22
PCI
1 2
AZALIA
CONNECTOR
SPEAKER
LINE OUT
OPTICAL OUT
COMBO OUT CONNECTOR
PAGE 153
SPEAKER
U6800
J7303
PAGE 72
J7301
PAGE 73
PORT F
AUDIO CODEC
STA9221
PAGE 68
PORT C
PORT A
PORT B
LINE IN
CONNECTOR
J7300
PAGE 73
JE350
MIC IN
BNDI
INTERFACE
S/PDIF
PAGE 22 PAGE 22
PAGE 21
FW323-06
PAGE 44
PAGE 21
LPC
4-BIT (3.3V/33MHZ)
JE000, JE001
PAGE 58
SMC
PAGE 67
JE310/JE320/JE330
CONNECTORS
USB
PAGE 47
0 4
J5300
JE350
0,2,4
3,7
BNDI
INTERFACE
PAGE 47
2 3 7
CAMERA
IR
156
PAGE 48
J4700
CONN
BT
USB
PAGE 22
SMB
PAGE 23
J5300 (AIRPORT CONN)
J5300
AIRPORT
U3301
CK410MDIMM’S
J2900
J2800
U5800
RMT
BOOTROM
PAGE 63
U6300/01
PAGE 24
GPIOS
PAGE 23
ITP CONN
J1101
PAGE 11
U6100 GPU+NB TSENS
U1000 CPU TSENS
MLB FAN
J6602 ODD TSENS
J6500,J6501,J6600 FAN CONNS
J2901 ALS+ATS TSENS
U6700
TPM
PAGE 60
CONNLPC+
J6000
PAGE 34
TERMS
CLOCKS
PAGE 33
CK410
U3301
VIDEO
64-BIT
VGA FOR DEBUG
6DUAL CHANNEL LVDS - 6BIT
PAGE 94
CORE (1.50V)
NB- GT
J6601 HD TSENS
System Block Diagram
97
051-7032
??
2
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
Page 3
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PANEL INVERTER FAN
PAGE 83
FET
PP5V_S0
PP5V_S3 FET
PAGE 83
SB ODD HDD
FHB IR
USB
PAGE 82
PP5V_S5
2.5V @ 0.9A
SB
NB_GRAPHICS
TMDS
AUDIO(+VREG)
FW
HDD
PAGE 83
FET
SPK_AMP
PP12V_S0
AUDIO(ALTERNATE)
1.3V @ 36A PAGE 75
PPVCORE_CPU_S0
CPU_CORE
1.05V @ 5.4A PAGE 80
PP1V05_S0
SB_CPU_IO
NB_VTT
CPU_FSB SB_CORE
NB_FSB
1.50V @ 10.12A PAGE 80
PP1V5_S0
SB_IO NB_GRAPHICS
NB_CORE
CPU_AVDD NB_PCIE
PAGE 79
PP1V2_S3
AC/DC POWER SUPPLY
1.21V @ 0.426A
PAGE 83
ODD
AIRPORT TMDS CK410
ENET_CORE
PAGE 83
FET
PP1V8_S0
PAGE 79
PP1V8_S3
1.81V @ 10A
TMDS
S5
12V, 180W, 15A
DRAM_CORE DRAM_IO
NB_DRAM
PAGE 83
FET
PP2V5_S0
PAGE 78
PP2V5_S5
2.5V @ 0.426A ???
NB_GRAPHICS TMDS
FET
PP3V3_S0
PAGE 83
PP2V5_S3
2.5V @ ?A PAGE 42
FET
3.35V @ 4.0A
PP3V3_S5
PAGE 78
PP3V3_S3
BT
TPM
ENET
SB_GPIO HARD DRIVE
AUDIO CODEC
FANS
FW SPI_BOOTROM
SB LCD
SMC
ENET
2.5V @ 0.9A PAGE 82
PP5V_S5_AUDIO
Power Block Diagram
051-7032
??
973
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
Page 4
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_ALT_ITEM
TABLE_ALT_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
TABLE_5_ITEM
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
TABLE_5_ITEM
M50 1.83G LOW SPEED CPU (D0)
(335S0384)
337S3280
OPS REQUESTED QUAL PARTS
COMMON
337S3242 M38 CPU(C0)
ALTERNATE PARTS
(335S0382)
338S0274
341S1859 IC EFI BOOTROM DEV M50
MECHANICAL PARTS
155S0295
L9703
CRITICAL
1
CHOKE,COMMON_MODE,165OHM,4PIN
CRITICAL124-0359
PCAP,120UF,16V,20%,ELEC
C6505,C6504,C6602
3
PCB,SCHEM,MLB,M50
1
051-7032
IC,FW32306,1394A LINK,TQFP
U4400
1
CRITICAL338S0279
U5800
CRITICALIC,SMC,M50
1
341T0022
IC,TPM,TSSOP,28P
U6700
1
341S1789 CRITICAL LEMENU
CRITICAL
1
IC,CPU VREG,IMVP,TWO PHASE
U7500
353S1235
U2100
IC,SB,652BGA
1
CRITICAL343S0385
1
CRITICALBT2600
BAT,COIN,3V,220MAH,CR2032
742-0048
C625
126S0092
FACTORY SHORTAGE
126S0091
IC,945GT,NORTHBRIDGE
338S0298
U1200
CRITICAL
1
353S1278353S1381
U5940
SMC VREF
378S0140 378S0141
LED601,LED602,LED603
IC,CPU-SKT,479BGA
511S0025
J0700
CRITICAL
1
IC,ENET LAN ROM
CRITICAL
U4102
1
341S1797
1
IC,CY28445-5,CLK GEN,68PIN QFN
U3301
CRITICAL359S0101
IC,88E8053,GIGABIT ENET XCVR,64P QFN,NO
U4101
CRITICAL
1
338S0270
603-9187
1
CRITICAL
HS2
SUBASSY, M50 NB HEATSINK
SUBASSY, M50 CPU HEATSINK
CRITICAL
1
603-9186
HS1
WASH1
MYLAR WASHER
1
CRITICAL725-0668
[EEE:V3M]
BARCODE LABEL, M50
825-6447 CRITICAL
1
CRITICAL
1
725-0720
MYLAR BLACK LED CVR, M50
CVR1
MLB1
PCB,FAB,MLB,M50
1
820-1960
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
??
4 97
051-7032
Table Items
YONAH
1
CRITICAL
CPU
1
341T0021
EFI ROM,M50
CRITICAL
MEROM
CPU
1
CRITICAL
M38 CPU (C0)
SCH1
337S3242
337S3244
U6301
M50 1.66G CPU (C0)
Page 5
PP
PP
PP PP PP
PP PP
PP
PP
PP PP PP
PP
PP PP
PP
PP PP
PP PP PP
PP
PP
PP
PP PP
PP
PP PP
PP PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP PP
PP
PP
PP
PP PP
PP PP PP PP PP
PP
PP PP PP
PP
PP
PP
PP
A
A
A
A
A
A
PP
A
A
IN IN IN IN IN
IN IN
IN
IN
IN
IN IN
IN IN IN IN IN
PP
IN
IN
IN IN
IN
PP
PP PP PP
PP
PP
PP PP
PP
PP PP
IN IN IN IN
PP PP
PP
PP
PP
PP
PP
PP
PP
PP
PP PP
PP
PP
PP
PP
PP PP PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP
PP PP PP
PP PP
PP
PP
PP
PP
PP PP
PP PP
PP
PP
PP
PP
PP PP PP
PP
PP
PP PP PP PP
PP
PP
PP
PP PP PP
PP
PP
PP PP PP
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SPARE USB PORT
INVERTER DOES NOT USE THIS SIGNAL
LAYOUT NOTE: PLACE NEAR U2100
MISC GROUND VIAS
PLACE NEAR R2800 AND R2801
PLACE NEAR R1210 AND R1211
8 TESTPOINTS
LAYOUT NOTE: PLACE NEAR J0700
PLACE NEAR R0705 AND R0706
LAYOUT NOTE: PLACE NEAR U4101LAYOUT NOTE: PLACE NEAR U1200
FSB_DSTBP_L<0>
FSB_D_L<41>
FSB_DBSY_L
VR_PWRGOOD_DELAY
NO_TEST=TRUE
NC_PEG_R2D_C_N<4>
MAKE_BASE=TRUE
PEG_R2D_C_N<5>
PEG_R2D_C_N<4>
PEG_R2D_C_N<10>
PEG_D2R_N<4>
PEG_D2R_N<7>
PEG_D2R_N<14>
TP_USB_F_N MAKE_BASE=TRUE
TP_USB_F_P MAKE_BASE=TRUE
=PP1V05_S0_FSB_NB
FSB_D_L<59>
FSB_DSTBP_L<2>
NB_RST_IN_L_R
FSB_ADSTB_L<0>
SW_RST_BTN_L
FUNC_TEST=TRUE
XDP_TDO
FUNC_TEST=TRUE
DMI_N2S_N<0>
PM_CLKRUN_L
PP3V3_S5_SB_RTC
FUNC_TEST=TRUE
POWER_BUTTON_L
FUNC_TEST=TRUE
SMC_MANUAL_RST_L
FUNC_TEST=TRUE
SMC_RX_L
FUNC_TEST=TRUE
XDP_TRST_L
FUNC_TEST=TRUE
XDP_TMS
FUNC_TEST=TRUE
XDP_TDI
FUNC_TEST=TRUE
XDP_TCK
FUNC_TEST=TRUE
PPVCORE_CPU
FUNC_TEST=TRUE
PP3V3_S5
FUNC_TEST=TRUE
PP5V_S5
FUNC_TEST=TRUE
PP1V8_S3
FUNC_TEST=TRUE
SMC_TX_L
FUNC_TEST=TRUE
SMC_TDO
FUNC_TEST=TRUE
SMC_TDI
FUNC_TEST=TRUE
SMC_TCK
FUNC_TEST=TRUE
=PP1V8_S3_MEM
FSB_DSTBN_L<3>
FSB_DINV_L<2> FSB_D_L<59>
FSB_DINV_L<3>
FSB_DSTBP_L<3>
FSB_LOCK_L FSB_CPURST_L
FSB_HITM_L
FSB_HIT_L
FSB_BNR_L
CPU_IGNNE_L
FSB_DINV_L<3>
FSB_DSTBP_L<3>
FSB_D_L<41> FSB_DSTBN_L<2>
FSB_DSTBN_L<1>
FSB_REQ_L<2>
FSB_DPWR_L FSB_REQ_L<0>
SB_CLK100M_SATA_P
FSB_LOCK_L
FSB_A_L<6>
FSB_ADSTB_L<1>
FSB_A_L<27>
FSB_ADSTB_L<0>
FSB_CLK_CPU_N
CPU_SMI_L
FSB_DINV_L<1>
FSB_CLK_NB_N
FSB_DINV_L<2>
FSB_DSTBN_L<0>
FSB_A_L<27>
FSB_DSTBP_L<1>
NB_FSB_VREF
MEM_VREF
IDE_PDIORDY
PCI_CLK_SB
IDE_PDD<9>
SB_CLK100M_SATA_N
IDE_PDIOR_L
FSB_BREQ0_L
ENET_CLK100M_PCIE_N
ENET_CLK100M_PCIE_P
PCIE_A_D2R_N
PCIE_A_D2R_P
PCIE_B_D2R_P PCIE_B_D2R_N
DMI_N2S_P<0>
SB_CLK100M_DMI_P SB_CLK100M_DMI_N
PM_SYSRST_L
SB_CLK14P3M_TIMER SB_CLK48M_USBCTLR
FSB_ADSTB_L<1>
FSB_A_L<6>
FSB_CLK_NB_P
FSB_REQ_L<4>
FSB_DSTBN_L<3>
FSB_D_L<0> FSB_DSTBN_L<0>
FSB_DSTBP_L<0> FSB_DINV_L<0>
SPI_ARB
NO_TEST=TRUE
TP_PCI_CLK_SPARE
NO_TEST=TRUE
TP_MEM_B_A<14>
NO_TEST=TRUE
PP12V_S5
FUNC_TEST=TRUE
FSB_D_L<16>
FSB_DINV_L<0> FSB_D_L<16> FSB_DSTBN_L<1> FSB_DSTBP_L<1> FSB_DINV_L<1>
FSB_DSTBN_L<2> FSB_DSTBP_L<2>
CPU_INIT_L CPU_A20M_L
CPU_STPCLK_L CPU_INTR
FSB_CLK_CPU_P
CPU_NMI
NB_CLK_DREFSSCLKIN_N
DMI_S2N_N<0> DMI_S2N_P<0>
MEM_VREF_NB_0 MEM_VREF_NB_1
MEM_A_DQ<14>
MEM_A_DQ<7>
MEM_A_DQ<54>
MEM_A_DQ<47>
MEM_A_DQ<59> MEM_A_DQS_P<0> MEM_A_DQS_N<0>
MEM_A_DQS_N<1>
MEM_A_DQS_P<1>
MEM_A_DQS_P<2> MEM_A_DQS_N<2> MEM_A_DQS_P<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4> MEM_A_DQS_P<5> MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_P<6>
MEM_A_DQS_P<7> MEM_A_DQS_N<7>
MEM_B_DQ<6>
MEM_B_DQ<23>
MEM_B_DQ<8>
MEM_B_DQ<25> MEM_B_DQ<38> MEM_B_DQ<44>
MEM_B_DQ<62>
MEM_B_DQ<48>
MEM_B_DQS_P<0> MEM_B_DQS_N<0> MEM_B_DQS_P<1> MEM_B_DQS_N<1> MEM_B_DQS_P<2> MEM_B_DQS_N<2> MEM_B_DQS_P<3> MEM_B_DQS_N<3> MEM_B_DQS_P<4> MEM_B_DQS_N<4> MEM_B_DQS_P<5> MEM_B_DQS_N<5> MEM_B_DQS_P<6> MEM_B_DQS_N<6> MEM_B_DQS_P<7> MEM_B_DQS_N<7>
NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N
NB_CLK_DREFCLKIN_N
NB_CLK_DREFCLKIN_P
FSB_REQ_L<3>
FSB_REQ_L<1>
NB_CLK_DREFSSCLKIN_P
SMC_TMS
FUNC_TEST=TRUE
SMC_TRST_L
FUNC_TEST=TRUE
=PP1V05_S0_CPU
USB_F_P
USB_F_N
LVDS_BKLTEN
TP_LVDS_BKLTEN
MAKE_BASE=TRUE
FSB_D_L<0>
MEM_A_DQ<16> MEM_A_DQ<25> MEM_A_DQ<39>
NO_TEST=TRUE
NC_PEG_D2R_N<10>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_D2R_N<5>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_D2R_N<4>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<14>
NO_TEST=TRUE
NC_PEG_D2R_N<7>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_D2R_N<6>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_D2R_N<3>
MAKE_BASE=TRUE
PEG_D2R_N<15>
PEG_D2R_N<13>
PEG_D2R_N<12>
PEG_D2R_N<11>
PEG_D2R_N<10>
PEG_D2R_N<9>
PEG_D2R_N<8>
PEG_D2R_N<6>
PEG_D2R_N<5>
PEG_D2R_N<3>
PEG_R2D_C_N<15>
PEG_R2D_C_N<13> PEG_R2D_C_N<14>
PEG_R2D_C_N<11> PEG_R2D_C_N<12>
PEG_R2D_C_N<8> PEG_R2D_C_N<9>
PEG_R2D_C_N<6> PEG_R2D_C_N<7>
NO_TEST=TRUE
NC_PEG_R2D_C_N<5>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_R2D_C_N<7>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_R2D_C_N<6>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_R2D_C_N<10>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_R2D_C_N<9>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<12>
NO_TEST=TRUE
NC_PEG_R2D_C_N<11>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_R2D_C_N<14>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_R2D_C_N<13>
MAKE_BASE=TRUE
NO_TEST=TRUE
NC_PEG_R2D_C_N<15>
MAKE_BASE=TRUE
TP_MEM_B_A<15>
NO_TEST=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<11>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<15>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<9>
NO_TEST=TRUE
NC_PEG_D2R_N<8>
MAKE_BASE=TRUE
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<12>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_D2R_N<13>
NO_TEST=TRUE
MAKE_BASE=TRUE
NC_PEG_R2D_C_N<8>
FUNC_TEST=TRUE
FUNC TEST 1 OF 2
051-7032
975
??
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
SM
P4MM
OMIT
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
OMIT
SM
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
SM
OMIT
P4MM
SM
OMIT
P4MM P4MM
OMIT
SM
SM
P4MM
OMIT
P4MM
OMIT
SM
P4MM
OMIT
SM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM SM
OMIT
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
SM
OMIT
SM
OMIT
P4MM
SM
P4MM
OMIT
OMIT
P4MM
SM
SM
OMIT
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
SM
OMIT
P4MM
SM
OMIT
P4MM
SM
OMIT
P4MM P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
SM
OMIT
P4MM
OMIT
P4MM
SM
OMIT
P4MM
SM
P4MM
OMIT
SM
OMIT
P4MM
SM
P4MM
SM
OMIT
P4MM
SM
OMIT
P4MM
OMIT
SM
P4MM
OMIT
SM
SM
OMIT
P4MM
OMIT
SM
P4MM P4MM
OMIT
SM
SM
OMIT
P4MM P4MM
OMIT
SM
P4MM
OMIT
SM
OMIT
SM
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
OMIT
P4MM
SM
P4MM
OMIT
SM SM
OMIT
P4MM
OMIT
P4MM
SM
SM
OMIT
P4MM
SM
OMIT
P4MM
OMIT
P4MM
SM
SM
OMIT
P4MM P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
SM
OMIT
SM
OMIT
P4MM
SM
P4MM
OMIT
OMIT
SM
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
SM
OMIT
P4MM
P4MM
OMIT
SM
SM
OMIT
P4MM
OMIT
P4MM
SM
HOLE-VIA
HOLE-VIA
HOLE-VIA
P4MM
OMIT
SM
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
OMIT
SM
P4MM
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
SM
OMIT
P4MM
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
OMIT
P4MM
SM
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
SM
OMIT
P4MM
OMIT
SM
P4MM
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
HOLE-VIA
P4MM
OMIT
SM
SM-TP50-TOP
SM-TP50-TOP
P4MM
OMIT
SM
SM-TP50-TOP
SM-TP50-TOP
SM-TP50-TOP
SM-TP50-TOP
SM-TP50-TOP
SM-TP50-TOP
OMIT
SM
P4MM
SM
OMIT
P4MM
P4MM
SM
OMIT
P4MM
SM
OMIT
P4MM
OMIT
SM
P4MM
SM
OMIT
P4MM
OMIT
SM
SM
OMIT
P4MM
SM
OMIT
P4MM
SM
P4MM
OMIT
SM
OMIT
P4MM
OMIT
P4MM
SM
SM
OMIT
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
SM
OMIT
P4MM
SM
OMIT
P4MM
SM
P4MM
OMIT
SM
P4MM
OMIT
P4MM
OMIT
SM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
SM
OMIT
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
SM
OMIT
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
OMIT
SM
P4MM
SM
P4MM
OMIT
P4MM
OMIT
SM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
SM
OMIT
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
SM
OMIT
P4MM
OMIT
P4MM
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
SM
P4MM
OMIT
P4MM
OMIT
SM SM
OMIT
P4MM
SM
OMIT
P4MM
P4MM
OMIT
SM
SM
OMIT
P4MM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
OMIT
SM
P4MM
SM
OMIT
PP600
1
PP601
1
PP602
1
PP603
1
PP620
1
PP621
1
PP604
1
PP605
1
PP606
1
PP607
1
PP608
1
PP609
1
PP610
1
PP611
1
PP612
1
PP613
1
PP614
1
PP615
1
PP616
1
PP617
1
PP618
1
PP619
1
PP632
1
PP631
1
PP634
1
PP633
1
PP635
1
PP636
1
PP637
1
PP638
1
PP640
1
PP639
1
PP641
1
PP642
1
PP643
1
PP645
1
PP644
1
PP648
1
PP646
1
PP647
1
PP650
1
PP649
1
PP652
1
PP651
1
PP653
1
PP654
1
PP655
1
PP657
1
PP656
1
PP658
1
PP660
1
PP659
1
PP662
1
PP661
1
PP663
1
PP623
1
PP622
1
PP625
1
PP624
1
PP626
1
PP627
1
PP628
1
PP629
1
PP630
1
PP664
1
PP666
1
PP665
1
PP667
1
PP668
1
PP673
1
PP674
1
PP675
1
PP677
1
PP676
1
PP678
1
PP679
1
PP680
1
PP682
1
PP681
1
PP683
1
PP684
1
PP685
1
PP686
1
PP688
1
PP687
1
PP689
1
PP690
1
PP691
1
PP693
1
PP692
1
PP694
1
PP695
1
PP696
1
PP697
1
PP698
1
PP699
1
PP6A0
1
PP6A1
1
PP6A3
1
PP6A2
1
PP6A4
1
PP6A5
1
PP6A6
1
PP6A7
1
PP6A8
1
PP6B1
1
PP6A9
1
PP6B0
1
PP6B2
1
PP6B3
1
PP6B4
1
PP6B6
1
PP6B5
1
PP6B7
1
PP6B8
1
PP6C1
1
PP6B9
1
PP6C0
1
PP6C2
1
PP6C3
1
PP6C5
1
PP6C4
1
PP6C6
1
PP6C8
1
PP6C7
1
PP6D0
1
PP6D1
1
PP6D3
1
PP6D2
1
PP6D4
1
PP6D5
1
PP6D6
1
PP6D8
1
PP6D7
1
PP6D9
1
PP6E0
1
PP6E1
1
PP1200
1
PP1201
1
PP1202
1
PP700
1
PP702
1
PP2800
1
PP2801
1
PP2802
1
ZH500
1
ZH501
1
ZH502
1
ZH503
1
ZH504
1
ZH505
1
ZH506
1
ZH507
1
ZH508
1
ZH509
1
ZH510
1
ZH511
1
ZH512
1
ZH513
1
ZH514
1
ZH515
1
ZH516
1
ZH517
1
ZH518
1
ZH519
1
ZH520
1
ZH521
1
ZH522
1
ZH523
1
ZH524
1
ZH525
1
ZH526
1
ZH527
1
ZH528
1
ZH529
1
PP4100
1
PP4101
1
PP5E1
1
PP5E2
1
PP669
1
PP670
1
PP671
1
PP672
1
12
7 5
12
7 5
12
7
75 26 14
13
13
13
13
13
13
19 12
6
12
7 5
12
7 5
14
12
7 5
26
11
7
22 14
67 60
58 44 23
26 25 24 21
59
59
60 59 58
11
7
11
7
11
7
11
7
76 75
6
83 80 79
78 77 76 66 65 59 26
6
83 82 80 79 59
6
83 79
6
60 59 58
60 59 58
60 59 58
60 59 58
29 28
6
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
12 11
7
12
7
12
7
12
7
21
7
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
12
7
12
7
12
7
34 21
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
34
7
21
7
12
7 5
34 12
12
7 5
12
7 5
12
7 5
12
7 5
12
29 28
38 21
34 22
38 21
34 21
38 21
12
7
41 34
41 34
54 22
54 22
54 22
54 22
22 14
34 22
34 22
58 26 23
34 23
34 23
12
7 5
12
7 5
34 12
12
7
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
58 22
34
29
83 82 80 79 78 77 76
6
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
12
7 5
21
7
21
7
21
7
21
7
34
7
21
7
34 14
22 14
22 14
19 14
19 14
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
28 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
34 14
34 14
34 14
34 14
12
7
12
7
34 14
60 59 58
60 58
11
9 8 7 6
22
22
13
12
7 5
28 15
28 15
28 15
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
13
29
Page 6
125
125
125
125
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ALWAYS ON WHEN UNIT HAS AC POWER (TRICKLE)
SILKSCREEN:3
SILKSCREEN:RUN
SILKSCREEN:1
AC/DC CONN
"S5" RAILS
GND RAILS
SILKSCREEN:2
ONLY ON IN RUN
ON IN RUN AND SLEEP
"S0" RAILS
USING S3 TO DRIVE S0 OK IN THIS CASE
USING S3 TO DRIVE S0 OK IN THIS CASE
"S3" RAILS
CHASSIS GND
HDD POWER CONN
M-RT-TH2
CRITICAL
CRITICAL
POWER_GOOD
PP12V_S5_AC_DC
39-30-3058
NOSTUFF
=PP1V5_S0_SB_VCC1_5_A_ARX =PP1V5_S0_SB_VCCSATAPLL =PP1V5_S0_SB_VCC1_5_A_ATX
6.3X5.5-SM
MAKE_BASE=TRUE VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
PP4V5_S0_AUDIO_ANALOG
=PP4V5_S0_AUDIO_ANALOG
=PP3V3_S0_NB
=PP3V3_S0_TMDS
=PP3V3_S0_SB_VCCLAN3_3 =PP3V3_S0_AIRPORT
=PP3V3_S0_PCI
=PP3V3_S0_AUDIO
=PP3V3_S0_IMVP
=PP3V3_S0_CK410
=PPSPD_S0_MEM
=PP3V3_S0_TPM
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S0_HD_TSENS =PP3V3_S0_ODD_TSENS
=PP3V3_S0_FAN
=PP3V3_S0_PATA
=PP3V3_S0_SB_PM
=PP3V3_S0_SB_PCI
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_PCI
=PP3V3_S0_SB_VCC3_3
=PP3V3_S0_SB =PP3V3_S0_SB_GPIO
=PP3V3_S0_NB_VCC_HV
=PP3V3_S0_LCD
=PP3V3_S0_SATA
PP3V3_S0
MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM
=PP2V5_S0_NB_VCCA_LVDS
=PP1V8_S0_TMDS
VOLTAGE=5V
MAKE_BASE=TRUE
PP5V_S5
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
=PP2V5_S0_TMDS
=PP2V5_S0_NB_DISP_PLL
=PP2V5_S0_NB_VCCSYNC
=PP2V5_S0_NB_VCC_TXLVDS
=PP5V_S0_PATA
PP12V_S5
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=12V
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
GND_CHASSIS_BNDI
VOLTAGE=0
PP1V05_S0
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.3MM
VOLTAGE=1.05V
MAKE_BASE=TRUE
=PP12V_S5_CPU
=PP12V_S5_FW
=PP3V3_S5_SMC
=PP3V3_S5_DEBUG =PP3V3_S5_ROM =PP3V3_S5_LCD
=PP5V_S5_SB
=PP5V_S5_AUDIO_LDO
=PP5V_S3_BNDI
PP3V3_S5
MAKE_BASE=TRUE VOLTAGE=3.3V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
=PP3V3_S5_2V5_LDO
=PP3V3_S5_SB_IO
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_USB
=PP3V3_S5_SB
=PP5V_S0_MEMVTT
VOLTAGE=5V
PP5V_S3
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.25MM
=PP3V3_S3_BT
=PP1V8_S3_1V2_LDO
=PP1V8_S3_MEM
=PP3V3_S3_ENET
PLT_RST_L
POWER_GOOD
GND_CHASSIS_ODD_TEMP
GND_CHASSIS_AUDIO_INTERNAL
ZH704P1
=PP1V8_S3_MEM_NB
PP1V2_S3
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE VOLTAGE=1.8V
PP5V_S0
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUE VOLTAGE=5V
=PP5V_S0_NBISENSE
=PP1V5_S0_NB_VCCD_LVDS
=PP5V_S5_AUDIO
PP5V_S5_AUDIO
MAKE_BASE=TRUE
=PP3V3_S5_FW
=PP3V3_S5_SB_PM
=PP1V5_S0_NB_PLL
=PP1V5_S0_NB_3GPLL
=PP5V_S0_SB
=PP5V_S0_DEBUG =PP5V_S0_SATA
=PP1V5_S0_NB_VCCAUX
=PPVCORE_S0_SB
=PP3V3_S3_TPM
=PP1V05_S0_SB_CPU_IO
=PP1V05_S0_NB_VTT
=PP1V05_S0_FSB_NB
=PP5V_S0_NB_TVDAC
=PPVCORE_S0_CPU
PP3V3_LCD_CONN
LCD_SHOULD_ON
ITS_RUNNING
PP3V3_S0
=PP5V_S0_TMDS
=PP12V_S0_FAN
PP12V_S0_AUDIO_SPKRAMP
MAKE_BASE=TRUE
=PP12V_INVERTER
=PP12V_S0_SATA
=PP12V_S0_AUDIO_SPKRAMP
PP12V_S0
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM
VOLTAGE=12V
MAKE_BASE=TRUE
=PP1V2_S3_LAN
=PP5V_S3_USB
=PP1V5_S0_NB_TVDAC
SYS_POWERFAIL_L
GND_CHASSIS_AUDIO_EXTERNAL
PP3V3_S5
U600_6
PPVCORE_CPU
MIN_NECK_WIDTH=0.15MM
MAKE_BASE=TRUE VOLTAGE=1.25V MIN_LINE_WIDTH=0.6MM
PP0V9_S0
MIN_LINE_WIDTH=0.3MM
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.15MM
VOLTAGE=0.9V
U600_3
U600_8
U600_11
SMC_LRESET_L
NB_RST_IN_L
TMDS_RESET_L
ENET_RST_L
TPM_LRESET_L
AIRPORT_RST_L
DEBUG_RST_L
GND_AUDIO
GND_AUDIO_SPKRAMP
GND_CHASSIS_USB
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
MAKE_BASE=TRUE
GND_CHASSIS_IO_LEFT
GND_CHASSIS_FIREWIRE GND_CHASSIS_VGA GND_CHASSIS_RJ45
MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0
GND_CHASSIS_IO_RIGHT
ZH702P1
ZH703P1
PP3V3_S5
ITS_PLUGGED_IN
PP3V3_S3
ITS_ALIVE
=PP0V9_S0_MEM_TERM
=PP0V9_S0_MEMVTT_LDO
GPU_PWM_RST_L
=PP1V05_S0_CPU
=PP1V5_S0_SB
=PP1V8_S0_MEMVTT
PP1V8_S3
MAKE_BASE=TRUE VOLTAGE=1.8V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
PP3V3_S3
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE VOLTAGE=3.3V
ZH701P1
=PP1V5_S0_AIRPORT
=PP2V5_S0_NB_VCCA_3GBG
=PP1V5_S0_NB_VCCD_LVDS
=PP1V5_S0_NB_VCCD_HMPLL
=PP1V5_S0_CPU
=PPVCORE_S0_NB
=PP1V5_S0_NB_PCIE =PP1V5_S0_NB_TVDAC
=PP1V5_S0_NB
=PP1V5_S0_SB_VCC1_5_A
PP1V5_S0
MIN_LINE_WIDTH=0.6MM
MAKE_BASE=TRUE VOLTAGE=0
MIN_NECK_WIDTH=0.15MM
ZH702P1
PP1V8_S0
VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
=PP2V5_S0_NB_VCC_TXLVDS
PP2V5_S0
VOLTAGE=3.3V
MAKE_BASE=TRUE
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
=PP1V5_S0_SB_VCCUSBPLL
=PP2V5_S0_NB_CRTDAC
=PP5V_S0_SATA
=PP3V3_S0_SATA
=PP12V_S0_SATA
Power Conn / Alias
051-7032
6 97
??
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
ELEC
16V
20%
100UF
CRITICAL
88737-0553
M-ST-SM
MF-LF
1/16W 402
330
5%
GREEN-3.6MCD
2.0X1.25MM-SM
CERM
10V
10UF
20%
805-2
10UF
CERM
NOSTUFF
20%
805-2
10V
10UF
10%
1210
CERM
16V
603
20% 25V CERM
0.1UF
0.1UF
603
20% 25V CERM
I632
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
MF-LF
DEVELOPMENT
1/16W 402
5%
330
2.0X1.25MM-SM
GREEN-3.6MCD
MF-LF
5% 1/16W
402
330
402
5%
68
MF-LF
1/16W
MF-LF
402
68
1/16W
5%
1/16W MF-LF
68
5%
402
MF-LF
1/16W
68
402
5%
1/16W MF-LF
68
5%
402
68
MF-LF
1/16W
402
5%
1/16W MF-LF
68
5%
402
MF-LF
1/16W
68
5%
402
74LC125
CRITICAL
TSSOP
TSSOP
74LC125
CRITICAL
TSSOP
CRITICAL
74LC125
160R138
OMIT
0.01UF
NOSTUFF
402
20% CERM
16V
OMIT
4P25R3P5
5%
402
MF-LF
1/16W
0
NOSTUFF
MF-LF
5% 1/16W
402
330
NOSTUFF
0.01UF
CERM
16V
20%
402
NOSTUFF
0.01UF
CERM 402
16V
20%
NOSTUFF
20%
0.01UF
CERM
16V 402
OMIT
4P25R3P5
OMIT
4P25R3P5
4P25R3P5
OMIT
OMIT
SM
OMIT
SM
2.0X1.25MM-SM
GREEN-3.6MCD
0.1UF
CERM 402
20% 10V
CRITICAL
74LC125
TSSOP
SM
NOSTUFF
SM
NOSTUFF
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
R602
1
2
XW601
1 2
XW602
1 2
U600
2
7 1
14
3
C600
1
2
LED601
1
2
XW604
1 2
XW605
1 2
ZH601
1
ZH602
1
ZH603
1
C601
1
2
C602
1
2
C603
1
2
R603
1 2
ZH604
1
C604
1
2
ZH606
1
U600
5
7 4
14
6
U600
9
7
10
14
8
U600
12
7
13
14
11
R612
1 2
R611
1 2
R614
1 2
R615
1 2
R616
1 2
R617
1 2
R618
1 2
R619
1 2
R600
1
2
LED602
1
2
R605
1
2
LED600
1
2
C621
1
2
C620
1
2
C624
1
2
C622
1
2
C623
1
2
LED603
1
2
R601
1
2
J602
1 2 3 4 5
C625
1
2
J601
1 2 3 4 5
6
76
25 24
25 24
25 24
83
68
20 19 14
97 96 95
25 24
53
44
74 73 72 68
75
33
29 28
67
25 24
66
66
66 65 59
38
26
26
25 24
25 24
25 24
25 22
27 23 21
19 17
94
6
94 83 76 61 59 41 26 10
6
19 17
95
83 82 80 79 59
5
95
19
19
19 17
6
38
83 82 80 79 78 77 76
5
47
80 34
76
46
59 58
60
63
94
25
82
47
83 80
79 78 77 76 66 65 59 26
6 5
78
27 22
24
25 24
25 24
22
26 25 23
31
83 59
47
79
29 28
5
43 42 41
22
6
66
73
19 16 14
79
83 75
80
19 17
6
68
46 45 44
23 11
19
19
25
60
6
19
25 24
67
25 24 21
19 17
19 12
5
19
76
9 8
94 94 83 76 61 59 41 26 10
6
97 95
66 65
94
6
72
83 76
42
47
19
6
82 78 76
73
83 80
79 78 77 76 66 65 59 26
6 5
76 75
5
58
14
95
42
67
53
60
74
74 72
47
46
97
43
6
83 80
79 78 77 76 66 65 59 26
6 5
83 59 53
6
30
31
94
11
9 8 7 5
25
31
83 79
5
83 59 53
6
53
19 17
19 17
6
19 17
8
19 16
19 13
19
6
19
25 24
80
6
83
19 17
6
83
25 24
19
6
6
6
25 24
Page 7
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO IO
IO IO
IN
IN
IN
IN IN
IN
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO IO
IO IO
OUT
OUT
OUT
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO
IO IO
IO
IO IO
IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
OUT
OUT
OUT
OUT
IN
IN IN
IN
IN IN
IN IN
IN IN
OUT
IN IN
IN
IN
IN IN
IN
IN
OUT
IN
A3* A4* A5* A6*
A8*
A10* A11* A12* A13*
A16*
A15*
A14*
ADSTB0*
REQ2*
REQ0* REQ1*
REQ3* REQ4*
A17* A18* A19* A20* A21*
A23*
A22*
A24* A25* A26*
A29*
A28*
A27*
A31*
A30*
ADSTB1*
A20M* FERR* IGNNE*
STPCLK*
LINT1
LINT0
SMI*
RSVD10
RSVD9
RSVD5
RSVD4
RSVD3
RSVD2
RSVD1
RSVD8
RSVD7
RSVD6
RSVD11
ADS* BNR*
BPRI*
DEFER*
DRDY* DBSY*
BR0*
IERR* INIT*
LOCK*
RESET*
RS0* RS1* RS2*
TRDY*
HIT*
HITM*
BPM0*
BPM2*
BPM1*
BPM3* PRDY* PREQ*
TCK TDI TDO TMS
TRST*
DBR*
PROCHOT*
THERMDA THERMDC
THERMTRIP*
RSVD12
RSVD13
RSVD16
RSVD19
RSVD18
RSVD17
RSVD20
BCLK0 BCLK1
RSVD15
RSVD14
A7*
A9*
ADDR GROUP0
XDP/ITP SIGNALS
CONTROL
ADDR GROUP1
RESERVED
HCLK
THERM
(1 OF 4)
PSI*
SLP*
PWRGOOD
DPRSTP*
DPSLP*
DPWR*
COMP2 COMP3
COMP1
COMP0
DSTBP3*
DSTBN3*
DINV3*
D63*
D62*
D61*
D60*
D59*
D58*
D57*
D56*
D55*
D54*
D52* D53*
D51*
D50*
D49*
D48*
DINV2*
DSTBN2*
D47*
DSTBP2*
D45* D46*
D44*
D43*
D42*
D41*
D40*
D39*
D38*
D37*
D36*
D35*
D34*
D33*
D32*
BSEL2
DSTBN1*
BSEL0 BSEL1
TEST2
GTLREF
DINV1*
DSTBP1*
D31*
D30*
D29*
D26* D27* D28*
D24* D25*
D23*
D21* D22*
D20*
D19*
D18*
D16* D17*
DINV0*
DSTBP0*
DSTBN0*
D15*
D14*
D13*
D12*
D11*
D10*
D9*
D8*
D7*
D6*
D5*
D4*
D3*
D2*
D1*
D0*
TEST1
NC
(2 OF 4)
MISC
DATA GRP0
DATA GRP2
DATA GRP1
DATA GRP3
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NO STUFF R0701 IF USING ITP
TP_CPU_M_TEST3
SPARE[7-0],HFPLL:
ROUTE TO TP VIA AND PLACE GND VIA W/IN 1000 MILS
TP_CPU_M_TEST4
CPU SCH AND PCB
LAYOUT NOTE: 0.5" MAX LENGTH
PIN ACTUALLY DRIVEN BY ITP
DUMMY PIN
NOTE:
STUB)
WITHOUT T-ING (NO
ICH6-M AND GMCH
PM_THRMTRIP# SHOULD CONNECT TO
PLACE TESTPOINT ON
0.1" AWAY
SYMBOL NEED TO CHECK
FSB_IERR# WITH A GND
ON ITP SIGNALS?
NO SPACE FOR ITP
CONNECTOR, NEED TERM
CPU_PROCHOT_L TO SMC
AND CPU VR TO INFORM CPU IS HOT
TRACE LENGTH SHORTER THAN 0.5".
TRACE LENGTH SHORTER THAN 0.5".
COMP0,2 CONNECT WITH ZO=27.4OHM, MAKE
COMP1,3 CONNECT WITH ZO=55OHM, MAKE
LAYOUT NOTE:
1/16W
402
MF-LF
54.9
1%
68
1/16W
5%
402
MF-LF
1K
MF-LF 402
1% 1/16W
2.0K
MF-LF 402
1% 1/16W
1/16W
1%
402
MF-LF
54.9
1/16W
402
MF-LF
54.9
1%
1/16W
1%
402
MF-LF
54.9
54.9
402
1%
27.4
54.9
402
1%
402
27.4
NOSTUFF
402
0
NOSTUFF
1/16W
5%
402
MF-LF
1K51
1/16W
5%
402
MF-LF
OMIT
CPU
YONAH-SKT
OMIT
YONAH-SKT
CPU
402
MF-LF
1/16W
54.9
1%
54.9
MF-LF 402
1% 1/16W
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
CPU 1 OF 2-FSB
7
??
051-7032
97
TP_CPU_SPARE7
TP_CPU_SPARE4
TP_CPU_SPARE3
TP_CPU_SPARE2
CPU_GTLREF
FSB_IERR_L
FSB_DSTBP_L<0>
CPU_PSI_L
FSB_SLPCPU_L
CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_COMP<2> CPU_COMP<3>
CPU_COMP<1>
CPU_COMP<0>
FSB_DSTBP_L<3>
FSB_DSTBN_L<3>
FSB_DINV_L<3>
FSB_D_L<63>
FSB_D_L<62>
FSB_D_L<61>
FSB_D_L<60>
FSB_D_L<59>
FSB_D_L<58>
FSB_D_L<57>
FSB_D_L<56>
FSB_D_L<55>
FSB_D_L<54>
FSB_D_L<52> FSB_D_L<53>
FSB_D_L<51>
FSB_D_L<50>
FSB_D_L<49>
FSB_D_L<48>
FSB_DINV_L<2>
FSB_DSTBN_L<2>
FSB_D_L<47>
FSB_DSTBP_L<2>
FSB_D_L<45> FSB_D_L<46>
FSB_D_L<44>
FSB_D_L<43>
FSB_D_L<42>
FSB_D_L<41>
FSB_D_L<40>
FSB_D_L<39>
FSB_D_L<38>
FSB_D_L<37>
FSB_D_L<36>
FSB_D_L<35>
FSB_D_L<34>
FSB_D_L<33>
FSB_D_L<32>
CPU_BSEL<2>
FSB_DSTBN_L<1>
CPU_BSEL<0> CPU_BSEL<1>
CPU_TEST2
FSB_DINV_L<1>
FSB_DSTBP_L<1>
FSB_D_L<31>
FSB_D_L<30>
FSB_D_L<29>
FSB_D_L<26> FSB_D_L<27> FSB_D_L<28>
FSB_D_L<24> FSB_D_L<25>
FSB_D_L<23>
FSB_D_L<21> FSB_D_L<22>
FSB_D_L<20>
FSB_D_L<19>
FSB_D_L<18>
FSB_D_L<16> FSB_D_L<17>
FSB_DSTBN_L<0>
FSB_D_L<15>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<10>
FSB_D_L<9>
FSB_D_L<8>
FSB_D_L<7>
FSB_D_L<6>
FSB_D_L<5>
FSB_D_L<4>
FSB_D_L<3>
FSB_D_L<2>
FSB_D_L<1>
FSB_D_L<0>
CPU_TEST1
FSB_A_L<7>
TP_CPU_SPARE1
FSB_CLK_CPU_N
FSB_CLK_CPU_P
TP_CPU_SPARE5 TP_CPU_SPARE6
PM_THRMTRIP_L
CPU_THERMD_N
CPU_THERMD_P
XDP_DBRESET_L
XDP_TMS
XDP_TDO
XDP_TCK
XDP_BPM_L<1>
XDP_BPM_L<0>
FSB_HITM_L
FSB_HIT_L
FSB_TRDY_L
FSB_RS_L<1>
FSB_RS_L<0>
FSB_CPURST_L
FSB_LOCK_L
FSB_DBSY_L
FSB_DRDY_L
FSB_DEFER_L
FSB_BPRI_L
FSB_BNR_L
FSB_ADS_L
TP_CPU_HFPLL
TP_CPU_A37_L TP_CPU_A38_L
TP_CPU_A33_L TP_CPU_A34_L TP_CPU_A35_L TP_CPU_A36_L
TP_CPU_APM0_L TP_CPU_APM1_L
CPU_SMI_L
CPU_INTR CPU_NMI
CPU_STPCLK_L
CPU_IGNNE_L
CPU_FERR_L
CPU_A20M_L
FSB_ADSTB_L<1>
FSB_A_L<30> FSB_A_L<31>
FSB_A_L<27> FSB_A_L<28> FSB_A_L<29>
FSB_A_L<26>
FSB_A_L<25>
FSB_A_L<24>
FSB_A_L<22> FSB_A_L<23>
FSB_A_L<21>
FSB_A_L<20>
FSB_A_L<19>
FSB_A_L<18>
FSB_A_L<17>
FSB_REQ_L<4>
FSB_REQ_L<3>
FSB_REQ_L<1>
FSB_REQ_L<0>
FSB_REQ_L<2>
FSB_ADSTB_L<0>
FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>
FSB_A_L<13>
FSB_A_L<12>
FSB_A_L<11>
FSB_A_L<10>
FSB_A_L<9>
FSB_A_L<8>
FSB_A_L<5>
FSB_A_L<4>
FSB_A_L<3>
=PP1V05_S0_CPU
=PP1V05_S0_CPU
XDP_TMS
XDP_TCK
XDP_TDI
CPU_PWRGD
XDP_BPM_L<3>
FSB_DINV_L<0>
CPU_PROCHOT_L
=PP1V05_S0_CPU
XDP_BPM_L<4> XDP_BPM_L<5>
FSB_RS_L<2>
XDP_TRST_L
XDP_TDI
XDP_BPM_L<2>
TP_CPU_SPARE0
TP_CPU_A32_L
TP_CPU_EXTBREF
TP_CPU_A39_L
FSB_A_L<6>
=PP1V05_S0_CPU
FSB_BREQ0_L
CPU_INIT_L
R0703
1
2
R0704
1
2
R0705
1
2
R0706
1
2
R0720
1 2
R0721
1 2
R0722
1 2
R0719
1 2
R0718
1 2
R0717
1 2
R0716
1 2
R0730
1 2
R0712
1
2
R0707
1
2
J0700
N3 P5 P2 L1 P4 P1 R1
Y2 U5 R3 W6
A6
U4 Y5 U2 R4 T5 T3 W3 W5 Y4
J4
W2 Y1
L4 M3 K5 M1 N2 J1
H1
L2
V4
A22 A21
E2
AD4 AD3 AD1 AC4
G5
F1
C20
E1
H5 F21
A5
G6 E4
D20
C4
B3
C6 B4
H4
AC2 AC1
D21
K3 H2 K2 J3 L5
B1 F3 F4 G3
AA1
C3
B25
T22
D2 F6 D3 C1 AF1 D22 C23
AA4
C24
AB2 AA3
M4 N5 T2 V3 B2
A3
D5
AC5 AA6 AB3
A24 A25
C7
AB5
G2
AB6
J0700
B22 B23 C21
R26 U26 U1 V1
E22 F24
J24 J23 H26 F26 K22 H25
N22 K25 P26 R23
E26
L25 L22 L23 M23 P25 P22 P23 T24 R24 L26
H22
T25 N24
AA23 AB24 V24 V26 W25 U23 U25 U22
F23
AB25 W22 Y23 AA26 Y26 Y22 AC26 AA24
AC22 AC23
G25
AB22 AA21 AB21 AC25 AD20 AE22 AF23 AD24 AE21 AD21
E25
AE25 AF25 AF22 AF26
E23 K24 G24
J26
M26
V23
AC20
E5 B5 D24
H23
M24
W24
AD23
G22
N25
Y25
AE24
AD26
A2
AE6
D6 D7
C26
D25
R0702
1
2
R0701
1
2
12
5
75
12
75 21
21
12
5
12
5
12
5
12
5
12
12
12
12
12
5
12
12
12
12
12
12
12
12
12
12
12
12
5
12
5
12
12
5
12
12
12
12
12
12
5
12
12
12
12
12
12
12
12
12
34
12
5
34
34
12
5
12
5
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
5
12
12
5
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
12
5
12
34
5
34
5
59 21 14
10
10
26 11
11
7 5
11
5
11
7 5
11
11
12
5
12
5
12
12
12
12 11
5
12
5
12
5
12
12
12
12
5
12
21
5
21
5
21
5
21
5
21
5
21
21
5
12
5
12
12
12
5
12
12
12
12
12
12
12
12
12
12
12
12
12
5
12
5
12
5
12
5
12
5
12
5
12
12
12
12
12
12
12
12
12
12
12
12
11
9 8 7 6 5
11
9 8 7 6 5
11
7 5
11
7 5
11
7 5
21
11
12
5
59
11
9 8 7 6 5
11
11
12
11
5
11
7 5
11
12
5
11
9 8 7 6 5
12
5
21
5
Page 8
OUT OUT
OUT
OUT OUT
OUT
OUT
OUT
OUT
VCC_67
VCC_64
VCC_66
VCC_65
VCC_63
VCC_62
VCC_61
VCC_59 VCC_60
VCC_58
VCC_57
VCC_56
VCC_54 VCC_55
VCC_53
VCC_51 VCC_52
VCC_49 VCC_50
VCC_48
VCC_47
VCC_46
VCC_44 VCC_45
VCC_43
VCC_41 VCC_42
VCC_40
VCC_39
VCC_38
VCC_36 VCC_37
VCC_33
VCC_35
VCC_34
VCC_31 VCC_32
VCC_29 VCC_30
VCC_28
VCC_26 VCC_27
VCC_23
VCC_25
VCC_24
VCC_22
VCC_21
VCC_20
VCC_18 VCC_19
VCC_17
VCC_16
VCC_15
VCC_13 VCC_14
VCC_12
VCC_10 VCC_11
VCC_8 VCC_9
VCC_7
VCC_6
VCC_5
VCC_3 VCC_4
VCC_2
VCC_1 VCC_68
VCC_69
VCC_71
VCC_70
VCC_72
VCC_74
VCC_76
VCC_75
VCC_78
VCC_77
VCC_79
VCC_81
VCC_80
VCC_84
VCC_82 VCC_83
VCC_86
VCC_85
VCC_87
VCC_89
VCC_88
VCC_90 VCC_91 VCC_92
VCC_94
VCC_93
VCC_95 VCC_96 VCC_97
VCC_99
VCC_98
VCC_100
VCCP_1 VCCP_2 VCCP_3 VCCP_4 VCCP_5 VCCP_6 VCCP_7
VCCP_9
VCCP_8
VCCP_11
VCCP_10
VCCP_12 VCCP_13 VCCP_14
VCCP_16
VCCP_15
VCCA
VID0 VID1 VID2 VID3 VID4 VID5 VID6
VSSSENSE
VCCSENSE
VCC_73
(3 OF 4)
VSS_82 VSS_83 VSS_84 VSS_85
VSS_87
VSS_86
VSS_88 VSS_89 VSS_90
VSS_92
VSS_91
VSS_93 VSS_94 VSS_95
VSS_97
VSS_96
VSS_100
VSS_98 VSS_99
VSS_102
VSS_101
VSS_105
VSS_103 VSS_104
VSS_106 VSS_107
VSS_110
VSS_109
VSS_108
VSS_111 VSS_112
VSS_115
VSS_114
VSS_113
VSS_116 VSS_117 VSS_118
VSS_120
VSS_119
VSS_123
VSS_121 VSS_122
VSS_124 VSS_125
VSS_128
VSS_126 VSS_127
VSS_129 VSS_130
VSS_133
VSS_131 VSS_132
VSS_134 VSS_135
VSS_138
VSS_136 VSS_137
VSS_139 VSS_140 VSS_141
VSS_143
VSS_142
VSS_146
VSS_144 VSS_145
VSS_147 VSS_148
VSS_151
VSS_150
VSS_149
VSS_152 VSS_153
VSS_156
VSS_155
VSS_154
VSS_157 VSS_158 VSS_159
VSS_161
VSS_160
VSS_162
VSS_1 VSS_2 VSS_3
VSS_5
VSS_4
VSS_6 VSS_7 VSS_8
VSS_10
VSS_9
VSS_11 VSS_12
VSS_15
VSS_13 VSS_14
VSS_16 VSS_17 VSS_18 VSS_19 VSS_20
VSS_23
VSS_22
VSS_21
VSS_24 VSS_25
VSS_28
VSS_27
VSS_26
VSS_29 VSS_30
VSS_33
VSS_32
VSS_31
VSS_34 VSS_35
VSS_38
VSS_37
VSS_36
VSS_39 VSS_40 VSS_41 VSS_42 VSS_43
VSS_46
VSS_44 VSS_45
VSS_47 VSS_48
VSS_51
VSS_49 VSS_50
VSS_52 VSS_53
VSS_56
VSS_54 VSS_55
VSS_57 VSS_58 VSS_59 VSS_60 VSS_61
VSS_63
VSS_62
VSS_64 VSS_65 VSS_66
VSS_69
VSS_68
VSS_67
VSS_70 VSS_71
VSS_74
VSS_73
VSS_72
VSS_75 VSS_76
VSS_79
VSS_78
VSS_77
VSS_80 VSS_81
(4 OF 4)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
VCCA=1.5 ONLY
LAYOUT NOTE: CONNECT R0802-03 TO VCCSENSE_P/N WITH NO STUB
PROVIDE A TEST POINT (WITH NO STUB)
BETWEEN VCCSENSE AND VSSSENSE AT THE LOCATION WHERE THE TWO 54.9 OHM
RESISTORS TERMINATE THE 55 OHM TRANSMISSION LINE
TO CONNECT A DIFFERENCTIAL PROBE
LAYOUT NOTE:
0.01UF
CERM
402
20% 16V
6.3V
20%
10UF
CERM 805-1
1/16W
1%
402
MF-LF
100
1/16W
1%
402
MF-LF
100
YONAH-SKT
CPU
OMIT
YONAH-SKT
CPU
OMIT
CPU 2 OF 2-PWR/GND
051-7032
??
8 97
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
CPU_VID<5>
CPU_VID<2>
CPU_VID<0>
=PP1V05_S0_CPU
=PPVCORE_S0_CPU
=PPVCORE_S0_CPU
CPU_VCCSENSE_N
=PP1V5_S0_CPU
=PPVCORE_S0_CPU
=PP1V5_S0_CPU
CPU_VCCSENSE_P
CPU_VID<6>
CPU_VID<4>
CPU_VID<3>
CPU_VID<1>
C0800
1
2
C0801
1
2
R0803
1
2
R0802
1
2
J0700
A7
B7
AF20
B9 B10 B12 B14 B15 B17 B18 B20
C9
A9
C10 C12 C13 C15 C17 C18
D9 D10 D12 D14
A10
D15 D17 D18
E7
E9 E10 E12 E13 E15 E17
A12
E18 E20
F7
F9 F10 F12 F14 F15 F17 F18
A13
F20 AA7 AA9
AA10 AA12 AA13 AA15 AA17 AA18 AA20
A15
AB9
AC10 AB10 AB12 AB14 AB15 AB17 AB18
AB20 AB7
A17
AC7 AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10
A18
AD12 AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15
A20
AE17 AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18
B26
V6
N6 R21 R6 T21 T6 V21 W21
G21 J6 K6 M6 J21 K21 M21 N21
AF7
AD6 AF5 AE5 AF4 AE3 AF2 AE2
AE7
J0700
A4
B8
V25 W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2
B11
AA5 AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4
B13
AB8 AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8
B16
AC11 AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11
B19
AD13 AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14
B21
AE16 AE19 AE23 AE26 AF3 AF6 AF8 AF11 AF13 AF16
B24
AF19 AF21 AF24
C5 C8
C11
A8
C14 C16 C19
C2 C22 C25
D1
D4
D8 D11
A11
D13 D16 D19 D23 D26
E3
E6
E8 E11 E14
A14
E16 E19 E21 E24
F5
F8 F11 F13 F16 F19
A16
F2 F22 F25
G4
G1 G23 G26
H3
H6 H21
A19
H24
J2
J5 J22 J25
K1
K4 K23 K26
L3
A23
L6 L21 L24
M2
M5 M22 M25
N1
N4 N23
A26
N26
P3
P6 P21 P24 R2 R5 R22 R25 T1
B6 T4
T23 T26 U3 U6 U21 U24 V2 V5 V22
75
75
75
11
9 7 6 5
76
9 8 6
76
9 8 6
75
8 6
76
9 8 6
8 6
75
75
75
75
75
Page 9
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
MEROME VS. YONAH. SEE
USES DIFFERENT VALUES FOR
VCC CORE COUPLING CAPS
SECONDARY)
PRIMARY)
SECONDARY)
PLACE 6 INSIDE SOCKET
PLACE 8 INSIDE SOCKET CAVITY ON L8 (NORTH SIDE
PLACE 8 INSIDE SOCKET CAVITY ON L8 (SOUTH SIDE
SOUTH SIDE SECONDARY
PRIMARY)
DESIGN FOR 44 CERAMIC AND 3 ELECT BULK 1800UF
VCC CORE DECOUPLING
NEED LARGE BULK FOR 1.05V
PLACE INSIDE SOCKET CAVITY ON L8 (NORTH SIDE SECONDARY)
VCCP CORE DECOUPLING
CPU HEATSINK MOUNTING HOLES
WE HAD A 330UF ELEC CAP HERE FOR 1.05V RAIL - CHECK WE CAN REMOVE
CAVITY ON L1 (SOUTH SIDE
PLACE 6 INSIDE SOCKET
CAVITY ON L1 (NORTH SIDE
BOM TABLE.
X5R
20%
6.3V
22UF
805
6.3V
20%
805
X5R
22UF
OMIT
6.3V
20%
805
X5R
22UF
OMIT
X5R 805
20%
6.3V
22UF
OMIT
6.3V
20%
805
X5R
22UF
OMIT
6.3V
20%
805
X5R
22UF
OMIT
X5R 805
20%
6.3V
22UF
OMIT
X5R 805
20%
6.3V
22UF
OMIT
6.3V
20%
805
X5R
22UF
OMIT
X5R 805
20%
6.3V
22UF
OMIT
22UF
OMIT
X5R
20%
805
6.3V 805
20% X5R
6.3V
22UF
OMIT
805
20% X5R
6.3V
22UF
OMIT
805
20% X5R
22UF
6.3V
OMIT
805
20% X5R
6.3V
22UF
OMIT
805
20% X5R
6.3V
22UF
OMIT
NOSTUFF
20%
2.5V TANT D2T
470UF
805
X5R
6.3V
20%
22UF
805
X5R
20%
OMIT
6.3V
22UF
805
X5R
20%
6.3V
22UF
6.3V
20%
805
X5R
22UF
NOSTUFF
X5R
6.3V
20%
805
22UF
OMIT
805
X5R
6.3V
22UF
20%
805
X5R
6.3V
20%
22UF
805
X5R
6.3V
20%
22UF
805
X5R
6.3V
20%
22UF
805
6.3V
20%
22UF
X5R
805
X5R
20%
6.3V
22UF
805
6.3V X5R
20%
22UF
X5R
6.3V
20%
805
22UF
NOSTUFF
X5R
20%
22UF
805
6.3V
NOSTUFF
22UF
20%
6.3V X5R 805
OMIT
X5R
20%
805
6.3V
22UF
NOSTUFF
805
6.3V
20% X5R
22UF
22UF
6.3V 805
20% X5R
OMIT
805
X5R
20%
6.3V
22UF
OMIT
20%
805
X5R
22UF
6.3V
OMIT
805
20%
22UF
OMIT
X5R
6.3V
20%
805
X5R
6.3V
22UF
805
X5R
20%
6.3V
22UF
20%
805
X5R
6.3V
22UF
OMIT
20%
0.1UF
402
10V CERM
805
X5R
6.3V
20%
22UF
805
X5R
6.3V
20%
22UF
X5R
20%
6.3V 805
22UF
805
20%
6.3V
22UF
X5R
OMIT
6.3V X5R
20%
805
22UF
NOSTUFF
0.1UF
CERM
10V 402
20% 20%
402
10V CERM
0.1UF
CERM
10V 402
0.1UF
20% 20%
0.1UF
402
10V CERM CERM
10V 402
0.1UF
20%
805
X5R
20%
6.3V
22UF
OMIT
6.3V X5R
20%
805
22UF
NOSTUFF
4P75R4
OMIT
16V
20%
CERM
0.01UF
402
4P75R4
OMIT
16V
20%
CERM
0.01UF
402
4P75R4
OMIT
16V
20%
CERM
0.01UF
402
4P75R4
OMIT
16V
20%
CERM
0.01UF
402
X5R 805
20%
6.3V
22UF
OMIT
6.3V
20%
805
X5R
22UF
OMIT
X5R 805
20%
6.3V
22UF
OMIT
C922,C925,C906,C939,C919,C993,C942,C991,C995,C990,C989,C988,C920,C997,C992,C994,C996,C921,C999,C943,C998,C944,C945,C946,C941,C916,C931,C902
28138S0558
YONAH
CAP,10UF,6.3V,20%,X5R,0805
C922,C925,C906,C939,C919,C993,C942,C991,C995,C990,C989,C988,C920,C997,C992,C994,C996,C921,C999,C943,C998,C944,C945,C946,C941,C916,C931,C902
138S0552 28
CAP,22UF,6.3V,20%,X5R,0805
MEROM
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
??
051-7032
9 97
CPU DECAPS & VID<>
=PPVCORE_S0_CPU
CPU_HS_ZH610CPU_HS_ZH607 CPU_HS_ZH609CPU_HS_ZH608
=PP1V05_S0_CPU
C907
1
2
C909
1
2
C920
1
2
C939
1
2
C900
1
2
C901
1
2
C902
1
2
C904
1
2
C905
1
2
C906
1
2
C908
1
2
C910
1
2
C911
1
2
C912
1
2
C913
1
2
C914
1
2
C915
1
2
C916
1
2
C917
1
2
C918
1
2
C919
1
2
C921
1
2
C922
1
2
C923
1
2
C924
1
2
C925
1
2
C926
1
2
C928
1
2
C929
1
2
C930
1
2
C931
1
2
C932
1
2
C934
1
2
C935
1
2
C936
1
2
C937
1
2
C938
1
2
C903
1
2
ZH607
1
C950
1
2
ZH608
1
C951
1
2
ZH609
1
C952
1
2
ZH610
1
C953
1
2
C999
1
2
C998
1
2
C997
1
2
C996
1
2
C993
1
2
C994
1
2
C995
1
2
C988
1
2
C992
1
2
C991
1
2
C990
1
2
C989
1
2
C941
1
2
C942
1
2
C943
1
2
C944
1
2
C945
1
2
C946
1
2
C947
1
23
76
8 6
66
11
8 7 6 5
Page 10
D+ D-
ALERT*/
THM*
SCLK
SDATA
VDD
GND
THM2*
IO
IO IO
IN
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PLACE R1017 AND R1019 SUCH THAT THEY SHARE ONE PAD
PLACE R1002 AND R1018 SUCH THAT THEY SHARE ONE PAD
LAYOUT NOTE:
LAYOUT NOTE:
NOTE: IF CPU T DIODE TO BE READ IN OFF STATE, THEN THIS SHOULD BE S5
NOTE: SYMBOL SHOULD BE SHOWN ADT7461A
CPU THERMAL SENSOR
TEMPORARILY REMOVED BOMOPTION=CPU_TSENS_EXT
ROUTE ON SAME LAYER WITH 0.254MM TRACE WIDTH & SPACING.
ADD GND GUARD TRACES FOR CPU_THERMD_P/N
ADT7461
MSOP
CRITICAL
402
CPU_TSENS_INT
1/16W MF-LF
1%
499
50V 402
CERM
10%
0.001UF
NOSTUFF
402
16V
10% X5R
0.1UF
402
CPU_TSENS_INT
1/16W MF-LF
1%
499
402
10K
MF-LF
1/16W
5%
402
1/16W
5%
MF-LF
10K
SM-2MT-BLK-LF
CRITICAL
DEVELOPMENT
402
CPU_TSENS_EXT
1/16W
5%
MF-LF
0
402
CPU_TSENS_EXT
0
MF-LF
5%
1/16W
402
NOSTUFF
0
MF-LF
5%
1/16W
CPU TEMP SENSOR
051-7032
??
10 97
PP3V3_S0
THERM_DX_N
THRM_THM
=SMB_THRM_CLK
THRM_ALERT_L
PM_THRM_L
THERM_DX_P
CPU_THERMD_P
CPU_THERMD_N
THERM_DX_P THERM_DX_N
CPU_THERMD_EXT_P CPU_THERMD_EXT_N
=SMB_THRM_DATA
U1000
6
2
3
5
8
7
4
1
C1001
1
2
R1005
1 2
R1002
1 2
C1000
1
2
R1017
1 2
R1001
1
2
R1000
1
2
J1000
3
4
1 2
R1018
1 2
R1019
1 2
94 83 76 61 59 41 26
6
10
59
58 23
10
7
7
10
10
59
Page 11
OUT OUT
OUT
OUT
OUT
IN
IN IN
IO
IO
IO
IO
IO
IO
OUT
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CONNECTOR’S FBO PIN.
ROUTE THE TCK SIGNAL FROM ITP700FLEX CONNECTOR’S TCK PIN TO CPU’S
518S0320
(TCK)
(FBO)
CPU ITP700FLEX DEBUG SUPPORT
(DEBUG PORT ACTIVE) (DBR#)
(DBA#)
NC
NC
NC
INDICATE THAT ITP IS USING TAP I/F, NC IN 945GM CHIPSET SYSTEM.
TO ICH7M SYS_RST*, AND WITH SYSTEM RESET LOGIC
(AND WITH RESET BUTTON)
(DEBUG PORT RESET)
(FROM CK410M HOST 133/167MHZ)
P7 HAS OTHER PULL UP RESISTORS THAT MAY IMPACT ITP FUNCTIONALITY
ITP TCK SIGNAL LAYOUT NOTE:
TCK PIN AND THEN FORK BACK FROM CPU TCK PIN AND ROUTE BACK TO ITP700FLEX
ITP
402
1/16W
1%
22.6
MF-LF
22.6
MF-LF
1/16W
1%
402
ITP
MF-LF
ITP
402
1% 1/16W
54.9
ITP
0.1UF
10% X5R
402
16V
ITP
1/16W
5% MF-LF
402
240
DEVELOPMENT
52435-2872
F-RT-SM
1/16W MF-LF
1%
54.9
402
MF-LF
1/16W
5%
402
680
SYNC_MASTER=M38
9711
??
051-7032
SYNC_DATE=01/05/2006
CPU ITP700FLEX DEBUG
=PP1V05_S0_CPU
FSB_CPURST_L
XDP_TDO
ITPRESET_L
ITP_TDO
=PP3V3_S5_SB_PM
=PP1V05_S0_CPU
XDP_BPM_L<5> XDP_BPM_L<4>
XDP_BPM_L<2>
XDP_TDI XDP_TMS
XDP_TCK
CPU_XDP_CLK_P
CPU_XDP_CLK_N
XDP_TCK
XDP_BPM_L<3>
XDP_BPM_L<1> XDP_BPM_L<0>
XDP_TRST_L
XDP_DBRESET_L
R1100
1 2
R1102
1 2
R1103
1
2
C1100
1
2
R1104
1
2
J1101
1
10 11 12 13 14 15 16 17 18 19
2
20 21 22 23 24 25 26 27 28
29
3
30
4 5 6 7 8 9
R1101
1
2
R1106
1
2
11
9 8 7 6 5
12
7 5
7 5
23
6
11
9 8 7 6 5
7
7
7
7 5
7 5
11
7 5
34
34
11
7 5
7
7
7
7 5
26
7
Page 12
IO
IO IO
OUT
OUT
OUT
IO
IO
IO
IO IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
OUT
IO
OUT
OUT
OUT
OUT
IO IO
IO IO
IO
IN
IO
IN
IO
IO
HD4*
HD6*
HD16*
HTRDY*
HSLPCPU*
HRS1*
HRS0*
HHITM* HLOCK*
HHIT*
HDSTBP2* HDTSBP3*
HDSTBP1*
HDSTBP0*
HDSTBN3*
HDSTBN1* HDSTBN2*
HDSTBN0*
HDINV2* HDINV3*
HDINV1*
HDINV0*
HDVREF
HDRDY*
HDPWR*
HDEFER*
HDBSY*
HCPURST*
HBREQ0*
HBPRI*
HBNR*
HAVREF
HCLKIN*
HCLKIN
HYSWING
HYRCOMP HYSCOMP
HXSWING
HXSCOMP
HXRCOMP
HA13*
HADS*
HADSTB0*
HD3*
HD2*
HD1*
HD0*
HD63*
HD62*
HD61*
HD60*
HD59*
HD58*
HD57*
HD56*
HD55*
HD54*
HD53*
HD52*
HD51*
HD50*
HD49*
HD48*
HD47*
HD46*
HD45*
HD44*
HD43*
HD42*
HD41*
HD40*
HD39*
HD38*
HD37*
HD36*
HD35*
HD34*
HD33*
HD32*
HD31*
HD29*
HD28*
HD27*
HD26*
HD25*
HD24*
HD23*
HD22*
HD21*
HD20*
HD19*
HD18*
HD17*
HD15*
HD10* HD11* HD12* HD13* HD14*
HD5*
HD7* HD8* HD9*
HA30*
HA29*
HA28*
HA27*
HA26*
HA25*
HA24*
HA23*
HA31*
HA20*
HA19*
HA18*
HA16*
HA15*
HA14*
HA21* HA22*
HA17*
HA9*
HA8*
HA7*
HA6*
HA5*
HA4*
HA3*
HA10* HA11* HA12*
HADSTB1*
HREQ0* HREQ1* HREQ2* HREQ3*
HD30*
HREQ4*
HRS2*
(1 OF 10)
HOST
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
0.1uF
10% 16V X5R 402
402
MF-LF
1/16W
1%
200
402
MF-LF
1/16W
1%
100
402
MF-LF
1/16W
1%
54.9
24.9
1% 1/16W MF-LF
402
402
MF-LF
1/16W
1%
221
100
402
MF-LF
1/16W
1%
10% 16V X5R 402
0.1uF
0.1uF
10% 16V X5R 402
402
MF-LF
1/16W
1%
221
402
MF-LF
1/16W
1%
54.9
100
402
MF-LF
1/16W
1%
24.9
1% 1/16W MF-LF
402
OMIT
945GM
NB
BGA
051-7032
9712
??
NB CPU Interface
SYNC_DATE=01/05/2006
SYNC_MASTER=M1
NB_FSB_XRCOMP
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
=PP1V05_S0_FSB_NB
FSB_RS_L<2>
FSB_REQ_L<4>
FSB_D_L<30>
FSB_REQ_L<3>
FSB_REQ_L<2>
FSB_REQ_L<1>
FSB_REQ_L<0>
FSB_ADSTB_L<1>
FSB_A_L<12>
FSB_A_L<11>
FSB_A_L<10>
FSB_A_L<3> FSB_A_L<4> FSB_A_L<5> FSB_A_L<6> FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>
FSB_A_L<17>
FSB_A_L<22>
FSB_A_L<21>
FSB_A_L<14> FSB_A_L<15> FSB_A_L<16>
FSB_A_L<18> FSB_A_L<19> FSB_A_L<20>
FSB_A_L<31>
FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30>
FSB_D_L<14>
FSB_D_L<13>
FSB_D_L<12>
FSB_D_L<11>
FSB_D_L<15>
FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>
FSB_D_L<31> FSB_D_L<32> FSB_D_L<33> FSB_D_L<34> FSB_D_L<35> FSB_D_L<36> FSB_D_L<37> FSB_D_L<38> FSB_D_L<39> FSB_D_L<40> FSB_D_L<41> FSB_D_L<42> FSB_D_L<43> FSB_D_L<44> FSB_D_L<45> FSB_D_L<46> FSB_D_L<47> FSB_D_L<48> FSB_D_L<49> FSB_D_L<50> FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58> FSB_D_L<59> FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>
FSB_ADSTB_L<0>
FSB_ADS_L
FSB_A_L<13>
NB_FSB_XSCOMP NB_FSB_XSWING
NB_FSB_YSCOMP
NB_FSB_YRCOMP
NB_FSB_YSWING
FSB_CLK_NB_P FSB_CLK_NB_N
FSB_BNR_L FSB_BPRI_L FSB_BREQ0_L FSB_CPURST_L FSB_DBSY_L FSB_DEFER_L FSB_DPWR_L FSB_DRDY_L
FSB_DINV_L<3>
FSB_DSTBN_L<1>
FSB_DSTBP_L<0>
FSB_HIT_L
FSB_LOCK_L
FSB_HITM_L
FSB_RS_L<0> FSB_RS_L<1>
FSB_SLPCPU_L FSB_TRDY_L
FSB_D_L<16>
FSB_D_L<0>
FSB_D_L<3>
FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10>
FSB_D_L<6>
FSB_D_L<5>
FSB_D_L<4>
FSB_D_L<2>
FSB_D_L<1>
NB_FSB_VREF
FSB_DINV_L<2>
FSB_DINV_L<1>
FSB_DSTBN_L<0>
FSB_DINV_L<0>
FSB_DSTBP_L<3>
FSB_DSTBP_L<2>
FSB_DSTBP_L<1>
FSB_DSTBN_L<3>
FSB_DSTBN_L<2>
FSB_D_L<17>
C1211
1
2
R1211
1
2
R1210
1
2
R1220
1
2
R1221
1
2
R1225
1
2
R1226
1
2
C1226
1
2
C1236
1
2
R1235
1
2
R1230
1
2
R1236
1
2
R1231
1
2
U1200
H11 J12
G14
D9 J14
H13
J15 F14
D12 A11
C11
A12 A13
E13
G13 F12
B12
B14 C12
A14
H9
C14
D14
C9
E11 G11
F11 G12
F9
E8 B9
C13
J13 C6
F6
C7
AG2
AG1
B7
F1
J1
K7 J8
H4
J3
K11
G4 T10
W11
T3
U7
H1
U9
U11 T11
W9
T1
T8
T4
W7
U5
T9
J6
W6
T5
AB7 AA9
W4
W3
Y3
Y7
W5
Y10
H3
AB8
W2
AA4
AA7 AA2
AA6
AA10
Y8
AA1 AB4
K2
AC9
AB11 AC11
AB3
AC2 AD1
AD9
AC1 AD7
AC6
G1
AB5
AD10
AD4 AC8
G2
K9
K1
A7 C3
J7 W8
U3
AB10
J9
H8
K4
T7
Y5 AC4
K3
T6
AA5 AC5
K13
D3 D4
B3
D8
G8 B8
F8
A8
B4
E6 D6
E3
E7
E1
E2
E4
Y1
U1
W1
19 12
6 5
19 12
6 5
19 12
6 5
7
7 5
7
7 5
7 5
7 5
7 5
7 5
7
7
7
7
7
7
7 5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7 5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7 5
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7 5
7
7
7
7
7 5
7
7
34
5
34
5
7 5
7 7
5
7 5
7 7
5
7
7 5
7 5
7 5
7 5
7 5
7 5
7
7
7
7
7 5
7 5
7
7
7
7
7
7
7
7
7
7
5
7 5
7 5
7 5
7 5
7 5
7 5
7 5
7 5
7 5
7
Page 13
CRT_BLUE*
CRT_BLUE
CRT_GREEN*
CRT_GREEN
CRT_RED
CRT_DDC_CLK
CRT_RED*
HSYNC
CRT_DDC_DATA
CRT_VSYNC
CRT_IREF
TV_IRTNC
TV_IRTNB
TV_IREF TV_IRTNA
TV_DACB_OUT TV_DACC_OUT
TV_DACA_OUT
LB_DATA2
LB_DATA1
LB_DATA0
LB_DATA2*
LB_DATA1*
LB_DATA0*
LA_DATA2
LA_DATA1
LA_DATA0
LA_DATA2*
LA_DATA1*
LA_DATA0*
LB_CLK
LB_CLK*
LA_CLK
LA_CLK*
L_VDDEN
L_VREFL
L_VREFH
L_VBG
L_IBG
L_DDC_CLK L_DDC_DATA
EXP_A_COMPI EXP_A_COMPO
EXP_A_RXN0 EXP_A_RXN1 EXP_A_RXN2 EXP_A_RXN3 EXP_A_RXN4 EXP_A_RXN5 EXP_A_RXN6 EXP_A_RXN7 EXP_A_RXN8
EXP_A_RXN9 EXP_A_RXN10 EXP_A_RXN11 EXP_A_RXN12 EXP_A_RXN13
EXP_A_RXN15
EXP_A_RXN14
EXP_A_RXP0
EXP_A_RXP1
EXP_A_RXP2
EXP_A_RXP4
EXP_A_RXP3
EXP_A_RXP5
EXP_A_RXP6
EXP_A_RXP7
EXP_A_RXP10
EXP_A_RXP9
EXP_A_RXP8
EXP_A_RXP11 EXP_A_RXP12
EXP_A_RXP14
EXP_A_RXP13
EXP_A_RXP15
EXP_A_TXN1
EXP_A_TXN0
EXP_A_TXN3
EXP_A_TXN2
EXP_A_TXN6
EXP_A_TXN5
EXP_A_TXN4
EXP_A_TXN7
EXP_A_TXN8
EXP_A_TXN9 EXP_A_TXN10 EXP_A_TXN11 EXP_A_TXN12
EXP_A_TXN14
EXP_A_TXN13
EXP_A_TXN15
EXP_A_TXP0
EXP_A_TXP2
EXP_A_TXP1
EXP_A_TXP3
EXP_A_TXP4
EXP_A_TXP5
EXP_A_TXP7
EXP_A_TXP6
EXP_A_TXP8
EXP_A_TXP9 EXP_A_TXP10
EXP_A_TXP12
EXP_A_TXP11
EXP_A_TXP13 EXP_A_TXP14 EXP_A_TXP15
L_CLKCTLB
L_BKLTEN L_CLKCTLA
L_BKLTCTL
(3 OF 10)
LVDS
TV
VGA
PCI-EXPRESS GRAPHICS
IN
IN
OUT
IN
OUT OUT
OUT OUT
IN IN
OUT
OUT
OUT
OUT
IN
OUT
OUT
IO
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT
IN
IO IO
OUT
OUT OUT
OUT
OUT OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IO IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Tie VCC_TXLVDS and VCCA_LVDS to GND. If SDVO is used
Can leave all signals NC if LVDS is not implemented
CRT Disable
TV-Out Disable
Composite: DACA only
TV-Out Signal Usage:
HSYNC and VSYNC to GND. Tie VCCA_CRTDAC to VCC Core
Unused DAC outputs must remain powered, but can omit
S-Video: DACB & DACC only
connect to GND through 75-ohm resistors.
Tie VCCD_TVDAC, VCCD_QTVDAC, VCCA_TVDACx, and
Component: DACA, DACB & DACC
rail, and tie VSSA_CRTDAC and VCC_SYNC to GND.
VCCA_TVBG to 1.5V power rail. Tie VSSA_TVBG to GND.
Tie DACx_OUT, IRTNx, and IREF to 1.5V power rail.
filtering components. Unused DAC outputs should
Tie R/R#/G/G#/B/B# and IREF to VCC Core rail, tie
VCCD_LVDS must remain powered with proper decoupling.
LVDS Disable
Otherwise, tie VCCD_LVDS to GND also.
SDVOC_CLKP
SDVOC_BLUE
SDVOC_GREEN
SDVOC_RED
SDVOB_BLUE SDVOB_CLKP
SDVOB_RED# SDVOB_GREEN# SDVOB_BLUE# SDVOB_CLKN SDVOC_RED# SDVOC_GREEN# SDVOC_BLUE# SDVOC_CLKN
SDVOB_RED SDVOB_GREEN
SDVO_FLDSTALL
SDVO_INT
SDVO_TVCLKIN
SDVO_INT#
SDVO_TVCLKIN#
SDVO Alternate Function
SDVO_FLDSTALL#
BGA
NB
945GM
OMIT
402
MF-LF
1/16W
1%
24.9
051-7032
??
9713
SYNC_MASTER=M1
SYNC_DATE=01/05/2006
NB PEG / Video Interfaces
PEG_R2D_C_N<15>
PEG_R2D_C_N<13> PEG_R2D_C_N<14>
PEG_R2D_C_N<12>
PEG_R2D_C_N<11>
PEG_R2D_C_N<10>
PEG_R2D_C_N<9>
PEG_R2D_C_N<8>
PEG_R2D_C_N<7>
PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6>
PEG_D2R_N<10>
PEG_D2R_N<8>
PEG_D2R_N<6>
PEG_D2R_N<5>
PEG_D2R_N<4>
PEG_D2R_N<3>
PEG_D2R_N<9>
PEG_D2R_N<7>
PEG_D2R_N<14>
PEG_D2R_N<13>
PEG_D2R_N<12>
PEG_D2R_N<11>
PEG_D2R_N<15>
LVDS_BKLTCTL
LVDS_CLKCTLA
PEG_D2R_P<1>
CRT_HSYNC_R
CRT_VSYNC_R
LVDS_CLKCTLB
=PP1V5_S0_NB_PCIE
LVDS_BKLTEN
PEG_R2D_C_P<15>
PEG_R2D_C_P<14>
PEG_R2D_C_P<13>
PEG_R2D_C_P<11> PEG_R2D_C_P<12>
PEG_R2D_C_P<10>
PEG_R2D_C_P<9>
PEG_R2D_C_P<8>
PEG_R2D_C_P<6> PEG_R2D_C_P<7>
PEG_R2D_C_P<5>
PEG_R2D_C_P<4>
PEG_R2D_C_P<3>
PEG_R2D_C_P<1> PEG_R2D_C_P<2>
PEG_R2D_C_P<0>
PEG_R2D_C_N<2> PEG_R2D_C_N<3>
PEG_R2D_C_N<0> PEG_R2D_C_N<1>
PEG_D2R_P<15>
PEG_D2R_P<13> PEG_D2R_P<14>
PEG_D2R_P<12>
PEG_D2R_P<11>
PEG_D2R_P<8> PEG_D2R_P<9> PEG_D2R_P<10>
PEG_D2R_P<7>
PEG_D2R_P<6>
PEG_D2R_P<5>
PEG_D2R_P<3> PEG_D2R_P<4>
PEG_D2R_P<2>
PEG_D2R_P<0>
PEG_D2R_N<2>
PEG_D2R_N<1>
PEG_D2R_N<0>
PEG_COMP
LVDS_DDC_DATA
LVDS_DDC_CLK
LVDS_IBG TP_LVDS_VBG
LVDS_VREFH LVDS_VREFL
LVDS_VDDEN
LVDS_A_CLK_N LVDS_A_CLK_P LVDS_B_CLK_N LVDS_B_CLK_P
LVDS_A_DATA_N<0> LVDS_A_DATA_N<1> LVDS_A_DATA_N<2>
LVDS_A_DATA_P<0> LVDS_A_DATA_P<1> LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0> LVDS_B_DATA_N<1> LVDS_B_DATA_N<2>
LVDS_B_DATA_P<0> LVDS_B_DATA_P<1> LVDS_B_DATA_P<2>
CRT_IREF
CRT_DDC_DATA
CRT_RED_L
CRT_DDC_CLK
CRT_RED
CRT_GREEN CRT_GREEN_L
CRT_BLUE CRT_BLUE_L
TV_IRTNC
TV_IRTNB
TV_IRTNA
TV_IREF
TV_DACC_OUT
TV_DACB_OUT
TV_DACA_OUT
U1200
E23
D23
C26
C25
C22
B22
J22
A21 B21
H23
D40 D38
F34
G38
V34 W38
Y34 AA38
AB34
AC38
H34
J38
L34 M38
N34
P38 R34
T38
D34 F38
T34
V38 W34
Y38
AA34 AB38
G34
H38 J34
L38
M34 N38
P34 R38
F36
G40
V36 W40
Y36 AA40
AB36
AC40
H36
J40
L36 M40
N36
P40 R36
T40
D36 F40
T36
V40 W36
Y40
AA36 AB40
G36
H40 J36
L40
M36 N40
P36 R40
G23
D32 J30
H30
H29 G26
G25 B38
C35
F32 C33
C32
A32
A33
B37
C37
B34
B35
A36
A37
E26
E27
F30
G30
D29
D30
F28
F29
A16
C18
A19
J20 B16
B18 B19
R1310
1
2
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
5
94
94
95
96
96
94
19
6
5
95
95
95
95
95
95
95
95
95
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
94
96
97
96
97
96
96
96
96
96
96
96
96
96
96
96
96
Page 14
SM_CS0*
RSVD15
RSVD14
SM_CKE2
RSVD2 RSVD3
RSVD6
RSVD4 RSVD5
RSVD8
RSVD7
RSVD9
RSVD1
RSVD10 RSVD11 RSVD12 RSVD13
CFG1
CFG0
CFG2 CFG3 CFG4
CFG6
CFG5
CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14
CFG17
CFG16
CFG15
CFG18 CFG19 CFG20
PM_BM_BUSY* PM_EXTTS0* PM_EXTTS1* PW_THRMTRIP* PWROK RSTIN*
SDVO_CTRLCLK SDVO_CTRLDATA ICH_SYNC* CLK_REQ*
NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9
NC0 NC1
NC13
NC12
NC11
NC10
NC18
NC17
NC16
NC15
NC14
SM_CK0 SM_CK1 SM_CK2
SM_CK0*
SM_CK3
SM_CK1* SM_CK2* SM_CK3*
SM_CKE0 SM_CKE1
SM_CKE3
SM_CS1* SM_CS2* SM_CS3*
SMOCDCOMP0 SMOCDCOMP1
SM_ODT1
SM_ODT0
SM_ODT2
SMRCOMP*
SM_ODT3
SMRCOMP
SMVREF0 SMVREF1
G_CLKIN*
G_CLKIN
D_REFCLKIN*
D_REFCLKIN
D_REFSSCLKIN*
D_REFSSCLKIN
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3
DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3
DMI_TXP0
DMI_TXP2
DMI_TXP1
DMI_TXP3
DDR MUXING
CFG
NC PM
CLKDMI
MISC
(2 OF 10)
RSVD
IN
IN
IN
IN
IN
OUT
OUT
IN
IN
IN
IO IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT OUT
OUT
OUT OUT
OUT OUT
IN
IN
IN IN
IN
IN IN
IN
IN IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC NC
IPD
IPD
(LA_DATAN3) (LA_DATAP3) (LB_DATAN3) (LB_DATAP3)
(H_EDRDY#)
(D_PLLMON1)
(H_PROCHOT#)
(TESTIN#) (TV_DCONSEL0) (TV_DCONSEL1)
(H_PLLMON1)
(H_PLLMON1#)
(H_PCREQ#)
(VSS_MCHDETECT)
(D_PLLMON1#)
NC NC
NC
NC
NC
NC NC NC NC NC NC NC NC NC
NC
NC NC NC NC
IPU
IPD
IPU
IPU
IPU IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
IPU
NC
NC
IPU
IPU
NC
NC
NC
NC
NC
OMIT
945GM
NB
BGA
100
5% 1/16W MF-LF
402
1/16W MF-LF
5%
402
10K
MF-LF
1/16W
5%
402
10K
20% 10V CERM 402
0.1uF
20% 10V
CERM
402
0.1uF
80.6
MF-LF 402
1% 1/16W
80.6
MF-LF 402
1% 1/16W
10K
MF-LF
402
5%
1/16W
14 97
??
051-7032
NB Misc Interfaces
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
NB_BSEL<1>
TP_NB_XOR_FSB2_H7
TP_NB_XOR_LVDS_D27
TP_NB_XOR_LVDS_D28
TP_NB_XOR_LVDS_A34
MEM_VREF_NB_1
MEM_VREF_NB_0
MEM_RCOMP
MEM_RCOMP_L
=PP1V8_S3_MEM_NB
MEM_CKE<2>
MEM_CS_L<1> MEM_CS_L<2> MEM_CS_L<3>
MEM_ODT<1> MEM_ODT<2>
NB_CFG<12>
MEM_CS_L<0>
NB_BSEL<0>
NB_BSEL<2> NB_CFG<3> NB_CFG<4>
NB_CFG<6>
NB_CFG<5>
NB_CFG<7>
NB_CFG<9> NB_CFG<10>
NB_CFG<14>
NB_CFG<17>
NB_CFG<16>
NB_CFG<15>
NB_CFG<19> NB_CFG<20>
PM_BMBUSY_L
PM_THRMTRIP_L VR_PWRGOOD_DELAY
SDVO_CTRLCLK SDVO_CTRLDATA NB_SB_SYNC_L
MEM_CLK_P<0> MEM_CLK_P<1> MEM_CLK_P<2>
MEM_CLK_N<0>
MEM_CLK_P<3>
MEM_CLK_N<1> MEM_CLK_N<2> MEM_CLK_N<3>
MEM_CKE<0> MEM_CKE<1>
MEM_CKE<3>
MEM_ODT<0>
MEM_ODT<3>
NB_CLK100M_GCLKIN_N NB_CLK100M_GCLKIN_P
DMI_S2N_N<0> DMI_S2N_N<1> DMI_S2N_N<2> DMI_S2N_N<3>
DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2> DMI_S2N_P<3>
DMI_N2S_N<0> DMI_N2S_N<1> DMI_N2S_N<2> DMI_N2S_N<3>
DMI_N2S_P<0>
DMI_N2S_P<2>
DMI_N2S_P<1>
DMI_N2S_P<3>
NB_RST_IN_L
NB_CFG<8>
NB_CFG<11>
NB_CFG<13>
NB_CFG<18>
=PP3V3_S0_NB
PM_DPRSLPVR
TP_NB_TESTIN_L
TP_NB_XOR_LVDS_A35
NB_TV_DCONSEL0 NB_TV_DCONSEL1
=PP3V3_S0_NB
NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFCLKIN_P
NB_CLK_DREFCLKIN_N
CLK_NB_OE_L
NB_RST_IN_L_R
PM_EXTTS_L
TP_NB_RSVD3_F3 TP_NB_RSVD4_F7
U1200
K16
K18
E16 D15
G15
K15 C15
H16
G18 H15
J25 K27
J18
J26
F18
E15
F15 E18
D19 D16
G16
H32
A26
A27
D41
C40
AE35 AF39
AG35
AH39
AC35 AE39
AF35
AG39
AE37
AF41
AG37 AH41
AC37
AE41
AF37 AG41
AG33
AF33
K28
D1
C41
B2
AY41
AY1
AW41
AW1
A40
A4
A39
A3
C1
BA41
BA40 BA39
BA3
BA2 BA1
B41
G28
F25 H26
G6
AH33 AH34
T32
J29
A41
A35 A34
D28 D27
R32
F3 F7
AG11
AF11
H7
J19
K30
H28
H27
AY35
AW35
AR1
AT1
AW7
AY7
AW40
AY40
AU20
AT20
BA29 AY29
AW13
AW12 AY21
AW21
BA13 BA12
AY20 AU21
AL20
AF10
AT9
AV9
AK1
AK41
R1410
1
2
R1411
1
2
R1420
1
2
R1430
1 2
R1441
1
2
R1440
1
2
C1416
1
2
C1415
1
2
34
19 16
6
30 29
30 28
30 29
30 29
30 28
30 29
30 28
34
34
20
20
20
20
20
20
23
75 26
5
95
95
22
28
28
29
28
29
28
29
29
30 28
30 28
30 29
30 28
30 29
34
5
34
5
22
5
22
22
22
22
5
22
22
22
22
5
22
22
22
22
5
22
22
22
6
20
20 19 14
6
75 23
20 19 14
6
34
5
34
5
34
5
34
5
33
5
59 58
Page 15
SA_DQ1
SA_DQ0
SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10
SA_DQ12
SA_DQ11
SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27
SA_DQ29
SA_DQ28
SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33
SA_DQ35
SA_DQ34
SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44
SA_DQ46
SA_DQ45
SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
SA_BS1
SA_BS0
SA_BS2
SA_CAS*
SA_DM0 SA_DM1 SA_DM2 SA_DM3
SA_DM5
SA_DM4
SA_DM7
SA_DM6
SA_DQS0
SA_DQS2
SA_DQS1
SA_DQS3
SA_DQS5
SA_DQS4
SA_DQS6 SA_DQS7
SA_DQS3*
SA_DQS2*
SA_DQS4* SA_DQS5* SA_DQS6* SA_DQS7*
SA_MA1
SA_MA0
SA_MA2 SA_MA3
SA_MA5
SA_MA4
SA_MA6 SA_MA7
SA_MA9
SA_MA8
SA_MA10 SA_MA11 SA_MA12 SA_MA13
SA_RAS*
SA_RCVENIN*
SA_RCVENOUT*
SA_WE*
SA_DQS1*
SA_DQS0*
(4 OF 10)
DDR SYSTEM MEMORY A
IO
IO IO
IO IO
IO
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
IO IO
IO
IO
IO IO
IO IO
IO IO
IO IO
IO
IO IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
SB_DQ1
SB_DQ0
SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10
SB_DQ12
SB_DQ11
SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27
SB_DQ29
SB_DQ28
SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33
SB_DQ35
SB_DQ34
SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44
SB_DQ46
SB_DQ45
SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
SB_BS1
SB_BS0
SB_BS2
SB_CAS*
SB_DM0 SB_DM1 SB_DM2 SB_DM3
SB_DM5
SB_DM4
SB_DM7
SB_DM6
SB_DQS0
SB_DQS2
SB_DQS1
SB_DQS3
SB_DQS5
SB_DQS4
SB_DQS6 SB_DQS7
SB_DQS3*
SB_DQS2*
SB_DQS4* SB_DQS5* SB_DQS6* SB_DQS7*
SB_MA1
SB_MA0
SB_MA2 SB_MA3
SB_MA5
SB_MA4
SB_MA6 SB_MA7
SB_MA9
SB_MA8
SB_MA10 SB_MA11 SB_MA12 SB_MA13
SB_RAS*
SB_RCVENIN*
SB_RCVENOUT*
SB_WE*
SB_DQS1*
SB_DQS0*
(5 OF 10)
DDR SYSTEM MEMORY B
IO IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
IO
IO
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
OUT
OUT
IO
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO IO
IO
IO IO
IO
IO IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC NC
NC NC
BGA
945GM
NB
OMIT
BGA
945GM
NB
OMIT
SYNC_DATE=01/05/2006
SYNC_MASTER=M1
NB DDR2 Interfaces
051-7032
??
9715
MEM_A_DQ<5>
MEM_A_DQS_N<0> MEM_A_DQS_N<1>
MEM_A_WE_L
MEM_A_RAS_L
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<8> MEM_A_A<9>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<4> MEM_A_A<5>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<0> MEM_A_A<1>
MEM_A_DQS_N<7>
MEM_A_DQS_N<6>
MEM_A_DQS_N<5>
MEM_A_DQS_N<4>
MEM_A_DQS_N<2> MEM_A_DQS_N<3>
MEM_A_DQS_P<7>
MEM_A_DQS_P<6>
MEM_A_DQS_P<4> MEM_A_DQS_P<5>
MEM_A_DQS_P<3>
MEM_A_DQS_P<1> MEM_A_DQS_P<2>
MEM_A_DQS_P<0>
MEM_A_DM<6> MEM_A_DM<7>
MEM_A_DM<4> MEM_A_DM<5>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>
MEM_A_CAS_L
MEM_A_BS<2>
MEM_A_BS<0> MEM_A_BS<1>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQ<61>
MEM_A_DQ<60>
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<45> MEM_A_DQ<46>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<34> MEM_A_DQ<35>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<28> MEM_A_DQ<29>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<11> MEM_A_DQ<12>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<0> MEM_A_DQ<1>
MEM_B_DQS_N<0> MEM_B_DQS_N<1>
MEM_B_WE_L
MEM_B_RAS_L
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<8> MEM_B_A<9>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<4> MEM_B_A<5>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<0> MEM_B_A<1>
MEM_B_DQS_N<7>
MEM_B_DQS_N<6>
MEM_B_DQS_N<5>
MEM_B_DQS_N<4>
MEM_B_DQS_N<2> MEM_B_DQS_N<3>
MEM_B_DQS_P<7>
MEM_B_DQS_P<6>
MEM_B_DQS_P<4> MEM_B_DQS_P<5>
MEM_B_DQS_P<3>
MEM_B_DQS_P<1> MEM_B_DQS_P<2>
MEM_B_DQS_P<0>
MEM_B_DM<6> MEM_B_DM<7>
MEM_B_DM<4> MEM_B_DM<5>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>
MEM_B_CAS_L
MEM_B_BS<2>
MEM_B_BS<0> MEM_B_BS<1>
MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<45> MEM_B_DQ<46>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<34> MEM_B_DQ<35>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<28> MEM_B_DQ<29>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<11> MEM_B_DQ<12>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<0> MEM_B_DQ<1>
U1200
AU12
AV14
BA20
AY13 AJ33
AM35
AL26 AN22
AM14
AL9 AR3
AH4
AJ35
AJ34
AR31 AP31
AN38
AM36 AM34
AN33
AK26 AL27
AM26
AN24
AM31
AK28
AL28 AM24
AP26
AP23 AL22
AP21
AN20 AL23
AP24
AM33
AP20 AT21
AR12 AR14
AP13
AP12 AT13
AT12
AL14 AL12
AJ36
AK9
AN7 AK8
AK7 AP9
AN9
AT5 AL5
AY2
AW2
AK35
AP1
AN2
AV2 AT3
AN1 AL2
AG7
AF9 AG4
AF6
AJ32
AG9 AH6
AF4
AF8
AH31
AN35 AP33
AK33
AK32
AT33
AU33
AN28
AN27
AM22
AM21
AN12
AM12
AN8
AL8
AP3
AN3
AG5
AH5
AY16
AU14
AU13
AT17
AV20 AV12
AW16
BA16 BA17
AU16
AV17 AU17
AW17
AT16
AW14
AK23
AK24 AY14
U1200
AT24
AV23
AY28
AR24 AK36
AR38
AT36 BA31
AL17
AH8 BA5
AN4
AK39
AJ37
AU38 AV38
AP38
AR40 AW38
AY38
BA38 AV36
AR36
AP36
AP39
BA36
AU36 AP35
AP34
AY33 BA33
AT31
AU29 AU31
AW31
AR41
AV29 AW29
AM19 AL19
AP14
AN14 AN17
AM16
AP15 AL15
AJ38
AJ11
AH10
AJ9
AN10 AK13
AH11
AK10
AJ8
BA10
AW10
AK38
BA4
AW4
AY10
AY9
AW5 AY5
AV4
AR5 AK4
AK3
AN41
AT4 AK5
AJ5
AJ3
AP41
AT40 AV41
AM39
AM40
AT39
AU39
AU35
AT35
AR29
AP29
AR16
AP16
AR10
AT10
AR7
AT7
AN5
AP5
AY23
AW24
AV24
BA27
AY27 AR23
AY24
AR28 AT27
AT28
AU27 AV28
AV27
AW27
AU23
AK16
AK18 AR27
28
28
5
28
5
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
30 28
28
5
28
5
28
5
28
5
28
5
28
5
28
5
28
5
28
5
28
5
28
5
28
5
28
5
28
5
28
28
28
28
28
28
28
28
30 28
30 28
30 28
30 28
28
28
28
28
28
5
28
28
28
28
28
5
28
28
28
28
28
28
28
5
28
28
28
28
28
28
28
28
5
28
28
28
28
28
28
28
28
28
28
28
28
28
28
5
28
28
28
28
28
28
28
28
28
5
28
28
5
28
28
28
28
28
28
28
5
28
28
28
28
28
28
29
5
29
5
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
30 29
29
5
29
5
29
5
29
5
29
5
29
5
29
5
29
5
29
5
29
5
29
5
29
5
29
5
29
5
29
29
29
29
29
29
29
29
30 29
30 29
30 29
30 29
29
29
5
29
29
29
29
29
29
29
29
29
29
29
29
29
29
5
29
29
29
29
5
29
29
29
29
29
29
5
29
29
29
29
29
29
29
29
29
29
29
29
29
5
29
29
5
29
29
29
29
29
29
29
29
29
29
29
29
29
29
29
5
29
29
5
29
29
29
29
29
29
Page 16
VCC_SM19
VCC_SM107
VCC_SM105
VCC_SM106
VCC_SM102
VCC_SM104
VCC_SM103
VCC_SM100
VCC_SM101
VCC_SM98
VCC_SM99
VCC_SM97
VCC_SM95
VCC_SM96
VCC_SM93
VCC_SM94
VCC_SM92
VCC_SM91
VCC_SM90
VCC_SM89
VCC_SM88
VCC_SM86
VCC_SM87
VCC_SM85
VCC_SM84
VCC_SM83
VCC_SM81
VCC_SM80
VCC_SM82
VCC_SM79
VCC_SM78
VCC_SM77
VCC_SM74
VCC_SM75
VCC_SM76
VCC_SM73
VCC_SM72
VCC_SM70
VCC_SM71
VCC_SM68
VCC_SM67
VCC_SM69
VCC_SM65
VCC_SM66
VCC_SM64
VCC_SM63
VCC_SM62
VCC_SM61
VCC_SM60
VCC_SM59
VCC_SM58
VCC_SM56
VCC_SM57
VCC_SM55
VCC_SM53
VCC_SM54
VCC_SM52
VCC_SM50
VCC_SM51
VCC_SM49
VCC_SM48
VCC_SM46
VCC_SM47
VCC_SM44
VCC_SM45
VCC_SM43
VCC_SM41
VCC_SM42
VCC_SM40
VCC_SM39
VCC_SM37
VCC_SM38
VCC_SM36
VCC_SM34
VCC_SM35
VCC_SM32
VCC_SM33
VCC_SM30
VCC_SM31
VCC_SM28
VCC_SM29
VCC_SM27
VCC_SM26
VCC_SM25
VCC_SM23
VCC_SM24
VCC_SM22
VCC_SM21
VCC_SM20
VCC_SM18
VCC_SM16
VCC_SM17
VCC_SM15
VCC_SM13
VCC_SM14
VCC_SM11
VCC_SM12
VCC_SM10
VCC_SM9
VCC_SM8
VCC_SM7
VCC_SM6
VCC_SM5
VCC_SM4
VCC_SM3
VCC_SM0
VCC_SM1
VCC_SM2
VCC_110
VCC_109
VCC_108
VCC_105
VCC_106
VCC_107
VCC_104
VCC_103
VCC_101
VCC_100
VCC_102
VCC_98
VCC_99
VCC_96
VCC_97
VCC_95
VCC_94
VCC_93
VCC_92
VCC_91
VCC_90
VCC_88
VCC_89
VCC_87
VCC_86
VCC_85
VCC_83
VCC_84
VCC_82
VCC_80
VCC_81
VCC_79
VCC_78
VCC_76
VCC_77
VCC_74
VCC_73
VCC_75
VCC_72
VCC_71
VCC_70
VCC_69
VCC_68
VCC_67
VCC_66
VCC_65
VCC_64
VCC_62
VCC_63
VCC_61
VCC_60
VCC_59
VCC_57
VCC_58
VCC_55
VCC_56
VCC_53
VCC_54
VCC_52
VCC_50
VCC_51
VCC_49
VCC_46
VCC_47
VCC_48
VCC_44
VCC_45
VCC_43
VCC_42
VCC_41
VCC_40
VCC_39
VCC_38
VCC_37
VCC_36
VCC_34
VCC_35
VCC_33
VCC_32
VCC_31
VCC_30
VCC_28
VCC_29
VCC_25
VCC_26
VCC_27
VCC_24
VCC_23
VCC_21
VCC_20
VCC_22
VCC_13
VCC_14
VCC_12
VCC_16
VCC_15
VCC_17
VCC_18
VCC_19
VCC_11
VCC_10
VCC_9
VCC_8
VCC_7
VCC_4
VCC_5
VCC_6
VCC_2
VCC_3
VCC_0
VCC_1
(6 OF 10)
VCC
VCCAUX_NCTF57
VCCAUX_NCTF56
VCCAUX_NCTF55
VCCAUX_NCTF54
VCCAUX_NCTF53
VCCAUX_NCTF52
VCCAUX_NCTF51
VCCAUX_NCTF50
VCCAUX_NCTF49
VCCAUX_NCTF47 VCCAUX_NCTF48
VCCAUX_NCTF45
VCCAUX_NCTF44
VCCAUX_NCTF46
VCCAUX_NCTF40
VCCAUX_NCTF39
VCCAUX_NCTF37 VCCAUX_NCTF38
VCCAUX_NCTF36
VCCAUX_NCTF34 VCCAUX_NCTF35
VCCAUX_NCTF32 VCCAUX_NCTF33
VCCAUX_NCTF31
VCCAUX_NCTF30
VCCAUX_NCTF29
VCCAUX_NCTF27 VCCAUX_NCTF28
VCCAUX_NCTF26
VCCAUX_NCTF24 VCCAUX_NCTF25
VCCAUX_NCTF22
VCCAUX_NCTF21
VCCAUX_NCTF23
VCCAUX_NCTF42 VCCAUX_NCTF43
VCCAUX_NCTF41
VCCAUX_NCTF19 VCCAUX_NCTF20
VCCAUX_NCTF18
VCCAUX_NCTF17
VCCAUX_NCTF16
VCCAUX_NCTF14 VCCAUX_NCTF15
VCCAUX_NCTF13
VCCAUX_NCTF12
VCCAUX_NCTF11
VCCAUX_NCTF9
VCCAUX_NCTF10
VCCAUX_NCTF8
VCCAUX_NCTF7
VCCAUX_NCTF6
VCCAUX_NCTF5
VCCAUX_NCTF4
VCCAUX_NCTF3
VCCAUX_NCTF1
VCCAUX_NCTF0
VCCAUX_NCTF2
VSS_NCTF12
VSS_NCTF11
VSS_NCTF10
VSS_NCTF9
VSS_NCTF7 VSS_NCTF8
VSS_NCTF5 VSS_NCTF6
VSS_NCTF4
VSS_NCTF2 VSS_NCTF3
VSS_NCTF0 VSS_NCTF1
VCC_NCTF72
VCC_NCTF71
VCC_NCTF70
VCC_NCTF69
VCC_NCTF68
VCC_NCTF67
VCC_NCTF66
VCC_NCTF65
VCC_NCTF64
VCC_NCTF61 VCC_NCTF62 VCC_NCTF63
VCC_NCTF60
VCC_NCTF57 VCC_NCTF58 VCC_NCTF59
VCC_NCTF56
VCC_NCTF55
VCC_NCTF53 VCC_NCTF54
VCC_NCTF52
VCC_NCTF50 VCC_NCTF51
VCC_NCTF49
VCC_NCTF48
VCC_NCTF46 VCC_NCTF47
VCC_NCTF45
VCC_NCTF44
VCC_NCTF43
VCC_NCTF41
VCC_NCTF40
VCC_NCTF42
VCC_NCTF38 VCC_NCTF39
VCC_NCTF36 VCC_NCTF37
VCC_NCTF34 VCC_NCTF35
VCC_NCTF33
VCC_NCTF31 VCC_NCTF32
VCC_NCTF30
VCC_NCTF29
VCC_NCTF28
VCC_NCTF27
VCC_NCTF26
VCC_NCTF25
VCC_NCTF24
VCC_NCTF23
VCC_NCTF22
VCC_NCTF21
VCC_NCTF20
VCC_NCTF18 VCC_NCTF19
VCC_NCTF17
VCC_NCTF16
VCC_NCTF15
VCC_NCTF13 VCC_NCTF14
VCC_NCTF11 VCC_NCTF12
VCC_NCTF10
VCC_NCTF8 VCC_NCTF9
VCC_NCTF7
VCC_NCTF6
VCC_NCTF5
VCC_NCTF4
VCC_NCTF3
VCC_NCTF2
VCC_NCTF0 VCC_NCTF1
(7 OF 10)
NCTF
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Place in cavity
Layout Note:
(Need to better define cavity)
1.05V or 1.5V
Layout Note: Place near pin BA15
Place near pin BA23
Layout Note:
These connections can break without
NCTF balls are Not Critical To Function
impacting part performance.
OMIT
BGA
NB
945GM
20%
0.47uF
CERM-X5R
6.3V
402
10UF
CERM
20%
6.3V
805-1
6.3V
20%
10UF
CERM
805-1
OMIT
BGA
NB
945GM
20%
0.47uF
CERM-X5R
6.3V
402
20%
0.47uF
CERM-X5R
6.3V
402
0.47uF
20%
CERM-X5R
6.3V
402
0.47uF
20%
CERM-X5R
6.3V
402
0.47uF
20%
CERM-X5R
6.3V
402
16 97
??
051-7032
NB Power 1
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
=PPVCORE_S0_NB
PP1V5_S0_NB_FILT_VCCAUX
=PPVCORE_S0_NB
=PP1V8_S3_MEM_NB
NB_VCCSM_LF1
NB_VCCSM_LF2
NB_VCCSM_LF5
NB_VCCSM_LF4
U1200
AA33
W33
P32
M19
L19
N18
M18
L18
P17
N17
M17
N16
M16
N32
L16
M32
L32
J32
AA31
W31
V31
T31
R31
P33
P31
N31
M31
AA30
Y30
W30
V30
U30
T30
R30
N33
P30
N30
M30
L30
AA29
Y29
W29
V29
U29
R29
L33
P29
M29
L29
AB28
AA28
Y28
V28
U28
T28
R28
J33
P28
N28
M28
L28
P27
N27
M27
L27
P26
N26
AA32
L26
N25
M25
L25
P24
N24
M24
AB23
AA23
Y23
Y32
P23
N23
M23
L23
AC22
AB22
Y22
W22
P22
N22
W32
M22
L22
AC21
AA21
W21
N21
M21
L21
AC20
AB20
V32
Y20
W20
P20
N20
M20
L20
AB19
AA19
Y19
N19
AU41
AT41
AR34
AR6
AP6
AN6
AL6
AK6
AJ6
AV1
AJ1
BA30
AY30
AW30
AV30
AU30
AT30
AR30
AP30
AN30
AM41
AM30
AM29
AL29
AK29
AJ29
AH29
AJ28
AH28
AJ27
AH27
AU40
BA26
AY26
AW26
AV26
AU26
AT26
AR26
AJ26
AH26
AJ25
BA34
AH25
AJ24
AH24
BA23
AJ23
BA22
AY22
AW22
AV22
AU22
AY34
AT22
AR22
AP22
AK22
AJ22
AK21
AK20
BA19
AY19
AW19
AW34
AV19
AU19
AT19
AR19
AP19
AK19
AJ19
AJ18
AJ17
AH17
AV34
AJ16
AH16
BA15
AY15
AW15
AV15
AU15
AT15
AR15
AJ15
AU34
AJ14
AJ13
AH13
AK12
AJ12
AH12
AG12
AK11
BA8
AY8
AT34
AW8
AV8
AT8
AR8
AP8
BA6
AY6
AW6
AV6
AT6
U1200
AD27 AC27
AD26
AC26 AB26
AA26
Y26 W26
V26
U26 T26
R26
AB27
AD25 AC25
AB25 AA25
Y25
W25 V25
U25
T25 R25
AA27
AD24
AC24 AB24
AA24
Y24
W24
V24 U24
T24
R24
Y27
AD23
V23
U23 T23
R23
AD22
V22
U22 T22
R22
W27
AD21
V21
U21
T21 R21
AD20
V20
U20
T20 R20
V27
AD19
V19 U19
T19
AD18 AC18
AB18 AA18
Y18
W18
U27
V18
U18
T18
T27
R27
AG27
AF27
AG22 AF22
AG21
AF21 AG20
AF20
AG19 AF19
R19 AG18
AG26
AF18
R18 AG17
AF17
AE17 AD17
AB17
AA17 W17
V17
AF26
T17
R17
AG16 AF16
AE16
AD16 AC16
AB16
AA16 Y16
AG25
W16 V16
U16
T16 R16
AG15
AF15 AE15
AD15
AC15
AF25
AB15
AA15 Y15
W15
V15 U15
T15
R15
AG24
AF24 AG23
AF23
AE27 AE26
AC17
Y17 U17
AE25
AE24 AE23
AE22
AE21 AE20
AE19
AE18
C1611
1
2
C1612
1
2
C1613
1
2
C1614
1
2
C1615
1
2
C1610
1
2
C1621
1
2
C1620
1
2
19 16
6
19 17
19 16
6
19 14
6
Page 17
VTT0 VTT1 VTT2 VTT3 VTT4 VTT5 VTT6 VTT7 VTT8
VTT9 VTT10 VTT11 VTT12 VTT13
VTT15
VTT14
VTT16
VTT18
VTT17
VTT19 VTT20 VTT21 VTT22 VTT23 VTT24 VTT25
VTT27
VTT26
VTT28 VTT29
VTT31
VTT30
VTT32
VTT34
VTT33
VTT35 VTT36 VTT37
VTT39
VTT38
VTT40 VTT41 VTT42 VTT43 VTT44 VTT45
VTT48
VTT46 VTT47
VTT49 VTT50
VTT52
VTT51
VTT53
VTT55
VTT54
VTT57
VTT56
VTT58 VTT59 VTT60 VTT61 VTT62
VTT64
VTT63
VTT65 VTT66 VTT67
VTT69
VTT68
VTT70 VTT71
VTT73
VTT72
VTT74
VTT76
VTT75
VCCSYNC
VCC_TXLVDS0 VCC_TXLVDS1 VCC_TXLVDS2
VCC3G0 VCC3G1
VCC3G3
VCC3G2
VCC3G4
VCC3G6
VCC3G5
VCCA_3GPLL VCCA_3GBG VSSA_3GBG
VCCA_CRTDAC0 VCCA_CRTDAC1 VSSA_CRTDAC
VCCA_DPLLB
VCCA_DPLLA
VCCA_HPLL
VSSA_LVDS
VCCA_LVDS
VCCA_MPLL
VCCA_TVBG VSSA_TVBG
VCCA_TVDACC0 VCCA_TVDACC1 VCCA_TVDACB0 VCCA_TVDACB1 VCCA_TVDACA0 VCCA_TVDACA1
VCCD_HMPLL0 VCCD_HMPLL1
VCCD_LVDS2
VCCD_LVDS0 VCCD_LVDS1
VCCD_TVDAC
VCC_HV1 VCC_HV2
VCC_HV0
VCCD_QTVDAC
VCCAUX19
VCCAUX18
VCCAUX17
VCCAUX16
VCCAUX14 VCCAUX15
VCCAUX13
VCCAUX12
VCCAUX11
VCCAUX10
VCCAUX0 VCCAUX1 VCCAUX2 VCCAUX3 VCCAUX4
VCCAUX6
VCCAUX5
VCCAUX9
VCCAUX8
VCCAUX7
VCCAUX21
VCCAUX20
VCCAUX23 VCCAUX24
VCCAUX22
VCCAUX25 VCCAUX26
VCCAUX29
VCCAUX28
VCCAUX27
VCCAUX30 VCCAUX31
VCCAUX33
VCCAUX32
VCCAUX34 VCCAUX35 VCCAUX36
VCCAUX38
VCCAUX37
VCCAUX39 VCCAUX40
POWER
(8 OF 10)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NB
BGA
945GM
OMIT
CERM-X5R
402
6.3V
0.47uF
20%
402
6.3V
CERM-X5R
20%
0.47uF
402
0.22UF
20%
6.3V X5R
SYNC_DATE=01/05/2006
SYNC_MASTER=M40
NB Power 2
051-7032
??
9717
NB_VTTLF_CAP3
NB_VTTLF_CAP1
PP1V5_S0_NB_VCC3G
GND_NB_VSSA_CRTDAC
PP1V5_S0_NB_VCCA_HPLL
PP3V3_S0_NB_VCCA_TVDACA
=PP1V5_S0_NB_VCCD_HMPLL
PP1V5_S0_NB_VCCD_TVDAC
PP2V5_S0_NB_VCCA_CRTDAC
NB_VTTLF_CAP2
PP2V5_S0_NB_VCCSYNC
=PP2V5_S0_NB_VCC_TXLVDS
=PP1V05_S0_NB_VTT
GND_NB_VSSA_3GBG
=PP2V5_S0_NB_VCCA_3GBG
PP1V5_S0_NB_VCCA_3GPLL
PP1V5_S0_NB_VCCA_DPLLA PP1V5_S0_NB_VCCA_DPLLB
=PP2V5_S0_NB_VCCA_LVDS GND_NB_VSSA_LVDS
PP1V5_S0_NB_VCCA_MPLL
PP3V3_S0_NB_VCCA_TVBG GND_NB_VSSA_TVBG
PP3V3_S0_NB_VCCA_TVDACC
PP3V3_S0_NB_VCCA_TVDACB
=PP1V5_S0_NB_VCCD_LVDS
=PP3V3_S0_NB_VCC_HV
PP1V5_S0_NB_VCCD_QTVDAC
PP1V5_S0_NB_FILT_VCCAUX
U1200
AJ41 AB41
Y41 V41
R41
N41 L41
A23 B23
B25
C30
B30
A30
G41
AC33
F21
E21
B26
C39
AF1
A38
AF2
H20
E19
F19
C20
D20
E20 F20
AK31 AF31
AE30
AD30 AC30
AG29
AF29 AE29
AD29
AC29 AG28
AF28
AE31
AE28
AH22
AJ21 AH21
AJ20
AH20 AH19
P19
P16
AH15
AC31
P15 AH14
AG14
AF14 AE14
Y14
AF13 AE13
AF12
AE12
AL30
AD12
AK30
AJ30 AH30
AG30 AF30
AH1
AH2
A28
B28
C28
H19
D21
H22
H41
G21
B39
G20
AC14
AB14
AD13 AC13
AB13 AA13
Y13
W13 V13
U13
T13 R13
W14
N13
M13 L13
AB12 AA12
Y12
W12 V12
U12
T12
V14
R12
P12
N12 M12
L12 R11
P11
N11 M11
R10
T14
P10 N10
M10
P9 N9
M9 R8
P8
N8 M8
R14
P7
N7 M7
R6
P6 M6
A6 R5
P5
N5
P14
M5
P4
N4 M4
R3
P3 N3
M3 R2
P2
N14
M2 D2
AB1
R1 P1
N1
M1
M14
L14
C1711
1
2
C1713
1
2
C1712
1
2
19
19
19
19
19
6
19
19
19
19
6
19
6
19
19
6
19
19
19
19
6
19
19
19
19
19
19
19
6
19
6
19
19 16
Page 18
VSS_1
VSS_0
VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7
VSS_9
VSS_8
VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17
VSS_19
VSS_18
VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26
VSS_28
VSS_27
VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35
VSS_37
VSS_36
VSS_39
VSS_38
VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47
VSS_49
VSS_48
VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55
VSS_57
VSS_56
VSS_59
VSS_58
VSS_61
VSS_60
VSS_64
VSS_63
VSS_62
VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71
VSS_73
VSS_72
VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79
VSS_82
VSS_80 VSS_81
VSS_84
VSS_83
VSS_85
VSS_87
VSS_86
VSS_89
VSS_88
VSS_91
VSS_90
VSS_92 VSS_93 VSS_94
VSS_96
VSS_95
VSS_97 VSS_98
VSS_99 VSS_100 VSS_101 VSS_102 VSS_103 VSS_104 VSS_105 VSS_106 VSS_107 VSS_108 VSS_109 VSS_110 VSS_111 VSS_112
VSS_114
VSS_113
VSS_115
VSS_117
VSS_116
VSS_118 VSS_119 VSS_120 VSS_121 VSS_122 VSS_123 VSS_124 VSS_125
VSS_127
VSS_126
VSS_128 VSS_129 VSS_130 VSS_131 VSS_132 VSS_133 VSS_134 VSS_135
VSS_137
VSS_136
VSS_138 VSS_139 VSS_140 VSS_141
VSS_143
VSS_142
VSS_144 VSS_145 VSS_146 VSS_147 VSS_148 VSS_149 VSS_150 VSS_151 VSS_152 VSS_153 VSS_154 VSS_155 VSS_156
VSS_158
VSS_157
VSS_159 VSS_160 VSS_161 VSS_162
VSS_164
VSS_163
VSS_165 VSS_166 VSS_167 VSS_168 VSS_169 VSS_170
VSS_172
VSS_171
VSS_173 VSS_174 VSS_175 VSS_176 VSS_177 VSS_178 VSS_179
VSS
(9 OF 10)
VSS_272
VSS_271
VSS_269 VSS_270
VSS_268
VSS_266 VSS_267
VSS_265
VSS_264
VSS_263
VSS_261 VSS_262
VSS_260
VSS_259
VSS_258
VSS_256 VSS_257
VSS_255
VSS_254
VSS_253
VSS_251 VSS_252
VSS_250
VSS_248 VSS_249
VSS_247
VSS_246
VSS_245
VSS_243 VSS_244
VSS_242
VSS_241
VSS_240
VSS_238 VSS_239
VSS_237
VSS_236
VSS_235
VSS_233 VSS_234
VSS_232
VSS_231
VSS_230
VSS_228 VSS_229
VSS_227
VSS_225 VSS_226
VSS_224
VSS_223
VSS_222
VSS_220 VSS_221
VSS_219
VSS_218
VSS_217
VSS_215 VSS_216
VSS_214
VSS_213
VSS_212
VSS_210 VSS_211
VSS_209
VSS_207 VSS_208
VSS_205 VSS_206
VSS_204
VSS_202 VSS_203
VSS_201
VSS_200
VSS_199
VSS_197 VSS_198
VSS_196
VSS_195
VSS_194
VSS_192 VSS_193
VSS_191
VSS_190
VSS_189
VSS_187 VSS_188
VSS_186
VSS_184 VSS_185
VSS_183
VSS_182
VSS_180 VSS_181
VSS_273 VSS_274
VSS_276
VSS_275
VSS_277
VSS_279
VSS_278
VSS_281
VSS_280
VSS_282 VSS_283 VSS_284
VSS_286
VSS_285
VSS_287 VSS_288 VSS_289
VSS_291
VSS_290
VSS_293
VSS_292
VSS_294
VSS_296
VSS_295
VSS_297
VSS_299
VSS_298
VSS_301 VSS_302
VSS_300
VSS_304
VSS_303
VSS_305 VSS_306 VSS_307
VSS_309
VSS_308
VSS_311
VSS_310
VSS_312 VSS_313 VSS_314 VSS_315
VSS_317
VSS_316
VSS_318 VSS_319 VSS_320
VSS_322
VSS_321
VSS_323 VSS_324 VSS_325
VSS_327
VSS_326
VSS_328 VSS_329 VSS_330
VSS_332
VSS_331
VSS_334
VSS_333
VSS_335
VSS_337
VSS_336
VSS_338 VSS_339 VSS_340
VSS_342 VSS_343
VSS_341
VSS_345
VSS_344
VSS_346 VSS_347 VSS_348
VSS_350
VSS_349
VSS_352
VSS_351
VSS_353 VSS_354 VSS_355 VSS_356 VSS_357 VSS_358 VSS_359 VSS_360
VSS
(10 OF 10)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NB
945GM
BGA
OMIT
NB
945GM
BGA
OMIT
SYNC_DATE=01/05/2006
SYNC_MASTER=M1
NB Grounds
051-7032
??
9718
U1200
AC41
AA41
AN40
AE34
AC34 C34
AW33
AV33 AR33
AE33
AB33 Y33
V33
AK40
T33 R33
M33 H33
G33
F33 D33
B33
AH32 AG32
AJ40
AF32
AE32 AC32
AB32 G32
B32
AY31 AV31
AN31
AJ31
AH40
AG31
AB31
Y31 AB30
E30 AT29
AN29
AB29 T29
N29
AG40
K29 G29
E29
C29 B29
A29 BA28
AW28
AU28 AP28
AF40
AM28
AD28 AC28
W28
J28 E28
AP27 AM27
AK27
J27
AE40
G27
F27
C27 B27
AN26
M26 K26
F26 D26
AK25
B40
P25 K25
H25
E25 D25
A25
BA24 AU24
AL24 AW23
AY39 AW39
W41
AV39
AR39 AN39
AJ39
AC39 AB39
AA39
Y39
W39
V39
T41
T39
R39
P39 N39
M39
L39 J39
H39 G39
F39
P41
D39 AT38
AM38
AH38 AG38
AF38
AE38
C38
AK37 AH37
M41
AB37
AA37
Y37
W37
V37
T37
R37
P37
N37
M37
J41
L37
J37
H37
G37
F37
D37 AY36
AW36
AN36 AH36
F41
AG36 AF36
AE36
AC36
C36
B36
BA35 AV35
AR35
AH35
AV40
AB35
AA35
Y35
W35
V35
T35
R35
P35
N35
M35
AP40
L35
J35
H35
G35
F35
D35 AN34
AK34
AG34
AF34
U1200
AT23 AN23
AM23
AH23 AC23
W23 K23
J23
F23 C23
AA22
K22 G22
F22
E22 D22
A22 BA21
AV21
AR21 AN21
AL21
AB21
Y21
P21
K21
J21
H21
C21
AW20
AR20 AM20
AA20
K20
B20
A20
AN19 AC19
W19
K19
G19
C19 AH18
P18
H18
D18
A18
AY17 AR17
AP17 AM17
AK17
AV16 AN16
AL16
J16
F16
C16
AN15 AM15
AK15
N15
M15
L15
B15
A15
BA14 AT14
AK14
AD14 AA14
U14
K14
H14
E14 AV13
AR13
AN13 AM13
AL13
AG13
P13
F13
D13
B13
AY12 AC12
K12
H12
E12
AD11
AA11
Y11
J11 D11
B11
AV10 AP10
AL10 AJ10
AG10
AC10 W10
U10
BA9 AW9
AR9
AH9 AB9
Y9 R9
G9
E9 A9
AG8
AD8 AA8
U8
K8 C8
BA7 AV7
AP7
AL7 AJ7
AH7
AF7 AC7
R7
G7 D7
AG6 AD6
AB6
Y6 U6
N6
K6 H6
B6
AV5 AF5
AD5 AY4
AR4
AP4 AL4
AJ4
Y4 U4
R4
J4 F4
C4 AY3
AW3
AV3 AL3
AH3
AG3 AF3
AD3
AC3 AA3
G3 AT2
AR2
AP2 AK2
AJ2
AD2 AB2
Y2
U2 T2
N2 J2
H2
F2 C2
AL1
Page 19
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
NR/FB
IN
EN
OUT
GND
NC
NC
NOISE
GND
VOUT
CONT
VIN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
Layout Note: These 2 caps should be within 6.35 mm of NB edge
(MCH LVDS DATA/CLK TX 2.5V PWR)
(MCH LVDS DIGITAL 1.5V PWR)
INTEGRATED GFX (PG. 333)
Power Interface
MCH DISPLAY PLL POWER LDO
GMCH VCCD_LVDS BYPASS
MCH VCCSYNC BYPASS (MCH H/V SYNC 2.5V PWR)
FILTERING REQUIRED FOR
Layout Note: This 0.1uF cap should
GMCH VCCTX_LVDS BYPASS
945 EDS: 5 mOhm, 1nH (1210?)
Layout Note: Place on the edge
MCH VCCA_CRTDAC BYPASS
945 EDS: 1210?
be within 5 mm of NB edge
MCH VCCA_LVDS FILTER
(MCH LVDS ANALOG 2.5V PWR)
Layout Note: Route to caps, then GND
(MCH CRTDAC ANALOG 2.5V PWR)
Layout Note: Route to caps, then GND
MCH VCCA_DPLLA FILTER
(MCH DISPLAY A PLL 1.5V PWR)
(MCH DISPLAY B PLL 1.5V PWR)
GMCH VCCA_DPLL_B FILTER
(MCH TVDAC DIGITAL QUIET 1.5V PWR)
(MCH TVDAC DEDICATED PWR 1.5V)
GMCH VCCD_TVDAC FILTER
GMCH VCCD_QTVDAC FILTER
MCH VCCA_TVDACC FILTER (MCH TV OUT CHANNEL A 3.3V PWR)
(MCH TV OUT CHANNEL B 3.3V PWR)
MCH VCCA_TVDACC FILTER
within 6.35 mm of NB edge
These 8 caps should be
Layout Note:
Layout Note: Route to caps, then GND
(MCH TV DAC BAND GAP 3.3V PWR)
MCH VCCA_TVBG FILTER
MCH VCCA_TVDACC FILTER (MCH TV OUT CHANNEL C 3.3V PWR)
WAS A 330UF ELEC - CHECK WE CAN REMOVE
WAS A 330UF ELEC - CHECK WE CAN REMOVE
Layout Note: 3GPLL 10uF cap should be placed in cavity
Layout Note:
close to MCH
Place L and C
1uH, 20%
be within 5 mm of NB edge
be close to MCH
Layout Note: Place in cavity
10uF caps should
on opposite side.
Layout Note: Route to caps, then GND
Should be 1%
These 4 0.1uF caps should
Layout Note:
These are the power signals that leave the NB "block"
Layout Note:
Layout Note: PLACE CAPS NEAR NB EDGE ON THESE 2 RAILS
220UF
SMB2
POLY
2.5V
20%
X5R
6.3V
402
0.22uF
20%
2.2UF
10%
603
CERM1
6.3V
CERM
6.3V
20%
4.7uF
603
0.1uF
10V CERM 402
20%
10UF
805-1
6.3V
20%
CERM
1/16W MF-LF
402
1%
0.51
0805
1.0UH-220MA-0.12-OHM
20%
402
CERM
10V
0.1uF
10V CERM 402
20%
0.1uF10UF
805-1
6.3V
20%
CERM
0.1uF
20%
402
CERM
10V
1K
402
5%
MF-LF
1/16W
1K
5% 1/16W MF-LF 402
1K
5% 1/16W
402
MF-LF
1K
1/16W MF-LF
402
5%
1210
91NH
16V
22000pF-1000mA
NFM18
0.1uF
CERM
10V
20%
402
22000pF-1000mA
NFM18
16V
CERM
20%
402
10V
0.1uF
180-OHM-1.5A
0603
1/16W
402
MF-LF
5%
1
402
CERM
1UF
10%
6.3V
1/16W
5%
1
402
MF-LF
805-1
10UF
6.3V CERM
20%
CERM 402
1UF
10%
6.3V
16V CERM
10%
402
0.01uF
SOT23-5
TPS73115
402
CERM
10%
1UF
6.3V
SOT-363
BAT54DW
1%
10
1/16W
402
MF-LF
0603
180-OHM-1.5A
22000pF-1000mA
16V
NFM18
0.1uF
10V
20%
402
CERM
CERM 402
16V
10%
0.01uF0.1uF
20%
402
CERM
10V
I243
22000pF-1000mA
NFM18
16V
20%
CERM
10V
0.1uF
402
NFM18
22000pF-1000mA
16V
20%
402
CERM
10V
0.1uF
16V
22000pF-1000mA
NFM18
0.1uF
10V
20%
402
CERM
SOT-363
BAT54DW
22000pF-1000mA
16V
NFM18
20%
0.1uF
10V
CERM
402
10UF
6.3V CERM 805-1
20%
180-OHM-1.5A
0603
MF-LF
10
402
1/16W
1%
402
1UF
10%
6.3V CERM
402
CERM
16V
10%
0.01uF
SOT23-5-LF
MM157
CERM 402
1UF
10%
6.3V
0.1uF
402
CERM
10V
20%
10UF
805-1
6.3V CERM
20%
0.1uF
20%
402
CERM
10V
603
20%
CERM
4.7uF
6.3V
402
10V
20%
CERM
0.1uF
I276
0.1uF
20% 10V CERM 402
POLY
2.5V
20%
220UF
SMB2
20%
POLY
2.5V
220UF
SMB2
180-OHM-1.5A
0603
10UF
20%
6.3V X5R 603 603
X5R
6.3V
20%
10UF
180-OHM-1.5A
0603
10UF
20% X5R
6.3V 603
603
X5R
6.3V
20%
10UF
0603
FERR-120-OHM-0.2A
0.22uF
20%
6.3V X5R 402
10UF
805-1
6.3V
20%
CERM
10UF
805-1
6.3V
20%
CERM
0.22uF
20%
6.3V X5R 402402
6.3V
0.22uF
20%
X5R
1UF
CERM
6.3V
402
10%
0.1uF
20%
CERM
10V
402
CERM 402
20%
0.1uF
10V X5R 805
20%
6.3V
22uF
0603
FERR-120-OHM-0.2A
20%
6.3V
805
X5R
22uF
805-1
6.3V
20%
CERM
10UF10UF
805-1
6.3V
20%
CERM
NB (GM) Decoupling
SYNC_MASTER=(MASTER)
051-7032
??
9719
SYNC_DATE=(MASTER)
=PP1V5_S0_NB_VCCD_LVDS
=PP1V5_S0_NB_TVDAC
VOLTAGE=1.5V MIN_NECK_WIDTH=0.35MM
MIN_LINE_WIDTH=1.0 mm
PP1V5_S0_DPLL
PP1V5_S0_NB_QTVDAC
MIN_NECK_WIDTH=0.35MM
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=1.5V
PP1V5_S0_NB_FILT_VCCAUX
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.6 MM
VOLTAGE=1.5V
=PP1V5_S0_NB =PP1V5_S0_NB_PCIE
=PP1V5_S0_NB_3GPLL
=PP1V05_S0_NB_VTT
GND_NB_VSSA_3GBG
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=1.5V
PP1V5_S0_NB_3GPLL_F
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_3GPLL
MIN_NECK_WIDTH=0.2 MM
=PP1V5_S0_NB_3GPLL
=PP1V05_S0_NB_VTT
=PP1V5_S0_NB_PLL
=PP1V05_S0_FSB_NB
=PP2V5_S0_NB_VCCA_3GBG
=PP1V5_S0_NB_VCCAUX
=PP3V3_S0_NB_VCC_HV
VOLTAGE=3.3V
PP3V3_S0_NB_VCCA_TVDACB
MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=0.35MM
VOLTAGE=3.3V MIN_LINE_WIDTH=1.0 mm
PP3V3_S0_NB_VCCA_TVDACC
MIN_NECK_WIDTH=0.35MM
VOLTAGE=3.3V MIN_LINE_WIDTH=1.0 mm
PP3V3_S0_NB_VCCA_TVBG
MIN_NECK_WIDTH=0.35MM
GND_NB_VSSA_TVBG
VOLTAGE=3.3V MIN_LINE_WIDTH=1.0 mm
MIN_NECK_WIDTH=0.35MM
PP3V3_S0_NB_VCCA_TVDACA
=PP1V5_S0_NB
MIN_NECK_WIDTH=0.35MM
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=3.3V
PP3V3_S0_NB_TVDAC_FOLLOW
MM1573DN_NR
=PP5V_S0_NB_TVDAC
MIN_LINE_WIDTH=1.0 mm
PP1V5_S0_NB_VCCA_DPLLB
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.35MM
MIN_NECK_WIDTH=0.35MM
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCCA_DPLLA
=PP2V5_S0_NB_CRTDAC
=PP2V5_S0_NB_VCCA_LVDS
GND_NB_VSSA_LVDS
=PPVCORE_S0_NB
MEM_VREF_NB_0
=PP1V8_S3_MEM_NB
MEM_VREF_NB_1
=PP2V5_S0_NB_VCC_TXLVDS
=PP5V_S0_NB_TVDAC
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=1.5V
PP1V5_S0_NB_VCC3G
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.35MM
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=2.5V
PP2V5_S0_NB_CRTDAC_FOLLOW
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=1.0 mm
PP1V5_S0_NB_VCCA_HPLL
=PP3V3_S0_NB_VCC_HV
=PP3V3_S0_NB
=PP2V5_S0_NB_VCCA_LVDS
=PP2V5_S0_NB_VCCA_3GBG
=PP1V8_S3_MEM_NB
=PP1V5_S0_NB_PLL =PP1V5_S0_NB_TVDAC =PP1V5_S0_NB_VCCD_HMPLL =PP1V5_S0_NB_VCCD_LVDS =PP1V5_S0_NB_VCCAUX
PP2V5_S0_NB_VCCSYNC
=PP1V5_S0_NB_VCCAUX
=PP2V5_S0_NB_VCCSYNC
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.5V MIN_LINE_WIDTH=1.0 mm
PP1V5_S0_NB_VCCA_MPLL
VOLTAGE=3.3V
MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM
PP3V3_S0_NB_TVDAC_F
TPS73115_NR
=PP2V5_S0_NB_VCC_TXLVDS
=PP2V5_S0_NB_DISP_PLL
=PP2V5_S0_NB_VCCSYNC
=PPVCORE_S0_NB
MIN_LINE_WIDTH=1.0 mm MIN_NECK_WIDTH=0.35MM
PP3V3_S0_NB_TVDAC
VOLTAGE=3.3V
PP1V5_S0_NB_VCCD_QTVDAC
MIN_NECK_WIDTH=0.35MM
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.35MM
MIN_LINE_WIDTH=1.0 mm
PP1V5_S0_NB_TVDAC
VOLTAGE=1.5V
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=1.5V
MIN_NECK_WIDTH=0.35MM
PP1V5_S0_NB_VCCD_TVDAC
MIN_NECK_WIDTH=0.35MM
MIN_LINE_WIDTH=1.0 mm
VOLTAGE=2.5V
PP2V5_S0_NB_CRTDAC_F
MIN_NECK_WIDTH=0.35MM
PP2V5_S0_NB_VCCA_CRTDAC
VOLTAGE=2.5V MIN_LINE_WIDTH=1.0 mm
GND_NB_VSSA_CRTDAC
=PPVCORE_S0_NB
L1934
1 2
C1907
1
2
C1972
1
2
C1971
1
2
C1906
1
2
C1905
1
2
C1904
1
2
C1937
1
2
C1935
1
2
C1934
1
2
L1936
1 2
C1936
1
2
C1903
1
2
C1902
1
2
C1970
1
2
C1967
1
2
C1966
1
2
C1965
1
2
C1976
1
2
C1975
1
2
R1975
1 2
L1975
1 2
C1918
1
2
C1915
1
2
C1914
1
2
C1916
1
2
R1980
1 2
R1981
1
2
R1983
1
2
R1982
1 2
L1970
1 2
C1921
2
1 3
C1920
1
2
C1923
2
1 3
C1922
1
2
L1922
1 2
R1950
1 2
C1953
1
2
R1951
1 2
C1952
1
2
C1954
1
2
C1951
1
2
U1900
3
2
1
4
5
C1950
1
2
D1986
16
5
R1985
1 2
L1985
1 2
C1986
2
1 3
C1985
1
2
C1981
1
2
C1980
1
2
C1994
2
1 3
C1993
1
2
C1996
2
1 3
C1995
1
2
C1998
2
1 3
C1997
1
2
D1986
43
2
C1992
2
1 3
C1991
1
2
C1990
1
2
L1990
1 2
R1990
1 2
C1942
1
2
C1941
1
2
U1901
3
2
4
1 5
C1940
1
2
C1911
1
2
C1910
1
2
C1913
1
2
C1912
1
2
C1917
1
2
C1962
1
2
C1964
1
2
C1963
1
2
L1910
1 2
C1926
1
2
C1927
1
2
L1923
1 2
C1924
1
2
C1987
1
2
19 17
6
19
6
17 16
19
6
13
6
19
6
19 17
6
17
17
19
6
19 17
6
19
6
12
6 5
19 17
6
19
6
19 17
6
17
17
17
17
17
19
6
19
6
17
17
6
19 17
6
17
19 16
6
14
5
19 16 14
6
14
5
19 17
6
19
6
17
17
19 17
6
20 14
6
19 17
6
19 17
6
19 16 14
6
19
6
19
6
17
6
19 17
6
19
6
17
19
6
19
6
17
19 17
6
6
19
6
19 16
6
17
17
17
17
19 16
6
Page 20
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PCIe Backward Interop. Mode
VCC Select
Reversal
DMI Lane
High = Reversed
Low = Normal
High = 1.5V
Low = 1.05V
Internal pull-down
Internal pull-down
Internal pull-down
945 External Design Spec says reserved
High = Both active
Low = Only SDVO or PCIe x1
ODT
FSB Dynamic
RESERVED
Low = Disabled
High = Enabled
RESERVED
Internal pull-up
RESERVED
00 = Partial Clock Gating Disable 01 = XOR Mode Enabled 10 = All-Z Mode Enabled 11 = Normal Operation
Internal pull-up
Low = Reversed
RESERVED
CPU Strap
RESERVED
PCIE Graphics
High = Normal
Low = RESERVED
High = DMIx4
Low = DMIx2
NB_CFG<20>
NB_CFG<19>
NB_CFG<9>
NB_CFG<8>
NB_CFG<18>
NB_CFG<17>
NB_CFG<6>
NB_CFG<16>
NB_CFG<15>
NB_CFG<5>
NB_CFG<14>
NB_CFG<13:12>
RESERVED
NB_CFG<3>
NB_CFG<4>
Lane Reversal
PROBABLY NOT NEEDED
PROBABLY NOT NEEDED
DMI x2 Select
Internal pull-up
RESERVED
NB_CFG<7>
High = Mobile CPU
NB_CFG<10>
NB_CFG<11>
RESERVED
RESERVED
Internal pull-up
Internal pull-ups
NBCFG_DMI_X2
MF-LF
1/16W
2.2K
5%
402
NBCFG_DYN_ODT_DISABLE
402
MF-LF
1/16W
5%
2.2K
MF-LF
NBCFG_VCC_1V5
2.2K
5% 1/16W
402
NBCFG_DMI_REVERSE
2.2K
5% 1/16W MF-LF 402
2.2K
5% 1/16W MF-LF 402
NBCFG_SDVO_AND_PCIE
NO STUFF
2.2K
5% 1/16W MF-LF 402
NBCFG_PEG_REVERSE
2.2K
5% 1/16W MF-LF 402
SYNC_DATE=01/05/2006
SYNC_MASTER=M1
NB Config Straps
051-7032
??
9720
NB_CFG<9>
NB_CFG<7>
NB_CFG<5>
NB_CFG<16>
NB_CFG<20>
NB_CFG<19>
NB_CFG<18>
=PP3V3_S0_NB
=PP3V3_S0_NB
=PP3V3_S0_NB
R2075
1
2
R2077
1
2
R2079
1
2
R2085
1
2
R2058
1
2
R2059
1
2
R2060
1
2
14
14
14
14
14
14
14
20 19 14
6
20 19 14
6
20 19 14
6
Page 21
IO
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
IN
IN
IN
IN
IN
IO
IO IO
IO
IN
IO
DDACK*
SATARBIASN SATARBIASP
SATA_CLKN SATA_CLKP
SATA_2TXP
SATA_2TXN
SATA_2RXN SATA_2RXP
SATA_0TXP
SATA_0TXN
SATA_0RXP
SATA_0RXN
SATALED*
ACZ_SDOUT
ACZ_SDIN1 ACZ_SDIN2
ACZ_SDIN0
ACZ_SYNC
ACZ_BIT_CLK
LAN_TXD2
LAN_TXD0 LAN_TXD1
LAN_RXD1 LAN_RXD2
LAN_RSTSYNC
LAN_RXD0
LAN_CLK
EE_SHCLK
EE_CS
INTVRMEN
INTRUDER*
RTCRST*
RTCX2
RTCX1
THRMTRIP*
STPCLK*
NMI
SMI*
RCIN*
INTR
INIT*
INIT3_3V*
IGNNE*
GPIO49/CPUPWRGD
FERR*
TP1/DPRSTP*
TP2/DPSLP*
A20M*
CPUSPL*
A20GATE
LFRAME*
LDRQ1*/GPIO23
LDRQ0*
LAD3
LAD2
LAD0 LAD1
EE_DOUT EE_DIN
ACZ_RST*
DIOR*
IDEIRQ
DIOW*
IORDY DDREQ
DD0 DD1
DD3
DD2
DD5
DD4
DD6 DD7 DD8
DD11
DD9
DD10
DD12 DD13 DD14 DD15
DA0 DA1 DA2
DCS3*
DCS1*
AC-97/
AZALIA
RTC
LPC
LAN
CPU
IDE
SATA
(1 OF 6)
OUT
OUT
OUT
IN
OUT
IN IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
OUT
IN IN
IN
OUT
OUT
OUT
OUT
OUT
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE: EE_CS HAS INTERNAL PD, ONLY ENABLED WHEN LAN_RST#=L
(INT PU)
(INT PU)
(WEAK INT PD)
NOTE: R2108=56 IN CV.
BOM CONSOLIDATION
CHANGED TO 54.9 FOR
NOTE: R2110=56 IN CV.
NOTE: PULLED UP PER INTEL
NOTE: LDRQ<0-1># HAVE INTERNAL 20K PU
INTEL CONFIRMS OK TO LEAVE PINS AS NC
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
INTO RESET STATE TO SAVE PWR.
NOTE: POR IS SMC WILL PUT LAN INT’F
NOTE: KEYBOARD CONTROLLER RESET CPU
NOTE: RISING-EDGE TRIGGERED AT CPU
BOM CONSOLIDATION
< 2 IN OF SB
LAYOUT NOTE: R2107 TO BE
CHANGED TO 54.9 FOR
LAYOUT NOTE: R2108 TO BE < 2 IN OF R2107 W/O STUB
(DSTROBE)
20K PD
20K PD
20K PD
(STOP)
(HSTROBE)
NOTE: DD<7> HAS INTERNAL 11.5K PD
NOTE: ENABLE INTERNAL 1.05V SUSPEND REG
INTERNAL 20K PD ONLY ENABLED IN S3COLD
INTERNAL 20K PD
NONE
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
INTERNAL 20K PD ENABLED WHEN
INTERNAL 20K PD
INTERNAL 20K PD ENABLED DURING RESET AND WHEN
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
- BOTH FUNCTION 2 & 3 OF DEVICE 30 ARE DISABLED
- LSO BIT IN AC’97 GLOBAL CONTROL REG = 1; OR
AC ’07
INTERNAL 20K PD
INTERNAL 20K PD ENABLED WHEN
ACZ_SDIN[0-2]
ACZ_RST#
ACZ_BIT_CLK
ACZ_SYNC
ACZ_SDOUT
INTEL HIGH DEFINITION AUDIO
NOTE: LAD<0-3> HAVE INTERNAL 20K PU
NOTE: DDREQ HAS INTERNAL 11.5K PD
LAYOUT NOTE: PLACE R2101 & R2194 WHERE ACCESSIBLE
NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S
(WEAK INT PU)
NOSTUFF
1/16W
MF-LF
0
5%
402
NOSTUFF
402
2.2K
5% 1/16W MF-LF
MF-LF
5%
39
402
1/16W
39 39
39
402
10K
5% 1/16W MF-LF
SB
ICH7-M
OMIT
402
10K
5% 1/16W MF-LF
332K
402
1%
1/16W
MF-LF
24.9
MF-LF 1/16W
1%
402
402
MF-LF 1/16W
1%
54.9
MF-LF 1/16W
402
54.9
1%
??
21 97
051-7032
SYNC_MASTER=M38
SYNC_DATE=01/05/2006
SB: 1 OF 4
IDE_PDD<3>
IDE_PDD<2>
TP_SB_XOR_V3
TP_SB_XOR_W3
TP_SB_XOR_T5
TP_SB_XOR_V4
TP_SB_XOR_U5
TP_SB_XOR_U3
PP3V3_S5_SB_RTC
ACZ_RST_L
ACZ_BITCLK
SB_RTC_RST_L
SB_RTC_X2
LPC_FRAME_L
TP_SB_GPIO23
TP_SB_DRQ0_L
LPC_AD<3>
LPC_AD<2>
LPC_AD<1>
LPC_AD<0>
=PP3V3_S0_SB_GPIO
=PP3V3_S0_SB_GPIO
IDE_PDD<6>
ACZ_SDATAOUT
PM_THRMTRIP_L
=PP1V05_S0_SB_CPU_IO
SMC_RCIN_L
ACZ_SYNC
IDE_PDCS1_L IDE_PDCS3_L
IDE_PDA<2>
IDE_PDA<1>
IDE_PDA<0>
IDE_PDD<15>
IDE_PDD<14>
IDE_PDD<13>
IDE_PDD<12>
IDE_PDD<10>
IDE_PDD<9>
IDE_PDD<11>
IDE_PDD<8>
IDE_PDD<7>
IDE_PDD<4> IDE_PDD<5>
IDE_PDD<1>
IDE_PDD<0>
IDE_PDDREQ
IDE_PDIORDY
IDE_PDIOW_L
IDE_IRQ14
IDE_PDIOR_L
SB_ACZ_RST_L
TP_CPU_CPUSLP_L
CPU_A20M_L
CPU_DPSLP_L
CPU_DPRSTP_L
CPU_PWRGD
CPU_IGNNE_L
FWH_INIT_L CPU_INIT_L
CPU_INTR
CPU_SMI_L
CPU_NMI
CPU_STPCLK_L
CPU_THERMTRIP_R
SB_RTC_X1
SB_SM_INTRUDER_L
SB_ACZ_BITCLK SB_ACZ_SYNC
ACZ_SDATAIN<0>
TP_SB_ACZ_SDIN2
TP_SB_ACZ_SDIN1
SB_ACZ_SDATAOUT
TP_SB_SATALED_L
SATA_A_D2R_N SATA_A_D2R_P SATA_A_R2D_C_N SATA_A_R2D_C_P
SATA_C_D2R_N
SATA_C_R2D_C_N SATA_C_R2D_C_P
SB_CLK100M_SATA_P
SB_CLK100M_SATA_N
SATA_RBIAS_P
SATA_RBIAS_N
IDE_PDDACK_L
SATA_C_D2R_P
CPU_RCIN_L
SB_A20GATE
CPU_FERR_L
=PP1V05_S0_SB_CPU_IO
SB_INTVRMEN
TP_SB_XOR_W1 TP_SB_XOR_Y1 TP_SB_XOR_Y2
TP_SB_XOR_U7 TP_SB_XOR_V6 TP_SB_XOR_V7
R2105
1
2
R2107
1 2
R2108
1
2
R2110
1 2
R2100
1 2
R2101
1 2
R2195
1 2
R2198
1 2
R2197
1 2
R2196
1 2
R2199
1
2
U2100
AE22 AH28
U1
R5 T2 T3 T1
T4
R6
AG27
AH17 AE17 AF17
AE16 AD16
AB15 AE14
AB13 AC14 AF14 AH13 AH14 AC15
AG13 AF13 AD14 AC13 AD12 AC12 AE12 AF12
AF16
AE15
AF15 AH15
W1
W3
Y2
Y1
AG26
AG24
AH16
AG22
AF22
AG21
AF25
Y5 W4
AG16
AA6 AB5 AC4 Y6
V3
U3
U5 V4 T5
U7 V6 V7
AC3 AA5
AB3
AH24
AG23
AA3
AB1 AB2
AF3 AE3 AG2 AH2
AF7 AE7 AG6 AH6
AF1 AE1
AF18
AH10 AG10
AF23
AH22
AF26
AF24 AH25
R2194
1
2
38
38
26 25 24
5
68
68
26
26
67
60 58
67 60 58
67 60 58
67 60 58
67 60 58
27 23 21
6
27 23 21
6
38
68
59 14
7
25 24 21
6
58 68
38
38
38
38
38
38
38
38
38
38
38
5
38
38
38
38
38
38
38
38
38
5
38
38
38
5
7 5
7
75
7
7
7 5
60 59
7 5
7 5
7 5
7 5
7 5
26
26
68
38
38
38
38
38
38
38
34
5
34
5
38
38
38
38
7
25 24 21
6
Page 22
IN
IO
IO
IO
IO
IO
IO
IN
IN
IN
OUT
IN
IN
IN IN
IN IN
IN
IN
IN
IN
IN
IN
OUT OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
IO
IO IO
IN
IO IO
IO
IO IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IN
OUT
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
DMI_ZCOMP
DMI_CLKP
DMI_IRCOMP
USBRBIAS*
USBRBIAS
DMI0RXN DMI0RXP DMI0TXN DMI0TXP
DMI2TXN DMI2TXP
DMI3RXN
DMI3TXP
DMI3TXN
DMI3RXP
USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P
USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P
USBP4N
OC0* OC1* OC2* OC3* OC4*
OC6*/GPIO30
OC5*/GPIO29
SPI_CLK SPI_CS*
SPI_MOSI SPI_MISO
SPI_ARB
DMI_CLKN
DMI2RXP
DMI2RXN
DMI1TXP
DMI1TXN
DMI1RXN DMI1RXP
PERN1 PERP1 PETN1 PETP1
PERN2 PERP2 PETN2 PETP2
PERN3 PERP3 PETN3 PETP3
PERN4 PERP4 PETN4 PETP4
PERN5 PERP5 PETN5 PETP5
PERN6 PERP6 PETN6 PETP6
OC7*/GPIO31
PCI-EXP
(3 OF 6)
DMI
SPI
USB
REQ4*/GPIO22
REQ0*
MCH_SYNC*
RSVD8
RSVD7
RSVD6
RSVD5
RSVD4
GPIO5/PIRQH*
GPIO4/PIRQG*
GPIO3/PIRQF*
GPIO2/PIRQE*
GPIO17/GNT5*
GPIO1/REQ5*
GNT4*/GPIO48
C/BE0* C/BE1*
DEVSEL*
PERR*
STOP*
PCIRST*
PME*
PLTRST*
TRDY*
FRAME*
IRDY*
PCICLK
PAR
PLOCK*
SERR*
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
C/BE2* C/BE3*
GNT0* REQ1* GNT1* REQ2* GNT2* REQ3* GNT3*
PIRQA* PIRQB* PIRQC* PIRQD*
RSVD0 RSVD1 RSVD2 RSVD3
MISC
INT I/F
PCI
(2 OF 6)
IO
IO IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO IO
IO
IO IO
IO IO
IO
IO IO
IO
IO
IN
IO
IO
IO
IO
OUT
IO
IO
IO
IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
AND PWROK=H
ENABLED ONLY WHEN PCIRST#=0
GNT[0-3]# HAVE INT 20K PU
NOTE: R2210 WAS PD ON PIN A14 = FWH_TBL_L
BOM NOTE FOR PD ON PCI_GNT3_L:
IR
BT
CF/SD
CAMERA
AIRPORT (MINI-PCIE)
EXTERNAL 2
EXTERNAL 1
EXTERNAL 0
NOTE:
STUFF - A16 SWAP OVERRIDE
NO STUFF - DEFAULT
(STRAPPED TO TOP-BLOCK SWAP MODE IE SB INVERTS A16 FOR ALL CYCLES TARGETING FWH BIOS SPACE)
SB BOOT BIOS SELECT
GNT4#GNT5#
TO RSVD[1-9]
NOTE: CHANGE SYMBOL
(INT 20K PU)
R2210STRAP
11
10
01
STUFF
UNSTUFF
UNSTUFF UNSTUFF
STUFF
UNSTUFF
SPI
PCI
LPC (DEFAULT)
NOTE:
LAYOUT NOTE: PLACE R2203 < 1/2 IN FROM SB
LAYOUT NOTE: PLACE R2204 < 1/2 IN FROM SB
GNT4# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H
(AKA TP3, INTERNAL 20K PU)
(INT PD)
(INT PD)
GNT5# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)
NOTE: USBP[0-7]P/N HAVE INTERNAL 15K PD
NOTE: FWH_WP_L NOT USED
R2211
1/16W
402
24.9
MF-LF
1%
10K
1/16W MF-LF
5%
402
402
22.6
1% 1/16W MF-LF
1/16W
5%
10K
MF-LF 402
10K
5% 1/16W MF-LF 402
402
MF-LF
1/16W
10K
5%
10K
5% 1/16W MF-LF 402
OMIT
SB
ICH7-M
OMIT
ICH7-M
SB
MF-LF
5%
402
10K
1/16W
402
MF-LF
5%
10K
1/16W
10K
5% 1/16W MF-LF 402
MF-LF
1/16W
5%
10K
402
402
MF-LF
1/16W
5%
10K
MF-LF
402
5%
10K
1/16W
402
10K
MF-LF
5%
1/16W
NOSTUFF
MF-LF 1/16W
10K
402
5%
VOLTAGE=0
1/16W MF-LF
5%
1K
402
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
SB: 2 OF 4
??
22 97
051-7032
=PP3V3_S5_SB_USB
=PP3V3_S0_SB
TP_SB_XOR_AH8
TP_SB_XOR_AG8
TP_SB_XOR_AE9TP_SB_XOR_AE5
TP_SB_XOR_AD9
TP_SB_XOR_AH4
TP_SB_XOR_AG4
TP_SB_XOR_AD5
INT_PIRQD_L
USB_H_P
SPI_ARB
SB_GPIO29
USB_C_OC_L USB_D_OC_L USB_E_OC_L
USB_B_OC_L
USB_A_OC_L
USB_C_OC_L
=PP3V3_S5_SB_IO
PP1V5_S0_SB_VCC1_5_B
PCIE_F_R2D_C_P
PCIE_F_R2D_C_N
PCIE_F_D2R_P
PCIE_F_D2R_N
PCIE_E_R2D_C_P
PCIE_E_R2D_C_N
PCIE_E_D2R_P
PCIE_E_D2R_N
PCIE_D_R2D_C_P
PCIE_D_R2D_C_N
PCIE_D_D2R_P
PCIE_D_D2R_N
PCIE_C_R2D_C_P
PCIE_C_R2D_C_N
PCIE_C_D2R_P
PCIE_C_D2R_N
PCIE_B_R2D_C_P
PCIE_B_R2D_C_N
PCIE_B_D2R_P
PCIE_B_D2R_N
PCIE_A_R2D_C_P
PCIE_A_R2D_C_N
PCIE_A_D2R_P
PCIE_A_D2R_N
DMI_N2S_P<1>
DMI_N2S_N<1>
DMI_S2N_N<1> DMI_S2N_P<1>
DMI_N2S_N<2> DMI_N2S_P<2>
SB_CLK100M_DMI_N
SB_GPIO29 SB_GPIO30
USB_E_N
USB_H_N
USB_G_P
USB_G_N
USB_F_P
USB_F_N
USB_E_P
USB_D_P
USB_D_N
USB_C_P
USB_C_N
USB_B_P
USB_B_N
USB_A_P
USB_A_N
DMI_N2S_P<3> DMI_S2N_N<3> DMI_S2N_P<3>
DMI_N2S_N<3>
DMI_S2N_P<2>
DMI_S2N_N<2>
DMI_S2N_P<0>
DMI_S2N_N<0>
DMI_N2S_P<0>
DMI_N2S_N<0>
USB_RBIAS_PN
SB_CLK100M_DMI_P
DMI_IRCOMP_R
INT_PIRQC_L
INT_PIRQB_L
INT_PIRQA_L
TP_PCI_GNT0_L
PCI_C_BE_L<3>
PCI_C_BE_L<2>
PCI_AD<31>
PCI_AD<30>
PCI_AD<29>
PCI_AD<28>
PCI_AD<27>
PCI_AD<26>
PCI_AD<25>
PCI_AD<24>
PCI_AD<23>
PCI_AD<22>
PCI_AD<21>
PCI_AD<20>
PCI_AD<19>
PCI_AD<18>
PCI_AD<17>
PCI_AD<16>
PCI_AD<15>
PCI_AD<14>
PCI_AD<13>
PCI_AD<12>
PCI_AD<11>
PCI_AD<10>
PCI_AD<9>
PCI_AD<8>
PCI_AD<5>
PCI_AD<4>
PCI_AD<3>
PCI_AD<2>
PCI_AD<1>
PCI_AD<0>
PCI_SERR_L
PCI_LOCK_L
PCI_PAR
PCI_CLK_SB
PCI_IRDY_L
PCI_FRAME_L
PCI_TRDY_L
PLT_RST_L
TP_PCI_PME_L
PCI_RST_L
PCI_STOP_L
PCI_PERR_L
PCI_DEVSEL_L
PCI_C_BE_L<1>
PCI_C_BE_L<0>
SB_GPIO2 SB_GPIO3 SB_GPIO4
TP_SB_RSVD9
NB_SB_SYNC_L
PCI_REQ0_L
SPI_CE_L
SB_GPIO31
USB_A_OC_L
USB_E_OC_L
USB_B_OC_L
USB_D_OC_L
SPI_SI
SB_GPIO_48
ODD_PWR_EN_L
SPI_SCLK
SPI_SO
SB_GPIO31
PCI_GNT1_L
BOOT_LPC_SPI_L
PCI_PME_FW_L
PCI_GNT3_L
PCI_REQ2_L
TP_PCI_GNT2_L PCI_AD<6> PCI_AD<7>
PCI_REQ3_L
SB_CRT_TVOUT_MUX
PCI_REQ1_L
SB_GPIO30
R2204
1 2
R2203
1 2
R2205
1
2
R2206
1
2
R2207
1
2
R2211
1
2
R2222
1
2
R2223
1
2
R2225
1
2
R2226
1
2
R2299
1
2
U2100
V26 V25 U28 U27
Y26 Y25 W28 W27
AB26 AB25 AA28 AA27
AD25 AD24 AC28 AC27
AE28 AE27
D25
C25
D3 C4 D5 D4 E5 C3 A2 B3
F26
H26
K26
M26
P26
T25
F25
H25
K25
M25
P25
T24
E28
G28
J28
L28
N28
R28
E27
G27
J27
L27
N27
R27
P1
R2 P6
P2
P5
F1 F2 G4 G3 H1 H2 J4 J3 K1 K2 L4 L5 M1 M2 N4 N3
D1
D2
U2100
E18 C18
E14 D14 B12 C13 G15 G13 E12 C11 D11 A11
A16
A10 F11 F10
E9 D9 B9 A8 A6 C7 B6
F18
E6 D6
E16 A18 E17 A17 A15 C14
B15 C12 D12 C15
A12
F16
E7
D16
D17
F13
A14 C8 D8
G8 F7 F8 G7
A7
AH20
E10 A9
B18
C9
A3 B4 C5 B5
E11
C26
B19
D7
C16
C17
E13
A13
AE5 AD5 AG4 AH4 AD9
AE9 AG8 AH8 F21
B10 F15 F14
R2200
1
2
R2250
1
2
R2251
1
2
R2255
1
2
R2298
1
2
6
25
6
44 26
47
58
5
22
47 22
22
47 22
22
47 22
47 22
27
6
25 24
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
54
5
54
5
54
54
54
5
54
5
14
14
14
14
14
14
34
5
22
22
47
47
47
47
5
5
47
47
47
47
47
53
53
47
47
14
14
14
14
14
14
14
5
14
5
14
5
14
5
34
5
26
26
26
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44
44 26
26
44
34
5
44 26
44 26
44 26
6
44
44 26
44 26
44 26
44
44
26
38 26
26
14
26
63 58
22
47 22
47 22
22
22
63 58
94
26
63 58
63 58
22
27
60 58
44
27
26
44
44
27 26
96
27 26
22
Page 23
IN
IN
IN
IN
OUT
OUT
OUT OUT
OUT
IN
IN
IO
IO
OUT OUT
OUT
IN
IN
IO
IN
IN
IO
IN
IN
IN
IN
OUT
IO
IO
IN
OUT
IN
OUT
IN
OUT
GPIO19/SATA1GP
GPIO21/SATA0GP
GPIO36/SATA2GP
CLK48
GPIO37/SATA3GP
CLK14
SUSCLK
SLP_S3* SLP_S4* SLP_S5*
PWROK
TP0/BATLOW*
GPIO16/DPRSLPVR
PWRBTN*
LAN_RST*
RSMRST*
GPIO10
GPIO9
GPIO12
GPIO14
GPIO13
GPIO24
GPIO15
GPIO25 GPIO35 GPIO38 GPIO39
SMBCLK SMBDATA LINKALERT*
SMLINK1
SMLINK0
RI*
SYS_RST*
SPKR SUS_STAT*
GPIO0/BM_BUSY*
GPIO18/STPPCI*
GPIO11/SMBALERT*
GPIO20/STPCPU*
GPIO26
GPIO28
GPIO27
GPIO32/CLKRUN*
GPIO33/AZ_DOCK_EN*
WAKE*
GPIO34/AZ_DOCK_RST*
SERIRQ THRM*
GPIO7
GPIO6
VRMPWRGD
GPIO8
(4 OF 6)
SMB
GPIO
PWR MNGT
SYS GPIO
CLKS
SATA GPIO
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
- HAS INTERNAL 20K PU, ENABLED DURING RSMRST# AND DISABLED WITHIN 100MS AFTER RSMRST# DEASSERTS
- CAN NOT BE LOW FOR 35US AFTER RSMRST# ON BOOT (DMI AC COUPLING MODE STRAP)
AZALIA DOCKING INT’F
RESERVED FOR MOBILE
SYSTEM REBOOT FEATURE
STRAPPING @ PWROK RISING: SB WILL DISABLE TCO TIMER
NOTE FOR R2323 (DEF=NOSTUFF)
NOT USED
NOTE: RESERVED FOR FUTURE
(INT WEAK PD)
LAYOUT NOTE: PLACE R2306-14 WHERE PHYSICALLY ACCESSIBLE
NOTE: DPRSLPVR HAS INT 20K PD, ENABLED AT BOOT/RESET FOR STRAPPING FCN
NOTE FOR GPIO25:
(INT 20K PU)
OD
DEF=GPI
DEF=GPI
DEF=GPI
IN RESET STATE TO SAVE PWR
SMC WILL DRIVE 0-1-0 TO KEEP LAN INT’F
NOTE:
NOTE: SV_SET_UP IS LINDACARD DETECT
LO = NOT PRESENT
HI = PRESENT
PM_DPRSLPVR
=PP3V3_S0_SB_GPIO
INT_SERIRQ
PM_BATLOW_L
PM_RSMRST_L
SMC_WAKE_SCI_L
PM_STPPCI_L PM_STPCPU_L
PM_CLKRUN_L
PCIE_WAKE_L
PM_THRM_L
SMC_RUNTIME_SCI_L SMC_EXTSMI_L
SV_SET_UP
SMB_CLK
SATA_C_DET_L
SB_GPIO19
SB_GPIO21
SB_GPIO37
PM_SLP_S4_L PM_SLP_S5_L
PM_SB_PWROK
PM_PWRBTN_L
PM_LAN_ENABLE
SV_SET_UP
TP_SB_GPIO25_DO_NOT_USE
SB_CLK100M_SATA_OE_L
SATA_C_PWR_EN_L
SMB_LINK_ALERT_L
SMLINK<1>
SMLINK<0>
PM_RI_L
PM_SYSRST_L
PM_SUS_STAT_L
BIOS_REC
TP_AZ_DOCK_EN_L
VR_PWRGD_CK410
=PP3V3_S5_SB
=PP3V3_S5_SB
IDE_RESET_L
TP_SB_GPIO6
TP_SB_GPIO38
CRB_SV_DET
=PP3V3_S5_SB
FWH_MFG_MODE
BIOS_REC
SMC_SB_NMI
PATA_PWR_EN_L
SMS_INT_L
CRB_SV_DET
=PP3V3_S0_SB_GPIO
SATA_C_PWR_EN_L
=PP3V3_S5_SB
PATA_PWR_EN_L
TP_AZ_DOCK_RST_L
FWH_MFG_MODE
PM_BMBUSY_L
SB_SPKR
SMB_DATA
=PP3V3_S5_SB
SMB_ALERT_L
SB_GPIO26
SB_CLK14P3M_TIMER SB_CLK48M_USBCTLR
SUS_CLK_SB
PM_SLP_S3_L
=PP3V3_S5_SB_PM
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
??
23 97
051-7032
SB: 3 OF 4
MF-LF
1/16W
8.2K
402
5%
10K
402
1/16W MF-LF
5%
NOSTUFF
10K
MF-LF 5%
402
1/16W
NOSTUFF
1K
402
NO_REBOOT_MODE
1/16W
5%
MF-LF
NOSTUFF
10K
1/16W MF-LF
5%
402
10K
5% MF-LF
1/16W 402
MF-LF
1/16W
5%
10K
402
OMIT
SB
ICH7-M
5%
402 MF-LF
1/16W
8.2K
402
10K
1/16W
5%
MF-LF
402
8.2K
1/16W MF-LF
5%
1K
402 5%
MF-LF
1/16W
100K
1/16W MF-LF
402
5%
SM-LF
10K
5% 1/16W
10K
1/16W MF-LF
5%
402
10K
1/16W MF-LF
5%
402
5%
MF-LF
1/16W 402
10K
5%
MF-LF
1/16W
10K
402
5%
MF-LF
1/16W
10K
402
5%
MF-LF
1/16W
0
NOSTUFF
402
402 5%
MF-LF
1/16W
10K
10K
402
NOSTUFF
5%
MF-LF
1/16W
10K
1/16W MF-LF
5%
402
NOSTUFF
402
0
1/16W MF-LF
5%
10K
5%
MF-LF
1/16W 402
1/16W MF-LF
5%
402
10K
10K
1/16W MF-LF
5%
402
NOSTUFF
100
100
100
R2323
1
2
R2326
1
2
R2327
1
2
R2343
1
2
R2302
1 2
R2303
1 2
R2305
1 2
R2306
1
2
R2307
1
2
R2308
1
2
R2309
1
2
R2310
1
2
R2311
1
2
R2313
1
2
R2314
1
2
R2316
1
2
R2317
1
2
R2318
1
2
R2319
1
2
R2320
1
2
RP2300
1 2 3 4
8 7 6 5
R2399
1 2
R2398
1
2
R2397
1
2
R2396
1
2
R2395
1
2
U2100
AC1 B2
AB18
A20
B23
F19 E19 R4 E22
AC22
AC20
AH18
AF21
AF19
R3 D20
A21
B21 E23
AG18
AC19
U2
AD21
AH19 AE19
AD20 AE20
AC21 AC18
E21
E20
C19
A26
C23
AA4
A28
Y4
AH21
B24 D23 F22
C22 B22
B25 A25
A19 A27
C20
A22
AF20
C21
AD22
F20
R2390
1
2
R2388
1
2
R2387
1
2
75 14
27 23 21
6
67 60 58
58
58
58
33
33
67 60 58 44
5
53 41
58 10
58
58
60 23
27
38
77 58
58
26
58
58
60 23
33
23
58 26
5
67 60 58
23
26
26 25 23
6
26 25 23
6
38
23
26 25 23
6
23
23
58
23
58 26
23
27 23 21
6
23
26 25 23
6
23
23
14
27
26 25 23
6
34
5
34
5
59
80 79 77 58
11
6
Page 24
(6 OF 6)
VSS
V5REF_SUS
VCC3_3
VCCDMIPLL
VCCSATAPLL
VCC3_3
VCCRTC
VCCUSBPLL
VCCSAUS1_5
VCC PAUX
USB CORE
VCC1_5_A
ARX
USB
PCI
IDE
VCCA3GP
CORE
ATX
VCC1_5_A
VCC3_3
VCC3_3
VCCSUS3_3
VCC1_5_A
VCCSUS3_3
VCCSUS3_3
VCC1_5_A
VCC1_5_A
VCC1_5_A
VCCLAN1_5
V_CPU_IO
VCC3_3/VCCHDA
VCCSUS3_3/VCCSUSHDA
VCCLAN_3_3
VCC1_05
V5REF
VCC1_5_B
(5 OF 6)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE FOR VCCLAN_3_3: S3 IF INTERNAL LAN IS USED S0 OR S3 IF NOT
CHANGE SYMBOL TO 1.05
CHANGE SYMBOL TO 1.05
SO NO CONNECT HERE
VOLTAGE GENERATED INTERNALLY
SO NO CONNECT HERE
VOLTAGE GENERATED INTERNALLY
NOTE: VCCHDA AND VCCSUSHDA CAN BE 1.5V OR 3.3V DEPENDING ON VIO OF AZALIA INTERFACE CODEC IC’S CONSIDERED SO FAR ARE 3.3V
PP1V5_S0_SB_VCC1_5_B
PP5V_S0_SB_V5REF
PP5V_S5_SB_V5REF_SUS
=PPVCORE_S0_SB
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S5_SB_3V3_1V5_VCCSUSHDA
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0_SB_VCC3_3
PP1V5_S0_SB_VCCDMIPLL
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCCSATAPLL
=PP3V3_S0_SB_VCC3_3
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S0_SB_VCC3_3_IDE
=PP3V3_S0_SB_VCC3_3_PCI
PP3V3_S5_SB_RTC
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP1V5_S0_SB_VCC1_5_A
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
=PP1V5_S0_SB_VCCUSBPLL
SB: 4 OF 4
SYNC_DATE=01/05/2006
SYNC_MASTER=M38
??
24 97
051-7032
OMIT
SB
ICH7-M
OMIT
ICH7-M
SB
00
U2100
A4
A23
B1
B8 B11 B14 B17 B20 B26 B28 C2 C6 C27
D10
D13 D18 D21 D24 E1 E2 E4 E8 E15 F3
F4
F5 F12 F27 F28 G1 G2 G5 G6 G9 G14
G18
G21 G24 G25 G26 H3 H4 H5 H24 H27 H28
J1
J2 J5 J24 J25 J26 K24 K27 K28 L13 L15
L24
L25 L26 M3 M4 M5 M12 M13 M14 M15 M16
M17
M24 M27 M28 N1 N2 N5 N6 N11 N12 N13
N14
N15
N16 AE24 AE25
AF2 AF4
AF8 AF11 AF27 AF28
N17
AG1
AG3
AG7
AG11 AG14 AG17 AG20 AG25 AH1 AH3
N18
AH7 AH12 AH23 AH27
N24
N25
N26
P3
P4 P12 P13 P14 P15 P16 P17
P24
P27 P28
R1 R11 R12 R13 R14 R15 R16 R17
R18
T6 T12 T13 T14 T15 T16 T17
U4 U12 U13
U14
U15 U16 U17 U24 U25 U26
V2 V13 V15 V24
V27
V28
W6 W24 W25 W26
Y3 Y24 Y27 Y28 AA1
AA24
AA25 AA26
AB4 AB6
AB11 AB14 AB16 AB19 AB21 AB24
AB27
AB28
AC2 AC5 AC9
AC11
AD1
AD3 AD4 AD7 AD8
AD11
AD15 AD19 AD23 AE2 AE4 AE8 AE11 AE13 AE18 AE21
U2100
G10
AD17
F6
AE23 AE26 AH26
L11
P18 T11 T18 U11 U18 V11 V12 V14 V16 V17
L12
V18
L14 L16 L17 L18 M11 M18 P11
AB7 AC6
AB9 AC10 AD10 AE10 AF10
AF9
AG9
AH9
AB17 AC17
AC7
T7 F17 G17
AB8 AC8
A1 H6 H7 J6 J7
AD6
AE6
AF5
AF6
AG5
AH5
AB10
AA22 AA23
AD28
D26
D27
D28
E24
E25
E26
F23
F24
G22
AB22
G23
H22
H23
J22
J23
K22
K23
L22
L23
M22
AB23
M23
N22
N23
P22
P23
R22
R23
R24
R25
R26
AC23
T22
T23
T26
T27
T28
U22
U23
V22
V23
W22
AC24
W23
Y22
Y23
AC25 AC26 AD26 AD27
U6
B27
AH11
AG19
A5 B13 B16 B7 C10 D15 F9 G11 G12
AA7
G16
AB12 AB20 AC16 AD13 AD18 AG12 AG15
AG28
AA2
Y7
V5 V1 W2 W7
W5
AD2
K7
C28 G20
R7
P7
A24
L1 L2 L3 L6 L7 M6 M7 N7
E3
C24 D19 D22 G19
K3 K4 K5 K6
C1
25 22
25
25
25
6
25
6
25
6
6
25 21
6
25 24
6
25
25
6
25
6
25 24
6
25
6
25 24
6
25
6
25
6
26 25 21
5
25 24
6
25
6
25
6
25
6
25
6
Page 25
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
A24 ... G19 AND P7 OF SB
PLACE < 2.54MM OF SB ON
PLACEMENT NOTE:
SECONDARY SIDE OR 3.56MM ON PRIMARY
152S0315
1UH,0.5A,20%,1206
PLACE NEAR PINS AE23, AE26 & AH26 OF SB
AB8 AND AC8 OF SB
PLACEMENT NOTE: PLACE CAPS NEAR PINS
K3 ... N7 OF SB
PLACEMENT NOTE: PLACE CAPS NEAR PINS
PLACEMENT NOTE: PLACE CAPS NEAR PINS
PLACEMENT NOTE: PLACE CAPS AT EDGE OF SB
PLACEMENT NOTE: PLACE CAPS NEAR PIN W5 OF SB
PLACEMENT NOTE: PLACE C2520 NEAR PIN C1 OF SB
PLACEMENT NOTE: DISTRIBUTE IN PCI SECTION OF SB NEAR PINS A5 ... G16
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE: PLACE C2520 NEAR PIN E3 OF SB
V5, W2, OR W7
PLACE CAP UNDER SB NEAR PINS V1,
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACEMENT NOTE:
PLACE C2509 NEAR PIN B27 OF SB
PLACEMENT NOTE:
PLACEMENT NOTE:
NEAR PINS D28, T28, AD28
PLACEMENT NOTE: PLACE C2503 < 2.54MM OF PIN AD17 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY
PLACE C2504 < 2.54MM OF PIN F6 OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY
PLACE C2500 & C2505-07 < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY
3.56MM ON PRIMARY NEAR PIN AG9
3.56MM ON PRIMARY NEAR PIN AH11
3.56MM ON PRIMARY NEAR PIN AD2
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PIN U6
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PINS AA7 ... AG19
PLACEMENT NOTE: PLACE < 2.54MM OF SB ON SECONDARY OR
3.56MM ON PRIMARY NEAR PINS A1 ... J7
PLACEMENT NOTE:
155S0247
100-OHM,4A,0805
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACE < 2.54MM OF SB ON SECONDARY OR
PLACEMENT NOTE:
3.56MM ON PRIMARY NEAR PIN AG5
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.5V
PP1V5_S0_SB_VCC1_5_B
=PP1V05_S0_SB_CPU_IO
=PP3V3_S0_SB
=PP5V_S0_SB
=PP3V3_S5_SB
=PP1V5_S0_SB
=PP3V3_S0_SB_VCC3_3
=PP1V5_S0_SB_VCC1_5_A_ARX
=PP1V5_S0_SB_VCCSATAPLL
=PP1V5_S0_SB_VCC1_5_A_ATX
=PP3V3_S0_SB_VCC3_3
=PP3V3_S5_SB_VCCSUS3_3
=PPVCORE_S0_SB
=PP3V3_S0_SB_VCCLAN3_3
=PP3V3_S0_SB_3V3_1V5_VCCHDA
=PP3V3_S0_SB_VCC3_3_IDE
=PP1V5_S0_SB_VCC1_5_A
=PP3V3_S5_SB_VCCSUS3_3
=PP3V3_S5_SB_VCCSUS3_3_USB
=PP1V5_S0_SB_VCC1_5_A_USB_CORE
PP5V_S0_SB_V5REF
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
=PP1V5_S0_SB
VOLTAGE=1.5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.15MM
PP1V5_S0_SB_VCCDMIPLL
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=1.5V
PP1V5_S0_SB_R
=PP1V5_S0_SB_VCCUSBPLL
PP3V3_S5_SB_RTC
=PP3V3_S0_SB_VCC3_3_PCI
PP5V_S5_SB_V5REF_SUS
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V
=PP5V_S5_SB
051-7032
9725
??
SB:DECOUPLING
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
X5R
16V
10%
0.1UF
402
0
X5R
16V
10%
0.1UF
402
X5R
16V
10%
0.1UF
402
0
X5R
16V
10%
0.1UF
402
X5R
16V
10%
0.1UF
402
0
X5R
16V
10%
0.1UF
402
402
0.1UF
10% 16V X5RX5R
16V
10%
0.1UF
402402
10% X5R
16V
0.1UF
0
402
0.1UF
10% 16V X5R
0
402
0.1UF
10% 16V X5R
10%
402
X5R
16V
0.1UF
0
X5R
16V
10%
0.1UF
402
0
402
0.1UF
10% 16V X5R
0
X5R
16V
10%
0.1UF
402 402
6.3V CERM
10%
1UF
100
MF-LF
402
1/16W
5%
2.5V
20%
330UF
POLY CASE-C2
0
0
402
16V
10%
0.01UF
CERM
10% 16V
402
0.01UF
CERM
0
1UF
10% CERM
6.3V 402
0
0
402
X5R
16V
10%
0.1UF
0
10% 16V X5R 402
0.1UF
0
0.1UF
10% 16V X5R 402
0
402
X5R
16V
10%
0.1UF
0
10UF
805-1
CERM
6.3V
20%
402
CERM
16V
10%
0.01UF
1206
0.28-OHM
402
X5R
16V
10%
0.1UF
402
0.1UF
10% 16V X5R
402
X5R
16V
10%
0.1UF
0
100-OHM-EMI
SM-3
MF-LF
1/16W
402
10
1%
0
X5R
16V
10%
0.1UF
402
0
X5R
10%
402
0.1UF
16V
402
0.1UF
10% 16V X5R
402
6.3V CERM
10%
1UF
X5R
16V
10%
0.1UF
402
4.7UF
20%
6.3V CERM 603
SOT23
BAT54E3
SOT23
BAT54E3
MF-LF
5%
1
603
1/10W
0
X5R
16V
10%
0.1UF
402
0
402
0.1UF
10% 16V X5R
220UF
20% POLY
2.5V SMB2
R2502
1
2
C2500
1
2
R2500
1 2
C2503
1
2
C2504
1
2
R2501
1 2
L2500
1 2
C2505
1
2
C2506
1
2
C2507
1
2
L2507
1 2
C2501
1
2
C2508
1
2
C2509
1
2
C2511
1
2
C2517
1
2
C2513
1
2
C2514
1
2
C2520
1
2
C2515
1
2
C2516
1
2
C2502
1
2
C2518
1
2
C2519
1
2
C2521
1
2
C2522
1
2
C2523
1
2
C2525
1
2
C2526
1
2
C2527
1
2
C2528
1
2
C2529
1
2
C2530
1
2
C2534
1
2
C2531
1
2
C2532
1
2
C2533
1
2
C2510
1
2
C2512
1
2
D2501
1
3
D2500
1
3
C2524
1
2
C2540
1
2
C2541
1
2
C2542
1
2
24 22
24 21
6
22
6
6
26 23
6
25
6
25 24
6
24
6
24
6
24
6
25 24
6
25 24
6
24
6
24
6
24
6
24
6
24
6
25 24
6
24
6
24
6
24
25
6
24
24
6
26 24 21
5
24
6
24
6
Page 26
OUT
IO
IO
IN
IN
IN
IN
IO
IO
IO
IO IO
IO IO
OUT
OUT
IN
IN
OUT
OUT
IN
VCC
GND
IN
OUT
IN
IN
OUT
OUT
IO IO
IO IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NOTE: R2696 CAN’T EXIST WITH BOTH ITP & DEVELOPMENT
SHOULD BE STUFFED WITH ITP & NO DEVELOPMENT
NOTE: ISL6262 SPEC (P 5) SAID TO USE 1.9K
RESET
RESISTOR TO GND USED TO PROVIDE PADS TO SHORT THIS RESET_L IN CASE OF BAD SMC FLASH DURING DEVELOPMENT
PLACE R2603 IN ACCESSIBLE LOCATION
USING 1% FOR BOM CONSOLIDATION
0
1%
20.0K
402
1/16W
MF-LF
BAT54E3
SOT23
BAT54E3
SOT23
SOT23-5
74LVC1G04DBVG4
402
20% 10V
CERM
0.1UF
10%
6.3V CERM 402
1UF
SPST
SM-LF
DEVELOPMENT
DEVELOPMENT
10K
MF-LF
5% 1/16W
402
0
DEVELOPMENT
SOT143
MAX6816
402
DEVELOPMENT
20% 10V CERM
0.1UF
DEVELOPMENT
402
MF-LF
1/16W
5%
100K
0.1UF
20%
DEVELOPMENT
10V CERM 402
1%
402
1M
1/16W
MF-LF
SB_SYSRST_4_PVT
402
MF-LF
1/16W
5%
10K
MF-LF
1/16W
5%
0
402
32.768K
SM-LF
SOT23-5-LF
MC74VHC1G08
SOT23-5-LF
DEVELOPMENT
MC74VHC1G08
DEVELOPMENT
MF-LF
1/16W
5%
1K
402
402
10K
5% 1/16W MF-LF
MF-LF
1/16W
5%
402
1K
0
5% 1/16W MF-LF 402
NOSTUFF
0
CRITICAL
BB1020
SM
402
10M
MF-LF
1/16W
5%
1%
1.82K
1/16W MF-LF 402
402
0.1UF
CERM
10V
20%
402
5%
MF-LF
1/16W
10K
0
15PF
CERM 402
5%
50V
10K
15PF
50V
5%
402
CERM
8.2K
8.2K
8.2K
8.2K
0
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
8.2K
CERM
6.3V
10%
1UF
402
051-7032
??
26 97
SB: MISC
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
PP3V3_S5
MIN_LINE_WIDTH=0.6MM
PP3V3_S5_SB_RTC
VOLTAGE=3.3V
PPVBATT_S5_RTC_R
MIN_LINE_WIDTH=0.6MM
SB_RTC_RST_L
SW_RST_BTN_L
SB_RTC_X2
SB_RTC_X1
PM_SYSRST_L
VR_PWRGD_CK410
VR_PWRGD_CK410_L
=PP3V3_S5_SB
SB_SM_INTRUDER_L
PPVBATT_S5_RTC
MIN_LINE_WIDTH=0.6MM
CK410_PD_VTT_PWRGD_L
PP3V3_S0
PP3V3_S0
PCI_SERR_L PCI_DEVSEL_L
PCI_LOCK_L
PCI_REQ1_L
PCI_REQ3_L
INT_PIRQA_L INT_PIRQB_L
INT_PIRQD_L
INT_PIRQC_L
SB_GPIO4
SB_GPIO3
SB_GPIO2
=PP3V3_S0_SB_PM
PM_SB_PWROK
XDP_DBRESET_L
SW_RST_DEBNC
VR_PWRGOOD_DELAY
PCI_REQ2_L
PCI_REQ0_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L PCI_IRDY_L
PCI_PERR_L
PP3V3_S5
=PP3V3_S0_SB_PCI
PP3V3_S5
SMS_INT_L
U2698_4
ODD_PWR_EN_L
MAKE_BASE=TRUE
SB_GPIO5
ALL_SYS_PWRGD
VOLTAGE=3.3V
CRITICAL
NOT_DEVELOPMENT_PLUS_ITP
R2609
1
2
C2608
1 2
C2609
1 2
C2610
1
2
R2600
1 2
C2605
1
2
R2606
1
2
R2607
1
2
J2600
2
1
R2611
1 2
C2607
1 2
R2612
1 2
R2622
1 2
R2623
1 2
R2624
1 2
R2625
1 2
R2626
1 2
R2627
1 2
R2628
1 2
R2629
1 2
R2630
1 2
R2631
1 2
R2632
1 2
R2633
1 2
R2634
1 2
R2636
1 2
R2637
1 2
R2638
1 2
R2639
1 2
R2640
1 2
R2641
1 2
R2642
1 2
R2643
1 2
D2600
1 3
D2601
1 3
U2603
2
3
5
4
C2611
1 2
SW2600
1 2
3 4
R2699
1
2
U2699
1
2 3
4
C2699
1
2
R2698
1
2
C2698
1
2
R2697
1
2
R2696
1 2
Y2600
14
U2601
3
2
1
4
5
U2698
3
2
1
4
5
R2650
1 2
R2651
1
2
R2603
1
2
83 80
79 78 77 76 66 65 59 26
6 5
25 24 21
5
21
21
21
58 23
5
23 75
25 23
6
21
33
94 83 76 61 59 41 26 10
6
94 83 76 61 59 41 26 10
6
44 22
44 22
22
27 22
27 22
22
22
44 22
22
22
38 22
22
6
23
11
7
75 14
5
22
22
44 22
44 22
44 22
44 22
44 22
83 80
79 78 77 76 66 65 59 26
6 5
6
83 80
79 78 77 76 66 65 59 26
6 5
58 23
22
77 58
Page 27
IO IO
IO
IO
IO IO
IO IO
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SB I2C BUSSES
PCI CONTROL
NOSTUFF
2.2K
NOSTUFF
2.2K
2.2K
2.2K
SB: SMB HUB AND ALIAS
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
9727
??
051-7032
PCI_REQ1_L
MAKE_BASE=TRUE
PCI_FW_REQ_L
NO_TEST=TRUE
PCI_FW_GNT_L
SMB_CLK SMB_DATA
=PP3V3_S0_SB_GPIO
=PP3V3_S5_SB_IO
MAKE_BASE=TRUE
SMB_CLK
=I2C_MEM_SDA
=I2C_MEM_SCL
MAKE_BASE=TRUE
SMB_DATA
=SMB_AIRPORT_DATA
=SMB_AIRPORT_CLK
SMB_CK410_DATA
SMB_CK410_CLK
PCI_GNT3_L
PCI_GNT1_L
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_PCI_GNT3_L
PCI_REQ3_L
R2719
1 2
R2718
1 2
R2729
1 2
R2728
1 2
26 22
44
44
27 23
27 23
23 21
6
22
6
27 23
29 28
29 28
27 23
53
53
33
33
22
22
26 22
Page 28
DQ58 DQ59
SA1GNDVDDSPD
SDA SCL
DQ4
VSS11
VSS13
DQ14
VSS2
DQ5
SA0
VSS58
DQ63
DQ62
VSS56
DQS7
DQS7*
VSS54
DQ60
VSS52
DQ54
VSS50
VSS48
CK1*
CK1
VSS46
DQ53
DQ52
VSS44
VSS42
DQS5
DQS5*
VSS39
DQ45
DQ44
VSS37
DQ39
DQ38
VSS35
DM4
VSS34
DQ37
DQ36
VSS32
NC3
VDD11
NC/A13
ODT0
VDD9
S0*
RAS*
BA1
VDD7
A0
A2
A4
VDD5
A6
A7
A11
VDD3
NC/A14
NC/A15
VDD1
NC/CKE1
VSS30
DQ31
DQ30
VSS28
DQS3
DQS3*
VSS26
DQ29
DQ28
VSS24
DQ23
DQ22
VSS22
DM2
NC0
VSS19
DQ21
DQ20
VSS17
VSS15
DQ15
CK0*
CK0
DQ13
VSS7
VSS5
DM0
VSS0
DM1
DQ12
DQ6
DQ47
DQ46
DQ61
DQ55
DM6
VSS57
DM7
VSS53
DQ56
VSS51
DQ50
VSS49
DQS6*
VSS47
NC_TEST
VSS45
DQ49
DQ48
VSS43
VSS41
DM5
VSS40
DQ41
VSS38
DQ35
VSS36
DQS4
DQS4*
VSS33
DQ33
DQ32
VSS31
NC/ODT1
VDD10
NC/S1*
CAS*
VDD8
WE*
BA0
A10/AP
VDD6
A1
A3
A5
VDD4
A8
A9
A12
VDD2
BA2
NC2
VDD0
CKE0
VSS29
DQ27
DQ26
VSS27
NC1
DM3
VSS25
DQ25
DQ24
VSS23
DQ19
DQ18
VSS21
DQS2
DQS2*
VSS18
DQ17
DQ16
VSS16
VSS14
DQ11
DQ10
VSS12
DQS1
DQS1*
VSS10
DQ9
DQ8
VSS8
DQ3
DQ2
VSS6
DQS0
DQS0*
VSS4
VSS1
VREF
DQ0 DQ1
DQ34
DQ40
DQ42 DQ43
DQS6
DQ51
DQ57
KEY
VSS9
DQ7
VSS55
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
516S0403
ALL NC’S
to drive MCH and DIMM connectors. (See Capell Valley pg 47)
NC
NC
NC
Power aliases required by this page:
(For return current)
DDR2 Bypass Caps
(NONE)
- =I2C_MEM_SCL
- =I2C_MEM_SDA
BOM options provided by this page:
Signal aliases required by this page:
Page Notes
NC
ADDR=0xA0(WR)/0xA1(RD)
- =PP1V8_S3_MEM
- =PPSPD_S0_MEM (2.5V - 3.3V)
One 0.1uF per connector
DDR2 VRef
Yellow uses 10K divider and TLV2463
20%
402
CERM
0.1uF
10V
20%
402
CERM
0.1uF
10V
20%
402
CERM
0.1uF
10V
20%
402
CERM
0.1uF
10V
10V
0.1uF
CERM 402
20%
10V
0.1uF
CERM 402
20%
10V
0.1uF
CERM 402
20%
10V
0.1uF
CERM 402
20%
10V
0.1uF
CERM 402
20%
0.1uF
10V
CERM 402
20%
10V
0.1uF
CERM 402
20%
10V
0.1uF
CERM 402
20%
CERM
402
10V
20%
0.1uF
20%
10UF
6.3V
X5R 603
20%
10UF
6.3V
X5R 603
20%
10UF
6.3V
X5R 603
20%
10UF
6.3V
X5R 603
DDR2-SODIMM-STD
CRITICAL
F-RT-SM1
10%
2.2UF
6.3V
CERM1
603
402
10V
CERM
20%
0.1uF2.2UF
10%
6.3V
CERM1
603
MF-LF 402
1K
1% 1/16W
1/16W
1%
402
MF-LF
1K
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
28 97
??
051-7032
DDR2 SO-DIMM Connector A
MEM_VREF
MEM_VREF
MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm
VOLTAGE=0.9V
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
=PP1V8_S3_MEM
=PP1V8_S3_MEM
MEM_CLK_P<0>
MEM_A_DQ<52>
MEM_A_DQ<31>
MEM_A_DQ<63>
MEM_A_DQ<62>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQ<60>
MEM_A_DQ<54>
MEM_CLK_N<1>
MEM_CLK_P<1>
MEM_A_DQ<53>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DM<4>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_A<13>
MEM_ODT<0>
MEM_CS_L<0>
MEM_A_RAS_L
MEM_A_BS<1>
MEM_A_A<0>
MEM_A_A<2>
MEM_A_A<4>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<11>
TP_MEM_A_A<14>
TP_MEM_A_A<15>
=PP1V8_S3_MEM
MEM_A_DQ<46> MEM_A_DQ<47>
MEM_A_DM<6>
MEM_A_DQ<55>
MEM_A_DQ<61>
MEM_CKE<1>
MEM_A_DQ<30>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DM<2>
DIMM_OVERTEMP_L
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_CLK_N<0>
MEM_A_DQ<13>
MEM_A_DQ<7>
MEM_A_DM<0>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<6>
MEM_A_DQ<12>
MEM_A_DQ<43>
=I2C_MEM_SCL
=I2C_MEM_SDA
MEM_A_DQ<59>
MEM_A_DQ<58>
MEM_A_DM<7>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<41>
MEM_A_DQ<35>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_CS_L<1>
MEM_A_WE_L
MEM_A_BS<0>
MEM_A_A<10>
MEM_A_A<1>
MEM_A_A<3>
MEM_A_A<5>
MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<12>
MEM_A_BS<2>
=PP1V8_S3_MEM
MEM_CKE<0>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DM<3>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQS_P<2>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQS_N<1>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQS_N<0>
MEM_A_DQ<1>
MEM_A_DQ<0>
MEM_A_DQ<40>
MEM_A_DQ<42>
MEM_A_DQ<51>
MEM_A_DQ<57>
MEM_A_DQS_P<0>
MEM_A_DM<1>
MEM_A_DQS_P<6>
MEM_A_DQ<48>
MEM_A_DQ<34>
MEM_ODT<1>
MEM_A_CAS_L
MEM_A_DQ<56>
MEM_A_DQS_N<6>
MEM_A_DM<5>
=PPSPD_S0_MEM
R2800
1
2
R2801
1
2
C2813
1
2
C2812
1
2
C2811
1
2
C2810
1
2
C2819
1
2
C2818
1
2
C2817
1
2
C2816
1
2
C2821
1
2
C2820
1
2
C2815
1
2
C2814
1
2
C2800
1
2
C2804
1
2
C2803
1
2
C2802
1
2
C2801
1
2
J2800
102101
105
9089
100
99
9897
94
92
93
91
107
106
85
113
30 32
164 166
79
10
26
52
67
130
147
170
185
5 7
35 37
20 22
36 38
43 45
55 57
17
44 46
56 58
61 63
73 75
62 64
19
74 76
123 125
135 137
124 126
134 136
4
141 143
151 153
140 142
152 154
157 159
6
173 175
158 160
174 176
179 181
189 191
14
180 182
192 194
16
23 25
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
201
202
203
204
205
116
86
84
80
119
115
50
69
83
120
163
114
108 110
198 200
197
195
81 82
117 118
87 88
95 96
103 104
111 112
199
1 2 3
27 28
33 34
39 40
41 42
47 48
8
53 54
59 60
65 66
71 72
77 78
121 122
127 128
132
133
138
139
144
9
145
149 150
155 156
161 162
165
168
171
12
172
177 178
183 184
187
190
193
196
15
18
21
24
109
C2850
1
2
C2852
1
2
C2851
1
2
29 28
5
29 28
5
15
5
15
5
29 28
6 5
29 28
6 5
14
15
15
15
15
15
5
15
5
15
15
5
14
14
15
15
5
15
5
15
15
15
5
15
15
15
15
30 15
30 14
30 14
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
29 28
6 5
15
15
5
15
15
15
30 14
15
15
5
15
5
15
15
15
15
15
59 29
15
15
15
15
5
14
15
15
5
15
15
15
15
15
15
29 27
29 27
15
5
15
15
15
15
15
15
15
5
15
5
15
15
30 14
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
29 28
6 5
30 14
15
15
15
15
5
15
15
15
15
5
15
15
5
15
15
15
5
15
15
15
15
15
5
15
15
15
15
15
15
15
5
15
15
5
15
15
30 14
30 15
15
15
5
15
29
6
Page 29
DQ58 DQ59
SA1GNDVDDSPD
SDA SCL
DQ4
VSS11
VSS13
DQ14
VSS2
DQ5
SA0
VSS58
DQ63
DQ62
VSS56
DQS7
DQS7*
VSS54
DQ60
VSS52
DQ54
VSS50
VSS48
CK1*
CK1
VSS46
DQ53
DQ52
VSS44
VSS42
DQS5
DQS5*
VSS39
DQ45
DQ44
VSS37
DQ39
DQ38
VSS35
DM4
VSS34
DQ37
DQ36
VSS32
NC3
VDD11
NC/A13
ODT0
VDD9
S0*
RAS*
BA1
VDD7
A0
A2
A4
VDD5
A6
A7
A11
VDD3
NC/A14
NC/A15
VDD1
NC/CKE1
VSS30
DQ31
DQ30
VSS28
DQS3
DQS3*
VSS26
DQ29
DQ28
VSS24
DQ23
DQ22
VSS22
DM2
NC0
VSS19
DQ21
DQ20
VSS17
VSS15
DQ15
CK0*
CK0
DQ13
VSS7
VSS5
DM0
VSS0
DM1
DQ12
DQ6
DQ47
DQ46
DQ61
DQ55
DM6
VSS57
DM7
VSS53
DQ56
VSS51
DQ50
VSS49
DQS6*
VSS47
NC_TEST
VSS45
DQ49
DQ48
VSS43
VSS41
DM5
VSS40
DQ41
VSS38
DQ35
VSS36
DQS4
DQS4*
VSS33
DQ33
DQ32
VSS31
NC/ODT1
VDD10
NC/S1*
CAS*
VDD8
WE*
BA0
A10/AP
VDD6
A1
A3
A5
VDD4
A8
A9
A12
VDD2
BA2
NC2
VDD0
CKE0
VSS29
DQ27
DQ26
VSS27
NC1
DM3
VSS25
DQ25
DQ24
VSS23
DQ19
DQ18
VSS21
DQS2
DQS2*
VSS18
DQ17
DQ16
VSS16
VSS14
DQ11
DQ10
VSS12
DQS1
DQS1*
VSS10
DQ9
DQ8
VSS8
DQ3
DQ2
VSS6
DQS0
DQS0*
VSS4
VSS1
VREF
DQ0 DQ1
DQ34
DQ40
DQ42 DQ43
DQS6
DQ51
DQ57
KEY
VSS9
DQ7
VSS55
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ADDR=0XA4(WR)/0XA5(RD)
BOM options provided by this page:
- =PPSPD_S0_MEM (2.5V - 3.3V)
- =PP1V8_S3_MEM
Power aliases required by this page:
Page Notes
NC
NC
NC
Signal aliases required by this page:
NC
(For return current)
DDR2 Bypass Caps
- =I2C_MEM_SCL
- =I2C_MEM_SDA
(NONE)
NOTE: This page does not supply VREF.
by another page.
The reference voltage must be provided
Resistor prevents pwr-gnd short
516S0404
ALL NC’S
1UF
10% CERM
402
6.3V
20%
402
CERM
10V
0.1uF
10K
5% 1/16W MF-LF 402
1UF
10% CERM
6.3V
402 402
6.3V
CERM
10%
1UF
402
6.3V
CERM
10%
1UF
402
6.3V
CERM
10%
1UF
402
6.3V
CERM
10%
1UF
402
1UF
10% CERM
6.3V
402
1UF
10% CERM
6.3V
402
6.3V
CERM
10%
1UF
402
6.3V
CERM
10%
1UF
402
1UF
10% CERM
6.3V
402
1UF
10% CERM
6.3V
402
6.3V
CERM
10%
1UF
402
6.3V
CERM
10%
1UF
402
1UF
10% CERM
6.3V
402
1UF
10% CERM
6.3V
CRITICAL
F-RT-SM1
DDR2-SODIMM-REV
6.3V
CERM1
603
10%
2.2UF
0.1uF
20%
CERM
10V
402603
CERM1
6.3V
10%
2.2UF
DDR2 SO-DIMM Connector B
??
051-7032
29 97
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
=PPSPD_S0_MEM
MEM_B_DQ<17>
MEM_B_DQ<19>
MEM_B_DQ<16>
MEM_VREF
=PP1V8_S3_MEM
MEM_B_DM<1>
MEM_B_DQS_P<0>
MEM_B_DQ<57>
MEM_B_DQ<51>
MEM_B_DQS_P<6>
MEM_B_DQ<42>
MEM_B_DQ<40>
MEM_B_DQ<34>
MEM_B_DQ<0> MEM_B_DQ<1>
MEM_B_DQS_N<0>
MEM_B_DQ<2> MEM_B_DQ<3>
MEM_B_DQ<8> MEM_B_DQ<9>
MEM_B_DQS_N<1> MEM_B_DQS_P<1>
MEM_B_DQ<10> MEM_B_DQ<11>
MEM_B_DQS_N<2> MEM_B_DQS_P<2>
MEM_B_DQ<18>
MEM_B_DQ<24> MEM_B_DQ<25>
MEM_B_DM<3>
MEM_B_DQ<26> MEM_B_DQ<27>
MEM_CKE<2>
MEM_B_BS<2>
MEM_B_A<12> MEM_B_A<9> MEM_B_A<8>
MEM_B_A<5> MEM_B_A<3> MEM_B_A<1>
MEM_B_A<10> MEM_B_BS<0> MEM_B_WE_L
MEM_B_CAS_L MEM_CS_L<3>
MEM_ODT<3>
MEM_B_DQ<32> MEM_B_DQ<33>
MEM_B_DQS_N<4> MEM_B_DQS_P<4>
MEM_B_DQ<35>
MEM_B_DQ<49>
MEM_B_DQS_N<6>
MEM_B_DQ<50>
MEM_B_DQ<56>
MEM_B_DM<7>
MEM_B_DQ<58> MEM_B_DQ<59>
=I2C_MEM_SDA =I2C_MEM_SCL
MEM_B_DQ<43>
MEM_B_DQ<12>
MEM_B_DQ<6>
MEM_B_DQ<4> MEM_B_DQ<5>
MEM_B_DM<0>
MEM_B_DQ<7>
MEM_B_DQ<13>
MEM_CLK_N<3>
MEM_B_DQ<14> MEM_B_DQ<15>
MEM_B_DQ<20> MEM_B_DQ<21>
DIMM_OVERTEMP_L
MEM_B_DM<2>
MEM_B_DQ<22> MEM_B_DQ<23>
MEM_B_DQ<28> MEM_B_DQ<29>
MEM_B_DQS_N<3> MEM_B_DQS_P<3>
MEM_B_DQ<30>
MEM_CKE<3>
MEM_B_DQ<61>
MEM_B_DQ<55>
MEM_B_DM<6>
MEM_B_DQ<47>
MEM_B_DQ<46>
=PP1V8_S3_MEM
TP_MEM_B_A<15> TP_MEM_B_A<14>
MEM_B_A<11> MEM_B_A<7> MEM_B_A<6>
MEM_B_A<4> MEM_B_A<2> MEM_B_A<0>
MEM_B_BS<1> MEM_B_RAS_L MEM_CS_L<2>
MEM_ODT<2> MEM_B_A<13>
MEM_B_DQ<36> MEM_B_DQ<37>
MEM_B_DM<4>
MEM_B_DQ<38> MEM_B_DQ<39>
MEM_B_DQ<44> MEM_B_DQ<45>
MEM_B_DQS_N<5> MEM_B_DQS_P<5>
MEM_B_DQ<53>
MEM_CLK_P<2> MEM_CLK_N<2>
MEM_B_DQ<54>
MEM_B_DQ<60>
MEM_B_DQS_N<7> MEM_B_DQS_P<7>
MEM_B_DQ<62> MEM_B_DQ<63>
MEM_B_SPD_SA1
MEM_B_DQ<31>
MEM_B_DQ<52>
MEM_CLK_P<3>
=PP1V8_S3_MEM
=PPSPD_S0_MEM
MEM_B_DQ<48>
MEM_B_DQ<41>
MEM_B_DM<5>
C2908
1
2
C2900
1
2
R2900
1
2
C2909
1
2
C2910
1
2
C2911
1
2
C2915
1
2
C2914
1
2
C2913
1
2
C2912
1
2
C2919
1
2
C2918
1
2
C2917
1
2
C2916
1
2
C2923
1
2
C2922
1
2
C2921
1
2
C2920
1
2
J2900
102101
105
9089
100
99
9897
94
92
93
91
107
106
85
113
30 32
164 166
79
10
26
52
67
130
147
170
185
5 7
35 37
20 22
36 38
43 45
55 57
17
44 46
56 58
61 63
73 75
62 64
19
74 76
123 125
135 137
124 126
134 136
4
141 143
151 153
140 142
152 154
157 159
6
173 175
158 160
174 176
179 181
189 191
14
180 182
192 194
16
23 25
13
11
31
29
51
49
70
68
131
129
148
146
169
167
188
186
201
202
203
204
205
116
86
84
80
119
115
50
69
83
120
163
114
108 110
198 200
197
195
81 82
117 118
87 88
95 96
103 104
111 112
199
1 2 3
27 28
33 34
39 40
41 42
47 48
8
53 54
59 60
65 66
71 72
77 78
121 122
127 128
132
133
138
139
144
9
145
149 150
155 156
161 162
165
168
171
12
172
177 178
183 184
187
190
193
196
15
18
21
24
109
C2950
1
2
C2952
1
2
C2951
1
2
29 28
6
15
15
15
28
5
29 28
6 5
15
15
5
15
15
15
5
15
15
15
15
15
15
5
15
15
15
5
15
15
5
15
5
15
15
15
5
15
5
15
15
15
5
15
15
15
30 14
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 14
30 14
15
15
15
5
15
5
15
15
15
5
15
15
15
15
15
28 27
28 27
15
15
15
5
15
15
15
15
15
14
15
15
15
15
59 28
15
15
15
5
15
15
15
5
15
5
15
30 14
15
15
15
15
15
29 28
6 5
5
5
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 15
30 14
30 14
30 15
15
15
15
15
5
15
15
5
15
15
5
15
5
15
14
14
15
15
15
5
15
5
15
5
15
15
15
14
29 28
6 5
29 28
6
15
5
15
15
Page 30
IN
IN
IN
IN
IN IN IN IN IN IN IN IN IN IN IN IN IN IN
IN
IN
IN
IN
IN IN IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
One cap for each side of every RPAK, one cap for every two discrete resistors BOMOPTION shown at the top of each group applies to every part below it
402
MF-LF1/16W
5%
56
1/16W
56
402
MF-LF
5%
1/16W
56
5%
402
MF-LF
56
5%
1/16W MF-LF
402
56
402
MF-LF1/16W
5%
0
2
1
0.1uF
402
CERM
10V
20% 20%
CERM 402
0.1uF
10V
0.1uF
402
CERM
10V
20%
0.1uF
402
CERM
10V
20%
0.1uF
10V
402
CERM
20%
0.1uF
20% 10V CERM 402
0.1uF
20% 10V CERM 402
56
SM-LF
1/16W
5%
56
SM-LF
1/16W
5%
56
SM-LF
1/16W
5%
56
SM-LF
1/16W
5%
1/16W
56
SM-LF
5%
56
SM-LF
1/16W
5%
56
SM-LF
1/16W
5%
1/16W
56
SM-LF
5%
56
1/16W
SM-LF
5%
56
SM-LF
1/16W
5%
56
SM-LF
1/16W
5%
56
SM-LF
1/16W
5%
56
5%
1/16W
SM-LF
5%
1/16W
56
SM-LF
56
1/16W
5%
SM-LF
1/16W
56
5%
SM-LF
56
1/16W
5%
SM-LF
5%
1/16W
56
SM-LF
5%
1/16W
56
SM-LF
56
5%
1/16W
SM-LF
5%
1/16W
56
SM-LF
56
1/16W
5%
SM-LF
1/16W
5%
SM-LF
56
56
5%
1/16W
SM-LF
5%
1/16W
56
SM-LF
1/16W
5%
SM-LF
56
1/16W
SM-LF
5%
56
1/16W
SM-LF
56
5%
5%
1/16W
56
SM-LF
5%
1/16W
56
SM-LF
56
1/16W
5%
SM-LF
5%
1/16W
56
SM-LF
56
1/16W
5%
SM-LF
1/16W
5%
56
SM-LF
1/16W
5%
56
SM-LF
5%
1/16W
56
SM-LF
56
1/16W
5%
SM-LF
56
1/16W
5%
SM-LF
5%
1/16W
56
SM-LF
56
1/16W
5%
SM-LF
SM-LF
5%
1/16W
56
SM-LF
56
1/16W
5%
5%
1/16W
SM-LF
56
56
1/16W
5%
SM-LF
5%
1/16W
56
SM-LF
1/16W
5%
SM-LF
56
56
1/16W
5%
SM-LF
0.1uF
20% 10V CERM 402
0.1uF
402
CERM
10V
20%
0.1uF
20% 10V CERM 402
0.1uF
20% 10V CERM 402
0.1uF
20% 10V CERM 402
0.1uF
20% 10V CERM 402
0.1uF
20% 10V CERM 402
0.1uF
20% 10V CERM 402
0.1uF
20% 10V CERM 402
0.1uF
20% 10V
402
CERM
0.1uF
20% 10V CERM 402
20% 10V CERM 402
0.1uF
0
1
0
1
1
0
2
0
1
2
3
4
5
6
7
10
11
9
8
13
12
2
3
2
3
0.1uF
20% 10V CERM 402
0.1uF
20% 10V CERM 402
0.1uF
CERM 402
20% 10V
0.1uF
402
CERM
10V
20%
0.1uF
20% 10V CERM 402
0.1uF
402
CERM
10V
20%
0.1uF
402
CERM
10V
20%
0
1
2
3
Memory Active Termination
30 97
??
051-7032
MEM_A_A<13..0>
MEM_B_BS<2..0>
MEM_CS_L<3..0>
MEM_CKE<3..0>
MEM_ODT<3..0>
MEM_A_BS<2..0>
=PP0V9_S0_MEM_TERM
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_A_WE_L
MEM_B_A<0> MEM_B_A<3>
MEM_A_CAS_L
MEM_B_RAS_L
MEM_B_WE_L
MEM_B_CAS_L
MEM_B_A<2>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<1>
MEM_B_A<4>
MEM_B_A<10>
MEM_A_RAS_L
C3033
1
2
C3030
1
2
C3011
1
2
C3010
1
2
C3007
1
2
C3005
1
2
C3035
1
2
R3001
1 2
R3009
1 2
R3011
1 2
R3025
1 2
R3035
1 2
C3004
1
2
C3006
1
2
C3008
1
2
C3009
1
2
C3013
1
2
C3014
1
2
C3015
1
2
RP3000
3 6
RP3000
4 5
RP3000
1 8
RP3000
2 7
RP3001
2 7
RP3001
1 8
RP3001
4 5
RP3001
3 6
RP3002
4 5
RP3002
1 8
RP3002
2 7
RP3002
3 6
RP3003
1 8
RP3003
2 7
RP3003
3 6
RP3003
4 5
RP3004
1 8
RP3004
3 6
RP3004
4 5
RP3005
1 8
RP3005
2 7
RP3005
3 6
RP3005
4 5
RP3006
1 8
RP3006
2 7
RP3006
3 6
RP3007
4 5
RP3007
3 6
RP3007
2 7
RP3007
1 8
RP3008
4 5
RP3008
3 6
RP3008
2 7
RP3008
1 8
RP3009
1 8
RP3009
2 7
RP3009
3 6
RP3009
4 5
RP3010
3 6
RP3010
2 7
RP3010
1 8
RP3010
4 5
RP3011
1 8
RP3011
2 7
RP3011
4 5
RP3006
4 5
RP3011
3 6
C3031
1
2
C3032
1
2
C3043
1
2
C3036
1
2
C3037
1
2
C3038
1
2
C3001
1
2
C3000
1
2
C3040
1
2
C3039
1
2
C3042
1
2
C3041
1
2
28 15
29 15
29 28 14
29 28 14
29 28 14
28 15
6
29 15
29 15
29 15
29 15
29 15
28 15
29 15
29 15
28 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
29 15
28 15
Page 31
VREF
VTT
GND
VTT_IN
EN
VTTS
VDDQ
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
USING 1% FR BOM CONSOLIDATION
disable MEMVTT in sleep.
?Can 5V be S0 if 1V8 is S3?
If power inputs are not S0,
Page Notes
MEMVTT_EN can be used to
- =PP0V9_S0_MEMVTT_LDO
- =PP1V8_S0_MEMVTT
- =PP5V_S0_MEMVTT
BOM options provided by this page:
Signal aliases required by this page:
Power aliases required by this page:
(NONE)
(NONE)
DDR2 Vtt Regulator
805-1
CERM
10UF
20%
6.3V
MSOP-8
BD3533FVM
CRITICAL
5% 1/16W MF-LF
402
1K
MEMVTT_EN_PU
6.3V POLY
20%
150UF
SMC-LF
CRITICAL
805-1
CERM
10UF
20%
6.3V
1%
221
1/16W MF-LF
402
6.3V
2.2UF
10%
CERM1
603
20%
0.1UF
10V
CERM
402
402
CERM
1uF
10%
6.3V
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
31 97
??
051-7032
Memory Vtt Supply
U3100_VDDQ
MEMVTT_EN
=PP5V_S0_MEMVTT
MEMVTT_VREF
=PP0V9_S0_MEMVTT_LDO
=PP1V8_S0_MEMVTT
C3100
1
2
C3101
1
2
U3100
2
1
65
4
8
7
3
R3100
1
2
C3105
C3102
1
2
R3101
1 2
C3109
1
2
C3110
1
2
79
6
6
6
Page 32
VTT_PWRGD*/PD
DOT96T/27MHZ_NON-SPREAD
SRCT_0/LCD100MT
CPUC2_ITP/SRCC_10
VDD48
XIN
VDD_PCI1
VDD_SRC0
VDD_REF
VDD_SRC1
VDD_SRC2
VDD_SRC3
REF1/FCTSEL0
REF0/FSC
FSA/48M
DOT96C/27MHZ_SPREAD
CLKREQ_8*
SRCT_8
SRCC_8
SRCT_7
SRCC_7
CLKREQ_6*
CPUT2_ITP/SRCT_10
IREF
SDATA
SCLK
VSS_REF
VSS_PCI1
VSS_PCI0
VSS_CPU
VSS48
VSS_SRC
PCIF1
PCI1
SRCT_5
THRML_PAD
PCI4
PCI2
FSB
CLKREQ_4*
SRCC_5
SRCC_4 SRCT_4
SRCT_3
CLKREQ_3*
SRCC_3
SRCC_2 SRCT_2
SRCC_1
CLKREQ_1*
SRCT_1
SRCC_0/LCD100MC
CPUC1 CPUT1
CPUC0 CPUT0
PCI_STP* CPU_STP*
SRCC_6
CLKREQ_5*
SRCT_6
PCIF0/ITP_SEL
PCI5/FCTSEL1
PCI3
XOUT
VDDA VSSA
VDD_PCI0
VDD_CPU
IN IN
OUT OUT
OUT
OUT
OUT OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT OUT
IN IO
OUT
IN
IO
IO
OUT
OUT
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
OUT
OUT
OUT
OUT
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(INT PU)
(INT PU)
(INT PD)
PIN 7
DOT96C
SPREAD
27M
(NO USED)
(PULL UP PIN 68 TO ENABLE ITP HOST CLK)
(ICH SM BUS)
(ICH7M PCI 33MHZ)
(PORT80 LPC 33MHZ)
0
(INT PU)
(FOR PCI-E CARD)
(ICH7M,SIO,LPC REF. 14.318MHZ)
(INT PD)
(GMCH G_CLKIN 100 MHZ )
(FROM ICH7 GPIO18 STPPCI* ) (FROM ICH7 GPIO20 STPCPU* )
(GMCH HOST 133/167MHZ)
(ITP HOST 133/167MHZ)
(GMCH D_REFSSCLKIN DISPLAY PLL B 100MHZ)
PROTO TO REMOVE 100M FROM SIGNAL NAME)
(SIGNAL NAME WILL BE CHANGED POST
(INT PU)
(CPU HOST 133/167MHZ)
(NOT USED )
(INT PD)
(INT PU)
PIN 6
* FOR EXT. GRAPHIC SYSTEM
* FOR INT. GRAPHIC SYSTEM
SRCT0
SRCT0
DOT96T
DOT96T
PIN 10 PIN 11
100MC_SST
FCTSEL1
00 0 1 1 1 1
OFF LOW
27M NON SPREAD
DOT96C 100MT_SST
SRCT0
SRCC0
SRCC0
SRCC0
FCTSEL0
(INT PU)
(ICH SATA 100 MHZ)
(FW PCI 33MHZ) (TPM LPC 33MHZ) (SMC LPC 33MHZ)
(PLACED 0.1UF NEAR THE RELATIVE POWER PIN)
(EACH POWER PIN PLACED ONE 0.1UF)
(INT PU) (INT PU)
(GPU PCI-E 100 MHZ )
NEED TO DECIDE THE CLKREQ CONNECTION,TO GPIO?
(ICH7M DMI 100 MHZ )
(FROM ICH7 GPIO35)
(FROM GMCH CLK_REQ*)
(WIRELESS PCI-E 100 MHZ )
(GIGA LAN PCI-E 100 MHZ )
(GMCH D_REFCLKIN DISPLAY PLL A 96MHZ)
(FROM CPU VCORE PWR GOOD) (ICH7M USB 48MHZ)
603
X5R
20%
6.3V
10UF
FERR-120-OHM-1.5A
0402
402
0.1UF
10% X5R
16V
10% 16V X5R 402
0.1UF
16V X5R
0.1UF
10% 402
10% 402
0.1UF
16V X5R
CRITICAL
OMIT
CY284455
402
15PF
5% CERM
50V
402
5%
15PF
50V CERM
MF-LF
1%
475
402
1/16W
805-1
10UF
CERM
6.3V
20%
16V
0.1UF
402
X5R
10%
0.1UF
402
10% 16V X5RX5R
16V 402
0.1UF
10%
0.1UF
10% 16V X5R 402402
X5R
16V
0.1UF
10%
1UF
6.3V CERM
10%
402
603
X5R
6.3V
20%
10UF
10% X5R
16V 402
0.1UF
FERR-120-OHM-1.5A
0402
1UF
10% CERM
6.3V 402
402
MF-LF
1/16W
5%
2.2
402
1/16W
5%
MF-LF
1
603
X5R
6.3V
20%
10UF
MF-LF
402
2.2
5%
1/16W
10K
5% MF-LF
402
1/16W
CRITICAL
14.31818
5X3.2-SM
??
051-7032
33 97
CLOCKS
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK410_VDD_CPU_SRC
CK410_CPU1_N
=PP3V3_S0_CK410
CK410_XTAL_OUT
VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm
PP3V3_S0_CK410_VDDA
CK410_PCI4_CLK
CK410_DOT96_27M_N CK410_DOT96_27M_P
CK410_USB48_FSA
CK410_CPU2_ITP_SRC10_P
CK410_CPU0_N
PM_STPCPU_L
PM_STPPCI_L
CK410_CPU1_P
PP3V3_S0_CK410_VDD_REF
VOLTAGE=3.3V MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm
CK410_PCI5_FCTSEL1
CK410_PCIF1_CLK
CK410_IREF
SMB_CK410_DATA
CK410_SRC5_P
CLK_NB_OE_L
CK410_SRC_CLKREQ6_L
CK410_CPU0_P
=PP3V3_S0_CK410
CK410_PCI2_CLK
CK410_SRC_CLKREQ1_L
CK410_SRC2_N
CK410_SRC3_P
CK410_LVDS_P
CK410_LVDS_N
CK410_CPU2_ITP_SRC10_N
SMB_CK410_CLK
CK410_SRC_CLKREQ3_L
CK410_SRC1_P
SB_CLK100M_SATA_OE_L
CK410_SRC5_N
CK410_SRC4_P
CK410_SRC4_N
CK410_SRC8_N
CK410_SRC7_P
CK410_SRC7_N
CK410_SRC6_N CK410_SRC6_P
CK410_PCI3_CLK
CK410_SRC3_N
CK410_SRC2_P
=PP3V3_S0_CK410
PP3V3_S0_CK410_VDD48
MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V
CK410_SRC1_N
CK410_FSB_TEST_MODE
CK410_PCI1_CLK
CK410_XTAL_IN
CK410_PCIF0_CLK
CK410_REF1_FCTSEL0
CK410_CLK14P3M_TIMER
CK410_PD_VTT_PWRGD_L
CK410_SRC_CLKREQ8_L
CK410_SRC8_P
PP3V3_S0_CK410_VDD_PCI
MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V
C3309
1
2
C3305
1
2
L3302
1 2
C3306
1
2
C3307
1
2
C3308
1
2
U3301
9
59
20
60
25
34
55
44
41
36
45
42
37
7 6
4
8
40
57 58 63 64 65
56
68
1
54 53
47 48
11
14
16
19
22
24
27
30
32
10
13
15
18
21
23
26
29
33
69
34361674912172835
38
5
46
62 66
52
31
39
2
51 50
C3390
1
2
C3389
1
2
R3300
1
2
C3312
1
2
C3311
1
2
C3304
1
2
C3303
1
2
C3302
1
2
C3301
1
2
C3310
1
2
C3316
1
2
C3315
1
2
L3301
1 2
C3314
1
2
R3302
1 2
R3303
1 2
C3317
1
2
R3304
1 2
R3301
1
2
Y3301
1 2
34
33
6
34
34
34
34
34
34
23
23
34
34
34
27
34
14
53
34
33
6
34
34
34
34
34
34
34
27
34
34
23
34
34
34
34
34
34
34
34
34
34
34
33
6
34
34
34
34
34
34
26
34
34
Page 33
OUT
OUT
OUT OUT
OUT OUT
IN IN
IN
IN
IN
IN
IN IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IO
OUT
IN
OUT
IN
IN
IN
IN
IN
OUT OUT
OUT OUT
OUT OUT
OUT
OUT
OUT OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(GPU CLK OE*)
(YUKON CLK OE*)
(SPARE CLK OE*)
FSB FREQUENCY SELECT:
CPU DRIVEN
(133MHZ CPU CLK)
STUFF
R3459
R3454
R3461
R3457
R3452
R3463
R3457
R3463
R3459
R3454
NO STUFF
R3454 R3459 R3463
R3452 R3457 R3461
R3452 R3461
(166MHZ CPU CLK)
533MHZ
667MHZ
NO GPU SO LEAVE THIS CLK NOT CONNECTED AND DISABLE THE OUTPUT IN THE CLOCK CHIP
NOTE: USE THESE PULL-DOWNS IF NOT CONNECTED TO GPIO’S
402
33
1/16W5%MF-LF
33 33
33
33
33
33
33 33
33 33
33 33
33 33
33 33
33 33
33 33
33 33
MF-LF
1/16W
402
1%
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
49.9
402
MF-LF1/16W1K5%
402
MF-LF
1/16W
5%
1K
2.2K
5% 1/16W MF-LF
402
5% 1/16W MF-LF
0
402
0
MF-LF
1/16W
5%
402
NOSTUFF
1/16W MF-LF
0
5%
402
NOSTUFF
MF-LF
1/16W
5%
1K
402
0
5% 1/16W MF-LF 402
1/16W1KMF-LF5%402
1/16W
5% MF-LF
56
402
NOSTUFF
0
MF-LF
1/16W
5%
402
5%
1K
1/16W MF-LF
402
1K
5%
1/16W MF-LF
402
33 33
MF-LF1K402
5%
1/16W
402
MF-LF
1/16W
5%
2.2K
MF-LF
33
1/16W
5%
402
33
1K
1K
1K
33
33
33
33
49.9
49.9
49.9
49.9
33 33
49.9
49.9
49.9
49.9
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
??
051-7032
34 97
CLOCKS: TERMINATIONS
NC_CK410_SRC1_P
NO_TEST=TRUE
MAKE_BASE=TRUE
CK410_SRC3_P
SPARE_SRC7_P SPARE_SRC7_N
SPARE_SRC3_N
CK410_PCI3_CLK
CK410_PCI2_CLK
CK410_PCI1_CLK
CK410_PCIF1_CLK
PCI_CLK_PORT80
CK410_SRC1_N
NC_CK410_SRC1_N
NO_TEST=TRUE
MAKE_BASE=TRUE
CK410_SRC1_P
CK410_SRC7_N
CK410_SRC7_P
CK410_SRC4_N
NB_CLK_DREFCLKIN_P NB_CLK_DREFCLKIN_N
NB_CLK100M_GCLKIN_N
NB_CLK100M_GCLKIN_P
AIRPORT_CLK100M_PCIE_N
SB_CLK100M_DMI_N
ENET_CLK100M_PCIE_N
ENET_CLK100M_PCIE_P
CK410_DOT96_27M_P CK410_DOT96_27M_N
SB_CLK100M_DMI_P
CK410_FSA
NB_BSEL<0>
CPU_BSEL<0>
PP1V05_S0
CPU_BSEL<2>
NB_BSEL<2>
NB_BSEL<1>
FSB_CLK_CPU_N
AIRPORT_CLK100M_PCIE_P
FSB_CLK_XDP_N
FSB_CLK_XDP_P
NB_CLK100M_GCLKIN_P NB_CLK100M_GCLKIN_N
AIRPORT_CLK100M_PCIE_N
SB_CLK100M_DMI_P SB_CLK100M_DMI_N
SB_CLK100M_SATA_P
ENET_CLK100M_PCIE_N
ENET_CLK100M_PCIE_P
PP1V05_S0
PP1V05_S0
CK410_FSB_TEST_MODE
CPU_BSEL<1>
CK410_FSC
PCI_CLK_SMC
PCI_CLK_TPM
PCI_CLK_FW
PCI_CLK_SB
AIRPORT_CLK100M_PCIE_P
SB_CLK100M_SATA_P SB_CLK100M_SATA_N
CK410_PCIF0_CLK
CK410_SRC6_P
CK410_SRC4_P
CK410_SRC5_N
CK410_SRC5_P
CK410_SRC2_P
CK410_USB48_FSA
SB_CLK48M_USBCTLR
CK410_FSA
SB_CLK14P3M_TIMER
CK410_FSC
CK410_PCI4_CLK
TP_PCI_CLK_SPARE
CK410_REF1_FCTSEL0
TP_CLK14P3M_SPARE
CK410_SRC_CLKREQ3_L
CK410_SRC_CLKREQ1_L
CK410_SRC_CLKREQ8_L
FSB_CLK_CPU_N
FSB_CLK_NB_N
FSB_CLK_CPU_P
FSB_CLK_NB_P
SPARE_SRC3_P
CK410_SRC3_N
MAKE_BASE=TRUE
FSB_CLK_XDP_P
MAKE_BASE=TRUE
FSB_CLK_XDP_N CPU_XDP_CLK_N
CK410_SRC6_N
FSB_CLK_CPU_P
FSB_CLK_NB_P FSB_CLK_NB_N
CK410_PCI5_FCTSEL1
CK410_CLK14P3M_TIMER
CK410_CPU1_P CK410_CPU1_N
CK410_CPU0_P CK410_CPU0_N
CK410_CPU2_ITP_SRC10_P CK410_CPU2_ITP_SRC10_N
CK410_SRC8_P CK410_SRC8_N
CK410_LVDS_P CK410_LVDS_N
NB_CLK_DREFSSCLKIN_P NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFSSCLKIN_N
NB_CLK_DREFSSCLKIN_P
NB_CLK_DREFCLKIN_N
NB_CLK_DREFCLKIN_P
SB_CLK100M_SATA_N
CPU_XDP_CLK_P
CK410_SRC2_N
TP_CK410_PCI5_FCTSEL1
R3400
1 2
R3401
1 2
R3402
1 2
R3403
1 2
R3404
1 2
R3405
1 2
R3406
1 2
R3407
1 2
R3408
1 2
R3409
1 2
R3410
1 2
R3411
1 2
R3412
1 2
R3413
1 2
R3414
1 2
R3415
1 2
R3416
1 2
R3417
1 2
R3418
1 2
R3419
1 2
R3420
1 2
R3421
1 2
R3422
1 2
R3429
1 2
R3430
1 2
R3431
1 2
R3432
1 2
R3433
1 2
R3434
1 2
R3435
1 2
R3436
1 2
R3437
1 2
R3438
1 2
R3439
1 2
R3440
1 2
R3441
1 2
R3442
1 2
R3443
1 2
R3444
1 2
R3462
1 2
R3460
1
2
R3451
1 2
R3463
1
2
R3461
1
2
R3457
1
2
R3456
1
2
R3459
1
2
R3458
1 2
R3452
1
2
R3454
1
2
R3453
1 2
R3455
1 2
R3471
1 2
R3470
1 2
R3499
1 2
R3497
1 2
R3498
1 2
R3496
1 2
R3495
1 2
R3494
1 2
R3493
1 2
R3492
1 2
R3489
1 2
R3490
1 2
R3491
1 2
R3487
1 2
R3488
1 2
R3486
1 2
R3485
1 2
R3425
1 2
R3426
1 2
R3447
1 2
R3448
1 2
R3449
1 2
R3450
1 2
33
33
33
33
33
60
33
33
33
33
33
34 14
5
34 14
5
34 14
5
34 14
5
53 34
34 22
5
41 34
5
41 34
5
33
33
34 22
5
34
14
7
80 34
6
7
14
14
34
7 5
53 34
34
34
34 14
5
34 14
5
53 34
34 22
5
34 22
5
34 21
5
41 34
5
41 34
5
80 34
6
80 34
6
33
7
34
58
67
44
22
5
53 34
34 21
5
34 21
5
33
33
33
33
33
33
33
23
5
34
23
5
34
33
5
33
33
33
33
34
7 5
34 12
5
34
7 5
34 12
5
33
34
34 11
33
34
7 5
34 12
5
34 12
5
33
33
33
33
33
33
33
33
33
33
33
33
34 14
5
34 14
5
34 14
5
34 14
5
34 14
5
34 14
5
34 21
5
11
33
Page 34
OUT
OUT
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(SB_GPIO14)
PULL UP TO 5V ON P26
PLACE SHORT AT PACKAGE
FROM SB WITHIN EACH PAIR
CAPS TO BE SAME DISTANCE
SATA PORT 0 IS NOT USED
NOTE: GO TO SB AND SMC
PATA CONNECTOR
SATA CONNECTOR
518S0251
SATA DIFF PAIR GND VIAS
"IDE ACTIVE"
PER ATA7 SPEC
516S0327
NC NC
NC
NC
NC
NC
Obsolete
MIN_NECK & MIN_LINE WIDTH
PLACE C3805-06 CLOSE TO JC901 FOR PP5V_S0_PATA. APPLY A WIDE TRACE SHAPE FROM JC901 TO C3805-06.
ARE CONTROLLED BY PP5V_S0 1MM / 0.6MM.
NOTE: ATA-2, NOW OBSOLETE
Per ATA Spec
Per ATA Spec
STUFFED PER LARRY
NOTE: ???
VALUE=3900PF IN REFERENCE SCHEM
PLACE < 0.5 IN FROM BALL OF U2100
REMOVED TEST POINTS FROM SHORT TRACE BETWEEN CAP AND CONNECTOR TO IMPROVE SIGNAL INTEGRITY.
NO STUFF
10K
1K
4.7K
5%
50V
CERM
402
10pF
NO STUFF
402
1/16W
6.2K
5% MF-LF
5% 1/16W MF-LF 402
0
DEVELOPMENT
1/16W MF-LF
402
1%
499
M-ST-SM
EP00-081-91
CRITICAL
GREEN-3.6MCD
DEVELOPMENT
2.0X1.25MM-SM
F-ST-SM
CRITICAL
804RVS-0501S5RGM
402
10V
CERM
20%
0.1uF
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
HOLE-VIA-P5RP25
0
805-2
10V
10UF
20% CERM
402
0.0047UF
0.0047UF
402
0.0047UF
402
402
0.0047UF
NOSTUFF
10K
100
MF-LF
1/16W
5%
402
24.9
1/16W MF-LF
402
1%
0
5% 1/16W MF-LF 402
15K
402
MF-LF
1/16W
5%
0
402
MF-LF
1/16W
5%
0
NO STUFF
38 97
051-7032
??
Disk Connectors
SATA_C_R2D_N
NO_TEST=TRUE
SATA_C_R2D_P
NO_TEST=TRUE
MAKE_BASE=TRUE
SATA_RBIAS
SATA_A_R2D_C_N
IDE_RESET_L_CONN
=PP5V_S0_PATA
IDE_IOCS16_PU
IDE_CSEL_PD
IDE_PDD<8> IDE_PDD<9> IDE_PDD<10> IDE_PDD<11> IDE_PDD<12>
IDE_PDD<15>
IDE_PDIOR_L
IDE_PDA<0> IDE_PDA<2>
IDE_DASP_L_DS
SATA_C_R2D_C_P
SATA_C_D2R_P
SATA_C_R2D_C_N
SATA_C_D2R_N
NO_TEST=TRUE
SATA_C_D2R_C_N
NO_TEST=TRUE
SATA_C_D2R_C_P
=PP3V3_S0_PATA
TP_SATA_A_R2D_N
MAKE_BASE=TRUE
TP_SATA_A_R2D_P
MAKE_BASE=TRUE
TP_SATA_A_D2R_P
MAKE_BASE=TRUE
TP_SATA_A_D2R_N
MAKE_BASE=TRUE
SATA_A_D2R_P
SATA_A_D2R_N
SATA_C_DET_L
IDE_PDD<14>
IDE_PDDACK_L
IDE_PDD<13>
IDE_PDD<6>
IDE_PDD<7>
IDE_PDD<0>
IDE_PDD<1>
IDE_PDD<5>
IDE_DASP_L
IDE_PDCS3_L
IDE_PDD<4> IDE_PDD<3> IDE_PDD<2>
IDE_PDDREQ
=PP5V_S0_PATA
SATA_RBIAS_N
SATA_RBIAS_P
SATA_A_R2D_C_P
IDE_PDCS1_L
IDE_PDA<1>
IDE_IRQ14
IDE_PDIORDY
IDE_PDIOW_L
IDE_RESET_L_CONN
MAKE_BASE=TRUE
SB_GPIO14
IDE_RESET_L
SB_GPIO3
R3852
1
2
R3853
1
2
R3851
1
2
C3804
1
2
R3859
1
2
R3858
1
2
R3857
1
2
JC900
1 2 3 4 5 6 7
LED3800
1 2
JC901
51
52
1
10 11 12 13 14 15 16 17 18 19
2
20 21 22 23 24 25 26 27 28 29
3
30 31 32 33 34 35 36 37 38 39
4
40 41 42 43 44 45 46 47 48 49
5506 7 8 9
C3805
1
2
GV3808
1
GV3806
1
GV3801
1
GV3803
1
GV3805
1
GV3807
1
GV3802
1
GV3804
1
C3806
1
2
C3800
1 2
C3801
1 2
C3802
1 2
C3803
1 2
R3824
1
2
R3899
1
2
R3897
1 2
R2389
1
2
R3800
1 2
R3801
1 2
21
38
38
6
21
21
5
21
21
21
21
21
5
21 21
21
21
21
21
6
21
21
23
21
21
21
21
21
21
21
21
21
21
21
21
21
38
6
21
21
21
21
21
21
21
5
21
38
23
26 22
Page 35
OUT
OUT
AVDDL0
AVDDL4
AVDD
THRML_PAD
VDDO_TTL0
AVDDL6
VDDO_TTL1
RX_N
TESTMODE
TSTPT
LINK*
LED_LINK10/100* LED_LINK1000*
LED_ACT*
RSET
CTRL25 CTRL12
HSDACN
HSDACP
SWITCH_VAUX
SWITCH_VCC
VMAIN_AVLBL
VAUX_AVLBL
LOM_DISABLE*
XTALO
XTALI
SPI_DO
SPI_CLK
SPI_CS
SPI_DI
VPD_CLK
VPD_DATA
MDIP3 MDIN3
MDIN2
MDIP2
MDIN1
MDIP1
MDIN0
MDIP0
WAKE*
REFCLKN
TX_N
VDDO_TTL3
VDDO_TTL2
VDDO_TTL4
VDD0
VDD1
VDD3
VDD2
VDD6
VDD5
VDD4
VDD7
AVDDL1
AVDDL2
AVDDL5
VDD25
PERST*
REFCLKP
RX_P
AVDDL3
TX_P
PU_VDDO_TTL0 PU_VDDO_TTL1
TEST
TEST
TWSI
MAIN CLK
PCI EXPRESS
ANALOG
MEDIA
E2
WC*
NC0
NC1
VCC
VSS
SCL
SDA
IO
IO
IO IO
IO
IO
IO IO
IN IN
IN
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
NC
NC
NC
OPTIONAL EXTERNAL LDO
LAYOUT NOTE: PLACE C4112-13 AT U2100
LAYOUT NOTE: PLACE C4110-11 AT U4101
50V
5%
27PF
402
CERM
5%
MF-LF
402
1/16W
4.7K
MF-LF
4.7K
402
5%
1/16W
16V 402
X5R
10%
0.1UF
OMIT
88E8053
QFN
M24C08
SO8
OMIT
16V
10% 402
X5R
0.1UF
0.1UF
402
10V
CERM
20%
402
CERM
10V
0.1UF
20%
CERM
0.1UF
20% 10V
402
0.1UF
20% 10V
CERM
402
MF-LF
4.75K
402
1%
1/16W
4.7K
4.7K
0
MF-LF
402
5%
1/16W
NOSTUFF
MF-LF
1/16W
0
5%
402
SM-3.2X2.5MM
CRITICAL
25.0000M
402
MF-LF
1/16W 1%
49.9
402
MF-LF
1/16W 1%
49.9
402
MF-LF
1/16W 1%
49.9
402
MF-LF
1/16W 1%
49.9
MF-LF
49.9
1%
1/16W
402
MF-LF
1/16W
1%
402
49.9
49.9
1/16W
MF-LF
402
1%
MF-LF
1/16W
1%
402
49.9
4.7K
1/16W
5%
402
MF-LF
CERM 402
10% 50V
0.001UF
0.001UF
CERM 402
10% 50V
50V
0.001UF
CERM 402
10%
0.001UF
CERM 402
10% 50V
CERM 402
10% 50V
0.001UF
10%
0.1UF
402
16V X5R
0.1UF
X5R 402
10% 16V
0.1UF
X5R 402
10% 16V
CERM 402
10% 50V
0.001UF
10%
0.1UF
X5R 402
16V
CERM
50V
0.001UF
402
10% 10%
0.001UF
CERM 402
50V50V
CERM
0.001UF
402
10%
10%
0.001UF
CERM 402
50V
0.1UF
402
X5R
10% 16V
0.1UF
10% X5R
402
16V
10%
0.1UF
X5R 402
16V 16V
0.1UF
X5R 402
10%
CERM 402
0.001UF
10% 50V
0.001UF
CERM 402
10% 50V
0.1UF
X5R 402
10% 16V
402
X5R
10% 16V
0.1UF0.1UF
X5R 402
10% 16V
50V
5%
27PF
CERM 402
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
??
051-7032
9741
ETHERNET CONTROLLER
PCIE_ENET_R2D_N
PCIE_ENET_R2D_P
ENET_XTALI ENET_XTALO
ENET_VPD_CLK ENET_VPD_DATA
ENET_PU_VDDO_TTL0
=PP1V2_S3_ENET
ENET_MDI0
ENET_MDI_N<1>
ENET_MDI1
=PP2V5_S3_ENET
=PP3V3_S3_ENET
ENET_PU_VDDO_TTL1
VMAIN_AVLBL
=PP3V3_S3_ENET
ENET_LOM_DIS_L
ENET_LED_LINK10_100_L ENET_LED_LINK1000_L
PCIE_ENET_R2D_C_N
ENET_ANALOG_RSET
ENET_LED_LINK_L
=PP2V5_S3_ENET
ENET_CTRL25 ENET_CTRL12
ENET_CLK100M_PCIE_P
ENET_MDI2 ENET_MDI3
ENET_VPD_CLK
ENET_VPD_DATA
=PP3V3_S3_ENET
=PP3V3_S3_ENET
ENET_MDI_P<0> ENET_MDI_N<0>
ENET_MDI_P<1>
ENET_MDI_P<2>
ENET_MDI_P<3> ENET_MDI_N<3>
=PP1V2_S3_ENET
=PP3V3_S3_ENET
PCIE_ENET_D2R_C_N
PCIE_ENET_D2R_C_P
PCIE_ENET_D2R_N
PCIE_ENET_D2R_P
ENET_CLK100M_PCIE_N
PCIE_WAKE_L
ENET_GATED_RST_L
PCIE_ENET_R2D_C_P
ENET_MDI_N<2>
PP3V3_S0
ENET_LED_ACT_L
C4115
1
2
C4116
1
2
R4102
1 2
R4119
1 2
R4118
1 2
R4120
1 2
R4117
1 2
R4103
1 2
R4104
1 2
R4105
1 2
R4106
1 2
R4101
1 2
C4106
1
2
C4107
1
2
C4117
1
2
C4118
1
2
C4105
1
2
C4104
1
2
C4103
1
2
C4102
1
2
C4150
1
2
C4128
1
2
C4133
1
2
C4134
1
2
C4131
1
2
C4132
1
2
C4127
1
2
C4126
1
2
C4129
1
2
C4130
1
2
C4139
1
2
C4138
1
2
C4137
1
2
C4136
1
2
C4135
1
2
R4122
1 2
R4123
1 2
C4101
1
2
U4101
23
19222832515257
3
4
25
24
59 60 62 63
10
18
21
27
31
17
20
26
30
5
42 43
56
55
16
53
54
37 36
35 34
9
11
46
65
29
50
49
12
27136433
394448
58
18404561
47
38 41
6
15 14
U4102
3
1
2
6
5
8
4
7
C4140
1
2
C4110
1 2
C4111
1 2
C4112
1 2
C4113
1 2
R4130
1 2
R4131
1 2
R4151
1 2
R4150
1 2
Y4101
24
13
41
41
42 41
43
42 41
43 42 41
6
43 42 41
6
43
43
54
43
42 41
42
42
34
5
41
41
43 42 41
6
43 42 41
6
43
43
43
43
43
43
42 41
43 42 41
6
54
54
34
5
53 23
42
54
43
94 83 76 61 59 26 10
6
43
Page 36
IN
IN
IN
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
20%
6.3V X5R 805
22UF
20% CERM
6.3V 603
4.7UF
X5R 402
10% 16V
0.1UF
4.7K
MF-LF
1/16W
5%
402
CERM
20%
6.3V 603
4.7UF
16V
10% X5R
0.1UF
402
16V
10%
402
X5R
0.1UF
603
6.3V
20% CERM
4.7UF
FERR-330-OHM
SM
FERR-330-OHM
SM
I38
805-1
CERM
10UF
20%
6.3V
SOT223
PBSS5540Z
CRITICAL
20%
6.3V X5R 805
22UF
X5R
16V
10%
402
0.1UF
42 97
051-7032
??
ETHERNET MISC
ENET_CTRL12
TP_ENET_CTRL12
MAKE_BASE=TRUE
=PP1V2_S3_LAN
=PP3V3_S3_ENET
MAKE_BASE=TRUE
ENET_RST_L
ENET_GATED_RST_L
ENET_CTRL25
Q4201_3
=PP2V5_S3_ENET
=PP1V2_S3_ENET
VOLTAGE=1.2V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM
MAKE_BASE=TRUE
PP1V2_S3_ENET
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=2.5V
PP2V5_S3_ENET
MAKE_BASE=TRUE
Q4201
1
24
3
C4200
1
2
C4201
1
2
C4202
1
2
C4203
1
2
C4204
1
2
R4202
1
2
C4205
1
2
C4206
1
2
C4210
1
2
C4209
1
2
L4201
1 2
L4200
1 2
C4207
1
2
41
6
43 41
6
6
41
41
41
41
43
Page 37
IO IO
IO
IO IO
IO
IO IO
1CT:1CT
1CT:1CT
MDI_3-
ENET_CTAP
MDI_0+
75 OHM
MDI_0-
MDI_1­MDI_2+ MDI_2-
75 OHM
RJ45
CABLE SIDE
SECONDARY
J4
J8
J7
J6
J5
J1 J2 J3
1CT:1CT
RJ45
CHIP SIDE
ENET_CTAP
MDI_1+
MDI_3+
PRIMARY
SHIELD 1000PF, 2000V
1CT:1CT
75 OHM
75 OHM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
(514-0253)
RESISTOR PADS USED AS PLACEHOLDER FOR INDUCTOR IF NEEDED
0.1UF
10V
20% CERM
402
0.001UF
50V CERM 402
10%
10%
0.001UF
50V
CERM
402
10%
0.001UF
50V CERM 402
MF-LF
5%
0
805
1/8W
F-ANG-TH
OMIT
JFM38V10-0112-4F
DEVELOPMENT
330
603
MF-LF
1/10W
5%
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
603
5% 1/10W MF-LF
330
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
603
5% 1/10W MF-LF
330
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
603
5% 1/10W MF-LF
330
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
0 0 0 0 0 0 0 0
1
CRITICAL
17_INCH_LCD
JD600
514-0340
CON,RJ-45 7 DEGRESS, W/O RIBS
ETHERNET CONNECTOR
43
??
051-7032
97
PP2V5_S3_ENET
ENET_MDI_R_N<3>
ENET_MDI_R_P<3>
ENET_MDI_R_N<2>
ENET_MDI_R_P<2>
ENET_MDI_R_N<1>
ENET_MDI_R_P<1>
ENET_MDI_R_N<0>
ENET_MDI_R_P<0>
ENET_MDI_N<3>
ENET_MDI_P<3>
ENET_MDI_N<2>
ENET_MDI_P<2>
ENET_MDI_N<1>
ENET_MDI_P<1>
ENET_MDI_N<0>
ENET_MDI_P<0>
MAKE_BASE=TRUE
ENET_LED_LINK_L
MAKE_BASE=TRUE
ENET_LED_LINK1000_L
MAKE_BASE=TRUE
ENET_LED_LINK10_100_L
LED4303_1
=PP3V3_S3_ENET
LED4301_1 LED4302_1LED4300_1
MAKE_BASE=TRUE
ENET_LED_ACT_L
GND_CHASSIS_RJ45
MIN_LINE_WIDTH=0.50mm MIN_NECK_WIDTH=0.38mm
PP2V5_ENET_CTAP
VOLTAGE=2.5V
C4300
1
2
C4301
1
2
C4304
1
2
C4305
1
2
R4300
1 2
JD600
11
12
13
1
10
2 3 4
5 6
7 8 9
R4301
1
2
LED4300
1
2
R4302
1
2
LED4301
1
2
R4303
1
2
LED4302
1
2
R4304
1
2
LED4303
1
2
R4350
1 2
R4351
1 2
R4352
1 2
R4353
1 2
R4354
1 2
R4355
1 2
R4356
1 2
R4357
1 2
42
41
41
41
41
41
41
41
41
41
41
41
42 41
6
41
6
Page 38
IO IO
IO
OUT
PCI_AD1
VDD6
PCI_AD24
PCI_AD27
VDD5
XI
XO
RESET*
R1
R0
TPBIAS0
TPA0_P TPA0_N TPB0_P TPB0_N
TPBIAS1
TPA1_P TPA1_N TPB1_P TPB1_N
TPBIAS2
TPA2_P TPA2_N TPB2_P TPB2_N
LPS
CPS
LKON
CNA
NANDTREE
CONTENDER
PC1 PC2
PC0
VAUX_PRESENT
NU2
NU1
MPCIACT*
SE SM
TEST0 TEST1 PTEST
ROM_CLK
ROM_AD
PLLVSS
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS8
VSS7
VSS9
VSS10
VSS11
VSS13
VSS12
VSSA0
VSSA1
VSSA2
VSSA3
CARDBUS*
PCI_INTA*
PCI_RST*
PCI_PME/CSTSCHG*
CLKRUN*
PCI_CLK
PCI_SERR*
PCI_PERR*
PCI_GNT*
PCI_REQ*
PCI_IDSEL
PCI_STOP*
PCI_DEVSEL*
PCI_TRDY*
PCI_IRDY*
PCI_FRAME*
PCI_PAR
PCI_CBE3*
PCI_CBE0* PCI_CBE1* PCI_CBE2*
PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD26
PCI_AD28
PCI_AD25
PCI_AD21 PCI_AD22 PCI_AD23
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD13
PCI_AD15
PCI_AD14
PCI_AD11 PCI_AD12
PCI_AD8
PCI_AD10
PCI_AD9
PCI_AD6 PCI_AD7
PCI_AD3
PCI_AD5
PCI_AD4
PCI_AD2
PCI_AD0
PCI_VIOS
VDD10
VDD9
VDD8
VDD7
VDD4
VDD3
VDD1
VDD2
VDD0
PLLVDD
VDDA0
VDDA1
VDDA2
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO IO
IO
IO
IN
IO
IO
IO
IN
IO IO
IO IO
IO
IO IO
IO
IO
IO IO
IO IO
IO
IO IO
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
USING PCI [1]
??? CHECK YELLOW EDS
THESE POWER PLANES SHOULD BE MOSTLY ISOLATED
T1: TP (?)
NOTE: 1% FOR BOM CONSOLIDATION
10K
10K
MF-LF
1/16W
5%
10K
402
OMIT
FW32306
TQFP
600-OHM-300MA
0402
10K
10K 10K
10K 10K 10K
22
1% 1/16W MF-LF
402
150
NOSTUFF
MF-LF
402
0
1/16W
5%
CERM
10V 402
20%
0.1UF
CRITICAL
HC49-USMD
24.576M
402
412
1% 1/16W MF-LF
CERM5%
40250V
27PF
402
5%
50V
CERM
27PF
10V 20%
CERM
402
0.1UF
510K
1/16W5%MF-LF
402
2.49K
402
MF-LF
1%
1/16W
390K
5%
1/16W MF-LF
402
FW: FW323-06
9744
??
051-7032
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PCI_IDSEL
=PP3V3_S5_FW
PCI_AD<0>
VOLTAGE=3.3V MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
PP3V3_S5_FW_VDDA
PCI_RST_L
PCI_RST_FW_L
FW_SM
FW_SE
FW_TEST
FW_CONTENDER
FW_PC2
FW_PC1
PCI_AD<7>
PCI_PAR
=PP3V3_S5_FW
FW_A_TPA_N
FW_XTAL_XR
FW_XTAL_XI
FW_RESET_L
=PP3V3_S5_FW
=PP12V_S5_FW_PHY
FW_XTAL_X0
=PP3V3_S0_PCI
PCI_AD<2>
PCI_AD<4> PCI_AD<5>
PCI_AD<3>
PCI_AD<6>
PCI_AD<9> PCI_AD<10>
PCI_AD<8>
PCI_AD<12>
PCI_AD<11>
PCI_AD<14> PCI_AD<15>
PCI_AD<13>
PCI_AD<16> PCI_AD<17> PCI_AD<18>
PCI_AD<20>
PCI_AD<23>
PCI_AD<22>
PCI_AD<21>
PCI_AD<25>
PCI_AD<28>
PCI_AD<26>
PCI_AD<29> PCI_AD<30> PCI_AD<31>
PCI_C_BE_L<2>
PCI_C_BE_L<1>
PCI_C_BE_L<0>
PCI_C_BE_L<3>
PCI_FRAME_L PCI_IRDY_L PCI_TRDY_L PCI_DEVSEL_L PCI_STOP_L
PCI_PERR_L PCI_SERR_L
PCI_CLK_FW PM_CLKRUN_L
PCI_PME_FW_L
PCI_RST_FW_L INT_PIRQD_L
FW_CARDBUS_L
TP_FW_ROM_AD
FW_ROM_CLK
TP_FW_MPCIACT_L
NC_FW_NU1 NC_FW_NU2
TP_FW_VAUX_PRES
FW_PC0
TP_FW_NANDTREE
TP_FW_CNA
TP_FW_LKON
FW_CPS
TP_FW_LPS
FW_C_TPB_N
FW_C_TPB_P
FW_C_TPA_N
FW_C_TPA_P
FW_C_TPBIAS
FW_B_TPB_N
FW_B_TPB_P
FW_B_TPA_N
FW_B_TPA_P
FW_B_TPBIAS
FW_A_TPB_N
FW_A_TPB_P
FW_A_TPA_P
FW_A_TPBIAS
FW_R0
FW_R1
FW_RESET_L
FW_XTAL_X0
FW_XTAL_XI
PCI_AD<27>
PCI_AD<24>
PCI_AD<1>
=PP3V3_S5_FW
PCI_AD<19>
PCI_FW_REQ_L PCI_FW_GNT_L
R4403
1 2
R4407
1 2
R4411
1 2
C4410
1
2
Y4400
1
2
R4410
1 2
C4412
1 2
C4401
1 2
C4402
1 2
R4412
1 2
R4413
1 2
R4414
1 2
R4409
1 2
R4402
1 2
R4416
1
2
U4400
3
13
5
86
94
90
91
92
6
4 127
89 88 87
84 83
68 67 65 64 63 62 46 45 42 41
80
40 39 36 35 31 30 29 28 25 24
79
23 22
78 76 75 74 70 69
73 60 47 33
20
53
48
16
34
14
51
59
57
18
17
15
58
54
52
85
119
120
124
117
118
123
9
8
126 125
10 7
112
113
107
108
99
100
110
111
105
106
97
98
114
109
101
128
1
119319263743495572
82
104
116
96
12
2
667177
81
21273238445056
61
102
103
115
95
121
122
L4409
1 2
R4450
1 2
R4451
1 2
R4452
1 2
R4453
1 2
R4454
1 2
R4455
1 2
46 45 44
6
22
45
22
44
22
22
46 45 44
6
46
44
44
46 45 44
6
46
44
6
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
26 22
26 22
26 22
26 22
26 22
26 22
26 22
34
67 60 58 23
5
22
44
26 22
46
46
46
46
46
46
46
46
46
46
46
46
46
46
44
44
44
22
22
22
46 45 44
6
22
27
27
Page 39
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
0.01UF
20% 16V CERM 402
0.01UF
20% 16V CERM 402
0.01UF
20% 16V CERM 402
0.01UF
20% 16V CERM 402402
CERM
16V
20%
0.01UF
0.1UF
10V 402
CERM
20%
0.1UF
10V
20% CERM
402
0.1UF
10V
20% CERM
402
CERM
20% 10V
0.1UF
402
20% CERM
10V
0.1UF
402
0.01UF
20% 16V CERM 402
0.01UF
20% 16V CERM 402
CERM
10UF
20%
6.3V 805-1
CERM
6.3V
20%
10UF
805-1
20% CERM
402
10V
0.1UF
402
CERM
20% 10V
0.1UF
051-7032
??
45 97
FW: DECAPS
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
=PP3V3_S5_FW
PP3V3_S5_FW_VDDA
C4508
1
2
C4509
1
2
C4510
1
2
C4500
1
2
C4501
1
2
C4502
1
2
C4504
1
2
C4505
1
2
C4506
1
2
C4507
1
2
C4521
1
2
C4520
1
2
C4523
1
2
C4522
1
2
C4515
1
2
C4503
1
2
46 44
6
44
Page 40
TPI
VGND
VP
TPI#
TPO#
TPO
TPI
VGND
VP
TPI#
TPO#
TPO
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
IO IO
IO
IO
IO IO
IO
IO
IO IO
IO
IO
IO
IO
IO
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
TABLE_5_ITEM
TO FW CDS PIN (CABLE POWER DETECT)
8 WATTS MAX
PLACE R4657 PADS INSIDE R4656
"Snapback" & "Late VG" Protection
514-0251 20_INCH_VERSION SHOWN
514-0251 20_INCH_VERSION SHOWN
FW_VP MAX IS 33V
FW_VP MAX IS 33V
"Snapback" & "Late VG" Protection
12 VOLTS
Place close to FireWire PHY
(TPB-)
PORT 0
1394A
(TPA+)
(TPA-)
(TPB+)
(TPB-)
1394A
(TPA+)
(TPB+)
PORT 1
CURRENT THROUGH THE BIAS RESISTOR SHOULD BE 5MA FOR A VOLTAGE DROP TO 2.2V
ESD Rail
(TPA-)
Termination
DESIGNED WITH INTENTION TO RESIZE FUSE LIMITS EQUAL FW SPEC 1.5A LIMIT
POSSIBLE CURRENT SHARING SCENARIO KCL = CABLE POWER + SYSTEM POWER = > 1.5 AMPS
3rd TPA/TPB pair unused
R4690 VALUE WAS RECOMMENDED BY COLIN
IT IS 2.2V INSTEAD OF 2.7V BECAUSE THE SNAPBACK ESD DIODES HAVE A .5V DROP
[ LATE VG NOTES ]
FW_C_TPB_N
=PP3V3_S5_FW
VOLTAGE=33V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
PPFW_PORT1_VP
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
VOLTAGE=33V
PPFW_PORTS_VP
FW_VP
MIN_LINE_WIDTH=0.8MM MIN_NECK_WIDTH=0.25MM
VOLTAGE=33V
FW_B_TPA_N FW_B_TPB_P FW_B_TPB_N
FW_B_TPBIAS
VOLTAGE=1.86V
VOLTAGE=3.3V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm
PP3V3_FW_ESD_F
PP3V3_FW_ESD
MIN_LINE_WIDTH=0.38 mm
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.25 mm
PPFW_PORT1_VP
VOLTAGE=0V
FW_TPA_C<1>
FW_A_TPBIAS
VOLTAGE=1.86V
VOLTAGE=0V
FW_TPA_C<0>
FW_PORT0_TPA_P
MAKE_BASE=TRUE
FW_A_TPA_P
MAKE_BASE=TRUE
FW_PORT0_TPA_N
FW_A_TPA_N
MAKE_BASE=TRUE
FW_PORT0_TPB_N
FW_PORT0_TPB_P
MAKE_BASE=TRUE
FW_A_TPB_P
MAKE_BASE=TRUE
FW_PORT1_TPA_P
MAKE_BASE=TRUE
TP_FW_C_TPA_P
MAKE_BASE=TRUE
TP_FW_C_TPBIAS
FW_C_TPBIAS
FW_C_TPA_P
MAKE_BASE=TRUE
TP_FW_C_TPA_N
MAKE_BASE=TRUE
TP_FW_C_TPB_P
MAKE_BASE=TRUE
TP_FW_C_TPB_N
FW_C_TPA_N
FW_C_TPB_P
=PP12V_S5_FW_PHY
FW_PORT0_TPB_FL_P
FW_PORT0_TPB_FL_N
FW_PORT0_TPA_FL_P
FW_PORT0_TPA_FL_N
PP3V3_FW_ESD
FW_PORT0_TPA_P
FW_PORT0_TPB_P
FW_PORT0_TPB_N
FW_PORT0_TPA_N
FW_PORT1_TPA_FL_P
FW_PORT1_TPA_FL_N
FW_PORT1_TPB_FL_P
FW_PORT1_TPB_FL_N
FW_PORT1_TPA_N
FW_PORT1_TPA_P
FW_PORT1_TPB_N
PP3V3_FW_ESD
PP3V3_FW_ESD
GND_CHASSIS_FIREWIRE
PPFW_PORT0_VP_FL
MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.6 mm
PPFW_PORT1_VP_FL
VOLTAGE=33V
GND_CHASSIS_FIREWIRE
FW_PORT1_TPB_P
FW_A_TPB_N
FW_B_TPA_P
FW_PORT1_TPB_N
MAKE_BASE=TRUE
FW_PORT1_TPB_P
MAKE_BASE=TRUE
FW_PORT1_TPA_N
MAKE_BASE=TRUE
PP3V3_FW_ESD
=PP12V_S5_FW
MIN_NECK_WIDTH=0.25MM
PP12V_FW
MIN_LINE_WIDTH=0.8MM
VOLTAGE=12V MAKE_BASE=TRUE
051-7032
??
9746
FIREWIRE CONNECTORS
CON,1394A 7 DEGREES, W/O RIBS
514-0336
2
17_INCH_LCD
CRITICAL
JE000,JE001
0
805
MF-LF
1/8W
5%
50V
0.001UF
10%
CERM
402
50V
0.001UF
10%
CERM
402
402
CERM
10% 50V
0.001UF
402
CERM
10%
0.001UF
50V
50V
0.001UF
10%
CERM
402
50V
0.001UF
10%
CERM
402
50V
0.001UF
10%
CERM
402 402
CERM
10%
0.001UF
50V
603-1
X7R
10%
0.1UF
50V
50V
0.1UF
10% X7R
603-1
1/16W
1%
MF-LF
402
374
I443
SOT-363
BAV99DW-X-F BAV99DW-X-F
SOT-363
MINISMD-LF
CRITICAL
0.75AMP-13.2V
CRITICAL
1.5AMP-33V
SM-LF
FERR-160-OHM
1206-LF
FERR-160-OHM
1206-LF
CRITICAL
120-OHM
2012
CRITICAL
2012
120-OHM
CRITICAL
120-OHM
2012
CRITICAL
120-OHM
2012
CRITICAL
SOT23
BZX84C2V7-X-F
400-OHM-EMI
SM-1
25V
5%
CERM
402
220PF
402
1% 1/16W MF-LF
4.99K
1%
56.2
MF-LF
402
1/16W
56.2
1% 1/16W MF-LF 402
402
CERM
25V
5%
220PF
MF-LF 402
1/16W
1%
4.99K
56.2
1% 1/16W MF-LF
402
MF-LF
56.2
1% 1/16W
402
56.2
1%
402
1/16W MF-LF MF-LF
56.2
1% 1/16W
402
6.3V 402
10% CERM-X5R
0.33UF
MF-LF
56.2
1% 1/16W
402
MF-LF
56.2
402
1% 1/16W
402
6.3V
10% CERM-X5R
0.33UF
BAV99DW-X-F
SOT-363
SOT-363
BAV99DW-X-F
BAV99DW-X-F
SOT-363
SOT-363
BAV99DW-X-F
16V
20%
CERM
402
0.01uF
UF01613-M33-4F
OMIT
F-ST-TH
CRITICAL
UF01613-M33-4F
OMIT
CRITICAL
F-ST-TH
SOT-363
BAV99DW-X-F BAV99DW-X-F
SOT-363
0.01uF
402
CERM
16V
20%
FF
1W
1.3
20%
NOSTUFF
2512
SMC
MURS320XXG
D4600
1 2
R4656
1 2
C4626
1
2
DP4620
4
5
3
DP4620
1
2
6
JE001
10
7 8 9
4
3
6
5
2
1
JE000
10
7 8 9
4
3
6
5
2
1
C4616
1
2
DP4610
4
5
3
DP4611
4
5
3
DP4610
1
2
6
DP4611
1
2
6
C4660
1
2
R4661
1
2
R4660
1
2
C4650
1
2
R4651
1
2
R4650
1
2
R4663
1
2
R4662
1
2
R4664
1
2
C4664
1
2
R4653
1
2
R4652
1
2
R4654
1
2
C4654
1
2
L4690
1 2
D4690
1 3
FL4610
1
2 3
4
FLE011
1
2 3
4
FL4620
1
2 3
4
FLE021
1
2 3
4
L4610
1
2
L4620
1
2
F4600
1 2
F4602
1 2
DP4621
4
5
3
DP4621
1
2
6
R4690
1 2
C4615
1
2
C4625
1
2
C4623
1
2
C4622
1
2
C4612
1
2
C4613
1
2
C4621
1
2
C4620
1
2
C4610
1
2
C4611
1
2
R4657
1 2
44
45 44
6
46
44
44
44
44
46
46
44
46
44
46
44
46
46
44
46
44
44
44
44
44
46
46
46
46
46
46
46
46
46
46
46
6
46
6
46
44
44
46
46
46
46
6
Page 41
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-2
SYM_VER-2
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO
OUT
EN3*
EN1* EN2*
OC1* OC2* OC3*
IN1 IN2
OUT1 OUT2 OUT3
NC
NC
NC
GNDA GNDB
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PLACE C4742 CLOSED TO JE4702.
NEAR JE4702 PIN 14 IN THE
SB HAS INTERNAL 15K PULL-DOWNS
BLUETOOTH
ORDER LISTED, AND NOT ON
PLACE C4743, C4797 & L4740
SB HAS INTERNAL 15K PULL-DOWNS
External USB Ports
514-0247
IR CONNECTOR
MIC CONNECTOR
SB HAS INTERNAL 15K PULL-DOWNS
CAMERA CONNECTOR
STUFFING FOR PROTO, EVAL LATER
SB HAS INTERNAL 15K PULL-DOWNS
MAKE SURE 6.3V CAP HERE IS OK
SB HAS INTERNAL 15K PULL-DOWNS
NOTE: STANDOFFS FOR J4700
514-0247
740S0032
SB HAS INTERNAL 15K PULL-DOWNS
D+ GND
PORT 2
D-
VDD
GND
514-0247
PORT 1
VDD D-
D+ GND
TO M13D SLOT
BOTH SIDES OF THE PIN.
LAYOUT NOTE:
D+
STUFFING FOR PROTO, EVAL LATER
PORT 0
VDD D-
CRITICAL
120-OHM
2012
0.01uF
CERM
402
16V
20%
16V
CERM
20%
402
0.01uF
NOSTUFF
150UF
SMD2
6.3V POLY
20%
SM
FERR-250-OHM
16V
CERM
402
0.01uF
20%
16V
CERM
0.01uF
402
20%
FERR-250-OHM
SM
CRITICAL
2012
120-OHM
120-OHM
2012
CRITICAL
16V
0.01uF
CERM
402
20%
402
16V
20%
0.01uF
CERM
FERR-250-OHM
SM
0
402
NOSTUFF
402
0
NOSTUFF
402
0
NOSTUFF
0
402
NOSTUFF
402
0
NOSTUFF
0
402
NOSTUFF
402
NOSTUFF
0
402
0
NOSTUFF
120-OHM
CRITICAL
2012
NOSTUFF
402
0
NOSTUFF
0
402
0.01uF
20%
402
16V
CERMCERM
402
0.01uF
20% 16V
FERR-250-OHM
SM
5%
MF-LF
1/8W
805
0
2012
120-OHM
CRITICAL
0.75AMP-13.2V
MINISMD-LF
CRITICAL
805-1
10UF
6.3V
20% CERM
QT800101-1210S-8F
F-ST-SM
CRITICAL
10V
20% CERM
402
0.1UF
F-ST-TH
UB01123M23-4F
OMIT
UB01123M23-4F
F-ST-TH
OMIT
F-ST-TH
OMIT
UB01123M23-4F
805-1
10UF
6.3V
20% CERM
STDOFF-4OD4.5H-1.35-TH
STDOFF-4OD4.5H-1.35-TH
RCLAMP0502B
SC-75
CRITICAL
RCLAMP0502B
SC-75
RCLAMP0502B
SC-75
SOI
TPS2043B
CRITICAL
NOSTUFF
SMD2
6.3V POLY
20%
150UF
CRITICAL
ELEC
6.3V
20%
1800UF
TH-KZJ-LF
CRITICAL
87212-0400L
M-ST-SM
53261-0598
CRITICAL
M-RT-SM
CRITICAL
M-RT-SM
53261-0398
USB Device Interfaces
9747
051-7032
??
JE310,JE320,JE330
USB RECEPTACLE,4P,UB1123-M50-4F
514-0339
17_INCH_LCD
CRITICAL
3
AUD_MIC_IN_N_CONN
AUD_MIC_IN_P_CONN
GND_AUDIO_MIC_CONN
USB_IR_P
USB_IR_N
=PP5V_S3_USB
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
PP5V_USB2_PORT1 VOLTAGE=5V
USB_PORT0_P
VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
PP5V_USB2_PORT0_F
USB_PORT1_N
USB_A_OC_L
PP5V_USB2_PORT2 VOLTAGE=5V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
GND_CHASSIS_USB
MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V MIN_NECK_WIDTH=0.25MM
PP5V_USB2_PORT2_F
USB_E_P
USB_E_N
USB_C_N
USB_C_P
USB_PORT2_P
USB_PORT2_N
USB_PORT1_P
GND_CHASSIS_USB
USB_G_N USB_G_P
=PP5V_S3_BNDI
GND_CHASSIS_BNDI
GND_BNDI
VOLTAGE=0V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
PP5V_BNDI_LE340
USB_BT_P
MAKE_BASE=TRUE
PP5V_S3_BNDI
VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
=PP3V3_S3_BT
USB_C_OC_L USB_E_OC_L
VOLTAGE=5V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
PP5V_USB2_PORT1_F
USB_PORT0_N
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
PP5V_USB2_PORT0 VOLTAGE=5V
USB_A_P
USB_A_N
USB_D_P
USB_D_N
GND_BNDI
PP5V_S3_BNDI
GND_CHASSIS_BNDI
USB_H_P
=PP5V_S3_BNDI
USB_H_N
GND_CHASSIS_USB
MIN_NECK_WIDTH=0.2MM MIN_LINE_WIDTH=0.6MM
VOLTAGE=0
USB_CAMERA_P
USB_BT_N
MAKE_BASE=TRUE
USB_CAMERA_N
CAMERA
CAMERA
CAMERA
CAMERA
CAMERA
CAMERA
CAMERA
CAMERA
L4712
1
2 3
4
C4713
1
2
C4712
1
2
C4710
1
2
L4710
1 2
C4723
1
2
C4722
1
2
L4720
1 2
L4722
1
2 3
4
L4732
1
2 3
4
C4733
1
2
C4732
1
2
L4730
1 2
R4712
1 2
R4713
1 2
R4722
1 2
R4723
1 2
R4732
1 2
R4733
1 2
R4742
1 2
R4743
1 2
L4752
1
2 3
4
R4755
1 2
R4754
1 2
C4743
1
2
C4742
1
2
L4740
1 2
R4746
1 2
L4742
1
2 3
4
F4701
1 2
C4797
1
2
J4700
1
10
2
3
4
5
6
7
8
9
C4798
1
2
JE310
5 6
7
1 2 3 4
JE320
5 6
7
1 2 3 4
JE330
5 6
7
1 2 3 4
C4799
1
2
SDF4700
1
SDF4701
1
D4700
3
1
2
D4701
3
1
2
D4702
3
1
2
U4700
3 4 7
1 5
2
6
8 9 10
16 13 12
15
14
11
C4720
1
2
C4700
1
2
JE4700
5
6
1 2 3 4
JE4702
6
7
1 2 3 4 5
JE4701
4
5
1 2 3
73
73
73
6
22
47
6
22
22
22
22
47
6
22
22
47
6
47
6
47
47
6
22
22
22
22
22
22
47
47
47
6
22
47
6
22
47
6
Page 42
KEY
IO IO
IN
IN
IN
IO
IO
OUT
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PLACE CAPS < 250 MILS FROM U2100
LAYOUT NOTE:
MINIMIZED IF THE RESISTORS ARE NOT STUFFED
PLACE R5302-03 SUCH THAT STUB LENGTH IS
NOTE: STANDOFFS FOR J5300
SB HAS INTERNAL 15K PULL-DOWNS
STDOFF-4OD5.6H-1.35-TH
STDOFF-4OD5.6H-1.35-TH
0.1UF
0.1UF
ASOB226-S80N-7F
F-RT-SM
CRITICAL
20%
0.1UF
402
CERM
10V 10V
CERM
0.1UF
20%
402
20%
402
CERM
10V
0.1UF
20%
0.1UF
10V CERM 402
CERM
10V
0.1UF
20%
402
20%
0.1UF
CERM 402
10V10V
0.1UF
20%
402
CERM
0 0
20% 10V CERM
10UF
805-2
0
20% 10V CERM
10UF
805-2
20% 10V CERM
10UF
805-2
0.1UF
20% 10V CERM 402
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
AIRPORT CONN
??
53 97
051-7032
USB_B_N USB_B_P
=PP1V5_S0_AIRPORT
=PP3V3_S0_AIRPORT
AIRPORT_CONN_DATA
AIRPORT_WAKE_L
PP3V3_S3
AIRPORT_CLK100M_PCIE_N
PCIE_WAKE_L
PCIE_AIRPORT_D2R_P
AIRPORT_CONN_CLK =SMB_AIRPORT_CLK
=SMB_AIRPORT_DATA
AIRPORT_CLK100M_PCIE_P
CK410_SRC_CLKREQ6_L
AIRPORT_RST_L
PCIE_AIRPORT_R2D_C_N
PCIE_AIRPORT_R2D_P
PCIE_AIRPORT_R2D_N
PCIE_AIRPORT_R2D_C_P
PCIE_AIRPORT_D2R_N
C5300
1 2
C5301
1 2
J5300
53
54
1
10 11 12 13 14 15 16 17 18 19
2
20 21 22 23 24 25 26 27 28 29
3
30 31 32 33 34 35 36 37 38 39
4
40 41 42 43 44 45 46 47 48 49
5
50 51 52
6 7 8 9
C5304
1
2
C5305
1
2
C5306
1
2
C5307
1
2
C5308
1
2
C5310
1
2
C5309
1
2
R5302
1 2
R5303
1 2
C5311
1
2
R5304
1 2
C5312
1
2
C5314
1
2
C5313
1
2
SDF5300
1
SDF5301
1
22
22
6
6
83 59
6
34
41 23
54
27
27
34
33
6
54
54
54
Page 43
IN
IN
IN
IN
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN
OUT
OUT
IN
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
USED PCIE PORTS
PCIE PORT ALIASES
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
9754
??
051-7032
MAKE_BASE=TRUE
PCIE_B_R2D_C_N
MAKE_BASE=TRUE
PCIE_B_D2R_P
PCIE_ENET_D2R_P
MAKE_BASE=TRUE
PCIE_B_D2R_N
MAKE_BASE=TRUE
PCIE_B_R2D_C_P
PCIE_ENET_D2R_N
MAKE_BASE=TRUE
PCIE_A_D2R_N
MAKE_BASE=TRUE
PCIE_A_D2R_P
PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_AIRPORT_D2R_P
PCIE_AIRPORT_D2R_N
MAKE_BASE=TRUE
TP_PCIE_C_R2D_C_N
PCIE_AIRPORT_R2D_C_P
PCIE_AIRPORT_R2D_C_N
TP_PCIE_F_D2R_N
MAKE_BASE=TRUE
TP_PCIE_F_D2R_P
MAKE_BASE=TRUE
MAKE_BASE=TRUE
TP_PCIE_F_R2D_C_P
MAKE_BASE=TRUE
TP_PCIE_F_R2D_C_N
PCIE_F_D2R_N
PCIE_F_D2R_P
PCIE_F_R2D_C_P
PCIE_F_R2D_C_N
MAKE_BASE=TRUE
PCIE_A_R2D_C_N
MAKE_BASE=TRUE
PCIE_A_R2D_C_P
PCIE_E_D2R_P
PCIE_E_D2R_N
PCIE_E_R2D_C_P
PCIE_E_R2D_C_N
PCIE_D_D2R_P
PCIE_D_D2R_N
PCIE_D_R2D_C_P
PCIE_D_R2D_C_N
PCIE_C_D2R_P
PCIE_C_D2R_N
PCIE_C_R2D_C_P
MAKE_BASE=TRUE
TP_PCIE_C_R2D_C_P
MAKE_BASE=TRUE
TP_PCIE_E_D2R_N
MAKE_BASE=TRUE
TP_PCIE_E_D2R_P
TP_PCIE_E_R2D_C_P
MAKE_BASE=TRUE
TP_PCIE_E_R2D_C_N
MAKE_BASE=TRUE
TP_PCIE_D_D2R_P
MAKE_BASE=TRUE
TP_PCIE_D_D2R_N
MAKE_BASE=TRUE
TP_PCIE_D_R2D_C_N
MAKE_BASE=TRUE
TP_PCIE_D_R2D_C_P
MAKE_BASE=TRUE
TP_PCIE_C_D2R_P
MAKE_BASE=TRUE
TP_PCIE_C_D2R_N
MAKE_BASE=TRUE
PCIE_C_R2D_C_N
22
22
5
41
22
5
22
41
22
5
22
5
41
41
53
53
53
53
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
22
Page 44
IN
IN
IN
OUT
OUT
OUT
OUT
IN
IN
OUT
OUT
IN
IN
IN IN
IN
IN IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
OUT
P16
P51
P50
P42/SDA1
P97/IRQ15*/SDA0
P95/IRQ14*
P94/IRQ13*
P93/IRQ12*
P92/IRQ0*
P91/IRQ1*
P86/IRQ5*/SCK1/SCL1
P83/LPCPD*
P82/CLKRUN*
P80/PME*
P35/LRESET*
P34/LFRAME*
P10
P12 P13 P14 P15
P17
P31/LAD1
P30/LAD0
P32/LAD2 P33/LAD3
P36/LCLK P37/SERIRQ
P44/TMO1
P77/AN7
P76/AN6
P81/GA20
P96/EXCL
P11
P47/PWX1/PWM1
P45 P46/PWX0/PWM0
P40/TMIO
P43/TMI1/EXSCK1
P27
P26
P25
P24
P23
P22
P21
P20
P41/TMO0
P52/SCL0
P60/KIN0* P61/KIN1* P62/KIN2* P63/KIN3* P64/KIN4*
P65/KIN5* P66/IRQ6*/KIN6* P67/IRQ7*/KIN7*
P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5
P84/IRQ3*/TXD1 P85/IRQ4*/RXD1
P90/IRQ2*
(1 OF 4)
PA2/KIN10*/PS2AC PA3/KIN11*/PS2AD
PA5/KIN13*/PS2BD
PA4/KIN12*/PS2BC
PB2 PB3 PB4
PE0
PG6/EXIRQ14*/EXSDAB
PG5/EXIRQ13*/EXSCLA
PH1/EXIRQ7*
PH0/EXIRQ6*
PG7/EXIRQ15*/EXSCLB
PG4/EXIRQ12*/EXSDAA
PH3/EXEXCL
PH2/FWE
PB5
PF4/PWM4
PF2/IRQ10*/TMOY
PG2/EXIRQ10*/SDA2
PG0/EXIRQ8*/TMIX
PF7/PWM7
PC3/TIOCD0/TCLKB/WUE11*
PH5
PB7
PB6
PH4
PF5/PWM5 PF6/PWM6
PG1/EXIRQ9*/TMIY
PA6/KIN14*/PS2CC PA7/KIN15*/PS2CD
PD0/AN8 PD1/AN9 PD2/AN10 PD3/AN11 PD4/AN12 PD5/AN13 PD6/AN14 PD7/AN15
PF0/IRQ8*/PWM2 PF1/IRQ9*/PWM3
PB0/LSMI* PB1/LSCI
PC0/TIOCA0/WUE8* PC1/TIOCB0/WUE9* PC2/TIOCC0/TCLKA/WUE10*
PC4/TIOCA1/WUE12* PC5/TIOCB1/TCLKC/WUE13* PC6/TIOCA2/WUE14* PC7/TIOCB2/TCLKD/WUE15*
PG3/EXIRQ11*/SCL2
PF3/IRQ11*/TMOX
PA1/KIN9*/PA2DD
PA0/KIN8*/PA2DC
PE1*/ETCK PE2*/ETDI PE3*/ETDO PE4*/ETMS
(2 OF 4)
VCL
AVREF
VCC
VCC
VCC
AVCC
XTAL EXTAL
AVCC
VCC
MD1 MD2
NMI
RES*
ETRST*
AVREF
AVSS
VSS
(3 OF 4)
NC22
NC21
NC20
NC19
NC18
NC17
NC16
NC15
NC14
NC13
NC12
NC9
NC6
NC11
NC10
NC8
NC7
NC5
NC4
NC3
NC2
NC1
NC0
(4 OF 4)
OUT
OUT
IO
OUT
IN
IN
IN
OUT
IN
IO
IN
IO
OUT
OUT
IN
IN
OUT
OUT
IN
OUT OUT
OUT
OUT
IN
IN
IN
IN
IN IN
IN
IN
IN
IN
IN
IN
IN
IN
OUT
IN
IN
IN
OUT
OUT OUT
OUT
IO
IO
IO
IO IO
IO
IO
OUT
OUT
OUT
OUT OUT
IN
IN
IN
IN
OUT
IN
IN
OUT
OUT
IN
OUT
OUT
IN
IN
OUT OUT
IO IO
IO
IO IN
IN
IN
OUT
OUT OUT
IO
IN
IN
IN IN
IO
IO
IN IN
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SMC_XXX WHERE XXX IS THE PORT NUMBER.
CAN BE LEFT NO-CONNECTED.
UNUSED PINS HAVE THE FORMAT
LAYOUT NOTE:
SMC
PLACE R5899 AND C5820 NEAR SMC PIN N14,N15
VCL IS INTERNAL RAIL
PLACE C5807 NEAR PIN F1
LAYOUT NOTE:
DRIVEN OUTPUTS ALWAYS SO THEY
THEY ARE SET BY SOFTWARE TO BE
805
20%
6.3V X5R
22UF
402
0.47UF
20%
6.3V CERM-X5R
10V
0.1UF
20% CERM
402
0.1UF
20% CERM
10V 402
5%
1/16W
4.7
402
MF-LF
0.1UF
20% 10V CERM 402
SM
402
10V
20%
0.1UF
CERM
20% 10V CERM 402
0.1UF
BGA
OMIT
SMC_H8S2116
OMIT
SMC_H8S2116
BGA
BGA
SMC_H8S2116
OMIT
BGA
SMC_H8S2116
OMIT
MF-LF
5% 402
1/16W
10K
MF-LF 402
5%
10K
1/16W
1/16W
5%
10K
MF-LF 402
NOSTUFF
402
MF-LF
1/16W
5%
0
10K
MF-LF
5% 1/16W
402
051-7032
??
58 97
SMC_TX_L
SMC_SYS_LED SMC_SYS_KBDLED
SMB_B_S0_CLK
SMB_B_S0_DATA
SMB_A_S3_CLK
SMB_A_S3_DATA
SMB_BSA_CLK
SMB_BSA_DATA
SMB_0_S0_CLK
SMC_RSTGATE_L
PM_LAN_ENABLE
ALL_SYS_PWRGD RSMRST_PWRGD SMC_SB_NMI PM_RSMRST_L IMVP_VR_ON PM_PWRBTN_L
SMC_WAKE_SCI_L
SMB_BSB_CLK SMC_ONOFF_L
SC_RX_L
SC_TX_L
PM_SUS_STAT_L
PM_CLKRUN_L
SMC_TPM_GPIO
INT_SERIRQ
PCI_CLK_SMC
SMC_LRESET_L
LPC_FRAME_L
LPC_AD<3>
LPC_AD<2>
LPC_AD<1>
LPC_AD<0>
SMC_P27
SMC_RCIN_L BOOT_LPC_SPI_L
SMC_TPM_RESET_L PM_EXTTS_L PM_THRM_L SYS_ONEWIRE PM_BATLOW_L
SMC_FAN_0_TACH SMC_FAN_1_TACH SMC_FAN_2_TACH
SMC_FAN_3_CTL
SMC_TPM_PP
SMB_BSB_DATA
SMC_XDP_TMS
SMC_XDP_TCK
SMC_RX_L
SMC_EXTSMI_L
ISENSE_CAL_EN
SMC_EXCARD_PWR_EN
SMC_FWIRE_ISENSE
SMC_BATT_ISENSE
SMC_PBUS_VSENSE
SMC_GPU_VSENSE
SMC_PROCHOT_3_3_L
SPI_SO
SPI_SCLK
SMC_SUS_CLK
PM_SYSRST_L
SMC_XDP_TRST_L
SMC_THRMTRIP
ALS_GAIN
SMC_RST_L
PM_SLP_S3_L PM_SLP_S4_L PM_SLP_S5_L
=PP3V3_S5_SMC
SMC_VCL
SMC_EXCARD_CP
SMC_DCIN_ISENSE
SMC_GPU_ISENSE
SMC_CPU_RESET_3_3_L
SMC_XDP_TCK_3_3
SPI_CE_L
SMC_PF0
SMC_ADAPTER_EN
SMC_CPU_VSENSE
SMB_0_S0_DATA
SMC_RUNTIME_SCI_L SMC_ODD_DETECT
SMC_BATT_VSET SMC_SYS_ISET
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_CASE_OPEN
SMC_P26
SMC_BATT_CHG_EN
SMC_P20
SMC_BATT_TRICKLE_EN_L
SMC_P21
SMC_FAN_0_CTL SMC_FAN_1_CTL
SMC_FAN_3_TACH
SMS_Y_AXIS
ALS_RIGHT
SMC_FWE
SMC_BC_ACOK
SMC_P23
SMC_CPU_INIT_3_3_L
=PP3V3_S5_SMC
GND_SMC_AVSS
SMC_SYS_LED_16B
SMC_XDP_TDO_3_3
SPI_ARB
GND_SMC_AVSS
SMC_NMI
SMC_TRST_L
SMC_PROCHOT
PP3V3_AVREF_SMC
SMC_MD1
ALS_LEFT
KBC_MDE
=PP3V3_S5_SMC
PP3V3_AVCC_SMC
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
SMC_EXTAL
SMC_XTAL
SMC_P22
SMC_PM_G2_EN
SMC_EXCARD_OC_L
SMC_FAN_2_CTL
SPI_SI
SMC_CPU_ISENSE
SMS_INT_L
SMC_BS_ALRT_L
SMC_MEM_ISENSE
SMC_NB_ISENSE
SMC_ANALOG_ID
SMS_Z_AXIS
SMS_X_AXIS
SMS_ONOFF_L
SMC_PF1 SMC_LID
SMC_BATT_ISET
SMC_SYS_VSET
C5802
1
2
C5803
1
2
C5804
1
2
C5805
1
2
C5806
1
2
C5807
1
2
C5820
1
2
R5899
1 2
XW5800
1 2
U5800
B12 C13 A15 B14 B15 C14 D12 C15
D13 D14 D15 E12 E14 E15 E13 F14
D9 C9 A9 B9 D8 C8 A8 D7
A5 B5 D5 C3 B1 C2 D3 C1
G1 G4 F2
L13 L14 L15 K12 K13 K14 J12 J13
N12 R13 P13 R14 P14 R15 N13 P15
C7 A7 B7 D6 C6 A6 B6
K4 J2 J1 J3 J4 H2 H1 G2
U5800
R3 P3 R2 N3 R1 N2 M4 N1
B10 A10 D10 A11 B11 C11 A12 D11
G14 G15 G13 G12 H14 H15 H13 H12
M11 P11 R11 N11 P10 R10 N10 M10
M3 M2 M1 L4 L2
M7 P6 R6 N6 M6 R5 P5 N5
P9 R9 N9 P8 R8 M8 P7 R7
E1 F3 K2 C4 D4 B3
U5800
N14
N15
M14
M15
P12 R12
L1
B2
E2 K1
F4
E3
P2P1J15A1F1
D1P4R4
F12
F13
B13
A13
A4B4D2
A2
U5800
G3 H3
K15 J14
F15 A14 C12 C10 C5 A3 B8 E4
K3
H4 M9 N8
L3 N4 M5
N7 M12 M13 L12
R5809
1
2
R5801
1
2
R5802
1
2
R5803
1
2
R5898
1
2
60 59
5
59
59
59
59
59
59
59
59
59
59
23
77 26
76
23
23
75
23
23
59
59
59
59
67 60 23
67 60 44 23
5
59
67 60 23
34
6
67 60 21
67 60 21
67 60 21
67 60 21
67 60 21
59
21
60 22
67 59
59 14
23 10
59
23
65
65
66
59
59
59
59
59
60 59
5
23
76
59
59
59
76
59
59
63 22
63 22
59
26 23
5
59
59
59
60 59 80 79 77 23
77 23
23
59 58
6
59
76
59
59
59
63 22
59
59
76
59
23
59 59
59
60 59
5
60 59
5
60 59
5
60 59
5
59
59
59
59
59
59
65
65
59
59
59
59
59
59
59
59 58
6
80 76 59 58
59
59
22
5
80 76 59 58
60
59
59
60
59
59 58
6
59
59
59
59
59
66
63 22
76
26 23
59
59
80
59
59
59
59
59
59
59
59
Page 45
G
D
S
G
D
S
IO
IO
NC
CD
GND
OUT
VDD
G
D
S
D
G
S
LM393A
V+
GND
LM393A
V+
GND
GND
VIN
VOUT
OUT
IO IO
IO
IO
IO IO
IN
IO
IO
IO
IO
OUT
IO
IO
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CPU HIGH SIDE IN CURRENT
TIE ANALOG SENSOR OPAMP GROUNDS TO SMC GROUND
AND MINIMIZE ROUTE LENGTH TO U5999.
PCB: ENSURE FSB_CPURST_L FANS OUT FROM U1200
SELECT TPM GPIO
NEXT TO THIS GND TRACE AND SMC’S XW5800. PLACE XW5900 NEAR XW5800.
TIE INTO DIGITAL GND VERY CLOSE TO
ANALOG OPAMP PSEUDO-DIFFERENTIALLY
PCB: RUN A TRACE FROM EACH
PULLDOWNS FOR SYSTEM STATE PINS
SMC CRYSTAL
PULLUPS FOR SYSTEM STATE PINS
PULLDOWN UNUSED ANALOG SENSE PINS ON PORT 7.
TURN ON 3.3V VREF ONLY AFTER SMC
I2C ADDR:72(1001000)
(REF DES PRESERVED FOR PLACEMENT PURPOSE)
TPM CRYSTAL
518S0327
LAYOUT NOTE: PLACE CAPACITORS BETWEEN CRYSTAL AND SMC/TPM
518S0328
CPU 1.05V -> SMC 3.3V SHIFTER
DEBUG TESTPOINTS ON SELECTED INPUTS/OUTPUTS
(REF DES PRESERVED FOR PLACEMENT PURPOSE)
PRECISION 3.3V AVREF FOR SMC
SPARE COMPARATER
NO-CONNECT UNUSED PINS
3.3V RAIL AND AVCC RAIL IS UP.
SMC 3.3V -> CPU 1.05V SHIFTER
SMC PULL-UPS
TPM RESET PULLUP
WIRE-OR DIMM OVERTEMP TO SMC
WIRE SMC TO SB PINS
NC OR PULLDOWN UNUSED ANALOG SENSE PINS
GENERATE 0.48V MID-VREF
SENSE GPU VCORE
SMC ALIASES, PULLUPS, AND TESTPOINTS
WHITE SYSLED
SMC I2C BUS PULLUPS (INCLUDING UNUSED ONES)
ALIAS SENSORS INTO SMC I2C BUSSES
POWER BUTTON HEADER
SMC RESET BUTTON
PIN COMPATIBLE WITH TI REF3133 353S1278
SYS POWER BUTTON
AMBIENT LIGHT SENSOR CONNECTOR
PLACE R5908 CLOSE TO SW5901 ONLY USING PADS FOR SWITCH
F-ST-SM
CRITICAL
53398-0476
10K
0
SMC_TPM_GPIO1
1/16W
0
5%
MF-LF
402
SMC_TPM_GPIO2
0
DEVELOPMENT_SMC
DEVELOPMENT_SMC
0
402
MF-LF
1/16W
5%
SOT-363
2N7002DW-X-F
2N7002DW-X-F
SOT-363
10V
402
0.1uF
20% CERM
5%
402
MF-LF
1/16W
6.2K
53398-0276
M-ST-SM
1K
5%
402
MF-LF
1/16W
MF-LF
1/16W
1K
5%
402
3X2MM-SM
WHITE-500MCD
10K
1% MF-LF
402
1/16W
17_INCH_LCD
56.2
FDV301N
SOT23-LF
10K
10K
10K
402
5%
MF-LF
1/16W
NOT_DEVELOPMENT_SMC
10K
10K
10K
10K
4.7K
5%
402
MF-LF
NOSTUFF
1/16W
10K
NOT_DEVELOPMENT_SMC
10K 10K
100K
10K 10K 10K 10K 10K 10K
10K
MF-LF
402
1/16W
SMC_TPM_PP
0
5%
CERM 402
16V
20%
0.01uF
805-1
6.3V
20%
10UF
CERM
402
6.3V
20% CERM-X5R
0.47uF
20%
402
0.1uF
CERM
10V
402
1K
MF-LF
1/16W
5%
MF-LF
1/16W
5%
10K
SM
0
5% 1/16W MF-LF
402
NOSTUFF
RN5VD30A-F
SOT23-5
CRITICAL
10K
MF-LF
402
5%
1/16W
402
1UF
10%
6.3V CERM
SOT23-LF
2N7002
SOT-23
NTR4101P
10K
5% 1/16W MF-LF 402
1/16W MF-LF
5%
402
1K
1/16W MF-LF
5%
402
1K
SOI-1-LF
SPST
SM-LF
DEVELOPMENT
SOI-1-LF
CRITICAL
SOT23-3
ISL60002-33
NOSTUFF
100PF
5% 50V CERM 402
1/16W MF-LF 402
5%
1K
NOSTUFF
2.2K
2.2K
2.2K
2.2K
1/16W
5%
1K
MF-LF 402
1K
1/16W
402
5%
MF-LF
SM-3
20.000M
OMIT
22PF
40250V
5%CERM
22PF
CERM
50V5%402
SM-LF
32.768K
CRITICAL
15PF
5%
402
CERM
50V
15PF
402
CERM
50V
5%
0.01UF
10%
402
CERM
16V
0.1uF
402
20%
10V
CERM
10K 10K
DEVELOPMENT
SPST
SM-LF
10K
10K
10K 10K
051-7032
??
59 97
SMC & TPM SUPPORT
Y5800
XTAL,20.00,80PPM,HC49,SMD,LF
1
197S0165 CRITICAL
POWER_BUTTON_L
I2C_ALS_SDA
PP3V3_S3
=PP3V3_S5_SMC
SMC_EXCARD_OC_L
SMC_GPU_VSENSE
=PP3V3_S5_SMC
CPU_HISIDE_VSENSE
SMC_RST_L
SMC_SUS_CLK
SMC_XDP_TCK_3_3
SMC_CPU_RESET_3_3_L
=PP3V3_S0_FAN
SMB_B_S0_CLK
MAKE_BASE=TRUE
MAKE_BASE=TRUE
SMB_B_S0_DATA
=I2C_ODD_TEMP_SCL =I2C_ODD_TEMP_SDA
SMC_LID
SMB_BSA_DATA
TP_SMB_0_S0_CLK
FUNC_TEST=TRUE
MAKE_BASE=TRUE
SMB_A_S3_DATA
SMB_A_S3_CLK
SMB_B_S0_DATA
TP_SMC_ADAPTER_EN
MAKE_BASE=TRUE
FUNC_TEST=TRUE
TP_ALS_RIGHT
MAKE_BASE=TRUE
SYS_ONEWIRE
SMC_RX_L
SMC_BS_ALRT_L
SMC_TDO SMC_TDI SMC_TCK SMC_BC_ACOK SMC_FWE
SMC_TX_L
SMC_RX_L
UNUSED_SMC_SENSE
MAKE_BASE=TRUE
UNUSED_SMC_SENSE
MAKE_BASE=TRUE
SMC_MEM_ISENSE
SMS_Z_AXIS
SMS_Y_AXIS
SMC_CPU_INIT_3_3_L
NC_ALS_GAIN
MAKE_BASE=TRUE
NC_SMC_BATT_CHG_EN
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SMC_BATT_TRICKLE_EN_L
MAKE_BASE=TRUE
TP_SMC_SYS_LED
MAKE_BASE=TRUE
TP_SMC_RSTGATE_L
SMC_RSTGATE_L
SMC_SYS_LED
SMC_FAN_3_TACH SMC_FAN_3_CTL
SC_TX_L
SMC_TX_L
SMC_ODD_DETECT
SC_RX_L
SMS_ONOFF_L
SMC_TMS
SMC_ONOFF_L
SMC_EXCARD_CP
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V
GND_SMC_AVSS
SMC_REF_IN
MIN_NECK_WIDT=0.2 MM
MIN_LINE_WIDTH=0.4 MM
PP3V3_AVREF_SMC
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.4 MM
MAKE_BASE=TRUE
TP_SMC_XDP_TRST_L
SMC_XDP_TRST_L
SMC_PB7
FUNC_TEST=TRUE
TP_SMC_PB7
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SMC_P20 NC_SMC_P21
MAKE_BASE=TRUE
NC_SMC_P22
MAKE_BASE=TRUE
SMC_P22
SMC_XDP_TMS
TP_SMC_XDP_TMS
MAKE_BASE=TRUE
TP_SMC_XDP_TCK
MAKE_BASE=TRUE
SMC_XDP_TCK
NC_SMC_P26
MAKE_BASE=TRUE
MAKE_BASE=TRUE
NC_SMC_P27
SMC_PROCHOT_3_3_L
SMC_SYS_LED_16B
TPM_GPIO1
TPM_GPIO2
FUNC_TEST=TRUE
TP_SMC_FAN_3_CTL
MAKE_BASE=TRUE
FUNC_TEST=TRUE
TP_SMC_FAN_3_TACH
MAKE_BASE=TRUE
SMC_PB7
SMC_BATT_VSET
ALS_GAIN
=PP3V3_S5_SMC
SMC_XDP_TDO_3_3
SYS_LED_DRV_K
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
TP_SMC_PF1
MAKE_BASE=TRUE
TP_ALS_LEFT
MAKE_BASE=TRUE
FUNC_TEST=TRUE
SMC_PM_G2_EN
SMC_PF0
TP_SMC_SYS_KBDLED
MAKE_BASE=TRUE
FUNC_TEST=TRUE
MAKE_BASE=TRUE
TP_SMC_PF0
MAKE_BASE=TRUE
NC_SMC_SYS_ISET
SMC_SYS_ISET
SMC_P23
NC_SMC_P23
MAKE_BASE=TRUE
=PP3V3_S5_SMC
=PP3V3_S0_FAN
P0V48_SMC_LSREF
GND_NEXT_TO_SMC
SMC_EXTAL
SMC_THRMTRIP
SMC_PROCHOT
CPU_PROCHOT_L
PM_THRMTRIP_L
MAKE_BASE=TRUE
FWH_INIT_L
MAKE_BASE=TRUE
NC_SMS_Y_AXIS
MAKE_BASE=TRUE
NC_SMS_Z_AXIS
SMC_PF1
NC_SMC_ANALOG_ID
MAKE_BASE=TRUE
ALS_LEFT
SMC_P26 SMC_P27
SMC_XTAL
TPM_XTALO
SMB_B_S0_CLK
PP3V3_S3
SMB_0_S0_CLK
SMC_MANUAL_RST_L
ALS_RIGHT
SMC_ADAPTER_EN
NC_SMC_MEM_ISENSE
MAKE_BASE=TRUE
TPM_PP
=I2C_HD_TEMP_SCL =I2C_HD_TEMP_SDA
SMB_GPU_NB_THRM_CLK
SMB_GPU_NB_THRM_DATA
SMC_P21
SMC_ONOFF_L
SMC_TPM_GPIO
SMC_BATT_ISENSE SMC_FWIRE_ISENSE
UNUSED_SMC_SENSE
SMC_REF_GATE1
SC_TX_L
SC_RX_L
MAKE_BASE=TRUE
DIMM_OVERTEMP_L
MAKE_BASE=TRUE
NC_SMC_BATT_ISET
SMB_BSB_DATA
SMB_BSB_CLK
PP3V3_S0
MAKE_BASE=TRUE
SUS_CLK_SB
MAKE_BASE=TRUE
SMC_GPU_ISENSE
I2C_ALS_SCL
SMS_X_AXIS
MAKE_BASE=TRUE
SMB_A_S3_DATA
MAKE_BASE=TRUE
SMB_A_S3_CLK
=SMB_THRM_DATA
SMC_CASE_OPEN
SMC_TPM_PP
TPM_XTALI
MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM
SMC_REF_GATE2
PP3V3_TPM_3VSB
NC_SMC_BATT_VSET
MAKE_BASE=TRUE
I2C_ALS_SDA
=SMB_THRM_CLK
I2C_ALS_SCL
MAKE_BASE=TRUE
TP_SMC_EXCARD_PWR_EN
FUNC_TEST=TRUE
SMC_EXCARD_PWR_EN
FUNC_TEST=TRUE
TP_SMC_PB7
MAKE_BASE=TRUE
=PP3V3_S5_SMC
PP5V_S5
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
SYS_LED_DRV_C
PP3V3_S5
PP5V_S3
MAKE_BASE=TRUE
NC_SMS_X_AXIS
CPU_HISIDE_ISENSE
NC_SMC_SYS_VSET
MAKE_BASE=TRUE
SMC_P20
SMC_BATT_ISET
PM_EXTTS_L
SMC_TPM_RESET_L
SMC_SYS_VSET SMC_BATT_TRICKLE_EN_L SMC_BATT_CHG_EN
SMC_ANALOG_ID
SMB_BSA_CLK
TP_SMB_0_S0_DATA
FUNC_TEST=TRUE
MAKE_BASE=TRUE
SMB_0_S0_DATA
=PP3V3_S5_SMC
TP_PM_G2_EN
FUNC_TEST=TRUE
MAKE_BASE=TRUE
SMC_SYS_KBDLED
CPU_PROCHOT_L
P0V48_SMC_LSREF
R5900
1
2
C5900
1
2
SW5900
1 2
3 4
J2901
5
6
1 2 3 4
J2903
3
4
1 2
LED2901
1
2
R5901
1
2
Q5900
3
1
2
R5902
1
2
SW5901
1 2
3 4
R5903
1 2
R5904
1 2
R5905
1 2
R5906
1 2
R5907
1 2
Y5800
1
2
C5800
1 2
C5801
1 2
Y6700
14
C6704
1 2
C6705
1 2
C5902
1
2
R5910
1 2
R5911
1 2
R5913
1 2
R5912
1 2
R5914
1 2
R5915
1 2
R5917
1 2
R5920
1 2
R5921
1 2
R5922
1 2
R5923
1 2
Q5901
6
2
1
Q5901
3
5
4
C5903
1
2
R5930
1
2
R5931
1
2
R5933
1
2
R5916
1 2
R5830
1 2
R5829
1 2
R5808
1 2
R5832
1 2
R5831
1 2
R5817
1 2
R5815
1 2
R5833
1 2
R5819
1 2
R5821
1 2
R5818
1 2
R5822
1 2
R5823
1 2
R5824
1 2
R5825
1 2
R5826
1 2
R5828
1 2
R5827
1 2
R5995
1 2
C5941
1
2
C5942
1
2
C5940
1
2
C5901
1
2
R5932
1
2
R5924
1 2
XW5900
1 2
R5940
1 2
U5900
5
3
4
1
2
R5941
1 2
C5943
1
2
Q5911
3
1
2
Q5910
3
1
2
R5942
1
2
R5934
1 2
R5935
1 2
U5999
4
6
5
7
8
U5999
4
2
3
1
8
U5940
3
1 2
C5904
1
2
R5908
1
2
5
59
83 59 53
6
59 58
6
58
58
59 58
6
76
60 58
58
58
58
66 65 59
6
59 58
59 58
66
66
58
58
59 58
59 58
59 58
58
60 59 58
5
58
60 58
5
60 58
5
60 58
5
58
58
60 59 58
5
60 59 58
5
59
59
58
58
58
58
58
58
58
58
59 58
60 59 58
5
58
59 58
58
60 58
5
59 58
58
80 76 58
58
58
59
58
58
58
58
58
67
67
59
58
58
59 58
6
58
58
58
58
58
59 58
6
66
65 59
6
59
76
58
58
58
59
7
21 14
7
60 21
58
58
58
58
58
67
59 58
83 59 53
6
58
5
58
58
67
66
66
61
61
58
58
58
58
59
59 58
59 58
29 28
58
58
94
83 76 61 41 26 10
6
23
58
59
58
59 58
59 58
10
58
58
67
67
59
10
59
58
59 58
6
83 82 80 79
6 5
83
80 79 78 77 76 66 65 26
6 5
83
6
76
58
58
58 14
67 58
58
58
58
58
58
58
59 58
6
58
59
7
59
Page 46
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
F-ST-5047
SM1
402
6.3V CERM
1UF
10%
402
CERM
10V
20%
0.1UF
0.1UF
20% 10V
402
CERM
10%
402
6.3V CERM
1UF
LPC+ CONN
SYNC_DATE=12/09/2005
SYNC_MASTER=M38
051-7032
??
60 97
FWH_INIT_L
PCI_CLK_PORT80
SMC_TCK
PM_SUS_STAT_L
LPC_AD<2>
LPC_FRAME_L
SMC_TRST_L SMC_TDO
PM_CLKRUN_L
DEBUG_RST_L
SMC_TMS
BOOT_LPC_SPI_L
SMC_NMI
SMC_RST_L
SMC_TDI
INT_SERIRQ
LPC_AD<3>
SMC_RX_L
SMC_MD1
LPC_AD<1>
LPC_AD<0>
SV_SET_UP
SMC_TX_L
=PP5V_S0_DEBUG
=PP3V3_S5_DEBUG
J6000
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C6000
1
2
C6001
1
2
C6003
1
2
C6002
1
2
59 21
34
59 58
5
67 58 23
67 58 21
67 58 21
58
5
59 58
5
67 58 44 23
5
6
59 58
5
58 22
58
59 58
59 58
5
67 58 23
67 58 21
59 58
5
58
67 58 21
67 58 21
23
59 58
5
6
6
Page 47
SMBDATA
SMBCLK ALERT*
OT2*
DXP2
OT1*
DXN
DXP1
GND
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
I2C ADDR:30(0011000)
5% 1/16W MF-LF
47
402
DEVELOPMENT
0
5% 1/16W MF-LF
402
DEVELOPMENT
0.1UF
10V
20% CERM
402
DEVELOPMENT
UMAX
MAX6695AUB
CRITICAL
DEVELOPMENT
402
CERM
50V
10%
0.001UF
DEVELOPMENT
SM-2MT-BLK-LF
CRITICAL
DEVELOPMENT
NB THERMAL
051-7032
??
61 97
NB_THRM_SPARE_DXP
TSENSE_NB_GPU_DXN
U6100_VCC
SMB_GPU_NB_THRM_DATA SMB_GPU_NB_THRM_CLK
PP3V3_S0
TSENSE_NB_DXP
R6100
1 2
U6100
8
3
2
4
6
5 10
7
9
1
C6101
1
2
J3
3
4
1 2
R6101
1 2
C6100
1
2
59
59
94 83 76 59 41 26 10
6
Page 48
SCK
SO
WP*
SI
VDD
CE*
HOLD*
VSS
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
R6303 SHOULD BE PLACED LESS THAN 2.54MM FROM U6301
R6306-07 SHOULD BE PLACED LESS THAN 2.54MM FROM U2100
IS SHARED WITH SB AND SMC
R6309 NOT NEEDED SINCE SPI ROM
402
CERM
10V
0.1UF
20%
1/16W
402
5%
3.3K
MF-LF
1/16W
5%
3.3K
MF-LF
402
50V
5% 402
CERM
33PF
1/16W MF-LF
402
47
5%
33PF
402
50V
5% CERM
402
5% CERM
33PF
50V
5%
402
47
MF-LF
1/16W
5% 1/16W MF-LF
402
47
CERM
5%
33PF
50V 402
OMIT
SOI
16MBIT
SST25VF016B
402
10K
1/16W
5%
MF-LF
10K
1/16W
5%
MF-LF
402
NOSTUFF
SYNC_DATE=01/05/2006
SYNC_MASTER=M38
97
??
051-7032
SPI BOOTROM
63
SPI_WP_L
SPI_CE_L
SPI_SO_R
SPI_SI_R
=PP3V3_S5_ROM
SPI_SO
SPI_SCLK
SPI_SCLK_R
SPI_HOLD_L
SPI_SI
C6312
1
2
R6301
1
2
R6302
1
2
C6301
1
2
R6307
1 2
C6308
1
2
C6309
1
2
R6303
1 2
R6306
1 2
C6311
1
2
U6301
1
7
6
5
2
8
4
3
R6399
1
2
R6309
1
2
58 22
6
58 22
58 22 58 22
Page 49
IN
OUT
OUT
IN
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ODD FAN
HD FAN
TACH
518S0193
12V DC
GND
GND
FAN 0
12V DC
TACH
MOTOR CONTROL
FAN 1
MOTOR CONTROL
518S0326
NOTE: ADDED TO PROTECT SMC
MF-LF 402
1/16W
10K
5%
10K
5% 1/16W MF-LF 402
20%
NOSTUFF
CERM
25V
0.1UF
603
1.5K
5% 1/4W MF-LF 1206
1206A-03-LF
NTHS5443T1
1/8W
5%
MF-LF
805
1.5K
SOT23
MMBD914XXG
MF-LF
1/8W
5%
0
805
16V
10%
0.47UF
805
X7R
3.9K
5%
1/8W
MF-LF
805
10K
402
5% MF-LF
1/16W
NTHS5443T1
1206A-03-LF
20%
NOSTUFF
25V 603
0.1UF
CERM
1/8W
1.5K
5%
MF-LF
805
805
MF-LF
1/8W
0
5%
16V
10%
805
0.47UF
X7R
3.9K
5%
1/8W
805
MF-LF
MMBD914XXG
SOT23
MF-LF
5%
1206
1.5K
1/4W
402
10K
5% MF-LF
1/16W
OMIT CRITICAL
ELEC
16V
20%
6.3X11-TH-LF
120UF
OMIT
120UF
6.3X11-TH-LF
20% 16V ELEC
CRITICAL
NOSTUFF
MF-LF
1/8W
5%
1.0K
805
NOSTUFF
1.0K
5% 1/8W MF-LF 805
1/8W
5%
MF-LF
0
805
805
0
5%
MF-LF
1/8W
B130LBT01XF
NOSTUFF
SMB
NOSTUFF
SMB
B130LBT01XF
CRITICAL
M-RT-SM
53261-0498
CRITICAL
53261-0598
M-RT-SM
47K
5% 1/16W MF-LF
402
402
MF-LF
1/16W
5%
47K
SOT23-LF
2N7002
SOT23-LF
2N7002
65 97
??
051-7032
Fan 0, 1 & System Temp
SMC_FAN_1_CTL
FAN_TACH0
F1_GATESLOWDN
PP3V3_S5
=PP12V_S0_FAN
FAN_1_PWR
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
PP3V3_S5
=PP3V3_S0_FAN
FAN_1_OUT
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
F0_RCFEEDBK
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
F1_RCFEEDBK
=PP3V3_S0_FAN
SMC_FAN_0_TACH
SMC_FAN_1_TACH
FAN_RPM0
F0_VOLTAGE8R5
F1_VOLTAGE8R5
FAN_TACH1
FAN_RPM1
F0_GATESLOWDN
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
FAN_0_OUT
=PP12V_S0_FAN
SMC_FAN_0_CTL
FAN_0_PWR
MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM
R6500
1
2
R6501
1
2
C6500
1
2
R6502
1
2
Q6500
12367
8
4
5
R6503
1
2
D6500
1
3
R6504
1 2
C6501
1
2
R6505
R6506
1
2
Q6503
12367
8
4
5
C6502
1
2
R6507
1
2
R6508
1 2
C6503
1
2
R6509
D6501
1
3
R6510
1
2
R6511
1
2
C6504
1
2
C6505
1
2
R6512
1
2
R6513
1
2
R6514
1 2
R6515
1 2
D6502
1 2
D6503
1 2
J6500
5
6
1 2 3 4
J6501
6
7
1 2 3 4 5
R6599
1 2
R6598
1 2
Q6502
3
1
2
Q6505
3
1
2
58
83 80
79 78 77 76 66 65 59 26
6 5
66 65
6
83 80
79 78 77 76 66 65 59 26
6 5
66 65 59
6
66 65 59
6
58
58
66 65
6
58
Page 50
G
D
S
IN
OUT
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
CPU FAN
518S0328
ODD TEMP SENSOR
FAN 2
HD TEMP SENSOR
12V DC
TACH GND
MOTOR CONTROL
518S0193
518S0193
I2C ADDR:0X90(1001000)
I2C ADDR:0X92(1001001)
402
CERM
10V
0.1UF
HD_TEMP_SENSE
20%
402
CERM
10V
0.1UF
20%
2N7002
SOT23-LF
CRITICAL
ELEC
16V
20%
6.3X11-TH-LF
120UF
OMIT
MF-LF 402
10K
1/16W
5%
M-RT-SM
53261-0498
HD_TEMP_SENSE
CRITICAL
NTHS5443T1
1206A-03-LF
MMBD914XXG
SOT23
NOSTUFF
CERM
0.1UF
603
25V
20%
1.5K
5%
1/8W
MF-LF
805
0
1/8W
805
MF-LF
5%
0.47UF
10%
805
X7R
16V
3.9K
5%
1/8W
MF-LF
805
1206
1.5K
5% 1/4W MF-LF
MF-LF
10K
402
5% 1/16W
NOSTUFF
1/8W
1.0K
805
5% MF-LF
805
0
5%
1/8W
MF-LF
NOSTUFF
SMB
B130LBT01XF
M-RT-SM
53261-0498
CRITICAL
53398-0476
F-ST-SM
CRITICAL
47K
5% 1/16W MF-LF
402
CERM
0.01UF
402
HD_TEMP_SENSE
16V
20%
402
CERM
0.01UF
HD_TEMP_SENSE
16V
20%
402
17_INCH_LCD
CERM
0.01UF
16V
20%
402
0.01UF
CERM
17_INCH_LCD
16V
20%
051-7032
??
66 97
Fan 2 & HD Temp
SMC_FAN_2_CTL
F2_VOLTAGE8R5
=PP3V3_S0_ODD_TSENS
=PP3V3_S0_HD_TSENS
GND_CHASSIS_ODD_TEMP
GND_CHASSIS_ODD_TEMP
CPU_HS_ZH608
CPU_HS_ZH608
FAN_TACH2
=PP12V_S0_FAN
F2_GATESLOWDN
MIN_NECK_WIDTH=0.25MM
FAN_2_OUT
MIN_LINE_WIDTH=0.5MM
F2_RCFEEDBK
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
SMC_FAN_2_TACH
=I2C_HD_TEMP_SDA
=I2C_ODD_TEMP_SDA
=I2C_HD_TEMP_SCL
=I2C_ODD_TEMP_SCL
=PP3V3_S0_FAN
PP3V3_S5
FAN_RPM2
FAN_2_PWR
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.5MM
R6600
1
2
J6601
5
6
1 2 3 4
Q6600
12367
8
4
5
D6600
1
3
C6600
1
2
R6601
1
2
R6602
1 2
C6601
1
2
R6603
R6604
1
2
R6605
1
2
R6606
1
2
R6607
1 2
D6601
1 2
J6602
5
6
1 2 3 4
J6600
5
6
1 2 3 4
R6697
1 2
C6650
12
C6651
12
C6653
12
C6652
12
C6654
1
2
C6655
1
2
Q6602
3
1
2
C6602
1
2
58
6
6
66
6
66
6
66
9
66
9
65
6
58
59
59
59
59
65 59
6
83
80 79 78 77 76 65 59 26
6 5
Page 51
IN
IO
IO
IO
LAD1 LAD2
LCLK LFRAME* LRESET* LPCPD* SERRIRQ
LAD0
CLKRUN/GPIO*
PP/GPIO GPIO_EXPRESS_00 GPIO/SM_DAT GPIO/SM_CLK
XTALI/32K_IN
TESTBI/BADD/GPIO
TESTI
3V0 3V1 3V2
3VSB
VNC
VBAT
XTALO
GND2
GND3
GND0
GND1
LAD3
IO
IO
IN
IN
IO
IN
IN
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
(INT PD)
GND
NC
NC
VSB
VDD
VDD
VDD
NC
PP GPIO
CLKRUN*
NC
NC
NC
BASE ADDR = 0X2E/2F
LAYOUT NOTE: PLACE WHERE ACCESSIBLE
LAYOUT NOTE: PLACE R6702-03 WHERE ACCESSIBLE
NOTE: SINCE CURRENT OF VSB IS NOT YET ON SPEC, 1/8W (R6704/R6705) IS USED FOR NOW
TESTBI/BADD
GPIO2
BASE ADDR = 0X4E/4F
402
X5R
16V
10%
0.1UF 0.1UF
402
X5R
16V
10%
0.1UF
10% 16V X5R 402
0.1UF
10% 16V X5R 402
NOSTUFF
0
5% 1/16W MF-LF 402
OMIT
TSSOP
TPM
MF-LF
1/16W
5%
10K
402
NOSTUFF
5% 1/16W MF-LF
10K
402
805
MF-LF
1/8W
5%
0
NOSTUFF
805
MF-LF
1/8W
5%
0
0
5%
MF-LF
1/16W
402
MF-LF
5%
0
NOSTUFF
1/16W
402
TPM
SYNC_DATE=01/05/2006
SYNC_MASTER=M38
051-7032
??
67 97
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=3.3V
PP3V3_TPM_3VSB
TPM_PP
TPM_GPIO1
TPM_GPIO2
LPC_AD<3>
=PP3V3_S0_TPM
=PP3V3_S3_TPM
PM_CLKRUN_L
TPM_XTALI TPM_XTALO
=PP3V3_S0_TPM
INT_SERIRQ
PM_SUS_STAT_L
LPC_FRAME_L
PCI_CLK_TPM
LPC_AD<2>
LPC_AD<1>
LPC_AD<0>
TPM_BADD
TPM_RST_L
TPM_LRESET_L
SMC_TPM_RESET_L
C6700
1
2
C6701
1
2
C6702
1
2
C6703
1
2
R6700
1
2
U6700
10 19 24
5
15
4
111825
2
1
6
26 23 20 17
21 22
28
16
7
27
9 8
12
3
13 14
R6702
1
2
R6703
1
2
R6704
1 2
R6705
1
2
R6798
1 2
R6799
1 2
59
59
59
59
60 58 21
67
6
6
60 58 44 23
5
59
59
67
6
60 58 23
60 58 23
60 58 21
34
60 58 21
60 58 21
60 58 21
6
59 58
Page 52
IN IN
IN
IN
OUT
NR/FB
EN
IN
OUT
GND
GND TAB
GPIO1
GPIO0
GPIO2
SPDIF-OUT
AVDD1
AVDD2
DVDD_CORE3
DVDD_CORE1
BIT_CLK SYNC SDATA_OUT SDATA_IN
PORT-C_R
PORT-D_L_HP PORT-D_R_HP
CD-G
VOLUME_DOWN
VOLUME_UP
PC_BEEP
GPIO3/SPDIFIN
SENSE_A SENSE_B
PORT-A_L_HP PORT-A_R_HP
PORT-E_L PORT-E_R
AVSS3
AVSS1
DVSS2
DVSS3
VREF_FILT
AFILT1 AFILT2
NC1 NC2
CAP2
VREFOUT-D
VREFOUT-A
VREFOUT-B
VREFOUT-C
PORT-B_L PORT-B_R
PORT-F_R_HP
PORT-F_L_HP
PORT-C_L
CD-R
CD-L
RESET*
MIC1
HP
LO
MIC2
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
4.5V POWER SUPPLY FOR CODEC AND LINE IN AMP
NC
APN: 353S1233
MIC INPUT TO BOTH L&R
NC
14
11
10
10
10
10
13
15
10
APPLE P/N 353S1345
AUDIO CODEC
NC
NC
NC
NC
NC
12
NC
NC
0.1UF
16V X5R
10%
402
CERM 402
6.3V
10%
1UF
AUD_REG
MF-LF
100K
5%
402
1/16W
AUD_REG
16V
0.1UF
X5R
10%
402
AUD_REG
603
X5R
6.3V
20%
AUD_REG
10UF
AUD_REG
402
MF-LF
1/16W
1%
1K
10UF
TANT
SMA-LF
20%
6.3V
39
402
5% 1/16W MF-LF
402
1000PF
X7R
25V
10%
402
10% 25V X7R
1000PF
402
10%
1000PF
25V X7R X7R
25V 402
10%
1000PF
6.3V
20%
10UF
TANT
SMA-LF
402
1000PF
X7R
25V
10%
X7R 402
25V
10%
1000PF
20%
100UF
16V
ELEC
6.3X5.5-SM
20%
100UF
16V
ELEC
6.3X5.5-SM
X7R
1000PF
402
25V
10%
29.4K
1/16W MF-LF
1%
402
AUD_REG
1/16W
78.7K
1% MF-LF
402
AUD_REG
1000PF
10% X7R
402
25V
1000PF
402
10% 25V X7R
SOT223-6
TPS79501
AUD_REG
10UF
603
6.3V X5R
20%
AUD_REG
1UF
10%
6.3V 402
CERM
10%
402
CERM
6.3V
1UF
CERM
402
10%
6.3V
1UF
AUD_REG
0603
180-OHM-1.5A
1/16W MF-LF
0
402
5%
180-OHM-1.5A
0603
SMA-LF
TANT
6.3V
10UF
20%
LQFP
STAC9220
LEMENU
180-OHM-1.5A
0603
805
5%
50V
CERM
1000PF
MF-LF
0
1/16W
402
5%
MF-LF
1/16W
5%
402
39
805
1000PF
CERM
50V
5%
1000PF
25V 402
10% X7R
100K
MF-LF
1/16W 402
5%
805-1
CERM
6.3V
20%
10UF
1/8W
5%
0
MF-LF 805
68
051-7032
97
SYNC_MASTER=AUDIO
??
SYNC_DATE=03/30/2006
AUDIO: CODEC
TP_AUD_BI_PORT_E_R
AUD_VREF_PORT_B
AUD_BI_PORT_B_L AUD_BI_PORT_B_R
AUD_BYPASS
AUD_ANALOG_FILT_2
TP_AUD_BI_PORT_E_L
ACZ_SDATAIN_CHIP
ACZ_SDATAOUT
AUD_ANALOG_FILT_1
AUD_VREF_FILT
NC_AUD_VREF_PORT_D
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
5V_REG_IN
VOLTAGE=5V
AUD_4V5_SHDN_L
ACZ_RST_L
AUD_GPIO_1
ACZ_BITCLK
VOLTAGE=3.3V
=PP3V3_S0_AUDIO
AUD_BI_PORT_A_R
AUD_SENSE_B
AUD_SENSE_A
AUD_BI_PORT_F_L AUD_BI_PORT_F_R
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
PP4V5_AUDIO_ANALOG
VOLTAGE=4.5V
NC_AUD_VREF_PORT_A
AUD_BI_PORT_A_L
AUD_SPDIF_OUT_CHIP
PPV_3V3_AUDIO_CODEC
MIN_NECK_WIDTH=0.20MM VOLTAGE=3.3V
GND_AUDIO_CODEC
AUD_SPDIF_OUT
AUD_BI_PORT_B_RAUD_BI_PORT_B_L
VREG_FB
AUD_SPDIF_IN
BEEP
VOLTAGE=5V
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
=PP5V_S5_AUDIO
=PP3V3_S0_AUDIO
GND_AUDIO_CODEC
AUD_GPIO_0_A
AUD_GPIO_0
AUD_GPIO_1
AUD_GPIO_1_A
AUD_GPIO_2
AUD_BI_PORT_C_L
BAL_IN_R
NC_VOL_DOWN
NC_AUD1 NC_AUD2
TP_AUD_BI_PORT_D_L
AUD_BI_PORT_C_R
NC_AUD_VREF_PORT_C
ACZ_SDATAIN<0>
=PP4V5_S0_AUDIO_ANALOG
MIN_LINE_WIDTH=0.6MM VOLTAGE=5V
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
VOLTAGE=4.5V
MIN_LINE_WIDTH=0.6MM
PP4V5_AUDIO_ANALOG
VOLTAGE=0V
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
GND_AUDIO_CODEC
NC_VOL_UP
BAL_IN_COM
BAL_IN_L
ACZ_SYNC
AUD_GPIO_0
TP_AUD_BI_PORT_D_R
C6801
1
2
L6801
1 2
R6800
1
2
C6800
1
2
R6801
1
2
C6821
1
2
C6825
1
2
R6803
1
2
C6823
1
2
C6822
1
2
R6802
1 2
C6810
1
2
R6808
1 2
C6829
1
2
C6832
1
2
C6833
1
2
C6834
1
2
C6807
1
2
C6813
1
2
C6812
1
2
C6802
1
2
C6803
1
2
C6830
1
2
R6811
1
2
R6810
1
2
C6835
1
2
C6836
1
2
VR6800
1
3 6
2
5
4
C6826
1
2
C6808
1
2
C6809
1
2
C6811
1
2
L6800
1 2
R6812
1 2
C6804
1
2
U6800
30 31
25
38
26
42
6
33
19
18
20
1
9
4
7
45 46
44
47
40 43
12
39 41
21 22
23 24
35 36 14
15
16 17
11
8
5
13 34
48
10
3
2
27
37
28
29 32
L6802
1 2
C6805
1
2
R6814
1 2
R6807
1 2
C6806
1
2
MIN_LINE_WIDTH=0.30MM
74
74 68
68
21
21
68
21
74 73 72 68
6
74
74
74
74
74
74 68
74
74 73 72 68
73
68 74 68
73
6
74 73 72 68
6
74 73 72 68
72 68
68 74 73
74
72
74
72
21
6
74 68
74 73 72 68
74
74
21
68
Page 53
PGND
VDD
G1 G2
CHOLD
AGND
PAD
THM
NC
SHDN*
FS2
FS1
INL-
INL+
INR-
REG
INR+
OUTL+ OUTL+
OUTL­OUTL-
C1+
C1-
OUTR+ OUTR+
OUTR­OUTR-
SS
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
NC
GAIN AND SWITCHING FREQUENCY STUFF OPTIONS
MODULATION SETTING: LOW EMI
GAIN SETTINGS: +19DB
APPLE P/N 353S0680
SPEAKER AMP
MF-LF
1/16W
10K
1%
402
MAX9714
QFN-LF
SM
OMIT
2N7002DW-X-F
SOT-363
2N7002DW-X-F
SOT-363
CERM 402
50V
5%
100PF
100PF
5% 50V CERM 402
47K
MF-LF
402
5%
1/16W
402
MF-LF
1/16W
10K
5%
402
1/16W MF-LF
5%
0
1/16W 402
5%
0
MF-LF
NOSTUFF
402
MF-LF
1/16W
5%
0
NOSTUFF
NOSTUFF
5%
402
MF-LF
1/16W
0
0603
180-OHM-1.5A
X7R
10% 50V
0.1UF
603-1
0603
180-OHM-1.5A
10% 16V
805
X7R
0.47UF
FERR-250-OHM
SM-1
10% 16V
0.47UF
805
X7R
805
X7R
16V
10%
0.47UF
180-OHM-1.5A
0603
603
25V
10% X5R
1UF
805
0.47UF
16V X7R
10%
16V X7R 805
10%
0.47UF
220UF
20% 16V
ELEC
6.3X8-SM
180-OHM-1.5A
0603
402
MF-LF
1/16W
5%
0
220UF
ELEC
16V
6.3X8-SM
20%
1UF
10% 25V X5R 603
5%
47K
1/16W SM-LF
1%
10K
MF-LF
1/16W
402
50R28
0603
1000-OHM-200MA
50V CERM 402
100PF
5%
402
CERM
100PF
5% 50V
1000-OHM-200MA
0603
1000-OHM-200MA
0603
0603
1000-OHM-200MA
16V
20%
0.1UF
603
CERM
20%
CERM
16V 603
0.1UF
1210
CERM
16V
10%
10UF
1210
CERM
16V
10%
10UF
10%
1210
CERM
16V
10UF
25V
1000PF
10% X7R
402
25V
10% X7R
402
1000PF 1000PF
402
10% 25V X7R
1000PF
25V
10% X7R
402
SYNC_DATE=03/30/2006
AUDIO: SPEAKER AMP
051-7032
97
??
SYNC_MASTER=AUDIO
72
MIN_NECK_WIDTH=0.3MM
AUDSAMPOUTLN
MIN_LINE_WIDTH=0.5MM
NET_SPACING_TYPE=AUDIO
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM VOLTAGE=12V
PP12V_AUD_SPKRAMP_PLANE
NET_SPACING_TYPE=AUDIO
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTR_N
NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTR_P
NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM
AUD_GPIO_0_A
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
NET_SPACING_TYPE=AUDIO
GND_AUDIO_SPKRAMP_PLANE
=PP3V3_S0_AUDIO
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTL_P
MIN_LINE_WIDTH=0.5MM
NET_SPACING_TYPE=AUDIO
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTL_N
NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM
GND_AUDIO_SPKRAMP_PLANE
GND_AUDIO_SPKRAMP_PLANE
AUD_SAMP_INL_P
NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM
AUDSAMPOUTLP
MIN_NECK_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
AUD_MAX9714_VREG
MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
SPKRAMP_SS
AUD_SAMP_SHDN_L
AUD_SAMP_G2
MIN_NECK_WIDTH=0.3MM
NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM
AUDSAMPOUTRN
AUD_SAMP_INR_N
GND_AUDIO_SPKRAMP_PLANE
AUD_SAMP_G2
AUD_SAMP_FS1
AUD_SAMP_FS2
AUD_SAMP_INL_N
AUD_SAMP_INR_P
AUD_SAMP_G1
GND_AUDIO_SPKRAMP_PLANE
AUDSAMPOURTP
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.3MM
NET_SPACING_TYPE=AUDIO
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
GND_AUDIO_SPKRAMP
NET_SPACING_TYPE=AUDIO
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUDSAMPCPN
MIN_NECK_WIDTH=0.15MM
AUDSAMPCPP
MIN_LINE_WIDTH=0.2MM
AUD_SAMP_FS1
AUDSAMPINLP
AUDSAMPINRP
AUDSAMPINLN
AUD_SAMP_FS2
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
AUD_MAX9714_CHOLD
AUD_SAMP_G1
AUD_BI_PORT_C_L
=PP3V3_S0_AUDIO
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
=PP12V_S0_AUDIO_SPKRAMP
VOLTAGE=12V
NET_SPACING_TYPE=AUDIO
AUD_BI_PORT_C_R
GND_AUDIO_CODEC
GND_AUDIO_CODEC
AUDSAMPINRN
AUD_DEBOUNCE
SPKRAMP_MUTE
=PP3V3_S0_AUDIO
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
PP3V3_INTERCON
L7202
1 2
L7201
1 2
L7203
1 2
C7208
1
2
L7204
1 2
C7209
1
2
L7200
1 2
C7204
1 2
C7205
1 2
C7214
1
2
C7207
1 2
C7206
1 2
C7200
1
2
R7208
1
2
C7217
1
2
C7202
1
2
RP7200
1 2 3 4
8 7 6 5
R7212
1
2
XC7200
1
L7205
1 2
C7215
1
2
C7216
1
2
L7206
1 2
L7207
1 2
L7208
1 2
C7219
1
2
C7218
1
2
C7203
1
2
C7223
1
2
C7201
1
2
C7210
1
2
C7211
1
2
C7212
1
2
C7213
1
2
R7214
1
2
U7200
13
6
5
7
19 20
17 18
10
9
16
15
8
31
29
32
30
27
25
28
26
1
2
23
24
14
11
12
33
3
4
21
22
XW7201
1 2
Q7200
3
5
4
Q7200
6
2
1
C7220
1
2
C7221
1
2
R7213
1 2
R7215
1 2
R7217
1 2
R7216
1
2
R7218
1
2
R7219
1 2
73
73
68
74 72
74
73 72
68
6
73
73
74 72
74 72
72
74 72
72
72
72
72
74 72
74
6
72
72
72
68
74 73 72 68
6
6
68
74 73 72 68
74 73 72 68
74 73 72 68
6
Page 54
TYPE_DET TIP
GND
VIN VCC
LED
GND_2
GND_1
RING
TIP_DET
IN
IN
IN IN
VCC
VOUT
GND
SHELL
LED
TABLE_ALT_ITEM
TABLE_ALT_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PART NUMBER
ALTERNATE FOR
PART NUMBER
BOM OPTION
REF DES
COMMENTS:
TABLE_ALT_HEAD
APPLE P/N 514-0338
APPLE P/N 514-0341 (M50)
SPEAKER CABLE CONNECTOR
APPLE P/N 518S0325
NC
LINE IN JACK
LINE OUT JACK
NC
TO FHB CONNECTOR PAGE 47
TO POWER SUPPLY PAGE 6
100PF
50V CERM
5%
402402
50V
5%
CERM
100PF
0
402
MF-LF
5%
1/16W
402
5% 50V CERM
100PF
5%
50V
CERM
100PF
402
100PF
CERM
50V 402
5%
100PF
CERM
50V
5%
402
180-OHM-1.5A
0603
0603
180-OHM-1.5A
180-OHM-1.5A
0603
0603
180-OHM-1.5A
180-OHM-1.5A
0603
0603
180-OHM-1.5A
180-OHM-1.5A
0603
180-OHM-1.5A
0603
180-OHM-1.5A
0603
0603
180-OHM-1.5A
180-OHM-1.5A
0603
180-OHM-1.5A
0603
0603
180-OHM-1.5A
0603
180-OHM-1.5A
0603
180-OHM-1.5A
180-OHM-1.5A
0603
180-OHM-1.5A
0603
0603
180-OHM-1.5A
0603
180-OHM-1.5A
CRITICAL
M-RT-SM
53261-0798
F-ANG-TH
OPTI-AUD-OUT-JCK-M50
CRITICAL
180-OHM-1.5A
0603
50V CERM
100PF
5%
402
0603
180-OHM-1.5A
5% 50V CERM 402
100PF
0603
180-OHM-1.5A
0603
180-OHM-1.5A
0603
180-OHM-1.5A
402
CERM
50V
5%
100PF
180-OHM-1.5A
0603
SM
0405
5.6V-15A
0405
5.6V-15A
5.6V-15A
0405
NOSTUFF
5.6V-15A
0405
5.6V-15A
0405
4.7K
NOSTUFF
402
MF-LF
5%
1/16W
47K
1/16W
5%
MF-LF
402
NOSTUFF
10V
20%
0.1UF
CERM 402
805-1
CERM
20%
10UF
6.3V
0603
180-OHM-1.5A 180-OHM-1.5A
0603
5%
0
1/16W 402
MF-LF
402
100PF
5% 50V CERM
5%
402
39
1/16W MF-LF
5%
402
CERM
50V
100PF
0.1UF
20%
402
10V CERM
CERM
5%
402
50V
100PF
0
5%
MF-LF
1/8W
805
5%
402
100K
1/16W MF-LF
F-5.5-DEG-TH
WO-RIB-M50
OPTI-AUD-JCK
CRITICAL
0603
180-OHM-1.5A
5% CERM
50V 402
100PF
CERM
5% 50V
100PF
402
73 97
??
SYNC_MASTER=AUDIO
SYNC_DATE=03/30/2006
051-7032
AUDIO: CONNECTORS
126S0091 126S0092
FACTORY SHORTAGE
C6802,C6803
126S0091 126S0092
FACTORY SHORTAGE
C7403,C7404
GND_CHASSIS_AUDIO_EXTERNAL_J
NET_SPACING_TYPE=AUDIO
AUD_MIC_IN_N_CONN
AUD_MIC_IN_P_CONN
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=0.25MM MIN_NECK_WIDTH=0.2MM
AUD_SPDIFOUT_GND
GND_CHASSIS_AUDIO_EXTERNAL_J
AUD_SPDIF_OUT_JACK
AUD_LO_GND_JACK
MIN_NECK_WIDTH=0.4MM MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.3MM
PP3V3_AUDIO_SPDIF_JACK
AUD_LO_DET2_JACK
MIN_LINE_WIDTH=0.3MM
AUD_LO_R_JACK
MIN_NECK_WIDTH=0.2MM
AUD_LO_DET1_JACK
AUD_LO_L_JACK
MIN_NECK_WIDTH=0.2MMMIN_LINE_WIDTH=0.3MM
AUD_GPIO_1_A
=PP3V3_S0_AUDIO
AUD_MIC_IN_N
NET_SPACING_TYPE=AUDIO
NET_SPACING_TYPE=AUDIO
AUD_MIC_IN_P
NET_SPACING_TYPE=AUDIO AUD_MIC_IN_N_EMI
NET_SPACING_TYPE=AUDIO AUD_MIC_IN_P_EMI
NET_SPACING_TYPE=AUDIO
GND_AUDIO_MIC_CONN
MIN_NECK_WIDTH=0.2MM NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=0.5MM
AUD_SPKR_OUTL_N
AUD_SPKR_OUTL_P
NET_SPACING_TYPE=AUDIO MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.2MM
AUD_LI_DET_JACK
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_LI_L_JACK
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_SPDIF_IN_JACK
AUD_SPDIFIN_GND
AUD_PORT_F_L
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_SPDIF_IN_1
AUD_SPDIF_OUT
GND_CHASSIS_AUDIO_EXTERNAL_J
GND_CHASSIS_AUDIO_EXTERNAL
MIN_NECK_WIDTH=0.2MM
AUD_PORT_A_L
MIN_LINE_WIDTH=0.3MM
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
AUD_PORT_A_R
MIN_NECK_WIDTH=0.25MM
GND_AUDIO_CODEC
MIN_LINE_WIDTH=0.6MM
AUD_LO_DET1
MIN_NECK_WIDTH=0.2MM
AUD_SPKR_OUTR_P
NET_SPACING_TYPE=AUDIO
MIN_LINE_WIDTH=0.5MM
GND_AUDIO_CODEC
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.5MM
AUD_SPKR_OUTR_N
NET_SPACING_TYPE=AUDIO
PP3V3_AUDIO_SPDIF_JACK
AUD_PORT_F_R
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_LI_DET_H
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_LO_DET2
AUD_SPDIF_IN
AUD_LI_R_EMI
MIN_NECK_WIDTH=0.15MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.2MM
AUD_LI_L_EMI
AUD_LI_DET_EMI
MIN_LINE_WIDTH=0.2MM MIN_NECK_WIDTH=0.15MM
AUD_SPDIF_IN_EMI
AUD_LO_GND_EMI
MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.4MM
AUD_LO_DET1_EMI
PP3V3_AUDIO_SPDIF_EMI
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
AUD_LO_R_EMI
MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM
AUD_LO_DET2_EMI
AUD_SPDIF_OUT_EMI
=PP3V3_S0_AUDIO
MIN_NECK_WIDTH=0.2MM
AUD_LO_L_EMI
MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.15MM
AUD_LI_R_JACK
MIN_LINE_WIDTH=0.2MM
MIN_LINE_WIDTH=0.4MM MIN_NECK_WIDTH=0.3MM
AUD_LI_GND_JACK
GND_CHASSIS_AUDIO_INTERNAL
MIN_NECK_WIDTH=0.3MM
AUD_LI_GND_EMI
MIN_LINE_WIDTH=0.4MM
C7303
1
2
C7302
1
2
C7301
1
2
C7300
1
2
C7318
1
2
C7317
1
2
C7315
1
2
C7311
1
2
R7302
1
2
C7324
1
2
C7323
1
2
L7301
1 2
L7302
1 2
L7303
1 2
L7304
1 2
L7305
1 2
L7306
1 2
L7307
1 2
L7309
1 2
L7310
1 2
L7312
1 2
L7313
1 2
L7314
1 2
L7315
1 2
L7316
1 2
L7320
1 2
L7322
1 2
L7323
1 2
L7324
1 2
L7328
1 2
J7301
8
9
1 2 3 4 5 6 7
J7303
9
1
10 11
12 13
2
3
4
5
6
8
7
L7325
1 2
C7314
1
2
L7317
1 2
C7312
1
2
L7327
1 2
L7319
1 2
L7318
1 2
C7313
1
2
L7326
1 2
XW7300
1 2
DZ7301
13
24
DZ7302
1 3
2 4
DZ7304
1 3
2 4
DZ7300
1 3
2 4
DZ7303
1 3
2 4
R7304
1
2
R7303
1
2
C7325
1
2
L7329
1 2
L7330
1 2
R7305
1
2
C7328
1
2
R7306
1 2
C7322
1
2
C7321
1
2
R7307
1 2
R7308
1
2
J7300
8
1
10 11 12 13
2 3
4
5 6
7
9
L7300
1 2
74 73
47
47
74 73
73
74 68
74 73 72 68
6
74
74
72
72
74
68
74 73
6
74
74
74 73 72 68
74
72
74 73 72 68
72
73
74
74
74
68
74 73 72 68
6
6
Page 55
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
OUTR
CEXT
GND
INR
OUTL
SHDN* INL
VCC
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
UNUSED PORTS PORT E
JACK SENSE PULL UPS(PLACE NEXT TO CODEC)
MICROPHONE IMPEDANCE MATCHING CIRCUIT
PORT A HP/LI
PORT D
PORT F LI/LO
PORT C BI SPEAKERS
PORT F LI/LO
USED PORTS
PLACE NEAR ENTRY TO SPEAKER
PLACE AT J7303
UNUSED PORT TERMINATION
PORT A HP/LI
NC
PORT F (LI) PLUG DETECT
AMP GROUND PLANE
PLACE NEXT TO L6802
PLACE NEXT TO L6800
AUDIO GROUND RETURNS
PLACE ACROSS GROUND SPLIT
PLACE NEAR HEADPHONE PORT
PORT B MIC IN
PORT A/H (LO/DIG_OUT) PLUG DETECT (E TELLS H TO COME ON)
NC
NC
1/8W
5%
0
805
NOSTUFF
MF-LF
MF-LF
1% 1/16W
402
20.0K
SOT23-LF
2N7002
20%
402
10V
0.1UF
CERM
1/16W MF-LF
5%
402
47K
270K
5% MF-LF
402
1/16W
10V
20%
0.1UF
CERM 402
47K
MF-LF
1/16W
5%
402
0.1UF
402
10V
20% CERM
MF-LF
5%
47K
402
1/16W
5%
4.7
805
1/8W
MF-LF
1/8W
5%
4.7
MF-LF
805
5%
MF-LF
805
4.7
1/8W
805
1/8W
5%
4.7
MF-LF
ELEC
16V
100UF
20%
6.3X5.5-SM
6.3X5.5-SM
20% 16V
ELEC
100UF
MF-LF
1/16W
100K
5%
402
5% MF-LF
1/16W 402
470K
22K
1/16W MF-LF
402
5%
1/16W
5%
22K
MF-LF 402
402
MF-LF
1%
5.11K
1/16W
0.1UF
16V 402
X5R
10%
1% 1/16W MF-LF
5.11K
402
402
X5R
16V
10%
0.1UF
402
X5R
16V
10%
0.1UF
0.1UF
10%
402
16V X5R
X5R
0.1UF
16V 402
10% 50V
0.1UF
10% X7R
603-1
SM
2.2K
5% 1/16W
402
MF-LF
402
MF-LF
1/16W
100K
5%
1/10W
5%
MF-LF
603
330
CERM
50V
820PF
805
10%
1/16W
22K
402
MF-LF
5%
1/16W
5%
22K
MF-LF 402
10% 16V
402
X5R
0.1UF
2N7002DW-X-F
SOT-363
SOT-363
2N7002DW-X-F
0
5%
1/8W
805
MF-LF
1/16W MF-LF
5%
100K
402
2N7002DW-X-F
SOT-363 SOT-363
2N7002DW-X-F
402
39.2K
1/16W
1% MF-LF MF-LF
402
1%
39.2K
1/16W
0
805
5%
MF-LF
1/8W
MF-LF
1/8W
5%
805
0
AUD_REG
UCSP-LF
MAX9890
CERM-X5R
6.3V
0.22UF
402
10%
NOSTUFF
MF-LF
805
5%
1/8W
0
805
MF-LF
NOSTUFF
0
1/8W
5%
1% MF-LF
1/16W 402
10K
ELEC
16V
6.3X8-SM
20%
220UF
402
2.2K
5%
MF-LF
1/16W
SMA-LF
16V
3.3UF
TANT
10%
3.3UF
SMA-LF
10%
TANT
16V
5%
1/8W
0
805
NOSTUFF
MF-LF
0
5%
1/8W
NOSTUFF
MF-LF
805
SYNC_DATE=03/30/2006
SYNC_MASTER=AUDIO
051-7032
97
??
74
AUDIO: POWER SUPPLIES
GND_AUDIO_CODEC
AUD_PORT_A_L
AUD_PORT_F_DET_L
AUD_PORT_A_L1
GND_AUDIO_CODEC
GND_AUDIO_CODEC
AUD_LO_DET2_1
U7400_CEXT
AUD_PORT_A_R2
AUD_SENSE_A
AUD_SENSE_B
GND_AUDIO_CODEC
AUD_PORT_E_DET_L
AUD_BI_PORT_F_R
AUD_LO_DET1_INV
AUD_TYPE_DET_EN
AUD_PORT_A_R1
AUD_PORT_A_L1 AUD_PORT_A_R1
AUD_PORT_A_L2 AUD_PORT_A_R2
GND_CHASSIS_AUDIO_EXTERNAL_J
GND_AUDIO_CODEC
GND_AUDIO_SPKRAMP_PLANE
GND_CHASSIS_AUDIO_EXTERNAL_J
GND_AUDIO_SPKRAMP
GND_AUDIO_CODEC
NET_SPACING_TYPE=AUDIO MIN_NECK_WIDTH=0.25MM
VOLTAGE=0V
GND_AUDIO
MIN_LINE_WIDTH=0.6MM
=PP3V3_S0_AUDIO
AUDLINDETH
=PP3V3_S0_AUDIO
AUD_SENSE_B
AUD_PORT_A_L2
AUD_PORT_A_R1
AUD_BI_PORT_A_L
AUD_BI_PORT_A_R
PP4V5_AUDIO_ANALOG
=PP3V3_S0_AUDIO
GND_AUDIO_CODEC
AUD_LO_DET2
AUD_LO_DET1_1
AUD_PORT_A_DET_L
GND_AUDIO_CODEC
BAL_IN_L
AUD_PORT_A_L2
AUD_GPIO_2
AUD_SENSE_B
AUD_PORT_A_R
BAL_IN_COM
BAL_IN_R
GND_AUDIO_CODEC
GND_AUDIO_CODEC
PP4V5_AUDIO_ANALOG
AUD_LI_DET_H
AUD_PORT_A_R2
AUD_PORT_A_L1
AUD_MIC_IN_N
NET_SPACING_TYPE=AUDIO
AUD_MIC_IN_P
NET_SPACING_TYPE=AUDIO
GND_AUDIO_CODEC
AUD_BI_PORT_B_L
AUD_LO_DET1_1
GND_AUDIO_CODEC
AUD_MIC_P1
AUD_VREF_PORT_B
AUD_MIC_INTERCON
GND_AUDIO_CODEC
AUD_LO_DET1
AUD_GPIO_1_A
AUD_SENSE_A
AUD_BI_PORT_F_L
AUD_PORT_F_L
AUD_PORT_F_L1
AUD_PORT_F_R
AUD_PORT_F_R1
R7411
1 2
R7410
1 2
R7412
1 2
R7405
1
2
Q7401
3
1
2
C7401
1
2
R7404
1 2
R7409
1
2
C7400
1
2
R7400
1 2
C7402
1
2
R7408
1 2
R7414
1 2
R7415
1 2
R7416
1 2
R7417
1 2
C7403
1 2
C7404
1 2
R7420
1
2
R7413
1
2
R7418
1
2
R7419
1
2
R7422
1
2
C7408
1
2
R7421
1
2
C7407
1
2
C7417
1
2
C7416
1
2
C7415
1
2
C7419
1 2
XW6800
1 2
R7427
1
2
R7426
1
2
R7425
1 2
C7418
1
2
R7423
1
2
R7424
1
2
C7421
1
2
Q7400
6
2
1
Q7400
3
5
4
R7429
1 2
R7407
1 2
Q7402
3
5
4
Q7402
6
2
1
R7431
1
2
R7430
1
2
R7441
1 2
R7440
1 2
U7400
C3
A2
B1
B3
A1
A3
C1
C2
C7424
1
2
R7442
1 2
R7443
1 2
R7437
1
2
C7435
1
2
R7435
1 2
C7405
1 2
C7406
1 2
74 73 72 68
73
74
74 73 72 68
74 73 72 68
74
74 68
74 68
74 73 72 68
68
74
74
74
74
74
74 73
74 73 72 68 72
74 73
72
6
74 73 72 68
6
74 73 72 68
6
74 73 72 68
6
74 68
74
74
68
68
74 68
74 73 72 68
6
74 73 72 68
73
74
74 73 72 68
68
74
68
74 68
73
68
68
74 73 72 68
74 73 72 68
74 68
73
74
74
73
73
74 73 72 68
68
74
74 73 72 68
68
74 73 72 68
73
73 68
74 68
68 73
73
Page 56
TPAD
VSS
BOOT2
BOOT1
PHASE1
UGATE1
LGATE1
PGND1
ISEN1
UGATE2
PHASE2
LGATE2
PVCC
VDDVIN
PGND2
VID6 VID5 VID4
VID2
VID3
VID1 VID0
ISEN2
VSUM
OCSET
VO
DROOP
DFB
VSEN
RTN
DPRSTP* DPRSLPVR PSI* PGD_IN
3V3 CLK_EN*
PGOOD
VR_ON
NTC
VR_TT*
SOFT
RBIAS
VDIFF
FB2 FB COMP VW
NC
IN
IN
IN IN
OUT
IN
OUT
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
ROUTE AS 18MIL WIDE, 7MIL SPACE
CPU_VCCSENSE_P & N ARE DIFF PAIRS
1-Phase DCM
1-Phase DCM
(IMVP6_PHASE2)
IMVP6 CPU VCORE REGULATOR
(IMVP6_ISEN1)
(GND)
CLOSE TO CPU
PLACE R7526
LAYOUT NOTE:
1
Operation Mode
1
0
Note 1: C7532,C7533 = 27.4 Ohm For Validating CPU Only.
(IMVP6_VO)
DPRSLPVR
NTC
*NEED TO CHANGE R7531 TO NTC ERT-J1VR103J PANASONIC
ERT-J1VR103J
FROM 1.5V AND 1.05V VREGS
(GND)
(IMVP6_VW)
(IMVP6_FB)
(IMVP6_COMP)
MIN_NECK_WIDTHMIN_LINE_WIDTHMIN_NECK_WIDTHMIN_LINE_WIDTH
(IMVP6_ISEN2) (IMVP6_VSUM) (IMVP6_VO)
MIN_LINE_WIDTH
MIN_NECK_WIDTH
PSI*
0
DPRSTP*
0
01
1 0
0
FROM SMC
2-Phase CCM
(IMVP6_PHASE1)
1 1
1-Phase CCM
NO STUFF THIS CAP IF USING
YONAH
44A MAX CURRENT
50V
10% CERM
0.0022UF
NO STUFF
402
1.0
MF-LF
5% 1/4W
1206
4700PF
10%
603
50V CERM
402
10% CERM
50V
0.0022UF
NO STUFF
MF-LF 402
10K
1% 1/16W
6.3V 402
CERM-X5R
10%
0.22uF
SM
SM
ISL6262
QFN
OMIT
603
X5R
25V
0.22UF
20%
SM
SM
MF-LF
1%
402
10K
1/16W
0.22uF
40210%
6.3V
CERM-X5R
CERM
10% 50V
4700PF
603
1/4W MF-LF 1206
1.0
5%
NO STUFF
10%
402
CERM
0.0022UF
50V 50V
NO STUFF
0.0022UF
CERM 402
10%
603
X5R
25V
20%
0.22UF
10
1% 1/16W
402
MF-LF
10
1% 1/16W
402
MF-LF
1uF
25V
10%
603
X5R
402
0.1uF
X5R
10% 16V
10
1%
MF-LF
1/16W
402
402
X5R
16V
10%
0.1uF
499
402
MF-LF
1/16W
1%
402
CERM
47PF
5% 50V
1/16W
1%
402
MF-LF
4.42K
603
20% CERM
4.7uF
6.3V
B340LBXF
SMB
B340LBXF
SMB
0
0
0
0
0
0
0
16V
1210
X7R
20%
22UF
499
402
1%
1/16W MF-LF
4.02K
1%
1/16W
MF-LF
402
CERM
0.01uF
10%16V
402
147K
402 1%
MF-LF 1/16W
402
1%
NO STUFF
2.0K
1/16W MF-LF
CERM
470pF
50V
10% 402
1/16W
1%
402
MF-LF
1.40K
1.82K
MF-LF 402
1% 1/16W
50V
10%
402
CERM
390pF
CERM
50V
470PF
10% 402
5%
180K
MF-LF
1/16W 402
1
402
5% MF-LF
1/16W
1
402
5%
1/16W
MF-LF
NO STUFF
402
CERM
50V
10%
0.001uF
MF-LF
1/16W
1%
402
9.31K
5.76K
1/16W
1% MF-LF
402
402
180pF
5% 50V CERM
402
1%
1K
MF-LF
1/16W
2.61K
1% 1/16W
402
MF-LF
11K
MF-LF
1/16W
1%
402
CERM-X5R
6.3V 402
10%
0.33uF
X5R
16V
10%
402
0.033UF
0
5% 1/16W MF-LF 402
402
CERM
16V
10%
0.01uF
0.01uF
NO STUFF
16V 402
CERM
10%
402
0
5% MF-LF
1/16W
0.01uF
CERM
10%
402
16V
0.22UF
X5R
20%
6.3V 402
SM
3.65K
603
1/10W
1% MF-LF
MF-LF
3.65K
1% 1/10W
603
402
CERM
16V 10%
0.01uF
10KOHM-5%
0603-LF
CRITICAL
SM
0.36UH-30A-0.80MOHM
CRITICAL
CRITICAL
SM
0.36UH-30A-0.80MOHM
22UF
20% X7R
1210
16V
TH-KZJ-LF
16V ELEC
1000UF
20%
CRITICAL
20%
TH-KZJ-LF
16V ELEC
1000UF
CRITICAL
ELEC
16V
20%
TH-KZJ-LF
CRITICAL
1000UF
22UF
X7R
20% 16V
1210
680UF
2.5V POLY
20%
TH
CRITICAL
20%
680UF
2.5V POLY TH
CRITICAL
20%
2.5V POLY
680UF
CRITICAL
TH
IRLR7821PBF
TO-252AA
CRITICAL
IRLR7843PBF
CRITICAL
TO-252AA
IRLR7843PBF
TO-252AA
CRITICAL
CRITICAL
IRLR7821PBF
TO-252AA
IRLR7843PBF
TO-252AA
CRITICAL
IRLR7843PBF
TO-252AA
CRITICAL
22UF
16V
20% X7R
1210
22UF
16V
20% X7R
1210
22UF
1210
X7R
20% 16V
10K
1% 1/10W MF-LF
603
10K
1% 1/10W MF-LF 603
MEROM
CRITICAL
TH
20% POLY
2.5V
680UF
402
MF-LF
1/16W
1%
470K
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
IMVP6 CPU VCore Regulator
9775
??
051-7032
PPVCORE_CPU
IMVP6_NTC
IMVP6_NTC_R
R7504_1
R7507_1
IMVP6_VO
IMVP6_PHASE2
IMVP6_VSUM
IMVP6_VSUM_R1
MIN_NECK_WIDTH=0.2 MM
PP3V3_S0_IMVP6_3V3
MIN_LINE_WIDTH=0.25 MM
PP12V_S5_CPU_REG
IMVP6_BOOT2
IMVP6_FET_RC1
IMVP6_COMP_RC
IMVP6_VR_TT
IMVP_VID<1>
IMVP6_RTN
0.25 MM0.25 MM
IMVP6_VDIFF
0.25 MM 0.20 MM
IMVP6_RBIAS
0.25 MM 0.20 MM
IMVP6_SOFT
0.25 MM 0.20 MM
IMVP6_DROOP
0.25 MM 0.20 MM
IMVP6_VO
0.25 MM 0.20 MM
IMVP6_VSUM
0.25 MM 0.20 MM
IMVP6_OCSET
0.25 MM 0.20 MM
IMVP6_DFB
IMVP6_FET_RC1
0.25 MM 0.25 MM
IMVP6_VSUM_R1
0.25 MM 0.25 MM
R7504_1
0.25 MM 0.25 MM
IMVP6_LGATE1
1.5 MM
0.25 MM
IMVP6_ISEN1
0.25 MM 0.25 MM
IMVP6_UGATE1
1.5 MM
0.25 MM
IMVP6_BOOT1
0.25 MM 0.25 MM
IMVP6_PHASE1
1.5 MM
0.25 MM
IMVP6_UGATE2
0.25 MM 0.25 MM
IMVP6_RBIAS
CPU_VID<1>
CPU_VID<3>
CPU_VID<5>
CPU_VID<0>
CPU_VID<2>
CPU_VID<4>
CPU_VID<6>
VR_PWRGOOD_DELAY
IMVP_VR_ON
VR_PWRGD_CK410_L
IMVP_PGD_IN
CPU_PSI_L
CPU_DPRSTP_L
PP12V_S5_CPU_REG
IMVP6_VSEN
0.25 MM 0.25 MM
IMVP6_VW
0.25 MM 0.25 MM
IMVP6_COMP
0.25 MM 0.20 MM
IMVP6_FB
0.25 MM 0.20 MM
PM_DPRSLPVR
IMVP6_BOOT1
IMVP6_FET_RC2
IMVP_DPRSLPVR
IMVP6_DROOP
GND_IMVP6_SGND
IMVP6_DFB
0.25 MM 0.20 MM
IMVP6_VO_R
IMVP_VID<0>
IMVP_VID<3>
IMVP_VID<4>
IMVP6_SOFT
IMVP6_COMP
IMVP6_FB2
0.25 MM 0.20 MM
GND_IMVP6_SGND
0.50 MM 0.20 MM
IMVP6_UGATE2
IMVP6_OCSET
IMVP6_LGATE2
IMVP_VID<5>
IMVP6_FB2
IMVP6_LGATE2
0.25 MM 0.25 MM
IMVP_VID<2>
GND_IMVP6_SGND
MIN_LINE_WIDTH=0.25 MM VOLTAGE=5V
MIN_NECK_WIDTH=0.2 MM
PP5V_S0_IMVP6_VDD
PPVIN_S5_IMVP6_VIN
MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.25 MM
IMVP_VID<6>
IMVP6_UGATE1
PP5V_S0
IMVP6_VSUM_R2
IMVP6_VDIFF_RC
IMVP6_VDIFF
=PP3V3_S0_IMVP
R7507_1
0.25 MM 0.25 MM
IMVP6_VSUM_R2
0.60 MM 0.25 MM
IMVP6_FET_RC2
0.25 MM 0.25 MM
IMVP6_ISEN2
0.25 MM 0.25 MM
IMVP6_BOOT2
0.25 MM 0.25 MM
IMVP6_PHASE2
0.25 MM 0.25 MM
PP12V_S5_CPU_REG
IMVP6_ISEN1
IMVP6_ISEN2
IMVP6_FB
IMVP6_VW
GND_IMVP6_SGND
IMVP6_PHASE1 IMVP6_LGATE1
CPU_VCCSENSE_N
CPU_VCCSENSE_P
IMVP6_VSEN
IMVP6_RTN
C7500
1
2
R7503
1
2
C7512
1
2
C7590
1
2
R7500
1 2
C7503
1 2
XW7503
1
2
XW7504
1
2
U7500
48
36 26
47
10
17
45
46
16
11
12
24
23
32
30
25
6
8
3
33
29
1
34
28
2
31
4
15
7
49
35
27
22
13
37
38
39
40
41
42
43
20
18
44
5
14
21
19
9
C7515
1
2
XW7501
1
2
XW7502
1
2
R7505
1 2
C7504
1 2
C7511
1
2
R7502
1
2
C7502
1
2
C7592
1
2
C7527
1
2
R7520
1 2
R7512
1 2
C7526
1
2
C7596
1
2
R7521
1 2
C7530
1
2
R7519
1 2
C7507
1
2
R7510
1
2
C7535
1
2
D7500
1
2
D7501
1
2
R7595
1 2
R7593
1 2
R7591
1 2
R7596
1 2
R7594
1 2
R7592
1 2
R7590
1 2
C7508
1
2
R75A0
1 2
R7527
1 2
C7510
1 2
R7508
1 2
R7513
1 2
C7506
1
2
R7511
1
2
R7509
1
2
C7513
1
2
C7514
1
2
R7514
1
2
R7504
1
2
R7507
1
2
C7516
1
2
R7516
1
2
R7517
1 2
C7529
1
2
R7518
1
2
R7530
1
2
R7515
1
2
C7528
1
2
C7534
1
2
R7522
1
2
C7531
1 2
C7532
1 2
R7523
1
2
C7533
1 2
C7521
1 2
XW7500
1
2
R7501
1
2
R7506
1
2
C7505
1 2
R7531
1 2
L7500
1 2
L7501
1 2
C7501
1
2
C7517
1
2
C7509
1
2
C7550
1
2
C7551
1
2
C7579
1
2
C7578
1
2
C7577
1
2
Q7500
4
1
3
Q7501
4
1
3
Q7504
4
1
3
Q7502
4
1
3
Q7503
4
1
3
Q7505
4
1
3
C7552
1
2
C7554
1
2
C7553
1
2
R7540
1 2
R7541
1
2
C7580
1
2
R7526
1 2
76
6 5
75
75
76 75
75
75
75
76 75
75
75
75
75
75
75
76 75
76 75
75
75
75
75
75
75
75
75
75
75
75
75
75
8
8
8
8
8
8
8
26 14
5
58
26
77
7
21
7
76 75
75
75
75
75
23 14
75
75
76 75
75
75
75
75
75
75
75
75
75
75
75
75
75
83
6
75
75
6
75
75
75
75
75
75
76 75
75
75
75
75
75
75
75
8
8
75 75
Page 57
IN
G
D
S
D
G
S
VIN
IOUT
LOADNC
GND
VIN
IOUT
LOADNC
GND
D
S
G
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PROCESSOR DCIN VOLTAGE SENSE
(SCALING 12V INPUT VOLTAGE TO SMC)
2.73224 A/V
Current Sense Calibration Circuit
Switches in fixed load on power supplies to calibrate current sense circuits
ADC IS 10BIT 0 TO 1023
PROCESSOR VCORE CURRENT SENSE
(USING 12V INPUT CURRENT TO DERIVE CPU CURRENT)
WORKS WELL.
SO SMC ADC SAMPLING
1 MS TIME CONSTANT
PCB:PLACE D7699,R7697,C7699 BY SMC
0.0129 A/COUNT
PCB: PLACE D7599, C7599, R7597 WITHIN 1" OF SMC (U5800)
SYSTEM CURRENT SENSE
TO SMC
(MEASURING DC/DC INDUCTOR DCR TO DERIVE CPU CURRENT)
SYSTEM VOLTAGE SENSE
1 MS TIME CONSTANT SO SMC ADC SAMPLING
PCB: PLACE R7602, C7602 WITHIN 1" OF SMC (U5800)
SMC PWRGD PULLUP
PCB: PLACE R7612, C7612 WITHIN 1" OF SMC (U5800)
PROCESSOR VCORE SENSE
4 V/V
SCALE COUNT
.0129 V/COUNT
0 TO 3.3V
ADC IS 10BIT 0 TO 1023
SCALE COUNT
PROCESSOR VCORE CURRENT SENSE
TO SMC
WORKS WELL.
PCB: PLACE R7632, C7633 WITHIN 1" OF SMC (U5800)
COUNT
.0129 V/COUNT
COUNT
0 TO 3.3V
ADC IS 10BIT 0 TO 1023
SCALE
4 V/V
SCALE
0 TO 3.3V
PCB:PLACE D7650,R7652,C7650 BY SMC
PCB:KEEP SHORTS NEXT TO U7601
(SCALING 12V INPUT VOLTAGE TO SMC)
PCB: PLACE R7632, C7633 WITHIN 1" OF SMC (U5800)
PCB: PLACE D7599, C7599, R7597 WITHIN 1" OF SMC (U5800)
PCB:KEEP SHORTS NEXT TO U7602
3.33333 A/V
.010753 A/COUNT
ADC IS 10BIT 0 TO 1023
0 TO 3.3V
SYSTEM_DCIN_SENSE_R
GND_CPU_ISENSE_OPAMP
MIN_LINE_WIDTH=0.20 MM
PP12V_S0
IMVP6_VO
PP12V_S5_AC_DC
MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM VOLTAGE=12V
CPU_ISENSE_R_NEG
CPU_ISENSE_OUT_R
SMC_CPU_ISENSE
CPU_DCIN_SENSE
PP12V_S5
SMC_PBUS_VSENSE
SMC_SYSTEM_VSENSE_R
GND_SMC_AVSS
GND_SMC_AVSS
GND_SMC_AVSS
SMC_PBUS_VSENSE_R
PP12V_S5_CPU_REG
PPVCORE_CPU
SMC_CPU_VSENSE
GND_SMC_AVSS
ISENSE_CAL_EN
ISENSE_CAL_EN_L
MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.20 MM
ISENSE_CAL_EN_L_R
PP3V3_S0
GND_NEXT_TO_SMC
GND_SMC_AVSS
PP3V3_S5
RSMRST_PWRGD
SYS_POWERFAIL_L
=PP12V_S5_CPU
CPU_ISENSE_R_POS
IMVP6_VO_R_OA
IMVP6_DROOP_R
SYSTEM_SENSE_I_R
IMVP6_DROOP
PP3V3_S0
SMC_DCIN_ISENSE
PP3V3_S0
SYSTEM_DCIN_SENSE
PP12V_S5
PP12V_S5_CPU_REG
VOLTAGE=12V MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM
CPU_SENSE_I_R
CPU_HISIDE_ISENSE
CPU_HISIDE_VSENSE
GND_SMC_AVSS
VOLTAGE=12V
PP12V_L7502
MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.50 mm
CPUVCORE_ISENSE_CAL
ISENSE_CAL_EN_LS12V
=PPVCORE_S0_CPU
SYNC_DATE=(MASTER)
SYNC_MASTER=(MASTER)
9776
??
051-7032
CPU & SYSTEM SENSE CIRCUITRIES
DEVELOPMENT_ISENSE_CALIB
402
MF-LF
1/16W
5%
470K
DEVELOPMENT_ISENSE_CALIB
1.00
1%
1/4W
MF-LF
1206
402
MF-LF
5%
0
1/16W
NOSTUFF
1%
2512-1
MF
0.025
CRITICAL
1W
1/16W
10K
402
MF-LF
1%
2.0K
1/16W MF-LF 402
1%
402
MF-LF
6.04K
1/16W
1%
1K
1% 1/16W MF-LF 402
402
1/16W
1%
MF-LF
4.53K
X5R 402
6.3V
20%
0.22UF
0.22UF
X5R 402
6.3V
20%
1%
4.53K
1/16W MF-LF
402
6.3V X5R
0.22UF
402
20%
DEVELOPMENT
4.53K
402
1%
MF-LF
1/16W
DEVELOPMENT
SM
OMIT
0.22UF
6.3V X5R 402
20%
1%
402
MF-LF
1/16W
4.53K
20%
402 10V
0.1UF
CERM
DEVELOPMENT
1M
1% MF-LF
1/16W
DEVELOPMENT
402
10% 50V CERM 402
470PF
DEVELOPMENT
10%
470PF
402
CERM
50V
DEVELOPMENT
DEVELOPMENT_ISENSE_CALIB
CRITICAL
MICROFET3X3
FDM6296
NOSTUFF
SOT23-LF
BAS16-75V-0.25A
BAS16-75V-0.25A
SOT23-LF
NOSTUFF
1% 1/16W MF-LF
402
100
CRITICAL
ZXCT1010
SOT23-5
402
MF-LF
1/16W
1M
1%
DEVELOPMENT
MF-LF
1/16W
1%
464
402
CPU_DCIN_SENSE_R
CRITICAL
ZXCT1010
SOT23-5
1/16W MF-LF 402
2.0K
1%
6.04K
402
MF-LF
1/16W
1%
X5R
0.22UF
402
6.3V
20%
MF-LF
1%
4.53K
1/16W
402
1/16W
1% MF-LF
5.90K
402
402
20% X5R
6.3V
0.22UF
CRITICAL
1% MF
1W
2010
0.005
OMIT
SM
1/16W MF-LF
402
1%
4.53K
5%
0
402
1/16W MF-LF
DEVELOPMENT
CRITICAL
LMV2011MF
SOT23-5
DEVELOPMENT
1/16W
402
DEVELOPMENT
MF-LF
1%
40.2K
402
MF-LF
1/16W
1%
40.2K
DEVELOPMENT
402
1/16W
DEVELOPMENT
0
5%
MF-LF
1/16W
5%
10K
MF-LF 402
DEVELOPMENT_ISENSE_CALIB
402
MF-LF
1/16W
5%
10K
DEVELOPMENT_ISENSE_CALIB
SOT-23
NTR4101P
DEVELOPMENT_ISENSE_CALIB
2N7002
SOT23-LF
DEVELOPMENT_ISENSE_CALIB
NOSTUFF
1/16W
402
MF-LF
5%
0
402
MF-LF
1/16W
0
5%
DEVELOPMENT
5% 1/16W MF-LF
100K
402
DEVELOPMENT_ISENSE_CALIB
CRITICAL
1UH-20A-4.5MOHM
TH-VERT-LF
XW7698
1 2
R7698
1
2
R7699
1 2
L7602
1 2
U7600
3
4
1
5
2
R7600
1 2
C7600
1 2
C7603
1
2
R7603
1
2
C7601
1 2
R7697
1 2
C7699
1
2
R7602
1 2
C7602
1
2
R7612
1 2
C7612
1
2
C7633
1
2
R7632
1 2
R7630
1
2
R7631
1
2
R7623
1
2
R7620
1 2
R7643
1
2
R7642
1
2
R7640
1
2
R7607
1 2
R7604
1 2
Q7639
3
1
2
Q7640
3
1
2
R7639
1
2
R7641
1
2
R7659
1 2
R7605
1 2
R7606
1 2
R7669
1 2
R7652
1 2
XW7650
1 2
R7650
1 2
C7650
1
2
R7651
1
2
R7655
1 2
C7651
1
2
R7653
1
2
R7654
1
2
U7601
2
3
51
4
R7691
1 2
U7602
2
3
51
4
R7656
1 2
D7650
1
3
D7699
1
3
Q7641
5
4
1 2 3
83
6
75
6
58
83 82 80 79 78 77 76
6 5
58
80 76 59 58
80 76 59 58
80 76 59 58
76 75
75
6 5
58
80 76 59 58
58
94 83 76
61 59 41 26 10
6
59
80 76 59 58
83
80 79 78 77 66 65 59 26
6 5
58 82 78
6
6
75
94 83 76 61 59 41 26 10
6
58
94 83 76 61 59 41 26 10
6
83 82 80 79 78 77 76
6 5
76 75
59
59
80 76 59 58
9 8 6
Page 58
IN
G
D
S
G
D
S
IN
OUT
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
SILKSCREEN:SYS_PWRGD
TIMING OF VARIOUS RAILS COMING UP
PWGOOD SIMPLIFIED BASED ON AS MEASURED ON PROTO2 BOARDS
ALL AND GATE INPUTS ARE 7V TOLERANT REGARDLESS OF INPUT POWER
2N7002DW-X-F
SOT-363
10K
5% 1/16W MF-LF 402
10K
402
5%
NOSTUFF
10V
330
603
MF-LF
1/10W
5%
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
SYS_PWRGD_LED_R
DEVELOPMENT
5% 1/16W MF-LF 402
10K
DEVELOPMENT
2N7002
SOT23-LF
DEVELOPMENT
10K
402
MF-LF
1/16W
5%
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
??
051-7032
77 97
PWR GOOD
PP3V3_S5
SYS_PWRUP_L
MAKE_BASE=TRUE
PP12V_S5
PM_SLP_S4
SYS_PWRGD_LED
ALL_SYS_PWRGD
PP3V3_S5
PP12V_S5
PM_SLP_S4_L
1/16W MF-LF
SOT-363
0.1UF
10V
0.1UF
SOT23-5-LF
MC74VHC1G08
PP3V3_S5
PGOOD_PP1V8_S3
ALL_SYS_PWRGD
PGOOD_PP1V05_S0
PGOOD_PP1V5_S0
MF-LF
1/16W
5%
33
IMVP_PGD_IN
IMVP_PGD_IN_R
PP3V3_S5
PM_SLP_S3_L
2N7002DW-X-F
SOT23-5-LF
MC74VHC1G08
402
Q7703
6
2
1
R7793
1
2
R7794
1
2
Q7703
3
5
4
C7710
1 2
C7712
1 2
U7710
3
2
1
4
5
U7712
3
2
1
4
5
R7700
1
2
LED7700
1
2
R7701
1
2
Q7700
3
1
2
R7795
1
2
R7710
1 2
83 80
79 78 77 76 66 65 59 26
6 5
83
83 82 80 79 78 77 76
6 5
83 79
77 58 26
83 80
79 78 77 76 66 65 59 26
6 5
83 82 80 79 78 77 76
6 5
58
23
83 80
79 78 77 76 66 65 59 26
6 5
79
77 58 26
80
80
75
83 80
79 78 77 76 66 65 59 26
6 5
80 79
58 23
Page 59
FS_DIS
LDO_DR
LDO_FB
PVCC5
VCC5
DGND
THRML_PAD
AGND PGND
FB
COMP
PHASE
LGATE
BOOT
UGATE
VCC12
G
D
S
D
G
S
D
G
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
M50 POWER BUDGET
MISC=1.500A
M50 POWER BUDGET
3.3V AND 2.5V S5 REGULATOR
TOTAL=0.426A
3.3V S5
TOTAL=4.000A
PANEL=1.000A
AIRPORT=1.000A
VOUT=VREF*(1+R2/R1)
(R2)
(R1)
0.816V MAX
0.784V MIN
VREF = 0.800V TYP
2.5V S5
SB=0.500A
3.35V NOMINAL
2.50V NOMINAL
YUKON=0.426A
TH1
CRITICAL
3.0UH
TH-KZJ-LF
ELEC
20%
1000UF
16V
CRITICAL
0.1UF
25V
20%
603
CERM
805-1
10UF
6.3V
20% CERM
805-1
10UF
6.3V
20% CERM
6.3V
CRITICAL
TH-KZJ-LF
ELEC
20%
1800UF
402
1/16W
5% MF-LF
22
402
10% CERM
16V
0.01UF
MF-LF
1/16W
1%
402
1.24K
402
1/16W MF-LF
392
1%
5.11
1/4W
1% MF-LF
1206
CERM 1206
50V
5%
1000PF
10% 25V X7R 402
1000PF
CERM
16V 402
10%
0.047UF
1/16W
5%
MF-LF
402
2.2
603
X5R
25V
10%
1UF
10%
1UF
CERM 402
6.3V
1%
10
MF-LF 402
1/16W
10%
402
X7R
25V
1000PF
X5R
6.3V
20%
22UF
805
402
CERM
50V
560PF
10%
402
8.06K
1% 1/16W MF-LF
ISL6549
CRITICAL
QFN
SM
4.7UF
20%
6.3V CERM
603
1000PF
10% 25V X7R 402
NOSTUFF
402
1/16W MF-LF
5%
2.7K
1K
402
MF-LF
1/16W
1%
470
402
1/16W
1% MF-LF
805-1
10UF
20%
6.3V CERM
402
MF-LF
1/16W
5%
100K
2N7002
SOT23-LF
NOSTUFF
805-1
20%
10UF
CERM
6.3V
805-1
10UF
20%
6.3V CERM
805-1
10UF
20%
6.3V CERM
CTLSH3-30M833
TLM833
CRITICAL
SO-8
IRF1902PBF
TO-252AA
CRITICAL
IRLR7807Z
TO-252AA
IRLR7807Z
CRITICAL
1210
CERM
16V
10UF
10%
3V DC/DC 2.5V
9778
??
051-7032
TRUE
SYNC_MASTER=(MASTER)
SYNC_DATE=(MASTER)
PAGE_BORDER=TRUE
3V3REG_VCC5
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
=PP3V3_S5_2V5_LDO
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
3V3REG_UGATE
MIN_NECK_WIDTH=0.25MM
3V3REG_LDO_DR
MIN_LINE_WIDTH=0.6MM
3V3REG_FS_DIS
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
3V3REG_SNUB
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
3V3REG_PVCC5
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
SYS_POWERFAIL_L
MIN_NECK_WIDTH=0.25MM
3V3REG_COMP_R
MIN_LINE_WIDTH=0.6MM
3V3REG_BOOT
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
3V3REG_BOOT_R
MIN_NECK_WIDTH=0.25MM
PP2V5_S5
MIN_NECK_WIDTH=0.25MM
3V3REG_SWITCHNODE
MIN_LINE_WIDTH=0.6MM
PP12V_S5
PP3V3_S5
3V3REG_FB_R
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
3V3REG_COMP
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
3V3REG_LGATE
MIN_NECK_WIDTH=0.25MM
3V3REG_FB
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
3V3REG_GND
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0 V
2V5_LDODR_C
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
3V3REG_LDO_FB
C7811
1
2
L7803
1 2
C7853
1
2
C7801
1 2
C7813
1
2
C7814
1
2
C7815
1
2
R7899
1
2
C7807
1
2
R7803
1
2
R7801
1
2
R7802
1
2
C7809
1
2
C7802
1
2
C7808
1 2
R7840
1 2
C7892
1 2
C7800
1
2
R7805
1
2
C7823
1
2
C7820
1
2
C7806
1 2
R7804
1 2
U7800
5
15
1
6
2
16
3
4
11
12
13
10
17
14
7 8
9
XW7800
1
2
C7803
1
2
C7824
1
2
R7821
1
2
R7820
1
2
R7822
1
2
C7826
1
2
R7892
1
2
Q7802
3
1
2
C7821
1
2
C7825
1
2
C7822
1
2
D7800
1
2
3
4
5
Q7803
5678
4
123
Q7800
4
1
3
Q7801
4
1
3
6
82 76
6
83
83 82 80 79 77 76
6 5
83 80
79 77 76 66 65 59 26
6 5
Page 60
FS_DIS
LDO_DR
LDO_FB
PVCC5
VCC5
DGND
THRML_PAD
AGND PGND
FB
COMP
PHASE
LGATE
BOOT
UGATE
VCC12
G
D
S
D
G
S
D
G
S
LM393A
V+
GND
LM393A
V+
GND
GND
V+
LM339A
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
1.8V AND 1.2V S3 REGULATOR
SPARE COMPARATOR
PP1V8_S3
1.591V
TOTAL=0.426A
1.2V S3
YUKON=0.426A
NEAR VREG
PLACE LED
PP1V8_S3
VREF = 0.800V TYP
(R2)
(R1)
1.8V S3
DRAM=6.000A
NB=4.000A
0.816V MAX
0.784V MIN
1.21V NOMINAL
1.81V NOMINAL
TOTAL=10.000A
VOUT=VREF*(1+R2/R1)
M50 POWER BUDGET
M50 POWER BUDGET
1% 1/16W MF-LF 402
5.11K
5.49K
402
MF-LF
1/16W
1%
10K
1% 1/16W MF-LF 402
1/16W
22
MF-LF
5%
402
1.24K
MF-LF
1/16W
1%
402
CERM
0.01UF
10%
402
16V
976
MF-LF
1/16W
1%
402
1206
MF-LF
1% 1/4W
5.11
1206
CERM
50V
1000PF
5%
CERM
0.047UF
10% 16V
402
MF-LF
2.2
1/16W
5%
402
402
CERM
50V
560PF
10%
6.3V
10%
1UF
CERM 402
10
1/16W MF-LF 402
1%
402
8.06K
1% 1/16W MF-LF
CRITICAL
ISL6549
QFN
4.7UF
20%
6.3V CERM
603
402
MF-LF
1/16W
5%
100K
SOT23-LF
2N7002
603
X5R
25V
10%
1UF
402
X7R
25V
10%
1000PF
TH
POLY
680UF
20%
2.5V
CRITICAL
680UF
CRITICAL
2.5V POLY TH
20%
CRITICAL
20% 16V ELEC TH-MCZ
680UF
TH-MCZ
ELEC
16V
20%
680UF
CRITICAL
1000PF
402
X7R
10% 25V
NOSTUFF
1000PF
10% 25V X7R 402
2.7K
5% 1/16W
402
MF-LF
6.3V CERM
10UF
20%
805-1
MF-LF
1% 1/16W
1K
402
1.96K
MF-LF 402
1/16W
1%
22UF
20%
6.3V X5R 805
603
X5R
10% 16V
2.2UF
CRITICAL
1.5UH-19A
IHLP-LF
402
CERM
6.3V
10%
1UF
6.3V
1UF
10% CERM
402
1UF
10%
6.3V CERM 402
6.3V CERM
10UF
20%
805-1
CERM
6.3V
20%
10UF
805-1
CERM
6.3V
20%
10UF
805-1
TLM833
CTLSH3-30M833
TO-252AA
CRITICAL
IRLR7807Z
SO-8
IRF1902PBF
CRITICAL
TO-252AA
CRITICAL
IRLR7807Z
20% 10V
CERM
402
0.1UF
SOI-1-LF
SOI-1-LF
0.1UF
603
CERM
25V
20%
10UF
16V 1210
10% CERM
LED_PP1V8_S3_P
330
5% 1/16W MF-LF 402
DEVELOPMENT
2.0X1.25MM-SM
GREEN-3.6MCD
DEVELOPMENT
LED_PP1V8_S3_N
SOI-LF
DEVELOPMENT
CERM
10UF
6.3V
20%
805-1
SM
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
1.8V & 1.2V VREG
97
??
051-7032
79
PP1V8_S3
PP3V3_S5
MIN_LINE_WIDTH=0.6MM
1V8REG_DDR_COMP
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1V8REG_DDR_LGATE
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1V8REG_DDR_FB
MIN_NECK_WIDTH=0.25MM
1V8REG_DDR_COMP_R
MIN_LINE_WIDTH=0.6MM
1V8REG_DDR_GND
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
VOLTAGE=0 V
1V8REG_DDR_FS_DIS
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
1V8REG_DDR_BOOT
1V8REG_DDR_PVCC5
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
1V8REG_DDR_UGATE
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
1V8REG_DDR_BOOT_R
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1V8REG_DDR_SWITCHNODE
MIN_LINE_WIDTH=0.6MM
1V8REG_DDR_SNUB
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1V8REG_DDR_FB_R
MIN_NECK_WIDTH=0.25MM
PM_SLP_S4
PM_SLP_S3_L
MEMVTT_EN
1V0_REF
1V8REG_DDR_VCC5
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
=PP1V8_S3_1V2_LDO
PP1V2_S3
PP3V3_S5
PGOOD_PP1V8_S3
1V6_REF
PP5V_S5
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
1V8REG_DDR_LDO_DR
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1V2_LDODR_C
1V8REG_DDR_LDO_FB
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
PP12V_S5
C7901
1 2
C7911
1
2
R7906
1
2
LED7900
1
2
U7901
12
8
9
14
3
C7913
1
2
XW7900
1
2
R7912
1
2
R7911
1
2
R7910
1
2
R7999
1
2
R7903
1
2
C7907
1
2
R7901
1
2
R7902
1
2
C7909
1
2
C7908
1 2
R7940
1 2
C7906
1 2
C7900
1
2
R7905
1
2
R7904
1 2
U7900
5
15
1
6
2
16
3
4
11
12
13
10
17
14
7 8
9
C7903
1
2
R7992
1
2
Q7902
3
1
2
C7992
1 2
C7902
1
2
C7956
1
2
C7957
1
2
C7954
1
2
C7953
1
2
C7923
1
2
C7924
1
2
R7921
1
2
C7921
1
2
R7920
1
2
R7922
1
2
C7920
1
2
C7912
1
2
L7903
1 2
C7960
1
2
C7958
1
2
C7959
1
2
C7926
1
2
C7922
1
2
C7925
1
2
D7900
1
2
3
4
5
Q7900
4
1
3
Q7903
5678
4
123
Q7901
4
1
3
C7980
1 2
U7910
4
2
3
1
8
U7910
4
6
5
7
8
83
6 5
83 80 79 78 77
76 66 65 59 26
6 5
83 77
80 77 58 23
31
80
6
6
83 80
79 78 77 76 66 65 59 26
6 5
77
83 82 80 59
6 5
83 82 80 78 77 76
6 5
Page 61
D
G
S
D
G
S
D
G
S
D
G
S
GND
V+
LM339A
VIN
PHASE2
SOFT2
DDR
OCSET2
PG2/REF
EN2
VSEN2
PGND2
LGATE2
ISEN2
UGATE2
BOOT2
EN1 PG1
OCSET1
PGND1 VSEN1
PHASE1 ISEN1
UGATE1
BOOT1
SOFT1
LGATE1
GND
VCC
GND
V+
LM339A
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
M50 POWER BUDGET
M50 POWER BUDGET
KEEP C8080, R8080,
1.05V NOMINAL1.50V NOMINAL
TOTAL=10.120A
NB=8.000A SB=2.000A
CPU=0.120A
1.5V S0
1.5V S0 AND 1.05V S0 RAILS
TOTAL=5.374A
NB=2.000A SB=0.874A
1.05V S0
CPU=2.500A
PP1V5_S0
PLACE LED NEAR VREG
0.867V
PLACE LED NEAR VREG
Placement Note:
close to inductor
R8084 AND R8087
DEVELOPMENT
1%
1M
MF-LF
402
1/16W
CRITICAL
TO-252AA
IRLR7807Z
IRLR7807Z
CRITICAL
TO-252AA
IRLR7807Z
CRITICAL
TO-252AA
IRLR7807Z
CRITICAL
TO-252AA
CERM
10UF
6.3V
20%
805-1
20%
6.3V
10UF
CERM 805-1
CRITICAL
ELEC
6.3V
20%
1500UF
TH-MCZ
MF-LF
0
5% 1/16W
402
CRITICAL
ELEC
6.3V
20%
1500UF
TH-MCZ
MF-LF
1/10W
3.32K
1%
603
MF-LF
1/10W
20.0K
1%
603
X7R
50V
0.018UF
5%
603
SOT23
BAT54E3
10K
1% 1/16W MF-LF 402
402
MF-LF
1/16W
1%
2.43K
50V X7R
10%
603-1
0.01UF
1/10W
1% MF-LF
603
110K
DEVELOPMENT
330
5% 1/16W MF-LF 402
GREEN-3.6MCD
DEVELOPMENT
2.0X1.25MM-SM
LED_PP1V05_S0_P
DEVELOPMENT
0.1UF
402
CERM
10V
20%
SOI-LF
DEVELOPMENT
8.45K
1% 1/16W MF-LF 402
402
MF-LF
1/16W
1%
3.01K
SOT23
BAT54E3
CRITICAL
1000UF
20% 16V ELEC TH-KZJ-LF
CRITICAL
1000UF
20% 16V ELEC TH-KZJ-LF
402
0
1/16W
5% MF-LF
10UF
10% 16V CERM 1210
10UF
10% 16V CERM 1210
CERM
6.3V
20%
4.7UF
603
10UF
10% 16V CERM 1210
1.53UH
CRITICAL
TH-LF
10UF
CERM
16V
10%
1210
SSOP
1V05REG_SOFT
CRITICAL
ISL6539
1V05REG_ISEN
MF-LF
1/10W
1%
110K
603
603-1
10% X7R
50V
0.01UF
402
1%
MF-LF
1/16W
2.43K
603
20% CERM
25V
0.1UF
603
20% CERM
25V
0.1UF
TH-LF
CRITICAL
1.53UH
X7R
50V
0.018UF
5%
603
1%
3.32K
MF-LF
1/10W 603
CRITICAL
TH-MCZ
1500UF
20% ELEC
6.3V
MF-LF
1/10W
4.99K
1%
603
402
MF-LF
1/16W
1%
10K
CRITICAL
TH-MCZ
1500UF
20% ELEC
6.3V
805-1
20%
6.3V CERM
10UF
805-1
CERM
10UF
20%
6.3V
402
MF-LF
1/16W
5%
330
DEVELOPMENT
GREEN-3.6MCD
2.0X1.25MM-SM
DEVELOPMENT
LED_PP1V5_S0_P
SOI-LF
DEVELOPMENT
CTLSH3-30M833
TLM833
1206
MF-LF
1/4W
5.11
1%
402
1000PF
25V
10% X7R
CTLSH3-30M833
TLM833
1206
MF-LF
1/4W
5.11
1%
402
1000PF
25V
10% X7R
DEVELOPMENT
CRITICAL
0603-LF
10KOHM-5%
NO STUFF
MF-LF
402
1K
1%
1/16W
DEVELOPMENT
1K
MF-LF
402
1%
1/16W
DEVELOPMENT
10%
CERM
402
1uF
6.3V
DEVELOPMENT
1%
1/16W
402
MF-LF
649
DEVELOPMENT
15.0K
1%
MF-LF
402
1/16W
MF-LF
1/16W
402
1%
15.0K
DEVELOPMENT
DEVELOPMENT
X5R 402
0.22UF
6.3V
20%
DEVELOPMENT
402
1/16W
1%
MF-LF
4.53K
DEVELOPMENT
402
1uF
6.3V
10%
CERM
DEVELOPMENT
50V
470pF
402
CERM
10%
DEVELOPMENT
50V
470pF
402
CERM
10%
402
MF-LF
1/16W
1M
1%
DEVELOPMENT
DEVELOPMENT
LMV2011MF
CRITICAL
SOT23-5
1.5V_S0 & 1.05V_S0 VREG
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
80
051-7032
??
97
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
1V05_LGATE
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1V05_SWITCHNODE
PM_SLP_S3_L
PGOOD_PP1V05_S0
1V05REG_UGATE
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
PP12V_S5
MIN_LINE_WIDTH=0.6MM
1V5REG_SWITCHNODE
MIN_NECK_WIDTH=0.25MM
PGOOD_PP1V5_S0
PP1V5_S0
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
1V5REG_UGATE
NBISENS_POS
MIN_NECK_WIDTH=0.25MM
1V5REG_BOOT
MIN_LINE_WIDTH=0.6MM
1V05REG_BOOT
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
U8595_1
SMC_NB_ISENSE
PP3V3_S5
PP3V3_S5
1V0_REF
LED_PP1V05_S0_N
PP3V3_S5
LED_PP1V5_S0_N
PP1V5_S0
1V0_REF
PP5V_S5
PGOOD_PP1V5_S0
PP5V_S5
PGOOD_PP1V05_S0
PP1V05_S0
MIN_NECK_WIDTH=0.25MM
1V05_VSEN
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1V05REG_BOOT_R
1V05REG_SNUBBER_R
1V05_OCSET
1V5REG_ISEN
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
1V5REG_SNUBBER_R
1V5REG_BOOT_R
GND_SMC_AVSS
NBISENS_NTC
PP1V05_S0
=PP5V_S0_NBISENSE
NBISENS_RC
PP5V_S5
1V5REG_LGATE
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
NBISENS_NEG
PM_SLP_S3_L
1V5REG_SOFT
1V5REG_OCSET
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
1V5REG_VSEN
R8050
1
2
L8050
1 2
C8061
1
2
C8073
1
2
C8072
1
2
C8071
1
2
C8070
1
2
R8051
1
2
R8052
1
2
C8062
1
2
D8050
1
3
R8055
1
2
R8053
1 2
C8063
1
2
R8054
1
2
R8091
1
2
LED8091
1
2
C8090
1 2
U7901
12
4
5
2
3
R8092
1
2
R8093
1
2
D8000
1
3
C8005
1
2
C8004
1
2
R8000
1
2
C8003
1
2
C8002
1
2
C8010
1
2
C8001
1
2
C8000
1
2
U8000
6
23
13
8
21
1209
7
22
2
27
11 18
15 16
3
26
4
25
12 17
5
24
28
14
10 19
R8004
1
2
C8013
1
2
R8003
1 2
C8011
1
2
L8000
1 2
C8012
1
2
R8001
1
2
C8023
1
2
R8002
1
2
R8005
1
2
C8022
1
2
C8021
1
2
C8020
1
2
R8090
1
2
LED8090
1
2
U7901
12
6
7
1
3
D8001
1
2
3
4
5
R8006
1
2
C8024
1
2
D8051
1
2
3
4
5
R8056
1
2
C8064
1
2
R8087
1
2
R8084
1 2
R8086
1
2
C8080
12
R8080
1
2
R8083
1 2
R8081
1 2
C8086
1
2
R8089
12
C8085
1
2
C8088
1 2
C8082
1 2
R8088
12
U8085
3
4
1
5
2
R8082
12
Q8000
4
1
3
Q8001
4
1
3
Q8050
4
1
3
Q8051
4
1
3
80 79
77 58 23
80 77
83 82 79 78 77 76
6 5
80 77
80
6
58
83 80
79 78 77 76 66 65 59 26
6 5
83 80
79 78 77 76 66 65 59 26
6 5
80 79
83 80
79 78 77 76 66 65 59 26
6 5
80
6
80 79
83 82 80 79 59
6 5
80 77
83 82 80 79 59
6 5
80 77
80
34
6
76
59 58
80 34
6
6
83 82 80 79 59
6 5
80
79 77 58 23
Page 62
FS_DIS
LDO_DR
LDO_FB
PVCC5
VCC5
DGND
THRML_PAD
AGND PGND
FB
COMP
PHASE
LGATE
BOOT
UGATE
VCC12
G
D
S
D
G
S
D
G
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
4.50V NOMINAL
5V AUDIO S5
TOTAL=?A
AUDIO=?A
5.10V NOMINAL
TOTAL=5.000A
AUDIO O=1.000A
5V S5
ODD=1.000A
USB=1.500A
MISC=1.500A
(R1)
(R2)
VOUT=VREF*(1+R2/R1)
VREF = 0.800V TYP
0.816V MAX
0.784V MIN
POWER SUPPLY 3.3V/5V MAIN SWITCH
5V S5 AND 5V AUDIO S5 REGULATOR
M50 POWER BUDGET
M50 POWER BUDGET
PP4V5_S5_AUDIO_ANALOG
5V_AUDIO_LDODR_C
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_LDO_DR
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
5VREG_COMP_R
PP5V_S5
MIN_NECK_WIDTH=0.25MM
5VREG_PVCC5
MIN_LINE_WIDTH=0.6MM
SYS_POWERFAIL_L
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_COMP
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_BOOT
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_BOOT_R
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_VCC5
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_FB
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_FB_R
VOLTAGE=0 V MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
5VREG_GND
5VREG_SNUB
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
=PP5V_S5_AUDIO_LDO
PP12V_S5
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
5VREG_LGATE
5VREG_UGATE
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_SWITCHNODE
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
MIN_NECK_WIDTH=0.25MM
MIN_LINE_WIDTH=0.6MM
5VREG_FS_DIS
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.25MM
5VREG_LDO_FB
051-7032
??
82 97
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
5V DC/DC
805-1
10UF
20%
6.3V CERM
805-1
10UF
20%
6.3V CERM
20% 25V
CERM
0.1UF
603
TO-252AA
IRLR7807Z
CRITICAL
TO-252AA
CRITICAL
IRLR7807Z
SO-8
IRF1902PBF
CRITICAL
CTLSH3-30M833
TLM833
10UF
805-1
6.3V
20% CERM
20%
6.3V 805-1
10UF
CERM CERM
805-1
20%
6.3V
10UF
NOSTUFF
2N7002
SOT23-LF
100K
5% 1/16W MF-LF 402
805-1
6.3V
20%
10UF
CERM
402
221
MF-LF
1% 1/16W
1% 1/16W MF-LF 402
1K
1/16W 402
2.7K
5% MF-LF
1000PF
X7R
25V
10%
402
16V
1000UF
20% ELEC
TH-KZJ-LF
CRITICAL
1000PF
NOSTUFF
402
X7R
25V
10%
603
CERM
6.3V
20%
4.7UF
SM
CRITICAL
QFN
ISL6549
MF-LF
1/16W
1%
402
8.06K
10%
402
CERM
50V
470PF
TH1
3.0UH
CRITICAL
X5R 805
6.3V
20%
22UF
1%
402
MF-LF
1/16W
10
402
CERM
1UF
10%
6.3V
1UF
10% 25V X5R 603
2.2
402
MF-LF
5%
1/16W
402
16V
10%
CERM
0.047UF
1000PF
10% 25V X7R 402
1206
CERM
50V
5%
1000PF
5.11
1/4W
1% MF-LF
1206
232
402
1% 1/16W MF-LF
1/16W
1.24K
402
1% MF-LF
16V
10%
0.01UF
CERM 402
22
5% 1/16W
402
MF-LF
CRITICAL
TH-KZJ-LF
ELEC
6.3V
20%
1800UF
10%
10UF
16V CERM 1210
C8211
1
2
L8203
1 2
C8253
1
2
C8201
1 2
C8213
1
2
C8214
1
2
C8215
1
2
R8299
1
2
C8207
1
2
R8203
1
2
R8201
1
2
R8202
1
2
C8209
1
2
C8202
1
2
C8208
1 2
R8240
1 2
C8292
1 2
C8200
1
2
R8205
1
2
C8220
1
2
C8206
1 2
R8204
1 2
U8200
5
15
1
6
2
16
3
4
11
12
13
10
17
14
7 8
9
XW8200
1
2
C8203
1
2
C8224
1
2
C8223
1
2
R8221
1
2
R8220
1
2
R8222
1
2
C8226
1
2
R8292
1
2
Q8202
3
1
2
C8221
1
2
C8222
1
2
C8225
1
2
D8200
1
2
3
4
5
Q8203
5678
4
123
Q8200
4
1
3
Q8201
4
1
3
83
83
80 79 59
6 5
78 76
6
6
83 80 79 78 77 76
6 5
Page 63
G
D
S
G
D
S
G
D
S
G
D
S
D
G
S
G
D
S
G
D
S
G
D
S
G
D
S
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
4.5V S0 AUDIO
2.5V S0
12V S0
3.3V S0
5V S0
1.8V S0
3.3V AND 5V S3
GATE_3V3_S3
PM_SLP_S4
GATE_5V_S3
PP5V_S5
PP5V_S3
PP3V3_S5
PP3V3_S3
PP12V_S5
PP12V_S5
PP12V_S5
PP5V_S5
PP5V_S0
PP3V3_S0
PP12V_S5
PP12V_S5
SYS_PWRUP_L
START_G_1V8_S0
PP1V8_S3
SYS_PWRUP_L
START_G_3V3_S0
PP1V8_S0
PP3V3_S5
SYS_PWRUP_L
TO_GATE_12V_S0_R
PP12V_S0
START_G_12V_S0
GATE_12V_S0
PP12V_S5
START_G_2V5_S0
PP2V5_S0
PP12V_S5
PP12V_S5
SYS_PWRUP_L
PP4V5_S0_AUDIO_ANALOG
START_G_5V_S0
SYS_PWRUP_L
SYS_PWRUP_L
PP2V5_S5
MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM
VOLTAGE=2.5V
START_G_4V5_S0
MIN_LINE_WIDTH=0.60MM MIN_NECK_WIDTH=0.25MM
VOLTAGE=2.5V
PP4V5_S5_AUDIO_ANALOG
9783
??
051-7032
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
S0 AND S3 FETS
603
MF-LF
1/10W
1%
100K
10% 50V X7R 603-1
0.01UF
NOSTUFF
X7R
10%
50V
0.01UF
603-1
2N7002
SOT23-LF
CRITICAL
TSOP-LF
SI3446DV
2N7002
SOT23-LF
1/10W
100K
MF-LF
1%
603
0.01UF
603-1
X7R
50V
10%
NOSTUFF
0.01UF
50V
10% X7R
603-1
SI3446DV
TSOP-LF
CRITICAL
1UF
10V 603
20% CERM
1UF
10V 603
20% CERM
1/16W
47K
5%
402
MF-LF
3.6K
5% MF-LF
1/16W 402
IRF7413PBF
SO-8
CRITICAL
1/16W
3.6K
5%
MF-LF
402
603-1
50V X7R
10%
0.01UF
SOT23-LF
2N7002
TSOP-LF
SI3446DV
CRITICAL
100K
1/10W
603
1%
MF-LF
603-1
X7R
50V
10%
NOSTUFF
0.01UF
47K
402
MF-LF
1/16W
5%
CERM
16V 402
10%
0.01UF
603
20%
0.1UF
CERM
25V
2N7002
SOT23-LF
2N7002
SOT23-LF
603
0.1UF
20% 25V CERM
NOSTUFF
SO-8
IRF7410PBF
B0530WXF
SOD-123
603
1/10W MF-LF
5%
47K
IRF7413PBF
SO-8
CRITICAL
MF-LF
1/10W
1%
10K
603
1%
100K
603
1/10W MF-LF
SOT563
CMLDM7002A
SOT563
CMLDM7002A
SOT23-LF
2N7002
50V X7R 603-1
0.01UF
10%
NOSTUFF
1%
603
1/10W
100K
MF-LF
0.01UF
10% X7R
50V 603-1
SI3446DV
CRITICAL
TSOP-LF
SOT23-LF
2N7002
603-1
50V X7R
10%
0.01UF
603-1
X7R
50V
10%
NOSTUFF
0.01UF
1/10W
603
MF-LF
1%
100K
TSOP-LF
SI3446DV
CRITICAL
Q8300
5 6 7 8
4
1 2 3
R8300
1
2
R8301
1
2
Q8301
5 6 7 8
4
1 2 3
R8302
1
2
R8303
1
2
C8399
1
2
C8398
1
2
Q8310
125
63
4
C8310
1
2
C8311
1
2
R8310
1 2
Q8311
3
1
2
Q8312
125
63
4
Q3815
3
1
2
C8315
1
2
C8321
1
2
R8311
1 2
Q8319
125
63
4
R8318
1 2
C8318
1
2
C8317
1
2
Q8320
3
1
2
Q8323
125
63
4
C8323
1
2
R8319
1 2
C8324
1
2
Q8324
3
1
2
Q8318
3
4
5
Q8318
6
1
2
R8313
1
2
R8312
1
2
R8315
1 2
D8310
1 2
Q8313
5
6
7
8
4
1
2
3
C8316
1
2
Q8303
3
1
2
Q8302
3
1
2
C8319
1
2
C8320
1
2
C8326
1
2
R8325
1 2
Q8317
125
63
4
Q8316
3
1
2
C8325
1
2
79 77
83 82 80 79 59
6 5
59
6
83
80 79 78 77 76 66 65 59 26
6 5
59 53
6
83 82 80 79 78 77 76
6 5
83 82 80
79 78 77 76
6 5
83 82 80 79 78 77 76
6 5
83 82 80 79 59
6 5
75
6
94 76 61 59 41 26 10
6
83 82
80 79 78 77 76
6 5
83 82
80 79 78 77 76
6 5
83 77
79
6 5
83 77
6
83
80 79 78 77 76 66 65 59 26
6 5
83 77
76
6
83 82 80 79 78 77 76
6 5
6
83 82
80 79 78 77 76
6 5
83 82
80 79 78 77 76
6 5
83 77
6
83 77
83 77
78
82
Page 64
G
D
S
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
LCD (LVDS) INTERFACE
INVERTER INTERFACE
GATE TO PREVENT LEAKAGE ONTO PWM MIGHT BE ABLE TO BYPASS IF SMC DRIVES SIGNAL
518S0331
LVDS REFERENCE CURRENT, 1.5K OHM PULL DOWN RESISTOR NEEDED
RESISTOR TO SET DEFAULT VALUE OF PANEL ID
PANEL HAS 4.2K PULL-UPS
10K PULL-UPS ON I2C LINES
INTEL RECOMMENDS
402
MF-LF
1/16W
5%
100K
0.001UF
10% 50V
CERM
402
402
100K
1/16W MF-LF
5%
0.001UF
10% 50V
CERM
402
SM
FERR-250-OHM
CERM
20% 16V
0.1UF
603
402
47K
MF-LF
5%
1/16W
402
MF-LF
5%
1/16W
100K
SI3443DV
CRITICAL
TSOP-LF
SOT23-LF
2N7002
CERM
20%
4.7UF
16V
1206-1
402
47
5%
MF-LF
1/16W
5%
100K
1/16W
402
MF-LF
CRITICAL
53307-3072
F-ST-SM
STDOFF-3MMOD4.6MMH-1.35-TH
STDOFF-3MMOD4.6MMH-1.35-TH
CERM 1210
16V
10UF
10%
87437-0443-BLK
M-ST-SM
CRITICAL
402
1/16W
5%
47
MF-LF
402
10K
5% 1/16W MF-LF
402
CERM
20%
NOSTUFF
10V
0.1UF
NOSTUFF
MC74VHC1G08
SOT23-5-LF
402
1/16W
5%
MF-LF
0
402
NOSTUFF
MF-LF
10K
5% 1/16W
I512
I513
I514
402
MF-LF
10K
5% 1/16W
402
MF-LF
10K
5% 1/16W
402
1.5K
1% 1/16W MF-LF
402
5%
10K
1/16W MF-LF
NOSTUFF
0
5%
1/8W
MF-LF
805
94 97
??
051-7032
Internal Display Conns
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm
PP3V3_LCD_SW
LVDS_DDC_DATA
VOLTAGE=3.3V MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm
PP3V3_LCD_CONN
LVDS_VREFL
LCD_PWM_R
SB_GPIO_48
PANEL_ID
=PP3V3_S0_LCD
LVDS_DDC_CLK
=PP3V3_S0_LCD
LCD_PWM
LVDS_IBG
LVDS_VREFH
LVDS_CLKCTLB
LVDS_CLKCTLA
PP3V3_S0
=PP3V3_S0_LCD
LVDS_B_DATA_P<1>
LVDS_B_DATA_P<0>
LVDS_B_DATA_P<2>
LVDS_A_DATA_N<0>
LVDS_DDC_CLK
LVDS_A_DATA_P<2>
LVDS_B_DATA_N<0>
LCD_PWREN_L
GPU_PWM_RST_L
=PP3V3_DDC_LCD
LVDS_B_CLK_N
LVDS_A_DATA_P<1>
LCD_PWM
LVDS_DDC_DATA
LVDS_B_DATA_N<2>
LVDS_B_DATA_N<1>
LVDS_B_CLK_P
LVDS_A_DATA_P<0> LVDS_A_DATA_N<1>
LVDS_A_CLK_N
LVDS_A_DATA_N<2>
PP3V3_LCD_CONN PP3V3_LCD_CONN
LVDS_BKLTCTL
=PP12V_INVERTER
LVDS_VDDEN
=PP3V3_DDC_LCD
LCD_PWREN_L_RC
PP3V3_LCD_CONN
=PP3V3_DDC_LCD
LVDS_A_CLK_P
=PP3V3_S0_LCD
=PP3V3_S5_LCD
PANEL_ID
R9410
1
2
C9410
1
2
R9411
1
2
C9401
1
2
L9400
1 2
C9400
1 2
R9401
1 2
R9400
1
2
Q9400
1
2
5
63
4
Q9401
3
1
2
C9450
1
2
R9450
1 2
R9470
1
2
J9402
1
10
11
12
13
14
15
16
17
18
19
2
20
21
22
23
24
25
26
27
28
29
3
30
4
5
6
7
8
9
SDF9400
1
SDF9401
1
C9420
1
2
J9401
1 2 3 4
R9475
1 2
R9474
1
2
C9470
1
2
U9470
3
2
1
4
5
R9473
1 2
R9472
1
2
R9420
1
2
R9421
1
2
R9422
1 2
R9451
1
2
R9402
1 2
94 13
94
6
13
22 94
94
6
94 13
94
6
94
13
13
13
13
83 76 61 59 41 26 10
6
94
6
13
13
13
13
94 13
13
13
6
94
13
13
94
94 13
13
13
13
13
13
13
13
94
6
94
6
13
6
13
94
94
6
94
13
94
6
6
94
Page 65
IN
IN
IN
OUT
IN
IN
IN
IN
IN
OUT
OUT OUT
OUT
TX0_P TX0_N
TX1_N
TX1_P
TX2_P TX2_N TXC_P
SCLDDC SDADDC
SDG_P
TEST
EXT_SWING
TXC_N
SGND1
SGND0
PGND2
AGND0
AGND1
AGND2
GND1
SPGND
GND0
HTPLG
A1
SDSDA
SDSCL
RESET*
EXT_RES
SDI_P SDI_N
SDC_P SDC_N
SDB_P SDB_N
SDR_N
SDR_P
SDG_N
VCC1
VCC0
VCC2
AVCC0
AVCC1
PVCC1
PVCC2
SVCC0
SVCC1
SPVCC
OVCC
CORE
SDVO RCVR
I2C MASTER
INTER
TEXT MODE
CONFIG/
PRGRM
DIFF SIG
DATA
OUT OUT
OUT
IO IO
OUT
OUT
IO
IO
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
PLACE NEAR U9500
NEAR CONNECTOR
PLACE THIS SET OF TERMINATION
ONE 0.1UF AND 0.001UF FOR EACH PIN
TMDS CHIP SDVO INPUT INTERRUPT SIGNAL TO MCH
PLACE IT CLOSE TO CONNECTOR
ONE 0.1UF AND 0.001UF FOR EACH PIN
NC
IF HIGH, ADDRESS=0X72
ADDRESS=0X70
MCH SDVO CHANNEL R,G,B,CLK SIGNAL TO TMDS CHIP
PLACE THE CAP NEAR THE NB SIDE
ONE 0.1UF AND 0.001UF FOR EACH PIN
THESE 2 CAPS FOR EMI RIGHT ON TRACE WITH
NO STUB.
PP3V3_ANALOG_TMDS
TMDS_TX_CLK_P
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V
PP3V3_ANALOG_TMDS
=PP3V3_S0_TMDS
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM VOLTAGE=3.3V
PP3V3_PVCC2_TMDS
=PP3V3_S0_TMDS
PEG_R2D_C_P<3>
TMDS_SDC_N
TMDS_INT_P TMDS_INT_N
TMDS_RESET_L
=PP5V_S0_TMDS
TMDS_TX_CLK_N
TMDS_TX_CLK_P
TMDS_TX_N<2>
TMDS_EXT_SWING
TMDS_TX_P<2>
TMDS_TX_N<1>
PP1V8_ANALOG_SDVO
=PP1V8_S0_TMDS
PP3V3_ANALOG_SDVO
=PP3V3_S0_TMDS
SDVO_CTRLDATA
=PP2V5_S0_TMDS
TMDS_SDB_N
=PP3V3_S0_TMDS
PEG_D2R_N<1>
PEG_R2D_C_P<2>
PEG_R2D_C_N<3>
PEG_R2D_C_N<2>
=PP3V3_S0_TMDS
PP3V3_ANALOG_TMDS PP1V8_TMDS
TMDS_SDR_P TMDS_SDR_N TMDS_SDG_P
TMDS_TX_P<1>
TMDS_TX_P<0>
PP3V3_PVCC1_TMDS
TMDS_I2C_SDA
PEG_R2D_C_P<0>
=PP1V8_S0_TMDS
TMDS_EXT_RES
=PP3V3_S0_TMDS
TMDS_HTPLG
TMDS_TX_HPD
TMDS_HTPLG_R
TMDS_SDC_P
TMDS_SDG_N
PP3V3_PVCC2_TMDS
PEG_R2D_C_N<1>
PEG_R2D_C_P<1>
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V
PP1V8_ANALOG_SDVO
VOLTAGE=3.3V
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
PP3V3_ANALOG_SDVO
MIN_NECK_WIDTH=0.2MM VOLTAGE=3.3V
MIN_LINE_WIDTH=0.6MM
PP3V3_PVCC1_TMDS
TMDS_TX<0>
TMDS_TX<1>
TMDS_TX<2>
PP1V8_TMDS
MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM VOLTAGE=1.8V
SDVO_CTRLCLK
TMDS_SDB_P
PEG_R2D_C_N<0>
TMDS_TX_CLK
TMDS_TX_N<0>
TMDS_TX_N<1>
TMDS_TX_P<2>
TMDS_TX_CLK_N
TMDS_TX_N<2>
TMDS_TX_P<1>
TMDS_TX_N<0>
TMDS_I2C_SCL
EXTERNAL TMDS
051-7032
??
9795
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
PEG_D2R_P<1>
16V 402X5R
10%
0.1UF
16V
0.1UF
X5R 402
10%
X5R
0.1UF
16V
10% 402
10UF
CERM
6.3V
20% 805-1
CERM 402
50V
0.001UF
10%
10UF
805-1
CERM
20%
6.3V
402
10PF
5% 50V CERM
NOSTUFF
402
10PF
5% 50V CERM
NOSTUFF
805-1
6.3V
20%
10UF
CERM
16V X5R 402
10%
0.1UF
402
50V
10% CERM
0.001UF
16V X5R 402
10%
0.1UF
402
0.001UF
10% CERM
50V
0.001UF
10% 50V
402
CERM
402
X5R
16V
10%
0.1UF
301
402
1/16W MF-LF
1%
MF-LF
1/16W
5%
2.2K
402
402
5% 1/16W MF-LF
5.6K5.6K
5% 1/16W MF-LF 402
BAV99DW-X-F
SOT-363
MF-LF
1/16W
5%
1K
402
0402
FERR-120-OHM-1.5A
0402
FERR-120-OHM-1.5A
402
10K
5% 1/16W MF-LF
402
10K
5% 1/16W MF-LF
0402
FERR-120-OHM-1.5A
0402
FERR-120-OHM-1.5A
FERR-120-OHM-1.5A
0402
0402
FERR-120-OHM-1.5A
10% 16V X5R
0.1UF
402
1%
130
402
1/16W MF-LF
10% 16V X5R
0.1UF
402
1%
130
402
1/16W MF-LF
X5R
10% 16V
0.1UF
402
1/16W
1%
130
402
MF-LF
402
0.1UF
X5R
16V
10%
LQFP
SIL1362ACLU
402
CERM
10% 50V
0.001UF
402
0.001UF
50V
10% CERM
402
50V
10% CERM
0.001UF
0.001UF
CERM
10% 50V
402
402
CERM
10% 50V
0.001UF
402
50V
0.001UF
CERM
10%10%
50V
0.001UF
CERM 402 402
X5R
0.1UF
10% 16V
402
X5R
10%
0.1UF
16V
6.3V
20% CERM
10UF
805-1
0.1UF
10% 16V X5R 402
0.1UF
10%
402
X5R
16V
X5R
0.1UF
402
16V
10%
402
X5R
16V
10%
0.1UF
16V
10%
402
0.1UF
X5R
402
X5R
0.1UF
10%
16V
402
0.1UF
10%
16V
X5R
10%
402
0.1UF
X5R
16V
0.1UF
10%
402
16V
X5R
402
10%
0.1UF
16V
X5R
0.1UF
10%
16V
402
X5R
0.1UF
402
10% X5R
16V
402
16V10%
X5R
0.1UF
X5R 402
10% 16V
0.1UF
50V 402
10% CERM
0.001UF
X5R 402
16V
0.1UF
10%
0.001UF
CERM 402
10% 50V
10% 16V X5R
0.1UF
402
TMDS_TX_P<0>
MF-LF
1/16W
402
1%
PLACEHOLDER
100
C9513
1
2
C9512
1
2
C9504
1
2
C9503
1
2
C9521
1
2
C9519
1 2
C9511
1
2
C9510
1
2
C9509
1
2
C9508
1
2
C9507
1
2
C9520
1 2
C9548
1
2
C9547
1
2
C9546
1
2
C9545
1
2
C9544
1
2
C9543
1
2
C9542
1
2
C9541
1
2
C9531
1
2
C9502
1
2
C9533
1
2
C9535
1
2
C9540
1
2
C9539
1
2
C9538
1
2
C9536
1
2
C9537
1
2
C9532
1
2
C9534
1
2
C9501
1
2
C9500
1
2
C9530
1
2
U9500
6
121824
15
21
35
25
7
31
29
1
27
11
26
2
8 9
44
43
47
46
41
40
33
32
38
37
5 4
39
45
3
483642
30
16
17
19
20
22
23
13
14
102834
C9522
1 2
R9537
1 2
C9523
1 2
R9538
1 2
C9524
1 2
R9539
1 2
C9525
1 2
R9540
1 2
L9504
1 2
L9503
1 2
L9500
1 2
L9505
1 2
R9505
1
2
R9506
1
2
L9501
1 2
L9506
1 2
R9503
1
2
D9500
1
2
6
R9501
1
2
R9502
1
2
R9500
1 2
R9504
1
2
C9552
1
2
C9551
1
2
C9553
1
2
C9554
1
2
C9555
1
2
C9556
1
2
C9565
1
2
C9505
1
2
C9506
1
2
95
97 95
95
97 96 95
6
95
97 96 95
6
13
6
97
6
97 95
97 95
97 95
97 95
97 95
95
95
6
95
97 96 95
6
14
6
97 96 95
6
13
13
13
13
97 96 95
6
95
95
97 95
97 95
95
13
95
6
97 96 95
6
97
95
13
13
95
95
95
95
14
13
97
95
97 95
97 95
97 95
97 95
97 95
97 95
13
97
95
Page 66
125
125
GND
VCC
DA
S1A S2A
S1B S2B
S1C S2C
S1D S2D
IN EN_L
DD
DC
DB
125 125
LCFILTER
LCFILTER
LCFILTER
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
VIDEO_MUX_SEL
SPARE BUFFERS, TYING OE* HIGH
VGA SYNC BUFFERS
PLACE RESISTORS AT NORTHBRIDGE
0
1
TV
NC
NC NC
PLACE U9620 NEAR GMCH
ANALOG FILTERING
PLACE BY CONNECTOR
TSSOP
74LC125
74LC125
TSSOP
TS3V330
SOP
0.1UF
10% 16V X5R 402
74LC125
TSSOP TSSOP
74LC125
805-1
CERM
10UF
20%
6.3V
SM-220MHZ-LF
SM-220MHZ-LF
SM-220MHZ-LF
50V
NOSTUFF
CERM
5%
22PF
402
402
1/16W
5%
39
MF-LF
402
5%
50V
CERM
22PF
NOSTUFF
1/16W
5%
39
MF-LF
402
MF-LF
1%
1/16W
75
402
1/16W MF-LF
1%
75
402
1/16W MF-LF
1%
75
402
NOSTUFF
150
1%
402
MF-LF
1/16W
NOSTUFF
150
1%
402
MF-LF
1/16W
NOSTUFF
1/16W
150
1%
402
MF-LF
255
1%
402
MF-LF
1/16W
5% 1/16W MF-LF
39
402
MF-LF
5%
1/16W
402
39
I942
I943
I944
1%
1/16W
75
402
MF-LF
I961
1%
1/16W
75
402
MF-LF
I963
1%
1/16W
75
402
MF-LF
I967
402
4.99K
1% 1/16W MF-LF
TMDS/Inverter/ExtVGA
9796
??
051-7032
SYNC_MASTER=MASTER
SYNC_DATE=MASTER
VIDEO_MUX_GREEN
VIDEO_MUX_RED
VIDEO_MUX_BLUE
FILT_ANALOG_RED
FILT_ANALOG_BLU
FILT_ANALOG_GRN
=PP3V3_S0_TMDS
CRT_GREEN_L
CRT_RED_L
TV_IRTNC
=PP3V3_S0_TMDS
CRT_VSYNC
CRT_HSYNC
TV_DACA_OUT
CRT_RED
TV_IREF
CRT_IREF
CRT_HSYNC_R
VIDEO_MUX_RED
VIDEO_MUX_BLUE
VIDEO_MUX_GREEN
VGA_BUF_HSYNC
VGA_HSYNC
CRT_GREEN
CRT_BLUE
SB_CRT_TVOUT_MUX
TV_DACA_OUT
TV_DACB_OUT
CRT_RED
TV_DACC_OUT
CRT_VSYNC_R
VGA_VSYNC
VGA_BUF_VSYNC
CRT_BLUE_L
CRT_BLUE
TV_DACC_OUT
CRT_GREEN
TV_IRTNB
TV_DACB_OUT
TV_IRTNA
=PP3V3_S0_TMDS
402
CERM
1UF
10%
6.3V
FL9602
1 2
3 4
FL9601
1 2
3 4
FL9600
1 2
3 4
C9670
1
2
C9608
1
2
R9671
1 2
C9607
1
2
R9672
1 2
R9690
1
2
R9692
1
2
R9694
1
2
R9691
1
2
R9693
1
2
R9695
1
2
R96A0
1
2
R9600
1 2
R9601
1 2
R9696
1
2
R9697
1
2
R9698
1
2
R9699
1
2
U9670
2
7 1
14
3
U9670
5
7 4
14
6
U9620
4
7
9
12
15
8
1
2
5
11
14
3
6
10
13
16
C9620
1
2
U9670
9
7
10
14
8
U9670
12
7
13
14
11
C9621
1
2
96
96
96
97
97
97
97 96 95
6
13
13
13
97 96 95
6
96 13
96 13
13
13
13
96
96
96
97
96 13
96 13
22
96 13
96 13
96 13
96 13
13 97
13
96 13
96 13
96 13
13
96 13
13
97 96 95
6
Page 67
G
SD
G
SD
SYM_VER-1
SYM_VER-1
SYM_VER-1
SYM_VER-1
CRITICAL BOM OPTION
TABLE_5_HEAD
PART#
DESCRIPTION
QTY
REFERENCE DESIGNATOR(S)
TABLE_5_ITEM
D
SIZE
OF
SHT
DRAWING NUMBER
NOTICE OF PROPRIETARY PROPERTY
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE
III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART
II NOT TO REPRODUCE OR COPY IT
AGREES TO THE FOLLOWING
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
1
2
3
4
5
67
8
12
3
4
5
6
78
B
C
D
A
B
C
D
A
REV.
APPLE COMPUTER INC.
SCALE
NONE
WHEN PART AVAILABILITY FINALIZES,
(55mA requirement per DVI spec)
AS POSSIBLE
PLACE FILTER CLOSE TO TMDS CONNECTOR
3V LEVEL SHIFTERS
PLACE LEFT SIDE
REMOVE TABLE AND OMIT ON PART
514S0128
AS CLOSE TO GPU (U8400)
DVI INTERFACE
DVI DDC CURRENT LIMIT
1/16W MF-LF 402
10K
5%
MF-LF 402
5% 1/16W
10K
2N7002DW-X-F
SOT-363
2N7002DW-X-F
SOT-363
100K
MF-LF 402
5% 1/16W
100pF
CERM 402
5% 50V
MF-LF 402
5% 1/16W
4.7K
4.7K
MF-LF
402
5%
1/16W
100pF
CERM 402
5% 50V
50V
0.01UF
10% X7R
603-1
400-OHM-EMI
SM-1
CRITICAL
0.5AMP-13.2V
SM-LF
100pF
CERM 402
5% 50V
1/16W
5%
100
MF-LF
402
100
MF-LF
402
5%
1/16W
1/16W
402
MF-LF
20.0K
1%
2012H
90-OHM-300MA
CRITICAL
2012H
90-OHM-300MA
CRITICAL
2012H
90-OHM-300MA
CRITICAL
OMIT
SM
165-OHM
CRITICAL
F-ST-SM4
OMIT
MINI-DVI
MMSZ4681XXG
CASE425
0.1UF
10% 16V X5R 402 402
X5R
16V
10%
0.1UF
402
10%
0.1UF
X5R
16V
402
X5R
16V
10%
0.1UF
SOD-123
B0530WXF
SYNC_DATE=MASTER
SYNC_MASTER=MASTER
External Display Conns
051-7032
??
9797
CRITICAL
J9710
1
514S0128
MINI DVI CONNECTOR,32P,TH SHIELD, W/O RIBS
DIFFERENTIAL_PAIR=TMDS_TX_CLK
TMDS_TX_CLK_P
DIFFERENTIAL_PAIR=TMDS_TX_2
TMDS_TX_P<2>
TMDS_CONN_DP<2>
DIFFERENTIAL_PAIR=TMDS_CONN_D2
TMDS_CONN_DP<1>
TMDS_CONN_DN<1>
PP5V_S0_DDC_FUSE
MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
VOLTAGE=5V MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm
PP5V_S0_DDC
TMDS_CONN_CLKN
TMDS_CONN_CLKP
DIFFERENTIAL_PAIR=TMDS_CONN_D2
TMDS_CONN_DN<2>
DIFFERENTIAL_PAIR=TMDS_CONN_D0
TMDS_CONN_DP<0>
DIFFERENTIAL_PAIR=TMDS_CONN_D0
TMDS_CONN_DN<0>
=PP5V_S0_TMDS
PP5V_S0_TMDS_D
DIFFERENTIAL_PAIR=TMDS_TX_0
TMDS_TX_N<0>
DIFFERENTIAL_PAIR=TMDS_TX_0
TMDS_TX_P<0>
FILT_ANALOG_BLU
VGA_BUF_VSYNC
GND_CHASSIS_VGA_C_A
TMDS_CONN_CLKP
TMDS_CONN_CLKN
FILT_ANALOG_RED
TMDS_CONN_DN<0>
TMDS_CONN_DP<0>
FILT_ANALOG_GRN
VGA_BUF_HSYNC
DVI_DDC_DATA_UF
PP5V_S0_DDC
DVI_HPD_UF
DVI_DDC_CLK_UF
DVI_DDC_DATA_UF
TMDS_TX_CLK_N
DIFFERENTIAL_PAIR=TMDS_TX_CLK
TMDS_TX_N<2>
DIFFERENTIAL_PAIR=TMDS_TX_2
TMDS_TX_N<1>
DIFFERENTIAL_PAIR=TMDS_TX_1
DIFFERENTIAL_PAIR=TMDS_TX_1
TMDS_TX_P<1>
DVI_HPD_UF
TMDS_CONN_DP<2>
TMDS_CONN_DN<2>
TMDS_CONN_DN<1>
TMDS_CONN_DP<1>
DVI_DDC_CLK_UF
CRT_DDC_CLKDVI_DDC_CLK
TMDS_TX_HPD
DVI_DDC_DATA CRT_DDC_DATA
=PP3V3_S0_TMDS
GND_CHASSIS_VGA
GND_CHASSIS_VGA_C_B
R9721
1
2
R9720
1
2
Q9711
6
2
1
Q9711
3
5
4
R9722
1
2
C9713
1
2
R9712
1
2
R9710
1
2
C9711
1
2
C9710
1
2
L9710
1 2
F9710
1 2
C9714
1
2
R9711
1 2
R9713
1 2
R9714
1 2
L9700
1
2 3
4
L9701
1
23
4
L9702
1
2 3
4
L9703
1
2 3
4
J9710
20
8
7
6
5
4
3
2
1
26 18
25
9
10
32
11
12
13
14
15
16
28
30 22
29
17
24
33
34
19
27
31
D9700
2 1
C9720
1
2
C9721
1
2
C9722
1
2
C9723
1
2
D9710
1 2
95
95
97
97
97
97
97
97
97
97
97
95
6
95
95
96
96 97
97
96
97
97
96
96
97
97
97
97
97
95
95
95
95
97 97
97
97
97
97
13
95
13
96 95
6
6
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