Apple A1425 Schematics

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

D

C

B

7

6 5 4 3

2 1

REV ECN

DESCRIPTION OF REVISION

CK
APPD

DATE

<REV> <ECN>

<ECO_DESCRIPTION>

<ECODATE>

SCHEM,MLB,D1

8/8/12

Page

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(.csa)

1

Table of Contents

2

System Block Diagram

3

Power Block Diagram

4

Revision History

5

BOM Configuration

6

BOM Configuration

7

Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU DMI/PEG/FDI/RSVD

11

CPU CLOCK/MISC/JTAG

12

CPU DDR3 INTERFACES

13

CPU POWER

14

CPU GROUNDS

16

CPU DECOUPLING-I

17

CPU DECOUPLING-II

18

PCH SATA/PCIe/CLK/LPC/SPI

19

PCH DMI/FDI/PM/Graphics

20

PCH PCI/USB/TP/RSVD

21

PCH GPIO/MISC/NCTF

22

PCH POWER

23

PCH GROUNDS

24

PCH DECOUPLING

25

CPU & PCH XDP

26

Chipset Support

27

USB HUB & MUX

28

CPU Memory S3 Support

29

DDR3 SDRAM Bank A (Rank 0)

31

DDR3 SDRAM Bank B (Rank 0)

33

DDR3 Termination

34

DDR3/FRAMEBUF VREF MARGINING

35

ALS/CAMERA CONNECTOR

36

Thunderbolt Host (1 of 2)

37

Thunderbolt Host (2 of 2)

38

Thunderbolt Power Support

44

RIO CONNECTORS

45

SSD/HDD Connectors

46

USB 3.0 CONNECTORS

49

50

SMC Support

51

LPC+SPI Debug Connector

52

SMBus Connections

53

Power Sensor: Load Side

54

Power Sensor: High Side

55

Thermal Sensors

Contents

Sync

MASTER

MASTER

K17_REF

MASTER

MASTER

MASTER

MASTER

MASTER

D1_MLB_TEST

J30_MLB

J30_MLB

J30_MLB

J30_MLB

J30_MLB

MASTER

MASTER

J13_MLB

J13_MLB

J13_MLB

J13_MLB

J13_MLB

J13_MLB

J13_MLB

J30_MLB

MASTER

J5_AMD

J5_MLB

J5_MLB

J5_MLB

MASTER

J5_MLB

MASTER

J5_MLB_KEPLER

J5_MLB_KEPLER

J5_MLB_KEPLER

MASTER

MASTER

J5_AMD

D1_SENSORS

D1_SENSORS

D1_SENSORS

MASTER

D1_SENSORS

D1_SENSORS

D1_SENSORS

Date

MASTER

02/15/2011

06/30/2009

MASTER

MASTER

MASTER

MASTER

MASTER

01/27/2012

07/14/2011

07/14/2011

07/14/2011

07/14/2011

07/14/2011

MASTER

MASTER

09/15/2011

09/15/2011

09/15/2011

09/15/2011

09/15/2011

09/15/2011

09/15/2011

07/14/2011

MASTER

08/17/2011

07/29/2011

07/14/2011

07/14/2011

MASTER

07/29/2011

MASTER

11/14/2011

11/14/2011

11/14/2011

MASTER

MASTER

08/24/2011

02/20/2012

02/20/2012

02/20/2012

MASTER

02/20/2012

02/20/2012

02/20/2012

Page

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46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80

(.csa)

56

Fan Connectors

57

KEYBOARD/TRACKPAD (1 OF 2)

58

KEYBOARD/TRACKPAD (2 OF 2)

59

DIGITAL ACCELEROMETER & GYRO

61

SPI ROM

62

AUDIO: CODEC/REGULATOR

63

AUDIO: HEADPHONE FILTER

66

AUDIO: SPEAKER AMP

67

AUDIO: JACK

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

System Agent Supply

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

74

CPU IMVP7 & AXG VCore Regulator

75

CPU IMVP7 & AXG VCore Output

76

CPUVCCIO (1.05V) Power Supply

77

Misc Power Supplies

78

Power FETs

79

Power Control 1/ENABLE

90

eDP Display Connector

92

DDC Crossbar

94

Thunderbolt Connector A

96

Thunderbolt Connector B

97

LCD Backlight Driver (LP8545)

100

CPU Constraints

101

Memory Constraints

102

PCH Constraints 1

103

PCH Constraints 2

105

Thunderbolt Constraints

106

SMC Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

132

Power Sensors: Extended

Contents

J5_MLB

D2_MLB_KEPLER

D2_MLB_KEPLER

J5_MLB

J13_MLB

D1_AUDIO

D1_AUDIO

D1_AUDIO

D1_AUDIO

D1_AUDIO

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

D1_SENSORS

MASTER

J5_MLB_KEPLER

J5_MLB_KEPLER

J5_MLB_KEPLER

J5_MLB

J5_MLB

J5_MLB_KEPLER

J5_MLB

T29_CR

J5_MLB

J5_MLB

J5_MLB

D1_SENSORS

Sync

Date

07/29/2011

12/08/2011

12/08/2011

07/29/2011

01/20/2012

06/06/2012

06/06/2012

06/06/2012

06/06/2012

06/06/2012

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

MASTER

07/11/2012

MASTER

11/14/2011

11/14/2011

09/21/2011

09/13/2011

09/13/2011

09/21/2011

07/29/2011

08/31/2011

07/29/2011

07/29/2011

07/29/2011

07/11/2012

D

C

B

A

Schematic / PCB #’s

PART NUMBER

820-3462

DRAWING

TITLE=MLB
ABBREV=ABBREV

LAST_MODIFIED=Thu Aug 9 12:34:09 2012

QTY

1 SCH

DESCRIPTION

SCHEM,MLB,D1

PCBF,MLB(NEW),D1

REFERENCE DES

PCB1

CRITICAL

CRITICAL051-9216

CRITICAL

BOM OPTION

www.vinafix.vn

SIZE

A

D

DRAWING TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

3

SCHEM,MLB,D1

Apple Inc.

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

1 OF 132

SHEET

1 OF 80

1245678

8 7 6 5 4 3

J2500

XDP CONN

U1000

PG 23

12

J3502

U3100-U3170

Mem

CAMERA

PG 31

PG 28

U6100

SPI

Boot ROM

PG 49

J4410

RIO CONN

Bluetooth

PG 35

1 2 3

U2700

USB
HUB

PG 25

U4900

I2C Ser

U5701

TP/KB

PSOC

PG 46 PG 46

From PCH

SMC

PG 38

J5700, J5713

U4900

U2760

EHCI
XHCI

J2550

Fan

ADCSMS

Prt

TRACKPAD/

KEYBOARD

SMC

PG 38

USB
MUX

PG 25

PCH XDP

J6900, J6950

DC/BATT

PG 55

U5550,U5570

TEMP SENSOR

PG 47

U5920,U5940

Motion Sensor/GYRO

U5340,U5350,U5360,U5370,U5400,U5410,Q5480
Q5490

J5650,J5660

FAN CONN AND CONTROL

PG 48

POWER SENSE

PG 42, 43

PG 45

J5100

SPI

Port80,serial

J4410

RIO CONN

USB 3

PG 35

J4600

EXTERNAL A

USB 3

PG37

LPC+SPI Conn

PG 40

D

POWER SUPPLY

PG 56-65

C

B

INTEL CPU

2.X GHz

IVY BRIDGE 2C-35W

PG 9-15

D

U2600

SYSTEM

CLOCK

PG 24

GPIO

PG 19

CLK

BUFFER

PG 16

FDI

PG 17

DMI

PG 17

DDR3-1333/1600MHZ

U2900-U2970

Mem

PG 27

RTC

PG 16

MISC

PG 19

SPI

U4510

SATA

REDRIVER

PG 36

C

U9420

J9400

DP/TBT

PORT

CONN

PG 68,69

PortA

PortB

MUX

PG 68

U9620

U3600

CIO

TBT Host

CIO

PG 32,33

PCIe x4

DP

J4500

SATA
CONN

HDD

PG 36

MUX

PG 69

J9000

eDP

CONN

PG 66

J4410

RIO CONN

B

HDMI

PG 35

1.05V/6GHZ.
0

SATA

PG 16

LVDS OUT

RGB OUT

DP OUT

DVI OUT

TMDS OUT

PG 17

eDP OUT

PG 17

PCI

PG 18

HDMI

PG 17

JTAG

PG 16

PEG

PG 16

INTEL

PANTHER POINT-MPCH

U1800

PG 16-21

PCI-E

(UP TO 8 LINES)

PG 16

2 1

PG 16

LPC

PG 16

PWR

CTRL

PG 17

13
12
1110

98

USB

PG 18

4
3 5

(UP TO 14 DEVICES)

1 2
0 76

4
32

PG 18

1

USB 3

SMBUS

PG 16

HDA

PG 16

CONN

PG 23

U6201

EXTMIC LINEIN HPOUT SPDIF MICIN LINEOUT

J4410

AUDIO
Codec

PG 50

RIO CONN

J6802
J6803

PG 54

U6610,U6620
U6630,U6640

SPEAKER

AMPs

PG 52

SYNC_MASTER=MASTER

PAGE TITLE

System Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=02/15/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

2 OF 132

SHEET

2 OF 80

124578

SIZE

A

D

Airport/SD Card

PG 35

A

U6750

MIC BIAS

PG53

J6701

PG 53

AUDIO
CONNs

J5815
PG 47

6 3

www.vinafix.vn

8 7 6 5 4 3

12

D1 POWER SYSTEM ARCHITECTURE

PPDCIN_G3H

P5V1_VIN

D

J6900

AC

ADAPTER

IN

DCIN(16.5V)

F6905
6A FUSE

R7020

A

SMC_DCIN_ISENSE

SMC_RESET_L

ENABLE

LT3470A

U7090

(PAGE 56)

VIN

PBUS SUPPLY/

BATTERY CHARGER

PP5V1_CHGR_VDDP

U7000

ISL6259

R6920

VOUT

PPVBAT_G3H

R7050

SMC_BATT_ISENSE

(PAGE 56)

J6950

PPVBATT_G3H_CONN

3S2P

(9 TO 12.6V)

Q7055

CHGR_BGATE

PPVBAT_G3H_CHGR_R

PPDCIN_S5_P3V42G3H

F7040

A

www.qdzbwx.com

PPBUS_G3H

C

SMC

U4900

(PAGE 38)

Panther-POINT

(PCH)

(PAGE 16~21)

RC

DELAY

RC

DELAY

RC

DELAY

RC

DELAY

U1800

SLP_S3#(D4)

PVCCSA_EN

CPUVCCIOS0_EN

P1V8S0_EN

P1V5S0_EN

B

A

P60

SMC_S4_WAKESRC_EN

SLP_S5#(F6)

SLP_S4#(K10)

PG67

PG67

PG67

SMC_PM_G2_EN

PM_SLP_S5_L

PG67

RC

DELAY

PG 17

DDRREG_EN

RC

DELAY

P5VS3_EN

RC

DELAY

P3V3S3_EN

RC

DELAY

P1V2S3_EN

RC

DELAY

TPAD_VBUS_EN

RC

DELAY

PM_SLP_S4_L

PM_SLP_S3_L

R7978

PG65

PM_SLP_S3_R_L

P5VS0_EN

P3V3S0_EN

PBUSVSENS_EN

TBT_S0_EN

P3V3S5_EN

74LVG1G32

U7970

(PAGE 65)

PG67

PG 17

PG 17

TBTAPWRSW_EN
TBTBPWRSW_EN
P3V3S4_EN

P5VS4_EN

PG59

PG64

PG64

PG46

F9700

LCD_BKLT_EN

&&

BKLT_PLT_RST_L

PPBUS_S0_LCDBKLT_PWR

Q4260

PP3V3_S0 && FWPORT_PWR_EN

T29_A_HV_EN

Q9706

EN

Q3880

R5430

A

VIN

LP8545SQX-EXTJ

U9701

(PAGE 70)

PPBUS_S5_HS_OTHER_ISNS

P5V3V3S4_EN

P3V3S5_EN

PPVOUT_S0_LCDBKLT

VOUT

F4260

VIN

LT3957

U3890

VOUT

(PAGE 34)

EN1

EN2

PPVP_FW

PP15V_TBT_REG

VIN

TPS51980

U7201

(PAGE 60)

5V

(L/H)

3.3V

(R/H)

PGOOD

P5V3V3_PGOOD

VREG5

VOUT1

VOUT2

Q5720

SLG5AP020

VCC

(PAGE 64)

U7801

6 3

D6905

PP5V_S5RS4_CUMUUS

P5VS4_EN

P1V5CPU_EN

ON

P1V5_CPU_EN

PPVIN_S3_P1V5S3RS0_FET

PP5V_S4

PP3V3_S5

SMC_PBUS_VSENSE

V

P1V5S3RS0FET_GATE

PP3V3_S5

Q7800

P3V3_S4_EN

Q7840

Q7810

Q7830

Q7850

P5VS3_EN

Q7820

P3V3_SUS_EN

PP3V3_S4_FET

P5VSUS_EN

P3V3S3_EN

PP3V3_S0_FET

P3V3_S0_EN

PP5VS3_FET

PP3V3_SUS_FET

PP5V_S0

CPUVCCIOS0_EN

CPUIMVP_VR_ON

DDRREG_EN

MEMVTT_EN

PP5V_S0

PVCCSA_EN

Q7801

PP1V5_S3RS0_FET

PP5V_SUS_FET

PP3V3_S3

PP3V3_S0_P1V8S0

P1V8_S0_EN

ENABLE

3.425V G3HOT

LT3470A

U6990

(PAGE 55)

1.05V

VCC

ISL95874

U7600

EN

(PAGE 62)

CPU VCORE

VIN

MAX15119GTM

U7400

VR_ON

(PAGE 60)

VIN

1.5V

S5

S3

0.75V

TPS51916

U7300

(PAGE 59)

VCC

ISL95875

U7100

EN

(PAGE 57)

Q7850

Q7860

P5V_S0_EN

PP5V_S4_1V05BTS0

TBT_EN_LC_ISOL

PP3V3_S0_P1V5S0

P1V5_S0_EN

IN

MAX15053EWL

EN

U7760

(PAGE 63)

PP3V3_SUS_P1V05SUSLDO

EN

VOUT

CPUVCCIOS0_PGOOD

PGOOD

VOUT

VOUT

IMON

IMONG
PGOOD
PGOODG

VLDOIN

VOUT1

VOUT2

PGOOD

VOUT

PGOOD

P5V_S3_EN

VIN

ISL8014A

EN

U7720

(PAGE 63)

ISL8009B

EN

U7770

(PAGE 63)

PP1V8_S0_REG

IN

TPS720105

U7740

(PAGE 63)

PP3V42_G3H

R7640

SMC_CPU_ISENSE

A

SMC_CPU_ISENSE

A

CPUIMVP_IMON

CPUIMVP_IMONG

CPUIMVP_PGOOD
CPUIMVP_AXG_PGOOD

PP1V5R1V35_S3

PP0V75_S0_DDRVTT

TP_DDRREG_PGOOD

PPVCCSA_S0_REG

PVCCSA_PGOOD

PP5V_S0_FET

PP1V05_S0_P1V05BTREG_R

VIN

PP1V5_S0_REG

PP1V05_SUS_LDO

PP1V05_S0

A

SMC_CPU_FSB_ISENSE

V

PP5V_S3_FET

PP5V_S0_VMON

PP1V5_S3RS0_VMON

PP1V05_S0_VMON

SMC_CPU_VSENSE

V

PPVCORE_S0_CPUPPVCORE_S0_CPU

SMC_CPU_VSENSE

PPVCORE_S0_AXG

SMC_GFX_VSENSE

CPUIMVP_AXG_PWM2

SMC PWRGD

SN0903048

(PAGE 39)

VDD

MAX17491

PWN

U7542

(PAGE 61)

P1V5S0_PGOOD

P1V8S0_PGOOD
P5VS4_PGOOD

PVCCSA_PGOOD

CPUVCCIOS0_PGOOD

PP3V3_S0

VMON_Q2

VMON_Q3

VMON_Q4

U5010

PP5V_S0_CPUIMVP

2

U7960

ISL88042IRTEZ

(PAGE 67)

SMC_RESET_L

A

ALL_SYS_PWRGD

8

V

PPVCORE_S0_AXG

ALL_SYS_PWRGD

SMC_ONOFF_L

R7962

Panther-POINT

(PCH)

U1800

PM_PCH_PWROK

U7950

(PAGE 16~21)

CPU

U1000

SM_DRAMPWROK

UNCOREPWRGOOD

(PAGE 9~13)

SMC

PWRGD(P38)

S5_PWRGD

PM_SLP_S5_L

PM_SLP_S4_L

PM_SLP_S3_L

RSMRST_IN(P38)

PWR_BUTTON(P90)

SLP_S5_L(P38)

SLP_S4_L(P38)

SLP_S3_L(P38)

(PAGE 38)

SYNC_MASTER=K17_REF

PAGE TITLE

U4900

Power Block Diagram

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

PWRBTN#

SYS_RERST#

RSMRST#

PLTRST#

PROCPWRGD

DRAMPWROK

RESET*

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

SYSRST(PA2)

P17(BTN_OUT)

RES*

PM_PWRBTN_L

PM_SYSRST_L

PM_RSMRST_L

PLT_RERST_L

CPU_PWRGD

PM_MEM_PWRGD

PM_RSMRST_L

CPUIMVP_VR_ON

PM_SYSRST_L

PM_PWRBTN_L

SMC_RESET_L

SYNC_DATE=06/30/2009

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

3 OF 132

SHEET

3 OF 80

124578

SIZE

D

C

B

A

D

www.vinafix.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

Revision History

<BRANCH>

<SCH_NUM>

<E4LABEL>

4 OF 132

4 OF 80

www.vinafix.vn

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Bar Code Labels / EEE #’s

Alternate Parts

Module Parts

DDR3 SPD STRAPPINGS

Module Parts

D1 BOM GROUPS

BOM Variants

EEEE:F33G

[EEEE:F33G]

1

CRITICAL826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F2WR]

CRITICAL

1

826-4393

EEEE:F2WR

EEEE:F2WV

[EEEE:F2WV]

CRITICAL

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:F336

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

[EEEE:F336]

CRITICAL826-4393

EEEE:F33H

[EEEE:F33H]

1

826-4393

[EEEE:F33F]

CRITICAL

EEEE:F33F

1

[EEEE:F33D]

826-4393 CRITICAL

EEEE:F33D

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F16N]

826-4393 CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F16N

EEEE:F16P

[EEEE:F16P]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

EEEE:F16V

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEEE:F16V]

1

EEEE:DV7Q

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL826-4393

1

[EEEE:DV7Q]

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F26J

[EEEE:F26J]

826-4393

1

CRITICAL

[EEEE:F26M]

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393 CRITICAL

EEEE:F26M

1

[EEEE:F26L]

826-4393

EEEE:F26L

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F2WT

[EEEE:F2WT]

1

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:F26H

[EEEE:F26H]

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F337]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

EEEE:F337

[EEEE:F338]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

EEEE:F338

LBL,P/N LABEL,PCB,28MM X 6 MM

1

CRITICAL

EEEE:DWNW

826-4393

[EEEE:DWNW]

[EEEE:F16M]

1

826-4393 CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

EEEE:F16M

CRITICAL

EEEE:DWP0

1

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

[EEEE:DWP0]

EEEE:F2WQ

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

[EEEE:F2WQ]

[EEEE:F339]

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

EEEE:F339

1

EEEE:F33C

[EEEE:F33C]

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

ALL

128S0264128S0364

Kemet alt to Sanyo

Panasonic alt to Sanyo

128S0303

ALL

128S0353

ALL

128S0311 128S0329

NEC ALT TO SANYO

ALL

376S0953 376S0958

RENESAS ALT TO FAIRCHILD

353S3237

TI ALT TO INTERSIL

353S2192

ALL

ALL

138S0722 138S0691

Multi alt to Samsung

ALL

376S0977

Diodes alt to Toshiba

376S0859

197S0487

Epson alt to TXC

197S0485

ALL

NDK alt to TXC

ALL

197S0485197S0484

ALL

197S0478

NDK alt to TXC

197S0486

376S0612376S1017

ALL

ROHM alt to Toshiba

376S0604

ALL

376S1053

Diodes alt to Fairchild

ALL

138S0677138S0624

Murata alt to Taiyo Yuden

ALL

138S0681 138S0638

Taiyo Yuden alt to Samsung

152S1703

Sumida alt to Cyntec

ALL

152S1701

371S0490

ALL

Diodes alt to NXP

371S0730

138S0709138S0727

ALL

Samsung alt to Murata

376S0820376S1080

ALL

Diodes alt to ON Semi

372S0186 372S0185

ALL

NXP alt to Diodes

ALL

128S0296

NEC alt to Sanyo

128S0363

376S0796

ALL

376S0903

Fairchild alt to Siliconix

ALL

740S0118

Littlefuse alt to Polytronic

740S0144

Cyntec alt to Vishay

152S1645 152S0461

ALL

155S0583155S0667

ALL MAG LAYERS ALT TO MURATA

ALL

Yageo alt to Cyntec

112S0254112S0274

ALL

Diodes to AOS

376S1113 376S1110

ALL

murata ALT TO MURATA

155S0367155S0588

103S0266

Yageo alt to Cyntec

103S0305

ALL

152S1539

ALL

152S1598

Cyntec alt to Toko

138S0725 138S0724

ALL

Samsung alt to Murata

376S0612

ROHM alt to Toshiba

376S0972

ALL

ALL

197S0480

Epson alt to NDK

197S0481

Epson alt to TXC

ALL

197S0486197S0479

826-4393

1

[EEEE:DWP2]

EEEE:DWP2

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

1

CRITICAL

EEEE:DWNY

[EEEE:DWNY]

EEEE:F33N

CRITICAL826-4393

[EEEE:F33N]

1

[EEEE:F33J]

CRITICAL

1

826-4393

EEEE:F33J

D1_DEVEL:PVB

BOM Configuration

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

826-4393

EEEE:F33Q

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F33Q]

EEEE:F33P

826-4393 CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEEE:F33P]

EEEE:F33M

826-4393 CRITICAL

[EEEE:F33M]

[EEEE:F33L]

EEEE:F33L

CRITICAL

1

826-4393

EEEE:F33K

CRITICAL

1

[EEEE:F33K]

826-4393

1

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

826-4393

826-4393

085-4094

D1_COMMON

607-9189

CMN PTS,PCBA,MLB,D1

DEV BOM,MLB,D1

LBL,P/N LABEL,PCB,28MM X 6 MM

PCBA,2.6G,MICRON 8GB,MLB,D1

639-3887

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33K,RAM_4G_MICRON_1600_S

PCBA,2.8G,MICRON 8GB,MLB,D1

639-3888

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33F,RAM_4G_MICRON_1600_S

PCBA,2.9G,MICRON 8GB,MLB,D1

639-3847

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F2WQ,RAM_4G_MICRON_1600_S

PCBA,2.8G,MICRON 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F336,RAM_6G_MICRON_CH0_1600_S

639-3880

PCBA,2.5G,MICRON 8GB,MLB,D1

639-3846

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F2WV,RAM_4G_MICRON_1600_S

PCBA,2.6G,MICRON 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33M,RAM_6G_MICRON_CH0_1600_S

639-3879

PCBA,2.8G,ELPIDA 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F338,RAM_6G_ELPIDA_CH0_1600_S

639-3878

PCBA,2.6G,ELPIDA 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33J,RAM_4G_ELPIDA_1600_S

639-3885

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33N,RAM_4G_ELPIDA_1600_S

PCBA,2.8G,ELPIDA 8GB,MLB,D1

639-3886

639-3877

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33Q,RAM_6G_ELPIDA_CH0_1600_S

PCBA,2.6G,ELPIDA 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F337,RAM_4G_HYNIX_1600_S

PCBA,2.8G,HYNIX 8GB,MLB,D1

639-3884

639-3883

PCBA,2.6G,HYNIX 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33D,RAM_4G_HYNIX_1600_S

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33C,RAM_4G_SAMSUNG_35NM_1600_S

639-3882

PCBA,2.8G,SS 8GB,MLB,D1

639-3881

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33G,RAM_4G_SAMSUNG_35NM_1600_S

PCBA,2.6G,SS 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F339,RAM_6G_HYNIX_CH0_1600_S

639-3876

PCBA,2.8G,HYNIX 6GB,MLB,D1

639-3875

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33L,RAM_6G_HYNIX_CH0_1600_S

PCBA,2.6G,HYNIX 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.6G,PCH_C1,EEEE:F33H,RAM_6G_SAMSUNG_35NM_CH0_1600_S

639-3873

PCBA,2.6G,SS 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F2WR,RAM_6G_MICRON_CH0_1600_S

639-3848

PCBA,2.9G,MICRON 6GB,MLB,D1

639-3874

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.8G,PCH_C1,EEEE:F33P,RAM_6G_SAMSUNG_35NM_CH0_1600_S

PCBA,2.8G,SS 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F2WT,RAM_6G_MICRON_CH0_1600_S

639-3849

PCBA,2.5G,MICRON 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F26H,RAM_4G_ELPIDA_1600_S

639-3771

PCBA,2.9G,ELPIDA 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F26L,RAM_4G_ELPIDA_1600_S

639-3770

PCBA,2.5G,ELPIDA 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F26J,RAM_6G_ELPIDA_CH0_1600_S

639-3772

PCBA,2.9G,ELPIDA 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F16N,RAM_4G_HYNIX_1600_S

639-3696

PCBA,2.9G,HYNIX 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16V,RAM_4G_HYNIX_1600_S

639-3697

PCBA,2.5G,HYNIX 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F26M,RAM_6G_ELPIDA_CH0_1600_S

639-3773

PCBA,2.5G,ELPIDA 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:F16M,RAM_4G_SAMSUNG_35NM_1600_S

639-3695

PCBA,2.9G,SS 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:DWNW,RAM_6G_HYNIX_CH0_1600_S

639-3291

PCBA,2.9G,HYNIX 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:F16P,RAM_4G_SAMSUNG_35NM_1600_S

639-3694

PCBA,2.5G,SS 8GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:DWP0,RAM_6G_HYNIX_CH0_1600_S

639-3290

PCBA,2.5G,HYNIX 6GB,MLB,D1

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.9G,PCH_C1,EEEE:DWNY,RAM_6G_SAMSUNG_35NM_CH0_1600_S

PCBA,2.9G,SS 6GB,MLB,D1

639-3289

DEVEL_BOM,BASE_BOM,CPU_IVB_2C_2.5G,PCH_C1,EEEE:DWP2,RAM_6G_SAMSUNG_35NM_CH0_1600_S

PCBA,2.5G,SS 6GB,MLB,D1

639-3288

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

333S0660

16

CRITICAL

IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON

4G_MICRON_1600_S

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

8

CRITICAL333S0660

6G_MICRON_CH0_1600_S

IC,SDRAM,DDR3-1600,512MX8,78FBGA,MICRON

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

8

333S0649 CRITICAL

6G_MICRON_CH0_1600_S

IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON

333S0629

8

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

CRITICAL

6G_ELPIDA_CH0_1600_S

333S0625

8

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

6G_HYNIX_CH0_1600_S

CRITICAL

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

333S0628

8

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

6G_ELPIDA_CH0_1600_S

CRITICAL

333S0622

8

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

6G_HYNIX_CH0_1600_S

CRITICAL

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG

333S0624

16

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

CRITICAL

4G_SAMSUNG_35NM_1600_S

IC,SDRAM,DDR3-1600,512MX8,78FBGA,D35,SAMSUNG

333S0624

8

CRITICAL

6G_SAMSUNG_35NM_CH0_1600_S

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

333S0623

8

CRITICAL

6G_SAMSUNG_35NM_CH0_1600_S

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

333S0629

16

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

CRITICAL

4G_ELPIDA_1600_S

IC,SDRAM,DDR3-1600,512MX8,78FBGA,B-DIE,ELPIDA

IC,SDRAM,DDR3-1600,512MX8,78FBGA,HYNIX

333S0625

16

CRITICAL

4G_HYNIX_1600_S

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

16

CRITICAL333S0649

2G_MICRON_1600_S

IC,SDRAM,DDR3-1600,256MX8,78FBGA,MICRON

IC,SDRAM,DDR3-1600,256MX8,78FBGA,D-DIE,ELPIDA

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

2G_ELPIDA_1600_S

CRITICAL

16

333S0628

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

2G_SAMSUNG_35NM_1600_S

CRITICAL

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

16

333S0623

TBTRTR:B1

CRITICAL

IC,TBT,CR-4C,B1,PRQ,288FCBGA,12X12MM

1

U3600

338S1113

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

2G_HYNIX_1600_S

CRITICAL

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

16

333S0622

U1800

PCH_C1

IC,PCH,PPT-MB SFF,PRQ,C1

337S4283

1

CRITICAL

PCH_C0

U1800

1

CRITICAL337S4235

IC,PCH,PPT-MB SFF,P-QS,C0

IC,PCH,PPT-MB SFF,ES2,B0

PCH_ES2

U1800

337S4180 CRITICAL

1

IVB,S R0MU,PRQ,L1,2.9,35W,2+2,1.25,4M,BGA

CRITICAL

1

CPU_IVB_2C_2.9G

337S4265

U1000

U1000

IVB,S R0MY,PRQ,L1,2.6,35W,2+2,1.2,3M,BGA

CPU_IVB_2C_2.6G

1

CRITICAL337S4338

U1000

1

CPU_IVB_2C_2.8G

CRITICAL337S4339

IVB,S R0MU,PRQ,L1,2.8,35W,2+2,1.2,3M,BGA

CRITICAL

U1000

CPU_IVB_2C_2.5G

1

337S4264

IVB,S R0N0,PRQ,L1,2.5,35W,2+2,1.1,3M,BGA

CPU_IVB_2C_2.6G_QS

CRITICAL

IVB,QC96,QS,L1,2.6,35W,2+2,1.2,3M,BGA

U1000

1

337S4300

CPU_IVB_2C_2.8G_QS

IVB,QC94,QS,L1,2.8,35W,2+2,1.2,3M,BGA

CRITICAL

U1000

1

337S4302

CRITICAL

1

337S4294

IVB,QC4M,QS,L1,2.9,35W,2+2,1.25,4M,BGA

CPU_IVB_2C_2.9G_QS

U1000

CRITICAL

U1000

1

337S4292

CPU_IVB_2C_2.5G_QS

IVB,Q4CT,QS,L1,2.5,35W,2+2,1.1,3M,BGA

U1000

CPU_IVB_2C_2.3G_ES2

337S4181

1

CRITICAL

IVB,QBP0,ES2,K0,2.3,35W,2+2,1.0,3M,BGA

CPU_IVB_2C_2.6G_ES2

337S4182

U1000

1

CRITICAL

IVB,QBP0,ES2,K0,2.6,35W,2+2,1.05,4M,BGA

IC,SDRAM,2GBIT,256MX8,DDR3-1600,78FBGA

6G_SAMSUNG_28NM_CH0_1600_S

CRITICAL

8

333S0623

U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

6G_SAMSUNG_28NM_CH0_1600_S

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970

CRITICAL

8

333S0642

IC,SDRAM,DDR3-1600,512MX8,78FBGA,C-DIE,SAMSUNG

U2900,U2910,U2920,U2930,U2940,U2950,U2960,U2970,U3100,U3110,U3120,U3130,U3140,U3150,U3160,U3170

4G_SAMSUNG_28NM_1600_S

CRITICAL

16

333S0642

2G_HYNIX_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM_2G_HYNIX_1600_S

2G_SAMSUNG_35NM_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_2G_SAMSUNG_1600_S

6G_HYNIX_CH0_1600_S,RAMCFG3:H,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_6G_HYNIX_CH0_1600_S

6G_SAMSUNG_28NM_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_6G_SAMSUNG_28NM_CH0_1600_S

6G_ELPIDA_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_6G_ELPIDA_CH0_1600_S

6G_MICRON_CH0_1600_S,RAMCFG3:H,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_6G_MICRON_CH0_1600_S

4G_MICRON_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

RAM_4G_MICRON_1600_S

6G_SAMSUNG_35NM_CH0_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:H,RAMCFG0:L

RAM_6G_SAMSUNG_35NM_CH0_1600_S

4G_SAMSUNG_35NM_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:H

RAM_4G_SAMSUNG_35NM_1600_S

4G_SAMSUNG_28NM_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:L

RAM_4G_SAMSUNG_28NM_1600_S

2G_MICRON_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:H,RAMCFG0:H

RAM_2G_MICRON_1600_S

4G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:H,RAMCFG1:L,RAMCFG0:L

RAM_4G_ELPIDA_1600_S

2G_ELPIDA_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:H

RAM_2G_ELPIDA_1600_S

4G_HYNIX_1600_S,RAMCFG3:L,RAMCFG2:L,RAMCFG1:L,RAMCFG0:L

RAM_4G_HYNIX_1600_S

D1_DEVEL:PVB

ALTERNATE,IVB_PPT_XDP,VREFDQ:M1_M3,VREFCA:LDO

IVB_PPT_XDP

XDP,XDP_CONN,XDP_CPU:BPM,XDP_PCH

D1_DEVEL:ENG

ALTERNATE,IVB_PPT_XDP,LOADISNS:YES,S0PGOOD_ISL,DDRVREF_DAC,VREFDQ:M1_M3,VREFCA:LDO_DAC

D1_BLANK

D1_PROGPARTS

SMC_PROG:PVB,TBTROM:PROG,BOOTROM_PROG:PVB,TPAD_PSOC:PROG

D1_PVB

LOADISNS:NO,LCDBKLT:PROD,KBDBKLT:PROD

D1_COMMON2

EDP:YES,PPDDR:1V35,LPCPLUS_CONN:YES,LPCPLUS_R:YES,CAPS:INT,BTPWR:S4,SKIP_5V3V3:AUDIBLE,TPAD_5V_LDO:S5,SMS

D1_COMMON

ALTERNATE,COMMON,D1_COMMON1,D1_COMMON2,D1_PROGPARTS,D1_PVB

D1_COMMON1

CPUMEM:S0,SMC_DEBUG_YES,TBTBST:Y,TBTRTR:B1,TBTHV:P15V,HUB_2NONREM,USBHUB:2512B,AXG_PHASE2,TBTISNS:YES

<BRANCH>

<SCH_NUM>

<E4LABEL>

5 OF 132

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

PD Module Parts

DEVELOPMENT/BASE BOMs

EFI ROM

SMC

Programmables - All builds

946-4350

D1 MLB LOCTITE UV GLUE 190024/S 0.24G

STDOFF-1.9D2.93H-TH-0.85-1.2

STDOFF-1.80D1.53H-SM

LBL,PART CONFIG,BOARDS,D2

EDGE_BOND

1

CRITICAL

CRITICAL

1

825-7841 CONFIG_LABEL

IC,TP PSOC,V224,PVB,D1

341S3670

IC,EFI,ROM,FSB2, D1

IC,EFI,ROM,PVB, D1

64 MBIT SPI SERIAL DUAL I/O FLASH,Macronix

IC,TP PSOC,QFN,BLANK

IC,EEPROM,SERIAL,8KB,SOIC

IC,SMC12-A3,LX4FS1AH5BBCIGA3

341S3528

J6950_65860-1529

1

CRITICAL

J6950_64860-1530 CRITICAL

1

J6950_63860-1533

STDOFF,BMU,TOPSIDE,D1,SM

CRITICAL

1

341S3668

IC,EEPROM,CR,V14.1,D1 PVB

341S3406

IC,SMC,DEVELOPMENT-PVB,D1

SMC_PROG:PVB

341S3667

BOOTROM_PROG:PVB

1

BASE BASE_BOMCRITICAL

D1 MLB BASE BOM

607-9189

DEVEL

1

CRITICAL

DEVEL_BOM

D1 MLB DEVELOPMENT BOM

085-4094

SYNC_DATE=MASTER

BOM Configuration

SYNC_MASTER=MASTER

1

U4900

CRITICAL

IC,SMC,DEVELOPMENT-FSB,D1

SMC_PROG:FSB

341S3405

U6100

335S0809

BOOTROM_BLANK

1

CRITICAL

64 MBIT SPI SERIAL DUAL I/O FLASH,Numonyx

335S0803

1

U6100

BOOTROM_BLANK

CRITICAL

CRITICAL

TPAD_PSOC:PROG

U5701

1

337S2983

TPAD_PSOC:BLANK

CRITICAL

U5701

1

TBTROM:PROG

CRITICAL

U3690

1

U3690

TBTROM:BLANK

1

335S0865 CRITICAL

SMC_BLANK

U4900

CRITICAL

1

338S1098

SMC_SOCKET

1

998-3919 CRITICAL

SOCKET, SMC12

J4900

341S3650

IC,EFI,ROM,FSB, D1

BOOTROM_PROG:FSB

U6100

CRITICAL

1

BOOTROM_PROG:PIB2

IC,EFI,ROM,PIB2, D1

341S3636

U6100

CRITICAL

1

BOOTROM_PROG:FSB2

341SXXXX

1

CRITICAL

U6100

1

CRITICAL

U6100

BOOTROM_PROG:PIB

CRITICAL

U6100

IC,EFI,ROM,PIB, D1

341S3603

1

BOOTROM_PROG:PROTO

341S3571

IC,EF,ROM,PROTO1,D1

1

U6100

CRITICAL

1

U4900

CRITICAL

341S3404

IC,SMC,DEVELOPMENT-PIB,D1

U4900

CRITICAL

1

SMC_PROG:PIB

CRITICAL

1

U4900

SMC_PROG:PROTO

IC,SMC12,PROTO1,D1

<BRANCH>

<SCH_NUM>

<E4LABEL>

6 OF 132

6 OF 80

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PP
PP
PP
PP

PP
PP
PP
PP
PP
PP
PP
PP
PP
PP

PP

PP

PP

PP

PP

PP

PP

PP
PP

PP
PP

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH ALIASES

Functional Test Points

J6801 (2 MIC CONN)

J6701 (AUDIO JACK CONN)

NO_TEST

NC NO_TESTs

S2 CAMERA PCIE SIGNALS

J4410 (RIO FLEX CONN)

J6950 (MAIN BATT CONN)

per Fan

U1000 CHARZ TPS

U4900 CHARZ TPS

J5713 (KEY BOARD CONN)

J3502 (ALS/CAMERA CONN)

J5815 (KBD BACKLIGHT CONN)

J5650 (LEFT FAN CONN)

per Fan

U1800 CHARZ TPS

J5660 (RIGHT FAN CONN)

5 TPs

J4400 (RIO CABLE CONN)

J9000 (EDP CONN)

J3401 & J3402 (AIRPORT/BT/CAMERA CONN)

2 TP needed

J6802 (AUDIO LEFT SPEAKER CONN)

J6803 (AUDIO RIGHT SPEAKER CONN)

3 TPs

6 TPs

J5100 (LPC + SPI CONN)

FUNC_TEST

4 TPs

J6900 (DC POWER CONN)

J5700 (IPD FLEX CONN)

FUNC_TEST

FUNC_TEST

J4600 (LEFT USB CONN)

ICT Test Points

POWER RAILS

FUNC_TEST

J4500 (SSD/HDD FLEX CONN)

CPU NO_TESTs

I1493

I1502

I1503

I1504

I1511

I1512

I1513

I1514

I1515

I1516

I1517

I1518

I1519

I1520

I1522

I1523

I1524

I1525

I1526

I1527

I1528

I1529

I1531

I1533

I1534

I1535

I1536

I1538

I1540

I1541

I1542

I1543

I1544

I1545

I1547

I1566

I1567

I1569

I1571

I1584

I1585

I1586

I1601

I1602

I1603

I1604

I1605

I1606

I1607

I1608

I1609

I1610

I1611

I1612

I1613

I1614

I1615

I1616

I1617

I1618

I1619

I1620

I1621

I1622

I1623

I1624

I1625

I1626

I1627

I1628

I1629

I1630

I1631

I1632

I1633

I1634

I1635

I1636

I1637

I1638

I1639

I1640

I1644

I1646

I1647

I1648

I1649

I1651

I1652

I1653

I1654

I1655

I1656

I1657

I1658

I1659

I1660

I1661

I1662

I1663

I1664

I1668

I1669

I1670

I1671

I1672

I1673

I1674

I1675

I1676

I1677

I1678

I1679

I1680

I1681

I1682

I1683

I1684

I1685

I1709

I1710

I1711

I1712

I1713

I1714

I1715

I1716

I1717

I1718

I1719

I1720

I1721

I1722

I1723

I1724

I1725

I1726

I1731

I1806

I1808

I1809

I1811

I1812

I1814

I1815

I1817

I1818

I1820

I1821

I1822

I1823

I1824

I1825

I1826

I1827

I1828

I1829

I1830

I1831

I1834

I1835

I1836

I1837

I1838

I1839

I1840

I1841

I1842

I1843

I1844

I1845

I1846

I1847

I1848

I1849

I1850

I1851

I1852

I1853

I1854

I1855

I1856

I1857

I1858

I1859

I1860

I1861

I1862

I1863

I1864

I1865

I1866

I1867

I1868

I1869

I1870

I1871

I1872

I1873

I1874

I1875

I1876

I1877

I1878

I1879

I1880

I1881

I1884

I1885

I1886

I1887

I1888

I1889

I1892

I1893

I1894

I1895

I1896

I1897

I1899

I1901

I1902

I1903

I1904

I1905

I1906

I1909

I1910

I1911

I1912

I1913

I1914

I1915

I1916

I1917

P2MM

SM

I1919

I1920

I1921

I1922

I1923

I1924

I1925

I1926

I1927

I1928

I1929

I1930

I1931

I1932

SM

P2MM
P2MM

SM
SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM
P2MM

SM
SM

P2MM
P2MM

SM
SM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

P2MM

SM

P2MM

SM

P2MM

SM

P2MM

SM

SM

P2MM

I1954

I1955

I1956

I1957

I1958

I1959

I1960

I1961

I1962

I1963

I1964

I1965

I1966

I1967

I1968

I1969

I1970

I1971

I1972

P2MM

SM

I1974

I1975

I1976

P2MM

SM
SM

P2MM

I1979

I1980

SM

P2MM
P2MM

SM

I1983

I1984

I1985

I1986

I1987

I1988

I1989

I1990

Functional / ICT Test

SYNC_DATE=MASTERSYNC_MASTER=MASTER

GND

TRUE

GND

TRUE

TRUE

GND

TRUE

GND

GND

TRUE

GND

TRUE

GND

TRUE

TRUE

SYS_DETECT_L_R

PCIE_CLK100M_TBT_N

DMI_S2N_P<0>

AUD_SPDIF_OUT_JACK

TRUE

TRUE

PCH_VSS_NCTF<19>

TP_SDVO_INTP

TP_PCI_PME_L

TRUE

NC_ISNS_WLANN

MAKE_BASE=TRUE

TRUE

NC_ISNS_WLANP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_ISNS_LCD_PANELN

NC_PCI_PME_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_ISNS_LCDBKLTP

TRUE

TP_PCI_CLK33M_OUT3

NC_ISNS_LCDBKLTN

MAKE_BASE=TRUE

TRUE

TP_SDVO_INTN

TP_SDVO_STALLP

TP_SDVO_STALLN

TP_SDVO_TVCLKINP

TP_SDVO_TVCLKINN

TP_HDA_SDIN3

TP_CRT_IG_VSYNC

TP_CRT_IG_RED

LED_RETURN_3

TRUE

PP3V3_S5

TRUE

TP_SMS_INT2

TRUE

MEM_A_DQ<24..21>

TP_LPC_DREQ1_L

NC_SDVO_STALLN

MAKE_BASE=TRUE

TRUE

TP_HDA_SDIN1

TP_SATA_D_R2D_CP

TP_SATA_C_R2D_CN

TP_SATA_C_D2RN

TP_TBT_PCIE_RESET0_L

TRUE

PP1V05_S0

TRUE

WS_KBD3

TRUE

WS_KBD12

TRUE

MAKE_BASE=TRUE

NC_ISNS_LCD_PANELP

TRUE

MAKE_BASE=TRUE

NC_PCIE_5_D2RN

TRUE

MAKE_BASE=TRUE

NC_PCIE_5_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_5_R2D_CN

TRUE

MAKE_BASE=TRUE

NC_PCIE_5_R2D_CP

TRUE

MAKE_BASE=TRUE

NC_PCIE_6_D2RP

TRUE

MAKE_BASE=TRUE

NC_PCIE_6_D2RN

Z2_SCLK

TRUE

TP_PCH_TP23

NC_PCI_CLK33M_OUT3

TRUE
MAKE_BASE=TRUE

NC_SDVO_INTP

TRUE
MAKE_BASE=TRUE

NC_SDVO_INTN

MAKE_BASE=TRUE

TRUE

NC_SDVO_STALLP

TRUE
MAKE_BASE=TRUE

NC_SDVO_TVCLKINP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_SDVO_TVCLKINN

TRUE

NC_HDA_SDIN3

MAKE_BASE=TRUE

TP_HDA_SDIN2 NC_HDA_SDIN2

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_HDA_SDIN1

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

TRUE

TP_CRT_IG_HSYNC

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_HSYNC

TP_CRT_IG_DDC_DATA

TRUE

NC_CRT_IG_DDC_DATA

MAKE_BASE=TRUE

TP_CRT_IG_DDC_CLK NC_CRT_IG_DDC_CLK

TRUE
MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_CRT_IG_RED

TP_CRT_IG_GREEN NC_CRT_IG_GREEN

MAKE_BASE=TRUE

TRUE

TP_SATA_F_R2D_CP NC_SATA_F_R2D_CP

MAKE_BASE=TRUE

TRUE

TP_SATA_F_R2D_CN NC_SATA_F_R2D_CN

MAKE_BASE=TRUE

TRUE

TP_SATA_F_D2RP NC_SATA_F_D2RP

MAKE_BASE=TRUE

TRUE

TP_CRT_IG_BLUE NC_CRT_IG_BLUE

MAKE_BASE=TRUE

TRUE

TP_SATA_E_R2D_CN NC_SATA_E_R2D_CN

MAKE_BASE=TRUE

TRUE

TP_SATA_E_R2D_CP NC_SATA_E_R2D_CP

MAKE_BASE=TRUE

TRUE

TP_SATA_F_D2RN NC_SATA_F_D2RN

MAKE_BASE=TRUE

TRUE

TP_SATA_E_D2RP NC_SATA_E_D2RP

MAKE_BASE=TRUE

TRUE

TP_SATA_E_D2RN NC_SATA_E_D2RN

MAKE_BASE=TRUE

TRUE

TP_SATA_D_D2RP NC_SATA_D_D2RP

MAKE_BASE=TRUE

TRUE

TP_SATA_D_D2RN NC_SATA_D_D2RN

MAKE_BASE=TRUE

TRUE

TP_SATA_C_R2D_CP NC_SATA_C_R2D_CP

MAKE_BASE=TRUE

TRUE

TP_SATA_D_R2D_CN NC_SATA_D_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_SATA_D_R2D_CP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_C_D2RN

TRUE

TP_SATA_C_D2RP NC_SATA_C_D2RP

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_C_R2D_CN

TRUE

TP_PCIE_CLK100M_PEBP NC_PCIE_CLK100M_PEBP

TRUE
MAKE_BASE=TRUE

NC_PCIE_8_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_8_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_R2D_CN

MAKE_BASE=TRUE

TRUE

TP_PCIE_CLK100M_PEBN NC_PCIE_CLK100M_PEBN

MAKE_BASE=TRUE

TRUE

TP_PCIE_CLK100M_PE4P NC_PCIE_CLK100M_PE4P

TRUE
MAKE_BASE=TRUE

TP_PCIE_CLK100M_PE4N NC_PCIE_CLK100M_PE4N

TRUE
MAKE_BASE=TRUE

NC_PCIE_7_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_7_D2RP

MAKE_BASE=TRUE

TRUE

NC_PCIE_6_R2D_CP

MAKE_BASE=TRUE

TRUE

NC_PCIE_6_R2D_CN

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_CAMERAP

PCIE_CLK100M_EXCARD_P

NC_PCIE_CAMERA_R2D_CP

MAKE_BASE=TRUE TRUE

PCIE_EXCARD_R2D_C_P

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_CAMERAN

PCIE_CLK100M_EXCARD_N

NC_PCIE_CAMERA_R2D_CN

MAKE_BASE=TRUE TRUE

PCIE_EXCARD_R2D_C_N

NC_PCIE_CAMERA_D2RN

MAKE_BASE=TRUE

TRUE

PCIE_EXCARD_D2R_P

NC_PCIE_CAMERA_D2RP

MAKE_BASE=TRUE

TRUE

PCIE_EXCARD_D2R_N

DMI_S2N_N<0>

WS_KBD11

TRUE

TRUE

WS_KBD16_NUM

FAN_RT_TACH

TRUE

TRUE

PM_SLP_S4_L

TRUE

AP_RESET_CONN_L

SMBUS_SMC_1_S0_SCL

TRUE

DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

PCIE_TBT_D2R_P<0>
PCIE_TBT_D2R_N<0>

DMI_N2S_N<0>

PCIE_ENET_D2R_P

LPC_AD<0>

TRUE

WS_KBD14

WS_KBD9

TRUE

WS_KBD7

TRUE

WS_KBD5

TRUE

TRUE

PP3V42_G3H

TRUE

PP5V_S4

TRUE

PP3V3_S4

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

PP1V5_S0

TRUE

HDMI_IG_DDC_DATA

SD_PWR_EN

TRUE

PCIE_CLK100M_TBT_P

LPC_AD<1>

FDI_DATA_P<4>

FDI_DATA_N<4>
PCIE_AP_D2R_P
PCIE_AP_D2R_N

PPVBAT_G3H_CONN

TRUE

PP5V_S0

TRUE

TRUE

ENET_CLKREQ_L

TRUE

TRUE

SMBUS_SMC_1_S0_SDA

TRUE

KBDLED_CATHODE2

PCIE_ENET_D2R_N

DMI_N2S_P<0>

FDI_DATA_N<0>

SYSDET1

TRUE

AUD_DMIC_SDA1

LPC_CLK33M_SMC

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

AUD_SPDIF_IN

TP_AUD_MIC_INRP

TP_DP_TBTSRC_ML_CP<3>
TP_DP_TBTSRC_ML_CN<3>

PCIE_CLK100M_EXCARD_N

TP_XDP_PCH_OBSFN_A<0>

TP_AUD_CODEC_MICBIAS

TP_CLINK_CLK

TP_DP_TBTSRC_ML_CP<0>

TP_DP_TBTSRC_ML_CP<1>

TP_SPI_CS1_L
TP_PCH_GPIO8
TP_PCH_STRP_BBS1

TP_PCI_CLK33M_OUT2

TP_PCIE_CLK100M_PEGAP

TP_PCIE_CLK100M_PEGAN

TP_PCH_STRP_ESI_L

TP_PM_SLP_A_L

TP_SMC_MPM5_LED_CHG

TP_PPVOUT_PCH_DCPSUSBYP
TP_SMC_MPM5_LED_PWR

TP_DP_TBTSRC_ML_CN<1>

TP_DP_TBTSRC_ML_CN<2>

TP_TBT_PCIE_RESET3_L

TP_TBT_PCIE_RESET2_L

TP_TBT_MONDC1

TP_XDP_PCH_HOOK5
TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>

TP_XDP_PCH_OBSFN_D<0>

TP_XDP_PCH_OBSFN_A<1>

TP_XDP_PCH_TRST_L

TP_XDP_PCH_OBSFN_D<1>

TP_1V05_S0_PCH_VCCAPLLEXP

TP_AUD_MIC_INRN

TP_BKL_FAULT

TP_LPC_DREQ0_L

TP_CLINK_RESET_L

TP_XDP_PCH_HOOK4

TP_DP_TBTSRC_AUXCH_CN

TP_DP_TBTSRC_AUXCH_CP

TP_CLINK_DATA

TP_DP_TBTSRC_ML_CN<0>

TP_TBT_XTAL25OUT

TP_TBT_MONDC0

TP_DP_TBTSRC_ML_CP<2>

TP_TBT_PCIE_RESET1_L

FDI_DATA_P<0>

PP0V75_S0_DDRVTT

TRUE

TRUE

PP5V_S0_HDD_FLT

TRUE

SMC_OOB1_RX_L

TRUE

SMC_OOB1_TX_L

TRUE

PP3V3_S0_SSD_FLT

TRUE

PP3V3_WLAN_F

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_D2R_P

TRUE

PP5V_S3

DMI_N2S_P<3..1>

TRUE

TBTAPWRSW_ISET_S0

TRUE

TBT_A_R2D_P<1..0>

TRUE

TRUE

TBT_A_D2R_N<0>

TBT_B_D2R_P<0>

TRUE

TRUE

PCIE_AP_R2D_N

TRUE

PCIE_AP_R2D_P

TRUE
MAKE_BASE=TRUE

NC_TBT_MONDC0

NC_DP_TBTSRC_AUXCH_CP

MAKE_BASE=TRUE

TRUE

SMC_ONOFF_L

TRUE

TRUE

CON_DMIC_CLK

USB_LT1_P

TRUE

USB_LT1_N

TRUE

TRUE

SMC_KBDLED_PRESENT_L

TRUE

SYSDET_3_4

TRUE

CON_DMIC_PWR

TRUE

CON_DMIC_SDA1

TRUE

SMBUS_SMC_5_G3_SDA

TRUE

SMBUS_SMC_5_G3_SCL

TRUE

PP5V_S3_LTUSB_A_F

TRUE

PCH_VSS_NCTF<19>

TRUE

WS_KBD10

TRUE

WS_KBD15_CAP

TRUE

PCIE_TBT_D2R_P<3..1>

NC_XDP_PCH_HOOK4

MAKE_BASE=TRUE

TRUE

TRUE

USB_EXTB_N

TRUE

PP3V3_S3

TRUE

SMBUS_SMC_2_S3_SDA

WS_KBD4

TRUE

WS_KBD13

TRUE

PM_SLP_S3_L

TRUE

NC_PCH_GPIO8

TRUE

MAKE_BASE=TRUE

TRUE
MAKE_BASE=TRUE

NC_SPI_CS1_L

TRUE

PSOC_MOSI

TRUE

MEM_A_DQ<63..58>

TRUE

TBT_A_D2R_P<1>

TBT_A_D2R_P<0>

TRUE

TRUE

DMI_S2N_N<3..1>

DMI_S2N_P<3..1>

TRUE

TRUE

PCIE_TBT_D2R_N<3..1>

PP5V_S5

TRUE

PPBUS_G3H

TRUE

PPDCIN_G3H

TRUE

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD23

TRUE

WS_KBD22

TRUE

WS_KBD21

TRUE

WS_KBD20

TRUE

SMC_TCK

TRUE

HDMI_IG_DATA_C_N<2..0>

TRUE

HDMI_IG_DATA_C_P<2..0>

TRUE

HDMI_IG_CLK_C_P

TRUE

HDMI_IG_CLK_C_N

TRUE

TRUE

SPIROM_USE_MLB

TRUE

MEM_A_DQ<42..34>

TRUE

SDCONN_STATE_CHANGE_SMC

LPC_AD<3>

TRUE

TRUE

NC_MEM_EVENT_L

TRUE

MEM_B_DQ<63..59>

TRUE

MEM_B_DQ<35..27>
MEM_B_DQ<40..37>

TRUE
TRUE

MEM_B_DQ<47..42>

TRUE

MEM_B_DQ<57..49>

TRUE

MEM_B_DQ<25..21>

TRUE

MEM_B_DQ<2..0>

TRUE

MEM_B_DQ<13..4>

TRUE

MEM_B_DQ<19..15>

MEM_A_DQ<54..44>

TRUE

MEM_A_DQ<56>

TRUE

TRUE

MEM_A_DQ<32..26>

TRUE

MEM_A_DQ<19..14>

TRUE

MEM_A_DQ<12..2>

MEM_A_DQ<0>

TRUE

PCIE_TBT_D2R_C_N<3..1>

TRUE

TRUE

PCIE_TBT_D2R_C_P<3..1>

TRUE

TBT_B_D2R_N<0>

TBT_B_D2R_N<1>

TRUE

TRUE

TBT_B_D2R_P<1>

TBT_B_D2R_C_N<1>

TRUE

TBT_B_R2D_N<1..0>

TRUE

TRUE

TBT_B_D2R_C_N<0>
TBT_B_D2R_C_P<1>

TRUE

TRUE

TBT_B_R2D_P<1..0>

TRUE

TBT_B_R2D_C_N<1..0>

TRUE

TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>

TRUE

TRUE

TBT_A_D2R_N<1>

TRUE

TBT_A_D2R_C_N<1>

TRUE

TBT_A_D2R_C_P<1>

TBT_A_R2D_N<1..0>

TRUE

TBT_A_R2D_C_N<1..0>

TRUE

TRUE

TBT_A_R2D_C_P<1..0>

NC_LPC_DREQ0_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_BKL_FAULT

TRUE

TRUE

AUD_SPDIF_IN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TRUE

NC_AUD_MIC_INRP

MAKE_BASE=TRUE

TRUE

NC_AUD_CODEC_MICBIAS

TRUE
MAKE_BASE=TRUE

NC_1V05_S0_PCH_VCCAPLLEXP

NC_XDP_PCH_OBSFN_D<1>

TRUE
MAKE_BASE=TRUE
TRUE

NC_XDP_PCH_TRST_L

MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_A<1>

MAKE_BASE=TRUE

TRUE

NC_XDP_PCH_OBSFN_D<0>

TRUE
MAKE_BASE=TRUE

NC_XDP_PCH_OBSFN_A<0>

MAKE_BASE=TRUE

TRUE

NC_XDP_PCH_OBSFN_B<1>

MAKE_BASE=TRUE

TRUE

NC_XDP_PCH_OBSFN_B<0>

TRUE
MAKE_BASE=TRUE

TRUE

NC_XDP_PCH_HOOK5

MAKE_BASE=TRUE

DMI_N2S_N<3..1>

TRUE

PP5V_S3_ALSCAMERA_F

TRUE

PM_SYSRST_L

TRUE

LPC_AD<2>

TRUE

LPCPLUS_GPIO

TRUE

LPC_FRAME_L

TRUE

SMBUS_SMC_2_S3_SDA

TRUE

AP_RESET_CONN_L

TRUE

SMC_TDO

TRUE

TP_SMC_TRST_L

TRUE
TRUE

TP_SMC_MD1

TRUE

SPI_ALT_MISO

PM_CLKRUN_L

TRUE

TRUE

KBDLED_CATHODE1

TRUE

SMBUS_PCH_DATA

SPI_ALT_CS_L

TRUE

SPI_ALT_MOSI

TRUE

LPCPLUS_RESET_L

TRUE

PCIE_WAKE_L

TRUE

TRUE

HDMI_IG_DDC_CLK

Z2_KEY_ACT_L

TRUE

TRUE

Z2_MOSI

TRUE

Z2_HOST_INTN
PP5V_S4_CUMULUS

TRUE

TBTAPWRSW_ISET_V3P3

TRUE

TBTBPWRSW_ISET_S3

TRUE

TBTBPWRSW_ISET_S0_R

TRUE

TRUE

TBTBPWRSW_ISET_V3P3

TDM_ONEWIRE_MPM

TRUE

PSOC_SCLK

TRUE

TRUE

WS_KBD8

PICKB_L

TRUE

PSOC_F_CS_L

TRUE

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<3>

TRUE
MAKE_BASE=TRUE

NC_DP_TBTSRC_ML_CP<1>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<2>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CP<0>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<1>

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CN<0>

NC_DP_TBTSRC_AUXCH_CN

MAKE_BASE=TRUE

TRUE

NC_PPVOUT_PCH_DCPSUSBYP

TRUE
MAKE_BASE=TRUE

NC_PM_SLP_A_L

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_STRP_ESI_L

TRUE
MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEGAN

TRUE
MAKE_BASE=TRUE

NC_PCIE_CLK100M_PEGAP

NC_PCH_STRP_BBS1

MAKE_BASE=TRUE

TRUE

PP3V3_S3

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

TRUE

LED_RETURN_5

TRUE

Z2_CS_L

MAKE_BASE=TRUE

TRUE

NC_TBT_XTAL25OUT

MAKE_BASE=TRUE

TRUE

NC_TBT_PCIE_RESET3_L

MAKE_BASE=TRUE

NC_TBT_PCIE_RESET2_L

TRUE

MAKE_BASE=TRUE

TRUE

NC_TBT_PCIE_RESET1_L

MAKE_BASE=TRUE

TRUE

NC_TBT_PCIE_RESET0_L

MAKE_BASE=TRUE

TRUE

NC_TBT_MONDC1

LED_RETURN_6

TRUE

PP3V3_S0

TRUE

TRUE

PCIE_CLK100M_AP_CONN_N

PP3V42_G3H

TRUE

PPVTTDDR_S3

TRUE

TRUE

PP5V_S0

NC_LPC_DREQ1_L

MAKE_BASE=TRUE TRUE

WS_KBD1

TRUE

WS_LEFT_SHIFT_KBD

TRUE

TRUE

MAKE_BASE=TRUE

NC_CLINK_RESET_L

TRUE

MAKE_BASE=TRUE

NC_CLINK_DATA

TRUE
MAKE_BASE=TRUE

NC_CLINK_CLK

WS_KBD2

TRUE

WS_LEFT_OPTION_KBD

TRUE

TRUE

PCIE_CLK100M_AP_CONN_P

AP_CLKREQ_Q_L

TRUE

TRUE

PP3V3_WLAN_F

USB_CAMERA_CONN_N

TRUE

LPC_CLK33M_LPCPLUS

TRUE

LPC_AD<0>

TRUE

LPC_AD<1>

TRUE

SMC_TX_L

TRUE

SPI_ALT_CLK

TRUE

TRUE

LPC_SERIRQ

SMC_TDI

TRUE

LPC_PWRDWN_L

TRUE

SMC_RESET_L

TRUE
TRUE

SMC_ROMBOOT
SMC_RX_L

TRUE

SMC_TMS

TRUE

ADAPTER_SENSE

TRUE

TRUE

LED_RETURN_2

LED_RETURN_4

TRUE

PPVCORE_S0_CPU

TRUE

TBTAPWRSW_ISET_S3_R

TRUE

TRUE

TBT_B_D2R_C_P<0>

TRUE

PCIE_ENET_R2D_C_N

TRUE

PCIE_ENET_R2D_C_P

TRUE

PCIE_AP_R2D_C_P

TRUE

PCIE_AP_R2D_C_N

TRUE

PCIE_AP_D2R_N

TRUE

PCIE_AP_D2R_P

TRUE

PCIE_AP_D2R_PI_P

TRUE

PCIE_AP_D2R_PI_N

TRUE

PCIE_AP_R2D_PI_P

TRUE

PCIE_AP_R2D_PI_N

TRUE

PCIE_CLK100M_PCH_N

TRUE

PCIE_CLK100M_PCH_P

TRUE

PCIE_CLK100M_TBT_N

TRUE

PCIE_CLK100M_TBT_P

TRUE

PCH_CLK100M_SATA_P

TRUE

PCH_CLK33M_PCIIN

TRUE

PCIE_CLK100M_SSD_P

TRUE

PEG_CLK100M_P

TRUE

PEG_CLK100M_N

TRUE

PCIE_CLK100M_ENET_N

TRUE

PCIE_CLK100M_ENET_P

TRUE

PCIE_CLK100M_AP_N

TRUE

PCIE_CLK100M_AP_P

TRUE

PCIE_CLK100M_FW_P

TRUE

PCIE_CLK100M_EXCARD_P

TRUE

PCIE_CLK100M_FW_N

TRUE

SATA_HDD_D2R_RDROUT_P

SATA_HDD_R2D_RDRIN_N

TRUE

SATA_HDD_D2R_RDROUT_N

TRUE

TRUE

SATA_HDD_D2R_RDRIN_N

SATA_HDD_D2R_RDRIN_P

TRUE

SATA_HDD_R2D_RDROUT_N

TRUE
TRUE

SATA_HDD_R2D_RDROUT_P

TRUE

SATA_HDD_D2R_RC_N

TRUE

SATA_HDD_R2D_RC_N

SATA_HDD_R2D_C_P

TRUE

SATA_HDD_D2R_N

TRUE

PP18V5_DCIN_FUSE

TRUE

BKLT_EN

TRUE

TRUE

LCD_BKLT_PWM

TRUE

PM_CLKRUN_L

TRUE

PP3V3_S4

WS_CONTROL_KBD

TRUE

TRUE

PCIE_TBT_R2D_N<3..0>

PCIE_TBT_R2D_P<3..0>

TRUE

PCIE_TBT_R2D_C_N<3..0>

TRUE

PCIE_TBT_R2D_C_P<3..0>

TRUE

MAKE_BASE=TRUE

NC_SMS_INT2

TRUE

MAKE_BASE=TRUE

NC_SMC_MPM5_LED_CHG

TRUE

MAKE_BASE=TRUE

NC_AUD_MIC_INRN

TRUE

NC_SMC_MPM5_LED_PWR

TRUE
MAKE_BASE=TRUE

SATA_SSDRHDD_D2R_P

TRUE

SATA_SSDRHDD_R2D_P

TRUE

SATA_SSDRHDD_R2D_N

TRUE

USB_CAMERA_CONN_P

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

TRUE

WS_KBD6

TRUE

TBT_B_R2D_C_P<1..0>

TRUE

SATA_HDD_D2R_RC_P

SATA_HDD_R2D_RDRIN_P

TRUE

TRUE

SATA_HDD_D2R_P

NC_DP_TBTSRC_ML_CP<2>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_DP_TBTSRC_ML_CP<3>

SATA_HDD_R2D_C_N

TRUE

USB3_EXTA_RX_F_P

TRUE

USB3_EXTA_RX_F_N

TRUE

USB3_EXTA_RX_N

TRUE

TRUE

USB3_EXTA_RX_N

USB3_EXTA_TX_N

TRUE

USB3_EXTA_TX_C_N

TRUE

USB3_EXTB_RX_P

TRUE

USB3_EXTB_RX_RC_N

TRUE

USB3_EXTB_RX_RC_P

TRUE

USB3_EXTB_RX_N

TRUE

SATA_SSDRHDD_D2R_N

TRUE

SATA_HDD_R2D_RC_P

TRUE

USB3_EXTA_TX_C_P

TRUE

USB3_EXTA_RX_P

TRUE

TRUE

PCIE_CLK100M_SSD_N

NC_PCI_CLK33M_OUT2

TRUE
MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCH_TP23

TBTAPWRSW_ISET_S3

TRUE

PSOC_MISO

TRUE

USB_EXTB_P

TRUE

WIFI_EVENT_L

TRUE

TRUE

AP_RESET_CONN_L

TRUE

AP_CLKREQ_Q_L

TRUE

PCIE_WAKE_L

ENET_RESET_L

TRUE

SMBUS_PCH_CLK

TRUE

TRUE

PP_KBD_BOOST_VOUT

TRUE

WS_KBD17

TRUE

WS_KBD18

TRUE

WS_KBD19

PP3V3_S4

TRUE

TRUE

FAN_RT_PWM

TRUE

AUD_CONN_SLEEVE

TRUE

AUD_CONN_MIC_XW

TRUE

AUD_CONN_SLEEVE_XW
AUD_CONN_HP_LEFT

TRUE

TRUE

PP3V3_S0

AUD_CONN_TIPDET_INV

TRUE

TRUE

AUD_CONN_MIC

TRUE

AUD_CONN_HP_RIGHT
AUD_CONN_TYPEDET

TRUE

TRUE

SPKRCONN_L_ID

TRUE

SPKRCONN_L_OUT_N

SPKRCONN_L_OUT_P

TRUE

SPKRCONN_SL_OUT_P

TRUE
TRUE

SPKRCONN_SL_OUT_N

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_R_ID
SPKRCONN_SR_OUT_P

TRUE

GND

TRUE

TRUE

SPKRCONN_SR_OUT_N

TRUE

PP5VR3V3_SW_LCD

LED_RETURN_6

TRUE

PPVOUT_S0_LCDBKLT

TRUE

TRUE

LED_RETURN_5
LED_RETURN_4

TRUE
TRUE

LED_RETURN_3

TRUE

LED_RETURN_2
LED_RETURN_1

TRUE
TRUE

LCD_HPD_CONN

TRUE

DP_INT_AUX_P

TRUE

DP_INT_AUX_N

SMBUS_SMC_2_S3_SDA

TRUE

SMBUS_SMC_2_S3_SCL

TRUE

Z2_CLKIN

TRUE

Z2_MISO

TRUE

FAN_LT_TACH

TRUE

TRUE

FAN_LT_PWM

TRUE

AP_CLKREQ_Q_L

TRUE

PM_SLP_S3_L

TRUE

HDMI_HPD_L

TRUE

USB_EXTB_OC_L

TRUE

USB3_EXTB_TX_C_N

TRUE

USB3_EXTB_TX_C_P

TRUE

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

TRUE

TP_LPC_DREQ0_L

MAKE_BASE=TRUE

NC_LPC_DREQ0_L

TRUE

I1521

USB_BT_CONN_P
USB_BT_CONN_N

PP0700

1

PP0701

1

PP0702

1

PP0703

1

PP0704

1

PP0705

1

PP0706

1

PP0707

1

PP0708

1

PP0709

1

PP0710

1

PP0711

1

PP0712

1

PP0713

1

PP0719

1

PP0718

1

PP0717

1

PP0716

1

PP0715

1

PP0714

1

PP0720

1

PP0721

1

PP0722

1

PP0723

1

PP0724

1

<BRANCH>

<SCH_NUM>

<E4LABEL>

7 OF 132

7 OF 80

51 54

7

18

19

80

80

67 80

80

19

80

18

18

18

18

18

17

18

18

7

67 71

8

78

49

12 28 73

17

17

17

17

33

8

47

47

67 80

17

17

17

17

17

17

47

19

17

18

18

18

18

17

17

17

18

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

17

7

17 75

17

7

17 75

17

17

17

47

47

18 27 36 38 39 66

7

36

39 42 77

9

33 75

9

33 75

17 36 75

47

47

47

47

7 8

8

7 8

7

39 42 77

7

32

8

9

36

9

36

7

17 36 75

7

17 36 75

56 57

7 8

17 36

39 42 77

48

17 36 75

10

18 72

51 55

7

51

51

33

33

24

51

17

33

33

17

20

19

19

17

17

19

18

39

21

39

33

33

33

33

33

24

24

24

24

24

24

24

21

51

71

7

17

17

24

33

33

17

33

33

33

33

33

8

37

37 39 40

37 39 40

37

7

36 40 80

7

17 36 75

7

17 36 75

8

10 18 72

69

69 76

33 69 76

33 70 76

36 75

36 75

39 40 47

55

38 74

38 74

48

56

55

55

39 42

39 42

38

7

47

47

9

33 75

26 36 74

7 8

39 42 77

47

47

7

18 27 36 39 66

47

12 28 73

33 69 76

33 69 76

10 18 72

10 18 72

9

33 75

8

8

8

47

47

47

47

47

39 40 41

9

36 78

9

36 78

9

36 78

9

36 78

20 41 50

12 28 73

25 40

7

17 39 41 75

40

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

33 75

33 75

33 70 76

33 70 76

33 70 76

70 76

70 76

70 76

70 76

70 76

33 70 76

69 76

69 76

33 69 76

69 76

69 76

69 76

33 69 76

33 69 76

7

51

10 18 72

7

32

18 25 39

7

17 39 41 75

20 41

7

17 39 41 75

7

39 42 77

7

36

39 40 41

41

41

41

7

18 39 41

48

17 42 75

41

41

25 41

7

18 36

9

36

47

47

47

47

69

70

70

70

47

47

47

47

7 8

39 40

7 8

7 8

7

67 71

47

7

67 71

7 8

78

36 78

7 8

8

7 8

47

47

47

47

36 78

7

36

7

36 40 80

32 74

25 41 75

7

17 39 41 75

7

17 39 41 75

39 40 41

41

17 39 41

39 40 41

18 25 39 41

39 40 41 57

40 41

39 40 41

39 40 41

56

7

67 71

7

67 71

8

69

70 76

56

71

9

71

7

18 39 41

7 8

47

33 75

33 75

9

33 75

9

33 75

32 74

7

39 42 77

47

33 70 76

69

47

26 36 74

36 39 40

7

36

7

36

7

18 36

25

17 42 75

48

47

47

47

7 8

54

54

54

54

7 8

78

54

54

54

51 55

53 55 78

53 55 78

53 55 78

53 55 78

53 55 78

53 55 78

51 55

53 55 78

53 55 78

67

7

67 71

67 71 80

7

67 71

7

67 71

7

67 71

7

67 71

67 71

67

67 79

67 79

7

39 42 77

7

39 42 77

47

47

46

46

7

36

7

18 27 36 39 66

36 40

24 36

36 79

36 79

7

17 36 75

7

17 36 75

7

46

46

7 7

17

9

36 74

9

36 74

www.vinafix.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

5V Rails

For PCH RTC Power

3.3V Rails

Backlight Rails

1.8V/1.5V/1.2V/1.05V Rails

2A max supply

Chipset "VCore" Rails

TBT Rails (off when no cable)

G3H Rails

I1709

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

Power Aliases

MIN_LINE_WIDTH=0.2 mm

PP1V5R1V35_MEM

VOLTAGE=1.35V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.17 mm

=PP1V5R1V35_S3_MEM_B
=PP1V5_S3_MEMRESET

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.2 mm
VOLTAGE=1.35V

MAKE_BASE=TRUE

PP1V5R1V35_S3

=PP1V8_S0_REG

PP1V8_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.8V

=PPVDDIO_S0_SBCLK

=PP1V8_S0_PCH_VCC_DFTERM

VOLTAGE=3.3V

PP3V3_S5

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

=PP3V3_S5_PCH_VCCDSW

=PP3V3_S5_VMON

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

PP3V3_S3

VOLTAGE=3.3V

PP3V3_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.075 mm

MIN_LINE_WIDTH=0.5 MM

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_LCD

=PP3V3_S0_PCH_GPIO

=PPBUS_G3H_T25

=PPBUS_SW_BKL

=PP3V3_S4_TBTBPWRSW

=PP3V3_S4_TBTAPWRSW

=PP18V5_DCIN_CONN

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=12.8V

MIN_NECK_WIDTH=0.25 mm

PP3V3_SUS

MIN_NECK_WIDTH=0.2 MM MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=3.3V

=PP3V3_SUS_PCH_VCCSUS_USB

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVIN_S0_CPUIMVP

=PPBUS_S0_VSENSE

=PP1V5_S0_REG

=PPVTT_S3_DDR_BUF

=PP1V5_S3RS0_FET

=PPVTT_S0_DDR_LDO

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM

MAKE_BASE=TRUE

VOLTAGE=1.5V

=PP1V5_S0_AUDIO

=PPBUS_G3H

=PPVIN_S5_HS_COMPUTING_ISNS_R

=PP3V42_G3H_AUDIO
=PP3V42_G3H_TDM

=PP3V3_S5_P1V5S0

=PP5V_S0_AUDIO

=PP3V3_S4_TPAD

=PP3V3_SUS_PCH_VCCSUS_GPIO

=PP3V3_SUS_PCH_VCC_SPI

=PP3V3_S5_PCHPWRGD

=PP3V3_S5_PCH

=PP3V3_TBT_PCH_GPIO

=PP1V05_TBTLC

=PP3V3_TBT_PCH_GPIO

=PP1V05_S0_P1V05TBTREG_R

=PP1V05_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PPVCORE_S0_CPU

=PP3V3_TBTLC_RTR
=PPVDDIO_TBT_CLK

=PPVIN_S0_CPUAXG

=PP5V_S4_TPAD

=PPVIN_S3_DDRREG

=PP3V3_S3_P1V2S3

=PP1V5R1V35_S3_CPU_VCCDDR

=PP3V3_TBTLC_FET

=PPHV_SW_TBTAPWRSW
=PPHV_SW_TBTBPWRSW

=PP15V_TBT_REG

=PP1V05_S0_P1V05TBTREG

=PP1V05_TBTCIO_FET

=PP3V3_S3_P3V3S3FET

=PP3V3_S0_P3V3S0FET

=PP3V3_S5_PWRCTL

=PP3V3_S0_FET

=PP3V3_S0_PCH_STRAPS

=PP5V_S0_BKL

=PP3V3_SUS_ROM

=PP3V3_S3_USBMUX

=PP3V3_S3_VREFMRGN

=PP3V3_S3_SMS

=PPVCORE_S0_AXG_REG

=PP3V3_S3_MEMRESET

=PP3V3_S3_SMBUS_SMC_3

=PP3V42_G3H_BMU

=PPVIN_S5_P5VP3V3

=PPVIN_S0_VCCSAS0

=PP3V3_S3_FET

=PP3V3_S0_CPUTHMSNS

=PP3V3_S3_USB_RESET

=PP3V3_S3_ISNS

=PP3V3_S5_XDP

=PPBUS_G3H_T25_R

=PPDCIN_S5_CHGR

=PP3V3_S5_LPCPLUS

=PPVRTC_G3_PCH

=PP3V3_S0_AUDIO_DIG

=PP3V3_S0_P1V5S0

=PP3V3_S0_FAN_RT

=PP3V3_S0_P3V3TBTFET

=PP3V3_S0_PCH_VCC3_3_CLK

=PP3V3_S0_PCH_VCCADAC
=PP3V3_S0_PCH_VCC3_3

=PP3V3_S0_SYSCLK

=PP3V3_S0_SSD

=PP3V3_S0_SMBUS_SMC_1_S0

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_PCH

=PP3V3_S0_PCH_VCC3_3_HVCMOS

=PP3V3_S0_PCH_VCC3_3_GPIO

=PP3V3_S0_CPU_VCCIO_SEL

=PP3V3_S0_GPUTHMSNS

=PP3V3_S0_FAN_LT

=PP3V3_S0_DDCMUX

=PP3V3_S0_BKLI2C

=PP3V3_S0_P1V8S0

=PP3V3_S0_AUDIO

=PP3V3_S3_BT

=PP3V3_S3_P1V8S3

=PP3V3_S3_CAMERA

=PP3V3_S3_SDBUF

=PP3V3_S3_WLAN
=PP3V3_S3_GYRO

=PP3V3_S3_USB_HUB

=PP3V3_S3_SMBUS_SMC_2_S3

=PP3V3_S3_RIO

=PP3V3_S3_PCH_GPIO

=PPVBAT_G3_SYSCLK

=PP3V3_S5_SMCBATLOW

=PP3V3_S5_REG

=PP0V75_S0_MEM_VTT_B

=PP3V42_G3H_ONEWIREPROT

=PP3V42_G3H_SMCUSBMUX

=PP5V_S5_P1V5S3RS0FET

=PP3V3_S4_P3V3S4FET

=PP3V3_S5_P3V3SUSFET

=PP1V8_S0_CPU_VCCPLL_R

=PP3V3_S5_CPU_VCCDDR

=PP3V3_S5_PCH_GPIO

=PP18V5_DCIN_ISOL

=PP3V3_S5_SMC

=PP3V3_SUS_SMC

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_SUS_P1V05SUSLDO

=PP5V_S0_HDD

=PP3V3_SUS_CNTRL

=PP3V42_G3H_PWRCTL

=PP5V_SUS_PCH

=PP3V42_G3H_CHGR

=PP3V3_S5_SYSCLK

=PP3V3_SUS_PCH_GPIO

=PP1V5_S3_CPU_VCCDQ

=PPVCORE_S0_CPU_VCCAXG

=PP3V42_S3_HALL

=PP5V_S0_FAN_RT

=PP5V_S0_LPCPLUS

=PP5V_S0_PCH

=PP5V_S0_VMON

=PPVCCSA_S0_REG

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V8_S0_AUDIO

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V42_G3H_SMBUS_SMC_5

=PP5V_S4_P5VS0FET

=PPDDR_S3_REG

PPBUS_S0_LCDBKLT_PWR

=PPVIN_S3_MEM_ISNS

=PP1V5R1V35_S3_MEM_A

=PP1V5_S3RS0_VMON

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP0V75_S0_MEM_VTT_A

=PPVCCIO_S0_SMC
=PP1V05_S0_VMON

=PPVIN_S0_DDRREG_LDO

=PPVIN_S3_MEM_ISNS_R

=PP5V_S0_LCD

=PP5V_S0_KBDLED

=PPDDR_S3_MEMVREF
=PPVIN_S3_P1V5S3RS0_FET

=PPDCIN_S5_VSENSE

=PPDCIN_S5_CHGR_ISOL

=PP3V3_SUS_PCH

=PP3V3_S4_FET

=PP3V3_S4_RIO

=PP3V3_S4_BT

=PP3V3_S4_SMC

=PP5V_S0_VCCSAS0

=PP5V_S0_RMC

=PP5V_S0_FAN_LT

=PP5V_S0_CPUVCCIOS0

=PP5V_S3_DEBUG_ISNS

=PP5V_S3_DEBUG_ADC_AVDD

=PP5V_S3_DDRREG

=PP5V_S3_ALSCAMERA

=PP1V5_S0_RDRVR

=PP5V_S0_CPUIMVP

=PP5V_S0_AUDIO_XW

=PP3V3_S0_HS_COMPUTING_ISNS

=PP5V_S3_DEBUG_ADC_DVDD

=PP3V3_S0_XDP
=PP3V3_S0_DDR3THMSNS

=PP5V_S3_ISNS

=PPVIN_S5_HS_OTHER_ISNS

=PPVIN_S0_CPUVCCIOS0

=PPVIN_S5_HS_OTHER_ISNS_R

=PPBUS_S0_LCDBKLT

=PP3V3_S4_TBT

=PP5V_S4_REG

=PP3V3_SUS_FET

=PP5V_S4_RIO

=PP5V_S4_AUDIO

=PP5V_S4_P5VS3FET

=PP5V_S3_LTUSB

=PP5V_S3_MEMRESET

=PP3V3_S0_IMVPISNS

=PP3V3_S0_HS_ISNS

=PP3V3_S0_ISNS

=PP3V3_S0_PCH

=PP5V_S4_P1V05TBTS0

=PP5V_S0_FET

=PP3V42_G3H_REG

=PP3V3_S0_TBTI2C

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCIO_USB

=PP1V05_S0_PCH_VCCIO_CLK

=PP1V05_S0_PCH_VCC_CORE
=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_PLLUSB
=PP1V05_S0_PCH_VCC_DMI
=PP1V05_S0_PCH_VCCIO_PLLFDI
=PP1V05_S0_PCH_VCCDMI_FDI

=PP3V3_S0_SATAMUX

=PP3V3_S0_RSTBUF

=PP3V3_S0_PCH_VCC3_3_SATA

=PP3V3_S0_PCH_VCC3_3_PCI

=PPCPUVCCIO_S0_REG

=PP1V05_SUS_LDO

=PP1V05_S0_PCH

=PP1V05_S0_PCH_VCCDIFFCLK

=PP1V05_S0_PCH_VCCIO_CLK

=PP3V3_S0_SPKRTHMSNS

=PP3V3_S0_VMON

=PP3V3_S0_TPAD

=PP3V3_S0_SB_PM

=PP3V3_S0_PWRCTL

=PPVCCSA_S0_CPU

=PPVCCIO_S0_XDP

=PP3V3_S0_HS_OTHER_ISNS

=PP3V3_S0_HDMI

=PP3V3_S0_TBTPWRCTL

=PP1V05_S0_PCH_VCCSSC

=PP1V05_S0_RMC

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_PCH_V_PROC_IO

=PPVCORE_S0_CPU_REG

=PP5V_S3_FET

=PP5V_SUS_FET

=PP5V_S5_P5VSUSFET

=PP5V_S5_TPAD

=PPVIN_S5_SMCVREF

=PP3V42_G3H_TPAD

=PP5V_S5_LDO

=PPVRTC_G3_OUT

=PP1V05_S0_PCH_VCCIO_PCIE

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH_VCCIO_PLLPCIE

=PPVCCIO_S0_CPUIMVP

=PP1V05_SUS_PCH_JTAG

=PPVTT_S0_VTTCLAMP

=PPVIN_SW_TBTBST

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_SUS

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.15 MM

MIN_NECK_WIDTH=0.1 MMMAKE_BASE=TRUE

PP5V_S5

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM

PPVCCSA_S0_REG

VOLTAGE=0.9V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.17 mm
MAKE_BASE=TRUE

VOLTAGE=0.675V

MIN_LINE_WIDTH=0.6 mm

PP0V75_S0_DDRVTT

PP5V_S4

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=5V
MAKE_BASE=TRUE

PPVIN_S5_HS_COMPUTING_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.8V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm

PP5V_S3

VOLTAGE=5V

PP3V3_S4

MIN_NECK_WIDTH=0.1 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=18.5V

PPDCIN_G3H_ISOL

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=0.675V

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=12.8V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PPBUS_G3H_T25_PWR

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MMMAKE_BASE=TRUE

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 MM

PPVRTC_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=3.42V

VOLTAGE=1.05V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_CPU_VCCPQE

PP5V_SUS

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V
MAKE_BASE=TRUE

VOLTAGE=1.8V
MAKE_BASE=TRUEMIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0_CPU_VCCPLL_R

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PPVIN_S5_HS_OTHER_ISNS

VOLTAGE=12.8V

MAKE_BASE=TRUE

PP3V42_G3H

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.42V

PP1V5_S3_CPU_VCCDQ

VOLTAGE=1.5V

MAKE_BASE=TRUEMIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=12.8V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

PPVIN_SW_TBTBST

MIN_NECK_WIDTH=0.2 MM

PP5V_S0

VOLTAGE=5V
MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 MM

PP15V_TBT

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=15V

PP1V05_TBTCIO

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PPVCORE_S0_AXG

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE
VOLTAGE=1.25V

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

VOLTAGE=3.3V
MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_TBTLC

PP1V05_S0_P1V05TBTREG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V
MAKE_BASE=TRUE

PP1V05_S0_P1V05TBTREG_R

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

MAKE_BASE=TRUE

VOLTAGE=1.05V

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PP1V5_S3RS0_CPUDDR

<BRANCH>

<SCH_NUM>

<E4LABEL>

8 OF 132

8 OF 80

29

27

64

25

20 21 23

7

78

21 23

66

7

7

78

71

67

17 18 19 20 25 35

80

70

69

56

7

21 23

44

61 62

44

64

31 60

65

60

7

51

56 57

44

54

51

47

21 23

66

18

8

17 20

35

8

17 20

64 80

34

34

10 13 15 43

33 34 35

25

62

47

60

11 13 16 27

35

69

70

35

35 80

35

65

65

66

65

20

71

50

26

31

49

62

27

42

59

58

65

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26

43

24

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41

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42

42

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64

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36 66

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42

36

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40

59

30

56

38

65

65

65

13 15

27

20

56

39 40

40

21 23

64

37

66

66

23

57 66

25

17 18 19 20

13 16

10 13 16 43

40

46

41

23 25

66

58 80

13 15

15

21

42

65

60

71

43

28

66

21 23 25

30

40

66

60

43

67

48

31

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23

65

36

36

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46

63

60

32

36

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59

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17 23

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17 23

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21 23

21 23

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63

64

17 23

17 21 23

8

66

48

25 66

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66

13 16

24

44

36

35

21 23

10 11 13 15

21 23

62

65

65

65

47

40

47

59

25

18

21 23

23

61

24

27

35

7

7

7

7

7

7

7

7

7

35

7

7

78

www.vinafix.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TH0904,5 for USB can gnd slot

APN:862-0118

Unused Memory Signals

Unused PGOOD signal

D1 POGO PINS (870-2451)

Digital Ground

CR SFF DG v1p0 Table 3-56 mapping for HDMI

Unused GPU signals

CPU signals

T29 Signals Through PEG

Unused SATA ODD Signals

USB SIGNALS

UNUSED USB SIGNALS

Unused PEG signals

D1 BMU MODULE STANDOFFS

APN:998-3975

Frame Holes

D1 THERMAL MODULE STANDOFF (860-1439)

APN: 860-1490

FAN BOSSES (4X 860-1327)

eDP signals

TH0903 for lower TBT can gnd slot

APN:860-1557

SH0963 is BMU standoff with flange. 860-1534

D1 ELIPTICAL SLOT HOLES

Bosses for limiting deflection

TH0900 for upper TBT can gnd slot

SM

SM

STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD1.8H-SM

STDOFF-4.5OD2.15H-SM STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.73H-SM

1/20W

5%

201

MF

1K

RAMCFG0:L

RAMCFG1:L

1/20W

5%

201

1K

MF

RAMCFG3:L

1/20W

5%

201

MF

1K

201

5%
MF

1K

1/20W

STDOFF-4.5OD2.15H-SM

STDOFF-4.5OD1.8H-SM

SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

SL-3.9X2.3-4.2x2.6

TH-NSP TH-NSP

SL-2.8X1.8-3.1x2.1

SL-3.9X2.3-4.2x2.6

MF

10K

201

5%

1/20W

TH-NSP

SL-1.1X0.45-1.4x0.75

SL-1.1X0.45-1.4x0.75

TH-NSP

TH-NSP

SL-1.1X0.5-1.4x0.8

2.8OD1.2ID-2.25H-SM-D1

2.8OD1.2ID-2.25H-SM-D1

SM

SHLD-D1-USB

SHLD-D1-MLB-T29

SM

2.8OD1.2ID-2.25H-SM-D1

4P5R2P3-3P5B

STDOFF-4.5OD2.33H-SM

SM

POGO-2.3OD-5.5H-SM-LOW-FORCE

TH-NSP

SL-1.1X0.5-1.4x0.8

4P5R2P3-3P5B

Signal Aliases

SYNC_MASTER=D1_MLB_TEST

SYNC_DATE=01/27/2012

GND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

NC_PCH_GPIO65_CLKOUTFLEX1

TRUE

MAKE_BASE=TRUE

ENET_LOW_PWR_PCH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_RXN

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_P<3..0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

DP_TBTSNK1_ML_C_N<3..0>

DP_TBTSNK1_DDC_CLK

MAKE_BASE=TRUE

NC_PCH_GPIO66_CLKOUTFLEX2

TRUE

MAKE_BASE=TRUE

NC_PCH_GPIO67_CLKOUTFLEX3

TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTC_RXP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB3_EXTC_RXN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTCP

DP_TBTSNK1_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_CLK100MN

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP5V_S0_AUDIO_AMP_R

DP_INT_AUX_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_P<3..0>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_FWN

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_SSDN

TRUE

MAKE_BASE=TRUE

NC_PCIE_CLK100M_SSDP

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_FWP

HDMI_IG_CLK_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_P

MAKE_BASE=TRUE

DP_TBTSNK0_AUXCH_C_N

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LCD_FSS

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_P<3..0>

PP5V_S0_AUDIO_AMP_L

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_D2RN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_D2RP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_FW_R2D_CN

SD_PWR_EN_PCH

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2RN<15..12>

NC_PEG_R2D_CN<15..12>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLKN<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_CLKP<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_A_CLKP<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MEM_B_CLKN<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SATA_ODD_D2RN

NC_SATA_ODD_R2D_CP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_R2D_CN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SATA_ODD_D2RP

NO_TEST=TRUE

SD_PWR_EN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

PCIE_TBT_D2R_P<3..0>

NC_CPU_THERMDN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CPU_THERMDP

MAKE_BASE=TRUE

NO_TEST=TRUE

DP_TBTSNK1_DDC_DATA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

TP_P1V5S3RS0_RAMP_DONE

MAKE_BASE=TRUE

MEMVTT_EN

MAKE_BASE=TRUE

PCIE_TBT_R2D_C_N<3..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_R2D_CN<7..0>

PCIE_TBT_D2R_N<3..0>

MAKE_BASE=TRUE

NC_DPA_IG_AUX_CHP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_DPA_IG_AUX_CHN

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_FW_R2D_CP

MAKE_BASE=TRUE

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK0_DDC_CLK

MAKE_BASE=TRUE

NC_PEG_D2RP<15..12>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_FW_PWR_EN

MAKE_BASE=TRUE

HDMI_HPD

DP_TBTSNK0_DDC_DATA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

LCD_PWR_EN

DP_INT_AUX_C_N

MAKE_BASE=TRUE

DP_INT_ML_C_P<3..0>

MAKE_BASE=TRUE

DP_INT_ML_C_N<3..0>

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

HDMI_IG_CLK_C_N

MAKE_BASE=TRUE

HDMI_IG_DATA_C_P<2..0>

MAKE_BASE=TRUE

MAKE_BASE=TRUE

HDMI_IG_DDC_CLK

MAKE_BASE=TRUE

DP_TBTSNK0_ML_C_N<3..0>

TRUE

NC_PCH_GPIO64_CLKOUTFLEX0

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_TXN

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTD_EHCIP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTD_EHCIN

NC_USB3_EXTD_RXP

NO_TEST=TRUE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB3_EXTD_TXP

MAKE_BASE=TRUE

NC_USB3_EXTD_TXN

NO_TEST=TRUE

NC_USB_4N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_4P

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_SDP

NO_TEST=TRUE

NC_USB_SDN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_WLANP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_WLANN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_BT_HSN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_BT_HSP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

USB_BT_P

MAKE_BASE=TRUE

USB_TPAD_P

MAKE_BASE=TRUE

USB_BT_N

MAKE_BASE=TRUE

USB_TPAD_N

MAKE_BASE=TRUE

USB_SMC_P

MAKE_BASE=TRUE

USB_SMC_N

MAKE_BASE=TRUE

PU_USBHUB_DN4_P

MAKE_BASE=TRUE

PU_USBHUB_DN4_N

NC_USB_12N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_12P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_13P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_13N

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NC_USB3_EXTC_TXP

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_CLK100MP

NC_PEG_R2D_CP<15..12>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2RP<7..0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2RN<7..0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_R2D_CP<7..0>

MAKE_BASE=TRUE

LCD_BKLT_PWM

USB3_EXTC_RX_P

PEG_CLK100M_N

=PP3V3_S0_PWRCTL

CPUIMVP_AXG_PGOOD

TP_EDP_AUX_P

MLB_RAMCFG1

MLB_RAMCFG0

PCIE_CLK100M_SSD_P

PCIE_CLK100M_SSD_N

PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P

TP_EDP_TX_P<3..0>

LCD_FSS

LVDS_IG_PANEL_PWR

=PP5V_S0_AUDIO_XW

DPB_IG_AUX_CH_P

TP_PCH_GPIO67_CLKOUTFLEX3

TP_PCH_GPIO64_CLKOUTFLEX0

=DDRVTT_EN

=PEG_R2D_C_P<11..8>
=PEG_R2D_C_N<11..8>

=PEG_D2R_N<11..8>

CPU_THERMD_N

=PEG_R2D_C_N<7..0>

DPA_IG_HPD

PCIE_FW_R2D_C_N

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

SATA_ODD_D2R_N
SATA_ODD_D2R_P

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

FW_PWR_EN

TP_DP_IG_D_AUXN

TP_PCH_GPIO66_CLKOUTFLEX2

CPU_THERMD_P

=PEG_D2R_P<11..8>

TP_DP_IG_D_CTRL_DATA

TP_PCH_GPIO65_CLKOUTFLEX1

DDRREG_PGOOD

P1V5S3RS0_RAMP_DONE

LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON

PCIE_FW_D2R_N
PCIE_FW_D2R_P

PCIE_FW_R2D_C_P

TP_DP_IG_D_MLP<3..0>

DPA_IG_DDC_DATA

TP_DP_IG_C_MLP<3..0>

TP_DP_IG_D_CTRL_CLK

TP_DP_IG_D_HPD

DPA_IG_AUX_CH_N

DPA_IG_AUX_CH_P

ENET_LOW_PWR

PEG_CLK100M_P

TP_DP_IG_B_MLP<0..2>

DPA_IG_DDC_CLK

TP_DP_IG_B_MLN<0..2>

DPB_IG_AUX_CH_N

DPB_IG_DDC_CLK
DPB_IG_DDC_DATA

DPB_IG_HPD

TP_DP_IG_B_MLN<3>

USB3_EXTC_TX_N

USB3_EXTC_TX_P

USB3_EXTD_TX_P

USB_EXTC_N

TP_USB_SDP

TP_USB_WLANP

TP_USB_WLANN

TP_USB_BT_HSN
TP_USB_BT_HSP

TP_DP_IG_C_MLN<3..0>

USB3_EXTC_RX_N
USB_EXTC_P

USBHUB_DN1_P

USBHUB_DN2_P

USBHUB_DN1_N

USBHUB_DN2_N
USBHUB_DN3_P
USBHUB_DN3_N
USBHUB_DN4_P
USBHUB_DN4_N

TP_USB_12N

TP_USB_13P

TP_USB_13N

TP_USB_12P

TP_USB_SDN

TP_USB_4P

TP_USB_4N

USB_EXTD_EHCI_P

USB3_EXTD_RX_N

USB3_EXTD_TX_N

TP_DP_IG_B_MLP<3>

=PEG_R2D_C_N<15..12>

=PEG_R2D_C_P<15..12>

=PEG_D2R_N<15..12>

=PEG_D2R_P<15..12>

=PEG_D2R_N<7..0>
=PEG_R2D_C_P<7..0>

=PEG_D2R_P<7..0>

MLB_RAMCFG2

TP_EDP_AUX_N

TP_DP_IG_D_MLN<3..0>

USB3_EXTD_RX_P

TP_DP_IG_D_AUXP

USB_EXTD_EHCI_N

MAKE_BASE=TRUE

DP_TBTSNK0_HPD

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTCN

TP_EDP_TX_N<3..0>

MAKE_BASE=TRUE

HDMI_IG_DDC_DATA

MAKE_BASE=TRUE

HDMI_IG_DATA_C_N<2..0>

2.8OD1.2ID-2.25H-SM-D1

MLB_RAMCFG3

RAMCFG2:L

TH-NSP

POGO-2.3OD-5.5H-SM-LOW-FORCE

SM

POGO-2.3OD-4.1H-SM-LOW-FORCE

STDOFF-4.5OD1.8H-SM

ZT0960

1

XW0902

1 2

XW0903

1 2

SH0921

1

SH0922

1

SH0925

1

SH0926

1

SH0927

1

SH0928

1

SH0924

1

R0910

1

2

R0911

1

2

R0913

1

2

R0912

1

2

SH0920

1

SH0923

1

SH0932

1

SH0933

1

SH0934

1

SH0935

1

SH0936

1

ZT0930

1

ZT0920

1

ZT0931

1

R0991

1

2

TH0905

1

TH0904

1

TH0900

1

SH0910

1

SH0911

1

SH0912

1

SH0950

1

SH0951

1

SH0913

1

ZT0940

1

SH0963

1

SH0937

1

TH0903

1

<BRANCH>

<SCH_NUM>

<E4LABEL>

9 OF 132

9 OF 80

20 24 25

33 79

33 79

33 79

68

33

53

67 79

33 79

7

36 78

33 79

33 79

7

33 75

53

7

36

7

33 75

68

27

7

33 75

7

33 75

33 79

68

36

68

67

67 79

67 79

67 79

71

7

36 78

7

36 78

7

36

33 79

7

36 74

47 74

7

36 74

47 74

39 74

39 74

78

78

7

71

19

7

17 75

8

66

61

10

20

20

7

17 75

7

17 75

7

17 75

7

17 75

10

67

18

8

18

17

17

27 60

10

10

10

10 78

10

18

17

12

12

12

12

17

17

17

17

25

18

17

10 78 10

18

17

60

65

18

18

17

17

17

18

18

18

18

18

18

18

25

7

17 75

18

18

18

18

18

18

18

18

19

19

19

19

19

19

19

19

19

18

19

19

26

26

26

26

26

26

26

26

19

19

19

19

19

19

19

19

19

19

18

10

10

10

10

10

10

10

20

20

10

18

19

18

19

33

10

7

36 78

www.vinafix.vn

IN
IN
IN
IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT
OUT
OUT

OUT

OUT
OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN
IN
IN
IN
IN

IN

IN

IN

IN

IN

IN
IN

OUT

OUT

OUT

OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

IN
IN

IN

IN
IN

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC

NC
NC

NC

NC

NC

NC

NC

NC

NC

EDP_TX_3

EDP_TX_0
EDP_TX_1
EDP_TX_2

EDP_TX_2*
EDP_TX_3*

EDP_TX_0*
EDP_TX_1*

EDP_AUX

EDP_AUX*

EDP_COMPIO

EDP_HPD

EDP_ICOMPO

FDI1_LSYNC

DMI_TX_3*

FDI0_LSYNC

FDI0_TX_3

FDI1_TX_1

FDI1_TX_0

FDI1_TX_2
FDI1_TX_3

FDI0_FSYNC
FDI1_FSYNC

FDI_INT

FDI1_TX_3*

FDI1_TX_2*

FDI0_TX_1

FDI0_TX_0

FDI0_TX_2

FDI1_TX_1*

FDI0_TX_3*

FDI1_TX_0*

FDI0_TX_2*

FDI0_TX_1*

DMI_TX_1*
DMI_TX_2*

DMI_TX_0

DMI_TX_2

DMI_TX_1

DMI_TX_3

FDI0_TX_0*

DMI_RX_2*

DMI_RX_0
DMI_RX_1
DMI_RX_2
DMI_RX_3

DMI_TX_0*

DMI_RX_3*

DMI_RX_1*

DMI_RX_0*

PEG_ICOMPI
PEG_ICOMPO
PEG_RCOMPO

PEG_RX_2*

PEG_RX_0*
PEG_RX_1*

PEG_RX_3*
PEG_RX_4*
PEG_RX_5*

PEG_RX_7*

PEG_RX_6*

PEG_RX_8*
PEG_RX_9*

PEG_RX_10*

PEG_RX_12*

PEG_RX_11*

PEG_RX_14*

PEG_RX_13*

PEG_RX_15*

PEG_RX_0
PEG_RX_1

PEG_RX_3

PEG_RX_2

PEG_RX_4

PEG_RX_6

PEG_RX_5

PEG_RX_7
PEG_RX_8

PEG_RX_10

PEG_RX_9

PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15

PEG_TX_1*
PEG_TX_2*

PEG_TX_0*

PEG_TX_3*
PEG_TX_4*
PEG_TX_5*

PEG_TX_7*

PEG_TX_6*

PEG_TX_10*

PEG_TX_8*
PEG_TX_9*

PEG_TX_11*
PEG_TX_12*
PEG_TX_13*
PEG_TX_14*
PEG_TX_15*

PEG_TX_1

PEG_TX_0

PEG_TX_2
PEG_TX_3
PEG_TX_4

PEG_TX_6

PEG_TX_5

PEG_TX_7
PEG_TX_8

PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12

PEG_TX_14

PEG_TX_13

PEG_TX_15

(1 OF 9)

PCI EXPRESS BASED INTERFACE SIGNALS

DMI

INTEL FLEXIBLE DISPLAY INTERFACE SIGNALS

EMBEDDED DISPLAY PORT

NC
NC

RSVD_26
RSVD_27

RSVD_25

RSVD_23
RSVD_24

RSVD_22

RSVD_21

RSVD_19

RSVD_18

RSVD_16
RSVD_17

RSVD_15

RSVD_14

RSVD_13

RSVD_12

DC_TEST_BG1

DC_TEST_BD1

DC_TEST_BE1

DC_TEST_BG3
DC_TEST_BE3

DC_TEST_BG4

DC_TEST_BG58

DC_TEST_BG59

DC_TEST_BE59
DC_TEST_BG61

DC_TEST_BD61
DC_TEST_BE61

DC_TEST_D61

DC_TEST_A61
DC_TEST_C61

DC_TEST_A59
DC_TEST_C59

DC_TEST_A58

DC_TEST_D3
DC_TEST_D1

DC_TEST_C4

DC_TEST_A4

RSVD_45

RSVD_44

RSVD_41

RSVD_43

RSVD_42

RSVD_39
RSVD_40

RSVD_38

RSVD_36

RSVD_33

RSVD_31
RSVD_32

RSVD_30

CFG_3

CFG_2

CFG_1

CFG_0

CFG_9

CFG_8

CFG_7

CFG_6

CFG_14

CFG_12

CFG_10

CFG_16
CFG_17

VCC_VAL_SENSE

RSVD_8

RSVD_7

RSVD_6

CFG_15

CFG_13

CFG_11

CFG_5

CFG_4

VSS_VAL_SENSE

VAXG_VAL_SENSE

VCC_DIE_SENSE

VSSAXG_VAL_SENSE

RSVD_11

RSVD_9
RSVD_10

RSVD_20

RSVD_37

RSVD_35

RSVD_34

SB_DIMM_VREFDQ

SA_DIMM_VREFDQ

RESERVED

(5 OF 9)

NC
NC
NC

NC

OUT
OUT

OUT
OUT

IN

G

SYM_VER_1

D

S

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CFG [4] :eDP ENABLE/DISABLE 1 = DISABLED 0 = ENABLED

FOR IVYBRIDGE PROCESSOR

CFG [7] :PEG DEFER TRAINING 1 = (DEFAULT) IMMEDIATELY AFTER xxRESETB 0 = WAIT FOR BIOS
CFG [6:5] :PCIE BIFURCATION 11 = 1 X16 (DEFAULT) 10 = 2 X8 01 = RSVD 00 = X8, X4, X4

If HPD is disabled while eDP interface is still enabled,

NOTE: The EDP_HPD processor input is a low voltage active low signal.

even if internal Graphics is disabled since they are

Note. VOLTAGE=1.25V
Note. VOLTAGE=0V

Note. VOLTAGE=1.05V
Note. VOLTAGE=0V

NOTE: Intel does not recommend to use

NOTE: Intel validation sense lines per

this alnalog sense due to accuracy concern.

doc 439028 rev1.0 HR_PPDG sections 6.2.1 and 6.3.1.

NOTE: Intel provides an internal pull-up OF 5-15k to VCCIO on all CFG signals.

CFG [2] :PCIE x16 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

shared with other interfaces.

NOTE: eDP_COMPIO and eDP_ICOMPO can not be left floating

This signal can be left as no-connect if entire eDP interface is disabled.

connect it to CPU VCCIo via a 10-kOhm pull-up resistor on the motherboard.

to low voltage signals for the processor

to convert the active high signal from Embedded DisplayPort sink device

Therefore, an inverting level shifter is required on the motherboard

Intel Doc 460452 ChiefRiver Platform design guild rev1.0 section 2.2.12 recommendation.

CFG [3] :PCIE x4 LANE REVERSAL 1 = NORMAL OPERATION 0 = LANES REVERSED

These can be Placed close to J2500 and Only for debug access

(refer to latest Processor EDS for DC specifications).

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

7

18 72

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

PLACE_NEAR=U1000.G3:12.7MM

1%

24.9

402

MF-LF

1/16W

10 24 72

10 24 72

10 24 72

10 24 72

10 24 72

10 24 72

10 24 72

10 24 72

24 72

24 72

24 72

24 72

24 72

24 72

24 72

24 72

10 24 72

24 72

201

1/20W

MF

1K

5%

NOSTUFF

201

1/20W

MF

5%

1K

NOSTUFF

1K

201

1/20W

MF

5%

NOSTUFF

201

1/20W

MF

5%

1K

NOSTUFF

201

1/20W

MF

5%

1K

NOSTUFF

7

18 72

18 72

18 72

18 72

7

18 72

18 72

18 72

18 72

7

18 72

18 72

18 72

18 72

7

18 72

18 72

18 72

18 72

18 72

18 72

18 72

18 72

18 72

24.9

1%

MF-LF

1/16W

402

PLACE_NEAR=U1000.AF3:12.7MM

OMIT_TABLE

PLACE_NEAR=U1000.AG11:12.7MM

402

1/16W

1%

10K

MF-LF

EDP:YES

201

1/20W

MF

5%

1K

201

1/20W

MF

1K

5%

NOSTUFF

201

1/20W

MF

1K

5%

201

1/20W

MF

1K

5%

NOSTUFF

PLACE_SIDE=TOP

NOSTUFF

PLACE_NEAR=U1000.H43:50.8MM

1/16W

402

MF-LF

49.9

1%

PLACE_NEAR=U1000.H45:50.8MM
PLACE_SIDE=TOP

49.9

1/16W

402

1%

NOSTUFF

MF-LF

PLACE_SIDE=TOP

PLACE_NEAR=U1000.K43:50.8MM

49.9

1/16W
MF-LF

402

1%

NOSTUFF

PLACE_NEAR=U1000.K45:50.8MM

PLACE_SIDE=TOP

NOSTUFF

1%

MF-LF
402

49.9

1/16W

2C-35W

IVY-BRIDGE

BGA

CRITICAL

OMIT_TABLE

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

BGA

9

78

9

78

31 72

31 72

67

SOT523

DMN5L06TK

EDP:YES

SYNC_DATE=07/14/2011

CPU DMI/PEG/FDI/RSVD

SYNC_MASTER=J30_MLB

RES,MTL FILM,1/16W,10K,0402,SMD,LF

EDP:NO

R1031

1

116S0090

116S0066

RES,MTL FILM,1/16W,1K,0402,SMD,LF

1

EDP:YES

R1031

=PEG_D2R_N<11>

=PEG_D2R_N<13>
=PEG_D2R_N<14>
=PEG_D2R_N<15>

LCD_HPD

EDP_HPD_L

TP_EDP_TX_P<3>

TP_EDP_TX_P<2>

TP_EDP_TX_N<1>

TP_EDP_AUX_P

TP_EDP_AUX_N

TP_EDP_TX_N<0>

TP_EDP_TX_P<0>

DMI_S2N_P<1>

FDI_DATA_P<3>

DMI_N2S_N<1>

DMI_N2S_N<0>

FDI_DATA_N<2>

FDI_DATA_N<4>

FDI_DATA_N<6>

=PEG_R2D_C_P<12>

=PEG_R2D_C_P<14>

DMI_S2N_N<1>

=PEG_D2R_P<7>

=PEG_D2R_P<5>

CPU_VCC_VALSENSE_N

CPU_CFG<6>

CPU_CFG<4>

CPU_CFG<0>

=PEG_R2D_C_P<1>

=PEG_R2D_C_N<12>

=PEG_D2R_N<6>

=PEG_D2R_N<5>

=PEG_R2D_C_P<0>

CPU_THERMD_N

CPU_THERMD_P

=PEG_D2R_P<12>

CPU_DC_TEST_C59_A59

CPU_VCC_VALSENSE_P

CPU_AXG_VALSENSE_P

=PEG_D2R_P<13>

=PEG_R2D_C_P<2>

=PEG_R2D_C_P<9>

CPU_CFG<17>

CPU_DC_TEST_C4_BE1_BG1

TP_CPU_DC_TEST_BD1

CPU_DC_TEST_C4_BE3_BG3

TP_CPU_DC_TEST_BG4

TP_CPU_DC_TEST_BG58

CPU_DC_TEST_BG59_BG61

CPU_DC_TEST_BE59_BE61

TP_CPU_DC_TEST_BD61

TP_CPU_DC_TEST_D61

CPU_DC_TEST_C61_A61

TP_CPU_DC_TEST_A58

CPU_DC_TEST_C4_D3

TP_CPU_DC_TEST_D1

TP_CPU_DC_TEST_A4

CPU_CFG<3>

CPU_CFG<2>

CPU_CFG<1>

CPU_CFG<9>

CPU_CFG<8>

CPU_CFG<7>

CPU_CFG<14>

CPU_CFG<12>

CPU_CFG<10>

CPU_CFG<16>

CPU_CFG<15>

CPU_CFG<13>

CPU_CFG<11>

CPU_CFG<5>

TP_CPU_VCC_DIE_SENSE

CPU_AXG_VALSENSE_N

CPU_CFG<4>

=PPVCORE_S0_CPU_VCCAXG

=PP1V05_S0_CPU_VCCIO

CPU_CFG<1>
CPU_CFG<0>

CPU_CFG<3>

CPU_CFG<16>

=PPVCORE_S0_CPU

=PEG_R2D_C_P<13>

=PEG_R2D_C_P<11>

=PEG_R2D_C_P<10>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<7>

=PEG_R2D_C_P<5>
=PEG_R2D_C_P<6>

=PEG_R2D_C_P<4>

=PEG_R2D_C_P<3>

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_N<13>

=PEG_R2D_C_N<11>

=PEG_R2D_C_N<9>

=PEG_R2D_C_N<8>

=PEG_R2D_C_N<10>

=PEG_R2D_C_N<6>
=PEG_R2D_C_N<7>

=PEG_R2D_C_N<5>

=PEG_R2D_C_N<4>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<1>

=PEG_D2R_P<15>

=PEG_D2R_P<14>

=PEG_D2R_P<9>

=PEG_D2R_P<8>

=PEG_D2R_P<6>

=PEG_D2R_P<4>

=PEG_D2R_P<2>
=PEG_D2R_P<3>

=PEG_D2R_P<1>

=PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_N<9>

=PEG_D2R_N<8>

=PEG_D2R_N<7>

=PEG_D2R_N<4>

=PEG_D2R_N<3>

=PEG_D2R_N<1>

CPU_PEG_COMP

DMI_S2N_N<3>

DMI_S2N_P<3>

FDI_DATA_N<0>

DMI_N2S_P<3>

DMI_N2S_P<2>

DMI_N2S_P<0>

FDI_DATA_N<1>

FDI_DATA_N<5>

TP_EDP_TX_N<3>

TP_EDP_TX_N<2>

=PEG_D2R_P<0>

=PEG_R2D_C_P<15>

CPU_CFG<2>

=PP1V05_S0_CPU_VCCIO

DMI_S2N_P<0>

DMI_N2S_N<2>

DMI_N2S_P<1>

FDI_DATA_N<3>

FDI_DATA_N<7>

FDI_DATA_P<1>

FDI_DATA_P<7>

FDI_DATA_P<5>

DMI_S2N_N<0>

FDI_LSYNC<1>

FDI_DATA_P<0>

=PEG_D2R_N<2>

=PEG_D2R_N<0>

DMI_S2N_P<2>

DMI_N2S_N<3>

DMI_S2N_N<2>

TP_EDP_TX_P<1>

FDI_LSYNC<0>

FDI_INT

FDI_FSYNC<1>

FDI_FSYNC<0>

CPU_EDP_COMP

CPU_CFG<5>

CPU_CFG<6>

CPU_CFG<7>

FDI_DATA_P<6>

FDI_DATA_P<4>

FDI_DATA_P<2>

=PEG_D2R_P<11>

=PEG_D2R_P<10>

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PPCPU_MEM_VREFDQ_B

MIN_LINE_WIDTH=0.3 MM
VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

PPCPU_MEM_VREFDQ_A

R1010

1 2

R1042

1

2

R1049

1

2

R1043

1

2

R1041

1

2

R1040

1

2

R1030

1 2

R1031

1 2

R1044

1

2

R1046

1

2

R1045

1

2

R1047

1

2

R1064

1

2

R1070

1

2

R1065

1

2

R1071

1

2

U1000

N3

M2

P7

P6

P3

P1

P11

P10

K3

K1

M7

M8

P4

N4

T3

R2

AF4

AG4

AF3

AG11

AD2

AC1

AC3

AA4

AC4

AE10

AE11

AE6

AE7

AA11

AA10

U6

U7

W10

W11

W3

W1

AA7

AA6

AC12

AG8

W7

W6

T4

V4

AA3

Y2

AC8

AC9

U11

G3
G1
G4

K22

H22

K19

J21

F8

G8

C8

A8

C5

B6

H6

H8

F6

E5

K6

K7

C21

B22

D19

D21

C19

A19

D16

D17

C13

B14

D12

D13

C11

A11

C9

B10

F22

G22

A23

C23

K13

J14

G13

H13

K10

M10

G10

F10

D8

D9

K4

J4

D24

D23

E21

F21

G19

H19

B18

C17

K17

K15

G17

F17

E14

F14

C15

A15

U1000

B50
C51

K49
K53
F53
G53
L51
F51
D52
L53

B54
D53
A51
C53
C55
H49
A55
H51

A4

A58
A59

A61

BD1

BD61

BE1

BE3

BE59

BE61

BG1

BG3

BG4

BG58

BG59

BG61

C4

C59

C61

D1

D3

D61

AG13

AH2

AM14
AM15

AT21

AT49

AU19
AU21

AV19

AY21

AY22

BA19

BA22

BB19

BB21

BD21
BD22
BD25
BD26

BE22

BE24

BE26
BF23

BG22

BG26

H48

K24

K48

L42
L45
L47

M13
M14

N42

N50

P13

U14
W14

BE7
BG7

H45

F48

H43
K43

K45

Q1031

3

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

10 OF 132

10 OF 80

9

9

9

9

9

9

9

10 24 72

8

13

16 43

8

10 11 13 15

10 24 72

10 24 72

10 24 72

10 24 72

8

13 15 43

72

9

9

10 24 72

8

10 11

13 15

9

72

10 24 72

10 24 72

10 24 72

www.vinafix.vn

BI
BI
BI
BI
BI

IN

IN

OUT

IN
IN

OUT

OUT

BI

BI

NC

OUT

SM_RCOMP_2

SM_RCOMP_1

SM_RCOMP_0

SM_DRAMRST*

BCLK_ITP

BCLK_ITP*

DPLL_REF_CLK*

DPLL_REF_CLK

BCLK*

BCLK

RESET*

SM_DRAMPWROK

UNCOREPWRGOOD

PM_SYNC

PROC_SELECT*

PROC_DETECT*

PREQ*

TMS

TRST*

TDI
TDO

DBR*

BPM_0*
BPM_1*
BPM_2*
BPM_3*
BPM_4*
BPM_5*
BPM_6*
BPM_7*

TCK

PRDY*

THERMTRIP*

CATERR*

PROCHOT*

PECI

(2 OF 9)

CLOCKS

THERMAL

PWR MGMT

JTAG & BPM

DDR3 MISC

IN
IN

IN

OUT

IN
IN

IN

OUT

IN

IN
IN

IN

IN

OUT

BI
BI
BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)
(IPU)

(IPU)
(IPU)
(IPU)
(IPU)
(IPU)
(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

(IPU)

24 72

24 72

24 72

24 72

24 72

5%

10K

MF

1/20W

201

18 27 72

20 24 72

27

7

17 72

7

17 72

20 72

20 40 72

39 40 61 72

20 40 72

MF-LF

402

1/16W

1%

75

402

200

1%

MF-LF

1/16W

MF-LF

1/16W

402

25.5

1%

402

1/16W
MF-LF

140

1%

39 72

56

5%

MF

1/20W

201

BGA

2C-35W

CRITICAL

OMIT_TABLE

IVY-BRIDGE

17 72

17 72

NOSTUFF

201

1%

4.99K

MF

1/20W

5%

62

MF

1/20W

201

5%

1K

NOSTUFF

MF

1/20W

201

24 72

24 72

24 72

24 72

24 72

24 72

24 72

200

1/16W

402

MF-LF

1%

130

402

1%

MF-LF

1/16W

17 72

17 72

18 72

51

5%

NOSTUFF

MF

1/20W

201

43.2

1%

MF

1/20W

201

24 25

5%

NOSTUFF

1K

MF

1/20W

201

24 25 72

24 72

24 72

24 72

CPU CLOCK/MISC/JTAG

SYNC_MASTER=J30_MLB

SYNC_DATE=07/14/2011

=MEM_RESET_L

=PP1V05_S0_CPU_VCCIO

PLT_RESET_LS1V1_L

=PP1V5R1V35_S3_CPU_VCCDDR

PM_MEM_PWRGD

=PP1V05_S0_CPU_VCCIO

CPU_RESET_L

CPU_PECI

PM_THRMTRIP_L

XDP_CPU_PRDY_L

XDP_CPU_TCK

XDP_BPM_L<7>

XDP_BPM_L<6>

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

XDP_DBRESET_L

XDP_CPU_TDO

XDP_CPU_TDI

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_PREQ_L

ITPCPU_CLK100M_N

ITPCPU_CLK100M_P

CPU_SM_RCOMP<0>
CPU_SM_RCOMP<1>
CPU_SM_RCOMP<2>

CPU_PROCHOT_L

CPU_PROC_SEL_L

DPLL_REF_CLK_P
DPLL_REF_CLK_N

PM_MEM_PWRGD_R

CPU_PWRGD

PM_SYNC

CPU_PROCHOT_R_L

CPU_CATERR_L

DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

R1101

1

2

R1100

1

2

R1120

1

2

R1121

12

R1104

1

2

R1125

12

R1102

1

2

R1111

1

2

R1126

1

2

R1114

1

2

R1113

1

2

R1112

1

2

R1103

12

U1000

J3
H2

N59
N58

G58
E55
E59
G55
G59
H60
J59
J61

C49

K58

AG3
AG1

A48

C48

N53
N55

C57

F49

C45

D44

BE45

AT30

BF44
BE43
BG43

L56

M60
L59

D45

L55
J58

B46

R1115

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

11 OF 132

11 OF 80

8

10 11 13 15

8

13 16 27

8

10 11 13 15

72

72

72

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BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

BI
BI
BI
BI
BI
BI

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT

OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT

OUT
OUT

OUT

OUT
OUT

OUT
OUT

BI
BI
BI
BI
BI
BI
BI
BI

BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

SA_MA_14
SA_MA_15

SA_MA_12
SA_MA_13

SA_MA_11

SA_MA_9

SA_MA_10

SA_MA_8

SA_MA_7

SA_MA_6

SA_MA_5

SA_MA_4

SA_MA_3

SA_MA_2

SA_MA_1

SA_MA_0

SA_DQS_7

SA_DQS_5
SA_DQS_6

SA_DQS_3
SA_DQS_4

SA_DQS_2

SA_DQS_0
SA_DQS_1

SA_DQS_7*

SA_DQS_6*

SA_DQS_5*

SA_DQS_4*

SA_DQS_3*

SA_DQS_2*

SA_DQS_0*
SA_DQS_1*

SA_ODT_1

SA_ODT_0

SA_CS_1*

SA_CS_0*

SA_CKE_1

SA_CK_1*

SA_CK_1

SA_CKE_0

SA_CK_0*

SA_CK_0

SA_WE*

SA_RAS*

SA_CAS*

SA_BS_0
SA_BS_1
SA_BS_2

SA_DQ_62
SA_DQ_63

SA_DQ_61

SA_DQ_60

SA_DQ_59

SA_DQ_58

SA_DQ_57

SA_DQ_56

SA_DQ_55

SA_DQ_54

SA_DQ_53

SA_DQ_52

SA_DQ_50
SA_DQ_51

SA_DQ_49

SA_DQ_48

SA_DQ_47

SA_DQ_46

SA_DQ_45

SA_DQ_44

SA_DQ_42
SA_DQ_43

SA_DQ_41

SA_DQ_39
SA_DQ_40

SA_DQ_38

SA_DQ_37

SA_DQ_36

SA_DQ_34
SA_DQ_35

SA_DQ_31

SA_DQ_33

SA_DQ_32

SA_DQ_29
SA_DQ_30

SA_DQ_26

SA_DQ_28

SA_DQ_27

SA_DQ_24
SA_DQ_25

SA_DQ_23

SA_DQ_22

SA_DQ_21

SA_DQ_19
SA_DQ_20

SA_DQ_18

SA_DQ_17

SA_DQ_16

SA_DQ_13
SA_DQ_14
SA_DQ_15

SA_DQ_11
SA_DQ_12

SA_DQ_9
SA_DQ_10

SA_DQ_8

SA_DQ_7

SA_DQ_6

SA_DQ_5

SA_DQ_4

SA_DQ_3

SA_DQ_2

SA_DQ_1

SA_DQ_0

(3 OF 9)

MEMORY CHANNEL A

SB_MA_15

SB_MA_14

SB_MA_12
SB_MA_13

SB_MA_11

SB_MA_10

SB_MA_9

SB_MA_7
SB_MA_8

SB_MA_6

SB_MA_5

SB_MA_4

SB_MA_3

SB_MA_2

SB_MA_1

SB_MA_0

SB_DQS_7

SB_DQS_6

SB_DQS_5

SB_DQS_4

SB_DQS_3

SB_DQS_2

SB_DQS_1

SB_DQS_0

SB_DQS_7*

SB_DQS_6*

SB_DQS_5*

SB_DQS_4*

SB_DQS_3*

SB_DQS_2*

SB_DQS_1*

SB_DQS_0*

SB_ODT_0
SB_ODT_1

SB_CS_1*

SB_CS_0*

SB_CKE_1

SB_CK_1

SB_CK_1*

SB_CK_0*

SB_CKE_0

SB_CK_0

SB_DQ_37

SB_DQ_36

SB_DQ_34
SB_DQ_35

SB_DQ_33

SB_DQ_31
SB_DQ_32

SB_DQ_30

SB_DQ_29

SB_DQ_26
SB_DQ_27
SB_DQ_28

SB_DQ_24
SB_DQ_25

SB_DQ_21
SB_DQ_22
SB_DQ_23

SB_DQ_20

SB_DQ_19

SB_DQ_18

SB_DQ_17

SB_DQ_16

SB_DQ_15

SB_DQ_14

SB_DQ_13

SB_DQ_12

SB_DQ_11

SB_DQ_10

SB_DQ_8
SB_DQ_9

SB_DQ_7

SB_DQ_6

SB_DQ_4
SB_DQ_5

SB_DQ_3

SB_DQ_2

SB_DQ_1

SB_DQ_0

SB_DQ_39

SB_DQ_38

SB_DQ_40
SB_DQ_41
SB_DQ_42

SB_DQ_44

SB_DQ_43

SB_DQ_46

SB_DQ_45

SB_DQ_47

SB_DQ_49

SB_DQ_48

SB_DQ_51

SB_DQ_50

SB_DQ_52

SB_DQ_54

SB_DQ_53

SB_DQ_56

SB_DQ_55

SB_DQ_57

SB_DQ_59

SB_DQ_58

SB_DQ_61

SB_DQ_60

SB_DQ_62

SB_BS_0

SB_DQ_63

SB_BS_2

SB_BS_1

SB_RAS*

SB_CAS*

SB_WE*

(4 OF 9)

MEMORY CHANNEL B

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

7

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9

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29 30 73

CRITICAL

OMIT_TABLE

BGA

IVY-BRIDGE

2C-35W

CRITICAL

OMIT_TABLE

2C-35W

IVY-BRIDGE

BGA

SYNC_MASTER=J30_MLB

SYNC_DATE=07/14/2011

CPU DDR3 INTERFACES

MEM_A_DQ<0>
MEM_A_DQ<1>
MEM_A_DQ<2>

MEM_A_DQ<4>
MEM_A_DQ<5>
MEM_A_DQ<6>
MEM_A_DQ<7>
MEM_A_DQ<8>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<16>
MEM_A_DQ<17>
MEM_A_DQ<18>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<21>
MEM_A_DQ<22>
MEM_A_DQ<23>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<27>
MEM_A_DQ<28>

MEM_A_DQ<26>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<32>
MEM_A_DQ<33>

MEM_A_DQ<31>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<36>
MEM_A_DQ<37>
MEM_A_DQ<38>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<41>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<44>
MEM_A_DQ<45>
MEM_A_DQ<46>
MEM_A_DQ<47>
MEM_A_DQ<48>
MEM_A_DQ<49>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<52>
MEM_A_DQ<53>
MEM_A_DQ<54>
MEM_A_DQ<55>
MEM_A_DQ<56>
MEM_A_DQ<57>
MEM_A_DQ<58>
MEM_A_DQ<59>
MEM_A_DQ<60>
MEM_A_DQ<61>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_CAS_L
MEM_A_RAS_L
MEM_A_WE_L

MEM_A_CLK_N<0>
MEM_A_CKE<0>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CKE<1>

MEM_A_CS_L<0>
MEM_A_CS_L<1>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>
MEM_A_DQS_N<3>
MEM_A_DQS_N<4>
MEM_A_DQS_N<5>
MEM_A_DQS_N<6>
MEM_A_DQS_N<7>

MEM_A_DQS_P<1>

MEM_A_DQS_P<0>

MEM_A_DQS_P<2>

MEM_A_DQS_P<4>

MEM_A_DQS_P<3>

MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<7>

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>
MEM_A_A<5>
MEM_A_A<6>
MEM_A_A<7>
MEM_A_A<8>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<11>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<15>

MEM_A_A<14>

MEM_B_WE_L

MEM_B_CAS_L
MEM_B_RAS_L

MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_DQ<63>
MEM_B_BA<0>

MEM_B_DQ<62>

MEM_B_DQ<60>
MEM_B_DQ<61>

MEM_B_DQ<58>
MEM_B_DQ<59>

MEM_B_DQ<57>

MEM_B_DQ<55>
MEM_B_DQ<56>

MEM_B_DQ<53>
MEM_B_DQ<54>

MEM_B_DQ<52>

MEM_B_DQ<50>
MEM_B_DQ<51>

MEM_B_DQ<48>
MEM_B_DQ<49>

MEM_B_DQ<47>

MEM_B_DQ<45>
MEM_B_DQ<46>

MEM_B_DQ<43>
MEM_B_DQ<44>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<38>
MEM_B_DQ<39>

MEM_B_DQ<0>
MEM_B_DQ<1>
MEM_B_DQ<2>
MEM_B_DQ<3>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<6>
MEM_B_DQ<7>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<10>
MEM_B_DQ<11>
MEM_B_DQ<12>
MEM_B_DQ<13>
MEM_B_DQ<14>
MEM_B_DQ<15>
MEM_B_DQ<16>
MEM_B_DQ<17>
MEM_B_DQ<18>
MEM_B_DQ<19>
MEM_B_DQ<20>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<29>
MEM_B_DQ<30>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<33>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<36>
MEM_B_DQ<37>

MEM_B_CLK_P<0>

MEM_B_CKE<0>

MEM_B_CLK_N<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

MEM_B_CKE<1>

MEM_B_CS_L<0>
MEM_B_CS_L<1>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_DQS_N<0>
MEM_B_DQS_N<1>
MEM_B_DQS_N<2>
MEM_B_DQS_N<3>
MEM_B_DQS_N<4>
MEM_B_DQS_N<5>
MEM_B_DQS_N<6>
MEM_B_DQS_N<7>

MEM_B_DQS_P<0>
MEM_B_DQS_P<1>
MEM_B_DQS_P<2>
MEM_B_DQS_P<3>
MEM_B_DQS_P<4>
MEM_B_DQS_P<5>
MEM_B_DQS_P<6>
MEM_B_DQS_P<7>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>
MEM_B_A<4>
MEM_B_A<5>
MEM_B_A<6>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<9>
MEM_B_A<10>
MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<14>
MEM_B_A<15>

MEM_A_CLK_P<0>

MEM_A_DQ<3>

U1000

BD37
BF36
BA28

BE39

AU36
AV36

AT40
AU40

AY26

BB26

BB40
BC41

AG6
AJ6

AU6
AV9
AR6

AP8
AT13
AU13

BC7

BB7
BA13
BB11

AP11

BA7

BA9

BB9
AY13
AV14
AR14
AY17
AR19
BA14
AU14

AL6

BB14
BB17
BA45
AR43
AW48
BC48
BC45
AR45
AT48
AY48

AJ10

BA49
AV49
BB51
AY53
BB49
AU49
BA53
BB55
BA55
AV56

AJ8

AP50
AP53
AV54
AT54
AP56
AP52
AN57
AN53
AG56
AG53

AL8

AN55
AN52
AG55
AK56

AL7
AR11

AP6

AJ11

AL11

AR10

AR8

AY11

AV11

AU17

AT17

AW45

AV45

AV51

AY51

AT56

AT55

AK54

AK55

BG35
BB34

BE37
BA30
BC30
AW41
AY28
AU26

BE35
BD35
AT34
AU34
BB32
AT32
AY32
AV32

AY40
BA41

BD39
AT41

U1000

BG39
BD42
AT22

AV43

BA34
AY34

BA36
BB36

AR22

BF27

BE41
BE47

AL4
AL1

AV4
BA4
AU3
AR3
AY2
BA3
BE9

BD9
BD13
BF12

AN3

BF8
BD10
BD14
BE13
BF16
BE17
BE18
BE21
BE14
BG14

AR4

BG18
BF19
BD50
BF48
BD53
BF52
BD49
BE49
BD54
BE53

AK4

BF56
BE57
BC59
AY60
BE54
BG54
BA58
AW59
AW58
AU58

AK3

AN61
AN59
AU59
AU61
AN58
AR58
AK58
AL58
AG58
AG59

AN4

AM60
AL59
AF61
AH60

AR1

AU4

AT2

AM2

AL3

AV1

AV3

BE11

BG11

BD18

BD17

BE51

BG51

BA61

BA59

AR59

AT60

AK61

AK59

BF32
BE33

BD43
AT28
AV28
BD46
AT26
AU22

BD33
AU30
BD30
AV30
BG30
BD29
BE30
BE28

AT43
BG47

BF40
BD45

<BRANCH>

<SCH_NUM>

<E4LABEL>

12 OF 132

12 OF 80

www.vinafix.vn

OUT
OUT

OUT
OUT

OUT
OUT

OUT

OUT

IN

BI

OUT

VCCIO_29

VCCIO_28

VCCIO_27

VCCIO_26

VCCIO_25

VCCIO_24

VCCIO_23

VCCIO_22

VCCIO_21

VCCIO_20

VCCIO_19

VCCIO_18

VCCIO_17

VCCIO_16

VCCIO_15

VCCIO_14

VCCIO_13

VCCIO_12

VCCIO_11

VCCIO_10

VCCIO_9

VCCIO_8

VCCIO_7

VCCIO_6

VCCIO_49

VCCIO_48

VCCIO_5

VCCIO_4

VCCIO_3

VCCIO_47

VCCIO_46

VCCIO_45

VCCIO_44

VCCIO_43

VCCIO_1

VCCIO_42

VCCIO_41

VCCIO_40

VCCIO_39

VCCIO_38

VCCIO_37

VCCIO_36

VCCIO_35

VCCIO_34

VCCIO_33

VCCIO_32

VCCIO_31

VCCIO_30

VCCIO_51

VCCIO_50

VCC_76

VCC_75

VCC_74

VCC_73

VCC_72

VCC_71

VCC_70

VCC_69

VCC_68

VCC_67

VCC_66

VCC_64

VCC_63

VCC_62

VCC_61

VCC_60

VCC_59

VCC_58

VCC_57

VCC_56

VCC_55

VCC_54

VCC_53

VCC_52

VCC_51

VCC_50

VCC_49

VCC_48

VCC_47

VCC_46

VCC_45

VCC_44

VCC_43

VCC_42

VCC_41

VCC_40

VCC_39

VCC_38

VCC_37

VCC_36

VCC_35

VCC_34

VCC_33

VCC_32

VCC_31

VCC_30

VCC_29

VCC_28

VCC_27

VCC_26

VCC_25

VCC_24

VCC_23

VCC_22

VCC_21

VCC_20

VCC_19

VCC_18

VCC_17

VCC_16

VCC_15

VCC_14

VCC_13

VCC_12

VCC_11

VCC_10

VCC_9

VCC_8

VCC_7

VCC_6

VCC_5

VCC_4

VCC_3

VCC_2

VCC_1

VCCIO_SEL

VCCPQE_1
VCCPQE_2

VIDALERT*

VIDSCLK
VIDSOUT

VCC_SENSE
VSS_SENSE

VCCIO_SENSE

VSS_SENSE_VCCIO

LINES

SENSE

SVID QUIET

RAIL

PEG AND DDR

CORE SUPLLY

(6 OF 9)

(7 OF 9)

SENSE

LINE

1.8V

RAIL

SA RAIL

QUIET

RAIL

SENSE

LINE

DDR3-1.5V RAILS

GRPHICS

VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8

VDDQ_10

VDDQ_9

VDDQ_11
VDDQ_12
VDDQ_13
VDDQ_14
VDDQ_15
VDDQ_16
VDDQ_17
VDDQ_18

VDDQ_20

VDDQ_19

VDDQ_21
VDDQ_22
VDDQ_23
VDDQ_24
VDDQ_25
VDDQ_26

VCCDQ_1
VCCDQ_2

VDDQ_SENSE

VSS_SENSE_VDDQ

VCCSA_SENSE

VCCSA_VID_0
VCCSA_VID_1

SM_VREF

VAXG_1
VAXG_2

VAXG_4

VAXG_3

VAXG_5
VAXG_6
VAXG_7
VAXG_8
VAXG_9
VAXG_10
VAXG_11
VAXG_12
VAXG_13
VAXG_14
VAXG_15
VAXG_16
VAXG_17
VAXG_18
VAXG_19
VAXG_20
VAXG_21
VAXG_22
VAXG_23
VAXG_24
VAXG_25

VAXG_28

VAXG_26
VAXG_27

VAXG_30

VAXG_29

VAXG_33

VAXG_31
VAXG_32

VAXG_35

VAXG_34

VAXG_36
VAXG_37
VAXG_38
VAXG_39
VAXG_40
VAXG_41
VAXG_42
VAXG_43

VAXG_45

VAXG_44

VAXG_46
VAXG_47
VAXG_48
VAXG_49
VAXG_50
VAXG_51
VAXG_52
VAXG_53
VAXG_54
VAXG_55
VAXG_56

VAXG_SENSE
VSSAXG_SENSE

VCCPLL_1
VCCPLL_2
VCCPLL_3

VCCSA_2

VCCSA_1

VCCSA_3
VCCSA_4
VCCSA_5
VCCSA_6
VCCSA_7
VCCSA_8
VCCSA_9
VCCSA_10
VCCSA_11
VCCSA_12
VCCSA_13

VCCSA_15

VCCSA_14

VCCSA_16

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Note. VOLTAGE=0V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

(IPU)

Fixed at 1.05V

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

Note. VOLTAGE=0V

Note. VOLTAGE=0V

Note. VOLTAGE=1.05V

Note. VOLTAGE=1.05V

(NOT controlled by VCCIO_SEL)

(IPU)

Note. VOLTAGE=1.25V

Note. VOLTAGE=0V
Note. VOLTAGE=1.05V

VCCIO_SEL can be NC.

IVB supports 1.05V VCCIO.

PLACEMENT NOTE: Please place all sense line resistors on BOTTOM side.

61 72

61 72

61 72

61 72

63 72

63 72

58 72

1/16W

130

1%

402

MF-LF

PLACE_NEAR=U1000.C44:2.54mm

201

1/20W
MF

1%

75

PLACE_NEAR=R1310.2:2.54mm

1/20W

MF435%

201

PLACE_NEAR=U1000.A44:38mm

1/20W

MF5%

0

201

201

1/20W

MF5%

0

61 72

61 72

61 72

100

MF-LF

402

1/16W

1%

PLACE_NEAR=U1000.F43:50.8mm

PLACE_SIDE=TOP

100

1/16W

402

MF-LF

1%

PLACE_NEAR=U1000.AN16:50.8mm
PLACE_SIDE=TOP

402

100

1%
1/16W
MF-LF

PLACE_NEAR=U1000.G43:50.8mm

PLACE_SIDE=TOP

1%

402

100

MF-LF

1/16W

PLACE_NEAR=U1000.AN17:50.8mm

PLACE_SIDE=TOP

201

1/20W
MF

10K

5%

201

1/20W

MF

5%

10K

PLACE_NEAR=U1000.F45:50.8mm

1%

1/16W

402

MF-LF

100

PLACE_SIDE=TOP

PLACE_NEAR=U1000.BC43:50.8mm

MF-LF

402

1/16W

100

1%

PLACE_SIDE=TOP

PLACE_NEAR=U1000.G45:50.8mm

402

100

1%
1/16W
MF-LF

PLACE_SIDE=TOP

402

100

1%
1/16W
MF-LF

PLACE_NEAR=U1000.BA43:50.8mm

PLACE_SIDE=TOP

PLACE_NEAR=U1000.BJ44:2.54mm

1K

MF-LF

402

1/16W

1%

PLACE_NEAR=U1000.BJ44:2.54mm

1K

MF-LF

402

1/16W

1%

PLACE_NEAR=U1000.BJ44:2.54mm

10%
16V

0.1UF

X7R-CERM
0402

402

1%

MF-LF

100

1/16W

PLACE_NEAR=U1000.U10:50.8mm

58 72

IVY-BRIDGE

2C-35W

BGA

OMIT_TABLE

CRITICAL

CRITICAL

OMIT_TABLE

BGA

IVY-BRIDGE

2C-35W

10K

5%

MF

201

NOSTUFF

1/20W

SYNC_MASTER=J30_MLB

SYNC_DATE=07/14/2011

CPU POWER

=PP1V05_S0_CPU_VCCIO

=PP1V05_S0_CPU_VCCIO

CPU_VCCIO_SEL

=PP1V5_S3_CPU_VCCDQ

CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N

CPU_VCCSASENSE

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

=PP1V05_S0_CPU_VCCIO

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_CPU

CPU_VIDALERT_L

CPU_VIDSOUT

=PP1V5R1V35_S3_CPU_VCCDDR

=PP1V5R1V35_S3_CPU_VCCDDR

=PPVCCSA_S0_CPU

CPU_SM_VREF

CPU_VCCSA_VID<0>
CPU_VCCSA_VID<1>

CPU_VIDALERT_L_R

=PPVCCSA_S0_CPU

CPU_AXG_SENSE_N

CPU_AXG_SENSE_P

CPU_VIDSOUT_R

CPU_VCCSENSE_P
CPU_VCCSENSE_N

CPU_VCCIOSENSE_N

CPU_VCCIOSENSE_P

=PP3V3_S0_CPU_VCCIO_SEL

=PPVCORE_S0_CPU_VCCAXG

=PP1V5R1V35_S3_CPU_VCCDDR

=PPVCORE_S0_CPU

CPU_VIDSCLK_R

CPU_VIDSCLK

VOLTAGE=0.75V

CPU_SM_VREF

R1302

1

2

R1300

1

2

R1310

1 2

R1311

1 2

R1312

1 2

R1360

1

2

R1362

1

2

R1361

1

2

R1363

1

2

R1314

1

2

R1313

1

2

R1370

1

2

R1380

1

2

R1371

1

2

R1381

1

2

R1331

1

2

R1330

1

2

C1330

1

2

R1382

1

2

U1000

A26
A29
A31
A34
A35
A38
A39
A42
C26
C27
C32
C34
C37
C39
C42
D27
D32
D34
D37
D39
D42
E26
E28
E32
E34
E37
E38
F25
F26
F28
F32
F34
F37
F38
F42
G42
H25
H26
H28
H29
H32
H34
H35
H37
H38
H40
J25
J26
J28
J29
J32
J34
J35
J37
J38
J40
J42
K26
K27
K29
K32
K34
K35
K37
K39
K42
L25
L28
L33
L36
L40
N26
N30
N34
N38

F43

AA14
AA15
AB17
AB20
AC13
AD16
AD18
AD21
AE14
AE15
AF16
AF18
AF20

AF46

AG15
AG16
AG17
AG20
AG21

AG48
AG50
AG51

AJ14
AJ15

AJ17
AJ21
AJ25
AJ43
AJ47
AK50
AK51
AL14
AL15
AL16
AL20
AL22
AL26
AL45
AL48
AM16
AM17
AM21
AM43
AM47
AN20
AN42
AN45
AN48

BC22

AN16

W16
W17

AM25
AN22

A44
B43
C44

G43

AN17

U1000

AY43

AA46
AB47
AB50
AB51
AB52
AB53
AB55
AB56
AB58
AB59
AC61
AD47
AD48
AD50
AD51
AD52
AD53
AD55
AD56
AD58
AD59
AE46

N45
P47
P48
P50
P51
P52
P53
P55
P56
P61

F45

T48
T58
T59
T61
U46
V47
V48
V50
V51
V52
V53
V55
V56
V58
V59
W50
W51
W52
W53
W55
W56
W61
Y48
Y61

AM28
AN26

BB3
BC1
BC4

L17
L21
N16
N20
N22
P17
P20
R16
R18
R21

U10

U15
V16
V17
V18
V21

D48
D49

W20

AJ28
AJ33
AJ36
AJ40
AL30
AL34
AL38
AL42
AM33
AM36
AM40
AN30
AN34
AN38
AR26
AR28
AR30
AR32
AR34
AR36
AR40
AV41
AW26
BA40
BB28
BG33

BC43
BA43

G45

R1320

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

13 OF 132

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11 13 16 27

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43

13

www.vinafix.vn

(8 OF 9)

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VSS
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VSS
VSS
VSS
VSS
VSS
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VSS

VSS

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VSS

VSS

VSS

VSS

VSS_NCTF
VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF

VSS_NCTF
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(9 OF 9)

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BGA

2C-35W

IVY-BRIDGE

OMIT_TABLE

CRITICAL

IVY-BRIDGE

CRITICAL

OMIT_TABLE

2C-35W

BGA

SYNC_DATE=07/14/2011

SYNC_MASTER=J30_MLB

CPU GROUNDS

U1000

A13
A17
A21
A25
A28
A33
A37
A40
A45
A49
A53

A9

AA1

AA13
AA50
AA51
AA52
AA53
AA55
AA56

AA8

AB16
AB18
AB21
AB48
AB61

AC10
AC14
AC46

AC6

AD17
AD20

AD4

AD61

AE13

AE8

AF1
AF17
AF21
AF47
AF48
AF50
AF51
AF52
AF53
AF55
AF56
AF58
AF59

AG10
AG14
AG18
AG47
AG52
AG61

AG7

AH4
AH58

AJ13
AJ16
AJ20
AJ22
AJ26
AJ30
AJ34
AJ38
AJ42
AJ45
AJ48

AJ7

AK1
AK52
AL10
AL13
AL17
AL21
AL25
AL28
AL33
AL36
AL40
AL43
AL47
AL61

AM13
AM20
AM22
AM26
AM30

AM34
AM38

AM4

AM42
AM45
AM48
AM58
AN1
AN21
AN25
AN28
AN33
AN36
AN40
AN43
AN47
AN50
AN54

AP10
AP51
AP55

AP7

AR13
AR17
AR21
AR41
AR48
AR61

AR7

AT14
AT19
AT36

AT4

AT45
AT52
AT58
AU1

AU11
AU28
AU32
AU51

AU7

AV17
AV21
AV22
AV34
AV40
AV48
AV55

AW13
AW43
AW61

AW7

AY14
AY19
AY30
AY36

AY4

AY41
AY45
AY49
AY55
AY58

AY9

BA1
BA11
BA17
BA21
BA26
BA32
BA48
BA51
BB53

BC13

BC5

BC57

BD12
BD16
BD19
BD23
BD27
BD32
BD36
BD40
BD44
BD48
BD52
BD56

BD8

BE5
BG9

U1000

BG13
BG17
BG21
BG24
BG28
BG37
BG41
BG45
BG49
BG53

C29
C35
C40

D10
D14
D18
D22
D26
D29
D35

D4

D40
D43
D46
D50
D54
D58

D6

E25
E29

E3

E35
E40
F13
F15
F19
F29
F35
F40
F55

G48
G51

G6

G61

H10
H14
H17
H21

H4

H53
H58

J1
J49
J55

K11
K21
K51

K8

L16
L20
L22
L26
L30
L34
L38
L43
L48
L61

M11
M15

M4

M58

M6

N1
N17
N21
N25
N28
N33
N36
N40
N43
N47
N48
N51
N52
N56
N61

A5
A57
BC61
BD3
BD59
BE4
BE58
BG5
BG57
C3
C58
D59
E1
E61

P14
P16
P18
P21
P58
P59

P9

R17
R20

R4

R46
T1
T47
T50
T51
T52
T53
T55
T56

U13

U8

V20
V61

W13
W15
W18
W21
W46

W8

Y4
Y47
Y58
Y59

<BRANCH>

<SCH_NUM>

<E4LABEL>

14 OF 132

14 OF 80

www.vinafix.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Intel recommendation (table 7-5): 2x 1uF, 1x 330uF

CPU VCCPLL DECOUPLING

PLACEMENT_NOTE (C1640-C1645):

Intel recommendation (Table 7-7): 26x 1uF, 10x 10uF, 2x 330uF

PLACEMENT_NOTE (C1684-C167F):

PLACEMENT_NOTE (C1672-C1681):

CPU VCCIO/VCCPQ DECOUPLING

CPU VCCPLL Low pass filter

PLACEMENT_NOTE (C1646-C1671):

Note:The smallest 10mOhm available in the library are 0805s

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

CPU VCORE DECOUPLING

PLACEMENT_NOTE (C1655-C1666):

All INTEL recommendations from Intel doc #458544 Chief River Platform Power Design Guide v0p9

Intel recommendation (Table 7-2): Option 2: 35x 2.2uF, 12x 22uF, 4x 470uF, or Option 3: 35x 2.2uF, 6x 22uF, 6x 330 uF

PLACEMENT_NOTE (C1667-C1679):

0603

1%

1/4W

MF

0.010

10%

X5R

10V

1UF

402

PLACE_NEAR=U1000.AK65:2.54 mm:NO_VIA

CRITICAL

20%

2.2UF

CERM
402-2

6.3V

CRITICAL

20%
CERM

6.3V
402-2

2.2UF 2.2UF

20%

6.3V
CERM
402-2

CRITICAL

402-2

20%

2.2UF

CERM

CRITICAL

6.3V

2.2UF

20%

CRITICAL

CERM

6.3V
402-2

2.2UF

20%

CRITICAL

CERM

6.3V
402-2

0402

10V
X5R-CERM

1UF

10%

CRITICAL

20%

2.2UF

CERM

6.3V
402-2

20%
CERM

6.3V
402-2

2.2UF

CRITICAL

2.2UF

CRITICAL

6.3V
CERM

CRITICAL

2.2UF

20%
CERM

6.3V
402-2

20%

2.2UF

6.3V
402-2

CRITICAL

CERM CERM

20%

6.3V
402-2

2.2UF

CRITICAL

CRITICAL

20%

2.2UF

CERM

6.3V
402-2

0402

10V
X5R-CERM

1UF

10%

20%

2.2UF

CERM

6.3V
402-2

CRITICAL CRITICAL

20%

2.2UF

CERM

6.3V
402-2

CRITICAL

20%

2.2UF

CERM

6.3V
402-2

CRITICAL

20%

2.2UF

CERM

6.3V
402-2

20%

CRITICAL

CERM

6.3V
402-2

2.2UF 2.2UF

CRITICAL

20%
CERM

6.3V
402-2

20%

2.2UF

CERM

6.3V
402-2

CRITICAL CRITICAL

20%

2.2UF

CERM

6.3V
402-2

20%

2.2UF

CRITICAL

CERM

6.3V
402-2

20%

2.2UF

CRITICAL

CERM

6.3V
402-2

CASE-B2-SM

TANT

20%
2V

270UF

20%
2V
TANT

270UF

CASE-B2-SM

PLACE_NEAR=U1000.AK61:5mm

2V

270UF

20%
TANT

CASE-B2-SM

Place near U1000 on bottom side

0402-1

20%

6.3V

10UF

CERM-X5R

Place near U1000 on bottom side

20%

10UF

CERM-X5R

6.3V

0402-1

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

0402

10V
X5R-CERM

10%

1UF

6.3V

Place near U1000 on bottom side

10UF

CERM-X5R

20%

0402-1

Place near U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

Place near U1000 on bottom side

0402-1

10UF

CERM-X5R

6.3V

20%

Place near U1000 on bottom side

10UF

0402-1

20%

6.3V
CERM-X5R

20%

270UF

TANT
CASE-B2-SM

2V

270UF

2V

20%

CASE-B2-SM

TANT

PLACE_NEAR=U1000.AK61:5mm

CASE-B2-SM

TANT

270UF

20%
2V

10UF

CERM-X5R

6.3V

20%

0402-1

Place near U1000 on bottom side

20%

20UF

X6T-CERM

2V
0402

20%

Place close to U1000 on bottom side.

20UF

X6T-CERM

2V
0402

0402

10V
X5R-CERM

1UF

10%

20%

Place close to U1000 on bottom side.

20UF

X6T-CERM

2V
0402

20%

Place close to U1000 on bottom side.

CRITICAL

20UF

X6T-CERM

2V
0402

CRITICAL

X6T-CERM

20%

CRITICAL

20UF

X6T-CERM

2V
0402

20%

CRITICAL

20UF

X6T-CERM

2V

CRITICAL

2V

CRITICAL

20%

NO STUFF

2V
0402

CRITICAL

20%

20UF

X6T-CERM

2V
0402

20%

CRITICAL

X6T-CERM

2V
0402

20%

20UF

X6T-CERM

2V
0402

20%
2V

20%

CRITICAL

20UF

X6T-CERM

2V
0402

20%

20UF

X6T-CERM

2V
0402

20%

Place close to U1000 on bottom side.

CRITICAL

20UF

X6T-CERM

2V
0402

20%

Place close to U1000 on bottom side.

CRITICAL

20UF

X6T-CERM

2V
0402

20%

20UF

X6T-CERM

2V
0402

2V
CASE-B2-SM

270UF

20%
TANT

20%

270UF

CASE-B2-SM

TANT

2V

0402

10V
X5R-CERM

1UF

10%

CRITICAL

20%

20UF

X6T-CERM

2V
0402

20%

20UF

X6T-CERM

2V
0402

20%

20UF

X6T-CERM

2V
0402

20%

CRITICAL

20UF

X6T-CERM

2V
0402

20%

20UF

X6T-CERM

2V
0402

CRITICAL

2V
0402

20%

CRITICAL

20UF

X6T-CERM

2V
0402

20%

CRITICAL

20UF

X6T-CERM

2V
0402

20%

CRITICAL

20UF

X6T-CERM

2V
0402

20%

20UF

X6T-CERM

2V
0402

X5R-CERM
0402

10V

1UF

10%

Place on bottom side of U1000

CRITICAL

20%
X6T-CERM

2V
0402

CRITICAL

20%
X6T-CERM

2V
0402

CRITICAL

0402

20%

20UF

X6T-CERM

2V
0402

20%

NO STUFF

20UF

X6T-CERM

2V
0402

20%

CRITICAL

20UF

2V
0402

20%

POLY-TANT

2.0V

D2T-SM1

Place near inductors on bottom side.

470UF-4MOHM

0402

10V
X5R-CERM

Place on bottom side of U100.

1UF

10%

0402

10V

1UF

Place on bottom side of U1000

10%
X5R-CERM

POLY-TANT

20%

Place near inductors on bottom side.

2.0V

D2T-SM1

470UF-4MOHM

CRITICAL

20%

Place close to U1000 on top side.

20UF

X6T-CERM

2V
0402

NO STUFF

20%

CRITICAL

20UF

2V
0402

1UF

0402

10V
X5R-CERM

Place on bottom side of U1000

10%

0402

10V
X5R-CERM

10%

1UF

D2T-SM1

20%

Place near inductors on bottom side.

2.0V
POLY-TANT

470UF-4MOHM

0402

10V
X5R-CERM

1UF

10%

470UF-4MOHM

D2T-SM1

POLY-TANT

2.0V

Place near inductors on bottom side.

20%

20%

20UF

X6T-CERM

2V
0402

20UF

X6T-CERM

CRITICAL

20%
2V

0402

20%

CRITICAL

20UF

X6T-CERM

2V
0402

10%

1UF

10V
X5R
402

CRITICAL

NO STUFF

CRITICAL

20%
2V

0402

20%

2.2UF

6.3V
402-2

CERM

2.2UF

20%
CERM

6.3V
402-2

CRITICAL

2.2UF

CERM
402-2

CRITICAL

20%

6.3V

2.2UF

20%

CRITICAL

CERM

6.3V
402-2

6.3V

20%
CERM

402-2

2.2UF

CRITICAL

20%
CERM

6.3V

402-2

2.2UF

20%

CRITICAL

CERM

6.3V

20%

CRITICAL

CERM

6.3V
402-2

2.2UF

CRITICAL

20%

402-2

CERM

6.3V

2.2UF

CRITICAL

20%

2.2UF

6.3V
CERM

2.2UF

20%
CERM

6.3V
402-2

CRITICAL

20%

6.3V

CRITICAL

2.2UF

CERM
402-2

0402

10V

1UF

10%
X5R-CERM

10%
X5R-CERM

0402

10V

1UF

0402

10V
X5R-CERM

1UF

10%

0402

10V

1UF

10%
X5R-CERM

0402

10V
X5R-CERM

10%

1UF

10%

0402

10V
X5R-CERM

1UF

10V
X5R-CERM

1UF

10%

0402

0402

10V
X5R-CERM

10%

1UF

0402

10V
X5R-CERM

1UF

10%

0402

10V
X5R-CERM

1UF

10%

0402

X5R-CERM

10%
10V

1UF

0402

10V
X5R-CERM

1UF

10%

20%

CRITICAL

20UF

X6T-CERM

2V
0402

CRITICAL2VCRITICAL

2V

0402

10V
X5R-CERM

10%

1UF

0402

10V
X5R-CERM

1UF

10%

0402

10V
X5R-CERM

1UF

10%

20%

20UF

2V
0402

10UF

CERM-X5R

6.3V

20%

0402-1

Place near U1000 on bottom side

NO STUFF

CRITICAL

20%

0402

CRITICAL

X6T-CERM
0402

20%

20UF

X6T-CERM

2V
0402

NO STUFF

CRITICAL

20%
X6T-CERM

20%

CRITICAL

20UF

X6T-CERM

2V
0402

1/16W

0

MF-LF

5%

402

10%
10V
X5R

1UF

402

PLACE_NEAR=U1000.AK63:2.54 mm:NO_VIA

CPU DECOUPLING-I

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

=PPVCORE_S0_CPU

=PP1V8_S0_CPU_VCCPLL_R

=PP1V05_S0_CPU_VCCPQE

=PP1V8_S0_CPU_VCCPLL

=PP1V05_S0_CPU_VCCIO

CRITICAL

402-2

2.2UF

CRITICAL

402-2

NO STUFF

NO STUFF

NO STUFF NO STUFF

NO STUFF

NO STUFF NO STUFF

NO STUFF

402-2

20%

CRITICAL

20UF 20UF

NO STUFF

20UF

20%
2V
X6T-CERM

CRITICAL CRITICAL

NO STUFF

CRITICAL

X6T-CERM

Place close to U1000 on bottom side.

CRITICAL CRITICAL

NO STUFF

CRITICAL

0402

X6T-CERM

2V

20%

20UF 20UF

X6T-CERM

CRITICAL

NO STUFF

NO STUFF

NO STUFF

CRITICAL

0402

X6T-CERM

20%

20UF

NO STUFF NO STUFF

20UF

20%
X6T-CERM

0402

CRITICAL

2V

20UF

X6T-CERM

X6T-CERM

NO STUFF

CRITICAL

2V

20%

20UF 20UF

2V
0402

CRITICAL

NO STUFF

20UF

NO STUFF

CRITICAL

20UF

X6T-CERM

CRITICAL

0402

X6T-CERM

20%

20UF

NO STUFF

0402

CRITICAL

NO STUFF

NO STUFF

0402

2V

20%

20UF

NO STUFF NO STUFF

20UF

20%
X6T-CERM

CRITICAL

20UF

X6T-CERM
0402

X6T-CERM

R1601

1 2

C167F

1

2

C1697

1

2

C161F

1

2

C1698

1

2

C1699

1

2

C169A

1

2

C169B

1

2

C169C

1

2

C1684

1

2

C1680

1

23

C1685

1

2

C1686

1

2

C1681

1

23

C1655

1

2

C1656

1

2

C1687

1

2

C1688

1

2

C1682

1

23

C1689

1

2

C1683

1

23

C1670

1

2

C1658

1

2

C1671

1

2

C1659

1

2

C1660

1

2

C1650

1

2

C1625

1

2

C1600

1

2

C1651

1

2

C1652

1

2

C1627

1

2

C1653

1

2

C1628

1

2

C1654

1

2

C1604

1

2

C1631

1

2

C1606

1

2

C169D

1

2

C169E

1

2

C169F

1

2

C161A

1

2

C161B

1

2

C161C

1

2

C161D

1

2

C1690

1

2

C1691

1

2

C1692

1

2

C1693

1

2

C1661

1

2

C1662

1

2

C1663

1

2

C1694

1

2

C1695

1

2

C1696

1

2

C1676

1

2

C1664

1

2

C1665

1

2

C1678

1

2

C1666

1

2

C1679

1

2

R1600

1 2

C160X

1

2

C160Y

1

2

C1632

1

2

C1607

1

2

C1608

1

2

C1635

1

2

C1609

1

2

C1610

1

2

C1637

1

2

C1612

1

2

C1638

1

2

C1613

1

2

C1639

1

2

C1640

1

2

C1615

1

2

C1641

1

2

C1642

1

2

C1617

1

2

C1643

1

2

C1644

1

2

C1645

1

2

C1647

1

2

C1648

1

2

C1623

1

2

C1624

1

2

C167D

1

2

C167E

1

2

C160Z

1

2

C162A

1

2

C162B

1

2

C162C

1

2

C162D

1

2

C162E

1

2

C167A

1

2

C167B

1

2

C167C

1

2

C168B

1

2

C168A

1

2

C168C

1

2

C161E

1

2

C1668

1

2

C1669

1

2

C1672

1

2

C1673

1

2

C165B

1

2

C165A

1

2

C166F

1

2

C166E

1

2

C166D

1

2

C166C

1

2

C166B

1

2

C166A

1

2

C164C

1

2

C164B

1

2

C165F

1

2

C165E

1

2

C165C

1

2

C165D

1

2

C168D

1

2

C168E

1

2

C1657

1

2

C1649

1

2

C164A

1

2

C1677

1

2

C164E

1

2

C1667

1

2

C1674

1

2

C164D

1

2

C164F

1

2

C1675

1

2

C1646

1

2

C168F

1

2

C16A0

1

2

C16A3

1

2

C16A2

1

2

C16A1

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

16 OF 132

15 OF 80

8

10 13 43

8

13

8

13

8

8

10 11 13

www.vinafix.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PLACEMENT_NOTE (C1711-C1716):

PLACEMENT_NOTE (C1717-C1722):

CPU VDDQ/VCCDQ DECOUPLING

VAXG DECOUPLING

Intel recommendation (Table 7-4) for GT2 3.9mOhm LL: 11x 1uF, 6x 10uF, 6x 22uF, 2x 470uF

PLACEMENT_NOTE (C1700-C1710):

PLACEMENT_NOTE (C1758-C1762):

CPU VCCSA DECOUPLING

Intel recommendation (Table 7-9): 5x 1uf, 5x 10uf, 1x 330uf

Intel recommendation: 1x 10mOhn resistor, 1x 1uF 0402

PLACEMENT_NOTE (C1738-C1747):

PLACEMENT_NOTE (C1723-C1724):

Intel recommendation (Table 7-11): 10x 1uF, 8x 10uF, 1x 330uF

0.010

1%

1/4W

MF

0603

0402

10V
X5R-CERM

10%

1UF

Place on bottom side of U1000

20%
TANT

CASE-B2-SM

270UF

2V

CASE-B2-SM

TANT

270UF

20%
2V

6.3V

20%

0402-1

10UF

CERM-X5R

CRITICAL

0402-1

CRITICAL

10UF

20%

6.3V
CERM-X5R

10UF

CERM-X5R

6.3V

CRITICAL

20%

0402-1

20%

0402-1

CRITICAL

10UF

CERM-X5R

6.3V

10UF

CRITICAL

6.3V
CERM-X5R

20%

0402-1

2.0V

20%

Place near inductors on bottom side.

POLY-TANT
D2T-SM1

470UF-4MOHM

CRITICAL

0402-1

20%

6.3V
CERM-X5R

10UF

20%

Place close to U1000 on bottom side

0402-1

CERM-X5R

10UF

6.3V

0402

2V
X6T-CERM

20UF

CRITICAL

20%

6.3V

Place close to U1000 on bottom side

10UF

CERM-X5R

20%

0402-1

CERM-X5R
0402-1

20%

6.3V

10UF

Place close to U1000 on bottom sidePlace close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1 0402-1

CERM-X5R

6.3V

20%

Place close to U1000 on bottom side

10UF 10UF

0402-1

20%

6.3V
CERM-X5R

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

10UF

CERM-X5R

6.3V

20%

0402-1

10UF

6.3V

0402-1

CERM-X5R

20%

0402

2V
X6T-CERM

20UF

20%

CRITICAL

10UF

CERM-X5R

6.3V

20%

0402-1 0402-1

20%

6.3V
CERM-X5R

10UF

CASE-B2-SM

TANT

270UF

20%
2V

CASE-B2-SM

TANT

270UF

20%
2V

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

Place close to U1000 on bottom side

10UF

CERM-X5R

6.3V

20%

0402-1

0402

2V
X6T-CERM

20UF

NO STUFF

CRITICAL

20%

0402

2V
X6T-CERM

20UF

NO STUFF

20%

CRITICAL

0402

2V
X6T-CERM

20UF

NO STUFF

CRITICAL

20%

0402

2V
X6T-CERM

20UF

NO STUFF

CRITICAL

20%

470UF-4MOHM

Place near inductors on bottom side.

POLY-TANT

2.0V

20%

D2T-SM1

0402

2V
X6T-CERM

20UF

NO STUFF

CRITICAL

20%
2V
X6T-CERM

NO STUFF

20%

CRITICAL

20UF

04020402

2V
X6T-CERM

20UF

20%

CRITICAL

1UF

0402

10V
X5R-CERM

10%

Place on bottom side of U1000

0402

10V
X5R-CERM

10%

1UF

0402

10V
X5R-CERM

10%

1UF

0402

10V
X5R-CERM

10%

1UF

0402

2V
X6T-CERM

20UF

20%

CRITICAL

0402

2V
X6T-CERM

20UF

CRITICAL

20%

0402

2V
X6T-CERM

20UF

20%

CRITICAL

10V

0402

X5R-CERM

10%

1UF

X5R-CERM
0402

10V

1UF

10%

0402

10V
X5R-CERM

10%

1UF

0402

10V
X5R-CERM

1UF

CRITICAL

10%

Place on bottom side of U1000

CRITICAL

0402

10V
X5R-CERM

1UF

Place on bottom side of U100.

10%

0402

10V
X5R-CERM

CRITICAL

10%

Place on bottom side of U1000

1UF

0402

10V
X5R-CERM

CRITICAL

1UF

10%

0402

10V
X5R-CERM

CRITICAL

1UF

10%

0402

10V
X5R-CERM

CRITICAL

10%

1UF

X5R

10%
10V

402

1UF

0402

10V
X5R-CERM

CRITICAL

1UF

10%

0402

10V
X5R-CERM

1UF

10%

CRITICAL

0402

10V
X5R-CERM

CRITICAL

1UF

10%

Place on bottom side of U1000

1UF

10V

10%
X5R-CERM

0402

1UF

Place on bottom side of U100.

10V

10%
X5R-CERM

0402

Place on bottom side of U1000

10V

1UF

10%
X5R-CERM

0402

Place on bottom side of U1000

1UF

10V

10%
X5R-CERM

0402

1UF

10%
10V
X5R-CERM
0402

0402

10V
X5R-CERM

CRITICAL

1UF

10%

0402

10V
X5R-CERM

CRITICAL

10%

1UF

Place on bottom side of U1000

10%

0402

10V
X5R-CERM

Place on bottom side of U1000

1UF

0402

10V
X5R-CERM

10%

Place on bottom side of U100.

1UF

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

CPU DECOUPLING-II

=PP1V5_S3_CPU_VCCDQ

=PPVCCSA_S0_CPU

=PP1V5R1V35_S3_CPU_VCCDDR

=PPVCORE_S0_CPU_VCCAXG

R1702

1 2

C1757

1

2

C1738

1

2

C1739

1

2

C1740

1

2

C1723

1

23

C1717

1

2

C1718

1

2

C1724

1

23

C1719

1

2

C1741

1

2

C1742

1

2

C1743

1

2

C1744

1

2

C1720

1

2

C1721

1

2

C1722

1

2

C1745

1

2

C1746

1

2

C1747

1

2

C1700

1

2

C1701

1

2

C1702

1

2

C1704

1

2

C1705

1

2

C1706

1

2

C1707

1

2

C1708

1

2

C1709

1

2

C1758

1

2

C1759

1

2

C1760

1

2

C1761

1

2

C1762

1

2

C1710

1

2

C1703

1

2

C1756

1

2

C1768

1

2

C1711

1

2

C1712

1

2

C1713

1

2

C1714

1

2

C1715

1

2

C1716

1

2

C1748

1

2

C1749

1

2

C1751

1

2

C1752

1

2

C1753

1

2

C1755

1

2

C1763

1

2

C1764

1

2

C1765

1

2

C1766

1

2

C1767

1

2

C1770

1

2

C1769

1

2

C1754

1

2

C1750

1

2

C172A

1

2

C1729

1

2

C1728

1

2

C1727

1

2

C1726

1

2

C1725

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

17 OF 132

16 OF 80

8

13

8

13

8

11 13 27

8

10 13 43

www.vinafix.vn

IN

OUT

OUT

BI

IN

IN
OUT
OUT

IN
IN
OUT
OUT

OUT

BI

OUT

BI

IN

IN

IN

IN

IN

OUT

OUT
OUT

OUT

OUT

IN

IN

OUT

OUT

BI

OUT
OUT

OUT
OUT

IN
IN

IN
IN

IN
IN

IN

IN

IN

IN

IN
OUT
OUT

IN

OUT
OUT
IN

OUT

OUT

OUT

OUT

OUT

OUT

BI
BI

OUT

BI

BI

NC

NC

IHDA

(1 OF 10)

JTAG

SATA

LPC

RTCSPI

HDA_SDIN2

HDA_SDIN0

HDA_SYNC

SPI_CS1*

JTAG_TMS

FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3

FWH4/LFRAME*

HDA_DOCK_EN*/GPIO33
HDA_DOCK_RST*/GPIO13

HDA_SDIN1

HDA_SDIN3

HDA_SDO

JTAG_TCK

JTAG_TDI

JTAG_TDO

LDRQ0*

LDRQ1*/GPIO23

RTCX2

SATA0GP/GPIO21

SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP

SATA1GP/GPIO19

SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP

SATA2RXN
SATA2RXP
SATA2TXN
SATA2TXP

SATA3COMPI
SATA3RBIAS

SATA3RCOMPO

SATA3RXN
SATA3RXP
SATA3TXN
SATA3TXP

SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP

SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP

SATAICOMPI

SATAICOMPO

SATALED*

SERIRQ

SPI_CLK

SPI_CS0*

SPI_MISO

SPI_MOSI

HDA_RST*

SPKR

RTCX1

HDA_BCLK

INTVRMEN

INTRUDER*

SRTCRST*

RTCRST*

IN

OUT

OUT

OUT

IN

C-LINK

SMBUS

PCI-E*

CLOCKS

FLEX

CLOCKS

(2 OF 10)

XTAL25_OUT

XTAL25_IN

XCLK_RCOMP

SML1DATA/GPIO75

SML1CLK/GPIO58

SML1ALERT*/PCHHOT*/GPIO74

SML0DATA

SML0CLK

SML0ALERT*/GPIO60

SMBDATA

SMBCLK

SMBALERT*/GPIO11

REFCLK14IN

PETP8

PETP7

PETP6

PETP5

PETP4

PETP3

PETP1

PETN8

PETN7

PETN6

PETN5

PETN4

PETN3

PETN2

PETN1

PERP8

PERP7

PERP6

PERP5

PERP4

PERP3

PERP1

PERN8

PERN6

PERN5

PERN4

PERN3

PERN2

PERN1

PEG_B_CLKRQ*/GPIO56

PEG_A_CLKRQ*/GPIO47

PCIECLKRQ7*/GPIO46

PCIECLKRQ6*/GPIO45

PCIECLKRQ5*/GPIO44

PCIECLKRQ4*/GPIO26

PCIECLKRQ3*/GPIO25

PCIECLKRQ2*/GPIO20

PCIECLKRQ1*/GPIO18

PCIECLKRQ0*/GPIO73

CL_RST1*

CL_DATA1

CL_CLK1

CLKOUT_PEG_B_P

CLKOUT_PEG_B_N

CLKOUT_PEG_A_P

CLKOUT_PEG_A_N

CLKOUT_PCIE7P

CLKOUT_PCIE7N

CLKOUT_PCIE6P

CLKOUT_PCIE6N

CLKOUT_PCIE5P

CLKOUT_PCIE5N

CLKOUT_PCIE4P

CLKOUT_PCIE4N

CLKOUT_PCIE3P

CLKOUT_PCIE3N

CLKOUT_PCIE2P

CLKOUT_PCIE2N

CLKOUT_PCIE1P

CLKOUT_PCIE1N

CLKOUT_PCIE0P

CLKOUT_PCIE0N

CLKOUT_ITPXDP_P

CLKOUT_ITPXDP_N

CLKOUT_DP_P

CLKOUT_DP_N

CLKOUT_DMI_P

CLKOUT_DMI_N

CLKOUTFLEX3/GPIO67

CLKOUTFLEX2/GPIO66

CLKOUTFLEX1/GPIO65

CLKOUTFLEX0/GPIO64

CLKIN_SATA_P

CLKIN_SATA_N

CLKIN_PCILOOPBACK

CLKIN_GND1_P

CLKIN_GND1_N

CLKIN_DOT_96P

CLKIN_DOT_96N

CLKIN_DMI_P

CLKIN_DMI_N

PERN7

PETP2

PERP2

OUT

OUT

OUT

OUT

OUT
OUT

IN

OUT
OUT

IN

IN

OUT
OUT

IN

IN

OUT
OUT

IN

OUT
OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPU)

(IPD-BOOT)

Connect to ENET_MEDIA_SENSE via alias if HDA = 3.3V.
Connect to ENET_MEDIA_SENSE via 12K R if HDA = 1.5V.
If HDA = S0, must also ensure that signal cannot be high in S3.

Unused clock terminations for FCIM Mode

(IPU-RSMRST#)

(IPD-PWROK)

(IPU/IPD)

(IPU)

(IPU)

(IPD)

(IPD-BOOT)

(IPD-BOOT)

(IPD)

DOES THIS NEED LENGTH MATCH???

VSel strap not functional (VCCVRM = 1.8V)

(IPD)

(IPU)

(IPD-PWROK)

(IPU)

(IPU)

(IPD-PWROK)

(IPD-PWROK)

1.8V -> 1.1V

(IPU-RSMRST#)

Controlled by PCIECLKRQ5#

(IPU/IPD)

(IPD-PLTRST#)

(IPD)

(IPD)

25 74

41 75

41 75

7

39 41

7

37 74

7

37 74

7

37 74

7

37 74

7

36 75

7

36 75

7

36 75

7

36 75

7

42 75

7

42 75

330K

MF

201

5%

1/20W

1M

MF
201

5%
1/20W

20K

MF

201

5%

1/20W

20K

MF
201

5%
1/20W

PLACE_NEAR=U1800.AB10:2.54mm

37.4

1/20W
MF
201

1%

10K

MF
201

5%
1/20W

PLACE_NEAR=U1800.AC49:2.54mm

90.9

MF

201

1%

1/20W

42 75

42 75

17

24

24

24

NO STUFF

0

MF

201

5%

1/20W

NO STUFF

0

MF

201

5%

1/20W

1K

MF
201

1%
1/20W

25 74

25

750

MF
201

1%
1/20W

PLACE_NEAR=U1800.AH4:2.54mm

PLACE_NEAR=U1800.AF12:2.54mm

MF
201

1%
1/20W

49.9

24

24

7

36 75

7

36 75

17 36

17

17

42 75

42 75

7

11 72

7

11 72

11 72

11 72

7

17 75

7

17 75

17 75

17 75

17 75

7

17 75

17 75

7

25 75

17

9

9

9

9

7

17 36

7

33 75

7

33 75

17 35

NO STUFF

10K

MF 2015%

1/20W

4.7K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

17 26

17

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

PLACE_NEAR=U1800.F35:1.27mm

33

MF 2015%

1/20W

PLACE_NEAR=U1800.K37:1.27mm

33

MF 2015%

1/20W

PLACE_NEAR=U1800.H35:1.27mm

33

MF 2015%

1/20W

PLACE_NEAR=U1800.H37:1.27mm

33

MF 2015%

1/20W

51 75

51 75

51 75

51 75

7

39 41 75

7

39 41 75

7

39 41 75

7

39 41 75

1/20W33MF 2015%

33

MF 2015%

1/20W

33

MF 2015%

1/20W

33

MF 2015%

1/20W

7

39 41 75

33

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

OMIT_TABLE

41 75

41 75

24

17 20

51 75

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

1.0UF

X5R

0201-MUR

20%

6.3V

1.0UF

X5R
0201-MUR

20%

6.3V

PLACE_NEAR=U1800.W49:5.1mm

604

MF201

1%

1/20W

7

36 75

7

36 75

7

75

7

75

7 9

75

7 9

75

7

36 75

7

36 75

7

36 75

7

36 75

9

9

9

9

7

7

7

7

7 9

75

7 9

75

17

SYNC_MASTER=J13_MLB

PCH SATA/PCIe/CLK/LPC/SPI

SYNC_DATE=09/15/2011

XDP_PCH_TDI

RTC_RESET_L

PCH_INTVRMEN_L

=PP1V05_S0_PCH

PCH_SATA3RBIAS

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

HDA_BIT_CLK

HDA_SYNC_R

PCH_SPKR

=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO

NC_PCIE_6_R2D_CP

NC_PCIE_5_D2RP

PCIE_AP_R2D_C_P

PCIE_AP_D2R_P

PCIE_ENET_R2D_C_N

PCIE_ENET_D2R_N
PCIE_ENET_D2R_P

PCIE_ENET_R2D_C_P

PCIE_FW_D2R_N

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

HDA_SDOUT

HDA_RST_L

HDA_SYNC

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

PCH_SATALED_L

TP_SATA_F_D2RN

TP_SATA_D_D2RP

TP_SATA_D_D2RN

NC_PCIE_5_R2D_CP

NC_PCIE_5_R2D_CN

NC_PCIE_5_D2RN

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

USB_EXTB_SEL_XHCI

SMBUS_PCH_CLK

DPLL_REF_CLK_P

DPLL_REF_CLK_N

TP_PCIE_CLK100M_PEGAP

DMI_CLK100M_CPU_N
DMI_CLK100M_CPU_P

PCIE_CLK100M_FW_P

PCIE_CLK100M_FW_N

PCIE_CLK100M_ENET_P

PCIE_CLK100M_ENET_N

NC_PCIE_8_R2D_CP

FW_CLKREQ_L

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

SSD_CLKREQ_L

TP_PCIE_CLK100M_PEBN

ENET_CLKREQ_L

PCIE_CLK100M_SSD_P

TP_PCIE_CLK100M_PEBP

PEG_CLK100M_N
PEG_CLK100M_P

PCIE_CLK100M_TBT_N

PCIE_CLK100M_SSD_N

PEG_CLKREQ_L

AP_CLKREQ_L

PEGCLKRQB_L_GPIO56

PCIE_CLK100M_AP_P

PCIE_CLK100M_AP_N

NC_PCIE_7_D2RP

JTAG_DPMUXUC_TRST_L

PCH_CLKIN_GNDN1

SML_PCH_0_DATA

NC_PCIE_6_D2RN
NC_PCIE_6_D2RP
NC_PCIE_6_R2D_CN

PCH_SPKR

AP_CLKREQ_L

JTAG_ISP_TMS

SYSCLK_CLK25M_SB_R

SYSCLK_CLK25M_SB

PCH_CLK96M_DOT_P

PCH_CLK96M_DOT_N

SML_PCH_1_CLK

PCH_SRTCRST_L
PCH_INTRUDER_L

PCH_CLKIN_GNDP1

PCIE_CLK100M_PCH_P

PCH_CLK100M_SATA_N

PCH_CLK96M_DOT_P

=PP3V3_S0_PCH

ITPCPU_CLK100M_P

PCIE_CLK100M_PCH_N

PCH_CLK100M_SATA_P

PCH_CLK96M_DOT_N

PCH_CLK14P3M_REFCLK

LPC_AD<0>

LPC_AD<3>

LPC_AD<2>

NC_PCIE_8_D2RN
NC_PCIE_8_D2RP

NC_PCIE_7_D2RN

NC_PCIE_7_R2D_CP

PCIE_AP_R2D_C_N

SML_PCH_0_CLK

USB_EXTD_SEL_XHCI

SML_PCH_1_DATA

TP_CLINK_CLK
TP_CLINK_DATA
TP_CLINK_RESET_L

PEGCLKRQA_L_GPIO47
TP_PCIE_CLK100M_PEGAN

PCIE_CLK100M_PCH_N

PCH_CLKIN_GNDN1
PCH_CLKIN_GNDP1

PCH_CLK100M_SATA_P

PCH_CLK100M_SATA_N

=PP1V05_S0_PCH_VCCDIFFCLK

PCH_XCLK_RCOMP

TP_PCH_GPIO64_CLKOUTFLEX0

TP_PCH_GPIO65_CLKOUTFLEX1

TP_PCH_GPIO66_CLKOUTFLEX2

=PPVRTC_G3_PCH

RTC_RESET_L

PCH_INTRUDER_L

PCH_INTVRMEN_L

HDA_BIT_CLK_R

HDA_RST_R_L

SPI_MOSI_R

SPI_MISO

TP_SATA_E_D2RN

TP_SATA_D_R2D_CN

TP_SATA_C_R2D_CP

TP_SATA_C_R2D_CN

TP_SATA_C_D2RP

TP_SATA_C_D2RN

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

TBT_PWR_EN_PCH

TP_LPC_DREQ0_L

XDP_PCH_TCK

HDA_SDOUT_R

TP_HDA_SDIN3

TP_HDA_SDIN1

ENET_MEDIA_SENSE_RDIV

JTAG_ISP_TMS

LPC_FRAME_R_L

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_AD_R<0>

HDA_SDIN0

TP_HDA_SDIN2

ITPCPU_CLK100M_N

SYSCLK_CLK25M_SB_R

LPC_FRAME_L

PCH_CLK33M_PCIIN

PCIE_FW_R2D_C_P

PCIE_FW_R2D_C_N

PCIE_FW_D2R_P

PCIE_EXCARD_D2R_N

=PP3V3_TBT_PCH_GPIO

TP_SATA_E_R2D_CP

PCIE_AP_D2R_N

SMBUS_PCH_DATA

SMBUS_PCH_ALERT_L

HDA_SDOUT_R

LPC_AD<1>

JTAG_DPMUXUC_TRST_L

TP_PCIE_CLK100M_PE4N
TP_PCIE_CLK100M_PE4P

TBT_CLKREQ_L

HDA_SYNC_R

ENET_MEDIA_SENSE_RDIV

USB_EXTD_SEL_XHCI

USB_EXTB_SEL_XHCI

SMBUS_PCH_ALERT_L

EXCARD_CLKREQ_L

FW_CLKREQ_L

PCH_SATALED_L
DP_AUXCH_ISOL

SATARDRVR_EN

SYSCLK_CLK32K_RTC

NC_PCIE_7_R2D_CN

PCIE_CLK100M_PCH_P

PCH_CLK14P3M_REFCLK

TP_PCH_GPIO67_CLKOUTFLEX3

PCIE_CLK100M_TBT_P

PCH_SRTCRST_L

EXCARD_CLKREQ_L

TP_SATA_E_D2RP
TP_SATA_E_R2D_CN

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>

HDA_BIT_CLK_R

LPC_FRAME_R_L

LPC_AD_R<3>

PEGCLKRQB_L_GPIO56

PEGCLKRQA_L_GPIO47

SSD_CLKREQ_L

TBT_CLKREQ_L

PEG_CLKREQ_L

ENET_CLKREQ_L

HDA_RST_R_L

XDP_PCH_TDO

XDP_PCH_TMS

SPI_CLK_R

SPI_CS0_R_L

TP_SPI_CS1_L

LPC_SERIRQ

=PP1V05_S0_PCH_VCCIO_SATA

TP_SATA_D_R2D_CP

PCH_SATAICOMP

NC_PCIE_8_R2D_CN

PCH_SATA3COMP

TP_SATA_F_R2D_CP

TP_SATA_F_D2RP
TP_SATA_F_R2D_CN

R1800

1

2

R1801

1

2

R1802

1

2

R1803

1

2

R1830

1

2

R1820

1

2

R1890

1

2

R1840

1 2

R1841

1 2

R1886

1

2

R1832

1

2

R1831

1

2

R1876

1 2

R1877

1 2

R1878

1 2

R1834

1 2

R1842

1 2

R1869

1 2

R1844

1 2

R1845

1 2

R1847

1 2

R1814

2 1

R1815

1 2

R1843

1 2

R1833

1 2

R1879

1 2

R1846

1 2

R1853

1 2

R1848

1 2

R1854

1 2

R1855

1 2

R1812

1 2

R1813

1 2

R1810

1 2

R1811

1 2

R1861

1 2

R1862

1 2

R1863

1 2

R1864

1 2

R1860

1 2

R1891

1 2

R1892

1 2

R1893

1 2

R1894

1 2

R1895

1 2

R1896

1 2

R1897

1 2

R1870

1 2

R1871

1 2

U1800

A37
A39
C39
C37
K40

H35

K35
M35

F35

D36
B36
C35
A35

K37

H37

K22

C21

M17

U12

M12

M15

H40
F37

F19

A19
C19

M2

AN3
AN1
AU3
AU1

R1

AN6
AN8
AR3
AR1

AD4
AD2
AL3
AL1

AF12
AH4

AF10

AD8
AD6
AG3
AG1

AE3
AE1
AH8
AH6

AC3
AC1
AJ3
AJ1

AB12

AB10

W10

Y4

AD12

AB8

AB6

Y2

W8

N1

A23

U1800

L3
J1
M8

BD17
BF17

M24
K24

BB26
AY26

E51

AK8
AK6

BB24
AY24

AN10
AN12

AR12
AR10

AD48
AD50

AE49
AE51

AD40
AD42

AA49
AA51

Y48
Y50

AB40
AB42

AB44
AB46

W44
W46

AF44
AF46

AF40
AF42

H50

D48

G49

J51

M4

U8

T4

B8

M19

K8

J3

H4

R8

C4

BJ33

BJ35

BH36

BJ37

BJ39

BH40

BJ41

BJ43

BL33

BL35

BK36

BL37

BL39

BK40

BL41

BL43

BB30

BB33

BF33

BD35

AY35

BD37

AY37

AY40

AY30

AY33

BD33

BF35

BB35

BF37

BB37

BB40

J49

H12
F17
F10

H22
K12
A9

C9
D12
C11

AC49

W49
W51

C1802

1

2

C1803

1

2

R1885

1 2

<BRANCH>

<SCH_NUM>

<E4LABEL>

18 OF 132

17 OF 80

17

17

8

23

17 75

17

8

18 19 20

8

18 19 20 25 35

7

7

24 72

24 72

17

7

7

7

7

7

7

7

7 9

75

7 9

75

7

17

7

7

17

7

17

17

7

7

7

17

17 36

17 20

17 74

17

17

17

7

17 75

17 75

17 75

8

23

11 72

7

17 75

7

17 75

17 75

17 75

7

7

7

7

7

7

7

17

7

17

17

8

21 23

9

9

9

8

18 21

17

17

17

17 75

17 75

7

7

7

7

7

7

7

17 25 75

7

7

17

17

17

17

17

7

11 72

17 74

8

20

7

17

17 25 75

7

7

17 75

17

17

17 26

17

17

17

17

24 25

24

7

9

17

7

7

17

17

17

17 75

17

17

17

17

17

17 35

17

7

17 36

17 75

7

8

23

7

74

7

74

7

7

7

www.vinafix.vn

IN

OUT

OUT
OUT

OUT
OUT

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

IN

OUT

IN

IN

IN

IN

IN

IN

IN

BI

OUT

OUT

OUT
OUT
OUT

OUT

IN

OUT

OUT

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN
IN
IN

IN

IN
IN
IN

OUT

FDI

(3 OF 10)

DMI

SYSTEM POWER

MANAGEMENT

DMI_ZCOMP

DMI3TXN

DMI2TXN

DMI1TXN

DMI0TXN

FDI_LSYNC1

DSWVRMEN

FDI_FSYNC1

FDI_FSYNC0

FDI_RXP5

FDI_RXP4

FDI_RXP3

FDI_RXP2

FDI_RXP1

FDI_RXP0

APWROK

CLKRUN*/GPIO32

DMI0RXN
DMI1RXN
DMI2RXN

DMI2RXP

DMI3RXN

DMI3RXP

DMI3TXP

DPWROK

DRAMPWROK

FDI_INT

FDI_LSYNC0

FDI_RXN0
FDI_RXN1
FDI_RXN2
FDI_RXN3
FDI_RXN4
FDI_RXN5
FDI_RXN6
FDI_RXN7

FDI_RXP6
FDI_RXP7

PMSYNCH

PWROK

SLP_A*

SLP_LAN*/GPIO29

SLP_S3*

SLP_S4*

SLP_S5*/GPIO63

SLP_SUS*

SUSACK*

SUSCLK/GPIO62

SUS_STAT*/GPIO61

SYS_PWROK

SYS_RESET*

WAKE*

RI*

BATLOW*/GPIO72

ACPRESENT/GPIO31

PWRBTN*

SUSWARN*/SUSPWRDNACK/GPIO30

RSMRST*

DMI1RXP

DMI0RXP

DMI_IRCOMP

DMI2RBIAS

DMI0TXP
DMI1TXP
DMI2TXP

(4 OF 10)

LVDS

DIGITAL DISPLAY INTERFACE

CRT

LVDSA_DATA0*
LVDSA_DATA1*

LVDSB_DATA3*

LVDSB_DATA2*

CRT_BLUE

CRT_DDC_CLK
CRT_DDC_DATA

CRT_GREEN

CRT_HSYNC

CRT_IRTN

CRT_RED

CRT_VSYNC

DAC_IREF

DDPB_0N
DDPB_0P
DDPB_1N
DDPB_1P
DDPB_2N
DDPB_2P
DDPB_3N
DDPB_3P

DDPB_AUXN
DDPB_AUXP

DDPB_HPD

DDPC_0N
DDPC_0P
DDPC_1N
DDPC_1P
DDPC_2N
DDPC_2P
DDPC_3N
DDPC_3P

DDPC_AUXN
DDPC_AUXP

DDPC_CTRLCLK

DDPC_CTRLDATA

DDPC_HPD

DDPD_0N
DDPD_0P
DDPD_1N
DDPD_1P
DDPD_2N
DDPD_2P
DDPD_3N
DDPD_3P

DDPD_AUXN
DDPD_AUXP

DDPD_CTRLCLK

DDPD_CTRLDATA

DDPD_HPD

LVDSA_CLK

LVDSA_CLK*

LVDSA_DATA2*
LVDSA_DATA3*

LVDSA_DATA0
LVDSA_DATA1

LVDSA_DATA3

LVDSB_CLK

LVDSB_CLK*

LVDSB_DATA0*
LVDSB_DATA1*

LVDSB_DATA0
LVDSB_DATA1
LVDSB_DATA2
LVDSB_DATA3

LVD_VREFH
LVD_VREFL

L_DDC_CLK
L_DDC_DATA

SDVO_CTRLCLK

SDVO_CTRLDATA

SDVO_INTN
SDVO_INTP

SDVO_STALLN
SDVO_STALLP

SDVO_TVCLKINN
SDVO_TVCLKINP

L_BKLTEN
L_VDD_EN

L_BKLTCTL

LVD_IBG
LVD_VBG

LVDSA_DATA2

L_CTRL_CLK
L_CTRL_DATA

NC
NC
NC
NC

NC

NC

NC
NC

NC

NC

NC
NC

NC

NC

NC
NC

NC

NC

NC

NC
NC

NC

NC

NC

NC

NC

NC
NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(IPU)

(IPU)

(IPU)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPD)
(IPD)

(IPD)
(IPD)

(IPD)
(IPD)

(IPD-DeepS4/S5)

(IPD-PLTRST#)

7

10 72

10 72

10 72

10 72

10 72

10 72

PLACE_NEAR=U1800.BF19:12.7mm

1/20W

1%

201

MF

49.9

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

7

10 72

1/20W

5%

201

MF

1K

PLACE_NEAR=U1800.R51:2.54mm

1%

201

MF

750

PLACE_NEAR=U1800.BK20:2.54mm

1/20W

1/20W

5%

201

MF

390K

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

0

18 66

1/20W

5%

201

MF

100K

7

25 39

24 39 66

11 27 72

25 66

66

66

18 24 39

39 40 66

40

7

18 36

7

18 39 41

7

25 39 41

40

18 39 66

7

18 27 36 38 39 66

7

18 27 36 39 66

11 72

39

9

9

9

7

10 72

10 72

10 72

10 72

7

10 72

10 72

10 72

10 72

10 72

10 72

10 72

7

10 72

7

10 72

10 72

10 72

10 72

1/20W

5% 201MF

100K

1/20W

5% 201MF

1K

1/20W

5% 201MF

8.2K

1/20W

5% 201MF

1K

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

1/20W

5%

201

MF

10K

1/20W

5% 201MF

10K

18

BGA

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

QP8D-MM915462

BGA

QP8D-MM915462

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

1/20W

5%

201

MF

100K

SYNC_DATE=09/15/2011

SYNC_MASTER=J13_MLB

PCH DMI/FDI/PM/Graphics

PCIE_WAKE_L

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

TP_PM_SLP_A_L

PM_SLP_SUS_L

PM_SYNC

PCH_GPIO29

LPC_PWRDWN_L

PCH_DSWVRMEN

FDI_INT

FDI_DATA_P<7>

SMC_ADAPTER_EN

PCH_DMI2RBIAS

FDI_DATA_N<1>

TP_CRT_IG_VSYNC

TP_DP_IG_D_MLP<1>

TP_DP_IG_D_MLN<1>

TP_DP_IG_D_MLN<0>

TP_DP_IG_D_AUXN

TP_DP_IG_C_MLP<1>

TP_DP_IG_C_MLN<1>

DPB_IG_DDC_DATA

TP_DP_IG_B_MLP<2>

TP_DP_IG_B_MLN<0>
TP_DP_IG_B_MLP<0>

DPA_IG_HPD

DPA_IG_AUX_CH_P

LVDS_IG_BKL_PWM

LVDS_IG_PANEL_PWR

DPA_IG_DDC_DATA

DPA_IG_AUX_CH_N

PM_RSMRST_L

PM_SLP_SUS_L

=PP3V3_SUS_PCH_GPIO

PM_PWRBTN_L
PM_CLKRUN_L
PCH_GPIO29

PM_SLP_S5_L

PCH_SUSWARN_L

PCH_DMI_COMP

=PP3V3_SUS_PCH_GPIO

TP_CRT_IG_GREEN

PCH_DAC_IREF

TP_DP_IG_B_MLN<1>

TP_DP_IG_B_MLN<2>

TP_DP_IG_B_MLN<3>
TP_DP_IG_B_MLP<3>

TP_DP_IG_C_MLN<0>

TP_DP_IG_C_MLN<2>

TP_DP_IG_C_MLN<3>
TP_DP_IG_C_MLP<3>

DPB_IG_AUX_CH_N
DPB_IG_AUX_CH_P

DPB_IG_DDC_CLK

DPB_IG_HPD

TP_DP_IG_D_MLP<0>

TP_DP_IG_D_MLN<2>

TP_DP_IG_D_MLN<3>
TP_DP_IG_D_MLP<3>

TP_DP_IG_D_AUXP

TP_DP_IG_D_CTRL_CLK
TP_DP_IG_D_CTRL_DATA

TP_DP_IG_D_HPD

DPA_IG_DDC_CLK

TP_SDVO_STALLN
TP_SDVO_STALLP

TP_SDVO_TVCLKINN

PM_CLK32K_SUSCLK_R

FDI_DATA_P<6>

FDI_DATA_P<5>

FDI_FSYNC<1>

FDI_LSYNC<1>

FDI_LSYNC<0>

=PPVRTC_G3_PCH

DMI_S2N_N<3>

DMI_S2N_N<1>

DMI_S2N_N<0>

PM_PCH_APWROK

PM_CLKRUN_L

DMI_N2S_N<0>
DMI_N2S_N<1>
DMI_N2S_N<2>

DMI_N2S_P<2>

DMI_N2S_N<3>

DMI_N2S_P<3>

PM_MEM_PWRGD

FDI_DATA_N<0>

FDI_DATA_N<2>
FDI_DATA_N<3>
FDI_DATA_N<4>

FDI_DATA_N<6>

PM_PCH_PWROK

PCH_SUSACK_L

PM_PCH_SYS_PWROK

PM_SYSRST_L

PCIE_WAKE_L

PM_BATLOW_L

PM_PWRBTN_L

PCH_SUSWARN_L

DMI_N2S_P<1>

DMI_N2S_P<0>

DMI_S2N_P<0>
DMI_S2N_P<1>

PM_DSW_PWRGD

=PP1V05_S0_PCH_VCCIO_PCIE

FDI_DATA_P<0>

DMI_S2N_N<2>

DMI_S2N_P<2>
DMI_S2N_P<3>

FDI_FSYNC<0>

FDI_DATA_P<4>

FDI_DATA_N<7>

FDI_DATA_P<3>

FDI_DATA_P<2>

FDI_DATA_P<1>

FDI_DATA_N<5>

TP_CRT_IG_BLUE

TP_CRT_IG_RED

TP_CRT_IG_DDC_CLK

TP_CRT_IG_HSYNC

PM_SLP_S3_L
PM_SLP_S4_L

=PP3V3_S0_PCH_GPIO
=PP3V3_S5_PCH

=PP3V3_SUS_PCH_GPIO

PCH_SUSACK_L

TP_CRT_IG_DDC_DATA

TP_DP_IG_D_MLP<2>

TP_SDVO_TVCLKINP

TP_SDVO_INTP

LVDS_IG_BKL_ON

TP_DP_IG_B_MLP<1>

TP_DP_IG_C_MLP<2>

TP_DP_IG_C_MLP<0>

TP_SDVO_INTN

PCH_RI_L

R1900

1

2

R1951

1

2

R1920

1

2

R1915

1

2

R1905

1

2

R1986

12

R1909

1

2

R1923

2 1

R1925

1 2

R1991

1 2

R1985

1 2

R1922

2 1

R1921

2 1

R1924

2 1

R1983

1

2

R1982

1 2

U1800

H19

G3

H10

T2

BL21

BJ21

BD22

BF22

BL23

BJ23

BB22

AY22

BK20

BJ19

BL19

BB19

AY19

BL17

BJ17

BB17

AY17

BD19

BF19

A21

B12

F22

BH12
BK8

BB10

BK12
BH8

BL13
BJ15
BD12
BJ11
AY15
AY12
BJ9
BF10

BJ13
BL15
BF12
BL11
BB15
BB12
BL9
BD10

BB8

K19

M22

F12

B20

C7

A7

D4

K10

F6

A15

G6

F15

D3

C13

M10

L1

D8

U1800

M46

R49
N49

R46

M50

T48

U46

N51

R51

AY48
AY50
AY44
AY46
BB44
BB46
BA49
BA51

AW51
AW49
AY42

BC49
BC51
BD48
BD50
BF46
BF45
BE49
BE51

AU51
AU49

T50
U44

BE46

BG51
BG49
BF42
BD42
BJ47
BL47
BL45
BJ45

AU46
AU44

M48
U42

BK44

L49

M44

R42
M40

L51
K46

M42

AH42
AH40

AG51
AG49

AK46

AK44

AR44

AR46

AN51

AN49

AN46

AN44

AK42

AK40

AH44

AH46

AM48

AM50

AL51

AL49

AJ49

AJ51

AH48

AH50

W42
R44

AT50
AT48

AR51
AR49

AU40
AU42

R1955

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

19 OF 132

18 OF 80

7

18 36

7

7

9

9

9

9

9

9

9

9

9

9

9

9

9

9

18 66

8

17 18 19 20

18 24 39

7

18 39 41

18

18 39 66

18

8

17 18 19 20

7

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

9

7

7

7

8

17 21

18

18

8

7

7

7

7

7

18 27 36 39 66

7

18 27 36 38 39 66

8

17 19 20 25 35

8

8

17 18 19 20

18

7

9

7

7

9

9

9

7

www.vinafix.vn

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC

NC
NC
NC

NC

NC

NC

BI

BI

BI

BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

OUT
OUT

IN
IN
IN

IN
IN
IN
IN

IN

OUT

IN

BI

IN

(5 OF 10)

USB

PCI

PME*

PLTRSTB*

PIRQA*

TP2

TP5

TP4

TP11

USB3RN4

USB3RN2

CLKOUT_PCI0
CLKOUT_PCI1
CLKOUT_PCI2
CLKOUT_PCI3
CLKOUT_PCI4

GNT1*/GPIO51
GNT2*/GPIO53
GNT3*/GPIO55

OC0*/GPIO59
OC1*/GPIO40
OC2*/GPIO41
OC3*/GPIO42
OC4*/GPIO43

OC5*/GPIO9
OC6*/GPIO10
OC7*/GPIO14

PIRQB*
PIRQC*
PIRQD*

PIRQE*/GPIO2
PIRQF*/GPIO3
PIRQG*/GPIO4
PIRQH*/GPIO5

REQ1*/GPIO50
REQ2*/GPIO52
REQ3*/GPIO54

RSVD

TP1

TP3

TP6
TP7
TP8
TP9
TP10

TP12
TP13
TP14
TP15
TP16
TP17
TP18
TP19
TP20
TP21
TP22
TP23
TP24

TP41
TP42

USB3RN1

USB3RN3

USB3RP1
USB3RP2
USB3RP3
USB3RP4

USB3TN1
USB3TN2
USB3TN3
USB3TN4

USB3TP1
USB3TP2
USB3TP3
USB3TP4

USBP0N
USBP0P

USBP10N
USBP10P

USBP11N
USBP11P

USBP12N
USBP12P

USBP1N
USBP1P

USBP2N
USBP2P

USBP3N
USBP3P

USBP4N
USBP4P

USBP5N
USBP5P

USBP6N
USBP6P

USBP7N
USBP7P

USBP8N
USBP8P

USBP9N
USBP9P

USBRBIAS

USBRBIAS*

USBP13P

USBP13N

NC

NC

NC
NC

BI

BI
BI

OUT

OUT

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ext A (XHCI/EHCI)

USB Hub (All LS/FS Devices)

RSVD: BT (HS)

(IPU-PCIERST#)

(IPU)

(IPD)

(IPD)

Unused

RSVD: SD

Ext B (EHCI)

Ext D (EHCI)

Unused

Unused

Redundant to pull-up on audio page

RSVD: WiFi

Ext B (XHCI)

Ext C (XHCI/EHCI)

Ext D (XHCI) (Mobiles: Trackpad)

Camera

Redundant to pull-up on audio page

26 74

26 74

9

9

9

9

26 74

26 74

26 74

26 74

26 74

26 74

7

38 74

7

38 74

7

38 74

38 74

9

9

9

9

7

36 74

7

36 74

36 74

36 74

9

9

9

9

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

19

19

19

19

19 55

19 33

19 54

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

19 24

19 24

19 24

19 24

19 24

24

24

38 74

24

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

38 74

32 74

32 74

PLACE_NEAR=U1800.A33:2.54mm

22.6

MF
201

1%
1/20W

25 27

25

25 75

25

SYNC_DATE=09/15/2011

PCH PCI/USB/TP/RSVD

SYNC_MASTER=J13_MLB

TP_PCI_CLK33M_OUT3

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

USB_EXTD_XHCI_P

USB_EXTB_XHCI_P

USB_EXTC_P

USB_EXTC_N

USB_EXTA_P

USB_EXTB_XHCI_N

USB_EXTD_XHCI_N

=PP3V3_SUS_PCH_GPIO
=PP3V3_S3_PCH_GPIO
=PP3V3_S0_PCH_GPIO

=PP3V3_S0_PCH_GPIO

AUD_IP_PERIPHERAL_DET
TBT_PWR_REQ_L

AUD_I2C_INT_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

AP_PWR_EN

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

PCI_INTB_L

USB_EXTB_EHCI_P

USB_EXTD_EHCI_N

USE_HDD_OOB_L

BLC_I2C_MUX_SEL

TP_USB_WLANN

USB_EXTA_N

TP_USB_4N
TP_USB_4P

TP_USB_SDN
TP_USB_SDP

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L
XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L
XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB2_PCH_GPIO10_AP_PWR_EN

TP_USB_13N
TP_USB_13P

USB_EXTD_EHCI_P

USB_EXTB_EHCI_N

USB_CAMERA_N

USB_HUB_UP_N

TP_USB_12P

TP_USB_BT_HSN
TP_USB_BT_HSP

TP_USB_12N

TP_PCH_TP23

USB3_EXTB_RX_N

USB3_EXTC_RX_N

USB3_EXTA_RX_N

USB3_EXTC_RX_P

USB3_EXTD_RX_P

USB3_EXTB_RX_P

USB3_EXTA_TX_N
USB3_EXTC_TX_N
USB3_EXTB_TX_N
USB3_EXTD_TX_N

USB3_EXTB_TX_P

USB3_EXTC_TX_P

USB3_EXTA_TX_P

USB3_EXTD_TX_P

PCI_INTC_L

PCI_INTA_L

PCI_INTD_L

LPC_CLK33M_SMC_R

TP_PCI_CLK33M_OUT2

LPC_CLK33M_LPCPLUS_R

PCH_CLK33M_PCIOUT

TP_PCI_PME_L
PLT_RESET_L

AUD_IP_PERIPHERAL_DET

AUD_I2C_INT_L

USB3_EXTD_RX_N

USB_HUB_UP_P

TP_USB_WLANP

USB3_EXTA_RX_P

USB_CAMERA_P

PCH_USB_RBIAS

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

JTAG_GMUX_TMS

BLC_GPIO

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

TBT_PWR_REQ_L

BLC_GPIO

PCH_STRP_TOPBLK_SWP_L

TP_PCH_STRP_ESI_L

TP_PCH_STRP_BBS1

USE_HDD_OOB_L

BLC_I2C_MUX_SEL

JTAG_GMUX_TMS

R2070

1

2

R2067

2 1

R2068

1 2

R2061

1 2

R2062

1 2

R2033

1 2

R2060

1 2

R2030

1 2

R2018

1 2

R2016

1 2

R2017

1 2

R2014

1 2

R2031

1 2

R2010

1 2

R2011

1 2

R2012

1 2

R2013

1 2

R2054

2 1

R2069

1 2

U1800

G51
E49
H48
J43
G45

F42
H42
D44

C17
A17
A13
D16
A11
B16
C23
H15

D49
C48
C47
C45

A47
C41
F45
F40

F7

H2

G46
K44
F46

AU6
AU8

BB6
BC1
BC3
BD2
BD4
BE1
BE3
BE6
BF6
BF7

AW1

BG1
BG3
BH3
BH4
BJ4
BJ5
BJ7
BK6
BL5

AW3
AY2
AY4
AY6
AY8
BA1
BA3

BH24

D20
M30

E3
AM4
AT4
AT2

AD10

B24
D24

AD44

BK24

AD46
BJ48

BL7
W40
K30

BH20
BK16

BH49
BB42

BH16
AN42
AN40
AR40
AR42

BJ25
BJ27
BJ31
BJ29

BL25
BL27
BL31
BL29

BF26
BB28
BF28
BF30

BD26
AY28
BD28
BD30

F24
H24

C31
A31

H33
F33

H30
F30

M33
K33

C25
A25

C27
A27

H28
F28

M26
K26

D28
B28

H26
F26

D32
B32

M28
K28

C29
A29

A33

C33

<BRANCH>

<SCH_NUM>

<E4LABEL>

20 OF 132

19 OF 80

7

19 24

8

17 18 20

8

25

8

17 18 19 20 25 35

8

17 18 19 20 25 35

19 55

19 33

19 54

19 24

19 24

19 24

24 36 66

19

19

9

9

9

9

9

9

9

9

9

9

9

7

7

7

9

74

19

19

19 24

7

7

www.vinafix.vn

OUTOUT

BI

IN

NC

IN

OUT

OUT

OUT

IN

BI

IN

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

BI

IN

OUT

NCTF

CPU/MISC

(6 OF 10)

GPIO

GPIO1
GPIO6

VSS_NCTF

VSS_NCTF

TS_VSS4

TS_VSS3

TS_VSS2

TS_VSS1

THRMTRIP*

STP_PCI*/GPIO34

SATA3GP/GPIO37

SATA2GP/GPIO36

RCIN*

PROCPWRGD

PECI

NC_1

INIT3_3V*

GPIO71

GPIO70

GPIO69

GPIO68

GPIO35

GPIO8

GPIO7

DF_TVS

A20GATE

GPIO24
GPIO27
GPIO28

BMBUSY*/GPIO0

LAN_PHY_PWR_CTRL/GPIO12
GPIO15
SATA4GP/GPIO16
GPIO17
SCLOCK/GPIO22

SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
SATA5GP/GPIO49
GPIO57

OUT

IN

IN

D

S G

D

S G

IN

OUT

OUT

NC

08

NC

IN

D

S G

D

S G

OUT

IN

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

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A

NOTICE OF PROPRIETARY PROPERTY:

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PAGE TITLE

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IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

THIS SIGNAL IS INTENDED FOR FIRMWARE HUB AND WE ARE NOT USING IT.

TBT_PWR_EN goes high for JTAG Programming

This has internal pull up and should not pulled low.

(IPD-PLTRST#)

(IPD-PLTRST#)

(IPU-RSMRST#)

(IPD-PLTRST#?)

(IPU)

(IPU-DeepS4/S5)

(IPU)

(IPD)

DF_TVS:DMI & FDI Term Voltage
Set to Vss when Low
Set to Vcc when High

Must stuff R2197 when R2180 NO STUFFed.

(IPU-RSMRST#)

NOTE: TCK from PCH is Push-Pull CMOS
NOTE: TMS/TDI from PCH is Open Drain
NOTE: TDO from CR is Push-Pull CMOS

JTAG Isolation due to glitch in and out of sleep

Systems with chip-down memory should add pull-downs on another page and set straps per software.

Systems with no chip-down memory should pull all 4 RAMCFG GPIOs high.

R2574 is 1K series resistor between U2100 output and PCH input to reduce the current between the two drivers..

11 24 72 24

7

20 41

20

1/20W

201

NO STUFF

1K

MF

5%

20

24

20

24

20

7

20 41 50

11 40 72

1/20W

RAMCFG3:H

10K

MF

201

5%

RAMCFG2:H

10K

MF
201

5%
1/20W

RAMCFG1:H

10K

MF

201

5%

1/20W

RAMCFG0:H

10K

MF
201

5%
1/20W

20 39

24

20

20 39

20 25

1K

MF

201

5%

1/20W

2.2K

MF
201

5%
1/20W

20K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

10K

MF 2015%

1/20W

100K

MF 2015%

1/20W

10K

MF 2015%

1/20W

MF 2015%

1/20W

10K

10K

MF 2015%

1/20W

24

MF

1/20W

5%

201

0

35

20 24

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

10K

MF 2015%

1/20W

NO STUFF

43

MF 201

5%

1/20W

0

MF 201

5%

1/20W

390

MF 201

5%

1/20W

11 40 72

24

20

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

BGA

20

20

17

10K

MF
201

5%
1/20W

201

1/20W

5%
MF

10K

SSM6N15AFE

SOT563

CRITICAL

MF

5%
1/20W

201

10K

SOT563

SSM6N15AFE

CRITICAL

10K

MF
201

5%
1/20W

201

MF

5%

10K

1/20W

33

33

1/20W

5%

201

MF

10K

33

5%
MF

1/20W
201

10K

CRITICAL

74LVC1G08

SOT891

X5R-CERM

0201

16V

10%

0.1UF

33

SSM6N15AFE

SOT563

CRITICAL

1/20W

5%

201

MF

10K

SSM6N15AFE

SOT563

CRITICAL

1/20W
201

5%
MF

10K

33 24

24

24

RAMCFG_SLOT

RAMCFG3:H,RAMCFG2:H,RAMCFG1:H,RAMCFG0:H

SYNC_MASTER=J13_MLB

SYNC_DATE=09/15/2011

PCH GPIO/MISC/NCTF

FW_PWR_EN_PCH

SPIROM_USE_MLB

TBT_CIO_PLUG_EVENT_ISOL

LPCPLUS_GPIO

PCH_A20GATE

XDP_FC1_TBT_CIO_PLUG_EVENT

TBT_GO2SX_BIDIR

SMC_RUNTIME_SCI_L

WOL_EN

JTAG_ISP_TCK JTAG_TBT_TCK

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TDO

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TDI

TBT_SW_RESET_R_L

=PP3V3_S0_PCH_STRAPS

JTAG_ISP_TDO

=PP3V3_S0_PCH_STRAPS

=PP3V3_TBT_PCH_GPIO

JTAG_TBT_TMS

=PP3V3_S0_PCH_STRAPS

JTAG_ISP_TMS

=PP3V3_S0_PCH_STRAPS

JTAG_ISP_TDI

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

TBT_SW_RESET_L

LPCPLUS_GPIO

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

DPMUX_UC_IRQ

FW_PME_L

TP_PCH_GPIO8

PCH_RCIN_L

PCH_PROCPWRGD

PCH_INIT3V3_L

PCH_A20GATE

=PP3V3_S0_PCH_GPIO

=PP3V3_SUS_PCH_GPIO
=PP3V3_S0_PCH_GPIO

WOL_EN

ENET_LOW_PWR_PCH

=PP3V3_S5_PCH_GPIO

SMC_RUNTIME_SCI_L

FW_PME_L

PCH_RCIN_L

=PP1V8_S0_PCH_VCC_DFTERM

CPU_PROC_SEL_L

CPU_PECI

CPU_PWRGD

ODD_PWR_EN_L

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

SMC_WAKE_SCI_L

TBT_GO2SX_BIDIR

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_DC1_PCH_GPIO35_MXM_GOOD

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK
JTAG_ISP_TDO
JTAG_ISP_TDI

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

TBT_SW_RESET_R_L

ODD_PWR_EN_L

DPMUX_UC_IRQ
AUD_IPHS_SWITCH_EN_PCH

SPIROM_USE_MLB

FW_PWR_EN_PCH

=PP3V3_S0_PCH_GPIO

PM_THRMTRIP_L_R

TBT_CIO_PLUG_EVENT

PM_THRMTRIP_L

PCH_DF_TVS

PCH_PECI

=PP3V3_TBT_PCH_GPIO

SMC_WAKE_SCI_L

MLB_RAMCFG0

MLB_RAMCFG1

MLB_RAMCFG2

MLB_RAMCFG3

R2130

1

2

R2172

1

2

R2173

1

2

R2174

1

2

R2175

1

2

R2178

12

R2179

1

2

R2111

2 1

R2195

2 1

R2191

1 2

R2192

1 2

R2193

1 2

R2194

1 2

R2184

1 2

R2197

1 2

R2190

1 2

R2196

1 2

R2185

1 2

R2112

2 1

R2180

1 2

R2198

2 1

R2116

2 1

R2150

1 2

R2155

1 2

R2170

1 2

R2140

1 2

R2156

1 2

U1800

U3

W1

BC7

B40

K6

B44

K15
C15

G1

W12

K17

C43

K42
A43

A45

D40
A41

H17

R6

C5

U40

AU12

AU10

U6

W6
M6

AA3

AA1

W3

U10

U1

N3

R3

BC9

AK10
AH12
AK12
AH10

A4
A5

BJ51

BL1
BL3
BL4

BL48
BL49
BL51
C3
C49
C51

A48

D1
D51
E1

A49
A51
BH1

BH51

BJ1
BJ3

BJ49

R2186

1

2

R2199

1

2

Q2160

3

5

4

R2188

1

2

Q2160

6

2

1

R2162

1

2

R2161

1

2

R2163

1

2

R2160

1

2

U2100

2

1

3

6

4

C2113

1

2

Q2162

6

2

1

R2164

1

2

Q2162

3

5

4

R2113

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

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20

8

20

7

20

20

8

17 18 19 20 25 35

8

17 18 19

8

17 18 19 20 25 35

20

9

24 25

8

20 39

20

20

8

21 23

11 72

20

20 24

20 39

20 33

20

20

24 25

7

20 41 50

20 25

8

17 18 19 20 25 35

40

8

17 20

9

9

9

9

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NC

NC

VCC CORE

LVDS

(7 OF 10)

DMI

DFT/SPI

CRTFDI

VCCIO

VCCCORE

VCC3_3

VCCADAC

VCCADMI_VRM

VCCAFDIPLL
VCCAFDI_VRM

VCCALVDS

VCCDFTERM

VCCDMI

VCCIO

VCCSPI

VCCTX_LVDS

VSSALVDS

VSSA_DAC

VCCAPLLEXP

VCCACLK

V_PROC_IO

VCCCLKDMI

VCCRTC

DCPSUSBYP

VCCDSW3_3

VCCAPLLDMI2

DCPRTC

VCCADPLLB

VCCADPLLA

VCCDIFFCLKN

DCPSST

V5REF

V5REF_SUS

VCCAPLL_SATA3

VCCASW

VCCIO

VCCPUSB

VCCSSC

VCCSUS3_3

VCCSUSHDA

VCCVRM

DCPSUS

USB

SATA

PCI/GPIO/LPC

(8 OF 10)

HDA

CLK/MISC

CPURTC

NC

NC
NC

NC

NC

NC
NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

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D

8 7 6 5 4 3

C

B

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NOTICE OF PROPRIETARY PROPERTY:

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A

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PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

55mA Max, 5mA Idle

PCH output, for decoupling only

VCCACLK pin left as NC per DG

10 mA Max, 1mA Idle

NC-ed per DG

PCH output, for decoupling only

1.44 A Max, 474mA Idle

AL24 left as NC per DG

VCCAPLLDMI2 pin left as NC per DG

BGA

QP8D-MM915462

OMIT_TABLE

pwrterm2gnd

pwrterm2gnd

pwrterm2gnd

pwrterm2gnd

pwrterm2gnd

pwrterm2gnd

PCH-PPT-MB-SFF-ES1

BGA

QP8D-MM915462

PCH-PPT-MB-SFF-ES1

OMIT_TABLE

PLACE_NEAR=U1800.N16:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.N16:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.U17:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.N16:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.R15:2.54mm

0.1UF

X5R-CERM

16V

10%

0201

SYNC_DATE=09/15/2011

SYNC_MASTER=J13_MLB

PCH POWER

=PP3V3_SUS_PCH_VCCSUS_USB

=PP5V_S0_PCH_V5REF

=PP3V3R1V5_S0_PCH_VCCSUSHDA

PP3V3_S0_PCH_VCC3_3_CLK_F

=PP1V05_S0_PCH_VCC_CORE

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_S5_PCH_VCCDSW

=PP5V_SUS_PCH_V5REFSUS

PP1V05_S0_PCH_VCCADPLLB_F

PP1V05_S0_PCH_VCCADPLLA_F

PP3V3_S0_PCH_VCCA_DAC_F

=PP1V8R1V5_S0_PCH_VCCVRM

=PP1V05_S0_PCH_VCC_DMI

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3_S0_PCH_VCC3_3

=PP1V8_S0_PCH_VCC_DFTERM

=PP1V8R1V5_S0_PCH_VCCVRM

=PP3V3_SUS_PCH_VCC_SPI

TP_1V05_S0_PCH_VCCAPLLEXP

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCIO

TP_PPVOUT_PCH_DCPSUSBYP

=PP1V05_S0_PCH_VCCDIFFCLK

=PPVRTC_G3_PCH

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_V_PROC_IO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm
VOLTAGE=3.3V

PPVOUT_G3_PCH_DCPRTC

PP1V05_S0_PCH_VCCCLKDMI_F

PPVOUT_S0_PCH_DCPSST

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.2 mm
VOLTAGE=3.3V

=PP1V05_S0_PCH_VCCSSC

U1800

AB19
AC19
AF6
BK28
R40
T39
U37
V37
V39

U51

AU21

AU19

AP13
AP15

AF33
AG33

AP19

AB21
AB23

AG25
AG27
AJ21
AJ23
AJ25
AJ27
AJ29
AJ31
AK29
AK31

AC21

AK33
AM33
AM35

AC23
AE21
AE23
AF21
AF23
AG21
AG23

AJ13
AJ15
AK15
AL13

AM23
AU15
AW16

AP27
AR15
AR23
AR25
AR27
AR29
AT13
AU23
AU25
AU27
AU29
AU35
AW34

AM21

Y19

AF37
AG37
AG39
AJ37

V50

AC33
AE33

U1800

R15
U15

U17

AR33
AU31
AU33
V13

R10

N36

M37

AM17

AC51

BF40
BD40

AM2

AW31

AB27
AB29

U19
U21
V19
V21
V23
V25
Y21
Y23

Y25

Y27

AB31

Y29
Y31

AC27
AC29
AC31
AE27
AE29
AE31

R19

AP39

AC37
AE37
AE39

R12

AA13
AB15
AC13

N18
R23
R25
U23
U25

AC15
AF15
AG13
AG15
AJ17
AK21

U27
U29

N16

AC35

AM27
N27
R27
R29
R33
R35
U33
U35

V31

AC39
AE19
AF17
AW18
AW21

C2232

1

2

C2233

1

2

C2222

1

2

C2231

1

2

C2210

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

22 OF 132

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23

23

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21

8

23

8

21

8

23

8

20 23

8

21

8

23

7

8

21 23

8

21 23

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17 18

8

23

8

23

23

8

23

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VSSVSS

(10 OF 10)

VSSVSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

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NOTICE OF PROPRIETARY PROPERTY:

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12

D

A

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PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

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SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

BGA

PCH-PPT-MB-SFF-ES1

QP8D-MM915462

OMIT_TABLE

BGA

QP8D-MM915462

OMIT_TABLE

PCH-PPT-MB-SFF-ES1

PCH GROUNDS

SYNC_DATE=09/15/2011

SYNC_MASTER=J13_MLB

U1800

AA7
AA9

AB25

AP25
AP29
AP31
AP33
AP35
AP37
AP41
AP43
AP45
AP48

AB33

AP50
AR6
AR8
AR17
AR19
AR21
AR31
AR35
AR37
AT7

AB35

AT9
AT11
AT39
AT41
AT43
AT45
AU17
AU37
AV2
AV4

AB37

AV48
AV50
AW7
AW9
AW11
AW13
AW23
AW25
AW27
AW29

AB48

AW36
AW39
AW41
AW43
AW45
AY10
B6
B10
B14
B18

AB50

B22
B26
B30
B34
B38
B42
B46
BA7
BA9
BA11

AC7

BA13
BA16
BA18
BA21
BA23
BA25
BA27
BA29
BA31
BA34

AC9

BA36
BA39
BA41
BA43
BA45
BB2
BB4
BB48
BB50
BC11

AC11

BC13
BC16
BC18
BC21

AC17

AA11

AC25
AC41
AC43
AC45

AE7

AE9
AE11
AE13
AE15
AE17

AA39

AE25
AE35
AE41
AE43
AE45

AF2

AF4

AF8
AF19
AF25

AA41

AF27
AF29
AF31
AF35
AF48
AF50

AG7

AG9
AG11
AG17

AA43

AG19
AG29
AG31
AG35
AG41
AG43
AG45

AH2

AJ7

AJ9

AA45

AJ11
AJ19
AJ33
AJ35
AJ39
AJ41
AJ43
AJ45

AK2

AK4

AB2

AK17
AK19
AK23
AK25
AK27
AK35
AK37
AK48
AK50

AL7

AB4

AL9
AL11
AL39
AL41
AL43
AL45
AM15
AM19
AM25
AM29

AB17

AM31
AM37

AP2
AP4
AP7
AP9
AP11
AP17
AP21
AP23

U1800

BC23
BC25
BC27
BC29
BC31
BC34
BC36
BC39
BC41
BC43
BC45
BD15
BD24

BE7

BE9
BE11
BE13
BE16
BE18
BE21
BE23
BE25
BE27
BE29
BE31
BE34
BE36
BE39
BE41
BE43
BE45

BF2

BF4
BF15
BF24
BF48
BF50

BH6
BH10
BH14
BH18
BH22
BH26
BH28
BH30
BH32
BH34
BH38
BH42
BH44
BH46
BH48
BK10
BK14
BK18
BK22
BK26
BK30
BK32
BK34
BK38
BK42
BK46

D6
D10
D14
D18
D22
D26
D30
D34
D38
D42
D46

F2

F4
F48
F50

G7

G9
G11
G13
G16
G18
G21
G23
G25
G27
G29
G31
G34
G36

G39
G41
G43
J7
J9
J11
J13
J16
J18
J21
J23
J25
J27
J29
J31
J34
J36
J39
J41
J45
K2
K4
K48
K50
L7
L9
L11
L13
L16
L18
L21
L23
L25
L27
L29
L31
L34
L36
L39
L41
L43
L45
N7
N9
N11
N13
N21
N23
N25
N29
N31
N34
N39
N41
N43
N45
P2
P4
P48
P50
R17
R21
R31
R37
T7
T9
T11
T13
T41
T43
T45
U31
U49
V2
V4
V7
V9
V11
V15
V17
V27
V29
V33
V35
V41
V43
V45
V48
Y15
Y17
Y33
Y35
Y37

<BRANCH>

<SCH_NUM>

<E4LABEL>

23 OF 132

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NC

NC

NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

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D

8 7 6 5 4 3

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B

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NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(PCH 1.05V CORE PWR)

PCH VCCCORE BYPASS

PCH VCCSUSHDA BYPASS

PCH VCCIO BYPASS

(PCH USB 1.05V PWR)

NEED PWR CONSTRAINT

1 mA

NEED PWR CONSTRAINT

(PCH Reference for 5V Tolerance on USB)

1 mA S0-S5

PCH V5REF_SUS Filter & Follower

PCH V5REF Filter & Follower

<1 MA

(PCH Reference for 5V Tolerance on PCI)

(PCH HD Audio 3.3V/1.5V PWR)

PCH VCC3_3 BYPASS

(PCH PCI 3.3V PWR)

PCH VCCIO BYPASS

(PCH SUSPEND USB 3.3V PWR)

PCH VCCSUS3_3 BYPASS

69 mA

68 mA

PCH VCCADPLLA Filter
(PCH DPLLA PWR)

(PCH DPLLB PWR)

PCH VCCADPLLB Filter

1/16W

0

MF-LF

5%

402

1/16W

0

MF-LF

402

5%

PLACE_NEAR=U1800.AB27:2.54mm

6.3V

X5R-CERM1

0603

20%

22UF

PLACE_NEAR=U1800.AB27:2.54mm

0603

X5R-CERM1

6.3V

20%

22UF

PLACE_NEAR=U1800.AB27:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AB27:2.54mm

0201

1UF

6.3V

20%
X5R

PLACE_NEAR=U1800.AB27:2.54mm

0201

6.3V

20%
X5R

1UF

PLACE_NEAR=U1800.AU27:2.54mm

CERM-X5R

6.3V

20%

0402-2

10UF

PLACE_NEAR=U1800.AR29:2.54mm

1UF

X5R
0201

20%

6.3V

PLACE_NEAR=U1800.AU29:2.54mm

X5R
0201

20%

6.3V

1UF

PLACE_NEAR=U1800.AU25:2.54mm

20%

1UF

0201

X5R

6.3V

PLACE_NEAR=U1800.AR25:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AB21:2.54mm

10UF

20%

6.3V

CERM-X5R

0402-2

PLACE_NEAR=U1800.AB21:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AB21:2.54mm

6.3V

20%

0201

X5R

1UF

PLACE_NEAR=U1800.AB21:2.54mm

6.3V

20%
X5R

1UF

0201

PLACE_NEAR=U1800.AJ13:2.54mm

X5R-CERM
0201

10%
16V

0.1UF

PLACE_NEAR=U1800.V31:2.54mm

0.1UF

X5R-CERM
0201

10%
16V

PLACE_NEAR=U1800.AM17:2.54mm

0.1UF

16V
0201

10%
X5R-CERM

PLACE_NEAR=U1800.N27:2.54mm

0.1UF

X5R-CERM
0201

10%
16V

PLACE_NEAR=U1800.AM17:2.54mm

10%

0.1UF

X5R-CERM
0201

16V

PLACE_NEAR=U1800.AM17:2.54mm

20%

4.7UF

402

X5R

6.3V

PLACE_NEAR=U1800.R27:2.54mm

X5R-CERM

16V

10%

0201

0.1UF

PLACE_NEAR=U1800.Y19:2.54mm

20%

1UF

6.3V
0201

X5R

PLACE_NEAR=U1800.R12:2.54mm

0.1UF

X5R-CERM

16V

0201

10%

PLACE_NEAR=U1800.AM23:2.54mm

6.3V

1UF

X5R
0201

20%

PLACE_NEAR=U1800.R33:2.54mm

1UF

X5R
0201

20%

6.3V

PLACE_NEAR=U1800.AG13:2.54mm

1UF

X5R
0201

20%

6.3V

PLACE_NEAR=U1800.AC35:2.54mm

1UF

X5R
0201

20%

6.3V

PLACE_NEAR=U1800.AB15:2.54mm

1UF

X5R
0201

20%

6.3V

PLACE_NEAR=U1800.AC37:2.54mm

1UF

X5R
0201

20%

6.3V

PLACE_NEAR=U1800.U27:2.54mm

20%

0201

X5R

1UF

6.3V

PLACE_NEAR=U1800.AJ17:2.54mm

1UF

X5R
0201

20%

6.3V

PLACE_NEAR=U1800.AP39:2.54mm

0402-2

CERM-X5R

6.3V

20%

10UF

0603

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.U51:2.54mm

0.01UF

0201

10%
16V

X5R-CERM

PLACE_NEAR=U1800.U51:2.54mm

X5R-CERM

16V

0.1UF

0201

10%

PLACE_NEAR=U1800.U51:2.54mm

CERM-X5R

6.3V

20%

10UF

0402-2

201

5%

0

MF

1/20W

SOT-363

BAT54DW-X-G

1/20W

5%

201

MF

100

PLACE_NEAR=U1800.N36:2.54mm

X5R
402

10V

10%

1UF

BAT54DW-X-G

SOT-363

10

MF

5%

1/20W

201

PLACE_NEAR=U1800.M37:2.54mm

10V

20%

CERM

0.1UF

402

PLACE_NEAR=U1800.AF6:2.54mm

X5R-CERM

16V

0.1UF

10%
0201

PLACE_NEAR=U1800.R40:2.54mm

16V

10%
0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.AC19:2.54mm

16V

10%
0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.BK28:2.54mm

10%
X5R-CERM

0201

16V

0.1UF

PLACE_NEAR=U1800.T39:2.54mm

16V

10%

0201

X5R-CERM

0.1UF

PLACE_NEAR=U1800.BF40:2.54MM

6.3V
0201

X5R

20%

1UF

PLACE_NEAR=U1800.BD40:2.54MM

0201

X5R

6.3V

20%

1UF

PLACE_NEAR=U1800.AB19:2.54mm

0201

16V

10%

0.1UF

X5R-CERM

402

MF-LF

1/16W

1

5%

0603

10UH-0.12A-0.36OHM

PLACE_NEAR=U1800.V37:2.54mm

6.3V

20%

10UF

0402-1

CERM-X5R

PLACE_NEAR=U1800.V37:2.54mm

X5R

10%
402

1UF

10V

PLACE_NEAR=U1800.AW16:2.54mm

1UF

X5R
0201

20%

6.3V

10UH-0.12A-0.36OHM

0603

10UH-0.12A-0.36OHM

0603

PLACE_NEAR=U1800.BD40:2.54MM

1206-1

6.3V
CERM-X5R

100UF

20%

PLACE_NEAR=U1800.BD40:2.54MM

1206-1

6.3V
CERM-X5R

100UF

20%

PLACE_NEAR=U1800.BF40:2.54MM

1206-1

6.3V
CERM-X5R

100UF

20%

PLACE_NEAR=U1800.BF40:2.54MM

20%

100UF

CERM-X5R

6.3V
1206-1

SYNC_MASTER=J13_MLB

SYNC_DATE=09/15/2011

PCH DECOUPLING

=PP1V05_S0_PCH

=PP3V3_S0_PCH

MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCC3_3_CLK_F

MIN_LINE_WIDTH=0.4 MM
VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

PP3V3_S0_PCH_VCC3_3_CLK_R

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.25MM

PP5V_SUS_PCH_V5REFSUS

VOLTAGE=5V
MAKE_BASE=TRUE

MAKE_BASE=TRUE

PP5V_S0_PCH_V5REF

MIN_LINE_WIDTH=0.3MM
VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCADPLLA_R

MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLB_R

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

VOLTAGE=3.3V

MAKE_BASE=TRUE
MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_PCH_VCCA_DAC_F

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_PCH_VCCADPLLA_F

PP1V05_S0_PCH_VCCADPLLB_F

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.25MM

PP1V05_S0_PCH_VCCCLKDMI_F

=PP1V05_S0_PCH_VCCADPLL

=PP1V05_S0_PCH_VCC_DMI

=PP3V3_S0_PCH_VCC3_3_CLK

=PP3V3_SUS_PCH_VCC_SPI

=PP1V05_S0_PCH_VCC_DMI

=PP1V05_S0_PCH_V_PROC_IO

=PP3V3R1V5_S0_PCH_VCCSUSHDA

=PP3V3_SUS_PCH_VCCSUS_USB

=PP1V05_S0_PCH_VCCASW

=PP1V05_S0_PCH_VCCIO_SATA

=PP1V05_S0_PCH_VCCDIFFCLK

=PP5V_S0_PCH_V5REF

=PP5V_SUS_PCH_V5REFSUS

=PP3V3_S5_PCH_VCCDSW

=PP3V3_SUS_PCH
=PP5V_SUS_PCH

=PP3V3_S0_PCH_VCC3_3

=PP3V3_S0_PCH_VCC3_3

=PP3V3_S0_PCH_VCC3_3

=PP1V05_S0_PCH_VCCIO

=PP1V05_S0_PCH_VCCSSC

=PP3V3_SUS_PCH_VCCSUS

=PP3V3_SUS_PCH_VCCSUS

=PP1V05_S0_PCH_VCC_CORE

=PP1V05_S0_PCH_VCCIO

=PP3V3_S0_PCH_VCC3_3

=PP1V8_S0_PCH_VCC_DFTERM

=PP3V3_S0_PCH_VCC3_3

=PP5V_S0_PCH

=PP3V3_S0_PCH_VCCADAC

R2460

1 2

R2465

1 2

C2420

1

2

C2428

1

2

C2496

1

2

C2456

1

2

C2426

1

2

C2401

1

2

C2463

1

2

C2407

1

2

C2414

1

2

C2429

1

2

C2460

1

2

C2483

1

2

C2482

1

2

C2481

1

2

C2440

1

2

C2441

1

2

C2430

1

2

C2413

1

2

C2417

1

2

C2416

1

2

C2484

1

2

C2442

1

2

C2499

1

2

C2419

1

2

C2476

1

2

C2452

1

2

C2475

1

2

C2444

1

2

C2434

1

2

C2446

1

2

C2469

1

2

C2411

1

2

L2406

1 2

C2455

1

2

C2451

1

2

C2450

1

2

R2450

1 2

D2400

1

6

R2405

12

C2439

1

2

D2400

4

3

R2404

12

C2438

1

2

C2423

1

2

C2485

1

2

C2486

1

2

C2421

1

2

C2424

1

2

C2461

1

2

C2466

1

2

C2422

1

2

R2451

1 2

L2451

1 2

C2453

1

2

C2454

1

2

C2418

1

2

L2460

1 2

L2465

1 2

C2465

1

2

C2462

1

2

C2402

1

2

C2403

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

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www.vinafix.vn

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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

NOTE: This is not the standard XDP pinout.
Use with 921-0133 Adapter Flex to
support chipset debug.

518S0847

PCH Micro2-XDP

HOOK3

- ’Output’ non-XDP signals require pulls.

CPU Micro2-XDP

support chipset debug.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

Non-XDP Signals

Use with 921-0133 Adapter Flex to

OBSFN_B1

PCH SIGNALS

- ’Output’ PCH/XDP signals require pulls.

and path to non-XDP signal destination.

needs to split between route from PCH to J2550

R252x, R253x, R257x and R259x should be placed where signal path

(R2564-R2567)

OBSDATA_A0
OBSDATA_A1

XDP SIGNALS

doc id 404081.

it is functional in that state, else add BOM options.

Initially, stuffing both 33 and 0 ohms and validate whether

- Following Intel’s Debug Prot Design Guid for HR and CR v1.3

PWRGD/HOOK0

OBSDATA_B0

OBSDATA_A2

OBSDATA_B1

TMS

TDI

PCH/XDP Signal Isolation Notes:

OBSDATA_B2

OBSDATA_D1

OBSDATA_D2
OBSDATA_D3

VCC_OBS_CD

DBR#/HOOK7

OBSDATA_D0

ITPCLK/HOOK4
ITPCLK#/HOOK5

XDP_PRESENT#

RESET#/HOOK6

RESET#/HOOK6

OBSFN_B0

OBSDATA_A2

VCC_OBS_AB

HOOK2

PWRGD/HOOK0

OBSDATA_B2

OBSFN_B1

VCC_OBS_CD

OBSDATA_B3

OBSDATA_B1

OBSDATA_A1

OBSFN_A1

OBSDATA_A3

OBSDATA_B0

- For isolated GPIOs:

VCC_OBS_AB

HOOK2
HOOK3

SDA
SCL

TCK1

OBSFN_C0

OBSDATA_C0

OBSFN_C1

TRSTn

TDO

OBSDATA_A3

OBSFN_B0

OBSFN_A1

OBSFN_A0

OBSFN_D0
OBSFN_D1

OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSDATA_C2

OBSFN_D0

ITPCLK/HOOK4

TCK0

SDA

HOOK1

TDI
TMS

TDO
TRSTn

DBR#/HOOK7

ITPCLK#/HOOK5

OBSFN_D1

OBSFN_C1

OBSDATA_C3

OBSDATA_C0

OBSDATA_D2

OBSDATA_D0
OBSDATA_D1

1K series R on PCH Support Page

XDP_PRESENT#

TCK0

OBSDATA_D3

TCK1

SCL

OBSDATA_B3

NOTE: This is not the standard XDP pinout.

NOTE: XDP_DBRESET_L pulled-up to 3.3V on PCH Support Page

OBSDATA_C1

OBSFN_C0

OBSDATA_A0

OBSFN_A0

518S0847

(R2520-R2537)

HOOK1

PCH SIGNALS

(R2560-R2563)

10 72

11 25

11 72

11 72

11 72

11 72

11 72

10 24 72

10 72

10 72

25

17 24

17 24

17 24

10 72

17 24

10 72

24 42

24 42

11 24 25 72

16V

10%

XDP

X7R-CERM

0.1UF

0402

16V

10%

XDP

X7R-CERM

0.1UF

0402

18 24 39

18 39 66

11 24 72

11 24 25 72

10 72

11 24 72

17 72

17 72

11 24 72

11 24 72

1/16W

5%

402

MF-LF

1K

NO STUFF

PLACE_NEAR=R1841.1:2.54mm

XDP

1/20W

5% 201MF

0

PLACE_NEAR=R1840.1:2.54mm

1/20W

5% 201MF

0

XDP

PLACE_NEAR=U1000.G3:2.54mm

201

1/20W

5% MF

1K

XDP

PLACE_NEAR=J2550.52:2.54mm

1/20W

5% 201MF

51

XDP

PLACE_NEAR=U1800.K5:2.54mm

1/20W

XDP

5% 201MF

51

PLACE_NEAR=U1800.H7:2.54mm

1/20W

5% 201MF

51

XDP

PLACE_NEAR=U1800.J3:2.54mm

1/20W

5% 201MF

51

XDP

PLACE_NEAR=J2500.52:2.54mm

1/20W

5% 201MF

51

XDP

PLACE_NEAR=U1000.K61:2.54mm

1/20W

5% 201MF

51

XDP

PLACE_NEAR=U1000.H59:2.54mm

1/20W

5% 201MF

51

XDP

PLACE_NEAR=U1000.J58:2.54mm

1/20W

5% 201MF

51

XDP

PLACE_NEAR=U1000.H63:2.54mm

1/20W

5% 201MF

51

XDP

1/20W

5% 201MF

330

XDP

PLACE_NEAR=U1000.B57:2.54mm

1/20W

5% 201MF

1K

XDP

PLACE_NEAR=U4900.P17:2.54mm

5%

1/20W

201MF

0

XDP

PLACE_NEAR=U1000.C60:2.54mm

1K

1/20W

5% 201MF

XDP

MF

XDP_CPU:BPM

1/20W

5% 201

0

11 72

1/20W

5% 201MF

0

XDP_CPU:BPM

201

1/20W

5% MF

0

XDP_CPU:BPM

201

0

1/20W

5% MF

XDP_CPU:BPM

0

1/20W

5% 201MF

XDP_CPU:CFG

MF

1/20W

5% 201

0

XDP_CPU:CFG

0

5% 201MF

XDP_CPU:CFG

1/20W

201

1/20W

5% MF

0

XDP_CPU:CFG

10 72

10 72

10 72

10 72

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

201

1/20W

5% MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

20 24

20 24

20 24

20

10 24 72

17 24

17 24

20

20 24

19 24

19 24

19 24

19

19

19 24

PLACE_NEAR=J2550.39:2.54mm

XDP

1/20W

5% 201MF

1K

PLACE_NEAR=U4900.P17:2.54mm

1/20W

5% 201MF

0

XDP

39 66

18 24 39

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

24

DF40RC-60DP-0.4V

XDP_CONN

M-ST-SM1

CRITICAL

M-ST-SM1

XDP_CONN

DF40RC-60DP-0.4V

CRITICAL

1/20W

5% 201MF

33

XDP

25

27

17 25

20 25

MF

1/20W

5% 201

0

1/20W

5% 201MF

0

1/20W

5% 201MF

0

0

1/20W

5% 201MF

0

1/20W

5% 201MF

9

20 25

0

1/20W

5% 201MF

19 24

20 24

0402

X7R-CERM

XDP

16V

10%

0.1UF

20 24

20 24

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

1/20W

5% 201MF

33

XDP

5%

1/20W

201MF

33

XDP

20 24

20 24

19

19

1/20W

MF02015%

201

1/20W

5% MF

0

10 72

17 24

17 24

17

1/20W

5% 201MF

0

0

MF 2015%

1/20W

19 24

19 24

7

36

38

19 36 66

19 24

20 20 24

1/20W

5%

201 MF

1K

1/20W

5%

201 MF

1K

20 24

1K

MF 2015%

1/20W

0402

10%

0.1UF

X7R-CERM

XDP

16V

PPDDR:1V5

5%

1/20W

201MF

0

20 24 60

20

11 72

11 72

10 72

10 72

10 72

10 72

24 42

24 42

11 24 72

10 72

11 20 72

10 72

11 72

11 72

SYNC_MASTER=J30_MLB

CPU & PCH XDP

SYNC_DATE=07/14/2011

XDP_BPM_L<5>
XDP_BPM_L<6>
XDP_BPM_L<7>

CPU_CFG<12>

CPU_CFG<15>

CPU_CFG<14>

CPU_CFG<13>

XDP_OBSDATA_B<3>

XDP_OBSDATA_B<2>

XDP_CPU_CLK100M_P

CPU_RESET_L

XDP_CPU_TRST_L

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_CPURST_L
XDP_DBRESET_L

XDP_CPU_TDO

TBT_CIO_PLUG_EVENT_ISOL

XDP_CPU_TMS

XDP_CPU_TDI

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_BPM_L<4>

XDP_PCH_TDO

XDP_PCH_TDI

XDP_DA0_USB_EXTA_OC_L

XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_DA1_PCH_GPIO40_USB_EXTB_OC_L

XDP_CPU_PRDY_L

XDP_DD1_JTAG_ISP_TCK

XDP_DA3_USB_EXTD_OC_L

XDP_DD0_DP_GPU_TBT_SEL

XDP_DB0_PCH_GPIO43_USB_EXTB_OC_EHCI_L

XDP_DD1_JTAG_ISP_TCK

XDPPCH_PLTRST_L
XDP_DBRESET_L

XDP_PCH_TDO

XDP_PCH_TMS

=SMBUS_XDP_SDA

=PP3V3_S0_XDP

XDP_FC0_MEM_VDD_SEL_1V5_L

PM_PWRBTN_L

XDP_DC0_ISOLATE_CPU_MEM_L

CPU_CFG<6>
CPU_CFG<7>

XDP_DC2_DP_AUXCH_ISOL

XDP_PCH_TCK

XDP_PCH_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_CPU_TMS

XDP_CPU_TDI

XDP_CPU_TDO

=PPVCCIO_S0_XDP

XDP_DB2_AP_PWR_EN

XDP_PCH_TCK

=SMBUS_XDP_SCL

TP_XDPPCH_HOOK2
TP_XDPPCH_HOOK3

XDP_DB1_USB_EXTD_OC_EHCI_L

XDP_PCH_TDI

XDP_DC1_MXM_GOOD

CPU_CFG<16>

ITPXDP_CLK100M_P

ITPXDP_CLK100M_N

XDP_CPU_PREQ_L

XDP_BPM_L<0>

CPU_CFG<10>
CPU_CFG<11>

CPU_CFG<2>

=PP1V05_SUS_PCH_JTAG

XDP_BPM_L<1>

XDP_BPM_L<2>

PM_PCH_SYS_PWROK

XDP_DD3_ENET_LOW_PWR

XDP_DD0_DP_GPU_TBT_SEL

=SMBUS_XDP_SDA

XDP_DD2_AUD_IPHS_SWITCH_EN
XDP_DD3_ENET_LOW_PWR

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH
XDP_DD3_PCH_GPIO49_ENET_LOW_PWR_PCH

XDP_DC0_ISOLATE_CPU_MEM_L

XDP_DC3_SATARDRVR_EN

XDP_PCH_PWRBTN_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DB3_SDCONN_STATE_CHANGE

XDP_PCH_S5_PWRGD

XDP_CPU_CLK100M_N

ISOLATE_CPU_MEM_L

DP_AUXCH_ISOL

USB_EXTB_OC_L

CPU_CFG<4>

AP_PWR_EN

XDP_DC2_DP_AUXCH_ISOL

XDP_DA1_USB_EXTB_OC_L

XDP_DB0_USB_EXTB_OC_EHCI_L

XDP_DC1_MXM_GOOD

XDP_DC3_SATARDRVR_EN

XDP_DB2_AP_PWR_EN

XDP_DA2_USB_EXTC_OC_L

XDP_DD2_AUD_IPHS_SWITCH_EN

XDP_FC1

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DD2_PCH_GPIO16_AUD_IPHS_SWITCH_EN_PCH

XDP_DA1_USB_EXTB_OC_L

XDP_DA3_USB_EXTD_OC_L

XDP_DA2_USB_EXTC_OC_L

XDP_DD0_PCH_GPIO36_DP_GPU_TBT_SEL

XDP_DD1_PCH_GPIO37_JTAG_ISP_TCK

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_DB2_PCH_GPIO10_AP_PWR_EN

XDP_DA2_PCH_GPIO41_USB_EXTC_OC_L

CPU_PWRGD

XDP_DB1_PCH_GPIO9_USB_EXTD_OC_EHCI_L

XDP_DC1_PCH_GPIO35_MXM_GOOD

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

XDP_CPU_PWRGD

CPU_CFG<5>

XDP_DB1_USB_EXTD_OC_EHCI_L

ALL_SYS_PWRGD

XDP_DB3_SDCONN_STATE_CHANGE

XDP_DA0_USB_EXTA_OC_L

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL
XDP_DC3_PCH_GPIO19_SATARDRVR_EN

XDP_OBSDATA_B<0>

USB_EXTA_OC_L

CPU_CFG<9>

CPU_CFG<1>

MEM_VDD_SEL_1V5_L

TP_XDP_PCH_HOOK4
TP_XDP_PCH_HOOK5

PM_PWRBTN_L

TP_XDP_PCH_OBSFN_A<0>
TP_XDP_PCH_OBSFN_A<1>

TP_XDP_PCH_OBSFN_B<0>
TP_XDP_PCH_OBSFN_B<1>

TP_XDP_PCH_OBSFN_D<0>
TP_XDP_PCH_OBSFN_D<1>

XDP_FC1

XDP_FC0_MEM_VDD_SEL_1V5_L

TP_XDP_PCH_TRST_L

XDP_DB3_PCH_GPIO14_SDCONN_STATE_CHANGE

XDP_DA3_PCH_GPIO42_USB_EXTD_OC_L

XDP_FC0_PCH_GPIO15_MEM_VDD_SEL_1V5_L

XDP_FC1_TBT_CIO_PLUG_EVENT

XDP_DC2_PCH_GPIO21_DP_AUXCH_ISOL

XDP_OBSDATA_B<1>

XDP_BPM_L<3>

XDP_DC0_PCH_GPIO28_ISOLATE_CPU_MEM_L

CPU_CFG<3>

CPU_CFG<0>

SATARDRVR_EN

SDCONN_STATE_CHANGE

CPU_CFG<8>

=PPVCCIO_S0_XDP

CPU_CFG<17>

ENET_LOW_PWR_PCH

AUD_IPHS_SWITCH_EN_PCH

JTAG_ISP_TCK

CPU_CFG<0>

XDP_VR_READY

XDP_CPU_CFG<0>

=SMBUS_XDP_SCL

=PP3V3_S5_XDP

XDP_DA0_PCH_GPIO59_USB_EXTA_OC_L

XDP_CPU_PWRBTN_L

XDP_CPU_TCK

C2501

1

2

C2500

1

2

C2580

1

2

C2581

1

2

R2540

1

2

R2515

1 2

R2516

1 2

R2505

1 2

R2550

2 1

R2551

2 1

R2552

2 1

R2556

2 1

R2510

2 1

R2511

2 1

R2512

2 1

R2513

2 1

R2514

2 1

R2504

1 2

R2501

1 2

R2502

1 2

R2500

1 2

R2560

1 2

R2561

1 2

R2562

1 2

R2563

1 2

R2566

1 2

R2565

1 2

R2564

1 2

R2567

1 2

R2524

1 2

R2525

1 2

R2526

1 2

R2527

1 2

R2530

1 2

R2532

1 2

R2533

1 2

R2534

1 2

R2535

1 2

R2536

1 2

R2537

1 2

R2584

1 2

R2585

1 2

J2500

1

10

1112
1314
1516
1718
19

2

20

2122
2324
2526
2728
29

3

30

3132
3334
3536
3738
39

4

40

4142
4344
4546
4748
49

5

50

5152
5354
5556
5758
59

6

60

61

62

6364

78
9

J2550

1

10

1112
1314
1516
1718
19

2

20

2122
2324
2526
2728
29

3

30

3132
3334
3536
3738
39

4

40

4142
4344
4546
4748
49

5

50

5152
5354
5556
5758
59

6

60

61

62

6364

78
9

R2521

1 2

R2597

1 2

R2596

1 2

R2572

1 2

R2570

1 2

R2576

1 2

R2577

1 2

R2528

1 2

R2529

1 2

R2520

1 2

R2522

1 2

R2523

1 2

R2531

1 2

R2575

1 2

R2573

1 2

R2591

1 2

R2590

1 2

R2580

1 2

R2581

1 2

R2574

1 2

R2595

1 2

<BRANCH>

<SCH_NUM>

<E4LABEL>

25 OF 132

24 OF 80

72

17 24

17 24

24

24

8

24

24

24

17 24

17 24

11 24 72

11 24 72

11 24 72

11 24 72

11 24 72

8

24

24

24

24

8

24

24

24

24

24

72

24

24

24

24

24

72

7

7

7

7

7

7

7

7

7

8

24

8

www.vinafix.vn

IN

OUT

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

OUT

OUT

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

NC

NC

OUT

PAD

+3.42V

VDD_25M

+V3.3A

VDDIO_25M_C

VDDIO_25M_B

VDDIO_25M_A

25MHZ_C

25MHZ_B

25MHZ_A

X1

X2

VDD_RTC_OUT

THRM

GND

32KHZ_A

NC
NC

08

Y1

Y2

GND

B2

VCC

A1
B1
A2

OUT

OUT

IN
IN
IN

IN

D

SG

D

S G

OUT

OUT

OUT

OUT

08

Y1

Y2

GND

B2

VCC

A1
B1
A2

IN
IN
IN

Y

B

A

D

G S

IN

OUT

OUT

IN

IN

OUT

D

S G

D

S G

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Ethernet XTAL Power (Unused on J5)
SB XTAL Power
TBT XTAL Power

NOTE: 30 PPM crystal required

VDDIO_25M_A: SB power rail for XTAL circuit.

GPIO Glitch Prevention

System RTC Power Source & 32kHz / 25MHz Clock Generator

VDDIO_25M_C: Thunderbolt power rail for XTAL circuit.

33 MHz Clock Series Termination

GreenClk 25MHz Power

NOTE: VDD_25M must be powered if any VDDIO_25M_x is powered.

VDDIO_25M_B: Ethernet power rail for XTAL circuit.

Platform Reset Connections

Unbuffered

Q2620 & 5V pull-up allows circuit to work regardless of HDA voltage.

to reduce VBAT draw.

available ~3.3V power

No Coin-Cell: 3.42V G3Hot (no RC)

VBAT and +V3.3A are

create VDD_RTC_OUT.

VTT voltage divider on CPU page

Buffered

PCH uses HDA_SDO as a power-up strap. If low, ME functions normally.

SMC controls strap enable to allow in-field control of strap setting.

internally ORed to

+V3.3A should be first

Coin-Cell & G3Hot: 3.42V G3Hot

IPD = 9-50k

No Coin-Cell: 3.3V S5
No bypass necessary

If high, ME is disabled. This allows for full re-flashing of SPI ROM.

Buffered CPU reset

PCH ME Disable Strap

Series R on Pg38, R3803

Coin-Cell: VBAT (300-ohm & 10uF RC)

Coin-Cell & No G3Hot: 3.3V S5

DP_AUXIO_EN INVERSION

For SB RTC Power

SDCONN_STATE_CHANGE ISOLATION

PCH Reset Button

11 24 72

XDP

0

MF-LF

5%

1/16W

402

33

MF-LF

402

5%

1/16W

33

MF-LF

402

5%

1/16W

7

41

39

36

19 27

PLACE_NEAR=U1800.E49:5.1MM

22

5%

1/20W

MF

201

12

201

1/20W

5%
MF

PLACE_NEAR=U1800.G51:5.1MM

19 75

31

0

MF-LF

402

5%

1/16W

7

41 75

7

39 75

19

24

MF-LF

402

1/16W

5%

1K

XDP

0.1UF

CERM

402

20%
10V

CRITICAL

SC70-HF

MC74VHC1G08

100K

MF-LF
402

5%
1/16W

7

17 75

PLACE_NEAR=U1800.G45:2.54MM:5.1MM

22

MF

5%

1/20W

201

19

SILK_PART=SYS RESET

OMIT

0

MF-LF
402

5%
1/16W

75

71

402

1/16W

5%
MF-LF

10K

7

18 39

17 74

17 74

33 74

CERM

1UF

402

10%

6.3V

X5R

402-1

10V

10%

1UF

0.1UF

NO STUFF

CERM

402

20%
10V

0.1UF

CERM

402

20%
10V

1M

MF-LF
402

5%
1/16W

NO STUFF

0.1UF

CERM

402

20%
10V

0

MF-LF

402

5%

1/16W

12PF

CRITICAL

5%

50V

CERM

402

CRITICAL

12PF

402

5%

50V

CERM

11 24

100K

MF-LF
402

5%
1/16W

CRITICAL

74LVC1G07

SC70

0.1UF

CERM

402

20%
10V

5%
1/16W
MF-LF

402

0

MF-LF

402

5%

1/16W

0

35

TQFN

CRITICAL

SLG3NB148A

CRITICAL

25.000MHZ-20PPM-12PF-85C

3.2X2.5MM-SM

NO STUFF

MF-LF

402

5%

1/16W

0

0

MF-LF
402

5%
1/16W

CRITICAL

74LVC2G08GT

SOT833

CERM
402

20%
10V

0.1UF

9

9 9

20 24

18 25 66

20

0

MF-LF

402

5%
1/16W

39 40

1K

1/20W
MF
201

5%

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

SOT563

100K

MF
201

5%
1/20W

17 75

36

54

33

10V

0.1UF

CERM
402

20%

74LVC2G08GT

CRITICAL

SOT833

17

7

18 39 41

20 24

TC7SZ08AFEAPE

CRITICAL

SOT665

10%
X5R

6.3V

0.1UF

201

SOD-VESM-HF

SSM3K15FV

CRITICAL

16V

10%

0201

X5R-CERM

0.1UF

1/20W

5%

201

MF

10K

17 24

69 70

24

36

18 25 66

7

40

SOT563

SSM6N37FEAPE

5%
MF

470K

201

1/20W

SOT563

SSM6N37FEAPE

5%

201

470K

1/20W

MF

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

Chipset Support

=PP3V3_S0_SB_PM

FW_PWR_EN

PLT_RESET_L

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3MM

GND_SYSCLK_25M_B

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

LPCPLUS_RESET_L

MAKE_BASE=TRUE

PLT_RST_CPU_BUF_L

MAKE_BASE=TRUE

ENET_RESET_L

MAKE_BASE=TRUE

PLT_RST_BUF_L

MAKE_BASE=TRUE

=PP3V3_S4_SMC

AUD_IPHS_SWITCH_EN

=PP3V3_S0_PCH_GPIO

SDCONN_STATE_CHANGE

SDCONN_STATE_CHANGE_RIO

SDCONN_STATE_CHANGE_SMC

=PP3V3_S4_SMC

DP_AUXCH_ISOL

DP_AUXIO_EN

ENET_LOW_PWR

=PP3V3_S5_SYSCLK

SPI_DESCRIPTOR_OVERRIDE_LS5V

PCA9557D_RESET_L

AP_RESET_L

=TBT_RESET_L

LPC_PWRDWN_L

SPI_DESCRIPTOR_OVERRIDE_L

=PP3V3_S0_RSTBUF

=PP3V3_S0_RSTBUF

=PP3V3_S3_SDBUF

XDPPCH_PLTRST_L

SYSCLK_CLK25M_X2_R

LPC_CLK33M_SMC

AUD_IPHS_SWITCH_EN_PCH

TBT_PWR_EN

ENET_LOW_PWR_PCH

LPC_RESET_L

SPI_DESCRIPTOR_OVERRIDE

HDA_SDOUT_R

=PP3V3R1V5_S0_PCH_VCCSUSHDA

CPU_RESET_L

SMC_LRESET_L

PM_SYSRST_L

TP_SYSCLK_CLK25M_ENET

PCH_CLK33M_PCIIN

=PP5V_S0_PCH

LPC_CLK33M_LPCPLUS

SYSCLK_CLK32K_RTC

SYSCLK_CLK25M_SB

BKLT_PLT_RST_L

=PPVRTC_G3_OUT

SYSCLK_CLK25M_TBT

XDP_DBRESET_L

=PPVBAT_G3_SYSCLK

=ENET_RESET_L

SDCONN_STATE_CHANGE_INV

FW_PWR_EN_PCH

=PP3V3_S3_PCH_GPIO

PCH_CLK33M_PCIOUT

LPC_CLK33M_LPCPLUS_R

LPC_CLK33M_SMC_R

PM_PCH_PWROK

TBT_PWR_EN_PCH

=PP3V3_S0_SYSCLK

PM_PCH_PWROK

=PP3V3_S3_PCH_GPIO

=PPVDDIO_TBT_CLK

SYSCLK_CLK25M_X2

=PPVDDIO_S0_SBCLK

SYSCLK_CLK25M_X1

R2696

1 2

R2683

1 2

R2681

1 2

R2656

1 2

R2655

1 2

R2671

1 2

R2689

1 2

C2680

1

2

U2680

3

2

1

4

5

R2680

1

2

R2659

1 2

R2697

1

2

R2695

1

2

C2610

1

2

C2602

1

2

C2620

1

2

C2622

1

2

R2606

1

2

C2624

1

2

R2605

1 2

C2605

12

C2606

1 2

R2690

1

2

U2690

2

3

5

4

C2690

1

2

R2688

1 2

R2693

1 2

U2600

9
8
15

12

71016

13

2

17

5

1

11

6

14

4

3

Y2605

24

13

R2607

1 2

R2608

1

2

U2650

1

5

2

6

4

8

7

3

C2650

1

2

R2686

1 2

R2621

1

2

Q2620

6

2

1

Q2620

3

5

4

R2620

1

2

C2652

1

2

U2652

1

5

2

6

4

8

7

3

U2630

2

1

3

5

4

C2630

1

2

Q2630

3

1

2

C2639

1

2

R2630

1 2

Q2640

3

5

4

R2640

1

2

Q2640

6

2

1

R2641

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

26 OF 132

25 OF 80

1

8

66

7

8

25 36 40

8

17 18 19 20 35

8

25 36 40

8

8

25

8

25

8

8

21 23

8

23

8

8

8

19 25

8

8

19 25

8

8

www.vinafix.vn

BI
BI

BI

BI

VDD33

PLLFILT

CRFILT

SUSP_IND/LOCAL_PWR/NON_REM0

SDA/SMBDATA/NON_REM1

SCL/SMBCLK/CFG_SEL0

HS_IND/CFG_SEL1

XTALIN/CLKIN
XTALOUT

TEST

RESET*

THRM_PAD

USBDP_UP

NC

OSC3*

OCS1*
OCS2*

USBDM_UP

RBIAS

VBUS_DET

NC

NC
NC

USBDP_DN3/PRT_DIS_P3

USBDM_DN3/PRT_DIS_M3

USBDP_DN2/PRT_DIS_P2

USBDM_DN2/PRT_DIS_M2

USBDP_DN1/PRT_DIS_P1

USBDM_DN1/PRT_DIS_M1

PRTPWR3/BC_EN3*

PRTPWR1/BC_EN1*
PRTPWR2/BC_EN2*

SYM VER 1

BI
BI

BI
BI

BI
BI

IN

VCC

GND

SELOE*

D+
D-

Y+
Y-

M+
M-

BI

BI

BI
BI

BI

BI

BI

BI

NC

NC

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

IPU

NC FOR D1/D2, SMC DEBUG PORT FOR J3X

SMC DEBUG PORT FOR D1/D2, TPAD/KBD FOR J3X

TRACKPAD/KEYBOARD FOR D1/D2, IR FOR J3X

BLUETOOTH FOR D1/D2 & J3X

D1,D2 ENGINEERING: USE USB2513B PRODUCTION: USE USB2512B

BOM TABLE

J3X ENGINEERING: USE USB2514B PRODUCTION: USE USB2513B

PCH PORT 9 (EHCI2)

PCH PORT 1 (XHCI)

PCH PORT 7 (EHCI1)

IPU
IPU
IPU

TO TP/KB

TO CONNECTOR

1 : 0 PORT 1&2 ARE NON REMOVABLE

SEL=0 CHOOSE USB EHCI2 PORT
SEL=1 CHOOSE USB XHCI PORT

PCH GPIO60

PULL-UP TO 3.3V SUS ON PCH PAGE, SEL PIN IS LEAKAGE-SAFE

J3X USE 197S0284 FOR Y2700 TO SAVE COST

TO PCH XHCI

NOSTUFF R5701 & R5702, STUFF R2720 & R2721

USB XHCI/EHCI2 PORT MUX FOR EXT B

J5 USES 197S0181 FOR Y2700 DUE TO HEIGHT LIMITATION

NON_REM 1 : NON_REM 0 STRAP PIN CFG
0 : 0 ALL PORTS ARE REMOVABLE

0 : 1 PORT 1 IS NON REMOVABLE
1 : 1 PORT 1&2&3 ARE NON REMOVABLE

CANNOT INDICATE ALL 4 PORTS ARE NON REMOVABLE ON USB2514B VIA STRAPPING, PROGRAM NON_REMOVABLE DEVICE REGISTER 09H

TO CONNECT TP/KB TO PCH XHCI

USB MUX FOR LS/FS INTERNAL DEVICES

1/16W

5%

402

MF-LF

10K

1M

5%

CRITICAL

1/16W

402

MF-LF

16V

10%

402

X5R

1UF

0.1UF

X7R-CERM

10%
16V

0402

16V

10%
402

X5R

1UF

0.1UF

X7R-CERM

10%
16V

0402

BYPASS=U2700.23::2MM

0.1UF

X7R-CERM

10%
16V

0402

10K

1/16W

5%

402

MF-LF

1/16W

1%

402

MF

12K

CRITICAL

19 74

19 74

16V

BYPASS=U2700.15::2MM

0.1UF

X7R-CERM

10%

0402

0402

X7R-CERM

16V

10%

0.1UF

BYPASS=U2650.29::2MM

BYPASS=U2700.36::2MM

0.1UF

X7R-CERM

10%
16V

0402

1/16W

5%

402

MF-LF

100

5%

18PF

402

CERM

50V

CRITICAL

402

CERM

18PF

50V

5%

CRITICAL

5%
1/16W

402

MF-LF

10K

1/16W

5%

402

MF-LF

10K

HUB_NONREM0_1

1/16W

5%

402

MF-LF

10K

1/16W

5%

402

MF-LF

10K

HUB_NONREM1_1

HUB_NONREM0_0

1/16W

5%

402

MF-LF

10K

1/16W

5%

402

MF-LF

10K

HUB_NONREM1_0

9

9

OMIT_TABLE

SM-2

CRITICAL

24.000MHZ-16PF

OMIT_TABLE

QFN

USB2513B

CKPLUS_WAIVE=ndifpr_badterm

BYPASS=U2700.10::2MM

0.1UF

X7R-CERM

10%
16V

0402

BYPASS=U2700.5::2MM

0.1UF

X7R-CERM

10%
16V

0402

4.7UF

6.3V

20%
603

X5R

BYPASS=U27000.5::5MM

BYPASS=U2700.23::5MM

6.3V

20%
603

X5R

4.7UF

9

26

9

26

BYPASS=U2700.26::2MM

0.1UF

X7R-CERM

10%
16V

0402

9

26

9

26

1/16W

5%

402

MF-LF

10K

NOSTUFF

1/16W

5%

402

MF-LF

10K

NOSTUFF

1/16W

5%

402

MF-LF

10K

NOSTUFF

1/16W

5%

402

MF-LF

10K

NOSTUFF

7

36 74

7

36 74

17

10V

20%

402

CERM

0.1UF

TQFN

PI3USB102ZLE

CRITICAL

19 74

19
74

19
74

19 74

47 78

47 78

1/16W

5%

402

MF-LF

27

NOSTUFF

1/16W

5%

402

MF-LF

27

NOSTUFF

19 74

19 74

1/16W

5%

402

MF-LF

10K

NOSTUFF

1/16W

5%

402

MF-LF

10K

NOSTUFF

XTAL,24MHZ,60PPM,16PF,2.5X2X0.55MM,90C

CRITICAL

Y2700

1

197S0485

USBHUB:2514B

CRITICAL

USB HUB 2514B

338S0824

1

U2700

USBHUB:2513B

CRITICAL

USB HUB 2513B

338S0923

1

U2700

USBHUB:2512B

CRITICAL

USB HUB 2512B

338S0983

1

U2700

HUB_NONREM1_0,HUB_NONREM0_0

HUB_ALLREM

HUB_NONREM1_0,HUB_NONREM0_1

HUB_1NONREM

HUB_3NONREM

HUB_NONREM1_1,HUB_NONREM0_1

HUB_2NONREM

HUB_NONREM1_1,HUB_NONREM0_0

USB HUB & MUX

SYNC_DATE=08/17/2011

SYNC_MASTER=J5_AMD

USB_HUB_CFG_SEL1

=PP3V3_S3_USB_HUB

USB_HUB_XTAL2

USB_HUB_XTAL1

USB_HUB_NONREM0
USB_HUB_NONREM1

USBHUB_DN4_P

TP_USB_HUB_PRTPWR1

USBHUB_DN4_P

USBHUB_DN2_N

=PP3V3_S3_USB_HUB

USBHUB_DN4_N

TP_USB_HUB_OCS1

USB_EXTD_XHCI_P

USB_TPAD_R_P

=PP3V3_S3_USB_HUB

USB_HUB_VBUS_DET

USB_HUB_RBIAS

USBHUB_DN2_P

USBHUB_DN4_N

USBHUB_DN3_P

USBHUB_DN3_N

USB_EXTB_SEL_XHCI

USB_EXTB_XHCI_N

=PP3V3_S3_USBMUX

USB_EXTB_P

USB_HUB_RESET_L

=PP3V3_S3_USB_RESET

USBHUB_DN2_N

USB_EXTB_XHCI_P

USB_EXTB_EHCI_N

USB_EXTB_EHCI_P

USB_EXTB_N

USB_EXTD_XHCI_N

USB_TPAD_R_N

TP_USB_HUB_OCS2

TP_USB_HUB_OCS4

TP_USB_HUB_OCS3

TP_USB_HUB_PRTPWR4

TP_USB_HUB_PRTPWR3

TP_USB_HUB_PRTPWR2

USB_HUB_CFG_SEL0

USB_HUB_RESET_L

USBHUB_DN3_P

USBHUB_DN3_N

USBHUB_DN2_P

USBHUB_DN1_P

USBHUB_DN1_NUSB_HUB_TEST

PPUSB_HUB2_VDD1V8PLL

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.4MM

VOLTAGE=1.8V

PPUSB_HUB2_VDD1V8

USB_HUB_UP_P

USB_HUB_UP_N

R2712

1

2

R2700

1 2

C2714

1

2

C2713

1

2

C2712

1

2

C2711

1

2

C2708

1

2

R2708

1

2

R2709

1

2

C2701

1

2

C2706

1

2

C2705

1

2

R2701

1 2

C2710

1

2

C2709

1

2

R2707

1

2

R2706

1

2

R2703

1

2

R2702

1

2

R2705

1

2

R2704

1

2

Y2700

2 4

1 3

U2700

14

25

8
9

20

21

13
17
19

34

12
16
18

35

26

24

22

28

11

37

1

3

6

30

2

4

7

31

27

510152329

36

33
32

C2702

1

2

C2703

1

2

C2700

1

2

C2704

1

2

C2715

1

2

R2716

1

2

R2717

1

2

R2718

1

2

R2719

1

2

C2760

1

2

U2760

6

7

3

4

5

8

10

9

2

1

R2720

1 2

R2721

1 2

R2722

1

2

R2723

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

27 OF 132

26 OF 80

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8

9

26

26

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www.vinafix.vn

IN IN

IN

OUT

OUT

D

SG

D

S G

D

SG

D

S G

D

SG

D

S G

D

S G

D

SG

OUT

IN

IN

D

SG

D

SG

IN

G

D

S

OUT

IN

IN

IN

IN

IN

S0_READY

ISOL*

S0_EN

S3_EN

RST_IN*

GND

THRM

VDD

VTT_EN

VDDIO_EN

RST_OUT*

PAD

OUT

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Step ISOLATE_CPU_MEM_L PLT_RESET_L PM_SLP_S3_L PM_SLP_S4_L CPU_MEM_RESET_L MEM_RESET_L MEMVTT_EN P1V5CPU_EN

P1V5CPU_EN = (ISOLATE_CPU_MEM_L + PM_SLP_S3_L) * PM_SLP_S4_L

Ensures CKE signals are held low in S3

to

75mA max load @ 0.75V

6 0 1 1 1 1 1 1 1

3 0 0 0 1 X 1 0 0

S0

to

S3

S0

60mW max power

MEMVTT Clamp

1 0 1 1 1 1 1 1 1

PM_MEM_PWRGD pull-up to CPU VTT rail is on CPU page

1V35 S0 "PGOOD" for CPU

must deassert ISOLATE_CPU_MEM_L and then generate a valid reset cycle on CPU_MEM_RESET_L.

NOTE: In the event of a S3->S5 transition ISOLATE_CPU_MEM_L will still be asserted on next S5->S0

(*) CPU_MEM_RESET_L asserts due to loss of PM_MEM_PWRGD, must wait for software to clear before deasserting ISOLATE_CPU_MEM_L GPIO.

7 1 1 1 1 1 CPU_MEM_RESET_L 1 1

2 0 0 1 1 1 1 0 1

5 0 1 1 1 0 (*) 1 1 1

MEM_RESET_L = !ISOLATE_CPU_MEM_L + CPU_MEM_RESET_L

MEMVTT_EN = (ISOLATE_CPU_MEM_L + PLT_RST_L) * PM_SLP_S3_L

WHEN LOW: CPU 1.5V follows S0 rails, VTT ensures clean CKE transition, MEM_RESET_L isolated.

WHEN HIGH: CPU 1.5V remains powered in S3, VTT follows S0 rails, MEM_RESET_L not isolated.

ISOLATE_CPU_MEM_L GPIO state during S3<->S0 transitions determines behavior of signals.

as isolating the CPU’s SM_DRAMRST# output from the SO-DIMMs when necessary.

The circuit below handles CPU and VTT power during S0->S3->S0 transitions, as well

0 1 1 1 1 1 CPU_MEM_RESET_L 1 1

4 0 0 1 1 X 1 0 1

transition. Rails will power-up as if from S3, but MEM_RESET_L will not properly assert. Software

24 27

7

18 27 36 39 66

19 25 27

CPUMEM:S0

402

100K

MF-LF

5%

1/16W

9

27

402

MF-LF

5%
1/16W

10K

1/16W

5%

402

MF-LF

100K

CPUMEM:S0

27 28 29

1K

402

5%
1/16W
MF-LF

CPUMEM:S0

SSM6N37FEAPE

CRITICAL

SOT563

SSM6N37FEAPE

CPUMEM:S0

SOT563

CRITICAL

SSM6N37FEAPE

CPUMEM:S0

CRITICAL

SOT563

SSM6N37FEAPE

SOT563

CRITICAL

CPUMEM:S0

SSM6N37FEAPE

CPUMEM:S0

SOT563

CRITICAL

CPUMEM:S0

SSM6N37FEAPE

SOT563

CRITICAL

SSM6N37FEAPE

CPUMEM:S0

SOT563

CRITICAL

CRITICAL

SSM6N37FEAPE

SOT563

CPUMEM:S0

27 65

10K

1/16W

5%

402

MF-LF

7

18 27 36 38 39 66

MF-LF

100K

402

1/16W

5%

CPUMEM:S0

9

60

SSM6N37FEAPE

SOT563

CRITICAL

MF-LF

1/16W

5%

100K

402

NO STUFF

10%

0.047UF

10V
402

CERM

SSM6N37FEAPE

SOT563

CRITICAL

1/10W

603

5%

10

MF-LF

0

402

5%
1/16W
MF-LF

CPUMEM:S3

11 27

33.2K

MF-LF

1/16W

402

1%

MF-LF

1/16W

1%

27.4K

402

DMB53D0UV

CRITICAL

SOT-563

1/16W
MF-LF
402

10K

5%

CRITICAL

DMB53D0UV

SOT-563

11 18 72

0402

CPUMEM:S0

16V

10%
X7R-CERM

0.1UF

201

5%

1/20W

MF

CPUMEM:S0

0

7

18 27 36 38 39 66

11 27

7

18 27 36 39 66

24 27

19 25 27

CPUMEM:SLG

TQFN

SLG4AP022

10%
201

X5R

6.3V

0.1UF

CPUMEM:SLG

27 28 29

27 65

9

27

NOSTUFF

201

0.047UF

10%

6.3V
X5R

10%

0402

X5R-CERM

10V

0.047UF

NO STUFF

402

5%
1/16W

20K

MF-LF

SYNC_DATE=07/29/2011

SYNC_MASTER=J5_MLB

CPU Memory S3 Support

P1V35_S0_DIV

=PP3V3_S3_MEMRESET

=PP5V_S3_MEMRESET

PLT_RESET_L

PM_SLP_S3_L

ISOLATE_CPU_MEM_L_R

PLT_RESET_L

=PP1V5R1V35_S3_CPU_VCCDDR

MEMVTT_EN_L

P1V5CPU_EN_L

PM_MEM_PWRGD

MEMVTT_EN

P1V5CPU_EN

MEM_RESET_L

=PP3V3_S3_MEMRESET

PM_SLP_S4_L

ISOLATE_CPU_MEM_L

=MEM_RESET_L

VTTCLAMP_EN

=DDRVTT_EN

=MEM_RESET_L

MEMVTT_EN

PM_SLP_S3_L

P1V5CPU_EN

=PPVTT_S0_VTTCLAMP

VTTCLAMP_L

=PP5V_S3_MEMRESET

PM_SLP_S4_L

=PP3V3_S5_CPU_VCCDDR

PM_MEM_PWRGD_L

MEMRESET_ISOL_LS5V_L

MAKE_BASE=TRUE

CPU_MEM_RESET_L

ISOLATE_CPU_MEM_L

=PP1V5_S3_MEMRESET

MEM_RESET_L

R2802

1

2

R2810

1

2

R2815

1

2

R2816

1

2

Q2800

3

5

4

Q2805

3

5

4

Q2810

6

2

1

Q2810

3

5

4

Q2800

6

2

1

Q2815

6

2

1

Q2815

3

5

4

Q2805

6

2

1

R2805

1

2

R2801

1

2

Q2850

3

5

4

R2851

1

2

C2851

1

2

Q2850

6

2

1

R2850

1

2

R2817

1 2

R2821

1

2

R2820

1

2

Q2820

5

3

4

R2822

1

2

Q2820

6

2

1

C2816

1

2

R2890

12

U2800

5

9

7

8

3

1

6

11

10

4

2

C2800

1

2

C2817

1

2

C2820

1

2

R2895

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

28 OF 132

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www.vinafix.vn

NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC
NC
NC
NC
NC

NC

NC NC NCNC

NCNCNCNC

NC

NC

ZQ0
ZQ1

ODT1

ODT0

WE*

RAS*
CAS*

BA0

BA2

BA1

A15

A10/AP

A8

NF_DQ4

A4

DQS

DQS*

NF_TDQS*

CS0*

CS1*

NF_DQ7

NF_DQ6

NF_DQ5

DM/TDQS

CKE1

CKE0

CK

CK*

NC

DQ3

A0
A1
A2
A3

A5
A6

A11

A13

A14

DQ2

DQ1

DQ0

RESET*

VDDQ

VDD

VREFDQ

VREFCA

A9

A7

A12/BC*

VSSQ

VSS

NC
NC

ZQ0
ZQ1

ODT1

ODT0

WE*

RAS*
CAS*

BA0

BA2

BA1

A15

A10/AP

A8

NF_DQ4

A4

DQS

DQS*

NF_TDQS*

CS0*

CS1*

NF_DQ7

NF_DQ6

NF_DQ5

DM/TDQS

CKE1

CKE0

CK

CK*

NC

DQ3

A0
A1
A2
A3

A5
A6

A11

A13

A14

DQ2

DQ1

DQ0

RESET*

VDDQ

VDD

VREFDQ

VREFCA

A9

A7

A12/BC*

VSSQ

VSS

ZQ0
ZQ1

ODT1

ODT0

WE*

RAS*
CAS*

BA0

BA2

BA1

A15

A10/AP

A8

NF_DQ4

A4

DQS

DQS*

NF_TDQS*

CS0*

CS1*

NF_DQ7

NF_DQ6

NF_DQ5

DM/TDQS

CKE1

CKE0

CK

CK*

NC

DQ3

A0
A1
A2
A3

A5
A6

A11

A13

A14

DQ2

DQ1

DQ0

RESET*

VDDQ

VDD

VREFDQ

VREFCA

A9

A7

A12/BC*

VSSQ

VSS

ZQ0
ZQ1

ODT1

ODT0

WE*

RAS*
CAS*

BA0

BA2

BA1

A15

A10/AP

A8

NF_DQ4

A4

DQS

DQS*

NF_TDQS*

CS0*

CS1*

NF_DQ7

NF_DQ6

NF_DQ5

DM/TDQS

CKE1

CKE0

CK

CK*

NC

DQ3

A0
A1
A2
A3

A5
A6

A11

A13

A14

DQ2

DQ1

DQ0

RESET*

VDDQ

VDD

VREFDQ

VREFCA

A9

A7

A12/BC*

VSSQ

VSS

ZQ0
ZQ1

ODT1

ODT0

WE*

RAS*
CAS*

BA0

BA2

BA1

A15

A10/AP

A8

NF_DQ4

A4

DQS

DQS*

NF_TDQS*

CS0*

CS1*

NF_DQ7

NF_DQ6

NF_DQ5

DM/TDQS

CKE1

CKE0

CK

CK*

NC

DQ3

A0
A1
A2
A3

A5
A6

A11

A13

A14

DQ2

DQ1

DQ0

RESET*

VDDQ

VDD

VREFDQ

VREFCA

A9

A7

A12/BC*

VSSQ

VSS

ZQ0
ZQ1

ODT1

ODT0

WE*

RAS*
CAS*

BA0

BA2

BA1

A15

A10/AP

A8

NF_DQ4

A4

DQS

DQS*

NF_TDQS*

CS0*

CS1*

NF_DQ7

NF_DQ6

NF_DQ5

DM/TDQS

CKE1

CKE0

CK

CK*

NC

DQ3

A0
A1
A2
A3

A5
A6

A11

A13

A14

DQ2

DQ1

DQ0

RESET*

VDDQ

VDD

VREFDQ

VREFCA

A9

A7

A12/BC*

VSSQ

VSS

ZQ0
ZQ1

ODT1

ODT0

WE*

RAS*
CAS*

BA0

BA2

BA1

A15

A10/AP

A8

NF_DQ4

A4

DQS

DQS*

NF_TDQS*

CS0*

CS1*

NF_DQ7

NF_DQ6

NF_DQ5

DM/TDQS

CKE1

CKE0

CK

CK*

NC

DQ3

A0
A1
A2
A3

A5
A6

A11

A13

A14

DQ2

DQ1

DQ0

RESET*

VDDQ

VDD

VREFDQ

VREFCA

A9

A7

A12/BC*

VSSQ

VSS

ZQ0
ZQ1

ODT1

ODT0

WE*

RAS*
CAS*

BA0

BA2

BA1

A15

A10/AP

A8

NF_DQ4

A4

DQS

DQS*

NF_TDQS*

CS0*

CS1*

NF_DQ7

NF_DQ6

NF_DQ5

DM/TDQS

CKE1

CKE0

CK

CK*

NC

DQ3

A0
A1
A2
A3

A5
A6

A11

A13

A14

DQ2

DQ1

DQ0

RESET*

VDDQ

VDD

VREFDQ

VREFCA

A9

A7

A12/BC*

VSSQ

VSS

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

240

201

MF

1/20W

1%

MF

1/20W

1%

240

201201

240

1%

1/20W

MF

240

1%
1/20W
MF
201201

MF

1/20W

1%

240 240

1%
1/20W
MF
201201

1%

240

MF

1/20W

240

1%
1/20W
MF
201201

MF

1/20W

240

1% 1%

1/20W
MF
201

240

201

240

1%

1/20W

MF

240

1%
1/20W
MF
201201

MF

1/20W

1%

240 240

1%
1/20W
MF
201201

MF

1/20W

1%

240

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

402

10V

20%

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V 6.3V

0.1UF

10%

201

X5R

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V
201

X5R

0.1UF

10%

6.3V

10%

201

0.1UF

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

201

240

1%

1/20W

MF

0.47UF

CERM-X5R-1

4V

201

20%

CERM-X5R-1

20%
4V

201

0.47UF0.47UF

CERM-X5R-1

201

20%

4V

201

CERM-X5R-1

4V

20%

0.47UF0.47UF

20%

CERM-X5R-1

4V

201

CERM-X5R-1

4V

20%

201

0.47UF

20%
4V
CERM-X5R-1
201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

0.47UF

201

4V

20%

CERM-X5R-1

20%
4V
CERM-X5R-1
201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

4V

201

20%

0.47UF

CERM-X5R-1

201

4V

20%

0.47UF

CERM-X5R-1

4V

0.47UF

201

CERM-X5R-1

20%

201

CERM-X5R-1

4V

20%

0.47UF

0.47UF

201

CERM-X5R-1

4V

20%

201

0.47UF

4V

CERM-X5R-1

20%

201

CERM-X5R-1

20%

4V

0.47UF

0.47UF

201

CERM-X5R-1

4V

20%

CERM-X5R-1

0.47UF

201

4V

20%

20%

4V

CERM-X5R-1

201

0.47UF

201

4V

20%

0.47UF

CERM-X5R-1CERM-X5R-1

201

4V

0.47UF

20%

20%

CERM-X5R-1

201

0.47UF

4V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%

201

X5R

6.3V

0.1UF

10%
X5R

6.3V
201201

0.1UF

10%
X5R

6.3V

0.1UF

6.3V
201

X5R

10%

X5R-CERM

2.2UF

402

10V

20%

X5R-CERM

2.2UF

20%
10V

402

2.2UF

X5R-CERM

20%
10V

402

2.2UF

X5R-CERM

20%
10V

402

X5R-CERM

402

10V

20%

2.2UF

X5R-CERM

20%
10V

402

2.2UF

20%
10V

402

2.2UF

X5R-CERM

X5R-CERM

20%
10V

402

2.2UF

402

10V

20%

2.2UF

X5R-CERM

10V
402

2.2UF

X5R-CERM

20%

2.2UF

X5R-CERM

20%
10V

402

10V

20%

X5R-CERM

2.2UF

402

20%
10V

402

X5R-CERM

2.2UF

X5R-CERM

402

10V

2.2UF

20%

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

MT41K1G4

512MX8-4GBIT-DDR3-1600

MT41K1G4

OMIT_TABLE

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

FBGA-10.1X12.6-J4

MT41K1G4

OMIT_TABLE OMIT_TABLE

MT41K1G4

512MX8-4GBIT-DDR3-1600

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-10.1X12.6-J4

MT41K1G4

OMIT_TABLE

MT41K1G4

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

512MX8-4GBIT-DDR3-1600

MT41K1G4

FBGA-10.1X12.6-J4

OMIT_TABLE

MT41K1G4

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

DDR3 SDRAM Bank A (Rank 0)

SYNC_MASTER=J5_MLB

SYNC_DATE=07/14/2011

MEM_A_CAS_L

=PP1V5R1V35_S3_MEM_A

MEM_A_ODT<0>

=PP1V5R1V35_S3_MEM_A

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>
MEM_A_A<3>
MEM_A_A<4>

MEM_A_A<8>
MEM_A_A<9>
MEM_A_A<10>
MEM_A_A<11>

MEM_A_A<14>

MEM_A_CAS_L

MEM_A_ODT<1>

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>

PP0V75_S3_MEM_VREFDQ_A

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<0>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_ODT<0>
MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_ODT<1>MEM_A_ODT<1>

MEM_A_ODT<0>

=PP1V5R1V35_S3_MEM_A

MEM_A_WE_L

MEM_A_A<13>

MEM_A_A<3>

MEM_A_ZQ<12>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_ZQ<8>

MEM_A_WE_L

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_A<12>

MEM_A_A<7>

MEM_A_A<9>

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<2>

MEM_A_A<1>

=PP1V5R1V35_S3_MEM_A

MEM_A_A<8>

MEM_A_A<10>

MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_A<7>

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<13>

MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_A<12>

MEM_A_A<7>

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_A<4>

MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_RAS_L

MEM_A_A<12>

MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<4>

MEM_A_A<8>

MEM_A_A<10>

MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_A<8>

MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<4>

MEM_A_BA<2>

MEM_A_A<6>

MEM_A_A<3>
MEM_A_A<4>

MEM_A_A<8>

MEM_A_BA<1>

MEM_A_RAS_L

MEM_A_A<14>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_CAS_L

MEM_A_A<9>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<10>

MEM_A_A<5>

MEM_A_WE_L

MEM_A_A<8>

MEM_A_A<3>

MEM_A_A<0>

MEM_A_A<14>

MEM_A_A<13>

PP0V75_S3_MEM_VREFCA_A

MEM_A_A<15>

MEM_A_A<0>

MEM_A_A<15> MEM_A_A<15>

MEM_A_ZQ<7>

MEM_A_ZQ<3>

MEM_A_A<12>

MEM_A_ZQ<0>

MEM_A_ZQ<13>

MEM_A_ZQ<9>

MEM_A_ZQ<14>

MEM_A_ZQ<10>

MEM_A_ZQ<15>

MEM_A_ZQ<11>

MEM_A_A<9>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CKE<0>

MEM_A_CS_L<1> MEM_A_CS_L<1>

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_CS_L<0>
MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CS_L<1>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>

MEM_A_CKE<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CS_L<0>

MEM_A_A<12>

MEM_A_DQS_P<3>

MEM_A_DQS_P<5>
MEM_A_DQS_N<5>

MEM_RESET_L MEM_RESET_L

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

MEM_A_DQ<58>

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFCA_A

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<15>

MEM_A_A<12>

MEM_A_A<7>

MEM_A_A<9>

MEM_RESET_L

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<11>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CKE<0>
MEM_A_CKE<1>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_A<4>

MEM_A_A<8>

MEM_A_A<15>

MEM_A_BA<1>
MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_ZQ<2>

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFDQ_A

=PP1V5R1V35_S3_MEM_A

MEM_A_ZQ<4>

MEM_A_A<5>

MEM_A_A<12>

MEM_A_BA<0>

MEM_A_CLK_P<0>

MEM_A_A<7>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_CKE<0>

MEM_RESET_L

MEM_A_BA<2>

MEM_A_RAS_L
MEM_A_CAS_L

MEM_A_BA<0>

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_A<15>

MEM_A_A<8>

MEM_A_A<4>

MEM_A_DQS_P<1>
MEM_A_DQS_N<1>

MEM_A_CS_L<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_A<0>
MEM_A_A<1>
MEM_A_A<2>

MEM_A_A<14>

MEM_RESET_L

=PP1V5R1V35_S3_MEM_A

PP0V75_S3_MEM_VREFDQ_A
PP0V75_S3_MEM_VREFCA_A

MEM_A_A<9>

MEM_A_ZQ<1>

MEM_RESET_L

MEM_A_DQ<5> MEM_A_DQ<9>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<5>

MEM_A_DQS_P<6>
MEM_A_DQS_N<6>

MEM_A_A<15>

MEM_A_DQ<60>

MEM_A_DQ<57>

MEM_A_DQ<63>

MEM_A_DQ<61>

MEM_A_DQ<59>

MEM_A_DQ<62>

MEM_A_DQ<56>

MEM_A_A<5>
MEM_A_A<6>

MEM_A_DQ<52>
MEM_A_DQ<55>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<51>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<43>

MEM_A_DQ<41>

MEM_A_DQ<44>

MEM_A_DQ<42>

MEM_A_A<9>

MEM_A_DQ<40>

MEM_A_CKE<1>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQ<34>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<33>

MEM_A_DQ<39>

MEM_A_DQ<32>

MEM_RESET_L

MEM_A_A<10>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_ODT<1>

MEM_A_ZQ<6>

MEM_A_CAS_L

MEM_A_A<15>

MEM_RESET_L
MEM_A_DQ<28>

MEM_A_DQ<24>

MEM_A_DQ<25>
MEM_A_DQ<29>
MEM_A_DQ<31>

MEM_A_DQ<26>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQ<22>

MEM_A_DQ<21>
MEM_A_DQ<23>
MEM_A_DQ<20>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<19>

MEM_A_DQ<16>

MEM_A_A<10>

MEM_A_DQ<11>

MEM_A_DQ<14>

MEM_A_DQ<12>

MEM_A_DQ<8>

MEM_A_DQ<15>

MEM_A_DQ<10>
MEM_A_DQ<13>

MEM_A_CS_L<0>

MEM_A_ZQ<5>

MEM_A_CKE<1>

MEM_A_CS_L<0>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_DQ<3>

MEM_A_DQS_N<0>

MEM_A_DQ<2>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<7>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_DQS_P<0>

=PP1V5R1V35_S3_MEM_A

MEM_A_CKE<1>

MEM_A_DQS_N<3>

MEM_A_DQ<27>

MEM_A_DQ<30>

C2940

1

2

C2941

1

2

C2943

1

2

C2944

1

2

C2945

1

2

C2953

1

2

C2954

1

2

C2955

1

2

C2963

1

2

C2964

1

2

C2965

1

2

C2973

1

2

C2974

1

2

C2975

1

2

R2900

21

C2907

1

2

C2909

1

2

C2908

1

2

C2919

1

2

C2918

1

2

C2917

1

2

C2929

1

2

C2928

1

2

C2927

1

2

C2939

1

2

C2938

1

2

C2937

1

2

C2979

1

2

C2978

1

2

C2977

1

2

C2969

1

2

C2968

1

2

C2967

1

2

C2959

1

2

C2958

1

2

C2957

1

2

C2949

1

2

C2948

1

2

C2947

1

2

C2935

1

2

C2934

1

2

C2933

1

2

C2925

1

2

C2924

1

2

C2923

1

2

C2915

1

2

C2914

1

2

C2913

1

2

C2905

1

2

C2904

1

2

C2903

1

2

C2901

1

2

C2900

1

2

C2911

1

2

C2951

1

2

C2910

1

2

C2950

1

2

C2921

1

2

C2961

1

2

C2920

1

2

C2960

1

2

C2931

1

2

C2930

1

2

C2971

1

2

C2970

1

2

U2900

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

U2910

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
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12

<BRANCH>

<SCH_NUM>

<E4LABEL>

29 OF 132

28 OF 80

12 28 30 73

8

28

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www.vinafix.vn

ZQ0
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Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SDRAM Bypassing (NOTE: 2x 2.2uF and 3x 0.1uF per chip)

OMIT_TABLE

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

MT41K1G4

OMIT_TABLE

240

1%
1/20W
MF
201 201

MF

1/20W

1%

240

201

240

1%

1/20W

MF

201

MF

1/20W

1%

240

201

240

1%

1/20W

MF

201

MF

1/20W

1%

240

201

240

1%

1/20W

MF

1/20W
201

240

1%
MFMF

1/20W

1%

240

201

201

MF

1/20W

1%

240

201

240

1%

1/20W

MF

201

MF

1/20W

1%

240

201

240

1%

1/20W

MF

201

MF

1/20W

1%

240

201

240

1%

1/20W

MF

MF

1/20W

1%

240

201

0.47UF

CERM-X5R-1

20%

4V

201

0.47UF

CERM-X5R-1
201

4V

20%20%

201

4V

CERM-X5R-1

0.47UF

CERM-X5R-1

0.47UF

201

4V

20%

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%

4V

201

CERM-X5R-1

201

0.47UF

CERM-X5R-1

4V

20%

0.47UF

4V

CERM-X5R-1

20%

201

CERM-X5R-1

0.47UF

20%

4V

201

20%
4V
CERM-X5R-1
201

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

20%
4V

201

CERM-X5R-1

0.47UF

20%

CERM-X5R-1

4V

201

0.47UF

20%

4V

CERM-X5R-1

201

0.47UF

0.47UF

201

CERM-X5R-1

4V

20%

CERM-X5R-1

0.47UF

201

4V

20%

20%

201

CERM-X5R-1

0.47UF

4V

0.47UF

4V
201

CERM-X5R-1

20%

0.47UF

4V

CERM-X5R-1

20%

201

CERM-X5R-1

0.47UF

20%

4V

201

0.47UF

4V

20%
CERM-X5R-1

201

0.47UF

CERM-X5R-1

201

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

2.2UF

X5R-CERM

402

10V

20%

2.2UF

X5R-CERM

20%
10V

402

X5R-CERM

2.2UF

402

10V

20% 20%

10V
402

2.2UF

X5R-CERM

X5R-CERM

2.2UF

402

10V

20%

402

10V

20%

2.2UF

X5R-CERM

20%
10V

402

2.2UF

X5R-CERM

20%
10V

402

2.2UF

X5R-CERM

20%
10V

402

2.2UF

X5R-CERM

2.2UF

X5R-CERM

20%
10V

402

402

10V

20%

2.2UF

X5R-CERM

20%
10V

402

X5R-CERM

2.2UF

20%
10V

402

2.2UF

X5R-CERM

20%
10V

402

X5R-CERM

2.2UF

402

20%

X5R-CERM

10V

2.2UF

20%
10V

402

X5R-CERM

2.2UF

6.3V
X5R
201

10%

0.1UF 0.1UF

6.3V
X5R
201

10%

6.3V
X5R

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10%

201

6.3V
X5R
201

10%

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6.3V
X5R
201

10%

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6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

0.1UF

10%

6.3V

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201

10%

0.1UF

6.3V

X5R
201

10%

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6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF

10%

0.1UF

6.3V
X5R
201

0.1UF

6.3V
X5R
201

10%

X5R

6.3V
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

0.1UF 0.1UF

6.3V
X5R
201

10%

0.1UF

6.3V
X5R
201

10%

512MX8-4GBIT-DDR3-1600

FBGA-10.1X12.6-J4

MT41K1G4

OMIT_TABLE

FBGA-10.1X12.6-J4

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-10.1X12.6-J4

OMIT_TABLE

512MX8-4GBIT-DDR3-1600

MT41K1G4

512MX8-4GBIT-DDR3-1600

OMIT_TABLE

FBGA-10.1X12.6-J4

MT41K1G4

OMIT_TABLE

FBGA-10.1X12.6-J4

512MX8-4GBIT-DDR3-1600

MT41K1G4

DDR3 SDRAM Bank B (Rank 0)

SYNC_DATE=07/14/2011

SYNC_MASTER=J5_MLB

PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B

MEM_B_A<4>

MEM_B_A<2>

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFCA_B

PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B

=PP1V5R1V35_S3_MEM_B

=PP1V5R1V35_S3_MEM_B

PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B

MEM_B_DQ<30>

=PP1V5R1V35_S3_MEM_B

MEM_B_DQ<27>

MEM_B_DQ<29>
MEM_B_DQ<26>

MEM_B_DQS_P<3>
MEM_B_DQS_N<3>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_CKE<0>

MEM_B_CLK_P<0>

=PP1V5R1V35_S3_MEM_B

MEM_B_DQ<32>
MEM_B_DQ<39>
MEM_B_DQ<37>

MEM_B_DQ<35>

PP0V75_S3_MEM_VREFDQ_B

MEM_RESET_L
MEM_B_DQ<41>

MEM_B_DQ<47>

MEM_B_ODT<1>

MEM_B_DQ<45>

MEM_B_A<7>

MEM_B_DQ<50>
MEM_B_DQ<53>
MEM_B_DQ<51>
MEM_B_DQ<48>

MEM_B_DQ<49>
MEM_B_DQ<55>

MEM_B_DQS_P<6>

MEM_B_CS_L<0>

MEM_B_CLK_P<0>

MEM_B_A<8>

MEM_B_DQ<57>
MEM_B_DQ<63>

MEM_B_DQS_N<7>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_CKE<1>

MEM_B_DQ<34>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_DQ<25>

MEM_B_DQ<28>
MEM_B_DQ<31>

MEM_B_DQ<16>

=PP1V5R1V35_S3_MEM_B

MEM_B_CKE<1>

MEM_B_DQ<9>

MEM_B_DQ<11>

MEM_B_A<10>

MEM_B_DQ<5>

MEM_B_DQ<3>

MEM_RESET_L

PP0V75_S3_MEM_VREFDQ_B

=PP1V5R1V35_S3_MEM_B

MEM_B_WE_L

MEM_B_ODT<1>

MEM_B_A<2>

MEM_B_A<11>

MEM_B_ZQ<8>
MEM_B_ZQ<12>

MEM_B_CAS_L

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<1>

PP0V75_S3_MEM_VREFDQ_B

=PP1V5R1V35_S3_MEM_B

MEM_B_A<15> MEM_B_A<15> MEM_B_A<15> MEM_B_A<15>

MEM_B_A<15>MEM_B_A<15>MEM_B_A<15>MEM_B_A<15>

MEM_B_CS_L<1>

MEM_B_CKE<1>
MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CS_L<1>

MEM_B_CKE<1>
MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_CLK_N<0>

MEM_B_CKE<0>

MEM_B_CS_L<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CKE<1>
MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<1>

MEM_B_CKE<1>

MEM_B_CLK_N<0>

MEM_B_CS_L<0>
MEM_B_CKE<0>

MEM_B_CS_L<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<0>
MEM_B_CKE<0>MEM_B_CKE<0>

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CKE<1>

MEM_B_CS_L<1>

MEM_B_DQS_P<7>

MEM_B_DQ<56>
MEM_B_DQ<62>
MEM_B_DQ<61>

MEM_B_DQ<58>

MEM_RESET_L

MEM_B_DQS_N<6>

MEM_B_DQ<52>

MEM_B_DQ<54>

MEM_RESET_L

MEM_B_DQ<42>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQ<46>
MEM_B_DQ<44>

MEM_B_DQ<43>
MEM_B_DQ<40>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQ<36>
MEM_B_DQ<38>
MEM_B_DQ<33>

MEM_RESET_L

MEM_RESET_L

MEM_B_DQ<24>

MEM_B_DQ<19>

MEM_B_DQ<22>

MEM_B_DQ<20>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<23>

MEM_B_DQ<21>

MEM_RESET_L

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_RESET_L
MEM_B_DQ<8>

MEM_B_DQ<12>

MEM_B_DQ<14>

MEM_B_DQ<10>
MEM_B_DQ<13>

MEM_B_DQ<15>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_A<13>

MEM_B_A<6>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<11>
MEM_B_ZQ<15>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<10>
MEM_B_ZQ<14>

MEM_B_ODT<0>

MEM_B_ZQ<9>
MEM_B_ZQ<13>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<3>
MEM_B_ZQ<7>

MEM_B_ODT<0>
MEM_B_ODT<1>

MEM_B_ZQ<2>
MEM_B_ZQ<6>MEM_B_ZQ<5>MEM_B_ZQ<4>

MEM_B_ZQ<0>

MEM_B_ODT<0>

MEM_B_A<12>

MEM_B_A<0>
MEM_B_A<1>

MEM_B_A<5>

MEM_B_A<7>
MEM_B_A<8>

MEM_B_DQ<4>

MEM_B_DQ<2>

MEM_B_DQ<7>

MEM_B_DQ<0>

MEM_B_DQ<6>

MEM_B_DQ<1>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_BA<1>
MEM_B_BA<2>

MEM_B_RAS_L
MEM_B_CAS_L

MEM_B_A<14>

PP0V75_S3_MEM_VREFCA_B

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_A<4>

MEM_B_BA<2>

MEM_B_A<1>

MEM_B_A<8>

MEM_B_BA<0>

PP0V75_S3_MEM_VREFCA_B

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_WE_L

MEM_B_RAS_L
MEM_B_CAS_L

MEM_B_BA<1>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>
MEM_B_A<6>

MEM_B_A<11>

MEM_B_A<13>
MEM_B_A<14>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<12>

MEM_B_WE_L

MEM_B_RAS_L
MEM_B_CAS_L

MEM_B_BA<0>
MEM_B_BA<1>

MEM_B_A<10>

MEM_B_A<8>

=PP1V5R1V35_S3_MEM_B

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>
MEM_B_A<6>

MEM_B_A<11>

MEM_B_A<13>
MEM_B_A<14>

PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B

MEM_B_A<9>

MEM_B_A<12>

MEM_B_WE_L

MEM_B_RAS_L
MEM_B_CAS_L

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_A<10>

MEM_B_A<4>

MEM_B_A<0>

MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>
MEM_B_A<6>

MEM_B_A<11>

MEM_B_A<13>
MEM_B_A<14>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<12>

MEM_B_WE_L

MEM_B_RAS_L
MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_A<10>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<0>
MEM_B_A<1>

MEM_B_A<3>

MEM_B_A<5>
MEM_B_A<6>

MEM_B_A<13>
MEM_B_A<14>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<12>

MEM_B_WE_L

MEM_B_RAS_L
MEM_B_CAS_L

MEM_B_A<10>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<11>

MEM_B_A<13>
MEM_B_A<14>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<12>

MEM_B_RAS_L
MEM_B_CAS_L

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_A<10>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>
MEM_B_A<6>

MEM_B_A<11>

MEM_B_A<13>
MEM_B_A<14>

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<12>

MEM_B_WE_L

MEM_B_RAS_L

MEM_B_BA<0>

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_A<8>

MEM_B_A<4>

MEM_B_A<0>
MEM_B_A<1>
MEM_B_A<2>
MEM_B_A<3>

MEM_B_A<5>
MEM_B_A<6>

MEM_B_A<11>

MEM_B_A<14>

PP0V75_S3_MEM_VREFDQ_B
PP0V75_S3_MEM_VREFCA_B

MEM_B_A<9>

MEM_B_A<7>

MEM_B_A<12>

MEM_B_A<10>

MEM_B_A<3>

MEM_B_A<6>

MEM_B_A<11>

MEM_B_A<13>

MEM_B_A<9>

R3100

2

1

C3107

1

2

C3109

1

2

C3108

1

2

C3119

1

2

C3118

1

2

C3117

1

2

C3129

1

2

C3128

1

2

C3127

1

2

C3139

1

2

C3138

1

2

C3137

1

2

C3179

1

2

C3178

1

2

C3177

1

2

C3169

1

2

C3168

1

2

C3167

1

2

C3159

1

2

C3158

1

2

C3157

1

2

C3149

1

2

C3148

1

2

C3147

1

2

C3140

1

2

C3100

1

2

C3141

1

2

C3150

1

2

C3101

1

2

C3110

1

2

C3151

1

2

C3111

1

2

C3160

1

2

C3161

1

2

C3120

1

2

C3121

1

2

C3170

1

2

C3171

1

2

C3130

1

2

C3131

1

2

C3143

1

2

C3144

1

2

C3103

1

2

C3104

1

2

C3145

1

2

C3153

1

2

C3105

1

2

C3113

1

2

C3154

1

2

C3114

1

2

C3155

1

2

C3163

1

2

C3115

1

2

C3123

1

2

C3164

1

2

C3165

1

2

C3124

1

2

C3125

1

2

C3173

1

2

C3133

1

2

C3134

1

2

C3174

1

2

C3175

1

2

C3135

1

2

U3100

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

U3110

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

U3120

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

U3130

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

U3140

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

U3150

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

U3160

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

U3170

K3
L7

H7
M7
K7
N3
N7
J7

L3
K2
L8
L2
M8
M2
N8
M3

J2
K8
J3

G3

F7
G7

G9
F9

H2

H1

B7

B3
C7
C2
C8

C3
D3

A3
79
80
81
82

E3
E8
D2
E7

A7

G1
F1

F3

N2

A2A9D7G2G8K1K9M1M9B9C1E2E9J8E1

A1

A8

N1

N9

B1D8F2F8J1J9L1

L9

B2B8C9D1D9

H3

H8
H9

R3101

1

2

R3111

1

2

R3110

2

1

R3121

1

2

R3120

2

1

R3131

1

2

R3130

2

1

R3141

1

2

R3140

2

1

R3151

1

2

R3150

2

1

R3161

1

2

R3160

2

1

R3171

1

2

R3170

2

1

<BRANCH>

<SCH_NUM>

<E4LABEL>

31 OF 132

29 OF 80

29 31 72

29 31 72

12 29
30 73

12 29
30 73

8

29

29 31 72

29 31 72

29 31 72

8

29

8

29

29 31 72

29 31 72

7

12 73

8

29

7

12 73

7

12 73

12 73

12 73

12 73

12 29 30 73

12 29 30 73

12 29 30 73

12 29
30 73

8

29

7

12 73

7

12 73

7

12 73

7

12 73

29 31 72

27 28 29

12 73

7

12 73

12 29 30 73

7

12 73

7

12 73

7

12 73

7

12 73

12 73

7

12 73

7

12 73

12 73

12 29 30
73

12 29
30 73

12 29
30 73

7

12 73

7

12 73

12 73

7

12 73

7

12 73

12 29 30 73

7

12 73

12 29 30 73

12 29 30
73

12 29 30
73

7

12 73

7

12 73

7

12 73

7

12 73

8

29

12 29 30
73

7

12 73

7

12 73

12 29
30 73

7

12 73

12 73

27 28 29

29 31 72

8

29

12 29
30 73

12 29
30 73

12 29
30 73

12 29
30 73

12 29 30 73

12 29
30 73

12 29 30 73

29 31 72

8

29

12 29
30 73

12 29 30 73 12 29 30 73 12 29 30 73

12 29 30 73 12 29 30 73 12 29 30 73 12 29

30 73

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73

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30 73

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30 73

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30 73

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73

12 29
30 73

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73

12 29 30
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30 73

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30 73

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73

12 29 30
73

12 73

7

12 73

7

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7

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12 73

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73

12
29 30 73

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30 73

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73

12
29 30 73

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www.vinafix.vn

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

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IN

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IN

IN

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IN

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IN

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IN

IN

IN

IN

IN
IN

IN

IN
IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

JEDEC 4.20.18 Unbuffered SODIMM Raw Card F spec recommends 36 Ohm term to VTT for CS,CKE,ODT and 36 Ohm for BA,A,RAS,CAS,WE

Place Source Cterm at neckdown at first DRAM

Place RC end termination after last DRAM

MEM Clock Termination

12 29 73

36

5%

1/32W

4X0201

1/32W

5%

36

4X0201

1/32W

36

5%

4X0201

1/32W

36

5%

4X0201

1/32W

4X0201

5%

36

1/32W

5%

36

4X0201

1/32W

5%

36

4X0201

0.47UF

20%
4V

201

CERM-X5R-1

20%
4V
CERM-X5R-1
201

0.47UF

20%
4V
CERM-X5R-1
201

0.47UF

0.47UF

201

CERM-X5R-1

4V

20%

36

1/32W

4X0201

5%

CERM-X5R-1

0.47UF

201

4V

20%

0.47UF

201

CERM-X5R-1

4V

20%

4V
201

0.47UF

CERM-X5R-1

20%

20%

201

0.47UF

CERM-X5R-1

4V

0.47UF

CERM-X5R-1

4V
201

20%

5%

4X0201

36

1/32W

0.1UF

201

X5R

6.3V

10%

0.1UF

201

X5R

6.3V

10%

201

5%
MF

1/20W

30

36

4X0201

1/32W

5%

30

1/20W

MF

5%

201

PLACE_NEAR=U2900.F7:3.2mm

5%

25V
201

CERM

3.3PF

1/20W

MF

5%

201

30

201

5%
MF

1/20W

30

PLACE_NEAR=U3170.F7:3.2mm

5%

25V
201

CERM

3.3PF

12 28 73

12 28 73

12 29 73

12 29 73

0.47UF

201

CERM-X5R-1

4V

20%

1/32W

4X0201

5%

36

1/32W

4X0201

5%

36

5%

1/32W

4X0201

36

12 29 73

1/32W

5%

4X0201

36

20%
4V
CERM-X5R-1
201

0.47UF

12 29 73

1/32W

4X0201

36

5%

12 29 73

36

4X0201

1/32W

5%

12 28 73

36

5%

1/32W

4X0201

12 28 73

4X0201

36

5%

1/32W

12 29 73

12 28 73

0.47UF

201

CERM-X5R-1

4V

20%

12 28 73

12 28 73

12 29 73

12 29 73

12 29 73

12 29 73

12 28 73

36

4X0201

1/32W

5%

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 29 73

12 28 73

12 28 73

12 28 73

12 28 73

12 29 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

36

5%

4X0201

1/32W

1/32W

36

5%

4X0201

1/32W

36

4X0201

5%

4X0201

1/32W

36

5%

1/32W

4X0201

5%

36

12 29 73

5%361/32W

4X0201

5%361/32W

4X0201

4X0201

1/32W

36

5%

5%

36

1/32W

4X0201

36

5%

1/32W

4X0201

1/32W

4X0201

36

5%

36

5%

4X0201

1/32W

4X0201

1/32W

36

5%

36

5%

1/32W

4X0201

36

1/32W

5%

4X0201

12 29 73

1/32W

4X0201

36

5%

36

4X0201

5%

1/32W

CERM-X5R-1

4V

20%

0.47UF

201

CERM-X5R-1

20%
4V

201

0.47UF

CERM-X5R-1

0.47UF

20%
4V

201

36

4X0201

1/32W

5%

36

5%

4X0201

1/32W

4X0201

1/32W

5%

36

4X0201

36

5%

1/32W

36

4X0201

5%

1/32W

12 29 73

36

5%

1/32W

4X0201

4X0201

36

5%

1/32W

5%

36

4X0201

1/32W

5%

36

4X0201

1/32W

20%
4V
CERM-X5R-1
201

0.47UF

20%
4V

201

CERM-X5R-1

0.47UF

20%
4V
CERM-X5R-1
201

0.47UF

5%

4X0201

1/32W

36

12 28 73

12 28 73

36

5%

4X0201

1/32W

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

12 28 73

5%361/32W

4X0201

12 28 73

12 28 73

4X0201

1/32W

36

5%

4X0201

36

1/32W

5%

36

4X0201

5%

1/32W

4X0201

36

5%

1/32W

5%

1/32W

4X0201

36

1/32W

5%

4X0201

36

1/32W

5%

4X0201

36

1/32W

5%

4X0201

36

SYNC_DATE=MASTER

DDR3 Termination

SYNC_MASTER=MASTER

MEM_A_CS_L<1>

MEM_B_WE_L

=PP0V75_S0_MEM_VTT_B

MEM_B_CKE<0>

MEM_B_CAS_L

MEM_A_CKE<0>

MEM_A_BA<0>

MEM_A_A<15>

MEM_B_CLK0_TERM_R

MEM_A_A<11>
MEM_A_BA<1>

MEM_A_CLK_P<0>

MEM_B_CLK_N<0>

MEM_A_CKE<1>

MEM_A_A<5>

MEM_A_A<10>

MEM_A_A<0>

MEM_A_CS_L<0>
MEM_A_RAS_L

MEM_A_A<6>

MEM_B_A<13>

MEM_A_CLK0_TERM_R

MEM_A_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_A<14>

MEM_A_A<12>

MEM_A_A<4>

MEM_B_RAS_L

MEM_B_CS_L<0>

MEM_B_A<15>

MEM_B_A<12>

MEM_B_A<0>

MEM_B_CS_L<1>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_ODT<0>

MEM_B_A<6>

MEM_B_BA<0>

MEM_B_ODT<1>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<14>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_A<9>
MEM_A_WE_L

MEM_B_CKE<1>

MEM_B_A<2>

MEM_B_A<7>

MEM_B_BA<1>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<3>
MEM_B_A<10>

MEM_B_A<1>

MEM_B_A<11>

MEM_B_BA<2>

=PP0V75_S0_MEM_VTT_A

MEM_A_BA<2>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<3>

MEM_A_CAS_L

MEM_A_A<13>

RP3330

3 6

RP3326

1 8

RP3330

1 8

RP3328

2 7

RP3330

2 7

RP3324

2 7

C3330

1

2

C3328

1

2

C3326

1

2

RP3320

1 8

RP3324

4 5

RP3330

4 5

RP3320

3 6

RP3320

2 7

RP3322

2 7

RP3322

4 5

RP3326

3 6

RP3328

3 6

RP3328

4 5

RP3326

2 7

RP3324

3 6

RP3322

3 6

RP3320

4 5

RP3328

1 8

RP3324

1 8

RP3322

1 8

RP3326

4 5

C3324

1

2

C3322

1

2

C3320

1

2

RP3306

3 6

RP3301

1 8

RP3301

3 6

RP3304

4 5

RP3304

2 7

RP3307

4 5

RP3302

4 5

RP3303

3 6

RP3307

1 8

C3310

1

2

C3308

1

2

C3306

1

2

RP3307

2 7

RP3303

4 5

RP3304

1 8

RP3306

4 5

RP3302

3 6

RP3304

3 6

RP3303

2 7

RP3307

3 6

RP3306

1 8

RP3303

1 8

RP3302

1 8

RP3301

2 7

RP3301

4 5

RP3302

2 7

RP3306

2 7

C3304

1

2

C3302

1

2

C3300

1

2

C3323

1

2

C3327

1

2

C3325

1

2

C3307

1

2

C3303

1

2

C3305

1

2

C3351

1 2

C3361

1 2

R3350

1 2

R3351

1 2

C3350

1

2

R3360

1 2

R3361

1 2

C3360

1

2

RP3305

1 8

RP3305

2 7

RP3325

2 7

RP3325

3 6

RP3325

1 8

RP3305

3 6

RP3305

4 5

RP3325

4 5

<BRANCH>

<SCH_NUM>

<E4LABEL>

33 OF 132

30 OF 80

8

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www.vinafix.vn

OUT

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

IN

D

S G

D

S G

NC

NC

NC

NC

NC

NC

RESET*

A0
A1
A2

SCL
SDA

P0
P1
P2

P5
P6
P7

P3
P4

THRM

VCC

GND

PAD

NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Signal aliases required by this page:

- =PPDDR_S3_MEMVREF

- =PP3V3_S3_VREFMRGN

Power aliases required by this page:

Page Notes

- =PPVTT_S3_DDR_BUF

- =I2C_VREFDACS_SCL

- =I2C_PCA9557D_SCL

DDRVREF_DAC - Stuffs Apple margining circuit.

VREFDQ:LDO_DAC - Margined LDO outputs sent to DQ inputs.

VREFDQ:M1_DAC - DAC margined DDR voltage divider sent to DQ inputs.

VREFCA:LDO_DAC - DAC margined LDO outputs sent to CA inputs.

+61uA - -61uA (- = sourced)

Addr=0x98(WR)/0x99(RD)

Required zero ohm resistors when no VREF margining circuit stuffed

8.59mV / step @ output

MEM B VREF CA

watchdog will disable margining.

3

C

1.267V (DAC: 0x8B)

0.000V - 3.300V (0x00 - 0xFF)

GPU Frame Buffer (1.8V, 70% VRef)

1.056V - 1.442V (+/- 180mV)

+6.0mA - -5.0mA (- = sourced)

1.51mV / step @ output

MEM A VREF CA

4

(OD)

PCA9557D Pin:
Nominal value

DAC Channel:

A

2

B

0.300V - 1.200V (+/- 450mV)

C

0.000V - 1.501V (0x00 - 0x74)

5

D

MEM VREG

1.000V - 2.000V (+/- 500mV)

0.000V - 3.000V (0x00 - 0x74)

6

D

a DAC output, cannot enable

NOTE: MEMVREG and FRAMEBUF share

10mA max load

Addr=0x30(WR)/0x31(RD)

VREFDQ:LDO - LDO outputs sent to DQ inputs.

VREFCA:LDO - LDO outputs sent to CA inputs.

BOM options provided by this page:

- =I2C_PCA9557D_SDA

- =I2C_VREFDACS_SDA

DAC range:

1

DDR3L (1.35V) 6.99mV per step

both at the same time!

MEM A VREF DQ MEM B VREF DQ

Margined target:

VRef current:
DAC step size:

7.69mV / step @ output

+3.4mA - -3.4mA (- = sourced)

0.75V (DAC: 0x3A) 1.5V (DAC: 0x3A)

DDR3 (1.5V) 7.70mV per step

NOTE: CPU DAC output step sizes:

soft-resets and sleep/wake cycles.

NOTE: Margining will be disabled across all

RST* on ’platform reset’ so that system

VREFDQ:M1_M3 - CPU margined DDR voltage divider sent to DQ inputs.

buffers at once or VRef source may be overloaded.

NOTE: Must not enable more than two SO-DIMM margining

60

0.1UF

DDRVREF_DAC

20%

402

10V

CERM

33.2K

1%

1/16W

402

DDRVREF_DAC

MF-LF

PLACE_NEAR=R7320.2:1mm

DDRVREF_DAC

1/16W

5%

402

MF-LF

100K

DDRVREF_DAC

402

1/16W

5%
MF-LF

100K

DDRVREF_DAC

CRITICAL

MAX4253

UCSP

CRITICAL

DDRVREF_DAC

MAX4253

UCSP

UCSP

MAX4253

DDRVREF_DAC

CRITICAL

DDRVREF_DAC

CRITICAL

UCSP

MAX4253

DDRVREF_DAC

UCSP

MAX4253

CRITICAL

DDRVREF_DAC

UCSP

CRITICAL

MAX4253

200

VREFCA:LDO_DAC

402

MF-LF

1/16W

1%

PLACE_NEAR=R3410.2:2.54mm

VREFCA:LDO_DAC

MF-LF

402

1%

200

1/16W

PLACE_NEAR=R3412.2:2.54mm

SHORT

402

NONE

NONE
NONE

OMIT

SHORT

NONE

NONE

402

NONE

OMIT

25

PLACE_NEAR=R3404.2:2.54mm

VREFDQ:LDO_DAC

MF-LF

1/16W

200

1%

402

PLACE_NEAR=R3403.2:1mm

VREFDQ:LDO_DAC

402

133

1/16W

1%

MF-LF

PLACE_NEAR=R3406.2:2.54mm

VREFDQ:LDO_DAC

1/16W

1%

MF-LF

200

402

PLACE_NEAR=R3405.2:1mm

VREFDQ:LDO_DAC

402

MF-LF

1/16W

133

1%

DDRVREF_DAC

0

MF-LF

5%

402

1/16W

1/16W

5%

402

MF-LF

0

DDRVREF_DAC

PLACE_NEAR=Q3420.3:2mm

0402

X7R-CERM

16V

0.1UF

10%

VREFDQ:M1_M3

CRITICAL

SOT563

SSM6N15FEAPE

VREFDQ:M1_M3

PLACE_NEAR=Q3420.6:2mm

0402

X7R-CERM

16V

VREFDQ:M1_M3

0.1UF

10%

SSM6N15FEAPE

SOT563

CRITICAL

VREFDQ:M1_M3

PLACE_NEAR=R3421.2:1mm

VREFDQ:M1_M3

1K

1%
1/16W
MF-LF
402

PLACE_NEAR=R3441.2:1mm

MF-LF

VREFDQ:M1_M3

402

1K

1/16W

1%

PLACE_NEAR=Q3420.6:1mm

1%

402

VREFDQ:M1_M3

MF-LF

1/16W

1K

PLACE_NEAR=Q3420.3:1mm

402

MF-LF

VREFDQ:M1_M3

1K

1%
1/16W

DDRVREF_DAC

402

1/16W

5%
MF-LF

100K

DDRVREF_DAC

MF-LF

1/16W

5%

402

100K

PLACE_NEAR=R3409.2:1mm

1/16W

133

1%

MF-LF

402

VREFCA:LDO_DAC

DDRVREF_DAC

1/16W

100K

5%

402

MF-LF

PCA9557

CRITICAL

QFN

DDRVREF_DAC

DDRVREF_DAC

CERM

402

10V

20%

0.1UF

PLACE_NEAR=R3411.2:1mm

VREFCA:LDO_DAC

133

1%

402

MF-LF

1/16W

DDRVREF_DAC

402

5%

MF-LF

1/16W

100K

42

42

DDRVREF_DAC

DAC5574

MSOP

CRITICAL

42

42

DDRVREF_DAC

402

0.1UF

10V

20%
CERM

DDRVREF_DAC

402-LF

CERM

2.2UF

20%

6.3V

DDRVREF_DAC

20%

CERM

10V
402

0.1UF

DDRVREF_DAC

0.1UF

20%

402

10V

CERM

2

R3409,R3411

VREFCA:LDO

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

4

R3421,R3422,R3441,R3442

VREFDQ:M1_DAC

114S0218

RES,MTL FILM,1K,1%,0402,SM,LF

R3403,R3405

2

VREFDQ:LDO

116S0004

RES,MTL FILM,0,5%,0402,SM,LF

SYNC_MASTER=J5_MLB

DDR3/FRAMEBUF VREF MARGINING

SYNC_DATE=07/29/2011

114S0171

RES,MTL FILM,332,1%,0402,SM,LF

2

R3404,R3406

VREFDQ:M1_DAC

VREFMRGN_MEMVREG_EN

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_DQ_SODIMMB_EN

=PP3V3_S3_VREFMRGN

VREFMRGN_SODIMMS_CA

=PPVTT_S3_DDR_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_SODIMMB_DQ

VREFMRGN_FRAMEBUF_BUF

PPCPU_MEM_VREFDQ_A

=PPDDR_S3_MEMVREF

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

VREFMRGN_MEMVREG_FBVREF_R

VREFMRGN_FRAMEBUF_BUF_R

MEMRESET_ISOL_LS5V_L

PPCPU_MEM_VREFDQ_B

=I2C_PCA9557D_SCL

=I2C_VREFDACS_SCL

PCA9557D_RESET_L

MEMRESET_ISOL_LS5V_L

DDRREG_FB

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_SODIMMA_DQ

VREFMRGN_MEMVREG_BUF

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_FRAMEBUF_EN

PP3V3_S3_VREFMRGN_CTRL

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

PP3V3_S3_VREFMRGN_DAC

MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm
VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

VOLTAGE=0.75V

PP0V75_S3_MEM_VREFCA_B

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm

VREFMRGN_MEMVREG_FBVREF

VREFMRGN_CA_SODIMMB_EN

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFDQ_A

=PPDDR_S3_MEMVREF

U3401

3
4

5

8

6

7
9

10
11

12

13
14

15

1
2

17

16

C3403

1

2

C3402

1

2

R3402

1

2

R3401

1

2

R3410

1 2

R3407

1

2

C3404

1

2

R3412

1 2

R3408

1

2

U3400

9

10

3

6

7

8

1

2

4

5

C3401

1

2

C3400

1

2

C3405

1

2

R3414

1 2

R3413

1

2

R3415

1

2

U3402

C3

C2

C1

C4

B1

B4

U3403

A3

A2

A1

A4

B1

B4

U3402

A3

A2

A1

A4

B1

B4

U3403

C3

C2

C1

C4

B1

B4

U3404

A3

A2

A1

A4

B1

B4

U3404

C3

C2

C1

C4

B1

B4

R3409

1 2

R3411

1 2

R3418

1 2

R3419

1 2

R3403

1 2

R3404

1 2

R3405

1 2

R3406

1 2

R3417

1

2

R3416

1

2

C3440

1

2

Q3420

3

5

4

C3420

1

2

Q3420

6

2

1

R3422

1

2

R3442

1

2

R3421

1

2

R3441

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

34 OF 132

31 OF 80

8

8

60

10 72

8

31

27 31

10 72

27 31

29 31 72

28 31 72

29 72

28 72

29 31 72

28 31 72

8

31

www.vinafix.vn

BI

IN

SYM_VER-1

BI

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

206 mA nominal max

275 mA peak

518S0767

ALS

CAMERA

CRITICAL

819Q-3506-K281

F-RT-SM

42

42

PLACE_NEAR=J3502.2:2.54MM

CRITICAL

90-OHM

DLP0NS

19 74

19 74

0.1uF

CERM
402

20%
10V

PLACE_NEAR=J3502.4:2.54MM

FERR-120-OHM-1.5A

0402-LF

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

ALS/CAMERA CONNECTOR

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm

PP5V_S3_ALSCAMERA_F

=PP5V_S3_ALSCAMERA

=I2C_ALS_SCL

USB_CAMERA_P

USB_CAMERA_N

USB_CAMERA_CONN_P

USB_CAMERA_CONN_N

=I2C_ALS_SDA

J3502

7

8

1

2

3

4

5

6

L3507

4 3

21

C3552

1

2

L3508

12

<BRANCH>

<SCH_NUM>

<E4LABEL>

35 OF 132

32 OF 80

7

8

7

74

7

74

www.vinafix.vn

OUT

OUT

BI

BI

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

BI

BI

IN

IN
IN
IN
OUT

PETN_3

PETN_2

PETP_2

PETP_1
PETN_1

PETP_0
PETN_0

MONOBS_N

MONDC0
MONDC1

PERN_3

PERP_3

PERN_2

PERP_2

PERN_1

PERP_1

PERP_0
PERN_0

MONOBS_P

TMU_CLK_IN

TMU_CLK_OUT

DPSRC_3_P

DPSRC_2_P

DPSRC_3_N

DPSRC_1_P

DPSRC_2_N

DPSRC_1_N

DPSRC_0_P

DPSRC_AUX_P

DPSRC_0_N

DPSRC_HPD_OD

DPSRC_AUX_N

GPIO_2/GO2SX

GPIO_15

GPIO_9/OK2GO2SX_OD*

GPIO_14

GPIO_8/EN_CIO_PWR_OD*

GPIO_7/CIO_SCL_OD

GPIO_6/CIO_SDA_OD

GPIO_5/CIO_PLUG_EVENT

GPIO_4/WAKE_N_OD

GPIO_3

PB_CIO3_TX_N/DP_SRC_2_N

PB_CONFIG2/CIO_2_LSOE

PB_CIO2_RX_N

PB_CONFIG1/CIO_2_LSEO

PB_CIO2_RX_P

PB_CIO2_TX_P/DP_SRC_0_P
PB_CIO2_TX_N/DP_SRC_0_N

PB_CIO3_TX_P/DP_SRC_2_P

PB_DPSRC_3_N

PB_DPSRC_1_N

PB_DPSRC_1_P

PB_LSRX/CIO_3_LSOE

PB_CIO3_RX_N

PB_LSTX/CIO_3_LSEO

PB_CIO3_RX_P

PB_DPSRC_3_P

GPIO_11/PB_CIO_SEL/BYP1

GPIO_13/PB_DP_PWRDN/BYP2

GPIO_1/PB_HV_EN/BYP0

PB_DPSRC_HPD

PB_AUX_N

PB_AUX_P

THERMDA

EE_DI
EE_DO
EE_CS_N

TDI

EE_CLK

TDO

DPSNK0_2_P

DPSNK0_3_N

DPSNK0_1_P

DPSNK0_2_N

DPSNK0_0_P

DPSNK0_1_N

DPSNK0_AUX_P

DPSNK0_0_N

DPSNK0_HPD

DPSNK0_AUX_N

DPSNK1_3_N

DPSNK1_3_P

DPSNK1_2_N

DPSNK1_2_P

DPSNK1_1_N

DPSNK1_1_P

DPSNK1_0_N

DPSNK1_0_P

DPSNK1_AUX_N

DPSNK1_AUX_P

DPSNK1_HPD

PA_CIO0_TX_N/DP_SRC_0_N

PA_CIO0_TX_P/DP_SRC_0_P

PA_CIO0_RX_N

PA_CIO0_RX_P

PA_CONFIG2/CIO_0_LSOE

PA_CONFIG1/CIO_0_LSEO

PA_CIO1_TX_N/DP_SRC_2_N

PA_CIO1_TX_P/DP_SRC_2_P

PA_CIO1_RX_N

PA_CIO1_RX_P

PA_LSRX/CIO_1_LSOE

PA_LSTX/CIO_1_LSEO

PA_DPSRC_1_N

PA_DPSRC_1_P

PA_DPSRC_3_N

PA_DPSRC_3_P

PA_AUX_P

PA_DPSRC_HPD

PA_AUX_N

GPIO_10/PA_CIO_SEL/BYP1

GPIO_0/PA_HV_EN/BYP0

GPIO_12/PA_DP_PWRDN/BYP2

PETP_3

RSENSE

REFCLK_100_IN_P
REFCLK_100_IN_N

XTAL_25_IN

XTAL_25_OUT

TMS
TCK

TEST_EN
TEST_PWR_GOOD

DPSNK0_3_P

PWR_ON_POC_RSTN

PERST_N

NC

RBIAS

PCIE_RST_0_N
PCIE_RST_1_N

PCIE_RST_3_N

PCIE_RST_2_N

PCIE_CLKREQ_OD_N

EN_LC_PWR

PCIE RESET

PCIE GEN2

MISC

(SYM 1 OF 2)

CLOCKS

JTAG/TEST PORT

RECEIVE

TRANSMIT

EEPROM

SINK PORT 0SINK PORT 1

SOURCE PORT 0

PORT3 PORT2

PORT0PORT1

DISPLAYPORT

PORTS

OUT

NC

IN

IN
IN

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT
OUT

IN

OUT

IN

IN

OUT

OUT

IN

OUT

IN

IN

OUT
OUT

OUT

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

IN

OUT

IN

IN

OUT

OUT

D

C

Q

S*

W*

HOLD*

PAD

VSS

THM

VCC

IN

OUT

OUT

OUT

IN

BI

OUT

IN

OUT

BI

IN

IN

IN

IN

IN

IN

IN

IN

OUT

OUT

OUT

OUT

OUT

OUT

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(TBT_SPI_MISO)

Use AA8 GND ball for THERM_DN

(TBT_SPI_CLK)

(TBT_SPI_CS_L)

SNK1 AC Coupling

(TBT_SPI_MOSI)

DEBUG: For monitoring current/voltage

SNK0 AC Coupling

WF: Verify logic level!

For unused port, pull CONFIG1, CONFIG2, LSRX, HPD and CIO_SEL low (10k). All other port signals can be NC.

(FORCE_PWR)

Not used in host mode.

(TBT_EN_CIO_PWR_L)

5 - PCIE_RST_1_N

7 - PCIE_RST_3_N

4 - GPIO_5

2 - GPIO_2
3 - GPIO_3

1 - GPIO_1

0 - GPIO_13

10 - GPIO_14
11 - GPIO_0
12 - GPIO_12
13 - GPIO_10
14 - PB_LSTX
15 - PB_LSRX

8 - GPIO_15
9 - GPIO_11

NOTE: The following pins require testpoints:

6 - PCIE_RST_2_N

Divides 3.3V to 1.8V

R3681 for CYA,
allows separation
of GPIO_2/GPIO_9

Stuff one of R3861/2.

if necessary.

DEBUG: For monitoring clock

3.3K

MF

201

5%

1/20W

9

9

0

MF

201

5%

1/20W

100K

MF

201

1/20W

5%

100K

MF

201

5%

1/20W

100K

MF

201

5%

1/20W

0

MF
201

5%
1/20W

3.3K

MF
201

5%
1/20W

0.1UF

X5R-CERM0201

10% 16V

9

79

9

79

9

79

9

79

9

79

9

79

9

79

9

79

9

79

9

79

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

1K

MF
201

1%
1/20W

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

9

79

9

79

9

79

9

79

9

79

9

79

9

79

9

79

1UF

CERM

402

10%

6.3V

9

79

9

79

35

20

20

20

20

OMIT_TABLE

CACTUSRIDGE4C

FCBGA

CRITICAL

35

25 74

10K

MF
201

5%
1/20W

806

MF

1%

1/20W

201

1K

MF
201

5%
1/20W

NO STUFF

10K

MF

201

5%

1/20W

7

17 75

7

17 75

33 69

69

33 35

69

69 76

69 76

69 76

69 76

69 76

69 76

69

69

7

69 76

7

69 76

7

69 76

7

69 76

69

69

7

69 76

7

69 76

7

69 76

7

69 76

33 70

70

33 35

70

70 76

70 76

70 76

70 76

70 76

70 76

70

70

7

70 76

7

70 76

7

70 76

7

70 76

70

70

7

70 76

7

70 76

7

70 76

7

70 76

OMIT_TABLE

CRITICAL

M95256-RMC6XG

MLP

35

35

NO STUFF

0.1UF

X5R-CERM

0201

10%
16V

47K

MF

201

5%

1/20W

OMIT

NOSTUFF

NONE
0201

NONE
NONE

33 68

35

42

42

40

25

10K

MF

201

5%

1/20W

0.1UF

X5R-CERM0201

10% 16V

10K

MF
201

5%
1/20W

10K

MF
201

5%
1/20W

10K

MF

201

5%

1/20W

10K

MF

201

5%

1/20W

1/20W

5%

201

MF

10K

1/20W

5%

201

MF

10K

NO STUFF

MF
201

5%
1/20W

100K

20

0.1UF

X5R-CERM0201

10% 16V

20 33

1/20W

5%

201

MF

0

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

3.3K

MF

201

5%

1/20W

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

0201

10% 16V

X5R-CERM

0.1UF

X5R-CERM0201

10% 16V

3.3K

MF
201

5%
1/20W

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

0.1UF

X5R-CERM0201

10% 16V

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

7 9

75

SYNC_MASTER=J5_MLB_KEPLER

Thunderbolt Host (1 of 2)

SYNC_DATE=11/14/2011

TBT_CIO_PLUG_EVENT

=PP3V3_S4_TBT

TBT_A_HV_EN
TBT_B_HV_EN

TBT_B_DP_PWRDN

TBT_A_DP_PWRDN

TBT_MONOBSN

TBT_EN_LC_PWR

PCIE_CLK100M_TBT_N

TP_DP_TBTSRC_ML_CN<3>

TBT_GPIO_9
TBT_GPIO_14

TBT_GO2SX_BIDIR

TP_DP_TBTSRC_ML_CP<1>

TP_DP_TBTSRC_ML_CN<2>

TP_DP_TBTSRC_ML_CP<2>

TBT_RSENSE

TBT_RBIAS

TP_TBT_PCIE_RESET1_L

TP_DP_TBTSRC_ML_CN<1>

TBT_GO2SX_BIDIR

DP_TBTSNK0_ML_P<1>

TBT_B_D2R_P<0>

TBT_B_R2D_C_P<0>

TBT_DDC_XBAR_EN_L

JTAG_TBT_TDO

PCIE_TBT_R2D_C_N<1>

TBT_B_CIO_SEL

DP_TBTSNK1_ML_P<3>

TP_TBT_PCIE_RESET3_L

TBT_B_CONFIG2_RC

TP_DP_TBTSRC_ML_CP<0>
TP_DP_TBTSRC_ML_CN<0>

TP_DP_TBTSRC_AUXCH_CN

TBT_PWR_EN

=I2C_TBTRTR_SCL

TBT_PWR_REQ_L

TBT_GPIO_9

DP_TBTSNK1_ML_P<1>

DP_TBTSNK0_ML_P<1>

TBT_A_DP_PWRDN

=I2C_TBTRTR_SDA

=TBT_WAKE_L

DP_TBTSNK0_HPD

TBT_GPIO_14

DP_TBTPB_AUXCH_C_N

DP_TBTPB_ML_C_P<3>

DP_TBTPB_ML_C_P<1>
DP_TBTPB_ML_C_N<1>

DP_TBTPB_ML_C_N<3>

DP_TBTPB_AUXCH_C_P

DP_TBTPB_HPD

TBT_SPI_MISO

TBT_SPI_CLK

PCIE_TBT_R2D_C_N<3>

PCIE_TBT_R2D_C_P<3>

TBT_TMU_CLK_IN

DP_TBTSRC_HPD

TP_DP_TBTSRC_AUXCH_CP

TBT_B_R2D_C_N<0>

DP_TBTSNK0_ML_P<3>

SYSCLK_CLK25M_TBT_R

JTAG_TBT_TDI
JTAG_TBT_TMS

TP_TBT_XTAL25OUT

TBT_TEST_EN

=PP3V3_TBTLC_RTR

TBT_SPI_CS_L

TBT_B_R2D_C_N<1>

TBT_B_R2D_C_P<1>

TBT_A_D2R_N<1>

TBT_A_D2R_P<1>

TBT_A_R2D_C_N<1>

TBT_A_R2D_C_P<1>

TBT_A_D2R_N<0>

TBT_A_D2R_P<0>

TBT_A_R2D_C_P<0>

PCIE_TBT_D2R_N<3>

PCIE_TBT_D2R_P<3>

PCIE_TBT_D2R_N<2>

PCIE_TBT_D2R_P<2>

PCIE_TBT_D2R_N<1>

PCIE_TBT_D2R_P<1>

PCIE_TBT_D2R_N<0>

PCIE_TBT_D2R_P<0>

PCIE_TBT_R2D_C_P<0>

PCIE_TBT_R2D_C_P<1>

PCIE_TBT_R2D_C_P<2>

PCIE_TBT_R2D_C_N<2>

PCIE_TBT_R2D_C_N<0>

TBT_MONOBSP

=PP3V3_S4_TBT

TBT_B_HV_EN

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_P<3>

DP_TBTSNK0_AUXCH_P

TBT_B_CONFIG1_BUF

TBT_B_DP_PWRDN

TBT_B_LSTX
TBT_B_LSRX

TBT_A_CIO_SEL

TBT_A_HV_EN

DP_TBTPA_HPD

DP_TBTPA_AUXCH_C_N

DP_TBTPA_AUXCH_C_P

DP_TBTPA_ML_C_N<3>

DP_TBTPA_ML_C_P<3>

DP_TBTPA_ML_C_P<1>

TBT_A_LSRX

TBT_A_LSTX

TBT_A_CONFIG2_RC

TBT_A_CONFIG1_BUF

DP_TBTPA_ML_C_N<1>

TP_TBT_PCIE_RESET0_L

TP_TBT_PCIE_RESET2_L

DP_TBTSNK1_ML_P<1>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_ML_N<3>

DP_TBTSNK1_ML_P<2>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_ML_N<2>

=TBT_CLKREQ_L

DP_TBTSNK1_ML_P<0>

DP_TBTSNK1_ML_N<3>

DP_TBTSNK0_ML_N<2>

DP_TBTSNK0_ML_C_N<2>

DP_TBTSNK0_ML_N<0>

DP_TBTSNK1_ML_C_N<1>

DP_TBTSNK1_ML_C_P<2>

DP_TBTSNK1_ML_P<3>

DP_TBTSNK0_ML_P<0>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK1_AUXCH_N

DP_TBTSNK1_ML_C_P<1>

DP_TBTSNK1_ML_C_N<2>

DP_TBTSNK1_ML_C_N<3>

DP_TBTSNK1_AUXCH_C_P

DP_TBTSNK1_ML_C_P<3>

DP_TBTSNK1_ML_C_N<0>

DP_TBTSNK0_AUXCH_C_N

DP_TBTSNK0_AUXCH_C_P

DP_TBTSNK0_ML_C_N<3>

DP_TBTSNK0_ML_C_N<1>

DP_TBTSNK0_ML_C_N<0>

DP_TBTSNK0_ML_C_P<1>

DP_TBTSNK0_ML_C_P<2>

DP_TBTSNK1_ML_C_P<0>

DP_TBTSNK0_ML_N<1>

DP_TBTSNK0_AUXCH_N

DP_TBTSNK0_ML_P<0>

DP_TBTSNK1_ML_N<1>

DP_TBTSNK0_ML_N<0>
DP_TBTSNK0_AUXCH_P

DP_TBTSNK1_ML_N<2>

DP_TBTSNK1_ML_P<2>

JTAG_TBT_TCK

TP_TBT_MONDC1

TP_TBT_MONDC0

TBT_PCIE_RESET_L

DP_TBTSNK1_ML_N<0>
DP_TBTSNK1_AUXCH_P

DP_TBTSNK1_AUXCH_N

DP_TBTSNK0_ML_C_P<3>

DP_TBTSNK1_AUXCH_C_N

DP_TBTSNK1_HPD

DP_TBTSNK1_ML_N<0>

DP_TBTSNK1_ML_P<0>

DP_TBTSNK0_ML_N<3>

TP_TBT_THERM_DP

TBT_TEST_PWR_GOOD

TBTROM_HOLD_L

TBTROM_WP_L

PCIE_CLK100M_TBT_P

SYSCLK_CLK25M_TBT

=PP3V3_TBTLC_RTR

TBT_SPI_MOSI

DP_TBTSNK0_ML_P<2>

DP_TBTSNK0_ML_N<3>

TBT_DDC_XBAR_EN_L

=PP3V3_TBTLC_RTR

TBT_B_D2R_N<0>

TBT_B_D2R_P<1>
TBT_B_D2R_N<1>

DP_TBTSNK0_ML_C_P<0>

TBT_PWR_ON_POC_RST_L

TBT_A_R2D_C_N<0>

TP_DP_TBTSRC_ML_CP<3>

TBT_TMU_CLK_OUT

PCIE_TBT_D2R_C_N<3>

NO_TEST=TRUE

PCIE_TBT_D2R_C_N<0>

NO_TEST=TRUE

PCIE_TBT_D2R_C_P<0>

NO_TEST=TRUE

PCIE_TBT_R2D_N<2>

NO_TEST=TRUE

PCIE_TBT_R2D_P<2>

NO_TEST=TRUE

PCIE_TBT_D2R_C_N<2>

NO_TEST=TRUE

PCIE_TBT_D2R_C_P<2>

NO_TEST=TRUE

PCIE_TBT_D2R_C_P<3>

NO_TEST=TRUE

PCIE_TBT_D2R_C_P<1>

NO_TEST=TRUE

PCIE_TBT_D2R_C_N<1>

NO_TEST=TRUE

PCIE_TBT_R2D_P<0>

NO_TEST=TRUE

PCIE_TBT_R2D_N<3>

NO_TEST=TRUE

PCIE_TBT_R2D_P<3>

NO_TEST=TRUE

PCIE_TBT_R2D_N<1>

NO_TEST=TRUE

PCIE_TBT_R2D_P<1>

NO_TEST=TRUE

TBT_EN_CIO_PWR_L

MAKE_BASE=TRUE

PCIE_TBT_R2D_N<0>

NO_TEST=TRUE

R3690

1

2

C3690

1

2

R3692

1

2

R3691

1

2

R3655

1

2

C3601

1 2

C3600

1 2

C3602

1 2

C3603

1 2

C3604

1 2

C3605

1 2

C3606

1 2

C3607

1 2

C3640

1 2

C3641

1 2

C3642

1 2

C3643

1 2

C3645

1 2

C3644

1 2

C3646

1 2

C3647

1 2

R3625

1

2

R3632

1

2

R3630

1

2

R3631

1

2

R3629

1

2

R3693

1

2

C3629

1 2

C3628

1 2

C3627

1 2

C3626

1 2

C3625

1 2

C3624

1 2

C3623

1 2

C3622

1 2

C3621

1 2

C3620

1 2

C3630

1 2

C3631

1 2

C3632

1 2

C3633

1 2

C3634

1 2

C3635

1 2

C3636

1 2

C3637

1 2

C3638

1 2

C3639

1 2

U3600

D19

E20

D17

E18

D15

E16

D13

E14

B5

A6

U6

D11

E12

D9

E10

D7

E8

D5

E6

B3

A4

T5

B9

A8

B11

A10

B13

A12

B15

A14

D3

C2

V3

W4

AD3

R4
P5

K5

G2
M3 L2
H3 L4

T3
V5

M1

Y1
W2
J4
AA2
AB1
AC2
P3
M5

AD23
AC24

W16

W18

F1

F3

E22

G22

E24

G24

J22

L22

J24

L24

K1
G4

B17

A16

B19

A18

H1

J6

N2

E2

D1

N22

R22

N24

R24

U22

W22

U24

W24

P1
H5

B21

A20

B23

A22

K3

G6

L6

W6

N6
T1
Y5
U2

AA10

AB13

AA16

AB19

AB9

AA12

AB15

AA18

R6

AD7

AD11

AD15

AD19

AD5

AD9

AD13

AD17

J2

W20

AD21

AB21

U20

AA6

V1

R2
N4

AB5

Y7

AB3

Y3

AA4

AA24
AB23

R3698

1

2

R3695

1 2

R3696

1

2

R3699

1

2

U3690

6

5

7

2

1

9

8

4

3

C3610

1

2

R3610

1

2

R3615

1

2

R3685

1

2

R3686

1

2

R3687

1

2

R3688

1

2

R3680

1

2

R3683

1

2

R3682

1

2

R3697

1

2

R3681

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

36 OF 132

33 OF 80

U4

8

33 34 35

33 35

33 35

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33 69

7

33

33

20 33

7

7

7

7

7

33 79

33 79

7

7

7

7

19

33

33 79

33 79

33

76

76

7

33 79

74

7

8

33 34 35

76

8

33 34 35

33 79

33 79

33 79

7

7

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

33 79

7

7

33 79

33 79

33 79

33 79

33 79

33 79

45

8

33 34 35

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33 79

33 68

8

33 34 35

7

75

75

7

75

7

75

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75

7

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7

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www.vinafix.vn

VSSPE
VSSPE

VSSPE
VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE

VSSPE
VSSPE

VSSPE
VSSPE
VSSPE

VSSPE
VSSPE

VSS
VSS

VSS
VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS
VSS

VSS
VSS

VSS

VSS
VSS

VSS

VSS

VSS

VSS

VSS

VCC1P0_DPAUX

VCC1P0_DPAUX

VCC3P3_POC

VSSPE

VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE

VCC1P0_PE

VCC1P0_PE

VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE
VCC1P0_PE

VCC1P0
VCC1P0

VCC3P3_DP
VCC3P3_DP

VCC3P3_DP

VCC3P3_CIO

VCC3P3_CIO

VCC3P3_CIO

VCC3P3

VCC3P3

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0
VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC1P0_ON

VCC3P3

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE
VSSPE

VSSPE

VSSPE

VCC3P3_DP

VCC3P3_DPAUX

(SYM 2 OF 2)

VCCGND

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

EDP: 10 mA

??? mW (Single-Port)

250 mW (Dual-Port)
EDP: 240 mA

???? mW (Single-Port)

2700 mW (Dual-Port)

EDP: 3000 mA

???? mW (Single Port)

EDP: 1000 mA

250 mW (Dual Port)

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%
0201-1

X5R-CERM

1.0UF

6.3V

20%

0402-1

CERM-X5R

10UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

6.3V

20%

0402-1

CERM-X5R

10UF

6.3V

20%

0402-1

CERM-X5R

10UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%
0201-1

X5R-CERM

1.0UF

10V

20%
0201-1

X5R-CERM

1.0UF

FCBGA

CACTUSRIDGE4C

CRITICAL

OMIT_TABLE

6.3V

20%

0402-1

CERM-X5R

10UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

10V

20%

0201-1

X5R-CERM

1.0UF

Thunderbolt Host (2 of 2)

SYNC_DATE=11/14/2011

SYNC_MASTER=J5_MLB_KEPLER

=PP1V05_TBTLC_RTR

=PP3V3_TBTLC_RTR

=PP1V05_TBTCIO_RTR

=PP3V3_S4_TBT

C3714

1

2

C3715

1

2

C3716

1

2

C3710

1

2

C3711

1

2

C3712

1

2

C3717

1

2

C3713

1

2

C3700

1

2

C3701

1

2

U3600

K11
K15

R10
R14
T11
U10
V11
W10

L10
L14
M11
M15
N10
N14
P11
P15

G8
H9

J10
J12
J14
J16

J8
K17
T15
U14

V7

W8

G10
G12

V15
V19
W12
W14

G14
G16
G18
H19
K19
M19
P19
T19

M7
P7
T7

L18
N18
R18

H11
H13
H15
H17

H7

K7

AD1
K13

N16

N8
P13
P17

P9
R12
R16

R8
T13
T17

K9

T9
U12
U16

U8

V9

L12
L16

L8
M13
M17

M9
N12

A2
A24

AC12
AC14
AC16
AC18
AC20
AC22

AC4
AC6
AC8

B1

AA14

B7
C10
C12
C14
C16
C18
C20

C22
C24
C4

AA20

C6
C8
D21
D23
E4
F11
F13
F15
F17
F19

AA22

F21
F23
F5
F7
F9
G20
H21
H23
J18
J20

AA8

K21
K23
L20
M21
M23
N20
P21
P23
R20
T21

AB11

T23
U18
V13
V17
V21
V23
Y11
Y13
Y15
Y17

AB17

Y19
Y21
Y23
Y9

AB7

AC10

C3760

1

2

C3772

1

2

C3771

1

2

C3770

1

2

C3790

1

2

C3744

1

2

C3743

1

2

C3742

1

2

C3741

1

2

C3740

1

2

C3745

1

2

C3705

1

2

C3773

1

2

C3774

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

37 OF 132

34 OF 80

8

8

33 35

8

8

33 35

www.vinafix.vn

GND

VOUT

ON

VIN

OUT

OUT

IN

IN

RESET*

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

+

-

PAD

(OD)

0.7V

DLY

IN

IN

D

S G

D

S G

VIN

FBX

EN/UVLO

INTVCC

VC

RT

SS

SYNC

SW

SGND

GND

NC

SNS1

SNS2

NC

IN

SGD

D

SG

D

SG

VOUT

GND

ON

VIN

SENSE

THRM

RESET*

CT

GND

MR*

VDD

PAD

OUT

D

S G

D

SG

IN

IN

D

GS

IN

OUT

IN

OUT

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Vout = 15.47V

- =PP3V3_TBTLC_FET (3.3V FET Output)

- =PP1V05_TBT_P1V05TBTFET (1.05V FET Input)

- =PP1V05_TBTLC_FET (1.05V FET Output)

BOM options provided by this page:

Signal aliases required by this page:

- =PP3V3_S0_TBTPWRCTL

- =PP3V3_TBT_P3V3TBTFET (3.3V FET Input)

- =TBT_RESET_L

DLY = 60 ms +/- 20%

Platform (PCIe) Reset

Pull-ups provided by SB page.

TBTBST:Y - Stuffs 15V boost circuitry.

R(on)

@ 2.5V

Part

Type

Max Current = 2A (85C)

24 mOhm Max

TPS22924C

Load Switch

U3810

18.3 mOhm Typ

Max Current = 4A (85C)

1.05V TBT "CIO" Switch

Max Current = 2A?

Intel investigating whether RC is sufficient.

Pull-up: R3610

TPS22920

11.5 mOhm Max

Load Switch

Part

Type

<R2>

Max Vgs: 10V

add property on another page.

<Ra>

<R1>

- =TBT_CLKREQ_L

R(on)
@ 1.05V

Delay = 27.3ms

TPS3808G25
Vt = 2.33V +/- 2%

U3820

8 mOhm Typ

8-13V Input
Changes required

Freq = 500KHz

Power aliases required by this page:

UVLO(falling) = 1.22 * (R1 + R2) / R2

SI8409DB:

TBT "POC" Power-up Reset

3.3V TBT "LC" Switch

Thunderbolt 15V Boost Regulator

- =PPVIN_SW_TBTBST (8-13V Boost Input)

- =PP15V_TBT_REG (15V Boost Output)

no XW necessary.

SGND shorted to

UVLO = 4.55V (falling), 4.95 (rising)

UVLO(rising) = UVLO(falling) + (2uA * R1)

for 2S.

GND inside package,

<Rb>

Vout = 1.6V * (1 + Ra / Rb)

Page Notes

Id(max): 3.7A @ 70C

Rds(on): 46mOhm @ 4.5V Vgs

Vgs(max): +/-12V

Supervisor & CLKREQ# Isolation

Voltage not specified here,

Vgs(th): -1.4V

Vds(max): -30V

CSP

TPS22924

CRITICAL

33

17

0.1UF

16V

X5R-CERM

0201

10%

25

33

X5R

20%

6.3V

1UF

0201

TDFN

CRITICAL

SLG4AP016V

100K

MF

1/20W
201

5%

33 35

33 35

TBTBST:Y

1/16W

1%

402

MF-LF

73.2K

5%

330K

1/16W

402

MF-LF

TBTBST:Y

5%

TBTBST:Y

470K

402

MF-LF

1/16W

TBTBST:Y

10V

20%

402

X5R-CERM

2.2UF

10V

20%

402

X5R-CERM

TBTBST:Y

2.2UF

5%
CERM

50V

TBTBST:Y
68PF

402-1

10V

20%

402

X5R-CERM

2.2UF

TBTBST:Y

10%

402

X5R

25V

0.1UF

TBTBST:Y

SOT563

SSM6N37FEAPE

TBTBST:Y

402

1/16W

5%
MF-LF

330K

TBTBST:Y

SOT563

SSM6N37FEAPE

TBTBST:Y

1/16W

5%

402

MF-LF

330K

TBTBST:Y

TBTBST:Y

MF-LF

1%

1/16W

26.7K

402

1/16W

1%

402

MF-LF

TBTBST:Y

49.9K

1%

402

MF-LF

TBTBST:Y

200K

1/16W

QFN

LT3957

CRITICAL
TBTBST:Y

25V

20%
X5R-CERM

TBTBST:Y

10UF

0603

25V

20%
X5R-CERM

10UF

TBTBST:Y

0603

IHLP

3.3UH-6.5A

CRITICAL
TBTBST:Y

39 40 66

50V

5%

NO STUFF

402

CERM

100PF

50V

5%

402

TBTBST:Y

10PF

CERM

1/16W

1%

402

MF-LF

TBTBST:Y

15.8K

1/16W

1%

402

MF-LF

137K

TBTBST:Y

SM

PLACE_NEAR=C3895.1:2 mm

1/20W

5%
MF

0

TBTBST:Y

201

PWRDI5

PDS540XF

TBTBST:Y

CRITICAL

TBTBST:Y

25V

20%

33UF-0.06OHM

CASE-D3L

POLY-TANT

OMIT_TABLE

4.7UF

0603

35V

10%
X5R-CERM

OMIT_TABLE

4.7UF

10%
X5R-CERM

35V
0603

TBTBST:Y

0.001UF

X7R
402

10%
50V

402

CERM-X5R

6.3V

10%

0.33UF

TBTBST:Y

SI8409DB

BGA

TBTBST:Y

CRITICAL

SOT563

SSM6N37FEAPE

TBTBST:Y

SSM6N37FEAPE

SOT563

TBTBST:Y

25V

10%
402

CERM

0.0047UF

25V

10%
402

X5R

0.1UF

CSP

TPS22920

CRITICAL

QFN

TPS3808

CRITICAL

33

6.3V
X5R

1UF

20%

0201

50V

10%
402

CERM

0.0033UF

SOT563

SSM6N37FEAPE

SOT563

SSM6N37FEAPE

1/20W

5%
MF

100K

201

1/20W

5%
MF

100K

201

20

33

SOD-VESM-HF

SSM3K15FV

33

1/20W
MF

5%

10K

201

OMIT_TABLE

4.7UF

0603

35V
X5R-CERM

10%

OMIT_TABLE

4.7UF

0603

35V
X5R-CERM

10%

20%

6.3V

1UF

0201

X5R

NO STUFF

5%

1/20W

0

MF

201

201

5%
MF

1/20W

0

5%
MF

1/20W

10K

201

NO STUFF

MF

5%

1/20W

0

201

64

64

10%

330PF

X7R-CERM

16V
0201

0201

10%

X5R-CERM

1.0UF

6.3V

NO STUFF

MF

1/20W

201

0

5%

DFN1006

1N4448HLP-7

NO STUFF

69

DFN1006

1N4448HLP-7

NO STUFF

201

1/20W

MF

0

5%

6.3V

1.0UF

X5R-CERM

10%

0201

NO STUFF

70

CRITICAL TBTBST:Y

C3895,C3897,C3898,C389A

CAP,CER,4.7UF,10%,25V,X6S,0603

4

138S0811

Thunderbolt Power Support

SYNC_MASTER=J5_MLB_KEPLER

SYNC_DATE=11/14/2011

TBTBST_PWREN_L

VOLTAGE=0V

MIN_LINE_WIDTH=0.5 mm

GND_TBTBST_SGND

MIN_NECK_WIDTH=0.25 mm

TBT_B_HV_EN_RC

TBT_A_HV_EN_RC

TBT_EN_LC_ISOL_R

=PP3V3_S0_P3V3TBTFET

TBTBST_EN_UVLO

TBTBST_SNS2

TBT_B_HV_EN

TBT_A_HV_EN

TBT_A_HV_EN
TBT_B_HV_EN

MIN_NECK_WIDTH=0.25 mm

PPVIN_SW_TBTBST

MIN_LINE_WIDTH=0.5 mm

=PPVIN_SW_TBTBST

TBTBST_VC_RC

TBTBST_INTVCC

TBT_SW_RESET_L

TBTBST_SS

TBTBST_RT

=PP3V3_S0_TBTPWRCTL

TBT_EN_LC_RC

=TBT_RESET_L

TBTPOCRST_MR_L

TBT_PWR_ON_POC_RST_L

TBT_CLKREQ_L

=PP3V3_S0_PCH_GPIO

TBT_EN_LC_PWR

=PP3V3_S4_TBT

=PP1V05_TBTCIO_FET

=TBT_CLKREQ_L

TBTBST_VSNS

TBTBST_SHDN_DIV

TBTBST_SNS1

TBTPOCRST_CT

=PP3V3_TBTLC_RTR

=PP1V05_S0_P1V05TBTREG

SMC_DELAYED_PWRGD

TBTBST_FBX

TBT_EN_CIO_PWR

=PP1V05_TBTLC

TBT_EN_CIO_PWR_L

=PP3V3_TBTLC_FET

=PP3V3_TBTLC_RTR

TBT_PCIE_RESET_L

P1V05TBTS0_PGOOD

TBT_EN_LC_ISOL

TBTBST_VC

MAKE_BASE=TRUE

TBT_CLKREQ_ISOL_L

TBTBST_BOOST

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

SWITCH_NODE=TRUE
DIDT=TRUE

=PP15V_TBT_REG

TBTBST_PWREN_DIV_L

U3810

C1

C2

A2
B2

A1
B1

C3800

1

2

C3810

1

2

U3800

6

5

7

3

8

4

2

9

1

R3807

1

2

R3892

1

2

R3881

1

2

R3880

1

2

C3890

1

2

C3891

1

2

C3887

1

2

C3892

1

2

C3880

1

2

Q3888

6

2

1

R3887

1

2

Q3888

3

5

4

R3888

1

2

R3894

1

2

R3893

1

2

R3891

1

2

U3890

25

31

1213141516

17

28

1
2
10
35
36

33

6

3

42324

37

32

8

9

202138

34

30

27

C3860

1

2

C3861

1

2

L3895

1 2

C3889

1

2

C3888

1

2

R3896

1

2

R3895

1

2

XW3895

12

R3889

1

2

D3895

1 2

3

C3896

1

2

C3895

1

2

C3897

1

2

C3899

1

2

C3894

1

2

Q3880

2 3

1

4

Q3805

3

5

4

Q3805

6

2

1

C3831

1

2

C3830

1

2

U3820

D1

D2

A2
B2
C2

A1
B1
C1

U3830

3

5

4

62

7

1

C3820

1

2

C3893

1

2

Q3825

3

5

4

Q3825

6

2

1

R3830

1

2

R3820

1

2

Q3840

3

1

2

R3840

1

2

C3898

1

2

C389A

1

2

C3811

1

2

R3811

12

R3812

12

R3810

1

2

R3816

1

2

C3825

1

2

C3850

1

2

R3850

12

D3850

AK

D3860

AK

R3860

12

C3865

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

38 OF 132

35 OF 80

8

33 35

33 35

8

8

8

8

17 18 19 20 25

8

33 34

8

8

33 34 35

8

80

8

8

8

33 34 35

8

www.vinafix.vn

IN

IN

IN

OUT

OUT

IN

OUT

OUT

SYM_VER-1

IN
IN

OUT

OUT

IN

OUT

OUT

IN

OUT

IN

NC

A

B

NC

IN

VCC

GND

SEL OE*

D+
D-

Y+
Y-

M+
M-

BI

BI

D

G S

OUT

IN

IN

OUT

OUT
OUT

IN

OUT

IN

OUT

IN
IN

IN
IN

IN

IN

IN

IN

OUT

IN
IN

OUT

IN
BI

OUT

BI
BI

IN
IN

OUT

BI
BI

OUT

IN

IN

BI

BI

IN
IN

IN

IN
IN

IN

OUT

OUT

IN
IN

GND

VOUT

ON

VIN

IN

OUT

EN

MR*

GND

THRM

IN

VDD

SENSE

RESET*

+

-

PAD

(OD)

DLY

VREF

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

HPD sink Low: 0.0V-0.8V

HPD sink High: 2.0V-5.3V

516S1058

Supervisor & CLKFREG # Isolation

Delay = 130 ms +/- 20%

DEBUG CURRENT SENSE RD135 connects to PP3V3_WLAN_F

R(on)

@ 2.5V

Part

Type

Max Current = 2A (85C)

TPS22924C

18.3 mOhm Typ

Load Switch

24 mOhm Max

U4450

AIRPORT

3V S3 WLAN FET

RIO POWER CONNECTOR

518s0862

SEL OUTPUT

L USB_BT_WAKE
H USB_BT

Note: This receptacle mates with the plug with APN 998-4708.

APN:311S0302

*NOTE: This connector is shielded 70P Hirose Receptacle.

RIO FLEX CONNECTOR

7

17 75

7

17 75

7

17 75

7

17 75

7

17 75

7

17 75

PLACE_NEAR=J4400.28:2.54MM

0.1UF

16V10%

X7R-CERM0402

PLACE_NEAR=J4400.29:2.54MM

0.1UF

10% 16V

X7R-CERM0402

NOSTUFF

0.1UF

16V

10%

0201

X5R-CERM

NOSTUFF

16V
0201

X5R-CERM

10%

0.1UF

OMIT_TABLE

0.6NH+/-0.1NH-0.85A

0201

0.6NH+/-0.1NH-0.85A

0201

OMIT_TABLE

NOSTUFF

16V
X5R-CERM

0.1UF

10%

0201

NOSTUFF

X5R-CERM
0201

0.1UF

16V

10%

7

36 75

7

36 75

0201

16V

NOSTUFF

X5R-CERM

10%

0.1UF

NOSTUFF

0201

16V

0.1UF

10%
X5R-CERM

0201

OMIT_TABLE

0.6NH+/-0.1NH-0.85A

PLACE_NEAR=J4410.42:2.54MM

CRITICAL

DLP11S

90-OHM-100MA

0201

OMIT_TABLE

0.6NH+/-0.1NH-0.85A

16V

10%

0201

X5R-CERM

0.1UF
NOSTUFF

16V
0201

NOSTUFF

X5R-CERM

7

36 75

7

36 75

7

36 78

7

36 78

19 24 66

17

20%

0.1uF

CERM
402

10V

232K

1/16W
MF-LF
402

1%

1%

100K

MF-LF
402

1/16W

100K

MF-LF
402

1%
1/16W

7

36

7

36

9

PLACE_NEAR=U4430.5:4mm

0.1UF

X5R-CERM
0201

10%
16V

201

MF

1/20W

100K

5%

25

74LVC1G00GF

SOT891

7

18 27 36 38 39 66

BTPWR:S4

1/20W

5%

201

MF

0

16V

10%

402

CERM

0.01UF

NOSTUFF

1/20W

1%

201

MF

15K

NOSTUFF NOSTUFF

1/20W

1%

201

MF

15K

NOSTUFF

1%

201

MF

15K

1/20W 1/20W

5%

201

MF

0

BTPWR:S3

SIGNAL_MODEL=MOJO_MUX

TQFN

PI3USB102ZLE

CRITICAL

6.3V

10%
201

X5R

0.1UF

7 9

36

74

7 9

36

74

201

1/20W

1%
MF

15K

BTPWR:S4

201

MF

15K

NOSTUFF

1%
1/20W

1/20W

1%

201

MF

15K

NOSTUFF

SOD-VESM-HF

SSM3K15FV

BTPWR:S4

40

PLACE_NEAR=J3501.27:2.54MM

0402-LF

FERR-120-OHM-1.5A

BTPWR:S3

0402

16V
X7R-CERM

0.01UF

10%

PLACE_NEAR=J3501.27:2.54MM

BTPWR:S4

0402-LF

FERR-120-OHM-1.5A

19 74

19 74

0201

X5R-CERM

10% 16V

GND_VOID=TRUE

0.1UF

GND_VOID=TRUE

7

19 74

7

17 75

7

17 75

GND_VOID=TRUE

GND_VOID=TRUE

10%

0.1UF

X5R-CERM

16V

0201

7

36 75

7

36 75

7

36 75

7

36 75

7 9

78

7 9

78

7 9

78

7 9

78

7 9

78

7 9

78

7 9

78

7 9

78

7

19 74

7

17 75

7

17 75

7

36 40

GND_VOID=TRUE
GND_VOID=TRUE

DF40CG3.0-70DS-0.4V

F-ST-SM

CRITICAL

GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE
GND_VOID=TRUE

GND_VOID=TRUE

7 9

7 9

7

24

7

26 74

7

26 74

7

18

7

36

7

36

7 9

36 74

7 9

36 74

PLACE_NEAR=J4410.33:2.54MM

X5R-CERM

0.1UF

10%
16V

0201

7

39 40

42

42

42

42

7

18 27 39 66

7

18 27 36 38 39 66

25

7

17 75

7

17 75

7 9

7

17

25

7

36 78

7

36 78

PLACE_NEAR=J4440.2:2.54MM

16V
X5R-CERM
0201

0.1UF

10%

PLACE_NEAR=J4440.4:2.54MM

0201

10%

0.1UF

X5R-CERM

16V

PLACE_NEAR=J4440.1:2.54MM

0201

16V

10%
X5R-CERM

0.1UF

504050-0691

CRITICAL

M-RT-SM

PLACE_NEAR=J4440.4:2.54MM

0.1UF

X5R-CERM

10%
16V

0201

5%

0

GND_VOID=TRUE

1/20W

201

MF

5%

0

1/20W

201

MF

GND_VOID=TRUE

NOSTUFF

15PF

NPO
201

5%

25V

GND_VOID=TRUE

NOSTUFF

GND_VOID=TRUE

15PF

NPO
201

5%

25V

TPS22924

CRITICAL

CSP

66

CRITICAL

TDFN

SLG4AP041V

7

36 40

117S0002

4

RES, 0OHM, 0201

L4470,L4471,L4473,L4474

SYNC_MASTER=MASTER

RIO CONNECTORS

SYNC_DATE=MASTER

PCIE_AP_R2D_PI_P

HDMI_HPD_L

=PP3V3_S4_SMC

PCIE_AP_R2D_PI_N

=ENET_RESET_L

AP_RESET_CONN_L

HDMI_IG_DATA_C_P<1>

USB_EXTB_P

PM_SLP_S4_L

HDMI_IG_DDC_CLK

=I2C_HDMIRDRV_SCL

USB_EXTB_OC_L

PP3V3_WLAN_F

P3V3WLAN_VMON

AP_CLKREQ_L

AP_PWR_EN

AP_RESET_L

AP_CLKREQ_Q_L

=PP3V3_S3_WLAN

AP_RESET_CONN_L

=PP3V3_S3_WLAN

PM_WLAN_EN

PP3V3_WLAN_F

=PP1V5_S0_RDRVR

USB3_EXTB_RX_N

=PP3V3_S3_RIO

PCIE_AP_R2D_P

PCIE_AP_D2R_PI_N

PCIE_AP_D2R_PI_P

PCIE_WAKE_L

PCIE_AP_R2D_C_N

PP3V3_S3RS4_BT_F

=BT_WAKE_L

USB3_EXTB_RX_RC_P

PCIE_AP_R2D_C_P

PCIE_AP_D2R_N

PCIE_AP_D2R_P

PM_SLP_S3_L

=I2C_X29THMSNS_SCL

=PP5V_S4_RIO

=PP3V3_S3_BT

USB_BT_WAKE_P
USB_BT_WAKE_N

BTMUX_SEL

USB_BT_P
USB_BT_N

PM_SLP_S4_L

PCIE_CLK100M_AP_P

USB3_EXTB_TX_C_N

=PP3V3_S4_RIO

USB3_EXTB_TX_P

HDMI_IG_DATA_C_N<0>

HDMI_IG_DATA_C_P<0>

HDMI_HPD_L

PCIE_ENET_R2D_C_N

HDMI_IG_DATA_C_N<1>

PCIE_ENET_D2R_P
PCIE_ENET_D2R_N

PCIE_ENET_R2D_C_P

PCIE_AP_D2R_PI_N

=I2C_HDMIRDRV_SDA

PCIE_CLK100M_ENET_P

AP_CLKREQ_Q_L

ENET_CLKREQ_L

WIFI_EVENT_L

=PP3V3_S0_HDMI

HDMI_HPD

PCIE_CLK100M_AP_CONN_P

HDMI_IG_DATA_C_N<2>

HDMI_IG_CLK_C_P

HDMI_IG_CLK_C_N

PCIE_AP_D2R_PI_P

PCIE_CLK100M_ENET_N

HDMI_IG_DDC_DATA

SDCONN_STATE_CHANGE_RIO

USB3_EXTB_TX_C_P

USB3_EXTB_TX_N

USB_EXTB_N

PCIE_CLK100M_AP_N

SD_PWR_EN

PCIE_CLK100M_AP_CONN_N

=PP3V3_S4_BT

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=3.3V

PP3V3_S3RS4_BT_F

MIN_NECK_WIDTH=0.2 mm

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
VOLTAGE=3.3V

PP3V3_WLAN_R

PCIE_AP_R2D_N

=I2C_X29THMSNS_SDA

USB3_EXTB_RX_RC_N

USB3_EXTB_RX_P

PCIE_CLK100M_AP_CONN_P

PCIE_CLK100M_AP_CONN_N

USB_BT_CONN_P

USB_BT_CONN_P

USB_BT_CONN_N

USB_BT_CONN_N

0.1UF

10%

PCIE_AP_R2D_N

HDMI_IG_DATA_C_P<2>

PCIE_AP_R2D_P

C4433

1 2

C4432

1 2

C4473

1

2

C4471

1

2

L4470

1 2

L4471

1 2

C4472

1

2

C4470

1

2

C4477

1

2

C4475

1

2

L4474

1 2

L4401

4 3

21

L4473

1 2

C4474

1

2

C4476

1

2

C4440

1

2

R4454

1

2

R4455

1

2

R4453

1

2

C4430

1

2

R4430

1

2

U4430

2

1

3

6

4

R4411

1 2

C4416

1

2

R4415

1

2

R4416

1

2

R4417

1

2

R4418

1

2

U4410

6

7

3

4

5

8

10

9

2

1

C4415

1

2

R4412

1

2

R4413

1

2

R4414

1

2

Q4410

3

1

2

L4416

12

C4417

1

2

L4415

12

C4401

1 2

C4402

1 2

J4410

1

10

1112

1516
1718
19

2

20

2122
2324
2526

29

3

30

3132
3334
3536
3738
39

4

40

4142
4344

4748
49

5

50

5152
5354
5556
5758

6

6162
6364
6566
6768
69

7

70

7172

7374

8

9

C4410

1

2

C4491

1

2

C4492

1

2

C4490

1

2

J4400

7

8

1
2
3
4
5
6

C4493

1

2

R4420

1 2

R4421

1 2

C4420

1 2

C4421

1 2

U4450

C1

C2

A2
B2

A1
B1

U4440

6

5

7

3

8

4

2

9

1

<BRANCH>

<SCH_NUM>

<E4LABEL>

44 OF 132

36 OF 80

5

7

75

8

25 40

7

75

7

36 40 80

8

36 66

8

36 66

7

36 40 80

8

8

36

78

8

8

78

78

8

78

8

8

36

80

www.vinafix.vn

OUT

OUT

IN

IN

OUT

OUT

OUT

IN

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

R2D Passive DeEmphasis

D2R Passive DeEmphasis

516S1035 (recpt)

SATA GUMSTICK2 CONNECTOR

VALUE: 0.0 DB

VALUE: 0.0 DB

to U1800 pin AM1 and AM3.

It is critical that these two should be near

C4518 & C4517 Placement Note:

PLACE_NEAR=J4500.9:3mm

0603

FERR-70-OHM-4A

CRITICAL

43 78

43 78

CERM
402

20%
10V

0.1UF

PLACE_NEAR=L4500.2:2MM

PLACE_NEAR=L4500.1:2MM

CERM

10V

20%

402

0.1UF

0.001

1W

1%

0612

MF

CRITICAL

5%01/20W

201MF

GND_VOID=TRUE

NOSTUFF

201NPO

GND_VOID=TRUE

15PF

5%25V

NOSTUFF

15PF

GND_VOID=TRUE

2015% NPO25V

5%

0

GND_VOID=TRUE

201MF

1/20W

5%

0

GND_VOID=TRUE

201MF

1/20W

NOSTUFF

C0G

+/-0.1PF

GND_VOID=TRUE

5.0PF

25V

0201

GND_VOID=TRUE

C0G

0201 +/-0.1PF

25V

5.0PF

NOSTUFF

5%

0

201MF

GND_VOID=TRUE

1/20W

0.1UF

20%

PLACE_NEAR=L4510.1:2MM

10V
402

CERM

PLACE_NEAR=L4510.2:2MM

0.1UF

CERM

20%
10V

402

CRITICAL

0603

FERR-70-OHM-4A

PLACE_NEAR=J4500.39:3MM

0402X7R-CERM

16V10%

0.01UF

GND_VOID=TRUE

0402X7R-CERM

10%

0.01UF

GND_VOID=TRUE

16V

PLACE_NEAR=U1800.AM3:5MM

0402X7R-CERM

0.01UF

16V10%

GND_VOID=TRUE

PLACE_NEAR=U1800.AM1:5MM

0402X7R-CERM

GND_VOID=TRUE

0.01UF

10%16V

7

17 74

7

17 74

7

17 74

7

17 74

7

39 40

7

39 40

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

GND_VOID=TRUE

F-ST-SM

DF40CG1.5-48DS-0.4V

CRITICAL

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

SSD/HDD Connectors

SATA_SSDRHDD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_RC_P

SATA_HDD_R2D_RC_N

SATA_SSDRHDD_D2R_P

SMC_OOB1_TX_L

SATA_SSDRHDD_R2D_N

SATA_SSDRHDD_R2D_P

SATA_SSDRHDD_D2R_N

SATA_SSDRHDD_D2R_P

ISNS_SSD_P

=PP3V3_S0_SSD

=PP5V_S0_HDD

ISNS_SSD_N

SATA_SSDRHDD_R2D_P

SATA_SSDRHDD_R2D_N

SMC_OOB1_RX_L

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_D2R_RC_N

SATA_HDD_D2R_RC_P

MIN_NECK_WIDTH=0.4mm

PP3V3_S0_SSD_R

MIN_LINE_WIDTH=0.6mm
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2MM

PP5V_S0_HDD_FLT

MIN_LINE_WIDTH=0.6MM
VOLTAGE=5V

MIN_NECK_WIDTH=0.2mm
VOLTAGE=3.3V

PP3V3_S0_SSD_FLT

MIN_LINE_WIDTH=0.6mm

L4500

1 2

C4502

1

2

C4501

1

2

R4530

2 1
4 3

R4510

1 2

C4524

1 2

C4521

1 2

R4507

1 2

R4508

1 2

C4519

1 2

C4515

1 2

R4506

1 2

C4510

2

1

C4511

2

1

L4510

1 2

C4525

1 2

C4522

1 2

C4517

1 2

C4518

1 2

J4500

1

10
11 12
13 14
15 16

19

2

20
21 22
23 24
25 26
27 28
29

3

30
31 32

35 36
37 38
39

4

40
41 42
43 44
45 46
47 48

49

5

50

51 52

6

7 8
9

<BRANCH>

<SCH_NUM>

<E4LABEL>

45 OF 132

37 OF 80

7

37 74

7

74

7

74

7

37 74

7

37 74

7

37 74

7

37 74

7

37 74

8

8

7

37 74

7

37 74

7

74

7

74

7

7

www.vinafix.vn

OUT

OUT

IN

IN

SYM_VER-1

GND

VBUS

SSTX+

SSRX­GND

SSTX-

D+

D-

GND
SXRX+

NC

NC

GND

VBUS

IO

IO

BI

BI

IN
OUT

IN

OUT

VCC

GND

SELOE*

D+
D-

Y+
Y-

M+
M-

FAULT*

IN_1

IN_0

ILIM

OUT1
OUT2

EN

GND

THRM

PAD

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

CURRENT LIMIT (R4600): 2.19A MIN / 2.76A MAX

SEL=0 Choose SMC
SEL=1 Choose USB

USB/SMC Debug Mux

514-0835

Left USB Port A

USB Port Power Switch

7

19 74

7

19 74

7

19 74

19 74

CRITICAL

0603

FERR-120-OHM-3A

16V10%

0201

X5R-CERM

0.1UF

GND_VOID=TRUE

16V10%

0201

X5R-CERM

0.1UF

GND_VOID=TRUE

CRITICAL

90-OHM-50MA

TCM0605-1

CRITICAL

USB3.0-LEFT-D1

F-RT-TH

GND_VOID=TRUE

ESD0P2RF-02LS

CRITICAL

TSSLP-2-1

GND_VOID=TRUE

CRITICAL

ESD0P2RF-02LS

TSSLP-2-1

TSSLP-2-1

ESD0P2RF-02LS

GND_VOID=TRUE

CRITICAL

GND_VOID=TRUE

CRITICAL

TSSLP-2-1

ESD0P2RF-02LS

15PF

5%
25V
NPO
201

GND_VOID=TRUE

NOSTUFF

GND_VOID=TRUE

25V

5%

15PF

NPO
201

NOSTUFF

1/20W

201

MF

GND_VOID=TRUE

0

5%

1/20W

201

MF

GND_VOID=TRUE

0

5%

SLP1210N6

CRITICAL

RCLAMP0582N

1%

201

22.1K

1/20W

MF

MF

1/20W

1%

22.1K

201

220UF-35MOHM

CRITICAL

CASE-B2-SM1

20%

6.3V

POLY-TANT

CRITICAL

10UF

X5R
603

20%

6.3V

0.1UF

20%
CERM

402

10V

19 74

19 74

SMC_DEBUG_YES

0.1UF

CERM

402

20%
10V

SMC_DEBUG_YES

10K

MF-LF
402

5%
1/16W

39 40

39 40

39

MF-LF

NO_XNET_CONNECTION=TRUE

5%

1/16W

SMC_DEBUG_NO

0

402

0

NO_XNET_CONNECTION=TRUE

5%
1/16W
MF-LF

402

SMC_DEBUG_NO

0.1UF

CERM

402

20%
10V

24

CRITICAL

10UF

X5R

20%

6.3V
603

5.1K

402

MF-LF

5%

1/16W

10V

10%
X5R

0.47UF

0402

SMC_DEBUG_YES

CRITICAL

TQFN

PI3USB102ZLE

SIGNAL_MODEL=MOJO_MUX

TPS2557DRB

SON

CRITICAL

SYNC_DATE=08/24/2011

USB 3.0 CONNECTORS

SYNC_MASTER=J5_AMD

USB_EXTA_MUXED_N

USB3_EXTA_RX_F_N

USB3_EXTA_RX_F_P

USB3_EXTA_RX_N

USB3_EXTA_RX_P

USB_EXTA_MUXED_P

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP5V_S3_LTUSB_A_F

NO_TEST=TRUE

USB_ILIM

USB_ILIM_R

NO_TEST=TRUE

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

PP5V_S3_LTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm

=PP5V_S3_LTUSB

USB_PWR_EN

USB_LT1_P

USB_EXTA_P

=PP3V42_G3H_SMCUSBMUX

SMC_DEBUGPRT_TX_L

PM_SLP_S4_L

USB_EXTA_OC_L

SMC_DEBUGPRT_RX_L

USB3_EXTA_TX_C_P

USB3_EXTA_TX_C_N

USB3_EXTA_TX_N

USB3_EXTA_TX_P

USB_LT1_N

USB_EXTA_N

SMC_DEBUGPRT_EN_L

L4605

1 2

C4696

1

2

C4695

1

2

C4691

1

2

C4650

1

2

R4650

1

2

R4651

1 2

R4652

1 2

C4605

1

2

C4690

1

2

R4690

1

2

C4692

1

2

U4650

6

7

3

4

5

8

10

9

2

1

U4600

4

8

1

5

2
3

6
7

9

C4611

1 2

C4610

1 2

L4600

1

2 3

4

J4600

5
6

4

7

10

11

20
21
22
23

12
13
14
15
16
17
18
19

9

3

2

8

1

D4620

1

2

D4621

1

2

D4611

1

2

D4610

1

2

C4621

1 2

C4620

1 2

R4621

1 2

R4620

1 2

D4600

1

452 3

6

R4601

1

2

R4600

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

46 OF 132

38 OF 80

74

7

79

7

79

74

7

8

7

74

8

7

18 27 36 39 66

7

79

7

79

7

74

www.vinafix.vn

LPC0AD3
LPC0CLK
LPC0FRAME*

LPC0AD1
LPC0AD2

AIN08

AIN07
LPC0CLKRUN*
LPC0PD*

AIN13

AIN14

PM7/FAN0TACH0

PM6/FAN0PWM0

AIN04

C1-

I2C2SDA

AIN05

AIN09

AIN11

AIN21

AIN23

PK7/FAN0TACH1

AIN15

AIN06

AIN10

AIN20

AIN22

T1CCP1/PJ1

PK5

LPC0AD0

AIN12

PECI0RX
PECI0TX

PK6/FAN0PWM1

LPC0RESET*

PQ0/IRQ124

PP6/IRQ122

PN3/FAN0TACH2

I2C0SDA

AIN01

AIN00

PQ1/IRQ125

I2C0SCL

U1TX/PB1

USB0DP

USB0DM

AIN03

AIN02

T0CCP1/PB7

T0CCP0/PB6

PQ2/IRQ126

U1RX/B0

LPC0SCI*

AIN17

AIN16

PN2/FAN0PWM2

WT4CCP1/PH7

AIN18

AIN19

WT4CCP0/PH6

WT3CCP1/PH5

WT5CCP1/PM3

LPC0SERIRQ

PH3/FAN0TACH5

WT3CCP0/PH4

PH2/FAN0PWM5

PP3/IRQ119
PP4/IRQ120

C0-

WT2CCP0/PH0
WT2CCP1/PH1

PQ5/IRQ129

PP7/IRQ123

WT0CCP0/PG4

I2C3SDA

SSI1FSS/PF3

PC5/C1+

U0RX

SSI0RX/PA4

PP5/IRQ121

PQ7/IRQ131

WT0CCP1/PG5

I2C3SCL

SSI1CLK/PF2

PN4/FAN0PWM3

PP1/IRQ117

U0TX

SSI0CLK/PA2
SSI0FSS/PA3

I2C1SCL

PP2/IRQ118

PQ6/IRQ130

I2C4SDA

SSI1RX/PF0

PN7/FAN0TACH4

PP0/IRQ116

SSI0TX/PA5

I2C1SDA

I2C5SDA

PQ3/IRQ127
PQ4/IRQ128

I2C4SCL

I2C2SCL

SSI1TX/PF1

PN6/FAN0PWM4

PN5/FAN0TACH3

I2C5SCL

T3CCP0/PJ4/C2+

T3CCP1/PJ5/C2-

PF4
PF5

T1CCP0/PJ0

T2CCP0/PJ2
T2CCP1/PJ3

C0+

(1 OF 2)

VDDC

VREFA-

SWO/TDO

TDI

RST*

HIB*

WAKE*

XOSC0

VREFA+

VDDA

GNDA

PK4/RTCCLK

GND

NC

OSC0

XOSC1

SWCLK/TCK
SWDIO/TMS

OSC1

VBAT

VDD

(2 OF 2)

IN

IN

BI
BI
BI
BI

IN
IN

IN
BI
OUT

IN
OUT

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

IN
IN
IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

OUT
OUT
OUT
OUT

OUT

IN

OUT

OUT
OUT
OUT

IN

OUT

IN

IN

OUT

OUT
OUT

NC

OUT

NC

BI
OUT

IN
OUT

BI
BI

OUT

IN

OUT

IN

OUT

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN

IN
OUT

OUT

BI

IN

IN

OUT

IN

NC

OUT

IN

IN

OUT

OUT

BI

IN

IN

IN

IN

BI

OUT

OUT

IN

BI

BI

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

(OD)

those designated as inputs require pull-ups.

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR STACK BOARD

(OD)

NC FOR ENG PACKAGE

(OD)

(OD)

(OD)

(OD)

(OD)

NC FOR STACK BOARD

NC FOR ENG PACKAGE

NC FOR ENG PACKAGE

(OD)
(OD)

(OD)

(OD)

NC FOR STACK BOARD

NC FOR STACK BOARD

(OD)

NC FOR STACK BOARD

NC FOR STACK BOARD

NC FOR ENG PACKAGE

(OD)

NC FOR ENG PACKAGE

1.2V FOR ENG PACKAGE

NC FOR STACK BOARD

NC FOR STACK BOARD

(OD)

(OD)

NC FOR STACK BOARD

pins designed as outputs can be left floating,

NC FOR ENG PACKAGE

NOTE: Unused pins have "SMC_Pxx" names. Unused

OMIT_TABLE

LM4FSXAH5BB

BGA

OMIT_TABLE

LM4FSXAH5BB

BGA

PLACE_NEAR=U4900.A1:4MM

SM

7

40 41 57

0.1UF

CERM
402

20%
10V

CERM

0.1UF

402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

40

1M

MF
201

5%
1/20W

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

0.1UF

CERM
402

20%
10V

402

0.1UF

CERM

20%
10V

0.1UF

CERM
402

20%
10V

0603-1

X5R-CERM

10V

20%

1UF

0.1UF

CERM
402

20%
10V

7

17 41 75

7

17 41 75

7

17 41 75

7

17 41 75

7

25 75

7

17 41 75

25

7

17 41

7

18 41

7

18 25 41

20

42 77

42 77

7

42 77

7

42 77

7

42 77

7

42 77

42 77

42 77

40

40

7

42

7

42

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40

40 66

18

35 40 66

40

38 40

38 40

40

40

40

40

40

38

40

24 66

40

18 24

7

18 25

0.1UF

CERM
402

20%
10V

20

40

40

7

40 41

7

40 41

9

74

9

74

46

46

48

46

46

40

40

40 47

40 49

40 56

40

7

18 27 36 66

7

18 27 36 38 66

18 66

7

40 47

40

40 66

40 66

7

36 40

40

40

40

66

25 40

30-OHM-1.7A

0402

11 40 61 72

7

37 40

40

7

37 40

10%

1UF

25V
402

X5RX5R

402

25V

1UF

10%

25V

10%

1UF

402

X5R

56

18 24 66

40

11 72

40

40

40

18 40 66

40

40

40

0201

10%
X5R-CERM

10V

0.01UF

10%

6.3V
X5R

1UF

402

SYNC_DATE=02/20/2012

SYNC_MASTER=D1_SENSORS

SMC

GND_SMC_AVSS

=PP3V3_S5_SMC

SMC_ADC8

SMC_ADC4

SMC_ADC3

SMC_ADC2

SMC_ADC1

SMC_ADC7

LPC_AD<0>

CPU_CATERR_L

SMC_PM_G2_EN

SMC_ODD_DETECT

LPC_AD<2>

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_1_S0_SCL

SMBUS_SMC_2_S3_SCL

SMBUS_SMC_3_SCL

SMC_FAN_1_CTL

SMC_T25_EN_L
SYS_TDM_ONEWIRE
SYS_ONEWIRE

LPC_AD<3>

HISIDE_ISENSE_OC

SMC_ADC0

SMC_ADC13

SMBUS_SMC_4_ASF_SCL

SMBUS_SMC_5_G3_SCL

SMC_ONOFF_L

SMC_PME_S4_WAKE_L

SMBUS_SMC_1_S0_SDA

PP3V3_S5_AVREF_SMC

SMC_TCK

SMC_GFX_THROTTLE_L

SMC_ADC23

CPU_PROCHOT_L

SMC_VCCIO_CPU_DIV2

SMC_S5_PWRGD_VIN

SMC_DELAYED_PWRGD

SMC_DEBUGPRT_RX_L

CPU_THRMTRIP_3V3

SPI_SMC_MISO
SPI_SMC_MOSI

SPI_DESCRIPTOR_OVERRIDE_L

SMC_SYS_LED

SPI_SMC_CLK
SPI_SMC_CS_L

S5_PWRGD

PM_PCH_SYS_PWROK

SMC_DEBUGPRT_EN_L

PM_SYSRST_L
MEM_EVENT_L

SMC_ADAPTER_EN

SMC_OOB1_TX_L

LPC_AD<1>

SMC_RUNTIME_SCI_L

SMC_PECI_L

SMC_S4_WAKESRC_EN

PM_SLP_S3_L

SMC_TX_L

PM_SLP_S5_L

PM_SLP_S4_L

SMBUS_SMC_2_S3_SDA

TP_SMC_MPM5_LED_PWR
TP_SMC_MPM5_LED_CHG

SMS_INT_L

USB_SMC_P

BDV_BKL_PWM

SMC_THRMTRIP

SMC_ADC22

LPC_FRAME_L

LPC_CLK33M_SMC

SMC_ADC9

SMC_ADC11

SMC_ADC15

SMC_ADC6

SMC_ADC10

SMC_ADC12

SMC_ADC14

SMC_ADC5

SMC_BC_ACOK

SMC_ADC17

SMC_ADC16

SMC_ADC18

SMC_ADC20

SMC_ADC19

SMC_ADC21

PM_PWRBTN_L

ENET_ASF_GPIO

USB_SMC_N

SMBUS_SMC_4_ASF_SDA

G3_POWERON_L

SMC_OOB1_RX_L

IR_RX_OUT_RC

SMC_BATLOW_L

SMC_TMS
SMC_TDO
SMC_TDI

SMC_EXTAL

SMC_WAKE_L

SMC_DEBUGPRT_TX_L

PM_DSW_PWRGD

SMC_GFX_OVERTEMP

ALL_SYS_PWRGD

SMC_CLK32K

SMC_RESET_L

SMC_XTAL

WIFI_EVENT_L

LPC_SERIRQ

LPC_PWRDWN_L

SMC_WAKE_SCI_L

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_3_SDA

SMBUS_SMC_5_G3_SDA

SMC_FAN_0_CTL
SMC_FAN_0_TACH

SMC_FAN_1_TACH

SMC_SYS_KBDLED

CPU_PECI_R

SMC_PME_S4_DARK_L

SMC_DP_HPD_L

SMC_BIL_BUTTON_L

SMC_LID

SMC_RX_L

SMC_PROCHOT

PM_CLKRUN_L

SMC_LRESET_L

PP1V2_S5_SMC_VDDC

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM

NC_SMC_HIB_L

NO_TEST=TRUE

NO_TEST=TRUE

NC_SMC_XOSC1

PP3V3_S5_SMC_VDDA

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.1 MM

U4900

E2
E1
F2
F1
B3
A3
B4
A4
B5
A5
B6
A6
C1
C2
B1
B2
G2
G1
H1
H2
B7
A7
B8
A8

K2
K1
L2

E10
D13

M4
N2
N8
M8
L8
K8
N7
M7
N4
N3

B13
A13
C12
D11
H12

G11

D12

F13

C13

F12

H13

L1

C4
C6

L9
K9

J4
J2

B12

C11

A12

H11
L13

G3

D10

L11
N12
N11
M11

M13
L12

M5

J12

J13

L5
D8
K6

D4
E4
F5

N5
N6
K5
M6
L6

M2
M3
L4
N1

L10
K10

M9
N9

F4
F3

C9
B9
A9
C8

D5

C5

L3
M1

F11
E11

E13
E12

K7
L7

K3
K4

J3
H4
H3
G4

H10

U4900

A1
C7

K11

D9
E5
F9
H5
H9
J5
J8
J11

C3
E3

M12

G12

G13

B11

G10 C10

A10
A11
B10

K12

D7
E6
E8
E9

F10

J7
J9

J10

D3

J1
J6

K13

D6

D1

D2

N13

M10

N10

XW4900

12

C4914

1

2

C4915

1

2

C4916

1

2

C4917

1

2

C4913

1

2

R4902

1

2

C4906

1

2

C4905

1

2

C4909

1

2

C4908

1

2

C4904

1

2

C4903

1

2

C4902

1

2

C4907

1

2

C4901

1

2

L4901

1 2

C4911

1

2

C4910

1

2

C4912

1

2

C4920

1

2

C4921

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

49 OF 132

39 OF 80

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7

40

41

40

40

www.vinafix.vn

IN

OUT

BI

IN

IN

IN

REFOUT

MR1*

THRM

GND

RESET*

DELAY

MR2*

VIN

V+

SN0903048

PAD

IN

OUT

IN

OUT

IN

OUT

NCNC

NC NC

IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT

BI

IN

OUT

OUT

IN

NCNC

IN

D

GS

D

S G

D

S G

D

G S

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

SMC Reset "Button", Supervisor & AVREF Supply

Mac Mini: 5V

NOTE: Internal pull-ups are to VIN, not V+.

SMC Crystal Circuit

Mobiles: 3.42V

Debug Power "Buttons"

MR1* and MR2* must both be low to cause manual reset.

(IPU)

(IPU)

BATLOW# ISOLATION

Internal 20K pull-up on PM_BATLOW_L in PCH.

ADC10 AND ADC11 ARE SHARED WITH COMPARATORS ON STACK BOARD

To SMC

SMC12 PECI SUPPORT

From/To CPU/PCH

Used on mobiles to support SMC reset via keyboard.

SERIES RESISTORS ARE NO STUFFED UNTIL THE TOPOLOGY OF 2 SPI MASTERS IS VERIFIED

SMC12 SPI SUPPORT

S4 SMC WAKE SOURCES

HDMI HPD ESD PROTECTION

639-3261 (J4 Hall effect board) reports to 607-9320

Hall Effect pads

APN: 998-4692

SMC USB CLOCK REQUIRE THESE CRYSTAL VALUES:5,6,8,10,12,16,18,20,24,25 MHZ

5% 201MF

1/20W

10K

1/20W

5% 201MF

100K

5% 201MF

10K

1/20W

5% 201MF

100K

1/20W

1/20W

5% 201

10K

MF

1/20W

5% MF

10K

201

1/20W

5% MF

10K

201

1/20W

5% MF 201

10K

1/20W

5% 201MF

10K

39 40

20

SILK_PART=PWR_BTN

1/10W

5%

603

MF-LF

0

PLACE_SIDE=TOP

OMIT

11 39 61 72

39

1/20W

5% 201MF

10K

1/20W

5% MF 201

10K

1%
MF

201

1/20W

2.49K

0201

5%
25V
NP0-C0G

12PF

MF 2015%

1/20W

100K

1/20W

5% 201MF

10K

NOSTUFF

1/20W

201MF

10K

5%

OMIT

0

MF-LF

1/10W

5%

603

SILK_PART=PWR_BTN

PLACE_SIDE=BOTTOM

PLACE_SIDE=BOTTOM

OMIT

SILK_PART=SMC_RST

0

MF-LF
603

5%
1/10W

7

39 40 47

47

0.01UF

10%

X5R-CERM

0201

10V

0.47UF

10%

6.3V

CERM-X5R

402

CRITICAL

DFN

VREF-3.3V-VDET-3.0V

CERM-X5R

10UF

0402-1

20%

6.3V

NOSTUFF

10%
10V

0201

X5R-CERM

0.1UF

201

5%
1/20W
MF

100K

18

1/20W

5%
MF

22

PLACE_NEAR=U1800.N14:5.1mm

201

39

1/20W

5% 201MF

100K

47 39

100K

1/20W

5%

201

MF

39 66 18

1/20W

5%

201

MF

100K

1/16W

5%

402

MF-LF

0

NOSTUFF

50V

10%
0402

X7R-CERM

0.001UF

0

MF-LF

402

1/16W

5%

OMIT_TABLE

12.000MHZ-30PPM-10PF

CRITICAL

SM-3.2X2.5MM

5% 201MF

10K

1/20W
1/20W

5% 201

100K

MF

1/20W

5% 201MF

10K

1/20W

5%

201

MF

1K

12PF

NP0-C0G
0201

5%
25V

1/20W

5% 201MF

100K

1/20W

5%

201

MF

330

NONE

NONE

402

NONE

NOSTUFF

OMIT

1/20W

5%

201

MF

0

100K

MF 2015%

1/20W

NO STUFF

80

41 50

24

PLACE_NEAR=U6100.2:1MM

MF

201

5%

1/20W

39

41 50

43

MF

201

5%

1/20W

PLACE_NEAR=U6100.5:1MM

39

41 50

15

PLACE_NEAR=U6100.6:1MM

MF

201

5%

1/20W

39

41 50

15

PLACE_NEAR=U6100.1:1MM

MF

201

1/20W

5%

39

100K

1/20W

1%

201

MF

201

1/20W

1%
MF

100K

1/20W

5% 201MF

100K

39 40

1/20W

201MF

100K

5%

CRITICAL

DFN1006-3

MMBT3904LP-7

39

1/20W

5%

201

MF

43

11 20 72

1/20W

5% MF

10K

201

NOSTUFF

1/16W

5%

MF-LF

402

3.3K

11 20 72

7

39 40 47

39

7

36

36

OMIT_TABLE

SM

HALL-EFFECT-SENSOR-MLB-D1

1/20W

5% 201MF

100K

1/20W

5% 201MF

100K

VESM

SSM3K15AMFVAPE

CRITICAL

SSM6N15AFE

CRITICAL

SOT563

SSM6N15AFE

CRITICAL

SOT563

VESM

CRITICAL

SSM3K15AMFVAPE

201

MF

1/20W

1K

5%

4.7UF

6.3V
X5R

20%

402

47

MF

1/20W

5%

201

0

201

MF

1/20W

5%

1000PF

201

X7R

10%
16V

NOSTUFF

7

39 41 57

1/20W

5% 201MF

100K

NO STUFF

CRITICALY5010

XTAL,12MHZ,30PPM,10PF,3.2X2.5X0.7MM,90C

1

197S0486

CRITICAL

SUBASSY,PCBA HALL EFFECT,J4

J5050

1

607-9320

SMC Support

SYNC_MASTER=D1_SENSORS

SYNC_DATE=02/20/2012

SMC_EXTAL

=PP3V3_S5_SMC

SMC_LID_R

SMC_LID

=PP3V42_S3_HALL

SMC_XTAL_R

MIN_NECK_WIDTH=0.1 mm

GND_SMC_AVSS

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

SMC_ADC9

SMC_ADC16

SMBUS_SMC_4_ASF_SDA

SMC_ADC0

SMC_ADC2

SMC_ADC4

SMC_ADC6

SMC_ADC20

SMC_ADC23

HDMI_HPD_L

MAKE_BASE=TRUE

SMC_DP_HPD_L

HISIDE_ISENSE_OC

SMC_ADC13

SMC_ADC22

=PPVCCIO_S0_SMC

SMC_TPAD_RST_L

MIN_NECK_WIDTH=0.1 mm
VOLTAGE=3.42V

MIN_LINE_WIDTH=0.4 mm

PP3V42_G3H_SMC_SPVSR

NC_SYS_TDM_ONEWIRE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_GFX_OVERTEMP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_GFX_OVERTEMP

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_EVENT_L
NC_SMC_ODD_DETECT

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_IR_RX_OUT_RC

MAKE_BASE=TRUE

NO_TEST=TRUE

SMC_CPU_ISENSE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_SMC_GPU_P1V35_ISENSE

NO_TEST=TRUE

NC_SMC_GPU_HI_ISENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

SDCONN_STATE_CHANGE_SMC

SMC_BC_ACOK

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMC_TBT_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_PCH_CORE_ISENSE

MAKE_BASE=TRUE

SMC_BMON_ISENSE

MAKE_BASE=TRUE

SMC_X29_ISENSE

NC_HISIDE_ISENSE_OC

MAKE_BASE=TRUE

NO_TEST=TRUE

SMC_CPU_VSENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_BDV_BKL_PWM

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SDA

NC_SMC_SYS_LED

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_SSD_ISENSE

NC_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

SMC_LCD_PANEL_ISENSE

SMC_CPU_SA_VSENSE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMC_T25_ISENSE

MAKE_BASE=TRUE

SMC_AXG_ISENSE

SMC_LCDBKLT_VSENSE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMC_PME_S4_WAKE_L

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_OTHER_HI_ISENSE

MAKE_BASE=TRUE

SMC_CPU_SA_ISENSE

MAKE_BASE=TRUE

SMC_MEM_ISENSE

MAKE_BASE=TRUE

SMC_LCDBKLT_ISENSE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_SMBUS_SMC_4_ASF_SCL

MAKE_BASE=TRUE

SMC_AXG_VSENSE

MAKE_BASE=TRUE

NC_T25_EN_L

NO_TEST=TRUE

SMC_VCCIO_ISENSE

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMC_PBUS_VSENSE

MAKE_BASE=TRUE

SMC_DCIN_ISENSE

MAKE_BASE=TRUE

SMC_DCIN_VSENSE

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1 mm

SMC_CLK32K

=PPVIN_S5_SMCVREF

CPU_THRMTRIP_3V3

SMS_INT_L

SMC_S5_PWRGD_VIN

SMC_TCK

SMC_TDI

SMC_TDO

SMC_TMS

SMC_TX_L

SMC_OOB1_RX_L

PM_THRMTRIP_L

SMC_OOB1_TX_L

SMC_LID

SMC_RX_L
SMC_DEBUGPRT_TX_L

=PP3V3_S5_SMC

SPI_SMC_CLK

SPI_SMC_CS_L SPI_MLB_CS_L

=PP3V3_S4_SMC

SPI_MLB_MISO

SPI_MLB_MOSI

SMC_SYS_LED
MEM_EVENT_L
SMC_ODD_DETECT
IR_RX_OUT_RC

SMC_GFX_OVERTEMP
SYS_TDM_ONEWIRE

SMC_GFX_OVERTEMP

ENET_ASF_GPIO

SMC_GFX_THROTTLE_L

CPU_PROCHOT_L

CPU_PECI

SMC_DELAYED_PWRGD
SMC_PM_G2_EN

SMC_S4_WAKESRC_EN

SMC_THRMTRIP

SMC_ROMBOOT

SMC_ADC8

=PP3V3_S4_SMC

SPI_DESCRIPTOR_OVERRIDE_L

SMC_ADAPTER_EN

=CHGR_ACOK

SMC_ADC1

SMC_VCCIO_CPU_DIV2

SMBUS_SMC_4_ASF_SCL

BDV_BKL_PWM
SMC_PME_S4_DARK_L

=TBT_WAKE_L

SMC_ADC19

SMC_ADC21

PM_CLK32K_SUSCLK_R

SMC_ADC7

SMC_ADC17

SMC_ADC3

PM_THRMTRIP_B_L

SMC_ADC5

SMC_ONOFF_L

WIFI_EVENT_L

PP3V3_WLAN_F

SMC_BIL_BUTTON_L
SMC_BC_ACOK

SMC_ONOFF_L

SMC_PME_S4_DARK_L

G3_POWERON_L

SMC_DEBUGPRT_RX_L

SMC_PECI_L

SMC_XTAL

SPI_SMC_MOSI

CPU_THRMTRIP_3V3

SMC_ADC14

SMC_ADC10

SMC_ADC18

=PP3V3_S5_SMCBATLOW

SMC_T25_EN_L

SMC_ADC15

SMC_ADC12

SPI_MLB_CLK

SMC_BATLOW_L

PM_BATLOW_L

=PP3V3_SUS_SMC

SMC_PROCHOT

PM_THRMTRIP_L_R

=PPVCCIO_S0_SMC

CPU_PECI_R

SMC_PECI_L_R

SPI_SMC_MISO

SMC_THRMTRIP

SMC_ADC11

=PSOC_WAKE_L

SMC_RESET_R_L

SMC_RESET_L

=BT_WAKE_L

SMC_MANUAL_RST_L

GND_SMC_AVSS

SMC_ONOFF_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_ENET_ASF_GPIO

R5070

1 2

R5071

1 2

R5073

1 2

R5074

1 2

R5077

1 2

R5078

1 2

R5079

1 2

R5080

1 2

R5085

1 2

R5015

1

2

R5089

1 2

R5081

1 2

R5010

1 2

C5011

1

2

R5087

1 2

R5093

1 2

R5072

1 2

R5016

1

2

R5001

1

2

C5001

1

2

C5020

1

2

U5010

4

2

6
7

8

5

9

1

3

C5025

1

2

C5026

1

2

R5000

1

2

R5012

1 2

R5090

1 2

R5082

1

2

R5040

1

2

R5041

1 2

C5050

1

2

R5050

1 2

Y5010

2 4

1 3

R5075

1 2

R5076

1 2

R5086

1 2

R5088

1

2

C5010

1

2

R5069

1 2

R5031

1

2

R5033

1

2

R5032

1 2

R5068

1 2

R5021

1 2

R5022

1 2

R5023

1 2

R5024

1 2

R5097

1

2

R5096

1

2

R5092

1 2

R5094

1 2

Q5058

1

3

2

R5034

1 2

R5095

1 2

R5058

1 2

J5050

1
2
3
4 5

6

7

8

R5091

1 2

R5098

1 2

Q5040

3

1

2

Q5059

6

2

1

Q5059

3

5

4

Q5030

3

1

2

R5057

1 2

C5027

1

2

R5027

1 2

R5028

1 2

C5028

1

2

R5067

1 2

<BRANCH>

<SCH_NUM>

<E4LABEL>

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39 49

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39

39

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39

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OUT

IN

IN

IN

OUT

IN

OUT

OUT

IN

BI

BI

OUT

OUT

OUT

OUT

OUT

OUT

OUT

IN

BI

IN

IN

OUT

BI

BI

IN

OUT

IN

OUT

IN

IN

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

998-4235

LPC+SPI Connector

SPI Bus Series Termination

PLACE_NEAR=J5100.12:5mm

43

MF-LF
402

5%
1/16W

LPCPLUS_R:YES

40 50

43

1/16W

5%

402

MF-LF

PLACE_NEAR=R5127.2:5mm

PLACE_NEAR=U1800.AY1:5mm

15

MF-LF

402

5%

1/16W

17 75

PLACE_NEAR=J5100.9:5mm

43

MF-LF
402

5%
1/16W

LPCPLUS_R:YES

24

PLACE_NEAR=J5100.11:5mm

MF-LF
402

5%
1/16W

LPCPLUS_R:YES

7

39 40

7

25

7

41

7

17 39 75

7

20

7

39 40

7

17 39 75

7

17 39 75

7

25 75

7

17 39 75

LPCPLUS_CONN:YES

CRITICAL

DF40C-30DP-0.4V

M-ST-SM

7

39 40

7

39 40

7

40

7

39 40 57

7

39 40

7

39 40

7

18 25 39

7

17 39

7

41

7

41

7

18 39

7

20 50

7

17 39 75

7

41

40 50

PLACE_NEAR=U1800.AV3:5mm

15

MF-LF

402

5%

1/16W

17 75

40 50

PLACE_NEAR=U1800.BA2:5mm

15

MF-LF

402

5%

1/16W

17 75

40 50

24

1/16W

5%

402

MF-LF

PLACE_NEAR=U6100.2:5mm

17 75

43

1/16W

5%

402

MF-LF

PLACE_NEAR=R5125.2:5mm

43

PLACE_NEAR=J5100.14:5mm

MF-LF
402

5%
1/16W

LPCPLUS_R:YES

43

1/16W

5%

402

MF-LF

PLACE_NEAR=R5126.2:5mm

LPC+SPI Debug Connector

SYNC_DATE=02/20/2012

SYNC_MASTER=D1_SENSORS

SMC_TX_L

TP_SMC_MD1

TP_SMC_TRST_L

SMC_TDO

LPCPLUS_RESET_L

LPCPLUS_GPIO

LPC_AD<3>

LPC_AD<1>

SPI_ALT_MOSI

LPC_AD<0>

LPC_CLK33M_LPCPLUS

SMC_TMS

SMC_RX_L

SMC_ROMBOOT

SMC_RESET_L

SMC_TCK

SMC_TDI

LPC_PWRDWN_L

LPC_SERIRQ

SPI_ALT_CS_L

SPI_ALT_CLK

PM_CLKRUN_L

SPIROM_USE_MLB

LPC_FRAME_L

SPI_ALT_MISO

=PP3V3_S5_LPCPLUS

SPI_MOSI_R

SPI_MLB_MISO

SPI_MLB_CS_L

SPI_MLB_CLK

SPI_MLB_MOSI

SPI_CS0_R_L

SPI_CLK_R

=PP5V_S0_LPCPLUS

LPC_AD<2>

SPI_ALT_CS_L

SPI_ALT_MOSI
SPI_ALT_CLK

SPI_ALT_MISO

SPI_CS0_L

SPI_CLK

SPI_MOSI

SPI_MISO

R5110

1 2

R5111

1 2

R5123

1 2

R5120

1 2

R5125

1

2

R5121

1 2

R5126

1

2

R5122

1 2

R5112

1 2

R5127

1

2

R5128

1

2

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

<BRANCH>

<SCH_NUM>

<E4LABEL>

51 OF 132

41 OF 80

7

7

8

8

7

41

7

41

7

41

7

41

75

75

75

www.vinafix.vn

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

PCH SMBus "0" Connections

(Write: 0x30 Read: 0x31)

Margin Control

(Write: 0x98 Read: 0x99)

(WRITE: 0xCC READ: 0xCD)

(WRITE: 0X76 READ: 0X77)

HDMI Redriver (on RIO)

SMC "3" SMBUS CONNECTIONS

(WRITE: 0X58 READ: 0X59)

LED BACKLIGHT

U9700

U4900

(MASTER)

(Write: 0x10 Read: 0x11)

(Write: 0x98 Read: 0x99)

(Write: 0x72 Read: 0x73)

(WRITE: 0XD0 READ: 0XD1)

Trackpad

(MASTER)

U4900

SMS

(Write: 0x90 Read: 0x91)

J5800

EMC1414-A: U5550

Battery

SMC "5" SMBUS CONNECTIONS

(MASTER)

SMC

Battery Charger

ISL6258 - U7000

SMC

U3300

(See Table)

U4900

SMC

U5920

U5940

GYRO

DEBUG SENSOR ADC A

GPU Temp (Ext)

SMC "0" SMBus Connections

J6955

Battery

(Write: 0x12 Read: 0x13)

PCH "SMLink 0" Connections

(MASTER)

U1800

U3301

Panther Point

U1800

(MASTER)

XDP Connectors

(WRITE: 0X30/31 READ: 0X32/33)

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC "2" SMBUS CONNECTIONS

(MASTER)

U4900

(Write: 0x98 Read: 0x99)

CPU/DDR3/PCH/AIRFLOW TEMP

(WRITE: 0X92 READ: 0X93)

SMC "1" SMBUS CONNECTIONS

EMC1414-A: U5570

TMP105: U5523

X29 TEMP

SMC

U1800

access PCH & CPU via PECI.

SMLink 1 is slave port to

(Write: 0x88 Read: 0x89)

(MASTER)

U6411

U3600

TBT

(WRITE: 0XXX READ: 0XXX)

U6410

U6400

AUDIO

AUDIO

(WRITE: 0X34 READ: 0X35)

(WRITE: 0XE0 READ: 0XE1)

AUDIO

(WRITE: 0X32 READ: 0X33)

U6751

U6750

(WRITE: 0X38 READ: 0X39)

U6421

U6420

(WRITE: 0XD8 READ: 0XD9)

SPKR TEMP

PCH "SMLink 1" Connections

J4410

J2500 & J2550

(WRITE: 0X72 READ: 0X73)

AUDIO

SMC

U4900

(MASTER)

Battery Manager - (Write: 0x16 Read: 0x17)

UD000

Panther Point

Panther Point

J3502

ALS

MIKEY

VRef DACs

DEBUG_ADC

5%

4.7K

1/20W
MF
201

DEBUG_ADC

5%

4.7K

1/20W

MF

201

5%

2.0K

1/20W

MF

201

5%

2.0K

1/20W
MF
201

5%

1K

1/20W

MF

201

5%

1K

1/20W
MF
201

5%

4.7K

1/20W
MF
201

5%

4.7K

1/20W

MF

201

5%

8.2K

1/20W

MF

201

5%

8.2K

1/20W
MF
201

5%

1K

1/20W
MF
201

5%

1K

1/20W

MF

201

5%

1K

1/20W
MF
201

5%

1K

1/20W

MF

201

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

SMBus Connections

=I2C_CPUTHMSNS_SCL

=I2C_SPKRTHMSNS_SCL

=I2C_X29THMSNS_SCL

SMB_1_S0_CLK

SML_PCH_1_CLK

=I2C_CPUTHMSNS_SDA

=I2C_SPKRTHMSNS_SDA

=I2C_X29THMSNS_SDA

SMB_1_S0_DATA

SML_PCH_1_DATA

SMB_5_CLK
SMB_5_DATA

=I2C_BKL_1_SCL

=I2C_TBTRTR_SDA

=I2C_TBTRTR_SCL

=SMBUS_XDP_SCL
=SMBUS_XDP_SDA

=I2C_MIKEY_SDA

=PP3V3_S0_SMBUS_SMC_1_S0

SMB_0_S0_CLK

=I2C_SMC_SMS_SCL

=I2C_MIKEY_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

=PP3V3_S0_SMBUS_PCH

=I2C_SMC_ADCS_SCL

=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA

=SMBUS_BATT_SDA

=PP3V3_S0_SMBUS_PCH

=I2C_PCA9557D_SCL

=SMBUS_BATT_SCL

SMB_3_CLK

=I2C_SMC_SMS_SDA

=I2C_ALS_SCL
=I2C_ALS_SDA

SMB_3_DATA

=PP3V3_S3_SMBUS_SMC_2_S3

=PP3V3_S0_SMBUS_SMC_0_S0

=I2C_VREFDACS_SCL

=SMBUS_GPUTHMSNS_SCL

SMB_0_S0_DATA

=I2C_SMC_GYRO_SCL

=I2C_TPAD_SCL

=I2C_SMC_GYRO_SDA

SMB_2_S3_CLK
SMB_2_S3_DATA =I2C_TPAD_SDA

=SMBUS_GPUTHMSNS_SDA

=I2C_SMC_ADCS_SDA

=PP3V42_G3H_SMBUS_SMC_5

=I2C_BKL_1_SDA

=PP3V3_S3_SMBUS_SMC_3

MAKE_BASE=TRUE

SMBUS_SMC_3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_3_SDA

SMBUS_SMC_2_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_2_S3_SCL

MAKE_BASE=TRUE

SML_PCH_0_DATA

MAKE_BASE=TRUE

SML_PCH_0_CLK

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_5_G3_SDA

MAKE_BASE=TRUE

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_1_S0_SCL

SMBUS_PCH_CLK

MAKE_BASE=TRUE

=I2C_HDMIRDRV_SCL
=I2C_HDMIRDRV_SDA

SMBUS_PCH_DATA

MAKE_BASE=TRUE

R5291

1

2

R5290

1

2

R5280

1

2

R5281

1

2

R5270

1

2

R5271

1

2

R5251

1

2

R5250

1

2

R5210

1

2

R5211

1

2

R5201

1

2

R5200

1

2

R5261

1

2

R5260

1

2

<BRANCH>

<SCH_NUM>

<E4LABEL>

52 OF 132

42 OF 80

45

36

17 75

45

36

17 75

71

33

33

24

24

54

8

49

54

31

31

8

42

57

57

56

8

42

31

56

49

32

32

8

8

31

45

49

47

49

47

45

8

71

8

39

77

39

77

17 75

17 75

39

77

39

77

7

17 75

36

36

7

17 75

www.vinafix.vn

IN

OUT

OUT

IN

OUT

IN

IN

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

OUT

IN

IN

IN

OUT

IN

IN

IN

IN

V+

V-

OUT

OUT

V+

V-

THRM

V-

V+

THRM

V-

V+

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Gain: 649.35x, EDP: 5 A (16.5 W)

SMC ADC: 18

AXG Core Voltage Sense (VN0C)

CPU Core Voltage Sense (VC0C)

SSD Current Sense (ISDC)

Gain: 364.9x, EDP: 9 A

AXG Core Load Side Current Sense (IN0C)

Rsense: 0.001 (R5370)

Gain: 1x
SMC ADC: 00

V across Rsense: 17.25 mV

Rsense: 2x of 0.00075 (R7550, R7560), Rsum: 0.000375

Gain: 190.6x, EDP: 46 A

SMC ADC: 12

Gain: 1x

Rsense: 2x of 0.00075 (R7510, R7520), Rsum: 0.000375
V across Rsense: 19.8 mV

Gain: 161.7x, EDP: 53 A

CPU Core Load Side Current Sense (IC0C)

SMC ADC: 01

SMC ADC: 10

SMC ADC: 06

V across Rsense: 9 mV

V across Rsense: 5 mV

Rsense: 0.001 (R5370)

DDR 1.35V S3 (Memory) Current Sense (IM0C)

SMC ADC: 11

V across Rsense: 15 mV

Rsense: 0.001 (R7640)

Gain: 200x, EDP: 20 A

CPU/PCH VCCIO & TBT 1.05V Load Side Current Sense (IC1C)

37 78

0201

6.3V

20%
X5R

PLACE_NEAR=U4900.E2:5MM

0.22UF

MF

PLACE_NEAR=U4900.E2:5MM

201

1%

4.53K

1/20W

40

40

NO_XNET_CONNECTION=TRUE

1M

MF-LF

402

1%

1/16W

MF

201

1/20W

1%

1.54K

1/16W

1M

MF-LF
402

1%

1.54K

1/20W

1%

201

MF

37 78

1M

MF-LF
402

1%
1/16W

1/16W
MF-LF

402

1%

2.74K

2.74K

MF-LF

402

1%

1/16W

PLACE_NEAR=U4900.B4:5MM

0201

6.3V

20%
X5R

0.22UF

PLACE_NEAR=U4900.B4:5MM

201

4.53K

1/20W

MF

1%

NO_XNET_CONNECTION=TRUE

1/16W

1M

MF-LF

402

1%

8

PLACE_NEAR=U4900.B6:5MM

0201

6.3V

0.22UF

X5R

20%

PLACE_NEAR=U4900.B6:5MM

201

1%

1/20W

MF

4.53K

PLACE_NEAR=U5370.8:3MM

0.1UF

CERM
402

20%
10V

63 78

63 78

LOADISNS:YES

CRITICAL

SC70

INA210

PLACE_NEAR=R7640.4:5MM

PLACE_NEAR=R7640.3:5MM

10V

0.1uF

LOADISNS:YES

402

CERM

20%

PLACE_NEAR=U4900.A6:5MM

LOADISNS:YES

201

4.53K

1/20W

MF

1%

8

0201

6.3V

20%

PLACE_NEAR=U4900.A6:5MM

LOADISNS:YES

0.22UF

X5R

40

62 78

PLACE_NEAR=R7560.4:5MM

0402

0.1%

4.42K

1/16W

MF

NO_XNET_CONNECTION=TRUE

LOADISNS:YES

40

62 78

62 78

62 78

40

62 78

1W

1%

0612

MF-1

0.001

PLACE_NEAR=R7550.4:5MM

LOADISNS:YES

4.42K

0402

0.1%

1/16W

MF

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7560.3:5MM

LOADISNS:YES

4.42K

0402

0.1%

1/16W

MF

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7550.3:5MM

LOADISNS:YES

0402

4.42K

0.1%

1/16W

MF

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7520.4:5MM

LOADISNS:YES

1/16W

0.1%

0402

MF

4.42K

NO_XNET_CONNECTION=TRUE

LOADISNS:YES

0.1%

402

MF

NO_XNET_CONNECTION=TRUE

715K

1/16W

1/16W

402

MF

715K

NO_XNET_CONNECTION=TRUE

LOADISNS:YES

NO_XNET_CONNECTION=TRUE

0.1%

1/16W

1%

402

MF-LF

1.54K

LOADISNS:YES

LOADISNS:YES

1/16W

1%

402

MF-LF

1.54K

PLACE_NEAR=R7550.2:5 MM

SM

LOADISNS:YES

0.1%

NO_XNET_CONNECTION=TRUE

715K

MF
402

1/16W

PLACE_NEAR=U4900.H1:5MM

0.22UF

LOADISNS:YES

0201

X5R

20%

6.3V

PLACE_NEAR=U4900.H1:5MM

201

1/20W

MF

4.53K

1%

LOADISNS:YES

PLACE_NEAR=U5350.5:3MM

LOADISNS:YES

0.1UF

CERM
402

20%
10V

NO_XNET_CONNECTION=TRUE

1/16W

402

LOADISNS:YES

NO_XNET_CONNECTION=TRUE

715K

MF

0.1%

62 78

61 62 78

0201

6.3V
X5R

0.22UF

20%

PLACE_NEAR=U4900.C1:5MM

61 62 78

PLACE_NEAR=R7510.3:5MM

LOADISNS:YES

0.1%

0402

1/16W

MF

4.42K

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7520.3:5MM

LOADISNS:YES

1/16W

0.1%

0402

MF

4.42K

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=R7510.4:5MM

LOADISNS:YES

1/16W

0.1%

0402

4.42K

MF

NO_XNET_CONNECTION=TRUE

LOADISNS:YES

2.21K

MF

0402

0.1%

1/16W

LOADISNS:YES

2.21K

MF

0402

0.1%

1/16W

LOADISNS:YES

ISL28133

CRITICAL

SC70-5

PLACE_NEAR=U5340.5:3MM

LOADISNS:YES

0.1UF

CERM
402

20%
10V

PLACE_NEAR=U4900.E1:5MM

0201

6.3V

20%
X5R

0.22UF

LOADISNS:YES

201

1%

1/20W

PLACE_NEAR=U4900.C1:5MM

MF

4.53K

PLACE_NEAR=U4900.E1:5MM

201

4.53K

MF

1/20W

1%

LOADISNS:YES

40

40

LOADISNS:YES

ISL28133

SC70-5

CRITICAL

DFN

OPA2330

CRITICAL

CRITICAL

OPA2330

DFN

PLACE_NEAR=R7510.2:5 MM

SM

Power Sensor: Load Side

SYNC_DATE=02/20/2012

SYNC_MASTER=D1_SENSORS

LOADISNS:NO

3

C5349,C5359,C5369

117S0008

RES,MTL FLIM,100K,1/16W,0201,SMD,LF

=PP3V3_S0_ISNS

=PP3V3_S3_ISNS

CPUVCCIOS0_CS_P

CPUVCCIOS0_CS_N

CPUVCCIO_IOUT

ISNS_1V35_S3_MEM_R_N

=PP3V3_S3_ISNS

ISNS_SSD_P

ISNS_1V35_S3_MEM_N

=PPVIN_S3_MEM_ISNS_R

ISNS_1V35_S3_MEM_P

ISNS_SSD_N

GND_SMC_AVSS

GND_SMC_AVSS

SMC_VCCIO_ISENSE

CPUIMVP_ISNS2_N

GND_SMC_AVSS

CPUIMVP_ISNS_N

CPUIMVP_ISUM_R_P

CPUIMVP_ISUM_R_N

CPUIMVP_ISUM_IOUT

CPUIMVP_ISNS1_N

CPUIMVP_ISNS2_P

CPUIMVP_ISNS_P

=PP3V3_S0_IMVPISNS

SMC_CPU_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS

SMC_CPU_VSENSE

SMC_AXG_VSENSE

AXGVSENSE_IN

CPUIMVP_ISUMG_IOUT

CPUIMVP_ISUMG_R_N

CPUIMVP_ISNSG_P

CPUIMVP_ISNSG_N

CPUIMVP_ISUMG_R_P

CPUIMVP_ISNS1G_N

CPUIMVP_ISNS2G_P

CPUIMVP_ISNS2G_N

=PPVCORE_S0_CPU_VCCAXG

=PPVCORE_S0_CPU

SMC_MEM_ISENSE

=PPVIN_S3_MEM_ISNS

=PP3V3_S0_IMVPISNS

GND_SMC_AVSS

ISNS_1V35_S3_MEM_R_P

ISNS_3V3_S0_SSD_R_N

ISNS_3V3_S0_SSD_R_P

ISNS_3V3_S0_SSD_IOUT

CPUIMVP_ISNS1G_P

ISNS_1V35_S3_MEM_IOUT

CPUVSENSE_IN

GND_SMC_AVSS

SMC_AXG_ISENSE

CPUIMVP_ISNS1_P

SMC_SSD_ISENSE

R5370

123

4

XW5330

1 2

C5339

1

2

R5339

1 2

XW5320

1 2

C5329

1

2

R5329

1 2

R5384

1 2

R5382

1 2

R5383

1

2

R5381

1 2

R5373

1

2

R5372

1 2

R5371

1 2

C5389

1

2

R5389

1 2

R5374

1 2

C5379

1

2

R5379

1 2

C5370

1

2

U5360

2

5

4

6

1

3

C5360

1

2

R5369

1 2

C5369

1

2

R5358

1 2

R5357

1 2

R5356

1 2

R5355

1 2

R5348

1 2

R5354

1

2

R5351

1 2

R5353

1 2

R5352

1 2

R5344

1

2

C5359

1

2

R5359

1 2

C5350

1

2

R5341

1 2

R5347

1 2

R5346

1 2

R5345

1 2

R5343

1 2

R5342

1 2

U5340

3

1

4

2

5

C5340

1

2

C5349

1

2

R5349

1 2

U5350

3

1

4

2

5

U5370

3

2

1

9

4

8

U5370

5

6

7

9

4

8

<BRANCH>

<SCH_NUM>

<E4LABEL>

53 OF 132

43 OF 80

8

80

8

43

78

8

43

78

39 40 43 44 80

39 40 43 44 80

39 40 43 44 80

78

78

78

78

8

43

39 40 43 44 80

39 40 43 44 80

78

78

78

78

8

10 13 16

8

10 13 15

8

43

39 40 43 44 80

78

78

78

39 40 43 44 80

www.vinafix.vn

IN

OUT

OUT

IN-

IN+ REF

V+

GND

IN

OUT

IN

IN

IN

OUT

IN

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

OUT

IN

S

S

D

N-CHANNEL

G

D

G

P-CHANNEL

OUT

OUT

OUT

IN-

IN+ REF

V+

GND

OUT

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

SMC ADC: 04

V across Rsense: 26.4 mV

Gain: 100x, EDP: 8.8 A

SMC ADC: 03

SMC ADC: 09

PBUS Voltage Sense & Enable (VP0R)

divider when in S0.

Enables PBUS VSense

SMC ADC: 05

Gain: 0.167x

Rthevenin = 4573 Ohms

Rthevenin = 4573 Ohms

divider when AC present.

Gain: 0.167x

SMC ADC: 07

Rsense: 0.010 (R7050)

Rsense: 0.020 (R7020)

DC-In (AMON) Current Sense (ID0R)

Charger (BMON Production) Current Sense (IPBR)

Charger Gain: 36x, EDP: 6.6 A

Rsense: 0.003 (R5410)

DC In Voltage Sense & Enable (VD0R)

Enables DC-In VSense

Charger Gain: 20x, EDP: 4.6 A

SMC ADC: 08

OTHER High Side Current Sense (IO0R)

V across Rsense: 52.2 mV

Rsense: 0.003 (R5400)

Gain: 50x, EDP: 17.4 A

CPU High Side Current Sense (IC0R)

57

PLACE_NEAR=U4900.A4:5MM

0201

10V
X7R-CERM

10%

3300PF

40

CRITICAL

SC70

INA214

10V

20%
402

CERM

0.1UF

PLACE_NEAR=U4900.A5:5MM

4.53K

201

MF

1/20W

1%

PLACE_NEAR=U4900.A5:5MM

0201

X5R

20%

6.3V

0.22UF

8

8

57

PLACE_NEAR=U5400.5:10MM

PLACE_NEAR=U5400.4:10MM

1%

1W

CRITICAL

0.003

MF

0612

10V

20%
402

CERM

0.1UF

PLACE_NEAR=U4900.B5:5MM

0201

0.22UF

X5R

20%

6.3V

PLACE_NEAR=U4900.B5:5MM

201

MF

1/20W

4.53K

1%

1/16W

1%

402

MF-LF

100K

66

40 57

40

1/20W

5%

201

MF

0

8

0

1/20W

5%

201

MF

NOSTUFF

1/16W

1%

402

MF-LF

100K

PLACE_NEAR=U4900.F1:5MM

1/16W

1%

402

MF-LF

5.49K

PLACE_NEAR=U4900.F1:5MM

1/16W

1%

402

MF-LF

27.4K

PLACE_NEAR=U4900.F1:5MM

0201

0.22UF

X5R

20%

6.3V

SOT-963

NTUD3169CZ

CRITICAL

1/16W

1%

402

MF-LF

100K

PLACE_NEAR=U4900.A3:5MM

1/16W

1%

402

MF-LF

5.49K

PLACE_NEAR=U4900.A3:5MM

0201

0.22UF

X5R

20%

6.3V

8

40 66

SOT-963

NTUD3169CZ

CRITICAL

1/16W

1%

402

MF-LF

100K

PLACE_NEAR=U4900.A3:5MM

1/16W

1%

402

MF-LF

27.4K

40

40

PLACE_NEAR=R5400.1:10 MM

SM

CRITICAL

SC70

INA214

PLACE_NEAR=U5410.5:10MM

PLACE_NEAR=U5410.4:10MM

1%

1W

CRITICAL

0.003

MF

0612

PLACE_NEAR=U4900.B3:5MM

201

MF

1/20W

1%

45.3K

PLACE_NEAR=U4900.B3:5MM

X7R-CERM

2200PF

10%
10V

0201

40

PLACE_NEAR=U4900.A4:5MM

1/20W

1%

300K

201

MF

SYNC_DATE=02/20/2012

Power Sensor: High Side

SYNC_MASTER=D1_SENSORS

ISNS_HS_COMPUTING_N

=PP3V3_S0_HS_COMPUTING_ISNS

ISNS_HS_COMPUTING_P

HS_COMPUTING_IOUT

=PPVIN_S5_HS_COMPUTING_ISNS_R

GND_SMC_AVSS

=CHGR_ACOK

=PPVIN_S5_HS_COMPUTING_ISNS

=PPVIN_S5_HS_OTHER_ISNS_R

=PP3V3_S0_HS_OTHER_ISNS

=PPVIN_S5_HS_OTHER_ISNS

SMC_DCIN_ISENSE

ISNS_HS_OTHER_N

ISNS_HS_OTHER_P

CHGR_AMON

GND_SMC_AVSS

HS_OTHER_IOUT

SMC_OTHER_HI_ISENSE

GND_SMC_AVSS

=PPDCIN_S5_VSENSE

PM_SUS_EN

PDCINVSENS_EN_L_DIV

SMC_DCIN_VSENSE

GND_SMC_AVSS

DCIN_S5_VSENSE

PBUSVSENS_EN_L_DIV

DCINVSENS_EN_L

SMC_PBUS_VSENSE

GND_SMC_AVSS

=PBUSVSENS_EN

PBUS_S0_VSENSE

PBUSVSENS_EN_L

SMC_BMON_ISENSE

CHGR_BMON

DCIN_VSENSE_EN

SMC_CPU_HI_ISENSE

=PPBUS_S0_VSENSE

PBUS_S0_VSENSE_IN

GND_SMC_AVSS

R5410

123

4

R5439

1 2

C5439

1

2

R5429

1 2

C5429

1

2

U5410

2

5

4

6

1

3

C5411

1

2

R5419

1 2

C5419

1

2

R5400

123

4

C5401

1

2

C5409

1

2

R5409

1 2

R5491

1

2

R5494

1 2

R5493

1 2

R5481

1

2

R5499

1

2

R5498

1

2

C5499

1

2

Q5490

6

3

2

5

1

4

R5492

1

2

R5489

1

2

C5489

1

2

Q5480

6

3

2

5

1

4

R5482

1

2

R5488

1

2

XW5480

1 2

U5400

2

5

4

6

1

3

<BRANCH>

<SCH_NUM>

<E4LABEL>

54 OF 132

44 OF 80

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39 40 43 44 80

8

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39 40 43 44 80

39 40 43 44 80

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39 40 43 44 80

39 40 43 44 80

8

39 40 43 44 80

www.vinafix.vn

DP1

THERM*/ADDR

DN1

THRM_PAD

VDD

SMDATA

SMCLK

GND

ALERT*

DP2/DN3

DN2/DP3

BI

BI

BI

BI

BI

DP1

THERM*/ADDR

DN1

THRM_PAD

VDD

SMDATA

SMCLK

GND

ALERT*

DP2/DN3

DN2/DP3

Apple Inc.

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

124578

B

D

8 7 6 5 4 3

C

B

A

NOTICE OF PROPRIETARY PROPERTY:

PAGE

12

D

A

C

PAGE TITLE

SHEET

IV ALL RIGHTS RESERVED

R

D

SIZE

DRAWING NUMBER

REVISION

BRANCH

6 3

THE POSESSOR AGREES TO THE FOLLOWING:

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

II NOT TO REPRODUCE OR COPY IT

Place Q5502 on the bottom side, below left

Thermal Diode: Airflow (TA0P)

underneath the left fan well in the neck.

Place Q5504 on the either side,

CPU Proximity, Memory Proximity, Airflow

Thermal Diode: Left Fin Stack (Th1H)

Place Q5501 on the top side on the corner
close to the Left Fin Stack.

Place Q5503 under the top side on the corner

I2C Write: 0x98, I2C Read: 0x99

Thermal Sensor A:

I2C Write: 0x98, I2C Read: 0x99

Place U5570 on top side, on top of
the CPU.

Thermal Sensor: CPU Proximity (Tc0P)

of PCH.

Place U5550 on top side on top

None.

Placement Note:

Placement Note:

Note: Use GND pin B1 on U3600 for N leg.

Placement Note:

Thermal Sensor: T29 Die

Thermal Sensor B:

row of Memory device, between 2nd/3rd device.

Placement Note:

Placement Note: Placement Note:

close to the Right Fin Stack.

Thermal Diode: Airflow (TA1P)

near LCD connector and DCIN connector.

Thermal Diode: Memory Proximity (TM0P)

Place Q5506 on the bottom side, below the

PCH Proximity, Left Fin Pipe, Right Fin Stack

Placement Note:

Thermal Diode: Right Heat Pipe (Th2H)

Thermal Diode: None

Placement Note:

Thermal Sensor: PCH Proximity (TP0P)

BC846BLP

CRITICAL

DFN1006H4-3

CRITICAL

BC846BLP

DFN1006H4-3

47

MF-LF

402

5%

1/16W

10%

402

CERM

PLACE_NEAR=U5570.5:5mm

NO_XNET_CONNECTION=TRUE

50V

0.0022uF

PLACE_NEAR=U5570.4:5mm

0.0022uF

PLACE_NEAR=U5570.3:5mm

PLACE_NEAR=U5570.2:5mm

50V

10%

402

CERM

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U3600.B1:2mm

SM

10V

20%

402

CERM

0.1uF

1/16W

5%

402

MF-LF

10K

EMC1414-A-AIA

DFN

42

42

1/16W

5%

402

MF-LF

10K

42

42

33

0.1uF

CERM
402

20%
10V

10K

MF-LF

402

5%

1/16W

10K

MF-LF
402

5%
1/16W

402

PLACE_NEAR=U5550.3:5mm

PLACE_NEAR=U5550.2:5mm

50V

10%

CERM

0.0022uF

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U5550.4:5mm

PLACE_NEAR=U5550.5:5mm

50V

10%

402

CERM

0.0022uF

NO_XNET_CONNECTION=TRUE

1/16W

5%

402

MF-LF

47

CRITICAL

BC846BLP

DFN1006H4-3

CRITICAL

BC846BLP

DFN1006H4-3

DFN

EMC1414-A-AIA

NOSTUFF

10K

MF-LF
402

5%
1/16W

PLACE_SIDE=TOP

BC846BLP

DFN1006H4-3

CRITICAL

Thermal Sensors

SYNC_DATE=02/20/2012

SYNC_MASTER=D1_SENSORS

TBT_THERMD_P

MAKE_BASE=TRUE

PP3V3_S0_GPUTHMSNS_R

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

=SMBUS_GPUTHMSNS_SCL

CPUTHMSNS_ALERT_L

=I2C_CPUTHMSNS_SCL

=I2C_CPUTHMSNS_SDA

CPUTHMSNS_THM_L

GPU_TDIODE_P

=PP3V3_S0_GPUTHMSNS

=PP3V3_S0_CPUTHMSNS

GPUTHMSNS_THM_L

=SMBUS_GPUTHMSNS_SDA

TBT_THERMD_N

TP_TBT_THERM_DP

GPUTHMSNS_ALERT_L

GPUTHMSNS_D_N

DDR3THMSNS_D1_P

DDR3THMSNS_D1_N

GPUTHMSNS_D_P

GPU_TDIODE_N

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

XW5520

1 2

R5520

1

2

Q5501

1

3

2

Q5506

1

3

2

Q5503

1

3

2

R5570

1 2

C5590

1

2

C5571

1

2

C5570

1

2

R5571

1

2

U5550

83

5

2

4

6

10

9

7

11

1

R5572

1

2

C5550

1

2

R5551

1

2

R5552

1

2

C5551

1

2

C5552

1

2

R5550

1 2

Q5502

1

3

2

Q5504

1

3

2

U5570

83

5

2

4

6

10

9

7

11

1

<BRANCH>

<SCH_NUM>

<E4LABEL>

55 OF 132

45 OF 80

78

78

8

8

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78

78

78

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78

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8 7 6 5 4 3

12

D

C

=PP5V_S0_FAN_LT

8

=PP3V3_S0_FAN_LT

8

SMC_FAN_0_TACH

39 39

OUT OUT

R5651

100K

5%
1/16W
MF-LF

402

39

IN

1

2

Left Fan

R5655

47K

1 2

1/16W
MF-LF

402

5

G

S D

4

7

5%

Q5660

2N7002DW-X-G

SOT-363

3

7

FAN_LT_TACH

FAN_LT_PWM

R5650

1/16W
MF-LF

47K

Right Fan

=PP5V_S0_FAN_RT

8

=PP3V3_S0_FAN_RT

8

1

5%

402

2

CRITICAL

J5650

FF14A-5C-R11DL-B-3H

F-RT-SM

6

NC

1
2
3
4
5

NC NC

7

NC

39

SMC_FAN_1_TACH

SMC_FAN_1_CTLSMC_FAN_0_CTL

IN

R5661

100K

1/16W
MF-LF

1

5%

402

2

S D

1

1 2

2

G

R5665

47K

5%
1/16W
MF-LF

402

Q5660

2N7002DW-X-G

SOT-363

6

FAN_RT_TACH

7

FAN_RT_PWM

7

R5660

1/16W
MF-LF

47K

1

5%

402

2

CRITICAL

J5660

FF14A-5C-R11DL-B-3H

F-RT-SM

6

NC

1
2
3
4
5

7

NC

518S0769518S0769

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=J5_MLB

PAGE TITLE

Fan Connectors

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

56 OF 132

SHEET

46 OF 80

124578

www.vinafix.vn

8 7 6 5 4 3

12

D

C

B

A

PSOC USB CONTROLLER

PLACE_SIDE=BOTTOM

=PP3V3_S4_TPAD

8

47

=PSOC_WAKE_L

40

OUT

PICKB_L

7

47

BUTTON_DISABLE

47

Z2_HOST_INTN

7

47

WS_LEFT_SHIFT_KEY

47

WS_LEFT_OPTION_KEY

47

WS_CONTROL_KEY

47

Z2_KEY_ACT_L

7

47

TPAD_VBUS_EN

66

IN

PSOC_MISO

7

47

PSOC_F_CS_L

7

47

PSOC_MOSI

7

47

PSOC_SCLK

7

47

Z2_MISO

7

47

Z2_CS_L

7

47

Z2_MOSI

7

47

Z2_SCLK

7

47

TP_PSOC_SCL
TP_PSOC_SDA
TP_PSOC_P1_3
TP_ISSP_SCLK_P1_1

ISSP SCLK/I2C SCL

USB_TPAD_P

9

74

USB_TPAD_N

9

74

IC

TMP102

3V3 LDO

PSOC

18V BOOSTER

BOM Options available to CSA 5

TPAD_5V:S4 Original implementation off PP5V_S4
TPAD_5V:LDO_S4 PP5V_S5 LDO power in S4 only
TPAD_5V:LDO_S5 PP5V_S5 LDO power

59 66

IN

PIN NAME

TPAD_5V_FET:YES

SSM3K15FV

=P5VS4_EN

V+

VDD
VOUT

VDD

VIN

Q5721

SOD-VESM-HF

1

G S

R5704

1.5

2 1

R5701

1 2

1/20W

R5702

1 2

1/20W

CURRENT

10UA
80UA

60MA (MAX)
60MA (MAX)

8MA (TYP)
14MA (MAX)

4MA (MAX)

5%
1/16W
MF-LF

402

NC

NC
NC

24

5%
MF

201

24

5%
MF

201

R5703

P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1

78
26

78
26

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

PP3V3_S3_PSOC

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V

1

220K

5%

1/20W

MF

201

2

USB_TPAD_R_P

USB_TPAD_R_N

R_SNS V_SNS

All RC values are TBD

=PP5V_S5_TPAD

8

TPAD_5V_FET:YES

3

D

2

1

R5721

220K

5%

1/20W

MF

201

2

P5VCUMULUS_EN_L

- USB INTERFACES TO MLB

- SPI HOST TO Z2

- TRACKPAD PICK BUTTONS

- KEYBOARD SCANNER

BYPASS=U5701.49:50:5 mm

1

C5704

100PF

5%
25V

2

NP0-CERM
0201

51

P0_3

P0_1

CY8C24794

50

VDD

VSS

P0_5

P0_7

CRITICAL

OMIT

U5701

MLF

(SYM-VER2)

P0_4

P0_6

55

P2_5

P2_7

337S2983

P7_0

P7_7

VSS

VDD

P1_1

P1_3

P1_5

P1_7

15

5V TRACKPAD S4 FET

D+

D-

20

21

19

0.0255 V

0.204 V

0.6 V

0.012 V

0.012 V

0.021 V

0.0188 V

TPAD_5V_FET:YES

TPAD_5V_FET:YES

R5722

3.3K

1 2

1/20W

201

24

235722 49

1

C5702

100PF

5%
25V

2

NP0-CERM
0201

BYPASS=U5701.22:19:5 mm

0.255E-6 W

16.32E-6 W

0.72E-3 W

75.2E-6 W

C5722

0.033UF

10%
16V
X5R
402

5%
MF

BYPASS=U5701.49:50:8 mm

1

2

45544653475248

435644

P2_4

P2_6

P0_2

P0_0

P2_2
P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0

THRML

P1_0

25182617271628

PAD

P1_2

P1_4

P1_6

TP_ISSP_SDATA_P1_0

ISSP SDATA/I2C SDA

1

2

BYPASS=U5701.22:19:8 mm

POWER

36E-3 W

96E-6 W

294E-6 W

1

2

P5VCUMULUS_SS

C5705

0.1UF

10%

6.3V
X5R
201

WS_KBD23
WS_KBD22
WS_KBD21
WS_KBD20
WS_KBD19
WS_KBD18

421

WS_KBD17

412

WS_KBD16N

403

WS_KBD15_C

394

WS_KBD14

385

WS_KBD13

376

WS_KBD12

367

WS_KBD11

358

WS_KBD10

349

WS_KBD9

3310

WS_KBD8

3211

WS_KBD7

3112

WS_KBD1

3013

WS_KBD2

2914

WS_KBD3

WS_KBD4
WS_KBD5
WS_KBD6

Z2_CLKIN
TP_P7_7

C5703

0.1UF

10%

6.3V
X5R
201

TPAD_5V_FET:NO

R5720

0

1 2

5%
1/16W
MF-LF

402

TPAD_5V_FET:YES

CRITICAL

Q5720

SIA413DJ

SC70-6L

S

4 7

G

TPAD_5V_FET:YES

3

C5723

0.01UF

1 2

10%
10V
X5R
201

IPD Flex Connector

R5708

0

BYPASS=U5701.49:50:11 mm

1

C5706

4.7UF

20%

6.3V

2

X5R
402

7

47

7

47

7

47

7

47

7

47

7

47

7

47

47

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

7

47

(PP3V3_S3_PSOC)

1

C5701

4.7UF

20%

6.3V

2

X5R
402

BYPASS=U5701.22:19:11 mm

BUTTON_DISABLE

47

Q5701

SSM6N37FEAPE

39 40

IN

SOT563

SMC_LID

5V TPAD FET

MOSFET

CHANNEL

RDS(ON)

LOADING

D

1

PP5V_S5RS4_CUMULUS

VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM

6

D

2

SG

1

SiA413

P-TYPE 12V

29 mOhm @4.5V

16 mA (EDP)

47

BOM GROUP
TPAD_5V_LDO:S4
TPAD_5V_LDO:S5

=PP3V3_S4_TPAD

8

47

=PP5V_S4_TPAD

8

FERR-120-OHM-1.5A

PP5V_S5RS4_CUMULUS

47

www.qdzbwx.com

TPAD Buttons Disable

PLACE THESE COMPONENTS CLOSE TO J5800
THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

THE TPAD BUTTONS WILL BE DISABLE
WHEN THE LID IS CLOSED

LID OPEN => SMC_LID_LC ~ 3.42V
LID CLOSE => SMC_LID_LC < 0.50V

PLACE_NEAR=J5700.18:3MM

FERR-120-OHM-1.5A

TPAD_5V:S4

1

C5700

0.1UF

10%

PLACE_NEAR=J5700.18:3MM

10V

2

X5R-CERM
0201

TPAD_5V:S5

PLACE_NEAR=J5700.18:3MM

L5707

1 2

0402-LF

TPAD_5V:S5

1

C5707

0.1UF

10%

PLACE_NEAR=J5700.18:3MM

10V

2

X5R-CERM
0201

8

47

7

47

7

47

7

47

1 2

5%

1/20W

MF

201

TPAD_5V:S4

NOSTUFF

1

C5708

0.1UF

10%

6.3V

2

X5R
201

L5700

1 2

0402-LF

47

=PP3V3_S4_TPAD

WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD

=PP3V3_S4_TPAD

8

47

WS_KBD15_C

47

WS_KBD15_C

Z
1
0

TPAD_5V_FET:YES,TPAD_5V:S5

CAP_COMP_H CAP_COMP_L

BOM OPTIONS

TPAD_5V_FET:NO,TPAD_5V:S5

=PP3V42_G3H_TPAD

8

1
0
1

PP3V3_TPAD_CONN

VOLTAGE=3.3V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM

PP5V_S4_CUMULUS

7

VOLTAGE=5V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.50MM

10

VDD

U5750

SLG4AP021

4

OE

(IPD)

1

IN_1

(IPD)

2

IN_2

(IPD)

3

IN_3

(IPD)

CAPS:EXT

1

R5730

10K

5%
1/20W
MF
201

2

CAPS:EXT

1

R5731

10K

5%
1/20W
MF
201

2

TQFN

GND

5

CAPS:EXT

1

R5732

10K

5%
1/20W
MF
201

2

CAPS:EXT

1

R5733

20K

5%
1/20W
MF
201

2

THRM

PAD

Caps Lock LED Drive

Q5736 Q5738

1
1
0

off

off

on

6 3

47

42

42

47

47

47

47

47

47

47

47

47

47

47

11

CAPS:EXT

1

R5734

20K

5%
1/20W
MF
201

2

CAP_VREF_L

CAP_VREF_H

CAPS:EXT

1

R5735

10K

5%
1/20W
MF
201

2

Z2_CLKIN

7

=I2C_TPAD_SCL

=I2C_TPAD_SDA

PSOC_SCLK

7

PSOC_MOSI

7

Z2_SCLK

7

PSOC_MISO

7

Z2_MISO

7

Z2_MOSI

7

PSOC_F_CS_L

7

Z2_CS_L

7

Z2_KEY_ACT_L

7

PICKB_L

7

Z2_HOST_INTN

7

9

OUT_1

8

OUT_2

7

OUT_3

off
off

6

on

OUT_ALL#

FF14-18C-R11DL

1

R5700

220K

5%

1/20W

MF

201

2

1

C5750

0.1UF

10%
16V

2

X7R-CERM
0402

WS_LEFT_SHIFT_KEY
WS_LEFT_OPTION_KEY
WS_CONTROL_KEY

Pull-up in U5010.

SMC_TPAD_RST_L

CAPS:EXT

R5740

1/20W

CAPS:EXT

V+

U5730

LM393ADGKR

MSOP

6
5

2
3

GND

4

LED Current

none

source

sink

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

8

7

1

CRITICAL

J5700

F-RT-SM

20

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18

19

7

39 40

OUT

1

10K

5%
MF

201

2

Keyboard Connector

518S0848

CAPS:INT

R5714

WS_KBD15_C

47

WS_KBD16N

47

SMC_ONOFF_L

C5710

0.1UF

PLACEMENT_NOTE=NEAR J5713

47

SMC Manual Reset & Isolation

47

Left shift, option & control keys combined with power button cause SMC RESET# assertion.

47

40

OUT

R5738

1 2

R5715

1 2

R5710

1 2

1

20%
10V

2

CERM

402

Keys ANDed with MSP power to isolate when MSP is not powered.

CAPS:EXT CAPS:EXT

1

10K

5%

1/20W

MF

201

2

CAP_COMP_H

CAPS:EXT
CRITICAL

SSM3K15AMFVAPE

CAP_COMP_L

Q5734

D

VESM

1

G S

SYNC_MASTER=D2_MLB_KEPLER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

=PP3V3_S4_TPAD

8

47

=PP3V42_G3H_TPAD

8

47

WS_KBD1

7

47

WS_KBD2

7

47

WS_KBD3

7

47

WS_KBD4

7

47

WS_KBD5

7

47

WS_KBD6

7

47

WS_KBD7

7

47

WS_KBD8

7

47

WS_KBD9

7

47

WS_KBD10

7

47

WS_KBD11

7

47

WS_KBD12

7

47

113

1%
1/16W
MF-LF

402

0

5%
1/16W
MF-LF

402

1K

5%
1/16W
MF-LF

402

No IPD on OE input pin PP3V3_S4 (symbol error).

R5736

10K

1/20W

WS_KBD13

7

47

WS_KBD14

7

47

WS_KBD15_CAP

7

47

WS_KBD16_NUM

7

WS_KBD17

7

47

WS_KBD18

7

47

WS_KBD19

7

47

WS_KBD20

7

47

WS_KBD21

7

47

WS_KBD22

7

47

WS_KBD23

7

47

WS_KBD_ONOFF_L

7

WS_LEFT_SHIFT_KBD

7

47

WS_LEFT_OPTION_KBD

7

47

WS_CONTROL_KBD

7

47

1

5%
MF

201

2

CAPS:EXT

R5737

CAPS:EXT

R5739

CAP_COMP_L_INV

3

2

KEYBOARD/TRACKPAD (1 OF 2)

Apple Inc.

R

FF14A-30C-R11DL-B-3H

1

S

2

G

D

6

CAP_SOURCE

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

1

113

1%

1/20W

MF

201

2

WS_KBD15_CAP

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

1

113

1%

1/20W

MF

201

2

CAP_SINK

MIN_LINE_WIDTH=0.2MM
MIN_NECK_WIDTH=0.1MM

3

D

G

1

S

2

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

32

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

31

F-RT-SM

J5713

CRITICAL

518S0752

CAPS:EXT

Q5736

NTZD3152P

SOT-563-HF

CAPS:EXT

Q5738

DMN3730UFB4

DFN1006H4-3

SYM_VER_1

SYNC_DATE=12/08/2011

<SCH_NUM>

<E4LABEL>

<BRANCH>

57 OF 132

47 OF 80

D

C

B

7

47

A

SIZE

D

www.vinafix.vn

8 7 6 5 4 3

=PP3V3_S0_TPAD

8

1

R5858

470K

5%
1/16W
MF-LF
402

2

SMC_SYS_KBDLED

39 48

OUT

D

1

R5859

4.7K

5%
1/16W
MF-LF
402

2

7

48

SMC_KBDLED_PRESENT_L

7

KBDLED_CATHODE2

7

48

PP_KBD_BOOST_VOUT

Keyboard Backlight Driver & Detection

To detect Keyboard backlight, SMC will

tristate and read SMC_SYS_KBDLED:

If LOW, keyboard backlight present

If HIGH, keyboard backlight not present

Keyboard Backlight Connector

516S0899

CRITICAL

J5815

AA07A-S010-VA1

F-ST-SM

12
11

1

2

34
56
78
9

10

13
14

KBDLED_CATHODE1
PP_KBD_BOOST_VOUT

J5815 PIN 5 IS GROUNDED

7

48

7

48

ON KEYBOARD BACKLIGHT FLEX

12

D

C

PART NUMBER

138S0811

QTY

2

=PP5V_S0_KBDLED

8

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X6S,0603

B

SMC_SYS_KBDLED

39 48

A

GND_KBDLED_AGND

48

XW5810

SM

1 2

R5851

0

1 2

5%
1/16W
MF-LF

402

REFERENCE DES

C5810,C5811

PPVIN_S0_KBDLED_L

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

OMIT_TABLE

C5810

4.7UF

10%
35V

X5R-CERM

0603

R5802

1 2

1/16W
MF-LF

402

I_LED= 804/RSET

NOSTUFF

1

C5854

33PF

5%
50V

2

CERM
402

CRITICAL

CRITICAL

OMIT_TABLE

1

1

2

C5811

4.7UF

10%
35V

2

X5R-CERM
0603

PPVIN_S0_KBDLED_C

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=5V

0

5%

R5850

100K

5%
1/16W
MF-LF

402

1

R5855

40.2K

1%
1/16W
MF-LF
402

2

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

BOM OPTION

1

C5812

0.1UF

10%
25V

2

X5R
402

GND_KBDLED_AGND

48

PVDC_KBDLED

1

2

GND_KBDLED_AGND

48

KBDLED_EN

SMC_SYS_KBDLED_FILTER

KBDLED_RSET

KBDLED_FSW
KBDLED_COMP

1

1

R5856

137K

1%
1/16W
MF-LF
402

2

FSW =1 MHZ
SEE SPEC FOR OTHERS

C5853

33PF

5%
50V

2

CERM
402

KBDLEDCOMP_RC

152S1701 COMBO

CRITICAL

PST041H-CDH46D14-SM

KBDLED_FPW

1

R5854

10K

5%
1/16W
MF-LF
402

2

1

C5855

0.0082UF

10%
25V

2

X7R
402

L5850

1 2

1

2

1

C5852

1UF

10%
25V

2

X5R
603-1

10UH-20%-1.4A-0.17OHM

1

R5810

0

5%
1/16W
MF-LF
402

2

KBDLED_SW1

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

SWITCH_NODE=TRUE

C5850

1UF

10%
25V
X5R
603-1

6

5

3

8

4

2

NOSTUFF

1

R5857

100K

5%
1/16W
MF-LF
402

2

1

C5851

0.01UF

10%
16V

2

X7R-CERM
0402

11

VDC

U5850

TQFN

EN

PWMI

RSET

FPW/DIRECTPWM

FSW

COMP

CRITICAL

PGND

AGND

1

10

7

VIN

LX

OVP

ISL97682

CH1

CH2

NC

THRM

PAD

17

371S0490

9

12

13

KBDLED_CATHODE1_R

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM

15

VOLTAGE=35V

14

NC

16

NC

XW5800

1 2

CRITICAL

D5850

SOD-323
A K

PMEG4010BEA

XW5850

KBDLED_CATHODE2_R

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V

SM

2

SM

1

1

R5870

237K

1%
1/16W
MF-LF
402

2

1

R5871

10K

1%
1/16W
MF-LF
402

2

KBDBKLT:ENG

1

C5860

1.0UF

10%
50V

2

X5R
0603 0402

1

C5861

1.0UF

10%
50V

2

X5R
0603

NOSTUFF

1

C5870

33PF

5%
50V

2

CERM
402

NOSTUFF

1

C5871

33PF

5%
50V

2

CERM
402

GND_KBDLED_AGND

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=30V

PP_KBDBOOST_XW

PART NUMBER

KBDLED_OVP

R5852

10.2

1 2

0.1%

KBDBKLT:ENG

1/16W

TF

402

R5853

10.2

1 2

0.1%

1/16W

TF

402

6 3

1

C5862

1.0UF

10%
50V

2

X5R
0603

116S0004

48

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=35V

1

C5863

1.0UF

10%
50V

2

X5R
0603

1

C5864

220PF

2

QTY

RES,MTL FILM,1/16W,0,5,0402,SMD,LF

2

KBDLED_CATHODE1

KBDLED_CATHODE2

PP_KBD_BOOST_VOUT

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

10%
50V
X7R-CERM

DESCRIPTION

7

7

VOLTAGE=30V

48

48

7

48

REFERENCE DES

R5852,R5853

SYNC_MASTER=D2_MLB_KEPLER

PAGE TITLE

CRITICAL

CRITICAL

KEYBOARD/TRACKPAD (2 OF 2)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTION

KBDBKLT:PROD

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

58 OF 132

SHEET

48 OF 80

124578

SYNC_DATE=12/08/2011

SIZE

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

=PP3V3_S3_SMS

8

D

BYPASS=U5920.14:13:8 mm

Desired orientation when placed on top-side (view top):

+Y

+Z (up)

+X

C5926

10UF

6.3V

39 40

OUT

7

Front of system

BYPASS=U5920.14:13:8 mm

SMS

20%

X5R
603

SMS_INT_L
TP_SMS_INT2

SMS

1

1

C5922

0.1UF

10%

6.3V

2

2

X5R
201

PLACEMENT_NOTE=See schematic for orientation.

SMS

R5924

1/20W

10K

NC
NC

1

5%

MF

201

2

SMS

14

VDD

2

NC

3

10

RESERVED

15

11

INT1CSSDA/SDI/SDO

9

INT2

VDD_IO

U5920

LIS331DLH

LGA

CRITICAL

GND

5

121316

1

SDO

SCL/SPC

338S0687

PLACE_SIDE=TOP

8

SMS_I2C_SEL

7

SMS_ADDR_SELECT

6

I2C_SMC_SMS_SDA_R

4

I2C_SMC_SMS_SCL_R

R5920

1/20W

SMS

10K

NOSTUFF

1

5%

MF

201

2

R5925

1/20W

SMS

R5921

1/20W

1

10K

10K

5%

MF

201

2

1

5%

MF

201

2

SMS

R5923

0

1 2

R5922

1 2

SMS_ADDR_SELECT=0 Addr: 0x30(Wr)/0x31(Rd)
SMS_ADDR_SELECT=1 Addr: 0x32(Wr)/0x33(Rd)

NOTE: SDA and SCL have internal pull-ups to VDD_IO.

1/20W

SMS

1/20W

5%

MF

201

0

5%

MF

201

=I2C_SMC_SMS_SDA

=I2C_SMC_SMS_SCL

42

BI

42

IN

C

Circle indicates pin 1 location when placed
in correct orientation

12

D

C

=PP3V3_S3_GYRO

8

GYRO

1

C5940

0.1UF

10%

6.3V

2

GYRO

1

R5944

10K

5%
1/20W
MF
201

2

CS PU = I2C

INT ARE PUSH-PULL

B

TP_IRQ_GYRO_INT2_L
TP_GYRO_SYNC

TP_IRQ_GYRO_INT1_L

PLLFILT_GYRO1

GYRO_CS

PLLFILT_GYRO

GYRO

1

C5942

0.47UF

10%

6.3V

2

CERM-X5R
402

GYRO

1

R5945

10K

5%
1/20W
MF
201

2

GYRO

1

C5945

0.01UF

10%
10V

2

X5R
201

GYRO

14

5
6
8

7

RES/VDD

AP3GDL8B

CS
DRDY/

INT2

DEN

INT1
PLLFILT

15

16

VDD_IO

VDD

U5940

LGA

SDA_SDI_SDO

CRITICAL

GND

13

1

SCL_SPC

SDO_SA0

RES0
RES1
RES2
RES3

X5R
201

338S0927 = 8KHZ

2

I2C_SMC_GYRO_SCL_R

3

I2C_SMC_GYRO_SDA_R

4

9
10
11
12

A

6 3

GYRO

1

C5941

0.1UF

10%

6.3V

2

X5R
201

GYRO

1

C5943

10UF

20%

6.3V

2

CERM-X5R
0402-1

GYRO

R5946

1 2

1/20W

GYRO

R5947

1 2

1/20W

0

5%

MF

201

0

5%

MF

201

GYRO

(WRITE: 0XD0 READ: 0XD1)

=I2C_SMC_GYRO_SCL

=I2C_SMC_GYRO_SDA

42

IN

B

42

BI

SIZE

A

D

SYNC_MASTER=J5_MLB

PAGE TITLE

DIGITAL ACCELEROMETER & GYRO

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

59 OF 132

SHEET

49 OF 80

124578

www.vinafix.vn

8 7 6 5 4 3

12

D

C

DUAL I/O MODE (MODE 0 & 3) SUPPORTED

=PP3V3_SUS_ROM

8

40 41 40 41

IN IN

40 41

IN

7

20 41

IN

NOTE: If HOLD* is asserted
ROM will ignore SPI cycles.

High Speed CLK Frequency - 50MHz for fast read dual I/O

1

R6101

3.3K

5%
1/20W
MF
201

2

SPI_MLB_CLK

SPI_MLB_CS_L
SPI_WP_L
SPIROM_USE_MLB

C6100

0.1UF

X5R-CERM

0201

1

10%
16V

2

6

1
3
7

SCK

SST25VF064C

CE*
WP*

RST*/HOLD*

VDD

U6100

64MBIT

WSON

OMIT_TABLE

VSS

CRITICAL

SI/SIO0

SO/SOI1

THRM_PAD

984

5

2

SPI_MLB_MOSI

SPI_MLB_MISO

40 41

OUT

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=J13_MLB

PAGE TITLE

SPI ROM

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=01/20/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

61 OF 132

SHEET

50 OF 80

124578

www.vinafix.vn

8 7 6 5 4 3

12

www.qdzbwx.com

AUDIO CODEC

L6201

FERR-22-OHM-1A-0.065-OHM

8

IN

=PP1V5_S0_AUDIO

1 2

0201

D

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

8

55

MERRY = LOW

FG = HIGH

55

55

7

7

SPKRCONN_L_ID

IN

SPKRCONN_R_ID

IN

1 2

GPIO3 = SPKR AMP SHDN CONTROL

R6252

0

5%
1/16W
MF-LF

402

R6253

0

1 2

5%
1/16W
MF-LF

402

1

R6250

10K

5%
1/16W
MF-LF
402

2

53

51 54

1

R6251

10K

5%
1/16W
MF-LF
402

2

OUT

55

8

IN

IN

51 54 55

AUD_GPIO_3

AUD_SENSE_A

=PP3V3_S0_AUDIO_DIG

51 52 54 55

PP4V5_AUDIO_ANALOG

IN

C6216

1UF

10%
10V
X5R
402-1

C

HDA_BIT_CLK

17 75

IN

HDA_SYNC

17 75

IN

HDA_SDIN0

17 75

IN

HDA_SDOUT

17 75

OUT

HDA_RST_L

17 75

IN

B

7

54

OUT

R6211

22

1 2

5%
1/16W
MF-LF

402

AUD_SPDIF_OUT_JACK

U6201 CONSUMES 40MA MAX. FROM 1.5V RAIL

1

2

7

55

1

C6226

0.1UF

10%

6.3V

2

X5R
201

R6220

33

1 2

5%
1/16W
MF-LF

402

1

C6211

0.1UF

10%

6.3V

2

X5R
201

CRITICAL

C6221

AUD_DMIC_SDA1

IN

15UF

1

2

1

2

C6210

4.7UF

20%
4V
X5R-1
402

R6210

2.67K

1%
1/20W
MF
201

AUD_SDI_R

75

1

R6254

0

5%
1/20W
MF
201

2

PP1V5_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V

1

20%

4V

2

X5R

0402

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CRITICAL

C6222

15UF

20%
4V
X5R
0402

AUD_SPDIF_IN

7

AUD_SPDIF_OUT

CRITICAL

1

C6220

15UF

20%
4V

2

X5R
0402

1

2

0805-LLP-1

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CS4206_FP
CS4206_FN

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CS4206_FLYP
CS4206_FLYC

1

2

CS4206_FLYN

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

GND_AUDIO_CODEC

51 52 54 55

1

C6219

10UF

20%
16V

2

TANT-POLY

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

SPKRCONN_L_ID_R

SPKRCONN_R_ID_R

CRITICAL

C6223

15UF

20%

4V

X5R

0402

VBIAS_DAC

APPLE P/N 353S2355

29

44
41

2

12

14
15

13

45
43
42

3

1

6

10

8
5

11

47
48

MIN_LINE_WIDTH=0.5MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=0V

24

9

VA_REF

VD

VBIAS_DAC

VHP_FILT+
VHP_FILT-

GPIO0/DMIC_SDA1
GPIO1/DMIC_SDA2
GPIO2
GPIO3

U6201

CS4206B

/SPDIF_OUT2

SENSE_A

FLYP
FLYC
FLYN

VL_HD

CRITICAL

VL_IF

BITCLK

SYNC

SDI
SDO

RESET*

SPDIF_IN
SPDIF_OUT

THRM_PAD

DGND

7

49

46

VA_HP

QFN

LINEOUT_L1+
LINEOUT_L1­LINEOUT_R1+
LINEOUT_R1-

LINEOUT_L2+
LINEOUT_L2­LINEOUT_R2+
LINEOUT_R2-

AGND

26

25

VA

HPOUT_L
HPOUT_R

HPREF

MICBIAS

VCOM

LINEIN_L+
LINEIN_C­LINEIN_R+

MICIN_L+
MICIN_L­MICIN_R+
MICIN_R-

VREF+_ADC

DMIC_SCL

C6218

0.1UF

X7R-CERM

1

10%
16V

2

0402

38
40

39

35
34
36
37

31
30
32
33

16

CS4206_VCOM

28

21

22

23

18
17
19
20

27

AUD_DMIC_CLK_R

4

C6224

1UF

TANT

0603-SM

1

C6217

10UF

20%
16V

2

TANT-POLY
0805-LLP-1

R6241

0

1 2

5%

1/20W

MF

201

MIN_NECK_WIDTH=0.1MMMIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.20MMMIN_LINE_WIDTH=0.30MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.1MM

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

CS4206_VREF_ADC

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

1

1

C6225

20%
16V

10UF

20%
16V

2

2

TANT-POLY
0805-LLP-1

NC

CRITICAL

C6214

0.1UF

X5R-CERM

0201

10%
16V

1

2

AUD_DMIC_CLK

CRITICAL

1

C6213

10UF

20%
10V

2

X5R-CERM
0402-1

NO_TEST=TRUE
NO_TEST=TRUE
NO_TEST=TRUE

PP5V_AUDIO_HPAMP

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

GND_AUDIO_CODEC

AUD_HP_PORT_L
AUD_HP_PORT_R

AUD_HP_PORT_REF

AUD_LO1_L_P
AUD_LO1_L_N
AUD_LO1_R_P
AUD_LO1_R_N

AUD_LO2_L_P
AUD_LO2_L_N
AUD_LO2_R_P
AUD_LO2_R_N

TP_AUD_CODEC_MICBIAS

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM

NC_AUD_LI_P_L
NC_AUD_LI_REF
NC_AUD_LI_P_R

AUD_MIC_INL_P
AUD_MIC_INL_N

55

OUT

51

51 54 55

IN

51 52 54 55

51 52 54 55

52 54

OUT

52 54

OUT

54

IN

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

53 78

OUT

7

NC
NC
NC

54 78

IN

54 78

IN

TP_AUD_MIC_INRP

TP_AUD_MIC_INRN

D

LFT SUBWOOFER AMP. SIG. SOURCE

RT. SUBWOOFER AMP. SIG. SOURCE

LFT. SPKR AMP. SIG. SOURCE

RT. SPKR AMP. SIG. SOURCE

C

EXT MIC CODEC INPUT

7

7

B

4.5V POWER SUPPLY FOR CODEC
APPLE P/N 353S2456

L6202

D1: PLACE XW6201 NEAR 5V SOURCE

XW6201

SM

=PP5V_S0_AUDIO

8

IN

A

1 2

8

51 54

PP5V_S0_AUDIO_XW

MIN_LINE_WIDTH=0.60MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=5V

=PP3V3_S0_AUDIO_DIG

IN

FERR-22-OHM-1A-0.065-OHM

1 2

0201

L6200

FERR-22-OHM-1A-0.065-OHM

1 2

0201

R6200

2.2K

1 2

5%

1/20W

MF

201

1

2

C6200

1UF

10%
10V
X5R
402

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V

PP5V_AUDIO_HPAMP

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=5V

4V5_REG_IN

4V5_REG_EN

51

1

C6201

1UF

2

U6200

TPS71745

6

IN

CRITICAL

4

EN

10%
10V
X5R
402

GND

SON

2

OUT

NR/FB

XW6200

1 2

1

3

4V5_NR

5

NC

SM

CRITICAL

C6202

0.1UF

X5R-CERM

0201

PLACE XW6200 BENEATH U6200, BETWEEN PINS 2 & 5

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

1

10%
16V

2

CRITICAL

1

C6203

1.0UF

20%
10V

2

X5R-CERM
0201-1

GND_AUDIO_CODEC

OUT

51 52 54 55

51 54 55

6 3

NOTES ON CODEC I/O

DIFF FSINPUT= 2.45VRMS
SE FSINPUT= 1.22VRMS
DAC1 FSOUTPUT= 1.34VRMS
DAC2/3 FSOUTPUTDIFF= 2.67VRMS
DAC2/3 FSOUTPUTSE= 1.34VRMS

SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012

PAGE TITLE

AUDIO: CODEC/REGULATOR

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

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<BRANCH>

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8 7 6 5 4 3

12

D

C

D

C

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

AUD_HP_PORT_L

51 54

51 54

IN

B

AUD_HP_ZOBEL_L

NC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

GND_AUDIO_CODEC

51 54 55

IN

AUD_HP_ZOBEL_R

NC

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_R

51 54

51 54

IN

CRITICAL

C6300

0.1UF

R6300

R6310

1/20W

CRITICAL

C6310

0.1UF

6.3V

1

10%

6.3V
2

X5R
201

1

39

5%

1/20W

MF

201

2

1

39

5%
MF

201

2

1

10%

2

X5R
201

1

R6302

10K

1%
1/20W
MF
201

2

1

R6312

10K

1%
1/20W
MF
201

2

A

6 3

OUT

B

OUT

SIZE

A

D

PAGE TITLE

AUDIO: HEADPHONE FILTER

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=06/06/2012SYNC_MASTER=D1_AUDIO

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

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8 7 6 5 4 3

PP5V_S0_AUDIO_AMP_L

9

53

CRITICAL

CRITICAL

L6610

FERR-1000-OHM

1 2

51 78

AUD_LO2_L_N

IN

4X MONO SPEAKER AMPLIFIERS (MAX98300 & SSM2375)

APN: 353S2888 & 353S2958

D

GAIN = +3 DB
1ST ORDER FC (L&R) = NOM 569 HZ
1ST ORDER FC (SUB) = NOM 9 HZ

51 78

IN

AUD_LO2_L_P

AUD_SPKRAMP_SHUTDOWN_L

53

51 78

IN

C

51 78

PP5V_S0_AUDIO_AMP_R

9

53

1

2

CRITICAL

C6632

47UF

20%

6.3V
POLY-TANT

C2

CRITICAL

VDD

U6630

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

OUT+
OUT-

GAIN

EDGE

C1

CRITICAL

1

CRITICAL

L6630

FERR-1000-OHM

51 78

51 78

IN

IN

AUD_LO1_R_P

AUD_LO1_R_N

1 2

0402

CRITICAL

L6631

FERR-1000-OHM

1 2

78

0402

AUD_SPKRAMP_RSUBIN_P

78

AUD_SPKRAMP_RSUBIN_N

CRITICAL

CRITICAL

C6634

0.22UF

1 2

C6633

0.22UF

1 2

10%
16V

CERM

402

RSUBIN_N

10%
16V

CERM

402

RSUBIN_P

NO_TEST=TRUE

NO_TEST=TRUE

AUD_SPKRAMP_SHUTDOWN_L

53

C6635

47UF

20%

6.3V

2

POLY-TANT
0805-LLP 0805-LLP

AUD_LO2_R_N

IN

C3

B3

A3

TP_SWR_GAIN

B2

78

0402

L6611

FERR-1000-OHM

1 2

78

0402

CRITICAL

AUD_LO2_R_P

FERR-1000-OHM

1 2

CRITICAL

1 2

L6621

0402

PLACE_NEAR=U6630.C2:5.1MM

1

C6631

0.1UF

10%
16V

2

X7R-CERM
0402

AUD_SPKRAMP_LIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LIN_N

51

CRITICAL

L6620

FERR-1000-OHM

0402

78

NO_TEST=TRUE

AUD_GPIO_3

IN

78

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

CRITICAL

C6614

0.01UF

1 2

10%
50V

X7R-CERM

0402

CRITICAL

1 2

53

CRITICAL

C6624

0.01UF

1 2

10%
50V

X7R-CERM

0402

C6613

0.01UF

1 2

10%
50V

X7R-CERM

0402

78

L6601

FERR-1000-OHM

0402

CRITICAL

PP5V_S0_AUDIO_AMP_R

9

CRITICAL

C6623

0.01UF

1 2

10%
50V

X7R-CERM

0402

AUD_SPKRAMP_SHUTDOWN_L

53

SPKRCONN_SR_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SR_OUT_N

MIN_LINE_WIDTH=0.40 MM

MIN_NECK_WIDTH=0.10 MM

78

78

NO_TEST=TRUE

NO_TEST=TRUE

SPKRAMP_LIN_P
SPKRAMP_LIN_N

NO_TEST=TRUE

78

SPKRAMP_RIN_N

NOSTUFF

C6612

47UF

6.3V

TANT-POLY

CASE-A4

R6600

100K

1/16W
MF-LF

402

C6622

POLY-TANT

0805-LLP

CRITICAL

NO_TEST=TRUE

SPKRAMP_RIN_P

R6601

100K

5%

1/20W

MF

201

1

20%

2

A1

PVDD

U6610

MAX98300

WLP

A3

IN+

B3

IN-

C2

SHDN*

B2

NC

1

5%

2

1

47UF

20%

6.3V

2

1

2

PGND

PVDD

U6620

MAX98300

A3

IN+

B3

IN-

C2

SHDN*

B2

NC

PGND

B1

OUT+

C1

OUT-

C3

GAIN

A2

A1

WLP

OUT+
OUT-

GAIN

A2

PLACE_NEAR=U6610.A1:5.1MM

1

C6611

0.1UF

10%
16V

2

X7R-CERM
0402

CKPLUS_WAIVE=ndifpr_badterm
CKPLUS_WAIVE=pdifpr_badterm

SPKR_L_GAIN

1

R6610

100K

5%
1/16W
MF-LF

402

2

PLACE_NEAR=U6620.A1:5.1MM

1

C6621

0.1UF

10%
16V

2

X7R-CERM
0402

B1

C1

C3

SPKR_R_GAIN

1

R6620

100K

5%
1/16W
MF-LF

402

2

SPKRCONN_L_OUT_N

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

7

55 78

OUT

7

55 78

OUT

SPKRCONN_R_OUT_N

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

B

12

SPKRCONN_L_OUT_P

7

55 78

OUT

OUT

7

55 78

OUT

7

55 78

OUT

D

7

55 78

C

B

9

53

CRITICAL

L6640

FERR-1000-OHM

51 78

51 78

AUD_LO1_L_N

IN

AUD_LO1_L_P

IN

1 2

0402

CRITICAL

L6641

FERR-1000-OHM

1 2

0402

78

78

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_P

NO_TEST=TRUE

AUD_SPKRAMP_LSUBIN_N

CRITICAL

CRITICAL

C6643

0.22UF

1 2

C6644

0.22UF

1 2

10%
16V
CERM
402

NO_TEST=TRUE

LSUBIN_P

10%
16V

CERM

402

NO_TEST=TRUE
LSUBIN_N

AUD_SPKRAMP_SHUTDOWN_L

53

A

6 3

PP5V_S0_AUDIO_AMP_L

CRITICAL

1

C6645

47UF

20%

6.3V

2

POLY-TANT
0805-LLP

1

2

CRITICAL

C6642

47UF

20%

6.3V
POLY-TANT
0805-LLP

PLACE_NEAR=U6640.C2:5.1MM

1

C6641

0.1UF

10%
16V

C2

CRITICAL

VDD

U6640

SSM2375

WLCSP

B1

IN+

A1

IN-

A2

SD*

GND

OUT+
OUT-

GAIN

EDGE

C1

CKPLUS_WAIVE=ndifpr_badterm

C3

CKPLUS_WAIVE=pdifpr_badterm

B3

A3

TP_SWL_GAIN

B2

2

X7R-CERM
0402

SPKRCONN_SL_OUT_N

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SPKRCONN_SL_OUT_P

7

55 78

OUT

7

55 78

MIN_LINE_WIDTH=0.40 MM
MIN_NECK_WIDTH=0.10 MM

SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

OUT

AUDIO: SPEAKER AMP

Apple Inc.

R

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<SCH_NUM>

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I2C PULLUPS ON SOUTHBRIDGE PAGE

=I2C_MIKEY_SCL

42

IN

=I2C_MIKEY_SDA

42

BI

D

AUD_I2C_INT_L

19

OUT

AUD_IPHS_SWITCH_EN

25

IN

AUD_PORTA_DET_L

55

IN

C

8 7 6 5 4 3

PP4V5_AUDIO_ANALOG

51 55

51 54

R6757

1 2

R6758

GND_AUDIO_CODEC

51 52 54 55

51 78

OUT

51 78

OUT

1/20W

33

1 2

5%

1/20W

MF

201

NOSTUFF

R6761

47K

1 2

5%

1/20W

MF

201

AUD_MIC_INL_P

AUD_MIC_INL_N

=PP3V3_S0_AUDIO_DIG

8

33

5%
MF

201

54

54

HS_HDET

CRITICAL

C6752

CRITICAL

C6753

1

C6755

R6762

10K

1/20W

1

5%
MF

201

2

4.7UF

20%

6.3V

2

X5R-CERM1
402

AUDIO_SCL
AUDIO_SDA

1

R6755

100K

5%

1/20W

MF

201

2

0.1UF

1 2

10%

6.3V
X5R
201

0.1UF

1 2

10%

6.3V
X5R
201

HS_MIC_HI_RC

78

1

R6756

100K

1/20W

201

HS_MIC_LO_RC

78

R/C6750 FILTER TO ADDRESS OUT-OF-BAND
NOISE ISSUE SEEN ON EARLY HEADSETS
(SEE RADAR # 6210118)

1

5%
MF

2

2

CRITICAL

C3

B3

D3

A3

A1

B2

CRITICAL

C6750

6800PF

10%
10V
X5R-X7R-CERM
0201

AVDD

U6751

CD3282A1

WCSP

SCL

SDA

INT*

ENABLE

HDET

CS

DGND

C2

NO_XNET_CONNECTION=TRUE

PORT B LEFT(HEADSET MIC)

HP=80HZ, LP=10.63KHZ

MIKEY 1A
APN:353S2640
MIKEY ADDRESS: WRITE=72H, READ=73H

A2

C1

MICBIAS

DETECT

BYPASS

R6750

2.2K

1 2

R6759

1 2

1/20W

HS_MIC_BIAS

B1

HS_SW_DET

D1

HS_RX_BP

AGND

D2

5%

1/20W

MF

201

0

5%
MF

201

R6760

1/20W

NOSTUFF

GND_AUDIO_CODEC

51 52 54 55

NO_XNET_CONNECTION=TRUE

1

C6756

0.01UF

10%
10V

2

X5R-CERM
0201

1

47K

5%
MF

201

2

=PP3V42_G3H_AUDIO

8

1

R6754

1K

5%

1/20W

MF

201

2

CRITICAL

1

C6758

27PF

5%
25V

2

NP0-C0G
0201

R6751

1K

12

5%

1/20W

MF

201

GND_AUDIO_CODEC

51 52 54
55

AUD_HP_PORT_REF

51

L6754

FERR-22-OHM-1A-0.065-OHM

1 2

0201

NO_XNET_CONNECTION=TRUE

1

2

R6752

2.2K

1 2

1%

1/20W

MF

201

C6751

10UF

20%
10V
X5R-CERM
0402-1

1

C6791

10UF

20%
10V

2

X5R-CERM
0402-1

XW6751

SM

1 2

PLACE_NEAR=U6750.D1:5.1MM

NO_XNET_CONNECTION=TRUE

GND_AUDIO_CODEC

51 52 54 55

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.15MM
VOLTAGE=3.42V

PP3V42_GH3_AUDIO_LC

1

C6790

1UF

10%
10V

2

X5R
402

GND_AUDIO_CODEC

51 52 54 55

R6753

2.2K

1 2

1%

1/20W

MF

201

HS_MIC_HI

78

78

HS_MIC_LO

CHS_CLAMPI

CHS_CLAMPO

54

IN

54

BI

54

54

AUDIO_SCL
AUDIO_SDA

IN
IN

NO_XNET_CONNECTION=TRUE

AUDIO JACK: HP CONNECTOR WITH MIKEY & CHS

1

C6754

0.1UF

10%
16V

2

X5R-CERM
0201

A1

VDD

U6750

TS3A8235YFP

WCSP

CRITICAL

D4

RAMPI

D3

RAMPO

C4

CLAMPI

B4

CLAMPO

D2 B1

MIC

D1

REF

A3

SCL

A4

SDA

A2

ADDR

C2B2B3

US_HS_GND
CH_HS_GND

GND1

GND2

GND

C3

MIC1
MIC2

C1

51

CH_HS_MIC

FERR-33-OHM-0.8A-0.09-OHM

US_HS_MIC

54

OUT

54

OUT

=PP3V3_S0_AUDIO_DIG

8

51 54

7

OUT

AUD_TIPDET_INV

55

OUT

51 52

IN

1 2

US_HS_GND

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM

CH_HS_GND

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.06MM

AUD_SPDIF_OUT_JACK

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.1MM

FERR-33-OHM-0.8A-0.09-OHM

CRITICAL

L6701

0201

CRITICAL

L6700

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6702

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6704

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6703

1 2

0201

AUD_CONN_MIC

7

AUD_CONN_SLEEVE_XW

7

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

AUD_CONN_MIC_XW

7

MIN_LINE_WIDTH=0.4MM
MIN_NECK_WIDTH=0.2MM

AUD_CONN_HP_LEFT

7

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM

AUD_CONN_SLEEVE

7

APN:510S0009

CRITICAL

J6701

51138-0274

F-ST-SM

22
21

1

2
3 4
5 6
7 8
9

10

11 12
13 14
15 16
17 18

20

19

23
24

12

D

C

CRITICAL

L6705

B

51 52

IN

AUD_HP_PORT_R

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.1MM

I2C ADDRESSES

MIKEY U6751 READ 0111 0011 0X73
MIKEY U6751 WRITE 0111 0010 0X72
CHS U6750 READ 0111 0111 0X77
CHS U6750 WRITE 0111 0110 0X76

55

OUT

AUD_TYPEDET

A

6 3

120-OHM-25%-1.3A

1 2

0402

CRITICAL

L6706

FERR-470-OHM

1 2

0201

AUD_CONN_HP_RIGHT

7

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.1MM

AUD_CONN_TYPEDET

7

SYNC_MASTER=D1_AUDIO SYNC_DATE=06/06/2012

PAGE TITLE

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

AUDIO: JACK

Apple Inc.

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

67 OF 132

SHEET

54 OF 80

124578

SIZE

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

CODEC OUTPUT SIGNAL PATHS

FUNCTION

HP/LINE OUT

TWEETERS

SUB

SPDIF OUT

CODEC INPUT SIGNAL PATHS

D

FUNCTION

DMIC 1

DMIC2

SPDIF IN

HEADSET MIC

SYSTEM INT AND GPIO LINES

FUNCTION

MIKEY ENABLE

MIKEY INTERRUPT

PERIPHERAL DETECT

VOLUME

0X02 (2)

0X04 (4)

0X03 (3)

N/A

CONVERTER

0X02 (2)

0X04 (4)

0X03 (03)

0X08 (8)

CONVERTER

0X06 (6)

0X05 (5)

0X07 (7)

0X06 (6)

INT

PIRQ H

PIRQ F

C

55

51 54 55

B

=PP3V3_S0_AUDIO

8

51 55

1

R6866

475K

1%
1/20W
MF
201

2

R6892

IN

AUD_TIPDET_INV

54

A

NOM R6892-C6860 FC = 106Hz
SSM6N15FE Vth = 0.8V to 1.5V
SSM6N15FE IGSS = +/-1uA
FLEX-SIDE RPULLDOWN = 100k (TB 49.9k in REV 3)

1.5K

1 2

1%
1/16W
MF-LF

402

AUD_TIPDET_INV_R

1

C6860

1UF

10%

2

APN:376S0613

SSM6N15AFE

25V
402X5R

PIN COMPLEX

0X09 (9,A)

0X0B (11)

0X0A (10)

0X10 (16)

PIN COMPLEX

0X0E (D,E)

0X12 (12,C)

0X0F (15)

0X0D (13,V22,B,LEFT)

GPIO

SATA4GP/GPIO 16

GPIO 5

GPIO 3

51 55

OUT

IN

GND_AUDIO_CODEC

51 52 54 55

PP4V5_AUDIO_ANALOG

1

R6865

47K

5%
1/20W
MF
201

2

AUD_TIPDET_FET1

Q6803

SOT563

6

D

2

SG

1

MUTE CONTROL

N/A

GPIO_3

GPIO_3

N/A

VREF

3V3 N/A

3V3

N/A

MIKEY

PORT B DETECT(SPDIF DELEGATE)

AUD_SENSE_A

1

R6896

20.0K

1%
1/16W
MF-LF
402

2

AUD_PORTA_DET_L

6

Q6897

SSM6N15AFE

SOT563

D

2

SG

1

AUD_OUTJACK_INSERT_L

R6802

R6803

100K

12

5%

1/20W

MF

201

FERR-33-OHM-0.8A-0.09-OHM

AUD_TYPEDET_OD_INV

R6867

1 2

1/16W
MF-LF

402

CRITICAL

L6801

1 2

0201

0

5%

AUD_TIPDET_FET2

51 52 54 55

DET ASSIGNMENT

0X09 (B)

N/A

N/A

0X0C (A)

DET ASSIGNMENT

0X0C (12,C)

N/A

MIKEY

PORT A DETECT (HEADPHONES)

54

Q6897

SSM6N15AFE

SOT563

5

100K

12

5%

1/20W

MF

201

6

D

SOT563

N-CHN

S

1

G

Q6800

DMC2400UV

AUD_IP_PERIPHERAL_DET

EXTRACTION NOTIFICATION

AUD_OUTJACK_INSERT_L

3

25V
402X5R

D

5

SG

4

Q6803

SSM6N15AFE

SOT563

1

C6891

1UF

10%

2

GND_AUDIO_CODEC

=PP3V3_S0_AUDIO

51 55

8

51

1

R6895

39.2K

1%
1/16W
MF-LF
402

2

AUD_PORTB_DET_L

3

D

SG

4

AUD_TYPEDET_OD

3

D

G

P-CHN

SOT563

S

Q6800

DMC2400UV

4

2

AUD_TYPEDET_OD

OUT

AUD_DMIC_SDA1

7

OUT

AUD_DMIC_CLK

51

OUT

NC

OUT

1

R6801

150K

1%
1/20W
MF
201

2

5

PP4V5_AUDIO_ANALOG

GND_AUDIO_CODEC

19

OUT

51 55

55

PP4V5_AUDIO_ANALOG

AUD_TYPEDET

1

C6800

55

IN

55

0.1UF

PLACE_NEAR=Q6800.4:5.1MM

10%

6.3V
2

X5R
201

=PP5V_S4_AUDIO

8

55

Alternate Parts

PART NUMBER

MIN_LINE_WIDTH=0.40MM

CON_DMIC_PWR

CON_DMIC_CLK

7

SPEAKERID

R6810

100K

1/16W
MF-LF

402

R6812

100K

1/16W
MF-LF

402

SPEAKERID

MIN_NECK_WIDTH=0.15MM

VOLTAGE=3.3V

1

1%

2

1

1%

2

FF14A-6C-R11DL-B-3H

NC

NC

SPEAKERID

1

R6811

100K

1%
1/16W
MF-LF
402

2

SPKRCONN_R_ID

1

R6813

100K

1%
1/16W
MF-LF
402

2

SPEAKERID

8

55

MCP6514_POS

R6885

7

0

1 2

5%
1/16W
MF-LF

402

R6884

0

1 2

CON_DMIC_SDA1

7

5%
1/16W
MF-LF

402

R6883

0

1 2

5%
1/16W
MF-LF

402

=PP5V_S4_AUDIO

8

55

SPKRCONN_L_ID

7

IN IN

54

IN

51 54 55

51 52 54 55

MCP6514_NEG

SPEAKERID

1

R6814

274K

1%
1/16W
MF-LF

402

2

SPEAKERID

R6815

90.9K

1%
1/16W
MF-LF

402

ALTERNATE FOR
PART NUMBER

353S1286353S3452
376S1081376S0975

1

2

1

2

BOM OPTION

SPEAKERID

C6811

4.7UF

20%
10V
X5R-CERM
0402

REF DES

U6800
Q6800

2-MIC CONNECTOR

CRITICAL

J6801

F-RT-SM

7

1
2
3
4
5
6

8

7

51 55

SPEAKERID

R6816

100K

1 2

1%
1/16W
MF-LF

402

=PP5V_S4_AUDIO

SPEAKERID
CRITICAL

U6800

5

3

4

COMMENTS:

MAXIM ALT TO MICROCHIP
TOSHIBA ALT TO DIODES

2

SPEAKERID

R6817

45.3K

1 2

1%
1/16W
MF-LF

402

MCP6541T

SC70-5

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

SPEAKERID

1

C6810

0.1UF

10%

6.3V

2

X5R
201

1

MCP6514_OUT

SPKRCONN_L_OUT_P

7

53 78

IN

SPKRCONN_L_OUT_N

7

53 78

IN

SPKRCONN_L_ID

7

51 55

OUT

SPKRCONN_SL_OUT_P

7

53 78

IN

SPKRCONN_SL_OUT_N

7

53 78

IN

SPKRCONN_R_OUT_P

7

53 78

IN

SPKRCONN_R_OUT_N

7

53 78

IN

SPKRCONN_R_ID

7

51 55

OUT

SPKRCONN_SR_OUT_P

7

53 78

IN

SPKRCONN_SR_OUT_N

7

53 78

IN

SPEAKERID

L6802

FERR-1000-OHM

1 2

AUDIO CONNECTOR DETECT STATES

AUD_J1_TYPEDET_R 1 1 0

AUD_J1_TIPDET_R 0 1 1

AUD_OUTJACK_INSERT_L 1 0 0

AUD_SENSE_A 1 20K/2.67K RDIV 39.2K/2.67K RDIV

0402

SPEAKER CONNECTOR

SPKR_MATCH_DRV_R

NOTHING SPDIF HEADPHONE

PAGE TITLE

AUDIO: JACK TRANSLATORS

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

HP=80HZ

APN: 518S0627

PORT C DETECT(SPEAKER MISMATCH)

51 55

NC

SPEAKERID

R6820

33

1 2

1/16W
MF-LF

5%

402

SPKR_MATCH_DRV

51 52 54 55

CRITICAL

J6802

78171-6006

M-RT-SM

7

1
2
3
4
5
6

8

CRITICAL

J6803

78171-6006

M-RT-SM

7

1
2
3
4
5
6

8

AUD_SENSE_A

OUT

SPEAKERID

R6894

AUD_PORTC_DET_L

SPEAKERID

Q6896

SSM6N15AFE

SOT563

2

GND_AUDIO_CODEC

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

68 OF 132

SHEET

55 OF 80

124578

10K

1/16W
MF-LF

SYNC_DATE=06/06/2012SYNC_MASTER=D1_AUDIO

402

D

C

1

1%

2

6

D

B

SG

1

A

SIZE

D

www.vinafix.vn

D

C

CRITICAL

J6900

53780-8608

F-RT-SM

10

1
2
3
4
5
6
7
8

9

518S0543

8 7 6 5 4 3

MagSafe DC Power Jack

PP18V5_DCIN_FUSE

7

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

NC

PLACE COMPONENTS NEAR BATTERY CONNECTOR AREA

VOLTAGE=18.5V

ADAPTER_SENSE

7

NO STUFF

1

C6905

0.1UF

10%
50V

2

X7R
603-1

1-Wire OverVoltage Protection

The chassis ground will otherwise float and can

send transients onto ADAPTER_SENSE when AC is

connected.

C6900

0.1UF

CERM

20%
10V

402

CRITICAL

F6905

6AMP-32V-0.0095OHM

1 2

0603

SMC_BC_ACOK_VCC

1

1

2

VCC

U6900

MAX9940

SC70-5

5

EXT INT

CRITICAL

NC GND

2

3

NC

PPVBAT_G3H_CONN

CRITICAL

U6901

TC7SZ08FEAPE

SOT665

4

=PP3V42_G3H_ONEWIREPROT

1

C6908

2

5

2

Y

5%
1/16W
MF-LF
402

A

1

B

3

4

1

R6929

2.0K

2

SYS_ONEWIRE

DCIN_ISOL_BLEEDER_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

7

57

0.1UF

20%

PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

10V
CERM
402

SMC_BC_ACOK

=PP18V5_DCIN_ISOL

8

39

BI

Q6930

2N7002

SOT23-HF1

1

2

3

D

S

2

8

39 40

IN

BLEEDER

CRITICAL

D6920

SBR0330CW

SOT-323
1

2

BLEEDER

R6930

1K

5%
1/16W
MF-LF
402

BLEEDER

1

G

DCIN_ISOL_BLEEDER_NGATE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

www.qdzbwx.com

3

DCIN_ISOL_BLEEDER_PSRC

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.20MM

1

C6920

0.1UF

10%

BLEEDER

50V

2

X7R
603-1

2

BLEEDER

S

1

G

D

3

BLEEDER

1

R6921

10K

5%
1/16W
MF-LF
402

2

Q6920

AO3407A

SOT23

Q6910

SI5419DU

POWERPAK

5A

D

1

DCIN_ISOL_GATE_R

S

5

G

C6912

4

0.047UF

0402

6.8V Zener

=PP18V5_DCIN_CONN

1

10%
25V

2

X5R

R6911

10K

1 2

1/20W

201

1%
MF

8

1

R6912

68K

1%
1/20W
MF
201

2

1

2

Input impedance of 68K meets
sparkitecture requirements
for both MPM4 and MPM5.

R6910

When input voltage is 2V the FET will be off

100K

blocking the leakage path and 22.1K can be

5%
1/20W
MF

properly detected.

201

When input voltage is at 16V+, FET will
conduct and power charger and 3.42V reg

DCIN_ISOL_GATE

K

D6910

GDZT2R6.8

GDZ-0201

A

12

D

C

7

C6950

0.1UF

10%
25V
X5R
402

1

2

C6960

1UF

603-1

10%
25V
X5R

1

2

B

A

SYSDET_3_4

OMIT

998-4777

CRITICAL

J6950

INTERPOSER-D1-TOP

COMBO-SM

A1

A1
A2
A3
A4
A6
A7
A8
A9
A10

B1
B2
B3
B4
B6
B7
B8
B9
B10

C1
C2
C3
C4
C6
C7
C8
C9
C10

D1
D2
D3
D7
D8
D9
D10

E2
E3
E8
E9

E10

F2
F3
F8
F9

F10

G1
G2
G3
G7
G8

G10

H1
H2
H3
H4
H6
H7

J1
J2
J3
J4
J7
J6

STIFF

TALL

SHRT

A10

B10

C10

D10

A2
A3
A4
A6
A7
A8
A9

B1
B2
B3
B4
B6
B7
B8
B9

C1
C2
C3
C4
C6
C7
C8
C9

D1
D2
D3
D7
D8
D9

E2
E3
E8
E9
E10

F2
F3
F8
F9
F10

G1
G2
G3
G7
G8
G10

H1
H2
H3
H4
H6
H7

J1
J2
J3
J4
J7
J6

63

64

65

=PPBUS_G3H

8

57

SH6950

4.0OD2.7ID-1.8H

2

1

R6920

47

1 2

1%

1/3W

MF

805

R6905

10

1 2

5%

1/8W

MF-LF

805

=SMBUS_BATT_SCL

PP18V5_DCIN_CONN_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

PPBUS_G3H_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=18.5V

42

BI

CRITICAL

D6905

SBR0330CW

SOT-323
1

2

3

PPVIN_G3H_P3V42G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

PART NUMBER

138S0811

OMIT_TABLE

C6992

4.7UF

10%
35V

X5R-CERM

0603

1

2

QTY

3

OMIT_TABLE

C6991

4.7UF

10%
35V

X5R-CERM

0603

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X6S,0603

OMIT_TABLE

C6990

4.7UF

X5R-CERM

0603

10%
35V

1

2

1

2

NC

CRITICAL

RCLAMP2402B

3

=SMBUS_BATT_SDA

D6950

SC-75

1

2

3

42

BI

Pin 63 (SH0962) is Neoconix stiffener, 860-1533
Pin 64 (SH0961) is Neoconix tall locator pin. 860-1530
Pin 65 (SH0960) is Neoconix short clocking pin. 860-1529

6 3

REFERENCE DES

C6990,C6991,C6992

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

6

3

BOOST

VIN

U6990

LT3470AED

DFN

8 4

SHDN*

CRITICAL

7

NC

GND

SW

BIAS

1

FB

THRM

PAD

5

9

P3V42G3H_BOOST

DIDT=TRUE

NO_TEST=TRUE

P3V42G3H_SW

MIN_LINE_WIDTH=0.5 mm

2

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

P3V42G3H_FB

CRITICAL

CRITICAL

1

C6994

0.22UF

10%
10V

2

CERM

10UH-30%-0.85A-460MOHM

402

1

2

Vout = 1.25V * (1 + Ra / Rb)

SYNC_MASTER=MASTER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

BOM OPTION

CRITICAL

L6995

1 2

C6995

22PF

5%
50V
CERM
201

=PP3V42_G3H_REG

1

1%
MF

2

1

1%
MF

2

Vout = 3.425V

100MA MAX OUTPUT

(Switcher limit)

CRITICAL

1

C6999

22UF

20%

6.3V

2

X5R
0603

2520

R6995

R6996

348K

1/20W

201

200K

1/20W

201

<Ra>

<Rb>

DC-In & Battery Connectors

Apple Inc.

R

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

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<BRANCH>

PAGE

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SHEET

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8

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A

SIZE

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8 7 6 5 4 3

12

PPDCIN_G3H_DRAINS

MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=18.5V

Inrush Limiter

FROM ADAPTER

=PPDCIN_S5_CHGR

8

D

1

2

=PPDCIN_S5_CHGR_ISOL

8

CRITICAL

D7005

SBR0330CW

SOT-323
1

ACIN pin threshold is 3.2V, +/- 50mV
Divider sets ACIN threshold at 13.55V
Input impedance of ~90K meets

sparkitecture requirements

=PP3V42_G3H_CHGR

66

8

C

1

2

R7012

1/16W
MF-LF

R7010

68.1K

1%
1/16W
MF-LF
402

402

1

1K

1%

2

SMC_RESET_L

IN

C7002

1UF

10%
10V
X5R
402

1

2

GND_CHGR_AGND

R7000

0

1 2

5%

42

1/16W
MF-LF

42

402

66

57

IN
BI
IN

Float CELL for 1S

1

R7011

21.5K

1%
1/16W
MF-LF
402

2

B

1

R7015

100K

1%
1/16W
MF-LF
402

2

CHGR_VCOMP_R

1

R7042

0

5%
1/16W
MF-LF
402

2

CHGR_VNEG_R

1

C7016

470PF

10%
50V

2

CERM
0402

CHGR_ICOMP_RC

1

C7042

0.068UF

10%
10V

2

X5R-CERM
0402

1

C7015

330PF

5%
50V

2

COG
402

R7016

3.01K

1/16W
MF-LF

402

77

77

1

1%

2

2

30mA max load

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

NO STUFF

1

R7002

100K

5%
1/16W
MF-LF
402

2

CHGR_RST_L
=SMBUS_CHGR_SCL
=SMBUS_CHGR_SDA
CHGR_VFRQ
CHGR_CELL

CHGR_ACIN
CHGR_ICOMP

CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P
CHGR_CSO_N

1

C7050

1UF

10%
16V

2

X5R
402

C7011

0.01UF

X7R-CERM

C7085

0.1UF

10%
25V
X5R
402

R7086

10%

0402

1

R7085

470K

1/16W
MF-LF
402

2

332K

1%
1/16W
MF-LF

402

3

CHGR_DCIN_D_R

57

1

2

1%

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

1

2

R7001

4.7

1 2

5%
1/16W
MF-LF

402

19

VDD

12

CRITICAL

VHST

13

SMB_RST_N

11

SCL

U7000

10

SDA

4

VFRQ

6

CELL

3

ACIN

5

ICOMP

7

VCOMP

8

VNEG

18

CSOP

17

CSON

(AGND)

29

1

C7000

1UF

10%
10V16V

2

X5R
402-1

Q7080

IRF9395TRPBF

DIRECTFET-MC

(CHGR_AGATE)

R7005

20

1 2

5%
1/16W
MF-LF

402

PP5V1_CHGR_VDDP

57

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

20

VDDP

DCIN

SGATE
AGATE

TQFN

CSIP
CSIN

BOOT

UGATE

ISL6259

PHASE

LGATE

BGATE

AMON

20V/V

BMON

36V/V

(OD)

ACOK

THRM_PAD

PGND

353S2929

22

XW7000

SM

1 2

PLACE_NEAR=U7000.29:1mm
PLACE_NEAR=U7000.22:1mm

C7005

0.22UF

X5R-CERM

0603-1

2

S

G

3

(CHGR_DCIN)

C7001

2

CHGR_DCIN

57

26

CHGR_SGATE

1

CHGR_AGATE

28

CHGR_CSI_P

77

27

CHGR_CSI_N

77

25

CHGR_BOOT

24

CHGR_UGATE

23

21

CHGR_LGATE

16

CHGR_BGATE

9

CHGR_AMON

15

CHGR_BMON

14

=CHGR_ACOK

(GND)

(CHGR_CSO_P)
(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

1

10%
50V

2

GND_CHGR_AGND

57

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

Reverse-Current Protection

1

C7080

4.7UF

10%
35V

2

X5R-CERM

0603

NOSTUFF

NCNCNC

879

D

CRITICAL

1UF

10%
10V
X5R
402

10

1

2

415

S

D

G

6

1

C7020

0.047UF

10%
10V

2

X5R-CERM
0402

NO_XNET_CONNECTION=TRUE

C7022

0.1UF

R7025

1/16W
MF-LF

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

DIDT=TRUE

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm
MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE
DIDT=TRUE

44

OUT

44

OUT

44 40

OUT

1

C7026

0.001UF

10%
50V

2

X7R-CERM

0402

CHGR_SGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

(CHGR_SGATE)

R7021

1 2

R7022

1 2

1

1

C7021

10%
25V
X5R
402

1

0

5%

402

2

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

0.1UF

10%
25V

2

2

X5R
402

NO_XNET_CONNECTION=TRUE

CHGR_BOOT_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

1

C7025

0.22UF

10%
10V

2

CERM
402

PLACE_NEAR=U7000.25:2mm

SWITCH_NODE=TRUE

DIDT=TRUE

10

5%
1/16W
MF-LF

402

10

5%
1/16W
MF-LF

402

R7051
R7052

CHGR_DCIN_D_R

57

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

PPDCIN_G3H_INRUSH

MIN_LINE_WIDTH=0.1 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=18.5V

1

R7080

100K

5%
1/16W
MF-LF
402

2

1

R7081

62K

5%
1/16W
MF-LF
402

2

CHGR_CSI_R_P

78

CHGR_CSI_R_N

78

CRITICAL

2

1

6

3 4 5

1 2

2.2

1 2

0

4

Q7030

RJK03P0DPA

WPAK

7

CHGR_PHASE

CHGR_CSO_R_P

78

1/16W

CHGR_CSO_R_N

78

1/16W

(PPVBAT_G3H_CHGR_R)
(CHGR_BGATE)

4025%

C7090

4.7UF

X5R-CERM

0603

OMIT_TABLE

10%
35V

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

P5V1_VIN

1

2

R7092

1 2

MF-LF

1/16W

0

NC

CRITICAL

123

R7020

0.02

0.5%
1W
MF
RL1632W

PPDCIN_G3H_CHGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=18.5V

Max Current = 8.5A

(L7030 limit)
f = 400 kHz

CRITICAL

L7030

1 2

PIME103T-4R7MS

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

CRITICAL

R7050

0.01

0.5%
1W
MF

0612-3

1 2
3 4

MF-LF

MF-LF

4.7UH-20%-8.5A-18.3MOHM

4025%

4025%

For Erp Lot6 spec

P5V1_BOOST

DIDT=TRUE

3

6

BOOST

VIN

U7090

LT3470A

DFN

8 4

SHDN*

CRITICAL

7

NC

GND

SW

BIAS

FB

THRM

PAD

5

9

PART NUMBER

138S0811 CRITICAL

NO_TEST=TRUE

P5V1_SW

MIN_LINE_WIDTH=0.5 mm

2

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE
DIDT=TRUE

1

1

C7094

0.22UF

10%
10V

CERM

33UH-20%-0.39A-0.435OHM

402

2

CRITICAL

L7095

1 2

DP418C-SM

P5V1_BIAS

1

C7095

22PF

5%
50V

2

CERM
201

P5V1_FB

Vout = 1.25V * (1 + Ra / Rb)

QTY

1

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X6S,0603

MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm

<Ra>

1

R7095

681K

1%

1/20W

MF

201

2

<Rb>

1

R7096

200K

1%

1/20W

MF

201

2

REFERENCE DES

C7090

CRITICAL

1

C7098

10UF

20%
25V

2

X5R-CERM
0603

NOTE: C7080 is the same APN, but NOSTUFFed per <rdar://problem/11815538>.

1

C7030

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

CRITICALCRITICAL

1

C7031

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

CRITICAL

1

C7032

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

1

C7035

1.0UF

10%
50V

2

X5R
0603

1

C7036

1.0UF

10%
50V

2

X5R
0603

PLACE_NEAR=Q7030.5:1mm

1

C7037

0.001UF

20%
50V

2

CERM
0402

PLACE_NEAR=C7036.1:3mm

CRITICAL

F7040

12AMP-32V

1 2

1206

CRITICAL

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

C7055

1UF

10%
25V
X5R
402

1

C7040

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

C7056

2

0.1UF

10%
25V
X5R
402

1

2

1

C7045

0.001UF

10%
50V

2

X7R-CERM
0402

C7057

0.01UF

X7R-CERM

0402

10%
50V

CRITICAL

Q7055

SI7137DP

SO-8

SYM-VER-2

S

3
2

1

1

2

D

G

4

NOSTUFF

R7090

0

(P5V1_BIAS)

CRITICAL

1

C7099

10UF

20%
25V

2

X5R-CERM
0603

CRITICAL

1 2

5% 402

MF-LF

1/16W

R7091

0

1 2

MF-LF

4025%

1/16W

Vout = 5.50V
100MA MAX OUTPUT
(Switcher limit)

BOM OPTION

TO SYSTEM

=PPBUS_G3H

TO/FROM BATTERY

5

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V

CHGR_DCIN

PP5V1_CHGR_VDDP

56

8

56

7

57

57

D

C

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

PBus Supply & Battery Charger

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

70 OF 132

SHEET

57 OF 80

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

System Agent Power Supply

12

D

DESCRIPTION

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

1

1

C7122

0.001UF

10%
35V

12

20%
50V

2

2

CERM
0402

PLACE_NEAR=C7121.1:3mm

PPVCCSA_S0_REG_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

VCCSAS0_CS_P

78 80

VCCSAS0_CS_N

78 80

1

R7142

1K

1%
1/16W
MF-LF
402

2

NO_XNET_CONNECTION=TRUE

20%
16V

1/16W
MF-LF

402

1

2

1K

1%

QTY

1

OMIT_TABLE

C7121

1.0UF

CERM-X5R

0402

PLACE_NEAR=Q7100.2:1mm

CRITICAL

L7100

1.0UH-7A

1 2

PIMB053T-SM

152S1302

1

C7140

2

1000PF

5%

25V

NP0-C0G

402

PART NUMBER

138S0812 CRITICAL

=PPVIN_S0_VCCSAS0

8

=PP5V_S0_VCCSAS0

8

PVCC

PGND

20

2

CRITICAL

1

C7101

10UF

20%
10V

2

X5R
603

BOOT

UGATE

PHASE

LGATE

1

R7101

2.2

5%
1/16W
MF-LF

402

EN

10

FB

7

SREF

12

VO

11

OCSET

PGOOD

4

RTN

FSEL

8

SET0

9

SET1

6

VID0

5

VID1

XW7100

2

19

VCC

U7100

ISL95875

UTQFN

CRITICAL

(ENDIAN SWAP)

GND

3

SM

1 2

PLACE_NEAR=U7100.3:1mm

PP5V_S0_VCCSAS0_VCC

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

66

C

CPU_VCCSASENSE

13 72

IN

VCCSAS0_RTN

2

XW7101

PLACE_NEAR=C1761.2:1mm

SM

1

B

R7151

1.62K

1 2

1%
1/16W
MF-LF

402

R7153

1.62K

1 2

1%
1/16W
MF-LF

402

1

C7106

10PF

5%
50V

2

CERM
402

1

R7154

4.64K

1%
1/16W
MF-LF
402

2

1

R7152

4.64K

1%
1/16W
MF-LF
402

2

C7103

0.022UF

X5R-X7R-CERM

0402

1

C7105

10PF

5%
50V

2

CERM
402

10%
16V

1

2

1

R7147

41.2K

1%
1/16W
MF-LF
402

2

1

R7148

52.3K

1%
1/16W
MF-LF
402

2

R7150

82.5K

1 2

1%
1/16W
MF-LF

402

VCCSAS0_SET_R

1

R7149

499K

1%
1/16W
MF-LF
402

2

IN

66

OUT

NO STUFF

R7103

1

C7102

2.2UF

10%
16V

2

X5R
603

13 72

13 72

=PVCCSA_EN

CPU_VCCSASENSE_DIV

VCCSAS0_SREF

NO_TEST=TRUE

VCCSAS0_VO
VCCSAS0_OCSET
PVCCSA_PGOOD
VCCSAS0_RTN_DIV

NO_TEST=TRUE

VCCSAS0_FSEL

VCCSAS0_SET0

1

VCCSAS0_SET1

0

5%
1/16W
MF-LF

402

2

CPU_VCCSA_VID<1>

IN

CPU_VCCSA_VID<0>

IN

VCCSAS0_AGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

14

13

INTEL TABLE:

VCCSAS0_BOOT_RC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

VCCSAS0_VBST

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

1815

17

16

1

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

VCCSAS0_LL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE
DIDT=TRUE

VCCSAS0_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

(VCCSAS0_OCSET)

(VCCSAS0_VO)

R7130

5%
1/16W
MF-LF

402

VCCSAS0_DRVH

CRITICAL

C7120

1

C7130

1

0.22UF

0

10%
10V

2

CERM
402

2

2

1

6

3 4 5

68UF

POLY-TANT

CASE-D2E-SM

376S0944

CRITICAL

Q7100

RJK0222DNS

HWSON

7

R7141

NO_XNET_CONNECTION=TRUE

REFERENCE DES

CRITICAL

R7140

0.001

2%
1W
MF

0612

12
34

C7121

1

C7160

2

1000PF

10%
16V
X7R-CERM
0201

CRITICAL

OCP = R7141 x 8.5uA / R7140
OCP = 8.5A

BOM OPTION

=PPVCCSA_S0_REG

6A Max Output
f = 500 kHz

8

80

D

C

B

VID1 VID0 Voltage

0 0 0.9V

1 0 0.8V

0 1 0.725V

1 1 0.675V

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

System Agent Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

71 OF 132

SHEET

58 OF 80

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

12

D

=PPVIN_S5_P5VP3V3

8

CRITICAL

C7243

68UF

POLY-TANT

CASE-D2E-SM

=PP5V_S4_REG

8

59

20%
16V

1

2

CRITICAL

C7240

68UF

POLY-TANT

CASE-D2E-SM

20%
16V

1

2

CASE-D2E-SM

CRITICAL

C7242

68UF

POLY-TANT

20%
16V

VOUT = 5.0V
12A MAX OUTPUT
F = 600 KHZ F = 600 KHZ

C

CRITICAL

1

C7253

330UF

20%

6.3V

2

POLY-TANT
CASE-D3L-SM

CRITICAL

C7252

330UF

6.3V

POLY-TANT

CASE-D3L-SM

20%

1

2

1

C7271

0.001UF

10%
50V

2

X7R-CERM
0402

CRITICAL

C7250

10UF

20%
25V

X5R-CERM

0603

1

2

2

1

152S0688

CRITICAL

L7220

1.0UH-21A-0.006OHM

PCMB103T-1R0MS

2

P5VS4_VSW

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

PLACE_NEAR=L7220.1:3MM

XW7222

1

PLACE_NEAR=L7220.1:3MM

P5VS4_VFB1_R

1

R7220

40.2K

0.5%
1/16W
MF-LF
0402

2

B

1

R7221

10.0K

0.5%
1/16W
MF
402

2

XW7220

2

SM

1

PLACE_NEAR=L7220.2:3MM

2

XW7221

SM

1

P5VS4_CSP1_R

OMIT_TABLE

1

1

C7241

1.0UF

10%
35V

2

2

CERM-X5R
0402

NO STUFF

1

R7299

1

5%
1/10W
MF-LF
603

2

P5VS4_SNUBR

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

NO STUFF

C7299

0.0033UF

1

C7270

0.001UF

20%
50V

2

CERM
0402

CRITICAL

CSD58872Q5D

VIN

1

VSW

6
7
8

PGND

1

10%
50V

2

CERM

402

Q7220

SON5X6

9

TG

TGR

BG

R7256

3.01K

1/16W
MF-LF

402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1

C7224

0.1UF

10%
50V

2

X7R
603-1

3

P5VS4_TG

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

4

5

C7218

X7R-CERM

R7247

1 2

1

1%

2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

0.1UF

1 2

10%
16V

0402

1.5K

1%
1/16W
MF-LF

402

PART NUMBER

C7200

SKIP_5V3V3:AUDIBLE

1

R7244

1

5%
1/16W
MF-LF

402

2

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

1

C7237

150PF

5%

50V

2

CERM

402

QTY

2

1

1UF

10%
25V

2

X5R

603-1

SKIP_5V3V3:INAUDIBLE

R7201

1

R7200

0

5%

1/20W

MF

201

2

P5VP3V3_SKIPSEL

P5VS4_VBST

DIDT=TRUE

P5VS4_DRVH

DIDT=TRUE

P5VS4_LL

DIDT=TRUE

P5VS4_DRVL

DIDT=TRUE

P5VS4_CSP1
P5VS4_CSN1

P5VS4_VFB1
P5VS4_COMP1

=P5VS4_EN

47 66

IN

P5VS4_PGOOD

66

OUT

1

R7237

10K

1%
1/16W
MF-LF
402

2

P5VS4_COMP1_R P3V3S5_CSP2_R

1

C7236

4700PF

10%
100V

2

CERM
402

(P5VP3V3_VREF2)

DESCRIPTION

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

=PP5V_S4_REG

8

59

1

0

5%

1/20W

MF

201

2

R7236

12.1K

1%
1/16W
MF-LF

402

GND_5V3V3_AGND

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

6
19
14

31

1

32

30

7

8

11

9
10

4

5

1

2

REFERENCE DES

C7241,C7281

2

23

VIN

V5SW

SKIPSEL1
SKIPSEL2
OCSEL

DRVL1

CSP1

MODE
VFB1 VFB2

CRITICAL

GND

28

XW7200

PLACE_NEAR=U7200.28:1MM

29

VREG5

U7201

QFN

2

SM

1

22

VREG3

TPS51980

PGOOD2PGOOD1

THRM_PAD

33

VBST2VBST1

DRVH2DRVH1

DRVL2

CSP2
CSN2CSN1

COMP2COMP1

P5VP3V3_VREG3
P5VP3V3_VREF2

13

VREF2

12

EN

26

DIDT=TRUE

24

DIDT=TRUE

25

SW2SW1

EN2EN1

DIDT=TRUE

27

DIDT=TRUE

18
17

3

RF

16
15

21
20

CRITICAL

CRITICAL138S0812

1

C7201

0.22UF

10%
10V

2

CERM

402

=P5VS5_EN

P3V3S5_VBST
P3V3S5_DRVH
P3V3S5_LL
P3V3S5_DRVL
P3V3S5_CSP2

P3V3S5_CSN2
P3V3S5_RF

P3V3S5_VFB2
P3V3S5_COMP2

=P3V3S5_EN
P3V3S5_PGOOD

1

R7238

12.1K

1%
1/16W
MF-LF
402

2

P3V3S5_COMP2_R

(P5VP3V3_VREF2)

BOM OPTION

1

C7203

2.2UF

20%
10V

2

X5R-CERM
402

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

OUT

R7239

C7238

4700PF

100V
CERM

IN

IN

10%
402

66

66

66

10K

1/16W
MF-LF

402

1

2

1

1%

2

=PP5V_S5_LDO

VOUT = 5V
100MA MAX OUTPUT

CRITICAL

1

C7205

10UF

20%

6.3V

2

X5R
603

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

R7263

0

1 2

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1

2

MIN_LINE_WIDTH=0.6 MM

5%

MIN_NECK_WIDTH=0.2 MM

1/16W

DIDT=TRUE

MF-LF

GATE_NODE=TRUE

402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

1

R7206

165K

1%
1/16W
MF-LF

402

2

C7239

47PF

5%
50V
CERM
402

8

C7264

P3V3S5_TG

C7288

0.1UF

X7R-CERM

R7246

1 2

1/16W
MF-LF

0.1UF

603-1

1 2

10%
16V

0402

806

1%

402

10%
50V
X7R

1

2

1

6

1

R7216

5.23K

1%
1/16W
MF-LF
402

2

2

3 4 5

CRITICAL

C7284

68UF

POLY-TANT

CASE-D2E-SM

376S0958

CRITICAL

Q7260

FDMS3602S

POWER56

7

PHASE

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

1

2

CRITICAL

1

2

CASE-D2E-SM

C7280

POLY-TANT

20%
16V

NO STUFF

P3V3S5_SNUBR

NO STUFF

C7298

0.001UF

10%
50V
X7R
402

68UF

20%
16V

152S0754

CRITICAL

1.0UH-22A

PCMC063T-SM

R7298

1/10W
MF-LF

CRITICAL

1

2

CASE-D2E-SM

L7260

1

10

5%

603

2

XW7260

C7282

68UF

POLY-TANT

SM

OMIT_TABLE

1

20%
16V

2

12

PLACE_NEAR=L7260.2:3MM

2

XW7262

SMSM

1

PLACE_NEAR=L7260.1:3MM

PLACE_NEAR=L7260.2:3MM

2

2

XW7261

SM

1

1

1

C7281

1.0UF

10%
35V

2

CERM-X5R
0402

=PP3V3_S5_REG

VOUT = 3.3V

10.5A MAX OUTPUT

C7272

0.001UF

CRITICAL

1

C7290

2

P3V3S5_VFB2_R

X7R-CERM

0402

10UF

20%
25V
X5R-CERM
0603

1

C7283

0.001UF

20%
50V

2

CERM
0402

1

10%
50V

2

R7260

23.2K

1/16W
MF-LF

R7261

10.0K

1/16W

0.5%

0402

0.5%

402

CRITICAL

1

C7292

330UF

20%

6.3V

2

POLY-TANT
CASE-D3L-SM

1

2

1

MF

2

D

8

C

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

5V / 3.3V Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

72 OF 132

SHEET

59 OF 80

124578

SIZE

A

D

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8 7 6 5 4 3

12

PART NUMBER

138S0812 CRITICAL

QTY

2

DESCRIPTION

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

D

REFERENCE DES

C7332,C7335

CRITICAL

BOM OPTION

D

DDR3 (1V5R1V35 S3) REGULATOR

=PPVIN_S3_DDRREG

8

CRITICAL

1

C7336

68UF

20%
16V

2

POLY-TANT

=PPVIN_S0_DDRREG_LDO

8

VTT Enable

1

R7318

51.1K

1%
1/16W
MF-LF
402

2

CRITICAL

1

C7301

10UF

20%
10V

2

X5R-CERM

0402-1

PLACE_NEAR=U7300.2:1mm

12 15

V5IN

17

S3

16

19
18

TPS51916

S5

6

VREF

CRITICAL

8

REFIN

MODE
TRIP

PGND

10

DESCRIPTION

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

RES,MTL FILM,1/16W,60.4K,1,0402,SMD,LF

MOSFET,N-CH,30V,100MA,7.0OHM,SOT-723,HF

RES, MTL FILM,1/16W,150k,0402,SMD,LF

2

VLDOIN

U7300

QFN

VTT

GND

7

4

VDDQSNS

THRM

PADGND

VBST
DRVH

SW

DRVL

PGOOD

VTT

VTTSNS

VTTREF

21

XW7300

MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm

DDRREG_VBST

DDRREG_DRVH

14

DDRREG_LL

13

SWITCH_NODE=TRUE

DIDT=TRUE

DDRREG_DRVL

11

DDRREG_PGOOD

20

DDRREG_VDDQSNS

9

=PPVTT_S0_DDR_LDO

8

3
1

DDRREG_VTTSNS
=PPVTT_S3_DDR_BUF

5

10mA max load

2

C7350

0.22UF

SM

1

PLACE_NEAR=U7300.21:1mm

REFERENCE DES

R7316

R7316

Q7319

R7319

=PP5V_S3_DDRREG

8

CRITICAL

1

C7300

10UF

20%
10V

2

X5R-CERM

0402-1

PLACE_NEAR=U7300.12:1mm

C

DDRREG_FB

31

IN

=DDRVTT_EN

9

27

IN

=DDRREG_EN

66

IN

DDRREG_1V8_VREF

1

1

C7315

0.1UF

10%
16V

2

X7R-CERM

0402

PLACE_NEAR=U7300.6:1mm

OMIT_TABLE

DDRREG_P1V35_L

Q7319

SSM3K15FV

SOD-VESM-HF

CRITICAL

OMIT_TABLE

B

R7319

150K

1/16W
MF-LF

1

G S

1

1%

402

2

3

D

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

2

VOLTAGE=0V

MEM_VDD_SEL_1V5_L

R7315

20.0K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U7300.8:5mm

OMIT_TABLE

1

R7316

100K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U7300.8:5mm

IN

1

C7316

0.01UF

10%
16V

2

X7R-CERM
0402

PLACE_NEAR=U7300.8:1mm

24

PART NUMBER

114S0411

114S0391

376S0612

114S0428

1

R7317

200K

1%
1/16W
MF-LF
402

2

PLACE_NEAR=U7300.19:3mm

VDDQ/VTTREF Enable

DDRREG_MODE
DDRREG_TRIP

PLACE_NEAR=U7300.18:3mm

QTY

1

1

1

1

CASE-D2E-SM

NO_TEST=TRUE

GATE_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

C7360, C7361 close to memory

1

10%
10V

2

CERM

402

CRITICAL

CRITICAL

CRITICAL

CRITICAL

CRITICAL

OUT

1

2

R7325

402

5%

0

1 2

9

XW7360

SM

1 2

PLACE_NEAR=C7361.1:3mm

CRITICAL

C7360

10UF

X5R-CERM

0603

PLACE_NEAR=C7361.1:1mm

CRITICAL

C7331

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

MF-LF

1/16W

1

20%
25V

2

BOM OPTION

PPDDR:1V5

PPDDR:1V35

PPDDR:1V5

PPDDR:1V5

CRITICAL

1

C7334

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PLACE_NEAR=Q7330.5:1mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST_RC

MIN_NECK_WIDTH=0.17 mm
MIN_LINE_WIDTH=0.6 mm

(DDRREG_LL)

CRITICAL

1

C7361

10UF

20%
25V

2

X5R-CERM
0603

PLACE_NEAR=C7360.1:3mm

OMIT_TABLE

1

C7332

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=Q7330.5:1mm

(DDRREG_DRVH)

C7325

0.1UF

1 2

10%
25V
X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.17 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.17 mm

OMIT_TABLE

1

C7335

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=C7332.1:3mm

1

6

1

2

2

3 4 5

C7333

0.001UF

20%
50V
CERM
0402

PHASE

CRITICAL

Q7330

FDMS3602S

POWER56

0.68UH-18A-3.3MOHM

7

152S0905

CRITICAL

L7330

1 2

PCMB103T

CRITICAL

1

C7342

330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

CRITICAL

1

C7340

330UF

20%

2.0V

2

POLY-TANT
CASE-B2-SM1

CRITICAL

C7341

330UF

POLY-TANT

CASE-B2-SM1

2.0V

C

=PPDDR_S3_REG

Vout = 1.5V

15.5A max output

1

C7346

0.001UF

10%
50V

2

X7R-CERM

1

1

C7345

10UF

20%

20%
25V

2

2

X5R-CERM
0603

0402

2

XW7301

SM

1

PLACE_NEAR=C7340.1:1mm

(Q7335 limit)
f = 400 kHz

8

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

1.5V DDR3 Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

DRAWING NUMBER

<SCH_NUM>

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=MASTER

<E4LABEL>

<BRANCH>

73 OF 132

60 OF 80

SIZE

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8 7 6 5 4 3

12

=PP5V_S0_CPUIMVP

R7401

10

PP5V_S0_CPUIMVP_VCC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM

D

C

VOLTAGE=5V

1

R7468

5.76K

1%
1/20W
MF
201

2

1

CRITICAL

R7469

100KOHM

0402

2

CPU_PROCHOT_L

11 39 40 72

OUT

1

R7466

5.76K

1%
1/20W
MF
201

2

1

CRITICAL

R7467

100KOHM

0402

2

=PPVCCIO_S0_CPUIMVP

8

1

C7450

47PF

5%
50V

2

CERM
402

OMIT

1

R7464

NOSTUFF

NONE
NONE
NONE
0201

2

1

R7465

200K

1%
1/20W
MF
201

2

66

IN

13 72

IN

13 72

IN

13 72

IN

CPUIMVP_VR_ON
CPU_VIDSOUT

CPU_VIDSCLK
CPU_VIDALERT_L

R7479

54.9

1/16W
MF-LF

PLACE_NEAR=U7400.23:2mm

1

R7462

196K

1%
1/20W
MF
201

2

1

R7463

137K

1%
1/20W
MF
201

2

1

1

R7480

130

1%

1%
1/16W
MF-LF

402

402

2

2

PLACE_NEAR=U7400.21:2mm

1

R7460

301K

1%
1/20W
MF
201

2

1

R7461

137K

1%
1/20W
MF
201

2

CPUIMVP_AXG_PWN2

62

OUT

CPUIMVP_PGOOD

66

OUT

CPUIMVP_AXG_PGOOD

9

OUT

CPUIMVP_NTC
CPUIMVP_NTCG

CPUIMVP_SLEW
CPUIMVP_IMAXA

CPUIMVP_IMAXB

C7401

2.2UF

20%
10V

X5R-CERM

402

1

2

13

DRVPWMB

37

DRVPWMA

NC

45

CSPA3

4

VRHOT*

24

POKA

12

POKB

47

EN

21

VDIO

23

CLK

22

ALERT*

39

THERMA

40

THERMB

38

SR

35

IMAXA

36

IMAXB

8

CSPBAVE

AGND

5

1 2

1/16W
MF-LF

462919

VCC

VDDA

U7400

MAX15119GTM

QFN

CRITICAL

GNDSB

GNDSA

2

7

20

49

5%

402

VDDB

CSPAAVE

PAD

THRM

BSTA1

CSPA1

CSPA2
BSTA2

CSPB2

CSPB1

PGNDA

30

TONB

TONA

DHA1
LXA1
DLA1

CSNA

DHA2
LXA2
DLA2

BSTB

CSNB

1

48

25

27

26
28
42

41
43
3

FBA

44
34
32
33
31

14
16

DHB

15

LXB

18

DLB

11
9
10
6

FBB

PGNDB

17

XW7400

CPUIMVP_TONB
CPUIMVP_TONA
CPUIMVP_BOOT1

CPUIMVP_UGATE1
CPUIMVP_PHASE1
CPUIMVP_LGATE1
CPUIMVP_ISUM1P

CPUIMVP_ISUM
CPUIMVP_ISUMN
CPUIMVP_FBA

CPUIMVP_ISUM2P
CPUIMVP_BOOT2
CPUIMVP_UGATE2
CPUIMVP_PHASE2
CPUIMVP_LGATE2

CPUIMVP_BOOT1G
CPUIMVP_UGATE1G
CPUIMVP_PHASE1G
CPUIMVP_LGATE1G

CPUIMVP_FBB

NO_TEST=TRUE

SM

12

1

C7402

2.2UF

20%
10V

2

X5R-CERM
402

PLACE_NEAR=U7400.29:2mm
PLACE_NEAR=U7400.19:2mm

Note: value needs scrubbing

R7402

182K

1 2

1%

1/20W

MF

201

NO STUFF

1

C7418

100PF

5%
25V

2

CERM
201

1

C7419

100PF

5%
25V

2

CERM
201

1

C7403

2.2UF

20%
10V

2

X5R-CERM
402

OUT
OUT
OUT
OUT

61

OUT
OUT
OUT
OUT

OUT
OUT
OUT
OUT

61

R7403

182K

1 2

1/20W

62

62

62

62

62

62

NO_TEST=TRUE

62

62

62

62

62

62

NO STUFF

1

C7414

100PF

5%
25V

2

CERM
201

1%
MF

201

8

NO STUFF

1

C7415

100PF

5%
25V

2

CERM
201

62

=PPVIN_S0_CPUIMVP

NO STUFF

1

C7416

100PF

5%
25V

2

CERM
201

IN

NO STUFFNO STUFF

1

C7423

100PF

5%
25V

2

CERM
201

8

62

NO_XNET_CONNECTION=TRUE

R7406

200

1 2

R7407

1 2

C7408

220PF

1 2

62

OUT

62

62

OUT

10%
25V

X7R-CERM

0201

C7409

1000PF

CPUIMVP_ISUM_R

1 2

10%
16V
X7R
201

R7410

1

1 2

5%

1/20W

MF

201

CPUIMVP_ISNS1_P

5%

1/20W

MF

NO_XNET_CONNECTION=TRUE

201

200

CPUIMVP_ISNS2_P

5%

1/20W

MF

201

CPUIMVP_ISUMG2P

CPUIMVP_ISUMG1P

NO_TEST=TRUE

CPUIMVP_ISUMGN

43 62 78

IN

43 62 78

IN

62

IN

62

IN

62

IN

D

C

GND_CPUIMVP_SGND

B

PLACE_NEAR=Q7510.1:1mm
PLACE_NEAR=Q7550.1:1mm

CPUIMVP_ISUMG_AVEP

62

IN

NO_TEST=TRUE

A

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

C7441

NO_XNET_CONNECTION=TRUE

1000PF

X7R-CERM

NO_XNET_CONNECTION=TRUE

10%
16V

0201

1

C7440

1000PF

10%
16V

2

X7R-CERM
0201

1

2

NO_XNET_CONNECTION=TRUE

R7440

10

CPU_AXG_SENSE_R

CPU_VCCSENSE_R CPU_VCCSENSE_N

NO STUFF

1

C7442

1000PF

10%
16V

2

X7R
201

NO STUFF

1

C7443

1000PF

10%
16V

2

X7R
201

PLACE HOLDERPLACE HOLDER

1 2

R7441

10

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

5%

1/20W

MF

201

CPU_AXG_SENSE_N

13 72

IN

CPUIMVP_FBA

61

13 72

IN

CPUIMVP_FBB

61

6 3

C7413

100PF

1 2

5%

50V
CERM
0402

R7412

8.06K

1 2

1%
1/16W
MF-LF

402

CPUIMVP_FBA_R

R7422

16.9K

1 2

1%
1/16W
MF-LF

402

NO_XNET_CONNECTION=TRUE

1

C7412

1000PF

10%
16V

2

X7R-CERM
0201

CPUIMVP_FBB_R

R7413

10

1

C7422

1000PF

10%
16V

2

X7R-CERM
0201

SYNC_MASTER=MASTER

PAGE TITLE

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

R7423

10

1 2

5%

1/20W

MF

201

CPU_VCCSENSE_P

CPU_AXG_SENSE_P

CPU IMVP7 & AXG VCore Regulator

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

IN

IN

13 72

13 72

DRAWING NUMBER

REVISION

BRANCH

PAGE

SHEET

124578

SYNC_DATE=MASTER

<SCH_NUM>

<E4LABEL>

<BRANCH>

74 OF 132

61 OF 80

SIZE

B

A

D

www.vinafix.vn

8 7 6 5 4 3

=PPVIN_S0_CPUIMVP

8

61 62

PHASE 1

CPUIMVP_BOOT1

61

IN

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1

61

IN

D

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

61

IN

61

IN

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE1

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

GATE_NODE=TRUE

=PPVIN_S0_CPUIMVP

8

61 62

PHASE 2

CPUIMVP_BOOT2

61

IN

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

C

CPUIMVP_UGATE2

61

IN

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

61

IN

MIN_LINE_WIDTH=0.6 MM

61

IN

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

DIDT=TRUE

CPUIMVP_PHASE2

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE2

=PPVIN_S0_CPUAXG

8

AXG PHASE 1

B

CPUIMVP_BOOT1G

61

IN

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE1G

61

IN

MIN_NECK_WIDTH=0.2 MM
MIN_LINE_WIDTH=0.5 MM

61

IN

61

IN

CPUIMVP_PHASE1G

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE1G

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_BOOT1_RC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

R7511

5%
1/16W
MF-LF

402

DIDT=TRUE

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

R7521

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

CPUIMVP_BOOT1G_RC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

1

R7551

0

5%
1/16W
MF-LF

402

2

DIDT=TRUE

SWITCH_NODE=TRUE

DIDT=TRUE

GATE_NODE=TRUE

DIDT=TRUE

1

0

2

CPUIMVP_BOOT2_RC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

1/16W
MF-LF

402

DIDT=TRUE

DIDT=TRUE

C7551

0.22UF

DIDT=TRUE

0

5%

CERM

10%
10V

402

1

2

DIDT=TRUE

1

2

1

2

C7511

0.22UF

10%
10V
CERM
402

1

C7521

0.22UF

10%
10V

2

CERM
402

376S1010

376S1010

376S1010

CRITICAL

1

C7513

68UF

20%
16V

2

POLY-TANT

7

8

CRITICAL

Q7510

D

IRF6802SDTRPBF

G

2

DIRECTFET-SA

S

3

CASE-D2E-SM

NCNC

128

7

CRITICAL

D

Q7515

S

356

5

6

CRITICAL

Q7510

D

IRF6802SDTRPBF

DIRECTFET-SA

S

4

649135PBF

DIRECTFET_S3C

376S1011

CRITICAL

1

C7523

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7524

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

G

4

G

1

NCNC

128

7

CRITICAL

D

Q7525

S

356

5

6

CRITICAL

Q7550

IRF6802SDTRPBF

DIRECTFET-SA

4

7

CRITICAL

D

Q7551

S

649135PBF

DIRECTFET_S3C

376S1011

649135PBF

DIRECTFET_S3C

376S1011

CRITICAL

1

C7553

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7554

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

0.36UH-20%-36A-0.00108OHM

L7550

1 2

PIMS103T-SM

152S1538

G

4

D

G

1

S

NCNC

128

G

4

356

AXG PHASE 2

=PP5V_S0_CPUIMVP

8

61

AXG_PHASE2

1

AXG_PHASE2

1

R7540

10K

5%
1/16W
MF-LF
402

A

2

CPUIMVP_AXG_PWN2

61

IN

CPUIMVP_SKIP

AXG_PHASE2

2

PWN

6

SKIP*

5

VDD

U7542

MAX17491

TQFN

CRITICAL

THRM

GND

3

PAD

1

BST

8

DH

7

LX

4

DL

9

C7541

1UF

10%
16V

2

X5R
402

CPUIMVP_BOOT2G

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_UGATE2G

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_PHASE2G

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM

CPUIMVP_LGATE2G

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM

AXG_PHASE2

DIDT=TRUE

GATE_NODE=TRUE

SWITCH_NODE=TRUE

GATE_NODE=TRUE

R7542

DIDT=TRUE

DIDT=TRUE

DIDT=TRUE

CPUIMVP_BOOT2G_RC

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.25 MM

DIDT=TRUE

1

0

5%
1/16W
MF-LF

402

2

OMIT_TABLE

CRITICAL

1

C7515

4.7UF

10%
35V

2

X5R-CERM
0603

0.36UH-20%-36A-0.00108OHM

NOSTUFF

CRITICAL

1

C7525

4.7UF

10%
35V

2

X5R-CERM
0603

0.36UH-20%-36A-0.00108OHM

OMIT_TABLE

CRITICAL

1

C7516

4.7UF

10%
35V

2

X5R-CERM
0603

PLACE_NEAR=Q7510.1:1mm

CRITICAL

L7510

1 2

PIMS103T-SM

152S1538

NOSTUFF

CRITICAL

1

C7526

4.7UF

10%
35V

2

X5R-CERM
0603

PLACE_NEAR=Q7510.1:1mm

1 2

CRITICAL

L7520

PIMS103T-SM

152S1538

THESE TWO CAPS ARE FOR EMC

1

2

THESE TWO CAPS ARE FOR EMC

OMIT_TABLE

1

C7517

1.0UF

10%
35V

2

CERM-X5R
0402

PPVCORE_S0_CPU_PH1

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.25V

OMIT_TABLE

C7527

1.0UF

10%
35V
CERM-X5R
0402

PLACE_NEAR=C7527.1:3mm

PPVCORE_S0_CPU_PH2

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.25V

Removed snubber with EMC’s comment

NO_XNET_CONNECTION=TRUE

NOSTUFF

CRITICAL

1

C7555

4.7UF

10%
35V

2

X5R-CERM
0603

PPVCORE_S0_AXG_R

MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

CPUIMVP_ISNS1G_P

NO_XNET_CONNECTION=TRUE

AXG_PHASE2

1

C7542

0.22UF

10%
10V

2

CERM
402

NOSTUFF

CRITICAL

1

C7556

4.7UF

10%
35V

2

X5R-CERM
0603

R7553

46.4

1/20W

201

PLACE_NEAR=Q7550.1:1mm

R7550

0.00075

1%
1W
MF

0612

1 2
3 4

1

1%
MF

2

1

C7518

0.001UF

10%
50V

2

X7R-CERM
0402

PLACE_NEAR=C7517.1:3mm

NO_XNET_CONNECTION=TRUE

1

C7528

0.001UF

10%
50V

2

X7R-CERM
0402

NOSTUFF

R7598

NO_XNET_CONNECTION=TRUE

OMIT_TABLE

THESE TWO CAPS ARE FOR EMC

1

C7557

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=C7557.1:3mm

CRITICAL

200

1/20W

201

1%
MF

1

2

1

C7558

0.001UF

10%
50V

2

X7R-CERM
0402

1

2

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS1G_N

1

R7554

10

NO_XNET_CONNECTION=TRUE

1%
1/20W
MF
201

2

CPUIMVP_ISUMGN

1

C7574

2200PF

10%
10V

2

X7R-CERM

CPUIMVP_ISUMG1P

0201

1

C7519

0.001UF

10%
50V

2

X7R-CERM
0402

NOSTUFF

1

R7599

200

1%

1/20W

MF

201

2

NO_XNET_CONNECTION=TRUE

CRITICAL

46.4

1/20W

OUTOUT

IN

IN

CRITICAL

R7520

0.00075

1 2
3 4

1

1%
MF

201

2

1

2

43 78 43 62 78

61 62

61

1

C7522

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1%
1W
MF

0612

C7559

0.001UF

10%
50V
X7R-CERM
0402

1

R7524

10

1%
1/20W
MF
201

2

C7529

0.001UF

10%
50V
X7R-CERM
0402

R7523

PLACE_NEAR=U7400.10:1mm

CRITICAL

1

C7510

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

R7510

0.00075

1%
1W
MF

0612

1 2
3 4

1

R7513

46.4

1/20W

201

1

R7514

1%
MF

10

2

2

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS2_N
CPUIMVP_ISNS2_P

NO_XNET_CONNECTION=TRUE

PLACE_NEAR=U7400.43:1mm

1

C7572

2200PF

10%
10V

2

X7R-CERM
0201

CRITICAL

1

C7560

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

376S1010

8

62

4

61 62

OUT

G

2

G

CPUIMVP_ISUMGN

CRITICAL

1

C7512

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

PART NUMBER

=PPVCORE_S0_CPU_REG

CPUIMVP_ISNS1_N
CPUIMVP_ISNS1_P

NO_XNET_CONNECTION=TRUE

1%
1/20W
MF
201

PART NUMBER

138S0811

OUT
OUT

CPUIMVP_ISUMN

CPUIMVP_ISUM2P

7

8

CRITICAL

Q7550

D

IRF6802SDTRPBF

DIRECTFET-SA

S

3

NCNC

128

7

AXG_PHASE2

CRITICAL

D

Q7561

649135PBF

DIRECTFET_S3C

376S1011

S

356

NO_XNET_CONNECTION=TRUE

QTY

4

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

8

62

43 78

OUT

43 61 78

OUT

CPUIMVP_ISUMN

PLACE_NEAR=U7400.43:1mm

1

C7571

2200PF

10%
10V

2

X7R-CERM
0201

CPUIMVP_ISUM1P

QTY

4

CAP,CER,4.7UF,10%,25V,X6S,0603

8

62

43 78

43 61 78

61 62

IN

61

IN

CRITICAL

1

C7561

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

CRITICAL

1

C7562

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

0.36UH-20%-36A-0.00108OHM

1 2

PIMS103T-SM

43 78 43 78

OUT OUT

Removed snubber with EMC’s comment

1

R7563

200

1%

1/20W

MF

201

2

CPUIMVP_ISUMG_AVE_RP

NO_TEST=TRUE

C7568

1000PF

X7R-CERM

0201

10%
16V

1

2

DESCRIPTION

61 62

IN

61

IN

DESCRIPTION

OMIT_TABLE

CRITICAL

1

C7563

4.7UF

10%
35V

2

X5R-CERM
0603

AXG_PHASE2

CRITICAL

L7560

PPVCORE_S0_AXG2_L

152S1538

CPUIMVP_ISNS2G_P

CPUIMVP_ISNS1G_P

AXG_PHASE2

1

R7564

200

NO_XNET_CONNECTION=TRUE
1%
1/20W
MF
201

2

1

R7566

0

5%
1/20W
MF
201

2

NOSTUFF

1

C7569

330PF

10%
16V

2

X7R
201

REFERENCE DES

C7517,C7527,C7557,C7565

REFERENCE DES

C7515,C7516,C7563,C7564

CRITICAL

1

C7550

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

OMIT_TABLE

CRITICAL

1

C7564

4.7UF

10%
35V

2

X5R-CERM
0603

PLACE_NEAR=Q7560.1:1mm

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM

VOLTAGE=1.05V

AXG_PHASE2

NO_XNET_CONNECTION=TRUE

CRITICAL

1

C7552

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

THESE TWO CAPS ARE FOR EMC

OMIT_TABLE

1

C7565

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=C7565.1:3mm

AXG_PHASE2

CRITICAL

R7560

0.00075

1%
1W
MF

0612

1 2
3 4

1

R7561

46.4

1%

1/20W

MF

201

2

43 62 78

OUT

CPUIMVP_ISUMG_AVEP

SYNC_MASTER=MASTER

PAGE TITLE

CPU IMVP7 & AXG VCore Output

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

CRITICAL

CRITICAL138S0812

CRITICAL

CRITICAL

1

C7566

0.001UF

10%
50V

2

X7R-CERM
0402

=PPVCORE_S0_AXG_REG

CPUIMVP_ISNS2G_N

AXG_PHASE2

1

R7562

10

1%
1/20W
MF

NO_XNET_CONNECTION=TRUE

201

2

CPUIMVP_ISUMGN

PLACE_NEAR=U7400.10:1mm

1

C7573

2200PF

10%
10V

2

X7R-CERM
0201

CPUIMVP_ISUMG2P

61

OUT

6 3

1

C7567

0.001UF

10%
50V

2

X7R-CERM
0402

AXG_PHASE2

12

BOM OPTION

BOM OPTION

CRITICAL

1

2

8

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

75 OF 132

SHEET

62 OF 80

124578

C7580

68UF

20%
16V
POLY-TANT
CASE-D2E-SM

62

61 62

OUT

61

OUT

SYNC_DATE=MASTER

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

D

CPU_VCCIOSENSE_P

13 72

CPU_VCCIOSENSE_N

C

13 72

1

402

402

1

R7644

3.01K

1%

1%
1/16W
MF-LF
402

2

2

<Ra>

1

1

R7645

2.74K

1%

1%
1/16W
MF-LF
402

2

2

<Rb>

1

C7604

47PF

50V

CERM

402

5%

1

C7605

47PF

5%
50V

2

2

CERM
402

C7602

1

C7603

0.047UF

10%
16V

2

X7R-CERM
0402

66

66

2.2UF

R7604

3.01K

1/16W
MF-LF

R7605

2.74K

1/16W
MF-LF

B

PP5V_S0_CPUVCCIOS0_VCC

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

IN

OUT

1

1

10%
16V

2

X5R
603

2

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

CPU VCCIO (1.05V S0) Regulator

=PPVIN_S0_CPUVCCIOS0

8

=PP5V_S0_CPUVCCIOS0

8

=CPUVCCIOS0_EN
CPUVCCIOS0_FB
CPUVCCIOS0_SREF
CPUVCCIOS0_VO
CPUVCCIOS0_OCSET
CPUVCCIOS0_PGOOD
CPUVCCIOS0_RTN
CPUVCCIOS0_FSEL
NOSTUFF

R7603

0

5%
1/16W
MF-LF
402

CPUVCCIOS0_AGND

1

R7601

2.2

5%
1/16W
MF-LF

402

2

13

VCC

U7600

ISL95874

3

6

4

8

7

9

2

5

UTQFN

EN

CRITICAL

FB

SREF

VO

OCSET

PGOOD

RTN

FSEL

GND

1

XW7600

SM

1 2

PLACE_NEAR=U7600.1:1mm

PVCC

PGND

1

2

14

BOOT

UGATE

PHASE

LGATE

16

CPUVCCIOS0_VBST_RC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

1

C7601

10UF

20%
10V
X5R-CERM
0402-1

R7630

0

5%
1/16W
MF-LF
402

2

CPUVCCIOS0_VBST

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

12

11

10

CPUVCCIOS0_LL

MIN_NECK_WIDTH=0.2 mm

15

SWITCH_NODE=TRUE
DIDT=TRUE

CPUVCCIOS0_DRVH

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

CPUVCCIOS0_DRVL

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE
DIDT=TRUE

(CPUVCCIOS0_OCSET)

(CPUVCCIOS0_VO)

1

2

C7630

1UF

10%
16V
X5R
402

PART NUMBER

CRITICAL

1

C7620

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

2

1

6

3 4 5

OCP = R7641 x 8.5uA / R7640
OCP = 26.265A
Vout = 0.5V * (1 + Ra / Rb)

CRITICAL

Q7630

RJK0230DPA

WPAK

0.36UH-20%-36A-0.00108OHM

7

QTY

138S0812 CRITICAL

CRITICAL

1

C7621

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

1

152S1538

CRITICAL

L7630

1 2

PIMS103T-SM

R7631

2.2

5%
1/10W
MF-LF
603

NOSTUFF

R7641

3.48K

1%
1/16W
MF-LF

402

12

PPCPUVCCIO_S0_REG_R

DIDT=TRUE

1

C7640

2

1000PF

12

5%

25V

NP0-C0G

402

DESCRIPTION

CAP,CER,1UF,10%,35V,X6S,0402,MURATA

CRITICAL

1

C7626

68UF

20%
16V

2

POLY-TANT
CASE-D2E-SM

MIN_LINE_WIDTH=0.6 mmMIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V

CPUVCCIOS0_SNUB

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

NO_TEST=TRUE

NOSTUFF

1

C7631

0.001UF

10%
50V

2

CERM
402

CPUVCCIOS0_CS_P

43 78

CPUVCCIOS0_CS_N

43 78

1

R7642

3.48K

1%
1/16W
MF-LF
402

2

CRITICAL

R7640

0.001

REFERENCE DES

1

C7622

0.001UF

20%
50V

2

CERM
0402

PLACE_NEAR=C7624.1:3mm

2%
1W
MF

0612

12
34

C7627

270UF

CASE-B2-SM

C7624

OMIT_TABLE

1

C7624

1.0UF

10%
35V

2

CERM-X5R
0402

PLACE_NEAR=Q7630.2:1mm

1

20%

2V

2

TANT

C7625

270UF

TANT

CASE-B2-SM

20%

2V

1

2

CRITICAL

C7623

0.001UF

CERM
0402

BOM OPTION

=PPCPUVCCIO_S0_REG

20%
50V

Vout = 1.05V

20.5A Max Output

1

2

f = 500 kHz

8

D

C

B

A

SYNC_MASTER=MASTER

PAGE TITLE

CPUVCCIO (1.05V) Power Supply

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

76 OF 132

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SIZE

A

D

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8 7 6 5 4 3

12

=PP3V3_S0_P1V5S0

D

8

66

IN

66

OUT

=P1V5S0_EN
P1V5S0_PGOOD

353S2535

2

EN

3

POR

SKIP

1

VIN

U7770

ISL8009B

DFN

CRITICAL

GND

THRM_PAD

7

CRITICAL

1

C7770

22UF

20%

6.3V

2

X5R
0603

8

LX

6

VFB

54

RSI

9

P1V5_S0_SW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE
DIDT=TRUE

P1V5_S0_FB

152S1051

CRITICAL

L7770

2.2UH-2A-0.155-OHM

1 2

2512

C7776

47PF

5%

50V

CERM

402

=PP1V5_S0_REG

8

Vout = 1.508V

1

R7780

1

100K

1%
1/16W
MF-LF

2

402

2

<Ra>

1

R7781

113K

1%
1/16W
MF-LF
402

2

<Rb>

Max Current = 1.5A
Freq = 1.6MHZ

CRITICAL

1

C7773

22UF

20%

6.3V

2

X5R
0603

Cougar Point requires JTAG pull-ups to be powered at 1.05V in SUS.
Pull-ups (3) must be 51 ohms to support XDP (not required in production).
70mA is required to support pull-ups. Alternative is strong voltage
dividers (200/100) to 3.3V S5, which burns 100mW in all S-states.

=PP3V3_SUS_P1V05SUSLDO

8

1.5V S0 Switcher

1.05V SUS LDO

CRITICAL

XDP_PCH

U7740

TPS720105

SON

4

XDP_PCH

C7740

1UF

6.3V
CERM

10%

402

BIAS

6

IN

3

EN

1

2

GND

5

THRM

PAD

7

OUT

1

2

NC

NC

=PP1V05_SUS_LDO

8

Vout = 1.05V
Max Current = 0.35A

XDP_PCH

1

C7741

2.2UF

10%

6.3V

2

X5R
402

D

Vout = 0.8V * (1 + Ra / Rb)

C

=PP3V3_S0_P1V8S0

8

1

C7760

22UF

20%

6.3V

2

X5R
0603

PLACE_NEAR=C7768.1:3mm

66

1

C7764

0.022UF

10%
16V

2

X5R-X7R-CERM
0402

P1V8S0_SS

P1V8_S0_COMP_RC

1

C7765

0.0015UF

10%
50V

2

X7R-CERM
0402-1

1.8V S0 Switcher

1

2

=P1V8S0_EN

IN

R7765

3.24K

1 2

1/16W
MF-LF

402

C7761

0.1UF

10%
25V
X5R
402

1%

1

C7768

1UF

10%

6.3V

2

X5R

PLACE_NEAR=U7760.A3:1mm

402

P1V8S0_COMP

NO_TEST=TRUE

B2

B3

C2

C1

B1

SKIP

EN

SS/REFIN

FB

COMP

U7760

MAX15053EWL

WLP

CRITICAL

GND

A1

IN

LX

PGOOD

P1V8SO_FB

A3

A2

P1V8S0_SW

C3

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE
DIDT=TRUE

P1V8S0_PGOOD

MAX CURRENT = 2A

152S1415

1.0UH-20%-4.5A-24MOHM

1 2

1

R7767

10K

1%
1/16W
MF-LF

66

OUT

402

2

P1V8_S0_RC

1

C7767

100PF

5%
50V

NOSTUFF

2

CERM
402

F = 1MHZ

CRITICAL

L7760

PIMB042T-SM

NOSTUFF

1

R7760

20.0K

1%
1/16W
MF-LF
402

2

1

R7761

10K

1%
1/16W
MF-LF
402

2

1

C7766

100PF

5%
50V

2

CERM
0402

1

C7762

22UF

20%

6.3V

2

X5R
0603

=PP1V8_S0_REG

1

C7772

22UF

20%

6.3V

2

X5R
0603

1

C7763

0.1UF

10%
25V

2

X5R
402

8

Vout = 1.8V

C

SIZE

B

A

D

B

=PP5V_S4_P1V05TBTS0

8

C7724

1000PF

X7R-CERM

35

35

1

10%
16V

2

0201

IN

OUT

CRITICAL

C7720

22UF

20%

6.3V
X5R

0603

TBT_EN_LC_ISOL

P1V05TBTS0_PGOOD

1

2

5

EN

7

PG

4

SYNCH

SGND

9

10

1

2

VIN

U7720

ISL8014A

QFN

CRITICAL

PGND

11

12

3

VDD

THRM_PAD

17

VFB

LX
LX

NC

A

1.05V TBT S0 Regulator

152S1415

L7720

1.0UH-20%-4.5A-24MOHM

PIMB042T-SM

14

15

8

16

6
13

P1V05TBTS0_SW

SWITCH_NODE=TRUE
DIDT=TRUE

P1V05TBTS0_FB

NC
NC
NC

1 2

CRITICAL

R7720

1/20W

28K

1%

MF

201

<Ra>

R7721

90.9K

1%
1/16W
MF-LF

402

<Rb>

Vout = 0.8V * (1 + Ra / Rb)

6 3

=PP1V05_S0_P1V05TBTREG_R

22UF

1

20%

6.3V
2

X5R

0603

Vout = 1.05V
Max Current = 3A
Freq = 1 MHz

1

C7723

47PF

5%

1

2

1

2

25V

2

NP0-C0G-CERM
0201

CRITICAL

1

C7721

22UF

20%

6.3V

2

X5R
0603

CRITICAL

C7722

80

8

SYNC_MASTER=MASTER

PAGE TITLE

Misc Power Supplies

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

77 OF 132

SHEET

64 OF 80

124578

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8 7 6 5 4 3

NOSTUFF

R7803

0

1 2

5%

4 7

SIA427DJ

4 7

376S0945

CRITICAL

Q7800

SIA427DJ

S

3

CRITICAL

Q7810

SIA427DJ

4 7

CRITICAL

Q7850

SC70-6L

S

G

3

SC70-6L

G

SC70-6L

S

3

C7850

0.01UF

1 2

X7R-CERM

C7800

0.01UF

1 2

G

10%
16V

0402

X7R-CERM

0402

C7810

0.01UF

1 2

X7R-CERM

D

D

10%
16V

D

10%
16V

0402

1

3.3V S4 FET

=PP3V3_S4_P3V3S4FET

8

1

D

=P3V3S4_EN

66

IN

SSM6N37FEAPE

SOT563

2

SG

1

6

D

Q7802

R7802

220K

5%
1/16W
MF-LF

402

2

P3V3S4_EN_L

1

C7809

0.033UF

R7800

5.1K

5%
1/16W
MF-LF

402

1

10%
16V

2

X5R
402

2

P3V3S3_S4

3.3V S3 FET

=PP3V3_S3_P3V3S3FET

8

R7810

47K

1/16W
MF-LF

402

C7811

0.033UF

5%

1

10%
16V

2

X5R
402

P3V3S3_SS

1

6

D

Q7812

SSM6N37FEAPE

SOT563

2

SG

=P3V3S3_EN

66

IN

1

R7812

100K

5%
1/16W
MF-LF

402

2

P3V3S3_EN_L

1 2

5V S3 FET

C

66

IN

=P5VS3_EN

=PP5V_S4_P5VS3FET

8

Q7852

SSM3K15FV

SOD-VESM-HF

1

G S

R7850

47K

1/16W
MF-LF

C7851

0.033UF

5%

402

1

10%
16V

2

X5R
402

P5VS3_SS

1

3

D

2

R7852

100K

5%
1/16W
MF-LF

402

2

P5VS3_EN_L

1 2

1

1

1/16W
MF-LF

402

=PP3V3_S4_FET

=PP3V3_S3_FET

=PP5V_S3_FET

8

3.3V S4 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

3.3V S3 FET

MOSFET SiA427

CHANNEL

RDS(ON)

LOADING

8

5V S3 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

0.7? A (EDP)

8

P-TYPE 8V/5V

26 mOhm @1.8V

3 A (EDP)

SiA427

P-TYPE 8V/5V

26 mOhm @1.8V

3 A (EDP)

5V_SUS FET INPUT FILTER

=PP5V_S5_P5VSUSFET

8

PLACE_NEAR=Q7840.4:5mm

66

IN

=P3V3S0_EN

66

R7843

0

1 2

5%
1/16W
MF-LF

402

66

IN

IN

=P3V3SUS_EN

NO STUFF

C7843

2.2UF

X5R-CERM

=P5VSUS_EN

=PP3V3_S0_P3V3S0FET

8

SSM6N37FEAPE

=PP3V3_S5_P3V3SUSFET

8

Q7802

SSM6N37FEAPE

PP5V_S5_P5VSUSFET_R

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.1 MM

1

VOLTAGE=5V

20%
10V

402

Q7812

2

5

SOT563

Q7842

SSM3K15FV

SOD-VESM-HF

D

SG

3

2

R7832

R7822

100K

5%
1/16W
MF-LF

402

R7842

220K

1/16W
MF-LF

1

47K

5%
1/16W
MF-LF

402

2

P3V3S0_EN_L

3

D

SOT563

5

SG

4

D

1

G S

3

4

1

2

5%

402

P3V3SUS_EN_L

1

2

P5VSUS_EN_L

3.3V SUS FET

C7821

0.033UF

10%
16V
X5R
402

R7820

12K

1 2

5%
1/16W
MF-LF

402

5V SUS FET

C7841

0.033UF

10%
16V
X5R
402

R7840

3.3K

1 2

5%
1/16W
MF-LF

402

3.3V S0 FET

C7831

0.033UF

10%
16V

X5R
402

R7830

33K

1 2

5%
1/16W
MF-LF

402

CRITICAL

Q7820

SIA427DJ

SC70-6L

S

4 7

1

Q7840

SIA413DJ

4 7

CRITICAL

PWRPK-1212-8

3

CRITICAL

SC70-6L

S

3

Q7830

SI7615DN

2

P3V3SUS_SS

1

2

P5VSUS_SS

S

1

2

P3V3S0_SS

1 2 3

G

4

G

G

C7820

0.01UF

1 2

X7R-CERM

C7840

0.01UF

1 2

X7R-CERM

C7830

0.01UF

1 2

10%
16V

X7R-CERM

0402

1

D

=PP3V3_SUS_FET

8

3.3V SUS FET

MOSFET SiA427

CHANNEL

=PP5V_SUS_FET

RDS(ON)

LOADING

8

10%
16V

0402

1

D

5V SUS FET

MOSFET

CHANNEL

=PP3V3_S0_FET

RDS(ON)

LOADING

8

3.3V S0 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

10%
16V

0402

D

5

12

P-TYPE 8V/5V

26 mOhm @1.8V

100? mA (EDP)

SiA413

P-TYPE 12V

29 mOhm @4.5V

2 mA (EDP)

SI7615DN

P-TYPE 20V/12V

5.5 mOhm @4.5V

5.6 A (EDP)

D

C

1.5V S3/S0 FET

=PPVIN_S3_P1V5S3RS0_FET

G

S

PG

5

D

7

6

8

8

P1V5S3RS0FET_GATE

R7801

0

1 2

5%
1/16W
MF-LF

402

P1V5S3RS0FET_GATE_R

1.5V S3/S0 FET

APN 376S0651

5

CRITICAL

D

Q7801

S

1 2 3

SI7108DN

PWRPK-1212-8-HF

4

G

=PP1V5_S3RS0_FET

MOSFET

CHANNEL

RDS(ON)

LOADING

8

SI7108DN

N-TYPE

6 mOhm @4.5V

5 A (EDP)

B

=PP5V_S5_P1V5S3RS0FET

8

1

C7801

0.1UF

20%
10V

2

CERM

402

P1V5CPU_EN

27

IN

B

NO STUFF

C7802

1

1UF

10%
10V

2

X5R

402

2

3

ON

SHDN*

1

VCC

U7801

SLG5AP020

TDFN

CRITICAL

THRM

GND

PAD

4

9

P1V5S3RS0_RAMP_DONE

A

9

OUT

5.0V S0 FET

=PP5V_S4_P5VS0FET

8

1

R7862

220K

5%
1/16W
MF-LF

402

2

P5V0S0_EN_L

Q7865

SSM3K15FV

SOD-VESM-HF

=P5VS0_EN

66

IN

1

G S

3

D

2

R7860

10K

1 2

1/16W
MF-LF

1

C7861

0.033UF

10%
16V

2

X5R
402

5%

402

P5V0S0_SS

6 3

S

1 2 3

CRITICAL

Q7860

SI7615DN

PWRPK-1212-8

G

4

=PP5V_S0_FET

D

5

C7860

0.01UF

1

2

10%
16V

X7R-CERM

0402

SYNC_MASTER=MASTER

PAGE TITLE

5.0V S0 FET

MOSFET

CHANNEL

RDS(ON)

LOADING

Power FETs

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

8

SI7615DN

P-TYPE 20V/12V

5.5 MOHM @4.5V

5 A (EDP)

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

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SIZE

A

D

www.vinafix.vn

D

C

8

66

B

8

S0PGOOD_ISL

R7960

A

S0PGOOD_ISL

R7961

59

OUT

SMC_PM_G2_EN

39 40

IN

MAKE_BASE=TRUE

=PP3V42_G3H_PWRCTL

8

59

24 39 66

=PP3V3_S0_VMON

1

R7951

2

1

R7952

7.15K

1%
1/16W
MF-LF
402

2

66

66

Thresholds:
VDD: 2.734V-3.010V
V2MON: 2.815V-3.099V
V3MON: 0.572V-0.630V
V4MON: 0.572V-0.630V

=PP5V_S0_VMON

6.04K

=PP1V5_S3RS0_VMON

8

66

1

S0PGOOD_ISL

R7970

1%
1/16W
MF-LF

402

2

1/16W
MF-LF

P5V_DIV_VMON

1

S0PGOOD_ISL

15.0K

R7971

1%

402

12.4K

1/16W

2

MF-LF

1/16W

MF-LF

8 7 6 5 4 3

Mobile System Power State Table

SMC_ADAPTER_EN

toggle 3Hz

SMC_PM_G2_ENABLE

X
1
0
1
0
1
0

1

SMC_S4_WAKESRC_EN

1
1
1
1
1
1
1
0
0

PM_SUS_EN

1
1
1
1
1
0 0
0
0
0

PM_SLP_S5_L

1
1
1
0
0

0
0
0

1
1
1
0
0
0
0
0
0 0

3.3V S4 ENABLE

PM_SLP_S5_L:100K pull down on PCH page

PM_SLP_S5_L

18 39

IN

0.1uF

CERM

20%
10V

402

1

2

5

VCC

U7940

74AUP1G3208

SOT891

1

A

3

B

6

C

GND

2

4

44

Y

U7970

6

74LVC1G32

2

SOT891

1

NC

5

3

NC

PM_SUS_EN

MAKE_BASE=TRUE

4

P5V3V3_S4_EN

MAKE_BASE=TRUE

NOSTUFF

R7915

1 2

=P5VSUS_EN
=P3V3SUS_EN

NO STUFF

R7917

0

1 2

5%
1/16W
MF-LF

402

1

C7930

0.1uF

20%
10V

CERM

RESET*

MR*

402

15

3

6

VDD

SOT23-6

GND

2

"WLAN" = ("S3" && "AP_PWR_EN")

SSM6N37FEAPE

SMC_ADAPTER_EN

IN IN

R7933

2

PM_RSMRST_L

PM_RSMRST_L goes to U1800.C21

NC

NOTE: S3 term is guaranteed by S3 pull-up

on open-drain AP_PWR_EN signal.

Q7920

SOT563

=PP3V3_SUS_CNTRL

1

100K

5%
1/16W
MF-LF

402

2

6

D

2

SG

1

18

OUT

NO STUFF

R7929

1/16W
MF-LF

402

1

0

5%

2

18 27 36 39 66

PM_SLP_S3_LPM_SLP_S4_L

1
1
1
0
0
0
0
0

1
0
0
0
0
0
0
0
0

0

5%
1/16W
MF-LF

402

PM_SLP_S3_L:100K pull down in PCH page

8

66

25

24 39 66

IN

61

IN

7

18 27 36 39 66

IN

65

OUT

65

OUT

=PP3V3_S5_PCHPWRGD

8

=PP3V3_S0_SB_PM

8

ALL_SYS_PWRGD

CPUIMVP_PGOOD

AC_EN_L

Q7920

7

SSM6N37FEAPE

PM_SLP_S3_L

SOT563

=TBTAPWRSW_EN
=TBTBPWRSW_EN

=P3V3S4_EN

=P5VS4_EN

S0 ENABLE

PM_SLP_S3_L

CHGR VFRQ Generation

=PP3V42_G3H_CHGR

8
57

Q7931

SSM3K15FV

SOD-VESM-HF

1

G S

PLACE_NEAR=U1800.P12:7mm

6

D

S G

1

3

D

5

SG

4

7

18 27 36 38 39

PM_SLP_S4_L:100K pull down in PCH page

69

OUT

70

OUT

65

OUT

47 59

OUT

R7978

100

1 2

5%
1/16W
MF-LF

402

R7931

100K

5%
1/16W
MF-LF

1 2

402

CHGR_VFRQ

3

D

2

R7950

1/16W
MF-LF

OUT

1

1K

5%

402

2

1

A

U7950

2

B

SMC_DELAYED_PWRGD

35 39 40

PM_WLAN_EN_L

Q7925

SSM6N15AFE

SOT563

2

AP_PWR_EN

=P5VS5_EN

PLACE_NEAR=U7201.20:7mm

R7941

100K

1/16W
MF-LF

P3V3S5_PGOOD

=PP3V3_S5_VMON

8

15.0K

1%
1/16W
MF-LF
402

VMON_3V3_DIV

=PP1V5_S3RS0_VMON

8

PP1V5_S3RS0

=PP1V05_S0_VMON

8

S0PGOOD_ISL

=PP1V05_S0_VMON

8

66

1

S0PGOOD_ISL

10K

R7972

1%

6.04K

1%

1/16W

402

2

MF-LF

402

P1V5_DIV_VMON

1

S0PGOOD_ISL

R7973

1%

15.0K

1%

1/16W

402

2

MF-LF

402

S5 Rail Enables & PGOOD

R7940

100

1 2

5%
1/16W
MF-LF

PLACE_NEAR=U7201.21:7mm

1

5%

402

2

402

S5_PWRGD

MAKE_BASE=TRUE

1

C7942

0.0033UF

10%
50V

2

CERM
402

NO STUFF

OUT

CPUVCORE ENABLE

R7974

0

1 2

5%

PLACE_NEAR=U7400.7:5mm

1/16W
MF-LF

402

1

R7956

150K

1%
1/16W
MF-LF

402

2

R7953

1K

1 2

5%
1/16W
MF-LF

402

R7954

1K

1 2

5%
1/16W
MF-LF

402

R7955

1K

1 2

5%
1/16W
MF-LF

402

Worst-Case Thresholds:

Q2: 0.XXXV
Q3: 0.640V

3.3V w/Divider: 2.345V
Q4: 0.660V

VMON_Q2_BASE

VMON_Q3_BASE

VMON_Q4_BASE

S0PGD_C

NC

NC

S0 Rail PGOOD Circuitry

(ISL Version in development)

=PP3V3_S0_VMON

8

66

0.1uF

CERM

20%
10V

402

1

2

ISL88042IRTEZ

3

V2MON

5

V3MON

6

2

VDD

U7960

TDFN

CRITICAL

GND

4

7

THRM_PAD

C7960

1

2

P1V05_VID_VMON

1

2

P3V3S5_EN

MAKE_BASE=TRUE

S5_PWRGD (old name RSMRST_PWRGD)-->SMC

SMC-->PM_DSW_PWRGD

39

CPUIMVP_VR_ONALL_SYS_PWRGD

=P3V3S5_EN

61

OUT

S0 Rail PGOOD (BJT Version)

ALL_SYS_PWRGD

6

4

Q7950

Q1

5

Q2

8

7

Q3

CRITICAL

2

1

Q4

3

R7957

1/16W
MF-LF

64

64

59

S0PGOOD_ISL

(IPU)

MR*

RST*V4MON

9

353S2310

63

58

1

8

ALL_SYS_PWRGD_R

ASMCC0179

DFN2015H4-8

353S2809

S0PGD_BJT_GND_R

1

100

5%

402

2

P1V5S0_PGOOD

IN

P1V8S0_PGOOD

IN

P5VS4_PGOOD

IN

CPUVCCIOS0_PGOOD

IN

PVCCSA_PGOOD

IN

NC

S0PGOOD_ISL

=PP3V3_S0_PWRCTL

8 9

R7968

1 2

1/16W
MF-LF

NO STUFF

R7965

1 2

1/16W
MF-LF

R7969

1 2

1/16W
MF-LF

R7962

330

1 2

5%
1/16W
MF-LF

402

59

OUT

=PP3V3_S5_PWRCTL

8

66

PLACE_NEAR=U7940.1:2.3mm

39 40

IN

66

SMC_BATLOW_L:100K pull up on SMC page

PM_SLP_SUS_L:100K pull down on PCH page

=PP3V3_SUS_CNTRL

8

66

39 40

18

24 39 66

No stuff C7931, 12ms
Min delay time

U7930 Sense input
threhold is 3.07V

Sus_PGOOD_CT

1

R7967

10K

5%
1/16W
MF-LF

402

2

100

5%

R7966

402

100

1 2

5%
1/16W
MF-LF

100

402

402

5%

100

5%

R7963

402

100

1 2

5%
1/16W
MF-LF

402

ALL_SYS_PWRGD

State

Run (S0)

Sleep (S3AC)

Sleep (S3)

Deep Sleep (S4AC)

Deep Sleep (S4)

Deep Sleep (S5AC)

Deep Sleep (S5)

Battery Off (G3HotAC)

Battery Off (G3Hot)

1

C7970

0.1uF

20%
10V

2

CERM

402

SMC_S4_WAKESRC_EN

MAKE_BASE=TRUE

3.3V/5.0V Sus ENABLE

=PP3V3_S5_PWRCTL

8

PLACE_NEAR=U7940.1:2.3mm

IN

IN

66

C7940

SMC_BATLOW_L

PM_SLP_SUS_L

=PP3V3_S5_PWRCTL

8

PLACE_NEAR=U7930.6:2.3mm

CRITICAL

SENSE

TPS3808G33DBVRG4

4

CT

1

C7931

0.001UF

20%
50V

2

CERM
402

NO STUFF

24 39 66

OUT

18 39 40

3.3V SUS Detect

U7930

6 3

PM_SLP_S4_L

IN

(PM_SLP_S3_R_L)

R7987

2

33K

5%

1/16W

1

MF-LF
402

PLACE_NEAR=U7100.15:6mm

PVCCSA_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7100.15:6mm

57

1

C7987

0.47UF

10%

6.3V

2

CERM-X5R
402

VFRQ Low: Fix Frequency

VFRQ High: Variable Frequency

1

C7950

0.1UF

20%
10V

2

CERM
402

74LVC2G08GT

8

SOT833

7

Y

08

4

R7925

10K

5%
1/16W
MF-LF

1 2

402

2

R7911

5.1K

5%

1/16W

MF-LF

1

402

PLACE_NEAR=U7300.16:6mm

1

C7910

0.47UF

10%

6.3V

2

CERM-X5R
402

R7981

2

20K

5%

1/16W

1

MF-LF

402

PLACE_NEAR=U7600.3:6mm

CPUVCCIOS0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7600.3:6mm

1

C7981

0.47UF

10%

6.3V

2

CERM-X5R
402

PCH S0 PWRGD

PM_S0_PGOOD

Q7925

SSM6N15AFE

SOT563

5

19 24 36

IN

1.2V, 5V, 3.3V, DDR S3 ENABLE

2

R7912

5%

1/16W

MF-LF

1

402

PLACE_NEAR=Q7812.2:6mm

NO STUFF

1

C7912

0.47UF

10%

6.3V

2

CERM-X5R
402

0

R7985

20K

5%
1/16W
MF-LF

1 2

402

2

R7913

0

5%

1/16W

MF-LF

1

402

PLACE_NEAR=Q7842.2:6MM

NO STUFF

1

C7913

0.47UF

10%

6.3V

2

CERM-X5R
402

P1V05S0_EN

PLACE_NEAR=U7770.3:6mm

1

C7984

0.47UF

10%

6.3V

2

CERM-X5R
402

NC

74LVC2G08GT

8

SOT833

5

A

3

SYS_PWROK_R

Y

U7950

6

08

B

4

NC

R7948

0

1 2

5%
1/16W
MF-LF

402

=PP3V3_S3_WLAN

R7926

10K

5%

1/16W
MF-LF

1 2

402

3

D

SG

4

8

SYNC_MASTER=MASTER

PAGE TITLE

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

2

R7914

5%

1/16W
MF-LF

1

402

PLACE_NEAR=U4900.K5:6MM

2

0

R7916

3.3K

5%

1/16W
MF-LF

1

402

PLACE_NEAR=U4900.K5:6MM

P1V2S3_EN

P5VS3_EN

MAKE_BASE=TRUE

P3V3S3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

NO STUFF

1

C7914

0.47UF

10%

6.3V

2

CERM-X5R
402

PM_SLP_S3_R_L

MAKE_BASE=TRUE

R7988

10K

5%
1/16W
MF-LF

1 2

402

P1V5S0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7770.3:6mm

1

C7988

0.47UF

10%

6.3V

2

CERM-X5R
402

R7949

1K

1 2

5%
1/16W
MF-LF

402

NO STUFF

1

C7916

0.47UF

10%

6.3V

2

CERM-X5R
402

2

R7986

5.1K

5%
1/16W
MF-LF

1

402

PLACE_NEAR=U7760.B3:6mm

P1V8S0_EN

MAKE_BASE=TRUE

PLACE_NEAR=U7760.B3:6mm

1

C7986

0.47UF

10%

6.3V

2

CERM-X5R
402

PM_PCH_SYS_PWROK

PM_PCH_APWROK

PM_PCH_PWROK

MAKE_BASE=TRUE

36

PM_WLAN_EN

36

OUT

Power Control 1/ENABLE

Apple Inc.

R

12

TPAD_VBUS_EN

=P5VS3_EN

=P3V3S3_EN

=DDRREG_EN

=P5VS0_EN
=P3V3S0_EN
=PBUSVSENS_EN
=TBT_S0_EN

=P1V8S0_EN

=P1V5S0_EN

(Replaced by TBT_EN_LC_ISOL)

=CPUVCCIOS0_EN
=PVCCSA_EN

18 24 39

OUT

18

OUT

18 25

OUT

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

79 OF 132

SHEET

66 OF 80

124578

OUT

OUT

OUT

OUT

65

OUT

65

OUT

44

OUT

69 70

OUT

64

OUT

64

OUT

63

OUT

58

OUT

SYNC_DATE=MASTER

47

65

65

60

SIZE

D

C

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

SIZE

D

C

B

A

D

D

LCD PANEL INTERFACE (eDP)

PPVOUT_S0_LCDBKLT

7

71 80

LED_RETURN_6

7

71

LED_RETURN_5

7

71

LED_RETURN_4

7

71

LED_RETURN_3

7

71

LED_RETURN_2

7

LCD_HPD

10

OUT

9

OUT

DP_INT_AUX_C_P

9

79

BI

DP_INT_AUX_C_N

9

79

BI

DP_INT_ML_C_P<0>

9

79

C

IN

LCD_PWR_EN

R9010

1/16W
MF-LF

402

1K

5%

1

2

C9009

0.1UF

X7R-CERM

0402

10%
16V

CRITICAL

U9000

FPF1009

MFET-2X2-8IN

ON

2

VIN_1

3

VIN_2

1

2

GND
617

VOUT_1

VOUT_2

THRM

PAD

4

5

8

9

=PP5V_S0_LCD

8

B

LCD Panel HPD & AUX strapping

7

1

R9001

1M

5%
1/20W
MF
201

2

67 79

7

67

79

LCD_HPD_CONN

7

67

A

IN

9

79

IN

9

79

IN

9

79

IN

9

79

IN

9

79

IN

9

79

IN

9

79

IN

1

C9011

0.1UF

10%
16V

2

X7R-CERM
0402

=PP3V3_S0_LCD

DP_INT_AUX_N
DP_INT_AUX_P

DP_INT_ML_C_N<0>

DP_INT_ML_C_P<1>

DP_INT_ML_C_N<1>

DP_INT_ML_C_P<2>

DP_INT_ML_C_N<2>

DP_INT_ML_C_P<3>

DP_INT_ML_C_N<3>

LCD Panel Current XW Short

EDP: 1 A, Refdes: XW9020

PP5VR3V3_SW_LCD_ISNS

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1

C9012

10UF

20%

6.3V

2

X5R
603

NO_XNET_CONNECTION=TRUE

1

R9003

1M

5%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

1

R9002

1M

5%
1/20W
MF
201

2

R9000

XW9020

1 2

0

1 2

C9028

0.1UF

C9029

0.1UF

C9020

C9021

C9022
C9023

C9024
C9025

C9026

C9027

SM

NC_ISNS_LCD_PANELN
NC_ISNS_LCD_PANELP

1/20W

1 2

1 2

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

0.1UF

PP5VR3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

10%
X5R-CERM

10%
X5R-CERM

NO_XNET_CONNECTION=TRUE

MF 2015%

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

16V
0201

16V
0201

16V10%
0201X5R-CERM

16V10%
0201X5R-CERM

FERR-220-OHM

1 2

1

C9001

0.1UF

10%
16V

2

X5R-CERM

0201

7

80

OUT

7

80

OUT

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

NO_XNET_CONNECTION=TRUE

DP_INT_ML_P<0>

67 79

DP_INT_ML_N<0>

67 79

DP_INT_ML_P<1>

67 79

DP_INT_ML_N<1>

67 79

DP_INT_ML_P<2>

67 79

DP_INT_ML_N<2>

67 79

DP_INT_ML_P<3>

67 79

DP_INT_ML_N<3>

67 79

71

71

67 79

67 79

CRITICAL

L9000

0805

C9002

0.1UF

X5R-CERM

0201

BP9000

BEAD-PROBE

BP9001

BEAD-PROBE

BP9002

BEAD-PROBE

BP9003

BEAD-PROBE

BP9004

BEAD-PROBE

BP9005

BEAD-PROBE

BP9006

BEAD-PROBE

BP9007

BEAD-PROBE

LED_RETURN_1

7

LCD_HPD_CONN

7

67

LCD_FSS

DP_INT_AUX_P

7

67 79

DP_INT_AUX_N

7

67 79

BEAD_PROBE=TRUE

DP_INT_ML_P<0>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_N<0>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_P<1>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_N<1>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_P<2>

BEAD_PROBE=TRUE

DP_INT_ML_N<2>

BEAD_PROBE=TRUE

DP_INT_ML_P<3>

67 79

BEAD_PROBE=TRUE

DP_INT_ML_N<3>

67 79

PP5VR3V3_SW_LCD

7

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1

10%
16V

2

SM

NO_XNET_CONNECTION=TRUE

1
SM

1

NO_XNET_CONNECTION=TRUE

SM

1

SM

1

NO_XNET_CONNECTION=TRUE

SM

1

SM

1

NO_XNET_CONNECTION=TRUE

SM

1

SM

1

NO_XNET_CONNECTION=TRUE

C9003

1000PF

100V

X7R-CERM

0603

R9011

1M

1 2

5%

NO_XNET_CONNECTION=TRUE

1/20W

MF

201

R9013

1M

1 2

5%

1/20W

MF

201

R9015

1M

1 2

5%

1/20W

MF

201

R9017

1M

1 2

5%

1/20W

MF

201

1

C9000

10%

1000PF

2

X7R-CERM

R9012

1M

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

R9014

1M

1 2

5%

1/20W

MF

201

NO_XNET_CONNECTION=TRUE

R9016

1M

1 2

5%

1/20W

MF

201

TRUE

R9018

1M

1 2

5%

1/20W

MF

201

100V
0603

10%

NC

1

2

6 3

CRITICAL

J9000

20525-130E-01

F-RT-SM

31

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

33
34
35
36
37
38
39
40
41

32

518S0829

SYNC_MASTER=D1_SENSORS
PAGE TITLE

eDP Display Connector

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/11/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

90 OF 132

SHEET

67 OF 80

124578

www.vinafix.vn

8 7 6 5 4 3

12

D

=PP3V3_S0_DDCMUX

8

R9251

DDC Crossbar

On single-port hosts alias TBTPA_DDC to TBTSNK0_DDC.

DP_TBTPA_DDC_CLK

69

C

OUT

DP_TBTPA_DDC_DATA

69

BI

DP_TBTPB_DDC_CLK

70

OUT

DP_TBTPB_DDC_DATA

70

BI

TBT_DDC_XBAR_EN_L

33

IN

SAI/SBI = 1: INA == OUTA0, INB == OUTB0
SAI/SBI = 0: INA == OUTB0, INB == OUTA0

Only necessary on dual-port hosts.

NEVER SEND AUXCH THROUGH CROSSBAR!

13

VCC

U9200

TS3DS10224

16

ENA

QFN

CRITICAL

1

INA+

2

INA-

14

SAI

10

ENB

3

INB+

4

INB-

12 11

SBI

GND

5

OUTA1+
OUTA1-

OUTA0+
OUTA0-

OUTB1+
OUTB1-

OUTB0+
OUTB0-

PAD

THRM

21

SAO

SBO

20
19

18
17

15

6
7

8
9

1

C9280

0.1UF

20%
10V

2

CERM
402

1

2.2K

1%
1/20W
MF
201

2

R9252

1

2.2K

1%
1/20W
MF
201

2

DP_TBTSNK0_DDC_CLK
DP_TBTSNK0_DDC_DATA

DP_TBTSNK1_DDC_CLK
DP_TBTSNK1_DDC_DATA

R9253

1

2.2K

1%
1/20W
MF
201

2

R9254

1

2.2K

1%
1/20W
MF
201

2

9

IN

9

BI

9

IN

9

BI

D

C

SIZE

B

A

D

B

A

6 3

SYNC_MASTER=MASTER

PAGE TITLE

DDC Crossbar

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=MASTER

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

92 OF 132

SHEET

68 OF 80

124578

www.vinafix.vn

8 7 6 5 4 3

12

PART NUMBER

138S0811

QTY

1

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X5R,0603,MURATA

3.3V/HV Power MUX

V3P3 must be S4 to support

wake from Thunderbolt devices.

=PP3V3_S4_TBTAPWRSW

D

CRITICAL

C9487

100UF

6.3V

POLY-TANT

CASE-B2-SM

OMIT_TABLE

8

20%

8

18.9V Max

CRITICAL

1

2

X5R-CERM-1

C9480

22UF

20%

6.3V
603

1

2

=PPHV_SW_TBTAPWRSW

1

C9415

4.7UF

10%
25V

2

X5R-CERM
0603

66

35

66 70

C9410

0.1UF

=TBTAPWRSW_EN

IN

TBT_A_HV_EN_RC

IN

=TBT_S0_EN

IN

1

C9481

0.1UF

10%
16V

2

X5R-CERM
0201

10%
25V
X5R
402

1

2

C

For 12V systems:

PART NUMBER

118S0145
118S0145

Nominal Min Max

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT_A_D2R_P<0>

7

33 76

OUT

TBT_A_D2R_N<0>

7

33 76

OUT

DP_TBTPA_ML_C_P<3>

33 76

IN

DP_TBTPA_ML_C_N<3>

33 76

B

IN

7

33 76

OUT

7

33 76

OUT

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>

QTY

2
2

DESCRIPTION

RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF

RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF

GND_VOID=TRUE

(Both C’s)

C9474
C9475

C9476
C9477

0.47UF

0.47UF

C9478
C9479

0.47UF

0.47UF

1 2

1 2

GND_VOID=TRUE

0.22UF

0.22UF

GND_VOID=TRUE

(Both C’s)

1 2

1 2

GND_VOID=TRUE

69 76

69 76

Nominal Min Max

IV3P3 1100mA 1030mA 1200mA

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19
20

6
7

RSVD

5

EN

11 10

HV_EN

17

S0

V3P3OUT

V3P3

VHV

CRITICAL

U9410

CD3210A0RGP

QFN

ISET_V3P3

ISET_S0

ISET_S3

GND

123

4

13

TBTHV:P15V

R9413

22.6K

1/20W

201

<RHVS3> <RHVS0>

OUT

RSVD

THRM

1%
MF

PAD

21

1

2

REFERENCE DES

R9410,R9413
R9411,R9414

4V20%

201

CERM-X5R-1

4V

20%

CERM-X5R-1

201

1 2

20%

6.3V

X5R

0201

1 2

20%

6.3V

X5R

0201

TBT_A_BIAS

69

1

R9498

2.2K

5%

1/20W

MF

201

2

GND_VOID=TRUE

4V

20%

CERM-X5R-1

201

20% 4V

CERM-X5R-1

201

DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N

C9498

REFERENCE DES

18

12
14

C9485

1516

8

9

7

76

7

76

DP_TBTPA_ML_P<3>

76

DP_TBTPA_ML_N<3>

76

TBT: Unused

1

R9499

2.2K

5%
1/20W
MF
201

2

GND_VOID=TRUE

TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>

30PF

C0G-CERM

0201

1

0.1UF

10%
16V

2

X5R-CERM

0201

TBTAPWRSW_ISET_V3P3

7

TBTAPWRSW_ISET_S0

7

TBTAPWRSW_ISET_S3

7

12V: See
below

TBTAPWRSW_ISET_S3_R

7

TBTAPWRSW_ISET_S0_R

TBTHV:P15V

1

R9414

22.6K

1%
1/20W
MF
201

2

TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>

NO_XNET_CONNECTION=TRUE

1

5%

25V

2

C9415

1

C9486

10UF

20%

6.3V

2

CERM-X5R
0402

TBTHV:P15V

R9410

22.6K

1/20W

Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

ILIM = 40000 / RISET

CRITICAL

GND_VOID=TRUE

1

R9494

1K

5%

1/20W

MF

201

2

1

C9499

30PF

5%
25V

2

C0G-CERM
0201

CRITICAL

CRITICAL

PP3V3_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PPHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

1

C9411

0.1UF

10%
25V

2

X5R
402

1

1%
MF

201

2

BOM OPTION

TBTHV:P15V

1

R9411

22.6K

1%
1/20W
MF
201

2

BOM OPTION

TBTHV:P12V
TBTHV:P12V

GND_VOID=TRUE

1

R9495

1K

5%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

R9478

R9479

D9498

BAR90-02LRH

D9499

BAR90-02LRH

650NH-5%-0.430MA-0.52OHM

650NH-5%-0.430MA-0.52OHM

470K

470K

CRITICAL

CRITICAL

SIGNAL_MODEL=TBTPINSIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

GND_VOID=TRUE

(Both D’s)

A K

A K

CRITICAL

L9498

NO_XNET_CONNECTION=TRUE

CRITICAL

L9499

NO_XNET_CONNECTION=TRUE

0603

0603

69

1

R9412

36.5K

1%
1/20W
MF
201

2

<RV3P3>

C9400

0.01UF

X7R-CERM

1 2

1 2

TSLP-2-7

TSLP-2-7

12

12

FERR-120-OHM-3A

1 2

1

10%
50V

2

0402

76

76

GND_VOID=TRUE

GND_VOID=TRUE

5%
MF 201

5%
MF 201

1

2

1/20W

1/20W

TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

L9400

0603

C9401

0.01UF

10%
50V
X7R-CERM
0402

DP_TBTPA_AUXCH_C_N

33 76

BI

DP_TBTPA_AUXCH_C_P

33 76

BI

DP_TBTPA_ML_C_P<1>

33 76

IN

DP_TBTPA_ML_C_N<1>

33 76

IN

PP3V3_SW_TBTAPWR

69

33

OUT

PP3V3RHV_SW_TBTAPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

TBTACONN_20_RC

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

TBT Dir

DP Dir

TBT_A_LSRX

Y = B

R9401

1 2

1/20W

69

0.1UF

0.1UF

0.22UF

0.22UF

5

VCC

GND

2

1 2

10% 16V
X5R-CERM0201

1 2

10% 16V
X5R-CERM0201

1 2

20%

6.3V

X5R

0201

1 2

20%

6.3V

X5R

0201

3

1

B

6

C

CRITICAL

U9460

74AUP1T97

1

C9460

0.1UF

10%
16V

2

X5R-CERM
0201

SOT891

C9430
C9431

C9432
C9433

4

Y A

Thunderbolt Connector A

12

5%
MF

201

CRITICAL

B2
B4
B6

B10
B12

B16
B18
B20

514-0836

For J9400 TBT SMT pads
(3, 5, 17 & 19):

SHIELD PINS

J9400

HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
AUX_CHP
AUX_CHN
DP_PWR

SHIELD PINS

S22

S24

S15

S16

MDP-D1

F-RT-TH

PORT B

S20

S21

S12

S13

S14

GND0
ML_LANE0P
ML_LANE0N

GND1
ML_LANE1P
ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

S17

S18

S19

PP3V3_SW_TBTAPWR

C9420

0.1UF

X5R-CERM

SIGNAL_MODEL=TBT_MUX

TBT_A_CIO_SEL

33

IN

DP_AUXIO_EN

25 70

IN

76

DP_TBTPA_AUXCH_N
DP_TBTPA_AUXCH_P

76

DP_TBTPA_DDC_DATA

68

BI

DP_TBTPA_DDC_CLK

68

IN

TBT_A_CONFIG1_BUF

33

OUT

DP_TBTPA_ML_P<1>

76

DP_TBTPA_ML_N<1>

76

TBT_A_LSTX

33

IN

TBT_A_LSRX_UNBUF
TBT_A_DP_PWRDN

33

IN

DP_TBTPA_HPD

33

OUT

B1
B3
B5
B7B8
B9
B11
B13B14
B15
B17
B19

0201

10%
16V

DP Dir

1

2

1

C9421

0.1UF

10%
16V

2

X5R-CERM

0201

R9426

1M

5%

1/20W

MF

201

TBTACONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

(0-18.9V)

TBT Dir

TBT: TX_0

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

1

R9427

10K

5%
1/20W
MF
201

2

1 24

2

7
8

4
5

11
10

14
13

6

1

2

GND_VOID=TRUE

C9405

0.01UF

X5R-CERM

TBT_A_R2D_P<0>

7

76

7

76

TBT_A_R2D_N<0>
TBTACONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

TBT_A_R2D_P<1>

7

76

TBT_A_R2D_N<1>

7

76

CRITICAL

CBTL05023

BIASIN

AUXIO_EN

AUX­AUX+

DDC_DAT
DDC_CLK

CA_DETOUT

DP+
DP-

LSTX
LSRX

DP_PD

HPDOUT

1

10%
25V

2

0201

GND_VOID=TRUE

C9406

0.01UF

X5R-CERM

3
VDD

U9420

HVQFN

GND
9

10%
25V

0201

15

21

R9429

BIASOUT

AUXIO­AUXIO+

CA_DET

DPMLO+
DPMLO-

THMPAD

25

1

2

1

100K

5%

1/20W

MF

201

2

23
22

1816

19
20

1712

HPD

1

R9428

100K

5%
1/20W
MF
201

2

C9470
C9471

GND_VOID=TRUE

1

R9470

470K

5%
1/20W
MF
201

2

C9472
C9473

GND_VOID=TRUE

1

R9472

470K

5%
1/20W
MF
201

2

470k R’s for ESD protection
on AC-coupled signals.

TBT_A_BIAS

VOLTAGE=3.3V

1

C9425

0.1UF

10%
16V

2

X5R-CERM
0201

DP_A_AUXCH_DDC_N
DP_A_AUXCH_DDC_P

TBT: RX_1 Bias Sink

TBT_A_CONFIG1_RC

DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_A_HPD

GND_VOID=TRUE

(Both C’s)

1 2

1 2

GND_VOID=TRUE

1

2

GND_VOID=TRUE

(Both C’s)

1 2

1 2

1

2

20%
X5R

20%
X5R

GND_VOID=TRUE

R9471

470K

5%
1/20W
MF
201

20%
X5R

20%
X5R

GND_VOID=TRUE

GND_VOID=TRUE

R9473

470K

5%
1/20W
MF
201

0.22UF

0.22UF

0.22UF

0.22UF

TBT_A_R2D_C_P<0>

6.3V
0201

TBT_A_R2D_C_N<0>

6.3V
0201

DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBT_A_R2D_C_P<1>

6.3V
0201

TBT_A_R2D_C_N<1>

6.3V
0201

69

69 76

69 76

69

69 76

69 76

69

69 76

69 76

D

C

7

33 76

IN

7

33 76

IN

B

7

33 76

IN

7

33 76

IN

TBT_A_HPD

A

69

TBT_A_CONFIG1_RC

69

TBT_A_CONFIG2_RC

33

OUT

1

R9452

1M

5%

1/20W 1/20W

MF

201

2

1

R9451

1M

5%
MF

201

2

C9494

330PF

10%
16V

X7R-CERM

0201

SIZE

A

D

SYNC_MASTER=J5_MLB_KEPLER

1

C9402

0.01UF

10%
16V

2

X5R-CERM

1

1

1

C9495

330PF

10%
16V

2

2

X7R-CERM
0201

R9441

100K

5%
1/20W
MF
201

2

0201

DP Source must pull
down HPD input with

greater than or equal
to 100K (DPv1.1a).

Sink HPD range:
High: 2.0 - 5.0V

Low: 0 - 0.8V

PAGE TITLE

Thunderbolt Connector A

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=11/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

94 OF 132

SHEET

69 OF 80

124578

www.vinafix.vn

8 7 6 5 4 3

12

D

CRITICAL

C9687

100UF

POLY-TANT

CASE-B2-SM

OMIT_TABLE

6.3V

C

For 12V systems:

PART NUMBER

118S0145
118S0145

Nominal Min Max

IHVS0/S3 1120mA 1090mA 1170mA (12W minimum)

TBT_B_D2R_P<0>

7

33 76

OUT

TBT_B_D2R_N<0>

7

33 76

OUT

DP_TBTPB_ML_C_P<3>

33 76

IN

DP_TBTPB_ML_C_N<3>

33 76

B

IN

7

33 76

OUT

7

33 76

OUT

TBT_B_D2R_P<1>
TBT_B_D2R_N<1>

PART NUMBER

138S0811

V3P3 must be S4 to support

wake from Thunderbolt devices.

=PP3V3_S4_TBTBPWRSW

8

CRITICAL

1

C9680

22UF

X5R-CERM-1

1

C9615

4.7UF

10%
25V

2

X5R-CERM
0603

66

IN

35

IN

66 69

IN

20%

6.3V
603

=TBTBPWRSW_EN
TBT_B_HV_EN_RC
=TBT_S0_EN

20%

2

=PPHV_SW_TBTBPWRSW

8

18V Max

QTY

2
2

QTY

1

DESCRIPTION

CAP,CER,4.7UF,10%,25V,X5R,0603,MURATA

3.3V/HV Power MUX

Nominal Min Max

IV3P3 1100mA 1030mA 1200mA

1

1

C9681

0.1UF

10%
16V

2

2

X5R-CERM
0201

1

C9610

0.1UF

10%
25V

2

X5R
402

DESCRIPTION

RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF

RES,MTL FILM,1/16W,17.8K,1,0201,SMD,LF

GND_VOID=TRUE

(Both C’s)

C9674
C9675

C9676
C9677

0.47UF

0.47UF

C9678
C9679

0.47UF

0.47UF

1 2

1 2

GND_VOID=TRUE

0.22UF

0.22UF

GND_VOID=TRUE

(Both C’s)

1 2

1 2

GND_VOID=TRUE

70 76

70 76

IHVS0 890mA 830mA 930mA (assumes 15V, 12W minimum)
IHVS3 890mA 830mA 930mA (assumes 3S, 9-12.6V, 7.5-11.7W)

19

V3P3

20

6

VHV

7

CD3210A0RGP

RSVD

5

EN

11 10

HV_EN

17

S0

123

TBTHV:P15V

1 2

1 2

TBT_B_BIAS

70

20%
X5R

20%
X5R

201

201

4V20%

4V20%

CERM-X5R-1

CERM-X5R-1

R9698

GND_VOID=TRUE

4V20%

201

CERM-X5R-1

201

4V20%

CERM-X5R-1

DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N

18

V3P3OUT

12

OUT

14

RSVD

ISET_S0

ISET_S3

THRM

PAD

13

1%
MF

201

C9685

1516

8

9

21

1

2

CRITICAL

U9610

QFN

ISET_V3P3

GND

4

R9613

22.6K

1/20W

<RHVS3> <RHVS0>

REFERENCE DES

R9610,R9613
R9611,R9614

TBT_B_D2R_C_P<0>

7

76

TBT_B_D2R_C_N<0>

7

76

DP_TBTPB_ML_P<3>

201

76

DP_TBTPB_ML_N<3>

76

TBT: Unused

1

1

R9699

2.2K

5%

5%
1/20W

MF

MF
201

2

2

GND_VOID=TRUE

TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>

C9698

30PF

C0G-CERM

0201

6.3V
0201

6.3V
0201

2.2K

1/20W

REFERENCE DES

C9615

1

1

0.1UF

10%
16V

X5R-CERM

0201

TBTBPWRSW_ISET_V3P3

7

2

2

TBTBPWRSW_ISET_S0
TBTBPWRSW_ISET_S3

7

12V: See
below

TBTBPWRSW_ISET_S3_R
TBTBPWRSW_ISET_S0_R

7

TBTHV:P15V

1

R9614

22.6K

1%
1/20W
MF
201

2

ILIM = 40000 / RISET

CRITICAL

GND_VOID=TRUE

R9694

1/20W

NO_XNET_CONNECTION=TRUE

1

1

C9699

25V

5%

30PF

5%
25V

2

2

C0G-CERM
0201

CRITICAL

CRITICAL

C9686

10UF

20%

6.3V
CERM-X5R
0402

1

2

TBTHV:P15V

R9610

22.6K

1%

1/20W

MF

201

Single-fault protection
requires two R’s per HV
ISET_Sx with CD3210.
Single R on ISET_V3P3 OK.

GND_VOID=TRUE

1

1

1K

201

R9695

1K

5%
MF

2

5%
1/20W
MF
201

2

NO_XNET_CONNECTION=TRUE

BOM OPTION

PP3V3_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

PPHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

C9611

0.1UF

10%
25V
X5R
402

TBTHV:P15V

1

1

R9611

22.6K

1%
1/20W
MF
201

2

2

BOM OPTION

TBTHV:P12V
TBTHV:P12V

R9678

R9679

D9698

BAR90-02LRH

D9699

BAR90-02LRH

650NH-5%-0.430MA-0.52OHM

650NH-5%-0.430MA-0.52OHM

470K

470K

CRITICAL

CRITICAL

SIGNAL_MODEL=TBTPIN

SIGNAL_MODEL=TBTPIN

GND_VOID=TRUE

(Both D’s)

A K

A K

GND_VOID=TRUE

CRITICAL

L9698

0603

NO_XNET_CONNECTION=TRUE

CRITICAL

L9699

0603

NO_XNET_CONNECTION=TRUE

70

1

R9612

36.5K

1%
1/20W
MF
201

2

<RV3P3>

C9600

0.01UF

X7R-CERM

1 2

1 2

TSLP-2-7

TSLP-2-7

12

12

FERR-120-OHM-3A

1 2

1

10%
50V

2

0402

76

76

GND_VOID=TRUE

GND_VOID=TRUE

5%

5%

1

2

1/20W

201MF

1/20W

201MF

TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N

L9600

0603

C9601

0.01UF

10%
50V
X7R-CERM
0402

DP_TBTPB_AUXCH_C_N

33 76

BI

DP_TBTPB_AUXCH_C_P

33 76

BI

DP_TBTPB_ML_C_P<1>

33 76

IN

DP_TBTPB_ML_C_N<1>

33 76

IN

70

33

OUT

PP3V3RHV_SW_TBTBPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=15V

TBTBCONN_20_RC

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18V

TBT Dir

DP Dir

TBT_B_LSRX

Y = B

R9601

1 2

1/20W

70

0.1UF

0.1UF

0.22UF

0.22UF

5

VCC

GND

2

1 2

16V10%
0201X5R-CERM

1 2

16V10%
0201X5R-CERM

1 2

6.3V

20%

0201

X5R

1 2

6.3V

20%

0201

X5R

3

1

B

6

C

CRITICAL

U9660

74AUP1T97

1

C9660

0.1UF

10%
16V

2

X5R-CERM
0201

SOT891

C9630
C9631

C9632
C9633

4

Y A

Thunderbolt Connector B

12

5%
MF

201

CRITICAL

A2
A4
A6

A10
A12

A16
A18
A20

514-0836

For J9600 TBT SMT pads
(3, 5, 17 & 19):

SHIELD PINS

J9400

HPD
CONFIG1
CONFIG2
GND2
ML_LANE3P
ML_LANE3N
GND4
AUX_CHP
AUX_CHN
DP_PWR

SHIELD PINS

S11S2S23

MDP-D1

F-RT-TH

PORT A

S9

S10

S1

S3S4S5

GND0
ML_LANE0P
ML_LANE0N

GND1
ML_LANE1P
ML_LANE1N

GND3
ML_LANE2P
ML_LANE2N

RETURN

S6S7S8

PP3V3_SW_TBTBPWR

C9620

0.1UF

X5R-CERM

SIGNAL_MODEL=TBT_MUX

TBT_B_CIO_SEL

33

IN

DP_AUXIO_EN

25 69

IN

DP_TBTPB_AUXCH_N

76

DP_TBTPB_AUXCH_P

76

DP_TBTPB_DDC_DATA

68

BI

DP_TBTPB_DDC_CLK

68

IN

TBT_B_CONFIG1_BUF

33

OUT

DP_TBTPB_ML_P<1>

76

76

DP_TBTPB_ML_N<1>
TBT_B_LSTX

33

IN

TBT_B_LSRX_UNBUFPP3V3_SW_TBTBPWR
TBT_B_DP_PWRDN

33

IN

DP_TBTPB_HPD

33

OUT

A1
A3
A5
A7A8
A9
A11
A13A14
A15
A17
A19

0201

10%
16V

DP Dir

1

2

TBT: TX_0

C9621

0.1UF

10%
16V

X5R-CERM

0201

R9626

(0-18.9V)

TBT Dir

(0-18.9V)

TBT: LSX_R2P/P2R (P/N)

TBT: TX_1

1

1

R9627

10K

5%
1/20W

2

MF
201

2

1 24

BIASIN

2

AUXIO_EN

7

AUX-

8

AUX+

4

DDC_DAT

5

DDC_CLK

CA_DETOUT

11

DP+

10

DP-

14

LSTX

13

LSRX

6

DP_PD

HPDOUT

1

1M

5%

1/20W

MF

201

2

TBTBCONN_1_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

TBT_B_R2D_P<0>

7

76

TBT_B_R2D_N<0>

7

76

TBTBCONN_7_C

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=18.9V

TBT_B_R2D_P<1>

7

76

TBT_B_R2D_N<1>

7

76

3
VDD

CRITICAL

U9620

CBTL05023

HVQFN

GND
9

GND_VOID=TRUE

C9605

0.01UF

X5R-CERM

0201

GND_VOID=TRUE

C9606

0.01UF

10%
25V

X5R-CERM

0201

10%
25V

15

21

R9629

100K

1/20W

BIASOUT

AUXIO­AUXIO+

CA_DET

DPMLO+
DPMLO-

HPD

THMPAD

25

1

2

1

2

470k R’s for ESD protection
on AC-coupled signals.

1

5%
MF

201

2

23
22

1816

19
20

1712

GND_VOID=TRUE

1

R9670

470K

5%
1/20W
MF
201

2

GND_VOID=TRUE

1

R9672

470K

5%
1/20W
MF
201

2

1

R9628

100K

5%
1/20W
MF
201

2

C9670

0.22UF

C9671

0.22UF

C9672

0.22UF

C9673

0.22UF

VOLTAGE=3.3V

1

2

(Both C’s)

(Both C’s)

TBT_B_BIAS

C9625

0.1UF

10%
16V
X5R-CERM
0201

DP_B_AUXCH_DDC_N
DP_B_AUXCH_DDC_P

TBT: RX_1 Bias Sink

TBT_B_CONFIG1_RC

DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBT: LSX_A_R2P/P2R (P/N)

TBT_B_HPD

GND_VOID=TRUE

1 2

1 2

GND_VOID=TRUE

GND_VOID=TRUE

1

2

GND_VOID=TRUE

1 2

1 2

GND_VOID=TRUE

GND_VOID=TRUE

1

2

20%
X5R

20%
X5R

R9671

470K

5%
1/20W
MF
201

20%
X5R

20%
X5R

R9673

470K

5%
1/20W
MF
201

TBT_B_R2D_C_P<0>

6.3V
0201

TBT_B_R2D_C_N<0>

6.3V
0201

DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBT_B_R2D_C_P<1>

6.3V
0201

TBT_B_R2D_C_N<1>

6.3V
0201

70

70 76

70 76

70

70 76

70 76

70

70 76

70 76

D

C

7

33 76

IN

7

33 76

IN

B

7

33 76

IN

7

33 76

IN

TBT_B_HPD

A

70

TBT_B_CONFIG1_RC

70

TBT_B_CONFIG2_RC

33

OUT

R9652

1/20W

201

SIZE

A

D

SYNC_MASTER=J5_MLB_KEPLER

1

C9602

0.01UF

10%
16V

2

X5R-CERM

1

1

R9651

1M

1M

5%

5%
1/20W

MF

MF
201

2

2

C9694

330PF

10%
16V

X7R-CERM

0201

1

1

C9695

330PF

10%
16V

2

2

X7R-CERM
0201

1

R9641

100K

5%
1/20W
MF
201

2

0201

DP Source must pull
down HPD input with

greater than or equal
to 100K (DPv1.1a).

Sink HPD range:
High: 2.0 - 5.0V

Low: 0 - 0.8V

PAGE TITLE

Thunderbolt Connector B

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

6 3

SYNC_DATE=11/14/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

96 OF 132

SHEET

70 OF 80

124578

www.vinafix.vn

8 7 6 5 4 3

F9700

3AMP-32V-467

=PPBUS_S0_LCDBKLT

D

8

1 2

603-HF

BOTTOM

PPBUS_S0_LCDBKLT_FUSED

SSM6N15AFE

LCD_BKLT_EN

9

IN

C

BKLT_PLT_RST_L

25

IN

R9753 AND R9757 NEED TO BE 402 PACK FOR LAB ACCESS

7 9

R9753

R9757

IN

LCD_BKLT_PWM

=I2C_BKL_1_SCL

42

=I2C_BKL_1_SDA

42

PPBUS_S0_LCDBKLT_PWR

8

B

71

LCD_BKLT_PWM SHOULD BE KEPT AWAY FROM BOOST CIRCUIT

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

1

R9788

301K

1%
1/16W
MF-LF
402

2

LCDBKLT_EN_DIV

1

R9789

147K

1%
1/16W
MF-LF
402

2

LCDBKLT_EN_L

3

Q9707

SOT563

D

5

SG

4

LCDBKLT_DISABLE

SSM6N15AFE

0

1 2

0

1 2

R9731

1 2

301K

1%
1/16W
MF-LF

402

C9782

0.1UF

10%
16V

X7R-CERM

0402

Q9707

SOT563

1/16W

1/16W

R9715

100K

1%
1/16W
MF-LF

402

1 2

FDC638APZ_SBMS001

4

1

2

6

D

2

SG

1

MF-LF

MF-LF

R9704

0

1 2

5%
1/16W
MF-LF

402

CRITICAL

Q9706

SSOT6-HF

3

4025%

4025%

1 2 5 6

PPBUS_S0_LCDBKLT_PWR

8

71

=PP3V3_S0_BKL_VDDIO

8

NO STUFF

1

C9704

33PF

5%
50V

2

CERM
402

PPBUS S0 LCDBkLT FET

MOSFET

CHANNEL

RDS(ON)

LOADING

PPBUS_SW_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

PLACE_NEAR=U9701.22:3MM

FDC638APZ

P-TYPE

43 mOhm @4.5V

0.715 A (EDP)

80

THERE IS A SENSE RESISTOR BETWEEN
PPBUS_SW_LCDBKLT_PWR
AND PPBUS_SW_BKL
ON THE SENSOR PAGE

PLACE_NEAR=L9710.1:5MM

CRITICAL

1

2

1

C9714

0.01UF

10%
16V

2

X7R-CERM
0402

BKL_ISET
BKL_SCL
BKL_SDA

LVDS_BKL_PWM_RC

TP_BKL_FAULT

7

BKLT_EN

7

(EEPROM should set EN_I_RES=1)

1

R9714

16.2K

1/16W
MF-LF

402

1%

2

I_LED=22.7MA
I_LED=369/Riset

FPWM=19.2KHZ

details in spec

C9712

10UF

10%
25V
X5R
805

PLACE_NEAR=U9701.22:5MM

1

C9710

1UF

10%
25V

2

X5R
603-1

1

R9716

12.7K

1%
1/16W
MF-LF

402

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

=PP5V_S0_BKL

8

*L9710, Q9701, D9701, C9715-C9719 SHOULD ALL BE PLACED NEAR EACH OTHER.

CRITICAL

PLACE_NEAR=L9710.1:3MM

1

C9713

0.1UF

10%
25V

2

X5R
402

PLACE_NEAR=U9701.8:3MM

1

C9711

0.1UF

10%
16V

2

X7R-CERM
0402

VDDIO VLDO

6

GD

1

R9765

10K

5%
1/16W
MF-LF
402

2

5

FSET

20

FILTER

3

ISET

10

11

SDA

2

PWM

7

FAULT

4

EN

PLACE_NEAR=U9701.9:10MM

BKL_FSET

BKL_FLT

PLACE XW9710 AWAY FROM U9701.1 AND U9701.15
ADD VIAS IN TPAD OF U9701

PPBUS_S0_LCDBKLT_PWR_SW SHOULD BE KEPT AS SHORT AS POSSIBLE

82322

U9701

LLP

LP8545SQX-EXTJ

VSYNC

CRITICAL

THRM

GND_L

GND_SW

GND_S

9

1

15

BKL_SGND

22UH-20%-2.4A-0.105OHM

VOLTAGE=12.6V
MIN_LINE_WIDTH=0.5 MM

MIN_NECK_WIDTH=0.25 MM

BKL_FET_CNTL

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.25 MM

VIN

24

BKL_SW

SW

21

BKL_FB

FB

12

BKL_ISEN1

OUT1

13

BKL_ISEN2

OUT2

14

BKL_ISEN3

OUT3SCLK

16

BKL_ISEN4

OUT4

17

BKL_ISEN5

OUT5

18

BKL_ISEN6

OUT6

19

BKL_VSYNC_R

PAD

25

(APN: 353S3376)

PWM RES = 9+3

XW9710

SM

1 2

1 2

DEM8030C-SM

NEED VALUE CHANGES FOR 55V AND 96 LEDS !!!

L9710

PPBUS_S0_LCDBKLT_PWR_SW

MIN_LINE_WIDTH=0.6 MM

152S1527

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm

MIN_NECK_WIDTH=0.25 MM
VOLTAGE=50V

SWITCH_NODE=TRUE

4

1

R9755

10K

5%
1/16W
MF-LF
402

2

5

1 2 3

NEED TO BE CHANGED TO 371S0704

PLACE_NEAR=L9710.2:3MM

CRITICAL

Q9701

SI7308DN

PWRPK-1212-8

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

PLACE_NEAR=L9710.2:3MM

CRITICAL

D9701

POWERDI-123

A K

DFLS260

R9708

63.4K

1%
1/16W
MF-LF

402

R9709

59.0K

1%
1/16W
MF-LF

402

PLACE_NEAR=U9701.12:10MM

PLACE_NEAR=U9701.13:10MM

PLACE_NEAR=U9701.14:10MM

PLACE_NEAR=U9701.16:10MM

PLACE_NEAR=U9701.17:10MM

PLACE_NEAR=U9701.18:10MM

C9715, C9716 SHOULD BE PLACED IN T-BONE. SAME FOR C9718,C9719
C9715, C9716 SHOULD BE PLACED ON TOP SIDE. PLACE C9718,C9719 ON BOTTOM SIDE

1

2

1

2

PLACE_NEAR=D9701.2:5MM

CRITICAL

1

C9715

2.2UF

10%
100V

2

X7R-CERM
1210

PLACE_NEAR=D9701.2:3MM

CRITICAL

1

C9716

2.2UF

10%
100V

2

X7R-CERM
1210

PLACE_NEAR=D9701.2:3MM

CRITICAL

1

C9718

2.2UF

10%
100V

2

X7R-CERM
1210

PLACE_NEAR=D9701.2:5MM

CRITICAL

1

C9719

2.2UF

10%
100V

2

X7R-CERM
1210

1

C9717

1000PF

10%
100V

2

X7R-CERM
0603

PLACE_NEAR=R9708.1:5MM

PPVOUT_S0_LCDBKLT

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.25 MM
VOLTAGE=55V

LCDBKLT:ENG

R9717-R9722 CAN BE 0OHM IN PRODUCTION, ADD BOM OPTION

R9717

10.2

1 2

0.1%

1/16W

TF

402

R9718

10.2

1 2

0.1%

1/16W

TF

402

R9719

10.2

1 2

0.1%

1/16W

TF

402

R9720

10.2

1 2

0.1%

1/16W

TF

402

R9721

10.2

1 2

0.1%

1/16W

TF

402

LCDBKLT:ENG

R9722

10.2

1 2

0.1%

1/16W

TF

402

LCDBKLT:ENG

LCDBKLT:ENG

LCDBKLT:ENG

LCDBKLT:ENG

LED_RETURN_1

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

7

67

OUT

7

67

OUT

7

67

OUT

7

67

OUT

7

67

OUT

7

67

OUT

12

D

7

67 80

C

B

A

PART NUMBER

116S0004

QTY

6

DESCRIPTION

RES,MTL FILM,1/16W,0,5,0402,SMD,LF

6 3

REFERENCE DES

R9717,R9718,R9719,R9720,R9721,R9722

CRITICAL

CRITICAL

BOM OPTION

LCDBKLT:PROD

SYNC_MASTER=J5_MLB_KEPLER

PAGE TITLE

LCD Backlight Driver (LP8545)

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/21/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

97 OF 132

SHEET

71 OF 80

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

12

CPU Signal Constraints

CPU_50S
CPU_55S

LAYER

ALLOW ROUTE
ON LAYER?

*

=50_OHM_SE =50_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=27P4_OHM_SE

*

MINIMUM LINE WIDTH

=50_OHM_SE

=27P4_OHM_SECPU_27P4S

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=50_OHM_SE

=55_OHM_SE=55_OHM_SE

=27P4_OHM_SE =27P4_OHM_SE

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

LAYER

D

SPACING_RULE_SET

CPU_AGTL
CPU_8MIL
CPU_COMP

CPU_ITP =4x_DIELECTRIC

CPU_VCCSENSE

Most CPU signals with impedance requirements are 50-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.

LINE-TO-LINE SPACING

*
*
* ?

=STANDARD

8 MIL

=4X_DIELECTRIC
* ?
*

=6X_DIELECTRIC

WEIGHT

?
?

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

CPU_AGTL?TOP,BOTTOM

CPU_VID

CPU_VREF

LAYER

*
*

LINE-TO-LINE SPACING

=2x_DIELECTRIC

0.457 MM
12 MIL

SOURCE: IVB PLATFORM DG , Tables 205-207

PCI-Express

PCIE_85D

SPACING_RULE_SET

PCIE

CLK_PCIE

LAYER

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF

*

=90_OHM_DIFFCLK_PCIE_90D =90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

LAYER

LINE-TO-LINE SPACING

* ?

MINIMUM LINE WIDTH

=85_OHM_DIFF =85_OHM_DIFF
=90_OHM_DIFF =90_OHM_DIFF

WEIGHT

=6X_DIELECTRIC

=5X_DIELECTRIC

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?*

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF =85_OHM_DIFF=85_OHM_DIFF

C

B

WEIGHT

?
?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

0.1MM0.1MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

CPU Net Properties

ELECTRICAL_CONSTRAINT_SET

DMI_S2N
DMI_S2N
DMI_N2S
DMI_N2S
FDI_DATA PCIE_85D PCIE
FDI_DATA PCIE_85D PCIE
FDI_FSYNC
FDI_LSYNC
FDI_INT CPU_50S
DMI_CLK100M

I125

DMI_CLK100M

I126

CPU_EDP_COMP

I132

CPU_PEG_COMP

I130

CPU_CFG CPU_ITP

I133

XDP_CLK_CPU
XDP_CLK_CPU
XDP_CLK_PCH
XDP_CLK_PCH
DPLL_REF_CLK120M

I138

DPLL_REF_CLK120M

I139

XDP_TDI CPU_50S CPU_ITP
XDP_TDO CPU_50S CPU_ITP
XDP_TMS CPU_50S CPU_ITP
XDP_TCK CPU_50S CPU_ITP
XDP_TRST_L
XDP_BPM CPU_50S CPU_ITP
XDP_BPM_L
XDP_BDRESET_L

I134

XDP_PRDY_L

I135

XDP_PREQ_L

I136

CPU_CATERR_L
CPU_PROC_SEL_L CPU_50S

I115

CPU_PECI
CPU_PROCHOT_L
XDP_CPU_PWRGD
PM_THRMTRIP_L
PM_SYNC CPU_50S
PM_MEM_PWRGD
CPU_PWRGD

I150

CPU_SM_RCOMP

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

I120

CPU_VCCSENSE

I121

CPU_VCCSENSE

I122

CPU_VCCSENSE

I123

CPU_VCCSASENSE CPU_50S

I137

CPU_MEM_VREF CPU_VREF

I140

CPU_MEM_VREF CPU_VREF

I141

PHYSICAL

PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE

CPU_50S
CPU_50S

CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE

CPU_27P4S
CPU_27P4S
CPU_50S
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE

CPU_50S CPU_ITP

CPU_50S CPU_ITP
CPU_50S CPU_ITP
CPU_50S CPU_ITP
CPU_50S CPU_ITP

CPU_50S

CPU_50S CPU_VID
CPU_50S
CPU_50S CPU_ITP
CPU_50S

CPU_50S
CPU_50S
CPU_27P4S
CPU_50S CPU_VID
CPU_50S CPU_VID
CPU_50S CPU_VID
CPU_55S CPU_VID
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S

CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S

NET_TYPE

SPACING

CPU_AGTL
CPU_AGTL
CPU_AGTL

CPU_COMP
CPU_COMP

CLK_PCIE

CPU_AGTL
CPU_AGTL

CPU_AGTL

CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_COMP

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_AGTL

DMI_S2N_P<3:0>
DMI_S2N_N<3:0>
DMI_N2S_P<3:0>
DMI_N2S_N<3:0>
FDI_DATA_P<7:0>
FDI_DATA_N<7:0>

FDI_FSYNC<1..0>

FDI_LSYNC<1..0>
FDI_INT
DMI_CLK100M_CPU_P
DMI_CLK100M_CPU_N

CPU_EDP_COMP
CPU_PEG_COMP
CPU_CFG<17..0>
ITPCPU_CLK100M_P
ITPCPU_CLK100M_N
ITPXDP_CLK100M_P
ITPXDP_CLK100M_N
DPLL_REF_CLK_P
DPLL_REF_CLK_N

XDP_CPU_TDI

XDP_CPU_TDO

XDP_CPU_TMS

XDP_CPU_TCK

XDP_CPU_TRST_L

XDP_BPM_L<3..0>

XDP_BPM_L<7..4>

XDP_DBRESET_L

XDP_CPU_PRDY_L

XDP_CPU_PREQ_L
CPU_CATERR_L

CPU_PROC_SEL_L
CPU_PECI

CPU_PROCHOT_L

XDP_CPU_PWRGD

PM_THRMTRIP_L
PM_SYNC
PM_MEM_PWRGD

CPU_PWRGD
CPU_SM_RCOMP<2..0>

CPU_VIDSOUT

CPU_VIDSCLK

CPU_VIDALERT_L

CPU_VCCSA_VID<1..0>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CPU_VCCIOSENSE_P

CPU_VCCIOSENSE_N

CPU_AXG_SENSE_P

CPU_AXG_SENSE_N

CPU_VCC_VALSENSE_P

CPU_VCC_VALSENSE_N

CPU_AXG_VALSENSE_P

CPU_AXG_VALSENSE_N

CPU_VCCSASENSE

PPCPU_MEM_VREFDQ_A

PPCPU_MEM_VREFDQ_B

7

10 18

7

10 18

7

10 18

7

10 18

7

10 18

7

10 18

10 18

10 18

10 18

7

11 17

7

11 17

10

10

10 24

11 17

11 17

17 24

17 24

11 17

11 17

11 24

11 24

11 24

11 24

11 24

11 24

11 24

11 24 25

11 24

11 24

11 39

11 20

11 20 40

11 39 40 61

24

11 20 40

11 18

11 18 27

11 20 24

11

13 61

13 61

13 61

13 58

13 61

13 61

13 63

13 63

13 61

13 61

10

10

10

10

13 58

10 31

10 31

D

C

B

CPU_MEM_VREF CPU_VREF

I144

CPU_MEM_VREF CPU_VREF

I145

CPU_MEM_VREF CPU_VREF

I146

CPU_MEM_VREF CPU_VREF

I147

I148

I149

XDP_CLK_ITP
XDP_CLK_ITP

CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFCA_B

XDP_CPU_CLK100M_P
XDP_CPU_CLK100M_N

A

6 3

24

24

28 31

29 31

28 31

29 31

SYNC_MASTER=J5_MLB

PAGE TITLE

CPU Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/13/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

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SHEET

72 OF 80

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

12

Memory Bus Constraints

D

MEM_37S

MEM_40S

MEM_72D

MEM_50S

MEM_85D

SPACING_RULE_SET

MEM_CLK2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CMD2CMD

MEM_CMD2MEM

MEM_DATA2DATA

MEM_DATA2MEM

MEM_DQS2MEM

MEM_2OTHER

MEM_DQBL2BL

MEM_DQCH2CH

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

*

=37_OHM_SE =37_OHM_SE =37_OHM_SE

*

*

=72_OHM_DIFF

*

=85_OHM_DIFF

*

LINE-TO-LINE SPACING

* ?

* ?

*

* ?

* ?

*

*

* ?

MINIMUM LINE WIDTH

=4X_DIELECTRIC

=3X_DIELECTRIC

=3X_DIELECTRIC

=2X_DIELECTRIC

=3X_DIELECTRIC

=2X_DIELECTRIC

=3X_DIELECTRIC

=4X_DIELECTRIC

=6X_DIELECTRIC

=4X_DIELECTRIC

=6X_DIELECTRIC

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

MEM_CTRL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*

MEM_*

MEM_*

MEM_CTRLMEM_CTRL

MEM_*

* *

AREA_TYPE

*

AREA_TYPE

*

*

AREA_TYPE

*

AREA_TYPE

=40_OHM_SE

=72_OHM_DIFF

=50_OHM_SE

=85_OHM_DIFF

WEIGHT

?*

?*

?*

?

?

?

SPACING_RULE_SET

MEM_CLK2MEM

SPACING_RULE_SET

MEM_CTRL2MEM

MEM_CTRL2CTRL

SPACING_RULE_SET

MEM_DQS2MEM

SPACING_RULE_SET

MEM_2OTHER

MINIMUM NECK WIDTH

=40_OHM_SE =40_OHM_SE=40_OHM_SE

=72_OHM_DIFF

=50_OHM_SE=50_OHM_SE

=85_OHM_DIFF =85_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD

MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_*_DQ_BYTE*

MEM_*_DQ_BYTE*

MEM_A_DQ_BYTE*

MEM_B_DQ_BYTE*

MEM_A_DQ_BYTE* MEM_B_DQ_BYTE*

MAXIMUM NECK LENGTH

=37_OHM_SE

=72_OHM_DIFF

=50_OHM_SE

MEM_*

MEM_CMD

MEM_*

=SAME

MEM_A_DQ_BYTE*

MEM_B_DQ_BYTE*

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

=STANDARD

=72_OHM_DIFF

=STANDARD =STANDARD

=85_OHM_DIFF

AREA_TYPE

AREA_TYPE

*

*

*

*

*

*

*

SPACING_RULE_SET

MEM_CMD2MEM

MEM_CMD2CMD

SPACING_RULE_SET

MEM_DATA2MEM

MEM_DATA2DATA

MEM_DQBL2BL

MEM_DQBL2BL

MEM_DQCH2CH

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=72_OHM_DIFF

=85_OHM_DIFF

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK
MEM_A_CLK

MEM_A_CNTL

MEM_A_CNTL

I101

MEM_A_CNTL

I102

MEM_A_CNTL

I103

MEM_A_CNTL

I104

MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD

MEM_A_DQ_BYTE0 MEM_50S
MEM_A_DQ_BYTE1 MEM_50S MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3

I105

MEM_A_DQS0

I106

MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7

MEM_B_CLK
MEM_B_CLK

MEM_B_CNTL

I110

MEM_B_CNTL

I111

MEM_B_CNTL

MEM_B_CNTL

I109

NET_TYPE

PHYSICAL

MEM_37S

MEM_37S
MEM_37S

MEM_37S
MEM_37S
MEM_40S
MEM_40S
MEM_40S

MEM_40S

MEM_50S MEM_A_DQ_BYTE2
MEM_50S MEM_A_DQ_BYTE3
MEM_50SMEM_A_DQ_BYTE4
MEM_50SMEM_A_DQ_BYTE5

MEM_50SMEM_A_DQ_BYTE7

MEM_85D
MEM_85D
MEM_85D
MEM_85D

MEM_37S
MEM_37S

MEM_37S

MEM_37S

SPACING

MEM_CLKMEM_72D
MEM_CLKMEM_72D

MEM_CTRL

MEM_CTRL
MEM_CTRL

MEM_CTRL
MEM_CTRL
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMDMEM_40S
MEM_CMD

MEM_A_DQ_BYTE0

MEM_A_DQ_BYTE4
MEM_A_DQ_BYTE5
MEM_A_DQ_BYTE6MEM_50SMEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7

MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQS
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D

MEM_CLKMEM_72D
MEM_CLKMEM_72D

MEM_CTRL
MEM_CTRL

MEM_CTRL

MEM_CTRL

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CKE<1..0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>
MEM_A_A<15..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

MEM_B_CS_L<3..0>

MEM_B_ODT<1..0>

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

12 28 30

7

12 28

7

12 28

7

12 28

7

12 28

7

12 28

7

12 28

7

12 28

7

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 28

12 29 30

12 29 30

12 29 30

12 29 30

12 29 30

12 29 30

D

C

B

DDR3 (Memory Down):

DQ signals should be matched within 0.508mm of associated DQS pair

.

DQS intra-pair matching should be within 0.127mm, no inter-pair matching requirement.
DQS to clock matching should be within [CLK-139.73mm] and [CLK-30.48mm].
CLK intra-pair matching should be within 0.127mm, inter-pair matching should be within 0.508mm.
CONTROL signals should be matched within [CLK-2.54mm] to [CLK+0mm] of CLK pairs.
A/BA/CMD signals should be matched within [CLK-2.54mm] to [CLK+2.54mm] of CLK pairs.
DQ/DQS/A/BA/cmd signal spacing is 4x dielectric, CLK is 5x dielectric.
Maximum length of any signal from die pad to first DRAM device is 139.7mm max, to last DRAM device is 194.31mm max.

SOURCE: Chief River SFF Platform DG, Rev 0.7 (#460452), Section 2.6.3

A

MEM_B_CMD

I108

MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD

MEM_B_DQ_BYTE0 MEM_B_DQ_BYTE0MEM_50S
MEM_B_DQ_BYTE1 MEM_B_DQ_BYTE1MEM_50S
MEM_B_DQ_BYTE2 MEM_B_DQ_BYTE2MEM_50S
MEM_B_DQ_BYTE3 MEM_B_DQ_BYTE3MEM_50S
MEM_B_DQ_BYTE4 MEM_B_DQ_BYTE4MEM_50S
MEM_B_DQ_BYTE5 MEM_B_DQ_BYTE5MEM_50S
MEM_B_DQ_BYTE6 MEM_B_DQ_BYTE6MEM_50S
MEM_B_DQ_BYTE7 MEM_B_DQ_BYTE7MEM_50S

MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7

MEM_CMDMEM_40S

MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_CMDMEM_40S
MEM_CMDMEM_40S

MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D
MEM_DQSMEM_85D

MEM_B_A<15..0>

MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

6 3

12 29 30

12 29 30

12 29 30

12 29 30

12 29 30

7

12 29

7

12 29

7

12 29

7

12 29

7

12 29

7

12 29

7

12 29

7

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

12 29

SYNC_MASTER=J5_MLB

PAGE TITLE

Memory Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/13/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

101 OF 132

SHEET

73 OF 80

124578

SIZE

B

A

D

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8 7 6 5 4 3

Digital Video Signal Constraints

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

12

SPACING

D

SATA Interface Constraints

LAYER

SATA_90D

SATA_37SE

SATA_50SE

SPACING_RULE_SET

SATA

SATA_ICOMP

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

LAYER

*

*

*

*

*

ALLOW ROUTE
ON LAYER?

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

LINE-TO-LINE SPACING

C

USB 2.0 Interface Constraints

LAYER

PCH_USB_RBIAS

USB_85D

SPACING_RULE_SET

USB

USB_RBIAS

SOURCE: HR PLATFORM DESIGN GUIDE, TABLES 191,193

LAYER

USB 3.0 INTERFACE CONSTRAINTS

LAYER

USB3_85D

SPACING_RULE_SET

B

USB3

SOURCE: CR SFF PLATFORM DESIGN GUIDE V0.7, TABLE 4-211, 1X1+

LAYER

System Clock Signal Constraints

CLK_SLOW_55S

CLK_25M_55S

SPACING_RULE_SET

CLK_SLOW

CLK_25M =5x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

*

*

*

*

LAYER

LAYER

=STANDARD =STANDARD

=85_OHM_DIFF

LINE-TO-LINE SPACING

*

ALLOW ROUTE
ON LAYER?

=85_OHM_DIFF

LINE-TO-LINE SPACING

ALLOW ROUTE
ON LAYER?

*

*

LINE-TO-LINE SPACING

* ?

MINIMUM LINE WIDTH

=5:1_SPACING

15 MIL

MINIMUM LINE WIDTH

=4:1_SPACING

15 MIL

MINIMUM LINE WIDTH

=5:1_SPACING

=2x_DIELECTRIC

MINIMUM NECK WIDTH

=90_OHM_DIFF

=50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

=85_OHM_DIFF

WEIGHT

=85_OHM_DIFF

WEIGHT

MINIMUM LINE WIDTH

=55_OHM_SE=55_OHM_SE =55_OHM_SE=55_OHM_SE

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

NOTE: 25MHz system clocks very sensitive to noise.

?*

MAXIMUM NECK LENGTH

=90_OHM_DIFF

=37_OHM_SE=37_OHM_SE

=50_OHM_SE

SATA

=STANDARD =STANDARD

=85_OHM_DIFF

USB

USB3

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=85_OHM_DIFF

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

=85_OHM_DIFF=85_OHM_DIFF

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

=37_OHM_SE

LINE-TO-LINE SPACING

=5:1_SPACING

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

=85_OHM_DIFF

LINE-TO-LINE SPACING

=4:1_SPACING

DIFFPAIR PRIMARY GAP

=85_OHM_DIFF

LINE-TO-LINE SPACING

=5:1_SPACING

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

WEIGHT

WEIGHT

WEIGHT

SATA_HDD_R2D

I257

SATA_HDD_R2D SATA_90D

I259

SATA_HDD_D2R SATA_90D

I258

SATA_HDD_D2R SATA_90D

I260

SATA_HDD_D2R SATA

I261

SATA_HDD_D2R

I262

SATA_HDD_R2D

I264

SATA_HDD_R2D

I263

SATA_HDD_D2R

I265

SATA_HDD_D2R

I266

SATA_HDD_R2D

I267

SATA_HDD_R2D

I268

=90_OHM_DIFF=90_OHM_DIFF

=37_OHM_SE

=50_OHM_SE=50_OHM_SE

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

SATA_HDD_R2D SATASATA_90D
SATA_HDD_R2D SATASATA_90D
SATA_HDD_D2R SATASATA_90D
SATA_HDD_D2R

SATA_HDD_D2R

I232

SATA_HDD_D2R

I233

SATA_HDD_R2D

I234

SATA_HDD_R2D

I235

SATA_90D SATA

SATA_90D

SATA_90D SATA
SATA_90D SATA
SATA_90D SATA
SATA_90D SATA
SATA_90D SATA
SATA_90D SATA

SATA
SATA
SATA

SATASATA_90D

SATA_90D SATA

SATASATA_90D
SATASATA_90D
SATASATA_90D
SATASATA_90D

SATA_HDD_R2D_RDRIN_P
SATA_HDD_R2D_RDRIN_N
SATA_HDD_D2R_RDROUT_P
SATA_HDD_D2R_RDROUT_N
SATA_HDD_D2R_RDRIN_P
SATA_HDD_D2R_RDRIN_N
SATA_HDD_R2D_RDROUT_N
SATA_HDD_R2D_RDROUT_P
SATA_HDD_D2R_RC_P
SATA_HDD_D2R_RC_N
SATA_HDD_R2D_RC_N
SATA_HDD_R2D_RC_P

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N

SATA_SSDRHDD_D2R_P
SATA_SSDRHDD_D2R_N

SATA_SSDRHDD_R2D_P

SATA_SSDRHDD_R2D_N

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

7

37

37

37

37

17 37

17 37

17 37

17 37

37

37

37

37

D

C

=85_OHM_DIFF

=85_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

PCH_SATA3_ICOMP

I213

PCH_SATA_ICOMP

USB_EXTB

I236

USB_EXTB

I237

USB_EXTB
USB_EXTB
USB_HUB2_UP
USB_HUB2_UP
USB_EXTA
USB_EXTA
USB_EXTB
USB_EXTB
USB_EXTC
USB_EXTC
USB_CAMERA
USB_CAMERA
USB_BT
USB_BT
USB_TPAD
USB_TPAD
USB_SMC
USB_SMC
PCH_USB_RBIAS
USB_EXTD

I238

USB_EXTD

I239

USB_EXTA

I245

USB_EXTA

I244

USB_CAMERA

I247

USB_CAMERA

I246

USB_EXTA

I248

USB_EXTA

I249

USB3_EXTB_TX USB3_85D USB3

I220

USB3_EXTB_TX USB3_85D USB3

I221

USB3_EXTB_RX USB3_85D USB3

I222

USB3_EXTB_RX USB3_85D USB3

I223

USB3_EXTA_TX USB3_85D

I230

I229

USB3_EXTA_RX USB3_85D

I228

I231

SATA_50SE
SATA_37SE

USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
PCH_USB_RBIAS
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D
USB_85D

USB3_85DUSB3_EXTA_TX

USB3_85DUSB3_EXTA_RX

SATA_ICOMP
SATA_ICOMP

USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB_RBIAS
USB
USB
USB
USB
USB
USB
USB
USB

USB3
USB3
USB3
USB3

PCH_SATA3COMP

PCH_SATAICOMP
USB_EXTB_XHCI_P

USB_EXTB_XHCI_N
USB_EXTB_EHCI_P
USB_EXTB_EHCI_N
USB_HUB_UP_P
USB_HUB_UP_N
USB_EXTA_P
USB_EXTA_N
USB_EXTB_P
USB_EXTB_N
USB_EXTD_P
USB_EXTD_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_SMC_P
USB_SMC_N
PCH_USB_RBIAS
USB_EXTD_XHCI_P
USB_EXTD_XHCI_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_CAMERA_P
USB_CAMERA_N
USB_LT1_P
USB_LT1_N
USB3_EXTB_TX_P
USB3_EXTB_TX_N
USB3_EXTB_RX_P
USB3_EXTB_RX_N

USB3_EXTA_TX_P
USB3_EXTA_TX_N
USB3_EXTA_RX_P
USB3_EXTA_RX_N

17

17

19 26

19 26

19 26

19 26

19 26

19 26

19 38

19 38

7

26 36

7

26 36

7

32

7

32

7 9

7 9

9

47

9

47

9

39

9

39

19

19 26

19 26

38

38

19 32

19 32

7

38

7

38

19 36

19 36

7

19 36

7

19 36

19 38

7

19 38

7

19 38

7

19 38

36

36

B

A

Clock Net Properties

ELECTRICAL_CONSTRAINT_SET

SYSCLK_CLK32K_RTC

I256

SYSCLK_CLK25M_SB

I255

I254

SYSCLK_CLK25M_ENET

I253

I252

SYSCLK_CLK25M_TBT

I251

I250

CLK_SLOW_55S CLK_SLOW

CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S
CLK_25M_55S

PHYSICAL

NET_TYPE

SPACING

CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M
CLK_25M

SYSCLK_CLK32K_RTC
SYSCLK_CLK25M_SB

SYSCLK_CLK25M_SB_R
SYSCLK_CLK25M_ENET
SYSCLK_CLK25M_ENET_R
SYSCLK_CLK25M_TBT
SYSCLK_CLK25M_TBT_R

17 25

17 25

17

25 33

33

6 3

SYNC_MASTER=J5_MLB_KEPLER

PAGE TITLE

PCH Constraints 1

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=09/21/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

102 OF 132

SHEET

74 OF 80

124578

SIZE

A

D

www.vinafix.vn

8 7 6 5 4 3

LPC Bus Constraints

LAYER

LPC_50S

CLK_LPC_50S

SPACING_RULE_SET

LPC

CLK_LPC

D

SMBus Interface Constraints

SMB_50S

SPACING_RULE_SET

SMB

LAYER

LAYER

LAYER

HD Audio Interface Constraints

LAYER

HDA_50S

SPACING_RULE_SET

HDA

LAYER

SIO Signal Constraints

LAYER

CLK_SLOW_55S

ALLOW ROUTE
ON LAYER?

*

=50_OHM_SE

*

=50_OHM_SE =50_OHM_SE=50_OHM_SE

LINE-TO-LINE SPACING

*

* ?

ALLOW ROUTE
ON LAYER?

*

LINE-TO-LINE SPACING

*

*

*

*

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=50_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE

C

SPACING_RULE_SET

CLK_SLOW

LAYER

LINE-TO-LINE SPACING

*

MINIMUM LINE WIDTH

6 MIL

8 MIL

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

8 MIL

MINIMUM NECK WIDTH

=50_OHM_SE =50_OHM_SE

=50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

=50_OHM_SE

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=50_OHM_SE

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE=50_OHM_SE

MAXIMUM NECK LENGTH

=55_OHM_SE

DIFFPAIR PRIMARY GAP

=STANDARD

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

=STANDARD

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PCH Net Properties

ELECTRICAL_CONSTRAINT_SET

LPC_AD
LPC_FRAME_L
LPC_RESET_L

PCH_LPC_CLK0

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SMBUS_PCH_0_CLK
SMBUS_PCH_0_DATA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

SPI_CLK

SPI_MOSI

SPI_MISO

PCIE_ENET_R2D
PCIE_ENET_R2D
PCIE_ENET_D2R
PCIE_ENET_D2R

NET_TYPE

PHYSICAL

LPC_50S
LPC_50S
LPC_50S

CLK_LPC_50S
CLK_LPC_50S
CLK_LPC_50S

SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S

HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S
HDA_50S

SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55SSPI_CS0
SPI_55S

PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE

LPC
LPC
LPC

CLK_LPC
CLK_LPC
CLK_LPC

SMB
SMB
SMB
SMB
SMB
SMB

HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA

SPI
SPI
SPI
SPI
SPI
SPI
SPI

SPACING

LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L

LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS

SMBUS_PCH_CLK
SMBUS_PCH_DATA
SML_PCH_0_CLK
SML_PCH_0_DATA
SML_PCH_1_CLK
SML_PCH_1_DATA

HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
AUD_SDI_R
HDA_SDOUT
HDA_SDOUT_R

SPI_CLK_R
SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_CS0_R_L
SPI_CS0_L

PCIE_ENET_R2D_C_P
PCIE_ENET_R2D_C_N
PCIE_ENET_D2R_P
PCIE_ENET_D2R_N

7

17 39 41

7

17 39 41

25

19 25

7

25 39

7

25 41

7

17 42

7

17 42

17 42

17 42

17 42

17 42

17 51

17

17 51

17

17

17 51

17 51

51

17 51

17 25

17 41

41

17 41

41

17 41

17 41

41

7

17 36

7

17 36

7

17 36

7

17 36

12

D

C

SPI Interface Constraints

LAYER

SPI_55S

SPACING_RULE_SET

SPI

*

LAYER

*

B

A

ALLOW ROUTE
ON LAYER?

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

8 MIL

PCIE_AP_R2D

I275
I276

I278

I277

PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_R2D
PCIE_AP_D2R
PCIE_AP_D2R

PCIE_AP_D2R
PCIE_AP_D2R
PCIE_AP_D2R
PCIE_AP_D2R

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM NECK WIDTH

=55_OHM_SE =55_OHM_SE=55_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MAXIMUM NECK LENGTH

=55_OHM_SE

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

PCIE_85D
PCIE_85D
PCIE_85D
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE

PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE
PCIE_85D PCIE

PCIE
PCIE
PCIE

PCIE_AP_R2D_P
PCIE_AP_R2D_N
PCIE_AP_R2D_C_P
PCIE_AP_R2D_C_N
PCIE_AP_D2R_P
PCIE_AP_D2R_N

PCIE_AP_D2R_PI_P
PCIE_AP_D2R_PI_N
PCIE_AP_R2D_PI_P
PCIE_AP_R2D_PI_N

7

36

7

36

7

17 36

7

17 36

7

17 36

7

17 36

7

36

7

36

7

36

7

36

B

PCIE_CLK100M_PCH

I253

PCIE_CLK100M_PCH

I254

PCIE_CLK100M_TBT

I262

PCIE_CLK100M_TBT

I261

PCH_CLK96M

I255

PCH_CLK96M

I257

PCH_CLK100M_SATA

I256

PCH_CLK100M_SATA

I259

I258

I260

PCIE_CLK100M_SSD

I279

PCIE_CLK100M_SSD

I280

PCIE_CLK100M_ENET
PCIE_CLK100M_ENET
PCIE_CLK100M_AP
PCIE_CLK100M_AP
PCIE_CLK100M_FW
PCIE_CLK100M_FW
PCIE_CLK100M_EXCARD
PCIE_CLK100M_EXCARD

I263

PCIE_TBT_R2D PCIE_85D

I264

PCIE_TBT_R2D PCIE_85D

I265

I267

I266

I268

I270

I269

CLK_PCIE_90D

CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CLK_PCIE_90D CLK_PCIE
CPU_50S
CPU_50S

CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D

CLK_PCIE_90D
CLK_PCIE_90D

CLK_PCIE_90D
CLK_PCIE_90D
CLK_PCIE_90D

PCIE_85DPCIE_TBT_R2D

CLK_PCIE
CLK_PCIECLK_PCIE_90D

CLK_PCIE
CLK_PCIE

CLK_PCIE
CLK_PCIE
CLK_PCIEPCIE_CLK100M
CLK_PCIECLK_PCIE_90DPCIE_CLK100M
CLK_PCIECLK_PCIE_90D
CLK_PCIECLK_PCIE_90D
CLK_PCIE
CLK_PCIE
CLK_PCIECLK_PCIE_90D
CLK_PCIE
CLK_PCIE
CLK_PCIE

PCIE
PCIE
PCIE
PCIEPCIE_TBT_R2D PCIE_85D
PCIEPCIE_TBT_D2R PCIE_85D
PCIEPCIE_85DPCIE_TBT_D2R
PCIEPCIE_85DPCIE_TBT_D2R
PCIEPCIE_TBT_D2R PCIE_85D

6 3

PCIE_CLK100M_PCH_P
PCIE_CLK100M_PCH_N
PCIE_CLK100M_TBT_P
PCIE_CLK100M_TBT_N
PCH_CLK96M_DOT_P
PCH_CLK96M_DOT_N
PCH_CLK100M_SATA_P
PCH_CLK100M_SATA_N
PCH_CLK14P3M_REFCLK
PCH_CLK33M_PCIIN

PCIE_CLK100M_SSD_P
PCIE_CLK100M_SSD_N
PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_ENET_P
PCIE_CLK100M_ENET_N
PCIE_CLK100M_AP_P
PCIE_CLK100M_AP_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N

PCIE_TBT_R2D_C_P<3..0>
PCIE_TBT_R2D_C_N<3..0>
PCIE_TBT_R2D_P<3..0>
PCIE_TBT_R2D_N<3..0>
PCIE_TBT_D2R_P<3..0>
PCIE_TBT_D2R_N<3..0>
PCIE_TBT_D2R_C_P<3..0>
PCIE_TBT_D2R_C_N<3..0>

7

17

7

17

7

17 33

7

17 33

17

17

7

17

17

17

7

17 25

7 9

17

7 9

17

7 9

17

7 9

17

7

17 36

7

17 36

7

17 36

7

17 36

7 9

17

7 9

17

7

17

7

17

7 9

33

7 9

33

7

33

7

33

7 9

33

7 9

33

7

33

7

33

SYNC_MASTER=J5_MLB

PAGE TITLE

PCH Constraints 2

Apple Inc.

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NOTICE OF PROPRIETARY PROPERTY:

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DisplayPort Signal Constraints
NOTE: DisplayPort Physical/Spacing Constraints provided by Chipset or GPU page.

Thunderbolt SPI Signal Constraints

LAYER

TBT_SPI_55S

SPACING_RULE_SET

LAYER

TBT_SPI

D

Thunderbolt/DP Connector Signal Constraints

LAYER

TBTDP_85D =85_OHM_DIFF

SPACING_RULE_SET

LAYER

TBTDP

NOTE: Thunderbolt high-speed nets are NOT directly assigned to TBTDP_*D physical rules.
TABLE_PHYSICAL_ASSIGNMENT symbols must be used to create the assignments.
Proper differential impedance depends on mDP connector used.
For 514-0637: R2D nets (SMT pins) = 80D, D2R nets (TH pins) = 100D

SOURCE: Bill Cornelius’s Thunderbolt Routing Notes

ALLOW ROUTE
ON LAYER?

*

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

LINE-TO-LINE SPACING

=5x_DIELECTRIC

*

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM LINE WIDTH

WEIGHT

?

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

TBTDP

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM?=7x_DIELECTRIC

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

12

Thunderbolt/DP Net Properties

ELECTRICAL_CONSTRAINT_SET

I308

I309

I305

I304

TBT_A_R2D
TBT_A_R2D

TBT_A_R2D

DP_TBTPA_ML
DP_TBTPA_ML
DP_TBTPA_ML
DP_TBTPA_ML
DP_LSX_ML
DP_LSX_ML

TBT_A_D2R1
TBT_A_D2R1
TBT_A_D2R0
TBT_A_D2R0

TBT_A_D2R1
TBT_A_D2R1
TBT_A_D2R0
TBT_A_D2R0

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL

TBTDP_85D
TBTDP_85D
TBTDP_85DTBT_A_R2D
TBTDP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D

NET_TYPE

SPACING

TBTDP
TBTDP
TBTDP
TBTDP

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

TBTDP
TBTDP
TBTDP
TBTDP

TBTDP
TBTDP
TBTDP
TBTDP

TBT_A_R2D_C_P<1..0>
TBT_A_R2D_C_N<1..0>
TBT_A_R2D_P<1..0>
TBT_A_R2D_N<1..0>

DP_TBTPA_ML_C_P<3..1:2>
DP_TBTPA_ML_C_N<3..1:2>
DP_TBTPA_ML_P<3..1:2>
DP_TBTPA_ML_N<3..1:2>
DP_A_LSX_ML_P<1>
DP_A_LSX_ML_N<1>

TBT_A_D2R_C_P<1>
TBT_A_D2R_C_N<1>
TBT_A_D2R_C_P<0>
TBT_A_D2R_C_N<0>

TBT_A_D2R_P<1>
TBT_A_D2R_N<1>
TBT_A_D2R_P<0>
TBT_A_D2R_N<0>

7

7

7

7

33 69

33 69

69

69

69

69

7

7

7

7

7

7

7

7

33 69

33 69

69

69

69

69

69

69

33 69

33 69

33 69

33 69

D

Digital Video Signal Constraints

HDMI_90D

C

SPACING_RULE_SET

DISPLAYPORT

HDMI

B

LAYER

ALLOW ROUTE
ON LAYER?

*

=85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF =85_OHM_DIFF

*

*
*

LINE-TO-LINE SPACING

=3x_DIELECTRIC
=3x_DIELECTRIC

LAYER

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=85_OHM_DIFF =85_OHM_DIFFDP_85D
=90_OHM_DIFF=90_OHM_DIFF =90_OHM_DIFF

WEIGHT

=90_OHM_DIFF =90_OHM_DIFF =90_OHM_DIFF

?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

SPACING_RULE_SET

DISPLAYPORT

HDMI

LAYER

TOP,BOTTOM
TOP,BOTTOM

DIFFPAIR PRIMARY GAP

LINE-TO-LINE SPACING

=4x_DIELECTRIC
=4x_DIELECTRIC

WEIGHT

?
?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TBT_A_AUXCH
TBT_A_AUXCH
TBT_A_AUXCH
TBT_A_AUXCH

TBT_A_D2R1
TBT_A_D2R1

TBT_A_R2D TBTDP_85D
TBT_A_R2D TBTDP_85D
TBT_A_R2D
TBT_A_R2D

DP_TBTPB_ML DISPLAYPORT
DP_TBTPB_ML
DP_TBTPB_ML DISPLAYPORT
DP_TBTPB_ML DISPLAYPORT
DP_LSX_ML
DP_LSX_ML

TBT_A_D2R0
TBT_A_D2R0
TBT_A_D2R1

I310

TBT_A_D2R1

I311

TBT_A_D2R0
TBT_A_D2R0
TBT_A_D2R1

I306

TBT_A_D2R1

I307

TBT_B_AUXCH
TBT_B_AUXCH DISPLAYPORT
TBT_B_AUXCH DISPLAYPORT
TBT_B_AUXCH DISPLAYPORT

TBT_A_D2R1
TBT_A_D2R1

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
TBTDP_85D
TBTDP_85D

TBTDP_85D
TBTDP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D

TBTDP_85D
TBTDP_85D
TBTDP_85D
TBTDP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
TBTDP_85D
TBTDP_85D

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
TBTDP
TBTDP

TBTDP
TBTDP
TBTDP
TBTDP

DISPLAYPORT

DISPLAYPORT
DISPLAYPORT

TBTDP
TBTDP
TBTDP
TBTDP

TBTDP
TBTDP
TBTDP
TBTDP
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
TBTDP
TBTDP

DP_TBTPA_AUXCH_C_P
DP_TBTPA_AUXCH_C_N
DP_TBTPA_AUXCH_P
DP_TBTPA_AUXCH_N
DP_A_AUXCH_DDC_P
DP_A_AUXCH_DDC_N
TBT_A_D2R1_AUXDDC_P
TBT_A_D2R1_AUXDDC_N

TBT_B_R2D_C_P<1..0>
TBT_B_R2D_C_N<1..0>
TBT_B_R2D_P<1..0>
TBT_B_R2D_N<1..0>

DP_TBTPB_ML_C_P<3..1:2>
DP_TBTPB_ML_C_N<3..1:2>
DP_TBTPB_ML_P<3..1:2>
DP_TBTPB_ML_N<3..1:2>
DP_B_LSX_ML_P<1>
DP_B_LSX_ML_N<1>

TBT_B_D2R_C_P<0>
TBT_B_D2R_C_N<0>
TBT_B_D2R_C_P<1>
TBT_B_D2R_C_N<1>

TBT_B_D2R_P<0>
TBT_B_D2R_N<0>
TBT_B_D2R_P<1>
TBT_B_D2R_N<1>
DP_TBTPB_AUXCH_C_P
DP_TBTPB_AUXCH_C_N
DP_TBTPB_AUXCH_P
DP_TBTPB_AUXCH_N
DP_B_AUXCH_DDC_P
DP_B_AUXCH_DDC_N
TBT_B_D2R1_AUXDDC_P
TBT_B_D2R1_AUXDDC_N

33 69

33 69

69

69

69

69

69

69

7

33 70

7

33 70

7

70

7

70

33 70

33 70

70

70

70

70

Only used on dual-port hosts.

7

70

7

70

7

70

7

70

7

33 70

7

33 70

7

33 70

7

33 70

33 70

33 70

70

70

70

70

70

70

C

B

Thunderbolt IC Net Properties

ELECTRICAL_CONSTRAINT_SET

TBT_SPI_MOSI
TBT_SPI_MISO

A

TBT_SPI_CS_L

6 3

PHYSICAL

DP_85D
DP_85D
DP_85D
DP_85D

TBT_SPI_55STBT_SPI_CLK
TBT_SPI_55S
TBT_SPI_55S
TBT_SPI_55S

NET_TYPE

SPACING

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

TBT_SPI
TBT_SPI
TBT_SPI
TBT_SPI

DP_TBTSRC_ML_C_P<3..0>
DP_TBTSRC_ML_C_N<3..0>
DP_TBTSRC_AUXCH_C_P
DP_TBTSRC_AUXCH_C_N

TBT_SPI_CLK
TBT_SPI_MOSI
TBT_SPI_MISO
TBT_SPI_CS_L

Only used on hosts supporting Thunderbolt video-in

33

33

33

33

SYNC_MASTER=T29_CR

PAGE TITLE

Thunderbolt Constraints

NOTICE OF PROPRIETARY PROPERTY:

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THE POSESSOR AGREES TO THE FOLLOWING:
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12

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_SCL
SMBUS_SMC_5_SDA

D

SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA

SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S
SMB_50S

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

CHGR_CSI
CHGR_CSI

CHGR_CSO
CHGR_CSO

1TO1_DIFFPAIR
1TO1_DIFFPAIR

1TO1_DIFFPAIR
1TO1_DIFFPAIR

C

PHYSICAL

PHYSICAL

NET_TYPE

NET_TYPE

SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB

SPACING

SPACING

SMBUS_SMC_2_S3_SCL
SMBUS_SMC_2_S3_SDA
SMBUS_SMC_1_S0_SCL
SMBUS_SMC_1_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_5_SCL
SMBUS_SMC_5_SDA
SMBUS_SMC_3_SCL
SMBUS_SMC_3_SDA

CHGR_CSI_P
CHGR_CSI_N

CHGR_CSO_P
CHGR_CSO_N

7

39 42

7

39 42

7

39 42

7

39 42

39 42

39 42

39 42

39 42

57

57

57

57

D

C

SIZE

B

A

D

B

A

SYNC_MASTER=J5_MLB

PAGE TITLE

SMC Constraints

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SENSE_1TO1_55S
THERM_1TO1_55S

DIFFPAIR

AUDIODIFF

SPACING_RULE_SET

D

SENSE
THERM
AUDIO

SPACING_RULE_SET

GND

SPACING_RULE_SET

GND_P2MM
PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

GND
GND
GND
GND
GND

C

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_72D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_37S 0.09 MM 100 MIL

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

PCIE_85D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

USB_85D

CPU_27P4S

USB3_85D

*
*

ALLOW ROUTE
ON LAYER?

=1:1_DIFFPAIR
=1:1_DIFFPAIR

LAYER

*

=1:1_DIFFPAIR

*

LAYER

LAYER

LINE-TO-LINE SPACING

=2:1_SPACING

* ?

=2:1_SPACING

* ?

=2:1_SPACING

*

LINE-TO-LINE SPACING

*

LAYER

LINE-TO-LINE SPACING

*
*

MEM_CLK
MEM_CMD

MEM_CTRL

MEM_*_DQ_BYTE*

MEM_DQS

LAYER

ALLOW ROUTE
ON LAYER?

*

*

*

*

*

TOP

BOTTOM

TOP

=STANDARD

0.20 MM

0.20 MM

AREA_TYPE

*
*
*
*
*

MINIMUM LINE WIDTH

=55_OHM_SE
=55_OHM_SE

0.1 MM 0.1 MM

WEIGHT

WEIGHT

WEIGHT

1000
1000

SPACING_RULE_SET

GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM

MINIMUM LINE WIDTH

ISL10

DP_85D

PCIE_85D 0.075 MM

ISL9

ISL10

B

DDR3 Loaded Segment Constraint Relaxations
Alternate single ended and differential impedances between devices.

NET_PHYSICAL_TYPE

Graphics ,SATA Constraint Relaxations
Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

NET_PHYSICAL_TYPE

AREA_TYPE

AREA_TYPE

PHYSICAL_RULE_SET

PHYSICAL_RULE_SET

BGA 100_DIFF_BGADP_85D

SATA_90D

100_DIFF_BGABGA
100_DIFF_BGABGACLK_PCIE_90D

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_50SMEM_37S BGA_MEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_50SBGA_MEMMEM_40S

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MEM_85DMEM_72D BGA_MEM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=55_OHM_SE
=55_OHM_SE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CPU_COMP

CPU_VCCSENSE

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_PCIE

PCIE
SATA
USB3

CLK_PCIE SB_POWER

SATA
USB3

USB

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

0.09 MM 100 MIL

0.09 MM 100 MIL

0.09 MMMEM_85D

0.09 MM

0.1 MM

0.1 MM

0.075 MMUSB3_85D

0.075 MM

=55_OHM_SE
=55_OHM_SE

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR =1:1_DIFFPAIR
=1:1_DIFFPAIR =1:1_DIFFPAIR

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR =1:1_DIFFPAIR=1:1_DIFFPAIR=1:1_DIFFPAIR

10 MM

GND
GND

GND
GND
GND
GND
GNDUSB

SB_POWER
SB_POWER PWR_P2MM
SB_POWER

0.1 MM 0.1 MM

AREA_TYPE

SPACING_RULE_SET

*
*

AREA_TYPE

SPACING_RULE_SET

*
*
*
*
*
*
*
*
*

DIFFPAIR PRIMARY GAP

GND_P2MM
GND_P2MM

GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
GND_P2MM
PWR_P2MM
PWR_P2MM

PWR_P2MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

100 MIL

10 mm

500 MIL
100 MIL0.23 MM
500 MIL

*
*
*
*
*

PHYSICAL_RULE_SET

AUDIODIFF

1:1_DIFFPAIR

THERM_1TO1_55STHERM_1TO1_55S

DIFFPAIR

NET_PHYSICAL_TYPE

AREA_TYPE

AUDIODIFF

1TO1_DIFFPAIR

SENSE_1TO1_55S SENSE_1TO1_55S

DIFFPAIR

0.090 MM

0.090 MM

0.090 MM

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

D1 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET ELECTRICAL_CONSTRAINT_SET

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR THERM_1TO1_55S

I430

SENSE_DIFFPAIR THERM_1TO1_55S

I431

SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR THERM_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S

I432

SENSE_DIFFPAIR

I433

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR SENSE_1TO1_55S

I405

SENSE_DIFFPAIR

I406

SENSE_DIFFPAIR

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S

HDMI_CLK HDMIHDMI_90D

I414

HDMI_CLK HDMIHDMI_90D

I413

HDMI_DATA

I416

HDMI_DATA

I415

NET_TYPE

PHYSICAL

THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S
THERM_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S

SPACING

THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM
THERM

THERM
THERM
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE

HDMIHDMI_90D
HDMIHDMI_90D

CPUTHMSNS_D2_P

CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N

GPUTHMSNS_D_P

GPUTHMSNS_D_N

GPU_TDIODE_P

GPU_TDIODE_N

TBT_THERMD_P

TBT_THERMD_N

DDR3THMSNS_D1_P

DDR3THMSNS_D1_N
CPUVCCIOS0_CS_P
CPUVCCIOS0_CS_N

CPU_VDDQ_SENSE_P
CPU_VDDQ_SENSE_N
ISNS_LCD_PANEL_P
ISNS_LCD_PANEL_N
ISNS_1V35_S3_MEM_P
ISNS_1V35_S3_MEM_N
ISNS_SSD_P
ISNS_SSD_N
ISNS_3V3_S0_SSD_R_P
ISNS_3V3_S0_SSD_R_N
ISNS_WLAN_P
ISNS_WLAN_N
ISNS_LCDBKLT_P
ISNS_LCDBKLT_N

ISNS_TBT_P
ISNS_TBT_N

ISNS_1V35_S3_MEM_R_P

ISNS_1V35_S3_MEM_R_N
VCCSAS0_CS_P
VCCSAS0_CS_N

HDMI_IG_CLK_C_P

HDMI_IG_CLK_C_N

HDMI_IG_DATA_C_P<2..0>
HDMI_IG_DATA_C_N<2..0>

45

45

9

9

45

45

45

45

45

45

45

45

43 63

43 63

13

13

43

43

37 43

37 43

43

43

80

80

43

43

58 80

58 80

D1 Specific Net Properties

PCIE_CLK100M_AP

10

10

7 9

36

7 9

36

7 9

36

7 9

36

PCIE_CLK100M_AP

USB_BT
USB_BT
USB_BT

I434

USB_BT

I435

AUDIO_DIFFPAIR

I358

AUDIO_DIFFPAIR

I357

AUDIO_DIFFPAIR

I360

AUDIO_DIFFPAIR

I359

AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR

SENSE_DIFFPAIR

I421

SENSE_DIFFPAIR SENSE_1TO1_55S

I420

SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
SENSE_DIFFPAIR SENSE_1TO1_55S
SENSE_DIFFPAIR
SENSE_DIFFPAIR

I428

SENSE_DIFFPAIR

I429

SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR
SENSE_DIFFPAIR

I422

SENSE_DIFFPAIR

I423

SENSE_DIFFPAIR

I424

SENSE_DIFFPAIR

I425

SENSE_DIFFPAIR

I426

SENSE_DIFFPAIR

I427

AUDIO_DIFFPAIR

I343

AUDIO_DIFFPAIR

I344

AUDIO_DIFFPAIR

I345

AUDIO_DIFFPAIR

I346

AUDIO_DIFFPAIR

I348

AUDIO_DIFFPAIR

I347

AUDIO_DIFFPAIR

I350

AUDIO_DIFFPAIR

I349

AUDIO_DIFFPAIR

I351

AUDIO_DIFFPAIR

I352

AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR
AUDIO_DIFFPAIR

I361

AUDIO_DIFFPAIR

I362

AUDIO_DIFFPAIR

I397

AUDIO_DIFFPAIR

I398

AUDIO_DIFFPAIR

I399

AUDIO_DIFFPAIR

I400

AUDIO_DIFFPAIR

I401

AUDIO_DIFFPAIR

I402

AUDIO_DIFFPAIR

I403

AUDIO_DIFFPAIR

I404

AUDIO_DIFFPAIR

I438

AUDIO_DIFFPAIR

I439

AUDIO_DIFFPAIR

I440

AUDIO_DIFFPAIR

I441

AUDIO_DIFFPAIR

I445

AUDIO_DIFFPAIR

I444

AUDIO_DIFFPAIR

I443

AUDIO_DIFFPAIR

I442

USB_TPAD
USB_TPAD
USB_HUB USB_85D

I436

USB_HUB USB_85D

I437

DIFFPAIR
DIFFPAIR

DIFFPAIR
DIFFPAIR
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF

NET_TYPE

PHYSICAL

CLK_PCIE_90D
CLK_PCIE_90D
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
USB_85D
USB_85D
USB_85D
USB_85D

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
SENSE_1TO1_55S
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
AUDIODIFF
USB_85D
USB_85D

SPACING

CLK_PCIE
CLK_PCIE

USB
USB
USB
USB

AUDIO
AUDIO

AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
SENSE
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
USB
USB
USB
USB

SB_POWER
SB_POWER
SB_POWER

GND

PCIE_CLK100M_AP_CONN_P
PCIE_CLK100M_AP_CONN_N

CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N

USB_BT_CONN_P
USB_BT_CONN_N
USB_BT_WAKE_P
USB_BT_WAKE_N

SPKRCONN_SL_OUT_P
SPKRCONN_SL_OUT_N

SPKRCONN_SR_OUT_P
SPKRCONN_SR_OUT_N
SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P
SPKRCONN_R_OUT_N

CPUIMVP_ISNSG_P
CPUIMVP_ISNSG_N
CPUIMVP_ISNS1G_P
CPUIMVP_ISNS1G_N

CPUIMVP_ISNS2G_P

CPUIMVP_ISNS2G_N
CPUIMVP_ISUMG_R_P
CPUIMVP_ISUMG_R_N

ISNS_HS_OTHER_P

ISNS_HS_OTHER_N

ISNS_HS_COMPUTING_P

ISNS_HS_COMPUTING_N
CPUIMVP_ISNS_P
CPUIMVP_ISNS_N
CPUIMVP_ISNS1_P
CPUIMVP_ISNS1_N
CPUIMVP_ISNS2_P
CPUIMVP_ISNS2_N
CPUIMVP_ISUM_R_P
CPUIMVP_ISUM_R_N

AUD_LO1_L_P

AUD_LO1_L_N

AUD_LO1_R_P

AUD_LO1_R_N

AUD_LO2_L_P

AUD_LO2_L_N

AUD_LO2_R_P

AUD_LO2_R_N

AUD_MIC_INL_P

AUD_MIC_INL_N

AUD_SPKRAMP_LIN_P

AUD_SPKRAMP_LIN_N

AUD_SPKRAMP_RIN_P

AUD_SPKRAMP_RIN_N

AUD_SPKRAMP_LSUBIN_P

AUD_SPKRAMP_LSUBIN_N

AUD_SPKRAMP_RSUBIN_P

AUD_SPKRAMP_RSUBIN_N

RSUBIN_P

RSUBIN_N

LSUBIN_P

LSUBIN_N
SPKRAMP_LIN_P
SPKRAMP_LIN_N
SPKRAMP_RIN_P
SPKRAMP_RIN_N

HS_MIC_HI_RC

HS_MIC_LO_RC
HS_MIC_HI
HS_MIC_LO

SPKRCONN_L_OUT_P
SPKRCONN_L_OUT_N
SPKRCONN_R_OUT_P

SPKRCONN_R_OUT_N
USB_TPAD_R_P
USB_TPAD_R_N

PU_USBHUB_DN4_P
PU_USBHUB_DN4_N

PP3V3_S5
PP3V3_S0
PP1V5_S3RS0_CPUDDR

GND

57

57

57

57

7

36

7

36

36

36

36

36

7

53 55

7

53 55

7

53 55

7

53 55

7

53 55 78

7

53 55 78

7

53 55 78

7

53 55 78

43

43

43 62

43 62

43 62

43 62

43

43

44

44

44

44

43

43

43 61 62

43 62

43 61 62

43 62

43

43

51 53

51 53

51 53

51 53

51 53

51 53

51 53

51 53

51 54

51 54

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

53

54

54

54

54

7

53 55 78

7

53 55 78

7

53 55 78

7

53 55 78

26 47

26 47

9

9

7 8

7 8

8

D

C

B

Memory Constraint Relaxations

A

Allow 0.127 mm necks for >0.127 mm lines for ARD fanout.

TOP

ALLOW ROUTE
ON LAYER?

LAYER

MEM_72D 6.35 MM

BOTTOM

MEM_85D

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.127 MM

0.1 MM

MAXIMUM NECK LENGTH

6.35 MM

DIFFPAIR PRIMARY GAP

6 3

SIZE

A

D

SYNC_MASTER=J5_MLB

PAGE TITLE

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

Project Specific Constraints

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

108 OF 132

SHEET

78 OF 80

124578

www.vinafix.vn

8 7 6 5 4 3

12

D1 BOARD-SPECIFIC SPACING & PHYSICAL CONSTRAINTS

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

STANDARD

D

55_OHM_SE

LAYER

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

*
* Y

ALLOW ROUTE
ON LAYER?

Y

Y

55_OHM_SE

ALLOW ROUTE
ON LAYER?

Y
Y* =STANDARD

ALLOW ROUTE
ON LAYER?

Y

*

Y =STANDARD =STANDARD

ALLOW ROUTE
ON LAYER?

Y

* =STANDARD

Y =STANDARD

ALLOW ROUTE
ON LAYER?

Y

C

50_OHM_SE
50_OHM_SE

40_OHM_SE
40_OHM_SE

37_OHM_SE
37_OHM_SE

27P4_OHM_SE

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

TOP,BOTTOM

27P4_OHM_SE

LAYER

ALLOW ROUTE
ON LAYER?

72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF
72_OHM_DIFF

85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF
85_OHM_DIFF

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

* N

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

Y
Y
Y

ALLOW ROUTE
ON LAYER?

Y
Y
Y

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=50_OHM_SE

=DEFAULT =DEFAULT

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.090 MM

0.076 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.090 MM

0.070 MM 0.070 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.145 MM

0.105 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.165 MM

0.120 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.265 MM

0.190 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=STANDARD

0.124 MM

0.124 MM

0.140 MM

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=STANDARD

0.089 MM

0.089 MM

0.110 MM

=50_OHM_SE

0.090 MM

0.076 MM

0.090 MM

0.095 MM

0.090 MM

0.095 MM

0.090 MM

0.095 MM

0.1 MM

0.124 MM

0.124 MM

0.140 MM

=STANDARD =STANDARD

0.089 MM

0.089 MM

0.110 MM

BOARD AREAS

NO_TYPE,BGA,BGA_MEM

MAXIMUM NECK LENGTH

10 MM
10 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

MAXIMUM NECK LENGTH

BOARD UNITS
(MIL or MM)

MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0 MM

=DEFAULT =DEFAULT

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARDN*

0.200 MM

0.200 MM

0.120 MM

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD =STANDARD

0.180 MM

0 MM

=STANDARD* Y

=STANDARD=STANDARDY*

=STANDARD

0.200 MM

0.200 MM

0.120 MM

0.180 MM0.180 MM

0.180 MM

0.180 MM0.180 MM

ALLEGRO
VERSION

16.2

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

SPACING_RULE_SET

LAYER

DEFAULT

STANDARD =DEFAULT

P072_SPACE

*
*
*

LINE-TO-LINE SPACING

0.1 MM

0.071 MM

WEIGHT

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

* *

AREA_TYPE

BGA

P072_SPACE

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

D

Stackup-Defined Spacing Rules

WEIGHT

?
?
?

WEIGHT

?
?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

C

J4 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

SPACING_RULE_SET

1:1_SPACING
1:1_SPACING
1:1_SPACING

Note: Outer dielectric is 0.058 mm nominal,
Inner dielectric is 0.053 mm nominal.

SPACING_RULE_SET

1x_DIELECTRIC
1x_DIELECTRIC
1X_DIELECTRIC

LAYER

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

LAYER

TOP,BOTTOM

ISL3,ISL4,ISL9,ISL10

ISL2,ISL5,ISL6,ISL7,ISL8,ISL11

LINE-TO-LINE SPACING

0.1 MM

0.1 MM

0.101 MM

LINE-TO-LINE SPACING

0.058 MM

0.053 MM

0.101 MM

B

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

=100_OHM_DIFF

A

90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF
90_OHM_DIFF

100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF
100_OHM_DIFF

100_DIFF_BGA
100_DIFF_BGA
100_DIFF_BGA

LAYER

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ISL3,ISL4,ISL9,ISL10

ISL2,ISL11
TOP,BOTTOM

LAYER

ISL3,ISL4

ISL9,ISL10

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

LAYER

1:1_DIFFPAIR

ALLOW ROUTE
ON LAYER?

*

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=STANDARD =STANDARD
Y
Y
Y

N
Y
Y
Y

Y
Y

0.081 MM 0.081 MM

0.081 MM

0.099 MM

MINIMUM LINE WIDTH

=STANDARD

0.081 MM

0.090 MM

MINIMUM NECK WIDTH

=STANDARD

0.065 MM 0.065 MM

0.065 MM

0.079 MM

MINIMUM LINE WIDTH

=100_OHM_DIFF =100_OHM_DIFF

0.065 MM

0.079 MM

MINIMUM NECK WIDTH

=100_OHM_DIFF

0.075 MM 0.075 MM

0.075 MM

MINIMUM LINE WIDTH

=STANDARD

0.075 MM

MINIMUM NECK WIDTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARDN

DIFFPAIR PRIMARY GAP

0.200 MM

0.200 MM

0.200 MM 0.200 MM

DIFFPAIR PRIMARY GAP

0.125 MM 0.125 MM

DIFFPAIR PRIMARY GAP

DP_TBT_AUXCH

I64

DP_TBT_AUXCH

I63

DP_TBT_AUXCH

I65

DP_TBT_AUXCH

I67

DP_TBT_ML

I66

DP_TBT_ML

I69

DP_TBT_ML

I68

DP_TBT_ML

I70

DP_TBT_AUXCH

I72

DP_TBT_AUXCH

I71

DP_TBT_AUXCH

I74

DP_TBT_AUXCH

I73

DP_TBT_ML

I75

DP_TBT_ML

I77

DP_TBT_ML

I76

DP_TBT_ML

I78

DP_INT_ML

I62

DP_INT_ML

I61

DP_INT_AUX

I59

DP_INT_AUX

I60

DP_INT_AUX

I57

DP_INT_AUX

I58

DP_INT_ML

I56

DP_INT_ML

I55

DP_INT_ML

I54

DP_INT_ML

I53

USB3_EXTB_RX

I41

USB3_EXTB_RX

I42

USB3_EXTA_RX

I43

USB3_EXTA_RX

I44

USB3_EXTA_TX

I45

USB3_EXTA_TX

I46

USB3_EXTB_TX

I47

USB3_EXTB_TX USB3_85D USB3

I48

0.200 MM0.200 MM

0.200 MM0.200 MM

0.200 MM0.200 MM

=STANDARD=STANDARD

0.200 MM

0.200 MM

0.125 MM0.125 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF=100_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

0.1 MM 0.1 MMY

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D
DP_85D
DP_85D
DP_85D
DP_85D

DP_85D
DP_85D
DP_85D
DP_85D

USB3_85D USB3

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

USB3USB3_85D
USB3USB3_85D
USB3USB3_85D
USB3USB3_85D
USB3USB3_85D
USB3USB3_85D

DP_TBTSNK0_AUXCH_C_P
DP_TBTSNK0_AUXCH_C_N
DP_TBTSNK1_AUXCH_C_P
DP_TBTSNK1_AUXCH_C_N
DP_TBTSNK0_ML_C_P<3..0>
DP_TBTSNK0_ML_C_N<3..0>
DP_TBTSNK1_ML_C_P<3..0>
DP_TBTSNK1_ML_C_N<3..0>
DP_TBTSNK0_AUXCH_P
DP_TBTSNK0_AUXCH_N
DP_TBTSNK1_AUXCH_P
DP_TBTSNK1_AUXCH_N
DP_TBTSNK0_ML_P<3..0>
DP_TBTSNK0_ML_N<3..0>
DP_TBTSNK1_ML_P<3..0>
DP_TBTSNK1_ML_N<3..0>

DP_INT_ML_C_P<3..0>
DP_INT_ML_C_N<3..0>
DP_INT_AUX_C_P
DP_INT_AUX_C_N
DP_INT_AUX_P
DP_INT_AUX_N

DP_INT_ML_P<3..0>
DP_INT_ML_N<3..0>
DP_INT_ML_F_P<3..0>
DP_INT_ML_F_N<3..0>

USB3_EXTB_RX_RC_P
USB3_EXTB_RX_RC_N

USB3_EXTA_RX_F_P
USB3_EXTA_RX_F_N
USB3_EXTA_TX_C_P
USB3_EXTA_TX_C_N
USB3_EXTB_TX_C_P
USB3_EXTB_TX_C_N

6 3

9

33

9

33

9

33

9

33

9

33

9

33

9

33

9

33

33

33

33

33

33

33

33

33

9

67

9

67

9

67

9

67

7

67

7

67

67

67

SYNC_MASTER=J5_MLB

PAGE TITLE

7

36

7

36

7

38

7

38

7

38

7

38

7

36

7

36

PCB Rule Definitions

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

.

SYNC_DATE=07/29/2011

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

109 OF 132

SHEET

79 OF 80

124578

SIZE

B

A

D

www.vinafix.vn

8 7 6 5 4 3

12

LCD Backlight Current Sense (IBLC)

Gain: 500x. EDP: 0.9 A
Rsense: 0.005 (RD200 / XWD200)
V across Rsense: 4.5 mV
SMC AD: 17

D

=PPBUS_SW_BKL

8

OUT

NC_ISNS_LCDBKLTN

2

XWD200

PPBUS_SW_LCDBKLT_PWR

71

IN

Airport X29 Current Sense (IAPC)

Gain: 500x. EDP: 1.06 A
Rsense: 0.005 (RD230 / XWD230)
V across Rsense: 5.3 mV
SMC AD: 22

PP3V3_WLAN_F

7

36 40

OUT

MIN_LINE_WIDTH=0.6 mm

C

MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

XWD230

PP3V3_WLAN_R

36

IN

7

SM

7

1

2

7

SM

7

1

NC_ISNS_LCDBKLTP

=PP3V3_S0_ISNS

8

43 80

LOADISNS:YES

=PP3V3_S0_ISNS

8

43 80

NC_ISNS_WLANN

NC_ISNS_WLANP

LOADISNS:YES

1

CD200

3

V+

UD200

INA211

5

SC70

IN-

4

GND

OUT

REFIN+

2

0.1UF

20%
10V

2

CERM
402

LOADISNS:YES

6

ISNS_LCDBKLT_IOUT

1

RD209

4.53K

1 2

1/20W

PLACE_NEAR=U4900.G1:5MM

LOADISNS:YES

SMC_LCDBKLT_ISENSE

1%

1

MF

CD209

201

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.G1:5MM

LOADISNS:YES

40

OUT

www.qdzbwx.com

1

CD230

3

V+

UD230

INA211

5

SC70

IN-

4

GND

OUT

REFIN+

2

0.1UF

20%
10V

2

CERM
402

LOADISNS:YES

6

ISNS_WLAN_IOUT

1

RD239

4.53K

1 2

1/20W

PLACE_NEAR=U4900.B8:5MM

LOADISNS:YES

201

1%
MF

SMC_X29_ISENSE

1

CD239

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.B8:5MM

LOADISNS:YES

GND_SMC_AVSS

OUT

40

39 40 43 44 80

CPU SA Current Sense (IC2C)

Gain: 500x. EDP: 6 A
Rsense: 0.001 (R7140)
V across Rsense: 6 mV
SMC AD: 13

VCCSAS0_CS_N

58 78

IN

VCCSAS0_CS_P

58 78

IN

LCD Panel Current Sense (ILDC)

Gain: 500x. EDP: 1 A
Rsense: 0.005 (R9020, XW9020)
V across Rsense: 5 mV
SMC AD: 15

NC_ISNS_LCD_PANELN

7

67

NC_ISNS_LCD_PANELP

7

67

=PP3V3_S0_ISNS

8

43 80

LOADISNS:YES

=PP3V3_S0_ISNS

8

43 80

LOADISNS:YES

3

V+

UD210

INA211

5

SC70

IN-

4

GND

2

3

V+

UD220

INA211

5

SC70

IN-

4

GND

2

OUT

OUT

6

1

REFIN+

6

1

REFIN+

1

CD210

0.1UF

20%
10V

2

CERM
402

LOADISNS:YES

ISNS_CPU_SA_IOUT

PLACE_NEAR=U4900.G1:5MM

LOADISNS:YES

1

CD220

0.1UF

20%
10V

2

CERM
402

LOADISNS:YES

ISNS_LCD_PANEL_IOUT

PLACE_NEAR=U4900.B2:5MM

LOADISNS:YES

RD219

4.53K

1 2

1%

1/20W

MF

201

RD229

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_SA_ISENSE

1

CD219

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.G1:5MM

LOADISNS:YES

GND_SMC_AVSSGND_SMC_AVSS

SMC_LCD_PANEL_ISENSE

1

CD229

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.B2:5MM

LOADISNS:YES

GND_SMC_AVSS

OUT

OUT

40

39 40 43 44 80 39 40 43 44 80

40

39 40 43 44 80

D

C

Thunderbolt TBT Current/Voltage Sense (IHSP/VHSP)

Gain: 1000x. EDP: 2.8 A
Rsense: 0.001 (RD240)
V across Rsense: 2.8 mV
SMC AD: 23

=PP1V05_S0_P1V05TBTREG

8

35

B

OUT

=PP1V05_S0_P1V05TBTREG_R

8

64

IN

RD240

0.001

1%
1W
MF

0612

LCD Backlight Voltage Sense (VBLC)

Gain: 0.04434

PPVOUT_S0_LCDBKLT

7

67 71

A

XWD240

1 2

PLACE_NEAR=RD240.1:10 MM

123

ISNS_TBT_N

78

ISNS_TBT_P

78

4

XWD250

1 2

SM

=PP3V3_S0_ISNS

8

43 80

TBTISNS:YES

SM

VOUT_S0_LCDBKLT_XW

LOADISNS:YES

LOADISNS:YES

P1V05TBT_IN

3

V+

UD240

INA212

5

SC70

IN-

4

GND

2

1

RD256

1M

1%
1/16W
MF-LF
402

2

VOUT_S0_LCDBKLT_DIV

1

RD257

46.4K

1%
1/16W
MF-LF
402

2

OUT

REFIN+

PLACE_NEAR=U4900.A8:5MM

LOADISNS:YES

PLACE_NEAR=XWD240.2:10MM

TBTISNS:NO

1

CD240

0.1UF

20%
10V

2

CERM
402

TBTISNS:YES

6

ISNS_TBT_IOUT

1

RD259

4.53K

1 2

1%

1/20W

MF

201

RD248

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=XWD240.2:10MM

TBTISNS:YES

SMC_LCDBKLT_VSENSE

1

CD259

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.A8:5MM

LOADISNS:YES

GND_SMC_AVSS

IVSNS_TBT_IVOUT

RD247

0

1 2

5%

1/20W

MF

201

PLACE_NEAR=U4900.A8:5MM

OUT

40

39 40 43 44 80

RD249

4.53K

1 2

1%

1/20W

MF

201

SMC_TBT_ISENSE

1

CD249

0.22UF

20%

6.3V

2

X5R
0201

PLACE_NEAR=U4900.A8:5MM

GND_SMC_AVSS

OUT

40

39 40 43 44 80

6 3

CPU SA Voltage Sense (VC2C)

Gain: 1x
SMC ADC: 14

=PPVCCSA_S0_REG

8

58

PART NUMBER

117S0008
117S0008

PLACE_NEAR=R7140.1:5 MM

XWD260

SM

1 2

QTY

3
3

DESCRIPTION

RES,MTL FILM,100K,1/16W,0201,SMD,LF

RES,MTL FILM,100K,1/16W,0201,SMD,LF

PLACE_NEAR=U4900.B1:5MM

CPUVCCSA_IN

RD269

4.53K

1 2

1%

1/20W

MF

201

SMC_CPU_SA_VSENSE

PLACE_NEAR=U4900.B1:5MM

1

CD269

0.22UF

20%

6.3V

2

X5R
0201

GND_SMC_AVSS

REFERENCE DES

CD209,CD219,CD229

CD239,CD259

40

OUT

39 40 43 44 80

CRITICAL

BOM OPTION

LOADISNS:NO
LOADISNS:NO

SYNC_MASTER=D1_SENSORS

PAGE TITLE

Power Sensors: Extended

Apple Inc.

R

NOTICE OF PROPRIETARY PROPERTY:

THE INFORMATION CONTAINED HEREIN IS THE

PROPRIETARY PROPERTY OF APPLE INC.

THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED

SYNC_DATE=07/11/2012

DRAWING NUMBER

<SCH_NUM>

REVISION

<E4LABEL>

BRANCH

<BRANCH>

PAGE

132 OF 132

SHEET

80 OF 80

124578

SIZE

B

A

D

www.vinafix.vn