Apple A1286 Schematic RevA.0.0

8 7

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

6

5

4

SCHEM,MBP 15"MLB

08/18/2008

3

REV

? ?

2 1

ZONE

DESCRIPTION OF CHANGE

ECN

?

CK
APPD

DATE

? ?

ENG
APPD

DATE

Date

N/A1

12/12/2007

12/12/2007

N/A4

N/A5

07/22/2008

N/A7

(MASTER)

(MASTER)

10/17/2007

10/17/2007

10/17/2007

01/08/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

03/31/2008

06/18/2008

06/18/2008

12/17/2007

07/22/2008

07/22/2008

07/22/2008

06/18/2008

07/02/2008

07/02/2008

07/01/2008

07/01/2008

07/01/2008

08/14/2008

08/14/2008

08/14/2008

07/01/2008

07/02/2008

07/01/2008

06/18/2008

06/18/2008

07/01/2008

07/22/2008

Page

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54

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55

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56

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57

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58

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59

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60

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61

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62

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64

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90

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

53

Current & Voltage Sensing

54

Current Sensing

55

Thermal Sensors

56

Fan Connectors

57

WELLSPRING 1

58

WELLSPRING 2

59

Sudden Motion Sensor (SMS)

61

SPI ROM

62

AUDIO:CODEC

63

AUDIO: LINE IN

65

AUDIO: HEADPHONE AMP

66

AUDIO:SPEAKER AMP

67

AUDIO: JACKS

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

IMVP6 CPU VCore Regulator

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

75

1.05V / MCP Core Regulator

76

CPU VTT Power Supply

77

Misc Power Supplies

78

Power Control

79

Power FETs

80

NV G96 PCI-E

81

NV G96 Core/FB Power

82

NV G96 Frame Buffer I/F

84

GDDR3 Frame Buffer A (Top)

85

GDDR3 Frame Buffer B (Top)

86

NV G96 GPIO/MIO/Misc

87

G96 GPIOs & Straps

88

NV G96 Video Interfaces

89

GPU (G84M) Core Supply

90

LVDS Display Connector

93

Muxed Graphics Support

94

DisplayPort Connector

95

1.1V / 1V8 FB Power Supply

96

Graphics MUX (GMUX)

97

LCD BACKLIGHT DRIVER

98

LCD Backlight Support

99

Misc Power Supplies

100

CPU/FSB Constraints

101

Memory Constraints

102

MCP Constraints 1

103

MCP Constraints 2

Contents

Sync

SENSOR

SENSOR

SENSOR

M87_MLB

AMASON_M98_MLB

PWRSQNC

SENSOR

CHANG_M98_MLB

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

T18_MLB

M99_MLB

M87_MLB

M99_MLB

M99_MLB

M99_MLB

M99_MLB

M99_MLB

PWRSQNC

PWRSQNC

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

M87_MLB

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

YITE_M98_MLB

YITE_M98_MLB

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

Date

08/14/2008

08/14/2008

08/14/2008

10/17/2007

06/18/2008

05/12/2008

08/14/2008

07/01/2008

07/09/2008

07/09/2008

07/09/2008

07/09/2008

07/09/2008

07/09/2008

12/06/2007

12/10/2007

10/17/2007

01/09/2008

12/13/2007

01/08/2008

12/14/2007

12/14/2007

05/12/2008

05/12/2008

07/10/2008

07/10/2008

07/10/2008

07/10/2008

07/10/2008

07/10/2008

07/09/2008

07/10/2008

10/17/2007

02/25/2008

07/10/2008

07/10/2008

07/10/2008

07/10/2008

07/02/2008

07/02/2008

02/01/2008

02/18/2008

02/18/2008

02/18/2008

02/18/2008

Page

TABLE_TABLEOFCONTENTS_HEAD

91

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92

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93

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94

TABLE_TABLEOFCONTENTS_ITEM

95

TABLE_TABLEOFCONTENTS_ITEM

96

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

104

Ethernet Constraints

105

FireWire Constraints

106

SMC Constraints

107

GPU (G96) Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

Contents Sync

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

M99_MLB

Date

02/18/2008

02/18/2008

02/18/2008

02/18/2008

02/21/2008

01/22/2008

D

C

B

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

(.csa)

Contents Sync

Table of Contents

2

System Block Diagram

3

Power Block Diagram
Power Block Diagram
BOM Configuration

6

JTAG Scan Chain
Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling & VID

13

eXtended Debug Port(MiniXDP)

14

MCP CPU Interface

15

MCP Memory Interface

16

MCP Memory Misc

17

MCP PCIe Interfaces

18

MCP Ethernet & Graphics

19

MCP PCI & LPC

20

MCP SATA & USB

21

MCP HDA & MISC

22

MCP Power & Ground

24

MCP79 A01 Silicon Support

25

MCP Standard Decoupling

26

MCP Graphics Support

28

SB Misc

29

FSB/DDR3/FRAMEBUF Vref Margining

31

DDR3 SO-DIMM Connector A

32

DDR3 SO-DIMM Connector B

33

DDR3 Support

34

Right Clutch Connector

35

ExpressCard Connector

37

Ethernet PHY (RTL8211CL)

38

Ethernet & AirPort Support

39

Ethernet Connector

41

FireWire LLC/PHY (FW643)

42

FireWire Port Power

43

FireWire Ports

45

SATA Connectors

46

External USB Connectors

48

Front Flex Support

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

M98 SMBus Connections

N/A

T18_MLB

T18_MLB

N/A

N/A

DDR

N/A

(MASTER)

(MASTER)

M87_MLB

M87_MLB

M87_MLB

M99_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

AMASON_M98_MLB

T18_MLB

DDR

DDR

DDR

T18_MLB

YITE_M98_MLB

YITE_M98_MLB

SUMA_M98_MLB

SUMA_M98_MLB

SUMA_M98_MLB

SENSOR

SENSOR

SENSOR

CHANG_M98_MLB

AMASON_M98_MLB

CHANG_M98_MLB

T18_MLB

AMASON_M98_MLB

CHANG_M98_MLB

DDR

D

C

B

Page

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A

Schematic / PCB #’s

PART NUMBER

DRAWING

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Mon Aug 18 01:48:34 2008

QTY

1
1

8

DESCRIPTION

SCHEM,FIBBO,M98

PCBF,FIBBO,M98

REFERENCE DES

SCH
PCB

CRITICAL

CRITICAL051-7546
CRITICAL820-2330

BOM OPTION

7 6

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

5

4

3

DRAFTER

ENG APPD

QA APPD

RELEASE

METRIC

MATERIAL/FINISH

NOTED AS

APPLICABLE

DESIGN CK

MFG APPD

DESIGNER

SCALE

NONE

SIZE

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TITLE

SCHEM,MBP 15MLB

DRAWING NUMBER

D

APPLE INC.

051-7546

A

REV.

1

A.0.0

OF

96

SHT

1

8 7

6

U1000

INTEL CPU

2.X OR 3.X GHZ
PENRYN

PG 9

5

U1300

XDP CONN

PG 12

4

3

2 1

FSB

D

PG 13

GPIOs

FSB INTERFACE

64-Bit

800/1067/1333 MHz

MAIN

MEMORY

PG 14

2 UDIMMs

DDR2-800MHZ

DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

J6950

U4900

DC/BATT

PG 60

D

POWER SUPPLY

TEMP SENSOR

CLK

SYNTH

J4510

SATA
Conn

PG 38

HD

J4520

SATA
Conn

PG 38

C

ODD

1.05V/3GHZ.

1.05V/3GHZ.

SATA

PG 19

NVIDIA

MCP79

U1400

J9000

LVDS
CONN

PG 71

J9400

DISPLAY PORT

CONN

PG 71

LVDS OUT

RGB OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

PG 17

UP TO 20 LANES3

PCI-E

PG 16

B

RGMII

PG 17

PCI

(UP TO FOUR PORTS)

PG 18

Misc

PG 24

SPI

PG 20

LPC

PG 18

PWR

CTRL

J4720

Bluetooth

USB

PG 19

4
3 8 9
2

(UP TO 12 DEVICES)

10 5 6 7

SMB

PG 20

HDA

PG 20

PG 40

U6100

SPI

Boot ROM

PG 52

J4700

TRACKPAD/

KEYBOARD

PG 40

DIMM’s

J4710

J4900

IR

PG 40

B,0

BSB

SMC

PG 41

J4710

FanADC

CAMERA

PG 40

SMB

CONN

PG 44

J5650,5600,5610,5611,5660,5720,5730,5750

FAN CONN AND CONTROL

Ser
Prt

J3900,4635,4655

EXTERNAL

USB

Connectors

PG 41

POWER SENSE

PG 45

PG 48,49

J5100

Port80,serial

PG 39

LPC Conn

PG 43

C

B

U6200

U3700

A

J3400 U3900

Mini PCI-E

AirPort

PG 28

8

7 6

GB

E-NET

88E1116

PG 31

E-NET

Conn

PG 33

5

U6301 U6500U6400

Line In

Amp

PG 54

HEADPHONE

Amp Amp

J6800,6801,6802,6803

4

Audio
Codec

PG 53

Audio
Conns

PG 59

Line Out

PG 56PG 55

U6600,6605,6610,6620

Speaker

Amps

PG 57

System Block Diagram

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=12/12/2007

051-7546

SHT

OF

2 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

AC

ADAPTER

IN

3S2P

(9 TO 12.6V)

C

MCP79

SLP_S5#(H17)

SLP_S3#(G17)

U1400

(PAGE 14~22)

B

A

DELAY

DELAY

DELAY

DELAY

DELAY

DCIN(16.5V)

J6950

P5VRIGHT_EN

RC

P1V8S0_EN

RC

MCPDDR_EN

RC

CPUVTTS0_EN

RC

MCPCORES0_EN

RC

M98 POWER SYSTEM ARCHITECTURE

6A FUSE

BATT_POS_F

Q3801

PM_ENET_EN_L

PM_SLP_S3_L

U5705

A

LIO_DCIN_ISENSE

Q7055

CHGR_BGATE

P3V3S3_EN

P5VS3_EN

LIO_S3_EN

Q3805

WOW_EN

PM_ENET_EN

PM_ENET_EN_L

Q3800

WOL_EN
SMC_ADAPTER_EN

P5VS0_EN

(S0)

P3V3S0_EN

(S0)

PBUSVSENS_EN

(S0)

PM_SLP_S3_DELAY_L

(S0)

PM_WLAN_EN_L

RC

DELAY

CHGR_EN

(S5)

ENABLES

VIN

(PAGE 60)
PBUS SUPPLY/
BATTERY CHARGER

ISL6258A

U7000

PPVBAT_G3H_CHGR_R

SMC

U4900

(PAGE 42)

P5V_RT_EN

BKLT_EN

DDRREG_EN

DDRVTT_EN

VOUT

P60

PPVBAT_G3H_CHGR_REG

A

PPBUS_G3H

P1V1GPU_EN

U7859

SMC_PM_G2_EN

(S5)

VIN

U7400

EN/PSV

SC417

(PAGE 64)

ENL

VIN
GOSHAWK6P

U9701

ENA

(PAGE 84)

P1V2ENET_EN

ENETAVDD_EN

VIN

S5
S3

TPS51116
(PAGE 63)

MCPCORES0_EN

P1V05S0_EN

PGOOD

1.8V

0.9V

U7300

PP5V_RT_REG

VOUT

P5V_RT_PGOOD

VOUT

PPVIN_S0_DDRREG_LDO

VLDOIN

VOUT1

VOUT2

D6905

D6905

8A FUSE

U5715

SMC_BATT_ISENSE

IMVP_VR_ON_R

VIN

EN1

1.103V(L/H)

P1V8FB_EN

PPVOUT_S0_LCDBKLT

VIN

RUN2

(PAGE 33)

RUN1

PPDDR_S3_REG

(12A MAX CURRENT)

PPVTT_S0_DDR_LDO

P3V3S5_EN

LTC3407

VOUT1

U3850

VOUT2

MCP_CORE

EN2

EN1

VIN

(PAGE 65)

EN2

1.8V(R/H)

TPS51124

U9500

(PAGE 82)

VOUT2

1.1V

VOUT1

ISL6236

U7500

PPVIN_G3H_P3V42G3H

PBUSB_VSENSE

PPBUS_G3H

PM_GPUVCORE_EN

CPU VCORE

VIN

ISL9504B

VR_ON

VOUT

U7100

PGOOD

(PAGE 61)

VOUT1

VOUT2

PP1V9_ENET_REG

PP1V2_ENET_REG

PP1V1_S0GPU_REG

PP1V8_GPU_REG

VIN

EN0

PGOOD1,2

MCPCPCORE_S0_REG

PP5V_RT_REG

VOUT1

5V

(L/H)

VOUT2

3.3V

(R/H)

TPS51125

U7201

(PAGE 62)

VREG3

P5V3V3_S5_PGOOD

ENABLE

3.425V G3HOT

LT3470

V

Q5315

(PAGE 59)

U5498

GPU VCORE

VIN

ISL6263B

EN_PSV

(PAGE 78)

U5400

A

VR_PWRGD_CLKEN_L
VR_PWRGOOD_DELAY

PP5V_S5_REG
(8A MAX CURRENT)

PP3V3_S5_REG
(5.5A MAX CURRENT)

VOUT

U8900

PGOOD

GPUVCORE_PGOOD

SMC_CPU_VSENSE

V

CPUVCORE_IOUT

Q7920

Q7900

(25A MAX CURRENT)

(5A MAX CURRENT)

U6990

PP3V42_G3H_REG

SMC_GPU_VSENSE

V

A

GPUVCORE_IOUT

PPVCORE_CPU_S0

PP5V_S0_FET

P5VS0_SS

PP5V_S3_FET

P5VS3_SS

Q7910

P3V3S3_SS

Q7930

Q7970

Q3810

PP3V3_S0GPU_FET

P3V3S0_SS

P3V3GPU_SS

P3V3ENET_EN_L

PPVCORE_GPU_REG

(18A MAX CURRENT)

PP3V3_S0_FET

P3V3_ENET_FET

SMC PWRGD

RN5VD30A-F

U5000

(PAGE 43)

CPUVTTS0_EN

PP3V3_S3_FET

S0PGOOD_PWROK

PP5V_S0
PP3V3_S0

PP1V5_S0_REG

SMC_RESET_L

EN_PSV

PP5V_S3

PP3V3_S5

P1V05S0_PGOOD

P5VRIGHT_PGOOD
MCPCORES0_PGOOD
CPUVTTS0_PGOOD

P1V8S0_PGOOD

P1V5S0_PGOOD

RST*

V1
V2
V3

LTC2900

V4

U7870

(PAGE 68)

VIN

VOUT

1.05V

TPS51117

U7600

(PAG 66)

PGOOD

CPUVTTS0_PGOOD

U2830

VR_PWRGD_CLKEN

ALL_SYS_PWRGD

PPCPUVTT_S0_REG

(6A MAX CURRENT)

MCP_PS_PWRGD

U2850

ISL8009

V4

U7750

(PAGE 66)

RSMRST_PWRGD

SMC_ONOFF_L

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

APPLE INC.

MCP79

CK_PWRGD

VRMPWRGD

PWROK

CPUPWRGD(GPIO49)

(PAGE 14~22)

(PAGE 10,11)

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)

PWRBTN#

PLTRST*
RSMRST*

U1400

CPU

PWRGOOD

U1000

RESET*

PP1V05_S5_MCP

SMC

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

PLT_RST*

P17(BTN_OUT)

RST*

U4900

(PAGE 42)

PLT_RST_L

CPU_PWRGD

PM_RSMRST_L

IMVP_VR_ON

PM_PWRBTN_L

SMC_RESET_L

Power Block Diagram

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

SYNC_DATE=12/12/2007

051-7546

3

REV.

OF

96

D

C

B

A

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

C

D

C

B

B

Power Block Diagram

A

8

7 6

5

4

3

SYNC_MASTER=N/A

APPLE INC.

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

SYNC_DATE=N/A

OF

4 96

1

A

REV.

A.0.0

8 7

BOM Variants

BOM NUMBER

630-9334
630-9335
630-9336
630-9337
630-9585
630-9586

D

M98 BOM Groups

PCBA,2.4GHZ,256SAM_VRAM,M98
PCBA,2.4GHZ,256HYN_VRAM,M98
PCBA,2.5GHZ,512SAM_VRAM,M98
PCBA,2.5GHZ,512QIM_VRAM,M98
PCBA,2.8GHZ,512SAM_VRAM,M98
PCBA,2.8GHZ,512QIM_VRAM,M98

BOM GROUP

M98_COMMON
M98_COMMON1
M98_COMMON2
M98_COMMON3

M98_DEBUG

M98_PROGPARTS

BOM GROUP

FB_256_SAMSUNG

FB_256_HYNIX
FB_512_SAMSUNG
FB_512_QIMONDA

BOM NAME

ALTERNATE,COMMON,M98_COMMON1,M98_COMMON2,M98_COMMON3,M98_DEBUG,M98_PROGPARTS

ONEWIRE_PU,ISL6258A,MEMRESET_HW,MEMRESET_MCP,MCP_B02,MCP_PROD,MCPSEQ_SMC

BKLT_PLL_NOT,BMON_ENG,MIKEY,BOOT_MODE_USER,GPUVID_1P00V,MUXGFX

DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_HW,DP_CA_DET_EG_PLD,MCP_CS1_NO

Bar Code Labels / EEE #’s

C

PART NUMBER

826-4393

826-4393

826-4393

QTY

1
1
1
1
1
1

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM

BOM OPTIONS

M98_COMMON,EEE_0ZA,CPU_2_4GHZ,FB_256_SAMSUNG

M98_COMMON,EEE_0ZB,CPU_2_4GHZ,FB_256_HYNIX
M98_COMMON,EEE_0ZC,CPU_2_5GHZ,FB_512_SAMSUNG
M98_COMMON,EEE_0ZD,CPU_2_5GHZ,FB_512_QIMONDA
M98_COMMON,EEE_2NH,CPU_2_8GHZ,FB_512_SAMSUNG
M98_COMMON,EEE_2NJ,CPU_2_8GHZ,FB_512_QIMONDA

BOM OPTIONS

SMC_DEBUG_YES,XDP,LPCPLUS,VREFMRGN

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

BOM OPTIONS

VRAM4,VRAM_256_SAMSUNG

VRAM4,VRAM_256_HYNIX
VRAM4,VRAM_512_SAMSUNG
VRAM4,VRAM_512_QIMONDA

REFERENCE DES

[EEE:0ZA]
[EEE:0ZB]
[EEE:0ZC]
[EEE:0ZD]
[EEE:2NH]
[EEE:2NJ]

CRITICAL

CRITICAL
CRITICAL826-4393
CRITICAL
CRITICAL826-4393
CRITICAL826-4393
CRITICAL

BOM OPTION

EEE_0ZA
EEE_0ZB
EEE_0ZC
EEE_0ZD
EEE_2NH
EEE_2NJ

6

5

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

4

3

2 1

D

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

C

Module Parts

PART NUMBER

337S3639
337S3640
338S0554
338S0570
338S0523
338S0600
338S0563
341S2289

B

A

335S0384
341S2366 CRITICAL
341S2272
341S2384
338S0635
341S2383
337S3641
333S0482 CRITICAL
333S0483

333S0472

PART NUMBER

138S0603

353S1681

152S0276 152S0683

152S0876 152S0867

157S0058

353S2312

514-0613

152S0915

ALTERNATE FOR
PART NUMBER

138S0602

353S1294

341S2366341S2367

157S0055

353S1466

514-0607514-0612

514-0608

152S0796

QTY

1
1
1

IC,GPU,55nm,NV G96-GS,BGA969,LF

1

IC,RTL8211CL,GIGE TRANSCEIVER,48P TQFP

1
1
1
1
1
1
1
1
1
1
1
4
4
4
4

BOM OPTION

DESCRIPTION

IC,PDC,SLB4N,PRQ,2.4G,25W,1066,M0,3M,BGA

IC,PDC,SL3BX,PRQ,2.53G,35W,1066,C0,6M,BGA

IC,FW643-06,1394B PHY/OHCI LINK/PCI-E,12

IC,GMCP,MCP79-B01,35x35MM,BGA1437

IC,SMC,HS8/2117,9MMX9MM,TLP

IC,SMC,DEVELOPMENT,M98

IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8

IC,EFI ROM,DEVELOPMENT,M98

IC,HDCP ROM,NVG96, 8 PIN SOIC,LF,HF

IR,ENCORE II, CY7C63803-LQXC

IC,GMCP,MCP79-B02,35x35MM,BGA1437

IC,PSOC +W/USB,56PIN,MLF,M98

IC,PDC,SLB43,PRQ,2.8G,35W,1066,C0,6M,BGA

IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA

IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

REF DES

ALL

ALL

ALL

ALL

ALL

ALL

ALL INTERSIL ALT TO INTERSIL

ALL

ALL

ALL

COMMENTS:

Murata alt to Samsung

LMV2011,OPAMP. GBW

Maglayers alt to Dale/Vishay

Macronix alt to SST

Maglayer alt to Delta

Delta alt to TDK Magnetics

FOXLINK XCVR ALT TO FOXCONN

FOXLINK RCVR ALT TO FOXCONN

Maglayers alt to Cyntec IND

REFERENCE DES

U1000
U1000
U8000
U3700
U4100
U1400
U4900
U4900
U6100
U6100
U8770
U4800
U1400
U5701

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL
CRITICAL333S0481
CRITICAL

BOM OPTION

CPU_2_4GHZ
CPU_2_5GHZ

MCP_B01

SMC_BLANK

SMC_PROG

BOOTROM_BLANK

BOOTROM_PROG

HDCP_YES

MCP_B02

TPAD_PROG

CPU_2_8GHZU1000

VRAM_256_SAMSUNG

VRAM_256_HYNIX
VRAM_512_SAMSUNG
VRAM_512_QIMONDA

BOM Configuration

SYNC_MASTER=N/A

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7546

SHT

SYNC_DATE=N/A

OF

5 96

B

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

=PP3V3_S0_XDP

13

8

6

D

62 13 12

C

11

10

8

=PP1V05_S0_CPU

JTAG_ALLDEV

R0601

1/16W
MF-LF

NOSTUFF

R0602

1/16W
MF-LF

10K

402

402

To XDP connector
and/or level translator

XDP

R0603

10

21

XDP_TDO

JTAG_MCP_TDO

1 2

1/16W
MF-LF

402

XDP

R0604

1 2

1/16W
MF-LF

402

PLACEMENT_NOTE=Place near pin U1000.AB3

0

5%

PLACEMENT_NOTE=Place near pin U1400.F19

0

5%

XDP_TDO_CONN

JTAG_MCP_TDO_CONN

OUT

XDP connector

OUT

XDP connector

13

13

21

13

23

21

13

23

21

13

21

13

U1000

CPU

87

U1400

MCP

MAKE_BASE=TRUE

From XDP connector

JTAG_ALLDEV

1

C0601

0.1UF

20%
10V

2

CERM
402

1

5%

2

87

13

1

0

5%

2

87

13

87

13

XDP_TCK

10

6

XDP_TMS

10

6

XDP_TRST_L

10

6

JTAG_LVL_TRANS_EN_L

JTAG_ALLDEV

1

C0602

0.1UF

20%
10V

2

CERM
402

NLSV4T244

2

A1

3

A2

4

A3

5

A4

12

OE*

1

11

VCCB

VCCA

U0600

UQFN

JTAG_ALLDEV

GND

6

IN
IN
IN
IN

XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L

6

10 13 87

10 13 87

6

10 13 87

6

10 13 87

From XDP connector

or via level translator

10

B1

9

B2

8

B3

7

B4

1

R0606

10K

5%
1/16W
MF-LF
402

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L

D

C

NOSTUFF

R0605

1 2

75

75

75

6

75

83

83

9

83

9

U8000

GPU

U9200

GMUX

75

83

9

GPU_JTAG_TDO

JTAG_GMUX_TDO

6

VCC

U0601

74LVC1G07

2

1

GMUX CPLD Programming Port

NC NC

CRITICAL

J0600

1909782

M-RT-SM

7

=PP3V3_S0_XDP

1
2

TDO

3

TDI
TMS

4
5

TCK

B

6

8

13

8

6

YA

4

5

NCNC

SOT886

GND

3

PLACEMENT_NOTE=Place close to U0600

GPU_JTAG_TCK

GPU_JTAG_TDI
GPU_JTAG_TMS
GPU_JTAG_TRST_L

JTAG_GMUX_TCK

JTAG_GMUX_TDI
JTAG_GMUX_TMS

=PP3V3_GPU_VDD33

76

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

PLACEMENT_NOTE=Place close to U8000

10K

5%
1/16W
MF-LF

402

GPU_JTAG_TMS

75 75

6 8

B

JTAG Scan Chain

A

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=07/22/2008

051-7546

SHT

1

A

REV.

A.0.0

OF

966

8 7

6

5

4

3

2 1

Functional Test Points

Fan Connectors

FUNC_TEST

3 TPs

D

TRUE

TRUE
TRUE

TRUE
TRUE
TRUE

=PP5V_S0_FAN_LT
FAN_LT_PWM

FAN_LT_TACH
FAN_RT_PWM

FAN_RT_TACH
GND

LVDS Connectors

FUNC_TEST

I568
I567

I570
I571

I572

I573
I569

I574
I566

I575

C

I576

I577

I578
I579

I580

I581

I582

I583

I584

I585
I586

I587

I588

I590
I589

I592

I591

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

=PP3V3_S0_DDC_LCD
PP3V3_SW_LCD

BKL_SYNC

LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_N<1>
LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_N<2>
LVDS_CONN_A_DATA_P<2>

LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_N<1>
LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_DATA_P<2>

LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_CLK_F_P

LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6

76

8

79

84

79

80

79

80

79

79

80

80

79

80

79

79

80

79

80

80

79

79

94

79

94

80

79

79

80

80

79

80

79

80

79

80

79

94

79

94

79

84

79

84

79

79

84

79

84

84

79

84

79

EXCARD Connector

FUNC_TEST

TRUE

B

I642

I643
I644

I645

I646
I648

I647

I650
I649

I651
I653

I652

I654
I655

I641

I657
I656

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

USB2_EXCARD_CONN_N
USB2_EXCARD_CONN_P
PCIE_CLK100M_EXCARD_CONN_N
PCIE_CLK100M_EXCARD_CONN_P

PCIE_EXCARD_R2D_N

PP3V3_S3_EXCARD_SWITCH

PP1V5_S0_EXCARD_SWITCH

PLT_RESET_SWITCH_L

SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA

PCIE_EXCARD_R2D_P

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_N

PP3V3_S0_EXCARD_SWITCH

EXCARD_CPPE_L

EXCARD_CPUSB_L

EXCARD_CLKREQ_CONN_L

32

95

32

95

32

32

32

32

32

A

per Fan

8

49

49

49

49

49

5 TPs
per Fan

79

Speaker Connectors

94

94

94

94

94

94

94

94

94

94

94

94

95

32

95

32

32

95

89

95

32

89

32

17

17

32

32

32

21

13

FUNC_TEST

TRUE

I557

TRUE

I558

TRUE

I559

TRUE

I560

TRUE

I561

TRUE

I562

TRUE

I563

TRUE

I564

TRUE

I565

TRUE

6 TPs

SATA ODD Connectors

FUNC_TEST

TRUE

I595

TRUE

I594

TRUE

I596

TRUE

I597

TRUE

I593

TRUE

I598

TRUE

PM_SLP_S3_L

TRUE

I640

PPBUS_G3H

TRUE

I602
I603

I604

I605
I607

89

I606

89

I609
I608

I610
I612

I611

I613
I600

I625

21

13

I624

45

90

45

90

I623

I622

I620
I621

I618
I619

I617

I615
I616

I614

I627
I626

I639

I638
I637

I636
I709

I760

I761
I762

I765

PPBUS_CPU_IMVP_ISNS

TRUE

PP3V42_G3H

TRUE

PP5V_S3

TRUE

PP5V_S0

TRUE

PPVCORE_S0_CPU

TRUE

PPVCORE_S0_MCP_REG

TRUE

PPVCORE_S0_MCP

TRUE

PP3V3_S5

TRUE

PP3V3_S3

TRUE

PP3V3_S0

TRUE

PP2V5_S0

TRUE

PP1V2_S0

TRUE

PP1V8_S0

TRUE

PP1V8R1V5_S3

TRUE

PP1V8R1V5_S0_FET

TRUE

PPMCPDDR_ISNS

TRUE

PP1V05_S0_REG

TRUE

PP1V2R1V05_S5

TRUE

PPCPUVTT_S0

TRUE

PPCPUFSB_ISNS_R

TRUE

PP0V9R0V75_S0_DDRVTT

TRUE

PP1V2R1V05_ENET

TRUE

PP3V3_ENET_PHY

TRUE

PPVP_FW

TRUE

PP1V0_FW

TRUE

PP3V3_S0GPU

TRUE

PP1V1_S0GPU_REG

TRUE

PP1V8_S0GPU_ISNS

TRUE

PPVCORE_GPU

TRUE

PP1V8_S0GPU_ISNS_R

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PPVOUT_S0_LCDBKLT

TRUE

PPDCIN_G3H

TRUE

PPVTTDDR_S3

TRUE

PP1V8_GPUIFPX

TRUE

BI_MIC_LO
BI_MIC_SHIELD

BI_MIC_HI
SPKRCONN_L_P_OUT
SPKRCONN_L_N_OUT
SPKRCONN_R_P_OUT
SPKRCONN_R_N_OUT
SPKRCONN_S_P_OUT
SPKRCONN_S_N_OUT

GND

PP5V_SW_ODD
SMC_ODD_DETECT

SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P

GND

POWER RAILS

58

59

58

59

59

58

95

57

58

95

57

58

57

95

58

95

58

57

95

58

57

57

95

58

I757

I758

I759
I756

I753
I752

I754

I755
I751

I749

4 TPs

39

42

39

89

39

89

39

89

39

89

39

5 TPs

37

34

21

8

8

95

8

95

8

8

8

8

8

8

8

8

8

8

8

8

43

42

79

84

8

8

8

83 81 68 44 42

46

7

43

8

8

8

8

8

8

8

8

8

8

8

8

8

8

I750
I748

I746

I747
I745

I744
I743

I741

I742
I740

I739

I736

I737

I735
I734

I733

I731
I732

I730

I728
I729

I726
I727

I725

I724
I723

I721

I722
I720

I718

I719
I717

I715
I716

I713

I714
I712

I711

I710
I763

I764

IPD_FLEX_CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP3V3_S3_LDO
PP18V5_S3
TPAD_GND_F
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_BOOT_CFG1
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
PSOC_F_CS_L
PICKB_L

KEYBOARD CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
KBDLED_ANODE
TPAD_GND_F

ICT Test Points

CPU FSB NO_TESTs

NO_TEST

TRUE
TRUE
TRUE

TRUE

TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

51

51

7

50

50

50

50

50

51

50

50

50

50

50

50

50

50

45

45

50

50

7

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

51

7

FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>

FSB_D_L<63..0>

FSB_DINV_L<3..0>

FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>

51

51

51

51

51

51

51

51

51

51

51

51

51

51

93

93

51

51

43

8

51

87

14

10

87

14

10

87

14

10

87

14

10

87

14

10

87

14

10

14

87

10

14

87

10

87

14

10

87

14

10

87

14

10

D

C

B

Functional / ICT Test

SYNC_MASTER=N/A

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7546

SHT

SYNC_DATE=N/A

OF

7 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

"G3Hot" (Always-Present) Rails

=PPBUS_G3H

61

D

=PPVIN_S5_CPU_IMVP_ISNS

46

=PP18V5_DCIN_CONN

60

=PP3V42_G3H_REG

60

C

=PP5V_S3_REG

63

5V Rails

B

=PP5V_RT_REG

65

Chipset "VCore" Rails

=PPVCORE_S0_CPU_REG

62

A

=PPMCPCORE_S0_REG

65

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVIN_S5_P5VP3V3

=PPVIN_S0_CPUVTTS0

=PPBUS_S0_LCDBKLT

=PPBUS_S5_FWPWRSW
=PPVIN_GPU_GPUVCORE

=PPVIN_S5_CPU_IMVP_ISNS_R
=PPVIN_S0_P5VRTS0_MCPCORE

=PPVIN_S3_DDRREG

=PPVIN_S0GPU_P1V8P1V1

=PPVBAT_G3H_P3V42G3H

=PPVIN_S0_P1V05S5

PPBUS_CPU_IMVP_ISNS

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVIN_S5_CPU_IMVP

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.42V
MAKE_BASE=TRUE

=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_LIDSWITCH
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PPVIN_S5_SMCVREF
=PP3V42_G3H_PWRCTL

=PP3V42_G3H_CHGR
=PP3V3_S5_RTC_D

=PP3V42_G3H_BATT
=PP3V42_G3H_TPAD
=PP3V42_G3H_BMON_ISNS

=PP3V42_G3H_CPUCOREISNS

PP5V_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_SYSLED

=PP5V_S3_BTCAMERA

=PP5V_S3_WLAN
=PP5V_S3_IR

=PP5V_S3_DDRREG

=PP5V_S3_GPUVCORE
=PP5V_S3_RTUSB

=PP5V_S3_TPAD

=PP5V_S3_P1V05S0FET

=PP5V_S3_MCPDDRFET
=PP5V_S3_VTTCLAMP

=PP5V_S3_AUDIO_PWR

PP5V_S0

MIN_LINE_WIDTH=0.60 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP

=PP5V_S0_CPUVTTS0

=PP5V_S0_KBDLED
=PP5V_S0GPU_P1V1P1V8_GPU
=PP5V_S0_LPCPLUS
=PP5V_S0_ODD

=PP5V_S0_HDD

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PPVCORE_S0_CPU

PPVCORE_S0_MCP_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PPVCORE_S0_MCP

46

63

7

63

66

85

37

78

46

65

64

82

60

67

7

69

62

7

61

7

43

40

45

41

42

52

43

44

43

63

69

68

61

26

60

50

46

46

7

43

31

31

41

64

78

40

51

69

69

69

9

7

7

49

49

62

66

51

82

44

39

39

7

12

11

46

46

22

24

86

7

86

6

=PP3V3_S5_REG

=PP3V3_S3_FET

=PP3V3_S0_FET

=PP2V5_S0_REG

=PP1V2_S0_REG

3.3V-2.5V Rails

PP3V3_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S5_MCP_A01

=PP3V3_S5_ROM
=PP3V3_S5_MEMRESET
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_LCD
=PP3V3_S0_P3V3S0FET
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S5_PWRCTL

=PP3V3_S5_P1V05FET
=PP3V3_S5_MCP
=PP3V3_S5_MCP_GPIO

=PP3V3_FW_LATEVG_ACTIVE

=PP3V3_S5_MCPPWRGD

=PP3V3_FW_LATEVG
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_DP_PORT_PWR

PP3V3_S3

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_FW_REG
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMS
=PP3V3_S3_REMTHMSNS

=PP3V3_S3_TPAD

=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO

=PP3V3_S3_VREFMRGN
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_EXCARD

=PP3V3_S3_P1V8S0

=PP3V3_S0_LPCPLUS

=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_GPU1V8ISNS

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_GPUTHMSNS

=PP3V3_S0_FAN_LT

=PP3V3_S0_FAN_RT

=PP3V3_S0_IMVP

=PP3V3_S0_PWRCTL

=PP3V3_S0_DDC_LCD

=PP3V3_S0_XDP

=PP3V3_S0_MCPCOREISNS

=PPSPD_S0_MEM_A

=PPSPD_S0_MEM_B

=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_GMUX

=PP3V3_S0_DPMUX

=PP3V3_S0_DPCONN

=PP3V3_S0_P1V2P2V5

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_HDCPROM

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP

=PP3V3_S0_AUDIO
=PP3V3_S0_ODD

=PP3V3_S0_VMON

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_FC_CON

=PP3V3_S0_EXCARD

=PP3V3_S0_LVDSDDCMUX

=PP3V3_S0_BATTCHARGERTMPSNSR

=PP3V3_GPU_SMBUS_SMC_0_S0

=PP3V3_S0_TPAD

PP2V5_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=2.5V
MAKE_BASE=TRUE

=PP2V5_S0_GMUX

PP1V2_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PP1V2_S0_GMUX

5

PP3V3_S0

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

67

7

95

500 mA max supply

23

44

53

44

64

30

69

79

69

69

68

69

22

24

18

20

69

37

26

38

34

34

81

16

24

7

8

69

45

52

48

50

31

21

27

45

32

67

24

8

95

7

24

44

24

8

43

45

24

47

47

48

48

49

49

241 mA max load

62

68

7

79

76

6

13

47

66

28

29

45

83

80

81

86

19

21

18

25

64

24

21

24

25

25

24

21

22

54

59

58

39

68

45

32

32

80

48

45

51

7

83

7

83

=PP1V8_S0_REG

=PPDDR_S3_REG

=PP1V8R1V5_S0_FET

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_S0_FET

1034 mA

=PP1V05_S0_MCP_PEX_DVDD

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

=PP1V05_S0_MCP_SATA_DVDD

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

=PP1V05_S5_MCP

67

=PPCPUVTT_S0_REG

5300 mA

=PPVTT_S3_DDR_BUF

27

=PPVTT_S0_DDR_LDO

64

=PP1V05_ENET_FET

34

=PP3V3_ENET_FET

34

4

1.8V/DDR 1.5V Rails

190 mA

4771 mA

130 mA
500 mA

105 mA/241 mA
139 mA/ 0 mA

4500 mA

1182 mA

ENET Rails

PP1V8_S0

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP3V3R1V8_S0_MCP_IFP_VDD

PP1V8R1V5_S3

MIN_LINE_WIDTH=0.8 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V8R1V5_S0_MCP_FET
=PPVIN_S0_DDRREG_LDO
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_MEMRESET

PP1V8R1V5_S0_FET

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PPMCPDDR_ISNS_R
=PP1V5_S0_CPU
=PP1V5_S0_EXCARD

=PP1V5_S0_VMON

=PP1V5_FC_CON

PPMCPDDR_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_MEM_A
=PP1V5_S0_MEM_B

=PPMCPDDR_ISNS

PP1V05_S0_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_HDMI_VDD

=PP1V05_S0_VMON

=PP1V05_S0_MCP_PEX_DVDD0
=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_AVDD0

PP1V2R1V05_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S5_MCP_VDD_AUXC
=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_P1V05S0FET

PPCPUVTT_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_CPU
=PP1V05_S0_SMC_LS
=PP1V05_S0_MCP_FSB

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

PP0V9R0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP

PP1V2R1V05_ENET

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_MCP_RMGT

=PP1V05_ENET_PHY

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_ENET_MCP_RMGT
=PP3V3_ENET_PHY

(1.1V for A01)

OR 0.75V

3

7

18

25

7

69

64

28

29

30

7

47

12

11

32

68

32

7

28

29

47

7

24

8

24

24

8

24

18

25

68

17

17

17

17

20

20

7

22

34

69

7

6

43

9

7

7

28

29

69

7

24

18

24

33

7

18

24

33

37

8

67

69

82

24

67

62 13

12

10

11

24

22

14

47

46

78

82

=PPBUS_S5_FW_FET

=PP3V3_FW_REG

=PP1V0_FW_REG

=PP3V3_S0GPU_FET

=PP1V1_S0GPU_REG

=PP1V8_GPUIFPX_REG

=PP1V8_S0GPU_ISNS

=PPVCORE_GPU_REG

=PP1V8_GPU_REG

2 1

"FW" (FireWire) Rails

PPVP_FW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET

=PP3V3_FW_FWPHY

=PP3V3_FW_P1V0FW

PP1V0_FW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.00V
MAKE_BASE=TRUE

=PP1V0_FW_FWPHY

"GPU" Rails

SYNC_MASTER=(MASTER)

APPLE INC.

PP3V3_S0GPU

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_GPU_VDD33
=PP3V3_GPU_MIO

=PP3V3_GPU_LVDS_DDC

=PP3V3_GPU_PWRCTL
=PP3V3_GPU_VCORELOGIC

=PP3V3_GPU_P1V8S0

PP1V1_S0GPU_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.1V
MAKE_BASE=TRUE

=PP1V1_GPU_PEX_IOVDDQ
=PP1V1_GPU_PEX_IOVDD
=PP1V1_GPU_PEX_PLLXVDD
=PP1V1_GPU_PLLVDD
=PP1V1_GPU_H_PLLVDD
=PP1V1_GPU_VID_PLLVDD
=PP1V1_GPU_FBPLLAVDD
=PP1V1_GPU_IFPCD_IOVDD

PP1V8_GPUIFPX

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_IFPX

PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_FB_VDD
=PP1V8_GPU_FB_VDDQ
=PP1V8_GPU_FBVDDQ
=PP1V8_GPU_FBIO

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PPVCORE_GPU

PP1V8_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PP1V8_S0GPU_ISNS_R

Power Aliases

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

7

38

38

SYNC_DATE=(MASTER)

051-7546

SHT

OF

D

38

36

67

7

36

7

6

76

75

75

76

80

68

78

67

7

70

70

70

75

75

75

72

77

7

77

7

73

74

9

74

73

71

72

7

71

7

47

C

B

A

REV.

A.0.0

968

8

7 6

5

4

3

2

1

D

C

B

ZT0915

3R2P5

1

ZT0940

3R2P5

1

ZT0945

3R2P5

1

ZT0950

TH

SL-3.1X2.7-6CIR-NSP

ZT0965

3R2P5

ZT0960

3R2P5

1

ZT0990

3R2P5

1

8 7

Thermal Module Holes

STDOFF-4.5OD.98H-1.1-3.48-TH

Frame Holes

GND_CHASSIS_LVDS

GND_CHASSIS_USB

GND_CHASSIS_FAN

1

GND_CHASSIS_CLUTCH

GND_CHASSIS_SATA

GND_CHASSIS_BATTCONN

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

Left CPU

TM Hole

61

60

ZT0983

Right CPU

TM Hole TM Hole

GND_BATT_CHGND

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0984

Top GPU Right

TM Hole

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0980

Bottom Left GPU

STDOFF-4.5OD.98H-1.1-3.48-TH

=PP1V8_GPU_FB_VDDQ

ZT0987

R0900

10

1%
1/16W
MF-LF

402

R0901

10

1%
1/16W
MF-LF

402

Extra FSB Pull-ups

Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa

=PP1V05_S0_MCP_FSB

24 22

8

14

CPU_DPRSTP_L

10 14 62 87

OUT

FSB_BREQ0_L

10 14 87

OUT

FSB_CPURST_L

10 13 14 87

OUT

CPU_INTR

10 14 87

OUT

CPU_NMI

10 14 87

OUT

6

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_A

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_B

NO STUFF

R0950

220

1/16W
MF-LF

402

1

5%

2

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0986

STDOFF-4.5OD.98H-1.1-3.48-TH

NO STUFF

NO STUFF

1

R0960

62

5%
1/16W
MF-LF
402

2

R0970

200

1/16W
MF-LF

402

1

5%

2

ZT0985

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

ZT0930

1.4DIA-SHORT-EMI-MLB-M97-M98

73

1.4DIA-SHORT-EMI-MLB-M97-M98

74

NO STUFF

NO STUFF

1

R0980

150

1%
1/16W
MF-LF
402

2

R0990

150

1/16W
MF-LF

402

1

1%

2

5

SH0902

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0903

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0910

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0912

SM

1

Bosses for VRAM HS

ZT0951

4.0OD1.65H-M1.6X0.35

1

ZT0952

4.0OD1.65H-M1.6X0.35

1

ZT0953

4.0OD1.65H-M1.6X0.35

1

SH0900

1

SH0901

SM

1

SH0911

SM

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0913

1

SM

4

3

2 1

CPU signals

MAKE_BASE=TRUE

95

95

95

95

95

95

CPU_VID<0..6>

87 87

11

MAKE_BASE=TRUE

CPU_BSEL<0..2>

87

10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_SPI_CS1_R_L_USE_MLB

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

70

89

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

89

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

89

70

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

70

89

MAKE_BASE=TRUE

PCIE_CLK100M_FC_P

32

MAKE_BASE=TRUE

PCIE_CLK100M_FC_N

32

MAKE_BASE=TRUE

PCIE_FC_R2D_C_P

32

MAKE_BASE=TRUE

PCIE_FC_R2D_C_N

32

MAKE_BASE=TRUE

FC_CLKREQ_L

32 29

MAKE_BASE=TRUE

FC_PRSNT_L

32

MAKE_BASE=TRUE

PCIE_FC_D2R_P

32

MAKE_BASE=TRUE

PCIE_FC_D2R_N

32

MAKE_BASE=TRUE

GPU signals

VR_PWRGD_CLKEN_LTP_IMVP6_CLKEN_L

IMVP6_VID<0..6>

=MCP_BSEL<0..2>

=DDRVTT_ENMEM_VTT_EN

=SPI_CS1_R_L_USE_MLB

=PEG_D2R_P<0..15>
=PEG_D2R_N<0..15>
=PEG_R2D_C_P<0..15>
=PEG_R2D_C_N<0..15>

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
TP_PE4_CLKREQ_L
TP_PE4_PRSNT_L

TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN

62

14

64 26

17

17 70

62

69

44

21

17

17

17

17

17

17

17

17

17

17

GMUX ALIASES

LCD_BKLT_EN

83 85

MAKE_BASE=TRUE

DP_IG_ML_P<3>

80

89

MAKE_BASE=TRUE

DP_IG_ML_N<3>

89

80 18

MAKE_BASE=TRUE

DP_IG_ML_P<2..0>

89

80 18

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

80

89

MAKE_BASE=TRUE

DP_IG_DDC_CLK

76

80

MAKE_BASE=TRUE

DP_IG_DDC_DATA

80

76

MAKE_BASE=TRUE

DP_IG_HPD

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

68

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

EG_RESET_L

83

MAKE_BASE=TRUE

JTAG_GMUX_TDI

6

83

MAKE_BASE=TRUE

JTAG_GMUX_TMS

6

83

MAKE_BASE=TRUE

JTAG_GMUX_TDO

83

6

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

18

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

18

MAKE_BASE=TRUE

LVDS_BKL_ON

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_TXD_N<0..2>

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

ALL_EG_PGOOD

LVDS_MUX_SEL_EG

GPU_RESET_L

GMUX_JTAG_TDI
GMUX_JTAG_TMS

GMUX_JTAG_TDO

IG_BKLT_EN
IG_LCD_PWR_EN

18

18

18

18

18

83

83

70

19

19

17

83

83

TP_USB_EXTDP

MAKE_BASE=TRUE

TP_USB_EXTDN

MAKE_BASE=TRUE

TP_USB_MINIP

MAKE_BASE=TRUE

TP_USB_MININ

MAKE_BASE=TRUE

GMUX_INT

83

MAKE_BASE=TRUE

MCP_SPKR

21

TP_MEM_A_A<15>

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MAKE_BASE=TRUE

TP_USB_EXTCP

MAKE_BASE=TRUE

TP_USB_EXTCN

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

TP_MCP_GPIO_17

MAKE_BASE=TRUE

PCIE_RESET_L

26

17

MAKE_BASE=TRUE

HDA_BITCLK

54

MAKE_BASE=TRUE

=PP5V_S3_AUDIO_PWR

8

ETHERNET ALIASES

=P3V3ENET_EN

34

=P1V05ENET_EN

34

=PP3V3_ENET_PHY_VDDREG

33

=RTL8211_REGOUT

33

AUDIO ALIASES

USB_EXTD_P
USB_EXTD_N

=DVI_HPD_GMUX_INT

R0903

0

5%
1/16W
MF-LF

402

MEM_A_A<15>
MEM_B_A<15>

USB_EXTC_P
USB_EXTC_N

CPU_PECI_MCP
AUD_IP_PERIPHERAL_DET

FC_RESET_L

HDA_BIT_CLK

XW0900

SM

12

SM

12

XW0901

R0902

10K

1 2

5%
1/16W
MF-LF

402

TP_PP3V3_ENET_PHY_VDDREG

=RTL8211_ENSWREG

USB_MINI_P
USB_MINI_N

SMC_MCP_SAFE_MODE

PP5V_S3_AUDIO

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

PP5V_S3_AUDIO_AMP

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

AUD_IPHS_SWITCH_EN

MAKE_BASE=TRUE

PM_SLP_RMGT_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

20

90

20

90

20

90

90

20

D

18

42

28

90

20

20

90

14

17

32

21

90

54

56

57

19

C

59

21

33

B

ZT0931

STDOFF-4.0OD3.0H-TH

ZT0934

STDOFF-4.0OD3.0H-TH

STDOFF-4.0OD3.0H-TH

1

ZT0935

1

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

A

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0991

1

8

1

VENICE

ZT0932

STDOFF-4.0OD3.0H-TH

1

VENICE

ZT0933

STDOFF-4.0OD3.0H-TH

1

VENICE

ZT0988

1

ZT0989

1

7 6

NC_LVDS_B_DATAP<3>

9

MAKE_BASE=TRUE

NC_LVDS_B_DATAN<3>

9

MAKE_BASE=TRUE

NC_LVDS_A_DATAP<3>

9

MAKE_BASE=TRUE

NC_LVDS_A_DATAN<3>

9

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_A_DATAP<3>

9

MAKE_BASE=TRUE

NC_LVDS_A_DATAN<3>

9

MAKE_BASE=TRUE

NC_LVDS_B_DATAP<3>

9

MAKE_BASE=TRUE

NC_LVDS_B_DATAN<3>

9

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

LVDS_B_DATA_P<3>

LVDS_B_DATA_N<3>

LVDS_A_DATA_P<3>

LVDS_A_DATA_N<3>

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N

LVDS_IG_BKL_PWM

LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

LVDS_A_DATA_P<3>
LVDS_A_DATA_N<3>

LVDS_B_DATA_P<3>
LVDS_B_DATA_N<3>

9

9

9

9

18

89

89

18

18

89

18

89

18

89

18

18

89

9

9

9

9

5

MCP79 PCIe PRSNT# Straps

R0925

0

5%
1/16W
MF-LF

402

R0927

1/16W
MF-LF

402

MCP_MII_PD

MAKE_BASE=TRUE

1

R0930

47K

5%
1/16W
MF-LF
402

2

4

These need work. Add other PRSNT# straps if needed. .

PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

17

OUT

NO STUFF

0

5%

PEG_PRSNT_L

MAKE_BASE=TRUE

R0926

5%
1/16W
MF-LF

402

0

OUT

EG_CLKREQ_OUT_L

=MCP_MII_RXER
=MCP_MII_CRS
=MCP_MII_COL

17

83

IN

18

18

18

3

=PP1V05_S0_MCP_SATA_DVDD1
=PP1V05_S0_MCP_SATA_AVDD1

Digital Ground

Signal Aliases

SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

2

GND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.09MM
VOLTAGE=0V

DRAWING NUMBER

SIZE

D

SCALE

NONE

20

20

SYNC_DATE=(MASTER)

051-7546

SHT

OF

9 96

1

A

REV.

A.0.0

8 7

FSB_A_L<3>

7

14 87

BI

FSB_A_L<4>

7

14 87

BI

FSB_A_L<5>

7

14 87

BI

FSB_A_L<6>

7

14 87

BI

FSB_A_L<7>

7

14 87

BI

FSB_A_L<8>

7

14 87

BI

FSB_A_L<9>

7

14 87

BI

FSB_A_L<10>

7

14 87

BI

FSB_A_L<11>

7

14 87

BI

FSB_A_L<12>

7

14 87

D

C

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

14 87

BI

14 87

BI

14 87

BI

14 87

BI

7

14 87

BI

14 87

IN

14 87

OUT

14 87

IN

14 87

IN

9

14 87

IN

9

14 87

IN

14 87

IN

FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>

CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L

CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L

TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
TP_CPU_RSVD5
TP_CPU_RSVD6
TP_CPU_RSVD7
TP_CPU_RSVD8

B

XDP_TMS

87

13

10

6

XDP_TDI

87

13

10

6

XDP_TDO

87

10

87

87

13

10

13

10

6

XDP_TCK

6

XDP_TRST_L

6

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

A

AA4
AB2
AA3

D22

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

K3
H2
K2
J3
L1

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3

V1

A6
A5
C4

D5
C6
B4
A3

M4
N5
T2
V3
B2
F6
D2

D3

A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*

A20M*
FERR*
IGNNE*

STPCLK*
LINT0
LINT1
SMI*

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

R1021

R1023

U1000

PENRYN

1 OF 4

ADDR GROUP0

ADDR GROUP1

54.9

1%
1/16W
MF-LF

402

649

1%
1/16W
MF-LF

402

OMIT

FCBGA

ICH

RESERVED

ADS*
BNR*

BPRI*

DEFER*

DRDY*
DBSY*

BR0*

IERR*
INIT*

CONTROL

LOCK*

RESET*

RS0*
RS1*
RS2*

TRDY*

HIT*

HITM*

BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*

TCK
TDI
TDO

XDP/ITP SIGNALS

TMS

TRST*

DBR*

THERMAL

PROCHOT*

THERMDA
THERMDC

THERMTRIP*

H CLK

BCLK0
BCLK1

R1020

54.9

1%
1/16W
MF-LF

402

R1024

54.9

1%
1/16W
MF-LF

402

R1022

54.9

1%
1/16W
MF-LF

402

H1

FSB_ADS_L

E2

FSB_BNR_L

G5

FSB_BPRI_L

H5

FSB_DEFER_L

F21

FSB_DRDY_L

E1

FSB_DBSY_L

F1

FSB_BREQ0_L

D20

CPU_IERR_L

87

B3

CPU_INIT_L

H4

FSB_LOCK_L

C1

FSB_CPURST_L

F3

FSB_RS_L<0>

F4

FSB_RS_L<1>

G3

FSB_RS_L<2>

G2

FSB_TRDY_L

G6

FSB_HIT_L

E4

FSB_HITM_L

AD4

XDP_BPM_L<0>

AD3

XDP_BPM_L<1>

AD1

XDP_BPM_L<2>

AC4

XDP_BPM_L<3>

AC2

XDP_BPM_L<4>

AC1

XDP_BPM_L<5>

AC5

XDP_TCK

AA6

XDP_TDI

AB3

XDP_TDO

AB5

XDP_TMS

AB6

XDP_TRST_L

C20

XDP_DBRESET_L

D21

CPU_PROCHOT_L

A24

CPU_THERMD_P

B25

CPU_THERMD_N

C7

PM_THRMTRIP_L

A22

FSB_CLK_CPU_P

A21

FSB_CLK_CPU_N

=PP1V05_S0_CPU

2 1

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

9

14 62 87

IN

14 87

IN

14 87

IN

13 14 87

IN

14 87

IN

62

OUT

LAYOUT NOTE:

14 87

COMP0,2 CONNECT WITH ZO=27.4OHM,

14 87

MAKE TRACE LENGTH SHORTER THAN 0.5".

14 87

COMP1,3 CONNECT WITH ZO=55OHM,

14 87

MAKE TRACE LENGTH SHORTER THAN 0.5".

14 87

14 87

14 87

14 87

14 87

14 87

14 87

14 87

R1017

54.9

1%
1/16W
MF-LF

402

R1019

54.9

1%
1/16W
MF-LF

402

R1016

27.4

1%
1/16W
MF-LF

402

R1018

27.4

1%
1/16W
MF-LF

402

D

C

B

OMIT

U1000

PENRYN

FCBGA

2 OF 4

DATA GRP 0DATA GRP 1

MISC

3

DSTBN2*
DSTBP2*

DINV2*

DATA GRP 3 DATA GRP 2

DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*

D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*

SLP*
PSI*

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>

FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>

CPU_COMP<0>

87 27

CPU_COMP<1>

87

CPU_COMP<2>

87

CPU_COMP<3>

87

CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L

6

7

14 87

BI

14 87

BI

14 87

BI

14 87

BI

14 87

BI

14 87

BI

9

14 87

BI

14 87

IN

7

14 87

BI

9

13 14 87

IN

14 87

IN

14 87

IN

14 87

IN

14 87

IN

7

14 87

BI

7

14 87

BI

13 87

BI

13 87

BI

13 87

BI

13 87

BI

13 87

BI

6

10 13 87

IN

6

10 13 87

IN

6

10 87

OUT

6

10 13 87

IN

6

10 13 87

IN

13 26

OUT

48 95

OUT

48 95

OUT

14 43 87

OUT

14 87

IN

14 87

IN

62

13

12

62

13

12

11

10

8

6

PLACE C1000 CLOSE TO CPU_TEST4
PIN. MAKE SURE CPU_TEST4 IS
REFERENCED TO GND

=PP1V05_S0_CPU

1

R1002

54.9

1%
1/16W
MF-LF
402

2

R1003

54.9

1/16W
MF-LF

PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)

=PP1V05_S0_CPU

11

10

8

6

5

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

0.1" AWAY

=PP1V05_S0_CPU

1

1%

402

2

BI

1

R1004

68

5%
1/16W
MF-LF
402

2

OUT

R1005

1K

1/16W
MF-LF

402

R1006

2.0K

1/16W
MF-LF

402

13 87

14 43 62 87

1

1%

2

1

1%

2

62

13

12

11

10

8

6

62

13

12

11

10

8

6

0.5" MAX LENGTH FOR CPU_GTLREF

NOSTUFF

1

C1000

0.1uF

10%
16V

2

X5R
402

9

87

9

87

9

87

CPU_GTLREF

87

CPU_TEST1

CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7

CPU_BSEL<0>

OUT

CPU_BSEL<1>

OUT

CPU_BSEL<2>

OUT

4

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

NOSTUFF

R1012

1/16W
MF-LF

402

1K

5%

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>

FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>

NOSTUFF

R1030

0

5%

1/16W

1

MF-LF

402

2

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

C3
B22
B23
C21

NOSTUFF

1

R1007

1K

5%
1/16W
MF-LF
402

2

D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*

D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2

CPU FSB

SYNC_MASTER=M87_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=10/17/2007

051-7546

SHT

OF

10

96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

C

B

A10
A12
A13
A15
A17
A18
A20

B10
B12
B14
B15
B17
B18
B20

C10
C12
C13
C15
C17
C18

D10
D12
D14
D15
D17
D18

E10
E12
E13
E15
E17
E18
E20

F10
F12
F14
F15
F17
F18
F20
AA7

AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

A7
A9

B7
B9

C9

D9

VCC

E7
E9

F7
F9

OMIT

U1000

PENRYN

FCBGA

3 OF 4

VCC

VCCP

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

A

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

8

(CPU CORE POWER)
=PPVCORE_S0_CPU

46

12

11

8

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

30.4 A (LFM)

25.5 A (SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

16.8 A (Sleep SuperLFM)

25.0 A (Deep Sleep HFM)

16.0 A (Deep Sleep SuperLFM)

11.5 A (Deeper Sleep)

9.4 A (Enhanced Deeper Sleep)

(CPU IO POWER 1.05V)

=PP1V05_S0_CPU

4500 mA (before VCC stable)
2500 mA (after VCC stable)

62 13

12

10

8

6

(CPU INTERNAL PLL POWER 1.5V)
=PP1V5_S0_CPU

12

8

130 mA

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

9

87

OUT

9

87

OUT

9

87

OUT

9

87

OUT

9

87

OUT

9

87

OUT

9

87

OUT

CPU_VCCSENSE_P

CPU_VCCSENSE_N

7 6

Low Voltage:

23.0 A (Design Target)

21.0 A (HFM)

18.7 A (LFM)
TBD A (SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Sleep HFM)
TBD A (Sleep SuperLFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep SuperLFM)

TBD A (Deeper Sleep)
TBD A (Enhanced Deeper Sleep)

=PPVCORE_S0_CPU

1

R1100

100

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

62 87

OUT

62 87

OUT

1

R1101

100

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

46

12

11

8

5

Ultra Low Voltage:

17.0 A (Design Target)
TBD A (HFM)

TBD A (LFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep HFM)
TBD A (Sleep LFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep LFM)

TBD A (Deeper Sleep)
TBD A (Enhanced Deeper Sleep)

4

A4

A8
A11
A14
A16
A19
A23
AF2

B6

B8
B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3

E6

E8
E11
E14

VSS VSS
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

P3

B1

OMIT

U1000

PENRYN

FCBGA

4 OF 4

3

P6
P21
P24
R2
R5
R22
R25
T1
T4

T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

CPU Power & Ground

SYNC_MASTER=M87_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

2

SYNC_DATE=10/17/2007

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

11 96

1

D

C

B

A

REV.

A.0.0

OF

8 7

6

5

4

3

2 1

D

D

CPU VCORE HF AND BULK DECOUPLING

=PPVCORE_S0_CPU

46

11

8

CRITICAL

C1250

330UF

POLY-TANT

PLACEMENT_NOTE=Place in CPU center cavity.

C

PLACEMENT_NOTE=Place in CPU center cavity.

PLACEMENT_NOTE=Place in CPU center cavity.

PLACEMENT_NOTE=Place in CPU center cavity.

D2T-SM2

CRITICAL

C1252

330UF

POLY-TANT

D2T-SM2

4x 330uF, 20x 22uF 0805

CRITICAL

2.0V

2.0V

20%

20%

1

2 3

CRITICAL

1

2 3

C1251

330UF

2.0V

POLY-TANT

D2T-SM2

C1253

330UF

2.0V

POLY-TANT

D2T-SM2

1

20%

2 3

1

20%

2 3

CRITICAL

1

C1200

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

C1210

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL
22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1203C1202C1201

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1213C1212C1211

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1205 C1209

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1215 C1217

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1206C1204

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1216C1214

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1208C1207

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1219C1218

22UF

20%

6.3V
X5R-CERM
603

C

VCCP (CPU I/O) DECOUPLING

62 13 11

=PP1V05_S0_CPU

10

8

6

CRITICAL

C1235

470UF

1x 470uF, 6x 0.1uF 0402

1

C1236

0.1UF

20%
10V

2

CERM
402

2.5V
POLY

1

20%

2 3

D2T

WF: Consider sharing bulk cap with NB Vtt?

1

C1237

0.1UF

20%

10V

2

CERM
402

1

C1238

0.1UF

20%
10V

2

CERM
402

1

C1239

0.1UF

20%

10V

2

CERM
402

1

C1240

0.1UF

20%
10V

2

CERM
402

1

C1241

0.1UF

20%
10V

2

CERM
402

VCCA (CPU AVdd) DECOUPLING

B

=PP1V5_S0_CPU

11

8

1x 10uF, 1x 0.01uF

1

1

C1280

10uF

20%

6.3V
X5R
603

C1281

0.01UF

10%
16V

2

2

CERM
402

PLACEMENT_NOTE=Place near CPU pin B26.

CPU Decoupling & VID

A

SYNC_MASTER=M87_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=10/17/2007

051-7546

SHT

OF

9612

1

REV.

B

A

A.0.0

8 7

6

5

4

3

2 1

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

D

Use with 920-0620 adapter board to support CPU, MCP debugging.

D

MCP79-specific pinout

=PP3V3_S0_XDP

8

6

62 12 11 10

10 87

10 87

10 87

10 87

10 87

10 87

C

XDP

R1399

1K

10 14 87

IN

CPU_PWRGD

1 2

5%
1/16W
MF-LF

402

19 23

6

21

7

21 45 90

7

21 45 90

6

10 87

B

=PP1V05_S0_CPU

8

6

XDP_BPM_L<5>

BI

XDP_BPM_L<4>

BI

XDP_BPM_L<3>

BI

XDP_BPM_L<2>

IN

XDP_BPM_L<1>

IN

XDP_BPM_L<0>

IN

TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3

XDP_PWRGD

PM_LATRIGGER_L

IN

JTAG_MCP_TCK

OUT

SMBUS_MCP_0_DATA

BI

SMBUS_MCP_0_CLK

BI

XDP_TCK

OUT

XDP

R1315

54.9

1/16W
MF-LF

1%

402

1

2

XDP_OBS20

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

TCK1
TCK0

C1300

0.1uF

CRITICAL
XDP_CONN

J1300

LTH-030-01-G-D-NOPEGS

SDA
SCL

XDP

1

10%
16V

2

X5R X5R
402

F-ST-SM

1

2

3

4

5

6

10

20

30

40

50

NC

60

78

9
1112
1314
1516
1718
19
2122
2324
2526
2728
29
3132
3334
3536
3738
39
4142
4344
4546
4748
49
5152
5354
5556
5758
59

998-1571

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1OBSDATA_B1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C1301

0.1uF

10%
16V

2

402

JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L

MCP_DEBUG<0>
MCP_DEBUG<1>

MCP_DEBUG<2>
MCP_DEBUG<3>

JTAG_MCP_TDI
JTAG_MCP_TMS

MCP_DEBUG<4>
MCP_DEBUG<5>

MCP_DEBUG<6>
MCP_DEBUG<7>

FSB_CLK_ITP_P
FSB_CLK_ITP_N

XDP_CPURST_L

87

XDP_DBRESET_L

XDP_TDO_CONN
XDP_TRST_L
XDP_TDI
XDP_TMS

OUT

OUT
OUT

OUT

OUT
OUT
OUT

6

IN

6

21

19 90

BI

19 90

BI

19 90

BI

19 90

BI

6

21 23

6

21 23

19 90

BI

19 90

BI

19 90

BI

19 90

BI

14 87

IN

14 87

IN

10 26

6

IN

6

10 87

6

10 87

6

10 87

XDP

R1303

1K

1 2

FSB_CPURST_L

5%

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1/16W
MF-LF

402

9

10 14 87

IN

C

B

Direction of XDP module

Please avoid any obstructions
on even-numbered side of J1300

eXtended Debug Port(MiniXDP)

A

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=01/08/2008

051-7546

SHT

OF

13

96

1

A

REV.

A.0.0

8 7

6

D

C

=PP1V05_S0_MCP_FSB

24

22

14 9 9

8

R1415

1/16W
MF-LF

R1421

1/16W
MF-LF

1

1

R1416

62

62

5%

5%
1/16W
MF-LF

402

402

2

2

NO STUFF

1

1

R1422

1K

1K

5%

5%

1/16W
MF-LF
402

402

2

2

1

R1430

49.9

1/16W
MF-LF

1

R1435

49.9

1%

1%
1/16W
MF-LF

402

402

2

2

1

R1410

54.9

1%
1/16W
MF-LF

402

2

B

10 43 87

IN

10 87

IN

9

IN

9

IN

9

IN

PM_THRMTRIP_L
CPU_FERR_L

NO STUFF

R1420

=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>

1/16W
MF-LF

1K

5%

402

NO STUFF

1

2

A

1

1

R1431

49.9

1/16W
MF-LF

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

R1436

49.9

1%

1%

1/16W
MF-LF
402

402

2

2

FSB_DSTB_L_P<0>

7

10 87

BI

FSB_DSTB_L_N<0>

7

10 87

BI

FSB_DINV_L<0>

7

10 87

BI

FSB_DSTB_L_P<1>

7

10 87

BI

FSB_DSTB_L_N<1>

7

10 87

BI

FSB_DINV_L<1>

7

10 87

BI

FSB_DSTB_L_P<2>

7

10 87

BI

FSB_DSTB_L_N<2>

7

10 87

BI

FSB_DINV_L<2>

7

10 87

BI

FSB_DSTB_L_P<3>

7

10 87

BI

FSB_DSTB_L_N<3>

7

10 87

BI

FSB_DINV_L<3>

7

10 87

BI

FSB_A_L<3>

7

10 87

BI

FSB_A_L<4>

7

10 87

BI

FSB_A_L<5>

7

10 87

BI

FSB_A_L<6>

7

10 87

BI

FSB_A_L<7>

7

10 87

BI

FSB_A_L<8>

7

10 87

BI

FSB_A_L<9>

7

10 87

BI

FSB_A_L<10>

7

10 87

BI

FSB_A_L<11>

7

10 87

BI

FSB_A_L<12>

7

10 87

BI

FSB_A_L<13>

7

10 87

BI

FSB_A_L<14>

7

10 87

BI

FSB_A_L<15>

7

10 87

BI

FSB_A_L<16>

7

10 87

BI

FSB_A_L<17>

7

10 87

BI

FSB_A_L<18>

7

10 87

BI

FSB_A_L<19>

7

10 87

BI

FSB_A_L<20>

7

10 87

BI

FSB_A_L<21>

7

10 87

BI

FSB_A_L<22>

7

10 87

BI

FSB_A_L<23>

7

10 87

BI

FSB_A_L<24>

7

10 87

BI

FSB_A_L<25>

7

10 87

BI

FSB_A_L<26>

7

10 87

BI

FSB_A_L<27>

7

10 87

BI

FSB_A_L<28>

7

10 87

BI

FSB_A_L<29>

7

10 87

BI

FSB_A_L<30>

7

10 87

BI

FSB_A_L<31>

7

10 87

BI

FSB_A_L<32>

10 87

BI

FSB_A_L<33>

10 87

BI

FSB_A_L<34>

10 87

BI

FSB_A_L<35>

10 87

BI

FSB_ADSTB_L<0>

7

10 87

BI

FSB_ADSTB_L<1>

7

10 87

BI

FSB_REQ_L<0>

7

10 87

BI

FSB_REQ_L<1>

7

10 87

BI

FSB_REQ_L<2>

7

10 87

BI

FSB_REQ_L<3>

7

10 87

BI

FSB_REQ_L<4>

7

10 87

BI

FSB_ADS_L

7

10 87

BI

FSB_BNR_L

10 87

BI

FSB_BREQ0_L

9

10 87

BI

FSB_BREQ1_L

87

FSB_DBSY_L

10 87

BI

FSB_DRDY_L

10 87

BI

FSB_HIT_L

7

10 87

BI

FSB_HITM_L

7

10 87

BI

FSB_LOCK_L

7

10 87

IN

FSB_TRDY_L

10 87

OUT

CPU_PECI_MCP

9

OUT

CPU_PROCHOT_L

10 43 62 87

OUT

(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)

FSB_RS_L<0>

10 87

OUT

FSB_RS_L<1>

10 87

OUT

FSB_RS_L<2>

10 87

OUT

PP1V05_S0_MCP_PLL_FSB

24

270 mA (A01) 206 mA

MCP_BCLK_VML_COMP_VDD

87

MCP_BCLK_VML_COMP_GND

87

MCP_CPU_COMP_VCC

87

MCP_CPU_COMP_GND

87

20 mA
29 mA
15 mA

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

T40

CPU_DSTBP0#

U40

CPU_DSTBN0#

V41

CPU_DBI0#

W39

CPU_DSTBP1#

W37

CPU_DSTBN1#

V35

CPU_DBI1#

N37

CPU_DSTBP2#

L36

CPU_DSTBN2#

N35

CPU_DBI2#

M39

CPU_DSTBP3#

M41

CPU_DSTBN3#

J41

CPU_DBI3#

AC34

CPU_A3#

AE38

CPU_A4#

AE34

CPU_A5#

AC37

CPU_A6#

AE37

CPU_A7#

AE35

CPU_A8#

AB35

CPU_A9#

AF35

CPU_A10#

AG35

CPU_A11#

AG39

CPU_A12#

AE33

CPU_A13#

AG37

CPU_A14#

AG38

CPU_A15#

AG34

CPU_A16#

AN38

CPU_A17#

AL39

CPU_A18#

AG33

CPU_A19#

AL33

CPU_A20#

AJ33

CPU_A21#

AN36

CPU_A22#

AJ35

CPU_A23#

AJ37

CPU_A24#

AJ36

CPU_A25#

AJ38

CPU_A26#

AL37

CPU_A27#

AL34

CPU_A28#

AN37

CPU_A29#

AJ34

CPU_A30#

AL38

CPU_A31#

AL35

CPU_A32#

AN34

CPU_A33#

AR39

CPU_A34#

AN35

CPU_A35#

AE36

CPU_ADSTB0#

AK35

CPU_ADSTB1#

AC38

CPU_REQ0#

AA33

CPU_REQ1#

AC39

CPU_REQ2#

AC33

CPU_REQ3#

AC35

CPU_REQ4#

AD42

CPU_ADS#

AD43

CPU_BNR#

AE40

CPU_BR0#

AL32

CPU_BR1#

AD39

CPU_DBSY#

AD41

CPU_DRDY#

AB42

CPU_HIT#

AD40

CPU_HITM#

AC43

CPU_LOCK#

AE41

CPU_TRDY#

E41

CPU_PECI

AJ41

CPU_PROCHOT#

AG43

CPU_THERMTRIP#

AH40

CPU_FERR#

F42

CPU_BSEL2

D42

CPU_BSEL1

F41

CPU_BSEL0

AC41

CPU_RS0#

AB41

CPU_RS1#

AC42

CPU_RS2#

AG27

+V_DLL_DLCELL_AVDD

AH27

+V_PLL_MCLK

AG28

+V_PLL_FSB

AH28

+V_PLL_CPU

AM39

BCLK_VML_COMP_VDD

AM40

BCLK_VML_COMP_GND

AM43

CPU_COMP_VCC

AM42

CPU_COMP_GND

(1 OF 11)

FSB

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

BCLK_OUT_ITP_P
BCLK_OUT_ITP_N

BCLK_OUT_NB_P
BCLK_OUT_NB_N

BCLK_IN_N
BCLK_IN_P

CPU_A20M#

CPU_IGNNE#

CPU_INIT#

CPU_PWRGD

CPU_RESET#

CPU_DPSLP#

CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#

5

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#

CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

CPU_INTR

CPU_NMI
CPU_SMI#

CPU_SLP#

4

Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43

AA41
AA40

G42
G41

AL43
AL42

AL41
AK42

AK41
AJ40

AF41
AH39
AH42
AF42
AG41
AH41

AH43
H38

AM33
AN33
AM32
AG42
AN32

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_BPRI_L
FSB_DEFER_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_CLK_ITP_P
FSB_CLK_ITP_N

FSB_CLK_MCP_P

87

FSB_CLK_MCP_N

87

CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L

CPU_PWRGD
FSB_CPURST_L

FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

10 87

OUT

10 87

OUT

10 87

OUT

10 87

OUT

13 87

OUT

13 87

OUT

Loop-back clock for delay matching.

10 87

OUT

10 87

OUT

10 87

OUT

9

10 87

OUT

9

10 87

OUT

10 87

OUT

9

10 13 87

OUT

10 87

OUT

10 87

OUT

10 87

OUT

10 87

OUT

9

10 62 87

OUT

=PP1V05_S0_MCP_FSB

NO STUFF

1

R1440

150

5%
1/16W
MF-LF
402

2

10 13 87

OUT

3

24

22

14

8

SYNC_MASTER=T18_MLB

APPLE INC.

2

MCP CPU Interface

SYNC_DATE=06/18/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

1

D

C

B

A

REV.

A.0.0

OF

9614

8 7

6

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0

MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0

(2 OF 11)

MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N

MEMORY PARTITION 0

MEMORY

CONTROL

MCLK0A_2_P
MCLK0A_2_N

MCLK0A_1_P
MCLK0A_1_N

MCLK0A_0_P
MCLK0A_0_N

MRAS0#
MCAS0#

MWE0#

MBA0_2
MBA0_1
MBA0_0

MA0_14
MA0_13
MA0_12
MA0_11
MA0_10

MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0

0A

MCS0A_1#
MCS0A_0#

MODT0A_1
MODT0A_0

MCKE0A_1
MCKE0A_0

AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39

AV17
AP17
AR17

AP23
AP19
AW17

AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19

AW33
AV33

BA24
AY24

BB20
BC20

AT15
AR18

AP15
AV15

AU23
AT23

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>

MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>

TP_MEM_A_CLK2P
TP_MEM_A_CLK2N

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CKE<0>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>

AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8

BA9
BB10
BB12
AW12

BB8

BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42

AT5

BA2

AY7
BA11
BB34
BB38
AY43
AR42

MEM_A_DQ<63>

28 88

BI

MEM_A_DQ<62>

28 88

BI

MEM_A_DQ<61>

28 88

BI

MEM_A_DQ<60>

28 88

BI

MEM_A_DQ<59>

28 88

D

C

B

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>

AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5

AN10

AR5
AU6
AV5
AU7
AU8
AW9

AP11

AW6
AY5
AU9

AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35

AN5

AU5
AR10
AN13
AN27
AW29
AV35
AR34

OMIT

U1400

MCP79-TOPO-B

BGA

(3 OF 11)

MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0

MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0

CONTROL

MRAS1#
MCAS1#

MWE1#

MBA1_2
MBA1_1
MBA1_0

MA1_14
MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43

AW16
BA15
BA16

BB29
BB18
BB17

BA29
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N

MEMORY PARTITION 1

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>

MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

MEMORY

1A

MCLK1A_2_P
MCLK1A_2_N

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MCS1A_1#
MCS1A_0#

MODT1A_1
MODT1A_0

MCKE1A_1
MCKE1A_0

BA42
BB42

BB22
BA22

BA19
AY19

BB14
BB16

BB13
AY15

AY31
BB30

TP_MEM_B_CLK2P
TP_MEM_B_CLK2N

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_ODT<1>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

D

C

B

MCP Memory Interface

A

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

15

96

1

A

REV.

A.0.0

8 7

6

D

=PP1V8R1V5_S0_MCP_MEM

24

16

8

1

R1610

40.2

1%
1/16W
MF-LF

402

2

1

R1611

40.2

C

1/16W
MF-LF

1%

402

2

B

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

TP_MEM_A_CLK5P
TP_MEM_A_CLK5N

TP_MEM_A_CLK4P
TP_MEM_A_CLK4N

TP_MEM_A_CLK3P
TP_MEM_A_CLK3N

TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>

TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>

TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>

PP1V05_S0_MCP_PLL_CORE

24

87 mA (A01)

MCP_MEM_COMP_VDD

88

MCP_MEM_COMP_GND

88

17 mA
12 mA
19 mA
39 mA

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

AU33

MCLK0B_2_P

AU34

MCLK0B_2_N

BB24

MCLK0B_1_P

BC24

MCLK0B_1_N

BA21

MCLK0B_0_P

BB21

MCLK0B_0_N

AU17

MCS0B_0#

AR15

MCS0B_1#

AN17

MODT0B_0

AN15

MODT0B_1

AV23

MCKE0B_0

AN25

MCKE0B_1

T27

+V_PLL_XREF_XS

U28

+V_PLL_DP

U27

+V_PLL_CORE

T28

+V_VPLL

AN41

MEM_COMP_VDD

AM41

MEM_COMP_GND

AA22

GND1

AP12

GND2

G30

GND3

P10

GND4

T10

GND5

T6

GND6

V10

GND7

V34

GND8

W5

GND9

AA39

GND10

AB22

GND11

AB7

GND12

AD22

GND13

AE20

GND14

AF24

GND15

AG24

GND16

AH35

GND17

AK7

GND18

AM28

GND19

AT25

GND20

AP30

GND21

AR36

GND22

AU10

GND23

F28

GND24

BC21

GND25

AY9

GND26

BC9

GND27

D34

GND28

F24

GND29

G32

GND30

H31

GND31

K7

GND32

M38

GND33

M5

GND34

M6

GND35

M7

GND36

M9

GND37

N39

GND38

N8

GND39

P33

GND40

P34

GND41

P37

GND42

P4

GND43

P40

GND44

P7

GND45

R36

GND46

R40

GND47

R43

GND48

R5

GND49

T18

GND50

T20

GND51

AK11

GND52

T24

GND53

T26

GND54

5

(4 OF 11)

MCLK1B_2_P
MCLK1B_2_N

MCLK1B_1_P
MCLK1B_1_N

MCLK1B_0_P
MCLK1B_0_N

MEMORY CONTROL 0B

MEMORY CONTROL 1B

+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8

+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45

MCS1B_0#
MCS1B_1#

MODT1B_0
MODT1B_1

MCKE1B_0
MCKE1B_1

MRESET0#

GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64

BA41
BB41

AY23
BA23

BA20
AY20

BC16
BA13

AY16
BC13

BA30
BA31

AY32

AM17
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31

T33
T34
T35
T37
T38
T7
T9
U18
U20
U22

TP_MEM_B_CLK5P
TP_MEM_B_CLK5N

TP_MEM_B_CLK4P
TP_MEM_B_CLK4N

TP_MEM_B_CLK3P
TP_MEM_B_CLK3N

TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>

TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>

MCP_MEM_RESET_L

TP or NC for DDR2.

=PP1V8R1V5_S0_MCP_MEM

4771 mA (A01, DDR3)

4

D

30

OUT

24

16

8

C

B

MCP Memory Misc

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

16 96

1

A

REV.

A.0.0

8 7

6

D

C

31

31

36

32

32

83

23 31 32

31 89

31 89

36 89

B

36 89

32 89

32 89

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

=PEG_D2R_P<0>

9

IN

=PEG_D2R_N<0>

9

IN

=PEG_D2R_P<1>

9

IN

=PEG_D2R_N<1>

9

IN

=PEG_D2R_P<2>

9

IN

=PEG_D2R_N<2>

9

IN

=PEG_D2R_P<3>

9

IN

=PEG_D2R_N<3>

9

IN

=PEG_D2R_P<4>

9

IN

=PEG_D2R_N<4>

9

IN

=PEG_D2R_P<5>

9

IN

=PEG_D2R_N<5>

9

IN

=PEG_D2R_P<6>

9

IN

=PEG_D2R_N<6>

9

IN

=PEG_D2R_P<7>

9

IN

=PEG_D2R_N<7>

9

IN

=PEG_D2R_P<8>

9

IN

=PEG_D2R_N<8>

9

IN

=PEG_D2R_P<9>

9

IN

=PEG_D2R_N<9>

9

IN

=PEG_D2R_P<10>

9

IN

=PEG_D2R_N<10>

9

IN

=PEG_D2R_P<11>

9

IN

=PEG_D2R_N<11>

9

IN

=PEG_D2R_P<12>

9

IN

=PEG_D2R_N<12>

9

IN

=PEG_D2R_P<13>

9

IN

=PEG_D2R_N<13>

9

IN

=PEG_D2R_P<14>

9

IN

=PEG_D2R_N<14>

9

IN

=PEG_D2R_P<15>

9

IN

=PEG_D2R_N<15>

9

IN

PEG_PRSNT_L

9

IN

MINI_CLKREQ_L

IN

PCIE_MINI_PRSNT_L

IN

FW_CLKREQ_L

IN

PCIE_FW_PRSNT_L

9

IN

EXCARD_CLKREQ_L

IN

PCIE_EXCARD_PRSNT_L

IN

TP_PE4_CLKREQ_L

9

TP_PE4_PRSNT_L

9

AUD_IP_PERIPHERAL_DET

9

IN

GMUX_JTAG_TCK_L

OUT

TP_MCP_GPIO_18
GMUX_JTAG_TDO

9

IN

PCIE_WAKE_L

IN

PCIE_MINI_D2R_P

IN

PCIE_MINI_D2R_N

IN

PCIE_FW_D2R_P

IN

PCIE_FW_D2R_N

IN

PCIE_EXCARD_D2R_P

7

IN

PCIE_EXCARD_D2R_N

7

IN

TP_PCIE_PE4_D2RP

9

TP_PCIE_PE4_D2RN

9

=PP1V05_S0_MCP_PEX_DVDD0

8

57 mA (A01, DVDD0 & 1)

=PP1V05_S0_MCP_PEX_DVDD1

8

PP1V05_S0_MCP_PLL_PEX

24

84 mA (A01)

MCP_PEX_CLK_COMP

89

NO STUFF

1

R1710

2.37K

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 12.7mm of U1400

5

4

OMIT

U1400

MCP79-TOPO-B

BGA

F7

PE0_RX0_P

E7

PE0_RX0_N

D7

PE0_RX1_P

C7

PE0_RX1_N

E6

PE0_RX2_P

F6

PE0_RX2_N

E5

PE0_RX3_P

F5

PE0_RX3_N

E4

PE0_RX4_P

E3

PE0_RX4_N

C3

PE0_RX5_P

D3

PE0_RX5_N

G5

PE0_RX6_P

H5

PE0_RX6_N

J7

PE0_RX7_P

J6

PE0_RX7_N

J5

PE0_RX8_P

J4

PE0_RX8_N

L11

PE0_RX9_P

L10

PE0_RX9_N

L9

PE0_RX10_P

L8

PE0_RX10_N

L7

PE0_RX11_P

L6

PE0_RX11_N

N11

PE0_RX12_P

N10

PE0_RX12_N

N9

PE0_RX13_P

P9

PE0_RX13_N

N7

PE0_RX14_P

N6

PE0_RX14_N

N5

PE0_RX15_P

N4

PE0_RX15_N

Int PU

C9 D11

PE0_PRSNT_16#

Int PU

D5

PEB_CLKREQ#/GPIO_49

D9

PEB_PRSNT#

Int PU

E8

PEC_CLKREQ#/GPIO_50

C10

PEC_PRSNT#

Int PU

M15

PED_CLKREQ#/GPIO_51

B10

PED_PRSNT#

Int PU

L16

PEE_CLKREQ#/GPIO_16

L18

PEE_PRSNT#/GPIO_46

Int PU

M16

PEF_CLKREQ#/GPIO_17

M18

PEF_PRSNT#/GPIO_47

Int PU

M17

PEG_CLKREQ#/GPIO_18

M19

PEG_PRSNT#/GPIO_48

F17

PE_WAKE#

K9

PE1_RX0_P

J9

PE1_RX0_N

H9

PE1_RX1_P

G9

PE1_RX1_N

F9

PE1_RX2_P

E9

PE1_RX2_N

H7

PE1_RX3_P

G7

PE1_RX3_N

T17

+DVDD0_PEX1

W19

+DVDD0_PEX2

U17

+DVDD0_PEX3

V19

+DVDD0_PEX4

W16

+DVDD0_PEX5

W17

+DVDD0_PEX6

W18

+DVDD0_PEX7

U16

+DVDD0_PEX8

T19

+DVDD1_PEX1

U19

+DVDD1_PEX2

T16

+V_PLL_PEX

A11

PEX_CLK_COMP

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

(5 OF 11)

PCI EXPRESS

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU (S5)

PE0_TX0_P

PE0_TX0_N

PE0_TX1_P

PE0_TX1_N

PE0_TX2_P

PE0_TX2_N

PE0_TX3_P

PE0_TX3_N

PE0_TX4_P

PE0_TX4_N

PE0_TX5_P

PE0_TX5_N

PE0_TX6_P

PE0_TX6_N

PE0_TX7_P

PE0_TX7_N

PE0_TX8_P

PE0_TX8_N

PE0_TX9_P

PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE2_REFCLK_P
PE2_REFCLK_N

PE3_REFCLK_P
PE3_REFCLK_N

PE4_REFCLK_P
PE4_REFCLK_N

PE5_REFCLK_P
PE5_REFCLK_N

PE6_REFCLK_P
PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE1_TX0_N

PE1_TX1_P

PE1_TX1_N

PE1_TX2_P

PE1_TX2_N

PE1_TX3_P

PE1_TX3_N

+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8

+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13

+AVDD1_PEX1

+AVDD1_PEX2

+AVDD1_PEX3

5

C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1

E11

G11
F11

J11
J10

G13
F13

J13
H13

L14
K14

N14
M14

K11

D8
C8

B8
A8

A7
B7

B6
C6

Y12
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12

M13
N13
P13

=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>

PEG_CLK100M_P
PEG_CLK100M_N

PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

=PP1V05_S0_MCP_PEX_AVDD0

206 mA (A01, AVDD0 & 1)

Minimum 1.025V for Gen2 supportMinimum 1.025V for Gen2 support

=PP1V05_S0_MCP_PEX_AVDD1

4

3

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

70 89

OUT

70 89

OUT

31 89

OUT

31 89

OUT

36 89

OUT

36 89

OUT

32 89

OUT

32 89

OUT

9

9

9

26

OUT

31 89

OUT

31 89

OUT

36 89

OUT

36 89

OUT

32 89

OUT

32 89

OUT

9

9

8

8

2 1

D

C

B

MCP PCIe Interfaces

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

17 96

1

A

REV.

A.0.0

8 7

6

D

33 91

IN

33 91

IN

33 91

IN

33 91

IN

33 91

IN

33 91

IN

9

IN

9

=PP3V3_ENET_MCP_RMGT

24

18

8

R1810

49.9

1/16W
MF-LF

R1811

49.9

1/16W
MF-LF

1

1%

402

2

1

1%

402

2

IN

9

IN

24

91

91

25

25

C

25 89

OUT

25 89

OUT

=PP3V3_S5_MCP_GPIO

20

8

25

1

R1820

47K

5%
1/16W
MF-LF

402

2

44

BI

Interface Mode
MCP Signal
=MCP_HDMI_TXC_P/N

=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

B

=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.

TMDS/HDMI
TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N

LVDS: Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V

DisplayPort
DP_IG_ML_P/N<3>

DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

IN

25

OUT

80

IN

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

80 89

OUT

80 89

OUT

9

IN

9

IN

25

8

25

25

8

25 89

OUT

25 89

OUT

GPIOs 57-59 (if LCD panel is used):
In MCP79 these pins have undocumented internal

pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.

=DVI_HPD_GMUX_INT:
Alias to DVI_HPD for systems using IFP for DVI.

Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>

ENET_CLK125M_RXCLK
ENET_RX_CTRL

=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS

TP_ENET_INTR_L
PP1V05_ENET_MCP_PLL_MAC

5 mA (A01)

MCP_MII_COMP_VDD
MCP_MII_COMP_GND

TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF

MCP_TV_DAC_RSET
MCP_TV_DAC_VREF

MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT

LPCPLUS_GPIO
DP_IG_CA_DET

LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR

=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>

DP_IG_AUX_CH_P
DP_IG_AUX_CH_N

=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD

=PP3V3R1V8_S0_MCP_IFP_VDD

190 mA (A01, 1.8V)

PP3V3_S0_MCP_VPLL

16 mA (A01)

=PP1V05_S0_MCP_HDMI_VDD

95 mA (A01)

MCP_HDMI_RSET
MCP_HDMI_VPROBE

(See below)

(See below)

8 mA
8 mA

5

C23

RGMII_RXD0

B23

RGMII_RXD1

E24

RGMII_RXD2

A24

RGMII_RXD3

A23

RGMII_RXC/MII_RXCLK

C22

RGMII_RXCTL/MII_RXDV

F23

MII_RXER/GPIO_36

B26

MII_COL/GPIO_20/MSMB_DATA

B22

MII_CRS/GPIO_21/MSMB_CLK

J22

RGMII_INTR/GPIO_35

T23

+V_DUAL_MACPLL

C27

MII_COMP_VDD

B27

MII_COMP_GND

C39

RGB_DAC_RSET

B38

RGB_DAC_VREF

E36

TV_DAC_RSET

A35

TV_DAC_VREF

C38

XTALIN_TV

D38

XTALOUT_TV

E16

GPIO_6/FERR*/IGPU_GPIO_6

B15

GPIO_7/NFERR*/IGPU_GPIO_7

G39

LCD_BKL_CTL/GPIO_57

E37

LCD_BKL_ON/GPIO_59

F40

LCD_PANEL_PWR/GPIO_58

D35

HDMI_TXC_P/ML0_LANE3_P

E35

HDMI_TXC_N/ML0_LANE3_N

G35

HDMI_TXD0_P/ML0_LANE2_P

F35

HDMI_TXD0_N/ML0_LANE2_N

F33

HDMI_TXD1_P/ML0_LANE1_P

G33

HDMI_TXD1_N/ML0_LANE1_N

J33

HDMI_TXD2_P/ML0_LANE0_P

H33

HDMI_TXD2_N/ML0_LANE0_N

D43

DP_AUX_CH0_P

C43

DP_AUX_CH0_N

C31

HPLUG_DET2/GPIO_22

F31

HPLUG_DET3

M27

+VDD_IFPA

M26

+VDD_IFPB

M28

+V_PLL_IFPAB

M29

+V_PLL_HDMI

T25

+VDD_HDMI

J31

HDMI_RSET

J30

HDMI_VPROBE

5

OMIT

U1400

MCP79-TOPO-B

BGA

(6 OF 11)

LAN

DACS

TV / Component
C / Pr
Y / Y
Comp / Pb

4

MII_VREF

DDC_CLK0

DDC_CLK3

J24
K24

U23
V23

E28

B24
C24
C25
D25

D24
C26

D21
C21

G23

E23

J23

J32
K32

B31
A31

B39
A39
B40

A40
A41

A36
B36
C36

D36
C37

B35
C35

B32
A32
D32
C32
D33
C33
B34
C34

L31
K31

J29
H29
L29
K29
L30
K30
N30
M30

C30
B30

D31
E31

E32
G31

+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2

+V_DUAL_RMGT1
+V_DUAL_RMGT2

RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3

RGMII_TXC/MII_TXCLK

RGMII_TXCTL/MII_TXEN

RGMII_MDC

RGMII_MDIO

RGMII_PWRDWN/GPIO_37

BUF_25MHZ

MII_RESET#

+V_RGB_DAC

+V_TV_DAC

DDC_DATA0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC

RGB ONLY

RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N

FLAT PANEL

DDC_CLK2/GPIO_23

DDC_DATA2/GPIO_24

DDC_DATA3

IFPAB_RSET

IFPAB_VPROBE

4

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_MCP_RMGT

131 mA (A01)

MCP_MII_VREF
ENET_TXD<0>

ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>

ENET_CLK125M_TXCLK
ENET_TX_CTRL

ENET_MDC
ENET_MDIO

TP_ENET_PWRDWN_L

MCP_CLK25M_BUF0_R

ENET_RESET_L

PP3V3_S0_MCP_DAC
103 mA
103 mA

MCP_DDC_CLK0
MCP_DDC_DATA0

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB

CRT_IG_HSYNC
CRT_IG_VSYNC

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

1

R1850

10K

5%
1/16W
MF-LF
402

2

206 mA (A01)

3

24

18

8

83 mA (A01)

24

8

24

IN

33 91

OUT

33 91

OUT

33 91

OUT

33 91

OUT

33 91

OUT

33 91

OUT

33 91

OUT

BI

34 91

OUT

33 91

OUT

25

25

25

25

25

25

25 89

OUT

25 89

OUT

25 89

OUT

25 89

OUT

25 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

9

OUT

9

OUT

9

OUT

9

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

9

OUT

9

OUT

80

OUT

BI

9

OUT

BI

25 89

OUT

25 89

OUT

3

2 1

Network Interface Select

Interface

RGMII

NOTE: All Apple products set strap to
MII, RGMII products will enable

33 91

1

R1860

100K

5%
1/16W
MF-LF

402

2

89

89

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

89

89

89

89

80

9

feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.

=PP3V3_S0_MCP_GPIO

1

R1861

100K

5%
1/16W
MF-LF
402

2

RGB DAC Disable:
Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

TV DAC Disable:
Okay to float all TV_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.

MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

2

MII

SIZE

SCALE

19

8

D

NONE

ENET_TXD<0>

21

DRAWING NUMBER

051-7546

SHT

1
0

SYNC_DATE=06/18/2008

REV.

A.0.0

OF

18 96

1

D

C

B

A

8 7

6

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

Int PU

(7 OF 11)

PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_PERR#/GPIO_43/RS232_DCD#

LPC_PWRDWN#/GPIO_54/EXT_NMI#

LPC PCIGND

PCI_GNT0#

PCI_GNT1#/FANCTL2

PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_SERR#
PCI_STOP#

PCI_PME#/GPIO_30

Int PU (S5)

PCI_RESET0#
PCI_RESET1#

PCI_CLK0
PCI_CLK1
PCI_CLK2

PCI_CLKIN

LPC_FRAME#

LPC_RESET0#

LPC_CLK0

PCI_REQ0_L

90

19

PCI_REQ1_L

90

19

CRTMUX_SEL_TV_L

19

OUT

AUD_IPHS_SWITCH_EN

9

59

OUT

MCP_RS232_SIN_L

19

IN

D

C

13 90

BI

13 90

BI

13 90

BI

13 90

BI

13 90

BI

13 90

BI

13 90

BI

13 90

BI

MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>

TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L

TP_PCI_TRDY_L

PM_CLKRUN_L

42 44

IN

FW_PME_L

36

IN

TP_LPC_DRQ0_L
LPC_SERIRQ

42 44 26 90

BI

B

A

T2

PCI_REQ0#

V9

PCI_REQ1#/FANRPM2

T3

PCI_REQ2#/GPIO_40/RS232_DSR#

U9

PCI_REQ3#/GPIO_38/RS232_CTS#

T4

PCI_REQ4#/GPIO_52/RS232_SIN#

AC3

PCI_AD0

AE10

PCI_AD1

AC4

PCI_AD2

AE11

PCI_AD3

AB3

PCI_AD4

AC6

PCI_AD5

AB2

PCI_AD6

AC7

PCI_AD7

AC8

PCI_AD8

AA2

PCI_AD9

AC9

PCI_AD10

AC10

PCI_AD11

AC11

PCI_AD12

AA1

PCI_AD13

AA5

PCI_AD14

Y5

PCI_AD15

W3

PCI_AD16

W6

PCI_AD17

W4

PCI_AD18

W7

PCI_AD19

V3

PCI_AD20

W8

PCI_AD21

V2

PCI_AD22

W9

PCI_AD23

U3

PCI_AD24

W11

PCI_AD25

U2

PCI_AD26

U5

PCI_AD27

U1

PCI_AD28

U6

PCI_AD29

T5

PCI_AD30

U7

PCI_AD31

P2

PCI_INTW#

N3

PCI_INTX#

N2

PCI_INTY#

N1

PCI_INTZ#

Y3

PCI_TRDY#

AD11

PCI_CLKRUN#/GPIO_42

AE2

LPC_DRQ1#/GPIO_19

AE1
AE6

U24
U26
U39

V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37

V40

W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25

U4
U8

V4

V7

LPC_DRQ0#
LPC_SERIRQ

GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97

Int PU
Int PU

PCI_PAR

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

GND98

GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130

R3
U10
R4
U11
P3

AA3
AA6
AA11
W10

AA9
Y4
AA10
Y1
AB9
AA7
Y2

T1

R10
R11

R6
R7
R8

R9

AD4
AE12

AE5

AD3
AD2
AD1
AD5

AE9

Y26
Y27
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
AD28
AD33
AD34

TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L

TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>

TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L

PM_LATRIGGER_L

MEM_VTT_EN_R
TP_PCI_RESET1_L

TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R

90

PCI_CLK33M_MCP

90

LPC_FRAME_R_L

44

LPC_PWRDWN_L

9

OUT

9

OUT

19

OUT

13 23

OUT

26

OUT

1

R1910

22

5%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place close to pin R8

R1960

22

1 2

LPC_RESET_L

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

R1950
R1951
R1952
R1953

22
22

1 2
1 2
1 2
1 2

LPC_CLK33M_SMC_R

1

R1961

10K

5%
1/16W
MF-LF
402

2

Strap for Boot ROM Selection (See HDA_SDOUT)

1/16W MF-LF

5%

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

5%

1/16W MF-LF

5%

LPC_FRAME_L

402

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>

402

LPC_AD<3>

402

MF-LF1/16W

OUT
OUT

OUT

BI
BI
BI
BI

OUT

42 44 83 90

42 44

26 83 90

42 44 83 90

42 44 83 90

42 44 83 90

42 44 83 90

MCP_RS232_SOUT_L

19

PCI_REQ0_L

90

19

PCI_REQ1_L

90

19

CRTMUX_SEL_TV_L

19

MCP_RS232_SIN_L

19

R1989
R1990

R1991
R1992
R1994

SYNC_MASTER=T18_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

8.2K

8.2K

8.2K

8.2K

8.2K

MCP PCI & LPC

NOTICE OF PROPRIETARY PROPERTY

SIZE

SCALE

=PP3V3_S0_MCP_GPIO

21 18

8

1 2

1 2
1 2
1 2
1 2

DRAWING NUMBER

D

NONE

5%

5%
5%
5%
5%

MF-LF1/16W

MF-LF1/16W
MF-LF1/16W

1/16W MF-LF

MF-LF1/16W

SYNC_DATE=06/18/2008

051-7546

SHT

OF

9619

REV.

402

402
402
402
402

A.0.0

D

C

B

A

8

7 6

5

4

3

2

1

8 7

6

39 89

OUT

39 89

OUT

39 89

IN

39 89

IN

D

39 89

OUT

39 89

OUT

39 89

IN

39 89

IN

C

24

84 mA (A01)

8

43 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

9

B

8

127 mA (A01, AVDD0 & 1)

Minimum 1.025V for Gen2 support

9

89

1

2

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N

SATA_HDD_D2R_N
SATA_HDD_D2R_P

SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N

SATA_ODD_D2R_N
SATA_ODD_D2R_P

TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN

TP_SATA_C_D2RN
TP_SATA_C_D2RP

TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN

TP_SATA_D_D2RN
TP_SATA_D_D2RP

TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN

TP_SATA_E_D2RN
TP_SATA_E_D2RP

TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN

TP_SATA_F_D2RN
TP_SATA_F_D2RP

TP_MCP_SATALED_L

PP1V05_S0_MCP_PLL_SATA

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_AVDD1

MCP_SATA_TERMP

R2010

2.49K

1%
1/16W
MF-LF
402

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

AJ7
AJ6

AJ5
AJ4

AJ11
AJ10

AJ9
AK9

AK2
AJ3

AJ2
AJ1

AM4
AL3

AL4
AK3

AN1
AM1

AM2
AM3

AP3
AP2

AN3
AN2

E12

AE16

AF19
AG16
AG17
AG19

AH17
AH19

AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13

AN14
AL14
AM13
AM14

AE3

5

SATA_A0_TX_P
SATA_A0_TX_N

SATA_A0_RX_N
SATA_A0_RX_P

SATA_A1_TX_P
SATA_A1_TX_N

SATA_A1_RX_N
SATA_A1_RX_P

SATA_B0_TX_P
SATA_B0_TX_N

SATA_B0_RX_N
SATA_B0_RX_P

SATA_B1_TX_P
SATA_B1_TX_N

SATA_B1_RX_N
SATA_B1_RX_P

SATA_C0_TX_P
SATA_C0_TX_N

SATA_C0_RX_N
SATA_C0_RX_P

SATA_C1_TX_P
SATA_C1_TX_N

SATA_C1_RX_N
SATA_C1_RX_P

SATA_LED#

+V_PLL_SATA

+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4

+DVDD1_SATA1
+DVDD1_SATA2

+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9

+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4

SATA_TERMP

5

OMIT

U1400

MCP79-TOPO-B

BGA

(8 OF 11)

SATA

USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO

USB

USB_OC0#/GPIO_25
USB_OC1#/GPIO_26

USB_RBIAS_GND

4

USB0_P
USB0_N

USB1_P
USB1_N

USB2_P
USB2_N

USB3_P
USB3_N

USB4_P
USB4_N

USB5_P
USB5_N

USB6_P
USB6_N

USB7_P
USB7_N

USB8_P
USB8_N

USB9_P
USB9_N

USB10_P
USB10_N

USB11_P
USB11_N

+V_PLL_USB

GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160

4

External A

C29
D29

C28
D28

A28
B28

F29
G29

K27
L27

J26
J27

F27
G27

D27
E27

K25
L25

H25
J25

F25
G25

K23
L23

L21
K21
J21
H21

L28

A27

AD35
AD37
AD38
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24

USB_EXTA_P
USB_EXTA_N

AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N

External D

USB_EXTD_P
USB_EXTD_N

Camera

USB_CAMERA_P
USB_CAMERA_N

IR

USB_IR_P
USB_IR_N

Geyser Trackpad/Keyboard

USB_TPAD_P
USB_TPAD_N

Bluetooth

USB_BT_P
USB_BT_N

External B

USB_EXTB_P
USB_EXTB_N

ExpressCard

USB_EXCARD_P
USB_EXCARD_N

External C

USB_EXTC_P
USB_EXTC_N

TP_USB_10P
TP_USB_10N

TP_USB_11P
TP_USB_11N

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

90

19 mA (A01)

R2060

1/16W
MF-LF

806

402

3

40 90

BI

40 90

BI

9

90

BI

9

90

BI

9

90

BI

9

90

BI

31 90

BI

31 90

BI

41 90

BI

41 90

BI

50 90

BI

50 90

BI

31 90

BI

31 90

BI

40 90

BI

40 90

BI

32 90

BI

32 90

BI

9

90

BI

9

90

BI

R2050

8.2K

1/16W
MF-LF

24

1

1%

2

1

R2051

8.2K

5%
1/16W
MF-LF
402

2

1

R2052

8.2K

5%

402

2

1/16W
MF-LF

5%

402

2 1

=PP3V3_S5_MCP_GPIO

1

R2053

8.2K

5%
1/16W
MF-LF
402

2

1

2

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L

18

8

40

IN

40

IN
IN

32 43

IN

D

C

B

MCP SATA & USB

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

20 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

(9 OF 11)

D

54 90

IN

HDA_SDIN0

TP_MLB_RAM_SIZE

=PP3V3R1V5_S0_MCP_HDA

24

8

21

1

R2110

49.9

1%
1/16W
MF-LF
402

2

PP3V3_G3_RTC

22

26

1

1

R2120

C

49.9K

1/16W
MF-LF

R2121

49.9K

1%

1%

1/16W
MF-LF
402

402

2

2

TP_MLB_RAM_VENDOR

(MXM_OK for MXM systems)

90

MCP_HDA_PULLDN_COMP

PP1V05_S0_MCP_PLL_NV

24

37 mA (A01)

=SPI_CS1_R_L_USE_MLB

9

44

OUT

SMC_ADAPTER_EN

34 37 42 43

IN

TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L

23 42

IN

SMC_RUNTIME_SCI_L

23 42

IN

20 mA
17 mA

SM_INTRUDER_L

TP_MCP_LID_L

23

PM_BATLOW_L

23 42

IN

PM_DPRSLPVR

62 87

IN

PM_PWRBTN_L

23 42

IN

PM_SYSRST_DEBOUNCE_L

23 26

IN

RTC_RST_L

PM_RSMRST_L

42

IN

MCP_PS_PWRGD

26

IN

MCP_CPU_VLD

26 26

IN

JTAG_MCP_TDI

6

13 23

IN

JTAG_MCP_TDO

6

OUT

JTAG_MCP_TMS

6

13 23

IN

JTAG_MCP_TRST_L

6

13

IN

JTAG_MCP_TCK

6

13

B

IN

MCP_CLK25M_XTALIN

26

IN

MCP_CLK25M_XTALOUT

26

OUT

RTC_CLK32K_XTALIN

26

IN

RTC_CLK32K_XTALOUT

26

OUT

R2150

10K

1/16W
MF-LF

1

5%

402

2

G15

HDA_SDATA_IN0

Int PD

J14

HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK

Int PD

J15

HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA

Int PD

A15

HDA_PULLDN_COMP

AE18

+V_PLL_NV_H

AE17

+V_PLL_SP_SPREF

L24

GPIO_1/PWRDN_OK/SPI_CS1

L26

GPIO_12/SUS_STAT#/ACCLMTR

K13

A20GATE

L13

KBRDRSTIN#

C19

SIO_PME#

C18

EXT_SMI/GPIO_32#

B20

INTRUDER#

M25

LID#

M24

LLB#

M22

CPU_DPRSLPVR

C16

PWRBTN#

D16

RSTBTN#

C20

RTC_RST#

D20

PWRGD_SB

E20

PS_PWRGD

C17 D17

CPU_VLD

E19

JTAG_TDI

F19

JTAG_TDO

J19

JTAG_TMS

J18

JTAG_TRST#

G19

JTAG_TCK

A16

XTALIN

B16

XTALOUT

A19

XTALIN_RTC

B19

XTALOUT_RTC

1

R2151

100K

5%
1/16W
MF-LF
402

2

Int PU
Int PU
Int PU (S5)

Int PU (S5)
Int PU (S5)

Int PU (S5)
Int PU

Int PU

Int PU

Int PU (S5)

HDA

HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK

HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA

(MGPIO2)

MISC

(MGPIO3)

+V_DUAL_HDA1
+V_DUAL_HDA2

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET#

SLP_RMGT#

THERM_DIODE_P
THERM_DIODE_N

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT#/GPIO_64

FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62

CPUVDD_EN

SPI_CS0/GPIO_10
SPI_CLK/GPIO_11

SPI_DI/GPIO_8
SPI_DO/GPIO_9

SUS_CLK/GPIO_34

BUF_SIO_CLK

TEST_MODE_EN

HDA_SYNC

SLP_S3#

SLP_S5#

SPKR

SMB_CLK0

PKG_TEST

J16
K16

F15

E15

K15

L15

K17
L17

G17
J17
H17

B11
C11

L20
M20
M21

C13

L19
K19
G21
F21
M23

B12
A12
D12
C12

C14
D13
C15
B14

B18
AE7

K22
L22

=PP3V3R1V5_S0_MCP_HDA

1

R2160

8.2K

5%
1/16W
MF-LF
402

2

21

HDA_SDOUT_R

90

21

HDA_BIT_CLK_R

90

HDA_RST_R_L

21

90

HDA_SYNC_R

21

90

MCP_GPIO_4
AUD_I2C_INT_L

PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L

MCP_THMDIODE_P
MCP_THMDIODE_N

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

MCP_SPKR

SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN

MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT

MCP_CPUVDD_EN

SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R

PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK

MCP_TEST_MODE_EN

1

R2163

10K

5%
1/16W
MF-LF
402

2

24

21

8

7 mA (A01)

R2171

22

1 2

5%
1/16W
MF-LF

402

R2173

22

1 2

5%
1/16W
MF-LF

402

21

IN

OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT

BI

OUT

BI

OUT

IN

OUT

IN

21

OUT

OUT
OUT

IN

OUT

OUT

1

2

R2170

22

1 2

5%
1/16W
MF-LF

402

R2172

22

1 2

5%
1/16W
MF-LF

402

21 59

7

34 37 42 44 68 81 83

9

40 42 43 68

48 95

48 95

21 65

21 65

21 65

7

13 45 90

7

13 45 90

45 90

45 90

21 31 34

21 28 29 42

39

21 43

44 90

44 90

44 90

44 90

26 90

R2190

1K

1%
1/16W
MF-LF
402

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

HDA_SYNC

BOOT_MODE_SAFE

1

R2180

10K

2

54 90

OUT

9

90

OUT

54 90

OUT

54 90

OUT

=PP3V3_S0_MCP

5%
1/16W
MF-LF
402

9

OUT

BOOT_MODE_USER

1

R2181

10K

USER mode: Normal

5%
1/16W

SAFE mode: For ROMSIP

MF-LF
402

2

recovery
Connects to SMC for

automatic recovery.

D

BIOS Boot Select

I/F HDA_SDOUT
LPC

PCI
SPI0
SPI1

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
R1961 and R2160 selects SPI0 ROM by

default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.

NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.

NOTE: MCP79 rev A01 does not support

24

8

22

SPI1 option. Rev B01 will.

0
0
1
1

BUF_SIO_CLK Frequency

Frequency

24 MHz

14.31818 MHz

LPC_FRAME#

0
1
0
1

C

HDA_SYNC

1
0

SPI Frequency Select

0
0
1
1

SPI_CLK

0
1
0
1

Frequency

SPI_DO
31 MHz
42 MHz
25 MHz

1 MHz

NOTE: Straps not provided on this page.

B

HDA Output Caps

For EMI Reduction on HDA interface

HDA_SDOUT_R
HDA_BIT_CLK_R

HDA_RST_R_L
HDA_SYNC_R

A

10PF

CERM

5%

50V

2

402

1

2

1

C2170

C2172

10PF

CERM

C2171

10PF

5%
50V
CERM
402

1

5%

50V

2

402

1

C2173

10PF

5%
50V

2

CERM
402

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

21

90

21

90

21

90

21

90

7 6

1

R2140

5%
1/16W
MF-LF
402

2

1

R2141

10K

5%
1/16W
MF-LF
402

2

1

R2142

10K

5%
1/16W
MF-LF
402

2

=PP3V3_S0_MCP_GPIO

1

R2143

10K10K

5%
1/16W
MF-LF
402

2

MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L

ARB_DETECT

1

R2147

100K

5%
1/16W
MF-LF
402

2

5

19

8

18

21

21

59

42

29

21

28

21

43

21

1

R2155

22K

5%
1/16W
MF-LF

2

1

R2156

22K

5%
1/16W
MF-LF
402402

2

4

=PP3V3_S3_MCP_GPIO

2

R2154

100K

5%
1/16W
MF-LF
402

1

AP_PWR_EN

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

1

R2157

22K

5%
1/16W
MF-LF
402

2

21

21

21

21

3

8

34

31

65

65

65

SYNC_MASTER=T18_MLB

APPLE INC.

2

MCP HDA & MISC

SYNC_DATE=06/18/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

21 96

1

A

REV.

A.0.0

OF

8 7

6

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

AH26
AH33
AH34
AH37
AH38
AJ39

D

C

B

A

AK10
AK33
AK34
AK37

AK40
AL36
AL40

AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38

AP26
AN28
AN30
AN39

AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37

AP40

AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33

AY21
AY22

AU12
AU28
AP33
AU32
AR30
AU36
AU38

AV28
AV32
AV36

AW11

AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41

(11 OF 11) (10 OF 11)

GND161
GND162
GND163
GND164
GND165
GND166

AJ8

GND167
GND168
GND169
GND170
GND171

AK4

GND172
GND173
GND174
GND175

AL5

GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188

AM5

GND189

AM6

GND190

AM7

GND191

AM9

GND192
GND193
GND194
GND195
GND196

AN4

GND197

Y7

GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207

AP4

GND208
GND209

AP7

GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219

AT6

GND220

AT7

GND221

AT9

GND222
GND223
GND224

L12

GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232

AU4

GND233

G28

GND234

F20

GND235
GND236
GND237
GND238

AV4

GND239

AV7

GND240
GND241

G20

GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250 GND342
GND251
GND252

GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301

GND

GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341

GND343

AV40
BA1
BA4
AW31
AY6
L35
BC33
BC37
BC41
AY14
BC5
C2
D10
D14
D15
D18
D19
D22
D23
D26
D30
D37
D6
E13
E17
E21
E25
E29
E33
F12
F16
F32
F8
G10
G12
G14
G16
BC12
G22
G24
AW20
G34
G4
G43
G6
G8
H11
H15
AW35
H23
AN8
G40
J12
J8
K10
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
Y11
AH16
T22

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

=PPVCORE_S0_MCP

24

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

PP3V3_G3_RTC

26

21

10 uA (G3)
80 uA (S0)

OMIT

U1400

MCP79-TOPO-B

BGA

AA25
AC23

U25
AH12
AG10

AG5

Y21

Y23
AA16
AA26
AA27
AA28
AC16
AC17
AC18
AC19
AC20
AC21
AA17
AC24
AC25
AC26
AC27
AC28
AD21
AD23

W27

V25
AA18
AE19
AE21
AE23
AE25
AE26
AE27
AE28
AF10
AF11
AA19

AF2
AF21
AF23
AF25

AF3

AF4

AF7
AH23

AF9
AA20
AG11
AG12
AG21
AG23
AG25

AG3

AG4
AA21

AG6

AG7

AG8

AG9

AH1
AH10
AH11

W26

AH2
AA23

W28
AH25
AH21

AH3

AH4

AH5

AH6

AH7

AH9
AA24

W21

W23

W25
AF12

A20

+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81

+VBAT

+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8

+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36

POWER

+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52

+VTT_CPUCLK

+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8

+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4

+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4

+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3

5

=PP1V05_S0_MCP_FSB

R32

1139 mA

AC32
E40
J36
N32
T32
U32
V32
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32

AG32

43 mA

=PP3V3_S0_MCP

AD10
AE8
AB10
AD9
Y10
AB11
AA8
Y9

=PP3V3_S5_MCP

G18

16 mA

H19
J20
K20

G26

250 mA

H27
J28
K28

=PP1V05_S5_MCP_VDD_AUXC

T21
U21
V21

4

9

8 8

1182 mA (A01)

24

21

8

450 mA (A01)

24

8

266 mA (A01)

24

8

105 mA (A01)

24 14 46

D

C

B

MCP Power & Ground

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

9622

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

D

3.3V Interface Pull-ups

These internal pull-ups are missing in Revs A01 & A01P.

=PP3V3_S5_MCP_A01

44

8

MCP_A01&MCP_A01P&MCP_A01Q

PM_LATRIGGER_L

13 19

OUT

PCIE_WAKE_L

17 31 32

OUT

JTAG_MCP_TDI

6

13 21

OUT

JTAG_MCP_TMS

6

13 21

OUT

PM_SYSRST_DEBOUNCE_L

21 26

C

OUT

TP_MCP_LID_L

21

OUT

MCP_LID_L

MAKE_BASE=TRUE

SMC_WAKE_SCI_L

21 42

OUT

SMC_RUNTIME_SCI_L

21 42

OUT

PM_PWRBTN_L

21 42

OUT

PM_BATLOW_L

21 42

OUT

R2400
R2401
R2402
R2403
R2404
R2405

R2410
R2411
R2412
R2413

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

5%

1/16W MF-LF

5%

5%

5%

1/16W MF-LF

5%

1/16W MF-LF

5%

1/16W MF-LF

5%

5%

5%

1/16W MF-LF

5%

1/16W MF-LF

402

402

MF-LF1/16W

402

MF-LF1/16W

402

402

402

402

MF-LF1/16W

402

MF-LF1/16W

402

402

C

B

B

MCP79 A01 Silicon Support

A

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

SYNC_DATE=03/31/2008

DRAWING NUMBER

051-7546

SHT

NONE

A

REV.

A.0.0

OF

9623

1

8 7

6

5

4

3

2 1

MCP Core Power

=PPVCORE_S0_MCP

46

22

8

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

(No IG vs. EG data)

D

MCP PCIE (DVDD) Power

=PP1V05_S0_MCP_PEX_DVDD

C2500

C2515

MCP 1.05V AUX Power

=PP1V05_S5_MCP_VDD_AUXC

22 18

8 8

105 mA (A01) 131 mA (A01)

MCP FSB (VTT) Power

=PP1V05_S0_MCP_FSB

22

14

9

8

1182 mA (A01)

C

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

4.7UF

20%
X5R

402

1

4V

2

C2501

4.7UF

20%
X5R

402

1

C2502

4V

2

4.7UF

20%
X5R

402

1

C2503

4V

2

4.7UF

20%
X5R

402

1

1

C2504

1UF

4V

10%
10V

2

2

X5R
402-1

MCP SATA (DVDD) Power

=PP1V05_S0_MCP_SATA_DVDD

8 8

43 mA (A01)57 mA (A01)

4.7UF

20%
X5R

402

1

1

C2516

1UF

10%

4V

10V

2

2

X5R
402-1

1

C2517

1UF

10%
10V

2

X5R
402-1

1

C2518

0.1uF

20%
10V

2

CERM
402

1

C2519

0.1uF

20%
10V

2

CERM
402

MCP 1.05V RMGT Power

=PP1V05_ENET_MCP_RMGT

1

C2525

0.1uF

20%
10V

2

CERM
402

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)

1

C2530

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2526

0.1uF

20%
10V

2

CERM
402

1

C2531

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2532

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2533

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2534

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2505

1UF

10%
10V

2

X5R
402-1

1

C2535

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2506

1UF

10%
10V

2

X5R
402-1

C2520

4.7UF

C2528

4.7uF

1

C2536

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2507

1UF

10%
10V

2

X5R
402-1

20%

4V
X5R
402

20%

4V
X5R
402

1

C2508

0.1UF

20%
10V

2

CERM
402

1

1

C2521

0.1uF

20%
10V

2

2

CERM
402

1

1

C2529

0.1uF

20%
10V

2

2

CERM
402

1

C2509

0.1UF

20%
10V

2

CERM
402

1

C2510

0.1UF

20%
10V

2

CERM
402

1

C2511

0.1UF

20%
10V

2

CERM
402

1

C2512

0.1UF

20%
10V

2

CERM
402

=PP1V05_S0_MCP_AVDD_UF

8

333 mA (A01)

=PP1V05_S0_MCP_PLL_UF

8

562 mA (A01)

1

C2513

0.1UF

20%
10V

2

CERM
402

L2570

30-OHM-5A

1 2

0603

L2575

30-OHM-5A

1 2

0603

R2580

0.2

1 2

1%

1/6W

MF

C2580

402-HF

4.7UF

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)

1

C2570

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)

1

C2575

2.2UF

20%

6.3V

2

402-LF

1

1

20%

4V

2

X5R
402

2

1

C2571

2.2UF

20%

6.3V

2

CERM
402-LF

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2576

2.2UF

20%

6.3V

2

CERMCERM
402-LF

PP1V05_S0_MCP_PLL_FSB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

C2581

2.2UF

20%

6.3V
CERM
402-LF

1

C2572

2.2UF

20%

6.3V

2

CERM
402-LF

14

270 mA (A01)

1

C2573

2.2UF

20%

6.3V

2

CERM
402-LF

8

127 mA (A01)

PP1V05_S0_MCP_PEX_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2574

2.2UF

20%

6.3V

2

CERM
402-LF

8

206 mA (A01)

D

C

MCP Memory Power

=PP1V8R1V5_S0_MCP_MEM

16

8

4771 mA (A01, DDR3)

1

C2553

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2544

0.1UF

20%
10V

2

CERM
402

8

MCP 3.3V Power

=PP3V3_S0_MCP

22

21

8

450 mA (A01)

C2540

4.7UF

1

C2551

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2542

0.1UF

20%
10V

2

CERM
402

1

1

C2541

0.1UF

20%
X5R

402

4V

20%
10V

2

2

CERM
402

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)

1

C2550

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2552

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2543

0.1UF

20%
10V

2

CERM
402

B

MCP 3.3V AUX/USB Power

=PP3V3_S5_MCP

22

8

266 mA (A01)

MCP 3.3V/1.5V HDA Power

=PP3V3R1V5_S0_MCP_HDA

21

8

7 mA (A01)

A

=PP1V05_ENET_MCP_PLL_MAC

8

5 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2560

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2562

2.2UF

20%

6.3V

2

CERM
402-LF

L2595

30-OHM-1.7A

1 2

0402

C2595

4.7UF

20%
X5R

402

4V

PP1V05_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2596

0.1UF

20%

10V

2

2

CERM

402

7 6

18

5 mA (A01)

1

C2545

0.1UF

20%
10V

2

CERM
402

=PP3V3_S0_MCP_PLL_UF

19 mA (A01)

1

C2546

0.1UF

20%
10V

2

CERM
402

MCP 3.3V Ethernet Power

=PP3V3_ENET_MCP_RMGT

24

18

8

83 mA (A01)

24

18

1

C2547

0.1UF

20%
10V

2

CERM
402

1

C2548

0.1UF

20%
10V

2

CERM
402

L2555

30-OHM-1.7A

1 2

0402

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

2

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

2

MCP79 Ethernet VRef

=PP3V3_ENET_MCP_RMGT

8

1

R2591

1.47K

1%
1/16W
MF-LF

402

2

1

R2590

1.47K

1%
1/16W
MF-LF

402

2

5

1

C2549

0.1UF

20%
10V

2

CERM
402

PP3V3_S0_MCP_PLL_USB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

C2555

2.2UF

20%

6.3V
CERM
402-LF

C2564

2.2UF

20%

6.3V
CERM
402-LF

MCP_MII_VREF

1

C2591

0.1UF

20%
10V

2

CERM
402

19 mA (A01)

18

OUT

L2582

30-OHM-1.7A

1 2

0402

C2582

4.7UF

20%

4V
X5R
402

L2584

20

30-OHM-1.7A

1 2

0402

C2584

4.7UF

20%
X5R

402

4V

PP1V05_S0_MCP_PLL_PEX

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2583

0.1UF

20%
10V

2

2

CERM
402

PP1V05_S0_MCP_PLL_SATA

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2585

0.1UF

20%
10V

2

2

CERM
402

17

84 mA (A01)

20

84 mA (A01)

B

L2586

30-OHM-1.7A

1 2

0402

C2586

4.7UF

20%

4V
X5R
402

L2588

30-OHM-1.7A

1 2

0402

C2588

4.7UF

20%

4V
X5R
402

4

3

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2587

0.1UF

20%
10V

2

2

CERM
402

1

1

C2589

0.1UF

20%
10V

2

2

CERM
402

87 mA (A01)

PP1V05_S0_MCP_PLL_NV

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2590

0.1UF

20%
10V

2

CERM
402

SYNC_MASTER=T18_MLB

APPLE INC.

2

16

21

37 mA (A01)

MCP Standard Decoupling

SYNC_DATE=06/18/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

OF

24

96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

=PP3V3R1V8_S0_MCP_IFP_VDD

Apple: 1x 2.2uF 0402 (2.2 uF)

18

8

190 mA (A01, 1.8V)

D

=PP1V05_S0_MCP_HDMI_VDD

18

8

95 mA (A01)

C2615

4.7UF

20%
X5R

402

1

C2610

2.2UF

20%

6.3V

2

CERM
402-LF

1

1

C2616

2.2UF

4V

20%

6.3V

2

2

CERM
402-LF

=PP3V3_S0_MCP_DAC_UF

8

206 mA (A01)

NO STUFF

L2650

30-OHM-1.7A

1 2

0402

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

NO STUFF

1

C2650

2.2UF

20%

6.3V

2

CERM
402-LF

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

R2651

0

5%
1/16W
MF-LF
402

2

18

206 mA (A01)

D

18

18

18

18

MCP_HDMI_RSET

89 89

18

MCP_HDMI_VPROBE

89

18

C

NO STUFF

C2620

0.1UF

20%
10V

CERM

402

1

R2620

1

1K

1%
1/16W
MF-LF
402

2

2

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

L2640

=PP3V3_S0_MCP_VPLL_UF

8

16 mA (A01)

30-OHM-1.7A

1 2

0402

C2640

4.7UF

6.3V
CERM

20%
603

1

2

MCP_IFPAB_RSET

18

MCP_IFPAB_VPROBE

18

89

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: ???

PP3V3_S0_MCP_VPLL

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2641

0.1uF

20%
10V

2

CERM
402

NO STUFF

C2630

0.1UF

20%
10V

CERM

402

NO STUFF

1

R2630

1

1K

1%
1/16W
MF-LF
402

2

2

18

16 mA (A01)

18

89

18

89

18

18

89

89

18

89

18

TP_MCP_RGB_DAC_RSET

18

TP_MCP_RGB_DAC_VREF

18

MCP_TV_DAC_RSET

18

89

MCP_TV_DAC_VREF

18

89

MCP_CLK27M_XTALIN

18

MCP_CLK27M_XTALOUT

18

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB

CRT_IG_HSYNC
CRT_IG_VSYNC

B

NC_MCP_RGB_RED

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNCTP_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

MAKE_BASE=TRUE

C

B

HDCP ROM

WF: Open question on which packge option(s) nVidia can support.

=PP3V3_S0_HDCPROM

8

1

C2690

0.1UF

CERM

1

20%
10V

2

402

1
2
3

U2695

AT24C08

A0
A1
A2

VCC

SOIC

GND

8

4

OMIT

SDA
SCL

WP

5
6

7

=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL

HDCPROM_WP

R2690

10K

1/16W
MF-LF

402

5%

2

A

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

8

7 6

45

BI

45

IN

MCP Graphics Support

SYNC_MASTER=AMASON_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

25 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

RTC Power Sources

=PP3V3_S5_RTC_D

8

1

VIN

U2801

MIC5232-2.8YD5

TSOT-23-5

1

10%
10V

2

X5R
402

R2811

10M

1/16W
MF-LF

402

3

GND

2

RTC Crystal

1

5%

2

D

C2802

1UF

RTC_CLK32K_XTALOUT

21

IN

NO STUFF

C

RTC_CLK32K_XTALIN

21

OUT

MCP 25MHz Crystal

MCP_CLK25M_XTALOUT

21

IN

MCP_CLK25M_XTALIN

21

OUT

NO STUFF

R2816

1/16W
MF-LF

402

1

1M

5%

2

VOUTEN

NC

R2810

1 2

R2815

1 2

0

5%
1/16W
MF-LF

402

0

5%
1/16W
MF-LF

402

5

4

RTC_DISCHARGE_R

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

R2801

1/16W
MF-LF

CRITICAL

Y2810

32.768K

7X1.5X1.4-SM

CRITICAL

Y2815

25.0000M

SM-3.2X2.5MM

402

10

5%

1

2

1 4

1 3

C2801

NO STUFF

R2802

1.0M

5%
1/10W
MF-LF

603

NC

2 4

NC

1UF

10%

6.3V
CERM

402

12

C2810

12pF

1 2

5%

50V

CERM

402

C2811

12pF

1 2

5%

50V

CERM

402

C2815

12pF

1 2

5%

50V

CERM

402

C2816

12pF

1 2

5%

50V

CERM

402

1

R2800

100

5%
1/16W
MF-LF

1

402

2

PP3V3_G3_SUPERCAP

2

1

C2800

0.08F

2%

3.3V

2

XHHG
SM

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

22 8 21

19 83 90

IN

9

17

IN

19

IN

19 90

IN

LPC_RESET_L

PCIE_RESET_L

MEM_VTT_EN_R

LPC_CLK33M_SMC_R

MCP S0 PWRGD & CPU_VLD

=PP3V3_S5_MCPPWRGD

B

ALL_SYS_PWRGD

42 68

IN

VR_PWRGOOD_DELAY

62

IN

MCP_CPUVDD_EN

21

IN

A

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
but results in MCP79 ROMSIP sequence happening after CPU powers up.

MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

U2850

MCPSEQ_SMC

1

C2850

0.1UF

20%
10V

2

CERM
402

TC7SZ08AFEAPE

SOT665

A

B

S0_AND_IMVP_PGOOD

MCPSEQ_SMC

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_MIX

R2851

0

1 2

5%
1/16W
MF-LF

402

MCPSEQ_SMC

R2853

0

1 2

5%
1/16W
MF-LF

402

MCPSEQ_MIX

R2852

0

1 2

5%
1/16W
MF-LF

402

MCPSEQ_SMC

R2850

0

1 2

5%
1/16W
MF-LF

402

MCP_PS_PWRGD

MCP_CPU_VLD

PM_CLK32K_SUSCLK_R

21 90

IN

21

OUTY

21

OUT

PM_SYSRST_L

42

IN

XDP_DBRESET_L

10 13 21 23

IN

Reset Button

XDP

R2896

0

1 2

5%
1/16W
MF-LF

402

R2897

SILK_PART=FP SYS RESET

Platform Reset Connections

LPC Reset (Unbuffered)

R2881

33

1 2

5%
1/16W
MF-LF

402

R2890

0

1 2

5%
1/16W
MF-LF

402

R2893

0

1 2

5%
1/16W
MF-LF

402

R2895

1 2

1/16W
MF-LF

R2825

33

1 2

5%
1/16W
MF-LF

402

R2827

33

1 2

5%
1/16W
MF-LF

402

R2829

22

1 2

5%
1/16W
MF-LF

402

OUT

OMIT

1/16W
MF-LF

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

PCIE Reset (Unbuffered)

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

R2899

1 2

1

0

5%

402

2

10K pull-up to 3.3V S0 inside MCP

33

5%
1/16W
MF-LF

402

PM_SYSRST_DEBOUNCE_L

NO STUFF

1

C2899

1UF

10%
10V

2

X5R
402

R2883

1 2

1/16W
MF-LF

R2892

1 2

1/16W
MF-LF

GMUX_PCIE_RESET_L

R2891

1 2

1/16W
MF-LF

BKLT_PLT_RST_L

R2894

1 2

0

EXCARD_RESET_L

5%

402

R2870

33

1 2

5%
1/16W
MF-LF

402

R2826

1 2

1/16W
MF-LF

APPLE INC.

DEBUG_RESET_L

33

SMC_LRESET_L

5%

402

0

FW_RESET_L

5%

402

MAKE_BASE=TRUE

=GMUX_PCIE_RESET_L

0

PCA9557D_RESET_L

5%

402

0

MINI_RESET_L

5%
1/16W
MF-LF

402

MEM_VTT_EN

LPC_CLK33M_SMC

33

LPC_CLK33M_LPCPLUS

5%

PLACEMENT_NOTE=Place close to U1400

402

LPC_CLK33M_GMUX

PM_CLK32K_SUSCLK

SB Misc

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

44

OUT

42

OUT

36

OUT

83

OUT

27

OUT

85

OUT

31

OUT

32

OUT

9

OUT

42 90

OUT

44 90

OUT

83

OUT

42 90

OUT

SYNC_DATE=12/17/2007

051-7546

SHT

OF

26

96

D

C

B

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PP3V3_S5_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

D

VREFMRGN
NO_VREFMRGN

C

B

=PP3V3_S3_VREFMRGN

8

ADDR=0x30(WR)/0x31(RD)

=I2C_PCA9557D_SCL

45

IN

=I2C_PCA9557D_SDA

45

BI

DAC channel A B A B C D
Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00
Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF
Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA
Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA
Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V
Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V
Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V
Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV
(per DAC LSB)

VREFMRGN

1

C2900

2.2UF

20%

6.3V

2

CERM
402-LF

IN

BI

=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA

45

45

ADDR=0x98(WR)/0x99(RD)

1

2

VREFMRGN

1

C2901

0.1UF

20%

10V

2

CERM

402

VREFMRGN

C2902

0.1UF

20%
10V
CERM
402

6

7

9

10

3
4
5

1
2

SCL

SDA

A0

A1

PCA9557

A0
A1
A2

SCL
SDA

THRM

PAD

17

VREFMRGN

U2900

8
VDD

MSOP

DAC5574

GND

3

16

VCC

U2901

QFN

GND

8

VOUTA

VOUTB

VOUTC

VOUTD

VREFMRGN

P0
P1
P2
P3
P4
P5
P6
P7

RESET*

6

MEM A VREF CA

1

VREFMRGN_DQ_SODIMM

2

VREFMRGN_CA_SODIMM

4

VREFMRGN_CPUFSB

5

VREFMRGN_FRAMEBUF

6

NC

7
9
10
11
12
13
14

NC

15

MEM B VREF DQMEM A VREF DQ

VREFMRGN_CPUFSB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_FRAMEBUF_EN

PCA9557D_RESET_L

5

MEM B VREF CA

CPU FSB VREF

4

FRAME BUFFER VREF

3

2 1

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

=PPVTT_S3_DDR_BUF

64

8

10mA max load

R2903

1 2

B1

VREFMRGN

1

C2903

0.1UF

20%
10V

2

CERM
402

VREFMRGN

1

C2904

0.1UF

20%
10V

2

CERM
402

VREFMRGN

1

C2905

0.1UF

20%
10V

2

CERM
402

27

27

27

27

27

27

26

IN

A2

A3

C2

C3

A2

A3

C2

C3

A2

A3

C2

C3

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

U2902

MAX4253

UCSP

A1

A4

U2902

MAX4253

UCSP

C1

C4

U2903

MAX4253

UCSP

A1

A4

U2903

MAX4253

UCSP

C1

C4

U2904

MAX4253

UCSP

A1

A4

U2904

MAX4253

UCSP

C1

C4

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMA_EN

27

R2901

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

27

R2902

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

27

R2907

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMB_EN

27

R2908

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF_EN

27

R2915

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB_EN

27

R2913

100K

1/16W
MF-LF

100K

1/16W
MF-LF

100K

1/16W
MF-LF

100K

1/16W
MF-LF

100K

1/16W
MF-LF

100K

1/16W
MF-LF

R2904

1 2

R2905

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

1 2

R2906

1 2

R2909

1 2

R2910

1 2

R2911

1 2

R2912

1 2

R2916

1 2

R2917

1 2

R2914

1 2

VREFMRGN

200

1%
1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to J3100.1

1/16W
MF-LF

402

VREFMRGN

200

1%
1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to J3200.1

1/16W
MF-LF

402

VREFMRGN

200

1%
1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to J3100.126

1/16W
MF-LF

402

VREFMRGN

200

1%
1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to J3200.126

1/16W
MF-LF

402

VREFMRGN

49.9

1%

Place close to U8400, U8450

1/16W
MF-LF

402

VREFMRGN

49.9

1%

Place close to U8500, U8550

1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to U1000.AD26

1/16W
MF-LF

402

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

CPU_GTLREF

28

29

28

29

9

OUT

9

OUT

10 87

OUT

D

C

B

A

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

116S0004
116S0004
116S0004

QTY

1116S0004

1 R2909 CRITICAL

8

DESCRIPTION

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

7 6

REFERENCE DES

R2903 CRITICAL

CRITICAL

CRITICAL1 R2905

CRITICAL1 R2911

BOM OPTION
NO_VREFMRGN
NO_VREFMRGN
NO_VREFMRGN
NO_VREFMRGN

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SYNC_DATE=07/22/2008

051-7546

SHT

OF

9627

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

Page Notes

Power aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:

D

(NONE)

C

B

8

A

=PPSPD_S0_MEM_A

1

C3140

2

2.2UF

20%

6.3V
CERM
402-LF

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

1

R3140

10K

5%
1/16W
MF-LF
402

2

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_A_A<12>
MEM_A_A<9>

MEM_A_A<8>
MEM_A_A<5>

MEM_A_A<3>
MEM_A_A<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_A<10>
MEM_A_BA<0>

MEM_A_WE_L
MEM_A_CAS_L

MEM_A_A<13>
MEM_A_CS_L<1>

MEM_A_DQ<33>
MEM_A_DQ<32>

MEM_A_DQS_N<4>
MEM_A_DQS_P<4>

MEM_A_DQ<34>
MEM_A_DQ<35>

MEM_A_DQ<44>
MEM_A_DQ<41>

MEM_A_DM<5>

MEM_A_DQ<45>
MEM_A_DQ<42>

MEM_A_DQ<52>
MEM_A_DQ<51>

MEM_A_DQS_N<6>
MEM_A_DQS_P<6>

MEM_A_DQ<55>
MEM_A_DQ<54>

MEM_A_DQ<61>
MEM_A_DQ<60>

MEM_A_DM<7>

MEM_A_DQ<58>
MEM_A_DQ<59>

MEM_A_SA<0>

MEM_A_SA<1>

1

R3141

10K

5%
1/16W
MF-LF
402

2

=PP1V5_S0_MEM_A

8

=PP1V5_S3_MEM_A

8

73 74
75 76
77
79
81 82

85
87 88
89

93 94

99
101
103
105 106
107
109
111 112
113
115
117 118
119
121
123 124
125
127 128
129
131
133 134
135
137
139
141
143
145
147
149
151
153
155 156
157
159
161 162
163
165
167 168
169
171
173
175
177
179
181
183
185
187
189 190
191
193
195 196
197
199
201 202
203 204

1

C3100

10UF

20%

6.3V

2

X5R
603

KEY

CKE0
VDD
NC

J3100

BA2
VDD
A12/BC*
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0*
VDD
A10/AP
BA0
VDD
WE*
CAS*
VDD
A13
S1*
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4*
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6*
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

516-0196

SPD ADDR=0xA0(WR)/0xA1(RD)

CKE1

F-RT-THB

(SYMBOL 2 OF 2)

CK1*

DDR3-SODIMM-DUAL-M97-3

RAS*

ODT0

ODT1

VREFCA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5*

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7*

DQS7

DQ62
DQ63

EVENT*

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VTT

A15
A14

A11

CK1

BA1

S0*

DM4

DM6

SDA
SCL

VDD

1

2

A7

A6
A4

A2
A0

NC

C3101

10UF

20%

6.3V
X5R
603

78
80

8483
86

90
9291

9695
9897
100
102
104

108
110

114
116

120
122

126

130
132

136
138
140
142
144
146
148
150
152
154

158
160

164
166

170
172
174
176
178
180
182
184
186
188

192
194

198
200

MEM_A_CKE<1>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_A<11>
MEM_A_A<7>

MEM_A_A<6>
MEM_A_A<4>

MEM_A_A<2>
MEM_A_A<0>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_BA<1>
MEM_A_RAS_L

MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_DQ<36>
MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<38>
MEM_A_DQ<39>

MEM_A_DQ<47>
MEM_A_DQ<40>

MEM_A_DQS_N<5>
MEM_A_DQS_P<5>

MEM_A_DQ<46>
MEM_A_DQ<43>

MEM_A_DQ<48>
MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50>
MEM_A_DQ<49>

MEM_A_DQ<57>
MEM_A_DQ<56>

MEM_A_DQS_N<7>
MEM_A_DQS_P<7>

MEM_A_DQ<62>
MEM_A_DQ<63>

MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

1

C3110

0.1UF 0.1UF

20%
10V

2

CERM
402

1

C3111

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFDQ_A

27

15 88

IN

9

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

21 29 42

OUT

45

BI

45

IN

1

C3112

0.1UF

20%
10V

2

CERM
402

1

C3113

0.1UF

20%
10V

2

CERM
402

1

C3130

2.2UF

20%

6.3V

2

CERM
402-LF

15 88

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

1

C3135

2.2UF

20%

6.3V

2

CERM
402-LF

=PP0V75_S0_MEM_VTT_A

1

C3114

0.1UF

20%
10V

2

CERM
402

1

C3131

0.1UF

20%
10V

2

CERM
402

MEM_A_DQ<0>
MEM_A_DQ<1>

MEM_A_DM<0>

MEM_A_DQ<3>
MEM_A_DQ<2>

MEM_A_DQ<9>
MEM_A_DQ<13>

MEM_A_DQS_N<1>
MEM_A_DQS_P<1>

MEM_A_DQ<11>
MEM_A_DQ<14>

MEM_A_DQ<16>
MEM_A_DQ<18>

MEM_A_DQS_N<2>
MEM_A_DQS_P<2>

MEM_A_DQ<23>
MEM_A_DQ<19>

MEM_A_DQ<24>
MEM_A_DQ<30>

MEM_A_DM<3>

MEM_A_DQ<27>
MEM_A_DQ<25>

PP0V75_S3_MEM_VREFCA_A

1

C3136

0.1UF

20%
10V

2

CERM
402

1

C3115

0.1UF

20%
10V 10V

2

CERM
402

1

C3116

0.1UF

20%

2

CERM
402

1 2

VREFDQ

3

VSS

5

DQ0
DQ1

VSS

DM0

VSS
DQ2
DQ3

VSS
DQ8
DQ9

VSS
DQS1*
DQS1

VSS
DQ10
DQ11

VSS
DQ16
DQ17

VSS
DQS2*
DQS2

VSS
DQ18
DQ19

VSS
DQ24
DQ25

VSS
DM3

VSS
DQ26
DQ27

VSS

CRITICAL

J3100

7

9
11
13 14
15
17
19 20
21
23
25 26
27
29
31 32
33
35
37 38
39
41
43 44
45
47
49
51
53
55
57
59
61
63
65 66
67
69
71 72

516-0196

8

1

C3117

0.1UF

20%
10V

2

CERM
402

VSS
DQ4
DQ5

VSS

DQS0*

DQS0

F-RT-THB

VSS

DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

(SYMBOL 1 OF 2)

RESET*

VSS
DQ14
DQ15

VSS

DDR3-SODIMM-DUAL-M97-3

DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3*

DQS3

VSS
DQ30
DQ31

VSS

KEY

27

1

C3118

2

4
6
8
10
12

16
18

22
24

28
30

34
36

40
42

46
48
50
52
54
56
58
60
62
64

68
70

0.1UF

20%
10V
CERM
402

1

C3119

0.1UF

20%

10V

2

CERM
402

MEM_A_DQ<4>
MEM_A_DQ<5>

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>

MEM_A_DQ<6>
MEM_A_DQ<7>

MEM_A_DQ<8>
MEM_A_DQ<12>

MEM_A_DM<1>
MEM_RESET_L

MEM_A_DQ<15>
MEM_A_DQ<10>

MEM_A_DQ<21>
MEM_A_DQ<20>

MEM_A_DM<2>

MEM_A_DQ<17>
MEM_A_DQ<22>

MEM_A_DQ<29>
MEM_A_DQ<28>

MEM_A_DQS_N<3>
MEM_A_DQS_P<3>

MEM_A_DQ<26>
MEM_A_DQ<31>

1

C3120

0.1UF

20%
10V

2

CERM
402

1

C3121

0.1UF

20%
10V

2

CERM
402

1

C3122

0.1UF

20%
10V

2

CERM
402

1

C3123

0.1UF

20%
10V

2

CERM
402

D

15 88

BI

15 88

BIBI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

29 30

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

C

B

"Factory" (top) slot

DDR3 SO-DIMM Connector A

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7546

SHT

SYNC_DATE=07/22/2008

REV.

A.0.0

OF

9628

A

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

Power aliases required by this page:

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

BOM options provided by this page:

D

(NONE)

C

B

A

Page Notes

=PPSPD_S0_MEM_B

8

1

R3240

10K

5%
1/16W
MF-LF
402

2

1

C3240

2.2UF

20%

6.3V

2

CERM
402-LF

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_B_A<12>
MEM_B_A<9>

MEM_B_A<8>
MEM_B_A<5>

MEM_B_A<3>
MEM_B_A<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_A<10>
MEM_B_BA<0>

MEM_B_WE_L
MEM_B_CAS_L

MEM_B_A<13>
MEM_B_CS_L<1>

MEM_B_DQ<32>
MEM_B_DQ<37>

MEM_B_DQS_N<4>
MEM_B_DQS_P<4>

MEM_B_DQ<34>
MEM_B_DQ<35>

MEM_B_DQ<41>
MEM_B_DQ<40>

MEM_B_DM<5>

MEM_B_DQ<43>
MEM_B_DQ<42>

MEM_B_DQ<55>
MEM_B_DQ<49>

MEM_B_DQS_N<6>
MEM_B_DQS_P<6>

MEM_B_DQ<52>
MEM_B_DQ<51>

MEM_B_DQ<56>
MEM_B_DQ<57>

MEM_B_DM<7>

MEM_B_DQ<63>
MEM_B_DQ<59>

MEM_B_SA<0>

MEM_B_SA<1>

1

R3241

10K

5%
1/16W
MF-LF
402

2

=PP1V5_S0_MEM_B

8

=PP1V5_S3_MEM_B

8

73 74
75 76
77
79
81 82

85
87 88
89

93 94

99
101
103
105 106
107
109
111 112
113
115
117 118
119
121
123 124
125
127 128
129
131
133 134
135
137
139
141
143
145
147
149
151
153
155 156
157
159
161 162
163
165
167 168
169
171
173
175
177
179
181
183
185
187
189 190
191
193
195 196
197
199
201 202
203 204

205 206
207 208
209 210
211 212

1

C3200

10UF

20%

6.3V

2

X5R
603

KEY

(2 OF 2)

DDR3-SODIMM

MTG PINS

MTG PIN

MTG PIN

MTG PIN

CKE1

CK1*

RAS*

ODT0

ODT1

VREFCA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5*

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7*

DQS7

DQ62
DQ63

EVENT*

CKE0

VDD
NC

BA2

J3200

F-RT-BGA3

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

MTG PIN

MTG PIN

MTG PIN MTG PIN

MTG PIN

516s0704

SPD ADDR=0xA2(WR)/0xA3(RD)

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VTT

A15
A14

A11

CK1

BA1

S0*

DM4

DM6

SDA
SCL

VDD

1

2

A7

A6
A4

A2
A0

NC

C3201

10UF

20%

6.3V
X5R
603

78
80

8483
86

90
9291

9695
9897
100
102
104

108
110

114
116

120
122

126

130
132

136
138
140
142
144
146
148
150
152
154

158
160

164
166

170
172
174
176
178
180
182
184
186
188

192
194

198
200

MEM_B_CKE<1>

MEM_B_A<15>
MEM_B_A<14>

MEM_B_A<11>
MEM_B_A<7>

MEM_B_A<6>
MEM_B_A<4>

MEM_B_A<2>
MEM_B_A<0>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_BA<1>
MEM_B_RAS_L

MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_DQ<33>
MEM_B_DQ<36>

MEM_B_DM<4>

MEM_B_DQ<38>
MEM_B_DQ<39>

MEM_B_DQ<44>
MEM_B_DQ<45>

MEM_B_DQS_N<5>
MEM_B_DQS_P<5>

MEM_B_DQ<47>
MEM_B_DQ<46>

MEM_B_DQ<48>
MEM_B_DQ<54>

MEM_B_DM<6>

MEM_B_DQ<53>
MEM_B_DQ<50>

MEM_B_DQ<60>
MEM_B_DQ<61>

MEM_B_DQS_N<7>
MEM_B_DQS_P<7>

MEM_B_DQ<58>
MEM_B_DQ<62>

MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

1

C3210

0.1UF

20%
10V

2

CERM
402

1

C3211

0.1UF

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFDQ_B

27

15 88

IN

9

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

21 28 42

OUT

45

BI

45

IN

1

C3212

0.1UF

20%
10V

2

CERM
402

1

C3213

0.1UF

20%
10V

2

CERM
402

1

C3230

2.2UF

20%

6.3V

2

CERM
402-LF

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

1

C3235

2.2UF

20%

6.3V

2

CERM
402-LF

=PP0V75_S0_MEM_VTT_B

1

C3214

0.1UF

20%
10V 10V

2

CERM
402

1

C3231

0.1UF

20%
10V

2

CERM
402

MEM_B_DQ<0>
MEM_B_DQ<1>

MEM_B_DM<0>

MEM_B_DQ<2>
MEM_B_DQ<3>

MEM_B_DQ<28>
MEM_B_DQ<24>

MEM_B_DQS_N<3>
MEM_B_DQS_P<3>

MEM_B_DQ<31>
MEM_B_DQ<30>

MEM_B_DQ<9>
MEM_B_DQ<8>

MEM_B_DQS_N<1>
MEM_B_DQS_P<1>

MEM_B_DQ<15>
MEM_B_DQ<10>

MEM_B_DQ<21>
MEM_B_DQ<17>

MEM_B_DM<2>

MEM_B_DQ<18>
MEM_B_DQ<22>

PP0V75_S3_MEM_VREFCA_B

1

C3236

0.1UF

20%
10V

2

CERM
402

1

C3215

0.1UF

20%

2

CERM
402

1

C3216

0.1UF

20%
10V

2

CERM
402

1 2

VREFDQ

3

VSS

5

DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1*
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2*
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

CRITICAL

J3200

F-RT-BGA3

7

9
11
13 14
15
17
19 20
21
23
25 26
27
29
31 32
33
35
37 38
39
41
43 44
45
47
49
51
53
55
57
59
61
63
65 66
67
69
71 72

516s0704

8

1

C3217

0.1UF

20%
10V

2

CERM
402

(1 OF 2)

DDR3-SODIMM

RESET*

KEY

27

DQS0*

DQS0

VSS

VSS
DQ12
DQ13

VSS

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3*

DQS3

VSS
DQ30
DQ31

VSS

VSS
DQ4
DQ5
VSS

DQ6
DQ7

DM1

DM2

1

2

4
6
8
10
12

16
18

22
24

28
30

34
36

40
42

46
48
50
52
54
56
58
60
62
64

68
70

C3218

0.1UF

20%
10V
CERM
402

1

C3219

0.1UF

20%
10V

2

CERM
402

MEM_B_DQ<4>
MEM_B_DQ<5>

MEM_B_DQS_N<0>
MEM_B_DQS_P<0>

MEM_B_DQ<6>
MEM_B_DQ<7>

MEM_B_DQ<29>
MEM_B_DQ<25>

MEM_B_DM<3>
MEM_RESET_L

MEM_B_DQ<26>
MEM_B_DQ<27>

MEM_B_DQ<13>
MEM_B_DQ<12>

MEM_B_DM<1>

MEM_B_DQ<14>
MEM_B_DQ<11>

MEM_B_DQ<20>
MEM_B_DQ<16>

MEM_B_DQS_N<2>
MEM_B_DQS_P<2>

MEM_B_DQ<19>
MEM_B_DQ<23>

1

C3220

0.1UF

20%
10V

2

CERM
402

1

C3221

0.1UF

20%

10V

2

CERM
402

1

C3222

0.1UF

20%
10V

2

CERM
402

1

C3223

0.1UF

20%
10V

2

CERM
402

D

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

28 30

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

C

B

"Expansion" (bottom) slot

DDR3 SO-DIMM Connector B

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7546

SHT

SYNC_DATE=07/22/2008

OF

29 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

D

DDR3 RESET Support

MCP79 cannot control this signal directly since it must be high in sleep and MCP MEM rails are not powered in sleep.

=PP1V5_S3_MEMRESET

8

3.3V input must be stable before
before 1.5V starts to rise to

=PP3V3_S5_MEMRESET

8

C

MEMRESET_HW

R3300

MEMRESET_HW

R3301

avoid glitch on MEM_RESET_L.

1

10K

5%
1/16W
MF-LF

402

2

MEM_RESET_RC_L

MEMRESET_HW

1

1

20K

1/16W
MF-LF

402

C3300

0.1UF

5%

20%
10V

2

CERM
402

2

5

MEMRESET_HW

1

R3305

20K

5%
1/16W
MF-LF
402

2

MEM_RESET

MEMRESET_HW

3

Q3305

MMDT3904-X-G

SOT-363-LF

4

2

1

R3310

1K

5%
1/16W
MF-LF
402

2

MEMRESET_HW

6

Q3305

MMDT3904-X-G

SOT-363-LF

1

MEM_RESET_L

MEMRESET_MCP

1

R3309

0

5%
1/16W
MF-LF
402

2

28 29

OUT

C

MCP_MEM_RESET_L

16

IN

B

B

DDR3 Support

A

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

30 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

PCIE_MINI_PRSNT_L

17

OUT

3

D

Q3401

SSM6N15FEAPE

SOT563

5

S G

4

D

17

OUT

MINI_CLKREQ_L

6

1

D

S G

Q3401

SSM6N15FEAPE

SOT563

2

6

AP_PWR_EN

5

34 21

IN

4

5V S3 WLAN FET

MOSFET
CHANNEL

RDS(ON)

LOADING

3

FDC606P
P-TYPE
26 mOhm @4.5V

0.8 A (EDP)

2 1

D

CRITICAL
518S0610

J3401

20347-325E-12

C

B

F-RT-SM

PLACEMENT_NOTE=Place close to J3401.

1 2

0.1uF

16V

C3430

31

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

NC

16

NC

17
18
19
20
21
22
23
24
25

26
27
28
29
30

32

PCIE_MINI_D2R_P
PCIE_MINI_D2R_N

PCIE_MINI_R2D_P

95

89

PCIE_MINI_R2D_N

95

89

PCIE_CLK100M_MINI_CONN_P

95

PCIE_CLK100M_MINI_CONN_N

95

MINI_CLKREQ_Q_L

PCIE_WAKE_L

PP5V_S3_BTCAMERA_F

USB_CAMERA_CONN_P

95

USB_CAMERA_CONN_N

95

CONN_USB2_BT_P

95

CONN_USB2_BT_N

95

89 17

OUT

89 17

OUT

32 23 17

OUT

I2C_ALS_SDA
I2C_ALS_SCL

PLACEMENT_NOTE=Place close to J3401.

PLACEMENT_NOTE=Place close to J3401.

45

BI

45

IN

PLACEMENT_NOTE=Place close to J3401.

PLACEMENT_NOTE=Place close to J3401.

C3431

1 2

0.1uF

10%

DLP11S

SYM_VER-1

L3402

90-OHM
DLP0NS

SYM_VER-1

L3403

90-OHM
DLP0NS

SYM_VER-1

16V X5R

34

PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N

34

34

402X5R10%

L3401

90-OHM-100MA

1 2

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

1 2

1 2

PCIE_MINI_R2D_C_P

402

PCIE_MINI_R2D_C_N

AIRPORT

ALS
CAMERA

USB_CAMERA_P
USB_CAMERA_N

BLUETOOTH

USB_BT_P
USB_BT_N

1000 mA peak

750 mA nominal max

IN
IN

275 mA peak

206 mA nominal max

89 17

89 17

89 17

IN

89 17

IN

C3452

0.1uF

OUT

OUT

BI

BI

PP5V_WLAN

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

20%
10V

CERM

402

90 20

90 20

90 20

90 20

FERR-120-OHM-1.5A

C3422

0.1uF

PLACEMENT_NOTE=Place close to J3401.

L3405

FERR-120-OHM-1.5A

1

2

0402-LF

L3404

0402-LF

12

1

C3421

0.1uF

20%
10V

2

CERM

402

PLACEMENT_NOTE=Place close to Q3450.

12

20%
10V

CERM

402

PLACEMENT_NOTE=Place close to Q3450.

31

1

1

C3420

10UF

20%
10V

2

2

X5R
805

=PP5V_S3_BTCAMERA

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

PP5V_WLAN_F

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

8

Q3450

FDC606P_G

D

1 2 5 6

C3450

0.1UF

1 2

10%
16V
X5R
402

SOT-6

S

G

3

P5VWLAN_SS

4

C3451

0.033UF

10%
16V
X5R
402

1

2

R3450

100K

1 2

5%
1/16W
MF-LF

402

1

R3451

10K

5%
1/16W
MF-LF
402

2

=PP5V_S3_WLAN

MIN_LINE_WIDTH=1 mm
MIN_NECK_WIDTH=0.5 mm
VOLTAGE=5V

PM_WLAN_EN_L

8

34

IN

C

B

PP5V_WLAN_F

=PP3V3_S3_WLAN

TC7SZ08AFEAPE

MINI_RESET_CONN_L

SOT665

A

8

7 6

4

Y

U3401

5

2

WLAN_SMIT_BUF

A

1

B

3

MINI_RESET_L

8

74LVC1G17DRL

U3402

SOT-553

26

IN

1

R3453

33K

5%
1/16W

5

3 1

NC

NC

C3453

2

4

MF-LF
402

2

WLAN_SMIT_RC

1

1UF

10%

6.3V
2

CERM

402

1

R3454

62K

5%
1/16W
MF-LF
402

2

5

31

Right Clutch Connector

SYNC_MASTER=YITE_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

4

3

2

SCALE

NONE

SYNC_DATE=07/02/2008

051-7546

SHT

OF

31 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

D

EXPRESSCARD/34 FLEX CONNECTOR

L3502

90-OHM
DLP0NS

SYM_VER-1

SYM_VER-1

0.1uF

16V 402X5R10%

34

34

C3571

1 2

PCIE_CLK100M_EXCARD_CONN_N

PCIE_CLK100M_EXCARD_CONN_P

402

PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_P

0.1uF

16V10%

X5R

32

95

7

32

95

7

PCIE_EXCARD_R2D_N

32

89

95

7

PCIE_EXCARD_D2R_P

7

17 89

OUT

32

95

7

32

95

7

32

89

95

7

32

89

95

7

PCIE_CLK100M_EXCARD_CONN_N

32

95

7

EXCARD_CLKREQ_CONN_L

32

7

PP3V3_S0_EXCARD_SWITCH

32

7

PP3V3_S3_EXCARD_SWITCH

32

7

PP1V5_S0_EXCARD_SWITCH

32

7

=SMBUS_EXCARD_SDA

45

BI

EXCARD_CPUSB_L

32

7

USB2_EXCARD_CONN_N

32

95

7

EXCARD_CPPE_L

32

7

R3501

20 90

INPUT DECOUPLING

=PP3V3_S3_EXCARD

32

8

=PP1V5_S0_EXCARD

32

8

1

C3530

0.1uF

20%
10V

2

CERM
402

1

C3534

0.1uF

20%
10V

2

CERM
402

1

C3531

10uF

20%

6.3V

2

X5R
603

1

C3535

10uF

20%

6.3V

2

X5R
603

20 90

17 89

17 89

17 89

17 89

C

USB_EXCARD_N USB2_EXCARD_CONN_N

BI

USB_EXCARD_P USB2_EXCARD_CONN_P

BI

PCIE_CLK100M_EXCARD_N

IN

PCIE_CLK100M_EXCARD_P

IN

PCIE_EXCARD_R2D_C_N

IN

PCIE_EXCARD_R2D_C_P

IN

PLACEMENT_NOTE=Place close to J3500

PLACEMENT_NOTE=Place close to J3500

1 2

L3503

90-OHM-100MA

DLP11S

1 2

PLACEMENT_NOTE=Place close to J3500

1 2

C3570

PLACEMENT_NOTE=Place close to J3500

OUTPUT DECOUPLING

VOLTAGE=3.3V

MIN_LINE_WIDTH=.3mm

32

MIN_NECK_WIDTH=0.2mm

VOLTAGE=3.3V

MIN_LINE_WIDTH=.6mm
MIN_NECK_WIDTH=0.2mm

VOLTAGE=1.5V

MIN_LINE_WIDTH=.6mm
MIN_NECK_WIDTH=0.2mm

CRITICAL

U3500

=PP3V3_S3_EXCARD

32

8

=PP3V3_S0_EXCARD

32

8

=PP1V5_S0_EXCARD

32

8

SMC_EXCARD_PWR_EN

42

IN

TP_EXCARD_STBY_L

26

IN

20 43

IN

EXCARD_RESET_L

EXCARD_OC_L

B

R3500

MF-LF

1 2

0

4025%1/16W

EXCARD_SHDN_L_R

NC
NC
NC
NC
NC

TPS2231

AUXIN
VIN3P3

VIN1P5

SHDN*
STBY*
SYSRST*
OC*

4

NC0

5

NC1
NC2
NC3
NC4

QFN

VOUT3P3
VOUT1P5

THRML_PAD

GND

7

AUXOUT

PERST*

CPPE*

CPUSB*

RCLKEN

15
3
11

8
10
9

EXCARD_RCLKEN

18

21

17

2

12

20

1
6

19

13
14
16

PP3V3_S3_EXCARD_SWITCH

C3500

0.1uF

20%
10V
CERM
402

1

C3503

10uF

20%

6.3V

2

X5R
603

1

2

PP3V3_S0_EXCARD_SWITCH

1

2

C3501

0.1uF

10%
16V
X5R
402

1

C3504

10uF

20%

6.3V

2

X5R
603

PP1V5_S0_EXCARD_SWITCH

1

2

1

C3502

0.1uF

10%
16V
X5R
402

C3505

10uF

20%

6.3V

2

X5R
603

PLT_RESET_SWITCH_L

EXCARD_CPPE_L

EXCARD_CPUSB_L

32

7

32

7

9

OUT

9

95

VENICE

C3573

402X5R

VENICE

1 2

0.1uF

X5R16V 40210%

PCIE_FC_R2D_C_P

9

95

32

7

7

7

7

IN

PCIE_FC_R2D_C_N

9

95

IN

PLACEMENT_NOTE=Place close to J3501.

32

32

32

1 2

10% 16V

C3572

0.1uF

IN

9

95

IN

PCIE_FC_R2D_P

95

PCIE_FC_R2D_N

95

9

95

OUT

9

95

OUT

CRITICAL

J3500

502250-8727

F-RT-SM

28

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

NC

MF-LF

24
26

1 2

0

402

23
25
27

29

1/16W

FC_CLKREQ_L

PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N

PCIE_FC_D2R_P
PCIE_FC_D2R_N

NC

5%

PCIE_EXCARD_PRSNT_L

PCIE_EXCARD_R2D_P

PCIE_CLK100M_EXCARD_CONN_P

PCIE_EXCARD_D2R_N

PP3V3_S0_EXCARD_SWITCH

PP1V5_S0_EXCARD_SWITCH

EXCARD_CPPE_L

PLT_RESET_SWITCH_L

PCIE_WAKE_L

=SMBUS_EXCARD_SCL

USB2_EXCARD_CONN_P

CRITICAL

J3501

503219-0221

M-ST-SM

24
23

1

2
3 4
5 6
7 8
9

11 12
13 14
15 16
17 18
19
21 22

NC

10

NC
NC

NC

20

25
26

VENICE

7

OUT

7

7

7

OUT

7

17

=PP3V3_FC_CON

=PP1V5_FC_CON

FC_PRSNT_L
FC_RESET_L

32

89

95

7

17 89

32

95

32

32

7

32

17 23 31

32

45

BI

32

95

7

C

B

8

8

9

OUT

9

OUT

Venice Connector

=PP3V3_S3_EXCARD

32

8

=PP3V3_S0_EXCARD

32

8

1

5

74HC1G00GWDG

EXCARD_CPUSB_L

32

A

7

EXCARD_CPPE_L

32

7

C3550

0.1uF

CERM

20%
10V

402

8

1

2

1

2

U3551

3

SC70-5

4

SMC_EXCARD_CP

42 43

OUT

EXCARD_CLKREQ_CONN_L

32

7

7 6

R3561

100K

1/16W
MF-LF

402

5

74HC1G00GWDG

20%
10V

402

1

2

1

2

U3560

3

4

SC70-5

4

EXCARD_CLKREQ_L

17

OUT

3

1%

2

B1

EXCARD_RCLKEN

32

EXCARD_CLKREQ_CONN

A2

U3561

SN74LVC1G04YZPR

C2

BGA

C1

C3560

0.1uF

CERM

5

ExpressCard Connector

SYNC_MASTER=YITE_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

2

SYNC_DATE=07/02/2008

051-7546

SHT

OF

32

96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

WF: Marvell numbers, update for Realtek

C

18 91

IN

ENET_RESET_L is not asserted when WOL is active.
Hence, RC (R3725 and C3725) are made NOSTUFF.

B

=PP3V3_ENET_PHY
(43mA typ - 1000base-T)
(19mA typ - Energy Detect)

ENET_CLK125M_TXCLK

PLACE R3796 CLOSE TO U1400, PIN D24

ENET_RESET_L

18 91

IN

8

Alias to =PP3V3_ENET_PHY for internal switcher.

Alias to GND for external 1.05V supply.

R3796

1 2

5%
1/16W
402
MF-LF

R3724

1 2

NO STUFF

22

0

5%
1/16W
MF-LF

402

1

C3725

0.1UF

20%
10V

2

CERM
402

R3730

2.49K

1

CRITICAL

L3705

FERR-120-OHM-1.5A

0402-LF

2

PP3V3_ENET_PHYAVDD

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

ENET_CLK125M_TXCLK_R

1

1%
1/16W
MF-LF

402

2

=RTL8211_ENSWREG

9

IN

ENET_TXD<0>

18 91

IN

ENET_TXD<1>

18 91

IN

ENET_TXD<2>

18 91

IN

ENET_TXD<3>

18 91

IN

ENET_TX_CTRL

18 91

IN

ENET_MDC

18 91

IN

ENET_MDIO

18 91

BI

RTL8211_PHYRST_L

RTL8211_RSET

TP_RTL8211_CLK125

RTL8211_CLK25M_CKXTAL1

34 91

IN

TP_RTL8211_CKXTAL2

1

C3700

0.1UF

10%
16V

2

X5R
402

1

C3705

0.1UF

10%
16V

2

X5R
402

R3720

10K

1/16W
MF-LF

402

=PP1V05_ENET_PHY
(221mA typ - 1000base-T)
( 7mA typ - Energy Detect)

0402-LF

R3752

4.7K

1/16W
MF-LF

35 91

BI

35 91

BI

35 91

BI

35 91

BI

35 91

BI

35 91

BI

35 91

BI

35 91

BI

R3756

4.7K

1/16W
MF-LF

1

WF: Marvell numbers, update for Realtek

2

=PP3V3_ENET_PHY_VDDREG

If internal switcher is used, must place 1x 22uF &
1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

1

=RTL8211_REGOUT

5%

If internal switcher is used, must place inductor within 5mm

402

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

2

If internal switcher is not used, VDDREG and REGOUT can float.

R3790
R3791

R3792
R3793
R3794

R3795

1

1

R3757

4.7K

5%

5%
1/16W
MF-LF

402

402

2

2

1

C3710

0.1UF

10%
16V

2

X5R
402

1

C3701

0.1UF

10%
16V

2

X5R
402

1

C3706

0.1UF

10%
16V

2

X5R
402

1

1

5%

2

2

NO STUFF

R3725

4.7K

5%
1/16W
MF-LF
402

39

22

23
24
25
26

27

30
31

29

46

32

42
43

1

C3702

0.1UF

10%
16V

2

X5R
402

ENSWREG

TXC

TXD[0]
TXD[1]
TXD[2]
TXD[3]

TXCTL

MDC
MDIO

PHYRSTB*

RSET

CLK125

CKXTAL1
CKXTAL2

6

41

AVDD33

152137

DVDD33

MANAGEMENT

REFERENCE

1

C3714

0.1UF

10%
16V

2

X5R
402

44

45

VDDREG

OMIT

U3700

RTL8211CLGR

TQFP

RGMII/MII

RESET

MEDIA DEPENDENT

CLOCK

LED

GND

7

203347

3

FB12

10

28

40

36

DVDD12

AVDD12

REGOUT

RXC

RXD[0]

RXD[1]/TXDLY

RXD[2]/AN0
RXD[3]/AN1

RXCTL

MDI+[0]
MDI-[0]

MDI+[1]
MDI-[1]

MDI+[2]
MDI-[2]

MDI+[3]
MDI-[3]

LED0/PHYAD0
LED1/PHYAD1

LED2/RXDLY

Reserved for EMI
per RealTek request.

C3715

0.1UF

R3750

48

19

14
16
17
18

13

1
2

4
5

8
9

11
12

34
35
38

10%
16V
X5R
402

4.7K

1/16W
MF-LF

1

2

1

5%

402

2

C3790

10PF

1

C3711

0.1UF

10%
16V

2

X5R
402

MIN_LINE_WIDTH=0.6 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C3716

0.1UF

10%
16V

2

X5R
402

1

R3751

4.7K

5%
1/16W
MF-LF
402

2

ENET_CLK125M_RXCLK_R

91

ENET_RXD_R<0>

91

ENET_RXD_R<1>

91

91

ENET_RXD_R<2>
ENET_RXD_R<3>

91

ENET_RXCTL_R

ENET_MDI_P<0>
ENET_MDI_N<0>

ENET_MDI_P<1>
ENET_MDI_N<1>

ENET_MDI_P<2>
ENET_MDI_N<2>

ENET_MDI_P<3>
ENET_MDI_N<3>

RTL8211_PHYAD0
RTL8211_PHYAD1
RTL8211_RXDLY

1

5%

50V

2

CERM

402

CRITICAL

FERR-120-OHM-1.5A

L3715

PP1V05_ENET_PHYAVDD

1

R3755

4.7K

5%
1/16W
MF-LF

402

2

22

22
22
22
22

22

8

1 2

1 2
1 2
1 2
1 2

1 2

D

9

9

C

1/16W

MF-LF

MF-LF1/16W
MF-LF1/16W
MF-LF1/16W
MF-LF1/16W

MF-LF1/16W

5%

5%
5%
5%
5%

5%

ENET_CLK125M_RXCLK

402

ENET_RXD<0>

402

ENET_RXD<1>

402

ENET_RXD<2>

402

ENET_RXD<3>

402

ENET_RX_CTRL

402

18 91

OUT

18 91

OUT

18 91

OUT

18 91

OUT

18 91

OUT

18 91

OUT

B

A

Configuration Settings:

PHYAD = 01 (PHY Address 00001)
AN[1:0] = 11 (Full auto-negotiation)
RXDLY = 0 (RXCLK transitions with data)
TXDLY = 0 (No TXCLK Delay)

8

7 6

Ethernet PHY (RTL8211CL)

SYNC_MASTER=SUMA_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SYNC_DATE=07/01/2008

051-7546

SHT

OF

33 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

3.3V ENET FET

@ 2.5V Vgs:
Rds(on) = 90mOhm max
I(max) = 1.7A (85C)

=PP3V3_S5_P3V3ENETFET

8 8

D

Q3801

SSM6N15FEAPE

=P3V3ENET_EN

9

IN

R3800

1/16W
MF-LF

SOT563

5

10K

402

1

5%

2

3

D

SG

4

P3V3ENET_EN_L

R3810

100K

1 2

1/16W
MF-LF

402

1

C3811

0.033UF

10%
16V

2

X5R
402

5%

P3V3ENET_SS

MOBILE:
Recommend aliasing PM_SLP_RMGT_L and

=P3V3ENET_EN. Nets separated on
ARB for alternate power options.

CRITICAL

Q3810

NTR4101P

SOT-23-HF

2

G

1

C3810

0.01UF

DS

10%
16V

CERM

402

=PP3V3_ENET_FET

3

12

D

WLAN Enable Generation

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

PM_WLAN_EN_L

C

Q3805

21 31

IN

21 37 42 43

IN

7

21 37 42 44 68 81 83

IN

SSM6N15FEAPE

AP_PWR_EN

SSM6N15FEAPE

SMC_ADAPTER_EN

PM_SLP_S3_L

SOT563

2

Q3805

SOT563

5

Pull-up is with power FET.

6

D

SG

1

AC_OR_S0_L

3

D

SG

4

6

1

OUT

D

S G

31

Q3801

SSM6N15FEAPE

SOT563

2

=PP3V3_S5_P1V05ENETFET

8

Q3841

SSM6N15FEAPE

R3842

69.8K

1/16W
MF-LF

SOT563

1

1%

402

2

P1V05ENET_EN_L

3

D

1.05V ENET FET

=PP1V05_ENET_P1V05ENETFET

8

C3840

0.1UF

20%
10V

CERM

R3840

100K

1 2

5%
1/16W
MF-LF

402

P1V05ENET_SS

SSM6N15FEAPE

R3841

10K

1 2

1%
1/16W
MF-LF

402

402

Q3841

SOT563

2

P1V05ENET_EN_L_RC

C

1

2

1

6

D

SG

1

1.8V Vgs

3

CRITICAL

D

Q3840

G

SI2312BDS

SOT23

S

2

=PP1V05_ENET_FET

1

C3841

0.01UF

10%
16V

2

CERM
402

8

5

SG

=P1V05ENET_EN

9

B

IN

Non-ARB:
Recommend aliasing PM_SLP_RMGT_L and

=P1V05ENET_EN. Nets separated on
ARB for alternate power options.

RTL8211 25MHz Clock

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered.

A

Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

R3895

MCP_CLK25M_BUF0_R

18 91

IN

PLACEMENT_NOTE=Place close to U1400

1 2

1/16W
MF-LF

4

22

RTL8211_CLK25M_CKXTAL1

5%

402

B

Ethernet & AirPort Support

SYNC_MASTER=SUMA_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR

33 91

OUT

AGREES TO THE FOLLOWING
I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

SYNC_DATE=07/01/2008

051-7546

SHT

OF

9634

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

Page Notes

Power aliases required by this page:
(NONE)

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

6

5

4

3

2 1

D

Place one of 0.1uf cap close to each centertap pin of transformer

D

ENETCONN_CTAP

1/16W
MF-LF

402

75

5%

1

C3906

0.1UF

10%
16V

2

X5R
402

1

1

2

2

R3902

75 75

5%
1/16W
MF-LF
402

1

2

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm

R3903

5%
1/16W
MF-LF
402

ENET_BOB_SMITH_CAP

CRITICAL

C3908

1000PF

1 2

10%

2KV
CERM
1206

CRITICAL

J3900

RJ45-M97-2

F-RT-TH

9

10

1
2
3
4
5
6
7
8

11
12

514-0596

C

B

R3900

1/16W
MF-LF

402

1

C3904

0.1UF

10%10%
16V

2

X5R
402

1

R3901

75

5%

2

1

C3900

0.1UF

10%
16V

2

X5R
402

CRITICAL

T3900

ENET_MDI_P<0>

33 91

BI

ENET_MDI_N<0>

33 91

BI

C

ENET_MDI_N<1>

33 91

BI

ENET_MDI_P<1>

33 91

BI

ENET_MDI_N<2>

33 91

BI

ENET_MDI_P<2>

33 91

BI

ENET_MDI_N<3>

33 91

BI

ENET_MDI_P<3>

33 91

BI

Transformers should be
mirrored on opposite

B

sides of the board

1

2

3

4

5

6 7

1

2

3

4

5

6 7

SM

TX

TLA-6T213HF

RX

CRITICAL

T3901

SM

TX

TLA-6T213HF

RX

1

C3902

0.1UF

16V

2

X5R
402

12

ENETCONN_P<0>

95

11

ENETCONN_N<0>

95

10

ENET_CTAP0

9

ENET_CTAP1

8

ENETCONN_N<1>

95

ENETCONN_P<1>

95

12

ENETCONN_N<2>

95

11

ENETCONN_P<2>

95

10

ENET_CTAP2

9

ENET_CTAP3

8

ENETCONN_N<3>

95

ENETCONN_P<3>

95

Ethernet Connector

A

SYNC_MASTER=SUMA_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=07/01/2008

051-7546

SHT

OF

35

96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

C4170
C4171

C4175
C4176

89 17

89 17

=PP3V3_FW_FWPHY

0.1UF

0.1UF

0.1UF

0.1UF

138 mA

PLACEMENT_NOTE=Place C4170 close to U1400
PLACEMENT_NOTE=Place C4171 close to U1400

16V

10%

1 2

X5R 402

16V

10%

1 2

X5R 402

16V

10%

1 2

X5R 402

16V

10%

1 2

X5R 402

PLACEMENT_NOTE=Place C4175 close to U4000
PLACEMENT_NOTE=Place C4176 close to U4000

FW643_LDO

R4165

10K

1/16W
MF-LF

1

R4164

10K

5%
1/16W
MF-LF
402

2

FireWire LLC/PHY (FW643)

SYNC_MASTER=SENSOR

7 mA I/O

1

C4120

1UF

10%

6.3V
2

CERM

402

D

L4110

=PP1V0_FW_FWPHY

8

135 mA

120-OHM-0.3A-EMI

1 2

0402-LF

110 mA Digital Core

1

C4100

1UF

10%

6.3V

2

CERM
402

1

C4101

1UF

10%

6.3V

2

CERM
402

PP1V0_FW_FWPHY_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.0V

1

C4102

1UF

10%

6.3V

2

CERM
402

1

C4103

1UF

10%

6.3V

2

CERM
402

1

C4104

1UF

10%

6.3V

2

CERM
402

25 mA PCIe SerDes 17 mA PCIe SerDes

1

C4110

1UF

10%

6.3V

2

CERM
402

1

C4105

1UF

10%

6.3V

2

CERM
402

1

C4111

1UF

10%

6.3V

2

CERM
402

1

C4106

1UF

10%

6.3V

2

CERM
402

C4121

1UF

6.3V
CERM

C4130

1UF

6.3V
CERM

1

C4122

10%

402

1UF

10%

6.3V

2

CERM

402

114 mA FireWire PHY

1

C4131

2

1UF

6.3V
CERM

C4135

1UF

6.3V
CERM

10%

402

10%
402

10%

402

1

C4123

1UF

10%

6.3V

2

CERM

402

1

C4132

1UF

10%

6.3V

2

CERM

402

1

C4136

1UF

10%

6.3V

2

CERM

402

0 mA VReg PWR

1

C4141

0.1UF

20%
10V

2

CERM

402

1

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

2

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

2

1

2

1

C4124

1UF

10%

6.3V
2

CERM

402

PP3V3_FW_FWPHY_VDDA

PP3V3_FW_FWPHY_VP25

C4140

1UF

10%

6.3V
CERM
402

L4130

120-OHM-0.3A-EMI

1 2

0402-LF

L4135

120-OHM-0.3A-EMI

1 2

0402-LF

C

A1

B1

B12

C13E2E10H2H12K2L1

B13

ATBUSB

NC

A13

ATBUSH

NC

A11

ATBUSN

NC

=FW_PHY_DS0

38

IN

=FW_PHY_DS1

38

IN

=FW_PHY_DS2

38

IN

FW_P0_TPA_N

92 38

BI

FW_P0_TPA_P

92 38

BI

FW_P1_TPA_N

92 38

BI

FW_P1_TPA_P

92 38

BI

FW_P2_TPA_N

38

BI

FW_P2_TPA_P

38

BI

FW_P0_TPB_N

92 38

BI

FW_P0_TPB_P

92 38

BI

FW_P1_TPB_N

92 38

BI

FW_P1_TPB_P

92 38

BI

FW_P2_TPB_N

38

=PPVP_FW_PHY_CPS

38

1

R4160

B

C4150

22PF

1 2

5%

50V

CERM

402

C4151

22PF

1 2

5%

50V

CERM

402

1 3

2 4

NC
NC

FW_CLK24P576M_XO

CRITICAL

Y4150

24.576MHZ

SM-3.2X2.5MM

R4150

412

1 2

1%
1/16W
MF-LF

402

390K

5%
1/16W
MF-LF

402

2

R4161

2.94K

1/16W
MF-LF

402

R4162

470K

1/16W
MF-LF

402

1

1

R4170

191

1%

1%

1/16W
MF-LF
402

2

2

1

1

C4162

0.33UF

5%

10%

6.3V

2

CERM-X5R
402

2

BI

FW_P2_TPB_P

38

BI

FW_P0_TPBIAS

38

BI

FW_P1_TPBIAS

38

BI

FW_P2_TPBIAS

38

BI

FW643_R0
FW643_TPCPS

TP_FW643_NAND_TREE
FW643_REXT
FW_CLK24P576M_XO_R
FW_CLK24P576M_XI

TP_FW643_SE
TP_FW643_SM
TP_FW643_MODE_A
TP_FW643_CE
TP_FW643_FW620_L
TP_FW643_JASI_EN
TP_FW643_AVREG
TP_FW643_VBUF
FW643_PU_RST_L

TP_FW643_OCR10_CTL

F12

DS0

(IPD) NT-19

E12

DS1

(IPD) NT-20

E13

DS2

(IPD) NT-21

B8

TPA0N

A8

TPA0P

B5

TPA1N

A5

TPA1P

B3

TPA2N

A3

TPA2P

B9

TPB0N

A9

TPB0P

B6

TPB1N

A6

TPB1P

B4

TPB2N

A4

TPB2P

B7

TPBIAS0

C3

TPBIAS1

A2

TPBIAS2

B11

R0

B10

TPCPS

K1

NAND_TREE

L8

REXT

F13

XO

G13

XI

NT-9

M13

SE

(IPD)

N13

(IPD)

SM

J2

MODE_A

L13

CE

(IPD)

D12

FW620*

(IPU)

D1

JASI_EN

A10

AVREG

H13

VBUF

K13

FW_RESET*

J12

OCR_CTL_V10

J13

OCR_CTL_V12

NC

B2

VDD10

NT-OUT

NOTE: NT-xx notes show
NAND tree order.

(IPD) NT-18

(IPD) NT-11

(IPU) NT-8

(Reserved)

D4

E4E5E9F4F6

D10

M12N3N11

MISCELLANEOUS

F7

F8

F10

C1

C12F1G12J1L3

1394 PHY

G4G6G7

VDD33

OMIT

CRITICAL

U4100

FW643

VSS

G8

H4

G10

BGA

H6D7H7

L11M2A12D5D6D8L5

VDDH

PCI EXPRESS PHY

TEST CONTROLLER

FIXME!!! - TYPO IN SYMBOL REGCTL

POWER MANAGEMENT

SCIF

L10L6L9

VP

NT-12 (IPD)

NT-13

VP25

NT-10 (IPD)

NT-16 (IPD)
NT-14 (IPD)

NT-15 (IPD)

SERIAL EEPROM
CONTROLLER

CHIP RESET

H8

J4J5J9

H10

K4K5K7D9K8K9L7

J10

K12

VREG_PWR

PCIE_RXD0N
PCIE_RXD0P
PCIE_TXD0N
PCIE_TXD0P

NT-4 (IPU)
NT-3 (IPU)

(IPU)

NT-1 (IPU)

NT-2 (IPU)

VAUX_DETECT

VAUX_DISABLE

(OD)

NT-17

NT-7
NT-6

NT-5

VREG_VSS

K6

K10

REFCLKN
REFCLKP

TRST*

WAKE*

REGCLT

CLKREQN

SCIFCLK
SCIFDAIN
SCIFDOUT

SCIFMC

PERST*

L12

TCK
TDI
TDO
TMS

SCL
SDA

N8
N7
N5
N6

N9
N10

M4
N2
M1
M3

N1

C2
D13
E1
D2
L2

G2
G1
H1
F2

N12
M11

N4

PCIE_FW_R2D_N

89

PCIE_FW_R2D_P

89

PCIE_FW_D2R_C_N

89

PCIE_FW_D2R_C_P

89

PCIE_CLK100M_FW_N
PCIE_CLK100M_FW_P

TP_FW643_TCK
TP_FW643_TDI
TP_FW643_TDO
TP_FW643_TMS

FW643_TRST_L

FW_PME_L
FW643_REGCTL
FW643_VAUX_DETECT
TP_FW643_VAUX_ENABLE
FW_CLKREQ_L

TP_FW643_SCIFCLK
TP_FW643_SCIFDAIN
TP_FW643_SCIFDOUT
TP_FW643_SCIFMC

FW643_SCL
TP_FW643_SDA

FW_RESET_L

1

R4163

10K

5%
1/16W
MF-LF
402

2

IN
IN

19

OUT

17

OUT

26

IN

A

APPLE INC.

38

36

8

PCIE_FW_R2D_C_N

PCIE_FW_R2D_C_P

PCIE_FW_D2R_N

PCIE_FW_D2R_P

=PP3V3_FW_FWPHY

1

1

R4166

10K

5%

5%
1/16W
MF-LF

402

402

2

2

89 17

IN

89 17

IN

89 17

OUT

89 17

OUT

38

36

8

SYNC_DATE=08/14/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

D

C

B

A

REV.

A.0.0

OF

9636

8

7 6

5

4

3

2

1

8 7

Page Notes

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PP3V3_FW_LATEVG_ACTIVE

- =PPVP_FW_SUMNODE (power passthru summation node)
Signal aliases required by this page:

(NONE)
BOM options provided by this page:

- FW_PORT_FAULT_PU

D

C

8

Enables port power when machine
is running or on AC.

IN

7

IN

SMC_ADAPTER_EN
PM_SLP_S3_L

43 42 34 21

83 81 68 44 42 34 21

6

=PPBUS_S5_FWPWRSW

Q4261

SSM6N15FEAPE

SOT563

2

1

R4260

470K

5%
1/16W
MF-LF
402

2

FWPWR_EN_L_DIV

1

R4261

330K

5%
1/16W
MF-LF
402

2

FWPWR_EN_L

6

D

SG

1

Q4261

SSM6N15FEAPE

FW_PORTPWR_EN_FET

C4260

0.01uF

SOT563

5

CERM

20%
16V

402

5

4

3

2 1

FireWire Port Power Switch

CRITICAL

Q4260

NDS9407

SOI-HF

3
2
1

1

2

3

D

SG

4

8

PPBUS_FW_FWPWRSW_F

MIN_LINE_WIDTH=0.5 mm

7

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

6
5

4

OMIT

CRITICAL

F4260

1.5A-24V

1 2

1812L15024HF

PPBUS_FW_FWPWRSW_D

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

CRITICAL

D4260

PWRDI5

2

1

PDS540XF

=PPBUS_S5_FW_FET

3

8

D

C

Q4262

FW_PORTPWR_EN

37

SSM3K15FV

SOD-VESM-HF

1

G S

3

D

2

Late-VG Event Detection

=PP3V3_FW_LATEVG_ACTIVE

8

PP2V4_FW_LATEVG

38

1

B

R4211

1/16W
MF-LF

C4211

100pF

CERM

10K

402

50V
402

1

R4212

10K

5%

1%
1/16W
MF-LF
402

2

2

P2V4_FWLATEVG_RC

FWLATEGV_3V_REF

1

R4213

1

80.6K

1%

5%

1/16W
MF-LF

2

402

2

4

3

2

V+

V-

5

R4210

200K

1 2

1%
1/16W
MF-LF

402

U4210

LMC7211

SM-HF

1

1

C4210

0.1UF

20%
10V

2

CERM
402

D4219

LATEVG_EVENT_L

SOD-123

MBR0540XXH

FWLATEVG_3V_REF Hysteresis:

2.95V when port power is on

2.81V on late Vg event and port power is off

1

R4219

2.0M

5%
1/16W
MF-LF
402

2

12

FW_PORTPWR_EN

1

C4219

0.33UF

10%
10V

2

CERM-X5R
603

37

B

FireWire Port Power

A

PART NUMBER

740S0080

QTY

1

DESCRIPTION

LITTLEFUSE, 1.5A RESETTABLE 24V

REFERENCE DES

F4260

CRITICAL

CRITICAL

BOM OPTION

SYNC_MASTER=SENSOR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=08/14/2008

051-7546

SHT

OF

37 96

1

A

REV.

A.0.0

8 7

Page Notes

Power aliases required by this page:

- =PPVP_FW_PORT1

- =PP3V3_FW_LATEVG

- =GND_CHASSIS_FW_PORT1

- =GND_CHASSIS_FW_EMI_R
Signal aliases required by this page:

(NONE)

D

NOTE: This page is expected to contain
the necessary aliases to map the
FireWire TPA/TPB pairs to their
appropriate connectors and/or to
properly terminate unused signals.

BOM options provided by this page:
(NONE)

NOTE: FireWire TPA/TPB pairs are NOT
constrained on this page. It is
assumed that FireWire PHY page will
provide the appropriate constraints
to apply to entire TPA/TPB XNets.

1394b implementation based on Apple
FireWire Design Guide (FWDG 0.6, 5/14/03)

Termination

Place close to FireWire PHY

FW_P1_TPBIAS

36

C

SIGNAL_MODEL=EMPTY

1

R4360

56.2

1%
1/16W
MF-LF
402

FW_P1_TPA_P

92

36

FW_P1_TPA_N

92

36

FW_P1_TPB_P

92

36

FW_P1_TPB_N

92

36

B

2

SIGNAL_MODEL=EMPTY

1

R4362

56.2

1%
1/16W
MF-LF
402

2

1

2

FireWire PHY Config Straps

TI PHYs require 1uF even though
FW spec calls out 0.33uF

1

C4360

0.33UF

10%

6.3V

2

CERM-X5R
402

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

FW_PORT1_TPB_C

C4364

220pF

5%
25V
CERM
402

R4361

56.2

1/16W
MF-LF

402

R4363

56.2

1/16W
MF-LF

402

R4364

4.99K

1/16W
MF-LF

402

1

1%

2

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

1

1%

2

1

1%

2

6

Configures PHY for:

- 1-port Portable Power Class (0)

- Port "1" Bilingual (1394B)

=PPVP_FW_PHY_CPS_FET

8

1

R4311

470K

5%
1/16W
MF-LF

402

2

CPS_EN_L_DIV

1

R4312

330K

5%
1/16W
MF-LF

402

2

38

38

38

38

=PP3V3_FW_FWPHY

38

36

8

CPS_EN_L

5

=PP3V3_FW_FWPHY

38

36

8

SOT-363

BSS8402DW

(SYM-VER2)

Q4300

SGD

5

6

D

S

1

3

Q4300

BSS8402DW

SOT-363

(SYM-VER1)

PPVP_FW_CPS

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=12.6V

MAKE_BASE=TRUE

"Snapback" & "Late VG" Protection

PP2V4_FW_LATEVG

38

37

38

38

38

38

4

G

2

1

R4382

10K

1/16W
MF-LF

402

R4380

1%

2

R4381

36

36

36

92

92

36

36

36

92

36

92

36

36

36

=PPVP_FW_PHY_CPS

C4310

0.01uF

10%
50V
X7R
402

FW_PORT1_TPB_N

FW_PORT1_TPB_P

FW_PORT1_TPA_N

FW_PORT1_TPA_P

C4312

0.01uF

10%
50V
X7R
402

10K

1%
1/16W
MF-LF

402

1

10K

1%
1/16W
MF-LF

402

2

FW_P0_TPBIAS
FW_P2_TPBIAS
FW_P0_TPA_N
FW_P0_TPA_P
FW_P2_TPA_N
FW_P2_TPA_P

FW_P0_TPB_N
FW_P0_TPB_P
FW_P2_TPB_N
FW_P2_TPB_P

1

2

1

2

4

1

2

FWPHY_DS0

MAKE_BASE=TRUE

FWPHY_DS2

MAKE_BASE=TRUE

FWPHY_DS1

MAKE_BASE=TRUE

DP4310

BAV99DW-X-G

SOT-363

2

1

DP4311

BAV99DW-X-G

SOT-363

2

1

=FW_PHY_DS0

=FW_PHY_DS2

=FW_PHY_DS1

NC_FW0_TPBIAS
NC_FW2_TPBIAS
NC_FW0_TPAN
NC_FW0_TPAP
NC_FW2_TPAN
NC_FW2_TPAP

NC_FW0_TPBN
NC_FW0_TPBP
NC_FW2_TPBN
NC_FW2_TPBP

36

1

C4311

0.01uF

10%
50V

2

X7R
402

6

6

1

C4313

0.01uF

10%
50V

2

X7R
402

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

DP4310

BAV99DW-X-G

SOT-363

5

4

DP4311

BAV99DW-X-G

SOT-363

5

4

Cable Power

=PPVP_FW_PORT1

8

3

3

3

36

36

36

MAKE_BASE=TRUE

MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE
MAKE_BASE=TRUE

C4319

1

R4319

1M

5%
1/16W
MF-LF
402

2

0.1uF

603-1

CRITICAL

L4310

FERR-250-OHM

1 2

SM

1

C4314

0.01UF

10%
50V

2

X7R
402

1

10%
50V

2

X7R

AREF needs to be isolated from all
local grounds per 1394b spec

When a bilingual device is connected to a
beta-only device, there is no DC path
between them (to avoid ground offset issue)

BREF should be hard-connected to logic
ground for speed signaling and connection

Note: Trace PPVP_FW_PORT1 must handle up to 5A
PPVP_FW_PORT1_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=33V

2 1

PORT 1

BILINGUAL

CRITICAL

J4310

1394B-M97

TPB-

1

(FW_PORT1_BREF)

(GND_FW_PORT1_VG)

FW_PORT1_AREF

9
2
8
7

NC

6

TPA-

3
5

TPA+

4

10
11

12
13
14
15

F-RT-TH1

TPB(R)

TPB­TPB<R>

VPTPB+

TPB+
VP
NC

NC

VG

VG

TPA­TPA<R>

TPA(R)

TPA+

CABLE OUTER

SHLD

CHASSIS

GND

514S0605

D

C

OUTPUT

B

INPUT

Late-VG Protection Power

=PP3V3_FW_LATEVG

A

PP2V4_FWLATEVG needs to be biased
to at least 2.1V for FW signal integrity
and should be biased to 2.4V for margin
R4390 should be 390 Ohms max for a 3.3V rail

8

8

7 6

R4390

332

1 2

1%
1/16W
MF-LF

402

PP2V4_FW_LATEVG

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=2.4V

CRITICAL

3

D4390

MMBZ5227BLT1H

SOT23

1

38

37

ESD and late-VG rail
for snap-back diodes
(Common to all ports)

5

4

3

SYNC_MASTER=SENSOR

APPLE INC.

2

FireWire Ports

SYNC_DATE=08/14/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

38 96

1

A

REV.

A.0.0

OF

8 7

6

5

4

3

2 1

ODD Power Control

CRITICAL

Q4590

FDC606P_G

=PP5V_S0_ODD

8

D

NOTE: 3.3V must be S0 if 5V is S3 or S5 to
ensure the drive is unpowered in S3/S5.

21

IN

=PP3V3_S0_ODD

8

39

SSM6N15FEAPE

ODD_PWR_EN_L

R4597

Q4596

SOT563

100K

5

1/16W
MF-LF

402

5%

3

D

SG

4

ODD_PWR_EN

SSM6N15FEAPE

R4596

Q4596

SOT563

2

100K

1/16W
MF-LF

5%

402

D

SG

ODD_PWR_EN_LS5V_L

6

1

R4595

100K

1 2

5%
1/16W
MF-LF

402

1

C4595

0.068UF

10%
10V

2

CERM
402

ODD_PWR_SS

4

SOT-6

SGD

3

C4596

0.01UF

1 2

CERM

10%
16V

402

PP5V_SW_ODD

7

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.4mm
VOLTAGE=5V

1 2 5 6

D

C

C

SATA ODD Port

FL4520

90-OHM-100MA

DLP11S

SYM_VER-1

CRITICAL

=PP3V3_S0_ODD

39

8

SMC_ODD_DETECT

7

42

OUT

Indicates disc presence

R4590

33K

1/16W
MF-LF

402

3 4

J4500

CRITICAL

1

5%

2

55560-0168

M-ST-SM-LF
2

10

516S0617

1
34
56
78
9
1112
1314
1516

89

SATA_ODD_R2D_P

7

SATA_ODD_R2D_N

89

7

SATA_ODD_D2R_C_N

89

7

SATA_ODD_D2R_C_P

89

7

PLACEMENT_NOTE=Place FL4520 close to J4500

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500
PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

C4526

1 2

0.01UF

C4525

1 2

0.01UF

10% 16V

95

12

95

95

95

16V10%

SATA_ODD_R2D_UF_P

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_N

402

CERM

SATA_ODD_D2R_UF_P

CERM

402

B

CRITICAL

J4501

20374020E31

F-ST-SM

21

1
2
3
4
5

NC

6

NC

7
8

NC

9
10
11
12
13

NC

14
15

A

NC

16

NC

17
18
19
20

22

PP5V_S0_HDD_FLT

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

SATA_HDD_R2D_P

89

SATA_HDD_R2D_N

89

SATA_HDD_D2R_C_N

89

SATA_HDD_D2R_C_P

89

518S0654

1

C4501

0.1UF

20%
10V

2

CERM
402

FERR-70-OHM-4A

1

C4502

0.1UF

20%
10V

2

DLP11S

SYM_VER-1

1 2

1 2

CERM
402

12

16V10%

CERM

16V10%

CERM

CRITICAL

L4500

1 2

0603

FL4501

90-OHM-100MA

CRITICAL

3 4

PLACEMENT_NOTE=Place FL4501 close to J4501

C4515

0.01UF

C4516

0.01UF

PLACEMENT_NOTE=Place C4515 next to C4516
PLACEMENT_NOTE=Place C4516 close to J4501

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501
PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

=PP5V_S0_HDD

SATA_HDD_R2D_UF_P

95

SATA_HDD_R2D_UF_N

95

SATA_HDD_D2R_UF_N

95

402

SATA_HDD_D2R_UF_P

95

402

8

PLACEMENT_NOTE=Place C4510 close to MCP79
PLACEMENT_NOTE=Place C4511 next to C4510

FL4502

90-OHM-100MA

1 2

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

DLP11S

SYM_VER-1

C4510

0.01UF

C4511

0.01UF

CRITICAL

34

SATA HDD Port

1 2

1 2

SATA_HDD_R2D_C_P

16V10%

CERM

SATA_HDD_R2D_C_N

16V10%

CERM

SATA_HDD_D2R_N

SATA_HDD_D2R_P

402

402

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79
PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

0.01UF

0.01UF

20 89

IN

20 89

IN

20 89

OUT

20 89

OUT

C4521

1 2

16V10%

C4520

1 2

10% 16V

FL4525

90-OHM-100MA

DLP11S

SYM_VER-1

1 2

PLACEMENT_NOTE=Place FL4525 close to J4500

CERM

CERM

SATA_ODD_R2D_C_P

402

SATA_ODD_R2D_C_N

402

CRITICAL

34

SATA_ODD_D2R_N

SATA_ODD_D2R_P

20 89

IN

20 89

IN

20 89

OUT

20 89

OUT

B

SATA Connectors

SYNC_MASTER=CHANG_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=07/01/2008

051-7546

SHT

OF

39 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

Port Power Switch

CRITICAL

Q4690

TPS2064DGN

=PP5V_S3_RTUSB

C4692

0.47UF

10%
10V
X5R
402

8

1

2

1

2

R4690

5.1K

5%
1/16W
MF-LF
402

USB_PWR_EN

20

OUT

20

OUT

USB_EXTA_OC_L

USB_EXTB_OC_L

C4690

10UF

6.3V

20%
X5R

603

1

1

C4691

0.1UF

20%
10V

2

2

CERM
402

C

68 43 42

PM_SLP_S4_L

21

2

IN

8

OC1*

3

EN1

5

OC2*

4

EN2

GND

1

MSOP

TPAD

9

OUT1

OUT2

7

6

C4695

10UF

6.3V

20%
X5R

603

PP5V_S3_RTUSB_A_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

PP5V_S3_RTUSB_B_ILIM

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

CRITICAL

1

1

C4696

100UF

20%

6.3V

2

2

POLY-TANT
CASE-B2-SM

C4617

10UF

6.3V
X5R
603

20%

1

2

CRITICAL

1

C4616

100UF

20%

6.3V

2

POLY-TANT
CASE-B2-SM

C4605

USB2_EXTA_MUXED_N

95

USB2_EXTA_MUXED_P

95

0.01uF

CERM

20%
16V

402

1

2

Left USB Port A

CRITICAL

L4605

FERR-220-OHM-2.5A

1 2

0603

CRITICAL

L4600

90-OHM-100MA

DLP11S

SYM_VER-1

1 2

PP5V_S3_RTUSB_A_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

34

USB2_LT1_N

95

USB2_LT1_P

95

6

VBUS

1

GND

CRITICAL

J4600

USB

F-RT-TH-M97-3

5
6

1
2
3
4

5 42 3

IOIONC

NC

7
8

D

C

514-0606

D4600

RCLAMP0502N

SLP1210N6

34

USB_LT2_N

95

CRITICAL

USB_LT2_P

6

VBUS

1

GND

RCLAMP0502N

Place L4600 and L4605 at connector pin

CRITICAL

J4610

USB

F-RT-TH-M97-3

5
6

1
2
3
4

7

5 42 3

IOIONC

NC

8

D4610

SLP1210N6

CRITICAL

APPLE INC.

External USB Connectors

SYNC_MASTER=AMASON_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SYNC_DATE=07/02/2008

051-7546

SHT

OF

B

A

REV.

A.0.0

9640

CRITICAL

L4615

FERR-220-OHM-2.5A

1 2

C4615

0.01uF

20%
16V
CERM
402

0603

B

1

2

We can add protection to 5V if we want, but leaving NC for now

PP5V_S3_RTUSB_B_F

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.375 mm
VOLTAGE=5V

USB/SMC Debug Mux

=PP3V42_G3H_SMCUSBMUX

8

SMC_DEBUG_YES

C4650

0.1UF

20%
10V

CERM

42 43 44

42 43 44

20 90

20 90

IN

OUT

BI
BI

SMC_RX_L
SMC_TX_L

USB_EXTA_P
USB_EXTA_N

402

A

SIGNAL_MODEL=USB_MUX

1

2

5
4

7
6

8

SMC_DEBUG_NO

R4651

0

1 2

5%
1/16W
MF-LF

402

9

VCC

M+
M-

U4650

PI3USB102ZLE

TQFN

D+

CRITICAL

D-

GND

3

SMC_DEBUG_NO

R4652

1 2

5%
1/16W
MF-LF

402

1

R4650

10K

5%
1/16W
MF-LF
402

1

Y+

2

Y-

10

SELOE*

2

USB_DEBUGPRT_EN_L
SEL=0 Choose SMC
SEL=1 Choose USB

42

IN

20 90

BI

20 90

BI

USB_EXTB_N

USB_EXTB_P

Left USB Port B

0

SMC_DEBUG_YES

CRITICAL

L4610

90-OHM-100MA

DLP11S

SYM_VER-1

95

1 2

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

20 90

BI

20 90

BI

C

=PP5V_S3_IR

41

8

DIFFERENTIAL_PAIR=USB2_IR

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_P

USB_IR_N

1

C4803

2

1UF

10%
10V
X5R
402-1

1

C4801

0.1UF

10%
16V

2

X7R-CERM
402

IR_VREF_FILTER

U4800

CY7C63803-LQXC

12

P1.0/D+

13

P1.1/D-

15

P1.2/VREG

16

P1.3/SSEL

17

P1.4/SCLK

18

P1.5/SMOSI

19

P1.6/SMISO

8
9

10

P/N 338S0633

20

NC

21
22
23
24

THRML

CRITICAL

25

VCC

QFN

OMIT

14

INT0/P0.2
INT1/P0.3
INT2/P0.4
TIO0/P0.5
TIO1/P0.6

VSSPAD

7

P0.0

6

P0.1

5
4
3
2

IR_RX_OUT_RC

1

1

2

11

C4804

0.001UF

10%
50V
CERM
402

R4800

100

1 2

5%
1/16W
MF-LF

402

IR_RX_OUT

41

IN

D

C

B

PLACE R4805 NEAR J4800
PLACE R4806 NEAR J4800

1

C4807

2

402

R4806

1 2

1/16W

0.001UF

10%
50V
CERM
402

MF-LF

10

5%

PLACE R4807 NEAR J4800
PLACE R4808 NEAR J4800

402

R4807

100

1 2

1/16W

402

5%

MF-LF

1

C4808

2

0.001UF

10%
50V
CERM
402

PLACE C4805 NEAR J4800
PLACE C4806 NEAR J4800
PLACE C4807 NEAR J4800
PLACE C4808 NEAR J4800

=PP3V42_G3H_LIDSWITCH

R4808

4.7

1 2

1/16W

402

5%

MF-LF

=PP5V_S3_IR

SMC_LID

SYS_LED_ANODE

IR_RX_OUT

8

41

8

50

43

42

43

41

J4800

FF18-6A-R11AD-B-3H

F-RT-SM

CRITICAL

1
2
3
4
5
6

518S0692

PP3V42_G3H_LIDSWITCH_R
PP5V_S3_IR_R

SMC_LID_R
SYS_LED_ANODE_R

1

C4805

0.1UF

10%
16V

2

X7R-CERM
402

1

C4806

0.1UF

10%
16V

2

X7R-CERM
402

1 2

1/16W

R4805

10

5%

MF-LF

B

Front Flex Support

A

SYNC_MASTER=CHANG_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=07/01/2008

051-7546

SHT

OF

41 96

1

A

REV.

A.0.0

8 7

NOTE: Unused pins have "SMC_Pxx" names. Unused
pins designed as outputs can be left floating,
those designated as inputs require pull-ups.

D

SMC_EXCARD_PWR_EN

32

OUT

SMC_RSTGATE_L

43

OUT

ALL_SYS_PWRGD

26 68

IN

RSMRST_PWRGD

68

IN

PM_RSMRST_L

21

OUT

IMVP_VR_ON

62

OUT

PM_PWRBTN_L

21 23

OUT

ESTARLDO_EN

43

OUT

SMC_P24

43

SMC_P26

43

LPC_AD<0>

19 44 83 90

BI

LPC_AD<1>

19 44 83 90

BI

LPC_AD<2>

19 44 83 90

BI

LPC_AD<3>

19 44 83 90

C

BI

LPC_FRAME_L

19 44 83 90

IN

SMC_LRESET_L

26

IN

LPC_CLK33M_SMC

26 90

IN

LPC_SERIRQ

19 44

BI

SMC_P41

43

SMB_MGMT_DATA

45

BI

SMS_ONOFF_L

52

OUT

SMC_GFX_THROTTLE_L

76

OUT

SMC_SYS_KBDLED

51

OUT

SMC_TX_L

40 42 43 44

OUT

SMC_RX_L

40 42 43 44

IN

SMB_0_S0_CLK

45

BI

(OC)

(OC)

6

B12

P10

A13

P11

A12

P12

B13

P13

D11

NC

NC
NC
NC

NC

NC

NC

NC
NC

P14

C13

P15

C12

P16 P66

D10

P17

D13

P20

E11

P21

D12

P22

F11

P23

E13

P24

E12

P25

F13

P26

E10

P27

A9

P30

D9

P31

C8

P32

B7

P33

A8

P34

D8

P35

D7

P36

D6

P37

D4

P40

A5

P41

B4

P42

A1

P43

C2

P44

B2

P45

C1

P46

C3

P47

G2

P50

F3

P51

E4

P52

U4900

HS82117

LGA-HF

(1 OF 3)

OMIT

P60
P61
P62
P63
P64
P65

P67

P70
P71
P72
P73
P74
P75
P76
P77

P80
P81
P82
P83
P84
P85
P86

P90
P91
P92
P93
P94
P95
P96
P97

L13
K12
K11
J12
K13
J10
J11
H12

N10
M11
L10
N11
N12
M13
N13
L12

A7
B6
C7
D5
A6
B5
C6

J4
G3
H2
G1
H4
G4
F4
F1

SMC_PM_G2_EN

NC
NC
NC

SMC_ADAPTER_EN

NC

SMC_PROCHOT_3_3_L
SMC_BIL_BUTTON_L

SMC_CPU_ISENSE
SMC_CPU_VSENSE
SMC_GPU_ISENSE
SMC_GPU_VSENSE
SMC_DCIN_ISENSE
SMC_PBUS_VSENSE
SMC_BATT_ISENSE
SMC_NB_MISC_ISENSE

SMC_WAKE_SCI_L

NC

PM_CLKRUN_L
LPC_PWRDWN_L
SMC_TX_L
SMC_RX_L
SMB_MGMT_CLK

(OC)

SMC_ONOFF_L
SMC_BC_ACOK
SMC_BS_ALRT_L
PM_SLP_S3_L
PM_SLP_S4_L
PM_SLP_S5_L
PM_CLK32K_SUSCLK
SMB_0_S0_DATA

(OC)

5

43

7

52

43

8

68

OUT

21 34 37 43

OUT

43

IN

43

IN

46

IN

46

IN

47

IN

46

IN

46

IN

46

IN

46

IN

43

IN

21 23

OUT

19 44

OUT

19 44

IN

40 42 43 44

OUT

40 42 43 44

IN

45

BI

43 50

IN

43 60

IN

43 60

IN

7

21 34 37 44 68 81 83

IN

21 40 43 68

IN

43

IN

26 90

IN

45

BI

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15
PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

NOTE: P94 and P95 are shorted, P95 could be spare.

4

PP3V3_S5_AVREF_SMC
=PP3V3_S5_SMC

1

C4902

22UF

20%

6.3V

2

CERM

805

1

C4903

0.1UF

20%
10V

2

CERM
402

R4999

4.7

1 2

5%
1/16W
MF-LF

402

1

C4904

0.1UF

20%
10V

2

CERM
402

PP3V3_S5_SMC_AVCC

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

43 44

IN

43

43

3

1

C4905

0.1UF

20%
10V

2

CERM
402

C4920

0.1UF

SMC_RESET_L
SMC_XTAL

SMC_EXTAL

20%
10V

CERM

402

1

C4906

0.1UF

20%
10V

2

CERM
402

M12

AVCC

RES*

XTAL
EXTAL

D2

B1M1H10

U4900

HS82117

VSS

L3

F10

LGA-HF

(3 OF 3)

B11

1

2

D3

A3
A2

OMIT

C5

L11

E1

VCLVCC

AVREF

ETRST

XW4900

SM

2 1

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

SMC_VCL

1

C4907

0.47UF

10%

6.3V
2

CERM-X5R

AVSS

MD1
MD2

NMI

NC

12

E5

NC

D1
H1

E3

H3

L9

GND_SMC_AVSS

402

SMC_KBC_MDE

1

R4902

10K

5%
1/16W
MF-LF
402

2

R4909

10K

1/16W
MF-LF

1

R4998

10K

5%
1/16W
MF-LF
402

2

46

43

402

5%

47

1

2

1

R4901

10K

5%
1/16W
MF-LF
402

2

SMC_MD1

SMC_NMI

SMC_TRST_L

NO STUFF

1

R4903

0

5%
1/16W
MF-LF
402

2

D

44

IN

44

IN

44

IN

C

(DEBUG_SW_1)
(DEBUG_SW_2)

B

A

SMC_PA0

43

SMC_PA1

43

PM_SYSRST_L

26

OUT

USB_DEBUGPRT_EN_L

40

OUT

MEM_EVENT_L

21 28 29

BI

43

SYS_ONEWIRE

43 60

BI

PM_BATLOW_L

21 23

OUT

SMC_RUNTIME_SCI_L

21 23

OUT

SMC_ODD_DETECT

7

39

IN

43

SMC_EXCARD_CP

32 43

IN

SMC_EXCARD_OC_L

43

IN

SMC_GFX_OVERTEMP_L

76

IN

SMC_FAN_0_CTL

49

OUT

SMC_FAN_1_CTL

49

OUT

SMC_FAN_2_CTL

43

OUT

SMC_FAN_3_CTL

43

OUT

SMC_FAN_0_TACH

49

IN

SMC_FAN_1_TACH

49

IN

SMC_FAN_2_TACH

43

IN

SMC_FAN_3_TACH

43

IN

SMS_X_AXIS

52

IN

SMS_Y_AXIS

52

IN

SMS_Z_AXIS

52

IN

SMC_ANALOG_ID

43

IN

SMC_NB_CORE_ISENSE

43

IN

SMC_NB_DDR_ISENSE

43

IN

ALS_LEFT

43

IN

ALS_RIGHT

43

IN

SMC_PA5

SMC_PB3

(See below)

(OC)
(OC)
(OC)
(OC)
(OC)
(OC)

NC

NC

SMC_PB3:
SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

A10
C10
B10
C11
A11

G11
G13
F12
H13
G10
G12
H11
J13

M10

K10

N3

PA0

N1

PA1

M3

PA2

M2

PA3

N2

PA4

L1

PA5

K3

PA6

L2

PA7

B8

PB0

C9

PB1

B9

PB2
PB3
PB4
PB5
PB6
PB7

PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7

PD0

N9

PD1
PD2

L8

PD3

M9

PD4

N8

PD5

K9

PD6

L7

PD7

U4900

HS82117

LGA-HF

(2 OF 3)

OMIT

PE0
PE1
PE2
PE3
PE4
PF0

PF1
PF2
PF3
PF4
PF5
PF6
PF7

PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7

PH0
PH1
PH2
PH3
PH4
PH5

K1
J3
K2
J1
K4
K5

N5
M6
L5
M5
N4
L4
M4

M8
N7
K8
K7
K6
N6
M7
L6

E2
F2
J2
A4
B3
C4

SMC_CASE_OPEN
SMC_TCK
SMC_TDI
SMC_TDO
SMC_TMS

NC

SMC_SYS_LED
SMC_LID

NC
NC

SMC_MCP_SAFE_MODE

NC
NC

NC

=SMC_SMS_INT
SMB_BSA_DATA

(OC)

SMB_BSA_CLK

(OC)

SMB_A_S3_DATA

(OC)

SMB_A_S3_CLK

(OC)

SMB_B_S0_DATA

(OC)

SMB_B_S0_CLK

(OC)

SMC_PROCHOT
SMC_THRMTRIP
SMC_PH2
ALS_GAIN

NC
NC

43

IN

43 44

IN

43 44

IN

43 44

OUT

43 44

IN

43

OUT

41 43 50

IN

9

OUT

43

IN

45

BI

45

BI

45

BI

45

BI

45

BI

45

BI

43

OUT

43

OUT

43

43

OUT

NOTE: SMS Interrupt can be active high or low, rename net accordingly.
If SMS interrupt is not used, pull up to SMC rail.

B

SMC

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

9642

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

SMC Reset "Button" / Brownout Detect

=PP3V3_S5_SMC

52

43

42

8

1

C5000

0.1uF

20%
10V

2

CERM

402

D

SILK_PART=SMC_RST

SMC_MANUAL_RST_L

OMIT

1

R5001

0

5%
1/10W
MF-LF
603

2

50

C5001

0.01UF

SMC_TPAD_RST_L

50

SMC_ONOFF_L

43

42

CERM

10%
16V

402

52

1

2

43

42

NC

=PP3V3_S5_SMC

8

NCP303LSN

5

CD

4

NC

U5000

SOT23-5-HF

GND

3

CRITICAL

1

2

1

OUT

2

IN

U5001

5

SN74LVC1G02

SOT553-5

02

3

1

R5000

1K

5%
1/16W
MF-LF
402

2

SMC_RESET_L

SSM6N15FEAPE

4

SMC_TPAD_RST

Q5032

SOT563

C

SMC AVREF Supply

CRITICAL

VR5020

REF3333

SOT23-3

1 2

IN

GND

3

1

C5020

0.47UF

10%

6.3V

2

CERM-X5R
402

COMMENTS:

OUT

C5025

10uF

6.3V

20%
X5R

603

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C5026

0.01UF

10%
16V

2

CERM
402

1

2

GND_SMC_AVSS

TABLE_ALT_HEAD

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

TABLE_ALT_ITEM

PART NUMBER

=PPVIN_S5_SMCVREF

8

ALTERNATE FOR
PART NUMBER

353S1278353S1381 Intersil ISL60002-33

BOM OPTION

REF DES

ALL

B

6

42

42

42

42

42 44

OUT

3

D

5

SG

4

42

7

SMC_XTAL

42

47

46

42

SMC_EXTAL

42

SMC Crystal Circuit

42

60

43

42 46

42 46

42 47

42

42

42

42

42

42

42

42

SMC_EXCARD_OC_L

42 20 32

OUT

R5010

0

1 2

SMC_XTAL_R

5%
1/16W
MF-LF

402

CRITICAL

Y5010

20.00MHZ

5X3.2-SM

5

SMC_FAN_2_CTL

SMC_FAN_2_TACH

SMC_FAN_3_CTL

SMC_FAN_3_TACH

ESTARLDO_EN

SMC_BC_ACOK

MAKE_BASE=TRUE

ALS_LEFT

ALS_RIGHT

SMC_NB_CORE_ISENSE

SMC_NB_DDR_ISENSE

SMC_NB_MISC_ISENSE
SMC_ANALOG_ID

SMC_P24
SMC_P26
SMC_P41

ALS_GAIN

SMC_PB3
SMC_RSTGATE_L

SMS_INT_L

52

MAKE_BASE=TRUE

1

2

C5010

15pF

1 2

5%

50V

CERM

402

C5011

15pF

1 2

5%

50V

CERM

402

NC_SMC_FAN_2_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

NC_ESTARLDO_EN

MAKE_BASE=TRUE

=CHGR_ACOK

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

SMC_MCP_DDR_ISENSE

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

MAKE_BASE=TRUE

SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

TP_SMC_P41

MAKE_BASE=TRUE

NC_ALS_GAIN

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

MAKE_BASE=TRUE

R5095

0

1 2

5%
1/16W
MF-LF

402

Debug Power "Button"

SILK_PART=PWR_BTN

EXCARD_OC_L

4

61 42

47

47

47

46 42

21

IN

=SMC_SMS_INT

SMC_ONOFF_L

OMIT

1

R5015

0

5%

Place R5015,R5001 on bottom side

1/10W
MF-LF
603

2

42

42 43 50

OUT

TO CPU

10 14 62 87

10 14 87

CPU_PROCHOT_L

BI

PM_THRMTRIP_L

OUT

3

6

1

3

4

D

S G

D

S G

SMC FSB to 3.3V Level Shifting

=PP1V05_S0_SMC_LS

8

R5062

3.3K

1 2

CPU_PROCHOT_L_R

5%
1/16W
MF-LF

402

Q5059

SSM6N15FEAPE

SOT563

2

SMC_PROCHOT

Q5059

SSM6N15FEAPE

SOT563

5

SMC_THRMTRIP

42

42

50

43

42

50

42

41

42

44

42

40

44

42

40

60

42

60

42

44

42

44

42

44

42

44

42

43

42

43

42

60

42

IN

42

IN

SMC_PA0
SMC_PA1

SMC_ONOFF_L
SMC_LID
SMC_PH2
SMC_TX_L
SMC_RX_L

SYS_ONEWIRE
SMC_BS_ALRT_L
SMC_TMS
SMC_TDO
SMC_TDI
SMC_TCK
SMC_BIL_BUTTON_L
SMC_BC_ACOK

2 1

=PP3V3_S0_SMC

43

8

1

R5061

3.3K

5%
1/16W
MF-LF
402

2

2

CPU_PROCHOT_BUF

6

Q5060

BC847BV-X-F
SOT563-HF

1

R5091
R5092

R5070
R5071
R5072
R5073
R5074

R5075
R5076
R5077
R5078
R5079
R5080
R5081
R5087

5

100K
100K

10K

100K

10K
10K

100K

2.0K
100K

10K
10K
10K
10K
10K

470K

1

R5060

470

5%
1/16W
MF-LF
402

2

SMC_PROCHOT_3_3_L

3

Q5060

BC847BV-X-F
SOT563-HF

4

43

42

52

8

1 2

1 2

1 2

1 2

1 2

1 2

1 2

ONEWIRE_PU

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

5%

5%

5%
5%

5%

5%
5%

5%

5%

5%

5%
5%

TO SMC

=PP3V3_S5_SMC

1/16W5%MF-LF

MF-LF

1/16W

MF-LF

1/16W
1/16W5%MF-LF

1/16W MF-LF

MF-LF

1/16W

MF-LF1/16W

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

1/16W5%MF-LF
1/16W MF-LF

MF-LF1/16W

1/16W MF-LF
1/16W

MF-LF

42

OUT

D

C

402
402

402
402

402
402

402

402
402

402

402
402

402

402
402

B

System (Sleep) LED Circuit

PP3V42_G3H

8

=PP5V_S3_SYSLED

8

1

1

R5031

523

1/16W
MF-LF

R5032

1.47K

1/16W
MF-LF

A

SMC_SYS_LED

42

IN

R5030

20

1%

1%

1/16W
MF-LF
402

402

2

2

SYS_LED_ILIM

SYS_LED_L_VDIV

1

1%

402

2

SYS_LED_L

Q5032

SSM6N15FEAPE

SOT563

SMC_BIL_BUTTON_L

43

2

SOD

2SA2154MFV-YAE

1

Q5030

3

SYS_LED_ANODE

6

D

2

SG

1

41

OUT

42

7

74LVC1G17DRL

U5050

SOT-553

4

3 1

NC

1

1

C5050

0.1UF

10%
16V

2

X5R
402

5

2

R5051

10K

5%
1/16W
MF-LF
402

2

SMC_BIL_BUTTON_DB_L

60

NC

1

C5051

0.01UF

10%
25V

2

X7R
402

42

68

37

34

42

40

42

42

SMC_ADAPTER_EN

21

SMC_CASE_OPEN

42

SMC_EXCARD_CP

32

PM_SLP_S5_L

42

PM_SLP_S4_L

21

SMC_PA5

R5085
R5086

R5088

R5090

R5089

SYNC_MASTER=AMASON_M98_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

10K

10K

10K

10K

100K

1 2

1 2

1 2

1 2

1 2

5%

5%

5%

5%

=PP3V3_S0_SMC

43

8

5%

1/16W

1/16W MF-LF

SMC Support

SYNC_DATE=06/18/2008

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

MF-LF1/16W

MF-LF1/16W

MF-LF

MF-LF1/16W

OF

402

402

402

402

402

A

REV.

A.0.0

9643

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

LPC+SPI Connector

CRITICAL

LPCPLUS

J5100

55909-0374

M-ST-SM

31

=PP3V3_S5_LPCPLUS

44

8

=PP5V_S0_LPCPLUS

44

44

19 42 83 90

19 42

42 43

42

42

40 42 43

OUT
OUT

OUT
OUT

SPI_ALT_CS_L

SPI_MISO_MUX

R5126

402

MCP_CS1_NO

8

19 42 83 90

BI

19 42 83 90

BI

IN

OUT

IN
OUT
OUT

IN
OUT

IN
OUT

IN

44

44

44 53

44 53

SPI_MLB_CS_L

R5144

20K

5%
1/16W
MF-LF

402

LPC_AD<0>
LPC_AD<1>

SPI_ALT_MOSI
SPI_ALT_MISO
LPC_FRAME_L
PM_CLKRUN_L
SMC_TMS
DEBUG_RESET_L
SMC_TDO
SMC_TRST_L
SMC_MD1
SMC_TX_L

516S0573

MCP SPI Override Options

MCP79 REV A01 REQUIRES EXTERNAL MUX, REV B01 STILL DOES NOT SUPPORT INTERNAL MUX

SPIROM_USE_MLB

44

44

IN

Pull-up on debug card

44

OUT

44 53

IN

53

OUT

1

=PP3V3_S5_ROM

2

53

44

8

D

Alternate SPI ROM Support

MUX SEL CONTROLLED BY FRANKCARD SWITCH ONCE CS1 IS SUPPORTED IN MCP

=PP3V3_S5_LPCPLUS

44

=PP3V3_S5_ROM

53

44

8

R5190

SPI_CLK_R

21 44 90

IN

C

SEL HIGH OUTPUTS TO D (ON BOARD ROM)
SEL LOW OUTPUTS TO M (FRANKCARD ROM)

R5191

10K

1/16W
MF-LF

402

1

5%

2

SPI_MOSI_R

21 44 90

IN

SPIROM_USE_MLB

44

21 44 90

OUT

21 90

IN

SPI_MISO
SPI_CS0_R_L

B

8

1

10K

1/16W
MF-LF

402

5%

2

LPCPLUS

1

Y+

2

Y-

10

SEL OE*

=PP3V3_S5_LPCPLUS

8
44

PI3USB102ZLE

LPCPLUS

1

Y+

2

Y-

PI3USB102ZLE

10

SEL OE*

MCP_CS1_YES&LPCPLUS_NOT

R5146

0

1 2

5%

PLACEMENT_NOTE=PLACE NEXT TO U1400
1/16W
MF-LF

402

9

VCC

U5110

TQFN

CRITICAL

GND

3

9

VCC

U5120

TQFN

CRITICAL

GND

3

5

M+

4

M-

7

D+

6

D-

8

5

M+

4

M-

7

D+

6

D-

8

LPCPLUS

1

C5114

0.1UF

20%
10V

2

CERM
402

SPI_ALT_CLK
SPI_ALT_MOSI

SPI_CLK_MUX
SPI_MOSI_MUX

LPCPLUS

1

C5124

0.1UF

20%
10V

2

CERM
402

SPI_ALT_CS_L_MUX

SPI_MLB_CS_L_MUX

MCP_CS1_NO

1 2

1/16W

MF-LF

1/16W

SPI_ALT_MISO

0

R5127

402

5%

MCP_CS1_NO

0

1 2

5%

MF-LF

SPI MUX BYPASS

LPCPLUS_NOT

R5156

0

SPI_CLK_MUX

44 53

OUT

SPI_MOSI_MUX

44 53

OUT

SPI_MISO_MUX

44 53

IN

A

1 2

5%
1/16W
MF-LF

402

LPCPLUS_NOT

R5158

0

1 2

5%
1/16W
MF-LF

402

LPCPLUS_NOT

R5157

0

1 2

5%
1/16W
MF-LF

402

SPI_CLK_R

SPI_MOSI_R

SPI_MISO

21 44 90

IN

21 44 90

IN

21 44 90

OUT

21 34 37 42 68 81 83

32

2

1

4

3

6

5

8

7

10

9

12

11

14

13

16

15

18

17

20

19

22

21

24

23

26

25

28

27

30

29

33

34

LPC_CLK33M_LPCPLUS
LPC_AD<2>
LPC_AD<3>

SPIROM_USE_MLB
SPI_ALT_CLK

SPI_ALT_CS_L
LPC_SERIRQ
LPC_PWRDWN_L
SMC_TDI
SMC_TCK
SMC_RESET_L
SMC_NMI
SMC_RX_L
LPCPLUS_GPIO

From Frank Card

MCP_CS1_YES

R5147

0

1 2

5%
1/16W
MF-LF

402

To Frank Card

PLACEMENT_NOTE=PLACE NEXT TO U5120

ENSURES MCP79 SPI_DO OR SPI_CLK INPUT IS LOW WHEN STRAP IS LATCHED.NOT NEEDED FOR B01 OR LATER.

23

SLP_S3# nVidia recommendation,
not compatible with button-mashing.

PM_SLP_S3_L

7

IN

MCP_A01&MCP_A01Q

R5160

0

1 2

5%
1/16W
MF-LF

402

MCP_SPI_FORCE_L

26 90

IN

19 42 83 90

BI

19 42 83 90

BI

44

OUT

44

IN

44

IN

19 42

BI

19 42

IN

42 43

OUT

42 43

OUT

42 43

OUT

42

OUT

40 42 43

OUT

18

OUT

MCP79 Internal SPI MUX Support

=PP3V3_S0_LPCPLUS

8

=PP3V3_S5_LPCPLUS

8

44

R5140

100K

1/16W
MF-LF

MCP_CS1_NO

R5142

0

1 2

5%

PLACEMENT_NOTE=Place near J5100
1/16W
MF-LF

402

SPI Frequency Clamp

=PP3V3_S5_MCP_A01

8

MCP_A01&MCP_A01Q

MCP_A01&MCP_A01Q

Q5160

SSM6N15FEAPE

R5163

100K

1/16W
MF-LF

SOT563

5

5%

402

MCP_A01&MCP_A01Q

1

2

MCP_SPI_FORCE

3

D

SG

4

Q5160

SSM6N15FEAPE

SOT563

2

NOT SUPPORTED IN REV A01 OR B01 MCP79 SILICON

MCP_CS1_YES

1

2

5%

402

2

GS

1

Keep very short

MCP_FORCE_SPI_DO_L

6

D

3

LPC_FRAME_PU

D

MCP_CS1_YES

Q5140

SSM3J16FV

SOD-VESM-HF

SPI_CS1_R_L_USE_MLB

MAKE_BASE=TRUE

NO STUFF

R5141

R5161

0

1 2

5%
1/16W
MF-LF

402

1/16W
MF-LF

MCP_A01&MCP_A01Q

R5162

0

SG

1

1 2

5%
1/16W
MF-LF

402

LPC+SPI Debug Connector

SYNC_MASTER=CHANG_M98_MLB

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

1

470

5%

402

2

LPC_FRAME_R_L

=SPI_CS1_R_L_USE_MLB

SPI_MOSI

SPI_CLK

19

OUT

BI

53 90

OUT

53 90

OUT

SYNC_DATE=07/01/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

D

C

9

21

B

A

REV.

A.0.0

OF

9644

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

MCP79 SMBus "0" Connections

=PP3V3_S0_SMBUS_MCP_0

8

1

4.7K

1/16W
MF-LF

2.0K

1

R5201

4.7K

5%

5%
1/16W
MF-LF

402

402

2

2

SO-DIMM "A"

(Write: 0xA0 Read: 0xA1)

=I2C_SODIMMA_SCL

=I2C_SODIMMA_SDA

=I2C_SODIMMB_SCL

=I2C_SODIMMB_SDA

ExpressCard Slot

=SMBUS_EXCARD_SCL

=SMBUS_EXCARD_SDA

J3100 U4900

SO-DIMM "B"

J3200

(Write: 0xA2 Read: 0xA3)

J3500

SMB_0_S0_CLK

28 48

28 42

29

29

32

32

42

SMB_0_S0_DATA

SMB_BSA_CLK

42

SMB_BSA_DATA

42

Battery

Battery Manager - (Write: 0x16 Read: 0x17)
Battery LED Driver - (Write: 0x36 Read: 0x37)

Battery Temp - (Write: 0x90 Read: 0x91)

1

1

R5231

2.0K

5%

5%
1/16W
MF-LF

402

402

2

2

HDCP ROM

U2690 or U2695

(Write: 0xA0-0xAE,

Read: 0xA1-0xAF)

=I2C_HDCPROM_SCL

=I2C_HDCPROM_SDA

Mikey

(WRITE: 0X72 READ: 0X73)

U6860

=I2C_MIKEY_SCL
=I2C_MIKEY_SDA

25

25

SMB_MGMT_CLK

SMB_MGMT_DATA

42

59

59

MCP79

U2300

(MASTER)

SMBUS_MCP_0_CLK

90

21

13

7

D

90

21

13

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

7

MAKE_BASE=TRUE

R5200

C

MCP79 SMBus "1" Connections

=PP3V3_S0_SMBUS_MCP_1

8

R5230

1/16W
MF-LF

SMBUS_MCP_1_CLK

90

21

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

90

21

MAKE_BASE=TRUE

MCP79

U2300

(MASTER?)

B

SMC "0" SMBus Connections

=PP3V3_GPU_SMBUS_SMC_0_S0

8

1

1

SMC

(MASTER)

SMBUS_SMC_0_S0_SCL

93

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

93

MAKE_BASE=TRUE

R5250

4.7K

1/16W
MF-LF

SMC "Battery A" SMBus Connections

=PP3V42_G3H_SMBUS_SMC_BSA

8

SMC

U4900

(MASTER)

SMBUS_SMC_BSA_SCL

93

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

93

MAKE_BASE=TRUE

R5280

1.6K

1/16W
MF-LF

SMC "Management" SMBus Connections

=PP3V3_S3_SMBUS_SMC_MGMT

8

R5290

U4900

(MASTER)

SMBUS_SMC_MGMT_SCL

93

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

93

MAKE_BASE=TRUE

4.7K

1/16W

R5251

4.7K

5%

5%

1/16W
MF-LF
402

402

2

2

1

1

R5281

1.6K

5%

5%
1/16W
MF-LF

402

402

2

2

The bus formerly known as "Battery B"

1

1

R5291

4.7K

5%

5%

1/16W
MF-LFMF-LF
402

402

2

2

GPU Temp (Ext)

EMC1043-1: U5550

(Write: 0x98 Read: 0x99)

=SMBUS_GPUTHMSNS_SCL

=SMBUS_GPUTHMSNS_SDA

GPU Temp (Int)

G96: U8000

(Write: 0x9E Read: 0x9F)

=GPU_I2CS_SCL

=GPU_I2CS_SDA

Battery

J6955

(See Table)

=SMBUS_BATT_SCL

=SMBUS_BATT_SDA

Battery Charger

ISL6258A - U7000

(Write: 0x12 Read: 0x13)

=SMBUS_CHGR_SCL

=SMBUS_CHGR_SDA

Vref DACsSMC

(Write: 0x98 Read: 0x99)

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

Margin Control

(Write: 0x30 Read: 0x31)

=I2C_PCA9557D_SCL

=I2C_PCA9557D_SDA

U2900

U2901

SMB_A_S3_CLK

42

48

77

77

60

60

61

61

27 42

27

27

27

SMB_A_S3_DATA

42

SMB_B_S0_CLK

42

SMB_B_S0_DATA

42

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

=PP3V3_S3_SMBUS_SMC_A_S3

8

1

SMC

(MASTER)

SMBUS_SMC_A_S3_SCL

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

R5270

2.2K

1/16W
MF-LF

5%

402

2

SMC "B" SMBus Connections

=PP3V3_S0_SMBUS_SMC_B_S0

8

1

SMC

U4900

(MASTER)

SMBUS_SMC_B_S0_SCL

93

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SDA =I2C_CPUTHMSNS_SDA

93

MAKE_BASE=TRUE

R5260

3.3K

1/16W
MF-LF

5%

402

2

1

R5271

2.2K

5%
1/16W
MF-LF
402

2

1

R5261

3.3K

5%
1/16W
MF-LF
402

2

TRACKPAD

(Write: 0x90 Read: 0x91)

=I2C_TPAD_SCL

=I2C_TPAD_SDA

(Write: 0x72 Read: 0x73)

I2C_ALS_SCL

I2C_ALS_SDA

(Write: 0x98 Read: 0x99)

=SMBUS_MCPTHMSNS_SCL

=SMBUS_MCPTHMSNS_SDA

(Write: 0x98 Read: 0x99)

=I2C_CPUTHMSNS_SCL

Battery Charger Temp

(Write: 0x92 Read: 0x93)

=SMBUS_TMPSNSR_SCL

=SMBUS_TMPSNSR_SDA

J5800U4900

ALS

J3401

MCP Temp

EMC1043-1: U5500

CPU Temp

EMC1043-1: U5570

TMP102: U5540

51

51

31

31

48

48

D

C

48

48

48

48

B

SMS

(Write: 0x70 Read: 0x71)

=I2C_SMS_SCL

=I2C_SMS_SDA

U5930

52

52

M98 SMBus Connections

A

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=07/22/2008

051-7546

SHT

45 96

1

A

REV.

A.0.0

OF

8 7

CPU Voltage Sense / Filter

=PPVCORE_S0_CPU

12

8

11

Place short near U1000 center

D

=PPVCORE_GPU_REG

78

8

Place short near U8000 center

XW5309

SM

1 2

CPUVSENSE_IN

GPU Voltage Sense / Filter

XW5359

SM

1 2

GPUVSENSE_IN

MCP Voltage Sense / Filter

=PPVCORE_S0_MCP

22

8

24

PLACEMENT_NOTE=Place near U1400 center

XW5399

SM

1 2

MCPVSENSE_IN

R5309

4.53K

1 2

1%
1/16W
MF-LF

402

Place RC close to SMC

R5359

4.53K

1 2

1%
1/16W
MF-LF

402

Place RC close to SMC

R5399

4.53K

1 2

1%
1/16W
MF-LF

402

Place RC close to SMC

SMC_CPU_VSENSE

1

C5309

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

SMC_GPU_VSENSE

1

C5359

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

SMC_MCP_VSENSE

1

C5399

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

6

5

PBUS Voltage Sense & Filter

Q5315

1

5%
1/16W
MF-LF

402

2

PBUSVSENS_EN_DIV

FDG6332CG

SC70-6

P-CHN

D

S

4

G

5

PBUSVSENS_EN_L

3

PPBUS_G3H_VSENSE

MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.20 mm
VOLTAGE=18.5V

1

R5316

100K

5%
1/16W
MF-LF

402

2

6

G

2

1

D

S

N-CHN

Q5315

FDG6332CG

SC70-6

42

OUT

PPBUS_G3H

8

7

R5315

47

43

42

46

42

OUT

47

43

42

46

Enables PBUS VSense divider when high.

43

OUT

47

43

42

46

100K

=PBUSVSENS_EN

68

4

1

R5385

27.4K

1%
1/16W
MF-LF

402

2

1

R5386

5.49K

1%
1/16W
MF-LF

402

2

Place RC close to SMC

Rthevanin = 4573 ohms

SMC_PBUS_VSENSE

1

C5385

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

OUT

47

46

43

42

3

42

2 1

D

C

C

BMON Current Sense - Entire circuit must be near SMC (U4900)

=PP3V42_G3H_BMON_ISNS

8

BMON_ENG

BMON_ENG

1

C5318

0.1uF

20%
10V

2

CERM
402

5

IN-

4

95 61

95 61

REGULATOR SIDE:

CHGR_CSO_R_P

OUT

CHGR_CSO_R_N

IN

LOAD SIDE:

B

Monitors battery discharge

current from battery to PBUS

3

V+

U5303

INA213

SC70

GND

2

BMON_ENG

OUT

REFIN+

6

1

BMON_INA_OUT

61

IN

CHGR_BMON

BMON_PROD

R5330

1/16W
MF-LF

402

0

5%

U5313

NC7SB3157P6XG

B1

1

2

GND

B0

VER 1

12

SC70

1

0

SEL

6

SMC_BMON_MUX_SEL

5

VCC

43

A

BMON_AMUX_OUT

BMON_ENG

1

R5371

100K

5%
1/16W
MF-LF
402

2

43

IN

R5391

4.53K

1 2

1/16W
MF-LF

BMON_ENG

1

C5369

0.1uF

20%
10V

2

CERM
402

DCIN Current Sense Filter

1%

402

SMC_BATT_ISENSE

1

C5390

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

42

OUT

61

CHGR_AMON

IN

47

43

42

46

Place RC close to SMC

R5380

4.53K

1 2

1%
1/16W
MF-LF

402

SMC_DCIN_ISENSE

1

C5380

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

42

OUT

47

46

42

43

B

INA213 has gain of 50V/V

CPU VCore High Side Current Sensor

=PP3V42_G3H_CPUCOREISNS

8

1

C5388

0.1UF

20%
10V

2

CERM
402

6

CPUVCORE_HISIDE_IOUT

1

R5335

4.53K

1 2

1%
1/16W
MF-LF

402

Place RC close to SMC

SMC_CPU_HI_ISENSE

1

C5335

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

43

OUT

47

46

43

42

IN-

3

V+

U5388

INA210

SC70

GND

2

OUT

REFIN+

=PPVIN_S5_CPU_IMVP_ISNS

8

OUT

123

ISNS_CPU_N

R5388

0.001

0.5W

A

=PPVIN_S5_CPU_IMVP_ISNS_R

8

IN

1206

95

1%
MF

95

4

ISNS_CPU_P

5

4

Consider INA211 (GAIN 500 version) since I=4.93 Amps across R5388

CPU VCore Load Side Current Sense / Filter

R5331

6.19K

IMVP6_IMON

62

IN

1 2

1/16W
MF-LF

1%

402

R5332

17.4K

Place RC close to SMC

SMC_CPU_ISENSE

1

1

C5330

0.22UF

2

20%

6.3V

2

X5R
402

GND_SMC_AVSS

1/16W
MF-LF

1%

402

43

42

46

42

OUT

Current & Voltage Sensing

SYNC_MASTER=SENSOR

47

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

SYNC_DATE=08/14/2008

051-7546

SHT

46 96

A

REV.

A.0.0

OF

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

MCP VCore Current Sense

=PP3V3_S0_MCPCOREISNS

8

3

V+

U5420

D

MCPCOREISNS_N

65

95

MCPCOREISNS_P

65

95

5

4

IN-

INA213

SC70

GND

2

OUT

1

C5420

0.1UF

20%
10V

2

CERM
402

6

1

REFIN+

MCP VCore Current Sense Filter

MCPCORE_IOUT

Place RC close to SMC

R5470

4.53K

1 2

1%
1/16W
MF-LF

1

402

2

SMC_MCP_CORE_ISENSE

C5470

0.22UF

20%

6.3V
X5R
402

GND_SMC_AVSS

R5493

4.53K

GFXIMVP6_IMON

78

IN

43

OUT

42

47

46

43

New Gain: 2x can sense current up to 16.6 Amps

1 2

1%
1/16W
MF-LF

402

R5491

1 2

10K

1/16W
MF-LF

402

MCP MEM VDD Current Sense

=PP3V3_S0_MCPDDRISNS

8

=PPMCPDDR_ISNS_R

8

IN

123

DDRISNS_P

1/4W
1206

1%
MF

95

4

DDRISNS_N

95

R5445

0.002

C

8

OUT

=PPMCPDDR_ISNS

SIGNAL_MODEL=EMPTY

R5444

3.65K

1 2

1/16W
MF-LF

R5443

3.65K

1 2

1%
1/16W
MF-LF

402

C5442

470PF

CERM

DDRISNS_R_P

95

1%

402

DDRISNS_R_N

95

SIGNAL_MODEL=EMPTY

1

R5442

1

1M

10%
50V

402

1%
1/16W
MF-LF

2

402

2

3

2

R5441

1M

1 2

1%
1/16W
MF-LF

402

U5440

OPA2333DRBG4

8

DFN

V+

1

V-

THRM

4

9

SIGNAL_MODEL=EMPTY

C5441

470PF

1 2

SIGNAL_MODEL=EMPTY

10%
50V

CERM

402

OPA2333s for proto are placeholders for OPA2330

1

C5440

0.1UF

20%
10V

2

CERM
402

MCP MEM VDD Current Sense Filter

Gain: 274x

Place RC close to SMC

MCPDDR_IOUT

R5440

4.53K

1 2

1%
1/16W
MF-LF

402

SMC_MCP_DDR_ISENSE

1

C5490

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

GPU VCore Current Sense and GPU 1.8V Current Sense share

43

OUT

47

42

46

43

=PP3V3_S0_GPU1V8ISNS

8

=PP1V8_S0GPU_ISNS_R

8

IN

123

P1V8GPU_P

1/4W
1206

95

1%
MF

4

P1V8GPU_N

95

8

OUT

R5413

0.002

=PP1V8_S0GPU_ISNS

SIGNAL_MODEL=EMPTY

B

MCP MEM VDD Current Sense and CPU FSB 1.05V Current Sense share

dual package opamp U5440

CPU FSB 1.05V Current Sense

GPU VCore Current Sense

GPUISENS_P

1%

95

95

GPUISENS_N

3

2

THRM

9

NC

R5498

1 2

1/16W
MF-LF

C5498

470PF

1 2

CERM

dual package opamp U5410

GPU 1.8V Current Sense

R5415

3.65K

1 2

R5414

3.65K

1 2

C5412

470PF

1/16W
MF-LF

1/16W
MF-LF

1%

402

1%

402

10%
50V

CERM

402

P1V8GPUISNS_R_P

95

P1V8GPUISNS_R_N

95

SIGNAL_MODEL=EMPTY

1

R5412

1

1M

1%
1/16W
MF-LF

2

402

2

Gain: 274x

NC

U5410

OPA2333DRBG4

8

DFN

V+
V-

4

NC

10K

1%

402

10%
50V

402

5

6

THRM

R5411

1M

1 2

1%
1/16W
MF-LF

402

1

GPUVCORE_IOUT

U5410

OPA2333DRBG4

8

DFN

V+

7

V-

4

9

SIGNAL_MODEL=EMPTY

C5411

470PF

1 2

SIGNAL_MODEL=EMPTY

10%
50V

CERM

402

1

C5410

0.1UF

20%
10V

2

CERM
402

P1V8_S0GPU_IOUT

GPU VCore Current Sense Filter

Place RC close to SMC

R5475

4.53K

1 2

1%
1/16W
MF-LF

402

GPU 1.8V Current Sense Filter

1 2

SMC_GPU_ISENSE

1

C5475

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

Place RC close to SMC

R5465

4.53K

1%
1/16W
MF-LF

1

402

C5465

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

OUT

47

42

46

43

SMC_GPU_1V8_ISENSE

47

42

46

43

42

D

C

43

OUT

B

NC

R5431

3.65K

1 2

1/16W
MF-LF

402

R5436

3.65K

1%
1/16W
MF-LF

402

470PF

CERM

95

1V05CPUISNS_R_P

1%

1V05CPUISNS_R_N

95

1

10%
50V

2

402

Gain: 274x

SIGNAL_MODEL=EMPTY

1

R5437

1M

1%
1/16W
MF-LF
402

2

5

6

SIGNAL_MODEL=EMPTY

R5432

1M

1 2

1%
1/16W
MF-LF

402

1V05CPU_P

66

95

1V05CPU_N

95

66

A

8

SIGNAL_MODEL=EMPTY

7 6

1 2

C5472

U5440

OPA2333DRBG4

8

DFN

V+

7

V-

THRM

4

9

NC

NC

SIGNAL_MODEL=EMPTY

C5432

470PF

1 2

10%
50V

CERM

402

1.05V CPU Current Sense Filter

CPU1V05_S0_IOUT

1 2

1%
1/16W
MF-LF

402

Place RC close to SMC

SMC_CPU_FSB_ISENSE

1

C5435

0.22UF

20%

6.3V

2

X5R
402

GND_SMC_AVSS

R5495

4.53K

5

43

OUT

Current Sensing

47

42

46

43

SYNC_MASTER=SENSOR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

4

3

2

SCALE

NONE

SYNC_DATE=08/14/2008

051-7546

SHT

OF

47 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

Detect CPU Die Temperature

Detect Right Fin Stack Temperature

Placement note:

Place Q5501 on bottom side
close to right fin stack

C

B

CPU Proximity/CPU Die/Right Fin Stack

=PP3V3_S0_CPUTHMSNS

8

Q5501

BC846BMXXH

SOT732-3

95 10

95 10

3

2

1 2

1/16W
MF-LF

CPU_THERMD_P

BI

SIGNAL_MODEL=EMPTY

CPU_THERMD_N

BI

CPUTHMSNS_D2_P

95

1

SIGNAL_MODEL=EMPTY

CPUTHMSNS_D2_N

95

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm

5%

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

402

C5580

0.0022UF

10%
50V

CERM

402

C5590

0.0022uF

1

2

10%
50V

CERM

402

1

C5570

0.1uF

R5571

1
VDD

U5570

EMC1403-1

DP1

DN1

DP2

DN2

6

DFN

CRITICAL

GND

THRM_PAD

THERM*

ALERT*

SMDATA

SMCLK

11

2

4

5

1

2

20%
10V

2

CERM
402

7

CPUTHMSNS_THM_L

83

CPUTHMSNS_ALERT_L

9

=I2C_CPUTHMSNS_SDA

10

=I2C_CPUTHMSNS_SCL

Placement note:

Place U5570 under CPU
and close to left fin stack

1/16W
MF-LF

10K

402

1

1

R5572

10K

5%

2

2

R5570

47

MCP Proximity/MCP Die/Right Heat Pipe

R5500

47

1 2

5%
1/16W
MF-LF

402

MCP_THMDIODE_P

SIGNAL_MODEL=EMPTY

MCP_THMDIODE_N

SIGNAL_MODEL=EMPTY

Placement note:

Keep 2 caps as close
to IC pins as possible

Detect MCP Die Temperature

Detect Right Heat Pipe Temperature

518S0519

J5502

78171-0002

M-RT-SM

3

1
2

4

=PP3V3_S3_REMTHMSNS

8

95 21

BI

95 21

BI

95

95

MCPTHMSNS_D_P

MCPTHMSNS_D_N

5%
1/16W
MF-LF
402

45

BI

45

BI

PP3V3_S3_REMTHMSNS_R

MIN_LINE_WIDTH=0.38 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

CERM

CERM

1

10%
50V

2

402

1

10%
50V

2

402

C5511

0.0022uF

C5521

0.0022uF

2

4

5

EMC1403-1

DP1

DN1

CRITICAL

DP2

DN2

GND

6

1
VDD

U5500

DFN

THERM*

ALERT*

SMDATA

SMCLK

THRM_PAD

11

Battery Charger Proximity

1

C5500

0.1uF

20%

R5501

10V

2

CERM
402

7

REMTHMSNS_THM_L

83

REMTHMSNS_ALERT_L

9

=SMBUS_MCPTHMSNS_SDA

10

=SMBUS_MCPTHMSNS_SCL

Placement note:

Place U5500 near MCP

10K

1/16W
MF-LF

5%

402

TEMP SENSOR HAS ADDRESS WRITE:0X92, READ: 0X93

=SMBUS_TMPSNSR_SDA

45

=SMBUS_TMPSNSR_SCL

45

Placement note:

Place U5540 near battery
charger circuit

1

1

R5502

10K

5%
1/16W
MF-LF
402

2

2

45

BI

45

BI

=PP3V3_S0_BATTCHARGERTMPSNSR

8

5

V+

U5540

HPA00330AI

SOT563

6

SDA

1

SCL

GND

2

ADD0

ALERT

4

3

1

C5540

0.1uF

20%
10V

2

CERM
402

Note: EMC1403 can perform Beta

Compensation for External Diode 1 only

D

C

B

GPU Proximity/GPU Die/Left Heat Pipe

R5550

47

=PP3V3_S0_GPUTHMSNS

8

95 76

BI

Detect GPU Die Temperature

95 76

BI

GPUTHMSNS_D_P

Detect Left Heat Pipe Temperature

A

Placement note:

Place on top side under left heat pipe near CPU

8

7 6

Q5503

BC846BMXXH

SOT732-3

3

1

2

95

GPUTHMSNS_D_N

95

1 2

1/16W
MF-LF

GPU_TDIODE_P

SIGNAL_MODEL=EMPTY

GPU_TDIODE_N

SIGNAL_MODEL=EMPTY

Placement note:

Keep 2 caps as close
to IC pins as possible

5

PP3V3_S0_GPUTHMSNS_R

MIN_LINE_WIDTH=0.38 mm

5%

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

402

C5551

0.0022uF

C5552

0.0022uF

CERM

CERM

1

C5550

0.1uF

20%
10V

2

CERM

1

EMC1403-1

DP1

DN1

CRITICAL

DP2

DN2

GND

6

VDD

U5550

DFN

THERM*

ALERT*

SMDATA

SMCLK

THRM_PAD

11

1

10%
50V

2

402

1

10%
50V

2

402

2

4

5

402

7

GPUTHMSNS_THM_L

83

GPUTHMSNS_ALERT_L

9

=SMBUS_GPUTHMSNS_SDA

10

=SMBUS_GPUTHMSNS_SCL

Placement note:

Place U5550 near GPU

4

R5551

10K

1/16W
MF-LF

402 402

1

1

R5552

10K

5%

5%
1/16W
MF-LF

2

2

45

BI

45

BI

SYNC_MASTER=SENSOR

APPLE INC.

3

2

Thermal Sensors

SYNC_DATE=08/14/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

48 96

1

A

REV.

A.0.0

OF

8 7

6

5

4

3

2 1

D

C

=PP5V_S0_FAN_LT

8

7

=PP3V3_S0_FAN_LT

8

SMC_FAN_0_TACH

42 42

OUT OUT

R5651

100K

5%
1/16W
MF-LF

402

42

IN

SMC_FAN_0_CTL

Left Fan

R5655

47K

1 2

5%
1/16W
MF-LF

S D

4

402

5

G

Q5660

2N7002DW-X-G

SOT-363

3

1

2

Right Fan

=PP5V_S0_FAN_RT

8

=PP3V3_S0_FAN_RT

CRITICAL

J5650

1

5%

402

2

78171-0004

M-RT-SM

5

1
2
3
4

6

FAN_LT_TACH

7

R5650

47K

1/16W
MF-LF

518S0369

FAN_LT_PWM

7 7

8

42

IN

SMC_FAN_1_TACH

R5661

100K

SMC_FAN_1_CTL

1/16W
MF-LF

R5665

47K

1 2

5%
1/16W
MF-LF

S D

1

2

G

402

Q5660

2N7002DW-X-G

SOT-363
6

1

5%

402

2

R5660

FAN_RT_TACH

7

FAN_RT_PWM

47K

1/16W
MF-LF

1

5%

402

2

CRITICAL

J5660

78171-0004

M-RT-SM

5

1
2
3
4

6

518S0369

D

C

B

B

Fan Connectors

A

SYNC_MASTER=M87_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=10/17/2007

051-7546

SHT

OF

9649

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

PIN NAME

PSOC USB CONTROLLER

USB INTERFACES TO MLB

SPI HOST TO Z2

D

PICKB_L

7

51

BUTTON_DISABLE

50

Z2_HOST_INTN

51

7

WS_LEFT_SHIFT_KEY

50

WS_LEFT_OPTION_KEY

50

WS_CONTROL_KEY

50

Z2_KEY_ACT_L

7

51

Z2_BOOT_CFG1

51

7

TP_P4_5
Z2_DEBUG3

51

7

Z2_RESET

51

7

PSOC_MISO

7

51

PSOC_F_CS_L

51

7

PSOC_MOSI

51

7

PSOC_SCLK

7

51

Z2_MISO

7

51

Z2_CS_L

7

51

Z2_MOSI

7

51

Z2_SCLK

7

51

C

ISSP_SCLK_P1_1

50

DIFFERENTIAL_PAIR=USB2_TPAD

B

TO MLB CONNECTOR

DIFFERENTIAL_PAIR=USB2_TPAD

90

90

20

20

USB_TPAD_P

USB_TPAD_N

P2_3
P2_1
P4_7
P4_5
P4_3
P4_1
P3_7
P3_5
P3_3
P3_1
P5_7
P5_5
P5_3
P5_1

TP_PSOC_SCL

TP_PSOC_SDA

TP_PSOC_P1_3

ISSP SCLK/I2C SCL

R5701

24

1 2

5%

1/16W
MF-LF

402

R5702

24

1 2

5%

1/16W
MF-LF

402

P2_5

P1_7

15

TRACKPAD PICK BUTTONS
KEYBOARD SCANNER

PP3V3_S3_PSOC

50
7

WS_KBD23

51

55

P2_7

P0_3

P0_1

P0_5

P0_7

50

VSS

VDD

P0_4

P0_6

CRITICAL

U5701

CY8C24794

MLF

(SYM-VER2)

APN 337S2983

OMIT

VSS

19

P7_7

D+

D-

VDD

20

21

24

235722 49

P1_1

P1_3

P1_5

USB_TPAD_R_P

DIFFERENTIAL_PAIR=USB2_TPAD
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D

USB_TPAD_R_N

DIFFERENTIAL_PAIR=USB2_TPAD
NET_SPACING_TYPE=USB
NET_PHYSICAL_TYPE=USB_90D

50

50

50

50

50

7

7 7 7

7

WS_KBD18

WS_KBD19

WS_KBD20

WS_KBD21

WS_KBD22

45544653475248

435644

P2_2

P2_4

P2_6

P0_2

P0_0

P2_0
P4_6
P4_4
P4_2
P4_0
P3_6
P3_4
P3_2
P3_0
P5_6
P5_4
P5_2
P5_0

P1_0

P1_2

P1_4

THRML

P1_6

P7_0

25182617271628

ISSP_SDATA_P1_0

ISSP SDATA/I2C SDA

PP3V3_S3_PSOC

50

PAD

421

WS_KBD17

412

WS_KBD16N

403

WS_KBD15_C

394

WS_KBD14

385

WS_KBD13

376

WS_KBD12

367

WS_KBD11

358

WS_KBD10

349

WS_KBD9

3310

WS_KBD8

3211

WS_KBD7

3112

WS_KBD1

3013

WS_KBD2

2914

WS_KBD3

WS_KBD4
WS_KBD5
WS_KBD6

Z2_CLKIN

TP_P7_7

50

7

50

50

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

7

50

50

7

50

7

50

7

50

51

7

IC

TMP102

3V3 LDO

PSOC

18V BOOSTER

PSOC PROGRAMMING CONNECTOR

TEST POINTS ARE FOR ON BOARD PROGRAMMING

=PP3V3_S3_TPAD

50

8

ISSP_SCLK_P1_1

50

ISSP_SDATA_P1_0

50

=PP3V3_S3_TPAD

50

8

WS_LEFT_SHIFT_KBD

50

7

=PP3V3_S3_TPAD

50

8

WS_LEFT_OPTION_KBD

50

7

50

8

50

7

CURRENT
10UA

V+

80UA
60MA MAX

VDD
VOUT

60MA MAX

VDD

8MA (TYP)

14MA (MAX)

VIN

4MA (MAX)

ISOLATION CIRCUIT

=PP3V42_G3H_TPAD

50

8

=PP3V42_G3H_TPAD

50

8

=PP3V42_G3H_TPAD

50

8

=PP3V3_S3_TPAD

WS_CONTROL_KBD

U5701 CHIP DECOUPLING
PLACE C5701, C5702 & C5703

CLOSE TO U5701

PP3V3_S3_PSOC

50

1

C5701

4.7UF

20%

6.3V

2

X5R
603

VDD PIN 22

1

C5702

100PF

5%
50V

2

CERM

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

1

C5703

0.1UF

10%
16V

2

X7R-CERM
402402

PLACE C5704, C5705 & C5706

CLOSE TO U5701

1

2

C5704

100PF

5%
50V
CERM

VDD PIN 49

1

2

C5705

0.1UF

10%
16V
X7R-CERM
402402

1

C5706

4.7UF

20%

6.3V

2

X5R
603

R5704

1.5

1 2

5%
1/16W
MF-LF

402

=PP3V3_S3_TPAD

8

50

TPAD BUTTONS DISABLE

R_SNS

2.55 KOHM

10 OHM

0.2 OHM

1.5 OHM

4.7 OHM

2

A

U5725

1

B

2

A

U5726

1

B

2

A

U5727

1

B

BUTTON_DISABLE

50

Q5701

SSM3K15FV

SOD-VESM-HF

0.0255 V

0.204 V

0.6 V

0.012 V

0.012 V

0.021 V

0.0188 V

CRITICAL

TC7SZ08AFEAPE

5

SOT665

4

Y

3

CRITICAL

TC7SZ08AFEAPE

5

SOT665

4

Y

3

CRITICAL

TC7SZ08AFEAPE

5

SOT665

Y

3

3

D

POWERV_SNS

0.255E-6 W

16.32E-6 W
36E-3 W

0.72E-3 W
96E-6 W

294E-6 W

75.2E-6 W

TPAD_DEBUG

APN 518S0430

J5702

FH19C-4S-0.5SH25

F-RT-SM1

5

NC

1
2
3

ISSP CLOCK

4

ISSP DATA

6

NC

42

43

C5725

0.1UF

12

20%
10V

CERM

402

WS_LEFT_SHIFT_KEY

WS_LEFT_OPTION_KEY

4

PLACE THESE COMPONENTS CLOSE TO J5800

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

WS_CONTROL_KEY

50

50

50

50

50

SMC_ONOFF_L

OUT

WS_KBD15_C

WS_KBD16N

PLACEMENT_NOTE=NEAR J5713

50

50

50

R5714

470

1 2

1%
1/16W
MF-LF

402

R5715

10K

1 2

1%
1/16W
MF-LF

402

1

C5710

0.1UF

20%
10V

2

CERM
402

SMC_MANUAL_RESET LOGIC

WS_LEFT_SHIFT_KBD

7

WS_LEFT_OPTION_KBD

7

WS_CONTROL_KBD

7

1

R5769

33K

5%

1/16W
MF-LF
402

2

A

1

SMC_LID

41 42 43

IN

G S

THE TPAD BUTTONS WILL BE DISABLE

2

WHEN THE LID IS CLOSED
LID OPEN => SMC_LID_LC ~ 3.42V

LID CLOSE => SMC_LID_LC < 0.50V

KEYBOARD CONNECTOR

J5713

APN 518S0637

NC

R5710

1K

1 2

5%
1/16W
MF-LF

402

50

8

=PP3V3_S3_TPAD

IN

WS_KBD1

50

7

WS_KBD2

7

50

WS_KBD3

7

50

WS_KBD4

7

50

WS_KBD5

7

50

WS_KBD6

7

50

WS_KBD7

7

50

WS_KBD8

7

50

WS_KBD9

7

50

WS_KBD10

7

50

WS_KBD11

7

50

WS_KBD12

50

7

WS_KBD13

7

50

WS_KBD14

7

50

WS_KBD15_CAP

7

WS_KBD16_NUM

7

WS_KBD17

7

50

WS_KBD18

7

50

WS_KBD19

7

50

WS_KBD20

7

50

WS_KBD21

7

50

WS_KBD22

7

50

WS_KBD23

7

50

WS_KBD_ONOFF_L

7

=PP3V42_G3H_TPAD

8

50

WS_LEFT_SHIFT_KBD

7

50

WS_LEFT_OPTION_KBD

7

50

WS_CONTROL_KBD

7

50

NC

FF14-30A-R11B-B-3H

=PP3V42_G3H_TPAD

8

50

APN 311S0406

CRITICAL

5

SN74LVC1G10

1

R5770

33K

5%

1/16W
MF-LF
402

2

1

R5771

33K

5%
1/16W
MF-LF
402

2

1
3
6

A
B

U5703

C

SC70

4

Y

2

WELLSPRING 1

SYNC_MASTER=AMASON_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

32

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10

9
8
7
6
5
4
3
2
1

31
F-RT-SM

1

C5758

0.1UF

10%
16V

2

X7R-CERM
402

SMC_TPAD_RST_L

DRAWING NUMBER

SIZE

D

SCALE

NONE

43

SYNC_DATE=06/18/2008

REV.

051-7546

SHT

A.0.0

OF

9650

D

C

B

A

8

7 6

5

4

3

2

1

D

8

PLACEMENT_NOTE=NEAR J5800

C

8 7

PLACEMENT_NOTE=under L5800 on top side

R5800

NO STUFF

CRITICAL

=PP5V_S3_TPAD

1

C5800

0.1UF

20%
10V

2

CERM
402

PLACEMENT_NOTE=NEAR J5800

L5800

0.01H-0.3A-80V
SM-HF

SYM_VER-1

1

2 3

PLACEMENT_NOTE=under L5800 on top side

0

1 2

5%
1/10W
MF-LF

603

4

R5801

0

1 2

5%
1/10W
MF-LF

603

VOLTAGE=3V3
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

PP5V_S3_TPAD_F

TPAD_GND_F

VOLTAGE=0V
MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

6

5

4

3

2 1

BOOSTER +18.5VDC FOR SENSORS

BOOSTER DESIGN CONSIDERATION:

- POWER CONSUMPTION

- DROOP LINE REGULATION

- RIPPLE TO MEET ERS

- 100-300 KHZ CLEAN SPECTRUM

- STARTUP TIME LESS THAN 2MS

PP5V_S3_TPAD_F

51

0

5%

402

1/16W

MF-LF

R5805

1 2

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

51

51

7

1

C5816

0.1UF

10%
16V

2

X7R-CERM
402

INPUT_SW

0.50MM

0.20MM

PP5V_S3_BOOSTER

1

C5817

2.2UF

10%
16V

2

X5R
603

APN 152S0504

CRITICAL

L5801

3.3UH-870MA

VLF3010AT-SM-HF

APN 353S1401

2

VIN

U5805

1

L

TPS61045

QFN

DO

CRITICAL

THRML

PAD

PGND

7

9

CTRL

GND

6

FB

SW

BOOST_SW

4

53

8

- R5812,R5813,C5818 MODIFIED

D5802

SOD-323

MIN_LINE_WIDTH=0.50MM

MIN_NECK_WIDTH=0.20MM
SWITCH_NODE=TRUE

B0520WSXG

APN 371S0313

BOOST_FB

Z2_BOOST_EN

1

R5811

100K

1%
1/16W
MF-LF
402

2

51

7

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM

1

2

TPAD_GND_F

51

7

C5818

39PF

5%
50V
CERM
402

PP18V5_S3_SW

1

R5812

1M

1%
1/16W
MF-LF
402

2

1

R5813

71.5K

1%

1/16W
MF-LF

402

2

1

C5819

1UF

10%
25V

2

X5R
603-1

R5806

0

1 2

5%
1/16W
MF-LF

402

PP18V5_S3

7

51

TPAD_GND_F

7

51

Z2_CS_L

50

7

Z2_DEBUG3

7

50

Z2_MOSI

7

50

Z2_MISO

50

7

Z2_SCLK

7

50

Z2_BOOST_EN

7

51

Z2_HOST_INTN

7

50

Z2_BOOT_CFG1

7

50

Z2_CLKIN

7

50

PP3V3_S3_LDO

7

51

IPD FLEX CONNECTOR

APN 516S0689

CRITICAL

J5800

55560-0227

0.50MM

M-ST-SM

0.50MM

0.20MM

0.20MM

1

2

34
56
78

10

9
1112
1314
1516
1718
19

20

2122

Z2_KEY_ACT_L

PSOC_F_CS_L

=I2C_TPAD_SDA

=I2C_TPAD_SCL

0.50MM

0.20MM

Z2_RESET

PICKB_L

PSOC_MISO

PSOC_MOSI

PSOC_SCLK

PP18V5_S3

50

7

7

50

50

7

50

7

50

7

50

7

50

7

45

45

51

7

D

C

3V3 LDO FOR IPD

R5873

PP5V_S3_TPAD_F

51

10

1 2

1%
1/16W
MF-LF

402

PP5V_S3_VR

7

PP3V3_S3_LDO

51

CRITICAL

APN 353S1364

2

1

C5853

2.2UF

10%

16V

2

X5R

603

B

VDD

VR5802

MM3243DRRE

MLF

1

CE

GND

4

PP3V3_S3_LDO_R

3

VOUT

2

0.2

R5836

1

MF

1/6W

402-HF

1

C5838

0.1UF

10%

16V

2

X7R-CERM
402

1%

1

C5854

4.7UF

20%

6.3V

2

X5R
603

B

TPAD_GND_F

51

7

Keyboard LED Driver

=PP3V3_S0_TPAD

8

1

To detect Keyboard backlight, SMC will
tristate SMC_SYS_KBDLED:

LOW = keyboard backlight present
HIGH= keyboard backlight not present

BOM OPTION: KBDLED_YES

A

R5853 ALWAYS PRESENT

42

SMC_SYS_KBDLED

IN

SMC_KDBLED_PRESENT_L

51

R5853

470K

1/16W
MF-LF

402

R5854

5%

4.7K

1/16W
MF-LF

402

2

1

5%

2

=PP5V_S0_KBDLED

8

C5850

1UF

10%
10V
X5R

402-1

NO STUFF

R5852

1/16W
MF-LF

10K

402

1

5%

2

CRITICAL

L5850

10UH-0.58A-0.35OHM

1 2

1

2

6

CTRL

CRITICAL

GND

1

VIN

U5850

LT3491

DFN

THRML

2

PAD

7

1098AS-SM

3

SW

5

LED

4

CAP

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM
MIN_NECK_WIDTH=0.25 MM
SWITCH_NODE=TRUE

1

R5855

10

1%

1/16W

MF-LF

402

2

KBDLED_CAP

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

KBDLED_ANODE

7

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM

1

C5855

1UF

10%
35V

2

X5R
603

SMC_KDBLED_PRESENT_L

51

KBD BACKLIGHT CONNECTOR

CRITICAL

J5815

FF18-4A-R11AD-B-3H

F-RT-SM

1
2
3
4

APN 518S0612

J5815 pin 1 is grounded
on keyboard backlight flex

APPLE INC.

WELLSPRING 2

SYNC_MASTER=PWRSQNC

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

SCALE

SYNC_DATE=05/12/2008

DRAWING NUMBER

NONE

051-7546

SHT

51 96

A

REV.

A.0.0

OF

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

Pull-up required if SMS_INT_L not used.

52

8

43 42

8

SMS_INT_L

43

OUT

=PP3V3_S5_SMC

1

R5932

10K

5%

1/16W

MF-LF

402

2

1

R5931

10K

5%

1/16W

MF-LF

402

2

PROD_DIGSMS

ENG_DIGSMS

=I2C_SMS_SCL

45

=I2C_SMS_SDA

45

Digital SMS

=PP3V3_S3_SMS

2

VDD

U5930

6

SCK

273141043

7

SDO

CRITICAL

8

SDI

4

INT

5

CSB

VDDIO

LGA

RESERVED

GND

3

9

11

NC

12

1
10

ENG_DIGSMS

ENG_DIGSMS

1

C5931

0.022UF

10%

NC
NC

NC
NC

16V

2

CERM-X5R

402

ENG_DIGSMS

1

C5932

0.1UF

10%

16V

2

X5R

402

Circle indicates pin 1 location when placed
in correct orientation

Desired orientation when
placed on board top-side:

+Y

Front of system

+Z (up)

+X

D

Stuff R5931 AND NoStuff R5932 to use U5930

C

NoStuff R5931 AND Stuff R5932 if U5930 is not used

C

Analog SMS

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

=PP3V3_S3_SMS

52

8

B

42

IN

SMS_ONOFF_L

SMS_PWRDN

MAKE_BASE=TRUE

R5921

10K

1/16W
MF-LF

5%

402

1

2

SMS_SELFTEST

5%
1/16W
MF-LF
402

NC
NC

NC
NC

1

R5922

10K

2

1
5
2

15

4
3

6
9

14

VDD

U5920

AP344ALH

LGA

FS
PD

CRITICAL

ST

RES
RES

NC
NC
NC

GND

7

VOUTX

VOUTY

VOUTZ

NC
NC
NC

SMS_X_AXIS

12
10

SMS_Y_AXIS

8

SMS_Z_AXIS

11

NC

13

NC

16

NC

1

C5922

0.1UF

10%
16V

2

X5R
402

1

C5923

0.01UF

10%
16V

2

CERM
402

1

2

1

C5924

0.01UF

10%
16V

2

CERM
402

C5926

10UF

20%
4V
X5R
603

1

C5925

0.01UF

10%
16V

2

CERM
402

42

OUT

42

OUT

42

OUT

A

Desired orientation when
placed on board top-side:

+Y

Front of system

+Z (up)

Circle indicates pin 1 location when placed
in correct orientation

+X

Sudden Motion Sensor (SMS)

SYNC_MASTER=SENSOR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=08/14/2008

051-7546

SHT

52 96

B

A

REV.

A.0.0

OF

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

=PP3V3_S5_ROM

44

8

NO STUFF

1

R6190

10K

5%
1/16W
MF-LF

402

C

44

IN

SPI_CLK_MUX

SPI_MLB_CS_L

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6150

0

1 2

5%
1/16W
MF-LF

402

2

R6100

3.3K

1/16W
MF-LF

402 402

1

1

R6101

3.3K

5%

5%
1/16W
MF-LF

2

2

SPI_CLK

90 44

44

SPI_WP_L
SPI_HOLD_L

C6100

0.1UF

CERM

20%
10V

402

1

2

6

SCLK

1

CE*

3

WP*/ACC

7

HOLD*

CRITICAL

8

VCC

U6100

32MBIT

SOP

OMIT

GND

4

SI/SIO0

SO/SIO1

MX25L3205DM2I-12G

5

2

SPI_MOSI

90

SPI_MISO_R

90

NO STUFF

1

R6191

10K

5%
1/16W
MF-LF
402

2

R6152

0

1 2

5%

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6105

0

1 2

5%
1/16W
MF-LF

402

1/16W
MF-LF

402

PLACEMENT_NOTE=PLACE CLOSE TO U6100

SPI_MOSI_MUX

SPI_MISO_MUX

44 44

ININ

44

OUT

D

C

MCP79 SPI Frequency Select

Frequency

B

31 MHz

42 MHz

25 MHz

1 MHz

25MHz is selected with R5190 and R5191
Any of the 4 frequencies can be selected
with R6190, R6191, R5190 and R5191

0

0

1

1

SPI_CLKSPI_MOSI

0

B

1

0

1

SPI ROM

A

SYNC_MASTER=CHANG_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

SYNC_DATE=07/01/2008

051-7546

SHT

OF

53 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

AUDIO CODEC

APPLE P/N 353S1527

XW6203

SM

4V6_REG_SENSE

54

L6201

FERR-220-OHM

=PP3V3_S0_AUDIO

59

58

54

D

8

HDA_BITCLK

9

IN

HDA_SYNC

21 90

IN

HDA_SDOUT

21 90

IN

HDA_SDIN0

21 90

OUT

AUD_GPIO_0

56

OUT

AUD_GPIO_1

IN

AUD_BI_PORT_C_R

57

OUT

AUD_BI_PORT_D_L

56

OUT

AUD_BI_PORT_D_R

56

OUT

1 2

0402

R6204

22

1 2

5%
1/16W
MF-LF

402

R6251

20K

1/16W
MF-LF

402

1

5%

2

NC_AUD_BI_PORT_C_L

C

HDA_RST_L

21 90

IN

59

GND_AUDIO_CODEC

57

56

55

54

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

C6200

4.7UF

20%

4V
X5R
402

CODEC_SDATA_IN

R6250

33

1 2

5%
1/16W
MF-LF

402

VOLTAGE=3.3V

1

1

2

C6201

0.001UF

10%
50V

2

CERM
402

AUD_GPIO_0_R

NC_BAL_IN_L
NC_BAL_IN_COM
NC_BAL_IN_R

1

R6205

100K

5%
1/16W
MF-LF
402

2

BEEP

1

C6220

0.1UF

10%
16V

2

X5R
402

MIN_LINE_WIDTH=0.20MM

25

38

AVDD2

AVDD1

LQFP

PORT-A-VREFO/DCVOL

AVSS2

AVSS1

26

42

MIN_NECK_WIDTH=0.20MM

CODEC_DVDD

1

C6203

0.001UF

10%
50V

2

CERM
402

6

BCLK

10

SYNC

5

SDATA_OUT

8

SDATA_IN

2

GPIO0/DMIC-CLK

3

GPIO1/DMIC-L

23

NO_TEST

NO_TEST
NO_TEST
NO_TEST

PORT-C-L

24

PORT-C-R

35

PORT-D-L

36 14

PORT-D-R

18

CD-L

19

CD-GND

20

CD-R

12

BEEP

11

RESET*

2

XW6201

SM

1

1

9

DVDD

DVDD_IO

SPDIFI/EAPD/MIDI-I/DMIC-R

CRITICAL

U6200

ALC885-VB3-GR

REV B3

DVSS

4

7

AVDD_ADC_DAC

SPDIFO

SENSE_A
SENSE_B

PORT-A-L
PORT-A-R

PORT-F-L
PORT-F-R

PORT-F-VREFO

PORT-E-L

PORT-E-R
PORT-E-VREFO
PORT-B-VREFO

PORT-B-L

PORT-B-R

PORT-C-VREFO

PORT-B-VREFO2

PORT-G-L

PORT-G-R

PORT-H-L

PORT-H-R

VREF

JDREF

NC

1 2

CRITICAL

C6204

100UF

20%

6.3V
TANT

CASE-AL1

48
47

13
34

39
41

16
17
30
33

15
31

NO_TEST

28
21
22

29

NO_TEST

32

NO_TEST

43

NO_TEST

44

NO_TEST

45

NO_TEST

46

NO_TEST

27

AUD_CODEC_JDREF

40

NC_VRP

37

NO_TEST

1

1

C6206

0.001UF

10%
50V

2

2

CERM
402

AUD_SPDIF_O

NC_AUD_VREF_PORT_E

NC_AUD_VREF_PORT_C

NC_AUD_VREF_PORT_B2

NC_AUD_BI_PORT_G_L
NC_AUD_BI_PORT_G_R

NC_AUD_BI_PORT_H_L
NC_AUD_BI_PORT_H_R

AUD_CODEC_VREF

1

R6206

20.0K

1%
1/16W
MF-LF
402

2

R6208

1 2

5%
1/16W
MF-LF

402

CRITICAL

C6221

3.3UF

10%
16V

TANT

SMA-HF

0

R6203

33

1 2

5%
1/16W
MF-LF

402

1

C6222

0.001UF

10%

50V

2

CERM

402

1

2

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=4.6V

PP4V6_AUDIO_ANALOG

1

C6207

0.001UF

20%
50V

2

CERM
402

GND_AUDIO_CODEC

1

R6207

100K

5%
1/16W
MF-LF
402

2

59

55

54

59

57

56

55

54

AUD_SPDIF_OUT

AUD_SPDIF_IN
AUD_SENSE_A
AUD_SENSE_B

AUD_BI_PORT_A_L
AUD_BI_PORT_A_R

AUD_BI_PORT_F_L
AUD_BI_PORT_F_R
AUD_VREF_PORT_F
AUD_VREF_PORT_A
AUD_BI_PORT_E_L
AUD_BI_PORT_E_R

AUD_VREF_PORT_B
AUD_BI_PORT_B_L
AUD_BI_PORT_B_R

D

58

OUT

58

IN

59

IN

59

IN

55

IN

55

IN

59

IN

59

IN

59

OUT

55

OUT

59

IN

59

IN

57

OUT

57

OUT

57

OUT

C

B

AUDIO 4.6V REGULATOR

B

APPLE P/N 353S1897

C6211

0.015UF

4V6_REG_BP

CRITICAL

L6200

FERR-220-OHM

C6210

0.1UF

10%
16V
X5R
402

1 2

0402

PP5V_S3_AUDIO

56

9

R6220

1K

=PP3V3_S0_AUDIO

59

58

54

8

A

8

7 6

1 2

5%
1/16W
MF-LF

402

XW6200

SM

1 2

AUD_REG_SHDN_L

1

2

MIN_LINE_WIDTH=0.30 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=5V

AUD_4V6_REG_IN

1

R6221

10K

5%
1/16W
MF-LF
402

2

CRITICAL

C6208

10UF

20%
16V

TANT-POLY

2012-LLP

3

1

7

1

1

C6209

0.001UF

10%
50V

2

2

CERM
402

5

10%
16V
X7R
402

U6201

MAX8902A

TDFN

IN

BP

GNDENPAD
2

12

SELA
SELB

OUTS

THRML

9

OUT

4
5

8
6

4V6_REG_SENSE

4

PP4V6_AUDIO_ANALOG

54

CRITICAL

1

C6205

100UF

20%

6.3V

2

TANT
CASE-AL1

1

C6212

0.1UF

10%
16V

2

X5R
402

GND_AUDIO_CODEC

3

59

55

54

AUDIO:CODEC

SYNC_MASTER=AUDIO

59

57

56

55

54

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

2

SYNC_DATE=07/09/2008

051-7546

SHT

OF

9654

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

D

Pseudo-Diff Line-In Filter
GAIN = -5.4DB AV = 0.52

FC = 1.8 HZ

L6300

FERR-220-OHM

PP4V6_AUDIO_ANALOG

59

54

AUD_LI_INL

58

IN

C

AUD_LI_GND

58

IN

57

56

55

54

GND_AUDIO_CODEC

59

B

AUD_LI_INR

58

IN

1 2

0402

R6302

27.4K

1/16W
MF-LF

R6301

10

1 2

5%
1/16W
MF-LF

402

R6303

27.4K

1/16W
MF-LF

MIN_LINE_WIDTH=0.20MM
MIN_NECK_WIDTH=0.20MM

PP4V6_AUDIO_LINE_IN

CRITICAL

C6310

10UF

20%
16V

TANT-POLY

2012-LLP

1

1%

402

2

CRITICAL

C6311

10UF

20%
16V

TANT-POLY

2012-LLP

C6320

10UF

20%
16V

TANT-POLY

2012-LLP

CRITICAL

1

1%

402

2

CRITICAL

C6321

10UF

20%
16V

TANT-POLY

2012-LLP

12

AUD_LI_INL_C

12

AUD_LIFILT_LT_R

12

AUD_LIFILT_RT_R

12

R6310

25.5K

1 2

1%

1/16W

402

CRITICAL

C6301

R6311

25.5K

1 2

1%
1/16W
MF-LF

402

R6320

25.5K

1 2

1%
1/16W
MF-LF

402

R6321

25.5K

1 2

1%
1/16W
MF-LF

402

AUD_LI_INL_R

1

2.2UF

20%

6.3V

2

CERM

402-LF

AUD_LIFILT_LT

AUD_LIFILT_RT

AUD_LI_INR_RAUD_LI_INR_C

CRITICAL

C6300

0.001UF

10%
50V

CERM

402

R6312

13.3K

1 2

1%
1/16W
MF-LFMF-LF

402

AUD_PORTA_L

CRITICAL

10

8

U6300

7

13.3K

1%
1/16W
MF-LF

402

13.3K

1%
1/16W
MF-LF

402

3

U6300

2

R6323

V+

V-

4

4

V-

V+

10

13.3K

1 2

1%
1/16W
MF-LF

402

MAX4253EUB

UMAX-HF

9

6

AUD_CODEC_INREF

CRITICAL

C6303

0.001UF

5

1

UMAX-HF

MAX4253EUB

CRITICAL

AUD_LIFILT_SHUTDOWN_L

1

10%
50V

2

CERM

402

AUD_PORTA_R

1

2

R6313

1 2

R6322

1 2

CRITICAL

R6300

1 2

1/16W
MF-LF

CRITICAL

1

C6302

100UF

20%

6.3V

2

TANT
CASE-AL1

C6312

2.2UF

1 2

10%
16V
X5R
603

165

1%

402

C6322

2.2UF

1 2

10%
16V
X5R
603

CRITICAL

AUD_BI_PORT_A_L

AUD_VREF_PORT_A

GND_AUDIO_CODEC

AUD_BI_PORT_A_R

54

OUT

C

59

IN

54

IN

59

57

56

55

54

54

OUT

B

AUDIO: LINE IN

A

SYNC_MASTER=AUDIO

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

SYNC_DATE=07/09/2008

DRAWING NUMBER

051-7546

SHT

NONE

A

REV.

A.0.0

OF

9655

1

8 7

6

5

4

3

2 1

Headphone Amplifier (MAX9724A)

APN:353S1637

D

PP5V_S3_AUDIO

54

9

AUD_HPAMP_INL_M

56

IN

AUD_HPAMP_INR_M

56

IN

L6501

FERR-1000-OHM

54

IN

AUD_GPIO_0

1 2

0402

C

GND_AUDIO_CODEC

59 57

55

54

L6500

FERR-120-OHM-1.5A

1 2

0402

AUD_HPAMP_MUTE_L

XW6500

SM

1 2

XW6501

PP5V_AUDIO_HPAMP_PVDD_F

VOLTAGE=5V
MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 mm

CRITICAL

C6500

TANT-POLY

2012-LLP

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 mm

GND_AUDIO_HPAMP_PGND

SM

1 2

10UF

20%
16V

R6500

10K

1/16W
MF-LF

402

1

C6501

1

2

1

5%

2

0.001UF

10%
50V

2

CERM
402

AUD_HPAMP_OUTL_R

0

5%

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.15 mm

AUD_PORTD_L

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.15 mm

AUD_PORTD_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.15 mm

AUD_HPAMP_OUTR_R

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.15 mm

AUD_LO_GND

12

6

INL

U6500

8

INR

MAX9724A

SHDN*

THRM
13

PAD

SGND

TQFN

PGND

247

5

OUTL
OUTR

C1P
C1N

SVSS

9

CRITICAL

1

C6503

1UF

10%
10V

2

X5R
402

PVSS

11
10

1
3

MAX9724_C1P

MAX9724_C1N

MIN_LINE_WIDTH=0.20 mm
MIN_NECK_WIDTH=0.10 mm

MAX9724_PVSS

CRITICAL

C6502

10UF

X5R-CERM

0805

10%
16V

1

2

CRITICAL

C6504

1UF

10%
10V
X5R
402

1

2

R6514

2.21K

1% 1%
1/16W
MF-LF

402

1

1

2

2

VDD

CRITICAL

R6513

0

1 2

5%
1/16W
MF-LF

402

R6524

2.21K

1/16W
MF-LF
402

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 mm

R6523

1 2

1/16W
MF-LF

402

56

58

OUT

58

OUT

56

58

IN

D

C

1st Order DAC Filter

HP:3.52 HZ
VOLTAGE GAIN:1.53

B

CRITICAL

C6510

3.3UF

AUD_BI_PORT_D_L

54

IN

AUD_HPAMP_INL_M

56

AUD_HPAMP_INR_M

56

1 2

10%
16V

TANT

SMA-HF

AUD_CODEC_OUTL_C

CRITICAL

C6520

3.3UF

AUD_BI_PORT_D_R

54

IN

A

1 2

10%
16V

TANT

SMA-HF

AUD_CODEC_OUTR_C

R6510

13.7K

1 2

1%
1/16W
MF-LF

402

R6520

13.7K

1 2

1%
1/16W
MF-LF

402

LP:34 KHZ

R6511

21K

1 2

1%
1/16W
MF-LF

402

CRITICAL

C6511

220PF

5%

25V

CERM

402

CRITICAL

C6521

220PF

5%

25V

CERM

402

R6521

21K

1 2

1%
1/16W
MF-LF

402

B

AUD_HPAMP_OUTL_R

12

12

AUD_HPAMP_OUTR_R

56

56

APPLE INC.

AUDIO: HEADPHONE AMP

SYNC_MASTER=AUDIO

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SYNC_DATE=07/09/2008

051-7546

SHT

OF

56 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

2X MONO SPEAKER AMPLIFIERS (LM48310)

APN: 353S1901

GAIN = 12DB

79Hz < FC (L&R) < 93Hz
53Hz < FC (SUB) < 62Hz

D

C

PP5V_S3_AUDIO_AMP

9

57

54

54

AUD_BI_PORT_B_L

IN

AUD_VREF_PORT_B

IN

59

57

L6610

FERR-1000-OHM

1 2

L6601

FERR-1000-OHM

1 2

0402

GND_AUDIO_CODEC

56

54 57

55

AUD_SPKRAMP_SHUTDOWN_L

57

0402

R6601

100K

1/16W
MF-LF

AUD_SPKRAMP_INL_L

1

5%

402

2

CRITICAL

C6613

0.1UF

1 2

10%
16V

X7R-CERM

402

PLACE C6611/C6612 CLOSE TO PVDD PIN

CRITICAL

C6612

47UF

20%

6.3V

TANT-POLY

CASE-A4

LM48310L_PIN
LM48310L_NIN

CRITICAL

1

C6614

0.1UF

10%
16V

2

X7R-CERM
402

CRITICAL

1

1

C6611

0.001UF

10% 10%
50V

2

2

CERM
402

1
2

4

9

PVDD

U6610

LM48310

IN_P
IN_N

SD*

CRITICAL

GND
8

3
VDD

LLP

SYNC_OUT

SYNC_IN

THRML

PAD

11

OUTA
OUTB

CRITICAL

1

C6610

1UF

10V

2

X5R
402-1

MIN_LINE_WIDTH=0.30 mm

10

7

6
5

U6610_SOUT

PLACE CLOSE TO U6610 PIN6

1

R6602

33

5%
1/16W
MF-LF
402

2

SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT

95

57

95

57

MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L_P_OUT

57

95

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L_N_OUT

57

95

SPEAKER CHECKPOINTS

R6610

0

12

5%
1/16W
MF-LF

402

R6611

0

12

5%
1/16W
MF-LF

402

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRCONN_L_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRCONN_L_N_OUT

7

58 95

OUT

7

58 95

OUT

SPKRAMP_SYNC1

D

C

PP5V_S3_AUDIO_AMP

9

57

L6620

FERR-1000-OHM

54

59

57

AUD_BI_PORT_B_R

IN

AUD_SPKRAMP_SHUTDOWN_L

57

GND_AUDIO_CODEC

56

54

55

1 2

0402

AUD_SPKRAMP_INR_L

CRITICAL

C6623

0.1UF

1 2

10%
16V

X7R-CERM

402

B

PP5V_S3_AUDIO_AMP

9

57

L6630

FERR-1000-OHM

54

A

59

57

AUD_BI_PORT_C_R

IN

AUD_SPKRAMP_SHUTDOWN_L

57

GND_AUDIO_CODEC

56

54

55

1 2

0402

AUD_SPKRAMP_INS_L

CRITICAL

C6633

0.15UF

1 2

10%
10V
X5R
402

PLACE C6621/C6622 CLOSE TO PVDD PIN

CRITICAL

C6622

47UF

20%

6.3V

TANT-POLY

CASE-A4

LM48310R_PIN
LM48310R_NIN

CRITICAL

1

C6624

0.1UF

10%
16V

2

X7R-CERM
402

PLACE C6631/C6632 CLOSE TO PVDD PIN

CRITICAL

C6632

100UF

20%

6.3V
TANT

CASE-AL1

LM48310S_PIN
LM48310S_NIN

CRITICAL

1

C6634

0.15UF

10%
10V

2

X5R
402

CRITICAL

1

1

C6621

0.001UF

10%
50V

2

2

CERM
402

CRITICAL

1

1

C6631

0.001UF

10%
50V

2

2

CERM
402

1

IN_P

2

IN_N

4

SD*

1

IN_P

2

IN_N

4

SD*

9

PVDD

U6620

LM48310

LLP

SYNC_OUT

SYNC_IN

CRITICAL

GND
8

9

PVDD

U6630

LM48310

LLP

SYNC_OUT

SYNC_IN

CRITICAL

GND
8

3
VDD

THRML

PAD

11

3
VDD

THRML

PAD

11

OUTA
OUTB

OUTA
OUTB

MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R_P_OUT

57

CRITICAL

1

C6620

1UF

10%
10V

2

X5R
402-1

10
7

6
5

NOSTUFF

R6603

0

1 2

5%
1/16W
MF-LF

402

SPKRAMP_SYNC1

57

SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT

95

57

95

57

U6620_SOUT

R6604

33

1 2

PLACE CLOSE TO U6620 PIN6

CRITICAL

1

C6630

1UF

10%
10V

2

X5R
402-1

10
7

6
5

NOSTUFF

R6605

1 2

5%
1/16W
MF-LF

402

5%
1/16W
MF-LF

402

0

SPKRAMP_SYNC2

SPKRAMP_SYNC2

57

SPKRAMP_S_P_OUT
SPKRAMP_S_N_OUT

57

95

57

95

57

95

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R_N_OUT

57

95

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRAMP_S_P_OUT

57

95

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MM

SPKRAMP_S_N_OUT

57

95

R6620

0

5%
1/16W
MF-LF

402

R6621

0

5%
1/16W
MF-LF

402

R6630

0

5%
1/16W
MF-LF

402

R6631

0

5%
1/16W
MF-LF

402

12

12

12

12

APPLE INC.

MIN_LINE_WIDTH=0.30 mmMIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRCONN_R_P_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRCONN_R_N_OUT

MIN_LINE_WIDTH=0.30 mm
MIN_NECK_WIDTH=0.20 MM

SPKRCONN_S_P_OUT

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_S_N_OUT

OUT

OUT

OUT

OUT

AUDIO:SPEAKER AMP

SYNC_MASTER=AUDIO

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

7

58 95

7

58 95

7

58 95

7

58 95

SYNC_DATE=07/09/2008

051-7546

SHT

OF

57 96

B

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

AUDIO JACK 1 LO/HP JACK, SPDIF TX

4

3

2 1

D

L6703

R6713

0

R6716

0

1 2

5%
1/16W
MF-LF

402

1 2

5%
1/16W
MF-LF

402

R6711

0

1 2

5%
1/10W
MF-LF

603

R6714

0

1 2

5%
1/16W
MF-LF

402

R6715

0

1 2

5%
1/16W
MF-LF

402

R6710

0

1 2

5%
1/16W
MF-LF

402

CRITICAL

DZ6705

6.8V-100PF

AUD_CONNJ1_SLEEVE2_F

AUD_CONNJ1_SLEEVE_F

AUD_CONNJ1_RING_F

2

402

1

6.8V-100PF

CRITICAL

2

DZ6706

6.8V-100PF

402

1

CRITICAL

DZ6702

402

AUD_CONNJ1_TIPDET_F

AUD_CONNJ1_TIP_F

AUD_CONNJ1_SLEEVEDET_F

2

1

6.8V-100PF

CRITICAL

2

DZ6703

6.8V-100PF

402

1

CRITICAL

DZ6704

2

402

1

1

2

AUD_CONNJ1_SLEEVE2

=PP3V3_S0_AUDIO

59

58

54

8

APN: 514-0607

CRITICAL

AUDIO-JACK-TRANS-M97

J6700

F-RT-TH3

6
5
2
1
3
4

AUD_CONNJ1_SLEEVE

AUD_CONNJ1_RING

AUD_CONNJ1_TIPDET

AUDIO

7

A - VIN

8

B - VCC

9

C

OPERATING VOLTAGE 3.3

C - GND

POF

SHELL

SHIELD

PINS

10
11
12
13

1

2

AUD_CONNJ1_TIP

AUD_CONNJ1_SLEEVEDET

C6700

0.1UF

10%
16V
X5R
402

1

2

C6701

2.2UF

20%

6.3V
CERM
402-LF

FERR-1000-OHM

1 2

FERR-1000-OHM

1 2

FERR-220-OHM-2.5A

1 2

FERR-220-OHM

1 2

FERR-220-OHM

1 2

FERR-1000-OHM

1 2

C6705

100PF

5%
50V
CERM
402

0402

L6702

0402

CRITICAL

L6701

0603

CRITICAL

L6704

0402

CRITICAL

L6706

0402

R6700

10K

1 2

5%
1/16W
MF-LF

402

L6705

0402

GND_CHASSIS_AUDIO_JACK

AUD_SPDIF_OUT

HS_MIC_HI

HS_MIC_LO

AUD_LO_GND

AUD_PORTD_R

AUD_PORTD_L

AUD_J1_SLEEVEDET_R

AUD_J1_TIPDET_R

58

RETURN FOR HF NOISE

R6701

0

402

1 2

5%
1/16W
MF-LF

402

2

1

AUD_CONNJ2_TIP_F

CRITICAL

DZ6755

6.8V-100PF

CRITICAL

2

DZ6754

6.8V-100PF

402

1

402

AUD_SPDIF_IN

L6751

FERR-220-OHM

1 2

0402

L6754

FERR-1000-OHM

1 2

0402

L6756

FERR-1000-OHM

1 2

0402

L6758

FERR-220-OHM

1 2

0402

L6752

2

1

FERR-1000-OHM

1 2

1

C6756

100PF

5%
50V

2

CERM
402

0402

GND_CHASSIS_AUDIO_JACK

AUD_LI_INR

AUD_LI_INL

AUD_J2_COM

AUD_J2_TIPDET_R

XW6701

1 2

58

GND_CHASSIS_AUDIO_JACK

=PP3V3_S0_AUDIO

59

58

54

8

B

APN: 514-0608

CRITICAL

J6750

AUDIO-RCVR-M97

F-RT-TH3

5
2
1
3
4

AUDIO

6

A - VDD

7

B - GND

SHELL

SHIELD

PINS

8

9
10
11
12

C - VOUT

OPERATING VOLTAGE 3.3

POF

AUD_J2_OPT_OUT

1

C6750

0.1UF

10%
16V

2

X5R
402

AUD_CONNJ2_SLEEVE

AUD_CONNJ2_TIPDET

AUD_CONNJ2_RING

AUD_CONNJ2_TIP

AUD_CONNJ2_SLEEVEDET

A

58

R6749

10

1 2

5%
1/16W
MF-LF

402

R6761

0

1 2

5%
1/16W
MF-LF

402

R6764

0

1 2

5%
1/16W
MF-LF

402

R6768

0

1 2

5%
1/16W
MF-LF

402

AUD_CONNJ2_SLEEVE_F

R6762

0

1 2

AUD_CONNJ2_TIPDET_F

5%
1/16W
MF-LF

402

AUD_CONNJ2_RING_F

R6766

0

1 2

5%
1/16W
MF-LF

402

2

1

AUD_CONNJ2_SLEEVEDET_F

CRITICAL

DZ6753

6.8V-100PF

CRITICAL

DZ6752

6.8V-100PF

402

AUDIO JACK 2 LINE IN JACK, SPDIF RX

54

IN

MIC CONNECTOR

D

CRITICAL

J6780

59

OUT

BI_MIC_LO

7

59

OUT

BI_MIC_SHIELD

7

59

OUT

56

OUT

56

BI

56

BI

59

OUT

59

OUT

59

59

7

OUT

BI_MIC_HI

OUT

APN: 518S0520

SPEAKER CONNECTOR

APN: 518S0519

SPKRCONN_L_P_OUT

7

57 95

IN

SPKRCONN_L_N_OUT

7

57 95

IN

78171-0003

M-RT-SM
4

1
2
3

5

CRITICAL

J6781

78171-0002

M-RT-SM

3

1
2

4

C

CRITICAL

J6782

78171-0004

APN: 518S0521

SPKRCONN_S_P_OUT

7

57 95

IN

SPKRCONN_S_N_OUT

7

57 95

IN

SPKRCONN_R_P_OUT

7

57 95

IN

SPKRCONN_R_N_OUT

7

57 95

54

OUT

55

BI

55

BI

SM

AUD_LI_GND

59

OUT

IN

NOSTUFF
CRITICAL

C6781

55

100PF

CERM

50V
402

1

5%

2

CRITICAL

NOSTUFF

CRITICAL

1

C6782

100PF

5%
50V

2

CERM
402

NOSTUFF

C6783

100PF

50V

CERM

402

5%

SYNC_MASTER=AUDIO

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

NOSTUFF
CRITICAL

1

1

C6784

100PF

5%
50V

2

2

CERM
402

AUDIO: JACKS

DRAWING NUMBER

SIZE

D

SCALE

NONE

M-RT-SM

5

1
2
3
4

6

SYNC_DATE=07/09/2008

051-7546

SHT

OF

9658

B

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

NOSTUFF

L6881

PP4V6_AUDIO_ANALOG

59

55

54

FERR-1000-OHM

1 2

0402

VOLTAGE=4.6V
MIN_LINE_WIDTH=0.10 mm
MIN_NECK_WIDTH=0.10 mm

CODEC OUTPUT SIGNAL PATHS

FUNCTION
HP/LINE OUT
SATELLITES

D

SUB
SPDIF OUT

VOLUME
0X0C (12)
0X0D (13)
0X0F (15)
N/A

CONVERTER
0X02 (2)
0X03 (3)
0X05 (05)
0X06 (6)

MIXER(OUTPUT)
0X0C (12)
0X0D (13)
0X0F (15)

PIN COMPLEX
0X14 (20,D)
0X18 (24,B)
0X1A (26,C)
0x1E (SPDIF OUT)

MUTE CONTROL

GPIO_0
VREF_B (100%)
VREF_B (100%)
N/A

DET ASSIGNMENT
0X14 (20,D)
N/A
N/A
0X16 (22,G)

CODEC INPUT SIGNAL PATHS

SSM6N15FEAPE

1

C6801

0.1UF

20%

2

CERM

R6803

100K

1 2

5%
1/16W
MF-LF

402

SSM6N15FEAPE

CONVERTER
0X08 (8)
0X0A (10)
0X07 (7)
0X07 (7)

AUD_OUTJACK_INSERT_L

3

Q6800

SOT563

10V
402

D

5

SG

4

AUD_J1_SLEEVEDET_INV

6

Q6800

SOT563

D

2

SG

1

PIN COMPLEX
0X15 (21,A)
0x1F (SPDIF IN)
0X19 (25,F)
0X1B (27,E)

VREF

VREF_A (50%)
N/A
VREF_F (100%)
MIKEY MIKEY

PORT D DETECT (Line-out)

1

R6806

5.11K

1%
1/16W
MF-LF
402

2

AUD_PORTD_DET_L

3

Q6801

SSM6N15FEAPE

SOT563 SOT563

D

5

SG

4

AUD_J1_SLEEVEDET_R

59

58

DET ASSIGNMENT
0X15 (21,A)
N/A
N/A

Q6801

SSM6N15FEAPE

PORT G DETECT(SPDIF DELEGATE)

1

R6805

10K

1%
1/16W
MF-LF
402

2

AUD_PORTG_DET_L

NC

6

D

2

SG

1

NC

FUNCTION
LINE IN
SPDIF IN
BUILT-IN MIC
HEADSET MIC

AUD_SENSE_B

54

OUT

AUD_SENSE_A

54 59

OUT

PP3V3_S0_AUDIO_F

59

AUD_J1_TIPDET_R

58

C

IN

59

59

GND_AUDIO_CODEC

57

56

55

54

PP3V3_S0_AUDIO_F

59

AUD_J1_SLEEVEDET_R

58 59

IN

GND_AUDIO_CODEC

57

56

55

54

MIXER(INPUT)
0X23 (35)
N/A
0X24 (36)
0X24 (36)

1

R6801

220K

5%
1/16W
MF-LF
402

2

R6802

47K

1 2

5%
1/16W
MF-LF

402

1

R6861

220K

5%
1/16W
MF-LF
402

2

1

C6802

2

AUD_J1_DET_RC

0.01UF

10%
16V
CERM
402

=PP3V3_S0_AUDIO

59

58

54

8

=I2C_MIKEY_SCL

45

IN

=I2C_MIKEY_SDA

45

BI

AUD_I2C_INT_L

21

OUT

AUD_IPHS_SWITCH_EN

9

19

IN

R6890

0

MIKEY

MIKEY

MIKEY

HS_INT_L PULLUP ON MCP PAGE

59

57

56

59

57

56

12

5%

1/16W
MF-LF

402

R6891

12

5%01/16W

MF-LF

402

R6892

0

12

1/16W

5%

MF-LF

402

R6893

0

12

1/16W

5%

MF-LF

402

MIKEY

GND_AUDIO_CODEC

55

54

AUD_BI_PORT_E_L

54

OUT

MAKE_BASE=TRUE

AUD_BI_PORT_E_R

54

OUT

GND_AUDIO_CODEC

55

54

PART#

116S0114

131S1513

132S0045

116S0004

116S0004

116S0004

QTY

PORT E (HEADSET MIC)

MIKEY

L6880

FERR-1000-OHM

1 2

0402

CRITICAL

MIKEY

C6880

6.3V
603

HS_SCL
HS_SDA
HS_INT_L
HS_RST_L

MIKEY

R6880

100K

1/16W
MF-LF

CRITICAL

C6883

XW6880

DESCRIPTION

1

100K 5% 0402 RESISTOR

1

15PF 5% 0402 CAPACITOR

1

100PF 10% 0402 CAPACITOR

1

0 OHMS 5% 0402 RESISTOR

1

0 OHMS 5% 0402 RESISTOR

0 OHMS 5% 0402 RESISTOR

1

10UF

20%
X5R

1

5%

402

2

MIKEY

0.1UF

1 2

10%
25V
X5R
402

SM

1 2

PP3V3_S0_HS_RX

1

2

B3

A3

C3

B2

A2

AVDD

U6880

CD3272A2

WCSP9

SCL

MICBIAS

SDA

INT*

ENABLE

GND

C2

OMIT

1

R6883

100K

5%
1/16W
MF-LF
402

2

REFERENCE DESIGNATOR(S)

MIKEY

B1

A1

DETECT

C1

BYPASS

MIKEY

C6881

0.01UF

16V

10%

402

CERM

OMIT

C6884

15PF

50V

5%

CERM

402

R6883

C6884 MIKEY

C6885

R6883

C6884

C6885

HS_MIC_BIAS
HS_SW_DET
HS_RX_BP

1

MIKEY

2

R6881

10K

1/16W
MF-LF

1

1

C6885

0.001UF

10%

2

2

CERM

BOM OPTION

MIKEY

MIKEY

NOMIKEY

NOMIKEY

NOMIKEY

1%

402

OMIT

D

MIKEY

CRITICAL

1

C6882

4.7UF

20%

6.3V

2

TANT
603-HF

GND_AUDIO_CODEC

MIKEY

1

1

R6882

2.2K

5%
1/16W
MF-LF
402

2

2

50V
402

HS_MIC_HI

HS_MIC_LO

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

TABLE_5_ITEM

IN

IN

59

57

56

55

54

58

C

58

LINE_IN AMP SHUTDOWN CONTROL

PP4V6_AUDIO_ANALOG

59

55

54

PORT A DETECT (Line-in)

AUD_SENSE_A

54 59

OUT

1

B

59

59

58

IN

57

56

55

54

PP3V3_S0_AUDIO_F

AUD_J2_TIPDET_R

GND_AUDIO_CODEC

1

R6811

270K

5%
1/16W
MF-LF
402

2

R6812

47K

1 2

5%
1/16W
MF-LF

402

AUD_J2_DET_RC

A

R6813

39.2K

1%
1/16W
MF-LF

402

2

AUD_INJACK_INSERT_L

3

D

1

G S

2

PLACE L6800/C6800 CLOSE TO Q6800/01/02

=PP3V3_S0_AUDIO

SSM6N15FEAPE

L6800

FERR-1000-OHM

1 2

0402

GND_AUDIO_CODEC

SSM3K15FV

1

C6811

0.1UF

20%

2

CERM

59

58

59

57

Q6802

SOD-VESM-HF

10V
402

54

8

56

55

54

NC

Q6803

SOT563

1

2

3

D

5

SG

4

PP3V3_S0_AUDIO_F

1

C6800

0.1UF

10V

20%

2

402

CERM

R6814

100K

5%
1/16W
MF-LF
402

AUD_LIN_SHUTDOWN

1

R6815

100K

5%
1/16W
MF-LF
402

2

AUD_LIFILT_SHUTDOWN_L

Q6803

SSM6N15FEAPE

SOT563

59

AUD_VREF_PORT_F

54

IN

55

OUT

6

D

2

SG

1

59

59

57

GND_AUDIO_CODEC

57

56

55

54

AUD_BI_PORT_F_L

54

OUT

AUD_BI_PORT_F_R

54

OUT

GND_AUDIO_CODEC

56

55

54

MAKE_BASE=TRUE

GND_CHASSIS_AUDIO_MIC

1

R6851

0

5%
1/16W
MF-LF
402

2

PORT F (BUILT-IN MIC)

R6855

2.2K

1 2

CRITICAL

C6850

XW6850

1 2

XW6851

1 2

5%
1/16W
MF-LF

402

0.1UF

1 2

10%
25V
X5R
402

SM

SM

BI_MIC_BIAS

CRITICAL

1

C6853

10UF

20%
16V

2

TANT-POLY
2012-LLP

BI_MIC_HI_F

1

R6852

100K

5%
1/16W
MF-LF
402

2

BI_MIC_LO_F

C6852

50V
402

R6850

1 2

15PF

CERM

2.2K

5%
1/16W
MF-LF

402

5%

1

2

L6850

FERR-1000-OHM

1

C6851

0.001UF

10%

2

CERM

50V
402

FERR-1000-OHM

1 2

1 2

0402

L6851

0402

BI_MIC_HI

BI_MIC_LO

BI_MIC_SHIELD

AUDIO: JACK TRANSLATORS

SYNC_MASTER=AUDIO

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=07/09/2008

051-7546

SHT

B

7

58

IN

7

58

IN

7

58

IN

A

REV.

A.0.0

OF

9659

8

7 6

5

4

3

2

1

8 7

MagSafe DC Power Jack

6

5

4

3

2 1

CRITICAL

J6900

D

78048-0573

M-RT-SM

1

PWR

2

PWR

3

GND

4

GND

5

SIG

PP18V5_DCIN_FUSE

MIN_LINE_WIDTH=1mm
MIN_NECK_WIDTH=0.20mm
VOLTAGE=18.5V

3

1

2

SC-75

RCLAMP2402B

D6900

CRITICAL

1

C6905

0.01UF

20%
50V

2

CERM
603

ADAPTER_SENSE

The chassis ground will otherwise float and can
send transients onto ADAPTER_SENSE when AC is

C

connected.

CRITICAL

F6905

6AMP-24V

1 2

1206-1

PLACEMENT_NOTE=Place near L6900

<Ra>

1

R6913

100K

5%
1/16W
MF-LF

402

2

ONEWIRE_DCIN_DIV

100K

1/16W
MF-LF

402

<Vth>

1

ONEWIRE_ESD

5%

2

Vth = Vdcin * (Rb / (Ra + Rb))
Vth = Vdcin / 2

1

R6920

24.3K

1%
1/16W
MF-LF
402

2

<Rb>

R6914

1-Wire OverVoltage Protection

PP18V5_DCIN_ONEWIRE

MIN_LINE_WIDTH=0.25mm
MIN_NECK_WIDTH=0.20mm

270K

1/16W
MF-LF

402

5%

402

1

5%

2

SSM6N15FEAPE

1

2

VOLTAGE=18.5V

CRITICAL

Q6915

SOT563

5

SSM6N15FEAPE

C6915

0.1UF

10%
25V
X5R
402

1

2

If ADAPTER_SENSE > Vth
then turn off FET

R6915

CRITICAL

U6915

5

1

3

V+

V-

2

LM397

SOT23-5-HF

4

ONEWIRE_OVERVOLT

R6916

270K

1/16W
MF-LF

Voltage divider from DCIN ensures Q6901
Vgs is met when SYS_ONEWIRE is high or low.
Q6920 used as bilateral switch to ensure
SYS_ONEWIRE doesn’t drive unpowered U6990

Q6910 restricts system load to 10K-70K window until
adapter detects system and enables 16.5V output.

CRITICAL

Q6910

BSS84V

SOT-563

Vgs(max) = 20V

D S

ONEWIRE_EN

3

D

SG

4

CRITICAL

Q6920

SOT563

3

6

1

R6917

270K

5%
1/16W
MF-LF

402

2

Vgs = 11.750V @ 20V DCIN

1

R6918

270K

1/16W
MF-LF

402

1

C6917

0.001UF

10%
50V

2

CERM
402

5

D

S G

SYS_ONEWIRE_BILAT

4

Vgs = 7.63V @ 13V DCIN

5%

2

1

G

2

ONEWIRE_PWR_EN_L_DIV

ONEWIRE_PWR_EN_L

6

D

Q6915

SSM6N15FEAPE

SOT563

2

S G

1

CRITICAL

Q6920

SSM6N15FEAPE

2

SOT563

S G

1

R6911

470K

1/16W
MF-LF

R6912

330K

1/16W
MF-LF

SMC_BC_ACOK_RC

C6910

0.001UF

D

SYS_ONEWIRE

6

=PP18V5_DCIN_CONN

1

5%

402

2

1

5%

402

2

R6910

1 2

1

10%
50V

2

CERM

402

BI

1K

5%
1/16W
MF-LF

402

42 43

SMC_BC_ACOK

60

8

42 43

IN

D

C

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

5

PPVIN_G3H_P3V42G3H

4

6

NC

1

SHDN*

2

NC

3

VIN

BOOST

U6990

LT3470ETS8

TSOT23-8
CRITICAL

GND

4

BIAS

SW

FB

7

8

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

P3V42G3H_FB

P3V42G3H_SW

5

1

2

NC

NC

C6990

10UF

10%
25V

2

X5R
805

Vout = 1.25V * (1 + Ra / Rb)

=PP3V42_G3H_BATT
=SMBUS_BATT_SDA
=SMBUS_BATT_SCL

SMC_BIL_BUTTON_DB_L

1

C6954

0.001UF

CERM

C6953

10%
50V

402

47PF

5%

50V

2

CERM

402

1

2

C6952

47PF

CERM

1

1

5%

50V

2

402

2

C6955

0.001UF

10%
50V
CERM
402

8

45 60

BI

45 60

BI

43

OUT

P3V42G3H_BOOST

C6994

0.22UF

6.3V

1

2

CRITICAL

L6995

33UH

1 2

CDPH4D19FHF-SM

C6995

22pF

5%

50V

CERM

402

=PP3V42_G3H_REG

Vout = 3.425

<Ra>

1

R6995

1

348K

1%
1/16W
MF-LF

2

402

2

<Rb>

1

R6996

200K

1%
1/16W
MF-LF
402

2

200mA max output
(Switcher limit)

1

C6999

22UF

20%

6.3V

2

X5R-CERM
603

8

B

20%
X5R

402

DC-In & Battery Connectors

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=12/06/2007

051-7546

SHT

OF

9660

A

REV.

A.0.0

=PP18V5_DCIN_CONN

60

8

R6905

47

1 2

5%

1/8W

MF-LF

805

PPDCIN_S5_P3V42G3H

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm
VOLTAGE=18.5V

=PPVBAT_G3H_P3V42G3H

8

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

D6905

HN2D01JEAPE

SOT665

1

3

B

CRITICAL

Battery Connector

J6950

BAT-M98

F-RT-SM

10

1
2
3
4
5
6
7
8
9

11

516S0698

PPVBAT_G3H_CONN_F

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm

VOLTAGE=12.6V

=SMBUS_BATT_SCL
=SMBUS_BATT_SDA
SMC_BS_ALRT_L

1

C6950

0.001UF

10%
50V

2

CERM
402

GND_BATT_CHGND

A

L6950

FERR-50-OHM

1 2

SM-LF

1

3

PPVBAT_G3H_CONN

CRITICAL

2

D6950

RCLAMP2402B

SC-75

61

60

45

60

45

43

42

CRITICAL

J6955

78171-0005

M-RT-SM

6

1
2
3
4
5

7

518S0588

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

FROM ADAPTER

=PPDCIN_S5_CHGR

8

2

D7005

1SS418

SOD-723-HF

1

D

C

ACIN pin threshold
is 3.2V, +/- 50mV

Divider sets ACIN
threshold at 13.07V

Input impedance of ~40K meets
sparkitecture requirements

1

R7010

30.1K

1%
1/16W
MF-LF

402

2

1

R7011

9.31K

1%
1/16W
MF-LF

402

B

1

2

R7015

56.2K

1%
1/16W
MF-LF
402

2

CHGR_VCOMP_R

C7015

0.001UF

CHGR_VNEG_R

1

C7016

470PF

10%
50V

2

CERM
402

61

10%
50V

CERM

402

R7016

3.01K

1/16W
MF-LF

8

1%

402

=PP3V42_G3H_CHGR

C7002

=SMBUS_CHGR_SCL

45

IN

=SMBUS_CHGR_SDA

45

BI

VREF = 3.2V, < 300uA

1

2

1

2

CHGR_ACIN

CHGR_ICOMP
CHGR_VCOMP
CHGR_VNEG
CHGR_CSO_P

93

93

CHGR_CSO_N

SIGNAL_MODEL=EMPTY

1

C7050

0.1uF

10%
16V

2

X5R
402

1UF

10%
10V
X5R
402

1

2

61

PP5V1_CHGR_VDD

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

30mA max load

Inrush Limiter

1

R7060

470K

5%
1/16W
MF-LF
402

2

CHGR_AGATE_DIV

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

1

R7061

330K

5%
1/16W
MF-LF
402

2

NC

12
11
10

18
17

4
3

5
7
8

VHST
SCL
SDA

VREF
ACIN

ICOMP
VCOMP
VNEG
CSOP
CSON

VDD

C7060

19

CRITICAL

29

0.1UF

10%
25V
X5R
402

R7001

4.7

1 2

5%
1/16W
MF-LF

402

U7000

QFN

ISL6258A

OMIT

(OD)
20V/V
32V/V

(OD)

THRM_PAD

AGND

26

XW7000

SM

1 2

1

2

(CHGR_AGATE)
(CHGR_DCIN)

20

VDDP

AGATE

CSIP
CSIN

BGATE

DCIN

BOOT
UGATE
PHASE

LGATE

TRKL*

AMON

BMON

ACOK

PGND

6

22

1 2 3

CRITICAL

SOI

S

4

G

5 6 7 8

PP5V1_CHGR_VDDP

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5.1V

1
28
27

16
2

25
24
23

21
13
9
15
14

HAT1128R01HAT1128R01

Q7060

D

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

C7001

1UF

CHGR_AGATE

93

CHGR_CSI_P

93

CHGR_CSI_N
CHGR_BGATE

CHGR_DCIN
CHGR_BOOT

CHGR_UGATE
CHGR_PHASE

CHGR_LGATE
TP_CHGR_TRKL
CHGR_AMON
CHGR_BMON
=CHGR_ACOK

(CHGR_CSO_P)
(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

Reverse-Current Protection

PPDCIN_S5_CHGR_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

1 2 3

CRITICAL

SOI

Q7065

PPDCIN_S5_INRUSH

1

2

1

10%
10V

2

X5R
402 25V

46 61

OUT

46

OUT

43

OUT

S

G

D

5 6 7 8

SIGNAL_MODEL=EMPTY

C7020

0.047UF

10%
16V
CERM
402

1

C7022

0.1UF

10%
25V

2

X5R
402

1

C7035

0.1UF

10%
25V

2

X5R
402

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

Max Current = 8.5A
(L7030 limit)
f = 400 kHz

CHGR_SGATE_DIV

4

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.3 mm

R7021

R7022

1

C7021

0.1UF

10%

2

X5R
402

R7051

1 2

10

1 2

5%
1/16W
MF-LF

402

10

1 2

5%
1/16W
MF-LF

402

4

10

5%
1/16W
MF-LF

402

4

1

R7065

100K

5%
1/16W
MF-LF

402

2

1

R7066

62K

5%
1/16W
MF-LF

402

2

CHGR_CSI_R_P

95

95

CHGR_CSI_R_N

PPDCIN_S5_FET_CHGR

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=18.5V

5

1 2 3

5

CRITICAL

Q7035

1 2 3

R7052

10

1 2

5%
1/16W
MF-LF

402

CHGR_SGATE

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.25 mm

CRITICAL

Q7030

RJK0305DPB

LFPAK-HF

CRITICAL

L7030

3

4.7UH-10.2A

2

FDA1254F-SM

1

RJK0305DPB

LFPAK-HF

152S0542

CHGR_CSO_R_P

95

46

95
46

CHGR_CSO_R_N

U7070

TL331

SOT23-5

CRITICAL

123

R7020

0.02

0.5%
1W
MF
0612

4

CRITICAL

1

C7030

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

1

C7032

1UF

10%
25V

2

X5R
603-1

PPVBAT_G3H_CHGR_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

CRITICAL

R7050

0.01

0.5%
1W
MF

0612

2 1
4 3

5

1

VCC

4

GND

2

NOSTUFF

D7040

1 2

1SS418

SOD-723-HF

CRITICAL

1

C7031

22UF

20%
25V

2

POLY-TANT
CASE-D2-SM

1

C7033

1UF

10%
25V

2

X5R
603-1

1

C7034

1000PF

10%
25V

2

X7R
402

CRITICAL

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

1

C7055

1UF

10%
25V

2

X5R

603-1

1

C7070

0.1uF

10%
16V

2

X5R
402

3

C7040

22UF

POLY-TANT

CASE-D2-SM

1

C7056

0.1UF

10%
16V

2

X5R
402

SGATE_P0V1_VREF

CRITICAL

1

F7040

8AMP-24V

1206

2

1

1

C7041

2

CERM

10%
16V

402

1000PF

2

1

2

20%
25V

C7057

0.01uF

R7070

R7071

10%
25V
X7R
402

57.6K

1/16W
MF-LF

1.82K

1/16W
MF-LF

3
2
1

1

1%

402

2

1

1%

402

2

CRITICAL

HAT1127H

LFPAK-SM

Q7055

S

G

4

3

4

D

S G

D

Q7074

SSM6N15FEAPE

SOT563

5

5

AMON_CLAMP

TO SYSTEM

=PPBUS_G3H

PPVBAT_G3H_FET

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

=PP3V42_G3H_CHGR

1

R7074

1M

5%
1/16W
MF-LF
402

2

CHGR_AMON
R7075 clamps CHGR_AMON when charger is
not powered to counter TL331 bias current.

6

D

S G

1

46

Q7074

SSM6N15FEAPE

SOT563

2

PP5V1_CHGR_VDD

61

8

61

61

8

CRITICAL

HAT1127H

LFPAK-SM

5

Q7056

D

4

60

S

1 2 3

G

PPVBAT_G3H_CONN

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.4 mm
VOLTAGE=12.6V

1

C7058

0.1UF

10%
16V

2

X5R
402

R7056

MF-LF
402
1/16W

1 2

BATT_POS_GATE

R7057

MF-LF
402
1/16W

GND_BATT_CHGND

60

9

1 2

1M

5%

330K

5%

D

C

B

A

PART NUMBER

1

2

8

C7042

0.033UF

10%
16V
X5R
402

QTY

1

IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L

1

DESCRIPTION

IC,ISL6258A,BAT CHARGER,4X4MM,QFN28

1

2

U7000
U7000

1

C7011

0.01UF

10%
16V

2

CERM
402

CRITICAL

CRITICAL353S1811
CRITICAL353S1832

C7005

BOM OPTION

ISL6258

ISL6258A

C7000

1UF

10%
10V
X5R
402

REFERENCE DES

7 6

0.1UF

1

10%
25V

2

X5R
402

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

2S Battery Default
3S Battery Default

1

C7026

0.001UF

10%
50V

2

CERM
402

5

M99 differences from last sync on 12/02/07 to T18 MLB:

1. L7030 changed from T18 MLB inductor to 152S0542.

2. Added Q7056, C7058,R7055,R7056..

3. U7000 Thermal Pad is now connected to GND, not through XW.

4. Q7060 and Q7065 changed to 376S0667.

5. Q7055 and Q7056 changed to 376S0666.

4

3

PBus Supply & Battery Charger

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=12/10/2007

051-7546

SHT

61 96

2

A

REV.

A.0.0

OF

1

2 1

These caps are for Q7102

C7152

1000PF

CRITICAL

0.36UH-30A-1.05MOHM

1 2

PCMC104T-SM

XW7103

1 2

62

IMVP6_VSUM1

R7100

10K

1 2

1%
1/16W
MF-LF

402

1

R7101

3.65K

1%
1/10W
MF-LF
603

2

CRITICAL

0.36UH-30A-1.05MOHM

1 2

PCMC104T-SM

XW7101

1 2

IMVP6_VSUM2

62

R7105

10K

1 2

1%
1/16W
MF-LF

402

1

R7106

3.65K

1%
1/10W
MF-LF
603

2

10%
25V

2

X7R
402

L7100

SM

L7101

SM

C7153

CASE-D2-SM

C7103

0.22UF

1 2

CERM

C7104

0.22UF

1 2

CERM

CRITICAL

1

IMVP6 CPU VCore Regulator

SYNC_MASTER=M87_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

1

1

C7154

22UF

POLY-TANT

20%
25V

1UF

10%
25V

2

2

X5R
603-1

=PPVCORE_S0_CPU_REG

44A MAX CURRENT

XW7104

SM

12

62

IMVP6_VO1

1

R7104

1

5%
1/16W
MF-LF
402

2

10%
10V

402

XW7102

SM

12

IMVP6_VO2

62

1

R7107

1

5%
1/16W
MF-LF
402

2

10%
10V

402

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SIZE

D

SCALE

NONE

8

1000PF

1000PF

10%
25V
X7R
402

10%
25V
X7R
402

1

2

1

2

C7156

C7157

SYNC_DATE=10/17/2007

051-7546

SHT

OF

62 96

D

C

B

A

REV.

A.0.0

5

1 2 3

5

1 2 3

1

C7109

1UF

10%
25V

2

X5R
603-1

4

4

3

5

1 2 3

CRITICAL

Q7101

RJK0328DPB

LFPAK-HF

5

1 2 3

CRITICAL

Q7103

RJK0328DPB

LFPAK-HF

CRITICAL

Q7100

RJK0305DPB

LFPAK-HF

CRITICAL

Q7102

RJK0305DPB

LFPAK-HF

I848I849

CRITICAL

CASE-D2-SM

C7155

22UF

POLY-TANT

1

20%
25V

2

(IMVP6_PHASE1)

(IMVP6_ISEN1)

(IMVP6_PHASE2)

(IMVP6_ISEN2)

(IMVP6_VSUM)
(IMVP6_VO)

8 7

=PPVIN_S5_CPU_IMVP

8

R7120

10

1 2

1%
1/16W
MF-LF

402

=PP5V_S0_CPU_IMVP

8

D

=PP3V3_S0_IMVP

8

13 12 11 10

C

=PP1V05_S0_CPU

8

6

PM_DPRSLPVR

21 87

IN

CPU_PROCHOT_L

10 14 43 87

OUT

LAYOUT NOTE:
Place R7126 in hot
spot of reg circuit.

CRITICAL

R7126

470K

402

R7119

(IMVP6_NTC)

1

2

499

1 2

1%
1/16W
MF-LF

402

C7110

0.01uF

R7112

10

1 2

1/16W
MF-LF

402

R7121

10

1 2

1/16W
MF-LF

402

R7198

1 2

1/16W
MF-LF

402

10%
16V

CERM

402

1%

1%

0

5%

1

2

IMVP6_NTC_R

1

R7127

4.02K

1%
1/16W
MF-LF

C7105

0.015UF

1

R7108

1

147K

2

1

2

1%
1/16W
MF-LF
402

2

C7106

0.001UF

10%
50V
CERM
402

10%
16V
X7R
402

402

2

R7113

IMVP6_VDIFF_RC

1

1

402

R7109

1K

1%

1%

1/16W
MF-LF
402

2

2

R7111

255

1/16W
MF-LF

(IMVP6_FB)

B

1

C7114

470PF

10%
50V

2

CERM
402

IMVP6_COMP_RC

R7160

0

IMVP_VR_ON

42 62

IMVP6_OCSET

A

62

IMVP6_VO

62

IMVP6_DROOP

62

IMVP6_DFB

62

IMVP6_SOFT

62

IMVP6_RBIAS

62

IMVP6_VDIFF

62

IMVP6_FB2

62

IMVP6_FB

62

IMVP6_COMP

62

IMVP6_VW

62

1 2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM
MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

5%
1/16W
MF-LF

402

IMVP_VR_ON_R

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=12.6V

PP5V_S0_IMVP6_VDD

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

PP3V3_S0_IMVP6_3V3

MIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

R7199

68

5%
1/16W
MF-LF
402

2

1

1K

1%
1/16W
MF-LF

402

2

C7113

220PF

10%
50V

X7R-CERM

402

1

R7114

97.6K

1%
1/16W
MF-LF

402

2

MIN_NECK_WIDTH=0.20 MM
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

9

87

9

87

9

87

9

87

9

87

9

87

9

87

9

10 14 87

10

46

9

62

26

1

2

IMVP6_VID<6>

IN

IMVP6_VID<5>

IN

IMVP6_VID<4>

IN

IMVP6_VID<3>

IN

IMVP6_VID<2>

IN

IMVP6_VID<1>

IN

IMVP6_VID<0>

IN

CPU_DPRSTP_L

IN

IMVP_DPRSLPVR

87

CPU_PSI_L

IN

IMVP6_IMON

OUT

VR_PWRGD_CLKEN_L

OUT

IMVP_VR_ON_R

IN

VR_PWRGOOD_DELAY

OUT

IMVP6_VR_TT_L
IMVP6_NTC
(GND_IMVP6_SGND)
IMVP6_SOFT

62

IMVP6_RBIAS

62

(GND_IMVP6_SGND)
IMVP6_VDIFF

62

62

IMVP6_FB2
IMVP6_FB

62

IMVP6_COMP

62

62

IMVP6_VW

(IMVP6_VW)

C7107

0.001UF

CERM

(IMVP6_COMP)

C7126

C7130

0.1uF

1

10%
50V

2

402

C7196

0.1UF

1UF

10%
10V
X5R
402

1

10%
16V

2

X5R
402

1

R7110

6.81K

1%
1/16W
MF-LF
402

2

10%
16V
X5R
402

1

2

1

2

62

62

62

62

62

62

62

62

6

1

R7197

10K

5%
1/16W
MF-LF
402

2

43
42
41
40
39
38
37

46
45

2
3

48
47
44

1
5
6

7

4

13

12
11
10

9

25

GND_IMVP6_SGND

MIN_LINE_WIDTH=0.50 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=0V

IMVP6_PHASE1
IMVP6_BOOT1
IMVP6_UGATE1
IMVP6_LGATE1
IMVP6_ISEN1
IMVP6_VSUM1
IMVP6_VO1
IMVP6_VSEN_P

VIN VDD

VID6
VID5
VID4
VID3
VID2
VID1
VID0

DPRSTP*
DPRSLPVR
PSI*
IMON

3V3
CLK_EN*
VR_ON
PGOOD
VR_TT*
NTC

SOFT

RBIAS

VDIFF

FB2
FB
COMP
VW

NC

XW7100

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM
MIN_LINE_WIDTH=0.25 MM

U7100

(PGD_IN)
(ISL9504A)

1 2

PVCC

QFN

UGATE1

PHASE1

LGATE1

ISL9504BCRZ

UGATE2

PHASE2

LGATE2

TPAD

GND

21

SM

31

22

20

BOOT1
BOOT2

PGND1

ISEN1

PGND2

ISEN2

VSUM

OCSET

DROOP

VSEN

DFB

RTN

49

1

C7135

2

VO

C7121

0.22UF

DPRSLPVR

4.7UF

20%

6.3V
X5R-CERM
402

36

IMVP6_BOOT1

62

26

IMVP6_BOOT2

62

35

IMVP6_UGATE1

62

34

62

IMVP6_PHASE1

32

IMVP6_LGATE1

62

33

(GND)

24

62

IMVP6_ISEN1

27

IMVP6_UGATE2

62

28

IMVP6_PHASE2

62

30

IMVP6_LGATE2

62

29

(GND)

23

IMVP6_ISEN2

62

19

IMVP6_VSUM

8

IMVP6_OCSET

62

18

IMVP6_VO

16

IMVP6_DROOP

17

IMVP6_DFB

62

14
15

SIGNAL_MODEL=EMPTY

1

20%

6.3V

2

X5R
402

MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=1.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

5

DPRSTP*
0 1
0
1
1

0.01UF

CERM

0.01uF

CERM

1

10%
16V

2

402

87

87

1

10%
16V

2

402

C7131

C7133

1
0
0

C7127

0.22UF

R7117

3.92K

1 2

1

R7118

1K

1%
1/16W
MF-LF
402

2

1

2

IMVP6_VSEN_P

62

IMVP6_VSEN_N

62

NO STUFF

1

C7132

0.01uF

10%
16V

2

CERM
402

Operation

PSI*

2-Phase

1

1-Phase

0

1-Phase

1
0

1-Phase

1

1

C7115

0.22UF

2

6.3V

10%

402

2

1

C7129

180pF

5%
50V

2

CERM
402

1

2

20%
25V
X5R
603

OUT
OUT

1

R7115

11K

1%
1/16W
MF-LF
402

2

20%
25V
X5R
603

1%
1/16W
MF-LF

402

C7134

0.068UF

10%

10V

CERM

402

C7128

0.22UF

CERM-X5R

Place R7131 Between L7100,L7101 and CPU

R7122

0

1 2

5%
1/16W
MF-LF

402

IMVP6_PHASE2

62

IMVP6_BOOT2

62

IMVP6_UGATE2

62

IMVP6_LGATE2

62

IMVP6_ISEN2

62

IMVP6_VSUM2

62

IMVP6_VO2

62

IMVP6_VSEN_N

87 87

62

62

62

1

2

4

Mode

CCM
CCM
DCM
DCM

NO STUFF

C7116

0.001uF

10%
50V

CERM

402

1

R7116

13.3K

1%
1/16W
MF-LF
402

2

(IMVP6_VO)

R7130

2.61K

1/16W
MF-LF

IMVP6_VO_R

CRITICAL

R7131

10KOHM-5%

0603-LF

R7123

0

1 2

5%
1/16W
MF-LF

402

MIN_LINE_WIDTH=1.5 MM
MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

These caps are for Q7100

1

C7108

1000PF

10%
25V

2

X7R
402

1

2

1

1%

402

2

CPU_VCCSENSE_P

CPU_VCCSENSE_N

CRITICAL

CASE-D2-SM

1

C7117

22UF

20%
25V

2

POLY-TANT

4

4

11 87

IN

11 87

IN

MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MMMIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM
MIN_NECK_WIDTH=0.2 MM

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

=PPVIN_S5_P5VP3V3

8

R7264

0

12

CRITICAL

C7240

22UF

POLY-TANT

CASE-D2-SM

f=365KHz f=460KHz

=PP5V_S3_REG

C

Vout = 5.0V

8 8

6A max output
(Q7220 limit)

CRITICAL

1

C7252

330UF

20%

6.3V

2

POLY-TANT

CASE-D3L-SM1

PLACEMENT_NOTE=Place XW7220 next to L7220.

PP5V_S5_REG_XW

B

C7250

10UF

1

20%
10V

2

X5R
805

PART NUMBER

376S0651

376S0652

2

XW7220

SM

1

PATH=I623

1

R7220

15K

5%
1/16W
MF-LF
402

2

1

R7221

10K

1%
1/16W
MF-LF
402

2

1

20%
25V

2

CRITICAL

Q7220

RJK0305DPB

LFPAK-HF

CRITICAL

L7220

2.2UH-14A

1 2
IHLP2525CZ-SM1

NO STUFF

R7222

10

5%
1/16W
MF-LF

402

ALTERNATE FOR
PART NUMBER

376S0668

376S0669

152S0693152S0778

1

C7241

1UF

10%
25V

2

X5R
603-1

1

RJK0301DPB

2

P5VS5_RC

NO STUFF

C7222

100PF

50V

CERM

402

BOM OPTION

CRITICAL

Q7225

1

5%

2

5

123

LFPAK-HF

P5VS5_VBST_R

4

REF DES

ALL

ALL

ALL

R7224

0

5%

1

2

1/16W
MF-LF

C7224

0.1UF

10%
50V
X7R
603-1

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

5

402

4

123

COMMENTS:

FET FDM8678S alternate to Si7108

FET FDM8676 alternate to Si7110

4.7uH inductor Cyntec a;ternate to MagLayers

12

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

68

1

C7200

1UF

10%
25V

2

X5R

603-1

P5VS5_VBST

P5VS5_DRVH

GATE_NODE=TRUE

P5VS5_LL

SWITCH_NODE=TRUE

P5VS5_DRVL

GATE_NODE=TRUE

(P5VS5_VO1)

P5VS5_VFB

P5VS5_ENTRIP

1

R7200

75K

1%
1/16W
MF-LF
402

2

GND_P5VP3V3_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

One master PGOOD for both 5V and 3V3

P5V3V3_PGOOD

68

OUT

Q7210

=PP3V42_G3H_PWRCTL

68

8

Q7210

SSM6N15FEAPE

SOT563

5

SSM6N15FEAPE

D

SG

1

R7210

10K

5%
1/16W
MF-LF
402

2

P5VS3_EN_L

3

4

SOT563

=P5VS3_EN

PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15.

2

P5VP3V3_VREG5

P5VP3V3_VREF

VIN

14

SKIPSEL

4

TONSEL

22 9

VBST1

TPS51125

21 10

DRVH1

20 11

LL1

19 12

DRVL1

24 7

VO1

2 5

VFB1

1 6

ENTRIP1

GND

6

D

SG

1

16

U7201

15

VREF

QFN

THRM_PAD

68

3

8

VREG3

17

VREG5

VBST2

DRVH2

LL2

DRVL2

VO2

VFB2

ENTRIP2

18

VCLK

23

PGOOD

13

EN0

25

XW7200

SM

1 2

Q7211

SSM6N15FEAPE

P3V3S5_EN_L

SOT563

C7201

0.22UF

5

P5VP3V3_VREG3

1

1

C7205

10UF

20%

6.3V

2

2

X5R
603

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

10%
10V

CERM

402

C7203

10UF

6.3V

1

2

P3V3S5_VBST

P3V3S5_DRVH

GATE_NODE=TRUE

P3V3S5_LL

SWITCH_NODE=TRUE

P3V3S5_DRVL

GATE_NODE=TRUE

(P3V3S5_V02)

20%
X5R

603

P3V3S5_VFB

P3V3S5_ENTRIP

NO STUFF

1

C7208

220PF

5%
25V

2

CERM
402

3

D

SG

4

M99 differences from last sync on 11/01/07 to M88 MLB:

1. L7260 changed from M88 MLB inductors to 152S0693.

2. Q7220 changed to 372S0512. Q7225 changed to 376S0511.

3. U7200 changed to 353S2087.

4. Added R7200, R7220,R7221, R7260,R7261, C7201.

1

R7206

75K

1%
1/16W
MF-LF
402

2

1/16W
MF-LF

402

5%

P3V3S5_VBST_R

1

C7264

0.1UF

10%
50V

2

X7R

603-1

CRITICAL

FDMS9600S

A

Q7260

1

8

MLP

CRITICAL

C7280

POLY-TANT

CASE-D2-SM

Q1

Q2

7

22UF

56

20%
25V

2349

10

SW

1

2

NO STUFF

R7262

1/16W
MF-LF

NO STUFF

C7262

100PF

50V

CERM

402

10

5%

402

5%

1

C7281

1UF

10%
25V

2

X5R
603-1

1

2

P3V3S5_RC

1

2

APPLE INC.

CRITICAL

L7260

4.7UH-5.5A

1 2

IHLP2525CZ

2

XW7260

SM

1

PLACEMENT_NOTE=Place XW7260 next to L7260.

PATH=I621

1

R7260

6.49K

1%
1/16W
MF-LF
402

2

1

R7261

10K

1%
1/16W
MF-LF
402

2

PP3V3_S5_REG_XW

5V / 3.3V Power Supply

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

.

DRAWING NUMBER

D

SCALE

NONE

=PP3V3_S5_REG

Vout = 3.3V

5.5A max output
(L7260 limit)

1

C7290

10UF

20%

6.3V

2

X5R
603

SYNC_DATE=01/09/2008

051-7546

SHT

63 96

OF

CRITICAL

1

C7292

150UF

20%

6.3V

2

POLY-TANT
CASE-B2-SM

REV.

D

C

B

A

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

=PPVIN_S0_DDRREG_LDO

8

=PPVIN_S3_DDRREG

1

C7355

10UF

20%

6.3V

2

X5R
603

6.3V
CERM

20%

603

R7305

1 2

1

C7305

2

C7350

0.033UF

4.7

5%
1/16W
MF-LF

402

10%
16V
X5R
402

1UF

10%
10V
X5R
402

1

2

NC
NC

1

2

PP5V_S3_DDRREG_V5FILT

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=5V

15

V5IN

6

COMP

10

S3

VTT Enable

11

S5

VDDQ/VTTREF Enable

13

PGOOD

VDDQ PGOOD

5

VTTREF

24

VTT

2

VTTSNS

7

NC0

12

NC1

VTTGND

THRM_PAD

1

25

14

CRITICAL

U7300

TPS51116

QFN

SYM (2 OF 2)

GND

3

XW7300

23

VLDOINV5FILT

8

VDDQSNS

4

MODE

22

VBST

21

DRVH

20

LL

19

DRVL

16

CS

9

VDDQSET

CS_GND

PGND

17

18

2

SM

1

=PP5V_S3_DDRREG

8

C7300

4.7UF

C

=DDRVTT_EN

9

69

IN

=DDRREG_EN

68

IN

DDRREG_PGOOD

68

OUT

=PPVTT_S3_DDR_BUF

27 8 8

=PPVTT_S0_DDR_LDO

8

MIN_LINE_WIDTH=2 mm

MIN_NECK_WIDTH=0.2 mm

CRITICAL

C7360

22UF

20%

6.3V

X5R-CERM

603

1

2

XW7360

SM

1 2

CRITICAL

1

C7361

22UF

20%

6.3V

2

X5R-CERM
603

10mA max load
Vout = VDDQSNS/2

Vout = VTTREF

DDRREG_VTTSNS

B

GND_DDRREG_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

8

DDRREG_VDDQSNS

R7310

DDRREG_VBST

DDRREG_DRVH

GATE_NODE=TRUE

DDRREG_LL

SWITCH_NODE=TRUE

DDRREG_DRVL

GATE_NODE=TRUE

DDRREG_CS

DDRREG_FB

DDRREG_CSGND

10K

1/16W
MF-LF

402

CRITICAL

1

1%

2

C7330

POLY-TANT

CASE-D2-SM

CRITICAL

1

22UF

PLACEMENT_NOTE=Place next to Q7335

C7331

20%
25V

2

POLY-TANT

CASE-D2-SM

(DDRREG_DRVH)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_VBST)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_LL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_DRVL)

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_CSGND)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_VDDQSNS)

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm

(DDRREG_FB)

22UF

1

1

C7332

1UF

20%
25V

10%
25V

2

2

X5R
603-1

1

C7333

1000PF

10%
25V

2

X7R
402

5

CRITICAL

Q7330

RJK0305DPB

LFPAK-HF

CRITICAL

1 2 3

L7330

1.0UH-13A-5.6MOHM

1 2

PCMB065T-SM

CRITICAL

Q7335

RJK0301DPB

LFPAK-HF

CRITICAL

1

C7340

330UF

20%

2.5V

2

POLY-TANT
CASE-C2-SM

CRITICAL

C7341

330UF

POLY-TANT

CASE-C2-SM

2.5V

20%

Vout = 0.75V * (1 + Ra / Rb)

=PPDDR_S3_REG
Vout = 1.50V or 1.80V
15A max output
(Q7335 limit)
f = 400 kHz

1

1

C7345

10UF

20%

6.3V

2

2

X5R
603

NO STUFF

C7320

100PF

CERM

50V
402

1

5%

2

1

C7346

1000PF

10%
25V

2

X7R
402

1

R7320

15.0K

1%
1/16W
MF-LF
402

2

<Ra>

1

R7321

15.0K

1%
1/16W
MF-LF
402

2

<Rb>

2

XW7345

SM

PLACEMENT_NOTE=Place next to C7345

1

C7325

0.1UF

1 2

10%
50V
X7R

603-1

4

4

XW7335

SM

1 2

5

1 2 3

D

C

B

1.5V DDR3 Supply

A

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=12/13/2007

051-7546

SHT

OF

9664

1

A

REV.

A.0.0

2 1

1

1

C7561

1UF

10%
25V

2

2

X5R
603-1

R5425

0.001

1%
1W
MF

1206

PPMCPCORE_ISENSE

MCPCOREISNS_P

MCPCOREISNS_N

95

47

MCP_PROD

1

R7582

110K

0.1%
1/16W
MF
402

2

MCP_VID2_LMCP_VID0_L

Q7582

SOT563

1 2
3 4

3

D

5

SG

4

C7566

10UF

1

C7567

10UF

20%
4V

2

X5R
603

Vout = See below

=PPMCPCORE_S0_REG

Max Current: 25A?

1

(Q7560 Limit)

20%

4V

2

X5R

f = 300 kHz

603

CRITICAL

1

C7565

330UF

20%

2.5V

2

POLY-TANT
CASE-C2-SM

1

2

C7569

1000PF

10%
25V
X7R
402

8

CRITICAL

1

C7568

330UF

20%

2.5V

2

POLY-TANT
CASE-C2-SM

D

C

B

C7564

0.22UF

CERM-X7R

MCP_PROD

1

R7580

475K

0.1%
1/16W
MF
402

2

Q7580

SOT563

3

<Rc>

5

10V
603

5%

D

SG

1

C7563

1000PF

10%
25V

2

X7R
402

4

1

2

4

3

SSM6N15FEAPE

4

CRITICAL

5

CASE-D2-SM

CRITICAL

Q7560

RJK0305DPB

LFPAK-HF

1 2 3

CRITICAL

L7560

0.6UH-30A-1.5MOHM

1 2

MPL104-SM

5

CRITICAL

Q7565

RJK0328DPB

1 2 3

MCP_PROD

1

R7581

237K

0.1%
1/16W
MF
402

2

MCP_VID1_L

Q7580

SOT563

2

C7560

22UF

POLY-TANT

95

LFPAK-HF

6

D

SG

1

20%
25V

47

SSM6N15FEAPE

8 7

=PPVIN_S0_P5VRTS0_MCPCORE

8

CRITICAL

D

POLY-TANT

CASE-D2-SM

=PP5V_RT_REG

8

Vout = 5.03V

C

5A max output

(Q7510 limit?)

f = 400 kHz

CRITICAL

1

C7515

330UF

20%

6.3V

2

POLY-TANT

CASE-D3L-SM1

B

C7510

22UF

20%
25V

1 2

1

C7516

10UF

20%
10V

2

X5R
805

1

1

2

CRITICAL

L7510

2.2UH-14A

IHLP2525CZ-SM1

C7511

1UF

10%
25V

CRITICAL

2

X5R
603-1

Q7510

SI7110DN

PWRPK-1212-8-HF

CRITICAL

Q7511

SI7108DN

PWRPK-1212-8-HF

5

D

G

S

123

5

D

G

S

123

(=PP5V_RTS0_REG)

2

XW7516

SM

PLACEMENT_NOTE=Place next to C7516

1

P5VRTS0_VSNS

NO STUFF

1

R7520

61.9K

1%
1/16W
MF-LF
402

2

<Ra>

1

R7521

0

5%
1/16W
MF-LF
402

2

<Rb>

NO STUFF

C7520

100PF

CERM

50V
402

5%

Vout = 0.7V * (1 + Ra / Rb)

=P5V_RTS0_EN

68

IN

MCPCORES0_PGOOD

68

OUT

P5V_RTS0_PGOOD

68

OUT

=MCPCORES0_EN

68

IN

4

(P5VRTS0_UGATE)

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

(P5VRTS0_LGATE)

4

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

(P5VRTS0_BOOT)

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

1

C7514

0.22UF

10%
16V

2

X7R
603

(P5VRTS0_PHASE)

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

1

2

6

1

R7500

4.7

5%
1/16W
MF-LF

402

2

PVIN_P5VRTS0_MCPCORE

1

C7500

10UF

10%
25V

2

X5R
805

P5VRTS0_BOOT
P5VRTS0_UGATE
P5VRTS0_PHASE

P5VRTS0_LGATE

(=P5V_RTS0_EN)

P5V_RTS0_FB
P5V_RTS0_ILIM

1

R7514

100K

1%
1/16W
MF-LF
402

2

5

1

C7501

1UF

10%
10V

2

X5R

402-1

PVCC

VIN

17 24

BOOT1

9

4

2

UGATE1
PHASE1
LGATE1
OUT1
EN1
BYP
FB1
ILIM1
SKIP*
EN_LDO
SECFB
TON

THRM_PAD

CRITICAL

33

15 26
16 25
18 23
10 30
14 27

11
12 31
29

20

(Internal 10-ohm path

from PVCC to VCC)

PP5V_S0_MCPREG_VCC

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

PP3V3_S0_MCP_VREF

19

365

VCC

VREF3

LDOREFIN

BOOT2

QFN

GND

UGATE2
PHASE2
LGATE2

REFIN2

ILIM2

PGND

21

22

U7500

ISL6236

XW7500

1 2

OUT2

POK1
POK2

SM

LDO

EN2

REF

C7504

1UF

402-1

7
8

32

1
13
28

1

10%
10V

2

X5R

Max load 100mA

PP5V_S0_MCPREG_LDO

(SGND)

MCPCORES0_BOOT
MCPCORES0_UGATE
MCPCORES0_PHASE
MCPCORES0_LGATE

(=PPMCPCORE_S0_REG)

MCPCORES0_REFIN
MCPCORES0_ILIM

PP2V_S0_MCPREG_REF

VOLTAGE=2V

Max load 50uA

1

C7530

0.1UF

20%
10V

2

CERM
402

GND_MCPREG_SGND

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=0V

Vout = 2.0V * Req / (Ra + Req)
Req = Rb || Rc || Rd || Re

4

C7503

VOLTAGE=5V

R7564

100K

1/16W
MF-LF

1UF

402-1

1%

402

10%
10V
X5R

1

2

(MCPCORES0_UGATE)

1

1

C7502

4.7UF

20%

2

6.3V

2

X5R-CERM
402

MCP_PROD

R7570

48.7K

0.1%

1/16W

MF

402

<Ra>

MCP_PROD

R7571

54.9K

0.1%

1/16W

MF

402

<Rb> <Re><Rd>

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE

1

2

1

1

C7590

0.01UF

10%
16V

2

CERM
402

2

(MCPCORES0_PHASE)

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
SWITCH_NODE=TRUE

(MCPCORES0_LGATE)

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
GATE_NODE=TRUE

SSM6N15FEAPE

MCP_VID<0>

21

IN

MCP_VID<1>

21

IN

MCP_VID<2>

21

IN

MCP79 Rev A01 requires higher core & analog voltage

PART NUMBER

114S0382
114S0400
114S0482
114S0453
114S0422
114S0373
114S0404

A

114S0458
114S0447
114S0411

8

7 6

QTY

1
1
1
1
1
1
1
1
1
1

DESCRIPTION

RES,MTL FILM,1/16W,48.7K,1,0402,SMD,LF

RES,MTL FILM,1/16W,76.8K,1,0402,SMD,LF

RES,MTL FILM,1/16W,523K,1,0402,SMD,LF

RES,MTL FILM,1/16W,267K,1,0402,SMD,LF

RES,MTL FILM,1/16W,130K,1,0402,SMD,LF

RES,MTL FILM,1/16W,40.2K,1,0402,SMD,LF

RES,MTL FILM,1/16W,84.5K,1,0402,SMD,LF

RES,MTL FILM,1/16W,301K,1,0402,SMD,LF

RES,MTL FILM,1/16W,237K,1,0402,SMD,LF

RES,MTL FILM,1/16W,100K,1,0402,SMD,LF

REFERENCE DES

R7570
R7571
R7580
R7581
R7582
R7570
R7571
R7580
R7581
R7582

CRITICAL

BOM OPTION

MCP_A01
MCP_A01
MCP_A01
MCP_A01

MCP_A01
MCP_A01Q
MCP_A01Q
MCP_A01Q
MCP_A01Q
MCP_A01Q

5

Rev A01 Production
VID<2:0> Voltage Voltage MCP Target

000 +1.224V +1.060V +1.05V
001 +1.159V +0.994V +1.00V
010 +1.101V +0.937V +0.95V
011 +1.049V +0.885V +0.90V
100 +0.995V +0.830V +0.85V
101 +0.952V +0.789V +0.80V
110 +0.913V +0.752V +0.75V
111 +0.876V +0.719V +0.70V

4

1.05V / MCP Core Regulator

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=01/08/2008

051-7546

SHT

OF

65 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

=PPVIN_S0_CPUVTTS0

8

CRITICAL

C7690

22UF

20%
25V

POLY-TANT

CASE-D2-SM

=PP5V_S0_CPUVTTS0

8

R7601

200

1 2

C

B

PP5V_S0_CPUVTTS0_V5FILT

MIN_LINE_WIDTH=0.6 mm

1%

MIN_NECK_WIDTH=0.2 mm

1/16W

VOLTAGE=5V

MF-LF

402

68

IN

68

OUT

C7601

2.2UF

CPUVTTS0_PGOOD

(=PPCPUVTT_S0_REG)

CPUVTTS0_VFB
CPUVTTS0_TRIP

1

R7685

6.34K

1%
1/16W
MF-LF
402

2

10%
16V
X5R
603

1

2

TPS51117RGY_QFN14

1

EN_PSV

6

PGOOD

3

VOUT

5

VFB

11

TRIP

GND

4

V5FILT

CRITICAL

U7600

SYM (2 OF 2)

THRM_PAD

7

XW7600

QFN

15

SM

1 2

V5DRV

10

PGND

VBST

DRVH

DRVL

8

TON

1

C7600

1UF

10%
10V

2

X5R
402

CPUVTTS0_TON=CPUVTTS0_EN

2

CPUVTTS0_VBST

14

CPUVTTS0_DRVH

13

GATE_NODE=TRUE

CPUVTTS0_LL

12

LL

SWITCH_NODE=TRUE

CPUVTTS0_DRVL

9

GATE_NODE=TRUE

(GND)

GND_CPUVTTS0_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

(CPUVTTS0_VFB)
(=PPCPUVTT_S0_REG)

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

1

2

C7680

1

C7695

1UF

2

R7679

0.1UF

603-1

10%
25V
X5R
603-1

165K

10%
50V
X7R

1/16W
MF-LF

1%

402

1

2

CRITICAL

Q7660

FDMS9600S

1

2

MLP

1

8

2349

Q1

Q2

7

56

Vout = 0.75V * (1 + Ra / Rb)

CRITICAL

2.2UH-14A

10

1 2

SW

IHLP2525CZ-SM1

CPUVTTS0_VSNS

1

R7670

8.06K

1%
1/16W
MF-LF
402

2

<Ra>

1

R7671

20.0K

1%
1/16W
MF-LF
402

2

<Rb>

L7660

NO STUFF

C7670

100PF

50V

CERM

402

5%

R5435

0.002

1%

1/4W

MF

PPCPUFSB_ISNS

1V05CPU_P

95

47

1V05CPU_N

95

47

1206

1 2
3 4

XW7665

PLACEMENT_NOTE=Place XW7665 next to C7665

1

2

=PPCPUVTT_S0_REG

1

C7665

10UF

20%

6.3V

2

X5R
603

CRITICAL

C7660

2

SM

1

330UF

POLY-TANT

B2-SM

2.0V

Vout = 1.052V
6A max output
(Q7660 limit?)
f = 360 kHz

1

20%

2

8

D

C

B

CPU VTT Power Supply

A

M99 differences from last sync on 12/03/07 to T18 MLB:

1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=12/14/2007

051-7546

SHT

OF

66 96

1

A

REV.

A.0.0

8 7

6

1.8V S0 Switcher / 1.0VFW SWITCHER

S5 power required for output discharge feature

5

4

3

2 1

D

=PP3V3_S3_P1V8S0

8

2.2UF

6.3V
CERM

402-LF

1

20%

2

3

VIN

U7700

DFN-HF

PAD

LTC3547

9

GND

RUN1
RUN2

5

SW1

SW2

1

VFB1

8

VFB2

THRML

CRITICAL

P1V0FW_SW

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

4

6

2
7

P1V0FW_VFB

P1V8S0_LX

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

C7700

C

P1V8S0_VFB

=P1V8S0_EN

68

IN

=PP3V3_FW_P1V0FW

8

Vout = 0.6V * (1 + Ra/Rb)

MCP 1.05V AUXC Supply

R7751

4.7

B

=PPVIN_S0_P1V05S5

67

8

1

C7752

1UF

10%
25V

2

X5R
603-1

1 2

MIN_LINE_WIDTH=0.6 mm

5%

MIN_NECK_WIDTH=0.2 mm

1/16W

VOLTAGE=5V

MF-LF

402

P5V_P1V05S5

P1V05_S5_FSET

1

C7753

0.01UF

10%
16V

CERM

402

R7752

38.3K

1%

1

1/16W
MF-LF
402

2

2

P1V05_S5_COMP

1

R7753

49.9K

2

1%
1/16W
MF-LF
402

C7755

33PF

CERM

50V
402

1

5%

2

68

IN

68

OUT

=P1V05S5_EN

P1V05_S5_PGOOD

P1V05S5_VFB

P1V05S5_COMP_R

1

C7754

470PF

10%
50V

2

CERM

A

402

P5V_P1V05S5_V5FILT

1

C7751

2.2UF

10%
16V

2

X5R
603

16

1

7

4
3

5

6

8

VIN

FSET

EN
FCCM
PGOOD

COMP

FB

VO

12

PVCC

U7750

ISL6269

QFN

THRML

PAD

17

2

XW7750

SM

1

2
VCC

BOOT

PHASE

ISEN

PGND

14

UG

13
15
9

11

LG

10

1

C7750

2.2UF

10%
16V

2

X5R
603

P1V05S5_DRVH

GATE_NODE=TRUE

P1V05S5_VBST
P1V05S5_LL

SWITCH_NODE=TRUE

P1V05S5_DRVL

GATE_NODE=TRUE

GND_P1V05S5_SGND

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0V

(P1V05S5_VFB)
(=PP1V05_S5_REG)

CRITICAL

L7780

2.2UH

1 2

CPL2512-SM

C7782

CRITICAL

L7700

2.2UH

1 2

CPL2512-SM

C7701

=PPVIN_S0_P1V05S5

67

8

<Ra>

1

R7782

1

10PF

10PF

50V

CERM

402

50V

CERM

402

5%

187K

5%

1%
1/16W
MF-LF

2

402

2

<Rb>

1

R7783

280K

1%
1/16W
MF-LF
402

2

1

2

P1V05S5_ISEN

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

(GND)

<Ra>

1

R7700

562K

1%
1/16W
MF-LF
402

2

<Rb>

1

R7701

280K

1%
1/16W
MF-LF
402

2

C7770

0.1UF

=PP1V0_FW_REG

8

Vout = 1.001V
300mA max output
(Switcher limit)
f = 2.25 MHz

1

C7785

4.7UF

20%
4V

2

X5R
402

=PP1V8_S0_REG

8

Vout = 1.816V

0.3A max output
(Switcher limit)
f = 1.6 MHz

1

C7705

4.7UF

20%
4V

2

X5R
402

1

C7775

1UF

10%
25V

2

X5R
603-1

R7779

2.43K

1/16W
MF-LF

10%
25V
X5R
402

1

1%

402

2

1

2

5

CRITICAL

D

S

1 2 3

5

D

S

1 2 3

Q7770

CRITICAL

Q7771

4

G

4

G

Vout = 0.6V * (1 + Ra / Rb)

SI7110DN

PWRPK-1212-8-HF

SI7108DN

PWRPK-1212-8-HF

INPUT RAIL IS 3.3V S0

CRITICAL

L7770

1.5UH-6.0A

1 2

PCMB053T

XW7775

P1V05S5_VSNS

<Ra>

1

R7780

3.74K

1%
1/16W
MF-LF
402

2

<Rb>

1

R7781

4.42K

1%
1/16W
MF-LF
402

2

=PP3V3_GPU_P1V8S0

8

1

C7760

10uF

20%

6.3V
2

X5R
603

=P1V8FB_EN

83 82

68

PLACEMENT_NOTE=Place XW7775 next to C7775

2

1

C7776

SM

4.7UF

20%
4V

2

X5R
402

CRITICAL

C7771

330UF

2.0V

POLY-TANT

B2-SM

1

20%

2

1

1.8V S0 Switcher

CRITICAL

1

VI

U7760

TPS62202

SOT23-5

4

FB

3

EN

GND

5

SW

2

=PP1V05_S5_MCP

Vout = 1.052V
5A max output

(L7770 limit)

f = 400 kHz

P1V8GPU_SW

8

CRITICAL

L7760

10UH-0.55A-330MOHM

PCAA031B-SM

1 2

Misc Power Supplies

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

C7762

MAX CURRENT = 300MA

=PP1V8_GPUIFPX_REG

1

10uF

20%

6.3V

2

X5R
603

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

8

SYNC_DATE=12/14/2007

REV.

OF

9667

D

C

B

A

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

3.3V 1,05V S5 ENABLE

R7802

100K

=PP3V42_G3H_PWRCTL

68

63

8

SMC_PM_G2_EN

42

D

IN

R7858

PLACEMENT_NOTE=near U4900

100K

1/16W
MF-LF

1

5%

402

2

5%
1/16W
MF-LF

402

Q7800

SSM3K15FV

SOD-VESM-HF

12

1

G S

P3V3S5_EN_L

NO STUFF

1

C7802

0.068UF

10%
10V

2

3

D

CERM
402

PLACEMENT_NOTE=near U7201

63

OUT

2

R7801

5.1K

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=near U7750

12

PM_G2_P1V05S5_EN

MAKE_BASE=TRUE

1

C7801

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=near U7750

=P1V05S5_EN

State

Run (S0)

Sleep (S3)

Soft-Off (S5)

Battery Off (G3Hot)

67

OUT

S0 ENABLE

(PM_SLP_S3_L)

R7878

PM_SLP_S3_L

7

21 34 37 42 44 81 83

IN

C

100

1 2

5%
1/16W
MF-LF

402

R7879

PLACEMENT_NOTE=near U1400

100K

1/16W
MF-LF

1

5%

402

2

2

1

Unused PGOOD signal

TP_DDRREG_PGOOD

MAKE_BASE=TRUE

DDRREG_PGOOD

64

PM_SLP_S3_L_R

R7880

22K

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=nearU7500

MCPCORES0_EN

MAKE_BASE=TRUE

1

C7880

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=nearU7500

MAKE_BASE=TRUE

R7881

2

33K

5%

1/16W

1

MF-LF
402

PLACEMENT_NOTE=nearU7600

CPUVTTS0_EN

MAKE_BASE=TRUE

1

C7881

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=nearQ7600

R7882

2

0

5%

1/16W

1

MF-LF
402

PLACEMENT_NOTE=nearQ7971

MCPDDR_EN

MAKE_BASE=TRUE

NO STUFF

1

C7882

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=nearQ7971

R7883

2

10K

5%

1/16W

1

MF-LF
402

PLACEMENT_NOTE=nearU7700

P1V8S0_EN

MAKE_BASE=TRUE

1

C7883

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=nearU7700

SMC_PM_G2_ENABLE

2

R7884

0

5%
1/16W
MF-LF

1

402

PLACEMENT_NOTE=nearU7951

NO STUFF

1

C7884

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=nearU7951

1
1
1
0

=PP3V42_G3H_PWRCTL

68

63

8

=PP3V3_S5_PWRCTL

68

8

C7841

0.001UF

20%
50V

CERM

402

2

R7885

10K

5%
1/16W
MF-LF

1

402

PLACEMENT_NOTE=nearU9900

P1V2_S0_EN

MAKE_BASE=TRUE

1

C7885

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=nearU9900

CT

1

2

4

2

R7886

5.1K

5%
1/16W
MF-LF

1

402

PLACEMENT_NOTE=nearU9900

P2V5S0_EN

MAKE_BASE=TRUE

1

C7886

2

PLACEMENT_NOTE=nearU9900

PM_SLP_S4_L

1
1
0 0
0

S5 rail PWRGD

6

VDD

SENSE

U7840

TPS3808G33DBVRG4

SOT23-6

CT

GND

2

0.47UF

10%

6.3V
CERM-X5R
402

PM_SLP_S3_L

1
0

0

1

C7840

0.1uF

20%
10V

2

CERM

402

15

RESET*

3

MR*

TPS3808 MR* HAS INTERNAL PULLUP

=P5V_RTS0_EN

=P3V3S0_EN

=PBUSVSENS_EN

=P2V5S0_EN

=P1V2S0_EN

P1V05S0_EN

=P1V8S0_EN
=MCPDDR_EN

=CPUVTTS0_EN

=MCPCORES0_EN

1

R7840

100K

5%
1/16W
MF-LF
402

2

RSMRST_PWRGD

P1V05_S5_PGOOD

3.3V,5V S3 ENABLE

PM_SLP_S4_L

21 40 42 43

IN

MAKE_BASE=TRUE

PLACEMENT_NOTE=near U1400

42

67

R7810

100K

1/16W
MF-LF

1

2

R7811

5%

402

2

5.1K

5%
1/16W

MF-LF

1

402

PLACEMENT_NOTE=near U7300

1

C7810

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=near U7300

2

R7812

0

5%
1/16W
MF-LF

1

402

PLACEMENT_NOTE=near U7201

NO STUFF

1

C7812

0.47UF

10%

6.3V

2

CERM-X5R
402

PLACEMENT_NOTE=near U7201

Other S0 RAILS

=PP3V3_S0_PWRCTL

68

8

65

OUT

69

OUT

46

OUT

S0PGOOD_PWROK

86

OUT

86

OUT

69

OUT

67

OUT

69

OUT

66

OUT

65

OUT

65

IN

66

IN

IN

65

IN

63

IN

68

9

68

MCPCORES0_PGOOD
CPUVTTS0_PGOOD
P1V8S0_PGOOD
P5V_RTS0_PGOOD
P5V3V3_PGOOD

PM_ALL_GPU_PGOOD

1

R7892

10K

5%
1/16W
MF-LF

402

2

NO STUFF

R7891

0

1 2

5%
1/16W
MF-LF

402

PLACEMENT_NOTE=near U7880

R7894

1/16W
MF-LF

PLACEMENT_NOTE=near U7880

S0_PWR_PGOOD

MAKE_BASE=TRUE

ALL_GFX_PGOOD_R

1

0

5%

2

402

(PM_S4_STATE_L)

IG high
EG PM_ALL_GPU_PGOOD

TC7SZ08AFEAPE

5

2

A

U7880

1

B

3

PM_ALL_GFX_PGOOD

1

C7889

0.1UF

20%
10V

2

CERM
402

SOT665

4

ALL_SYS_PWRGD

Y

P5VS3_EN

MAKE_BASE=TRUE

DDRREG_EN

MAKE_BASE=TRUE

=PP3V3_S5_PWRCTL

=P3V3S3_EN

=P5VS3_EN

=DDRREG_EN

68

8

26 42

OUT

69

OUT

63

OUT

64

OUT

D

C

EG_PWRSEQ_HW

R7851

10K

R7850

100K

1 2

5%
1/16W
MF-LF

402

Q7850

SOT563

2

1 2

5%

1/16W

MF-LF

402

EG_PWRSEQ_HW

SSM6N15FEAPE

6

D

SG

1

=PP3V3_S0_PWRCTL

68

B

8

=PP3V3_S5_PWRCTL

68

8

EXTGPU_PWR_EN

83

IN

R7853

100K

1/16W
MF-LF

5%

402

EG_PWRSEQ_HW

EG_PWRSEQ_HW

1

2

SSM6N15FEAPE

1.1V GPU ENABLE

P1V1_GPU_EN_RC

3

Q7850

D

SOT563

5

SG

GPU_S0_EN_L

MAKE_BASE=TRUE

4

EG_PWRSEQ_HW

12

R7852

0

5%
1/16W
MF-LF
402

PLACEMENT_NOTE=near U9500

P1V1_GPU_EN

MAKE_BASE=TRUE

NO STUFF

1

C7850

0.022UF

20%
16V

2

CERM

402

PLACEMENT_NOTE=near U9500

GPUVCORE_EN_RC_L

=P1V1GPU_EN

68

=PP3V3_GPU_PWRCTL

68

8

82 83

OUT

GPUVCORE_PGOOD

78

EG_PWRSEQ_HW

R7868

100K

5%

1 2

MF-LF
1/16W

402

EG_PWRSEQ_HW

SSM6N15FEAPE

P1V8_S0GPU_EN_RC

SOT563

D

5

SG

Q7861

EG_PWRSEQ_HW

R7869

1 2

1/16W
MF-LF

402

PLACEMENT_NOTE=near U9500

3

4

Graphic MEM ENABLE

0

P1V8_S0GPU_EN

MAKE_BASE=TRUE

5%

NO STUFF

PLACEMENT_NOTE=near U9500

C7869

0.022UF

1

20%
16V

2

CERM

402

=P1V8FB_EN

G96 GPU requires rails to come
up in the following order:

1) 1.1V

2) GPU_3.3V

3) GPUVcore

4) GDDR3 1.8V
BOMOPTION: EG

67 82 83

OUT

=PP3V3_S0_VMON

8

=PP1V5_S0_VMON

8

=PP1V05_S0_VMON

8

GPUVCORE ENABLE

EG_PWRSEQ_HW

R7863

100K

=PP3V3_GPU_PWRCTL

68

8

A

GPUVCORE_EN_RC_L

68

1 2

EG_PWRSEQ_HW

Q7861

SSM6N15FEAPE

1/16W

MF-LF

402

5%

SOT563

2

GPUVCORE_EN_RC

D

SG

6

1

EG_PWRSEQ_HW

R7864

0

5%

1 2

1/16W

402

MF-LF

PLACEMENT_NOTE=near U8900

GPUVCORE_EN

MAKE_BASE=TRUE

C7861

0.01UF

PLACEMENT_NOTE=near U8900

=GPUVCORE_EN

1

10%
16V

2

CERM

402

78 83

OUT

=PP3V3_S0_PWRCTL

68

8

EG_PWRSEQ_HW

PLACEMENT_NOTE=near U7972

P1V1GPU_PGOOD

82

R7889

100K

1/16W
MF-LF

1

5%

402

2

EG_PWRSEQ_HW

R7888

1

MF-LF
1/16W

0

5%

402

P3V3GPU_EN

2

69 83

OUT

EXT GPU PWRGD Pullup

=PP3V3_S0_PWRCTL

68

8

1

R7890

100K

5%
1/16W
MF-LF

402

2

P1V8FB_PGOOD

82

PM_ALL_GPU_PGOOD

MAKE_BASE=TRUE

OUT

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

place XW0402 if needed to save trace space for pin 7,8

3

VCC

U7870

LTC2909

1
8

7
6

NC

9

68

SEL

ADJ1
ADJ2

REF

GND

5

DFN

TMR

RST*

THRM_PAD

9

LTC2909 THRESHOLD IS 3.136V

1.5V 1.05V COMPARED TO 0.5V

APPLE INC.

1

C7870

0.1uF

20%
10V

2

CERM

402

TIE TMR TO GND

2

TRST = 200MS

4

S0PGOOD_PWROK

Power Control

SYNC_MASTER=PWRSQNC

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

68

SYNC_DATE=05/12/2008

REV.

051-7546

SHT

A.0.0

OF

9668

B

A

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

68

IN

C

=PP5V_S3_P1V05S0FET

8

=PP3V3_S5_P1V05FET

8

8

=P3V3S3_EN

=PP3V3_S3_P3V3S3FET

Q7912

SSM6N15FEAPE

SOT563

2

R7953

Q7951

SSM6N15FEAPE

SOT563

D

SG

1/16W
MF-LF

6

1

10K

402

5%

R7912

1

2

P1V05_EN_L

3

D

1/16W
MF-LF

3.3V S3 FET

1

10K

5%

402

2

P3V3S3_EN_L

1.05V S0 FET

R7952

220K

1 2

5%
1/16W
MF-LF

402

SSM6N15FEAPE

R7951

100K

1 2

5%
1/16W
MF-LF

402

C7911

0.033UF

R7910

47K

1 2

5%
1/16W
MF-LF

402

P1V05S0_SS

Q7951

SOT563

2

P1V05_EN_L_RC

CRITICAL

Q7910

FDC638P_G

SM

1

10%
16V

2

X5R
402

6

D

4

3

C7910

P3V3S3_SS

=PP1V05_S5_P1V05S0FET

8

0.01UF

5

D

4

G

S

1 2 3

1 2

10%
16V

CERM

402

CRITICAL

Q7953

SI7108DN

PWRPK-1212-8-HF

APN 376S0651

=PP1V05_S0_FET

1

SG

1

C7953

0.068UF

10%
10V

2

CERM
402

6
5
2
1

=PP3V3_S3_FET

MOSFET
CHANNEL

RDS(ON)

LOADING

CHANNEL
RDS(ON)
LOADING

8

3.3V S3 FET

FDC638P
P-TYPE
48 mOhm @4.5V

0.087 A (EDP)

1.05V S0 FET

SI7108DNMOSFET
N-TYPE
5 mOhm @4.5V

2.1 A (EDP)

8

=PP3V3_S0_P3V3S0FET

8

1

R7932

R7972

1

G S

1/16W
MF-LF

51K

402

100K

1/16W
MF-LF

1

5%

2

3

D

5%

402

2

P3V3GPU_EN_L

2

3

SOT563

5

D

SG

4

Q7972

SSM3K15FV

SOD-VESM-HF

Q7912

SSM6N15FEAPE

=P3V3S0_EN

68

IN

=PP3V3_GPU_P3V3GPUFET

8

P3V3GPU_EN

68 83

IN

3.3V S0 FET

C7931

0.033UF

R7930

47K

P3V3S0_EN_L

1 2

5%
1/16W
MF-LF

402

3.3V GPU FET

1

C7971

1UF

10%
10V

2

X5R
402

R7970

1K

1 2

5%
1/16W
MF-LF

402

1

10%
16V

2

X5R
402

P3V3GPU_SS

P3V3S0_SS

4

CRITICAL

Q7930

FDC606P_G

SOT-6

4

CRITICAL

Q7970

FDC606P_G

SOT-6

SGD

3

C7970

0.01UF

1 2

SGD

3

C7930

0.01UF

1 2

CERM

10%
16V

CERM

402

1 2 5 6

10%
16V

402

1 2 5 6

=PP3V3_S0_FET

MOSFET
CHANNEL

RDS(ON)

LOADING

=PP3V3_S0GPU_FET

MOSFET
CHANNEL

RDS(ON)

LOADING
BOM_OPTION

8

3.3V S0 FET

FDC606P
P-TYPE
26 mOhm @4.5V

2.9 A (EDP)

8

3.3V GPU FET

FDC606P
P-TYPE
26 mOhm @4.5V

1.1 A (EDP)
EG

D

C

5

SG

P1V05S0_EN

68

IN

B

4

MCP79 DDR FETs

MCP79 DDR pad leakage is high enough that nVidia recommends unpowering during sleep.
In order to support unpowering rail, hardware must guarantee MEM_CKE signals are low
before rail is turned off, and remains low until after rail turns back on or DIMMs
will exit self-refresh prematurely. MEM_VTT_EN output from MCP79 used to enable clamp
on VTT rail, which pulls all CKE signals low through VTT termination resistors.

B

1.5V S0 FET

=PPVTT_S0_VTTCLAMP

=PP1V8R1V5_S0_MCP_FET

8

APN 376S0651

1

C7902

0.1UF
20%
10V

2

CERM

402

Q7971

SSM6N15FEAPE

SOT563

2

MCPDDR_EN_L_RC

6

D

SG

1

100K

1/16W
MF-LF

5%

402

R7901

1 2

1/16W
MF-LF

1

2

MCPDDR_EN_L

3

D

SG

4

10K

402

5%

MCPDDR_SS

R7971

1 2

1/16W
MF-LF

47K

5%

402

=PP5V_S3_MCPDDRFET

8

R7903

A

Q7971

SSM6N15FEAPE

SOT563

5

68

IN

=MCPDDR_EN

5

CRITICAL

D

Q7901

S

1 2 3

1

C7903

0.068UF
10%
10V

2

CERM
402

SI7108DN

PWRPK-1212-8-HF

=PP1V8R1V5_S0_FET

4

G

1.5V S0 FET

MOSFET
CHANNEL
RDS(ON)
LOADING

8

SI7108DN
N-TYPE
5 mOhm @4.5V

5.4 A (EDP)
=PP5V_S3_VTTCLAMP

8

=DDRVTT_EN

9

64

IN

Q7975

SSM6N15FEAPE

SOT563

R7976

100K

1/16W
MF-LF

5

1

5%

402

2

D

SG

VTTCLAMP_EN

3

4

8

SSM6N15FEAPE

NO STUFF

C7976

0.001UF

CERM

Q7975

SOT563

20%
50V

402

1

R7975

10

90mA max load @ 0.9V

5%

81mW max power

1/16W
MF-LF

402

VTTCLAMP_L

6

D

2

SG

1

1

2

2

Power FETs

SYNC_MASTER=PWRSQNC

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=05/12/2008

051-7546

SHT

69

A

REV.

A.0.0

OF

96

8

7 6

5

4

3

2

1

8 7

Page Notes

Power aliases required by this page:

- =PP1V2_GPU_PEX_PLLXVDD

- =PP1V2_GPU_PEX_IOVDDQ

- =PP1V2_GPU_PEX_IOVDD

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

D

NC_GPU_DFM

NO_TEST=TRUE

C

H32

M7
P6
P7
R7
U7

V6
AB7
AD6
AF6
AG6
AJ5
D35

AK15

AL7

E7
E35

F7

A2

U8000

NB9P-GS

SYMBOL 2 OF 9

NC

B

OMIT

BGA

PEX_IOVDD1
PEX_IOVDD2
PEX_IOVDD3
PEX_IOVDD4
PEX_IOVDD5

PEX_IOVDDQ1
PEX_IOVDDQ2
PEX_IOVDDQ3
PEX_IOVDDQ4
PEX_IOVDDQ5
PEX_IOVDDQ6
PEX_IOVDDQ7
PEX_IOVDDQ8

PEX_IOVDDQ9
PEX_IOVDDQ10
PEX_IOVDDQ11
PEX_IOVDDQ12
PEX_IOVDDQ13
PEX_IOVDDQ14
PEX_IOVDDQ15
PEX_IOVDDQ16
PEX_IOVDDQ17
PEX_IOVDDQ18
PEX_IOVDDQ19
PEX_IOVDDQ20
PEX_IOVDDQ21
PEX_IOVDDQ22
PEX_IOVDDQ23
PEX_IOVDDQ24
PEX_IOVDDQ25

PEX_PLLVDD

VDD_SENSE

GND_SENSE

8

8

8

PEX 1.1V Current = 2A

250mA

AK16
AK17
AK21
AK24
AK27

1500mA

AG11
AG12
AG13
AG15
AG16
AG17
AG18
AG22
AG23
AG24
AG25
AG26
AJ14
AJ15
AJ19
AJ21
AJ22
AJ24
AJ25
AJ27
AK18
AK20
AK23
AK26
AL16

AG14

AD20

AD19

180mA

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.2V

GPU_VDD_SENSE
GPU_GND_SENSE

=PP1V1_GPU_PEX_PLLXVDD
=PP1V1_GPU_PEX_IOVDDQ
=PP1V1_GPU_PEX_IOVDD

1

C8002

1UF

10%

6.3V

2

CERM
402

1

C8003

1UF

10%

6.3V

2

CERM
402

1

C8008

1UF

10%

6.3V

2

CERM
402

1

C8009

1UF

10%

6.3V

2

CERM
402

1

C8001

4.7UF

20%

6.3V

2

CERM
603

1

C8004

0.1UF

20%
10V

2

CERM
402

1

C8007

4.7UF

20%

6.3V

2

CERM
603

1

C8010

0.1UF

20%
10V

2

CERM
402

PP1V1_GPU_PEX_PLLVDD_F

78

78

1

C8017

0.1UF

20%
10V

2

CERM
402

1

C8000

22UF

20%

6.3V

2

CERM-X5R
805

1

C8005

0.1UF

20%
10V

2

CERM
402

1

C8006

22UF

20%

6.3V

2

CERM-X5R
805

1

C8011

0.1UF

20%
10V

2

CERM
402

L8015

10NH-600MA

1 2

1

C8016

4.7UF

20%

6.3V

2

CERM
603

0603

C8015

4.7UF

20%

6.3V
CERM

603

6

5

4

3

2 1

OMIT

U8000

NB9P-GS

PEG_R2D_C_P<0>

9

89

IN

PEG_R2D_C_N<0>

9

89

IN

PEG_R2D_C_P<1>

9

89

IN

PEG_R2D_C_N<1>

9

89

IN

PEG_R2D_C_P<2>

9

89

IN

PEG_R2D_C_N<2>

9

89

IN

PEG_R2D_C_P<3>

9

89

IN

PEG_R2D_C_N<3>

9

89

IN

PEG_R2D_C_P<4>

9

89

IN

PEG_R2D_C_N<4>

9

89

IN

PEG_R2D_C_P<5>

9

89

IN

PEG_R2D_C_N<5>

9

89

IN

PEG_R2D_C_P<6>

9

89

IN

PEG_R2D_C_N<6>

9

89

IN

PEG_R2D_C_P<7>

9

89

IN

PEG_R2D_C_N<7>

9

89

IN

PEG_R2D_C_P<8>

9

89

IN

PEG_R2D_C_N<8>

9

89

IN

PEG_R2D_C_P<9>

9

89

IN

PEG_R2D_C_N<9>

9

89

IN

PEG_R2D_C_P<10>

9

89

IN

PEG_R2D_C_N<10>

9

89

IN

PEG_R2D_C_P<11>

9

89

IN

PEG_R2D_C_N<11>

9

89

IN

PEG_R2D_C_P<12>

9

89

IN

PEG_R2D_C_N<12>

9

89

IN

PEG_R2D_C_P<13>

9

89

IN

PEG_R2D_C_N<13>

9

89

1

2

IN

9

89

IN

9

89

IN

9

89

IN

9

89

IN

17 89

IN

17 89

IN

9

IN

PEG_R2D_C_P<14>

PEG_R2D_C_N<14>

PEG_R2D_C_P<15>

PEG_R2D_C_N<15>

PEG_CLK100M_P
PEG_CLK100M_N

GPU_RESET_L

C8020
C8021

C8022
C8023

C8024
C8025

C8026
C8027

C8028
C8029

C8030
C8031

C8032
C8033

C8034
C8035

C8036
C8037

C8038
C8039

C8040
C8041

C8042
C8043

C8044
C8045

C8046
C8047

C8048
C8049

C8050
C8051

R8020

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0

1 2

5%
1/16W
MF-LF

402

1 2

10% 16V X5R 402

1 2

10% 16V

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

10% 16V

1 2

1 2

1 2

1 2

1 2

1 2

1 2

10% X5R 40216V

1 2

1 2

1 2

1 2

1 2

1 2

1 2

10% X5R 40216V

PEG_R2D_P<0>

89

PEG_R2D_N<0>

89

X5R 402

PEG_R2D_P<1>

89

402X5R10% 16V

PEG_R2D_N<1>

89

X5R 40210% 16V

89

PEG_R2D_P<2>

X5R 40210% 16V

89

PEG_R2D_N<2>

X5R 40210% 16V

89

PEG_R2D_P<3>

X5R 40210% 16V

89

PEG_R2D_N<3>

X5R 40210% 16V

89

PEG_R2D_P<4>

X5R 40210% 16V

PEG_R2D_N<4>

89

X5R 40210% 16V

PEG_R2D_P<5>

89

X5R 40210% 16V

89

PEG_R2D_N<5>

X5R 40210% 16V

89

PEG_R2D_P<6>

X5R 40210% 16V

89

PEG_R2D_N<6>

X5R 40210% 16V

89

PEG_R2D_P<7>

X5R 40210% 16V

PEG_R2D_N<7>

89

X5R 40210% 16V

89

PEG_R2D_P<8>

X5R 40210% 16V

PEG_R2D_N<8>

X5R 402

PEG_R2D_P<9>

89

X5R

40210% 16V

89

PEG_R2D_N<9>

40210% 16V X5R

89

PEG_R2D_P<10>

X5R 40210% 16V

PEG_R2D_N<10>

89

X5R 40210% 16V

PEG_R2D_P<11>

89

X5R 40210% 16V

PEG_R2D_N<11>

89

X5R 40210% 16V

PEG_R2D_P<12>

89

PEG_R2D_N<12>

89

16V 402X5R10%

PEG_R2D_P<13>

89

X5R 40210% 16V

PEG_R2D_N<13>

89

X5R 40210% 16V

89

PEG_R2D_P<14>

X5R 40210% 16V

PEG_R2D_N<14>

89

X5R 40210% 16V

89

PEG_R2D_P<15>

X5R 40210% 16V

PEG_R2D_N<15>

89

GPU_RESET_R_L

TP_PEX_CLKREQ_L

AP17
AN17

AN19
AP19

AR19
AR20

AP20
AN20

AN22
AP22

AR22
AR23

AP23
AN23

AN25
AP25

AR25
AR26

AP26
AN26

AN28
AP28

AR28
AR29

AP29
AN29

AN31
AP31

AR31
AR32

AR34
AP34

AR16
AR17

AM16

AR13

PEX_RX0
PEX_RX0*

PEX_RX1
PEX_RX1*

PEX_RX2
PEX_RX2*

PEX_RX3
PEX_RX3*

PEX_RX4
PEX_RX4*

PEX_RX5
PEX_RX5*

PEX_RX6
PEX_RX6*

PEX_RX7
PEX_RX7*

PEX_RX8
PEX_RX8*

PEX_RX9
PEX_RX9*

PEX_RX10
PEX_RX10*

PEX_RX11
PEX_RX11*

PEX_RX12
PEX_RX12*

PEX_RX13
PEX_RX13*

PEX_RX14
PEX_RX14*

PEX_RX15
PEX_RX15*

PEX_REFCLK
PEX_REFCLK*

PEX_RST*

PEX_CLKREQ*

SYMBOL 1 OF 9

PEX_TSTCLK_OUT

PEX_TSTCLK_OUT*

PEX_TX0

PEX_TX0*

PEX_TX1

PEX_TX1*

PEX_TX2

PEX_TX2*

PEX_TX3

PEX_TX3*

PEX_TX4

PEX_TX4*

PEX_TX5

PEX_TX5*

PEX_TX6

PEX_TX6*

PEX_TX7

PEX_TX7*

PEX_TX8

PEX_TX8*

PEX_TX9

PEX_TX9*

PEX_TX10

PEX_TX10*

PEX_TX11

PEX_TX11*

PEX_TX12

PEX_TX12*

PEX_TX13

PEX_TX13*

PEX_TX14

PEX_TX14*

PEX_TX15

PEX_TX15*

PEX_TERMP

PEX_RFU1

PEX_RFU2

AL17
AM17

AM18
AM19

AL19
AK19

AL20
AM20

AM21
AM22

AL22
AK22

AL23
AM23

AM24
AM25

AL25
AK25

AL26
AM26

AM27
AM28

AL28
AK28

AK29
AL29

AM29
AM30

AM31
AM32

AN32
AP32

AJ17

AJ18

AG21

AG19
AG20

89

89

89

89

89

89

89

89

89

89

89

89

89

89

89

89

89

89 89

89

89

89

89

89

89

89

89

89

89

89

89

89

89

NC
NC

PEG_D2R_C_P<0>
PEG_D2R_C_N<0>

PEG_D2R_C_P<1>
PEG_D2R_C_N<1>

PEG_D2R_C_P<2>
PEG_D2R_C_N<2>

PEG_D2R_C_P<3>
PEG_D2R_C_N<3>

PEG_D2R_C_P<4>
PEG_D2R_C_N<4>

PEG_D2R_C_P<5>
PEG_D2R_C_N<5>

PEG_D2R_C_P<6>
PEG_D2R_C_N<6>

PEG_D2R_C_P<7>
PEG_D2R_C_N<7>

PEG_D2R_C_P<8>
PEG_D2R_C_N<8>

PEG_D2R_C_P<9>
PEG_D2R_C_N<9>

PEG_D2R_C_P<10>
PEG_D2R_C_N<10>

PEG_D2R_C_P<11>
PEG_D2R_C_N<11>

PEG_D2R_C_P<12>
PEG_D2R_C_N<12>

PEG_D2R_C_P<13>
PEG_D2R_C_N<13>

PEG_D2R_C_P<14>
PEG_D2R_C_N<14>

PEG_D2R_C_P<15>
PEG_D2R_C_N<15>

PEX_TSTCLK_P
PEX_TSTCLK_N

PEX_TERMP_PD

BGA

C8055
C8056

C8057
C8058

C8059
C8060

C8061
C8062

C8063
C8064

C8065
C8066

C8067
C8068

C8069
C8070

C8071
C8072

C8073
C8074

C8075
C8076

C8077
C8078

C8079
C8080

C8081
C8082

C8083
C8084

C8085
C8086

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

R8050

2.49K

1 2

1%
1/16W
MF-LF

402

1 2

10% 402X5R16V

1 2

10% 402X5R16V

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% 16V X5R 402

1 2

10%

1 2

10% 16V X5R 402

1 2

10% 16V X5R 402

1 2

10% 16V X5R 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% 16V X5R 402

1 2

10% 16V X5R 402

1 2

10% 16V X5R 402

1 2

10% 16V X5R 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% X5R16V 402

1 2

10% 16V X5R 402

1 2

10% 16V X5R 402

1 2

10% 16V X5R 402

16V X5R 402

PEG_D2R_P<0>

PEG_D2R_N<0>

PEG_D2R_P<1>

PEG_D2R_N<1>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<5>

PEG_D2R_N<5>

PEG_D2R_P<6>

PEG_D2R_N<6>

PEG_D2R_P<7>

PEG_D2R_N<7>

PEG_D2R_P<8>

PEG_D2R_N<8>

PEG_D2R_P<9>

PEG_D2R_N<9>

PEG_D2R_P<10>

PEG_D2R_N<10>

PEG_D2R_P<11>

PEG_D2R_N<11>

PEG_D2R_P<12>

PEG_D2R_N<12>

PEG_D2R_P<13>

PEG_D2R_N<13>

PEG_D2R_P<14>

PEG_D2R_N<14>

PEG_D2R_P<15>

PEG_D2R_N<15>

R8060

200

1 2

1%
1/16W
MF-LF

402

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

9

89

OUT

D

C

B

NV G96 PCI-E

A

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=07/10/2008

051-7546

SHT

1

A

REV.

A.0.0

OF

9670

8 7

Page Notes

Power aliases required by this page:

- =PPVCORE_GPU

- =PP1V8_GPU_FBVDDQ

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

D

C

B

A

=PPVCORE_GPU

8

=PP1V8_GPU_FBVDDQ

8

Nvidia PRD for GB-128 uses 4x4.7uF, 8x0.47uF, 16x0.1uF

1

C8156

0.1UF

C8162

0.1UF

C8168

0.47UF

CERM-X5R

C8157

0.1UF

C8163

0.1UF

C8169

0.47UF

CERM-X5R

20%
10V

CERM

402

20%
10V

CERM

402

10%

6.3V

402

20%
10V

2

CERM

402

1

20%
10V

2

CERM

402

1

10%

6.3V
2

402

6

???A @ ???/???MHz Core/Mem Clk for VDD

C8158

0.1UF

C8164

0.1UF

C8170

0.47UF

CERM-X5R

1

C8101

4.7UF

20%

6.3V

2

X5R-CERM
402

1

C8104

0.47UF

10%

6.3V

2

CERM-X5R
402

1

C8109

0.47UF

10%

6.3V

2

CERM-X5R
402

1

C8114

0.1UF0.1UF

20%
10V

2

CERM
402

1

C8119

0.1UF

20%
10V

2

CERM
402

1

20%
10V

2

CERM

402

1

20%
10V

2

CERM

402

1

10%

6.3V
2

402

C8159

0.1UF

C8165

0.1UF

C8171

0.47UF

CERM-X5R

1

C8102

4.7UF

20%

6.3V

2

X5R-CERM
402

1

C8105

0.47UF

10%

6.3V

2

CERM-X5R
402

1

C8110

0.47UF

10%

6.3V

2

CERM-X5R
402

1

C8115

0.1UF

20%

2

CERM
402

1

C8120

0.1UF

20%
10V

2

CERM
402

1

20%
10V

2

CERM

402

1

20%
10V

2

CERM

402

1

10%

6.3V
2

402

1

2

1

2

1

2

1

2

1

2

C8100

4.7UF

20%

6.3V
X5R-CERM
402

C8103

0.47UF

10%

6.3V
CERM-X5R
402

C8108

0.47UF

10%

6.3V
CERM-X5R
402

C8113

20%
10V
CERM
402

C8118

0.1UF

20%
10V
CERM
402

1

2

1

2

1

2

1

C8106

0.47UF

10%

6.3V

2

CERM-X5R
402

1

C8111

0.47UF

10%

6.3V

2

CERM-X5R
402

1

C8116

0.1UF

20%
10V10V

2

CERM
402

1

C8121

0.1UF

20%
10V

2

CERM
402

???A @ ???MHz 1.8V GDDR3

1

C8150

4.7UF

C8160

0.47UF

CERM-X5R

C8166

0.47UF

CERM-X5R

6.3V
CERM

6.3V

6.3V

C8151

4.7UF

C8161

0.47UF

CERM-X5R

C8167

0.47UF

CERM-X5R

20%

6.3V
CERM

603

10%

6.3V

402

10%

6.3V

402

20%

2

603

1

10%

2

402

1

10%

2

402

1

C8107

2

1

C8112

2

1

C8117

2

1

C8122

2

1

2

1

2

1

2

0.47UF

10%

6.3V
CERM-X5R
402

0.47UF

10%

6.3V
CERM-X5R
402

0.1UF

20%
10V
CERM
402

0.1UF

20%
10V
CERM
402

5

L11
L12
L13
L14
L15
L16
L17
L18
L19
L20
L21
L22
L23
L24
L25
M12
M14
M16
M18
M20
M22
M24
P11
P13
P15
P17
P19
P21
P23
P25
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
R21
R22
R23
R24
R25
T12
T14
T16
T18
T20
T22
T24
V11
V13
V15
V17

AB27
AB29
AC27
AD27
AE27
AJ28

SYMBOL 9 OF 9

VDD VDD

NB9P-GS

SYMBOL 7 OF 9

B18
J17
U27

E21

FBVDDQ FBVDDQ

G8

G9
G17
G18
G22
H29
J14
J15
J16

OMIT

U8000

NB9P-GS

BGA

OMIT

U8000

BGA

J20
J21
J22
J23
J24
J29
N27
P27
R27
T27
U29
V27
V29
V34
W27
Y27
AA27
AA29
AA31

V19
V21
V23
V25
W11
W12
W13
W14
W15
W16
W17
W18
W19
AD24
W21
W22
W23
W24
W25
Y12
Y14
Y16
Y18
Y20
Y22
Y24
AB11
AB13
AB15
AB17
AB19
AB21
AB23
AB25

AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20

AC21
AC22
AC23

AC24
AC25
AD12
AD14
AD16
AD18
AD22

W20

4

U8000

NB9P-GS

BGA

SYMBOL 8 OF 9

B12
B15
B21
B24
B27
B30
B33

C34

E12
E15
E18
E24
E27
E30

F31
F34

J31
J34

M11
M13
M15
M17
M19
M21
M23
M25
M31
M34
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
N21
N22
N23
N24
N25
P12
P14
P16
P18
P20
P22
P24

R31
R34
T11
T13
T15
T17
T19
T21
T23
T25
U11
U12
U13
U14
U15

U16
U17
U18
U19
U20
U21
U22
U23
U24
U25

V12
V14
V16

B3
B6
B9

C2

E6
E9

F2
F5

J2
J5

L9
M2
M5

R2
R5

V2
V5
V9

3

V18
V20
V22
V24
V31
Y11
Y13
Y15
Y17
Y19
Y21
Y23
Y25
AA2
AA5
AA11
AA12
AA13
AA14
AA15
AA16
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA34

AB12
AB14

AB16
AB18
AB20
AB22
AB24
AC9
AD2
AD5
AD11
AD13
AD15
AD17
AD21
AD23
AD25

GNDGND

AD31
AD34
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AG2
AG5
AG31
AG34
AK2
AK5
AP33
AK31
AK34
AL6
AL9
AL12
AL15
AL18
AL21
AL24
AL27
AL30
AN2
AN34
AP3
AP6
AP9
AP12
AP15
AP18
AP21
AP24
AP27
AP30

2 1

NV G96 Core/FB Power

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

APPLE INC.

SIZE

D

SCALE

NONE

051-7546

SHT

71 96

SYNC_DATE=07/10/2008

REV.

A.0.0

OF

D

C

B

A

8

7 6

5

4

3

2

1

8 7

Page Notes

Power aliases required by this page:

- =PP1V2_GPU_FBPLLAVDD

- =PP1V8_GPU_FBIO

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

D

C

B

A

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

73 94

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

FB_A_DQ<0>
FB_A_DQ<1>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<4>
FB_A_DQ<5>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<8>
FB_A_DQ<9>
FB_A_DQ<10>
FB_A_DQ<11>
FB_A_DQ<12>
FB_A_DQ<13>
FB_A_DQ<14>
FB_A_DQ<15>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<18>
FB_A_DQ<19>
FB_A_DQ<20>
FB_A_DQ<21>
FB_A_DQ<22>
FB_A_DQ<23>
FB_A_DQ<24>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<27>
FB_A_DQ<28>
FB_A_DQ<29>
FB_A_DQ<30>
FB_A_DQ<31>
FB_A_DQ<32>
FB_A_DQ<33>
FB_A_DQ<34>
FB_A_DQ<35>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<40>
FB_A_DQ<41>
FB_A_DQ<42>
FB_A_DQ<43>
FB_A_DQ<44>
FB_A_DQ<45>
FB_A_DQ<46>
FB_A_DQ<47>
FB_A_DQ<48>
FB_A_DQ<49>
FB_A_DQ<50>
FB_A_DQ<51>
FB_A_DQ<52>
FB_A_DQ<53>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<56>
FB_A_DQ<57>
FB_A_DQ<58>
FB_A_DQ<59>
FB_A_DQ<60>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<63>

6

5

4

OMIT

U8000

NB9P-GS

BGA

R30
R32
P31
N30

L31
M32
M30
L30
P33
P34
N35
P35
N34
L33
L32
N33
K31
K30
G30
K32
G32
H30
F30

G31
H33
K35

K33
G34
K34
E33
E34

G33
AG30
AH31
AG32
AF31
AF30
AD30
AC32
AE30
AE32
AF33
AF34
AE35
AE33
AE34
AC35
AB32
AN33
AK32
AL33
AM33
AL31
AK30
AJ30
AH30
AM35
AH33
AH35
AH32

AH34
AM34
AL35
AJ33

P29

NC

R29

NC NC

L29

NC

M29

NC

AD29

NC

AE29

NC

AG29

NC

AH29

NC

SYMBOL 3 OF 9
FBA_D0
FBA_D1
FBA_D2
FBA_D3
FBA_D4
FBA_D5
FBA_D6
FBA_D7
FBA_D8
FBA_D9
FBA_D10
FBA_D11
FBA_D12
FBA_D13
FBA_D14
FBA_D15
FBA_D16
FBA_D17
FBA_D18
FBA_D19
FBA_D20
FBA_D21
FBA_D22
FBA_D23
FBA_D24
FBA_D25
FBA_D26
FBA_D27
FBA_D28
FBA_D29
FBA_D30
FBA_D31
FBA_D32
FBA_D33
FBA_D34
FBA_D35
FBA_D36
FBA_D37
FBA_D38
FBA_D39
FBA_D40
FBA_D41
FBA_D42
FBA_D43
FBA_D44
FBA_D45
FBA_D46
FBA_D47
FBA_D48
FBA_D49
FBA_D50
FBA_D51
FBA_D52
FBA_D53
FBA_D54
FBA_D55
FBA_D56
FBA_D57
FBA_D58
FBA_D59
FBA_D60
FBA_D61
FBA_D62
FBA_D63

FBA_RFU0
FBA_RFU1*
FBA_RFU2
FBA_RFU3*
FBA_RFU4
FBA_RFU5*
FBA_RFU6
FBA_RFU7*

FBA_CMD0
FBA_CMD1
FBA_CMD2
FBA_CMD3
FBA_CMD4
FBA_CMD5
FBA_CMD6
FBA_CMD7
FBA_CMD8

FBA_CMD9
FBA_CMD10
FBA_CMD11
FBA_CMD12
FBA_CMD13
FBA_CMD14
FBA_CMD15
FBA_CMD16
FBA_CMD17
FBA_CMD18
FBA_CMD19
FBA_CMD20
FBA_CMD21
FBA_CMD22
FBA_CMD23
FBA_CMD24
FBA_CMD25
FBA_CMD26
FBA_CMD27
FBA_CMD28
FBA_CMD29
FBA_CMD30

FBA_CLK0
FBA_CLK0*

FBA_CLK1
FBA_CLK1*

FBA_DQM0

FBA_DQM1

FBA_DQM2

FBA_DQM3

FBA_DQM4

FBA_DQM5

FBA_DQM6

FBA_DQM7

FBA_DQS_RN0
FBA_DQS_RN1
FBA_DQS_RN2
FBA_DQS_RN3
FBA_DQS_RN4
FBA_DQS_RN5
FBA_DQS_RN6
FBA_DQS_RN7

FBA_DQS_WP0
FBA_DQS_WP1
FBA_DQS_WP2
FBA_DQS_WP3
FBA_DQS_WP4
FBA_DQS_WP5
FBA_DQS_WP6
FBA_DQS_WP7

FB_DLLAVDD0
FB_PLLAVDD0

FBA_DEBUG

FB_CAL_PD_VDDQ

FB_CAL_PU_GND

FB_CAL_TERM_GND

V32
W31

U31
Y32
AB35
AB34
W35
W33
W30
T34
T35
AB31
Y30
Y34
W32
AA30
AA32
Y33
U32
Y31
U34
Y35
W34
V30
U35
U30
U33
AB30
AB33
T33
W29

T32
T31
AC31
AC30

P30
P32
J30
H34
AF32
AF35
AL32
AL34

N32
L35

H31
G35
AD32
AC34
AJ31
AJ35

N31
L34
J32
H35
AE31
AC33
AJ32
AJ34

AG27
AF27

T30

K27
L27

M27

FB_A_LMA<4>
FB_A_RAS_L
FB_A_LMA<5>
FB_A_BA<1>
FB_A_UMA<2>
FB_A_UMA<4>
FB_A_UMA<3>
FB_A_CS1_L
FB_A_CS0_L
FB_A_MA<11>
FB_A_CAS_L
FB_A_WE_L
FB_A_BA<0>
FB_A_UMA<5>
FB_A_MA<12>
FB_A_DRAM_RST
FB_A_MA<7>
FB_A_MA<10>
FB_A_CKE
FB_A_MA<0>
FB_A_MA<9>
FB_A_MA<6>
FB_A_LMA<2>
FB_A_MA<8>
FB_A_LMA<3>
FB_A_MA<1>
FB_A_MA<13>
FB_A_BA<2>
TP_FBA_CMD28
TP_FBA_CMD29
TP_FBA_CMD30

FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CLK_P<1>
FB_A_CLK_N<1>

FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>
FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>

FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>
FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>

FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>
FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>

FBA_DEBUG

FBCAL_PD_VDDQ
FBCAL_PU_GND
FBCAL_TERM_GND

76

76

76

PLACEMENT_NOTE=Place close to U8000.

FB_B_DQ<0>

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

76

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

76

OUT

73 94 74 94

OUT OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

BI

73 94

BI

73 94

BI

73 94

BI

73 94

BI

73 94

BI

73 94

BI

73 94

BI

73 94

IN

73 94

IN

73 94

IN

73 94

IN

73 94

IN

73 94

IN

73 94

IN

73 94

IN

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

73 94

OUT

1

R8201

10K

5%
1/16W
MF-LF
402

2

=PP1V1_GPU_FBPLLAVDD

72

8

PP1V1_GPU_FBPLLAVDD_F

MIN_LINE_WIDTH=0.2 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.1V

1

C8202

0.1UF

20%
10V

2

CERM
402

1

2

C8201

0.1UF

20%
10V
CERM
402

1

R8200

10K

5%
1/16W
MF-LF
402

2

OUT

73 94

L8200

FERR-220-OHM

1 2

1

C8200

1UF

10%

6.3V

2

CERM
402

0402

72

8

R8293

=PP1V8_GPU_FBIO

1

R8290

60.4

1%
1/16W
MF-LF

402

2

48.7

1/16W
MF-LF

1%

402

74 94

BI

FB_B_DQ<1>

74 94

BI

FB_B_DQ<2>

74 94

BI

FB_B_DQ<3>

74 94

BI

FB_B_DQ<4>

74 94

BI

FB_B_DQ<5>

74 94

BI

FB_B_DQ<6>

74 94

BI

FB_B_DQ<7>

74 94

BI

FB_B_DQ<8>

74 94

BI

FB_B_DQ<9>

74 94

BI

FB_B_DQ<10>

74 94

BI

FB_B_DQ<11>

74 94

BI

FB_B_DQ<12>

74 94

BI

FB_B_DQ<13>

74 94

BI

FB_B_DQ<14>

74 94

BI

FB_B_DQ<15>

74 94

BI

FB_B_DQ<16>

74 94

BI

FB_B_DQ<17>

74 94

BI

FB_B_DQ<18>

74 94

BI

FB_B_DQ<19>

74 94

BI

FB_B_DQ<20>

74 94

BI

FB_B_DQ<21>

74 94

BI

FB_B_DQ<22>

74 94

BI

FB_B_DQ<23>

74 94

BI

FB_B_DQ<24>

74 94

BI

FB_B_DQ<25>

74 94

BI

FB_B_DQ<26>

74 94

BI

FB_B_DQ<27>

74 94

BI

FB_B_DQ<28>

74 94

BI

FB_B_DQ<29>

74 94

BI

FB_B_DQ<30>

74 94

BI

FB_B_DQ<31>

74 94

BI

FB_B_DQ<32>

74 94

BI

FB_B_DQ<33>

74 94

BI

FB_B_DQ<34>

74 94

BI

FB_B_DQ<35>

74 94

BI

FB_B_DQ<36>

74 94

BI

FB_B_DQ<37>

74 94

BI

FB_B_DQ<38>

74 94

BI

FB_B_DQ<39>

74 94

BI

FB_B_DQ<40>

74 94

BI

FB_B_DQ<41>

74 94

BI

FB_B_DQ<42>

74 94

BI

FB_B_DQ<43>

74 94

BI

FB_B_DQ<44>

74 94

BI

FB_B_DQ<45>

74 94

BI

FB_B_DQ<46>

74 94

BI

FB_B_DQ<47>

74 94

BI

FB_B_DQ<48>

74 94

BI

FB_B_DQ<49>

74 94

BI

FB_B_DQ<50>

74 94

BI

FB_B_DQ<51>

74 94

BI

FB_B_DQ<52>

74 94

BI

FB_B_DQ<53>

74 94

BI

FB_B_DQ<54>

74 94

BI

FB_B_DQ<55>

74 94

BI

FB_B_DQ<56>

74 94

BI

FB_B_DQ<57>

74 94

BI

FB_B_DQ<58>

74 94

BI

FB_B_DQ<59>

74 94

BI

FB_B_DQ<60>

74 94

BI

FB_B_DQ<61>

74 94

BI

FB_B_DQ<62>

74 94

74 94

BI
BI

FB_B_DQ<63>

1

2

PLACEMENT_NOTE=Place close to U8000.

1

R8291

1

R8292

40.2

1/16W
MF-LF

1%

402

2

33.2

1%

1/16W

PLACEMENT_NOTE=Place close to U8000.

MF-LF

402

2

3

2 1

OMIT

U8000

NB9P-GS

BGA

FBC_D0
FBC_D1
FBC_D2
FBC_D3
FBC_D4
FBC_D5
FBC_D6
FBC_D7
FBC_D8
FBC_D9
FBC_D10
FBC_D11
FBC_D12
FBC_D13
FBC_D14
FBC_D15
FBC_D16
FBC_D17
FBC_D18
FBC_D19
FBC_D20
FBC_D21
FBC_D22
FBC_D23
FBC_D24
FBC_D25
FBC_D26
FBC_D27
FBC_D28
FBC_D29
FBC_D30
FBC_D31
FBC_D32
FBC_D33
FBC_D34
FBC_D35
FBC_D36
FBC_D37
FBC_D38
FBC_D39
FBC_D40
FBC_D41
FBC_D42
FBC_D43
FBC_D44
FBC_D45
FBC_D46
FBC_D47
FBC_D48
FBC_D49
FBC_D50
FBC_D51
FBC_D52
FBC_D53
FBC_D54
FBC_D55
FBC_D56
FBC_D57
FBC_D58
FBC_D59
FBC_D60
FBC_D61
FBC_D62
FBC_D63

FBC_RFU0
FBC_RFU1*
FBC_RFU2
FBC_RFU3*
FBC_RFU4
FBC_RFU5*
FBC_RFU6
FBC_RFU7*

73 74 76

IN

SYMBOL 4 OF 9

FBC_DQS_RN0
FBC_DQS_RN1
FBC_DQS_RN2
FBC_DQS_RN3
FBC_DQS_RN4
FBC_DQS_RN5
FBC_DQS_RN6
FBC_DQS_RN7

FBC_DQS_WP0
FBC_DQS_WP1
FBC_DQS_WP2
FBC_DQS_WP3
FBC_DQS_WP4
FBC_DQS_WP5
FBC_DQS_WP6
FBC_DQS_WP7

FB_DLLAVDD1
FB_PLLAVDD1

FB_VREF_UNTERM

FBC_CMD0
FBC_CMD1
FBC_CMD2
FBC_CMD3
FBC_CMD4
FBC_CMD5
FBC_CMD6
FBC_CMD7
FBC_CMD8

FBC_CMD9
FBC_CMD10
FBC_CMD11
FBC_CMD12
FBC_CMD13
FBC_CMD14
FBC_CMD15
FBC_CMD16
FBC_CMD17
FBC_CMD18
FBC_CMD19
FBC_CMD20
FBC_CMD21
FBC_CMD22
FBC_CMD23
FBC_CMD24
FBC_CMD25
FBC_CMD26
FBC_CMD27
FBC_CMD28
FBC_CMD29
FBC_CMD30

FBC_CLK0
FBC_CLK0*

FBC_CLK1
FBC_CLK1*

FBC_DQM0

FBC_DQM1

FBC_DQM2

FBC_DQM3

FBC_DQM4

FBC_DQM5

FBC_DQM6

FBC_DQM7

FBC_DEBUG

FB_VREF

C17
B19
D18
F21
A23
D21

B23
E20
G21
F20
F19
F23
A22
C22
B17
F24
C25
E22
C20

B22
A19
D22
D20

E19
D19
F18
C19
F22
C23
B20

A20

E17
D17
D23
E23

F11
D10
D15
A16
D27

D28
D34
A34

D9
B10
E14

B14
F26

A26
D31
A31

E10
A10

D14
C14
E26

B26
D32
A32

J19
J18

G19

J27

Q8295

SSM6N15FEAPE

NO STUFF

SOT563

2

FB_B_LMA<4>
FB_B_RAS_L
FB_B_LMA<5>
FB_B_BA<1>
FB_B_UMA<2>
FB_B_UMA<4>
FB_B_UMA<3>
FB_B_CS1_L
FB_B_CS0_L
FB_B_MA<11>
FB_B_CAS_L
FB_B_WE_L
FB_B_BA<0>
FB_B_UMA<5>
FB_B_MA<12>
FB_B_DRAM_RST
FB_B_MA<7>
FB_B_MA<10>
FB_B_CKE
FB_B_MA<0>
FB_B_MA<9>
FB_B_MA<6>
FB_B_LMA<2>
FB_B_MA<8>
FB_B_LMA<3>
FB_B_MA<1>
FB_B_MA<13>
FB_B_BA<2>
TP_FBC_CMD28
TP_FBC_CMD29
TP_FBC_CMD30

FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CLK_P<1>
FB_B_CLK_N<1>

FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>
FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>

FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>
FB_B_RDQS<4>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>

FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>
FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>

FBC_DEBUG

GPU_FB_VREF_UNTERM_L

MIN_LINE_WIDTH=0.25 mm
MIN_NECK_WIDTH=0.25 mm

6

D

SG

1

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

76

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

76

OUT

76

76

76

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

BI

74 94

BI

74 94

BI

74 94

BI

74 94

BI

74 94

BI

74 94

BI

74 94

BI

74 94

IN

74 94

IN

74 94

IN

74 94

IN

74 94

IN

74 94

IN

74 94

IN

74 94

IN

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

74 94

OUT

1

R8251

10K

5%
1/16W
MF-LF
402

2

74 94

OUT

GPU_FB_VREF

NV G96 Frame Buffer I/F

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

1

R8250

10K

5%
1/16W
MF-LF
402

2

=PP1V1_GPU_FBPLLAVDD

72

8

72

8

NO STUFF

1

C8296

0.1uF

10%
16V

2

X5R
402

DRAWING NUMBER

D

NONE

74 94

OUT

1

C8290

0.1UF

20%
10V

2

CERM
402

=PP1V8_GPU_FBIO

1

R8294

60.4

1%
1/16W
MF-LF

402

2

NO STUFF

1

R8297

1%
1/16W
MF-LF

402

2

SYNC_DATE=07/10/2008

051-7546

SHT

72 96

OF

1

C8291

2

0.1UF

20%
10V
CERM
402

R8295

R8296

1.07K

1/16W
MF-LF

2.49K1.02K

1/16W
MF-LF

REV.

1%

402

1%

402

A.0.0

D

C

B

1

2

1

2

A

D11
E11
F10

D8
F8
F9

E8
F12
B11
C13
A11

B8

A8

C8
C11
C10
D12
E13
F17
F15
F16
E16
F14
F13
D13
A13
B13
A14
C16
A17
B16
D16
D24
D26
E25
F25
F27
E28
F28
D29
A25
B25
D25
C26
C28
B28
A28
A29
E29
F29
D30
E31
C33
D33
F32
E32
B29
C29
B31
C31
B32
C32
B34
B35

G11

NC

G12
G14

NC

G15

NC

G24

NC

G25

NC

G27

NC

G28

NC

8

7 6

5

4

3

2

1

8 7

6

5

4

OMIT

=PP1V8_GPU_FB_VDD =PP1V8_GPU_FB_VDD

74 74

73 73

8 8

C8400

10UF

1

1

C8401

0.1uF

20%

6.3V
X5R
603

10%
16V

2

2

X5R
402

1

C8402

0.1uF

10%
16V

2

X5R
402

1

2

C8403

0.1uF

10%
16V
X5R
402

1

C8404

2

0.1uF

10%
16V
X5R
402

A11

F12

M12

V11

D

1

C8410

10%
16V

2

X5R
402

=PP1V8_GPU_FB_VDDQ

73

9 8

8

1/16W
MF-LF

549

1

C8422

0.1uF

10%
16V

2

X5R
402

1

1%

402

2

1

1

C8420

10UF

20%

6.3V
2

X5R
603

=PP1V8_GPU_FB_VREF_A

73 73

9 9

C8421

2

0.1uF

10%
16V
X5R
402

R8430

1

C8423

2

0.1uF

10%
16V
X5R
402

1

C8424

2

0.1uF

10%
16V
X5R
402

R8433

1/16W
MF-LF

549

1

2

1

1%

402

2

FB_A0_VREF

C

1

R8440

1K

5%
1/16W
MF-LF

402

2

FB_A_MA<0>

72 73 94

IN

FB_A_MA<1>

72 73 94

IN

FB_A_LMA<2>

72 94

IN

FB_A_LMA<3>

72 94

IN

FB_A_LMA<4>

72 94

IN

FB_A_LMA<5>

72 94

IN

FB_A_MA<6>

72 73 94

B

A

IN

FB_A_MA<7>

72 73 94

IN

FB_A_MA<8>

72 73 94

IN

FB_A_MA<9>

72 73 94

IN

FB_A_MA<10>

72 73 94

IN

72 73 94

IN

FB_A_CKE

72 73 94

IN

FB_A_MA<12>

72 73 94 72 73 94

IN IN

FB_A_CLK_P<0>

72 94

IN

FB_A_CLK_N<0>

72 94

IN

FB_A_CS0_L

72 73 94

IN

FB_A_WE_L

72 73 94

IN

FB_A_CAS_L

72 73 94

IN

FB_A_RAS_L

72 73 94

IN

FB_A_DRAM_RST

72 73 94

IN

FB_A_RDQS<3>

72 94

OUT

FB_A_RDQS<2>

72 94

OUT

FB_A_RDQS<0>

72 94

OUT

FB_A_RDQS<1>

72 94

OUT

FB_A_WDQS<3>

72 94

IN

FB_A_WDQS<2>

72 94

IN

FB_A_WDQS<0>

72 94

IN

FB_A_WDQS<1>

72 94

IN

FB_A_BA<0>

72 73 94

IN

FB_A_BA<1>

72 73 94

IN

FB_A_BA<2>

72 73 94

IN

R8431

1.33K

1/16W
MF-LF

VRAM4

R8442

1/16W
MF-LF

121

1

1%

402

2

1

1%

402

2

R8432

1/16W
MF-LF

VRAM4

R8444

VRAM4

1

R8443

121

1%
1/16W
MF-LF
402

2

1

931

1%

402

2

121

1/16W
MF-LF

402

R8448

243

1/16W
MF-LF

1

C8431

0.01UF

10%
16V

2

CERM
402

1

R8446

243

VRAM4

1

R8445

121

1%
1/16W
MF-LF
402

2

FB_A0_ZQ
FB_A0_MF
FB_A0_SEN

1

R8449

100

5%
1/16W
MF-LF
402

2

1/16W
MF-LF

1%

402

1%

2

1

1%

402

2

1

R8434

1.33K

1%
1/16W
MF-LF

402

2

FB_A_CLK0_TERM

VOLTAGE=0.9V

1

2

1

R8447

243

1%
1/16W
MF-LF
402

2

C8446

0.01UF

1

C8415

0.1uF0.1uF

10%
16V

2

X5R
402

U8400.J12

C8425

0.1uF

10%
16V
X5R
402

1

C8426

0.1uF

2

10%
16V
X5R
402

FB_A2_VREF FB_A3_VREF

1

R8435

931

1%
1/16W
MF-LF

402

2

1

2

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

RFU

72 73 74
76

OMIT

CRITICAL

U8400

BGA

(1 OF 2)

MFHIGH

MFHIGH

MFHIGH

10%
16V

CERM

402

K9
H11
K10

M9

K4

H2

K3

L4

K2

M4
K11

L9

H9

J3

J11

J10

F4
H4
F9

H10

A4
A9
V4

V9

D3
D10
P10

P3

D2
D11

P11

P2

G9

G4

H3

J2

NC NC

K12

A12

C12

E12

N12

R12

V12

H12

1

C8432

0.01UF

10%
16V

2

CERM
402

FB_A2_VREF_UNTERM_L
FB_A0_VREF_UNTERM_L

FB_VREF_UNTERM

IN IN

DM0
DM1
DM2
DM3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6

K4J10324QD-HC11

DQ7

32MX32-900MHZ-MFH

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

A2

VDD0
VDD1

F1

VDD2
VDD3

M1

VDD4
VDD5

V2

VDD6
VDD7

K1

VDDA0
VDDA1

A1

VDDQ0
VDDQ1

C1

VDDQ2

C4

VDDQ3

C9

VDDQ4
VDDQ5

E1

VDDQ6

E4

VDDQ7

E9

VDDQ8
VDDQ9

J4

VDDQ10

J9

VDDQ11

N1

VDDQ12

N4

VDDQ13

N9

VDDQ14
VDDQ15

R1

VDDQ16

R4

VDDQ17

R9

VDDQ18
VDDQ19

V1

VDDQ20
VDDQ21

H1

VREF0
VREF1

SSM6N15FEAPE

E3
E10
N10
N3

B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11

R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

CRITICAL

U8400

(2 OF 2)

Q8400

VSS0
VSS1

BGA

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

VSSA0
VSSA1

VSSQ0

K4J10324QD-HC11

VSSQ1

32MX32-900MHZ-MFH

VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

D

SOT563

2

SG

FB_A_DQM_L<3>
FB_A_DQM_L<2>
FB_A_DQM_L<0>
FB_A_DQM_L<1>

FB_A_DQ<24>
FB_A_DQ<30>
FB_A_DQ<29>
FB_A_DQ<31>
FB_A_DQ<28>
FB_A_DQ<27>
FB_A_DQ<25>
FB_A_DQ<26>
FB_A_DQ<20>
FB_A_DQ<22>
FB_A_DQ<21>
FB_A_DQ<23>
FB_A_DQ<19>
FB_A_DQ<18>
FB_A_DQ<16>
FB_A_DQ<17>
FB_A_DQ<5>
FB_A_DQ<4>
FB_A_DQ<6>
FB_A_DQ<7>
FB_A_DQ<2>
FB_A_DQ<3>
FB_A_DQ<1>
FB_A_DQ<0>
FB_A_DQ<13>
FB_A_DQ<15>
FB_A_DQ<14>
FB_A_DQ<12>
FB_A_DQ<10>
FB_A_DQ<9>
FB_A_DQ<8>
FB_A_DQ<11>

A3
A10
G1
G12
L1
L12
V3
V10

J1
J12

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

6

SSM6N15FEAPE

1

Q8400

IN
IN
IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

SOT563

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

=PP1V8_GPU_FB_VDDQ

74 74 73

9

C8470

10UF

1

1

2

C8451

0.1uF

10%
16V

2

X5R X5R
402

C8450

10UF

20%

6.3V
X5R
603

Connect to designated pin, then GNDConnect to designated pin, then GND

1

1

20%

6.3V
2

X5R
603

C8471

2

0.1uF

10%
16V
X5R
402

1

C8472

2

0.1uF

10%
16V
X5R
402

1

2

C8473

0.1uF

10%
16V
X5R
402

1

2

C8452

0.1uF

10%
16V

402

1

C8474

0.1uF

10%
16V

2

X5R
402

1

C8453

2

1

C8460

2

U8400.J1U8400.J1

0.1uF

10%
16V
X5R
402

0.1uF

10%
16V
X5R
402

1

C8475

2

0.1uF

10%
16V
X5R
402

=PP1V8_GPU_FB_VREF_A

R8480

549

1/16W
MF-LF

1

1%

402

2

R8483

549

1/16W
MF-LF

1

1%

402

2

FB_A1_VREF

1

R8482

1/16W
MF-LF

VRAM4

R8494

VRAM4

1

R8493

121

1%
1/16W
MF-LF
402

2

931

1%

402

121

1/16W
MF-LF

402

R8498

1/16W
MF-LF

1

2

243

1

1%

2

R8484

1.33K

1%
1/16W
MF-LF

402

FB_A_CLK1_TERM

VOLTAGE=0.9V

1

R8497

243

1%
1/16W
MF-LF
402

2

1

2

C8496

0.01UF

CERM

R8485

1

10%
16V

2

402

K9

A0

H11

A1

K10

A2

M9

A3

K4

A4

H2

A5

K3

A6

L4

A7

K2

A8/AP

M4

A9

K11

A10

L9

A11

H9

CKE

J3

A12/CS1*

J11

CK

J10

CK*

F4

CS0*

H4

WE*

F9

CAS*

H10

RAS*

A4

ZQ

A9

MF

V4

SEN

V9

RESET

D3

RDQS0

D10

RDQS1

P10

RDQS2

P3

RDQS3

D2

WDQS0

D11

WDQS1

P11

WDQS2

P2

WDQS3

G9

BA0

G4

BA1

H3

BA2

J2

RFU

C8481

0.01uF

10%
16V

2

CERM
402

1

R8496

VRAM4

1

R8495

121

1%
1/16W
MF-LF
402

2

1

R8499

100

5%
1/16W
MF-LF
402

2

243

1/16W
MF-LF

402

FB_A1_ZQ
FB_A1_MF
FB_A1_SEN

1%

2

1

1%

402

2

1

R8481

1.33K

1%
1/16W
MF-LF

402

2

3

D

R8490

1/16W

5

SG

4

72 73 94

IN

72 73 94

IN

72 94

IN

72 94

IN

72 94

IN

72 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

72 94

IN

72 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

72 94

OUT

72 94

OUT

72 94

OUT

72 94

OUT

72 94

IN

72 94

IN

72 94

IN

72 94

IN

72 73 94

IN

72 73 94

IN

72 73 94

IN

MF-LF

FB_A_MA<0>
FB_A_MA<1>
FB_A_UMA<2>
FB_A_UMA<3>
FB_A_UMA<4>
FB_A_UMA<5>
FB_A_MA<6>
FB_A_MA<7>
FB_A_MA<8>
FB_A_MA<9>
FB_A_MA<10>
FB_A_MA<11>FB_A_MA<11>
FB_A_CKE
FB_A_MA<12>

FB_A_CLK_P<1>
FB_A_CLK_N<1>
FB_A_CS0_L
FB_A_WE_L
FB_A_CAS_L
FB_A_RAS_L

FB_A_DRAM_RST

FB_A_RDQS<7>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<4>

FB_A_WDQS<7>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<4>

FB_A_BA<0>
FB_A_BA<1>
FB_A_BA<2>

VRAM4

1

1K

5%

402

2

R8492

121

1/16W
MF-LF

1

1%

402

2

3

1

C8454

0.1uF

10%
16V

2

X5R
402

1

C8465

0.1uF

10%
16V

2

X5R
402

U8400.J12

1

C8476

0.1uF

10%
16V

2

X5R
402

1

931

1%
1/16W
MF-LF

402

2

72 73 74
76

OMIT

CRITICAL

U8450

BGA

(1 OF 2)

MFHIGH

32MX32-900MHZ-MFH

MFHIGH

MFHIGH

A2

VDD0

A11

VDD1

F1

VDD2

F12

VDD3

M1

VDD4

M12

VDD5

V2

VDD6

V11

VDD7

K1

VDDA0

K12

VDDA1

A1

VDDQ0

A12

VDDQ1

C1

VDDQ2

C4

VDDQ3

C9

VDDQ4

C12

VDDQ5

E1

VDDQ6

E4

VDDQ7

E9

VDDQ8

E12

VDDQ9

J4

VDDQ10

J9

VDDQ11

N1

VDDQ12

N4

VDDQ13

N9

VDDQ14

N12

VDDQ15

R1

VDDQ16

R4

VDDQ17

R9

VDDQ18

R12

VDDQ19

V1

VDDQ20

V12

VDDQ21

H1

VREF0

H12

VREF1

1

C8482

0.01uF

10%
16V

2

CERM
402

FB_A3_VREF_UNTERM_L
FB_A1_VREF_UNTERM_L

SSM6N15FEAPE

FB_VREF_UNTERM

E3

DM0

E10

DM1

N10

DM2

N3

DM3

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

K4J10324QD-HC11

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ7
DQ8
DQ9

T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10

OMIT

CRITICAL

U8450

(2 OF 2)

Q8450

VSS0
VSS1

BGA

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

VSSA0
VSSA1

VSSQ0

K4J10324QD-HC11

VSSQ1

32MX32-900MHZ-MFH

VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

D

SOT563

2

SG

FB_A_DQM_L<7>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<4>

FB_A_DQ<59>
FB_A_DQ<58>
FB_A_DQ<63>
FB_A_DQ<60>
FB_A_DQ<57>
FB_A_DQ<56>
FB_A_DQ<61>
FB_A_DQ<62>
FB_A_DQ<40>
FB_A_DQ<47>
FB_A_DQ<46>
FB_A_DQ<45>
FB_A_DQ<42>
FB_A_DQ<44>
FB_A_DQ<43>
FB_A_DQ<41>
FB_A_DQ<54>
FB_A_DQ<55>
FB_A_DQ<53>
FB_A_DQ<52>
FB_A_DQ<49>
FB_A_DQ<51>
FB_A_DQ<50>
FB_A_DQ<48>
FB_A_DQ<36>
FB_A_DQ<37>
FB_A_DQ<32>
FB_A_DQ<38>
FB_A_DQ<39>
FB_A_DQ<34>
FB_A_DQ<33>
FB_A_DQ<35>

A3
A10
G1
G12
L1
L12
V3
V10

J1
J12

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

6

SSM6N15FEAPE

1

2 1

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VREFA

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
VRAM4

3

IN
IN
IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

SOT563

5

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

D

SG

4

GDDR3 Frame Buffer A (Top)

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

Q8450

DRAWING NUMBER

NONE

SYNC_DATE=07/10/2008

051-7546

SHT

D

C

B

A

REV.

A.0.0

OF

9673

8

7 6

5

4

3

2

1

8 7

6

5

4

OMIT

=PP1V8_GPU_FB_VDD

74 74

73 73

8 8

C8500

10UF

1

1

C8501

0.1uF

20%

6.3V
X5R
603

10%
16V

2

2

X5R
402

1

C8502

0.1uF 0.1uF

10%
16V

2

X5R
402

1

2

C8503

0.1uF

10%
16V
X5R
402

1

C8504

2

10%
16V
X5R
402

A11

F12

M12

V11

D

1

C8510

0.1uF

10%
16V

2

X5R
402

C8524

0.1uF

10%
16V
X5R
402

R8533

1/16W
MF-LF

R8534

1.33K

1/16W
MF-LF

1

2

549

VOLTAGE=0.9V

U8500.J1

1

2

1

1%

402

2

1

1%

402

2

FB_B_CLK0_TERM

C8546

0.01UF

1

R8547

243

1%
1/16W
MF-LF
402

2

Connect to designated pin, then GND

=PP1V8_GPU_FB_VDDQ

9

8

1/16W
MF-LF

1.33K

1/16W
MF-LF

1/16W
MF-LF

549

121

1

C8522

0.1uF

10%
16V

2

X5R
402

1

1%

402

2

1

R8532

1%

402

2

1

1%

402

2

1

R8543

121

1%
1/16W
MF-LF
402

2

C8520

=PP1V8_GPU_FB_VREF_B

74

9

10UF

1

20%

6.3V
2

X5R
603

C8521

2

0.1uF

10%
16V
X5R
402

1

R8530

C

R8540

1/16W
MF-LF

FB_B_MA<0>

72 74 94

IN

FB_B_MA<1>

72 74 94

IN

FB_B_LMA<2>

72 94

IN

FB_B_LMA<3>

72 94

IN

FB_B_LMA<4>

72 94

IN

FB_B_LMA<5>

72 94

IN

FB_B_MA<6>

72 74 94

B

A

IN

FB_B_MA<7>

72 74 94

IN

FB_B_MA<8>

72 74 94

IN

FB_B_MA<9>

72 74 94

IN

FB_B_MA<10>

72 74 94

IN

FB_B_MA<11>

72 74 94

IN

FB_B_CKE

72 74 94

IN

FB_B_MA<12>

FB_B_CLK_P<0>

72 94

IN

FB_B_CLK_N<0>

72 94

IN

FB_B_CS0_L

72 74 94

IN

FB_B_WE_L

72 74 94

IN

FB_B_CAS_L FB_B_DQ<1>

72 74 94

IN

FB_B_RAS_L

72 74 94

IN

FB_B_DRAM_RST

72 74 94

IN

FB_B_RDQS<1>

72 94

OUT

FB_B_RDQS<0>

72 94

OUT

FB_B_RDQS<2>

72 94

OUT

FB_B_RDQS<3>

72 94

OUT

FB_B_WDQS<1>

72 94

IN

FB_B_WDQS<0>

72 94

IN

FB_B_WDQS<2>

72 94

IN

FB_B_WDQS<3>

72 94

IN

FB_B_BA<0>

72 74 94

IN

FB_B_BA<1>

72 74 94

IN

FB_B_BA<2>

72 74 94

IN

R8531

VRAM4

1

R8542

1K

5%

402

2

1/16W
MF-LF

VRAM4

R8544

VRAM4

R8548

931

1

C8523

0.1uF

10%
16V

2

X5R
402

1

1

1%

2

402

2

1

121

1%
1/16W
MF-LF

402

2

1

243

1%
1/16W
MF-LF

402

2

C8531

0.01uF

10%
16V
CERM
402

VRAM4

1

R8545

121

1%
1/16W
MF-LF
402

2

FB_B0_ZQ

FB_B0_SEN

1

R8549

100

5%
1/16W
MF-LF
402

2

R8546

243

1/16W
MF-LF

402

FB_B0_MF

1

2

1%

1

C8515

0.1uF

10%
16V

2

X5R
402

U8500.J12

C8525

0.1uF

10%
16V
X5R
402

1

C8526

0.1uF

2

10%
16V
X5R
402

FB_B2_VREF FB_B3_VREF

1

R8535

931

1%
1/16W
MF-LF

402

2

1

10%
16V

CERM

402

NC NC

H11
K10

K11

J11

J10

H10

D10
P10

D11

P11

2

K9

M9
K4
H2
K3
L4
K2
M4

L9
H9

J3

F4
H4
F9

A4
A9
V4

V9

D3

P3

D2

P2

G9
G4
H3

J2

72 73 74

IN IN

76

OMIT

CRITICAL

A0

U8500

A1

(1 OF 2)

A2
A3
A4
A5

MFHIGH

A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*

MFHIGH

RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

MFHIGH

RFU

K12

A12

C12

E12

N12

R12

V12

H12

1

C8532

0.01uF

10%
16V

2

CERM
402

FB_B2_VREF_UNTERM_L
FB_B0_VREF_UNTERM_L

FB_VREF_UNTERM

DM0
DM1

BGA

DM2
DM3

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6

K4J10324QD-HC11

DQ7

32MX32-900MHZ-MFH

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

A2

VDD0
VDD1

F1

VDD2
VDD3

M1

VDD4
VDD5

V2

VDD6
VDD7

K1

VDDA0
VDDA1

A1

VDDQ0
VDDQ1

C1

VDDQ2

C4

VDDQ3

C9

VDDQ4
VDDQ5

E1

VDDQ6

E4

VDDQ7

E9

VDDQ8
VDDQ9

J4

VDDQ10

J9

VDDQ11

N1

VDDQ12

N4

VDDQ13

N9

VDDQ14
VDDQ15

R1

VDDQ16

R4

VDDQ17

R9

VDDQ18
VDDQ19

V1

VDDQ20
VDDQ21

H1

VREF0
VREF1

SSM6N15FEAPE

E3
E10
N10
N3

B2
B3
C2
C3
E2
F3
F2
G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10
T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

CRITICAL

U8500

(2 OF 2)

Q8500

VSS0
VSS1

BGA

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

VSSA0
VSSA1

VSSQ0

K4J10324QD-HC11

VSSQ1

32MX32-900MHZ-MFH

VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

D

SOT563

2

SG

FB_B_DQM_L<1>
FB_B_DQM_L<0>
FB_B_DQM_L<2>
FB_B_DQM_L<3>

FB_B_DQ<12>
FB_B_DQ<8>
FB_B_DQ<11>
FB_B_DQ<10>
FB_B_DQ<13>
FB_B_DQ<15>
FB_B_DQ<14>
FB_B_DQ<9>
FB_B_DQ<6>
FB_B_DQ<5>
FB_B_DQ<3>
FB_B_DQ<4>
FB_B_DQ<0>
FB_B_DQ<2>

FB_B_DQ<7>
FB_B_DQ<21>
FB_B_DQ<16>
FB_B_DQ<19>
FB_B_DQ<17>
FB_B_DQ<20>
FB_B_DQ<22>
FB_B_DQ<18>
FB_B_DQ<23>
FB_B_DQ<26>
FB_B_DQ<27>
FB_B_DQ<31>
FB_B_DQ<28>
FB_B_DQ<24>
FB_B_DQ<25>
FB_B_DQ<29>
FB_B_DQ<30>

A3
A10
G1
G12
L1
L12
V3
V10

J1
J12

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

6

SSM6N15FEAPE

1

Q8500

SOT563

IN
IN
IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

5

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

74 74 73 73

9

8

74

9

3

D

SG

4

72 74 94

72 74 94

72 94

72 94

72 94

72 94

72 74 94

72 74 94

72 74 94

72 74 94

72 74 94

72 74 94

72 74 94

72 74 94 72 74 94

72 94

72 94

72 74 94

72 74 94

72 74 94

72 74 94

72 74 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 74 94

72 74 94

72 74 94

=PP1V8_GPU_FB_VDD

=PP1V8_GPU_FB_VDDQ

1

C8570

10UF

20%

6.3V
2

X5R
603

=PP1V8_GPU_FB_VREF_B

R8590

1/16W
MF-LF

FB_B_MA<0>

IN

FB_B_MA<1>

IN

FB_B_UMA<2>

IN

FB_B_UMA<3>

IN

FB_B_UMA<4>

IN

FB_B_UMA<5>

IN

FB_B_MA<6>

IN

FB_B_MA<7>

IN

FB_B_MA<8>

IN

FB_B_MA<9>

IN

FB_B_MA<10>

IN

FB_B_MA<11>

IN

FB_B_CKE

IN

FB_B_MA<12>

ININ

FB_B_CLK_P<1>

IN

FB_B_CLK_N<1>

IN

FB_B_CS0_L

IN

FB_B_WE_L

IN

FB_B_CAS_L

IN

FB_B_RAS_L

IN

FB_B_DRAM_RST

IN

FB_B_RDQS<6>

OUT

FB_B_RDQS<5>

OUT

FB_B_RDQS<4>

OUT

FB_B_RDQS<7>

OUT

FB_B_WDQS<6>

IN

FB_B_WDQS<5>

IN

FB_B_WDQS<4>

IN

FB_B_WDQS<7>

IN

FB_B_BA<0>

IN

FB_B_BA<1>

IN

FB_B_BA<2>

IN

1

C8550

10UF

20%

6.3V
2

X5R
603

Connect to designated pin, then GND

1

C8571

0.1uF

10%
16V

2

X5R
402

R8580

R8581

VRAM4

1

R8592

1K

5%

402

2

549

1/16W
MF-LF

1.33K

1/16W
MF-LF

121

1/16W
MF-LF

1

C8572

0.1uF

10%
16V

2

X5R
402

1

1%

402

2

1

R8582

1%

402

1%

402

931

1/16W
MF-LF

2

402

VRAM4

1

R8594

1/16W

VRAM4

1

R8593

121

1%
1/16W
MF-LF
402

2

MF-LF

2

R8598

1

C8551

0.1uF

10%
16V

2

X5R
402

1

2

1

1%

2

1

121

1%

402

2

1

243

1%
1/16W
MF-LF

402

2

C8573

0.1uF

10%
16V
X5R
402

FB_B1_VREFFB_B0_VREF

1

C8581

0.01uF

10%
16V

2

CERM
402

1

2

R8596

VRAM4

R8595

121

1%
1/16W
MF-LF
402

FB_B1_ZQ
FB_B1_MF
FB_B1_SEN

1

R8599

100

5%
1/16W
MF-LF
402

2

1

2

1/16W
MF-LF

243

C8552

0.1uF

10%
16V
X5R
402

1

C8574

2

1

1%

402

2

0.1uF

10%
16V
X5R
402

R8583

R8584

1.33K

549

1/16W
MF-LF

402

1/16W
MF-LF

402

VOLTAGE=0.9V

1

2

1

C8553

0.1uF

10%
16V

2

X5R
402

1

C8560

0.1uF

10%
16V

2

X5R
402

U8500.J1

1

C8575

0.1uF

10%
16V

2

X5R
402

1

1%

2

1

1%

2

FB_B_CLK1_TERM

C8596

0.01UF

10%
16V

CERM

402

R8597

243

1%
1/16W
MF-LF
402

K9
H11
K10

M9

K4

H2

K3

L4

K2

M4
K11

L9

H9

J3

J11

J10

F4

H4

F9
H10

A4

A9

V4

V9

D3
D10
P10

P3

D2
D11

P11

P2

G9

G4

H3

J2

R8585

1

2

A0
A1
A2
A3
A4
A5
A6
A7
A8/AP
A9
A10
A11
CKE

A12/CS1*

CK

CK*
CS0*
WE*
CAS*
RAS*

ZQ
MF
SEN

RESET

RDQS0
RDQS1
RDQS2
RDQS3

WDQS0
WDQS1

WDQS2
WDQS3

BA0
BA1
BA2

RFU

3

1

C8554

0.1uF

10%
16V

2

X5R
402

1

C8565

0.1uF

10%
16V

2

X5R
402

U8500.J12

1

C8576

0.1uF

10%
16V

2

X5R
402

1

931

1%
1/16W
MF-LF

402

2

72 73 74
76

OMIT

CRITICAL

U8550

BGA

(1 OF 2)

MFHIGH

32MX32-900MHZ-MFH

MFHIGH

MFHIGH

A2

VDD0

A11

VDD1

F1

VDD2

F12

VDD3

M1

VDD4

M12

VDD5

V2

VDD6

V11

VDD7

K1

VDDA0

K12

VDDA1

A1

VDDQ0

A12

VDDQ1

C1

VDDQ2

C4

VDDQ3

C9

VDDQ4

C12

VDDQ5

E1

VDDQ6

E4

VDDQ7

E9

VDDQ8

E12

VDDQ9

J4

VDDQ10

J9

VDDQ11

N1

VDDQ12

N4

VDDQ13

N9

VDDQ14

N12

VDDQ15

R1

VDDQ16

R4

VDDQ17

R9

VDDQ18

R12

VDDQ19

V1

VDDQ20

V12

VDDQ21

H1

VREF0

H12

VREF1

1

C8582

0.01uF

10%
16V

2

CERM
402

FB_B3_VREF_UNTERM_L
FB_B1_VREF_UNTERM_L

SSM6N15FEAPE

FB_VREF_UNTERM

E3

DM0

E10

DM1

N10

DM2

N3

DM3

B2

DQ0

B3

DQ1

C2

DQ2

C3

DQ3

E2

DQ4

F3

DQ5

F2

DQ6

K4J10324QD-HC11

DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQ7
DQ8
DQ9

T11
T10
M2
L3
N2
M3
R2
R3
T2
T3

G3
B11
B10
C11
C10
E11
F10
F11
G10
M11
L10
N11
M10
R11
R10

OMIT

CRITICAL

U8550

(2 OF 2)

Q8550

VSS0
VSS1

BGA

VSS2
VSS3
VSS4
VSS5
VSS6
VSS7

VSSA0
VSSA1

VSSQ0

K4J10324QD-HC11

VSSQ1

32MX32-900MHZ-MFH

VSSQ2
VSSQ3
VSSQ4
VSSQ5
VSSQ6
VSSQ7
VSSQ8

VSSQ9
VSSQ10
VSSQ11
VSSQ12
VSSQ13
VSSQ14
VSSQ15
VSSQ16
VSSQ17
VSSQ18
VSSQ19

D

SOT563

2

SG

FB_B_DQM_L<6>
FB_B_DQM_L<5>
FB_B_DQM_L<4>
FB_B_DQM_L<7>

FB_B_DQ<49>
FB_B_DQ<50>
FB_B_DQ<48>
FB_B_DQ<51>
FB_B_DQ<53>
FB_B_DQ<55>
FB_B_DQ<54>
FB_B_DQ<52>
FB_B_DQ<41>
FB_B_DQ<42>
FB_B_DQ<40>
FB_B_DQ<47>
FB_B_DQ<44>
FB_B_DQ<45>
FB_B_DQ<43>
FB_B_DQ<46>
FB_B_DQ<34>
FB_B_DQ<35>
FB_B_DQ<33>
FB_B_DQ<32>
FB_B_DQ<37>
FB_B_DQ<38>
FB_B_DQ<39>
FB_B_DQ<36>
FB_B_DQ<56>
FB_B_DQ<57>
FB_B_DQ<63>
FB_B_DQ<59>
FB_B_DQ<58>
FB_B_DQ<62>
FB_B_DQ<61>
FB_B_DQ<60>

A3
A10
G1
G12
L1
L12
V3
V10

J1
J12

B1
B4
B9
B12
D1
D4
D9
D12
G2
G11
L2
L11
P1
P4
P9
P12
T1
T4
T9
T12

6

SSM6N15FEAPE

1

2 1

Page Notes

Power aliases required by this page:

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VREF_B

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
VRAM4

3

SOT563

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

72 94

5

D

SG

4

GDDR3 Frame Buffer B (Top)

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

Q8550

IN
IN
IN
IN

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

DRAWING NUMBER

NONE

SYNC_DATE=07/10/2008

051-7546

SHT

74 96

D

C

B

A

REV.

A.0.0

OF

8

7 6

5

4

3

2

1

8 7

Page Notes

Power aliases required by this page:

- =PP3V3_GPU_VDD33

- =PP3V3_GPI_MIO

- =PP1V2_GPU_PLLVDD

- =PP1V2_GPU_H_PLLVDD

- =PP1V2_GPU_VID_PLLVDD

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

D

=PP3V3_GPU_VDD33

76

75

8

6

C

B

A

=PP3V3_GPU_MIO

76

75

8

=PP1V1_GPU_PLLVDD

8

=PP1V1_GPU_H_PLLVDD

8

=PP1V1_GPU_VID_PLLVDD

8

Typically <??mA

1

C8600

0.47UF

10%

6.3V

2

CERM-X5R
402

1

R8620

49.9

1%
1/16W
MF-LF

402

2

1

R8622

49.9

1%
1/16W
MF-LF

402

2

C8633

4.7UF

20%

6.3V
CERM

603

C8637

4.7UF

20%

6.3V
CERM

603

C8643

4.7UF

20%

6.3V
CERM

603

1

C8601

0.47UF 0.47UF

10%

6.3V

2

CERM-X5R
402

1

R8621

49.9

1%
1/16W
MF-LF
402

2

GPU_MIOA_PD_VDDQ
GPU_MIOB_PD_VDDQ

GPU_MIOA_PU_GND
GPU_MIOB_PU_GND

1

R8623

49.9

1%
1/16W
MF-LF
402

2

L8630

FERR-220-OHM

1 2

1

2

L8635

FERR-220-OHM

1 2

1

2

L8640

FERR-220-OHM

1 2

1

2

76

0402

0402

0402

1

C8602

10%

6.3V

2

CERM-X5R
402

=PP3V3_GPU_MIO

75

8

PP1V1_GPU_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

PP1V1_GPU_H_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

PP1V1_GPU_VID_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V

6

110mA

=PP3V3_GPU_VDD33

76

75

8

6

1

C8690

0.022UF

10%
16V

2

CERM-X5R
402

1

C8691

0.022UF

10%
16V

2

CERM-X5R
402

R8616

75

75

75

75

1/16W
MF-LF

R8617

1/16W
MF-LF

C8630

C8635

10K

402

10K

402

4.7UF

4.7UF

1

C8692

0.022UF

10%
16V

2

CERM-X5R
402

1

C8693

0.022UF

10%
16V

2

CERM-X5R
402

1

5%

2

1

1

C8617

5%

0.1uF

10%
16V

2

X5R
402

2

1

C8694

0.1UF

20%
10V

2

CERM
402

1

C8695

0.1UF

20%
10V

2

CERM
402

1

R8618

10K

5%
1/16W
MF-LF
402

2

1

R8619

10K

5%
1/16W
MF-LF
402

2

1

R8696

40.2K

1%
1/16W
MF-LF
402

2

1

C8696

0.47UF

10%

6.3V

2

CERM-X5R
402 402

1

C8697

0.47UF

10%

6.3V

2

CERM-X5R
402

1

R8697

40.2K

1%
1/16W
MF-LF
402

2

1

C8619

0.1uF

10%
16V

2

X5R
402

1

R8660

10K

5%
1/16W
MF-LF
402

2

1

C8698

1UF

10%

6.3V

2

CERM

76

76

76

76

GPU_TESTMODE_PD

GPU_MIOA_VREF
GPU_MIOB_VREF

GPU_MIOA_PD_VDDQ

75

GPU_MIOA_PU_GND

75

GPU_MIOB_PD_VDDQ

75

GPU_MIOB_PU_GND

75

65mA

1

1

C8631

0.1uF

10%20%

6.3V
CERM

603

6.3V
CERM

603

16V

2

2

X5R
402

76

25mA

1

1

C8636

0.1uF

10%20%
16V

2

2

X5R
402

IN

76

OUT

76

OUT

76

IN

5

GPU_ROM_CS_L
GPU_ROM_SCLK
GPU_ROM_SI
GPU_ROM_SO

GPU_STRAP_REF_3V3_PD
GPU_STRAP_REF_MIOB_PD

1

C8610

1UF

10%

6.3V
2

402

GPU_XTALIN
GPU_XTALOUT

GPU_XTALOUTBUFF

GPU_XTALSSIN

C8611

1UF

J9

VDD33_1

J10

VDD33_2

J11

VDD33_3

J12

VDD33_4

J13

VDD33_5

J25

RFU0

NC

J26

RFU1

NC

AK14

RFU0_GND

K9

RFU1_GND

C3

ROM_CS*

D4

ROM_SCLK

D3

ROM_SI

C4

ROM_SO

N9

STRAP_REF_3V3

M9

STRAP_REF_MIOB

P9

MIOA_VDDQ_1

R9

MIOA_VDDQ_2

AP35

AA9
AB9

AF1

AA7
AA6

AF9

AE9

AD9

T9
U9

W9
Y9

N5

U5
T5

B1
B2

D1

D2

MIOA_VDDQ_3
MIOA_VDDQ_4

MIOB_VDDQ_1
MIOB_VDDQ_2
MIOB_VDDQ_3
MIOB_VDDQ_4

TESTMODE

MIOA_VREF
MIOB_VREF

MIOA_CAL_PD_VDDQ
MIOA_CAL_PU_GND

MIOB_CAL_PD_VDDQ
MIOB_CAL_PU_GND

SP_PLLVDD

PLLVDD

VID_PLLVDD

XTAL_IN
XTAL_OUT

XTAL_OUTBUFF

XTAL_SSIN

1

10%

6.3V
2

CERMCERM

402

50mA

1

1

C8640

20%

6.3V
CERM

603

C8641

0.1uF4.7UF

10%
16V

2

2

X5R
402

4

OMIT

U8000

NB9P-GS

BGA

SYMBOL 6 OF 9

(IPD)

MIOA_CLKOUT

MIOA_CLKOUT*

MIOB_CLKOUT

MIOB_CLKOUT*

GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8

GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
GPIO20
GPIO21
GPIO22
GPIO23

HDA_SDI

HDA_SDO
HDA_SYNC
HDA_BCLK
HDA_RST*

SPDIF

BUFRST*

JTAG_TCK

JTAG_TDI

JTAG_TDO
JTAG_TMS

JTAG_TRST*

MIOA_CLKIN

MIOA_CTL3

MIOA_DE
MIOA_D0
MIOA_D1
MIOA_D2
MIOA_D3
MIOA_D4
MIOA_D5
MIOA_D6
MIOA_D7
MIOA_D8
MIOA_D9

MIOA_D10
MIOA_D11
MIOA_D12
MIOA_D13

MIOA_D14
MIOA_HSYNC
MIOA_VSYNC

MIOB_CLKIN

MIOB_CTL3

MIOB_DE
MIOB_D0
MIOB_D1
MIOB_D2
MIOB_D3
MIOB_D4
MIOB_D5
MIOB_D6
MIOB_D7
MIOB_D8

MIOB_D9
MIOB_D10
MIOB_D11
MIOB_D12
MIOB_D13
MIOB_D14
MIOB_D15
MIOB_D16
MIOB_D17

MIOB_HSYNC
MIOB_VSYNC

THERMDP

THERMDN

PGOOD_OUT*

K1
K2
K3
H3
H2
H1
H4
H5
H6
J7
K4
K5
H7
J4
J6
L1
L2
L4
M4
L7
L5
K6
L6
M6

C7
B7
A7
D7
D6

A5

A4

AP14
AN14
AN16
AR14
AP16

N4
R4
T4
P5
N2
N1
P4
P1
P2
P3
T3
T2
T1
U4
U1
U2
U3
R6
T6
N6
N3
L3

AE1
V4
W4
W3
Y5
Y1
Y2
Y3
AB3
AB2
AB1
AC4
AC1
AC2
AC3
AE3
AE2
U6
W6
Y6
W5
W7
V7
W1
W2

B5
B4

C5

GPU_GPIO_0
GPU_GPIO_1
GPU_GPIO_2
GPU_GPIO_3
GPU_GPIO_4
GPU_GPIO_5
GPU_GPIO_6
GPU_GPIO_7
GPU_GPIO_8
GPU_GPIO_9
GPU_GPIO_10
GPU_GPIO_11
GPU_GPIO_12
GPU_GPIO_13
GPU_GPIO_14
GPU_GPIO_15
GPU_GPIO_16
GPU_GPIO_17
GPU_GPIO_18
GPU_GPIO_19
GPU_GPIO_20
GPU_GPIO_21
GPU_GPIO_22
GPU_GPIO_23

GPU_HDA_SDI
GPU_HDA_SDO
GPU_HDA_SYNC
GPU_HDA_BCLK
GPU_HDA_RST_L

GPU_SPDIF

TP_GPU_BUFRST_L

GPU_JTAG_TCK
GPU_JTAG_TDI
GPU_JTAG_TDO
GPU_JTAG_TMS
GPU_JTAG_TRST_L

GPU_MIOA_CLKIN
GPU_MIOA_CLKOUT_P
GPU_MIOA_CLKOUT_N
GPU_MIOA_CTL3
GPU_MIOA_DE
GPU_MIOA_D<0>
GPU_MIOA_D<1>
GPU_MIOA_D<2>
GPU_MIOA_D<3>
GPU_MIOA_D<4>
GPU_MIOA_D<5>
GPU_MIOA_D<6>
GPU_MIOA_D<7>
GPU_MIOA_D<8>
GPU_MIOA_D<9>
GPU_MIOA_D<10>
GPU_MIOA_D<11>
GPU_MIOA_D<12>
GPU_MIOA_D<13>
GPU_MIOA_D<14>
GPU_MIOA_HSYNC
GPU_MIOA_VSYNC

GPU_MIOB_CLKIN
GPU_MIOB_CLKOUT_P
GPU_MIOB_CLKOUT_N
GPU_MIOB_CTL3
GPU_MIOB_DE
GPU_MIOB_D<0>
GPU_MIOB_D<1>
GPU_MIOB_D<2>
GPU_MIOB_D<3>
GPU_MIOB_D<4>
GPU_MIOB_D<5>
GPU_MIOB_D<6>
GPU_MIOB_D<7>
GPU_MIOB_D<8>
GPU_MIOB_D<9>
GPU_MIOB_D<10>
GPU_MIOB_D<11>
GPU_MIOB_D<12>
GPU_MIOB_D<13>
GPU_MIOB_D<14>
GPU_STRAP<0>
GPU_STRAP<1>
GPU_STRAP<2>
GPU_MIOB_HSYNC
GPU_MIOB_VSYNC

GPU_THERMD_P
GPU_THERMD_N

TP_GPU_PGOOD_OUT_L

3

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

OUT

76

OUT

76

OUT

76

OUT

76

OUT

76

IN

OUT

6

IN

6

IN

6

OUT

6

IN

6

IN

76

IN

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

IN

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

BI

76

IN

76

OUT

OUT

2 1

NV G96 GPIO/MIO/Misc

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

APPLE INC.

SIZE

D

SCALE

NONE

051-7546

SHT

75

SYNC_DATE=07/10/2008

REV.

A.0.0

OF

96

D

C

B

A

8

7 6

5

4

3

2

1

8 7

6

5

4

3

Renamed signals

Native Func

GPU_GPIO_0

75

GPU_GPIO_1

75

GPU_GPIO_2

75

GPU_GPIO_3

75

GPU_GPIO_4

75

GPU_GPIO_5

75

D

GPU_GPIO_6

75

GPU_GPIO_7

75

GPU_GPIO_8

75

GPU_GPIO_9

75

GPU_GPIO_10

75

GPU_GPIO_11

75

GPU_GPIO_12

75

GPU_GPIO_13

75

GPU_GPIO_14

75

GP

HPDC

LCD0_BL_PWM

LCD0_VDD

LCD0_BL_EN

VID0

VID1

VID2/MEM_VID

THERM

FAN_PWM

MEM_VREF

SLI_SYNC

AC_DET

PWR_CTL0

PWR_CTL1

Config Straps

=PP3V3_GPU_MIO

76

8

75

OMIT

R8707

C

B

75

75

75

75

75

75

GPU_ROM_SI

OUT

GPU_ROM_SO

IN

GPU_ROM_SCLK

IN

76

75

BI

BI

BI

8

GPU_STRAP<0>

GPU_STRAP<1>

GPU_STRAP<2>

OMIT

R8708

45.3K

=PP3V3_GPU_MIO

R8701

45.3K

NO STUFF

R8702

=PP3V3_GPU_VDD33

76

75

8

6

DP_CA_DET_EG_FET

EG_DP_CA_DET

76

A

2.0K

1/16W
MF-LF

1/16W
MF-LF

1/16W
MF-LF

2.0K

1/16W
MF-LF

5%

402

1%

402

1%

402

5%

402

1

R8709

2

NO STUFF

1

R8710

2

NO STUFF

1

R8703

2

1

R8704

2

R8742

GPIOs

1

4.99K

1%
1/16W
MF-LF

402

2

1

2.0K

5%
1/16W
MF-LF

402

2

1

10K

1%
1/16W
MF-LF

402

2

1

10K

1%
1/16W
MF-LF

402

2

1

100K

1%
1/16W
MF-LF

402

2

NC_GPU_GPIO_0

MAKE_BASE=TRUE

DP_EG_HPD

MAKE_BASE=TRUE

TP_LVDS_EG_BKL_PWM

MAKE_BASE=TRUE

EG_LCD_PWR_EN

MAKE_BASE=TRUE

EG_BKLT_EN

MAKE_BASE=TRUE

TP_GPU_GSTATE<0>

MAKE_BASE=TRUE

TP_GPU_GSTATE<1>

MAKE_BASE=TRUE

GPIO7_FBVDD_ALTVO

MAKE_BASE=TRUE

SMC_GFX_OVERTEMP_R_L

MAKE_BASE=TRUE

SMC_GFX_THROTTLE_R_L

MAKE_BASE=TRUE

FB_VREF_UNTERM

MAKE_BASE=TRUE

GPU_VCORE_VID0

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

TP_GPU_VCORE_VID3

MAKE_BASE=TRUE

NO STUFF

1

R8711

4.99K

1%
1/16W
MF-LF

402

2

1

R8712

15.0K

1%
1/16W
MF-LF

402

2

NO STUFF

1

R8705

10K

1%
1/16W
MF-LF

402

2

1

R8706

45.3K

1%
1/16W
MF-LF

402

2

DP_CA_DET_EG_FET

Q8742

SOD-VESM-HF

SSM3K15FV

1

GS

2

R8743

0

1 2

5%
1/16W
MF-LF

402

DP_CA_DET_EG_PLD

80

IN

83

76

83

76

76

82

76

76

76

74

73

72

78

OUT

78

OUT

78

OUT

Physical
Strapping Pin

ROM_SO
ROM_SCLK
ROM_SI
STRAP 2
STRAP 1
STRAP 0

Strap S1/S2 Bit[3:0] PU/PD Rval
0 0000 PD 5k
1 0001 PD 10k
2 0010 PD 15k
3 0011 PD 20k
4 0100 PD 25k
5 0101 PD 30k
6 0110 PD 35k
7 0111 PD 45k

PART NUMBER

114S0378

114S0361

114S0343

114S0331

114S0378

114S0361

D

DP_CA_DET

3

DP_CA_DET_EG

XCLK_277
PCI_DEVID[4]
RAMCFG[3]
PCI_DEVID[3]
3GIO_PADCFG[3]
USER[3]

QTY

1

1

1

1

1

1

79

76

75

76 80

IN

76 80

BI

9

80

IN

9

80

BI

80 81 83

IN

83

IN

GPU_GPIO_15

75

GPU_GPIO_16

75

GPU_GPIO_17

75

GPU_GPIO_18

75

GPU_GPIO_19

75

GPU_GPIO_20

75

GPU_GPIO_21

75

GPU_GPIO_22

75

GPU_GPIO_23

75

DESCRIPTION

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF

RES,MTL FILM,1/16W,30.1K,1,0402,SMD,LF

RES,MTL FILM,1/16W,20.0K,1,0402,SMD,LF

RES,MTL FILM,1/16W,15.0K,1,0402,SMD,LF

RES,MTL FILM,1/16W,45.3K,1,0402,SMD,LF

RES,MTL FILM,1/16W,30.1K,1,0402,SMD,LF

=PP3V3_S0_DDC_LCD

8

7

=PP3V3_GPU_VDD33

8

6

DP_EG_DDC_CLK

DP_EG_DDC_DATA

DP_IG_DDC_CLK

DP_IG_DDC_DATA

Native Func

HPDE

DVI_MODE0

HDMI_DETECT0

DVI_MODE1

HDMI_DETECT1

HPDD

HPDF

SWAPRDY_A

GP

Strapping Bit 2Strapping Bit 3
TVMODE[2]
SUB_VENDOR
RAMCFG[2]
PCI_DEVID[2]
3GIO_PADCFG[2]
USER[2]

Strap S1/S2 Bit[3:0] PU/PD Rval
8 1000 PU 5k
9 1001 PU 10k
A 1010 PU 15k
B 1011 PU 20k
C 1100 PU 25k
D 1101 PU 30k
E 1110 PU 35k
F 1111 PU 45k

Strapping Bit 1
TVMODE[1]
SLOT_CLK_CFG
RAMCFG[1]
PCI_DEVID[1]
3GIO_PADCFG[1]
USER[1]

REFERENCE DES

1

R8750

4.7K

5%
1/16W 1/16W
MF-LF

402

2

R8751

4.7K

MF-LF

1

R8752

4.7K

5%

402

5%
1/16W
MF-LF

402

2

GPIOs

R8708

R8708

R8708

R8708

R8707

R8707

1

R8753

2

4.7K

1/16W
MF-LF

5%

402

NC_GPU_GPIO_15

MAKE_BASE=TRUE

EG_DP_CA_DET

NC_GPU_GPIO_17

MAKE_BASE=TRUE

NC_GPU_GPIO_18

MAKE_BASE=TRUE

NC_GPU_GPIO_19

MAKE_BASE=TRUE

NC_GPU_GPIO_20

MAKE_BASE=TRUE

NC_GPU_GPIO_21

MAKE_BASE=TRUE

NC_GPU_GPIO_22

MAKE_BASE=TRUE

NC_GPU_GPIO_23

MAKE_BASE=TRUE

CRITICAL

1

2

NO_TEST=TRUE

Strapping Bit 0
TVMODE[0]
PEX_PLLEN_TERM100
RAMCFG[0]
PCI_DEVID[0]
3GIO_PADCFG[0]
USER[0]

BOM OPTION

VRAM_512_SAMSUNG

VRAM_512_QIMONDA

VRAM_256_SAMSUNG

VRAM_256_HYNIX

VRAM_1024_SAMSUNG

VRAM_1024_QIMONDA

=PP3V3_GPU_VDD33

76

75

8

6

76

76

76

76 94

IN

75 76

OUT

SMC_GFX_OVERTEMP_R_L

SMC_GFX_THROTTLE_R_L

1

1/16W
MF-LF

R8793

1K

5%

1/16W
MF-LF

402

2

R8792

GPU_XTALOUT

76

75

MAKE_BASE=TRUE

GPU_CLK27M

94

76

MAKE_BASE=TRUE

GPU_CLK27M_SS

94

MAKE_BASE=TRUE

GPU_TDIODE_P

95

48

MAKE_BASE=TRUE

GPU_TDIODE_N

95

48

MAKE_BASE=TRUE

LVDS_EG_DDC_CLK

80

MAKE_BASE=TRUE

LVDS_EG_DDC_DATA

80

MAKE_BASE=TRUE

DP_EG_DDC_CLK

76 77

80

MAKE_BASE=TRUE

76

DP_EG_DDC_DATA

80

MAKE_BASE=TRUE

GPU_XTALOUT

GPU_XTALIN

GPU_XTALSSIN

GPU_THERMD_P

GPU_THERMD_N

GPU_I2CA_SCL

GPU_I2CA_SDA

GPU_I2CB_SCL

GPU_I2CB_SDA

Unused I2C Buses

NC_GPU_I2CC_SCL

MAKE_BASE=TRUE

NC_GPU_I2CC_SDA

MAKE_BASE=TRUE

NC_GPU_I2CD_SCL

MAKE_BASE=TRUE

NC_GPU_I2CD_SDA

MAKE_BASE=TRUE

NC_GPU_I2CE_SCL

MAKE_BASE=TRUE

NC_GPU_I2CE_SDA

MAKE_BASE=TRUE

NC_GPU_I2CH_SCL

MAKE_BASE=TRUE

NC_GPU_I2CH_SDA

MAKE_BASE=TRUE

G96 HDCP ROM APN is 341S2272, blank device is 335S0574.

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

I2CS ties into SMBus connection page

(I2CS requires pullups even if not used)

GPU_I2CC_SCL

GPU_I2CC_SDA

GPU_I2CD_SCL

GPU_I2CD_SDA

GPU_I2CE_SCL

GPU_I2CE_SDA

GPU_I2CH_SDA

GPU_I2CH_SCL

GPU 27MHz Crystal

C8780

NC

2 4

NC

C8781

SMC_GFX_OVERTEMP_L

4025%01/16W

SMC_GFX_THROTTLE_L

4025%01/16W

EG_LCD_PWR_EN

EG_BKLT_EN

GPIO7_FBVDD_ALTVO

FB_VREF_UNTERM

1

1K

5%

402

2

GPU_CLK27M

NO STUFF

R8782

GPU_XTALOUT

1

R8796

2.2K

5%
1/16W
MF-LF

402

2

1

R8794

1K

5%
1/16W
MF-LF

402

2

10M

5%
1/16W
MF-LF

402

R8797

2.2K

1/16W
MF-LF

NO STUFF

R8795

1/16W
MF-LF

1

2

5%

402

1K

5%

402

R8783

1 2

1/16W
MF-LF

1

2

1

2

0

GPU_CLK27M_XTALOUT_R

5%

402

R8798
R8799

1 2

1 2

CRITICAL

Y8780

27MHZ

SM-2

1 3

MF-LF

MF-LF

12pF

1 2

5%

50V

CERM

402

12pF

1 2

5%

50V

CERM

402

NC_GPU_SPDIF

75

76

MAKE_BASE=TRUE

NC_CPU_HDA_SDI

75

MAKE_BASE=TRUE

NC_CPU_HDA_SD0

75

76

MAKE_BASE=TRUE

NC_CPU_HDA_SYNC

75

MAKE_BASE=TRUE

NC_CPU_HDA_BCLK

75

MAKE_BASE=TRUE

NC_CPU_HDA_RST_L

MAKE_BASE=TRUE

NC_FBA_MA<13>

77

MAKE_BASE=TRUE

NC_FBB_MA<13>

77

MAKE_BASE=TRUE

NC_FBA_CMD28

MAKE_BASE=TRUE

NC_FBC_CMD28

77

MAKE_BASE=TRUE

NC_FBA_CMD29

MAKE_BASE=TRUE

NC_FBC_CMD29

MAKE_BASE=TRUE

NC_FBA_CMD30

77

MAKE_BASE=TRUE

NC_FBC_CMD30

77

MAKE_BASE=TRUE

NC_GPU_ROM_CS_L

77

MAKE_BASE=TRUE

NC_FB_A_CS1_L

77

MAKE_BASE=TRUE

NC_FB_B_CS1_L

77

MAKE_BASE=TRUE

77

77

TP_LVDS_EG_B_CLK_P

77

MAKE_BASE=TRUE

TP_LVDS_EG_B_CLK_N

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_P<3>

MAKE_BASE=TRUE

NC_LVDS_EG_A_DATA_N<3>

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_P<3>

MAKE_BASE=TRUE

NC_LVDS_EG_B_DATA_N<3>

MAKE_BASE=TRUE

G96 MIOA_DE and MIOA_D<9..0> are used as Debug Port.

NC_GPU_MIOA_CLKOUT_P

MAKE_BASE=TRUE

NC_GPU_MIOA_CLKOUT_N

MAKE_BASE=TRUE

NC_GPU_MIOA_CTL3

MAKE_BASE=TRUE

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

TP_GPU_MIOA_D<9..0>

MAKE_BASE=TRUE

NC_GPU_MIOA_CLKIN

MAKE_BASE=TRUE

NC_GPU_MIOA_D<14..10>

MAKE_BASE=TRUE

NC_GPU_MIOA_HSYNC

MAKE_BASE=TRUE

NC_GPU_MIOA_VSYNC

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKIN

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKOUT_P

MAKE_BASE=TRUE

NC_GPU_MIOB_CLKOUT_N

MAKE_BASE=TRUE

NC_GPU_MIOB_CTL3

MAKE_BASE=TRUE

NC_GPU_MIOB_DE

MAKE_BASE=TRUE

NC_GPU_MIOB_D<14..0>

MAKE_BASE=TRUE

NC_GPU_MIOB_VSYNC

MAKE_BASE=TRUE

NC_GPU_MIOB_HSYNC

MAKE_BASE=TRUE

OUT

OUT

OUT

OUT

OUT

OUT

Isolation FETs for DP MUX inputs

2 1

Unused signals

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE
NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

Unused Clocks

GPU_XTALSSIN

76

75

GPU_XTALOUTBUFF

75

1

R8780

10K

5%
1/16W
MF-LF

402

2

42

42

76 83

76 83

76 82

72 73 74 76

SYNC_MASTER=MUXGFX

APPLE INC.

G96 GPIOs & Straps

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

SCALE

GPU_SPDIF

GPU_HDA_SDI

GPU_HDA_SDO

GPU_HDA_SYNC

GPU_HDA_BCLK

GPU_HDA_RST_L

FB_A_MA<13>

FB_B_MA<13>

TP_FBA_CMD28

TP_FBC_CMD28

TP_FBA_CMD29

TP_FBC_CMD29

TP_FBA_CMD30

TP_FBC_CMD30

GPU_ROM_CS_L

FB_A_CS1_L

FB_B_CS1_L

LVDS_EG_B_CLK_P

LVDS_EG_B_CLK_N

LVDS_EG_A_DATA_P<3>

LVDS_EG_A_DATA_N<3>

LVDS_EG_B_DATA_P<3>

LVDS_EG_B_DATA_N<3>

GPU_MIOA_CLKOUT_P

GPU_MIOA_CLKOUT_N

GPU_MIOA_CTL3

GPU_MIOA_DE

GPU_MIOA_D<9..0>

GPU_MIOA_CLKIN

GPU_MIOA_D<14..10>

GPU_MIOA_HSYNC

GPU_MIOA_VSYNC

GPU_MIOB_CLKIN

GPU_MIOB_CLKOUT_P

GPU_MIOB_CLKOUT_N

GPU_MIOB_CTL3

GPU_MIOB_DE

GPU_MIOB_D<14..0>

GPU_MIOB_VSYNC

GPU_MIOB_HSYNC

GPU_SS_INT

DRAWING NUMBER

R8781

1/16W
MF-LF

10K

1

5%

402

2

051-7546

SHT

NONE

75

75

75

75

75

75

72

72

72

72

72

72

72

72

75

72

72

77

77

77

77

77

77

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

75

SYNC_DATE=07/09/2008

REV.

A.0.0

OF

9676

D

C

B

A

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

Page Notes

Power aliases required by this page:

- =PP1V8_GPU_IFPX

- =PP3V3_GPU_IFPCD_IOVDD

Signal aliases required by this page:
(NONE)

BOM options provided by this page:
(NONE)

D

1

R8855

1K

1%
1/16W
MF-LF
402

2

C

1

R8856

10K

5%
1/16W
MF-LF

2

B

A

1

R8850

1K

1%
1/16W
MF-LF
402

2

PP1V1_GPU_IFPEF_IOVDD_F

PP1V8_GPU_IFPEF_PLLVDD_F

1

R8857

10K

5%
1/16W
MF-LF
402402

2

Sum of peak currents: 240mA

=PP1V8_GPU_IFPX

8

GPU_IFPEF_RSET
GPU_IFPCD_RSET
GPU_IFPAB_RSET

1

R8851

1K

1%
1/16W
MF-LF
402

2

=PP1V1_GPU_IFPCD_IOVDD

8

77

77

Power inputs must be pulled down if not used

L8800

FERR-220-OHM

1 2

0402

C8800

77

77

77

L8805

FERR-220-OHM

1 2

0402

C8805

L8810

FERR-220-OHM

1 2

0402

C8810

L8815

FERR-220-OHM

1 2

0402

C8815

?mA peak per diff pair
?mA peak for all pairs

1

4.7UF

20%

6.3V
2

CERM

603

80mA peak

1

4.7UF

20%

6.3V
2

CERM

603

?mA peak per diff pair
?mA peak for all pairs

1

4.7UF

20%

6.3V
2

CERM

603

160mA peak

1

4.7UF

20%

6.3V
2

CERM

603

1

C8801

0.1UF

20%
10V

2

CERM

402

Place at AG9

C8806

0.1UF

20%
10V

CERM

402

C8811

0.1UF

10V

CERM

402

Place at AJ8

I2CS must be pulled up if not used
I2CS addr fixed at 0x9E,0x9F

C8816

0.1UF

20%
10V

CERM

402

Place at AG10

PP1V8_GPU_IFPAB_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

1

2

1

2

Place at AK8

PP1V8_GPU_IFPCD_PLLVDD_F

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V

1

2

1

R8852

10K

5%
1/16W
MF-LF
402

2

PP1V8_GPU_IFPAB_IOVDD_F

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm

1

C8803

0.1UF

20%
10V

2

CERM

402

PP1V1_GPU_IFPCD_IOVDD_F

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=1.1V

1

C8813

0.1UF

20%20%
10V

2

CERM

402

I2CS must be pulled up if not used.
I2CS addr fixed at 0x9E,0x9F

GPU_DACB_VDD
GPU_DACC_VDD

1

1

R8853

R8854

10K

10K

5%

5%

1/16W

1/16W

MF-LF

MF-LF

402

2

402

2

VOLTAGE=1.8V

PP1V1_GPU_IFPCD_IOVDD_F

77

PP1V1_GPU_IFPEF_IOVDD_F

77

GPU_IFPAB_RSET

77

PP1V8_GPU_IFPCD_PLLVDD_F

77

GPU_IFPCD_RSET

77

PP1V8_GPU_IFPEF_PLLVDD_F

77

GPU_IFPEF_RSET

77

GPU_I2CA_SCL

76

BI

GPU_I2CA_SDA

76

BI

GPU_I2CC_SCL

76

BI

GPU_I2CC_SDA

76

BI

77

=GPU_I2CS_SCL

45

BI

=GPU_I2CS_SDA

45

BI

GPU_I2CH_SCL

76

BI

GPU_I2CH_SDA

76

BI

GPU_I2CB_SCL

76

BI

GPU_I2CB_SDA

76

BI

GPU_I2CD_SCL

76

BI

GPU_I2CD_SDA

76

BI

GPU_I2CE_SCL

76

BI

GPU_I2CE_SDA

76

BI

GPU_DACA_VDD

77

NC
NC

NC
NC

NC

AG10

AJ11

AJ12

AG9

AJ8
AK8
AE7
AD7

AK9

AJ9
AK7

AJ6
AL1

AK12
AK13

AC6

AC5
AB6

AG7

AK6
AH7

G1
G4

E3
E4

E2
E1

F6
G6

G3
G2

F4
G5

D5
E5

U8000

NB9P-GS

SYMBOL 5 OF 9

IFPA_IOVDD
IFPB_IOVDD
IFPC_IOVDD
IFPD_IOVDD
IFPE_IOVDD
IFPF_IOVDD

IFPAB_PLLVDD
IFPAB_RSET

IFPCD_PLLVDD
IFPCD_RSET

IFPEF_PLLVDD
IFPEF_RSET

I2CA_SCL
I2CA_SDA

I2CC_SCL
I2CC_SDA

I2CS_SCL
I2CS_SDA

I2CH_SCL
I2CH_SDA

I2CB_SCL
I2CB_SDA

I2CD_SCL
I2CD_SDA

I2CE_SCL
I2CE_SDA

DACA_VDD

DACA_VREF
DACA_RSET

DACB_VDD

DACB_VREF
DACB_RSET

DACC_VDD

DACC_VREF
DACC_RSET

OMIT

BGA

IFPA_TXC

IFPA_TXC*

IFPA_TXD0

IFPA_TXD0*

IFPA_TXD1

IFPA_TXD1*

IFPA_TXD2

IFPA_TXD2*

IFPA_TXD3

IFPA_TXD3*

IFPB_TXC

IFPB_TXC*

IFPB_TXD4

IFPB_TXD4*

IFPB_TXD5

IFPB_TXD5*

IFPB_TXD6

IFPB_TXD6*

IFPB_TXD7

IFPB_TXD7*

IFPC_AUX

IFPC_AUX*

IFPC_L0

IFPC_L0*

IFPC_L1

IFPC_L1*

IFPC_L2

IFPC_L2*

IFPC_L3

IFPC_L3*

IFPD_AUX

IFPD_AUX*

IFPD_L0

IFPD_L0*

IFPD_L1

IFPD_L1*

IFPD_L2

IFPD_L2*

IFPD_L3

IFPD_L3*

IFPE_AUX

IFPE_AUX*

IFPE_L0

IFPE_L0*

IFPE_L1

IFPE_L1*

IFPE_L2

IFPE_L2*

IFPE_L3

IFPE_L3*

IFPF_AUX

IFPF_AUX*

IFPF_L0

IFPF_L0*

IFPF_L1

IFPF_L1*

IFPF_L2

IFPF_L2*

IFPF_L3

IFPF_L3*

DACA_RED

DACA_GREEN

DACA_BLUE

DACA_HSYNC
DACA_VSYNC

DACB_RED

DACB_GREEN

DACB_BLUE

DACB_CSYNC

DACC_RED

DACC_GREEN

DACC_BLUE

DACC_HSYNC
DACC_VSYNC

AM11
AM12

AM8
AL8

AM10

AM9
AK10
AL10
AK11
AL11

AP13
AN13

AN8
AP8
AP10
AN10
AR11
AR10
AN11
AP11

AP2
AN3

AM7
AM6
AL5
AM5
AM3
AM4
AP1
AR2

AP4
AN4

AR8
AR7
AP7
AN7
AN5
AP5
AR5
AR4

AE4
AD4

AH6
AH5
AH4
AG4
AF4
AF5
AE6
AE5

AF3
AF2

AL2
AL3
AJ3
AJ2
AJ1
AH1
AH2
AH3

AM15
AM14
AL14

AM13
AL13

AA4
AB4
Y4

AB5

AK4
AL4
AJ4

AM1
AM2

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC

NC
NC

NC
NC
NC

NC

NC
NC
NC

NC
NCNC

LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N

LVDS_EG_A_DATA_P<0>
LVDS_EG_A_DATA_N<0>
LVDS_EG_A_DATA_P<1>
LVDS_EG_A_DATA_N<1>
LVDS_EG_A_DATA_P<2>
LVDS_EG_A_DATA_N<2>
LVDS_EG_A_DATA_P<3>
LVDS_EG_A_DATA_N<3>

LVDS_EG_B_CLK_P
LVDS_EG_B_CLK_N

LVDS_EG_B_DATA_P<0>
LVDS_EG_B_DATA_N<0>
LVDS_EG_B_DATA_P<1>
LVDS_EG_B_DATA_N<1>
LVDS_EG_B_DATA_P<2>
LVDS_EG_B_DATA_N<2>
LVDS_EG_B_DATA_P<3>
LVDS_EG_B_DATA_N<3>

DP_EG_AUX_CH_P
DP_EG_AUX_CH_N

DP_EG_ML_P<0>
DP_EG_ML_N<0>
DP_EG_ML_P<1>
DP_EG_ML_N<1>
DP_EG_ML_P<2>
DP_EG_ML_N<2>
DP_EG_ML_P<3>
DP_EG_ML_N<3>

83 94

OUT

83 94

OUT

83 94

OUT

83 94

OUT

83 94

OUT

83 94

OUT

83 94

OUT

83 94

OUT

76

OUT

76

OUT

76

OUT

76

OUT

83 94

OUT

83 94

OUT

83 94

OUT

83 94

OUT

83 94

OUT

83 94

OUT

76

OUT

76

OUT

80 94

OUT

80 94

OUT

80 94

OUT

80 94

OUT

80 94

OUT

80 94

OUT

80 94

OUT

80 94

OUT

1

R8861

1K

5%
1/16W
MF-LF
402

2

NO STUFF

1

R8860

1K

5%
1/16W
MF-LF
402

2

80 94

OUT

80 94

OUT

D

C

B

NV G96 Video Interfaces

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=07/10/2008

051-7546

SHT

77 96

A

REV.

A.0.0

OF

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

GPU VCore Regulator

=PP5V_S3_GPUVCORE

8

D

=PP3V3_GPU_VCORELOGIC

8

78

R8907

1/16W
MF-LF

C

GPU_VDD_SENSE

70

MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=1.25V

GPU_GND_SENSE

70

MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.25 mm
VOLTAGE=0V

PLACEMENT_NOTE=Place R8920 at U8900
PLACEMENT_NOTE=Place R8908 at U8900

B

GPU_VCORE_VID0

76

IN

GPU_VCORE_VID1

76

IN

A

GPU_VCORE_VID2

76

IN

R8911

1 2

1/16W
MF-LF

R8904

1 2

1/16W
MF-LF

1

1

10K

402

R8910

10K

5%

5%
1/16W
MF-LF
402

2

2

R8920

20

1 2

5%
1/16W
MF-LF

402

R8908

20

1 2

5%
1/16W
MF-LF

402

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.3MM

1

R8950

374K

1%
1/16W
MF-LF
402

2

1

R8951

4.99K

1%
1/16W
MF-LF
402

2

GFXIMVP6_VDIFF_RC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.3MM

8

78

R8986

0

5%
1/16W
MF-LF

402

R8990

0

1 2

5%
1/16W
MF-LF

402

R8994

0

1 2

5%
1/16W
MF-LF

402

1

5%

402

PP5V_S5_GFXIMVP6_PVCC

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

10

1%

402

1

2

C8920

0.001UF

10%
50V
CERM
402

1

C8901

1uF

10%
10V

2

X5R
402

C8950

180PF

5%

50V

CERM

402

C8951

560PF

=PP3V3_GPU_VCORELOGIC

12

GPUVID0_1

R8987

PP5V_S5_GFXIMVP6_VDD

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=5V

R8905

150K

2 1

1%

1/16W

C8904

MF-LF

402

0.033UF

12

10%
16V
X5R
402

47

GPUVCORE_PGOOD

68

OUT

GFXIMVP6_VID0

78

GFXIMVP6_VID1

78

GFXIMVP6_VID2

78

GFXIMVP6_VID3

78

GFXIMVP6_VID4

78

=GPUVCORE_EN

68 83

IN

GFXIMVP6_AF_EN
GFXIMVP6_FDE

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSEN_P

95

GFXIMVP6_VSEN_N

95

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

C8923

0.001UF

10%
50V

2

CERM
402

(GFXIMVP6_AGND)

GFXIMVP6_VW

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

1

R8909

12

1 2

10%
50V

CERM

402

2.2K

1/16W
MF-LF

402

4.99K

1/16W
MF-LF

1

5%

2

1

1%

2

402

2

1

C8952

68PF

5%
50V

2

CERM
402-1

1

R8953

2.21K

1%
1/16W
MF-LF
402

2

GFXIMVP6_VDIFF

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GPUVID1_1

R8984

2.2K

1/16W
MF-LF

C8922

1000PF

10%
25V
X7R
402

GFXIMVP6_COMP

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_FB

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

5%

402

GPUVID1_0

R8985

2.2K

5%
1/16W
MF-LF

402

C8902

4.7UF

X5R-CERM

GFXIMVP6_RBIAS

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_SOFT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_IMON

C8921

0.001UF

10%
50V

CERM

402

GPUVID2_1

R8982

2.2K

1/16W
MF-LF

1

5%

402

2

GPUVID2_0

R8983

2.2K

5%
1/16W
MF-LF

402

20%

6.3V
402

1

2

R8980

1

2

1/16W
MF-LF

RBIAS

SOFT

IMON

PGOOD
VID0
VID1
VID2
VID3
VID4
VR_ON
AF_EN
FDE

VSEN
RTN

VW

COMP

FB

VDIFF

402

1

C8903

0.01uF

10%
16V

2

CERM
402

VDD

CRITICAL

U8900

ISL6263C

PGND

XW8900

0

5%

PVCC

QFN

THRM_PAD

VSS

SM

1 2

GFXIMVP6_VID0
GFXIMVP6_VID1
GFXIMVP6_VID2
GFXIMVP6_VID3
GFXIMVP6_VID4

1

R8988

0

5%
1/16W
MF-LF
402

2

CRITICAL

C8931

22UF

POLY-TANT

CASE-D2-SM

VIN

UGATE

BOOT

PHASE

LGATE

VO

OCSET

ISP
ISN

ICOMP

CRITICAL

1

C8930

20%
25V

1

2

22UF

2

POLY-TANT

CASE-D2-SM

GFXIMVP6_VIN

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_UGATE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_BOOT

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_PHASE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

GFXIMVP6_LGATE

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

C8953

680pF

10%
50V
CERM
402

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_OCSET

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSUM

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DFB

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DROOP

MIN_LINE_WIDTH=0.3MM
MIN_NECK_WIDTH=0.2MM

GND_GFXIMVP6_AGND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

78

78

78

78

78

=PPVIN_GPU_GPUVCORE

8

1

C8932

1

1UF

20%
25V

2

R8902

9.76K

1/16W
MF-LF

402

1%

10%
25V

2

X5R
603-1

R8900

2

C8971

1

C8956

0.22UF

5.11K

1 2

1/16W
MF-LF

68PF

1 2

5%

50V

CERM

402-1

C8933

1UF

10%
25V
X5R

603-1

10%
16V
X7R
603

1%

402

C8972

1

2

1

2

1

R8901

5.11K

1%
1/16W
MF-LF
402

2

0.1uF

10%
16V
X5R
402

1

C8934

1000PF

10%
25V

2

X7R
402

R8930

1/16W
MF-LF

402

1

2

1

1K

5%

2

4

R8903

C8906

4

1/16W
MF-LF

330PF

5

1 2 3

5

CRITICAL

Q8951

RJK0328DPB

LFPAK-HF

1 2 3

GFXIMVP6_PHASE_VSUM

MIN_LINE_WIDTH=0.3MM

1

MIN_NECK_WIDTH=0.3MM

1K

1%

402

2

1

5%

50V

2

COG
402

CRITICAL

Q8950

RJK0305DPB

LFPAK-HF

CRITICAL

L8920

0.68UH-16A

1 2

PCMB065T-SM

(PPVCORE_GPU_REG)

GPU VCore Setpoints

Voltage

VID3

VID2 VID1

1

1 1
1

1
0

1 1

VID0

0.90125V

1
1
1

0

0.92700V

1.00425V

Other VID states may not be valid

M98 Default Vcore Setpoints

BOM GROUP
GPUVID_0P90V
GPUVID_1P00V

GPUVID2_1,GPUVID1_1,GPUVID0_1
GPUVID2_0,GPUVID1_1,GPUVID0_1

PPVCORE_GPU_REG_R

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

Max Batt
M98

-

-

BOM OPTIONS

M98

-

R8940

0.001

1%
1W
MF

1206

1 2
3 4

C8969

1000PF

Max perfBalanced

-

-

M98

10%
25V
X7R
402

D

Vout = 1.05V - 0.96V

=PPVCORE_GPU_REG

1

C8966

1

2

10UF

1

C8967

10UF

20%

6.3V

2

X5R
603

20%

6.3V
X5R
603

2

1

C8968

10UF

1

C8965

10UF

20%

6.3V

2

X5R
603

6.3V

20%
X5R

603

2

CRITICAL

C8942

POLY-TANT

CRITICAL

1

C8943

330UF

20%

2.0V

23

POLY-TANT
D2T-SM2

330UF

2.0V

D2T-SM2

1

20%

2 3

46

8

12A max output
(L8920 limit)

C

B

GPU (G84M) Core Supply

SYNC_MASTER=M87_MLB

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

APPLE INC.

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SYNC_DATE=10/17/2007

051-7546

SHT

OF

9678

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

D

LCD (LVDS) INTERFACE

=PP3V3_S5_LCD

8

C9000

1

R9000

100K

5%
1/16W
MF-LF

402

R9001

2

100K

5%
1/16W
MF-LF

402

LCD_PWREN_L

Q9001

SSM3K15FV

SOD-VESM-HF

LCD_PWR_EN

83

IN

1

G S

C

R9094

10K

1/16W
MF-LF

1

5%

402

2

B

0.0022uF

1 2

LCD_PWREN_L_RC

3

D

2

LVDS_CONN_A_CLK_N

80

94

LVDS_CONN_A_CLK_P

80

94

LVDS_CONN_B_CLK_N

80

94

LVDS_CONN_B_CLK_P

80

94

10%
50V

CERM

402

3

125

100K pull-ups are for
no-panel case (development).
Panel has 2K pull-ups

Place close to the connector

Place close to the connector

4

CRITICAL

Q9000

FDC638P_G

6

8

7

76

LVDS_DDC_CLK

7

80

LVDS_DDC_DATA

7

80

CRITICAL

L9010

90-OHM-100MA

1 2

CRITICAL

L9011

90-OHM-100MA

1 2

SM

=PP3V3_S0_DDC_LCD

DLP11S

SYM_VER-1

34

DLP11S

SYM_VER-1

34

PP3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

1

R9010

100K

5%
1/16W
MF-LF

402

2

1

R9011

100K

5%
1/16W
MF-LF
402

2

C9010

1000PF

C9001

0.1UF

10%
25V
X7R
402

CRITICAL

L9000

FERR-250-OHM

1

10%
16V

2

X5R
402

1

2

SM

C9002

94

94

94

94

94

94

94

94

94

94

94

94

LED_RETURN_1

7

84

LED_RETURN_2

7

84

LED_RETURN_3

7

84

LED_RETURN_4

84

7

LED_RETURN_5

7

84

LED_RETURN_6

7

84

PPVOUT_S0_LCDBKLT

7

84

1

1000PF

10%
25V

2

X7R
402

BKL_SYNC

7

84

LVDS_CONN_A_DATA_N<0>

7

80

LVDS_CONN_A_DATA_P<0>

7

80

LVDS_CONN_A_DATA_N<1>

7

80

LVDS_CONN_A_DATA_P<1>

7

80

LVDS_CONN_A_DATA_N<2>

7

80

LVDS_CONN_A_DATA_P<2>

7

80

LVDS_CONN_A_CLK_F_N

7

94

LVDS_CONN_A_CLK_F_P

94

7

LVDS_CONN_B_DATA_N<0>

7

80

LVDS_CONN_B_DATA_P<0>

7

80

LVDS_CONN_B_DATA_N<1>

7

80

LVDS_CONN_B_DATA_P<1>

7

80

LVDS_CONN_B_DATA_N<2>

7

80

LVDS_CONN_B_DATA_P<2>

7

80

LVDS_CONN_B_CLK_F_N

7

94

LVDS_CONN_B_CLK_F_P

7

94

PP3V3_SW_LCD

7

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=3.3V

NC

CRITICAL

J9000

20474-040E-11

F-RT-SM

41
42

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40

43
44

C

B

518S0651

LVDS Display Connector

A

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=02/25/2008

051-7546

SHT

1

A

REV.

A.0.0

OF

9679

8 7

6

5

4

3

2 1

DisplayPort Mux

=PP3V3_S0_DPMUX

80

8

MUXGFX

A2

LVDS Transmitter Termination

All emulated LVDS outputs require this termination

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

D

LVDS_A_CLK_P

83 94

IN

LVDS_A_CLK_N

83 94

IN

LVDS_A_DATA_P<0>

83 94

IN

LVDS_A_DATA_N<0>

83 94

IN

LVDS_A_DATA_P<1>

83 94

IN

C

LVDS_A_DATA_N<1>

83 94

IN

LVDS_A_DATA_P<2>

83 94

IN

LVDS_A_DATA_N<2>

83 94

IN

LVDS_B_CLK_P

83 94

IN

LVDS_B_CLK_N

83 94

IN

LVDS_B_DATA_P<0>

83 94

B

A

IN

LVDS_B_DATA_N<0>

83 94

IN

LVDS_B_DATA_P<1>

83 94

IN

LVDS_B_DATA_N<1>

83 94

IN

LVDS_B_DATA_P<2>

83 94

IN

LVDS_B_DATA_N<2>

83 94

IN

PLACEMENT_NOTE=Place at U9200

R9320

270

1 2

1%
1/16W
MF-LF

402

R9322

270

1 2

1%
1/16W
MF-LF

402

R9330

270

1 2

1%
1/16W
MF-LF

402

R9332

270

1 2

1%
1/16W
MF-LF

402

R9340

270

1 2

1%
1/16W
MF-LF

402

R9342

270

1 2

1%
1/16W
MF-LF

402

R9350

270

1 2

1%
1/16W
MF-LF

402

R9352

270

1 2

1%
1/16W
MF-LF

402

1

R9321

133

1%
1/16W
MF-LF
402

2

R9325

270

1 2

1%
1/16W
MF-LF

402

R9327

270

1 2

1%
1/16W
MF-LF

402

1

R9331

133

1%
1/16W
MF-LF
402

2

R9335

270

1 2

1%
1/16W
MF-LF

402

R9337

270

1 2

1%
1/16W
MF-LF

402

1

R9341

133

1%
1/16W
MF-LF
402

2

R9345

270

1 2

1%
1/16W
MF-LF

402

R9347

270

1 2

1%
1/16W
MF-LF

402

1

R9351

133

1%
1/16W
MF-LF
402

2

R9355

270

1 2

1%
1/16W
MF-LF

402

R9357

270

1 2

1%
1/16W
MF-LF

402

LVDS_CONN_A_CLK_P

SIGNAL_MODEL=EMPTY

LVDS_CONN_A_CLK_N

LVDS_CONN_A_DATA_P<0>

1

R9326

133

1%
1/16W
MF-LF
402

2

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_A_DATA_P<1>

SIGNAL_MODEL=EMPTY

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_A_DATA_P<2>

1

R9336

133

1%
1/16W
MF-LF
402

2

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_B_CLK_P

SIGNAL_MODEL=EMPTY

LVDS_CONN_B_CLK_N

LVDS_CONN_B_DATA_P<0>

1

R9346

133

1%
1/16W
MF-LF
402

2

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_B_DATA_P<1>

SIGNAL_MODEL=EMPTY

LVDS_CONN_B_DATA_N<1>

LVDS_CONN_B_DATA_P<2>

1

R9356

133

1%
1/16W
MF-LF
402

2

LVDS_CONN_B_DATA_N<2>

(All 24 resistors)

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

79 94

OUT

DP_IG_AUX_CH_N

79 94

79 94

79 94

79 94

79 94

79 94

79 94

18 89

9

BI

OUT

76

DP_IG_HPD

OUT

R9304

100K

1/16W
MF-LF

402

DP_EG_HPD

R9305

100K

1/16W
MF-LF

402

1

5%

2

1

R9306

1K

5%
1/16W
MF-LF

402

2

1

5%

2

DPMUX_EN_S0&DPMUX_EN_PLD

DP_MUX_EN

83

IN

=PP3V3_S0_DPMUX

80

8

DPMUX_EN_PLD

R9303

0

1 2

5%
1/16W
MF-LF

402

R9302

10K

1/16W
MF-LF

1

1%

402

2

79 94

OUT

7

OUT

7

OUT

7

OUT

7

OUT

7

OUT

7

OUT

79 94

OUT

79 94

OUT

7

OUT

LVDS DDC MUX

7

79 94

OUT

=PP3V3_S0_LVDSDDCMUX

7

79 94

OUT

7

79 94

OUT

7

79 94

OUT

7

79 94

OUT

8

LVDS_DDC_SEL_EG

83

IN

LVDS_DDC_SEL_IG

83

IN

C9370

0.1UF

CERM

20%
10V

402

9

89

IN

9

89

IN

9

89

IN

9

89

IN

9

89

IN

9

89

IN

9

89

IN

9

89

IN

18 89

BI

9

76

IN

9

76

BI

77 94

IN

77 94

IN

77 94

IN

77 94

IN

77 94

IN

77 94

IN

77 94

IN

77 94

IN

77 94

BI

77 94

BI

76

IN

76

BI

83

IN

83

OUT

18

OUT

1

2

DP_IG_ML_P<0>
DP_IG_ML_N<0>

DP_IG_ML_P<1>
DP_IG_ML_N<1>

DP_IG_ML_P<2>
DP_IG_ML_N<2>

DP_IG_ML_P<3>
DP_IG_ML_N<3>

DP_IG_AUX_CH_P

DP_IG_DDC_CLK
DP_IG_DDC_DATA

DP_EG_ML_P<0>
DP_EG_ML_N<0>

DP_EG_ML_P<1>
DP_EG_ML_N<1>

DP_EG_ML_P<2>
DP_EG_ML_N<2>

DP_EG_ML_P<3>
DP_EG_ML_N<3>

DP_EG_AUX_CH_P
DP_EG_AUX_CH_N

DP_EG_DDC_CLK
DP_EG_DDC_DATA

DP_MUX_SEL_EG

DP_HOTPLUG_DET

MAKE_BASE=TRUE

DP_IG_CA_DET

=PP3V3_GPU_LVDS_DDC

8

R9372

14

VCC

U9370

QFN1

13

C1

A1

C2

C3

C4
GND

THRM

7

B1
A2

B2
A3

B3

SN74LV4066A

A4
B4

15

5

6

12

DP_MUX_XSD_L

1

5%
1/16W
MF-LF

402

2
1
2

4
3

8
9

11
10

0.1uF

0.1uF

0.1uF

0.1uF

1 2

1 2

1 2

1 2

C9330
C9331

C9335
C9336

DPMUX_EN_HPD

R9301

R9370

20K

5%
1/16W
MF-LF

402

1

R9373

20K20K

5%
1/16W
MF-LF
402

2

DP_IG_AUX_CH_C_P

95

16V10% 402X5R

DP_IG_AUX_CH_C_N

95

16V10% 402X5R

DP_EG_AUX_CH_C_P

94

16V10% 402X5R

DP_EG_AUX_CH_C_N

94

16V

1

10K

1%
1/16W
MF-LF

402

2

1

1

R9371

20K

5%
1/16W
MF-LF
402

2

2

LVDS_EG_DDC_CLK

LVDS_IG_DDC_CLK
LVDS_DDC_CLK

LVDS_EG_DDC_DATA

LVDS_IG_DDC_DATA
LVDS_DDC_DATA

X5R 40210%

DPMUX_EN_HPD

1

C9301

1UF

10%

6.3V

2

CERM-X5R
402

B4
A4

B5
A5

B6
A6

A8
A9

H9
J9

H8
J8

J2

B8
B9

D8
D9

E8
E9

F8
F9

H6
J6

H5
J5

H3

A1

B7

76

IN

18

IN

7

OUT

76

BI

18

BI

7

BI

DIN1_0+
DIN1_0-

DIN1_1+
DIN1_1-

DIN1_2+
DIN1_2-

SIGNAL_MODEL=DPMUX
DIN1_3+
DIN1_3-

DAUX1+
DAUX1-

DDC_CLK1
DDC_DAT1

HPD_1

DIN2_0+
DIN2_0-

DIN2_1+
DIN2_1-

DIN2_2+
DIN2_2-

DIN2_3+
DIN2_3-

DAUX2+
DAUX2-

DDC_CLK2
DDC_DAT2

HPD_2

LO=PORT1
HI=PORT2

GPU_SEL

XSD*

79

79

J4

VDD

MUXGFX

U9320

CBTL06141EE

BGA

CRITICAL

LO=AUX_CH
HI=DDC

DDC_AUX_SEL

GND

B3C8G8H4H7

DOUT_0+
DOUT_0-

DOUT_1+
DOUT_1-

DOUT_2+
DOUT_2-

DOUT_3+
DOUT_3-

AUX+
AUX-

HPDIN

TST0

1

C9320

0.1UF

20%
10V

2

CERM
402

B2
B1

D2
D1

E2
E1

F2
F1

H2
H1

PLACEMENT_NOTE=Place at U9320

J1

DP_HPD_R

C2

G2

MAKE_BASE=TRUE

SYNC_MASTER=MUXGFX

APPLE INC.

MUXGFX

1

C9321

0.1UF

20%
10V

2

CERM
402

DP_ML_P<0>
DP_ML_N<0>

DP_ML_P<1>
DP_ML_N<1>

DP_ML_P<2>
DP_ML_N<2>

DP_ML_P<3>
DP_ML_N<3>

DP_AUX_CH_C_P
DP_AUX_CH_C_N

81 94

OUT

81 94

OUT

81 94

OUT

81 94

OUT

81 94

OUT

81 94

OUT

81 94

OUT

81 94

OUT

81 94

BI

81 94

BI

MUXGFX

R9307

1K

1 2

1/16W
MF-LF

DP_CA_DET

5%

402

IN

DP_HPD

76 81 83

81

IN

Muxed Graphics Support

SYNC_DATE=07/10/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

80 96

OF

D

C

B

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

Port Power Switch

CRITICAL

U9480

TPS2051B

SOT23

D

=PP3V3_S5_DP_PORT_PWR

8

PM_SLP_S3_L

7

21 34 37 42 44 68 83

IN

C9480

10UF

6.3V

1

1

C9481

0.1UF

20%
X5R

603

20%
10V

2

2

CERM
402

5

IN

4

EN

HDMI_CEC

C

B

1

R9425

1M

5%
1/16W
MF-LF
402

2

=PP3V3_S0_DPCONN

81

8

DP_CA_DET

76 80 83

OUT

80 94

IN

80 94

IN

80 94

BI

80 94

BI

DP_ML_P<3>

DP_ML_N<3>

DP_AUX_CH_C_P

DP_AUX_CH_C_N

2N7002DW-X-G

C9414

0.1uF

C9415

0.1uF

R9443

Q9440

100K

1/16W
MF-LF

SOT-363

1 2

94

10% X5R

1 2

94 94

10% X5R

1

5%

402

2

6

D

S

1

2N7002DW-X-G

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

1

OUT

3

OC*

GND

2

C9485

DP_ML_C_P<3>

16V 402

DP_ML_C_N<3>

16V 402

R9442

100K

2

G

DP_CA_DET_L_Q

Q9440

SOT-363

0.1UF

1/16W
MF-LF

20%
10V

CERM

402

R9403
R9413

1

5%

402

2

3

4

D

S

1

2

5

G

TP_DPPWR_OC_L

1

2

CRITICAL

C9486

22UF

20%

6.3V
X5R-CERM
603

NO STUFF

0

1 2

NO STUFF

0

1 2

FL9403

12-OHM-100MA

TCM1210-4SM

4

SYM_VER-2

6

PP3V3_S0_DPILIM

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

1/16W

1/16W

1

23

R9421

R9420

100K

5%
1/16W
MF-LF

402

MF-LF

4025%

MF-LF

4025%

1

100K

5%
1/16W
MF-LF

402

2

DP_CA_DET_Q

R9422

1/16W
MF-LF

1

2

DP_ML_CONN_P<3>

94

DP_ML_CONN_N<3>

RCLAMP0524P

DP to DVI/HDMI

1

Cable Adapter

1M

(CA) has 100k

5%

pull-up to DP_PWR.

402

2

DP_ESD

CRITICAL

D9411

SLP2510P8

2 1

IO
NC NC

GND

3

IO

9

5

FERR-120-OHM-3A

1

C9400

0.01UF

20%
50V

2

CERM
603

10

L9400

1 2

0603

PP3V3_S0_DPPWR

MIN_LINE_WIDTH=0.38 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=3.3V

CRITICAL

J9400

DSPLYPRT-M97-2

F-RT-THSM

BOT ROW

TH PINS

2

DP_HPD

4

DP_C_A_DET

6

HDMI_CEC
GND

10

ML_LANE3P

12

ML_LANE3N
GND

16

AUX_CHP

18

AUX_CHN

20

DP_PWR

SHIELD PINS

22

DP_ESD

CRITICAL

D9400

RCLAMP0504F

SC70-6-1

1

2 5

3

6

4

TOP ROW

SM PINS

ML_LANE0P
ML_LANE0N

ML_LANE1P
ML_LANE1N

ML_LANE2P
ML_LANE2N

RETURN

21

GND

GND

GND

2 1

10

MF-LF

1/16W

1/16W

4

94

94

94

94 94

4025%

4025%

4025%

MF-LF

DP_ML_C_P<0>

94

DP_ML_C_N<0>

94

DP_ML_C_P<1>

DP_ML_C_N<1>

DP_ML_C_P<2>

DP_ML_C_N<2>

C9410
C9411
C9412
C9413
C9416
C9417

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

0.1uF

1 2

1 2

10% 16V 402X5R

1 2

1 2

1 2

1 2

DP_ML_P<0>

16V10% 402X5R

DP_ML_N<0>

DP_ML_P<1>

16V10% 402X5R

DP_ML_N<1>

16V10% 402X5R

DP_ML_P<2>

16V10% 402X5R

DP_ML_N<2>

16V10% 402X5R

D

80 94

IN

80 94

IN

80 94

IN

80 94

IN

80 94

IN

80 94

IN

C

B

IO

1 2

1 2

FL9401

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

R9402
R9432

IO

3

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

2 1

IO

IO

NC NC

GND

3

NO STUFF

1 2

NO STUFF

1 2

FL9400

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

1

2 3

MF-LF

MF-LF

5% 402

5%

5%

4

1/16W

1/16W

0

0

R9400
R9430

402

MF-LF

402

MF-LF

FL9402

12-OHM-100MA

TCM1210-4SM

SYM_VER-2

1

2 3

NO STUFF

1 2

NO STUFF

1 2

9

0

0

4

1/16W

1/16W

4

DP_ESD

CRITICAL

D9410

RCLAMP0524P

SLP2510P8

5 4

IO

6 7

NC NC

GND

3

NO STUFF

R9401
R9431

94

1
3
5

94

78
9
11

94

1314
15
17
19

94

DP_ML_CONN_P<1>

DP_ML_CONN_N<1>

94

0

NO STUFF

0

DP_ML_CONN_P<0>
DP_ML_CONN_N<0>

1

2 3

DP_ML_CONN_P<2>

DP_ML_CONN_N<2>

DP_ESD

CRITICAL

D9411

RCLAMP0524P

SLP2510P8

5 4

IO

6 7

NC NC

GND

3

=PP3V3_S0_DPCONN

81

8

DP_HPD

80

OUT

2N7002DW-X-G

A

8

R9445

Q9441

SOT-363

10K

1/16W
MF-LF

1

5%

402

2

6

D

2

G

S

DP_HPD_L_Q

1

2N7002DW-X-G

R9444

Q9441

SOT-363

1/16W
MF-LF

10K

1

5%

402

2

3

D

5

G

S

4

DP_HPD_Q

7 6

R9423

100K

1/16W
MF-LF

DP Source must pull

1

down HPD input with
greater than or equal

5%

to 100K (DPv1.1a).

402

2

DisplayPort Connector

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SYNC_DATE=07/10/2008

051-7546

SHT

OF

9681

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

C

=PP1V1_S0GPU_REG

8

Vout = 1.103V
3A max output

(Q9510 limit?)

f = 400 kHz

B

XW9515

SM

1 2

C9515

10UF

20%

6.3V
X5R
603

P1V1S0_VSNS

<Ra>

1

R9520

5.76K

1%
1/16W
MF-LF
402

2

<Rb>

1

R9521

10K

1%
1/16W
MF-LF
402

2

1

2

1

2

NO STUFF

C9520

100PF

CERM

=PPVIN_S0GPU_P1V8P1V1

8

CRITICAL

C9510

330UF

20%

2.0V
POLY-TANT
B2-SM

1

5%

50V

2

402

Vout = 0.7V * (1 + Ra / Rb)
(Rb should be between 10K and 100K)

CRITICAL

C9540

22UF

20%
25V

POLY-TANT

CASE-D2-SM

CRITICAL

L9510

3.3UH-3.5A

1 2

PCMB053T

PLACEMENT_NOTE=Place XW9515 next to C7615

1

1

2

2

C9545

1UF

10%
25V
X5R
603-1

Q9510

CRITICAL

SI7904BDN

PWRPK-1212-8

Q9510

CRITICAL

SI7904BDN

PWRPK-1212-8

5

D

S

3

6

D

S

1

4

G

P1V1GPU_DRVH

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

2

P1V1GPU_DRVL

G

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

C9530

0.1UF

10%
50V
X7R

603-1

1

P1V1GPU_VBST

2

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

P1V1GPU_LL

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

68 83

68

68

67 68 83

R9500

4.7

5%
1/16W
MF-LF

402

P1V1GPU_VFB

P1V1GPU_TRIP

1

R9535

280K

1%
1/16W
MF-LF
402

2

=P1V1GPU_EN

IN

P1V1GPU_PGOOD

OUT

P1V8FB_PGOOD

OUT

=P1V8FB_EN

IN

12

PVIN_S0GPU_P1V1

C9500

1

10UF

10%
25V

2

X5R
805

GND_P1V1P1V8_SGND

=PP5V_S0GPU_P1V1P1V8_GPU

1

C9501

1UF

10%
10V

2

X5R

402-1

PP5V_S0GPU_VREF

19

365

VCC

PVCC

VREF3

VIN

17 24

BOOT1

15 26

UGATE1

16 25

PHASE1

18 23

LGATE1

10 30

OUT1

14 27

EN1

9

BYP

11

FB1

12 31

ILIM1

29

SKIP*

4

EN_LDO

20

SECFB

2

TON

THRM_PAD

CRITICAL

U9500

ISL6236

QFN

GND

21

33

LDOREFIN

PGND

XW9500

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
VOLTAGE=0V

1 2

8

(Internal 10-ohm path
from PVCC to VCC)

PP5V_S0GPU_P1V1P1V8_VCC

MIN_LINE_WIDTH=0.5 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=5V

1

C9504

1UF

10%
10V

2

X5R

402-1

7

LDO

NC

BOOT2
UGATE2
PHASE2
LGATE2

OUT2

REFIN2

ILIM2

POK1
POK2

EN2

REF

8

32

1
13
28

(SGND)

(=PP1V8FB_S0_REG)

GPU_P1V8_REFIN
P1V8FB_TRIP

PP2V_S0GPU_P1V8_REF

VOLTAGE=2V

R9585

22

1

C9585

SM

2

0.1UF

20%
10V
CERM
402

C9503

130K

1%
1/16W
MF-LF

402

1UF

402-1

1

2

10%
10V
X5R

1

2

<Ra>

R9563

R9564

P1V8FB_VBST

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM

1

14.0K

1%
1/16W
MF-LF

402

2

<Rb>

1

402

1

1%

2

2

127K

1/16W
MF-LF

P1V8_GPU_VSNS

C9561

0.01UF

10%
16V
CERM
402

1

C9580

0.1UF

10%
50V

2

X7R
603-1

1

R9562

78.7K

1%
1/16W
MF-LF
402

2

GPUFB_VID_L

CRITICAL

POLY-TANT

CASE-D2-SM

C9590

22UF

20%
25V

1

2

FDMS9600S

P1V8FB_DRVH

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

P1V8FB_DRVL

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
GATE_NODE=TRUE

P1V8FB_LL

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.2MM
SWITCH_NODE=TRUE

Q9565

SSM3K15FV

3

D

SOD-VESM-HF

GS

2

1

C9595

1UF

10%
25V

2

X5R
603-1

CRITICAL

Q9560

MLP

1

8

1

GPIO7_FBVDD_ALTVO

2349

CRITICAL

L9560

10

2.2UH-14A

1 2

MMD06CZ-SM

XW9565

SM

Q1

SW

Q2

7

56

PLACEMENT_NOTE=Place next to C7665

76

12

CRITICAL

C9560

220UF

2.5V

POLY-TANT

CASE-B2-SM2

20%

=PP1V8_GPU_REG

Vout = 1.8V
6A max output
(Q9560 limit?)

1

f = 300 kHz

1

C9565

2

10UF

20%

6.3V

2

X5R
603

D

C

8

B

1.1V / 1V8 FB Power Supply

A

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=07/10/2008

051-7546

SHT

OF

82 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

=PP3V3_S0_GMUX

83

8

1

C9610

0.1UF

20%
10V

2

CERM
402

=PP2V5_S0_GMUX

8

D

=PP1V2_S0_GMUX

8

R9640

C

NO STUFF

R9641

B

(Tie/strap low if EGPU doesn’t provide CLKREQ_L output, provide pullup to GPU rail if using CLKREQ_L output from EGPU)

10K

1/16W
MF-LF

10K

1/16W
MF-LF

1

C9621

0.1UF

20%
10V

2

CERM
402

1

1

1%

402

2

2

1

1

1%

402

2

2

1

2

C9600

4.7UF

20%
X5R

402

R9645

10K

1%
1/16W
MF-LF
402

NO STUFF

R9646

10K

1%
1/16W
MF-LF
402

NO STUFF

R9647

10K

1%
1/16W
MF-LF
402

1

2

1

2

4V

C9622

0.1UF

20%
10V
CERM
402

C9611

0.1UF

20%
10V
CERM
402

1

2

1

C9604

0.1UF

20%
10V

2

CERM
402

1

C9623

0.1UF

20%
10V

2

CERM
402

1

C9612

0.1UF

20%
10V

2

CERM
402

1

C9605

0.1UF

20%
10V

2

CERM
402

1

C9624

0.1UF

20%
10V

2

CERM
402

1

C9613

0.1UF

20%
10V

2

CERM
402

83 84

80 83

80 83

80

80 83

83

83

83

83

83

83

76

79

83

1

C9625

0.1UF

20%
10V

2

CERM
402

1

C9614

0.1UF

20%
10V

2

CERM
402

1

C9606

0.1UF

20%
10V

2

CERM
402

JTAG_GMUX_TCK

83

6

JTAG_GMUX_TDI

6 9

IN

JTAG_GMUX_TDO

6 9

OUT

JTAG_GMUX_TMS

6 9

IN

GMUX_TOE
GMUX_CFG0

LCD_BKLT_EN

9

OUT

LCD_BKLT_PWM

OUT

LVDS_DDC_SEL_EG

OUT

LVDS_DDC_SEL_IG

OUT

DP_MUX_EN

OUT

DP_MUX_SEL_EG

OUT

EG_RESET_L

9

OUT

EG_RAIL1_EN

OUT

EG_RAIL2_EN

OUT

EG_RAIL3_EN

OUT

EG_RAIL4_EN

OUT

EG_CLKREQ_OUT_L

9

OUT

DP_CA_DET_EG

OUT

LCD_PWR_EN

OUT

LPC_AD<0>

19 42 44 90

BI

LPC_AD<1>

19 42 44 90

BI

LPC_AD<2>

19 42 44 90

BI

LPC_AD<3>

19 42 44 90

BI

LPC_FRAME_L

19 42 44 90

BI

LPC_RESET_L

19 26 90

IN

LPC_CLK33M_GMUX

26

IN

GMUX_INT

9

OUT

LVDS_IG_B_DATA_P<2>

18 83 89

IN

LVDS_IG_B_DATA_N<2>

18 83 89

IN

TP_GMUX_PL10A
TP_GMUX_PL10B
LVDS_IG_A_DATA_P<0>

18 83 89

IN

LVDS_IG_A_DATA_N<0>

18 83 89

IN

LVDS_IG_A_DATA_P<1>

18 83 89

IN

LVDS_IG_A_DATA_N<1>

18 83 89

IN

LVDS_IG_A_DATA_P<2>

18 83 89

IN

LVDS_IG_A_DATA_N<2>

18 83 89

IN

LVDS_IG_B_DATA_P<0>

18 83 89

IN

LVDS_IG_B_DATA_N<0>

18 83 89

IN

LVDS_IG_B_DATA_P<1>

18 83 89

IN

LVDS_IG_B_DATA_N<1>

18 83 89

IN

LVDS_IG_A_CLK_P

18 83 89

IN

LVDS_IG_A_CLK_N

18 83 89

IN

LVDS_MUX_SEL_EG

9

OUT

TP_GMUX_PL18B_VSYNC
=GMUX_PCIE_RESET_L

26

IN

GMUX_PM_SLP_S3_L

83

IN

ALL_EG_PGOOD

9

IN

EG_CLKREQ_IN_L

83

IN

1

C9607

0.1UF

20%
10V

2

CERM
402

1

C9626

0.1UF

20%
10V

2

CERM
402

1

C9615

0.1UF

20%
10V

2

CERM
402

1

C9608

0.1UF

20%
10V

2

CERM
402

1

C9628

0.1UF

20%
10V

2

CERM
402

1

C9616

0.1UF

20%
10V

2

CERM
402

K14
L13
K13
L12

K2

K1

P2
N2
P4
N4
N3
M4
P5
M5
P6
M6
P7
M7
N7
N8
P9

N9
P10
M10
P12
P13
N12
P14

B1

B2

C2

D3

D1

E1

D2

E3

F1

G1

F3

G2

H2

G3

H1

H3

L1

L3

K3

L2

N1

P1

PM_SLP_S3_L Isolation

=PP3V3_S0_GMUX

83

8

A

PM_SLP_S3_L

7

21 34 37 42

IN

44 68 81

Q9670

SSM6N15FEAPE

SOT563

D

6

1

R9670

10K

2

1%
1/16W
MF-LF
402

2

S G

GMUX_PM_SLP_S3_L

1

MAKE_BASE=TRUE

EG_PWRSEQ_EN

83

83

PART#

336S0027

341S2350

GMUX CPLD

1

C9629

0.1UF

20%
10V

2

CERM
402

1

C9617

0.1UF

20%
10V

2

CERM
402

1

C9609

0.1UF

20%
10V

2

CERM
402

B11C4J3

J13

N11P8C11J2J14M8B5B7A12

VCC

TCK
TDI
TDO
TMS
TOE

CFG0

PB2A
PB2B
PB14A
PB14B
PB15A

(OD)

PB15B
PB16A
PB16B
PB17A
PB17B
PB18A
PB18B
PB19A
PB19B
PB20A
PB20B
PB30A
PB30B
PB31A
PB31B
PB32A
PB32B

PL2A
PL2B
PL10A
PL10B
PL11A
PL11B
PL12A
PL12B
PL13A
PL13B
PL14A
PL14B
PL15A
PL15B
PL16A
PL16B
PL18A
PL18B
PL19A
PL19B
PL32A
PL32B

BANK5

(OD)

BANK4 BANK6BANK7

GND

J1B8C6

DESCRIPTION

QTY

IC,XP2-8,HF,CPLD,BLANK

IC,CPLD,LATTICE,132CSBGA,M98

1

1

2

VCCAUX

GNDIO0

C9630

0.1UF

20%
10V
CERM
402

CRITICAL

GNDIO1

GNDIO2

C12

C13

E13

C9631

0.1UF

C14

F13

M12M9M3N5M1C3F2

VCCIO0

VCCIO1

VCCIO2

OMIT

U9600

XP28

CSBGA-HF

GNDIO3

GNDIO4

GNDIO5

N6P3M2C1E2

M14

N10

REFERENCE DESIGNATOR(S)

CERM

VCCIO3

VCCIO4

GNDIO6

20%
10V

402

GNDIO7

U9600

U9600

1

2

VCCIO5

VCCIO6

LRC_GNDPLL

ULC_GNDPLL

B4

M11

PP3V3_S0_ULC_F

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

P11

A4

K12

VCCJ

VCCIO7

LRC_VCCPLL

ULC_VCCPLL

PT2A
PT2B
PT3A
PT3B
PT4A

PT4B
PT14A
PT14B
PT15A
PT15B
PT16A

BANK0

PT16B
PT17A
PT17B
PT18A
PT18B
PT19A
PT19B
PT20A
PT20B
PT32A
PT32B

BANK1BANK2BANK3

PR2A

PR2B
PR10A
PR10B
PR11A
PR11B
PR12A
PR12B
PR13A
PR13B
PR14A
PR14B
PR15A
PR15B
PR16A
PR16B
PR18A
PR18B
PR30A
PR30B

83

6

CRITICAL BOM OPTION

CRITICAL1GMUX_8K_BLANK

CRITICAL

L9631

FERR-220-OHM

1 2

0402

PP3V3_S0_LRC_F

MIN_LINE_WIDTH=0.2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

1

C9627

0.1UF

20%
10V

2

CERM
402

LVDS_B_DATA_P<0>

A2

LVDS_B_DATA_N<0>

A3

LVDS_B_DATA_P<1>

A1

LVDS_B_DATA_N<1>

B3

LVDS_B_DATA_P<2>

C5

LVDS_B_DATA_N<2>

A5

EG_PWRSEQ_EN

B6

GMUX_DEBUG_RESET_L

C7

LVDS_A_CLK_P

A6

LVDS_A_CLK_N

A7

LVDS_B_CLK_P

C8

LVDS_B_CLK_N

C9

LVDS_A_DATA_P<0>

A8

LVDS_A_DATA_N<0>

B9

LVDS_A_DATA_P<1>

A9

LVDS_A_DATA_N<1>

C10

LVDS_A_DATA_P<2>

B10

LVDS_A_DATA_N<2>

A10

TP_GMUX_PT20A

A11

TP_GMUX_PT20B

B12

TP_GMUX_PT32A

B13

TP_GMUX_PT32B

A13

DP_CA_DET

A14

DP_HOTPLUG_DET

B14

LVDS_EG_A_DATA_P<0>

D12

LVDS_EG_A_DATA_N<0>

D13

LVDS_EG_A_DATA_P<1>

D14

LVDS_EG_A_DATA_N<1>

E14

LVDS_EG_A_DATA_P<2>

E12

LVDS_EG_A_DATA_N<2>

F12

LVDS_EG_B_DATA_P<0>

F14

LVDS_EG_B_DATA_N<0>

G14

LVDS_EG_B_DATA_P<1>

G12

LVDS_EG_B_DATA_N<1>

G13

LVDS_EG_B_DATA_P<2>

H13

LVDS_EG_B_DATA_N<2>

H12

LVDS_EG_A_CLK_P

H14

LVDS_EG_A_CLK_N

J12

IG_LCD_PWR_EN

L14

EG_LCD_PWR_EN

M13

IG_BKLT_EN

N14

EG_BKLT_EN

N13

JTAG_GMUX_TCK

GMUX_PROG

=PP3V3_S0_GMUX

L9627

FERR-220-OHM

1 2

0402

83

8

83

89

83

89

83

89

83

89

83

89

83

94

83 83

94 94

83

83

80 94

OUT

80 94

OUT

80 94

OUT

80 94

OUT

80 94

OUT

80 94

OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

(Use open-drain PGOOD output to hold off the start of the GPU PWRSEQ until the first GPU rail’s source is valid)

83

IN

83

IN

80 94

80 94

80 94

80 94

80 94

80 94

80 94

80 94

80 94

80 94

76 80 81

IN

80

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

77 83 94

IN

9

IN

76

IN

9

IN

76

IN

GMUX_JTAG_TCK Inversion

TABLE_5_HEAD

TABLE_5_ITEM

TABLE_5_ITEM

3

4

D

S G

Q9670

SSM6N15FEAPE

SOT563

5

GMUX_JTAG_TCK_L

LVDS Receiver Termination

LVDS_IG_A_CLK_P

18

LVDS_IG_A_DATA_P<0>

18

LVDS_IG_A_DATA_P<1>

18

LVDS_IG_B_DATA_P<1>

18

LVDS_IG_B_DATA_P<2>

18

LVDS_EG_A_DATA_P<0>

77

LVDS_EG_B_DATA_P<2>

77

R9650
R9651
R9652
R9653

R9654
R9655
R9656

R9660
R9661
R9662
R9663

R9664
R9665
R9666

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

1 2

100

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

SIGNAL_MODEL=EMPTY

1%
1%
1%
1%

1%
1%
1%

1%
1%
1%
1%

1%
1%
1%

MF-LF1/16W
MF-LF1/16W

1/16W

MF-LF
MF-LF1/16W

MF-LF1/16W
MF-LF1/16W
MF-LF1/16W

1/16W MF-LF

MF-LF1/16W
MF-LF1/16W
MF-LF1/16W

MF-LF1/16W
MF-LF1/16W
MF-LF1/16W

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

PLACEMENT_NOTE=Place at U9200

Required Pullups

GMUX_DEBUG_RESET_L

83

JTAG_GMUX_TCK

6

EG_CLKREQ_OUT_L

9

SILK_PART=GMUX_RST

NO STUFF

R9679

10K

1/16W
MF-LF

R9680
R9690

R9695

1

PLACEMENT_NOTE=Place on top side at U9200

1%

402

2

1K

4.7K

10K

1 2

1 2

1 2

5% 402

5%

5% 402

1/16W

MF-LF1/16W

MF-LF1/16W

MF-LF

Required Pulldowns

DP_MUX_SEL_EG

83

80

LVDS_DDC_SEL_IG

83

80

LVDS_DDC_SEL_EG

83

80

83

83

84

83

83

EG_RAIL1_EN

83

EG_RAIL2_EN

83

EG_RAIL3_EN

83

EG_RAIL4_EN

83

EG_RESET_L

9

GMUX_INT

9

LCD_BKLT_PWM

EG_CLKREQ_IN_L

17

IN

R9630

R9631
R9632

R9633

R9634

R9681

R9682
R9683

R9691

R9692
R9693

R9694

EG_PWRSEQ_GMUX

EG_PWRSEQ_GMUX

EG_PWRSEQ_GMUX

EG_PWRSEQ_GMUX

10K

1 2

5% 402

10K

1 2

10K

1 2

NO STUFF

100K

1 2

20K

1 2

100K

1 2

100K

1 2

1 2

1 2

1 2

1 2

1 2

5%

5%

5%

EG_PWRSEQ_HW

0

0

0

0

0

The MAKE BASE properties for these signals are on the POWER CONTROL page.

NO STUFF

1/16W

1/16W MF-LF

5%

1/16W

5% 402

1/16W

5%

1/16W

1/16W MF-LF

1/16W

MF-LF

1/16W MF-LF

MF-LF

1/16W

MF-LF

1/16W

MF-LF

1/16W

1

C9691

0.1UF

20%
10V

2

CERM
402

Graphics MUX (GMUX)

SYNC_MASTER=MUXGFX

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

(All 14 resistors)

LVDS_IG_A_CLK_N

402

LVDS_IG_A_DATA_N<0>

402

LVDS_IG_A_DATA_N<1>

402

LVDS_IG_A_DATA_N<2>LVDS_IG_A_DATA_P<2>

402

LVDS_IG_B_DATA_N<0>LVDS_IG_B_DATA_P<0>

402

LVDS_IG_B_DATA_N<1>

402

LVDS_IG_B_DATA_N<2>

402

LVDS_EG_A_CLK_NLVDS_EG_A_CLK_P

402

LVDS_EG_A_DATA_N<0>

402

LVDS_EG_A_DATA_N<1>LVDS_EG_A_DATA_P<1>

402

LVDS_EG_A_DATA_N<2>LVDS_EG_A_DATA_P<2>

402

LVDS_EG_B_DATA_N<0>LVDS_EG_B_DATA_P<0>

402

LVDS_EG_B_DATA_N<1>LVDS_EG_B_DATA_P<1>

402

LVDS_EG_B_DATA_N<2>

402

=PP3V3_S0_GMUX

402

MF-LF1/16W

MF-LF

4025%

402

MF-LF

4025%

MF-LF

MF-LF

402

4025%

4025%

4025%

402

402

402

NO STUFF

1

C9692

0.1UF

20%
10V

2

CERM
402

NO STUFF

1

C9693

0.1UF

20%
10V

2

CERM
402

EXTGPU_PWR_EN

=P1V1GPU_EN

P3V3GPU_EN

=GPUVCORE_EN

=P1V8FB_EN

NO STUFF

1

C9694

0.1UF

20%
10V

2

CERM
402

OUT

OUT

OUT

OUT

OUT

SYNC_DATE=07/10/2008

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

83 96

OF

18

18

18

18 18

18 18

18

18

77 77

77

77 77

77 77

77 77

77 77

77

68

68 82

68 69

68 78

67 68 82

83

89

83

89

83

89

83 83

89 89

83 83

89 89

83

89

83

89

83 83

94 94

83

94

83 83

94 94

83 83

94 94

83 83

94 94

83 83

94 94

D

C

B

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

*Q9701, D9701, C9709, C9710, L9701, R9702, AND R9715 SHOULD ALL BE PLACED NEAR EACHOTHER.

*BOOST_FET_CNTL AND PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

4

3

2 1

CRITICAL

L9701

22UH-2.5A

1 2

IHLP2525CZ-SM

R9701

PLACEMENT_NOTE=Place near Q9701

100

1%
1/16W
MF-LF
402

1 2

PLACEMENT_NOTE=Place near PPVOUT_S0_LCDBKLT_SW

BKL_VIN

1

C9702

0.1UF

10%
25V

2

X5R
402

PPVOUT_S0_LCDBKLT_SW

VOLTAGE=30V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.5 mm
SWITCH_NODE=TRUE

BOOST_FET_CNTL

MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.6MM

3

PPBUS_S0_LCDBKLT_PWR

84 85

IN

D

GND_BKL_PWRGND

PLACEMENT_NOTE=Place near C9701

VOLTAGE=12.6V
MIN_NECK_WIDTH=0.25 mm
MIN_LINE_WIDTH=0.4 mm

XW9701

SM

1 2

GND_BKL_PWRGND

84

MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM

R9730

0.1

1%
1/6W
MF

402-HF

12

CRITICAL

1

C9701

10UF

10%
25V

2

X5R
805

PLACEMENT_NOTE=Place near L9701

PPVIN_S0_LCDBKLT_BUF

VOLTAGE=12.6V
MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM

BOOST_SINK

R9704

100

BKL_VREF_4V9

PPBUS_S0_LCDBKLT_PWR

85

84

BKL_VREF_4V9

84

1

C

R9707

3.01K

1%
1/16W
MF-LF
402

1 2

PLACEMENT_NOTE=Away from Q9701

PLACEMENT_NOTE=Away from Q9701

R9708

100K

1%
1/16W
MF-LF
402

1 2

BKL_SSTCMP_RC

1

C9705

0.01UF

20%
16V

2

CERM
402

C9703

1UF

10%
10V

2

X5R
402

PLACEMENT_NOTE=Away from Q9701

R9709

1K

1%
1/16W
MF-LF

402

1 2

R9703

2.0M

5%
1/16W
MF-LF
402

1 2

B

CRITICAL

Q9702

NTUD3127CXXG

SOT-963

S

D

BKL_VREF_4V9

84

R9700

100K

1%
1/16W
MF-LF

402

1 2

BKL_PWR_EN_L

CRITICAL

Q9702

NTUD3127CXXG

SOT-963

2

83

IN

LCD_BKLT_PWM

A

N-CHN

4

6

D

G

S

1

BKL_VREF_IN_4V9

3

P-CHN

G

5

R9731

1 2

187K

1/16W
MF-LF

R9710

10K

1%
1/16W
MF-LF
402

1 2

R9711

30.1K

1%
1/16W
MF-LF
402

1 2

BKLT_EN

1%

402

1

C9713

2

0.1UF

10%
25V
X5R
402

100K

1 2

R9705

1%
1/16W
MF-LF
402

7

79

IN

BKL_SYNC

BKLT_PLL

R9734

0

5%

1/16W

MF-LF

402

12

BKL_VSYNC

R9706

10K

5%
1/16W
MF-LF
402

1 2

17

BKL_ISET
BKL_RT
BKL_SSTCMP

BKLT_PWM_RC

R9733

1

C9706

0.0022UF

10%
50V

2

CERM
402

NOSTUFF

BKL_VREF_4V9

84

PLACEMENT_NOTE=Away from Q9701

MF-LF

12

0

5%

1/16W

402

1 2

BKLT_PLL_NOT

1

C9714

1UF

10%
10V

2

X5R
402

NOSTUFF

R9713

0

5%
1/16W
MF-LF

402

BKL_DIM

BKL_LPF

PLACEMENT_NOTE=Away from Q9701

BKLT_PLL

R9714

10K

5%
1/16W
MF-LF
402

C9707

2.2UF

20%

6.3V
CERM
402-LF

1 2

BKLT_PLL

BKL_LRT_RC

1

2

C9708

0.1UF

10%
25V
X5R
402

BKLT_PLL

1

2

BKL_LRT

20

19

18

R9727

75K

1%
1/16W
MF-LF
402

1 2

PLACEMENT_NOTE=Away from Q9701

84

VIN

U9701

4

QFN

VREF

GOSHAWK6P

5

ENA

VSYNC

8

ISET

6

RT

7

SSTCMP

DIM

LPF

LRT

GNDA

13

GND_BKL_PWRGND

84

3

ISWSEN

ISEN1

ISEN2

ISEN3

ISEN4

ISEN5

ISEN6

THRM_PAD

VSEN

21

DRV

*R9702 AND R9715 PIN 1 SHOULD BE PLACED NEAR C9709 PIN 2

1

2

BKL_ISWSEN

10

BKL_ISEN1

11

BKL_ISEN2

12

BKL_ISEN3

14

BKL_ISEN4

15

BKL_ISEN5

16

BKL_ISEN6

9

BKL_VSEN

1/16W
MF-LF

1 2

1%

402

1

2

NOSTUFF

1%
1/10W
MF-LF

603

1 2

71.5K

1%
1/16W
MF-LF

402

1 2

*R9707, R9708, R9709, R9713, R9714, R9727, AND R9729 SHOULD AWAY FROM BOOST CIRCUIT

PLACEMENT_NOTE=Place near Q9701

1 2 5 6

D

G

S

PLACEMENT_NOTE=Place near C9709

4

MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM

PLACEMENT_NOTE=Place near C9709 and Q9701

R9702

0.4

1%

1/6W

MF

402

1 2

MIN_NECK_WIDTH=0.20MM
MIN_LINE_WIDTH=0.5MM

PLACEMENT_NOTE=Place near C9709 and Q9701

C9712

47PF

5%
50V
CERM
402

STPS1H100MF

Q9701

FDC5612

SSOT6

R9715

0.4

1%
1/6W

MF

402

1 2

GND_BKL_PWRGND_X

D9701

DO222-SM

1 2

PLACEMENT_NOTE=Place near C9710

GND_BKL_PWRGND

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

PPVOUT_S0_LCDBKLT

R9723

1.2M

R9724

PLACEMENT_NOTE=Place near J9000

CRITICAL

1

2

XW9702

SM

1 2

R9717

R9718

R9719

R9720

R9721

R9722

84

79

7

C9709

2.2UF

10%
100V
X7R
1210

10.2

1 2

1/16W

10.2

1 2

1/16W

10.2

1 2

1/16W

10.2

1 2

1/16W

10.2

1 2

1/16W

10.2

1 2

1/16W

CRITICAL

1

C9710

2.2UF

10%
100V

2

X7R
1210

0.1%

TF

402

0.1%

TF

402

0.1%

TF

402

0.1%

TF

402

0.1%

TF

402

0.1%

TF

402

PPVOUT_S0_LCDBKLT

LED_RETURN_6

LED_RETURN_5

LED_RETURN_4

LED_RETURN_3

LED_RETURN_2

LED_RETURN_1

LCD BACKLIGHT DRIVER

SYNC_MASTER=YITE_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

VOLTAGE=30V
MIN_NECK_WIDTH=0.20 mm
MIN_LINE_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.20 mm

DRAWING NUMBER

D

NONE

SYNC_DATE=07/02/2008

051-7546

SHT

84

D

7

79 84

OUT

7

79

OUT

7

79

OUT

7

79

OUT

7

79

OUT

7

79

OUT

7

79

OUT

C

B

A

REV.

A.0.0

OF

96

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

Q9806

FDC638APZ_SBMS001

F9800

2AMP-32V

=PPBUS_S0_LCDBKLT

8

IN

MIN_LINE_WIDTH=0.4 mm

9

IN

26

IN

MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

LVDS_BKL_ON

BKLT_PLT_RST_L

D

85

C

1 2

0402-HF

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

Q9807

SSM6N15FEAPE

SOT563

5

SSM6N15FEAPE

1

R9808

301K

1%
1/16W
MF-LF
402

2

PPBUS_S0_LCDBKLT_EN_L

3

D

SG

4

1

2

BKLT_EN_L

Q9807

SOT563

2

C9802

0.1UF

10%
16V
X5R
402

PPBUS_S0_LCDBKLT_EN_DIV

1

R9809

147K

1%
1/16W
MF-LF
402

2

6

D

SG

1

SSOT6-HF

4

1 2 5 6

3

PPBUS S0 LCDBkLT FET

MOSFET
CHANNEL

RDS(ON)

LOADING

FDC638APZ
P-TYPE
43 mOhm @4.5V

0.4 A (EDP)

PPBUS_S0_LCDBKLT_PWR

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V

D

84

OUT

C

B

LVDS_BKL_ON

1

R9840

4.7K

5%
1/16W
MF-LF
402

2

A

8

7 6

85

9

LCD Backlight Support

SYNC_MASTER=YITE_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

.

SYNC_DATE=07/02/2008

051-7546

SHT

1

REV.

OF

9685

B

A

A.0.0

8 7

6

5

4

3

2 1

2.5V/1.2V S3 Switcher

D

=PP3V3_S0_P1V2P2V5

8

2.2UF

6.3V
CERM

402-LF

1

20%

2

3

VIN

U9900

DFN-HF

PAD

LTC3547

9

GND

SW1

RUN1
RUN2

5

SW2

1

VFB1

8

VFB2

CRITICAL

THRML

P1V2S0_SW

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
SWITCH_NODE=TRUE

4

6

2
7

P1V2S0_VFB

P2V5S0_SW

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
SWITCH_NODE=TRUE

P2V5S0_VFB

C9900

C

=P2V5S0_EN

68

IN

=P1V2S0_EN

68

CRITICAL

L9980

2.2UH-1.2A

1 2

PCAA031B-SM

CRITICAL

L9900

2.2UH-1.2A

1 2

PCAA031B-SM

C9982

10PF

CERM

C9901

10PF

50V

CERM

402

=PP1V2_S0_REG

<Ra>

1

R9982

1

280K

1%

5%

50V
402

5%

1/16W
MF-LF

2

402

2

<Rb>

1

R9983

280K

1%
1/16W
MF-LF
402

2

1

2

<Ra>

1

2

<Rb>

1

2

Vout = 1.2V
300mA max output
(Switcher limit)
f = 2.25 MHz

1

C9985

4.7UF

20%
4V

2

X5R
402

R9900

475K

1%
1/16W
MF-LF
402

R9901

150K

1%
1/16W
MF-LF
402

=PP2V5_S0_REG

Vout = 2.5V

0.3A max output
(Switcher limit)
f = 2.25 MHz

1

C9905

4.7UF

20%
4V

2

X5R
402

8

8

D

C

Vout = 0.6V * (1 + Ra/Rb)

B

B

Misc Power Supplies

A

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

SCALE

NONE

SYNC_DATE=02/01/2008

051-7546

SHT

OF

86 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

FSB (Front-Side Bus) Constraints

LAYER

FSB_50S

FSB_DSTB_50S

LAYER

D

SPACING_RULE_SET

FSB_DATA
FSB_DSTB
FSB_ADDR

FSB_ADSTB

FSB_1X

*

*
*
*
*
*

ALLOW ROUTE
ON LAYER?

=50_OHM_SE

=50_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC
=3x_DIELECTRIC

=STANDARD

=2x_DIELECTRIC

=STANDARD

MINIMUM LINE WIDTH

=50_OHM_SE
=50_OHM_SE =50_OHM_SE =50_OHM_SE

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

SPACING_RULE_SET

FSB_DATA
FSB_DSTB
FSB_ADDR

FSB_ADSTB

FSB_1X

MAXIMUM NECK LENGTH

=50_OHM_SE=50_OHM_SE

LAYER

TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM
TOP,BOTTOM

LINE-TO-LINE SPACING

=4x_DIELECTRIC
=5x_DIELECTRIC
=3x_DIELECTRIC
=4x_DIELECTRIC
=3x_DIELECTRIC

6

DIFFPAIR PRIMARY GAP

=STANDARD*

=1:1_DIFFPAIR =1:1_DIFFPAIR

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

=STANDARD

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.
FSB 4X signals / groups shown in signal table on right.

Signals within each 4x group should be matched within 5 ps of strobe.
DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.
Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.
DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 2X signals / groups shown in signal table on right.
Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.
Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#.

FSB 1X signals shown in signal table on right.
Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

Design Guide recommends each strobe/signal group is routed on the same layer.
Intel Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.
SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

CPU Signal Constraints

C

CPU_50S

LAYER

CPU_27P4S

ALLOW ROUTE
ON LAYER?

* =27P4_OHM_SE

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=50_OHM_SE=50_OHM_SE =50_OHM_SE=50_OHM_SE

=27P4_OHM_SE

MAXIMUM NECK LENGTH

=27P4_OHM_SE=27P4_OHM_SE

DIFFPAIR PRIMARY GAP

7 MIL 7 MIL

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD*

TABLE_PHYSICAL_RULE_ITEM

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

TABLE_SPACING_RULE_HEAD

WEIGHT

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

CPU_AGTL

SR DG recommends at least 25 mils, >50 mils preferred

*
*
*
*
*
*

LINE-TO-LINE SPACING

=STANDARD

8 MIL
25 MIL
25 MIL

=2:1_SPACING

25 MIL

SPACING_RULE_SET

LAYER

CPU_AGTL
CPU_8MIL
CPU_COMP

CPU_GTLREF

CPU_ITP

CPU_VCCSENSE

Most CPU signals with impedance requirements are 55-ohm single-ended.
Some signals require 27.4-ohm single-ended impedance.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2
SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

B

MCP_50S

SPACING_RULE_SET

MCP_FSB_COMP

LAYER

LAYER

*

ALLOW ROUTE
ON LAYER?

LINE-TO-LINE SPACING

8 MIL

MINIMUM LINE WIDTH

=50_OHM_SE =50_OHM_SE=50_OHM_SE

WEIGHT

?

MINIMUM NECK WIDTH

=50_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

LINE-TO-LINE SPACING

=2x_DIELECTRIC

DIFFPAIR PRIMARY GAP

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD*

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

FSB Clock Constraints

CLK_FSB_100D

SPACING_RULE_SET

CLK_FSB

LAYER

LAYER

*

*

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

MINIMUM LINE WIDTH

WEIGHT

MINIMUM NECK WIDTH

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?

CLK_FSB =4x_DIELECTRIC

MAXIMUM NECK LENGTH

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

LINE-TO-LINE SPACING

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

A

5

CPU / FSB Net Properties

ELECTRICAL_CONSTRAINT_SET

FSB_DATA_GROUP0
FSB_DATA_GROUP0
FSB_DSTB0
FSB_DSTB0

FSB_DATA_GROUP1
FSB_DATA_GROUP1
FSB_DSTB1
FSB_DSTB1

FSB_DATA_GROUP2
FSB_DATA_GROUP2
FSB_DSTB2
FSB_DSTB2

FSB 4X Signal Groups

FSB 2X

Signals

FSB 1X Signals

FSB_DATA_GROUP3
FSB_DATA_GROUP3
FSB_DSTB3
FSB_DSTB3

FSB_ADDR_GROUP0
FSB_ADDR_GROUP0
FSB_ADSTB0

FSB_ADDR_GROUP1
FSB_ADSTB1

FSB_1X FSB_1X
FSB_BREQ0_L
FSB_BREQ1_L
FSB_1X FSB_1X
FSB_1X FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X
FSB_1X FSB_1X
FSB_1X FSB_1X
FSB_CPURST_L
FSB_1X
FSB_1X

CPU_ASYNC
CPU_BSEL
CPU_FERR_L
CPU_ASYNC
CPU_INIT_L
CPU_ASYNC_R
CPU_ASYNC_R
CPU_PROCHOT_L
CPU_PWRGD
CPU_ASYNC
CPU_ASYNC
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_FROM_SB
CPU_DPRSTP_L
CPU_ASYNC

FSB_CLK_CPU
FSB_CLK_CPU
FSB_CLK_ITP
FSB_CLK_ITP
FSB_CLK_MCP
FSB_CLK_MCP

CPU_IERR_L

PM_DPRSLPVR

(See above)

CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP
CPU_COMP CPU_COMP

XDP_TDI CPU_50S CPU_ITP
XDP_TDO CPU_50S CPU_ITP
XDP_TMS CPU_50S CPU_ITP
XDP_TCK CPU_50S CPU_ITP
XDP_TRST_L
XDP_BPM_L
XDP_BPM_L5

(FSB_CPURST_L)

CPU_VCCSENSE
CPU_VCCSENSE

(CPU_VCCSENSE)
(CPU_VCCSENSE)

4

PHYSICAL

FSB_50S
FSB_50S
FSB_DSTB_50S FSB_DSTB
FSB_DSTB_50S

FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S FSB_DSTB

FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S FSB_DSTB

FSB_50S
FSB_50S
FSB_DSTB_50S
FSB_DSTB_50S FSB_DSTB

FSB_50S
FSB_50S
FSB_50S

FSB_50S
FSB_50S

FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S
FSB_50S

CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
CPU_50S
MCP_50S
MCP_50S
MCP_50S
MCP_50S

CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D
CLK_FSB_100D

CPU_50S

CPU_50S
CPU_50S

CPU_50S
CPU_50S
CPU_27P4S
CPU_50S
CPU_27P4S

CPU_50S CPU_ITP
CPU_50S
CPU_50S CPU_ITP

CPU_50S
CPU_50S
CPU_27P4S
CPU_27P4S
CPU_27P4S
CPU_27P4S

NET_TYPE

SPACING

FSB_DATA
FSB_DATA

FSB_DSTB

FSB_DATA
FSB_DATA
FSB_DSTB

FSB_DATA
FSB_DATA
FSB_DSTB

FSB_DATA
FSB_DATA
FSB_DSTB

FSB_ADDR
FSB_ADDR
FSB_ADSTB

FSB_ADDR
FSB_ADSTB

FSB_1X
FSB_1X

FSB_1X
FSB_1X
FSB_1X
FSB_1X

FSB_1X
FSB_1X
FSB_1X

CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_8MIL
CPU_AGTL
CPU_AGTL
CPU_AGTL
CPU_AGTL
MCP_FSB_COMPMCP_CPU_COMP
MCP_FSB_COMPMCP_CPU_COMP
MCP_FSB_COMPMCP_CPU_COMP
MCP_FSB_COMPMCP_CPU_COMP

CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB
CLK_FSB

CPU_AGTL
CPU_AGTL

CPU_GTLREF
CPU_COMP
CPU_COMP
CPU_COMP

CPU_ITP

CPU_ITPCPU_50S

CPU_8MIL
CPU_8MIL
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE
CPU_VCCSENSE

FSB_D_L<15..0>
FSB_DINV_L<0>
FSB_DSTB_L_P<0>
FSB_DSTB_L_N<0>

FSB_D_L<31..16>
FSB_DINV_L<1>
FSB_DSTB_L_P<1>
FSB_DSTB_L_N<1>

FSB_D_L<47..32>
FSB_DINV_L<2>
FSB_DSTB_L_P<2>
FSB_DSTB_L_N<2>

FSB_D_L<63..48>
FSB_DINV_L<3>
FSB_DSTB_L_P<3>
FSB_DSTB_L_N<3>

FSB_A_L<16..3>
FSB_REQ_L<4..0>
FSB_ADSTB_L<0>

FSB_A_L<35..17>
FSB_ADSTB_L<1>

FSB_ADS_L
FSB_BREQ0_L
FSB_BREQ1_L
FSB_BNR_L
FSB_BPRI_L
FSB_DBSY_L
FSB_DEFER_L
FSB_DRDY_L
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_CPURST_L
FSB_RS_L<2..0>
FSB_TRDY_L

CPU_A20M_L
CPU_BSEL<2..0>
CPU_FERR_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_PROCHOT_L
CPU_PWRGD
CPU_SMI_L
CPU_STPCLK_L
PM_THRMTRIP_L
FSB_CPUSLP_L
CPU_DPSLP_L
CPU_DPRSTP_L

FSB_DPWR_L
MCP_BCLK_VML_COMP_VDD
MCP_BCLK_VML_COMP_GND
MCP_CPU_COMP_VCC
MCP_CPU_COMP_GND

FSB_CLK_CPU_P

FSB_CLK_CPU_N

FSB_CLK_ITP_P

FSB_CLK_ITP_N

FSB_CLK_MCP_P

FSB_CLK_MCP_N

CPU_IERR_L

PM_DPRSLPVR

IMVP_DPRSLPVR

CPU_GTLREF

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

CPU_COMP<0>

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TCK

XDP_TRST_L

XDP_BPM_L<4..0>

XDP_BPM_L<5>

XDP_CPURST_L

CPU_VID<6..0>

IMVP6_VID<6..0>

CPU_VCCSENSE_P

CPU_VCCSENSE_N

IMVP6_VSEN_P

IMVP6_VSEN_N

3

7

14

10

14

7

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

14

7

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

7

14

10

9

14

10

14

10

14

10

14

10

14

10

14

10

14

7

14

10

7

14

10

14

7

10

14

9

13

10

10

14

10

14

10

14

9

10

10

14

10

14

10

14

9

14

10

9

14

10

62

10

43

14

10

14

13

10

14

10

14

10

43

14

10

14

10

14

62

9

14

10

10

14

14

14

14

14

10

14

10

14

13

14

13

14

14

14

10

21

62

62

10

27

10

10

10

10

6

13

10

6

10

6

13

10

6

13

10

6

13

10

10

13

10

13

13

9

11

9

62

11

62

11

62

62

62

2 1

CPU/FSB Constraints

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=02/18/2008

051-7546

SHT

D

C

B

A

REV.

A.0.0

OF

9687

8

7 6

5

4

3

2

1

8 7

6

Memory Bus Constraints

LAYER

ALLOW ROUTE
ON LAYER?

MEM_40S

=40_OHM_SE

=70_OHM_DIFF

=70_OHM_DIFF

* =70_OHM_DIFF =70_OHM_DIFF

*
*
*
*
*
*
*
*

LINE-TO-LINE SPACING

=4:1_SPACING

=2:1_SPACING
=2.5:1_SPACING
=1.5:1_SPACING

=3:1_SPACING
=1.5:1_SPACING

=3:1_SPACINGMEM_DATA2MEM

=3:1_SPACING

LAYER

*

D

MEM_40S_VDD

MEM_70D

MEM_70D_VDD

SPACING_RULE_SET

MEM_CLK2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM

MEM_CMD2CMD
MEM_CMD2MEM

MEM_DATA2DATA

MEM_DQS2MEM

MEM_2OTHER

Memory Bus Spacing Group Assignments

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLKMEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK
MEM_CLK

NET_SPACING_TYPE1 NET_SPACING_TYPE2

C

MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CTRL
MEM_CTRL

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DQS
MEM_DQS
MEM_DQS MEM_CMD
MEM_DQS
MEM_DQS MEM_DQS

DDR2:

DQ signals should be matched within 20 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement.
All DQS pairs should be matched within 100 ps of clocks.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps.
A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

B

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DDR3:

DQ signals should be matched within 5 ps of associated DQS pair.
DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps
No DQS to clock matching requirement.
CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps.
A/BA/cmd signals should be matched within 5 ps of CLK pairs.
All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).
DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3
SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_DATA

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

=40_OHM_SE =40_OHM_SE =40_OHM_SE

=70_OHM_DIFF

25 MIL

AREA_TYPE

*
*
*
*
*

AREA_TYPE

*
*
*
*
*

AREA_TYPE

*
*
*
*
*

=70_OHM_DIFF

WEIGHT

SPACING_RULE_SET

MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM
MEM_CLK2MEM

SPACING_RULE_SET

MEM_CTRL2MEM

MEM_CTRL2CTRL

MEM_CTRL2MEM
MEM_CTRL2MEM
MEM_CTRL2MEM

SPACING_RULE_SET

MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM
MEM_DQS2MEM

=70_OHM_DIFF =70_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_ASSIGNMENT_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

MEM_CMD
MEM_CMD

MEM_CMD
MEM_CMD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

Need to support MEM_*-style wildcards!

MAXIMUM NECK LENGTH

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE

=70_OHM_DIFF=70_OHM_DIFF

MEM_CLK

MEM_CTRL

MEM_CMDMEM_CMD

MEM_DATA

MEM_DQS

MEM_CLK

MEM_CTRL

MEM_CMD

MEM_DATA

MEM_DQS

* *

* *

* *

DIFFPAIR PRIMARY GAP

=STANDARD* =STANDARD

AREA_TYPE

SPACING_RULE_SET

*
*
*
*
*

AREA_TYPE

SPACING_RULE_SET

*
*
*
*

MEM_DATA2DATA

*

AREA_TYPE

SPACING_RULE_SET

**

**

MCP MEM COMP Signal Constraints

LAYER

ALLOW ROUTE
ON LAYER?

MCP_MEM_COMP

SPACING_RULE_SET

MCP_MEM_COMP

LAYER

LINE-TO-LINE SPACING

*

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

Y

8 MIL

MINIMUM LINE WIDTH

7 MIL 7 MIL

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

A

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD* =STANDARD

=70_OHM_DIFF=70_OHM_DIFF*

MEM_CMD2MEM
MEM_CMD2MEM
MEM_CMD2CMD
MEM_CMD2MEM
MEM_CMD2MEM

MEM_DATA2MEM
MEM_DATA2MEM
MEM_DATA2MEM

MEM_DATA2MEM

MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER
MEM_2OTHER

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD*

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

Memory Net Properties

ELECTRICAL_CONSTRAINT_SET

MEM_A_CLK
MEM_A_CLK

MEM_A_CNTL
MEM_A_CNTL
MEM_A_CNTL

MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD
MEM_A_CMD

MEM_A_DQ_BYTE0
MEM_A_DQ_BYTE1
MEM_A_DQ_BYTE2
MEM_A_DQ_BYTE3 MEM_40S
MEM_A_DQ_BYTE4 MEM_40S
MEM_A_DQ_BYTE5 MEM_40S
MEM_A_DQ_BYTE6
MEM_A_DQ_BYTE7

MEM_A_DQ_BYTE0 MEM_40S
MEM_A_DQ_BYTE1 MEM_40S
MEM_A_DQ_BYTE2 MEM_40S
MEM_A_DQ_BYTE3 MEM_40S
MEM_A_DQ_BYTE4 MEM_40S
MEM_A_DQ_BYTE5 MEM_40S
MEM_A_DQ_BYTE6 MEM_40S
MEM_A_DQ_BYTE7 MEM_40S

MEM_A_DQS0
MEM_A_DQS0
MEM_A_DQS1
MEM_A_DQS1
MEM_A_DQS2
MEM_A_DQS2
MEM_A_DQS3
MEM_A_DQS3
MEM_A_DQS4
MEM_A_DQS4
MEM_A_DQS5
MEM_A_DQS5
MEM_A_DQS6
MEM_A_DQS6
MEM_A_DQS7
MEM_A_DQS7

MEM_B_CLK
MEM_B_CLK

MEM_B_CNTL
MEM_B_CNTL
MEM_B_CNTL

MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD
MEM_B_CMD

MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4 MEM_40S
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7

MEM_B_DQ_BYTE0
MEM_B_DQ_BYTE1
MEM_B_DQ_BYTE2
MEM_B_DQ_BYTE3
MEM_B_DQ_BYTE4
MEM_B_DQ_BYTE5
MEM_B_DQ_BYTE6
MEM_B_DQ_BYTE7

MEM_B_DQS0
MEM_B_DQS0
MEM_B_DQS1
MEM_B_DQS1
MEM_B_DQS2
MEM_B_DQS2
MEM_B_DQS3
MEM_B_DQS3
MEM_B_DQS4
MEM_B_DQS4
MEM_B_DQS5
MEM_B_DQS5
MEM_B_DQS6
MEM_B_DQS6
MEM_B_DQS7
MEM_B_DQS7

MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP
MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP

4

PHYSICAL

MEM_70D_VDD
MEM_70D_VDD

MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD

MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD

MEM_40S
MEM_40S
MEM_40S

MEM_40S
MEM_40S

MEM_70D

MEM_70D

MEM_70D

MEM_70D
MEM_70D

MEM_70D

MEM_70D_VDD
MEM_70D_VDD

MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD

MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD
MEM_40S_VDD

MEM_40S
MEM_40S
MEM_40S
MEM_40S

MEM_40S
MEM_40S
MEM_40S

MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S
MEM_40S

MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS
MEM_70D MEM_DQS

NET_TYPE

SPACING

MEM_CLK
MEM_CLK

MEM_CTRL
MEM_CTRL
MEM_CTRL

MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQS
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQS
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQS
MEM_DQSMEM_70D
MEM_DQSMEM_70D
MEM_DQS
MEM_DQS
MEM_DQSMEM_70D
MEM_DQS

MEM_CLK
MEM_CLK

MEM_CTRL
MEM_CTRL
MEM_CTRL

MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD
MEM_CMD

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA
MEM_DATA

MEM_DQS

MEM_A_CLK_P<5..0>
MEM_A_CLK_N<5..0>

MEM_A_CKE<3..0>
MEM_A_CS_L<3..0>
MEM_A_ODT<3..0>

MEM_A_A<14..0>
MEM_A_BA<2..0>
MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_DQ<7..0>
MEM_A_DQ<15..8>
MEM_A_DQ<23..16>
MEM_A_DQ<31..24>
MEM_A_DQ<39..32>
MEM_A_DQ<47..40>
MEM_A_DQ<55..48>
MEM_A_DQ<63..56>

MEM_A_DM<0>
MEM_A_DM<1>
MEM_A_DM<2>
MEM_A_DM<3>
MEM_A_DM<4>
MEM_A_DM<5>
MEM_A_DM<6>
MEM_A_DM<7>

MEM_A_DQS_P<0>
MEM_A_DQS_N<0>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<7>
MEM_A_DQS_N<7>

MEM_B_CLK_P<5..0>
MEM_B_CLK_N<5..0>

MEM_B_CKE<3..0>
MEM_B_CS_L<3..0>
MEM_B_ODT<3..0>

MEM_B_A<14..0>
MEM_B_BA<2..0>
MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_DQ<7..0>
MEM_B_DQ<15..8>
MEM_B_DQ<23..16>
MEM_B_DQ<31..24>
MEM_B_DQ<39..32>
MEM_B_DQ<47..40>
MEM_B_DQ<55..48>
MEM_B_DQ<63..56>

MEM_B_DM<0>
MEM_B_DM<1>
MEM_B_DM<2>
MEM_B_DM<3>
MEM_B_DM<4>
MEM_B_DM<5>
MEM_B_DM<6>
MEM_B_DM<7>

MEM_B_DQS_P<0>
MEM_B_DQS_N<0>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<7>
MEM_B_DQS_N<7>

MCP_MEM_COMP_VDD
MCP_MEM_COMP_GND

3

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

28

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

15

29

16

16

2 1

Memory Constraints

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=02/18/2008

051-7546

SHT

D

C

B

A

REV.

A.0.0

OF

9688

8

7 6

5

4

3

2

1

8 7

PCI-Express

LAYER

PCIE_90D

CLK_PCIE_100D

SPACING_RULE_SET

LAYER

PCIE

CLK_PCIE

MCP_PEX_COMP

D

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

Analog Video Signal Constraints

LAYER

CRT_50S

SPACING_RULE_SET

LAYER

CRT
CRT_2CRT
CRT_2CLK

CRT_2SWITCHER

CRT_SYNC

MCP_DAC_COMP

CRT signal single-ended impedence varies by location:

- 37.5-ohm from MCP to first termination resistor.

- 50-ohm from first to second termination resistor.

- 75-ohm from output of three-pole filter to connector (if possible).
R/G/B signals should be matched as close as possible and < 10 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.

Digital Video Signal Constraints

C

LAYER

DP_100D

LVDS_100D

MCP_DV_COMP

SPACING_RULE_SET

LAYER

DISPLAYPORT

LVDS

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SATA Interface Constraints

LAYER

SATA_100D

SPACING_RULE_SET

B

SATA

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

LAYER

ALLOW ROUTE
ON LAYER?

=90_OHM_DIFF

=100_OHM_DIFF

*

LINE-TO-LINE SPACING

=3X_DIELECTRIC

*
*
*

ALLOW ROUTE
ON LAYER?

=50_OHM_SE =50_OHM_SE

LINE-TO-LINE SPACING

*

=4:1_SPACING
*
*
*
*
*

*
*

=2:1_SPACING

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

=100_OHM_DIFF

*

LINE-TO-LINE SPACING

*

=3x_DIELECTRIC
=3x_DIELECTRIC

*

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

*

LINE-TO-LINE SPACING

*

=4x_DIELECTRIC

*

MINIMUM LINE WIDTH

=90_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

WEIGHT

20 MIL

8 MIL

MINIMUM LINE WIDTH

=50_OHM_SE

WEIGHT

=STANDARD

50 MIL

250 MIL

16 MIL

MINIMUM LINE WIDTH

=100_OHM_DIFF

MINIMUM NECK WIDTH

=90_OHM_DIFF

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

SPACING_RULE_SET

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

PCIE

MINIMUM NECK WIDTH

=50_OHM_SE

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

CRT CRT

MINIMUM NECK WIDTH

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

Y

8 MILSATA_TERMP

WEIGHT

?
?

MINIMUM LINE WIDTH

=100_OHM_DIFF

WEIGHT

?
?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

20 MIL20 MIL

SPACING_RULE_SET

DISPLAYPORT

LVDS

MINIMUM NECK WIDTH

=100_OHM_DIFF

SPACING_RULE_SET

SATA

MAXIMUM NECK LENGTH

13.1 MM

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=100_OHM_DIFF

=STANDARD

LAYER

TOP,BOTTOM
TOP,BOTTOM

MAXIMUM NECK LENGTH

=100_OHM_DIFF

LAYER

TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=90_OHM_DIFF =90_OHM_DIFF*

=100_OHM_DIFF =100_OHM_DIFF

LINE-TO-LINE SPACING

=4X_DIELECTRIC

DIFFPAIR PRIMARY GAP

=STANDARD* =STANDARD

AREA_TYPE

*

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF
=100_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC
=4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF

LINE-TO-LINE SPACING

=3x_DIELECTRIC

A

6

WEIGHT

SPACING_RULE_SET

CRT_2CRT

WEIGHT

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF
=100_OHM_DIFF

=STANDARD=STANDARD

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

ELECTRICAL_CONSTRAINT_SET

PEG_R2D

PEG_D2R

PCIE_MINI_R2D

PCIE_MINI_D2R

PCIE_FW_R2D

PCIE_FW_D2R

PCIE_EXCARD_R2D

PCIE_EXCARD_D2R

MCP_PE0_REFCLK

MCP_PE1_REFCLK

MCP_PE2_REFCLK

MCP_PE3_REFCLK

MCP_PEX_CLK_COMP

CRT_RED
CRT_GREEN
CRT_BLUE
CRT_SYNC
CRT_SYNC

TMDS_IG_TXC

TMDS_IG_TXD
TMDS_IG_TXD

DP_ML
DP_ML
DP_AUX_CH
DP_AUX_CH

MCP_HDMI_RSET
MCP_HDMI_VPROBE

LVDS_IG_A_CLK
LVDS_IG_A_CLK
LVDS_IG_A_DATA
LVDS_IG_A_DATA
LVDS_IG_A_DATA3
LVDS_IG_A_DATA3
LVDS_IG_B_CLK
LVDS_IG_B_CLK
LVDS_IG_B_DATA
LVDS_IG_B_DATA
LVDS_IG_B_DATA3
LVDS_IG_B_DATA3

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

SATA_HDD_R2D

SATA_HDD_D2R

SATA_ODD_R2D

SATA_ODD_D2R

MCP_SATA_TERMP

4

PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE

PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D
PCIE_90D
PCIE_90D
PCIE_90D PCIE

PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE
PCIE_90D PCIE

PCIE_90D PCIE

PCIE_90D
PCIE_90D
PCIE_90D

CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D
CLK_PCIE_100D

CRT_50S
CRT_50S
CRT_50S
CRT_50S
CRT_50S

DP_100D
DP_100D
DP_100D
DP_100D

DP_100D
DP_100D
DP_100D
DP_100D

MCP_DV_COMP
MCP_DV_COMP

LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D
LVDS_100D

MCP_DV_COMP

SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D

PHYSICAL

NET_TYPE

SPACING

PCIE

PCIE
PCIE
PCIE

PCIEPCIE_90D
PCIEPCIE_90D
PCIE
PCIE
PCIE

CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
CLK_PCIE
MCP_PEX_COMP

CRT
CRT
CRT
CRT_SYNC
CRT_SYNC
MCP_DAC_COMPMCP_DAC_RSET
MCP_DAC_COMPMCP_DAC_VREF

DISPLAYPORT
DISPLAYPORTTMDS_IG_TXC
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS
LVDS

SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA

SATA_TERMP

PEG_R2D_P<15..0>
PEG_R2D_N<15..0>
PEG_R2D_C_P<15..0>
PEG_R2D_C_N<15..0>
PEG_D2R_P<15..0>
PEG_D2R_N<15..0>
PEG_D2R_C_P<15..0>
PEG_D2R_C_N<15..0>

PCIE_MINI_R2D_P
PCIE_MINI_R2D_N
PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N
PCIE_MINI_D2R_P
PCIE_MINI_D2R_N

PCIE_FW_R2D_P
PCIE_FW_R2D_N
PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N
PCIE_FW_D2R_P
PCIE_FW_D2R_N
PCIE_FW_D2R_C_P
PCIE_FW_D2R_C_N

PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N
PCIE_EXCARD_D2R_P
PCIE_EXCARD_D2R_N

PEG_CLK100M_P
PEG_CLK100M_N
PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N
PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N
PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N
MCP_PEX_CLK_COMP

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB
CRT_IG_HSYNC
CRT_IG_VSYNC
MCP_TV_DAC_RSET
MCP_TV_DAC_VREF

TMDS_IG_TXC_P
TMDS_IG_TXC_N
TMDS_IG_TXD_P<2..0>
TMDS_IG_TXD_N<2..0>

DP_IG_ML_P<3..0>
DP_IG_ML_N<3..0>
DP_IG_AUX_CH_P
DP_IG_AUX_CH_N

MCP_HDMI_RSET
MCP_HDMI_VPROBE

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N
LVDS_IG_A_DATA_P<2..0>
LVDS_IG_A_DATA_N<2..0>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>
LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N
LVDS_IG_B_DATA_P<2..0>
LVDS_IG_B_DATA_N<2..0>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N
SATA_HDD_R2D_P
SATA_HDD_R2D_N
SATA_HDD_D2R_P
SATA_HDD_D2R_N
SATA_HDD_D2R_C_P
SATA_HDD_D2R_C_N
SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N
SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_P
SATA_ODD_D2R_N
SATA_ODD_D2R_C_P
SATA_ODD_D2R_C_N

MCP_SATA_TERMP

3

70

70

70

9

70

9

70

9

70

9

70

70

95

31

31

95

31

17

31

17

31

17

31

17

36

36

36

17

17

36

36

17

36

17

36

36

32

95

7

32

95

7

32

17

17

32

17

32

7

32

17

7

17

70

17

70

31

17

17

31

36

17

36

17

32

17

32

17

17

25

18

25

18

25

18

18

25

25

18

25

18

25

18

80

9

9

80

80

18

18

80

25

18

18

25

83

18

83

18

83

18

83

18

18

9

18

9

18

9

18

9

83

18

83

18

18

9

18

9

18

25

18

25

20

39

20

39

39

39

20

39

39

20

39

39

39

20

39

20

39

7

39

7

39

20

39

20

39

7

39

7

20

2 1

MCP Constraints 1

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=02/18/2008

051-7546

SHT

89 96

D

C

B

A

REV.

A.0.0

OF

8

7 6

5

4

3

2

1

8 7

PCI Bus Constraints

LAYER

PCI_55S

CLK_PCI_55S

SPACING_RULE_SET

LAYER

PCI

CLK_PCI

D

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

LPC Bus Constraints

LAYER

LPC_55S

CLK_LPC_55S

SPACING_RULE_SET

LAYER

LPC

CLK_LPC

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

USB 2.0 Interface Constraints

LAYER

MCP_USB_RBIAS

USB_90D

SPACING_RULE_SET

LAYER

USB

C

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

SMBus Interface Constraints

LAYER

SMB_55S

SPACING_RULE_SET

LAYER

SMB

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

HD Audio Interface Constraints

LAYER

HDA_55S

SPACING_RULE_SET

LAYER

HDA

MCP_HDA_COMP

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

SIO Signal Constraints

B

LAYER

CLK_SLOW_55S

SPACING_RULE_SET

LAYER

CLK_SLOW

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SPI Interface Constraints

LAYER

SPI_55S

SPACING_RULE_SET

SPI

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

LAYER

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

LINE-TO-LINE SPACING

*
*

ALLOW ROUTE
ON LAYER?

=STANDARD

8 MIL

MINIMUM LINE WIDTH

=55_OHM_SE
=55_OHM_SE

WEIGHT

?
?

MINIMUM LINE WIDTH

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE
=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

*
*

LINE-TO-LINE SPACING

6 MIL
8 MIL

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

8 MIL 8 MIL

=90_OHM_DIFF =90_OHM_DIFF

LINE-TO-LINE SPACING

*

=2x_DIELECTRIC

ALLOW ROUTE
ON LAYER?

=55_OHM_SE

* =STANDARD =STANDARD

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*

ALLOW ROUTE
ON LAYER?

* =STANDARD=STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE=55_OHM_SE

LINE-TO-LINE SPACING

=2x_DIELECTRIC

*
*

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE =55_OHM_SE

*

LINE-TO-LINE SPACING

*

ALLOW ROUTE
ON LAYER?

=55_OHM_SE =55_OHM_SE =55_OHM_SE

LINE-TO-LINE SPACING

*

MINIMUM LINE WIDTH

=55_OHM_SE =55_OHM_SE =55_OHM_SE

MINIMUM LINE WIDTH

8 MIL

MINIMUM LINE WIDTH

8 MIL

MINIMUM LINE WIDTH

=55_OHM_SE

8 MIL

WEIGHT

WEIGHT

WEIGHT

WEIGHT

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

=90_OHM_DIFF

SPACING_RULE_SET

USB

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=55_OHM_SE=55_OHM_SE=55_OHM_SE

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD=STANDARD

LAYER

TOP,BOTTOM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

6

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD*
=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD*

=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF*

LINE-TO-LINE SPACING

=4x_DIELECTRIC

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

WEIGHT

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD* =STANDARD
=STANDARD

=STANDARD

=STANDARD=STANDARD*

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

ELECTRICAL_CONSTRAINT_SET

MCP_DEBUG
PCI_AD
PCI_AD24
PCI_AD
PCI_AD
PCI_C_BE_L
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_CNTL
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L

MCP_PCI_CLK2

LPC_AD
LPC_FRAME_L
LPC_RESET_L

MCP_LPC_CLK0

USB_EXTA

USB_MINI

USB_EXTD

USB_CAMERA

USB_BT

USB_TPAD

USB_IR

USB_EXTB

USB_EXCARD

USB_EXTC

SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA

HDA_BIT_CLK

HDA_SYNC

HDA_RST_L

HDA_SDIN0

HDA_SDOUT

MCP_HDA_PULLDN_COMP

MCP_SUS_CLK

SPI_CLK SPI_55S

SPI_MOSI

SPI_MISO

4

PHYSICAL

PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S
PCI_55S

CLK_PCI_55S
CLK_PCI_55S

LPC_55S
LPC_55S
LPC_55S

CLK_LPC_55S
CLK_LPC_55S
CLK_LPC_55S

USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D
USB_90D

MCP_USB_RBIASMCP_USB_RBIAS

SMB_55S
SMB_55S
SMB_55S
SMB_55S

HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S
HDA_55S

CLK_SLOW_55S CLK_SLOW

SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55S
SPI_55SSPI_CS0
SPI_55S

NET_TYPE

SPACING

PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI
PCI

CLK_PCI
CLK_PCI

LPC
LPC
LPC

CLK_LPC
CLK_LPC
CLK_LPC

USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB
USB

SMB
SMB
SMB
SMB

HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA
HDA

MCP_HDA_COMP

CLK_SLOWCLK_SLOW_55S

SPI
SPI
SPI
SPI
SPI
SPI
SPI
SPI

MCP_DEBUG<7..0>
PCI_AD<23..8>
PCI_AD<24>
PCI_AD<31..25>
PCI_PAR
PCI_C_BE_L<3..0>
PCI_IRDY_L
PCI_DEVSEL_L
PCI_PERR_L
PCI_SERR_L
PCI_STOP_L
PCI_TRDY_L
PCI_FRAME_L
PCI_REQ0_L
PCI_GNT0_L
PCI_REQ1_L
PCI_GNT1_L
PCI_INTW_L
PCI_INTX_L
PCI_INTY_L
PCI_INTZ_L

PCI_CLK33M_MCP_R
PCI_CLK33M_MCP

LPC_AD<3..0>
LPC_FRAME_L
LPC_RESET_L

LPC_CLK33M_SMC_R
LPC_CLK33M_SMC
LPC_CLK33M_LPCPLUS

USB_EXTA_P
USB_EXTA_N
USB_EXTA_MUXED_P
USB_EXTA_MUXED_N
USB_MINI_P
USB_MINI_N
USB_EXTD_P
USB_EXTD_N
USB_CAMERA_P
USB_CAMERA_N
USB_BT_P
USB_BT_N
USB_TPAD_P
USB_TPAD_N
USB_IR_P
USB_IR_N
USB_EXTB_P
USB_EXTB_N
USB_EXCARD_P
USB_EXCARD_N
USB_EXTC_P
USB_EXTC_N

MCP_USB_RBIAS_GND
SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA

HDA_BIT_CLK
HDA_BIT_CLK_R
HDA_SYNC
HDA_SYNC_R
HDA_RST_R_L
HDA_RST_L
HDA_SDIN0
HDA_SDIN_CODEC
HDA_SDOUT
HDA_SDOUT_R

MCP_HDA_PULLDN_COMP
PM_CLK32K_SUSCLK_R

PM_CLK32K_SUSCLK
SPI_CLK_R

SPI_CLK
SPI_MOSI_R
SPI_MOSI
SPI_MISO
SPI_MISO_R
SPI_CS0_R_L
SPI_CS0_L

3

13

19

19

19

19

19

83

44

19

42

19

83

44

42

83

19

26

19

26

26

42

26

44

20

40

20

40

9

20

9

20

9

20

9

20

20

31

20

31

20

31

20

31

20

50

20

50

20

41

20

41

20

40

20

40

20

32

20

32

9

20

9

20

20

45

7

21

13

45

7

21

13

21

45

21

45

9

21

21

21

54

21

21

21

54

21

54

21

54

21

21

21

26

42

26

21

44

44

53

44

21

53

44

44

21

53

44

21

2 1

D

C

B

MCP Constraints 2

A

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=02/18/2008

051-7546

SHT

OF

9690

1

A

REV.

A.0.0

8 7

MCP RGMII (Ethernet) Constraints

LAYER

MCP_MII_COMP
ENET_MII_55S

SPACING_RULE_SET

MCP_BUF0_CLK

ENET_MII

D

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

LAYER

88E1116R (Ethernet PHY) Constraints

LAYER

ENET_MDI_100D

SPACING_RULE_SET

ENET_MDI

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

LAYER

ALLOW ROUTE
ON LAYER?

* =STANDARD
* =STANDARD=STANDARD

=55_OHM_SE

LINE-TO-LINE SPACING

*
*

*

*

=3:1_SPACING

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

LINE-TO-LINE SPACING

MINIMUM LINE WIDTH

7.5 MIL

=55_OHM_SE =55_OHM_SE =55_OHM_SE

WEIGHT

12 MIL

MINIMUM LINE WIDTH

WEIGHT

25 MIL

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

7.5 MIL

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF=100_OHM_DIFF

6

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF =100_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=STANDARD=STANDARD

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

ELECTRICAL_CONSTRAINT_SET

MCP_MII_COMP
MCP_MII_COMP

MCP_CLK25M_BUF0

ENET_INTR_L
ENET_MDIO

ENET_PWRDWN_L

ENET_RXCLK

ENET_RXD
ENET_RXD_STRAP
ENET_RXD

ENET_TXCLK
ENET_TXD0
ENET_TXD ENET_MII_55S ENET_MII
ENET_TXD

ENET_MDI

4

PHYSICAL

MCP_MII_COMP
MCP_MII_COMP

ENET_MII_55S MCP_BUF0_CLK
ENET_MII_55S MCP_BUF0_CLK

ENET_MII_55S
ENET_MII_55S
ENET_MII_55S ENET_MIIENET_MDC

ENET_MII_55S ENET_MII

ENET_MII_55S ENET_MII

ENET_MDI_100D
ENET_MDI_100D

NET_TYPE

SPACING

ENET_MII
ENET_MII

ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S
ENET_MIIENET_MII_55S
ENET_MIIENET_MII_55S
ENET_MIIENET_MII_55S
ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S
ENET_MIIENET_MII_55S

ENET_MIIENET_MII_55S

ENET_MDI
ENET_MDI

MCP_MII_COMP_VDD
MCP_MII_COMP_GND

MCP_CLK25M_BUF0_R
RTL8211_CLK25M_CKXTAL1

ENET_INTR_L
ENET_MDIO
ENET_MDC
ENET_PWRDWN_L

ENET_CLK125M_RXCLK_R
ENET_CLK125M_RXCLK
ENET_RXD_R<3..0>
ENET_RXD<0>
ENET_RXD<3..1>
ENET_RX_CTRL

ENET_CLK125M_TXCLK
ENET_TXD<0>
ENET_TXD<3..1>
ENET_TX_CTRL

ENET_RESET_L
ENET_MDI_P<3..0>

ENET_MDI_N<3..0>

3

18

18

18

34

33

34

18

33

18

33

33

33

18

33

18

33

18

33

18

33

18

33

18

33

18

33

18

33

18

33

33

35

33

35

2 1

D

C

B

C

B

Ethernet Constraints

A

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=02/18/2008

051-7546

SHT

OF

9691

1

A

REV.

A.0.0

8 7

FireWire Interface Constraints

LAYER

FW_110D

SPACING_RULE_SET

FW_TP

LAYER

*

*

ALLOW ROUTE
ON LAYER?

=110_OHM_DIFF

LINE-TO-LINE SPACING

=3:1_SPACING

MINIMUM LINE WIDTH

=110_OHM_DIFF =110_OHM_DIFF

WEIGHT

?

D

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

=110_OHM_DIFF

6

DIFFPAIR PRIMARY GAP

=110_OHM_DIFF =110_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

5

FireWire Net Properties

ELECTRICAL_CONSTRAINT_SET

FW_P0_TPA
FW_P0_TPA
FW_P0_TPB
FW_P0_TPB
FW_P1_TPA
FW_P1_TPA
FW_P1_TPB
FW_P1_TPB

4

NET_TYPE

PHYSICAL

FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D
FW_110D

SPACING

FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP
FW_TP

FW_P0_TPA_P
FW_P0_TPA_N
FW_P0_TPB_P
FW_P0_TPB_N
FW_P1_TPA_P
FW_P1_TPA_N
FW_P1_TPB_P
FW_P1_TPB_N

3

38

36

38

36

38

36

38

36

38

36

38

36

38

36

38

36

2 1

D

Port 2 Not Used

C

B

C

B

FireWire Constraints

A

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=02/18/2008

051-7546

SHT

OF

92 96

1

A

REV.

A.0.0

D

1TO1_DIFFPAIR

8 7

LAYER

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

=STANDARD=STANDARD

MINIMUM NECK WIDTH

=STANDARD =STANDARD

MAXIMUM NECK LENGTH

6

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM*

5

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SMC SMBus Net Properties

ELECTRICAL_CONSTRAINT_SET

SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA

4

NET_TYPE

PHYSICAL

SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S
SMB_55S

SPACING

SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB
SMB

SMBUS_SMC_A_S3_SCL
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_B_S0_SCL
SMBUS_SMC_B_S0_SDA
SMBUS_SMC_0_S0_SCL
SMBUS_SMC_0_S0_SDA
SMBUS_SMC_BSA_SCL
SMBUS_SMC_BSA_SDA
SMBUS_SMC_MGMT_SCL
SMBUS_SMC_MGMT_SDA

3

45

7

45

7

45

45

45

45

45

45

45

45

2 1

D

SMBus Charger Net Properties

ELECTRICAL_CONSTRAINT_SET

CHGR_CSI

CHGR_CSO

1TO1_DIFFPAIR
1TO1_DIFFPAIR

1TO1_DIFFPAIR
1TO1_DIFFPAIR

C

PHYSICAL

NET_TYPE

SPACING

CHGR_CSI_P
CHGR_CSI_N

CHGR_CSO_P
CHGR_CSO_N

61

61

61

61

C

B

B

SMC Constraints

A

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=02/18/2008

051-7546

SHT

OF

9693

1

A

REV.

A.0.0

8 7

GDDR3 Frame Buffer Signal Constraints

LAYER

GDDR3_40R55SE

GDDR3_40SE =40_OHM_SE

GDDR3_80D

LAYER

D

SPACING_RULE_SET

GDDR3_CLK

GDDR3_CMD

GDDR3_DATA

GDDR3_DQS

From T18 MXM:
Digital Video Signal Constraints

LAYER

C

DP_100D

LVDS_100D

SPACING_RULE_SET

LAYER

DISPLAYPORT

LVDS

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.
DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.
DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.
Max length of LVDS/DisplayPort/TMDS traces: 12 inches.
SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

ALLOW ROUTE
ON LAYER?

*

*

*

=55_OHM_SE

=40_OHM_SE

=80_OHM_DIFF

MINIMUM LINE WIDTH

=40_OHM_SE

=40_OHM_SE

=80_OHM_DIFF

LINE-TO-LINE SPACING

=2.5:1_SPACING

*

* ?

*

*
*

=2.5:1_SPACING

=2.5:1_SPACING

=2.5:1_SPACING

ALLOW ROUTE
ON LAYER?

=100_OHM_DIFF

=100_OHM_DIFF

MINIMUM LINE WIDTH

=100_OHM_DIFF
=100_OHM_DIFF

LINE-TO-LINE SPACING

*

=3x_DIELECTRIC
=3x_DIELECTRIC

*

WEIGHT

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_HEAD

?

TABLE_SPACING_RULE_ITEM

?

MINIMUM NECK WIDTH

0.095 MM

0.095 MM

0.095 MM

MINIMUM NECK WIDTH

SPACING_RULE_SET

DISPLAYPORT

LVDS

MAXIMUM NECK LENGTH

12.7 MM

=80_OHM_DIFF

MAXIMUM NECK LENGTH

=100_OHM_DIFF=100_OHM_DIFF
=100_OHM_DIFF=100_OHM_DIFF

LAYER

TOP,BOTTOM
TOP,BOTTOM

DIFFPAIR PRIMARY GAP

=STANDARD =STANDARD

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF
=100_OHM_DIFF

LINE-TO-LINE SPACING

=4x_DIELECTRIC
=4x_DIELECTRIC

6

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=80_OHM_DIFF=80_OHM_DIFF

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=100_OHM_DIFF
=100_OHM_DIFF

TABLE_SPACING_RULE_HEAD

WEIGHT

TABLE_SPACING_RULE_ITEMTABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

=STANDARD=STANDARD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

GDDR3 FB A/B Net Properties

ELECTRICAL_CONSTRAINT_SET

5

PHYSICAL

FB_A_CLK_P

FB_B_CLK_P

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD

FB_AB_CMD
FB_AB_CMD_PD

FB_AB_CS0

FB_AB_CMD_PD

FB_A_CMD

FB_B_CMD

FB_A_WDQS0 GDDR3_40SE

FB_A_WDQS1 GDDR3_40SE
FB_A_WDQS2

FB_A_WDQS3 GDDR3_40SE

FB_A_RDQS0

FB_A_RDQS1
FB_A_RDQS2

FB_A_RDQS3

FB_A_DQ_BYTE0
FB_A_DQ_BYTE1

FB_A_DQ_BYTE2

FB_A_DQ_BYTE3

FB_A_DQM0
FB_A_DQM1

FB_A_DQM2

FB_A_DQM3

FB_B_WDQS0
FB_B_WDQS1

FB_B_WDQS2
FB_B_WDQS3

FB_B_RDQS0 GDDR3_40SE

FB_B_RDQS1

FB_B_RDQS2

FB_B_DQ_BYTE0

FB_B_DQ_BYTE1

FB_B_DQ_BYTE2
FB_B_DQ_BYTE3

FB_B_DQM0

FB_B_DQM1
FB_B_DQM2

FB_B_DQM3

GDDR3_80D GDDR3_CLK

GDDR3_80D
GDDR3_80D

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE
GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE
GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE
GDDR3_40SE

GDDR3_40SE

GDDR3_40SE
GDDR3_40SE

GDDR3_40SE GDDR3_DATA

GDDR3_40SE

GDDR3_40SE
GDDR3_40SE

GDDR3_40SE
GDDR3_40SE

GDDR3_40SE

GDDR3_40SE
GDDR3_40SEFB_B_RDQS3

GDDR3_40SE

GDDR3_40SE GDDR3_DATA
GDDR3_40SE GDDR3_DATA

GDDR3_40SE

GDDR3_40SE GDDR3_DATA
GDDR3_40SE

NET_TYPE

SPACING

GDDR3_CLKGDDR3_80D

GDDR3_CLK
GDDR3_CLK

GDDR3_CMD

GDDR3_CMD

GDDR3_CMDFB_AB_CMD
GDDR3_CMD

GDDR3_CMD

GDDR3_CMD
GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_DQS

GDDR3_DQS
GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS
GDDR3_DQS

GDDR3_DQS

GDDR3_DATA
GDDR3_DATA

GDDR3_DATA

GDDR3_DATAGDDR3_40SE
GDDR3_DATAGDDR3_40SE

GDDR3_DATAGDDR3_40SE

GDDR3_DATAGDDR3_40SE

GDDR3_DQS
GDDR3_DQS

GDDR3_DQS
GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS
GDDR3_DQS

GDDR3_DATA

GDDR3_DATAGDDR3_40SE

GDDR3_DATA

GDDR3_DATA

GDDR3_DATAGDDR3_40SE

4

FB_A_CLK_P<0>
FB_A_CLK_N<0>
FB_A_CLK_P<1>
FB_A_CLK_N<1>

FB_A_MA<1..0>
FB_A_MA<12..6>
FB_A_BA<2..0>
FB_A_RAS_L
FB_A_CAS_L
FB_A_WE_L
FB_A_CKE
FB_A_CS0_L
FB_A_DRAM_RST

FB_A_LMA<5..2>
FB_A_UMA<5..2>

FB_A_WDQS<0>
FB_A_WDQS<1>
FB_A_WDQS<2>
FB_A_WDQS<3>

FB_A_RDQS<0>
FB_A_RDQS<1>
FB_A_RDQS<2>
FB_A_RDQS<3>

FB_A_DQ<7..0>
FB_A_DQ<15..8>
FB_A_DQ<23..16>
FB_A_DQ<31..24>

FB_A_DQM_L<0>
FB_A_DQM_L<1>
FB_A_DQM_L<2>
FB_A_DQM_L<3>

FB_A_WDQS<4>
FB_A_WDQS<5>
FB_A_WDQS<6>
FB_A_WDQS<7>

FB_A_RDQS<4>
FB_A_RDQS<5>
FB_A_RDQS<6>
FB_A_RDQS<7>

FB_A_DQ<39..32>
FB_A_DQ<47..40>
FB_A_DQ<55..48>
FB_A_DQ<63..56>

FB_A_DQM_L<4>
FB_A_DQM_L<5>
FB_A_DQM_L<6>
FB_A_DQM_L<7>

73

72

73

72

72

73

72

73

72

73

73

72

73

72

73

72

72

73

73

72

73

72

72

73

72

73

72

73

72

73

73

72

73

72

73

72

73

72

73

72

73

72

73

72

73

72

73

72

73

72

72

73

73

72

72

73

72

73

72

73

72

73

73

72

72

73

72

73

73

72

73

72

73

72

73

72

72

73

73

72

73

72

72

73

72

73

73

72

73

72

73

72

72

73

3

GDDR3 FB C/D Net Properties

ELECTRICAL_CONSTRAINT_SET

FB_C_CLK_P

FB_D_CLK_P

FB_CD_CMD

FB_CD_CMD GDDR3_CMD

FB_CD_CMD
FB_CD_CMD

FB_CD_CMD

FB_CD_CMD
FB_CD_CMD_PD

FB_CD_CMD_PD

FB_C_CMD

FB_D_CMD

FB_C_WDQS0 GDDR3_40SE

FB_C_WDQS1 GDDR3_40SE
FB_C_WDQS2 GDDR3_40SE

FB_C_WDQS3 GDDR3_40SE

FB_C_RDQS0 GDDR3_40SE

FB_C_RDQS1
FB_C_RDQS2

FB_C_RDQS3

FB_C_DQ_BYTE0
FB_C_DQ_BYTE1

FB_C_DQ_BYTE2

FB_C_DQ_BYTE3

FB_C_DQM0
FB_C_DQM1

FB_C_DQM2

FB_C_DQM3

FB_D_WDQS0 GDDR3_40SE
FB_D_WDQS1 GDDR3_40SE

FB_D_WDQS2 GDDR3_40SE
FB_D_WDQS3 GDDR3_40SE

FB_D_RDQS0 GDDR3_40SE

FB_D_RDQS1 GDDR3_40SE

FB_D_RDQS2 GDDR3_40SE
FB_D_RDQS3

FB_D_DQ_BYTE0

FB_D_DQ_BYTE1

FB_D_DQ_BYTE2
FB_D_DQ_BYTE3

FB_D_DQM0

FB_D_DQM1
FB_D_DQM2

FB_D_DQM3

PHYSICAL

GDDR3_80D
GDDR3_80D

GDDR3_80D
GDDR3_80D

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE
GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE
GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40R55SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE
GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE
GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE

GDDR3_40SE
GDDR3_40SE

GDDR3_40SE GDDR3_DATA

GDDR3_40SE

GDDR3_40SE

2 1

NET_TYPE

SPACING

GDDR3_CLK
GDDR3_CLK

GDDR3_CLK
GDDR3_CLK

GDDR3_CMD

GDDR3_CMD
GDDR3_CMD

GDDR3_CMD

GDDR3_CMD
GDDR3_CMD

GDDR3_CMDFB_CD_CS0

GDDR3_CMD

GDDR3_CMD

GDDR3_CMD

GDDR3_DQS

GDDR3_DQS
GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS
GDDR3_DQS

GDDR3_DQS

GDDR3_DATAGDDR3_40SE
GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA
GDDR3_DATA

GDDR3_DATA

GDDR3_DATA

GDDR3_DQS
GDDR3_DQS

GDDR3_DQS
GDDR3_DQS

GDDR3_DQS

GDDR3_DQS

GDDR3_DQS
GDDR3_DQS

GDDR3_DATA

GDDR3_DATA

GDDR3_DATA
GDDR3_DATA

GDDR3_DATA
GDDR3_DATAGDDR3_40SE

GDDR3_DATA

FB_B_CLK_P<0>
FB_B_CLK_N<0>
FB_B_CLK_P<1>
FB_B_CLK_N<1>

FB_B_MA<1..0>
FB_B_MA<12..6>
FB_B_BA<2..0>
FB_B_RAS_L
FB_B_CAS_L
FB_B_WE_L
FB_B_CKE
FB_B_CS0_L
FB_B_DRAM_RST

FB_B_LMA<5..2>
FB_B_UMA<5..2>

FB_B_WDQS<0>
FB_B_WDQS<1>
FB_B_WDQS<2>
FB_B_WDQS<3>

FB_B_RDQS<0>
FB_B_RDQS<1>
FB_B_RDQS<2>
FB_B_RDQS<3>

FB_B_DQ<7..0>
FB_B_DQ<15..8>
FB_B_DQ<23..16>
FB_B_DQ<31..24>

FB_B_DQM_L<0>
FB_B_DQM_L<1>
FB_B_DQM_L<2>
FB_B_DQM_L<3>

FB_B_WDQS<4>
FB_B_WDQS<5>
FB_B_WDQS<6>
FB_B_WDQS<7>

FB_B_RDQS<4>
FB_B_RDQS<5>
FB_B_RDQS<6>
FB_B_RDQS<7>

FB_B_DQ<39..32>
FB_B_DQ<47..40>
FB_B_DQ<55..48>
FB_B_DQ<63..56>

FB_B_DQM_L<4>
FB_B_DQM_L<5>
FB_B_DQM_L<6>
FB_B_DQM_L<7>

74

72

74

72

74

72

74

72

74

72

74

72

74

72

74

72

72

74

74

72

72

74

72

74

74

72

74

72

74

72

74

72

74

72

72

74

72

74

72

74

74

72

74

72

74

72

74

72

72

74

72

74

74

72

72

74

74

72

72

74

72

74

72

74

72

74

72

74

72

74

74

72

74

72

74

72

74

72

74

72

72

74

72

74

72

74

72

74

72

74

72

74

72

74

D

C

MUXGFX Net Properties

ELECTRICAL_CONSTRAINT_SET

LVDS_A_CLK

I148

LVDS_A_CLK

I149

B

I199
I198

I152
I153

I201

I200

I183
I182

I184

I185
I190

I191

I192
I193

I194
I195

I196

I197

LVDS_A_DATA
LVDS_A_DATA

LVDS_B_CLK
LVDS_B_CLK

LVDS_B_DATA
LVDS_B_DATA

PHYSICAL

LVDS_100D
LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D
LVDS_100D

LVDS_100D

LVDS_100D

LVDS_100D
LVDS_100D

LVDS_100D

LVDS_100D
LVDS_100D

LVDS_100D
LVDS_100D

LVDS_100D

LVDS_100D
LVDS_100D

NET_TYPE

SPACING

LVDS
LVDS

LVDS

LVDS

LVDS

LVDS

LVDS
LVDS

LVDS

LVDS

LVDS
LVDS

LVDS

LVDS
LVDS

LVDS
LVDS

LVDS

LVDS
LVDS

LVDS_A_CLK_P
LVDS_A_CLK_N

LVDS_A_DATA_P<2..0>
LVDS_A_DATA_N<2..0>

LVDS_B_CLK_P
LVDS_B_CLK_N

LVDS_B_DATA_P<2..0>
LVDS_B_DATA_N<2..0>

LVDS_CONN_A_CLK_F_P
LVDS_CONN_A_CLK_F_N
LVDS_CONN_B_CLK_F_P
LVDS_CONN_B_CLK_F_N
LVDS_CONN_A_CLK_P
LVDS_CONN_A_CLK_N
LVDS_CONN_A_DATA_P<2..0>
LVDS_CONN_A_DATA_N<2..0>
LVDS_CONN_B_CLK_P
LVDS_CONN_B_CLK_N
LVDS_CONN_B_DATA_P<2..0>
LVDS_CONN_B_DATA_N<2..0>

80

83

80

83

80

83

80

83

80

83

80

83

83

80

80

83

79

7

79

7

79

7

79

7

79

80

80

79

80

79

7

79

80

7

80

79

80

79

80

79

7

80

79

7

G96 Net Properties

ELECTRICAL_CONSTRAINT_SET

(CK505_DOT96)

CK505_CLK27MSS

LVDS_EG_A_CLK
LVDS_EG_A_CLK
LVDS_EG_A_DATA
LVDS_EG_A_DATA

LVDS_EG_B_DATA
LVDS_EG_B_DATA

DP_ML

I142

DP_ML

I144

DP_AUX_CH

I145

DP_AUX_CH

I143

I139

I138

PHYSICAL

CLK_SLOW_55S

CLK_SLOW_55S
LVDS_100D

LVDS_100D

LVDS_100D
LVDS_100D

LVDS_100D

LVDS_100D

DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D

NET_TYPE

SPACING

CLK_SLOW

CLK_SLOW
LVDS

LVDS

LVDS
LVDS

LVDS

LVDS

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

GPU_CLK27M
GPU_CLK27M_SS
LVDS_EG_A_CLK_P
LVDS_EG_A_CLK_N
LVDS_EG_A_DATA_P<2..0>
LVDS_EG_A_DATA_N<2..0>

LVDS_EG_B_DATA_P<2..0>
LVDS_EG_B_DATA_N<2..0>

DP_EG_ML_P<3..0>DP_EG_ML_P<3..0>
DP_EG_ML_N<3..0>

DP_EG_ML_N<3..0>
DP_EG_AUX_CH_P

DP_EG_AUX_CH_N
DP_EG_AUX_CH_C_P
DP_EG_AUX_CH_C_N

76

76

77

83

77

83

77

83

77

83

77

83

83

77

77

80

80

77

80

77

80

77

80

80

B

GPU (G96) Constraints

DP_ML

A

I161
I160

I155

I157
I202

I203

I159

I158

DP_ML

DP_ML

DP_AUX_CH
DP_AUX_CH

DP_100D
DP_100D
DP_100D
DP_100D
DP_100D
DP_100D

DP_100D
DP_100D

DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT
DISPLAYPORT

DISPLAYPORT
DISPLAYPORT

DP_ML_C_P<3..0>
DP_ML_C_N<3..0>
DP_ML_P<3..0>DP_ML_P<3..0>
DP_ML_N<3..0>

DP_ML_N<3..0>
DP_ML_CONN_P<3..0>
DP_ML_CONN_N<3..0>

DP_AUX_CH_C_P
DP_AUX_CH_C_N

81

81

81

80

81

80

81

81

81

80

81

80

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

SYNC_DATE=02/18/2008

051-7546

SHT

A

REV.

A.0.0

OF

9694

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

SENSE_1TO1_55S

THERM_1TO1_55S

DIFFPAIR

SPACING_RULE_SET

D

SENSE

THERM

AUDIO

SPACING_RULE_SET

ENETCONN

SPACING_RULE_SET

GND =STANDARD

PP1V8_MEM =STANDARD

SPACING_RULE_SET

GND_P2MM

PWR_P2MM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

MEM_CLK

MEM_CMD

C

MEM_DATA

MEM_DQS

LAYER

LAYER

LAYER

LAYER

LAYER

ALLOW ROUTE
ON LAYER?

=1:1_DIFFPAIR

*

*

=1:1_DIFFPAIR

*

LINE-TO-LINE SPACING

*

*

LINE-TO-LINE SPACING

LINE-TO-LINE SPACING

* ?

LINE-TO-LINE SPACING

*

*

GND

GND

GND

GND

GND

=2:1_SPACING

=2:1_SPACING

=2:1_SPACING

25 MILS

0.20 MM

0.20 MM

AREA_TYPE

*

*

*

*

*

MINIMUM LINE WIDTH

=55_OHM_SE

WEIGHT

?*

?

?

WEIGHT

?*

WEIGHT

?*

WEIGHT

1000

1000

SPACING_RULE_SET

GND_P2MM

GND_P2MM

GND_P2MMMEM_CTRL

GND_P2MM

GND_P2MM

MINIMUM NECK WIDTH

=55_OHM_SE

=55_OHM_SE=55_OHM_SE

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_FSB

CPU_COMP GND_P2MM

CPU_GTLREF

CPU_VCCSENSE

FSB_DSTB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

ENET_MDI

NET_SPACING_TYPE1 NET_SPACING_TYPE2

CLK_PCIE GND_P2MM

PCIE

SATA

USB

CLK_PCIE PWR_P2MM

SATA

USB

NET_SPACING_TYPE1 NET_SPACING_TYPE2

B

LVDS

AREA_TYPE

GND

GND

GND

GND

SB_POWER

SB_POWER PWR_P2MM

AREA_TYPE

GND

*

*

*

*

*

*

*

*

SPACING_RULE_SET

GND_P2MM

GND_P2MM

GND_P2MM

PWR_P2MMSB_POWER

SPACING_RULE_SET

GND_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

LAYER

MEM_70D 6.35 MM

BOTTOM

ALLOW ROUTE
ON LAYER?

MINIMUM LINE WIDTH

MINIMUM NECK WIDTH

0.127 MM

Graphics ,SATA Constraint Relaxations

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

PHYSICAL_RULE_SET

BGA

BGA

BGASATA_100D

A

NET_PHYSICAL_TYPE

LVDS_100D

DP_100D

AREA_TYPE

100_DIFF_BGA

100_DIFF_BGA

100_DIFF_BGA

TABLE_PHYSICAL_ASSIGNMENT_HEAD

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

MAXIMUM NECK LENGTH

=55_OHM_SE

=55_OHM_SE

=1:1_DIFFPAIR=1:1_DIFFPAIR

DIFFPAIR PRIMARY GAP

=1:1_DIFFPAIR

=1:1_DIFFPAIR =1:1_DIFFPAIR

AREA_TYPE

GND

GND

GND

GND

FSB_DSTB GND_P2MM

AREA_TYPE

GND

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

*

*

*

*

*

*

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

=1:1_DIFFPAIR

=1:1_DIFFPAIR=1:1_DIFFPAIR

GND_P2MM

GND_P2MM

GND_P2MM

GND_P2MM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

SPACING_RULE_SET

SPACING_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

M99 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

I146

I145
I144

I142

I143
I140

I141

I139

SENSE_DIFFPAIR

SENSE_DIFFPAIR SENSE_1TO1_55S

CPUTHMSNS_D2_DP

I124

I125

CPU_THERMD_DP

I127

I126

GPUTHMSNS_D_DP

I128

I130

GPU_THERMD_DP

I129

MCPTHMSNS_D_DP

I138

I137

MCP_THERMD_DP

I135

I136

SENSE_DIFFPAIR

I156

I157

SENSE_DIFFPAIR

I155
I154

SENSE_DIFFPAIR SENSE_1TO1_55S

I153

I152

SENSE_DIFFPAIR

I151

I150

SENSE_DIFFPAIR

I149
I148

SENSE_DIFFPAIR SENSE_1TO1_55S

I158
I147

SENSE_DIFFPAIR SENSE_1TO1_55S

I186

I185

SENSE_DIFFPAIR SENSE_1TO1_55S

I131

I132

SENSE_DIFFPAIR

I134

I133

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_40S_VDD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D_VDD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

PCIE_90D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

USB_90D 0.09 MM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_DV_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MEM_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_MII_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_USB_RBIAS

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MCP_DV_COMP

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

CPU_27P4S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_40S

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_40S_VDD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

MEM_70D_VDD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

Ground-referenced memory signals (DQ,DQM,DQS) MAY route on ISL9 (VDD-referenced plane)but not next to VDD island.
Forces power-referenced memory signals (CLK,ADDR,CTRL) to not route on ISL3, ISL4 & ISL10(GND-referenced planes).

ISL4,ISL9

ISL3,ISL10

ISL4,ISL9

ISL3,ISL10

LAYER

LAYER

*

*

*

*

*

TOP

TOP

TOP

TOP

*

BOTTOM

SENSE_1TO1_55S
SENSE_1TO1_55S

SENSE_1TO1_55S

PHYSICAL

ENET_MDI_100D
ENET_MDI_100D

SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D
SATA_100D

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S
THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S
THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S
THERM_1TO1_55S

THERM_1TO1_55S

THERM_1TO1_55S
THERM_1TO1_55S

THERM_1TO1_55S
THERM_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S
SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

SENSE_1TO1_55S

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

N

N

NET_TYPE

ENETCONN
ENETCONN

SATA
SATA
SATA
SATA
SATA
SATA
SATA
SATA

SENSE

SENSE
SENSE

SENSE
THERM

THERM

THERM
THERM

THERM

THERM
THERM

THERM

THERM
THERM

THERM
THERM

SENSE

SENSE
SENSE

SENSE

SENSE
SENSE

SENSE

SENSE
SENSE

SENSE
SENSE

SENSE

SENSE
SENSE

SB_POWER

SB_POWER

SB_POWER
SENSE

SENSE
SENSE

SENSE

MINIMUM LINE WIDTH

GND

MINIMUM LINE WIDTH

ENETCONN_P<3..0>

ENETCONN_N<3..0>

SATA_ODD_R2D_UF_P
SATA_ODD_R2D_UF_N
SATA_ODD_D2R_UF_P
SATA_ODD_D2R_UF_N

SATA_HDD_D2R_UF_P
SATA_HDD_D2R_UF_N
SATA_HDD_R2D_UF_P

SATA_HDD_R2D_UF_N
GFXIMVP6_VSEN_P
GFXIMVP6_VSEN_N
MCPCOREISNS_P
MCPCOREISNS_N
CPUTHMSNS_D2_P
CPUTHMSNS_D2_N
CPU_THERMD_P
CPU_THERMD_N
GPUTHMSNS_D_P
GPUTHMSNS_D_N
GPU_TDIODE_P
GPU_TDIODE_N
MCPTHMSNS_D_P
MCPTHMSNS_D_N
MCP_THMDIODE_P
MCP_THMDIODE_N

1V05CPUISNS_R_P
1V05CPUISNS_R_N
DDRISNS_R_P
DDRISNS_R_N
GPUISENS_P
GPUISENS_N
1V05CPU_P
1V05CPU_N
DDRISNS_P
DDRISNS_N
P1V8GPU_P
P1V8GPU_N
ISNS_CPU_P
ISNS_CPU_N

GND

PP3V3_S5
PP3V3_S0
PP1V5_S0
P1V8GPUISNS_P
P1V8GPUISNS_N
P1V8GPUISNS_R_P
P1V8GPUISNS_R_N

MINIMUM NECK WIDTH

0.09 MM

0.09 MM

0.09 MM

0.09 MM 100 MIL

0.1 MM

0.1 MM

0.1 MM

0.1 MMTOP

0.25 MM

MINIMUM NECK WIDTH

35

35

39

39

39

39

39

39

39

39

78

78

47

47

48

48

10

10

48

48

48

48

48

48

21

21

47

47

47

47

47

47

47

47

47

47

47

47

46

46

8

7

8

7

47

47

MAXIMUM NECK LENGTH

5.8 MM

5.8 MM

5.8 MM

100 MIL0.09 MM

500 MIL

500 MIL

500 MIL

500 MIL

500 MIL

250 MIL

100 MIL0.23 MM

MAXIMUM NECK LENGTH

65

65

48

48

76

76

48

48

66

66

M99 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

(PCIE_EXCARD)

I164

(PCIE_EXCARD)

I162
I163

(PCIE_MINI)

I161

(PCIE_MINI)

I160
I159

I168

I166
I167

I165

(USB_EXTA)

I182

(USB_EXTA)

I181

(USB_EXTA)

I179

(USB_EXTA)

I180

(USB_EXTD)

I177

(USB_EXTD)

I178

(USB_CAMERA)

I176

(USB_CAMERA)

I175

I174
I172

I173

I171
I169

I170
I183

I184

MCP_PE4_REFCLK

I187
I188

PCIE_FC_R2D

I189

I190

PCIE_FC_D2R

I191

I192

I193
I194

I195
I196

SPK_OUT

I198

I197

SPK_OUT

I201

I200

SPK_OUT

I199
I202

I206

I207
I204

I205
I208

I203

DIFFPAIR PRIMARY GAP

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PHYSICAL

PCIE_90D

PCIE_90D
PCIE_90D

PCIE_90D

CLK_PCIE_100D
CLK_PCIE_100D
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR
1TO1_DIFFPAIR

USB_90D

USB_90D

USB_90D
USB_90D

USB_90D
USB_90D

USB_90D

USB_90D
USB_90D

USB_90D

USB_90D
USB_90D

USB_90D

USB_90D
DP_100D

DP_100D

CLK_PCIE_100D
CLK_PCIE_100D

PCIE_90D
PCIE_90D

PCIE_90D

PCIE_90D
PCIE_90D

PCIE_90D

CLK_PCIE_100D

CLK_PCIE_100D
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR
DIFFPAIR

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

NET_TYPE

SPACINGSPACING

PCIE

PCIE
PCIE

PCIE

CLK_PCIE
CLK_PCIE

USB

USB

USB
USB

USB
USB

USB

USB
USB

USB

USB
USB

USB

USB

DISPLAYPORT
DISPLAYPORT

CLK_PCIE
CLK_PCIE

PCIE
PCIE

PCIE

PCIE
PCIE

PCIE

CLK_PCIE
CLK_PCIE
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO
AUDIO

APPLE INC.

PCIE_EXCARD_R2D_P
PCIE_EXCARD_R2D_N
PCIE_MINI_R2D_P
PCIE_MINI_R2D_N

PCIE_CLK100M_MINI_CONN_P
PCIE_CLK100M_MINI_CONN_N

CHGR_CSI_R_P
CHGR_CSI_R_N
CHGR_CSO_R_P
CHGR_CSO_R_N

USB2_EXTA_MUXED_P
USB2_EXTA_MUXED_N

USB2_LT1_P
USB2_LT1_N

CONN_TPAD_USB_P
CONN_TPAD_USB_N
USB_CAMERA_CONN_P
USB_CAMERA_CONN_N
CONN_USB2_BT_P
CONN_USB2_BT_N

USB_LT2_P
USB_LT2_N

USB2_EXCARD_CONN_P
USB2_EXCARD_CONN_N

DP_IG_AUX_CH_C_P
DP_IG_AUX_CH_C_N
PCIE_CLK100M_FC_P
PCIE_CLK100M_FC_N
PCIE_FC_R2D_C_P
PCIE_FC_R2D_C_N
PCIE_FC_D2R_P
PCIE_FC_D2R_N
PCIE_FC_R2D_P

PCIE_FC_R2D_N
PCIE_CLK100M_EXCARD_CONN_N
PCIE_CLK100M_EXCARD_CONN_P

SPKRCONN_L_P_OUT
SPKRCONN_L_N_OUT
SPKRCONN_S_P_OUT
SPKRCONN_S_N_OUT
SPKRCONN_R_P_OUT
SPKRCONN_R_N_OUT

SPKRAMP_L_P_OUT
SPKRAMP_L_N_OUT
SPKRAMP_R_P_OUT
SPKRAMP_R_N_OUT
SPKRAMP_S_P_OUT
SPKRAMP_S_N_OUT

Project Specific Constraints

SYNC_MASTER=MUXGFX

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

32

7

32

7

89

31

89

31

31

31

61

61

61

46

61

46

40

40

40

40

31

31

31

31

40

40

32

7

32

7

80

80

32

9

32

9

32

9

32

9

32

9

32

9

32

32

7

7

7

7

7

7

57

57

57

57

57

57

SYNC_DATE=02/21/2008

051-7546

SHT

89

89

D

32

7

32

7

57

58

57

58

58

57

58

57

58

57

58

57

C

B

A

REV.

A.0.0

OF

9695

8

7 6

5

4

3

2

1

8 7

M99 Board-Specific Spacing & Physical Constraints

BOARD LAYERS

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

LAYER

DEFAULT

STANDARD

D

55_OHM_SE

55_OHM_SE

LAYER

TOP,BOTTOM

LAYER

50_OHM_SE

50_OHM_SE =STANDARD

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

* Y

Y*

Y

Y

Y

Y

MINIMUM LINE WIDTH

=50_OHM_SE

MINIMUM LINE WIDTH

0.090 MM

0.076 MM

MINIMUM LINE WIDTH

0.090 MM

MINIMUM NECK WIDTH

=50_OHM_SE

=DEFAULT=DEFAULT

MINIMUM NECK WIDTH

0.090 MM

0.076 MM

MINIMUM NECK WIDTH

0.095 MM0.110 MM

0.090 MM

BOARD AREAS

NO_TYPE,BGA

MAXIMUM NECK LENGTH

14 MM

10 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

6

BOARD UNITS
(MIL or MM)

DIFFPAIR PRIMARY GAP

0 MM

=DEFAULT =DEFAULT

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

MM

0 MM

=STANDARD

=STANDARD=STANDARD

ALLEGRO
VERSION

15.5.1

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_BOARD_INFO

SPACING_RULE_SET

SPACING_RULE_SET

DEFAULT

STANDARD

BGA_P1MM

BGA_P3MM

1.5:1_SPACING

1.8:1_SPACING

2:1_SPACING

2.5:1_SPACING

3:1_SPACING

4:1_SPACING

5

LAYER

LAYER

LINE-TO-LINE SPACING

*

*

*

*

* ?

0.1 MM

=DEFAULT

=DEFAULT

=DEFAULTBGA_P2MM

=DEFAULT

LINE-TO-LINE SPACING

0.15 MM

0.18 MM

*

0.2 MM

0.25 MM

0.3 MM

0.4 MM

WEIGHT

WEIGHT

4

TABLE_SPACING_RULE_HEAD

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

TABLE_SPACING_RULE_ITEM

?*

* *

MEM_CLK

CLK_FSB

CLK_PCIE

CLK_SLOW

FSB_DSTB BGA_P3MMFSB_DSTB

*

*

*

*

NOTE:From T18 MLB, changed to reflect M99 stackup.

SPACING_RULE_SET

2X_DIELECTRIC
3X_DIELECTRIC
4X_DIELECTRIC
5X_DIELECTRIC

LAYER

*
*
*
*

AREA_TYPE

LINE-TO-LINE SPACING

0.140 MM

0.210 MM

0.280 MM

0.350 MM

BGA

BGA

BGA

BGA

BGA

BGA

3

BGA_P1MM

BGA_P2MM

BGA_P2MM

BGA_P2MM

BGA_P2MM

WEIGHT

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

TABLE_SPACING_RULE_ITEM

?

SPACING_RULE_SET

2 1

D

=STANDARD

=STANDARD

=STANDARD

0.175 MM0.175 MM

0.150 MM0.150 MM

=STANDARD

0.180 MM0.180 MM

0.190 MM0.190 MM

=STANDARD

0.220 MMISL9,ISL10

0.230 MM0.230 MM

=STANDARD=STANDARD

0.200 MM0.200 MM

0.200 MM

0.220 MM0.220 MM

=STANDARD

0.330 MM

0.330 MM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

1:1_DIFFPAIR

100_DIFF_BGA

100_DIFF_BGA

100_DIFF_BGA

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

LAYER

LAYER

ISL9,ISL10

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

*

=100_OHM_DIFF

Y*

Y

Y

MINIMUM LINE WIDTH

=STANDARD =STANDARD

MINIMUM LINE WIDTH

=100_OHM_DIFF =100_OHM_DIFF

0.075 MM

0.075 MM

MINIMUM NECK WIDTH

=STANDARD

MINIMUM NECK WIDTH

=100_OHM_DIFF

0.075 MM

0.075 MM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

0.1 MM 0.1 MM

DIFFPAIR PRIMARY GAP

=100_OHM_DIFF =100_OHM_DIFF

0.125 MM 0.125 MMISL3,ISL4

0.125 MM 0.125 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PCB Rule Definitions

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

SYNC_DATE=01/22/2008

051-7546

SHT

96 96

C

B

A

REV.

A.0.0

OF

LAYER

40_OHM_SE

40_OHM_SE

C

27P4_OHM_SE

27P4_OHM_SE

TOP,BOTTOM

LAYER

TOP,BOTTOM

LAYER

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

70_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

80_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

*

ALLOW ROUTE
ON LAYER?

*

Y

Y

Y

Y*

N

Y

Y

Y

Y

N

Y

Y

Y

Y

MINIMUM LINE WIDTH

0.165 MM

0.135 MM

MINIMUM LINE WIDTH

MINIMUM LINE WIDTH

=STANDARD

0.170 MM

0.170 MM

MINIMUM LINE WIDTH

=STANDARD

0.140 MM

0.140 MM

MINIMUM NECK WIDTH

0.095 MM

0.135 MM

MINIMUM NECK WIDTH

0.095 MM0.310 MM

0.250 MM0.250 MM

MINIMUM NECK WIDTH

=STANDARD

0.160 MM0.160 MM

0.160 MM0.160 MM

0.170 MM

0.095 MM

MINIMUM NECK WIDTH

=STANDARD

0.125 MM0.125 MM

0.125 MM0.125 MM

0.140 MM

0.095 MM

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

MAXIMUM NECK LENGTH

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

0.175 MM 0.175 MM

0.150 MM 0.150 MM

DIFFPAIR PRIMARY GAP

=STANDARD

0.180 MM 0.180 MM

0.190 MM 0.190 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

B

LAYER

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

90_OHM_DIFF

ISL3,ISL4

ISL2,ISL11

TOP,BOTTOM

LAYER

100_OHM_DIFF

100_OHM_DIFF

100_OHM_DIFF

100_OHM_DIFF

A

100_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

LAYER

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

110_OHM_DIFF

ISL3,ISL4

ISL9,ISL10

ISL2,ISL11

TOP,BOTTOM

ALLOW ROUTE
ON LAYER?

ALLOW ROUTE
ON LAYER?

* N

ALLOW ROUTE
ON LAYER?

*

N*

Y

Y

Y

Y

Y

Y

Y

Y

N

Y

Y

Y

Y

MINIMUM LINE WIDTH

0.102 MM

0.102 MM 0.102 MM

0.115 MM

0.115 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD

0.080 MM

0.080 MM

0.089 MM

0.089 MM 0.089 MM

MINIMUM LINE WIDTH

=STANDARD =STANDARD

0.077 MM

0.077 MM

0.077 MM

0.077 MM 0.077 MM

MINIMUM NECK WIDTH

0.102 MM

0.115 MM

0.095 MM

MINIMUM NECK WIDTH

=STANDARD

0.080 MM

0.080 MM

0.089 MM

MINIMUM NECK WIDTH

0.077 MM

0.077 MM

0.077 MM

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

MAXIMUM NECK LENGTH

=STANDARD=STANDARD=STANDARD

=STANDARD

DIFFPAIR PRIMARY GAP

=STANDARD

0.220 MM 0.220 MM

0.220 MM

0.230 MM 0.230 MM

DIFFPAIR PRIMARY GAP

0.200 MM

0.220 MM 0.220 MM

DIFFPAIR PRIMARY GAP

=STANDARD

0.330 MM

0.330 MM

0.330 MM 0.330 MM

0.330 MM 0.330 MM

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

8

7 6

5

4

3

2

1