Apple A1286 Schematic RevA.0.0

8 7

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

6

5

4

SCHEM,MBP 15"MLB

08/18/2008

3

REV

? ?

2 1

ZONE

DESCRIPTION OF CHANGE

ECN

?

CK
APPD

DATE

? ?

ENG
APPD

DATE

Date

N/A1

12/12/2007

12/12/2007

N/A4

N/A5

07/22/2008

N/A7

(MASTER)

(MASTER)

10/17/2007

10/17/2007

10/17/2007

01/08/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

06/18/2008

03/31/2008

06/18/2008

06/18/2008

12/17/2007

07/22/2008

07/22/2008

07/22/2008

06/18/2008

07/02/2008

07/02/2008

07/01/2008

07/01/2008

07/01/2008

08/14/2008

08/14/2008

08/14/2008

07/01/2008

07/02/2008

07/01/2008

06/18/2008

06/18/2008

07/01/2008

07/22/2008

Page

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54

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55

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56

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57

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58

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59

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60

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61

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62

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64

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90

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

53

Current & Voltage Sensing

54

Current Sensing

55

Thermal Sensors

56

Fan Connectors

57

WELLSPRING 1

58

WELLSPRING 2

59

Sudden Motion Sensor (SMS)

61

SPI ROM

62

AUDIO:CODEC

63

AUDIO: LINE IN

65

AUDIO: HEADPHONE AMP

66

AUDIO:SPEAKER AMP

67

AUDIO: JACKS

68

AUDIO: JACK TRANSLATORS

69

DC-In & Battery Connectors

70

PBus Supply & Battery Charger

71

IMVP6 CPU VCore Regulator

72

5V / 3.3V Power Supply

73

1.5V DDR3 Supply

75

1.05V / MCP Core Regulator

76

CPU VTT Power Supply

77

Misc Power Supplies

78

Power Control

79

Power FETs

80

NV G96 PCI-E

81

NV G96 Core/FB Power

82

NV G96 Frame Buffer I/F

84

GDDR3 Frame Buffer A (Top)

85

GDDR3 Frame Buffer B (Top)

86

NV G96 GPIO/MIO/Misc

87

G96 GPIOs & Straps

88

NV G96 Video Interfaces

89

GPU (G84M) Core Supply

90

LVDS Display Connector

93

Muxed Graphics Support

94

DisplayPort Connector

95

1.1V / 1V8 FB Power Supply

96

Graphics MUX (GMUX)

97

LCD BACKLIGHT DRIVER

98

LCD Backlight Support

99

Misc Power Supplies

100

CPU/FSB Constraints

101

Memory Constraints

102

MCP Constraints 1

103

MCP Constraints 2

Contents

Sync

SENSOR

SENSOR

SENSOR

M87_MLB

AMASON_M98_MLB

PWRSQNC

SENSOR

CHANG_M98_MLB

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

AUDIO

T18_MLB

M99_MLB

M87_MLB

M99_MLB

M99_MLB

M99_MLB

M99_MLB

M99_MLB

PWRSQNC

PWRSQNC

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

M87_MLB

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

YITE_M98_MLB

YITE_M98_MLB

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

Date

08/14/2008

08/14/2008

08/14/2008

10/17/2007

06/18/2008

05/12/2008

08/14/2008

07/01/2008

07/09/2008

07/09/2008

07/09/2008

07/09/2008

07/09/2008

07/09/2008

12/06/2007

12/10/2007

10/17/2007

01/09/2008

12/13/2007

01/08/2008

12/14/2007

12/14/2007

05/12/2008

05/12/2008

07/10/2008

07/10/2008

07/10/2008

07/10/2008

07/10/2008

07/10/2008

07/09/2008

07/10/2008

10/17/2007

02/25/2008

07/10/2008

07/10/2008

07/10/2008

07/10/2008

07/02/2008

07/02/2008

02/01/2008

02/18/2008

02/18/2008

02/18/2008

02/18/2008

Page

TABLE_TABLEOFCONTENTS_HEAD

91

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92

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93

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94

TABLE_TABLEOFCONTENTS_ITEM

95

TABLE_TABLEOFCONTENTS_ITEM

96

TABLE_TABLEOFCONTENTS_ITEM

(.csa)

104

Ethernet Constraints

105

FireWire Constraints

106

SMC Constraints

107

GPU (G96) Constraints

108

Project Specific Constraints

109

PCB Rule Definitions

Contents Sync

MUXGFX

MUXGFX

MUXGFX

MUXGFX

MUXGFX

M99_MLB

Date

02/18/2008

02/18/2008

02/18/2008

02/18/2008

02/21/2008

01/22/2008

D

C

B

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45

(.csa)

Contents Sync

Table of Contents

2

System Block Diagram

3

Power Block Diagram
Power Block Diagram
BOM Configuration

6

JTAG Scan Chain
Functional / ICT Test

8

Power Aliases

9

Signal Aliases

10

CPU FSB

11

CPU Power & Ground

12

CPU Decoupling & VID

13

eXtended Debug Port(MiniXDP)

14

MCP CPU Interface

15

MCP Memory Interface

16

MCP Memory Misc

17

MCP PCIe Interfaces

18

MCP Ethernet & Graphics

19

MCP PCI & LPC

20

MCP SATA & USB

21

MCP HDA & MISC

22

MCP Power & Ground

24

MCP79 A01 Silicon Support

25

MCP Standard Decoupling

26

MCP Graphics Support

28

SB Misc

29

FSB/DDR3/FRAMEBUF Vref Margining

31

DDR3 SO-DIMM Connector A

32

DDR3 SO-DIMM Connector B

33

DDR3 Support

34

Right Clutch Connector

35

ExpressCard Connector

37

Ethernet PHY (RTL8211CL)

38

Ethernet & AirPort Support

39

Ethernet Connector

41

FireWire LLC/PHY (FW643)

42

FireWire Port Power

43

FireWire Ports

45

SATA Connectors

46

External USB Connectors

48

Front Flex Support

49

SMC

50

SMC Support

51

LPC+SPI Debug Connector

52

M98 SMBus Connections

N/A

T18_MLB

T18_MLB

N/A

N/A

DDR

N/A

(MASTER)

(MASTER)

M87_MLB

M87_MLB

M87_MLB

M99_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

T18_MLB

AMASON_M98_MLB

T18_MLB

DDR

DDR

DDR

T18_MLB

YITE_M98_MLB

YITE_M98_MLB

SUMA_M98_MLB

SUMA_M98_MLB

SUMA_M98_MLB

SENSOR

SENSOR

SENSOR

CHANG_M98_MLB

AMASON_M98_MLB

CHANG_M98_MLB

T18_MLB

AMASON_M98_MLB

CHANG_M98_MLB

DDR

D

C

B

Page

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A

Schematic / PCB #’s

PART NUMBER

DRAWING

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Mon Aug 18 01:48:34 2008

QTY

1
1

8

DESCRIPTION

SCHEM,FIBBO,M98

PCBF,FIBBO,M98

REFERENCE DES

SCH
PCB

CRITICAL

CRITICAL051-7546
CRITICAL820-2330

BOM OPTION

7 6

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

ANGLES

DO NOT SCALE DRAWING

THIRD ANGLE PROJECTION

5

4

3

DRAFTER

ENG APPD

QA APPD

RELEASE

METRIC

MATERIAL/FINISH

NOTED AS

APPLICABLE

DESIGN CK

MFG APPD

DESIGNER

SCALE

NONE

SIZE

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

TITLE

SCHEM,MBP 15MLB

DRAWING NUMBER

D

APPLE INC.

051-7546

A

REV.

1

A.0.0

OF

96

SHT

1

8 7

6

U1000

INTEL CPU

2.X OR 3.X GHZ
PENRYN

PG 9

5

U1300

XDP CONN

PG 12

4

3

2 1

FSB

D

PG 13

GPIOs

FSB INTERFACE

64-Bit

800/1067/1333 MHz

MAIN

MEMORY

PG 14

2 UDIMMs

DDR2-800MHZ

DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

J6950

U4900

DC/BATT

PG 60

D

POWER SUPPLY

TEMP SENSOR

CLK

SYNTH

J4510

SATA
Conn

PG 38

HD

J4520

SATA
Conn

PG 38

C

ODD

1.05V/3GHZ.

1.05V/3GHZ.

SATA

PG 19

NVIDIA

MCP79

U1400

J9000

LVDS
CONN

PG 71

J9400

DISPLAY PORT

CONN

PG 71

LVDS OUT

RGB OUT

DP OUT

HDMI OUT

DVI OUT

TMDS OUT

PG 17

UP TO 20 LANES3

PCI-E

PG 16

B

RGMII

PG 17

PCI

(UP TO FOUR PORTS)

PG 18

Misc

PG 24

SPI

PG 20

LPC

PG 18

PWR

CTRL

J4720

Bluetooth

USB

PG 19

4
3 8 9
2

(UP TO 12 DEVICES)

10 5 6 7

SMB

PG 20

HDA

PG 20

PG 40

U6100

SPI

Boot ROM

PG 52

J4700

TRACKPAD/

KEYBOARD

PG 40

DIMM’s

J4710

J4900

IR

PG 40

B,0

BSB

SMC

PG 41

J4710

FanADC

CAMERA

PG 40

SMB

CONN

PG 44

J5650,5600,5610,5611,5660,5720,5730,5750

FAN CONN AND CONTROL

Ser
Prt

J3900,4635,4655

EXTERNAL

USB

Connectors

PG 41

POWER SENSE

PG 45

PG 48,49

J5100

Port80,serial

PG 39

LPC Conn

PG 43

C

B

U6200

U3700

A

J3400 U3900

Mini PCI-E

AirPort

PG 28

8

7 6

GB

E-NET

88E1116

PG 31

E-NET

Conn

PG 33

5

U6301 U6500U6400

Line In

Amp

PG 54

HEADPHONE

Amp Amp

J6800,6801,6802,6803

4

Audio
Codec

PG 53

Audio
Conns

PG 59

Line Out

PG 56PG 55

U6600,6605,6610,6620

Speaker

Amps

PG 57

System Block Diagram

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=12/12/2007

051-7546

SHT

OF

2 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

AC

ADAPTER

IN

3S2P

(9 TO 12.6V)

C

MCP79

SLP_S5#(H17)

SLP_S3#(G17)

U1400

(PAGE 14~22)

B

A

DELAY

DELAY

DELAY

DELAY

DELAY

DCIN(16.5V)

J6950

P5VRIGHT_EN

RC

P1V8S0_EN

RC

MCPDDR_EN

RC

CPUVTTS0_EN

RC

MCPCORES0_EN

RC

M98 POWER SYSTEM ARCHITECTURE

6A FUSE

BATT_POS_F

Q3801

PM_ENET_EN_L

PM_SLP_S3_L

U5705

A

LIO_DCIN_ISENSE

Q7055

CHGR_BGATE

P3V3S3_EN

P5VS3_EN

LIO_S3_EN

Q3805

WOW_EN

PM_ENET_EN

PM_ENET_EN_L

Q3800

WOL_EN
SMC_ADAPTER_EN

P5VS0_EN

(S0)

P3V3S0_EN

(S0)

PBUSVSENS_EN

(S0)

PM_SLP_S3_DELAY_L

(S0)

PM_WLAN_EN_L

RC

DELAY

CHGR_EN

(S5)

ENABLES

VIN

(PAGE 60)
PBUS SUPPLY/
BATTERY CHARGER

ISL6258A

U7000

PPVBAT_G3H_CHGR_R

SMC

U4900

(PAGE 42)

P5V_RT_EN

BKLT_EN

DDRREG_EN

DDRVTT_EN

VOUT

P60

PPVBAT_G3H_CHGR_REG

A

PPBUS_G3H

P1V1GPU_EN

U7859

SMC_PM_G2_EN

(S5)

VIN

U7400

EN/PSV

SC417

(PAGE 64)

ENL

VIN
GOSHAWK6P

U9701

ENA

(PAGE 84)

P1V2ENET_EN

ENETAVDD_EN

VIN

S5
S3

TPS51116
(PAGE 63)

MCPCORES0_EN

P1V05S0_EN

PGOOD

1.8V

0.9V

U7300

PP5V_RT_REG

VOUT

P5V_RT_PGOOD

VOUT

PPVIN_S0_DDRREG_LDO

VLDOIN

VOUT1

VOUT2

D6905

D6905

8A FUSE

U5715

SMC_BATT_ISENSE

IMVP_VR_ON_R

VIN

EN1

1.103V(L/H)

P1V8FB_EN

PPVOUT_S0_LCDBKLT

VIN

RUN2

(PAGE 33)

RUN1

PPDDR_S3_REG

(12A MAX CURRENT)

PPVTT_S0_DDR_LDO

P3V3S5_EN

LTC3407

VOUT1

U3850

VOUT2

MCP_CORE

EN2

EN1

VIN

(PAGE 65)

EN2

1.8V(R/H)

TPS51124

U9500

(PAGE 82)

VOUT2

1.1V

VOUT1

ISL6236

U7500

PPVIN_G3H_P3V42G3H

PBUSB_VSENSE

PPBUS_G3H

PM_GPUVCORE_EN

CPU VCORE

VIN

ISL9504B

VR_ON

VOUT

U7100

PGOOD

(PAGE 61)

VOUT1

VOUT2

PP1V9_ENET_REG

PP1V2_ENET_REG

PP1V1_S0GPU_REG

PP1V8_GPU_REG

VIN

EN0

PGOOD1,2

MCPCPCORE_S0_REG

PP5V_RT_REG

VOUT1

5V

(L/H)

VOUT2

3.3V

(R/H)

TPS51125

U7201

(PAGE 62)

VREG3

P5V3V3_S5_PGOOD

ENABLE

3.425V G3HOT

LT3470

V

Q5315

(PAGE 59)

U5498

GPU VCORE

VIN

ISL6263B

EN_PSV

(PAGE 78)

U5400

A

VR_PWRGD_CLKEN_L
VR_PWRGOOD_DELAY

PP5V_S5_REG
(8A MAX CURRENT)

PP3V3_S5_REG
(5.5A MAX CURRENT)

VOUT

U8900

PGOOD

GPUVCORE_PGOOD

SMC_CPU_VSENSE

V

CPUVCORE_IOUT

Q7920

Q7900

(25A MAX CURRENT)

(5A MAX CURRENT)

U6990

PP3V42_G3H_REG

SMC_GPU_VSENSE

V

A

GPUVCORE_IOUT

PPVCORE_CPU_S0

PP5V_S0_FET

P5VS0_SS

PP5V_S3_FET

P5VS3_SS

Q7910

P3V3S3_SS

Q7930

Q7970

Q3810

PP3V3_S0GPU_FET

P3V3S0_SS

P3V3GPU_SS

P3V3ENET_EN_L

PPVCORE_GPU_REG

(18A MAX CURRENT)

PP3V3_S0_FET

P3V3_ENET_FET

SMC PWRGD

RN5VD30A-F

U5000

(PAGE 43)

CPUVTTS0_EN

PP3V3_S3_FET

S0PGOOD_PWROK

PP5V_S0
PP3V3_S0

PP1V5_S0_REG

SMC_RESET_L

EN_PSV

PP5V_S3

PP3V3_S5

P1V05S0_PGOOD

P5VRIGHT_PGOOD
MCPCORES0_PGOOD
CPUVTTS0_PGOOD

P1V8S0_PGOOD

P1V5S0_PGOOD

RST*

V1
V2
V3

LTC2900

V4

U7870

(PAGE 68)

VIN

VOUT

1.05V

TPS51117

U7600

(PAG 66)

PGOOD

CPUVTTS0_PGOOD

U2830

VR_PWRGD_CLKEN

ALL_SYS_PWRGD

PPCPUVTT_S0_REG

(6A MAX CURRENT)

MCP_PS_PWRGD

U2850

ISL8009

V4

U7750

(PAGE 66)

RSMRST_PWRGD

SMC_ONOFF_L

PM_SLP_S5_L
PM_SLP_S4_L
PM_SLP_S3_L

APPLE INC.

MCP79

CK_PWRGD

VRMPWRGD

PWROK

CPUPWRGD(GPIO49)

(PAGE 14~22)

(PAGE 10,11)

PWRGD(P12)

RSMRST_IN(P13)

PWR_BUTTON(P90)

SLP_S5_L(P95)
SLP_S4_L(P94)
SLP_S3_L(P93)

PWRBTN#

PLTRST*
RSMRST*

U1400

CPU

PWRGOOD

U1000

RESET*

PP1V05_S5_MCP

SMC

RSMRST_OUT(P15)

99ms DLY

IMVP_VR_ON(P16)

PLT_RST*

P17(BTN_OUT)

RST*

U4900

(PAGE 42)

PLT_RST_L

CPU_PWRGD

PM_RSMRST_L

IMVP_VR_ON

PM_PWRBTN_L

SMC_RESET_L

Power Block Diagram

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

SHT

SYNC_DATE=12/12/2007

051-7546

3

REV.

OF

96

D

C

B

A

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

C

D

C

B

B

Power Block Diagram

A

8

7 6

5

4

3

SYNC_MASTER=N/A

APPLE INC.

2

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

SYNC_DATE=N/A

OF

4 96

1

A

REV.

A.0.0

8 7

BOM Variants

BOM NUMBER

630-9334
630-9335
630-9336
630-9337
630-9585
630-9586

D

M98 BOM Groups

PCBA,2.4GHZ,256SAM_VRAM,M98
PCBA,2.4GHZ,256HYN_VRAM,M98
PCBA,2.5GHZ,512SAM_VRAM,M98
PCBA,2.5GHZ,512QIM_VRAM,M98
PCBA,2.8GHZ,512SAM_VRAM,M98
PCBA,2.8GHZ,512QIM_VRAM,M98

BOM GROUP

M98_COMMON
M98_COMMON1
M98_COMMON2
M98_COMMON3

M98_DEBUG

M98_PROGPARTS

BOM GROUP

FB_256_SAMSUNG

FB_256_HYNIX
FB_512_SAMSUNG
FB_512_QIMONDA

BOM NAME

ALTERNATE,COMMON,M98_COMMON1,M98_COMMON2,M98_COMMON3,M98_DEBUG,M98_PROGPARTS

ONEWIRE_PU,ISL6258A,MEMRESET_HW,MEMRESET_MCP,MCP_B02,MCP_PROD,MCPSEQ_SMC

BKLT_PLL_NOT,BMON_ENG,MIKEY,BOOT_MODE_USER,GPUVID_1P00V,MUXGFX

DPMUX_EN_S0,DP_ESD,EG_PWRSEQ_HW,DP_CA_DET_EG_PLD,MCP_CS1_NO

Bar Code Labels / EEE #’s

C

PART NUMBER

826-4393

826-4393

826-4393

QTY

1
1
1
1
1
1

DESCRIPTION

LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM
LBL,P/N LABEL,PCB,28MM X 6 MM

BOM OPTIONS

M98_COMMON,EEE_0ZA,CPU_2_4GHZ,FB_256_SAMSUNG

M98_COMMON,EEE_0ZB,CPU_2_4GHZ,FB_256_HYNIX
M98_COMMON,EEE_0ZC,CPU_2_5GHZ,FB_512_SAMSUNG
M98_COMMON,EEE_0ZD,CPU_2_5GHZ,FB_512_QIMONDA
M98_COMMON,EEE_2NH,CPU_2_8GHZ,FB_512_SAMSUNG
M98_COMMON,EEE_2NJ,CPU_2_8GHZ,FB_512_QIMONDA

BOM OPTIONS

SMC_DEBUG_YES,XDP,LPCPLUS,VREFMRGN

GMUX_PROG,BOOTROM_PROG,SMC_PROG,TPAD_PROG

BOM OPTIONS

VRAM4,VRAM_256_SAMSUNG

VRAM4,VRAM_256_HYNIX
VRAM4,VRAM_512_SAMSUNG
VRAM4,VRAM_512_QIMONDA

REFERENCE DES

[EEE:0ZA]
[EEE:0ZB]
[EEE:0ZC]
[EEE:0ZD]
[EEE:2NH]
[EEE:2NJ]

CRITICAL

CRITICAL
CRITICAL826-4393
CRITICAL
CRITICAL826-4393
CRITICAL826-4393
CRITICAL

BOM OPTION

EEE_0ZA
EEE_0ZB
EEE_0ZC
EEE_0ZD
EEE_2NH
EEE_2NJ

6

5

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

4

3

2 1

D

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

TABLE_BOMGROUP_ITEM

C

Module Parts

PART NUMBER

337S3639
337S3640
338S0554
338S0570
338S0523
338S0600
338S0563
341S2289

B

A

335S0384
341S2366 CRITICAL
341S2272
341S2384
338S0635
341S2383
337S3641
333S0482 CRITICAL
333S0483

333S0472

PART NUMBER

138S0603

353S1681

152S0276 152S0683

152S0876 152S0867

157S0058

353S2312

514-0613

152S0915

ALTERNATE FOR
PART NUMBER

138S0602

353S1294

341S2366341S2367

157S0055

353S1466

514-0607514-0612

514-0608

152S0796

QTY

1
1
1

IC,GPU,55nm,NV G96-GS,BGA969,LF

1

IC,RTL8211CL,GIGE TRANSCEIVER,48P TQFP

1
1
1
1
1
1
1
1
1
1
1
4
4
4
4

BOM OPTION

DESCRIPTION

IC,PDC,SLB4N,PRQ,2.4G,25W,1066,M0,3M,BGA

IC,PDC,SL3BX,PRQ,2.53G,35W,1066,C0,6M,BGA

IC,FW643-06,1394B PHY/OHCI LINK/PCI-E,12

IC,GMCP,MCP79-B01,35x35MM,BGA1437

IC,SMC,HS8/2117,9MMX9MM,TLP

IC,SMC,DEVELOPMENT,M98

IC,32MBIT 8-PIN SPI SERIAL FLASH,SOIC8

IC,EFI ROM,DEVELOPMENT,M98

IC,HDCP ROM,NVG96, 8 PIN SOIC,LF,HF

IR,ENCORE II, CY7C63803-LQXC

IC,GMCP,MCP79-B02,35x35MM,BGA1437

IC,PSOC +W/USB,56PIN,MLF,M98

IC,PDC,SLB43,PRQ,2.8G,35W,1066,C0,6M,BGA

IC,SGRAM,GDDR3,16Mx32,800MHZ,136 FBGA

IC,SGRAM,GDDR3,16Mx32,900MHZ,136 FBGA

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

IC,SGRAM,GDDR3,32Mx32,900MHZ,136 FBGA

REF DES

ALL

ALL

ALL

ALL

ALL

ALL

ALL INTERSIL ALT TO INTERSIL

ALL

ALL

ALL

COMMENTS:

Murata alt to Samsung

LMV2011,OPAMP. GBW

Maglayers alt to Dale/Vishay

Macronix alt to SST

Maglayer alt to Delta

Delta alt to TDK Magnetics

FOXLINK XCVR ALT TO FOXCONN

FOXLINK RCVR ALT TO FOXCONN

Maglayers alt to Cyntec IND

REFERENCE DES

U1000
U1000
U8000
U3700
U4100
U1400
U4900
U4900
U6100
U6100
U8770
U4800
U1400
U5701

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

U8400,U8450,U8500,U8550

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM

CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL
CRITICAL
CRITICAL
CRITICAL
CRITICAL

CRITICAL
CRITICAL333S0481
CRITICAL

BOM OPTION

CPU_2_4GHZ
CPU_2_5GHZ

MCP_B01

SMC_BLANK

SMC_PROG

BOOTROM_BLANK

BOOTROM_PROG

HDCP_YES

MCP_B02

TPAD_PROG

CPU_2_8GHZU1000

VRAM_256_SAMSUNG

VRAM_256_HYNIX
VRAM_512_SAMSUNG
VRAM_512_QIMONDA

BOM Configuration

SYNC_MASTER=N/A

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7546

SHT

SYNC_DATE=N/A

OF

5 96

B

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

1.05V TO 3.3V LEVEL TRANSLATOR (M98: ON ICT FIXTURE)

=PP3V3_S0_XDP

13

8

6

D

62 13 12

C

11

10

8

=PP1V05_S0_CPU

JTAG_ALLDEV

R0601

1/16W
MF-LF

NOSTUFF

R0602

1/16W
MF-LF

10K

402

402

To XDP connector
and/or level translator

XDP

R0603

10

21

XDP_TDO

JTAG_MCP_TDO

1 2

1/16W
MF-LF

402

XDP

R0604

1 2

1/16W
MF-LF

402

PLACEMENT_NOTE=Place near pin U1000.AB3

0

5%

PLACEMENT_NOTE=Place near pin U1400.F19

0

5%

XDP_TDO_CONN

JTAG_MCP_TDO_CONN

OUT

XDP connector

OUT

XDP connector

13

13

21

13

23

21

13

23

21

13

21

13

U1000

CPU

87

U1400

MCP

MAKE_BASE=TRUE

From XDP connector

JTAG_ALLDEV

1

C0601

0.1UF

20%
10V

2

CERM
402

1

5%

2

87

13

1

0

5%

2

87

13

87

13

XDP_TCK

10

6

XDP_TMS

10

6

XDP_TRST_L

10

6

JTAG_LVL_TRANS_EN_L

JTAG_ALLDEV

1

C0602

0.1UF

20%
10V

2

CERM
402

NLSV4T244

2

A1

3

A2

4

A3

5

A4

12

OE*

1

11

VCCB

VCCA

U0600

UQFN

JTAG_ALLDEV

GND

6

IN
IN
IN
IN

XDP_TCK
XDP_TDI
XDP_TMS
XDP_TRST_L

6

10 13 87

10 13 87

6

10 13 87

6

10 13 87

From XDP connector

or via level translator

10

B1

9

B2

8

B3

7

B4

1

R0606

10K

5%
1/16W
MF-LF
402

2

MAKE_BASE=TRUE

MAKE_BASE=TRUE

JTAG_MCP_TCK
JTAG_MCP_TDI
JTAG_MCP_TMS
JTAG_MCP_TRST_L

D

C

NOSTUFF

R0605

1 2

75

75

75

6

75

83

83

9

83

9

U8000

GPU

U9200

GMUX

75

83

9

GPU_JTAG_TDO

JTAG_GMUX_TDO

6

VCC

U0601

74LVC1G07

2

1

GMUX CPLD Programming Port

NC NC

CRITICAL

J0600

1909782

M-RT-SM

7

=PP3V3_S0_XDP

1
2

TDO

3

TDI
TMS

4
5

TCK

B

6

8

13

8

6

YA

4

5

NCNC

SOT886

GND

3

PLACEMENT_NOTE=Place close to U0600

GPU_JTAG_TCK

GPU_JTAG_TDI
GPU_JTAG_TMS
GPU_JTAG_TRST_L

JTAG_GMUX_TCK

JTAG_GMUX_TDI
JTAG_GMUX_TMS

=PP3V3_GPU_VDD33

76

TP_GPU_JTAG_TDO

MAKE_BASE=TRUE

PLACEMENT_NOTE=Place close to U8000

10K

5%
1/16W
MF-LF

402

GPU_JTAG_TMS

75 75

6 8

B

JTAG Scan Chain

A

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=07/22/2008

051-7546

SHT

1

A

REV.

A.0.0

OF

966

8 7

6

5

4

3

2 1

Functional Test Points

Fan Connectors

FUNC_TEST

3 TPs

D

TRUE

TRUE
TRUE

TRUE
TRUE
TRUE

=PP5V_S0_FAN_LT
FAN_LT_PWM

FAN_LT_TACH
FAN_RT_PWM

FAN_RT_TACH
GND

LVDS Connectors

FUNC_TEST

I568
I567

I570
I571

I572

I573
I569

I574
I566

I575

C

I576

I577

I578
I579

I580

I581

I582

I583

I584

I585
I586

I587

I588

I590
I589

I592

I591

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

=PP3V3_S0_DDC_LCD
PP3V3_SW_LCD

BKL_SYNC

LVDS_DDC_CLK
LVDS_DDC_DATA
LVDS_CONN_A_DATA_N<0>
LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_N<1>
LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_N<2>
LVDS_CONN_A_DATA_P<2>

LVDS_CONN_A_CLK_F_N
LVDS_CONN_A_CLK_F_P
LVDS_CONN_B_DATA_N<0>
LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_N<1>
LVDS_CONN_B_DATA_P<1>

LVDS_CONN_B_DATA_N<2>
LVDS_CONN_B_DATA_P<2>

LVDS_CONN_B_CLK_F_N
LVDS_CONN_B_CLK_F_P

LED_RETURN_1
LED_RETURN_2
LED_RETURN_3
LED_RETURN_4
LED_RETURN_5
LED_RETURN_6

76

8

79

84

79

80

79

80

79

79

80

80

79

80

79

79

80

79

80

80

79

79

94

79

94

80

79

79

80

80

79

80

79

80

79

80

79

94

79

94

79

84

79

84

79

79

84

79

84

84

79

84

79

EXCARD Connector

FUNC_TEST

TRUE

B

I642

I643
I644

I645

I646
I648

I647

I650
I649

I651
I653

I652

I654
I655

I641

I657
I656

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

USB2_EXCARD_CONN_N
USB2_EXCARD_CONN_P
PCIE_CLK100M_EXCARD_CONN_N
PCIE_CLK100M_EXCARD_CONN_P

PCIE_EXCARD_R2D_N

PP3V3_S3_EXCARD_SWITCH

PP1V5_S0_EXCARD_SWITCH

PLT_RESET_SWITCH_L

SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA

PCIE_EXCARD_R2D_P

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R_N

PP3V3_S0_EXCARD_SWITCH

EXCARD_CPPE_L

EXCARD_CPUSB_L

EXCARD_CLKREQ_CONN_L

32

95

32

95

32

32

32

32

32

A

per Fan

8

49

49

49

49

49

5 TPs
per Fan

79

Speaker Connectors

94

94

94

94

94

94

94

94

94

94

94

94

95

32

95

32

32

95

89

95

32

89

32

17

17

32

32

32

21

13

FUNC_TEST

TRUE

I557

TRUE

I558

TRUE

I559

TRUE

I560

TRUE

I561

TRUE

I562

TRUE

I563

TRUE

I564

TRUE

I565

TRUE

6 TPs

SATA ODD Connectors

FUNC_TEST

TRUE

I595

TRUE

I594

TRUE

I596

TRUE

I597

TRUE

I593

TRUE

I598

TRUE

PM_SLP_S3_L

TRUE

I640

PPBUS_G3H

TRUE

I602
I603

I604

I605
I607

89

I606

89

I609
I608

I610
I612

I611

I613
I600

I625

21

13

I624

45

90

45

90

I623

I622

I620
I621

I618
I619

I617

I615
I616

I614

I627
I626

I639

I638
I637

I636
I709

I760

I761
I762

I765

PPBUS_CPU_IMVP_ISNS

TRUE

PP3V42_G3H

TRUE

PP5V_S3

TRUE

PP5V_S0

TRUE

PPVCORE_S0_CPU

TRUE

PPVCORE_S0_MCP_REG

TRUE

PPVCORE_S0_MCP

TRUE

PP3V3_S5

TRUE

PP3V3_S3

TRUE

PP3V3_S0

TRUE

PP2V5_S0

TRUE

PP1V2_S0

TRUE

PP1V8_S0

TRUE

PP1V8R1V5_S3

TRUE

PP1V8R1V5_S0_FET

TRUE

PPMCPDDR_ISNS

TRUE

PP1V05_S0_REG

TRUE

PP1V2R1V05_S5

TRUE

PPCPUVTT_S0

TRUE

PPCPUFSB_ISNS_R

TRUE

PP0V9R0V75_S0_DDRVTT

TRUE

PP1V2R1V05_ENET

TRUE

PP3V3_ENET_PHY

TRUE

PPVP_FW

TRUE

PP1V0_FW

TRUE

PP3V3_S0GPU

TRUE

PP1V1_S0GPU_REG

TRUE

PP1V8_S0GPU_ISNS

TRUE

PPVCORE_GPU

TRUE

PP1V8_S0GPU_ISNS_R

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PPVOUT_S0_LCDBKLT

TRUE

PPDCIN_G3H

TRUE

PPVTTDDR_S3

TRUE

PP1V8_GPUIFPX

TRUE

BI_MIC_LO
BI_MIC_SHIELD

BI_MIC_HI
SPKRCONN_L_P_OUT
SPKRCONN_L_N_OUT
SPKRCONN_R_P_OUT
SPKRCONN_R_N_OUT
SPKRCONN_S_P_OUT
SPKRCONN_S_N_OUT

GND

PP5V_SW_ODD
SMC_ODD_DETECT

SATA_ODD_R2D_P
SATA_ODD_R2D_N
SATA_ODD_D2R_C_N
SATA_ODD_D2R_C_P

GND

POWER RAILS

58

59

58

59

59

58

95

57

58

95

57

58

57

95

58

95

58

57

95

58

57

57

95

58

I757

I758

I759
I756

I753
I752

I754

I755
I751

I749

4 TPs

39

42

39

89

39

89

39

89

39

89

39

5 TPs

37

34

21

8

8

95

8

95

8

8

8

8

8

8

8

8

8

8

8

8

43

42

79

84

8

8

8

83 81 68 44 42

46

7

43

8

8

8

8

8

8

8

8

8

8

8

8

8

8

I750
I748

I746

I747
I745

I744
I743

I741

I742
I740

I739

I736

I737

I735
I734

I733

I731
I732

I730

I728
I729

I726
I727

I725

I724
I723

I721

I722
I720

I718

I719
I717

I715
I716

I713

I714
I712

I711

I710
I763

I764

IPD_FLEX_CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP3V3_S3_LDO
PP18V5_S3
TPAD_GND_F
Z2_CS_L
Z2_DEBUG3
Z2_MOSI
Z2_MISO
Z2_SCLK
Z2_BOOST_EN
Z2_HOST_INTN
Z2_BOOT_CFG1
Z2_CLKIN
Z2_KEY_ACT_L
Z2_RESET
PSOC_MISO
PSOC_MOSI
PSOC_SCLK
SMBUS_SMC_A_S3_SDA
SMBUS_SMC_A_S3_SCL
PSOC_F_CS_L
PICKB_L

KEYBOARD CONN

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

PP3V42_G3H
WS_KBD1
WS_KBD2
WS_KBD3
WS_KBD4
WS_KBD5
WS_KBD6
WS_KBD7
WS_KBD8
WS_KBD9
WS_KBD10
WS_KBD11
WS_KBD12
WS_KBD13
WS_KBD14
WS_KBD15_CAP
WS_KBD16_NUM
WS_KBD17
WS_KBD18
WS_KBD19
WS_KBD20
WS_KBD21
WS_KBD22
WS_KBD23
WS_KBD_ONOFF_L
WS_LEFT_SHIFT_KBD
WS_LEFT_OPTION_KBD
WS_CONTROL_KBD
KBDLED_ANODE
TPAD_GND_F

ICT Test Points

CPU FSB NO_TESTs

NO_TEST

TRUE
TRUE
TRUE

TRUE

TRUE

TRUE
TRUE
TRUE
TRUE
TRUE
TRUE

51

51

7

50

50

50

50

50

51

50

50

50

50

50

50

50

50

45

45

50

50

7

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

50

51

7

FSB_A_L<31..3>
FSB_ADS_L
FSB_ADSTB_L<1..0>

FSB_D_L<63..0>

FSB_DINV_L<3..0>

FSB_DSTB_L_N<3..0>
FSB_DSTB_L_P<3..0>
FSB_HIT_L
FSB_HITM_L
FSB_LOCK_L
FSB_REQ_L<4..0>

51

51

51

51

51

51

51

51

51

51

51

51

51

51

93

93

51

51

43

8

51

87

14

10

87

14

10

87

14

10

87

14

10

87

14

10

87

14

10

14

87

10

14

87

10

87

14

10

87

14

10

87

14

10

D

C

B

Functional / ICT Test

SYNC_MASTER=N/A

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7546

SHT

SYNC_DATE=N/A

OF

7 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

"G3Hot" (Always-Present) Rails

=PPBUS_G3H

61

D

=PPVIN_S5_CPU_IMVP_ISNS

46

=PP18V5_DCIN_CONN

60

=PP3V42_G3H_REG

60

C

=PP5V_S3_REG

63

5V Rails

B

=PP5V_RT_REG

65

Chipset "VCore" Rails

=PPVCORE_S0_CPU_REG

62

A

=PPMCPCORE_S0_REG

65

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVIN_S5_P5VP3V3

=PPVIN_S0_CPUVTTS0

=PPBUS_S0_LCDBKLT

=PPBUS_S5_FWPWRSW
=PPVIN_GPU_GPUVCORE

=PPVIN_S5_CPU_IMVP_ISNS_R
=PPVIN_S0_P5VRTS0_MCPCORE

=PPVIN_S3_DDRREG

=PPVIN_S0GPU_P1V8P1V1

=PPVBAT_G3H_P3V42G3H

=PPVIN_S0_P1V05S5

PPBUS_CPU_IMVP_ISNS

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVIN_S5_CPU_IMVP

PPDCIN_G3H

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPDCIN_S5_CHGR

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.42V
MAKE_BASE=TRUE

=PP3V42_G3H_SMCUSBMUX
=PP3V42_G3H_SMBUS_SMC_BSA
=PP3V42_G3H_LIDSWITCH
=PP3V3_S5_SMC
=PP3V3_S5_LPCPLUS
=PPVIN_S5_SMCVREF
=PP3V42_G3H_PWRCTL

=PP3V42_G3H_CHGR
=PP3V3_S5_RTC_D

=PP3V42_G3H_BATT
=PP3V42_G3H_TPAD
=PP3V42_G3H_BMON_ISNS

=PP3V42_G3H_CPUCOREISNS

PP5V_S3

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S3_SYSLED

=PP5V_S3_BTCAMERA

=PP5V_S3_WLAN
=PP5V_S3_IR

=PP5V_S3_DDRREG

=PP5V_S3_GPUVCORE
=PP5V_S3_RTUSB

=PP5V_S3_TPAD

=PP5V_S3_P1V05S0FET

=PP5V_S3_MCPDDRFET
=PP5V_S3_VTTCLAMP

=PP5V_S3_AUDIO_PWR

PP5V_S0

MIN_LINE_WIDTH=0.60 MM
MIN_NECK_WIDTH=0.20 MM
VOLTAGE=5V
MAKE_BASE=TRUE

=PP5V_S0_FAN_LT
=PP5V_S0_FAN_RT
=PP5V_S0_CPU_IMVP

=PP5V_S0_CPUVTTS0

=PP5V_S0_KBDLED
=PP5V_S0GPU_P1V1P1V8_GPU
=PP5V_S0_LPCPLUS
=PP5V_S0_ODD

=PP5V_S0_HDD

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PPVCORE_S0_CPU

PPVCORE_S0_MCP_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PPVCORE_S0_MCP

46

63

7

63

66

85

37

78

46

65

64

82

60

67

7

69

62

7

61

7

43

40

45

41

42

52

43

44

43

63

69

68

61

26

60

50

46

46

7

43

31

31

41

64

78

40

51

69

69

69

9

7

7

49

49

62

66

51

82

44

39

39

7

12

11

46

46

22

24

86

7

86

6

=PP3V3_S5_REG

=PP3V3_S3_FET

=PP3V3_S0_FET

=PP2V5_S0_REG

=PP1V2_S0_REG

3.3V-2.5V Rails

PP3V3_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_S5_MCP_A01

=PP3V3_S5_ROM
=PP3V3_S5_MEMRESET
=PP3V3_S3_P3V3S3FET
=PP3V3_S5_LCD
=PP3V3_S0_P3V3S0FET
=PP3V3_GPU_P3V3GPUFET
=PP3V3_S5_PWRCTL

=PP3V3_S5_P1V05FET
=PP3V3_S5_MCP
=PP3V3_S5_MCP_GPIO

=PP3V3_FW_LATEVG_ACTIVE

=PP3V3_S5_MCPPWRGD

=PP3V3_FW_LATEVG
=PP3V3_S5_P1V05ENETFET
=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_DP_PORT_PWR

PP3V3_S3

MIN_LINE_WIDTH=0.50MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_FW_REG
=PP3V3_S3_SMBUS_SMC_A_S3
=PP3V3_S3_SMS
=PP3V3_S3_REMTHMSNS

=PP3V3_S3_TPAD

=PP3V3_S3_WLAN
=PP3V3_S3_MCP_GPIO

=PP3V3_S3_VREFMRGN
=PP3V3_S3_SMBUS_SMC_MGMT
=PP3V3_S3_EXCARD

=PP3V3_S3_P1V8S0

=PP3V3_S0_LPCPLUS

=PP3V3_S0_SMC

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_GPU1V8ISNS

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_GPUTHMSNS

=PP3V3_S0_FAN_LT

=PP3V3_S0_FAN_RT

=PP3V3_S0_IMVP

=PP3V3_S0_PWRCTL

=PP3V3_S0_DDC_LCD

=PP3V3_S0_XDP

=PP3V3_S0_MCPCOREISNS

=PPSPD_S0_MEM_A

=PPSPD_S0_MEM_B

=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_GMUX

=PP3V3_S0_DPMUX

=PP3V3_S0_DPCONN

=PP3V3_S0_P1V2P2V5

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_HDCPROM

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_DAC_UF

=PP3V3_S0_MCP

=PP3V3_S0_AUDIO
=PP3V3_S0_ODD

=PP3V3_S0_VMON

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_FC_CON

=PP3V3_S0_EXCARD

=PP3V3_S0_LVDSDDCMUX

=PP3V3_S0_BATTCHARGERTMPSNSR

=PP3V3_GPU_SMBUS_SMC_0_S0

=PP3V3_S0_TPAD

PP2V5_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=2.5V
MAKE_BASE=TRUE

=PP2V5_S0_GMUX

PP1V2_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PP1V2_S0_GMUX

5

PP3V3_S0

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

67

7

95

500 mA max supply

23

44

53

44

64

30

69

79

69

69

68

69

22

24

18

20

69

37

26

38

34

34

81

16

24

7

8

69

45

52

48

50

31

21

27

45

32

67

24

8

95

7

24

44

24

8

43

45

24

47

47

48

48

49

49

241 mA max load

62

68

7

79

76

6

13

47

66

28

29

45

83

80

81

86

19

21

18

25

64

24

21

24

25

25

24

21

22

54

59

58

39

68

45

32

32

80

48

45

51

7

83

7

83

=PP1V8_S0_REG

=PPDDR_S3_REG

=PP1V8R1V5_S0_FET

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_S0_FET

1034 mA

=PP1V05_S0_MCP_PEX_DVDD

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

=PP1V05_S0_MCP_SATA_DVDD

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

=PP1V05_S5_MCP

67

=PPCPUVTT_S0_REG

5300 mA

=PPVTT_S3_DDR_BUF

27

=PPVTT_S0_DDR_LDO

64

=PP1V05_ENET_FET

34

=PP3V3_ENET_FET

34

4

1.8V/DDR 1.5V Rails

190 mA

4771 mA

130 mA
500 mA

105 mA/241 mA
139 mA/ 0 mA

4500 mA

1182 mA

ENET Rails

PP1V8_S0

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP3V3R1V8_S0_MCP_IFP_VDD

PP1V8R1V5_S3

MIN_LINE_WIDTH=0.8 mm
MIN_NECK_WIDTH=0.1 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V8R1V5_S0_MCP_FET
=PPVIN_S0_DDRREG_LDO
=PP1V5_S3_MEM_A
=PP1V5_S3_MEM_B
=PP1V5_S3_MEMRESET

PP1V8R1V5_S0_FET

MIN_LINE_WIDTH=0.6mm
MIN_NECK_WIDTH=0.2mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PPMCPDDR_ISNS_R
=PP1V5_S0_CPU
=PP1V5_S0_EXCARD

=PP1V5_S0_VMON

=PP1V5_FC_CON

PPMCPDDR_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.5V
MAKE_BASE=TRUE

=PP1V5_S0_MEM_A
=PP1V5_S0_MEM_B

=PPMCPDDR_ISNS

PP1V05_S0_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_MCP_AVDD_UF
=PP1V05_S0_MCP_PEX_DVDD
=PP1V05_S0_MCP_PLL_UF
=PP1V05_S0_MCP_SATA_DVDD
=PP1V05_S0_MCP_HDMI_VDD

=PP1V05_S0_VMON

=PP1V05_S0_MCP_PEX_DVDD0
=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD0
=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_AVDD0

PP1V2R1V05_S5

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S5_MCP_VDD_AUXC
=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_P1V05S0FET

PPCPUVTT_S0

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_S0_CPU
=PP1V05_S0_SMC_LS
=PP1V05_S0_MCP_FSB

PPVTTDDR_S3

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.75V
MAKE_BASE=TRUE

PP0V9R0V75_S0_DDRVTT

MIN_LINE_WIDTH=2 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=0.9V
MAKE_BASE=TRUE

=PP0V75_S0_MEM_VTT_A
=PP0V75_S0_MEM_VTT_B
=PPVTT_S0_VTTCLAMP

PP1V2R1V05_ENET

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.05V
MAKE_BASE=TRUE

=PP1V05_ENET_MCP_PLL_MAC
=PP1V05_ENET_MCP_RMGT

=PP1V05_ENET_PHY

PP3V3_ENET_PHY

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm

VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_ENET_MCP_RMGT
=PP3V3_ENET_PHY

(1.1V for A01)

OR 0.75V

3

7

18

25

7

69

64

28

29

30

7

47

12

11

32

68

32

7

28

29

47

7

24

8

24

24

8

24

18

25

68

17

17

17

17

20

20

7

22

34

69

7

6

43

9

7

7

28

29

69

7

24

18

24

33

7

18

24

33

37

8

67

69

82

24

67

62 13

12

10

11

24

22

14

47

46

78

82

=PPBUS_S5_FW_FET

=PP3V3_FW_REG

=PP1V0_FW_REG

=PP3V3_S0GPU_FET

=PP1V1_S0GPU_REG

=PP1V8_GPUIFPX_REG

=PP1V8_S0GPU_ISNS

=PPVCORE_GPU_REG

=PP1V8_GPU_REG

2 1

"FW" (FireWire) Rails

PPVP_FW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=12.6V
MAKE_BASE=TRUE

=PPVP_FW_PORT1
=PPVP_FW_PHY_CPS_FET

=PP3V3_FW_FWPHY

=PP3V3_FW_P1V0FW

PP1V0_FW

MIN_LINE_WIDTH=0.4 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.00V
MAKE_BASE=TRUE

=PP1V0_FW_FWPHY

"GPU" Rails

SYNC_MASTER=(MASTER)

APPLE INC.

PP3V3_S0GPU

MIN_LINE_WIDTH=0.30MM
MIN_NECK_WIDTH=0.20MM
VOLTAGE=3.3V
MAKE_BASE=TRUE

=PP3V3_GPU_VDD33
=PP3V3_GPU_MIO

=PP3V3_GPU_LVDS_DDC

=PP3V3_GPU_PWRCTL
=PP3V3_GPU_VCORELOGIC

=PP3V3_GPU_P1V8S0

PP1V1_S0GPU_REG

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.1V
MAKE_BASE=TRUE

=PP1V1_GPU_PEX_IOVDDQ
=PP1V1_GPU_PEX_IOVDD
=PP1V1_GPU_PEX_PLLXVDD
=PP1V1_GPU_PLLVDD
=PP1V1_GPU_H_PLLVDD
=PP1V1_GPU_VID_PLLVDD
=PP1V1_GPU_FBPLLAVDD
=PP1V1_GPU_IFPCD_IOVDD

PP1V8_GPUIFPX

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.15 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_IFPX

PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.8V
MAKE_BASE=TRUE

=PP1V8_GPU_FB_VDD
=PP1V8_GPU_FB_VDDQ
=PP1V8_GPU_FBVDDQ
=PP1V8_GPU_FBIO

PPVCORE_GPU

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.2V
MAKE_BASE=TRUE

=PPVCORE_GPU

PP1V8_S0GPU_ISNS_R

MIN_LINE_WIDTH=0.6 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=1.25V
MAKE_BASE=TRUE

=PP1V8_S0GPU_ISNS_R

Power Aliases

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

7

38

38

SYNC_DATE=(MASTER)

051-7546

SHT

OF

D

38

36

67

7

36

7

6

76

75

75

76

80

68

78

67

7

70

70

70

75

75

75

72

77

7

77

7

73

74

9

74

73

71

72

7

71

7

47

C

B

A

REV.

A.0.0

968

8

7 6

5

4

3

2

1

D

C

B

ZT0915

3R2P5

1

ZT0940

3R2P5

1

ZT0945

3R2P5

1

ZT0950

TH

SL-3.1X2.7-6CIR-NSP

ZT0965

3R2P5

ZT0960

3R2P5

1

ZT0990

3R2P5

1

8 7

Thermal Module Holes

STDOFF-4.5OD.98H-1.1-3.48-TH

Frame Holes

GND_CHASSIS_LVDS

GND_CHASSIS_USB

GND_CHASSIS_FAN

1

GND_CHASSIS_CLUTCH

GND_CHASSIS_SATA

GND_CHASSIS_BATTCONN

ZT0982

STDOFF-4.5OD.98H-1.1-3.48-TH

Left CPU

TM Hole

61

60

ZT0983

Right CPU

TM Hole TM Hole

GND_BATT_CHGND

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0984

Top GPU Right

TM Hole

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0980

Bottom Left GPU

STDOFF-4.5OD.98H-1.1-3.48-TH

=PP1V8_GPU_FB_VDDQ

ZT0987

R0900

10

1%
1/16W
MF-LF

402

R0901

10

1%
1/16W
MF-LF

402

Extra FSB Pull-ups

Exist in MRB but not Intel designs. Here for CYA.

If found to be necessary, will move to page14.csa

=PP1V05_S0_MCP_FSB

24 22

8

14

CPU_DPRSTP_L

10 14 62 87

OUT

FSB_BREQ0_L

10 14 87

OUT

FSB_CPURST_L

10 13 14 87

OUT

CPU_INTR

10 14 87

OUT

CPU_NMI

10 14 87

OUT

6

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

GPU_FB_A_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_A

GPU_FB_B_VREF_DIV

MAKE_BASE=TRUE

=PP1V8_GPU_FB_VREF_B

NO STUFF

R0950

220

1/16W
MF-LF

402

1

5%

2

ZT0981

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0986

STDOFF-4.5OD.98H-1.1-3.48-TH

NO STUFF

NO STUFF

1

R0960

62

5%
1/16W
MF-LF
402

2

R0970

200

1/16W
MF-LF

402

1

5%

2

ZT0985

2.0DIA-TALL-EMI-MLB-M97-M98

2.0DIA-TALL-EMI-MLB-M97-M98

ZT0930

1.4DIA-SHORT-EMI-MLB-M97-M98

73

1.4DIA-SHORT-EMI-MLB-M97-M98

74

NO STUFF

NO STUFF

1

R0980

150

1%
1/16W
MF-LF
402

2

R0990

150

1/16W
MF-LF

402

1

1%

2

5

SH0902

SM

2.0DIA-TALL-EMI-MLB-M97-M98

1

SH0903

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

SH0910

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

1

SH0912

SM

1

Bosses for VRAM HS

ZT0951

4.0OD1.65H-M1.6X0.35

1

ZT0952

4.0OD1.65H-M1.6X0.35

1

ZT0953

4.0OD1.65H-M1.6X0.35

1

SH0900

1

SH0901

SM

1

SH0911

SM

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0913

1

SM

4

3

2 1

CPU signals

MAKE_BASE=TRUE

95

95

95

95

95

95

CPU_VID<0..6>

87 87

11

MAKE_BASE=TRUE

CPU_BSEL<0..2>

87

10

MAKE_BASE=TRUE

MAKE_BASE=TRUE

TP_SPI_CS1_R_L_USE_MLB

MAKE_BASE=TRUE

PEG_D2R_P<0..15>

70

89

MAKE_BASE=TRUE

PEG_D2R_N<0..15>

89

MAKE_BASE=TRUE

PEG_R2D_C_P<0..15>

89

70

MAKE_BASE=TRUE

PEG_R2D_C_N<0..15>

70

89

MAKE_BASE=TRUE

PCIE_CLK100M_FC_P

32

MAKE_BASE=TRUE

PCIE_CLK100M_FC_N

32

MAKE_BASE=TRUE

PCIE_FC_R2D_C_P

32

MAKE_BASE=TRUE

PCIE_FC_R2D_C_N

32

MAKE_BASE=TRUE

FC_CLKREQ_L

32 29

MAKE_BASE=TRUE

FC_PRSNT_L

32

MAKE_BASE=TRUE

PCIE_FC_D2R_P

32

MAKE_BASE=TRUE

PCIE_FC_D2R_N

32

MAKE_BASE=TRUE

GPU signals

VR_PWRGD_CLKEN_LTP_IMVP6_CLKEN_L

IMVP6_VID<0..6>

=MCP_BSEL<0..2>

=DDRVTT_ENMEM_VTT_EN

=SPI_CS1_R_L_USE_MLB

=PEG_D2R_P<0..15>
=PEG_D2R_N<0..15>
=PEG_R2D_C_P<0..15>
=PEG_R2D_C_N<0..15>

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N
TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN
TP_PE4_CLKREQ_L
TP_PE4_PRSNT_L

TP_PCIE_PE4_D2RP
TP_PCIE_PE4_D2RN

62

14

64 26

17

17 70

62

69

44

21

17

17

17

17

17

17

17

17

17

17

GMUX ALIASES

LCD_BKLT_EN

83 85

MAKE_BASE=TRUE

DP_IG_ML_P<3>

80

89

MAKE_BASE=TRUE

DP_IG_ML_N<3>

89

80 18

MAKE_BASE=TRUE

DP_IG_ML_P<2..0>

89

80 18

MAKE_BASE=TRUE

DP_IG_ML_N<2..0>

80

89

MAKE_BASE=TRUE

DP_IG_DDC_CLK

76

80

MAKE_BASE=TRUE

DP_IG_DDC_DATA

80

76

MAKE_BASE=TRUE

DP_IG_HPD

MAKE_BASE=TRUE

PM_ALL_GPU_PGOOD

68

MAKE_BASE=TRUE

TP_LVDS_MUX_SEL_EG

MAKE_BASE=TRUE

EG_RESET_L

83

MAKE_BASE=TRUE

JTAG_GMUX_TDI

6

83

MAKE_BASE=TRUE

JTAG_GMUX_TMS

6

83

MAKE_BASE=TRUE

JTAG_GMUX_TDO

83

6

MAKE_BASE=TRUE

LVDS_IG_BKL_ON

18

MAKE_BASE=TRUE

LVDS_IG_PANEL_PWR

18

MAKE_BASE=TRUE

LVDS_BKL_ON

=MCP_HDMI_TXC_P

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0..2>

=MCP_HDMI_TXD_N<0..2>

=MCP_HDMI_DDC_CLK

=MCP_HDMI_DDC_DATA

=MCP_HDMI_HPD

ALL_EG_PGOOD

LVDS_MUX_SEL_EG

GPU_RESET_L

GMUX_JTAG_TDI
GMUX_JTAG_TMS

GMUX_JTAG_TDO

IG_BKLT_EN
IG_LCD_PWR_EN

18

18

18

18

18

83

83

70

19

19

17

83

83

TP_USB_EXTDP

MAKE_BASE=TRUE

TP_USB_EXTDN

MAKE_BASE=TRUE

TP_USB_MINIP

MAKE_BASE=TRUE

TP_USB_MININ

MAKE_BASE=TRUE

GMUX_INT

83

MAKE_BASE=TRUE

MCP_SPKR

21

TP_MEM_A_A<15>

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MAKE_BASE=TRUE

TP_USB_EXTCP

MAKE_BASE=TRUE

TP_USB_EXTCN

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

TP_MCP_GPIO_17

MAKE_BASE=TRUE

PCIE_RESET_L

26

17

MAKE_BASE=TRUE

HDA_BITCLK

54

MAKE_BASE=TRUE

=PP5V_S3_AUDIO_PWR

8

ETHERNET ALIASES

=P3V3ENET_EN

34

=P1V05ENET_EN

34

=PP3V3_ENET_PHY_VDDREG

33

=RTL8211_REGOUT

33

AUDIO ALIASES

USB_EXTD_P
USB_EXTD_N

=DVI_HPD_GMUX_INT

R0903

0

5%
1/16W
MF-LF

402

MEM_A_A<15>
MEM_B_A<15>

USB_EXTC_P
USB_EXTC_N

CPU_PECI_MCP
AUD_IP_PERIPHERAL_DET

FC_RESET_L

HDA_BIT_CLK

XW0900

SM

12

SM

12

XW0901

R0902

10K

1 2

5%
1/16W
MF-LF

402

TP_PP3V3_ENET_PHY_VDDREG

=RTL8211_ENSWREG

USB_MINI_P
USB_MINI_N

SMC_MCP_SAFE_MODE

PP5V_S3_AUDIO

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

PP5V_S3_AUDIO_AMP

MIN_LINE_WIDTH=0.5 mm
MIN_NECK_WIDTH=0.25 mm
VOLTAGE=5V

AUD_IPHS_SWITCH_EN

MAKE_BASE=TRUE

PM_SLP_RMGT_L

MAKE_BASE=TRUE

MAKE_BASE=TRUE

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

20

90

20

90

20

90

90

20

D

18

42

28

90

20

20

90

14

17

32

21

90

54

56

57

19

C

59

21

33

B

ZT0931

STDOFF-4.0OD3.0H-TH

ZT0934

STDOFF-4.0OD3.0H-TH

STDOFF-4.0OD3.0H-TH

1

ZT0935

1

STDOFF-4.5OD.98H-1.1-3.48-TH

STDOFF-4.5OD.98H-1.1-3.48-TH

A

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0991

1

8

1

VENICE

ZT0932

STDOFF-4.0OD3.0H-TH

1

VENICE

ZT0933

STDOFF-4.0OD3.0H-TH

1

VENICE

ZT0988

1

ZT0989

1

7 6

NC_LVDS_B_DATAP<3>

9

MAKE_BASE=TRUE

NC_LVDS_B_DATAN<3>

9

MAKE_BASE=TRUE

NC_LVDS_A_DATAP<3>

9

MAKE_BASE=TRUE

NC_LVDS_A_DATAN<3>

9

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_A_DATAP<3>

9

MAKE_BASE=TRUE

NC_LVDS_A_DATAN<3>

9

MAKE_BASE=TRUE

NC_LVDS_B_DATAP<3>

9

MAKE_BASE=TRUE

NC_LVDS_B_DATAN<3>

9

MAKE_BASE=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

NO_TEST=TRUE

TP_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

TP_LVDS_IG_B_CLKN

MAKE_BASE=TRUE

TP_LVDS_IG_BKL_PWM

MAKE_BASE=TRUE

LVDS_B_DATA_P<3>

LVDS_B_DATA_N<3>

LVDS_A_DATA_P<3>

LVDS_A_DATA_N<3>

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N

LVDS_IG_BKL_PWM

LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>

LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

LVDS_A_DATA_P<3>
LVDS_A_DATA_N<3>

LVDS_B_DATA_P<3>
LVDS_B_DATA_N<3>

9

9

9

9

18

89

89

18

18

89

18

89

18

89

18

18

89

9

9

9

9

5

MCP79 PCIe PRSNT# Straps

R0925

0

5%
1/16W
MF-LF

402

R0927

1/16W
MF-LF

402

MCP_MII_PD

MAKE_BASE=TRUE

1

R0930

47K

5%
1/16W
MF-LF
402

2

4

These need work. Add other PRSNT# straps if needed. .

PCIE_FW_PRSNT_L

MAKE_BASE=TRUE

17

OUT

NO STUFF

0

5%

PEG_PRSNT_L

MAKE_BASE=TRUE

R0926

5%
1/16W
MF-LF

402

0

OUT

EG_CLKREQ_OUT_L

=MCP_MII_RXER
=MCP_MII_CRS
=MCP_MII_COL

17

83

IN

18

18

18

3

=PP1V05_S0_MCP_SATA_DVDD1
=PP1V05_S0_MCP_SATA_AVDD1

Digital Ground

Signal Aliases

SYNC_MASTER=(MASTER)

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

2

GND

MIN_LINE_WIDTH=0.6MM
MIN_NECK_WIDTH=0.09MM
VOLTAGE=0V

DRAWING NUMBER

SIZE

D

SCALE

NONE

20

20

SYNC_DATE=(MASTER)

051-7546

SHT

OF

9 96

1

A

REV.

A.0.0

8 7

FSB_A_L<3>

7

14 87

BI

FSB_A_L<4>

7

14 87

BI

FSB_A_L<5>

7

14 87

BI

FSB_A_L<6>

7

14 87

BI

FSB_A_L<7>

7

14 87

BI

FSB_A_L<8>

7

14 87

BI

FSB_A_L<9>

7

14 87

BI

FSB_A_L<10>

7

14 87

BI

FSB_A_L<11>

7

14 87

BI

FSB_A_L<12>

7

14 87

D

C

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

14 87

BI

14 87

BI

14 87

BI

14 87

BI

7

14 87

BI

14 87

IN

14 87

OUT

14 87

IN

14 87

IN

9

14 87

IN

9

14 87

IN

14 87

IN

FSB_A_L<13>
FSB_A_L<14>
FSB_A_L<15>
FSB_A_L<16>
FSB_ADSTB_L<0>

FSB_REQ_L<0>
FSB_REQ_L<1>
FSB_REQ_L<2>
FSB_REQ_L<3>
FSB_REQ_L<4>

FSB_A_L<17>
FSB_A_L<18>
FSB_A_L<19>
FSB_A_L<20>
FSB_A_L<21>
FSB_A_L<22>
FSB_A_L<23>
FSB_A_L<24>
FSB_A_L<25>
FSB_A_L<26>
FSB_A_L<27>
FSB_A_L<28>
FSB_A_L<29>
FSB_A_L<30>
FSB_A_L<31>
FSB_A_L<32>
FSB_A_L<33>
FSB_A_L<34>
FSB_A_L<35>
FSB_ADSTB_L<1>

CPU_A20M_L
CPU_FERR_L
CPU_IGNNE_L

CPU_STPCLK_L
CPU_INTR
CPU_NMI
CPU_SMI_L

TP_CPU_RSVD0
TP_CPU_RSVD1
TP_CPU_RSVD2
TP_CPU_RSVD3
TP_CPU_RSVD4
TP_CPU_RSVD5
TP_CPU_RSVD6
TP_CPU_RSVD7
TP_CPU_RSVD8

B

XDP_TMS

87

13

10

6

XDP_TDI

87

13

10

6

XDP_TDO

87

10

87

87

13

10

13

10

6

XDP_TCK

6

XDP_TRST_L

6

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

A

AA4
AB2
AA3

D22

J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1

K3
H2
K2
J3
L1

Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3

V1

A6
A5
C4

D5
C6
B4
A3

M4
N5
T2
V3
B2
F6
D2

D3

A3*
A4*
A5*
A6*
A7*
A8*
A9*
A10*
A11*
A12*
A13*
A14*
A15*
A16*
ADSTB0*

REQ0*
REQ1*
REQ2*
REQ3*
REQ4*

A17*
A18*
A19*
A20*
A21*
A22*
A23*
A24*
A25*
A26*
A27*
A28*
A29*
A30*
A31*
A32*
A33*
A34*
A35*
ADSTB1*

A20M*
FERR*
IGNNE*

STPCLK*
LINT0
LINT1
SMI*

RSVD0
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8

R1021

R1023

U1000

PENRYN

1 OF 4

ADDR GROUP0

ADDR GROUP1

54.9

1%
1/16W
MF-LF

402

649

1%
1/16W
MF-LF

402

OMIT

FCBGA

ICH

RESERVED

ADS*
BNR*

BPRI*

DEFER*

DRDY*
DBSY*

BR0*

IERR*
INIT*

CONTROL

LOCK*

RESET*

RS0*
RS1*
RS2*

TRDY*

HIT*

HITM*

BPM0*
BPM1*
BPM2*
BPM3*
PRDY*
PREQ*

TCK
TDI
TDO

XDP/ITP SIGNALS

TMS

TRST*

DBR*

THERMAL

PROCHOT*

THERMDA
THERMDC

THERMTRIP*

H CLK

BCLK0
BCLK1

R1020

54.9

1%
1/16W
MF-LF

402

R1024

54.9

1%
1/16W
MF-LF

402

R1022

54.9

1%
1/16W
MF-LF

402

H1

FSB_ADS_L

E2

FSB_BNR_L

G5

FSB_BPRI_L

H5

FSB_DEFER_L

F21

FSB_DRDY_L

E1

FSB_DBSY_L

F1

FSB_BREQ0_L

D20

CPU_IERR_L

87

B3

CPU_INIT_L

H4

FSB_LOCK_L

C1

FSB_CPURST_L

F3

FSB_RS_L<0>

F4

FSB_RS_L<1>

G3

FSB_RS_L<2>

G2

FSB_TRDY_L

G6

FSB_HIT_L

E4

FSB_HITM_L

AD4

XDP_BPM_L<0>

AD3

XDP_BPM_L<1>

AD1

XDP_BPM_L<2>

AC4

XDP_BPM_L<3>

AC2

XDP_BPM_L<4>

AC1

XDP_BPM_L<5>

AC5

XDP_TCK

AA6

XDP_TDI

AB3

XDP_TDO

AB5

XDP_TMS

AB6

XDP_TRST_L

C20

XDP_DBRESET_L

D21

CPU_PROCHOT_L

A24

CPU_THERMD_P

B25

CPU_THERMD_N

C7

PM_THRMTRIP_L

A22

FSB_CLK_CPU_P

A21

FSB_CLK_CPU_N

=PP1V05_S0_CPU

2 1

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

7

BI

9

14 62 87

IN

14 87

IN

14 87

IN

13 14 87

IN

14 87

IN

62

OUT

LAYOUT NOTE:

14 87

COMP0,2 CONNECT WITH ZO=27.4OHM,

14 87

MAKE TRACE LENGTH SHORTER THAN 0.5".

14 87

COMP1,3 CONNECT WITH ZO=55OHM,

14 87

MAKE TRACE LENGTH SHORTER THAN 0.5".

14 87

14 87

14 87

14 87

14 87

14 87

14 87

14 87

R1017

54.9

1%
1/16W
MF-LF

402

R1019

54.9

1%
1/16W
MF-LF

402

R1016

27.4

1%
1/16W
MF-LF

402

R1018

27.4

1%
1/16W
MF-LF

402

D

C

B

OMIT

U1000

PENRYN

FCBGA

2 OF 4

DATA GRP 0DATA GRP 1

MISC

3

DSTBN2*
DSTBP2*

DINV2*

DATA GRP 3 DATA GRP 2

DSTBN3*
DSTBP3*

DINV3*

COMP0
COMP1
COMP2
COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

D32*
D33*
D34*
D35*
D36*
D37*
D38*
D39*
D40*
D41*
D42*
D43*
D44*
D45*
D46*
D47*

D48*
D49*
D50*
D51*
D52*
D53*
D54*
D55*
D56*
D57*
D58*
D59*
D60*
D61*
D62*
D63*

SLP*
PSI*

Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22

AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20

R26
U26
AA1
Y1

E5
B5
D24
D6
D7
AE6

FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_DSTB_L_N<2>
FSB_DSTB_L_P<2>
FSB_DINV_L<2>

FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>
FSB_DSTB_L_N<3>
FSB_DSTB_L_P<3>
FSB_DINV_L<3>

CPU_COMP<0>

87 27

CPU_COMP<1>

87

CPU_COMP<2>

87

CPU_COMP<3>

87

CPU_DPRSTP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_PWRGD
FSB_CPUSLP_L
CPU_PSI_L

6

7

14 87

BI

14 87

BI

14 87

BI

14 87

BI

14 87

BI

14 87

BI

9

14 87

BI

14 87

IN

7

14 87

BI

9

13 14 87

IN

14 87

IN

14 87

IN

14 87

IN

14 87

IN

7

14 87

BI

7

14 87

BI

13 87

BI

13 87

BI

13 87

BI

13 87

BI

13 87

BI

6

10 13 87

IN

6

10 13 87

IN

6

10 87

OUT

6

10 13 87

IN

6

10 13 87

IN

13 26

OUT

48 95

OUT

48 95

OUT

14 43 87

OUT

14 87

IN

14 87

IN

62

13

12

62

13

12

11

10

8

6

PLACE C1000 CLOSE TO CPU_TEST4
PIN. MAKE SURE CPU_TEST4 IS
REFERENCED TO GND

=PP1V05_S0_CPU

1

R1002

54.9

1%
1/16W
MF-LF
402

2

R1003

54.9

1/16W
MF-LF

PM_THRMTRIP#
SHOULD CONNECT TO ICH AND
GMCH WITHOUT T (NO STUB)

=PP1V05_S0_CPU

11

10

8

6

5

PLACE TESTPOINT ON
FSB_IERR_L WITH A GND

0.1" AWAY

=PP1V05_S0_CPU

1

1%

402

2

BI

1

R1004

68

5%
1/16W
MF-LF
402

2

OUT

R1005

1K

1/16W
MF-LF

402

R1006

2.0K

1/16W
MF-LF

402

13 87

14 43 62 87

1

1%

2

1

1%

2

62

13

12

11

10

8

6

62

13

12

11

10

8

6

0.5" MAX LENGTH FOR CPU_GTLREF

NOSTUFF

1

C1000

0.1uF

10%
16V

2

X5R
402

9

87

9

87

9

87

CPU_GTLREF

87

CPU_TEST1

CPU_TEST2
TP_CPU_TEST3
CPU_TEST4
TP_CPU_TEST5
TP_CPU_TEST6
TP_CPU_TEST7

CPU_BSEL<0>

OUT

CPU_BSEL<1>

OUT

CPU_BSEL<2>

OUT

4

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

7

14 87

BI

NOSTUFF

R1012

1/16W
MF-LF

402

1K

5%

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_DSTB_L_N<0>
FSB_DSTB_L_P<0>
FSB_DINV_L<0>

FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_DSTB_L_N<1>
FSB_DSTB_L_P<1>
FSB_DINV_L<1>

NOSTUFF

R1030

0

5%

1/16W

1

MF-LF

402

2

E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25

N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24

AD26

C23
D25
C24

AF26

AF1
A26

C3
B22
B23
C21

NOSTUFF

1

R1007

1K

5%
1/16W
MF-LF
402

2

D0*
D1*
D2*
D3*
D4*
D5*
D6*
D7*
D8*
D9*
D10*
D11*
D12*
D13*
D14*
D15*
DSTBN0*
DSTBP0*
DINV0*

D16*
D17*
D18*
D19*
D20*
D21*
D22*
D23*
D24*
D25*
D26*
D27*
D28*
D29*
D30*
D31*
DSTBN1*
DSTBP1*
DINV1*

GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
TEST7
BSEL0
BSEL1
BSEL2

CPU FSB

SYNC_MASTER=M87_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

DRAWING NUMBER

D

NONE

SYNC_DATE=10/17/2007

051-7546

SHT

OF

10

96

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

D

C

B

A10
A12
A13
A15
A17
A18
A20

B10
B12
B14
B15
B17
B18
B20

C10
C12
C13
C15
C17
C18

D10
D12
D14
D15
D17
D18

E10
E12
E13
E15
E17
E18
E20

F10
F12
F14
F15
F17
F18
F20
AA7

AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20

AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18

A7
A9

B7
B9

C9

D9

VCC

E7
E9

F7
F9

OMIT

U1000

PENRYN

FCBGA

3 OF 4

VCC

VCCP

VCCA

VID0
VID1
VID2
VID3
VID4
VID5
VID6

VCCSENSE

VSSSENSE

AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20

G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21

B26
C26

AD6
AF5
AE5
AF4
AE3
AF3
AE2

AF7

AE7

A

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

8

(CPU CORE POWER)
=PPVCORE_S0_CPU

46

12

11

8

Standard Voltage:

44.0 A (Design Target)

41.0 A (HFM)

30.4 A (LFM)

25.5 A (SuperLFM)

27.4 A (Auto-Halt/Stop-Grant HFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

27.4 A (Sleep HFM)

16.8 A (Sleep SuperLFM)

25.0 A (Deep Sleep HFM)

16.0 A (Deep Sleep SuperLFM)

11.5 A (Deeper Sleep)

9.4 A (Enhanced Deeper Sleep)

(CPU IO POWER 1.05V)

=PP1V05_S0_CPU

4500 mA (before VCC stable)
2500 mA (after VCC stable)

62 13

12

10

8

6

(CPU INTERNAL PLL POWER 1.5V)
=PP1V5_S0_CPU

12

8

130 mA

CPU_VID<0>
CPU_VID<1>
CPU_VID<2>
CPU_VID<3>
CPU_VID<4>
CPU_VID<5>
CPU_VID<6>

9

87

OUT

9

87

OUT

9

87

OUT

9

87

OUT

9

87

OUT

9

87

OUT

9

87

OUT

CPU_VCCSENSE_P

CPU_VCCSENSE_N

7 6

Low Voltage:

23.0 A (Design Target)

21.0 A (HFM)

18.7 A (LFM)
TBD A (SuperLFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Sleep HFM)
TBD A (Sleep SuperLFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep SuperLFM)

TBD A (Deeper Sleep)
TBD A (Enhanced Deeper Sleep)

=PPVCORE_S0_CPU

1

R1100

100

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

62 87

OUT

62 87

OUT

1

R1101

100

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

46

12

11

8

5

Ultra Low Voltage:

17.0 A (Design Target)
TBD A (HFM)

TBD A (LFM)

TBD A (Auto-Halt/Stop-Grant HFM)
TBD A (Auto-Halt/Stop-Grant LFM)

TBD A (Sleep HFM)
TBD A (Sleep LFM)

TBD A (Deep Sleep HFM)
TBD A (Deep Sleep LFM)

TBD A (Deeper Sleep)
TBD A (Enhanced Deeper Sleep)

4

A4

A8
A11
A14
A16
A19
A23
AF2

B6

B8
B11
B13
B16
B19
B21
B24

C5

C8
C11
C14
C16
C19

C2
C22
C25

D1

D4

D8
D11
D13
D16
D19
D23
D26

E3

E6

E8
E11
E14

VSS VSS
E16
E19
E21
E24

F5

F8
F11
F13
F16
F19

F2
F22
F25

G4

G1
G23
G26

H3

H6
H21
H24

J2

J5
J22
J25

K1

K4
K23
K26

L3

L6
L21
L24

M2

M5
M22
M25

N1

N4
N23
N26

P3

B1

OMIT

U1000

PENRYN

FCBGA

4 OF 4

3

P6
P21
P24
R2
R5
R22
R25
T1
T4

T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25

CPU Power & Ground

SYNC_MASTER=M87_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

2

SYNC_DATE=10/17/2007

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

11 96

1

D

C

B

A

REV.

A.0.0

OF

8 7

6

5

4

3

2 1

D

D

CPU VCORE HF AND BULK DECOUPLING

=PPVCORE_S0_CPU

46

11

8

CRITICAL

C1250

330UF

POLY-TANT

PLACEMENT_NOTE=Place in CPU center cavity.

C

PLACEMENT_NOTE=Place in CPU center cavity.

PLACEMENT_NOTE=Place in CPU center cavity.

PLACEMENT_NOTE=Place in CPU center cavity.

D2T-SM2

CRITICAL

C1252

330UF

POLY-TANT

D2T-SM2

4x 330uF, 20x 22uF 0805

CRITICAL

2.0V

2.0V

20%

20%

1

2 3

CRITICAL

1

2 3

C1251

330UF

2.0V

POLY-TANT

D2T-SM2

C1253

330UF

2.0V

POLY-TANT

D2T-SM2

1

20%

2 3

1

20%

2 3

CRITICAL

1

C1200

22UF

20%

6.3V

2

X5R-CERM
603

CRITICAL

C1210

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL
22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1203C1202C1201

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1213C1212C1211

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1205 C1209

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1215 C1217

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1206C1204

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1216C1214

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1208C1207

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

22UF

20%

6.3V
X5R-CERM
603

CRITICAL

C1219C1218

22UF

20%

6.3V
X5R-CERM
603

C

VCCP (CPU I/O) DECOUPLING

62 13 11

=PP1V05_S0_CPU

10

8

6

CRITICAL

C1235

470UF

1x 470uF, 6x 0.1uF 0402

1

C1236

0.1UF

20%
10V

2

CERM
402

2.5V
POLY

1

20%

2 3

D2T

WF: Consider sharing bulk cap with NB Vtt?

1

C1237

0.1UF

20%

10V

2

CERM
402

1

C1238

0.1UF

20%
10V

2

CERM
402

1

C1239

0.1UF

20%

10V

2

CERM
402

1

C1240

0.1UF

20%
10V

2

CERM
402

1

C1241

0.1UF

20%
10V

2

CERM
402

VCCA (CPU AVdd) DECOUPLING

B

=PP1V5_S0_CPU

11

8

1x 10uF, 1x 0.01uF

1

1

C1280

10uF

20%

6.3V
X5R
603

C1281

0.01UF

10%
16V

2

2

CERM
402

PLACEMENT_NOTE=Place near CPU pin B26.

CPU Decoupling & VID

A

SYNC_MASTER=M87_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=10/17/2007

051-7546

SHT

OF

9612

1

REV.

B

A

A.0.0

8 7

6

5

4

3

2 1

Mini-XDP Connector

NOTE: This is not the standard XDP pinout.

D

Use with 920-0620 adapter board to support CPU, MCP debugging.

D

MCP79-specific pinout

=PP3V3_S0_XDP

8

6

62 12 11 10

10 87

10 87

10 87

10 87

10 87

10 87

C

XDP

R1399

1K

10 14 87

IN

CPU_PWRGD

1 2

5%
1/16W
MF-LF

402

19 23

6

21

7

21 45 90

7

21 45 90

6

10 87

B

=PP1V05_S0_CPU

8

6

XDP_BPM_L<5>

BI

XDP_BPM_L<4>

BI

XDP_BPM_L<3>

BI

XDP_BPM_L<2>

IN

XDP_BPM_L<1>

IN

XDP_BPM_L<0>

IN

TP_XDP_OBSFN_B0
TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B0
TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B2
TP_XDP_OBSDATA_B3

XDP_PWRGD

PM_LATRIGGER_L

IN

JTAG_MCP_TCK

OUT

SMBUS_MCP_0_DATA

BI

SMBUS_MCP_0_CLK

BI

XDP_TCK

OUT

XDP

R1315

54.9

1/16W
MF-LF

1%

402

1

2

XDP_OBS20

OBSFN_A0
OBSFN_A1

OBSDATA_A0
OBSDATA_A1

OBSDATA_A2
OBSDATA_A3

OBSFN_B0
OBSFN_B1

OBSDATA_B0

OBSDATA_B2
OBSDATA_B3

PWRGD/HOOK0

HOOK1

VCC_OBS_AB

HOOK2
HOOK3

TCK1
TCK0

C1300

0.1uF

CRITICAL
XDP_CONN

J1300

LTH-030-01-G-D-NOPEGS

SDA
SCL

XDP

1

10%
16V

2

X5R X5R
402

F-ST-SM

1

2

3

4

5

6

10

20

30

40

50

NC

60

78

9
1112
1314
1516
1718
19
2122
2324
2526
2728
29
3132
3334
3536
3738
39
4142
4344
4546
4748
49
5152
5354
5556
5758
59

998-1571

OBSFN_C0
OBSFN_C1

OBSDATA_C0
OBSDATA_C1

OBSDATA_C2
OBSDATA_C3

OBSFN_D0
OBSFN_D1

OBSDATA_D0
OBSDATA_D1OBSDATA_B1

OBSDATA_D2
OBSDATA_D3

ITPCLK/HOOK4
ITPCLK#/HOOK5
VCC_OBS_CD
RESET#/HOOK6
DBR#/HOOK7
NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.
TDO
TRSTn
TDI
TMS
XDP_PRESENT#
XDP

1

C1301

0.1uF

10%
16V

2

402

JTAG_MCP_TDO_CONN
JTAG_MCP_TRST_L

MCP_DEBUG<0>
MCP_DEBUG<1>

MCP_DEBUG<2>
MCP_DEBUG<3>

JTAG_MCP_TDI
JTAG_MCP_TMS

MCP_DEBUG<4>
MCP_DEBUG<5>

MCP_DEBUG<6>
MCP_DEBUG<7>

FSB_CLK_ITP_P
FSB_CLK_ITP_N

XDP_CPURST_L

87

XDP_DBRESET_L

XDP_TDO_CONN
XDP_TRST_L
XDP_TDI
XDP_TMS

OUT

OUT
OUT

OUT

OUT
OUT
OUT

6

IN

6

21

19 90

BI

19 90

BI

19 90

BI

19 90

BI

6

21 23

6

21 23

19 90

BI

19 90

BI

19 90

BI

19 90

BI

14 87

IN

14 87

IN

10 26

6

IN

6

10 87

6

10 87

6

10 87

XDP

R1303

1K

1 2

FSB_CPURST_L

5%

PLACEMENT_NOTE=Place close to CPU to minimize stub.

1/16W
MF-LF

402

9

10 14 87

IN

C

B

Direction of XDP module

Please avoid any obstructions
on even-numbered side of J1300

eXtended Debug Port(MiniXDP)

A

SYNC_MASTER=M99_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=01/08/2008

051-7546

SHT

OF

13

96

1

A

REV.

A.0.0

8 7

6

D

C

=PP1V05_S0_MCP_FSB

24

22

14 9 9

8

R1415

1/16W
MF-LF

R1421

1/16W
MF-LF

1

1

R1416

62

62

5%

5%
1/16W
MF-LF

402

402

2

2

NO STUFF

1

1

R1422

1K

1K

5%

5%

1/16W
MF-LF
402

402

2

2

1

R1430

49.9

1/16W
MF-LF

1

R1435

49.9

1%

1%
1/16W
MF-LF

402

402

2

2

1

R1410

54.9

1%
1/16W
MF-LF

402

2

B

10 43 87

IN

10 87

IN

9

IN

9

IN

9

IN

PM_THRMTRIP_L
CPU_FERR_L

NO STUFF

R1420

=MCP_BSEL<2>
=MCP_BSEL<1>
=MCP_BSEL<0>

1/16W
MF-LF

1K

5%

402

NO STUFF

1

2

A

1

1

R1431

49.9

1/16W
MF-LF

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

R1436

49.9

1%

1%

1/16W
MF-LF
402

402

2

2

FSB_DSTB_L_P<0>

7

10 87

BI

FSB_DSTB_L_N<0>

7

10 87

BI

FSB_DINV_L<0>

7

10 87

BI

FSB_DSTB_L_P<1>

7

10 87

BI

FSB_DSTB_L_N<1>

7

10 87

BI

FSB_DINV_L<1>

7

10 87

BI

FSB_DSTB_L_P<2>

7

10 87

BI

FSB_DSTB_L_N<2>

7

10 87

BI

FSB_DINV_L<2>

7

10 87

BI

FSB_DSTB_L_P<3>

7

10 87

BI

FSB_DSTB_L_N<3>

7

10 87

BI

FSB_DINV_L<3>

7

10 87

BI

FSB_A_L<3>

7

10 87

BI

FSB_A_L<4>

7

10 87

BI

FSB_A_L<5>

7

10 87

BI

FSB_A_L<6>

7

10 87

BI

FSB_A_L<7>

7

10 87

BI

FSB_A_L<8>

7

10 87

BI

FSB_A_L<9>

7

10 87

BI

FSB_A_L<10>

7

10 87

BI

FSB_A_L<11>

7

10 87

BI

FSB_A_L<12>

7

10 87

BI

FSB_A_L<13>

7

10 87

BI

FSB_A_L<14>

7

10 87

BI

FSB_A_L<15>

7

10 87

BI

FSB_A_L<16>

7

10 87

BI

FSB_A_L<17>

7

10 87

BI

FSB_A_L<18>

7

10 87

BI

FSB_A_L<19>

7

10 87

BI

FSB_A_L<20>

7

10 87

BI

FSB_A_L<21>

7

10 87

BI

FSB_A_L<22>

7

10 87

BI

FSB_A_L<23>

7

10 87

BI

FSB_A_L<24>

7

10 87

BI

FSB_A_L<25>

7

10 87

BI

FSB_A_L<26>

7

10 87

BI

FSB_A_L<27>

7

10 87

BI

FSB_A_L<28>

7

10 87

BI

FSB_A_L<29>

7

10 87

BI

FSB_A_L<30>

7

10 87

BI

FSB_A_L<31>

7

10 87

BI

FSB_A_L<32>

10 87

BI

FSB_A_L<33>

10 87

BI

FSB_A_L<34>

10 87

BI

FSB_A_L<35>

10 87

BI

FSB_ADSTB_L<0>

7

10 87

BI

FSB_ADSTB_L<1>

7

10 87

BI

FSB_REQ_L<0>

7

10 87

BI

FSB_REQ_L<1>

7

10 87

BI

FSB_REQ_L<2>

7

10 87

BI

FSB_REQ_L<3>

7

10 87

BI

FSB_REQ_L<4>

7

10 87

BI

FSB_ADS_L

7

10 87

BI

FSB_BNR_L

10 87

BI

FSB_BREQ0_L

9

10 87

BI

FSB_BREQ1_L

87

FSB_DBSY_L

10 87

BI

FSB_DRDY_L

10 87

BI

FSB_HIT_L

7

10 87

BI

FSB_HITM_L

7

10 87

BI

FSB_LOCK_L

7

10 87

IN

FSB_TRDY_L

10 87

OUT

CPU_PECI_MCP

9

OUT

CPU_PROCHOT_L

10 43 62 87

OUT

(MCP_BSEL<2>)
(MCP_BSEL<1>)
(MCP_BSEL<0>)

FSB_RS_L<0>

10 87

OUT

FSB_RS_L<1>

10 87

OUT

FSB_RS_L<2>

10 87

OUT

PP1V05_S0_MCP_PLL_FSB

24

270 mA (A01) 206 mA

MCP_BCLK_VML_COMP_VDD

87

MCP_BCLK_VML_COMP_GND

87

MCP_CPU_COMP_VCC

87

MCP_CPU_COMP_GND

87

20 mA
29 mA
15 mA

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

T40

CPU_DSTBP0#

U40

CPU_DSTBN0#

V41

CPU_DBI0#

W39

CPU_DSTBP1#

W37

CPU_DSTBN1#

V35

CPU_DBI1#

N37

CPU_DSTBP2#

L36

CPU_DSTBN2#

N35

CPU_DBI2#

M39

CPU_DSTBP3#

M41

CPU_DSTBN3#

J41

CPU_DBI3#

AC34

CPU_A3#

AE38

CPU_A4#

AE34

CPU_A5#

AC37

CPU_A6#

AE37

CPU_A7#

AE35

CPU_A8#

AB35

CPU_A9#

AF35

CPU_A10#

AG35

CPU_A11#

AG39

CPU_A12#

AE33

CPU_A13#

AG37

CPU_A14#

AG38

CPU_A15#

AG34

CPU_A16#

AN38

CPU_A17#

AL39

CPU_A18#

AG33

CPU_A19#

AL33

CPU_A20#

AJ33

CPU_A21#

AN36

CPU_A22#

AJ35

CPU_A23#

AJ37

CPU_A24#

AJ36

CPU_A25#

AJ38

CPU_A26#

AL37

CPU_A27#

AL34

CPU_A28#

AN37

CPU_A29#

AJ34

CPU_A30#

AL38

CPU_A31#

AL35

CPU_A32#

AN34

CPU_A33#

AR39

CPU_A34#

AN35

CPU_A35#

AE36

CPU_ADSTB0#

AK35

CPU_ADSTB1#

AC38

CPU_REQ0#

AA33

CPU_REQ1#

AC39

CPU_REQ2#

AC33

CPU_REQ3#

AC35

CPU_REQ4#

AD42

CPU_ADS#

AD43

CPU_BNR#

AE40

CPU_BR0#

AL32

CPU_BR1#

AD39

CPU_DBSY#

AD41

CPU_DRDY#

AB42

CPU_HIT#

AD40

CPU_HITM#

AC43

CPU_LOCK#

AE41

CPU_TRDY#

E41

CPU_PECI

AJ41

CPU_PROCHOT#

AG43

CPU_THERMTRIP#

AH40

CPU_FERR#

F42

CPU_BSEL2

D42

CPU_BSEL1

F41

CPU_BSEL0

AC41

CPU_RS0#

AB41

CPU_RS1#

AC42

CPU_RS2#

AG27

+V_DLL_DLCELL_AVDD

AH27

+V_PLL_MCLK

AG28

+V_PLL_FSB

AH28

+V_PLL_CPU

AM39

BCLK_VML_COMP_VDD

AM40

BCLK_VML_COMP_GND

AM43

CPU_COMP_VCC

AM42

CPU_COMP_GND

(1 OF 11)

FSB

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P
BCLK_OUT_CPU_N

BCLK_OUT_ITP_P
BCLK_OUT_ITP_N

BCLK_OUT_NB_P
BCLK_OUT_NB_N

BCLK_IN_N
BCLK_IN_P

CPU_A20M#

CPU_IGNNE#

CPU_INIT#

CPU_PWRGD

CPU_RESET#

CPU_DPSLP#

CPU_DPWR#
CPU_STPCLK#
CPU_DPRSTP#

5

CPU_D0#
CPU_D1#
CPU_D2#
CPU_D3#
CPU_D4#
CPU_D5#
CPU_D6#
CPU_D7#
CPU_D8#

CPU_D9#
CPU_D10#
CPU_D11#
CPU_D12#
CPU_D13#
CPU_D14#
CPU_D15#
CPU_D16#
CPU_D17#
CPU_D18#
CPU_D19#
CPU_D20#
CPU_D21#
CPU_D22#
CPU_D23#
CPU_D24#
CPU_D25#
CPU_D26#
CPU_D27#
CPU_D28#
CPU_D29#
CPU_D30#
CPU_D31#
CPU_D32#
CPU_D33#
CPU_D34#
CPU_D35#
CPU_D36#
CPU_D37#
CPU_D38#
CPU_D39#
CPU_D40#
CPU_D41#
CPU_D42#
CPU_D43#
CPU_D44#
CPU_D45#
CPU_D46#
CPU_D47#
CPU_D48#
CPU_D49#
CPU_D50#
CPU_D51#
CPU_D52#
CPU_D53#
CPU_D54#
CPU_D55#
CPU_D56#
CPU_D57#
CPU_D58#
CPU_D59#
CPU_D60#
CPU_D61#
CPU_D62#
CPU_D63#

CPU_INTR

CPU_NMI
CPU_SMI#

CPU_SLP#

4

Y43
W42
Y40
W41
Y39
V42
Y41
Y42
P42
U41
R42
T39
T42
T41
R41
T43
W35
AA37
W33
W34
AA36
AA34
AA38
AA35
U38
U36
U35
U33
U34
W38
R33
U37
N34
N33
R34
R35
P35
R39
R37
R38
L37
L39
L38
N36
N38
J39
J38
J37
L42
M42
P41
N41
N40
M40
H40
K42
H41
L41
H43
H42
K41
J40
H39
M43

AA41
AA40

G42
G41

AL43
AL42

AL41
AK42

AK41
AJ40

AF41
AH39
AH42
AF42
AG41
AH41

AH43
H38

AM33
AN33
AM32
AG42
AN32

FSB_D_L<0>
FSB_D_L<1>
FSB_D_L<2>
FSB_D_L<3>
FSB_D_L<4>
FSB_D_L<5>
FSB_D_L<6>
FSB_D_L<7>
FSB_D_L<8>
FSB_D_L<9>
FSB_D_L<10>
FSB_D_L<11>
FSB_D_L<12>
FSB_D_L<13>
FSB_D_L<14>
FSB_D_L<15>
FSB_D_L<16>
FSB_D_L<17>
FSB_D_L<18>
FSB_D_L<19>
FSB_D_L<20>
FSB_D_L<21>
FSB_D_L<22>
FSB_D_L<23>
FSB_D_L<24>
FSB_D_L<25>
FSB_D_L<26>
FSB_D_L<27>
FSB_D_L<28>
FSB_D_L<29>
FSB_D_L<30>
FSB_D_L<31>
FSB_D_L<32>
FSB_D_L<33>
FSB_D_L<34>
FSB_D_L<35>
FSB_D_L<36>
FSB_D_L<37>
FSB_D_L<38>
FSB_D_L<39>
FSB_D_L<40>
FSB_D_L<41>
FSB_D_L<42>
FSB_D_L<43>
FSB_D_L<44>
FSB_D_L<45>
FSB_D_L<46>
FSB_D_L<47>
FSB_D_L<48>
FSB_D_L<49>
FSB_D_L<50>
FSB_D_L<51>
FSB_D_L<52>
FSB_D_L<53>
FSB_D_L<54>
FSB_D_L<55>
FSB_D_L<56>
FSB_D_L<57>
FSB_D_L<58>
FSB_D_L<59>
FSB_D_L<60>
FSB_D_L<61>
FSB_D_L<62>
FSB_D_L<63>

FSB_BPRI_L
FSB_DEFER_L

FSB_CLK_CPU_P
FSB_CLK_CPU_N

FSB_CLK_ITP_P
FSB_CLK_ITP_N

FSB_CLK_MCP_P

87

FSB_CLK_MCP_N

87

CPU_A20M_L
CPU_IGNNE_L
CPU_INIT_L
CPU_INTR
CPU_NMI
CPU_SMI_L

CPU_PWRGD
FSB_CPURST_L

FSB_CPUSLP_L
CPU_DPSLP_L
FSB_DPWR_L
CPU_STPCLK_L
CPU_DPRSTP_L

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

7

10 87

BI

10 87

OUT

10 87

OUT

10 87

OUT

10 87

OUT

13 87

OUT

13 87

OUT

Loop-back clock for delay matching.

10 87

OUT

10 87

OUT

10 87

OUT

9

10 87

OUT

9

10 87

OUT

10 87

OUT

9

10 13 87

OUT

10 87

OUT

10 87

OUT

10 87

OUT

10 87

OUT

9

10 62 87

OUT

=PP1V05_S0_MCP_FSB

NO STUFF

1

R1440

150

5%
1/16W
MF-LF
402

2

10 13 87

OUT

3

24

22

14

8

SYNC_MASTER=T18_MLB

APPLE INC.

2

MCP CPU Interface

SYNC_DATE=06/18/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

1

D

C

B

A

REV.

A.0.0

OF

9614

8 7

6

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

MDQ0_63
MDQ0_62
MDQ0_61
MDQ0_60
MDQ0_59
MDQ0_58
MDQ0_57
MDQ0_56
MDQ0_55
MDQ0_54
MDQ0_53
MDQ0_52
MDQ0_51
MDQ0_50
MDQ0_49
MDQ0_48
MDQ0_47
MDQ0_46
MDQ0_45
MDQ0_44
MDQ0_43
MDQ0_42
MDQ0_41
MDQ0_40
MDQ0_39
MDQ0_38
MDQ0_37
MDQ0_36
MDQ0_35
MDQ0_34
MDQ0_33
MDQ0_32
MDQ0_31
MDQ0_30
MDQ0_29
MDQ0_28
MDQ0_27
MDQ0_26
MDQ0_25
MDQ0_24
MDQ0_23
MDQ0_22
MDQ0_21
MDQ0_20
MDQ0_19
MDQ0_18
MDQ0_17
MDQ0_16
MDQ0_15
MDQ0_14
MDQ0_13
MDQ0_12
MDQ0_11
MDQ0_10
MDQ0_9
MDQ0_8
MDQ0_7
MDQ0_6
MDQ0_5
MDQ0_4
MDQ0_3
MDQ0_2
MDQ0_1
MDQ0_0

MDQM0_7
MDQM0_6
MDQM0_5
MDQM0_4
MDQM0_3
MDQM0_2
MDQM0_1
MDQM0_0

(2 OF 11)

MDQS0_7_P
MDQS0_7_N
MDQS0_6_P
MDQS0_6_N
MDQS0_5_P
MDQS0_5_N
MDQS0_4_P
MDQS0_4_N
MDQS0_3_P
MDQS0_3_N
MDQS0_2_P
MDQS0_2_N
MDQS0_1_P
MDQS0_1_N
MDQS0_0_P
MDQS0_0_N

MEMORY PARTITION 0

MEMORY

CONTROL

MCLK0A_2_P
MCLK0A_2_N

MCLK0A_1_P
MCLK0A_1_N

MCLK0A_0_P
MCLK0A_0_N

MRAS0#
MCAS0#

MWE0#

MBA0_2
MBA0_1
MBA0_0

MA0_14
MA0_13
MA0_12
MA0_11
MA0_10

MA0_9
MA0_8
MA0_7
MA0_6
MA0_5
MA0_4
MA0_3
MA0_2
MA0_1
MA0_0

0A

MCS0A_1#
MCS0A_0#

MODT0A_1
MODT0A_0

MCKE0A_1
MCKE0A_0

AL10
AL11
AR8
AR9
AW7
AW8
AP13
AR13
AV25
AW25
AU30
AU29
AT35
AU35
AU39
AT39

AV17
AP17
AR17

AP23
AP19
AW17

AR23
AU15
AN23
AW21
AN19
AV21
AR22
AU21
AP21
AR21
AN21
AV19
AU19
AT19
AR19

AW33
AV33

BA24
AY24

BB20
BC20

AT15
AR18

AP15
AV15

AU23
AT23

MEM_A_DQS_P<7>
MEM_A_DQS_N<7>
MEM_A_DQS_P<6>
MEM_A_DQS_N<6>
MEM_A_DQS_P<5>
MEM_A_DQS_N<5>
MEM_A_DQS_P<4>
MEM_A_DQS_N<4>
MEM_A_DQS_P<3>
MEM_A_DQS_N<3>
MEM_A_DQS_P<2>
MEM_A_DQS_N<2>
MEM_A_DQS_P<1>
MEM_A_DQS_N<1>
MEM_A_DQS_P<0>
MEM_A_DQS_N<0>

MEM_A_RAS_L
MEM_A_CAS_L
MEM_A_WE_L

MEM_A_BA<2>
MEM_A_BA<1>
MEM_A_BA<0>

MEM_A_A<14>
MEM_A_A<13>
MEM_A_A<12>
MEM_A_A<11>
MEM_A_A<10>
MEM_A_A<9>
MEM_A_A<8>
MEM_A_A<7>
MEM_A_A<6>
MEM_A_A<5>
MEM_A_A<4>
MEM_A_A<3>
MEM_A_A<2>
MEM_A_A<1>
MEM_A_A<0>

TP_MEM_A_CLK2P
TP_MEM_A_CLK2N

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_CS_L<1>
MEM_A_CS_L<0>

MEM_A_ODT<1>
MEM_A_ODT<0>

MEM_A_CKE<1>
MEM_A_CKE<0>

BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI
BI

OUT
OUT
OUT

OUT
OUT
OUT

OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

OUT
OUT

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

28 88

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

MEM_B_DQ<63>
MEM_B_DQ<62>
MEM_B_DQ<61>
MEM_B_DQ<60>
MEM_B_DQ<59>
MEM_B_DQ<58>
MEM_B_DQ<57>
MEM_B_DQ<56>
MEM_B_DQ<55>
MEM_B_DQ<54>
MEM_B_DQ<53>
MEM_B_DQ<52>
MEM_B_DQ<51>
MEM_B_DQ<50>
MEM_B_DQ<49>
MEM_B_DQ<48>
MEM_B_DQ<47>
MEM_B_DQ<46>
MEM_B_DQ<45>
MEM_B_DQ<44>
MEM_B_DQ<43>
MEM_B_DQ<42>
MEM_B_DQ<41>
MEM_B_DQ<40>
MEM_B_DQ<39>
MEM_B_DQ<38>
MEM_B_DQ<37>
MEM_B_DQ<36>
MEM_B_DQ<35>
MEM_B_DQ<34>
MEM_B_DQ<33>
MEM_B_DQ<32>
MEM_B_DQ<31>
MEM_B_DQ<30>
MEM_B_DQ<29>
MEM_B_DQ<28>
MEM_B_DQ<27>
MEM_B_DQ<26>
MEM_B_DQ<25>
MEM_B_DQ<24>
MEM_B_DQ<23>
MEM_B_DQ<22>
MEM_B_DQ<21>
MEM_B_DQ<20>
MEM_B_DQ<19>
MEM_B_DQ<18>
MEM_B_DQ<17>
MEM_B_DQ<16>
MEM_B_DQ<15>
MEM_B_DQ<14>
MEM_B_DQ<13>
MEM_B_DQ<12>
MEM_B_DQ<11>
MEM_B_DQ<10>
MEM_B_DQ<9>
MEM_B_DQ<8>
MEM_B_DQ<7>
MEM_B_DQ<6>
MEM_B_DQ<5>
MEM_B_DQ<4>
MEM_B_DQ<3>
MEM_B_DQ<2>
MEM_B_DQ<1>
MEM_B_DQ<0>

MEM_B_DM<7>
MEM_B_DM<6>
MEM_B_DM<5>
MEM_B_DM<4>
MEM_B_DM<3>
MEM_B_DM<2>
MEM_B_DM<1>
MEM_B_DM<0>

AT4
AT3
AV2
AV3
AR4
AR3
AU2
AU3
AY4
AY3
BB3
BC3
AW4
AW3
BA3
BB2
BB5
BA5
BA8
BC8
BB4
BC4
BA7
AY8

BA9
BB10
BB12
AW12

BB8

BB9
AY12
BA12
BC32
AW32
BA35
AY36
BA32
BB32
BA34
AY35
BC36
AW36
BA39
AY40
BA36
BB36
BA38
AY39
BB40
AW40
AV42
AV41
BA40
BC40
AW42
AW41
AT40
AT41
AP41
AN40
AU40
AU41
AR41
AP42

AT5

BA2

AY7
BA11
BB34
BB38
AY43
AR42

MEM_A_DQ<63>

28 88

BI

MEM_A_DQ<62>

28 88

BI

MEM_A_DQ<61>

28 88

BI

MEM_A_DQ<60>

28 88

BI

MEM_A_DQ<59>

28 88

D

C

B

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

BI

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

28 88

OUT

MEM_A_DQ<58>
MEM_A_DQ<57>
MEM_A_DQ<56>
MEM_A_DQ<55>
MEM_A_DQ<54>
MEM_A_DQ<53>
MEM_A_DQ<52>
MEM_A_DQ<51>
MEM_A_DQ<50>
MEM_A_DQ<49>
MEM_A_DQ<48>
MEM_A_DQ<47>
MEM_A_DQ<46>
MEM_A_DQ<45>
MEM_A_DQ<44>
MEM_A_DQ<43>
MEM_A_DQ<42>
MEM_A_DQ<41>
MEM_A_DQ<40>
MEM_A_DQ<39>
MEM_A_DQ<38>
MEM_A_DQ<37>
MEM_A_DQ<36>
MEM_A_DQ<35>
MEM_A_DQ<34>
MEM_A_DQ<33>
MEM_A_DQ<32>
MEM_A_DQ<31>
MEM_A_DQ<30>
MEM_A_DQ<29>
MEM_A_DQ<28>
MEM_A_DQ<27>
MEM_A_DQ<26>
MEM_A_DQ<25>
MEM_A_DQ<24>
MEM_A_DQ<23>
MEM_A_DQ<22>
MEM_A_DQ<21>
MEM_A_DQ<20>
MEM_A_DQ<19>
MEM_A_DQ<18>
MEM_A_DQ<17>
MEM_A_DQ<16>
MEM_A_DQ<15>
MEM_A_DQ<14>
MEM_A_DQ<13>
MEM_A_DQ<12>
MEM_A_DQ<11>
MEM_A_DQ<10>
MEM_A_DQ<9>
MEM_A_DQ<8>
MEM_A_DQ<7>
MEM_A_DQ<6>
MEM_A_DQ<5>
MEM_A_DQ<4>
MEM_A_DQ<3>
MEM_A_DQ<2>
MEM_A_DQ<1>
MEM_A_DQ<0>

MEM_A_DM<7>
MEM_A_DM<6>
MEM_A_DM<5>
MEM_A_DM<4>
MEM_A_DM<3>
MEM_A_DM<2>
MEM_A_DM<1>
MEM_A_DM<0>

AL8
AL9
AP9
AN9
AL6
AL7
AN6
AN7
AR6
AR7
AV6
AW5

AN10

AR5
AU6
AV5
AU7
AU8
AW9

AP11

AW6
AY5
AU9

AV9
AU11
AV11
AV13
AW13
AR11
AT11
AR14
AU13
AR26
AU25
AT27
AU27
AP25
AR25
AP27
AR27
AP29
AR29
AP31
AR31
AV27
AN29
AV29
AN31
AU31
AR33
AV37
AW37
AT31
AV31
AT37
AU37
AW39
AV39
AR37
AR38
AV38
AW38
AR35
AP35

AN5

AU5
AR10
AN13
AN27
AW29
AV35
AR34

OMIT

U1400

MCP79-TOPO-B

BGA

(3 OF 11)

MDQ1_63
MDQ1_62
MDQ1_61
MDQ1_60
MDQ1_59
MDQ1_58
MDQ1_57
MDQ1_56
MDQ1_55
MDQ1_54
MDQ1_53
MDQ1_52
MDQ1_51
MDQ1_50
MDQ1_49
MDQ1_48
MDQ1_47
MDQ1_46
MDQ1_45
MDQ1_44
MDQ1_43
MDQ1_42
MDQ1_41
MDQ1_40
MDQ1_39
MDQ1_38
MDQ1_37
MDQ1_36
MDQ1_35
MDQ1_34
MDQ1_33
MDQ1_32
MDQ1_31
MDQ1_30
MDQ1_29
MDQ1_28
MDQ1_27
MDQ1_26
MDQ1_25
MDQ1_24
MDQ1_23
MDQ1_22
MDQ1_21
MDQ1_20
MDQ1_19
MDQ1_18
MDQ1_17
MDQ1_16
MDQ1_15
MDQ1_14
MDQ1_13
MDQ1_12
MDQ1_11
MDQ1_10
MDQ1_9
MDQ1_8
MDQ1_7
MDQ1_6
MDQ1_5
MDQ1_4
MDQ1_3
MDQ1_2
MDQ1_1
MDQ1_0

MDQM1_7
MDQM1_6
MDQM1_5
MDQM1_4
MDQM1_3
MDQM1_2
MDQM1_1
MDQM1_0

CONTROL

MRAS1#
MCAS1#

MWE1#

MBA1_2
MBA1_1
MBA1_0

MA1_14
MA1_13
MA1_12
MA1_11
MA1_10

MA1_9
MA1_8
MA1_7
MA1_6
MA1_5
MA1_4
MA1_3
MA1_2
MA1_1
MA1_0

AT2
AT1
AY2
AY1
BB6
BA6
BA10
AY11
BB33
BA33
BB37
BA37
BA43
AY42
AT42
AT43

AW16
BA15
BA16

BB29
BB18
BB17

BA29
BA14
AW28
BC28
BA17
BB28
AY28
BA28
AY27
BA27
BA26
BB26
BA25
BB25
BA18

MDQS1_7_P
MDQS1_7_N
MDQS1_6_P
MDQS1_6_N
MDQS1_5_P
MDQS1_5_N
MDQS1_4_P
MDQS1_4_N
MDQS1_3_P
MDQS1_3_N
MDQS1_2_P
MDQS1_2_N
MDQS1_1_P
MDQS1_1_N
MDQS1_0_P
MDQS1_0_N

MEMORY PARTITION 1

MEM_B_DQS_P<7>
MEM_B_DQS_N<7>
MEM_B_DQS_P<6>
MEM_B_DQS_N<6>
MEM_B_DQS_P<5>
MEM_B_DQS_N<5>
MEM_B_DQS_P<4>
MEM_B_DQS_N<4>
MEM_B_DQS_P<3>
MEM_B_DQS_N<3>
MEM_B_DQS_P<2>
MEM_B_DQS_N<2>
MEM_B_DQS_P<1>
MEM_B_DQS_N<1>
MEM_B_DQS_P<0>
MEM_B_DQS_N<0>

MEM_B_RAS_L
MEM_B_CAS_L
MEM_B_WE_L

MEM_B_BA<2>
MEM_B_BA<1>
MEM_B_BA<0>

MEM_B_A<14>
MEM_B_A<13>
MEM_B_A<12>
MEM_B_A<11>
MEM_B_A<10>
MEM_B_A<9>
MEM_B_A<8>
MEM_B_A<7>
MEM_B_A<6>
MEM_B_A<5>
MEM_B_A<4>
MEM_B_A<3>
MEM_B_A<2>
MEM_B_A<1>
MEM_B_A<0>

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

BI

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

MEMORY

1A

MCLK1A_2_P
MCLK1A_2_N

MCLK1A_1_P
MCLK1A_1_N

MCLK1A_0_P
MCLK1A_0_N

MCS1A_1#
MCS1A_0#

MODT1A_1
MODT1A_0

MCKE1A_1
MCKE1A_0

BA42
BB42

BB22
BA22

BA19
AY19

BB14
BB16

BB13
AY15

AY31
BB30

TP_MEM_B_CLK2P
TP_MEM_B_CLK2N

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_CS_L<1>
MEM_B_CS_L<0>

MEM_B_ODT<1>
MEM_B_ODT<0>

MEM_B_CKE<1>
MEM_B_CKE<0>

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

29 88

OUT

D

C

B

MCP Memory Interface

A

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

15

96

1

A

REV.

A.0.0

8 7

6

D

=PP1V8R1V5_S0_MCP_MEM

24

16

8

1

R1610

40.2

1%
1/16W
MF-LF

402

2

1

R1611

40.2

C

1/16W
MF-LF

1%

402

2

B

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

TP_MEM_A_CLK5P
TP_MEM_A_CLK5N

TP_MEM_A_CLK4P
TP_MEM_A_CLK4N

TP_MEM_A_CLK3P
TP_MEM_A_CLK3N

TP_MEM_A_CS_L<2>
TP_MEM_A_CS_L<3>

TP_MEM_A_ODT<2>
TP_MEM_A_ODT<3>

TP_MEM_A_CKE<2>
TP_MEM_A_CKE<3>

PP1V05_S0_MCP_PLL_CORE

24

87 mA (A01)

MCP_MEM_COMP_VDD

88

MCP_MEM_COMP_GND

88

17 mA
12 mA
19 mA
39 mA

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

AU33

MCLK0B_2_P

AU34

MCLK0B_2_N

BB24

MCLK0B_1_P

BC24

MCLK0B_1_N

BA21

MCLK0B_0_P

BB21

MCLK0B_0_N

AU17

MCS0B_0#

AR15

MCS0B_1#

AN17

MODT0B_0

AN15

MODT0B_1

AV23

MCKE0B_0

AN25

MCKE0B_1

T27

+V_PLL_XREF_XS

U28

+V_PLL_DP

U27

+V_PLL_CORE

T28

+V_VPLL

AN41

MEM_COMP_VDD

AM41

MEM_COMP_GND

AA22

GND1

AP12

GND2

G30

GND3

P10

GND4

T10

GND5

T6

GND6

V10

GND7

V34

GND8

W5

GND9

AA39

GND10

AB22

GND11

AB7

GND12

AD22

GND13

AE20

GND14

AF24

GND15

AG24

GND16

AH35

GND17

AK7

GND18

AM28

GND19

AT25

GND20

AP30

GND21

AR36

GND22

AU10

GND23

F28

GND24

BC21

GND25

AY9

GND26

BC9

GND27

D34

GND28

F24

GND29

G32

GND30

H31

GND31

K7

GND32

M38

GND33

M5

GND34

M6

GND35

M7

GND36

M9

GND37

N39

GND38

N8

GND39

P33

GND40

P34

GND41

P37

GND42

P4

GND43

P40

GND44

P7

GND45

R36

GND46

R40

GND47

R43

GND48

R5

GND49

T18

GND50

T20

GND51

AK11

GND52

T24

GND53

T26

GND54

5

(4 OF 11)

MCLK1B_2_P
MCLK1B_2_N

MCLK1B_1_P
MCLK1B_1_N

MCLK1B_0_P
MCLK1B_0_N

MEMORY CONTROL 0B

MEMORY CONTROL 1B

+VDD_MEM1
+VDD_MEM2
+VDD_MEM3
+VDD_MEM4
+VDD_MEM5
+VDD_MEM6
+VDD_MEM7
+VDD_MEM8

+VDD_MEM9
+VDD_MEM10
+VDD_MEM11
+VDD_MEM12
+VDD_MEM13
+VDD_MEM14
+VDD_MEM15
+VDD_MEM16
+VDD_MEM17
+VDD_MEM18
+VDD_MEM19
+VDD_MEM20
+VDD_MEM21
+VDD_MEM22
+VDD_MEM23
+VDD_MEM24
+VDD_MEM25
+VDD_MEM26
+VDD_MEM27
+VDD_MEM28
+VDD_MEM29
+VDD_MEM30
+VDD_MEM31
+VDD_MEM32
+VDD_MEM33
+VDD_MEM34
+VDD_MEM35
+VDD_MEM36
+VDD_MEM37
+VDD_MEM38
+VDD_MEM39
+VDD_MEM40
+VDD_MEM41
+VDD_MEM42
+VDD_MEM43
+VDD_MEM44
+VDD_MEM45

MCS1B_0#
MCS1B_1#

MODT1B_0
MODT1B_1

MCKE1B_0
MCKE1B_1

MRESET0#

GND55
GND56
GND57
GND58
GND59
GND60
GND61
GND62
GND63
GND64

BA41
BB41

AY23
BA23

BA20
AY20

BC16
BA13

AY16
BC13

BA30
BA31

AY32

AM17
AM19
AM21
AM23
AM25
AM27
AM29
AN16
BC29
AN20
AN24
AT17
AP16
AN22
AP20
AP24
AV16
AR16
AR20
AR24
AW15
AP22
AP18
AU16
AN18
AU24
AT21
AY29
AV24
AU20
AU22
AW27
BC17
AV20
AY17
AY18
AM15
AU18
AY25
AY26
AW19
AW24
BC25
AL30
AM31

T33
T34
T35
T37
T38
T7
T9
U18
U20
U22

TP_MEM_B_CLK5P
TP_MEM_B_CLK5N

TP_MEM_B_CLK4P
TP_MEM_B_CLK4N

TP_MEM_B_CLK3P
TP_MEM_B_CLK3N

TP_MEM_B_CS_L<2>
TP_MEM_B_CS_L<3>

TP_MEM_B_ODT<2>
TP_MEM_B_ODT<3>

TP_MEM_B_CKE<2>
TP_MEM_B_CKE<3>

MCP_MEM_RESET_L

TP or NC for DDR2.

=PP1V8R1V5_S0_MCP_MEM

4771 mA (A01, DDR3)

4

D

30

OUT

24

16

8

C

B

MCP Memory Misc

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

16 96

1

A

REV.

A.0.0

8 7

6

D

C

31

31

36

32

32

83

23 31 32

31 89

31 89

36 89

B

36 89

32 89

32 89

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

=PEG_D2R_P<0>

9

IN

=PEG_D2R_N<0>

9

IN

=PEG_D2R_P<1>

9

IN

=PEG_D2R_N<1>

9

IN

=PEG_D2R_P<2>

9

IN

=PEG_D2R_N<2>

9

IN

=PEG_D2R_P<3>

9

IN

=PEG_D2R_N<3>

9

IN

=PEG_D2R_P<4>

9

IN

=PEG_D2R_N<4>

9

IN

=PEG_D2R_P<5>

9

IN

=PEG_D2R_N<5>

9

IN

=PEG_D2R_P<6>

9

IN

=PEG_D2R_N<6>

9

IN

=PEG_D2R_P<7>

9

IN

=PEG_D2R_N<7>

9

IN

=PEG_D2R_P<8>

9

IN

=PEG_D2R_N<8>

9

IN

=PEG_D2R_P<9>

9

IN

=PEG_D2R_N<9>

9

IN

=PEG_D2R_P<10>

9

IN

=PEG_D2R_N<10>

9

IN

=PEG_D2R_P<11>

9

IN

=PEG_D2R_N<11>

9

IN

=PEG_D2R_P<12>

9

IN

=PEG_D2R_N<12>

9

IN

=PEG_D2R_P<13>

9

IN

=PEG_D2R_N<13>

9

IN

=PEG_D2R_P<14>

9

IN

=PEG_D2R_N<14>

9

IN

=PEG_D2R_P<15>

9

IN

=PEG_D2R_N<15>

9

IN

PEG_PRSNT_L

9

IN

MINI_CLKREQ_L

IN

PCIE_MINI_PRSNT_L

IN

FW_CLKREQ_L

IN

PCIE_FW_PRSNT_L

9

IN

EXCARD_CLKREQ_L

IN

PCIE_EXCARD_PRSNT_L

IN

TP_PE4_CLKREQ_L

9

TP_PE4_PRSNT_L

9

AUD_IP_PERIPHERAL_DET

9

IN

GMUX_JTAG_TCK_L

OUT

TP_MCP_GPIO_18
GMUX_JTAG_TDO

9

IN

PCIE_WAKE_L

IN

PCIE_MINI_D2R_P

IN

PCIE_MINI_D2R_N

IN

PCIE_FW_D2R_P

IN

PCIE_FW_D2R_N

IN

PCIE_EXCARD_D2R_P

7

IN

PCIE_EXCARD_D2R_N

7

IN

TP_PCIE_PE4_D2RP

9

TP_PCIE_PE4_D2RN

9

=PP1V05_S0_MCP_PEX_DVDD0

8

57 mA (A01, DVDD0 & 1)

=PP1V05_S0_MCP_PEX_DVDD1

8

PP1V05_S0_MCP_PLL_PEX

24

84 mA (A01)

MCP_PEX_CLK_COMP

89

NO STUFF

1

R1710

2.37K

1%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place within 12.7mm of U1400

5

4

OMIT

U1400

MCP79-TOPO-B

BGA

F7

PE0_RX0_P

E7

PE0_RX0_N

D7

PE0_RX1_P

C7

PE0_RX1_N

E6

PE0_RX2_P

F6

PE0_RX2_N

E5

PE0_RX3_P

F5

PE0_RX3_N

E4

PE0_RX4_P

E3

PE0_RX4_N

C3

PE0_RX5_P

D3

PE0_RX5_N

G5

PE0_RX6_P

H5

PE0_RX6_N

J7

PE0_RX7_P

J6

PE0_RX7_N

J5

PE0_RX8_P

J4

PE0_RX8_N

L11

PE0_RX9_P

L10

PE0_RX9_N

L9

PE0_RX10_P

L8

PE0_RX10_N

L7

PE0_RX11_P

L6

PE0_RX11_N

N11

PE0_RX12_P

N10

PE0_RX12_N

N9

PE0_RX13_P

P9

PE0_RX13_N

N7

PE0_RX14_P

N6

PE0_RX14_N

N5

PE0_RX15_P

N4

PE0_RX15_N

Int PU

C9 D11

PE0_PRSNT_16#

Int PU

D5

PEB_CLKREQ#/GPIO_49

D9

PEB_PRSNT#

Int PU

E8

PEC_CLKREQ#/GPIO_50

C10

PEC_PRSNT#

Int PU

M15

PED_CLKREQ#/GPIO_51

B10

PED_PRSNT#

Int PU

L16

PEE_CLKREQ#/GPIO_16

L18

PEE_PRSNT#/GPIO_46

Int PU

M16

PEF_CLKREQ#/GPIO_17

M18

PEF_PRSNT#/GPIO_47

Int PU

M17

PEG_CLKREQ#/GPIO_18

M19

PEG_PRSNT#/GPIO_48

F17

PE_WAKE#

K9

PE1_RX0_P

J9

PE1_RX0_N

H9

PE1_RX1_P

G9

PE1_RX1_N

F9

PE1_RX2_P

E9

PE1_RX2_N

H7

PE1_RX3_P

G7

PE1_RX3_N

T17

+DVDD0_PEX1

W19

+DVDD0_PEX2

U17

+DVDD0_PEX3

V19

+DVDD0_PEX4

W16

+DVDD0_PEX5

W17

+DVDD0_PEX6

W18

+DVDD0_PEX7

U16

+DVDD0_PEX8

T19

+DVDD1_PEX1

U19

+DVDD1_PEX2

T16

+V_PLL_PEX

A11

PEX_CLK_COMP

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.
If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

(5 OF 11)

PCI EXPRESS

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU

Int PU (S5)

PE0_TX0_P

PE0_TX0_N

PE0_TX1_P

PE0_TX1_N

PE0_TX2_P

PE0_TX2_N

PE0_TX3_P

PE0_TX3_N

PE0_TX4_P

PE0_TX4_N

PE0_TX5_P

PE0_TX5_N

PE0_TX6_P

PE0_TX6_N

PE0_TX7_P

PE0_TX7_N

PE0_TX8_P

PE0_TX8_N

PE0_TX9_P

PE0_TX9_N
PE0_TX10_P
PE0_TX10_N
PE0_TX11_P
PE0_TX11_N
PE0_TX12_P
PE0_TX12_N
PE0_TX13_P
PE0_TX13_N
PE0_TX14_P
PE0_TX14_N
PE0_TX15_P
PE0_TX15_N

PE0_REFCLK_P
PE0_REFCLK_N

PE1_REFCLK_P
PE1_REFCLK_N

PE2_REFCLK_P
PE2_REFCLK_N

PE3_REFCLK_P
PE3_REFCLK_N

PE4_REFCLK_P
PE4_REFCLK_N

PE5_REFCLK_P
PE5_REFCLK_N

PE6_REFCLK_P
PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE1_TX0_N

PE1_TX1_P

PE1_TX1_N

PE1_TX2_P

PE1_TX2_N

PE1_TX3_P

PE1_TX3_N

+AVDD0_PEX1
+AVDD0_PEX2
+AVDD0_PEX3
+AVDD0_PEX4
+AVDD0_PEX5
+AVDD0_PEX6
+AVDD0_PEX7
+AVDD0_PEX8

+AVDD0_PEX9
+AVDD0_PEX10
+AVDD0_PEX11
+AVDD0_PEX12
+AVDD0_PEX13

+AVDD1_PEX1

+AVDD1_PEX2

+AVDD1_PEX3

5

C5
D4
C4
B4
A4
A3
B3
B2
C1
D1
D2
E1
E2
F2
F3
F4
G3
H4
H3
H2
H1
J1
J2
J3
K2
K3
L4
L3
M4
M3
M2
M1

E11

G11
F11

J11
J10

G13
F13

J13
H13

L14
K14

N14
M14

K11

D8
C8

B8
A8

A7
B7

B6
C6

Y12
AA12
AB12
M12
P12
R12
N12
T12
U12
AC12
AD12
V12
W12

M13
N13
P13

=PEG_R2D_C_P<0>
=PEG_R2D_C_N<0>
=PEG_R2D_C_P<1>
=PEG_R2D_C_N<1>
=PEG_R2D_C_P<2>
=PEG_R2D_C_N<2>
=PEG_R2D_C_P<3>
=PEG_R2D_C_N<3>
=PEG_R2D_C_P<4>
=PEG_R2D_C_N<4>
=PEG_R2D_C_P<5>
=PEG_R2D_C_N<5>
=PEG_R2D_C_P<6>
=PEG_R2D_C_N<6>
=PEG_R2D_C_P<7>
=PEG_R2D_C_N<7>
=PEG_R2D_C_P<8>
=PEG_R2D_C_N<8>
=PEG_R2D_C_P<9>
=PEG_R2D_C_N<9>
=PEG_R2D_C_P<10>
=PEG_R2D_C_N<10>
=PEG_R2D_C_P<11>
=PEG_R2D_C_N<11>
=PEG_R2D_C_P<12>
=PEG_R2D_C_N<12>
=PEG_R2D_C_P<13>
=PEG_R2D_C_N<13>
=PEG_R2D_C_P<14>
=PEG_R2D_C_N<14>
=PEG_R2D_C_P<15>
=PEG_R2D_C_N<15>

PEG_CLK100M_P
PEG_CLK100M_N

PCIE_CLK100M_MINI_P
PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P
PCIE_CLK100M_FW_N

PCIE_CLK100M_EXCARD_P
PCIE_CLK100M_EXCARD_N

TP_PCIE_CLK100M_PE4P
TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE5P
TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE6P
TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P
PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P
PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_P
PCIE_EXCARD_R2D_C_N

TP_PCIE_PE4_R2D_CP
TP_PCIE_PE4_R2D_CN

=PP1V05_S0_MCP_PEX_AVDD0

206 mA (A01, AVDD0 & 1)

Minimum 1.025V for Gen2 supportMinimum 1.025V for Gen2 support

=PP1V05_S0_MCP_PEX_AVDD1

4

3

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

70 89

OUT

70 89

OUT

31 89

OUT

31 89

OUT

36 89

OUT

36 89

OUT

32 89

OUT

32 89

OUT

9

9

9

26

OUT

31 89

OUT

31 89

OUT

36 89

OUT

36 89

OUT

32 89

OUT

32 89

OUT

9

9

8

8

2 1

D

C

B

MCP PCIe Interfaces

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

17 96

1

A

REV.

A.0.0

8 7

6

D

33 91

IN

33 91

IN

33 91

IN

33 91

IN

33 91

IN

33 91

IN

9

IN

9

=PP3V3_ENET_MCP_RMGT

24

18

8

R1810

49.9

1/16W
MF-LF

R1811

49.9

1/16W
MF-LF

1

1%

402

2

1

1%

402

2

IN

9

IN

24

91

91

25

25

C

25 89

OUT

25 89

OUT

=PP3V3_S5_MCP_GPIO

20

8

25

1

R1820

47K

5%
1/16W
MF-LF

402

2

44

BI

Interface Mode
MCP Signal
=MCP_HDMI_TXC_P/N

=MCP_HDMI_TXD_P/N<0>
=MCP_HDMI_TXD_P/N<1>
=MCP_HDMI_TXD_P/N<2>
=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

B

=MCP_HDMI_HPD
DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.
NOTE: 20K pull-down required on DP_HPD_DET.
NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: HDMI port requires level-shifting. IFP interface can
be used to provide HDMI or dual-channel TMDS without
level-shifters.

TMDS/HDMI
TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>
TMDS_IG_TXD_P/N<1>
TMDS_IG_TXD_P/N<2>
TMDS_IG_DDC_CLK
TMDS_IG_DDC_DATA
TMDS_IG_HPD
TP_DP_IG_AUX_CHP/N

LVDS: Power +VDD_IFPx at 1.8V
Dual-channel TMDS: Power +VDD_IFPx at 3.3V

DisplayPort
DP_IG_ML_P/N<3>

DP_IG_ML_P/N<2>
DP_IG_ML_P/N<1>
DP_IG_ML_P/N<0>
DP_IG_DDC_CLK
DP_IG_DDC_DATA
DP_IG_HPD
DP_IG_AUX_CH_P/N

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

IN

25

OUT

80

IN

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

9

OUT

80 89

OUT

80 89

OUT

9

IN

9

IN

25

8

25

25

8

25 89

OUT

25 89

OUT

GPIOs 57-59 (if LCD panel is used):
In MCP79 these pins have undocumented internal

pull-ups (~10K to 3.3V S0). To ensure pins are low
by default, pull-downs (1K or stronger) must be used.

=DVI_HPD_GMUX_INT:
Alias to DVI_HPD for systems using IFP for DVI.

Alias to GMUX_INT for systems with GMUX.
Alias to HPLUG_DET2 for other systems.
Pull-down (20k) required in all cases.

ENET_RXD<0>
ENET_RXD<1>
ENET_RXD<2>
ENET_RXD<3>

ENET_CLK125M_RXCLK
ENET_RX_CTRL

=MCP_MII_RXER
=MCP_MII_COL
=MCP_MII_CRS

TP_ENET_INTR_L
PP1V05_ENET_MCP_PLL_MAC

5 mA (A01)

MCP_MII_COMP_VDD
MCP_MII_COMP_GND

TP_MCP_RGB_DAC_RSET
TP_MCP_RGB_DAC_VREF

MCP_TV_DAC_RSET
MCP_TV_DAC_VREF

MCP_CLK27M_XTALIN
MCP_CLK27M_XTALOUT

LPCPLUS_GPIO
DP_IG_CA_DET

LVDS_IG_BKL_PWM
LVDS_IG_BKL_ON
LVDS_IG_PANEL_PWR

=MCP_HDMI_TXC_P
=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0>
=MCP_HDMI_TXD_N<0>
=MCP_HDMI_TXD_P<1>
=MCP_HDMI_TXD_N<1>
=MCP_HDMI_TXD_P<2>
=MCP_HDMI_TXD_N<2>

DP_IG_AUX_CH_P
DP_IG_AUX_CH_N

=DVI_HPD_GMUX_INT
=MCP_HDMI_HPD

=PP3V3R1V8_S0_MCP_IFP_VDD

190 mA (A01, 1.8V)

PP3V3_S0_MCP_VPLL

16 mA (A01)

=PP1V05_S0_MCP_HDMI_VDD

95 mA (A01)

MCP_HDMI_RSET
MCP_HDMI_VPROBE

(See below)

(See below)

8 mA
8 mA

5

C23

RGMII_RXD0

B23

RGMII_RXD1

E24

RGMII_RXD2

A24

RGMII_RXD3

A23

RGMII_RXC/MII_RXCLK

C22

RGMII_RXCTL/MII_RXDV

F23

MII_RXER/GPIO_36

B26

MII_COL/GPIO_20/MSMB_DATA

B22

MII_CRS/GPIO_21/MSMB_CLK

J22

RGMII_INTR/GPIO_35

T23

+V_DUAL_MACPLL

C27

MII_COMP_VDD

B27

MII_COMP_GND

C39

RGB_DAC_RSET

B38

RGB_DAC_VREF

E36

TV_DAC_RSET

A35

TV_DAC_VREF

C38

XTALIN_TV

D38

XTALOUT_TV

E16

GPIO_6/FERR*/IGPU_GPIO_6

B15

GPIO_7/NFERR*/IGPU_GPIO_7

G39

LCD_BKL_CTL/GPIO_57

E37

LCD_BKL_ON/GPIO_59

F40

LCD_PANEL_PWR/GPIO_58

D35

HDMI_TXC_P/ML0_LANE3_P

E35

HDMI_TXC_N/ML0_LANE3_N

G35

HDMI_TXD0_P/ML0_LANE2_P

F35

HDMI_TXD0_N/ML0_LANE2_N

F33

HDMI_TXD1_P/ML0_LANE1_P

G33

HDMI_TXD1_N/ML0_LANE1_N

J33

HDMI_TXD2_P/ML0_LANE0_P

H33

HDMI_TXD2_N/ML0_LANE0_N

D43

DP_AUX_CH0_P

C43

DP_AUX_CH0_N

C31

HPLUG_DET2/GPIO_22

F31

HPLUG_DET3

M27

+VDD_IFPA

M26

+VDD_IFPB

M28

+V_PLL_IFPAB

M29

+V_PLL_HDMI

T25

+VDD_HDMI

J31

HDMI_RSET

J30

HDMI_VPROBE

5

OMIT

U1400

MCP79-TOPO-B

BGA

(6 OF 11)

LAN

DACS

TV / Component
C / Pr
Y / Y
Comp / Pb

4

MII_VREF

DDC_CLK0

DDC_CLK3

J24
K24

U23
V23

E28

B24
C24
C25
D25

D24
C26

D21
C21

G23

E23

J23

J32
K32

B31
A31

B39
A39
B40

A40
A41

A36
B36
C36

D36
C37

B35
C35

B32
A32
D32
C32
D33
C33
B34
C34

L31
K31

J29
H29
L29
K29
L30
K30
N30
M30

C30
B30

D31
E31

E32
G31

+3.3V_DUAL_RMGT1
+3.3V_DUAL_RMGT2

+V_DUAL_RMGT1
+V_DUAL_RMGT2

RGMII_TXD0
RGMII_TXD1
RGMII_TXD2
RGMII_TXD3

RGMII_TXC/MII_TXCLK

RGMII_TXCTL/MII_TXEN

RGMII_MDC

RGMII_MDIO

RGMII_PWRDWN/GPIO_37

BUF_25MHZ

MII_RESET#

+V_RGB_DAC

+V_TV_DAC

DDC_DATA0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC

RGB ONLY

RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44
TV_DAC_VSYNC/GPIO_45

IFPA_TXC_P
IFPA_TXC_N

IFPA_TXD0_P
IFPA_TXD0_N
IFPA_TXD1_P
IFPA_TXD1_N
IFPA_TXD2_P
IFPA_TXD2_N
IFPA_TXD3_P
IFPA_TXD3_N

IFPB_TXC_P
IFPB_TXC_N

IFPB_TXD4_P
IFPB_TXD4_N
IFPB_TXD5_P
IFPB_TXD5_N
IFPB_TXD6_P
IFPB_TXD6_N
IFPB_TXD7_P
IFPB_TXD7_N

FLAT PANEL

DDC_CLK2/GPIO_23

DDC_DATA2/GPIO_24

DDC_DATA3

IFPAB_RSET

IFPAB_VPROBE

4

=PP3V3_ENET_MCP_RMGT

=PP1V05_ENET_MCP_RMGT

131 mA (A01)

MCP_MII_VREF
ENET_TXD<0>

ENET_TXD<1>
ENET_TXD<2>
ENET_TXD<3>

ENET_CLK125M_TXCLK
ENET_TX_CTRL

ENET_MDC
ENET_MDIO

TP_ENET_PWRDWN_L

MCP_CLK25M_BUF0_R

ENET_RESET_L

PP3V3_S0_MCP_DAC
103 mA
103 mA

MCP_DDC_CLK0
MCP_DDC_DATA0

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC
TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB

CRT_IG_HSYNC
CRT_IG_VSYNC

LVDS_IG_A_CLK_P
LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_P<0>
LVDS_IG_A_DATA_N<0>
LVDS_IG_A_DATA_P<1>
LVDS_IG_A_DATA_N<1>
LVDS_IG_A_DATA_P<2>
LVDS_IG_A_DATA_N<2>
LVDS_IG_A_DATA_P<3>
LVDS_IG_A_DATA_N<3>

LVDS_IG_B_CLK_P
LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<0>
LVDS_IG_B_DATA_N<0>
LVDS_IG_B_DATA_P<1>
LVDS_IG_B_DATA_N<1>
LVDS_IG_B_DATA_P<2>
LVDS_IG_B_DATA_N<2>
LVDS_IG_B_DATA_P<3>
LVDS_IG_B_DATA_N<3>

LVDS_IG_DDC_CLK
LVDS_IG_DDC_DATA

=MCP_HDMI_DDC_CLK
=MCP_HDMI_DDC_DATA

MCP_IFPAB_RSET
MCP_IFPAB_VPROBE

1

R1850

10K

5%
1/16W
MF-LF
402

2

206 mA (A01)

3

24

18

8

83 mA (A01)

24

8

24

IN

33 91

OUT

33 91

OUT

33 91

OUT

33 91

OUT

33 91

OUT

33 91

OUT

33 91

OUT

BI

34 91

OUT

33 91

OUT

25

25

25

25

25

25

25 89

OUT

25 89

OUT

25 89

OUT

25 89

OUT

25 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

9

OUT

9

OUT

9

OUT

9

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

83 89

OUT

9

OUT

9

OUT

80

OUT

BI

9

OUT

BI

25 89

OUT

25 89

OUT

3

2 1

Network Interface Select

Interface

RGMII

NOTE: All Apple products set strap to
MII, RGMII products will enable

33 91

1

R1860

100K

5%
1/16W
MF-LF

402

2

89

89

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

89

89

89

89

80

9

feature via software. This
avoids a leakage issue since
MCP79 requires a S5 pull-up.

=PP3V3_S0_MCP_GPIO

1

R1861

100K

5%
1/16W
MF-LF
402

2

RGB DAC Disable:
Okay to float all RGB_DAC signals.

DDC_CLK0/DDC_DATA0 pull-ups still required.

TV DAC Disable:
Okay to float all TV_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.
DDC_CLK0/DDC_DATA0 pull-ups still required.

MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

2

MII

SIZE

SCALE

19

8

D

NONE

ENET_TXD<0>

21

DRAWING NUMBER

051-7546

SHT

1
0

SYNC_DATE=06/18/2008

REV.

A.0.0

OF

18 96

1

D

C

B

A

8 7

6

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

Int PU

(7 OF 11)

PCI_GNT2#/GPIO_41/RS232_DTR#
PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_PERR#/GPIO_43/RS232_DCD#

LPC_PWRDWN#/GPIO_54/EXT_NMI#

LPC PCIGND

PCI_GNT0#

PCI_GNT1#/FANCTL2

PCI_CBE0#
PCI_CBE1#
PCI_CBE2#
PCI_CBE3#

PCI_DEVSEL#

PCI_FRAME#

PCI_IRDY#

PCI_SERR#
PCI_STOP#

PCI_PME#/GPIO_30

Int PU (S5)

PCI_RESET0#
PCI_RESET1#

PCI_CLK0
PCI_CLK1
PCI_CLK2

PCI_CLKIN

LPC_FRAME#

LPC_RESET0#

LPC_CLK0

PCI_REQ0_L

90

19

PCI_REQ1_L

90

19

CRTMUX_SEL_TV_L

19

OUT

AUD_IPHS_SWITCH_EN

9

59

OUT

MCP_RS232_SIN_L

19

IN

D

C

13 90

BI

13 90

BI

13 90

BI

13 90

BI

13 90

BI

13 90

BI

13 90

BI

13 90

BI

MCP_DEBUG<0>
MCP_DEBUG<1>
MCP_DEBUG<2>
MCP_DEBUG<3>
MCP_DEBUG<4>
MCP_DEBUG<5>
MCP_DEBUG<6>
MCP_DEBUG<7>
TP_PCI_AD<8>
TP_PCI_AD<9>
TP_PCI_AD<10>
TP_PCI_AD<11>
TP_PCI_AD<12>
TP_PCI_AD<13>
TP_PCI_AD<14>
TP_PCI_AD<15>
TP_PCI_AD<16>
TP_PCI_AD<17>
TP_PCI_AD<18>
TP_PCI_AD<19>
TP_PCI_AD<20>
TP_PCI_AD<21>
TP_PCI_AD<22>
TP_PCI_AD<23>
TP_PCI_AD<24>
TP_PCI_AD<25>
TP_PCI_AD<26>
TP_PCI_AD<27>
TP_PCI_AD<28>
TP_PCI_AD<29>
TP_PCI_AD<30>
TP_PCI_AD<31>

TP_PCI_INTW_L
TP_PCI_INTX_L
TP_PCI_INTY_L
TP_PCI_INTZ_L

TP_PCI_TRDY_L

PM_CLKRUN_L

42 44

IN

FW_PME_L

36

IN

TP_LPC_DRQ0_L
LPC_SERIRQ

42 44 26 90

BI

B

A

T2

PCI_REQ0#

V9

PCI_REQ1#/FANRPM2

T3

PCI_REQ2#/GPIO_40/RS232_DSR#

U9

PCI_REQ3#/GPIO_38/RS232_CTS#

T4

PCI_REQ4#/GPIO_52/RS232_SIN#

AC3

PCI_AD0

AE10

PCI_AD1

AC4

PCI_AD2

AE11

PCI_AD3

AB3

PCI_AD4

AC6

PCI_AD5

AB2

PCI_AD6

AC7

PCI_AD7

AC8

PCI_AD8

AA2

PCI_AD9

AC9

PCI_AD10

AC10

PCI_AD11

AC11

PCI_AD12

AA1

PCI_AD13

AA5

PCI_AD14

Y5

PCI_AD15

W3

PCI_AD16

W6

PCI_AD17

W4

PCI_AD18

W7

PCI_AD19

V3

PCI_AD20

W8

PCI_AD21

V2

PCI_AD22

W9

PCI_AD23

U3

PCI_AD24

W11

PCI_AD25

U2

PCI_AD26

U5

PCI_AD27

U1

PCI_AD28

U6

PCI_AD29

T5

PCI_AD30

U7

PCI_AD31

P2

PCI_INTW#

N3

PCI_INTX#

N2

PCI_INTY#

N1

PCI_INTZ#

Y3

PCI_TRDY#

AD11

PCI_CLKRUN#/GPIO_42

AE2

LPC_DRQ1#/GPIO_19

AE1
AE6

U24
U26
U39

V16
V17
V18
V20
V22
V24
V26
V27
V28
V33
V37

V40

W20
W22
W24
W36
W40
W43
Y16
Y17
Y18
Y19
Y20
Y22
Y24
Y25

U4
U8

V4

V7

LPC_DRQ0#
LPC_SERIRQ

GND65
GND66
GND67
GND68
GND69
GND70
GND71
GND72
GND73
GND74
GND75
GND76
GND77
GND78
GND79
GND80
GND81
GND82
GND83
GND84
GND85
GND86
GND87
GND88
GND89
GND90
GND91
GND92
GND93
GND94
GND95
GND96
GND97

Int PU
Int PU

PCI_PAR

LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3

GND98

GND99
GND100
GND101
GND102
GND103
GND104
GND105
GND106
GND107
GND108
GND109
GND110
GND111
GND112
GND113
GND114
GND115
GND116
GND117
GND118
GND119
GND120
GND121
GND122
GND123
GND124
GND125
GND126
GND127
GND128
GND129
GND130

R3
U10
R4
U11
P3

AA3
AA6
AA11
W10

AA9
Y4
AA10
Y1
AB9
AA7
Y2

T1

R10
R11

R6
R7
R8

R9

AD4
AE12

AE5

AD3
AD2
AD1
AD5

AE9

Y26
Y27
AB18
H34
AB20
AB21
AB23
AB24
AB25
AB26
AB27
AB28
AB34
AB37
AB4
AB40
AC22
AC36
AC40
AB33
AC5
AD16
AD17
AD18
AD19
AD20
AD24
AD25
AD26
AD27
AD28
AD33
AD34

TP_PCI_GNT0_L
TP_PCI_GNT1_L
GMUX_JTAG_TMS
GMUX_JTAG_TDI
MCP_RS232_SOUT_L

TP_PCI_C_BE_L<0>
TP_PCI_C_BE_L<1>
TP_PCI_C_BE_L<2>
TP_PCI_C_BE_L<3>

TP_PCI_DEVSEL_L
TP_PCI_FRAME_L
TP_PCI_IRDY_L
TP_PCI_PAR
TP_PCI_PERR_L
TP_PCI_SERR_L
TP_PCI_STOP_L

PM_LATRIGGER_L

MEM_VTT_EN_R
TP_PCI_RESET1_L

TP_PCI_CLK0
TP_PCI_CLK1
PCI_CLK33M_MCP_R

90

PCI_CLK33M_MCP

90

LPC_FRAME_R_L

44

LPC_PWRDWN_L

9

OUT

9

OUT

19

OUT

13 23

OUT

26

OUT

1

R1910

22

5%
1/16W
MF-LF
402

2

PLACEMENT_NOTE=Place close to pin R8

R1960

22

1 2

LPC_RESET_L

LPC_AD_R<0>
LPC_AD_R<1>
LPC_AD_R<2>
LPC_AD_R<3>

R1950
R1951
R1952
R1953

22
22

1 2
1 2
1 2
1 2

LPC_CLK33M_SMC_R

1

R1961

10K

5%
1/16W
MF-LF
402

2

Strap for Boot ROM Selection (See HDA_SDOUT)

1/16W MF-LF

5%

5%

1/16W MF-LF22402

5%

1/16W MF-LF22402

5%

1/16W MF-LF

5%

LPC_FRAME_L

402

LPC_AD<0>
LPC_AD<1>
LPC_AD<2>

402

LPC_AD<3>

402

MF-LF1/16W

OUT
OUT

OUT

BI
BI
BI
BI

OUT

42 44 83 90

42 44

26 83 90

42 44 83 90

42 44 83 90

42 44 83 90

42 44 83 90

MCP_RS232_SOUT_L

19

PCI_REQ0_L

90

19

PCI_REQ1_L

90

19

CRTMUX_SEL_TV_L

19

MCP_RS232_SIN_L

19

R1989
R1990

R1991
R1992
R1994

SYNC_MASTER=T18_MLB

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

APPLE INC.

8.2K

8.2K

8.2K

8.2K

8.2K

MCP PCI & LPC

NOTICE OF PROPRIETARY PROPERTY

SIZE

SCALE

=PP3V3_S0_MCP_GPIO

21 18

8

1 2

1 2
1 2
1 2
1 2

DRAWING NUMBER

D

NONE

5%

5%
5%
5%
5%

MF-LF1/16W

MF-LF1/16W
MF-LF1/16W

1/16W MF-LF

MF-LF1/16W

SYNC_DATE=06/18/2008

051-7546

SHT

OF

9619

REV.

402

402
402
402
402

A.0.0

D

C

B

A

8

7 6

5

4

3

2

1

8 7

6

39 89

OUT

39 89

OUT

39 89

IN

39 89

IN

D

39 89

OUT

39 89

OUT

39 89

IN

39 89

IN

C

24

84 mA (A01)

8

43 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

9

B

8

127 mA (A01, AVDD0 & 1)

Minimum 1.025V for Gen2 support

9

89

1

2

A

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

SATA_HDD_R2D_C_P
SATA_HDD_R2D_C_N

SATA_HDD_D2R_N
SATA_HDD_D2R_P

SATA_ODD_R2D_C_P
SATA_ODD_R2D_C_N

SATA_ODD_D2R_N
SATA_ODD_D2R_P

TP_SATA_C_R2D_CP
TP_SATA_C_R2D_CN

TP_SATA_C_D2RN
TP_SATA_C_D2RP

TP_SATA_D_R2D_CP
TP_SATA_D_R2D_CN

TP_SATA_D_D2RN
TP_SATA_D_D2RP

TP_SATA_E_R2D_CP
TP_SATA_E_R2D_CN

TP_SATA_E_D2RN
TP_SATA_E_D2RP

TP_SATA_F_R2D_CP
TP_SATA_F_R2D_CN

TP_SATA_F_D2RN
TP_SATA_F_D2RP

TP_MCP_SATALED_L

PP1V05_S0_MCP_PLL_SATA

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_AVDD1

MCP_SATA_TERMP

R2010

2.49K

1%
1/16W
MF-LF
402

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.
If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

AJ7
AJ6

AJ5
AJ4

AJ11
AJ10

AJ9
AK9

AK2
AJ3

AJ2
AJ1

AM4
AL3

AL4
AK3

AN1
AM1

AM2
AM3

AP3
AP2

AN3
AN2

E12

AE16

AF19
AG16
AG17
AG19

AH17
AH19

AJ12
AN11
AK12
AK13
AL12
AM11
AM12
AN12
AL13

AN14
AL14
AM13
AM14

AE3

5

SATA_A0_TX_P
SATA_A0_TX_N

SATA_A0_RX_N
SATA_A0_RX_P

SATA_A1_TX_P
SATA_A1_TX_N

SATA_A1_RX_N
SATA_A1_RX_P

SATA_B0_TX_P
SATA_B0_TX_N

SATA_B0_RX_N
SATA_B0_RX_P

SATA_B1_TX_P
SATA_B1_TX_N

SATA_B1_RX_N
SATA_B1_RX_P

SATA_C0_TX_P
SATA_C0_TX_N

SATA_C0_RX_N
SATA_C0_RX_P

SATA_C1_TX_P
SATA_C1_TX_N

SATA_C1_RX_N
SATA_C1_RX_P

SATA_LED#

+V_PLL_SATA

+DVDD0_SATA1
+DVDD0_SATA2
+DVDD0_SATA3
+DVDD0_SATA4

+DVDD1_SATA1
+DVDD1_SATA2

+AVDD0_SATA1
+AVDD0_SATA2
+AVDD0_SATA3
+AVDD0_SATA4
+AVDD0_SATA5
+AVDD0_SATA6
+AVDD0_SATA7
+AVDD0_SATA8
+AVDD0_SATA9

+AVDD1_SATA1
+AVDD1_SATA2
+AVDD1_SATA3
+AVDD1_SATA4

SATA_TERMP

5

OMIT

U1400

MCP79-TOPO-B

BGA

(8 OF 11)

SATA

USB_OC2#/GPIO_27/MGPIO
USB_OC3#/GPIO_28/MGPIO

USB

USB_OC0#/GPIO_25
USB_OC1#/GPIO_26

USB_RBIAS_GND

4

USB0_P
USB0_N

USB1_P
USB1_N

USB2_P
USB2_N

USB3_P
USB3_N

USB4_P
USB4_N

USB5_P
USB5_N

USB6_P
USB6_N

USB7_P
USB7_N

USB8_P
USB8_N

USB9_P
USB9_N

USB10_P
USB10_N

USB11_P
USB11_N

+V_PLL_USB

GND131
GND132
GND133
GND134
GND135
GND136
GND137
GND138
GND139
GND140
GND141
GND142
GND143
GND144
GND145
GND146
GND147
GND148
GND149
GND150
GND151
GND152
GND153
GND154
GND155
GND156
GND157
GND158
GND159
GND160

4

External A

C29
D29

C28
D28

A28
B28

F29
G29

K27
L27

J26
J27

F27
G27

D27
E27

K25
L25

H25
J25

F25
G25

K23
L23

L21
K21
J21
H21

L28

A27

AD35
AD37
AD38
AE22
AE24
AE39
AE4
AD6
AF16
AF17
AF18
AF20
AF22
AF26
AF27
AF28
AF33
AF34
AF37
AF40
AG18
AG20
AG22
AG26
AG36
AG40
AH18
AH20
AH22
AH24

USB_EXTA_P
USB_EXTA_N

AirPort (PCIe Mini-Card)

USB_MINI_P
USB_MINI_N

External D

USB_EXTD_P
USB_EXTD_N

Camera

USB_CAMERA_P
USB_CAMERA_N

IR

USB_IR_P
USB_IR_N

Geyser Trackpad/Keyboard

USB_TPAD_P
USB_TPAD_N

Bluetooth

USB_BT_P
USB_BT_N

External B

USB_EXTB_P
USB_EXTB_N

ExpressCard

USB_EXCARD_P
USB_EXCARD_N

External C

USB_EXTC_P
USB_EXTC_N

TP_USB_10P
TP_USB_10N

TP_USB_11P
TP_USB_11N

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

90

19 mA (A01)

R2060

1/16W
MF-LF

806

402

3

40 90

BI

40 90

BI

9

90

BI

9

90

BI

9

90

BI

9

90

BI

31 90

BI

31 90

BI

41 90

BI

41 90

BI

50 90

BI

50 90

BI

31 90

BI

31 90

BI

40 90

BI

40 90

BI

32 90

BI

32 90

BI

9

90

BI

9

90

BI

R2050

8.2K

1/16W
MF-LF

24

1

1%

2

1

R2051

8.2K

5%
1/16W
MF-LF
402

2

1

R2052

8.2K

5%

402

2

1/16W
MF-LF

5%

402

2 1

=PP3V3_S5_MCP_GPIO

1

R2053

8.2K

5%
1/16W
MF-LF
402

2

1

2

USB_EXTA_OC_L
USB_EXTB_OC_L
USB_EXTC_OC_L
EXCARD_OC_L

18

8

40

IN

40

IN
IN

32 43

IN

D

C

B

MCP SATA & USB

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

20 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

(9 OF 11)

D

54 90

IN

HDA_SDIN0

TP_MLB_RAM_SIZE

=PP3V3R1V5_S0_MCP_HDA

24

8

21

1

R2110

49.9

1%
1/16W
MF-LF
402

2

PP3V3_G3_RTC

22

26

1

1

R2120

C

49.9K

1/16W
MF-LF

R2121

49.9K

1%

1%

1/16W
MF-LF
402

402

2

2

TP_MLB_RAM_VENDOR

(MXM_OK for MXM systems)

90

MCP_HDA_PULLDN_COMP

PP1V05_S0_MCP_PLL_NV

24

37 mA (A01)

=SPI_CS1_R_L_USE_MLB

9

44

OUT

SMC_ADAPTER_EN

34 37 42 43

IN

TP_SB_A20GATE
TP_MCP_KBDRSTIN_L
SMC_WAKE_SCI_L

23 42

IN

SMC_RUNTIME_SCI_L

23 42

IN

20 mA
17 mA

SM_INTRUDER_L

TP_MCP_LID_L

23

PM_BATLOW_L

23 42

IN

PM_DPRSLPVR

62 87

IN

PM_PWRBTN_L

23 42

IN

PM_SYSRST_DEBOUNCE_L

23 26

IN

RTC_RST_L

PM_RSMRST_L

42

IN

MCP_PS_PWRGD

26

IN

MCP_CPU_VLD

26 26

IN

JTAG_MCP_TDI

6

13 23

IN

JTAG_MCP_TDO

6

OUT

JTAG_MCP_TMS

6

13 23

IN

JTAG_MCP_TRST_L

6

13

IN

JTAG_MCP_TCK

6

13

B

IN

MCP_CLK25M_XTALIN

26

IN

MCP_CLK25M_XTALOUT

26

OUT

RTC_CLK32K_XTALIN

26

IN

RTC_CLK32K_XTALOUT

26

OUT

R2150

10K

1/16W
MF-LF

1

5%

402

2

G15

HDA_SDATA_IN0

Int PD

J14

HDA_SDATA_IN1/GPIO_2/PS2_KB_CLK

Int PD

J15

HDA_SDATA_IN2/GPIO_3/PS2_KB_DATA

Int PD

A15

HDA_PULLDN_COMP

AE18

+V_PLL_NV_H

AE17

+V_PLL_SP_SPREF

L24

GPIO_1/PWRDN_OK/SPI_CS1

L26

GPIO_12/SUS_STAT#/ACCLMTR

K13

A20GATE

L13

KBRDRSTIN#

C19

SIO_PME#

C18

EXT_SMI/GPIO_32#

B20

INTRUDER#

M25

LID#

M24

LLB#

M22

CPU_DPRSLPVR

C16

PWRBTN#

D16

RSTBTN#

C20

RTC_RST#

D20

PWRGD_SB

E20

PS_PWRGD

C17 D17

CPU_VLD

E19

JTAG_TDI

F19

JTAG_TDO

J19

JTAG_TMS

J18

JTAG_TRST#

G19

JTAG_TCK

A16

XTALIN

B16

XTALOUT

A19

XTALIN_RTC

B19

XTALOUT_RTC

1

R2151

100K

5%
1/16W
MF-LF
402

2

Int PU
Int PU
Int PU (S5)

Int PU (S5)
Int PU (S5)

Int PU (S5)
Int PU

Int PU

Int PU

Int PU (S5)

HDA

HDA_DOCK_EN#/GPIO_4/PS2_MS_CLK

HDA_DOCK_RST#/GPIO_5/PS2_MS_DATA

(MGPIO2)

MISC

(MGPIO3)

+V_DUAL_HDA1
+V_DUAL_HDA2

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET#

SLP_RMGT#

THERM_DIODE_P
THERM_DIODE_N

MCP_VID0/GPIO_13
MCP_VID1/GPIO_14
MCP_VID2/GPIO_15

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT#/GPIO_64

FANRPM0/GPIO_60
FANCTL0/GPIO_61
FANRPM1/GPIO_63
FANCTL1/GPIO_62

CPUVDD_EN

SPI_CS0/GPIO_10
SPI_CLK/GPIO_11

SPI_DI/GPIO_8
SPI_DO/GPIO_9

SUS_CLK/GPIO_34

BUF_SIO_CLK

TEST_MODE_EN

HDA_SYNC

SLP_S3#

SLP_S5#

SPKR

SMB_CLK0

PKG_TEST

J16
K16

F15

E15

K15

L15

K17
L17

G17
J17
H17

B11
C11

L20
M20
M21

C13

L19
K19
G21
F21
M23

B12
A12
D12
C12

C14
D13
C15
B14

B18
AE7

K22
L22

=PP3V3R1V5_S0_MCP_HDA

1

R2160

8.2K

5%
1/16W
MF-LF
402

2

21

HDA_SDOUT_R

90

21

HDA_BIT_CLK_R

90

HDA_RST_R_L

21

90

HDA_SYNC_R

21

90

MCP_GPIO_4
AUD_I2C_INT_L

PM_SLP_S3_L
PM_SLP_RMGT_L
PM_SLP_S4_L

MCP_THMDIODE_P
MCP_THMDIODE_N

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

MCP_SPKR

SMBUS_MCP_0_CLK
SMBUS_MCP_0_DATA
SMBUS_MCP_1_CLK
SMBUS_MCP_1_DATA
AP_PWR_EN

MEM_EVENT_L
ODD_PWR_EN_L
SMC_IG_THROTTLE_L
ARB_DETECT

MCP_CPUVDD_EN

SPI_CS0_R_L
SPI_CLK_R
SPI_MISO
SPI_MOSI_R

PM_CLK32K_SUSCLK_R
TP_MCP_BUF_SIO_CLK

MCP_TEST_MODE_EN

1

R2163

10K

5%
1/16W
MF-LF
402

2

24

21

8

7 mA (A01)

R2171

22

1 2

5%
1/16W
MF-LF

402

R2173

22

1 2

5%
1/16W
MF-LF

402

21

IN

OUT
OUT
OUT

OUT
OUT

OUT
OUT
OUT

OUT

BI

OUT

BI

OUT

IN

OUT

IN

21

OUT

OUT
OUT

IN

OUT

OUT

1

2

R2170

22

1 2

5%
1/16W
MF-LF

402

R2172

22

1 2

5%
1/16W
MF-LF

402

21 59

7

34 37 42 44 68 81 83

9

40 42 43 68

48 95

48 95

21 65

21 65

21 65

7

13 45 90

7

13 45 90

45 90

45 90

21 31 34

21 28 29 42

39

21 43

44 90

44 90

44 90

44 90

26 90

R2190

1K

1%
1/16W
MF-LF
402

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

HDA_SYNC

BOOT_MODE_SAFE

1

R2180

10K

2

54 90

OUT

9

90

OUT

54 90

OUT

54 90

OUT

=PP3V3_S0_MCP

5%
1/16W
MF-LF
402

9

OUT

BOOT_MODE_USER

1

R2181

10K

USER mode: Normal

5%
1/16W

SAFE mode: For ROMSIP

MF-LF
402

2

recovery
Connects to SMC for

automatic recovery.

D

BIOS Boot Select

I/F HDA_SDOUT
LPC

PCI
SPI0
SPI1

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L
R1961 and R2160 selects SPI0 ROM by

default, LPC+ debug card pulls
LPC_FRAME# high for SPI1 ROM override.

NOTE: MCP79 does not support FWH, only
LPC ROMs. So Apple designs will
not use LPC for BootROM override.

NOTE: MCP79 rev A01 does not support

24

8

22

SPI1 option. Rev B01 will.

0
0
1
1

BUF_SIO_CLK Frequency

Frequency

24 MHz

14.31818 MHz

LPC_FRAME#

0
1
0
1

C

HDA_SYNC

1
0

SPI Frequency Select

0
0
1
1

SPI_CLK

0
1
0
1

Frequency

SPI_DO
31 MHz
42 MHz
25 MHz

1 MHz

NOTE: Straps not provided on this page.

B

HDA Output Caps

For EMI Reduction on HDA interface

HDA_SDOUT_R
HDA_BIT_CLK_R

HDA_RST_R_L
HDA_SYNC_R

A

10PF

CERM

5%

50V

2

402

1

2

1

C2170

C2172

10PF

CERM

C2171

10PF

5%
50V
CERM
402

1

5%

50V

2

402

1

C2173

10PF

5%
50V

2

CERM
402

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

21

90

21

90

21

90

21

90

7 6

1

R2140

5%
1/16W
MF-LF
402

2

1

R2141

10K

5%
1/16W
MF-LF
402

2

1

R2142

10K

5%
1/16W
MF-LF
402

2

=PP3V3_S0_MCP_GPIO

1

R2143

10K10K

5%
1/16W
MF-LF
402

2

MCP_GPIO_4
AUD_I2C_INT_L
MEM_EVENT_L
SMC_IG_THROTTLE_L

ARB_DETECT

1

R2147

100K

5%
1/16W
MF-LF
402

2

5

19

8

18

21

21

59

42

29

21

28

21

43

21

1

R2155

22K

5%
1/16W
MF-LF

2

1

R2156

22K

5%
1/16W
MF-LF
402402

2

4

=PP3V3_S3_MCP_GPIO

2

R2154

100K

5%
1/16W
MF-LF
402

1

AP_PWR_EN

MCP_VID<0>
MCP_VID<1>
MCP_VID<2>

1

R2157

22K

5%
1/16W
MF-LF
402

2

21

21

21

21

3

8

34

31

65

65

65

SYNC_MASTER=T18_MLB

APPLE INC.

2

MCP HDA & MISC

SYNC_DATE=06/18/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

21 96

1

A

REV.

A.0.0

OF

8 7

6

5

4

3

2 1

OMIT

U1400

MCP79-TOPO-B

BGA

AH26
AH33
AH34
AH37
AH38
AJ39

D

C

B

A

AK10
AK33
AK34
AK37

AK40
AL36
AL40

AM10
AM16
AM18
AM20
AM22
AM24
AM26
AM30
AM34
AM35
AM37
AM38

AP26
AN28
AN30
AN39

AP10
AU26
AP14
AU14
AP28
AP32
AP34
AP36
AP37

AP40

AW23
AR28
AR32
AR40
AT10
AR12
AT13
AT29
AT33

AY21
AY22

AU12
AU28
AP33
AU32
AR30
AU36
AU38

AV28
AV32
AV36

AW11

AR43
AW43
AY10
AV12
AY30
AY33
AY34
AY37
AY38
AY41

(11 OF 11) (10 OF 11)

GND161
GND162
GND163
GND164
GND165
GND166

AJ8

GND167
GND168
GND169
GND170
GND171

AK4

GND172
GND173
GND174
GND175

AL5

GND176
GND177
GND178
GND179
GND180
GND181
GND182
GND183
GND184
GND185
GND186
GND187
GND188

AM5

GND189

AM6

GND190

AM7

GND191

AM9

GND192
GND193
GND194
GND195
GND196

AN4

GND197

Y7

GND198
GND199
GND200
GND201
GND202
GND203
GND204
GND205
GND206
GND207

AP4

GND208
GND209

AP7

GND210
GND211
GND212
GND213
GND214
GND215
GND216
GND217
GND218
GND219

AT6

GND220

AT7

GND221

AT9

GND222
GND223
GND224

L12

GND225
GND226
GND227
GND228
GND229
GND230
GND231
GND232

AU4

GND233

G28

GND234

F20

GND235
GND236
GND237
GND238

AV4

GND239

AV7

GND240
GND241

G20

GND242
GND243
GND244
GND245
GND246
GND247
GND248
GND249
GND250 GND342
GND251
GND252

GND253
GND254
GND255
GND256
GND257
GND258
GND259
GND260
GND261
GND262
GND263
GND264
GND265
GND266
GND267
GND268
GND269
GND270
GND271
GND272
GND273
GND274
GND275
GND276
GND277
GND278
GND279
GND280
GND281
GND282
GND283
GND284
GND285
GND286
GND287
GND288
GND289
GND290
GND291
GND292
GND293
GND294
GND295
GND296
GND297
GND298
GND299
GND300
GND301

GND

GND302
GND303
GND304
GND305
GND306
GND307
GND308
GND309
GND310
GND311
GND312
GND313
GND314
GND315
GND316
GND317
GND318
GND319
GND320
GND321
GND322
GND323
GND324
GND325
GND326
GND327
GND328
GND329
GND330
GND331
GND332
GND333
GND334
GND335
GND336
GND337
GND338
GND339
GND340
GND341

GND343

AV40
BA1
BA4
AW31
AY6
L35
BC33
BC37
BC41
AY14
BC5
C2
D10
D14
D15
D18
D19
D22
D23
D26
D30
D37
D6
E13
E17
E21
E25
E29
E33
F12
F16
F32
F8
G10
G12
G14
G16
BC12
G22
G24
AW20
G34
G4
G43
G6
G8
H11
H15
AW35
H23
AN8
G40
J12
J8
K10
K12
K18
K26
K37
K4
K40
K8
AU1
L40
L43
L5
M10
M34
M35
M37
Y28
Y33
Y34
Y35
Y37
Y38
AB17
AB16
AN26
AD7
M11
AA4
AB19
AY13
P11
Y6
T11
V11
Y11
AH16
T22

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

7 6

=PPVCORE_S0_MCP

24

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

PP3V3_G3_RTC

26

21

10 uA (G3)
80 uA (S0)

OMIT

U1400

MCP79-TOPO-B

BGA

AA25
AC23

U25
AH12
AG10

AG5

Y21

Y23
AA16
AA26
AA27
AA28
AC16
AC17
AC18
AC19
AC20
AC21
AA17
AC24
AC25
AC26
AC27
AC28
AD21
AD23

W27

V25
AA18
AE19
AE21
AE23
AE25
AE26
AE27
AE28
AF10
AF11
AA19

AF2
AF21
AF23
AF25

AF3

AF4

AF7
AH23

AF9
AA20
AG11
AG12
AG21
AG23
AG25

AG3

AG4
AA21

AG6

AG7

AG8

AG9

AH1
AH10
AH11

W26

AH2
AA23

W28
AH25
AH21

AH3

AH4

AH5

AH6

AH7

AH9
AA24

W21

W23

W25
AF12

A20

+VDD_CORE1
+VDD_CORE2
+VDD_CORE3
+VDD_CORE4
+VDD_CORE5
+VDD_CORE6
+VDD_CORE7
+VDD_CORE8
+VDD_CORE9
+VDD_CORE10
+VDD_CORE11
+VDD_CORE12
+VDD_CORE13
+VDD_CORE14
+VDD_CORE15
+VDD_CORE16
+VDD_CORE17
+VDD_CORE18
+VDD_CORE19
+VDD_CORE20
+VDD_CORE21
+VDD_CORE22
+VDD_CORE23
+VDD_CORE24
+VDD_CORE25
+VDD_CORE26
+VDD_CORE27
+VDD_CORE28
+VDD_CORE29
+VDD_CORE30
+VDD_CORE31
+VDD_CORE32
+VDD_CORE33
+VDD_CORE34
+VDD_CORE35
+VDD_CORE36
+VDD_CORE37
+VDD_CORE38
+VDD_CORE39
+VDD_CORE40
+VDD_CORE41
+VDD_CORE42
+VDD_CORE43
+VDD_CORE44
+VDD_CORE45
+VDD_CORE46
+VDD_CORE47
+VDD_CORE48
+VDD_CORE49
+VDD_CORE50
+VDD_CORE51
+VDD_CORE52
+VDD_CORE53
+VDD_CORE54
+VDD_CORE55
+VDD_CORE56
+VDD_CORE57
+VDD_CORE58
+VDD_CORE59
+VDD_CORE60
+VDD_CORE61
+VDD_CORE62
+VDD_CORE63
+VDD_CORE64
+VDD_CORE65
+VDD_CORE66
+VDD_CORE67
+VDD_CORE68
+VDD_CORE69
+VDD_CORE70
+VDD_CORE71
+VDD_CORE72
+VDD_CORE73
+VDD_CORE74
+VDD_CORE75
+VDD_CORE76
+VDD_CORE77
+VDD_CORE78
+VDD_CORE79
+VDD_CORE80
+VDD_CORE81

+VBAT

+VTT_CPU1
+VTT_CPU2
+VTT_CPU3
+VTT_CPU4
+VTT_CPU5
+VTT_CPU6
+VTT_CPU7
+VTT_CPU8

+VTT_CPU9
+VTT_CPU10
+VTT_CPU11
+VTT_CPU12
+VTT_CPU13
+VTT_CPU14
+VTT_CPU15
+VTT_CPU16
+VTT_CPU17
+VTT_CPU18
+VTT_CPU19
+VTT_CPU20
+VTT_CPU21
+VTT_CPU22
+VTT_CPU23
+VTT_CPU24
+VTT_CPU25
+VTT_CPU26
+VTT_CPU27
+VTT_CPU28
+VTT_CPU29
+VTT_CPU30
+VTT_CPU31
+VTT_CPU32
+VTT_CPU33
+VTT_CPU34
+VTT_CPU35
+VTT_CPU36

POWER

+VTT_CPU37
+VTT_CPU38
+VTT_CPU39
+VTT_CPU40
+VTT_CPU41
+VTT_CPU42
+VTT_CPU43
+VTT_CPU44
+VTT_CPU45
+VTT_CPU46
+VTT_CPU47
+VTT_CPU48
+VTT_CPU49
+VTT_CPU50
+VTT_CPU51
+VTT_CPU52

+VTT_CPUCLK

+3.3V_1
+3.3V_2
+3.3V_3
+3.3V_4
+3.3V_5
+3.3V_6
+3.3V_7
+3.3V_8

+3.3V_DUAL1
+3.3V_DUAL2
+3.3V_DUAL3
+3.3V_DUAL4

+3.3V_DUAL_USB1
+3.3V_DUAL_USB2
+3.3V_DUAL_USB3
+3.3V_DUAL_USB4

+VDD_AUXC1
+VDD_AUXC2
+VDD_AUXC3

5

=PP1V05_S0_MCP_FSB

R32

1139 mA

AC32
E40
J36
N32
T32
U32
V32
W32
P31
AF32
AE32
AH32
AJ32
AK31
AK32
AD32
AL31
AB32
B41
B42
C40
C41
C42
D39
D40
D41
E38
E39
F37
F38
F39
G36
G37
G38
H35
H37
J34
J35
K33
K34
K35
L32
L33
L34
M31
M32
M33
N31
P32
Y32
AA32

AG32

43 mA

=PP3V3_S0_MCP

AD10
AE8
AB10
AD9
Y10
AB11
AA8
Y9

=PP3V3_S5_MCP

G18

16 mA

H19
J20
K20

G26

250 mA

H27
J28
K28

=PP1V05_S5_MCP_VDD_AUXC

T21
U21
V21

4

9

8 8

1182 mA (A01)

24

21

8

450 mA (A01)

24

8

266 mA (A01)

24

8

105 mA (A01)

24 14 46

D

C

B

MCP Power & Ground

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

9622

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

D

D

3.3V Interface Pull-ups

These internal pull-ups are missing in Revs A01 & A01P.

=PP3V3_S5_MCP_A01

44

8

MCP_A01&MCP_A01P&MCP_A01Q

PM_LATRIGGER_L

13 19

OUT

PCIE_WAKE_L

17 31 32

OUT

JTAG_MCP_TDI

6

13 21

OUT

JTAG_MCP_TMS

6

13 21

OUT

PM_SYSRST_DEBOUNCE_L

21 26

C

OUT

TP_MCP_LID_L

21

OUT

MCP_LID_L

MAKE_BASE=TRUE

SMC_WAKE_SCI_L

21 42

OUT

SMC_RUNTIME_SCI_L

21 42

OUT

PM_PWRBTN_L

21 42

OUT

PM_BATLOW_L

21 42

OUT

R2400
R2401
R2402
R2403
R2404
R2405

R2410
R2411
R2412
R2413

10K

10K

10K

10K

10K

10K

10K

10K

10K

10K

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

1 2

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

MCP_A01&MCP_A01P&MCP_A01Q

5%

1/16W MF-LF

5%

5%

5%

1/16W MF-LF

5%

1/16W MF-LF

5%

1/16W MF-LF

5%

5%

5%

1/16W MF-LF

5%

1/16W MF-LF

402

402

MF-LF1/16W

402

MF-LF1/16W

402

402

402

402

MF-LF1/16W

402

MF-LF1/16W

402

402

C

B

B

MCP79 A01 Silicon Support

A

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

D

APPLE INC.

8

7 6

5

4

3

2

SCALE

SYNC_DATE=03/31/2008

DRAWING NUMBER

051-7546

SHT

NONE

A

REV.

A.0.0

OF

9623

1

8 7

6

5

4

3

2 1

MCP Core Power

=PPVCORE_S0_MCP

46

22

8

23065 mA (A01, 1.2V)
16996 mA (A01, 1.0V)

(No IG vs. EG data)

D

MCP PCIE (DVDD) Power

=PP1V05_S0_MCP_PEX_DVDD

C2500

C2515

MCP 1.05V AUX Power

=PP1V05_S5_MCP_VDD_AUXC

22 18

8 8

105 mA (A01) 131 mA (A01)

MCP FSB (VTT) Power

=PP1V05_S0_MCP_FSB

22

14

9

8

1182 mA (A01)

C

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)
Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

4.7UF

20%
X5R

402

1

4V

2

C2501

4.7UF

20%
X5R

402

1

C2502

4V

2

4.7UF

20%
X5R

402

1

C2503

4V

2

4.7UF

20%
X5R

402

1

1

C2504

1UF

4V

10%
10V

2

2

X5R
402-1

MCP SATA (DVDD) Power

=PP1V05_S0_MCP_SATA_DVDD

8 8

43 mA (A01)57 mA (A01)

4.7UF

20%
X5R

402

1

1

C2516

1UF

10%

4V

10V

2

2

X5R
402-1

1

C2517

1UF

10%
10V

2

X5R
402-1

1

C2518

0.1uF

20%
10V

2

CERM
402

1

C2519

0.1uF

20%
10V

2

CERM
402

MCP 1.05V RMGT Power

=PP1V05_ENET_MCP_RMGT

1

C2525

0.1uF

20%
10V

2

CERM
402

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 7x 2.2uF 0402 (15.4 uF)

1

C2530

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2526

0.1uF

20%
10V

2

CERM
402

1

C2531

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2532

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2533

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2534

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2505

1UF

10%
10V

2

X5R
402-1

1

C2535

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2506

1UF

10%
10V

2

X5R
402-1

C2520

4.7UF

C2528

4.7uF

1

C2536

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2507

1UF

10%
10V

2

X5R
402-1

20%

4V
X5R
402

20%

4V
X5R
402

1

C2508

0.1UF

20%
10V

2

CERM
402

1

1

C2521

0.1uF

20%
10V

2

2

CERM
402

1

1

C2529

0.1uF

20%
10V

2

2

CERM
402

1

C2509

0.1UF

20%
10V

2

CERM
402

1

C2510

0.1UF

20%
10V

2

CERM
402

1

C2511

0.1UF

20%
10V

2

CERM
402

1

C2512

0.1UF

20%
10V

2

CERM
402

=PP1V05_S0_MCP_AVDD_UF

8

333 mA (A01)

=PP1V05_S0_MCP_PLL_UF

8

562 mA (A01)

1

C2513

0.1UF

20%
10V

2

CERM
402

L2570

30-OHM-5A

1 2

0603

L2575

30-OHM-5A

1 2

0603

R2580

0.2

1 2

1%

1/6W

MF

C2580

402-HF

4.7UF

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)
Apple: 5x 2.2uF 0402 (11 uF)

1

C2570

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)
Apple: 2x 2.2uF 0402 (4.4 uF)

1

C2575

2.2UF

20%

6.3V

2

402-LF

1

1

20%

4V

2

X5R
402

2

1

C2571

2.2UF

20%

6.3V

2

CERM
402-LF

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2576

2.2UF

20%

6.3V

2

CERMCERM
402-LF

PP1V05_S0_MCP_PLL_FSB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

C2581

2.2UF

20%

6.3V
CERM
402-LF

1

C2572

2.2UF

20%

6.3V

2

CERM
402-LF

14

270 mA (A01)

1

C2573

2.2UF

20%

6.3V

2

CERM
402-LF

8

127 mA (A01)

PP1V05_S0_MCP_PEX_AVDD

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2574

2.2UF

20%

6.3V

2

CERM
402-LF

8

206 mA (A01)

D

C

MCP Memory Power

=PP1V8R1V5_S0_MCP_MEM

16

8

4771 mA (A01, DDR3)

1

C2553

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2544

0.1UF

20%
10V

2

CERM
402

8

MCP 3.3V Power

=PP3V3_S0_MCP

22

21

8

450 mA (A01)

C2540

4.7UF

1

C2551

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2542

0.1UF

20%
10V

2

CERM
402

1

1

C2541

0.1UF

20%
X5R

402

4V

20%
10V

2

2

CERM
402

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)
Apple: 4x 2.2uF 0402 (8.8 uF)

1

C2550

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2552

2.2UF

20%

6.3V

2

CERM
402-LF

1

C2543

0.1UF

20%
10V

2

CERM
402

B

MCP 3.3V AUX/USB Power

=PP3V3_S5_MCP

22

8

266 mA (A01)

MCP 3.3V/1.5V HDA Power

=PP3V3R1V5_S0_MCP_HDA

21

8

7 mA (A01)

A

=PP1V05_ENET_MCP_PLL_MAC

8

5 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2560

2.2UF

20%

6.3V

2

CERM
402-LF

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

C2562

2.2UF

20%

6.3V

2

CERM
402-LF

L2595

30-OHM-1.7A

1 2

0402

C2595

4.7UF

20%
X5R

402

4V

PP1V05_ENET_MCP_PLL_MAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2596

0.1UF

20%

10V

2

2

CERM

402

7 6

18

5 mA (A01)

1

C2545

0.1UF

20%
10V

2

CERM
402

=PP3V3_S0_MCP_PLL_UF

19 mA (A01)

1

C2546

0.1UF

20%
10V

2

CERM
402

MCP 3.3V Ethernet Power

=PP3V3_ENET_MCP_RMGT

24

18

8

83 mA (A01)

24

18

1

C2547

0.1UF

20%
10V

2

CERM
402

1

C2548

0.1UF

20%
10V

2

CERM
402

L2555

30-OHM-1.7A

1 2

0402

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

2

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: 1x 2.2uF 0402 (2.2 uF)

1

2

MCP79 Ethernet VRef

=PP3V3_ENET_MCP_RMGT

8

1

R2591

1.47K

1%
1/16W
MF-LF

402

2

1

R2590

1.47K

1%
1/16W
MF-LF

402

2

5

1

C2549

0.1UF

20%
10V

2

CERM
402

PP3V3_S0_MCP_PLL_USB

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

C2555

2.2UF

20%

6.3V
CERM
402-LF

C2564

2.2UF

20%

6.3V
CERM
402-LF

MCP_MII_VREF

1

C2591

0.1UF

20%
10V

2

CERM
402

19 mA (A01)

18

OUT

L2582

30-OHM-1.7A

1 2

0402

C2582

4.7UF

20%

4V
X5R
402

L2584

20

30-OHM-1.7A

1 2

0402

C2584

4.7UF

20%
X5R

402

4V

PP1V05_S0_MCP_PLL_PEX

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2583

0.1UF

20%
10V

2

2

CERM
402

PP1V05_S0_MCP_PLL_SATA

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2585

0.1UF

20%
10V

2

2

CERM
402

17

84 mA (A01)

20

84 mA (A01)

B

L2586

30-OHM-1.7A

1 2

0402

C2586

4.7UF

20%

4V
X5R
402

L2588

30-OHM-1.7A

1 2

0402

C2588

4.7UF

20%

4V
X5R
402

4

3

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

1

C2587

0.1UF

20%
10V

2

2

CERM
402

1

1

C2589

0.1UF

20%
10V

2

2

CERM
402

87 mA (A01)

PP1V05_S0_MCP_PLL_NV

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=1.05V

1

C2590

0.1UF

20%
10V

2

CERM
402

SYNC_MASTER=T18_MLB

APPLE INC.

2

16

21

37 mA (A01)

MCP Standard Decoupling

SYNC_DATE=06/18/2008

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

051-7546

SHT

OF

24

96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

=PP3V3R1V8_S0_MCP_IFP_VDD

Apple: 1x 2.2uF 0402 (2.2 uF)

18

8

190 mA (A01, 1.8V)

D

=PP1V05_S0_MCP_HDMI_VDD

18

8

95 mA (A01)

C2615

4.7UF

20%
X5R

402

1

C2610

2.2UF

20%

6.3V

2

CERM
402-LF

1

1

C2616

2.2UF

4V

20%

6.3V

2

2

CERM
402-LF

=PP3V3_S0_MCP_DAC_UF

8

206 mA (A01)

NO STUFF

L2650

30-OHM-1.7A

1 2

0402

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

NO STUFF

1

C2650

2.2UF

20%

6.3V

2

CERM
402-LF

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

R2651

0

5%
1/16W
MF-LF
402

2

18

206 mA (A01)

D

18

18

18

18

MCP_HDMI_RSET

89 89

18

MCP_HDMI_VPROBE

89

18

C

NO STUFF

C2620

0.1UF

20%
10V

CERM

402

1

R2620

1

1K

1%
1/16W
MF-LF
402

2

2

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

L2640

=PP3V3_S0_MCP_VPLL_UF

8

16 mA (A01)

30-OHM-1.7A

1 2

0402

C2640

4.7UF

6.3V
CERM

20%
603

1

2

MCP_IFPAB_RSET

18

MCP_IFPAB_VPROBE

18

89

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)
Apple: ???

PP3V3_S0_MCP_VPLL

MIN_LINE_WIDTH=0.4 MM
MIN_NECK_WIDTH=0.2 MM
VOLTAGE=3.3V

1

C2641

0.1uF

20%
10V

2

CERM
402

NO STUFF

C2630

0.1UF

20%
10V

CERM

402

NO STUFF

1

R2630

1

1K

1%
1/16W
MF-LF
402

2

2

18

16 mA (A01)

18

89

18

89

18

18

89

89

18

89

18

TP_MCP_RGB_DAC_RSET

18

TP_MCP_RGB_DAC_VREF

18

MCP_TV_DAC_RSET

18

89

MCP_TV_DAC_VREF

18

89

MCP_CLK27M_XTALIN

18

MCP_CLK27M_XTALOUT

18

TP_MCP_RGB_RED
TP_MCP_RGB_GREEN
TP_MCP_RGB_BLUE

TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR
CRT_IG_G_Y_Y
CRT_IG_B_COMP_PB

CRT_IG_HSYNC
CRT_IG_VSYNC

B

NC_MCP_RGB_RED

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNCTP_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

MAKE_BASE=TRUE

C

B

HDCP ROM

WF: Open question on which packge option(s) nVidia can support.

=PP3V3_S0_HDCPROM

8

1

C2690

0.1UF

CERM

1

20%
10V

2

402

1
2
3

U2695

AT24C08

A0
A1
A2

VCC

SOIC

GND

8

4

OMIT

SDA
SCL

WP

5
6

7

=I2C_HDCPROM_SDA
=I2C_HDCPROM_SCL

HDCPROM_WP

R2690

10K

1/16W
MF-LF

402

5%

2

A

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

8

7 6

45

BI

45

IN

MCP Graphics Support

SYNC_MASTER=AMASON_M98_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SYNC_DATE=06/18/2008

051-7546

SHT

OF

25 96

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

RTC Power Sources

=PP3V3_S5_RTC_D

8

1

VIN

U2801

MIC5232-2.8YD5

TSOT-23-5

1

10%
10V

2

X5R
402

R2811

10M

1/16W
MF-LF

402

3

GND

2

RTC Crystal

1

5%

2

D

C2802

1UF

RTC_CLK32K_XTALOUT

21

IN

NO STUFF

C

RTC_CLK32K_XTALIN

21

OUT

MCP 25MHz Crystal

MCP_CLK25M_XTALOUT

21

IN

MCP_CLK25M_XTALIN

21

OUT

NO STUFF

R2816

1/16W
MF-LF

402

1

1M

5%

2

VOUTEN

NC

R2810

1 2

R2815

1 2

0

5%
1/16W
MF-LF

402

0

5%
1/16W
MF-LF

402

5

4

RTC_DISCHARGE_R

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

R2801

1/16W
MF-LF

CRITICAL

Y2810

32.768K

7X1.5X1.4-SM

CRITICAL

Y2815

25.0000M

SM-3.2X2.5MM

402

10

5%

1

2

1 4

1 3

C2801

NO STUFF

R2802

1.0M

5%
1/10W
MF-LF

603

NC

2 4

NC

1UF

10%

6.3V
CERM

402

12

C2810

12pF

1 2

5%

50V

CERM

402

C2811

12pF

1 2

5%

50V

CERM

402

C2815

12pF

1 2

5%

50V

CERM

402

C2816

12pF

1 2

5%

50V

CERM

402

1

R2800

100

5%
1/16W
MF-LF

1

402

2

PP3V3_G3_SUPERCAP

2

1

C2800

0.08F

2%

3.3V

2

XHHG
SM

PP3V3_G3_RTC

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm
VOLTAGE=3.3V

22 8 21

19 83 90

IN

9

17

IN

19

IN

19 90

IN

LPC_RESET_L

PCIE_RESET_L

MEM_VTT_EN_R

LPC_CLK33M_SMC_R

MCP S0 PWRGD & CPU_VLD

=PP3V3_S5_MCPPWRGD

B

ALL_SYS_PWRGD

42 68

IN

VR_PWRGOOD_DELAY

62

IN

MCP_CPUVDD_EN

21

IN

A

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,
but results in MCP79 ROMSIP sequence happening after CPU powers up.

MCPSEQ_MIX is cross between MLB and internal power sequencing, which
results in earlier ROMSIP and MCP FSB I/O interface initialization.

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for
VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before
CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

U2850

MCPSEQ_SMC

1

C2850

0.1UF

20%
10V

2

CERM
402

TC7SZ08AFEAPE

SOT665

A

B

S0_AND_IMVP_PGOOD

MCPSEQ_SMC

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_MIX

R2851

0

1 2

5%
1/16W
MF-LF

402

MCPSEQ_SMC

R2853

0

1 2

5%
1/16W
MF-LF

402

MCPSEQ_MIX

R2852

0

1 2

5%
1/16W
MF-LF

402

MCPSEQ_SMC

R2850

0

1 2

5%
1/16W
MF-LF

402

MCP_PS_PWRGD

MCP_CPU_VLD

PM_CLK32K_SUSCLK_R

21 90

IN

21

OUTY

21

OUT

PM_SYSRST_L

42

IN

XDP_DBRESET_L

10 13 21 23

IN

Reset Button

XDP

R2896

0

1 2

5%
1/16W
MF-LF

402

R2897

SILK_PART=FP SYS RESET

Platform Reset Connections

LPC Reset (Unbuffered)

R2881

33

1 2

5%
1/16W
MF-LF

402

R2890

0

1 2

5%
1/16W
MF-LF

402

R2893

0

1 2

5%
1/16W
MF-LF

402

R2895

1 2

1/16W
MF-LF

R2825

33

1 2

5%
1/16W
MF-LF

402

R2827

33

1 2

5%
1/16W
MF-LF

402

R2829

22

1 2

5%
1/16W
MF-LF

402

OUT

OMIT

1/16W
MF-LF

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

PCIE Reset (Unbuffered)

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

PLACEMENT_NOTE=Place close to U1400

R2899

1 2

1

0

5%

402

2

10K pull-up to 3.3V S0 inside MCP

33

5%
1/16W
MF-LF

402

PM_SYSRST_DEBOUNCE_L

NO STUFF

1

C2899

1UF

10%
10V

2

X5R
402

R2883

1 2

1/16W
MF-LF

R2892

1 2

1/16W
MF-LF

GMUX_PCIE_RESET_L

R2891

1 2

1/16W
MF-LF

BKLT_PLT_RST_L

R2894

1 2

0

EXCARD_RESET_L

5%

402

R2870

33

1 2

5%
1/16W
MF-LF

402

R2826

1 2

1/16W
MF-LF

APPLE INC.

DEBUG_RESET_L

33

SMC_LRESET_L

5%

402

0

FW_RESET_L

5%

402

MAKE_BASE=TRUE

=GMUX_PCIE_RESET_L

0

PCA9557D_RESET_L

5%

402

0

MINI_RESET_L

5%
1/16W
MF-LF

402

MEM_VTT_EN

LPC_CLK33M_SMC

33

LPC_CLK33M_LPCPLUS

5%

PLACEMENT_NOTE=Place close to U1400

402

LPC_CLK33M_GMUX

PM_CLK32K_SUSCLK

SB Misc

SYNC_MASTER=T18_MLB

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

SCALE

NONE

44

OUT

42

OUT

36

OUT

83

OUT

27

OUT

85

OUT

31

OUT

32

OUT

9

OUT

42 90

OUT

44 90

OUT

83

OUT

42 90

OUT

SYNC_DATE=12/17/2007

051-7546

SHT

OF

26

96

D

C

B

A

REV.

A.0.0

8

7 6

5

4

3

2

1

8 7

Page Notes

Power aliases required by this page:

- =PP3V3_S3_VREFMRGN

- =PP3V3_S5_VREFMRGN

- =PPVTT_S3_DDR_BUF

Signal aliases required by this page:

- =I2C_VREFDACS_SCL

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SCL

- =I2C_PCA9557D_SDA

BOM options provided by this page:

D

VREFMRGN
NO_VREFMRGN

C

B

=PP3V3_S3_VREFMRGN

8

ADDR=0x30(WR)/0x31(RD)

=I2C_PCA9557D_SCL

45

IN

=I2C_PCA9557D_SDA

45

BI

DAC channel A B A B C D
Min DAC code 0x00 0x00 0x00 0x00 0x00 0x00
Max DAC code 0x87 0x87 0x87 0x87 0x55 0xFF
Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA -59.04 mA
Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA 51.15 mA
Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V 1.248 V
Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V 1.042 V
Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V 1.426 V
Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV 1.5 mV
(per DAC LSB)

VREFMRGN

1

C2900

2.2UF

20%

6.3V

2

CERM
402-LF

IN

BI

=I2C_VREFDACS_SCL
=I2C_VREFDACS_SDA

45

45

ADDR=0x98(WR)/0x99(RD)

1

2

VREFMRGN

1

C2901

0.1UF

20%

10V

2

CERM

402

VREFMRGN

C2902

0.1UF

20%
10V
CERM
402

6

7

9

10

3
4
5

1
2

SCL

SDA

A0

A1

PCA9557

A0
A1
A2

SCL
SDA

THRM

PAD

17

VREFMRGN

U2900

8
VDD

MSOP

DAC5574

GND

3

16

VCC

U2901

QFN

GND

8

VOUTA

VOUTB

VOUTC

VOUTD

VREFMRGN

P0
P1
P2
P3
P4
P5
P6
P7

RESET*

6

MEM A VREF CA

1

VREFMRGN_DQ_SODIMM

2

VREFMRGN_CA_SODIMM

4

VREFMRGN_CPUFSB

5

VREFMRGN_FRAMEBUF

6

NC

7
9
10
11
12
13
14

NC

15

MEM B VREF DQMEM A VREF DQ

VREFMRGN_CPUFSB_EN
VREFMRGN_CA_SODIMMA_EN
VREFMRGN_DQ_SODIMMA_EN
VREFMRGN_CA_SODIMMB_EN
VREFMRGN_DQ_SODIMMB_EN
VREFMRGN_FRAMEBUF_EN

PCA9557D_RESET_L

5

MEM B VREF CA

CPU FSB VREF

4

FRAME BUFFER VREF

3

2 1

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

=PPVTT_S3_DDR_BUF

64

8

10mA max load

R2903

1 2

B1

VREFMRGN

1

C2903

0.1UF

20%
10V

2

CERM
402

VREFMRGN

1

C2904

0.1UF

20%
10V

2

CERM
402

VREFMRGN

1

C2905

0.1UF

20%
10V

2

CERM
402

27

27

27

27

27

27

26

IN

A2

A3

C2

C3

A2

A3

C2

C3

A2

A3

C2

C3

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

B1

V+

VREFMRGN

V-

B4

U2902

MAX4253

UCSP

A1

A4

U2902

MAX4253

UCSP

C1

C4

U2903

MAX4253

UCSP

A1

A4

U2903

MAX4253

UCSP

C1

C4

U2904

MAX4253

UCSP

A1

A4

U2904

MAX4253

UCSP

C1

C4

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_DQ_SODIMMA_EN

27

R2901

VREFMRGN_DQ_SODIMMB_BUF

VREFMRGN_DQ_SODIMMB_EN

27

R2902

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_EN

27

R2907

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMB_EN

27

R2908

VREFMRGN_FRAMEBUF_BUF

VREFMRGN_FRAMEBUF_EN

27

R2915

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB_EN

27

R2913

100K

1/16W
MF-LF

100K

1/16W
MF-LF

100K

1/16W
MF-LF

100K

1/16W
MF-LF

100K

1/16W
MF-LF

100K

1/16W
MF-LF

R2904

1 2

R2905

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

VREFMRGN

5%

1 2

402

1 2

R2906

1 2

R2909

1 2

R2910

1 2

R2911

1 2

R2912

1 2

R2916

1 2

R2917

1 2

R2914

1 2

VREFMRGN

200

1%
1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to J3100.1

1/16W
MF-LF

402

VREFMRGN

200

1%
1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to J3200.1

1/16W
MF-LF

402

VREFMRGN

200

1%
1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to J3100.126

1/16W
MF-LF

402

VREFMRGN

200

1%
1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to J3200.126

1/16W
MF-LF

402

VREFMRGN

49.9

1%

Place close to U8400, U8450

1/16W
MF-LF

402

VREFMRGN

49.9

1%

Place close to U8500, U8550

1/16W
MF-LF

402

VREFMRGN

100

1%

Place close to U1000.AD26

1/16W
MF-LF

402

PP0V75_S3_MEM_VREFDQ_A

PP0V75_S3_MEM_VREFDQ_B

PP0V75_S3_MEM_VREFCA_A

PP0V75_S3_MEM_VREFCA_B

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.3 mm
MIN_NECK_WIDTH=0.2 mm

GPU_FB_A_VREF_DIV

GPU_FB_B_VREF_DIV

CPU_GTLREF

28

29

28

29

9

OUT

9

OUT

10 87

OUT

D

C

B

A

Required zero ohm resistors when no VREF margining circuit stuffed

PART NUMBER

116S0004
116S0004
116S0004

QTY

1116S0004

1 R2909 CRITICAL

8

DESCRIPTION

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

RES,MTL FILM,0,5%,0402,SM,LF

7 6

REFERENCE DES

R2903 CRITICAL

CRITICAL

CRITICAL1 R2905

CRITICAL1 R2911

BOM OPTION
NO_VREFMRGN
NO_VREFMRGN
NO_VREFMRGN
NO_VREFMRGN

FSB/DDR3/FRAMEBUF Vref Margining

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

DRAWING NUMBER

SIZE

D

APPLE INC.

5

4

3

2

SCALE

NONE

SYNC_DATE=07/22/2008

051-7546

SHT

OF

9627

1

A

REV.

A.0.0

8 7

6

5

4

3

2 1

Page Notes

Power aliases required by this page:

- =PP1V5_S0_MEM_A

- =PP1V5_S3_MEM_A

- =PP0V75_S0_MEM_VTT_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMA_SCL

- =I2C_SODIMMA_SDA

BOM options provided by this page:

D

(NONE)

C

B

8

A

=PPSPD_S0_MEM_A

1

C3140

2

2.2UF

20%

6.3V
CERM
402-LF

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

1

R3140

10K

5%
1/16W
MF-LF
402

2

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

MEM_A_CKE<0>

MEM_A_BA<2>

MEM_A_A<12>
MEM_A_A<9>

MEM_A_A<8>
MEM_A_A<5>

MEM_A_A<3>
MEM_A_A<1>

MEM_A_CLK_P<0>
MEM_A_CLK_N<0>

MEM_A_A<10>
MEM_A_BA<0>

MEM_A_WE_L
MEM_A_CAS_L

MEM_A_A<13>
MEM_A_CS_L<1>

MEM_A_DQ<33>
MEM_A_DQ<32>

MEM_A_DQS_N<4>
MEM_A_DQS_P<4>

MEM_A_DQ<34>
MEM_A_DQ<35>

MEM_A_DQ<44>
MEM_A_DQ<41>

MEM_A_DM<5>

MEM_A_DQ<45>
MEM_A_DQ<42>

MEM_A_DQ<52>
MEM_A_DQ<51>

MEM_A_DQS_N<6>
MEM_A_DQS_P<6>

MEM_A_DQ<55>
MEM_A_DQ<54>

MEM_A_DQ<61>
MEM_A_DQ<60>

MEM_A_DM<7>

MEM_A_DQ<58>
MEM_A_DQ<59>

MEM_A_SA<0>

MEM_A_SA<1>

1

R3141

10K

5%
1/16W
MF-LF
402

2

=PP1V5_S0_MEM_A

8

=PP1V5_S3_MEM_A

8

73 74
75 76
77
79
81 82

85
87 88
89

93 94

99
101
103
105 106
107
109
111 112
113
115
117 118
119
121
123 124
125
127 128
129
131
133 134
135
137
139
141
143
145
147
149
151
153
155 156
157
159
161 162
163
165
167 168
169
171
173
175
177
179
181
183
185
187
189 190
191
193
195 196
197
199
201 202
203 204

1

C3100

10UF

20%

6.3V

2

X5R
603

KEY

CKE0
VDD
NC

J3100

BA2
VDD
A12/BC*
A9
VDD
A8
A5
VDD
A3
A1
VDD
CK0
CK0*
VDD
A10/AP
BA0
VDD
WE*
CAS*
VDD
A13
S1*
VDD
TEST
VSS
DQ32
DQ33
VSS
DQS4*
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
DQS6*
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SA0
VDDSPD
SA1
VTT

516-0196

SPD ADDR=0xA0(WR)/0xA1(RD)

CKE1

F-RT-THB

(SYMBOL 2 OF 2)

CK1*

DDR3-SODIMM-DUAL-M97-3

RAS*

ODT0

ODT1

VREFCA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5*

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7*

DQS7

DQ62
DQ63

EVENT*

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VTT

A15
A14

A11

CK1

BA1

S0*

DM4

DM6

SDA
SCL

VDD

1

2

A7

A6
A4

A2
A0

NC

C3101

10UF

20%

6.3V
X5R
603

78
80

8483
86

90
9291

9695
9897
100
102
104

108
110

114
116

120
122

126

130
132

136
138
140
142
144
146
148
150
152
154

158
160

164
166

170
172
174
176
178
180
182
184
186
188

192
194

198
200

MEM_A_CKE<1>

MEM_A_A<15>
MEM_A_A<14>

MEM_A_A<11>
MEM_A_A<7>

MEM_A_A<6>
MEM_A_A<4>

MEM_A_A<2>
MEM_A_A<0>

MEM_A_CLK_P<1>
MEM_A_CLK_N<1>

MEM_A_BA<1>
MEM_A_RAS_L

MEM_A_CS_L<0>
MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_DQ<36>
MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<38>
MEM_A_DQ<39>

MEM_A_DQ<47>
MEM_A_DQ<40>

MEM_A_DQS_N<5>
MEM_A_DQS_P<5>

MEM_A_DQ<46>
MEM_A_DQ<43>

MEM_A_DQ<48>
MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50>
MEM_A_DQ<49>

MEM_A_DQ<57>
MEM_A_DQ<56>

MEM_A_DQS_N<7>
MEM_A_DQS_P<7>

MEM_A_DQ<62>
MEM_A_DQ<63>

MEM_EVENT_L
=I2C_SODIMMA_SDA
=I2C_SODIMMA_SCL

1

C3110

0.1UF 0.1UF

20%
10V

2

CERM
402

1

C3111

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFDQ_A

27

15 88

IN

9

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

21 29 42

OUT

45

BI

45

IN

1

C3112

0.1UF

20%
10V

2

CERM
402

1

C3113

0.1UF

20%
10V

2

CERM
402

1

C3130

2.2UF

20%

6.3V

2

CERM
402-LF

15 88

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

1

C3135

2.2UF

20%

6.3V

2

CERM
402-LF

=PP0V75_S0_MEM_VTT_A

1

C3114

0.1UF

20%
10V

2

CERM
402

1

C3131

0.1UF

20%
10V

2

CERM
402

MEM_A_DQ<0>
MEM_A_DQ<1>

MEM_A_DM<0>

MEM_A_DQ<3>
MEM_A_DQ<2>

MEM_A_DQ<9>
MEM_A_DQ<13>

MEM_A_DQS_N<1>
MEM_A_DQS_P<1>

MEM_A_DQ<11>
MEM_A_DQ<14>

MEM_A_DQ<16>
MEM_A_DQ<18>

MEM_A_DQS_N<2>
MEM_A_DQS_P<2>

MEM_A_DQ<23>
MEM_A_DQ<19>

MEM_A_DQ<24>
MEM_A_DQ<30>

MEM_A_DM<3>

MEM_A_DQ<27>
MEM_A_DQ<25>

PP0V75_S3_MEM_VREFCA_A

1

C3136

0.1UF

20%
10V

2

CERM
402

1

C3115

0.1UF

20%
10V 10V

2

CERM
402

1

C3116

0.1UF

20%

2

CERM
402

1 2

VREFDQ

3

VSS

5

DQ0
DQ1

VSS

DM0

VSS
DQ2
DQ3

VSS
DQ8
DQ9

VSS
DQS1*
DQS1

VSS
DQ10
DQ11

VSS
DQ16
DQ17

VSS
DQS2*
DQS2

VSS
DQ18
DQ19

VSS
DQ24
DQ25

VSS
DM3

VSS
DQ26
DQ27

VSS

CRITICAL

J3100

7

9
11
13 14
15
17
19 20
21
23
25 26
27
29
31 32
33
35
37 38
39
41
43 44
45
47
49
51
53
55
57
59
61
63
65 66
67
69
71 72

516-0196

8

1

C3117

0.1UF

20%
10V

2

CERM
402

VSS
DQ4
DQ5

VSS

DQS0*

DQS0

F-RT-THB

VSS

DQ6
DQ7

VSS
DQ12
DQ13

VSS

DM1

(SYMBOL 1 OF 2)

RESET*

VSS
DQ14
DQ15

VSS

DDR3-SODIMM-DUAL-M97-3

DQ20
DQ21

VSS

DM2

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3*

DQS3

VSS
DQ30
DQ31

VSS

KEY

27

1

C3118

2

4
6
8
10
12

16
18

22
24

28
30

34
36

40
42

46
48
50
52
54
56
58
60
62
64

68
70

0.1UF

20%
10V
CERM
402

1

C3119

0.1UF

20%

10V

2

CERM
402

MEM_A_DQ<4>
MEM_A_DQ<5>

MEM_A_DQS_N<0>
MEM_A_DQS_P<0>

MEM_A_DQ<6>
MEM_A_DQ<7>

MEM_A_DQ<8>
MEM_A_DQ<12>

MEM_A_DM<1>
MEM_RESET_L

MEM_A_DQ<15>
MEM_A_DQ<10>

MEM_A_DQ<21>
MEM_A_DQ<20>

MEM_A_DM<2>

MEM_A_DQ<17>
MEM_A_DQ<22>

MEM_A_DQ<29>
MEM_A_DQ<28>

MEM_A_DQS_N<3>
MEM_A_DQS_P<3>

MEM_A_DQ<26>
MEM_A_DQ<31>

1

C3120

0.1UF

20%
10V

2

CERM
402

1

C3121

0.1UF

20%
10V

2

CERM
402

1

C3122

0.1UF

20%
10V

2

CERM
402

1

C3123

0.1UF

20%
10V

2

CERM
402

D

15 88

BI

15 88

BIBI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

29 30

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

C

B

"Factory" (top) slot

DDR3 SO-DIMM Connector A

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7546

SHT

SYNC_DATE=07/22/2008

REV.

A.0.0

OF

9628

A

8

7 6

5

4

3

2

1

8 7

6

5

4

3

2 1

Power aliases required by this page:

- =PP1V5_S0_MEM_B

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

Signal aliases required by this page:

- =I2C_SODIMMB_SCL

- =I2C_SODIMMB_SDA

BOM options provided by this page:

D

(NONE)

C

B

A

Page Notes

=PPSPD_S0_MEM_B

8

1

R3240

10K

5%
1/16W
MF-LF
402

2

1

C3240

2.2UF

20%

6.3V

2

CERM
402-LF

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

15 88

IN

IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

IN
IN

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

BI
BI

BI
BI

BI
BI

BI
BI

IN

BI
BI

MEM_B_CKE<0>

MEM_B_BA<2>

MEM_B_A<12>
MEM_B_A<9>

MEM_B_A<8>
MEM_B_A<5>

MEM_B_A<3>
MEM_B_A<1>

MEM_B_CLK_P<0>
MEM_B_CLK_N<0>

MEM_B_A<10>
MEM_B_BA<0>

MEM_B_WE_L
MEM_B_CAS_L

MEM_B_A<13>
MEM_B_CS_L<1>

MEM_B_DQ<32>
MEM_B_DQ<37>

MEM_B_DQS_N<4>
MEM_B_DQS_P<4>

MEM_B_DQ<34>
MEM_B_DQ<35>

MEM_B_DQ<41>
MEM_B_DQ<40>

MEM_B_DM<5>

MEM_B_DQ<43>
MEM_B_DQ<42>

MEM_B_DQ<55>
MEM_B_DQ<49>

MEM_B_DQS_N<6>
MEM_B_DQS_P<6>

MEM_B_DQ<52>
MEM_B_DQ<51>

MEM_B_DQ<56>
MEM_B_DQ<57>

MEM_B_DM<7>

MEM_B_DQ<63>
MEM_B_DQ<59>

MEM_B_SA<0>

MEM_B_SA<1>

1

R3241

10K

5%
1/16W
MF-LF
402

2

=PP1V5_S0_MEM_B

8

=PP1V5_S3_MEM_B

8

73 74
75 76
77
79
81 82

85
87 88
89

93 94

99
101
103
105 106
107
109
111 112
113
115
117 118
119
121
123 124
125
127 128
129
131
133 134
135
137
139
141
143
145
147
149
151
153
155 156
157
159
161 162
163
165
167 168
169
171
173
175
177
179
181
183
185
187
189 190
191
193
195 196
197
199
201 202
203 204

205 206
207 208
209 210
211 212

1

C3200

10UF

20%

6.3V

2

X5R
603

KEY

(2 OF 2)

DDR3-SODIMM

MTG PINS

MTG PIN

MTG PIN

MTG PIN

CKE1

CK1*

RAS*

ODT0

ODT1

VREFCA

DQ36
DQ37

DQ38
DQ39

DQ44
DQ45

DQS5*

DQS5

DQ46
DQ47

DQ52
DQ53

DQ54
DQ55

DQ60
DQ61

DQS7*

DQS7

DQ62
DQ63

EVENT*

CKE0

VDD
NC

BA2

J3200

F-RT-BGA3

VDD
A12/BC*
A9

VDD
A8
A5

VDD
A3
A1

VDD
CK0
CK0*

VDD
A10/AP
BA0

VDD
WE*
CAS*

VDD
A13
S1*

VDD
TEST

VSS
DQ32
DQ33

VSS
DQS4*
DQS4

VSS
DQ34
DQ35

VSS
DQ40
DQ41

VSS
DM5

VSS
DQ42
DQ43

VSS
DQ48
DQ49

VSS
DQS6*
DQS6

VSS
DQ50
DQ51

VSS
DQ56
DQ57

VSS
DM7

VSS
DQ58
DQ59

VSS
SA0
VDDSPD
SA1

VTT

MTG PIN

MTG PIN

MTG PIN MTG PIN

MTG PIN

516s0704

SPD ADDR=0xA2(WR)/0xA3(RD)

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VDD

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VSS

VTT

A15
A14

A11

CK1

BA1

S0*

DM4

DM6

SDA
SCL

VDD

1

2

A7

A6
A4

A2
A0

NC

C3201

10UF

20%

6.3V
X5R
603

78
80

8483
86

90
9291

9695
9897
100
102
104

108
110

114
116

120
122

126

130
132

136
138
140
142
144
146
148
150
152
154

158
160

164
166

170
172
174
176
178
180
182
184
186
188

192
194

198
200

MEM_B_CKE<1>

MEM_B_A<15>
MEM_B_A<14>

MEM_B_A<11>
MEM_B_A<7>

MEM_B_A<6>
MEM_B_A<4>

MEM_B_A<2>
MEM_B_A<0>

MEM_B_CLK_P<1>
MEM_B_CLK_N<1>

MEM_B_BA<1>
MEM_B_RAS_L

MEM_B_CS_L<0>
MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_DQ<33>
MEM_B_DQ<36>

MEM_B_DM<4>

MEM_B_DQ<38>
MEM_B_DQ<39>

MEM_B_DQ<44>
MEM_B_DQ<45>

MEM_B_DQS_N<5>
MEM_B_DQS_P<5>

MEM_B_DQ<47>
MEM_B_DQ<46>

MEM_B_DQ<48>
MEM_B_DQ<54>

MEM_B_DM<6>

MEM_B_DQ<53>
MEM_B_DQ<50>

MEM_B_DQ<60>
MEM_B_DQ<61>

MEM_B_DQS_N<7>
MEM_B_DQS_P<7>

MEM_B_DQ<58>
MEM_B_DQ<62>

MEM_EVENT_L
=I2C_SODIMMB_SDA
=I2C_SODIMMB_SCL

1

C3210

0.1UF

20%
10V

2

CERM
402

1

C3211

0.1UF

20%
10V

2

CERM
402

PP0V75_S3_MEM_VREFDQ_B

27

15 88

IN

9

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

IN

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

21 28 42

OUT

45

BI

45

IN

1

C3212

0.1UF

20%
10V

2

CERM
402

1

C3213

0.1UF

20%
10V

2

CERM
402

1

C3230

2.2UF

20%

6.3V

2

CERM
402-LF

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

1

C3235

2.2UF

20%

6.3V

2

CERM
402-LF

=PP0V75_S0_MEM_VTT_B

1

C3214

0.1UF

20%
10V 10V

2

CERM
402

1

C3231

0.1UF

20%
10V

2

CERM
402

MEM_B_DQ<0>
MEM_B_DQ<1>

MEM_B_DM<0>

MEM_B_DQ<2>
MEM_B_DQ<3>

MEM_B_DQ<28>
MEM_B_DQ<24>

MEM_B_DQS_N<3>
MEM_B_DQS_P<3>

MEM_B_DQ<31>
MEM_B_DQ<30>

MEM_B_DQ<9>
MEM_B_DQ<8>

MEM_B_DQS_N<1>
MEM_B_DQS_P<1>

MEM_B_DQ<15>
MEM_B_DQ<10>

MEM_B_DQ<21>
MEM_B_DQ<17>

MEM_B_DM<2>

MEM_B_DQ<18>
MEM_B_DQ<22>

PP0V75_S3_MEM_VREFCA_B

1

C3236

0.1UF

20%
10V

2

CERM
402

1

C3215

0.1UF

20%

2

CERM
402

1

C3216

0.1UF

20%
10V

2

CERM
402

1 2

VREFDQ

3

VSS

5

DQ0
DQ1
VSS
DM0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1*
DQS1
VSS
DQ10
DQ11
VSS
DQ16
DQ17
VSS
DQS2*
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
VSS
DQ26
DQ27
VSS

CRITICAL

J3200

F-RT-BGA3

7

9
11
13 14
15
17
19 20
21
23
25 26
27
29
31 32
33
35
37 38
39
41
43 44
45
47
49
51
53
55
57
59
61
63
65 66
67
69
71 72

516s0704

8

1

C3217

0.1UF

20%
10V

2

CERM
402

(1 OF 2)

DDR3-SODIMM

RESET*

KEY

27

DQS0*

DQS0

VSS

VSS
DQ12
DQ13

VSS

VSS
DQ14
DQ15

VSS
DQ20
DQ21

VSS

VSS
DQ22
DQ23

VSS
DQ28
DQ29

VSS

DQS3*

DQS3

VSS
DQ30
DQ31

VSS

VSS
DQ4
DQ5
VSS

DQ6
DQ7

DM1

DM2

1

2

4
6
8
10
12

16
18

22
24

28
30

34
36

40
42

46
48
50
52
54
56
58
60
62
64

68
70

C3218

0.1UF

20%
10V
CERM
402

1

C3219

0.1UF

20%
10V

2

CERM
402

MEM_B_DQ<4>
MEM_B_DQ<5>

MEM_B_DQS_N<0>
MEM_B_DQS_P<0>

MEM_B_DQ<6>
MEM_B_DQ<7>

MEM_B_DQ<29>
MEM_B_DQ<25>

MEM_B_DM<3>
MEM_RESET_L

MEM_B_DQ<26>
MEM_B_DQ<27>

MEM_B_DQ<13>
MEM_B_DQ<12>

MEM_B_DM<1>

MEM_B_DQ<14>
MEM_B_DQ<11>

MEM_B_DQ<20>
MEM_B_DQ<16>

MEM_B_DQS_N<2>
MEM_B_DQS_P<2>

MEM_B_DQ<19>
MEM_B_DQ<23>

1

C3220

0.1UF

20%
10V

2

CERM
402

1

C3221

0.1UF

20%

10V

2

CERM
402

1

C3222

0.1UF

20%
10V

2

CERM
402

1

C3223

0.1UF

20%
10V

2

CERM
402

D

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

28 30

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

IN

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

15 88

BI

C

B

"Expansion" (bottom) slot

DDR3 SO-DIMM Connector B

SYNC_MASTER=DDR

NOTICE OF PROPRIETARY PROPERTY

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY
PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR
AGREES TO THE FOLLOWING

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

SIZE

APPLE INC.

SCALE

D

NONE

DRAWING NUMBER

051-7546

SHT

SYNC_DATE=07/22/2008

OF

29 96

A

REV.

A.0.0

8

7 6

5

4

3

2

1