Apple A1286 Schematic RevA

OUT

IN

OUT

IN

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

4/24/2009

SCHEM,CORNHOLIO,K19

Schematic / PCB #’s

(Should rename J1300 nets now that JTAG level-shifter is gone)

Integration Issues to be Resolved

K19i

- PVT -

a.k.a.

ALIASES RESOLVED

42

02/05/2009

LPC+SPI Debug Connector

51

K19_MLB

41

(11/25/2008)

SMC Support

50

(K19_MLB)

40

02/05/2009

SMC

49

T18_MLB

39

02/05/2009

Front Flex Support

48

K19_MLB

38

02/05/2009

External USB Connectors

46

K19_MLB

37

03/23/2009

SATA Connectors

45

K19_MLB

36

02/05/2009

FireWire Ports

43

K19_MLB

35

03/18/2009

FireWire Port Power

42

K19_MLB

34

02/05/2009

FireWire LLC/PHY (FW643E)

41

T18_MLB

33

03/13/2009

Ethernet Connector

39

K19_MLB

32

02/05/2009

Ethernet & AirPort Support

38

K19_MLB

31

02/05/2009

Ethernet PHY (RTL8211CL)

37

(K19I_MLB)

30

03/23/2009

SECUREDIGITAL CARD READER

35

K19_MLB

29

03/04/2009

Right Clutch Connector

34

K19_MLB

28

02/05/2009

DDR3 Support

33

T18_MLB

27

02/05/2009

DDR3 SO-DIMM Connector B

32

K19_MLB

26

02/05/2009

DDR3 SO-DIMM Connector A

31

K19_MLB

25

02/05/2009

FSB/DDR3 Vref Margining

29

K24_MLB

24

01/06/2009

SB Misc

28

WFERRY_K19I

23

02/05/2009

MCP Graphics Support

26

K19_MLB

22

02/05/2009

MCP Standard Decoupling

25

T18_MLB

21

02/05/2009

MCP Power & Ground

22

T18_MLB

20

02/05/2009

MCP HDA & MISC

21

T18_MLB

19

02/05/2009

MCP SATA & USB

20

T18_MLB

18

02/05/2009

MCP PCI & LPC

19

T18_MLB

17

02/05/2009

MCP Ethernet & Graphics

18

T18_MLB

16

02/05/2009

MCP PCIe Interfaces

17

T18_MLB

15

02/05/2009

MCP Memory Misc

16

T18_MLB

14

02/05/2009

MCP Memory Interface

15

T18_MLB

13

02/05/2009

MCP CPU Interface

14

T18_MLB

12

02/05/2009

eXtended Debug Port(MiniXDP)

13

K19_MLB

11

02/05/2009

CPU Decoupling

12

K24_MLB

10

02/05/2009

CPU Power & Ground

11

K24_MLB

9

02/05/2009

CPU FSB

10

K24_MLB

8

01/13/2009

Signal Aliases

9

WFERRY_K19I

7

N/A

Power Aliases

8

N/A

6

N/A

Functional / ICT Test

7

N/A

5

N/A

Revision History

5

N/A

4

N/A

BOM Configuration

4

N/A

3

03/13/2008

Power Block Diagram

3

DRAGON

2

N/A

System Block Diagram

2

N/A

109

83

12/12/2008

WFERRY_K19I

K19i PCB Rule Definitions

108

82

01/08/2009

WFERRY_K19I

K19i Specific Constraints

106

81

02/05/2009

T18_MLB

SMC Constraints

105

80

02/05/2009

T18_MLB

FireWire Constraints

104

79

02/05/2009

T18_MLB

Ethernet Constraints

103

78

02/05/2009

T18_MLB

MCP Constraints 2

102

77

02/05/2009

T18_MLB

MCP Constraints 1

101

76

02/05/2009

T18_MLB

Memory Constraints

100

75

02/05/2009

T18_MLB

CPU/FSB Constraints

99

74

02/09/2009

VEMURI_K19I

LCD Backlight Driver (MC34845)

98

73

03/16/2009

K24_MLB

LCD Backlight Support

97

72

02/10/2009

K19_MLB

LCD BACKLIGHT DRIVER

94

71

02/05/2009

K19_MLB

DisplayPort Connector

93

70

12/19/2008

K24_MLB

DISPLAYPORT SUPPORT

90

69

02/05/2009

K19_MLB

LVDS Display Connector

79

68

03/12/2009

K24_MLB

POWER FETS

78

67

02/05/2009

K24_MLB

POWER SEQUENCING

77

66

02/25/2009

K24_MLB

MISC POWER SUPPLIES

76

65

(12/05/2008)

(K19_MLB)

CPU VTT Power Supply

75

64

02/03/2009

K19_MLB

MCP CORE REGULATOR

73

63

02/04/2009

K19_MLB

1.5V DDR3 Supply

72

62

01/13/2009

WFERRY_K19I

5V / 3.3V Power Supply

71

61

02/05/2009

K19_MLB

IMVP6 CPU VCore Regulator

70

60

03/18/2009

K19_MLB

PBus Supply & Battery Charger

69

59

03/18/2009

K19_MLB

DC-In & Battery Connectors

68

58

03/17/2009

K19_MLB

AUDIO: JACK TRANSLATORS

67

57

03/20/2009

CASEYHARDY_K19

AUDIO: JACKS

66

56

02/05/2009

K19_MLB

AUDIO:SPEAKER AMP

65

55

02/05/2009

K19_MLB

AUDIO: HEADPHONE FILTER

63

54

03/02/2009

K19_MLB

AUDIO: LINE INPUT FILTER

62

53

03/17/2009

K19_MLB

AUDIO: CODEC/REGULATOR

61

52

02/05/2009

K19_MLB

SPI ROM

60

51

03/25/2009

K19_MLB

DEBUG SENSORS AND ADC

59

50

02/05/2009

K19_MLB

Sudden Motion Sensor (SMS)

58

49

02/25/2009

K24_MLB

WELLSPRING 2

57

48

02/05/2009

K24_MLB

WELLSPRING 1

56

47

02/05/2009

K24_MLB

Fan

55

46

02/05/2009

K24_MLB

Thermal Sensors

54

45

12/16/2008

WFERRY_K19I

Current Sensing

53

44

02/05/2009

K24_MLB

VOLTAGE SENSING

1

SCH

CRITICAL051-7903

SCHEM,CORNHOLIO,K19

52

43

12/12/2008

WFERRY_K19I

K19i SMBus Connections

Contents

Date

Page

(.csa)

Sync

1

N/A

Table of Contents

1

N/A

PCBF,MLB IG,K19

CRITICAL

PCB

1

820-2533

(.csa)

Page

Date

Contents

Sync

?

? ?

051-7903

1 83

SCHEM,CORNHOLIO,K19

A

XDP_TDO

MAKE_BASE=TRUE

JTAG_MCP_TDOJTAG_MCP_TDO

MAKE_BASE=TRUE

XDP_TDO

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

J9400

DISPLAY PORT

J9000

CONN

LVDS

PG 71

CONN

PG 71

Conn

J4520

PG 17

(UP TO 12 DEVICES)

4

TMDS OUT

Line Out

2

CTRL

IR

J4710

CLK

SATA

(UP TO FOUR PORTS)

Conns

J6800,6801,6802,6803

PG 41

MCP79

PG 19

PCI

PG 19

LPC

3 8 9

PG 40

SATA

U6301 U6500U6400

PG 59

PG 56PG 55

HEADPHONE

Audio

Codec

FSB

64-Bit

2 UDIMMs

XDP CONN

POWER SUPPLY

PG 28

J3400 U3900

PG 33

Conn

88E1116

PG 31

GB

E-NET

Amp

Speaker

Amps

PG 54

PG 53

U6200

J4720

PG 57

J4710

U4900

J6950

PG 12

U1000

U1300

J4510

U6600,6605,6610,6620

PG 40

J4700

PG 40

HD

E-NET

ODD

Conn

SYNTH

PG 39

U6100

J3900,4635,4655

EXTERNAL

USB

PG 40

KEYBOARD

TRACKPAD/

USB

PG 45

POWER SENSE

J5650,5600,5610,5611,5660,5720,5730,5750

PG 48,49

J4900

DC/BATT

PENRYN

2.X OR 3.X GHZ

INTEL CPU

SPI

PG 20

PG 18

MEMORY

MAIN

800/1067/1333 MHz

DDR2-800MHZ

DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

SPI

TEMP SENSOR

FAN CONN AND CONTROL

J5100

PG 43

Ser

FanADC

SMC

B,0

Prt

BSB

PWR

Misc

PG 14

Port80,serial

LPC Conn

GPIOs

SATA

1.05V/3GHZ.

RGB OUT

PG 38

PG 13

FSB INTERFACE

PG 24

SMB

PG 20

HDA

NVIDIA

PG 41

CAMERA

Connectors

PG 44

SMB

DIMM’s

10 5 6 7

Bluetooth

PG 52

Boot ROM

U1400

DVI OUT

PCI-E

PG 16

UP TO 20 LANES3

PG 17

LVDS OUT

DP OUT

HDMI OUT

RGMII

PG 18

AirPort

Mini PCI-E

U3700

Line In

Amp Amp

PG 60

PG 9

CONN

System Block Diagram

SYNC_DATE=N/A

SYNC_MASTER=N/A

051-7903

A

2

83

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

S0PGOOD_PWROK

CPU_RESET#

FSB_CPURST_L

MCP_PS_PWRGD

29

CPUPWRGD(GPIO49)

PS_PWRGD

RSMRST*

CHGR_EN

M97 POWER SYSTEM ARCHITECTURE

(44A MAX CURRENT)

PP1V05_S0_FET

PP1V05_S5_REG

U7760

V

PPVBAT_G3H_CHGR_OUT

PP1V2_ENET_REG

(0.8A MAX CURRENT)

S5 S3

TPS51116

ADAPTER

SMC_PM_G2_EN

PPCPUVTT_S0

LPC_RESET_L

RSMRST_OUT(P15)

IMVP_VR_ON(P16)

RSMRST_IN(P13)

PLT_RST*

PWR_BUTTON(P90)

P17(BTN_OUT)

RST*

PP1V05_S0

PP3V3_S0

19-1

SLP_S3_L(P93)

U4900

MCPCORESO_PGOOD

P5V3V3_PGOOD

RSMRST_PWRGD

1.05V (S5)

IMVP_VR_ON

U5480

28

P5V3V3_PGOOD

P3V3ENET_EN_L

PP1V5_S0

TPS79918DRV

PP1V8_S0_REG

SLP_S4_L(P94)

PM_RSMRST_L

U1400

04

U5000

RN5VD30A-F

SMC PWRGD

4.6V AUDIO MAX8902A

U6201

VOUT

EN

VIN

PPVIN_G3H_P3V42G3H

3.425V G3HOT LT3470

PP4V6_AUDIO_ANALOG

U1000

SLP_S3_L

ALL_SYS_PWRGD

25

SMC

PPVOUT_ENET_AVDD_REG

(1.9V)

1.2V YUKON

PP1V5_S0_FET

U7200

PPVOUT_S0_LCDBKLT

PP3V3_S0_FET

13

SMC_CPU_ISENSE

VOUT

25

02

VIN

EN1

PPVBAT_G3H_CHGR_REG

U5403

SMC_BATT_ISENSE

BATTERY CHARGER

P5VRTS0_EN_L

PBUS SUPPLY/

U7970

32

PWRGOOD

U2850

CPU

30

31

06-1

17

16-3

03

PP3V42_G3H_REG

16-2

10

05

09

24

18

16-2

MCP_CORE

PPVCORE_S0_MCP_REG_R

(1A MAX CURRENT)

07

PP5VRT_S0

08

VOUT

12

20

21

02

14

11-2

02

04

(S5)

SMC_PM_G2_EN

16

SMC_ADAPTER_EN

04-1

=DDTVTT_EN

16-1

16-2

16-4

16-3

16-2

15

15-1

15

11-2

11-3

DELAY

RC

11-1

11

MCP79

A

SMC_DCIN_ISENSE

BATT_POS_F

3S2P

05

06

Q7800

P3V3S5_EN_L

P16

PPBUS_G3H

ENETADD_EN

Q7050

P1V05_S5_EN

3.3V

TPS51125

26

22

06

02

23

V

PPCPUVTT_S0_REG_R

(8A MAX CURRENT)

(1.05V)

CPUVTTS0_EN

PPBUS_G3H

D6905

02

Q5315

01

ENABLES

02

PWRBTN*

PLTRST*

R5492

PP1V5_S0

R5491

(12A MAX CURRENT)

(Q7901 & Q7971)

S3 TO S0

FETS

PPVCORE_S0_MCP

R5490

PP0V75_S0_REG

PP1V5_S3_REG

U4900

PP5VLT_S3_REG

(25A MAX CURRENT)

PP5VLT_S3

(7A MAX CURRENT)

PPVCORE_CPU_S0_REG

PP5VRT_S0_REG

P1V05S0_EN

P5V_LT_S3_PGOOD

CPUVTTS0_PGOOD

P1V05S0_EN

P5VRTS0_EN_L

BKLT_EN

CHGR_BGATE

SMC

V3

WOL_EN

VR_PWRGOOD_DELAY

PM_SLP_S3_L

DELAY

RC

(S0)

P3V3S0_EN

PBUSVSENS_EN

MCPCORES0_EN

CPUVTTS0_EN

MCPDDR_EN

P1V8S0_EN

CPUVTTS0_PGOOD

(S0)

DCIN(16.5V)

1.8V LDO

P3V3_ENET_FET

MCPCORES0_EN

VOUT1

EN1

EN2

VIN

SMC_CPU_VSENSE

A

CPU_PWRGD

VIN

ENABLE

7A FUSE

SMC_ONOFF_L

SLP_S5_L SLP_S4_L

SLP_S5_L(P95)

PWRGD(P12)

IMVP_VR_ON

SMC_RESET_L

VREG3

PGOOD1,2

VIN

RESET*

VOUT2

PM_PWRBTN_L

99ms DLY

IN

AC

(S5)

A

V1 V2

MCP79

DELAY

PP3V3_S5

PP3V3_S3_FET

CURRENT)

PP3V3_S5_REG

D6905

P5VLTS3_EN

VOUT2

=DDRREG_EN

(0.8A MAX CURRENT)

P1V2ENET_EN

PBUS_VSENSE

(4A MAX CURRENT)

P3V3S3_EN

P3V3S0_EN

DDRREG_EN

P5VLTS3_EN

DELAY

RC

(4A MAX

VOUT

1.05V SO

FETS

(Q7951 TO Q7953)

TPS62510

U7750

CPU VCORE

ISL9504B

VR_ON

U7400

PGOOD

5V

(RT)

VOUT1

VOUT2

EN2

GOSHAWK6P

VIN

U9701

ENA

VOUT

U3850

VOUT1

RUN1

DELAY

RC

LTC34074

RUN2

Q7930

Q7910

Q3810

RST*

VIN

PM_ENET_EN_L

PM_SLP_S3_L

Q3802

Q3801

U6990

VOUT

EN_PSV

VOUT

CPUVTT

TPS51117

U7600

PGOOD

VIN

ISL6258A

U7000

U7870

5V (LT)

ISL6236

U7500

U7300

VOUT2

0.75V

1.5V

VOUT1

VIN

J6950

(9 TO 12.6V)

6A FUSE

PM_SLP_S4_L

SLP_S3#

U1400

PCI_RESET0#

LTC2909

P60

P3V3S3_EN

3

A

Power Block Diagram

83

051-7903

SYNC_MASTER=DRAGON

SYNC_DATE=03/13/2008

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BOM Groups

Alternate Parts

Development BOM

Bar Code Label / EEE #

BOM Variant

Programmable Parts

Module Parts

83

A

051-7903

4

BOM Configuration

SYNC_MASTER=N/A

SYNC_DATE=N/A

085-0737

K19I MLB DEVELOPMENT

K19_DEVEL_PVT

K19_DEBUG_PROD

BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

CPU_2_0GHZ

CRITICAL

U1000

PDC,SLGE3,PRQ,2.00,25W,1066,R0,3M,BGA

1

337S3693

CPU_2_26GHZ

U1000

CRITICAL

PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA

1

337S3704

K19_DEBUG_ENG

DEVEL_BOM,SMC_DEBUG_YES,XDP

K19_MCP

MCP_B03,BOOT_MODE_USER

K19_COMMON

COMMON,ALTERNATE,K19_MCP,K19_MISC,K19_DEBUG_PVT,K19_PROGPARTS

BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG

K19_PROGPARTS K19_DEVEL_ENG

BMON_ENG,DEBUG_ADC,XDP_CONN,LPCPLUS,VREFMRGN,BKLT_FS

LPCPLUS

K19_DEVEL_PVT

K19_MISC

DP_ESD,EXTRACT_BUFF,ISL6258A,K19I,KB_BL,MIKEY,LDO_YES

DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN

K19_DEBUG_PVT

152S0586

ALL

MAGLAYERS AS ALTERNATE

152S0847

152S0516

ALL

MAGLAYERS AS ALTERNATE

152S0874

152S0778

CYNTEC AS ALTERNATE

ALL

152S0693

ALL

152S0968

Maglayer alt to Delta

152S0966

ALL

138S0602

Murata alt to Samsung

138S0603

MAGLAYERS AS ALTERNATE

ALL

152S0138152S0694

157S0058 157S0055

ALL

DELTA AS ALTERNATE

K19_COMMON,CPU_2_53GHZ,EEE_6Z9

630-9977

PCBA,CORNHOLIO,MLB,K19I

337S3641

1

CPU_2_8GHZ

CRITICAL

U1000

PDC,SLB43,PRQ,2.8,35W,1066,C0,6M,BGA

1

U1000

CRITICAL337S3680

CPU_2_4GHZ

PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA

1

U1000

CRITICAL337S3640

CPU_2_5GHZ

PDC,SL3BX,PRQ,2.5,35W,1066,C0,6M,BGA

1

338S0694

U3700

CRITICAL

IC,RTL8251CA-VB-GR,GIGE TRANSCEIVER,48P

1

U4900

CRITICAL341S2460

IC,PRGRM,SMC EXTERNAL,K19I

SMC_PROG

U5701

CRITICAL337S2983

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

1

WELLSPRING_BLANK

IR_BLANKCRITICAL

U4800

338S0633

IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN

1

ALL

128S0262

KEMET alt to SANYO

128S0220

ALL

128S0218

KEMET AS ALTERNATE

128S0093

DEVEL

1

DEVEL_BOM

K19I MLB DEVELOPMENT

085-0737 CRITICAL

ALL

152S0796 152S0685

CYNTEC AS ALTERNATE

DALE/VISHAY AS ALTERNATE

ALL

104S0023104S0018

338S0710

1

CRITICAL

U1400

IC,MCP79MXT-B3,35x35MM,BGA1437

MCP_B03

338S0654

IC-FW643-E,1394B PHY/OHCI LINK/PCI-E,12

1

U4100

CRITICAL

337S3756

PDC,SLCFG,PRQ,2.53,25W,1066,R0,3M,BGA

1

CRITICAL

U1000

CPU_2_53GHZ

U4900

1

CRITICAL338S0563

IC,SMC,HS8/2117,9X9MM,TLP,HF

SMC_BLANK

1

U6100

CRITICAL

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

335S0610

BOOTROM_BLANK

U6100

341S2458

1

IC,PRGRM,UNLOCK,K19I

BOOTROM_PROG

CRITICAL

341S2384

IR_PROG

IR,ENCORE II,CY7C63803-LQXC

CRITICAL

1

U4800

U57011341S2503 CRITICAL

IC,TP PSOC,M97,M98

WELLSPRING_PROG

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

1

EEE_6Z9

[EEE:6Z9]

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Revision History

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

SYNC_MASTER=N/A

SYNC_DATE=N/A

5

83

051-7903

Revision History

A

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FUNC_TEST

KBD Backlight Conn.

6 TPs

2 TPs

Keyboard Connector

FUNC_TEST

5 TPs

3 TPs

FUNC_TEST

6 TPs

3 TPs

Airport/BT/Camera Conn.

FUNC_TEST

3 TPs

Functional Test Points

DC Power Connector

ICT Test Points

FUNC_TEST

3 TPs

10 TPs

3 TPs

IPD Flex Connector

2 TPs

6 TPs

3 TPs

FUNC_TEST

Speaker Connectors

6 TPs

FUNC_TEST

2 TPs

FUNC_TEST

5 TPs

2 TPs

Note.

NO_TEST properties are also on page9,26,43,50

SD Card Connector

NO_TEST

FUNC_TEST

4 TPs

Battery Connector

SATA HDD Connector

Power Nets

BIL Connector

SATA ODD Connectors

Fan Connectors

FUNC_TEST

LVDS Connector

3 TPs

NO_TEST

4 TPs

SYNC_DATE=N/A

SYNC_MASTER=N/A

Functional / ICT Test

6

83

A

051-7903

MCPCORES0_OCSET

TRUE

NC_SATA_D_D2RP

TRUE

BKL_VLDO

NC_MEM_B_CKE<2>

NC_LPC_DRQ0_L

USB_BT_N

TRUE

USB_CAMERA_N

TRUE TRUE

USB_CAMERA_P

TRUE

SATA_ODD_D2R_UF_N SATA_ODD_D2R_UF_P

TRUE

DP_ML_C_P<3..0>

TRUE

FSB_ADSTB_L<1..0>

FSB_DINV_L<3..0>

TRUE

USB_BT_P

TRUE

SD_CLK

PP5V_S0

TRUE

MAKE_BASE=TRUE

TRUE

NC_SATA_C_R2D_CP

NC_PCI_STOP_L

TRUE

PP3V3_S0

TRUE

PP1V05_S0

WS_KBD10

TRUE

FSB_REQ_L<4..0>

TRUE

PP5V_S3_BTCAMERA_F

TRUE

MINI_RESET_CONN_L

FSB_HITM_L

TRUE

NC_SATA_D_D2RN

NC_SB_A20GATE

TRUE

SMC_LID_R

TRUE

SMBUS_SMC_BSA_SCL

TRUE

LVDS_CONN_A_CLK_F_N

PP3V3_SW_LCD

TRUE

FSB_HIT_L

TRUE

FSB_DSTB_L_N<3..0>

TRUE

FSB_ADS_L

TRUE

FAN_RT_TACH

TRUE

FAN_RT_PWM

TRUE

LVDS_CONN_A_DATA_N<1>

TRUE

LVDS_CONN_A_DATA_P<1>

TRUE

LVDS_CONN_A_DATA_N<2>

TRUE

LVDS_CONN_A_CLK_F_P

LVDS_CONN_B_DATA_P<0>

TRUE

LVDS_CONN_B_DATA_N<1>

TRUE

LVDS_CONN_B_DATA_N<0>

TRUE

LVDS_CONN_B_DATA_P<1>

TRUE

PP3V3_S0

TRUE

LVDS_DDC_CLK

TRUE TRUE

LVDS_DDC_DATA LVDS_CONN_A_DATA_N<0>

TRUE

LVDS_CONN_A_DATA_P<2>

TRUE

PP5V_SW_ODD

TRUE

SMBUS_SMC_BSA_SDA

PP3V42_G3H

TRUE

SMC_BIL_BUTTON_L

TRUE

PP0V75_S0_DDRVTT

PP1V5_S0

TRUE

PP3V3_S3

TRUE

PP3V3_S5

TRUE

PP3V42_G3H

PP3V3_ENET

TRUE

PP4V5_AUDIO_ANALOG

SMBUS_SMC_A_S3_SCL

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SCL

TRUE

PP1V8_S0

TRUE

PP1V5_S3

TRUE

PP5V_SW_ODD

MAKE_BASE=TRUE

TRUE

NC_PCI_AD<31..8>

NC_P7_7

TRUE

NC_MEM_B_CLK4N

MAKE_BASE=TRUE

TP_MEM_A_ODT<3..2>

NC_MEM_A_CS_L<3>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CS_L<3>

NC_MEM_A_CLK2N

TP_MEM_A_CKE<3..2>

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CKE<3..2>

NC_ISSP_SDATA_P1_0

NC_ENET_INTR_L

NC_USB_10P

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_USB_10N

NC_AUD_LO1_P_L NC_AUD_LO1_P_L

TRUE

MAKE_BASE=TRUE

NC_AUD_LO1_N_L

TRUE

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_SATA_D_D2RN

NC_SATA_C_R2D_CN

TRUE

NC_SATA_C_R2D_CN

MAKE_BASE=TRUE

NC_SATA_C_D2RP

TRUE

NC_PSOC_P1_3

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE4_D2RN

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE6P

MAKE_BASE=TRUE

NC_PCIE_CLK100M_PE5N

NC_PCIE_CLK100M_PE4P

TRUE

NC_PCIE_CLK100M_PE4N

MAKE_BASE=TRUE

TRUE

NC_PCI_TRDY_L

MAKE_BASE=TRUE

NC_PCI_SERR_L

TRUE

NC_PCI_SERR_L

MAKE_BASE=TRUE

NC_PCI_RESET1_L

TRUE

NC_PCI_RESET1_L

MAKE_BASE=TRUE

NC_PCI_PERR_L

TRUE

MAKE_BASE=TRUE

NC_PCI_PERR_L

NC_PCI_IRDY_L

NC_PCI_INTX_L

TRUE

NC_PCI_INTX_L

MAKE_BASE=TRUE

NC_PCI_INTW_L

TRUE

MAKE_BASE=TRUE

NC_PCI_INTW_L

TRUE

NC_PCI_GNT0_L

MAKE_BASE=TRUE

NC_PCI_FRAME_L

TRUE

MAKE_BASE=TRUE

NC_PCI_FRAME_L

NC_PCI_CLK1

TRUE

NC_PCI_CLK1

MAKE_BASE=TRUE

TRUE

NC_PCI_C_BE_L<3..0>

MAKE_BASE=TRUE

TRUE

WS_KBD15_CAP

TRUE

WS_KBD13

TRUE

SATA_ODD_R2D_P

SPKRCONN_S_OUT_N

TRUE

CONN_USB2_BT_N

TRUE

BKL_ISEN2

TRUE

WS_KBD8

TRUE

PP1V05_S5

Z2_BOOST_EN

TRUE

SATA_ODD_D2R_C_P

TRUE

PPVOUT_S0_LCDBKLT

TRUE

LVDS_CONN_B_CLK_F_P

TRUE

LVDS_CONN_B_CLK_F_N

TRUE

LED_RETURN_2

TRUE

LED_RETURN_3

TRUE

LED_RETURN_6 BKL_ISEN1

TRUE

BKL_ISEN5

TRUE TRUE

BKL_ISEN6

PP3V3_S3_LDO

TRUE

PP18V5_S3

TRUE TRUE

Z2_CS_L

TRUE

Z2_DEBUG3 Z2_MOSI

TRUE TRUE

Z2_MISO Z2_SCLK

TRUE

Z2_HOST_INTN

TRUE

Z2_CLKIN

TRUE

Z2_RESET

Z2_KEY_ACT_L

TRUE

PSOC_MISO

TRUE

PSOC_SCLK

PSOC_MOSI

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PSOC_F_CS_L

TRUE

SD_D<7..0> SD_CMD

TRUE

SD_CD_L

TRUE

SD_WP

BI_MIC_SHIELD

TRUE

BI_MIC_LO

TRUE

SPKRCONN_R_OUT_P

TRUE

SPKRCONN_R_OUT_N

TRUE

SPKRCONN_S_OUT_P

TRUE

WS_KBD17

TRUE

WS_KBD21

CONN_USB2_BT_P

TRUE

FSB_D_L<63..0>

PP5V_S3_IR_R

TRUE

PICKB_L

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

WS_KBD23

LED_RETURN_1

TRUE

NC_MEM_A_CLK4P

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK3P

NC_ENET_PWRDWN_L

NC_ISSP_SCLK_P1_1

NC_PCI_GNT1_L

NC_PCI_INTZ_L

NC_PCIE_PE4_D2RN

TRUE

NC_SB_A20GATE

MAKE_BASE=TRUE

NC_SATA_D_D2RP

TRUE

MAKE_BASE=TRUE

FSB_DSTB_L_P<3..0>

TRUE

SPKRCONN_L_OUT_N

SPKRCONN_L_OUT_P

TRUE

BI_MIC_HI

TRUE

LVDS_CONN_A_DATA_P<0>

TRUE

LVDS_CONN_B_DATA_N<2>

TRUE

LVDS_CONN_B_DATA_P<2>

TRUE

BKL_ISEN4

BKL_ISEN3

TRUE

WS_LEFT_SHIFT_KBD

NC_PSOC_P1_3

NC_PCI_GNT0_L

NC_PCI_DEVSEL_L

TRUE

WS_KBD22

WS_KBD5

TRUE

PP3V42_G3H

TRUE

WS_KBD4

TRUE

WS_KBD20

TRUE

WS_KBD19

TRUE

WS_KBD18

TRUE

WS_KBD16_NUM

WS_KBD11

TRUE

WS_KBD9

TRUE

PPVCORE_S0_MCP

NC_SATA_C_R2D_CP

TRUE

NC_P7_7

MAKE_BASE=TRUE

PP1V05_ENET

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP5V_S3

TRUE

PP3V3_S3_LDO

TRUE

PP5V_S0_HDD_FLT

TRUE

ADAPTER_SENSE

TRUE

PM_SLP_S3_L

NC_PCIE_CLK100M_PE6P

NC_PCI_TRDY_L

TRUE

NC_PCI_CLK0

MAKE_BASE=TRUE

TRUE

NC_PCI_GNT1_L

MAKE_BASE=TRUE

TRUE

PP1V05_S5

PPVCORE_S0_CPU

TRUE

WS_KBD2

SMBUS_SMC_BSA_SDA

TRUE

WS_KBD1

TRUE

NC_MEM_A_ODT<3..2>

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_MEM_A_CLK2N

TRUE

MAKE_BASE=TRUE

NC_LPC_DRQ0_L

TRUE

MAKE_BASE=TRUE

NC_ISSP_SDATA_P1_0

NC_ISSP_SCLK_P1_1

MAKE_BASE=TRUE

TRUE

NC_ENET_PWRDWN_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

TRUE

NC_ENET_INTR_L

TRUE

MAKE_BASE=TRUE

NC_LCDBKLT_FAIL

TRUE

NC_MEM_B_CLK3P

MAKE_BASE=TRUE

TP_PCI_AD<31..8>

PPBUS_G3H

TRUE

WS_KBD6

SMC_ODD_DETECT

TRUE

PP18V5_DCIN_FUSE

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK4P

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CLK5N

TRUE

MAKE_BASE=TRUE

NC_MEM_B_ODT<2>

NC_MEM_B_CLK5N

NC_MEM_B_CLK4P

NC_MEM_B_ODT<2> NC_MLB_RAM_SIZE

NC_PCI_CLK0

TP_PCI_C_BE_L<3..0>

NC_MEM_B_CLK3P

TRUE

MAKE_BASE=TRUE

NC_MLB_RAM_SIZE

TRUE

NC_PCI_INTZ_L

MAKE_BASE=TRUE

TRUE

NC_SATA_C_D2RP

MAKE_BASE=TRUE

TRUE

NC_PSOC_SDA

MAKE_BASE=TRUE

TRUE

NC_PE4_PRSNT_L

MAKE_BASE=TRUE

TRUE

NC_PCIE_PE4_R2D_CN

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5N

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE5P

MAKE_BASE=TRUE

TRUE

NC_PCIE_CLK100M_PE4P

MAKE_BASE=TRUE

TRUE

NC_PCI_STOP_L

MAKE_BASE=TRUE

TRUE

NC_PCI_IRDY_L

MAKE_BASE=TRUE

TRUE

NC_PCI_DEVSEL_L

MAKE_BASE=TRUE

TRUE

MAKE_BASE=TRUE

NC_MEM_B_CKE<2>

NC_MEM_A_CLK3N

MAKE_BASE=TRUE

TRUE

NC_LCDBKLT_FAIL

NC_USB_10P

NC_USB_10N

NC_AUD_LO1_N_L

NC_PSOC_SDA

TRUE

WS_CONTROL_KBD

TRUE

PCIE_MINI_D2R_P PCIE_MINI_D2R_N

TRUE

PCIE_CLK100M_MINI_CONN_P

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

PP5V_WLAN

MINI_CLKREQ_Q_L

TRUE

PCIE_MINI_R2D_N

TRUE

PCIE_MINI_R2D_P

USB_CAMERA_CONN_N

TRUE

NC_MEM_B_CLK4N

TRUE

PPVBAT_G3H_CONN

TRUE

GND_BATT_CHGND

PP5V_S0_HDD_FLT

TRUE

USB_CAMERA_CONN_P

TRUE

WS_KBD3

TRUE

WS_KBD14

TRUE

WS_KBD12

TRUE

WS_KBD7

TRUE

PP3V3_S3

SATA_ODD_D2R_C_N

TRUE

SATA_ODD_R2D_N

TRUE

NC_MEM_A_CLK3N NC_MEM_A_CLK3P NC_MEM_A_CLK4P

TRUE

PCIE_WAKE_L

TRUE

PCIE_CLK100M_MINI_CONN_N

TRUE

SATA_HDD_R2D_P SATA_HDD_R2D_N

TRUE

SATA_HDD_D2R_C_N

TRUE

SATA_HDD_D2R_C_P

TRUE

IR_RX_OUT SYS_LED_ANODE_R

TRUE

SMC_KDBLED_PRESENT_L

TRUE

KBDLED_ANODE

TRUE

PM_SLP_S4_L

TRUE

SMC_PM_G2_EN

PPVOUT_S0_LCDBKLT

TRUE

KBDLED_ANODE

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_KBD_ONOFF_L

TRUE

LED_RETURN_5

TRUE

LED_RETURN_4

TRUE

PP18V5_S3

NC_PCIE_CLK100M_PE4N

NC_PCIE_CLK100M_PE5P

NC_PCIE_PE4_R2D_CN NC_PE4_PRSNT_L

FSB_LOCK_L

TRUE

FSB_A_L<31..3>

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

6

19

72

6

15

6

18

19 29 78

37 82

71 82

9

13 75

9

13 75

19 29 78

30 82

7

37 42

47 49 61

64 65 67

68 70

72

6

19

6

18

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

7 9

10 11 12 13 16 17 19 21 22

23 35 61 65 66 67

48

9

13 75

29

9

13 75

6

19

6

20

59

6

40 43 59 60 81

69 82

69

9

13 75

9

13 75

9

13 75

47

8

69

8

69

8

69

69 82

8

69

8

69

8

69

8

69

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

8

17 69

8

17 69

8

69

8

69

6

37 51

6

40 43 59 60 81

6 7

20

21 24

38 40

41

42

43 45 48 59 60 67

40 41 59

7

26 27 63 68

7

10 11 15 22 37 66 67 68 82

6 7

20 25 29 30 43 48 50 68

7

17 19 21 22 24 28 32 35 36 42

52 62 66 67 68 69 71 82 6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

7

17 22 31 32

53

6

29 40 43 49 81

59

6

40 43 59 60 81

7

17 23 53 66

7

26 27 28 63 68

6

37 51

18

6

48

6

15

6

15

6

15

6

14

15

6

48

6

17

6

19

6

19

6

53

6

53

6

53

6

19

6

19

6

19

6

19

6

48

6

16

6

16

6

16

6

16

6

16

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

6

18

48

37 77

56 57 82

29 82

72

48

6 7

21 22 32 66

49

37 77

6

51 69 72 74

69 82

69 72 74

72

6

49

6

49

48 49

6

29 40 43 49 81

48 49

30 82

30

57 58

56 57 82

48

29 82

9

13 75

37

48 49

6

29 40 43 49 81

48

69 72 74

6

15

6

15

6

17

6

48

6

18

6

18

6

16

6

20

6

19

9

13 75

56 57 82

57 58

8

69

8

69

8

69

72

48

6

48

6

18

6

18

48

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

48

7

21 22 44 64

6

19

6

48

7

17 22 31 32

40 41

7 8

29 37 38 39 41 49 51 53 62

63 68

6

49

6

37

59

20 32 35 40 67 71

6

16

6

18

6

18

6

18

6 7

21 22 32 66

7

10 11 44 61

48

6

40 43 59 60 81

48

15

6

14

6

18

6

48

6

48

6

17

6

17

6

15

7

35 44 45 59 60 62 63 64 73

48

37 40

59

6

15

6

15

6

15

6

15

6

15

6

15

6

20

6

18

6

15

6

20

6

18

6

19

6

48

6

16

6

16

6

16

6

16

6

16

6

18

6

18

6

18

6

15

6

15

6

19

6

19

6

53

6

48

16 29 77

29 82

6

29 40 43 49 81

29

29 77 82

29 82

6

15

59 60

8

59

6

37

29 82

48

6 7

20 25 29 30 43 48 50 68

37 77

6

15

6

15

6

15

16 29

29 82

37 77

37 39

37

49

6

49

20 38 40 41 67

8

40 62 67

6

51 69 72 74

6

49

48

69 72 74

6

49

6

16

6

16

6

16

6

16

9

13 75

9

13 75

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

6600 MA

241 mA max load

K19i uses GND reference for ALL DDR3 signals.

139 mA/ 0 mA

DDR3 Reference Plane

500 mA max supply

190 mA

1.8V Rail

1.5V S3 Rail

4771 mA

130 mA

5V Rails

MCP79 PCIe/SATA Rails

3.3V Rails

0.75V Rails

Chipset "VCore" Rails

1182 mA

4500 mA

"FW" (FireWire) Rail

DCIN Rail

"G3Hot" (Always-Present) Rails

1034 mA

105 mA/241 mA

1.05V Rails

1.5V S0 Rail

Power Aliases

051-7903

SYNC_MASTER=N/A

SYNC_DATE=N/A

A

83

7

PP3V42_G3H

PP1V5_S0

MAKE_BASE=TRUE

VOLTAGE=1.5V

PP1V5_S0

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

PP3V3_S5 PP3V3_S5

PP3V3_S5

PPBUS_CPU_IMVP_ISNS

PP1V5_S0

PP1V05_S5

PP1V05_S0

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.05V

PP1V05_S0

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0 PP1V05_S0

PP1V05_S0

PP5V_S3

PPDCIN_S5

PP5V_S3

PP3V3_S5

VOLTAGE=12.6V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm

PPBUS_G3H

PP3V42_G3H

PP3V42_G3H PP3V42_G3H

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.42V

PP3V42_G3H

MIN_LINE_WIDTH=0.3 mm

MAKE_BASE=TRUE

PP0V75_S0_DDRVTT PP0V75_S0_DDRVTT

PP0V75_S0_DDRVTT

MIN_NECK_WIDTH=0.17 mm

PP0V75_S0_DDRVTT

VOLTAGE=0.75V MAKE_BASE=TRUE

MIN_LINE_WIDTH=2 mm

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0

PPVCORE_S0_CPU

MIN_LINE_WIDTH=0.4 mm VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V05_ENETPP1V05_ENET

PP3V3_S5

PP1V05_ENET

PP1V05_S0_MCP_PLL_UF

PP1V05_FW

PPVCORE_S0_CPU

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

PPVCORE_S0_CPU

PPVCORE_S0_MCP

PP1V05_S5

PPVCORE_S0_MCP

PP1V05_S0_MCP_PEX_AVDD

PP5V_S3

PP3V3_S5

PPBUS_G3H

GND

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

GND

PP1V05_S0_MCP_SATA_AVDDPP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

GND

PP1V05_S0PP1V05_S0

MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25 mm

PPBUS_CPU_IMVP_ISNS

PP3V42_G3H

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=12.6V

PPVP_FW

PP5V_S3

PP5V_S3 PP5V_S3

PP5V_S3

VOLTAGE=5V

PP5V_S3

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

GND

PP1V05_S5

PP1V05_ENET

PPVP_FW

PP1V05_ENET

PPVCORE_S0_MCP

PPVTTDDR_S3

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

MAKE_BASE=TRUE

VOLTAGE=0.75V

PPVTTDDR_S3

PP3V42_G3H

PP5V_S3

PPVP_FW

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

PPDCIN_S5

MAKE_BASE=TRUE

PP3V42_G3H

PPDCIN_S5

PP3V3_S5

PP3V3_S3

PPVCORE_S0_CPU

PP3V3_S3

PP3V3_S3 PP3V3_S3

PP3V3_S3

PPBUS_CPU_IMVP_ISNS

PP3V42_G3H PP3V42_G3H

PP1V05_FW

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PP1V05_FW

PPVCORE_S0_MCP

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 mm

PP3V3_ENET

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

PP3V3_S0

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP3V3_FW

VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V8_S0

PP3V3_ENET

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_S0

PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0 PP3V3_S0

PP3V3_FW PP3V3_FW

PP1V8_S0 PP1V8_S0

PP1V5_S3 PP1V5_S3 PP1V5_S3

PP3V3_S0

PP3V3_S3

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

PP3V3_S3

VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S3 PP3V3_S3

PP3V3_ENET

PP3V3_S3

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP5V_S0

MIN_LINE_WIDTH=0.4 MM

PP5V_S0

PP5V_S0 PP5V_S0 PP5V_S0

PP5V_S0

PPBUS_CPU_IMVP_ISNS

PP3V42_G3H

PP1V5_S3

PP1V8_S0

PP1V5_S3

PP5V_S0 PP5V_S0

PP5V_S3

PP3V3_FW

GND

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PP1V05_S5

MIN_LINE_WIDTH=0.4 mm

MAKE_BASE=TRUE

PP3V3_S5

MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V

PP3V3_S5

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

PP1V5_S0

PP1V5_S0 PP1V5_S0

PP1V05_S0

PP3V3_S0

MIN_LINE_WIDTH=0.6 mm

PP1V5_S3

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=1.5V

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

10 11 15 22 37 66 67 68

82

6 7

10 11 15 22 37 66 67 68

82

6 7

10 11 15 22 37 66 67 68

82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82 6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

7

45 61 65

6 7

10 11 15 22 37 66 67 68

82

6 7

21 22 32 66

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67 6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67 6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

7

59 60

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

35 44 45 59 60 62 63 64 73

6 7

35 44 45 59 60 62 63 64

73

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67 6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

26 27 63 68

6 7

26 27 63 68

6 7

26 27 63 68

6 7

26 27 63 68

6 7

26 27 63 68

7

22 66

7

22 66

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7

10 11 44 61

6 7

17 22 31 32

6 7

17 22 31 32

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 22 31 32

7

22 66

7

34 35

6 7

10 11 44 61

6 7

10 11 44 61

6 7

21 22 44 64

6 7

21 22 32 66

6 7

21 22 44 64

7

16 22

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7

17 19 21 22

24 28 32 35 36 42 52 62 66 67

68 69 71 82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

35 44 45 59 60 62 63 64 73

6 7

35 44 45 59 60 62 63 64 73

6 7

35 44 45 59 60 62 63 64 73

6 7

35 44 45 59 60 62 63 64 73

6 7

35 44 45 59 60 62 63 64 73

6 7

35 44 45 59 60 62 63 64 73

7

16 22

7

19 22

7

19 22

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

7

45 61 65

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

35 44 45 59 60 62 63 64 73

6 7

35 44 45 59 60 62 63 64 73

7

35 36

7

35 36

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68 6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7

21 22 32 66

6 7

17 22 31 32

7

35 36

6 7

17 22 31 32

6 7

21 22 44 64

7

25 63

7

25 63

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7 8

29 37 38 39 41 49 51 53

62 63 68

7

35 36

7

59 60

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

7

59 60

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

20 25 29 30 43 48 50 68

6 7

20 25 29 30 43 48 50 68

6 7

10 11 44 61

6 7

20 25 29 30 43 48 50 68

6 7

20 25 29 30 43 48 50 68

6 7

20 25 29 30 43 48 50 68

6 7

20 25 29 30 43 48 50 68

7

45 61 65

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67 6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

7

34 35

7

34 35

7

34 35

6 7

21 22 44 64

6 7

17 22 31 32

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

7

34 35 36

6 7

17 23 53 66

6 7

17 22 31 32

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27

35

37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27

35

37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12

17 18 20 21 22 23 26 27 35 37

41

43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57

58 61 66

67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43

45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12

17 18 20 21 22 23 26 27 35 37

41

43 45 46 47 49 53 57 58 61

66 67 68

69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27

35

37 41 43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12

17 18 20 21 22 23 26 27 35 37

41

43 45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57

58 61 66

67 68 69 71 72 82

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43

45 46 47 49 53 57 58 61 66 67 68 69 71 72 82

6 7

12

17 18 20 21 22 23 26 27 35 37

41

43 45 46 47 49 53 57 58 61

66 67 68

69 71 72 82 6 7

12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69

71 72 82

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47

49 53 57 58 61 66 67 68 69 71 72 82

6 7

12

17 18 20 21 22 23 26 27 35 37

41

43 45 46 47 49 53 57 58 61

66 67 68 69 71 72

82

7

34 35 36

7

34 35 36

6 7

17 23 53 66

6 7

17 23 53 66

6 7

26 27 28 63 68

6 7

26 27 28 63 68

6 7

26 27 28 63 68

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

6 7

20 25 29 30 43 48 50 68

6 7

20 25 29 30 43 48 50 68

6 7

20 25 29 30 43 48 50 68

6 7

20 25 29 30 43 48 50 68

6 7

17 22 31 32

6 7

17 22 31 32

6 7

20 25 29 30 43 48 50 68

6 7

37 42 47 49 61 64 65 67 68

70 72

6 7

37 42 47 49 61 64 65 67 68

70 72

6 7

37 42 47 49 61 64 65 67 68

70 72

6 7

37 42 47 49 61 64 65 67 68

70 72

6 7

37 42 47 49 61 64 65 67 68

70 72

6 7

37 42 47 49 61 64 65 67

68 70 72

6 7

37 42 47 49 61 64 65 67 68

70 72 6 7

37 42 47 49 61 64 65 67 68

70 72 6 7

37 42 47 49 61 64 65 67 68

70 72

6 7

37 42 47 49 61 64 65 67 68

70 72

7

45 61 65

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

26 27 28 63 68

6 7

17 23 53 66

6 7

26 27 28 63 68

6 7

26 27 28 63 68

6 7

37 42 47 49 61 64 65 67 68

70 72 6 7

37 42 47 49 61 64 65 67 68

70 72

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

7

34 35 36

6 7

21 22 32 66

6 7

17 19 21 22 24 28 32 35 36 42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36 42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36 42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36 42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35 36 42 52 62 66 67

68 69 71 82

6 7

10 11 15 22 37 66 67 68

82

6 7

10 11 15 22 37 66 67 68

82 6 7

10 11 15 22 37 66 67 68

82

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7

26 27 28 63 68

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

BI

IN

OUT

IN

BI

OUT

IN

OUT

BI

IN

OUT

IN

OUT

IN

OUT OUT OUT

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(RIGHT)

Other Board Pogos

(Keyboard Protector)

Memory Signals

Bosses

Board Mounting Holes

MCP Thermal Module Holes

DisplayPort Signals

Place VIAs in corresponding hole’s ground ring.

NOTE: VIAs represent non-plated holes with ground rings.

CPU Signals

Power Signals

Fan Screw Hole

PCIe Signals

(Internal pull-up)

CPU Thermal Module Holes

(ORIGIN)

PEG Signals

USB Signals

(Not to scale)

(UPPER)

(LOWER)

Audio Signals

Ethernet Signals

(Internal pull-up)

GMUX Signals

(FW800)

FireWire Signals

Left Speaker Standoffs

SO-DIMM Pogos

(Near IPD Connector)

(SD Card)

Digital Ground

(Mini-DP)

(Near BIL Connector)

(Audio)

(Upper USB)

(Lower USB)

CPU Pogo

(LEFT)

(Aliases on page70.csa)

(Internal pull-up)

LVDS Signals

(Ethernet)

I/O Row Pogos

(IPD Protector)

1/16W

5%

402

MF-LF

47K

R0930

1

2

0

MF-LF 402

5% 1/16W

NOSTUFF

R0925

1

2

16 35

10K

5% 1/16W MF-LF 402

R0902

1

2

SM

XW0901

12

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0910

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0912

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0911

1

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0913

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0902

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0900

1

2.0DIA-TALL-EMI-MLB-M97-M98

SM

SH0903

1

8

17 69 77

8

17 69 77

8

17 69 77

8

17 69 77

8

17 69 77

8

17 69 77

8

17 69 77

8

17 69 77

6

69

6

69

17 77

8

17 77

8

17 77

6

69

6

69

8

17 77

8

17 77

8

17 72 73 74

8

17 72 73 74

8

16 77

8

16 77

8

16 77

8

16 77

8

16

8

17 73

8

17 69

8

17 73

8

17 69

8

18

8

18

8

16

6 8

17 69

6 8

17 69

6 8

17 69

6 8

17 69

8

16 77

8

16 77

10 75

9

75

8

24 63 68

8

24 63 68

13

61 75

8

61

8

16

5%

20K

402

1/16W MF-LF

R0920

1

2

8

13

8

16

8

16 77

8

16 77

8

16

8

17

8

19 78

8

19 78

8

19 78

8

19 78

8

19 78

8

19 78

8

19 78

8

19 78

18 58

8

20 32

8

20 32

8

20 32

8

31

8

17

8

17

8

17

8

26

8

27

8

34 35

8

18 35

8

18 35

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0985

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0981

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0986

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0982

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0984

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0930

1

STDOFF-4.0OD3.0H-TH

ZT0934

1

TH

SL-3.1X2.7-6CIR-NSP

ZT0950

1

STDOFF-4.0OD3.0H-TH

ZT0935

1

3R2P5

ZT0990

1

3R2P5

ZT0960

1

STDOFF-4.5OD.98H-1.1-3.48-TH

ZT0988

1

3R2P5

ZT0940

1

3R2P5

ZT0915

1

22

5% 1/16W MF-LF 402

R0931

1

2

SM

1.4DIA-SHORT-EMI-MLB-M97-M98

SH0914

1

8

31

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0915

1

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

SH0916

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0906

1

SM

2.0DIA-TALL-EMI-MLB-M97-M98

SH0905

1

3R2P5

ZT0942

1

HOLE-VIA-P5RP25

ZT0965

1

HOLE-VIA-P5RP25

ZT0945

1

6 8

40 62 67

6 8

40 62 67

4.0OD1.85H-M1.6X0.35

ZT0952

1

4.0OD1.85H-M1.6X0.35

ZT0951

1

SYNC_DATE=01/13/2009

SYNC_MASTER=WFERRY_K19I

Signal Aliases

8

83

A

051-7903

LVDS_DDC_DATA

MAKE_BASE=TRUE

LVDS_DDC_DATA

LCD_BKLT_PWM

NC_LVDS_IG_B_DATAN<3>

LVDS_IG_B_DATA_N<0..2>

LVDS_IG_B_DATA_P<0..2>

LVDS_IG_A_DATA_N<0..2>

MAKE_BASE=TRUE

LVDS_CONN_A_CLK_N

MAKE_BASE=TRUE

LVDS_CONN_A_CLK_P

PCIE_FW_PRSNT_L

TP_PCIE_EXCARD_PRSNT_L

GND_CHASSIS_AUDIO_JACK

LVDS_IG_A_DATA_P<0..2>

MAKE_BASE=TRUE

LVDS_CONN_A_DATA_N<0..2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAP<3>

GND_BATT_CHGND

NC_MEM_B_A<15>

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MEM_A_A<15>

NO_TEST=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

SMC_PM_G2_EN

MAKE_BASE=TRUE

SMC_PM_G2_EN

TP_GMUX_JTAG_TCK_L

MAKE_BASE=TRUE

TP_GMUX_JTAG_TCK_L TP_GMUX_JTAG_TDI

MCP_HPLUG_DET2

MAKE_BASE=TRUE

MCP_HPLUG_DET2

TP_GMUX_JTAG_TDO

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDO

TP_GMUX_JTAG_TMS

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDI

MAKE_BASE=TRUE

RTL8211_CLK125

MAKE_BASE=TRUE

RTL8211_CLK125

MAKE_BASE=TRUE

MEM_VTT_EN MEM_VTT_EN

=PEG_R2D_C_N<0..15>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_CLK100MN

NO_TEST=TRUE

NC_PEG_CLK100MP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_CLK100M_EXCARDP

MAKE_BASE=TRUE

NC_PCIE_CLK100M_EXCARDN

NO_TEST=TRUE

NC_PCIE_EXCARD_R2DCP

MAKE_BASE=TRUE

CPU_BSEL<0..2>

IMVP6_VID<0..6>

NC_RTL8211_REGOUT

GND

MCP_MII_PD

RTL8211_VDDREG

MAKE_BASE=TRUE

RTL8211_VDDREG

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

NO_TEST=TRUE

PM_SLP_RMGT_L

AUD_IPHS_SWITCH_EN

NC_USB_EXTDP

NC_USB_EXTCN

NC_USB_EXTCP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_EXCARDP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_USB_EXCARDN

NO_TEST=TRUE

NC_USB_MININ

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_MINIP

MAKE_BASE=TRUE

NC_USB_EXTDP

NO_TEST=TRUE

NC_USB_EXTCP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_USB_EXTCN

MAKE_BASE=TRUE

MCP_MII_PD

PM_SLP_RMGT_L

MAKE_BASE=TRUE

LVDS_CONN_B_CLK_N

LVDS_CONN_B_DATA_P<0..2>

MAKE_BASE=TRUE

=MCP_BSEL<0..2>

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

NO_TEST=TRUE

NC_PEG_R2DCP<0..15>

MAKE_BASE=TRUE

=PEG_D2R_N<0..15>

TP_PEG_PRSNT_L

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PCIE_EXCARD_R2DCN

MAKE_BASE=TRUE

TP_IMVP6_CLKEN_L

TP_PEG_PRSNT_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2RN<0..15>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_PEG_D2RP<0..15>

MAKE_BASE=TRUE

TP_EXCARD_CLKREQ_L

NO_TEST=TRUE

NC_PCIE_EXCARD_D2RP

MAKE_BASE=TRUE

NC_PEG_CLK100MP

=PEG_R2D_C_P<0..15>

MAKE_BASE=TRUE

LVDS_CONN_A_DATA_P<0..2>

LVDS_CONN_A_CLK_P LVDS_CONN_A_CLK_N

MAKE_BASE=TRUE

LVDS_CONN_B_CLK_P LVDS_CONN_B_CLK_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_DATAP<3>

MAKE_BASE=TRUE

LVDS_CONN_B_DATA_N<0..2>

MAKE_BASE=TRUE

LCD_PWR_EN

MAKE_BASE=TRUE

LVDS_DDC_CLK

NC_PEG_CLK100MN

NC_PCIE_CLK100M_EXCARDN

PM_SLP_RMGT_L

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_AUDIO_AMP

PP5V_S3

TP_IMVP6_CLKEN_L CPU_VID<0..6>

MAKE_BASE=TRUE

NC_USB_EXTDN

=PEG_D2R_P<0..15>

NC_PCIE_EXCARD_R2DCP NC_PCIE_EXCARD_R2DCN

TP_PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PCIE_EXCARD_D2RN NC_PCIE_EXCARD_D2RN

NC_PCIE_EXCARD_D2RP

NC_USB_EXCARDN

NC_USB_EXCARDP

NC_USB_MININ

MAKE_BASE=TRUE

NC_USB_EXTDN

NO_TEST=TRUE

NC_USB_MINIP

MAKE_BASE=TRUE

NC_PEG_R2DCN<0..15>

NO_TEST=TRUE

TP_CPU_PECI_MCP

FW643_WAKE_L

NC_PCIE_CLK100M_EXCARDP

TP_GMUX_JTAG_TMS

TP_EXCARD_CLKREQ_L

LVDS_BKL_ON

MAKE_BASE=TRUE

LVDS_BKL_ON

LVDS_DDC_CLK

NC_MEM_B_A<15>

NC_MEM_A_A<15>

MAKE_BASE=TRUE

FW643_WAKE_L

NC_LVDS_IG_A_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>NC_LVDS_IG_A_DATAN<3>

LVDS_CONN_B_CLK_P

NO_TEST=TRUE

NC_LVDS_IG_B_DATAN<3>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAP<3>

FW_PLUG_DET_L

LCD_PWR_EN

MAKE_BASE=TRUE

FW_PLUG_DET_L

GND

MIN_NECK_WIDTH=0.20MM VOLTAGE=0V

MIN_LINE_WIDTH=0.50MM

57

8

17 77

6

59

8

27

8

26

8

16

8

17

8

16

8

18

8

18

8

16 77

8

16 77

8

16 77

8

16 77

8

16 77

8

31

8

31

8

31

8

19 78

8

19 78

8

19 78

8

19 78

8

19 78

8

19 78

8

19 78

8

17

8

13

16

8

16 77

8

61

8

16

8

16

8

16 77

8

17 77

56

6 7

29 37 38 39 41 49 51 53

62 63 68

8

16

8

16 77

8

19 78

16

8

34 35

8

17 77

8

17 77

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

CPU JTAG Support

PLACEMENT_NOTE (all 4 resistors):

1%

1/16W

54.9

MF-LF

402

R1000

1

2

68

5% 1/16W MF-LF

402

R1002

1

2

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.

402

1K

MF-LF

1% 1/16W

R1005

1

2

PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

1% MF-LF

2.0K

1/16W

402

R1006

1

2

Place within 12.7mm of CPU

54.9

1% 1/16W MF-LF

402

R1023

1

2

Place within 12.7mm of CPU

27.4

1% 1/16W MF-LF 402

R1022

1

2

Place within 12.7mm of CPU

402

MF-LF

1/16W

1%

54.9

R1021

1

2

Place within 12.7mm of CPU

27.4

1% 1/16W MF-LF 402

R1020

1

2

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

13 61 75

13 75

61

12 13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

8

75

8

75

8

75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

6

13 75

12 75

1 9

12 75

12 24

13 41 61 75

46 82

13 41 75

13 75

12 13 75

13 75

9

12 75

9

12 75

9

12 75

9

12 75

46 82

13 75

NO STUFF

5%

MF-LF

1/16W

0

402

R1010

1 2

NO STUFF

1/16W

5%

MF-LF

1K

402

R1011

1

2

54.9

402

MF-LF

1%

1/16W

R1001

1

2

54.9

1/16W MF-LF

1%

402

R1090

1 2

1%

MF-LF

1/16W

54.9

402

R1091

1 2

1%

MF-LF

1/16W

54.9

402

R1093

1 2

13 75

1%

MF-LF

1/16W

649

402

R1094

1 2

402

MF-LF

1K

5% 1/16W

NO STUFF

R1012

1

2

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

NO STUFF

X5R

0.1uF

10% 16V

402

C1014

1

2

FCBGA

PENRYN

OMIT

U1000

B22

B23 C21

R26

U26

AA1 Y1

E22

F24

J24 J23

H22

F26 K22

H23

N22

K25

P26 R23

E26

L23

M24 L22

M23 P25

P23

P22 T24

R24

L25

G22

T25

N25

Y22

AB24 V24

V26

V23 T22

U25 U23

F23

Y25

W22 Y23

W24

W25 AA23

AA24

AB25

AE24

AD24

G25

AA21 AB22

AB21

AC26 AD20

AE22 AF23

AC25

AE21 AD21

E25

AC22

AD23 AF22

AC23

E23 K24

G24

H25

N24

U22

AC20

E5 B5

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6 D7

C23 D25

C24

AF26

AF1

A26

C3

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

54.9

1/16W MF-LF

1%

402

R1092

1 2

FCBGA

OMIT

PENRYN

U1000

N3

P5 P2

L2

P4 P1

R1

Y2

U5

R3 W6

A6

U4

Y5 U1

R4 T5

T3

W2 W5

Y4

J4

U2 V4

W3

AA4 AB2

AA3

L5

L4

K5 M3

N2

J1

H1

M1

V1

A22 A21

E2

AD4 AD3

AD1

AC4

G5

F1

C20

E1

H5

F21

A5

G6 E4

D20

C4

B3

C6

B4

H4

AC2

AC1

D21

K3

H2 K2

J3

L1

C1 F3

F4 G3

M4

N5

T2 V3

B2

F6 D2

D22

D3

A3

D5

AC5

AA6

AB3

A24

B25

C7

AB5

G2

AB6

SYNC_DATE=02/05/2009

SYNC_MASTER=K24_MLB

CPU FSB

9

A

051-7903

83

XDP_TDI

XDP_TDO

XDP_TMS

FSB_D_L<0> FSB_D_L<1> FSB_D_L<2> FSB_D_L<3> FSB_D_L<4> FSB_D_L<5> FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9> FSB_D_L<10> FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_DSTB_L_N<0> FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24> FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30> FSB_D_L<31> FSB_DSTB_L_N<1> FSB_DSTB_L_P<1> FSB_DINV_L<1>

CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>

TP_CPU_TEST5

TP_CPU_TEST3

TP_CPU_TEST6

TP_CPU_TEST7

FSB_CPUSLP_L CPU_PSI_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_N<3> FSB_DSTB_L_P<3>

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

XDP_TRST_L

XDP_TCK

CPU_GTLREF CPU_TEST1 CPU_TEST2

CPU_TEST4

CPU_COMP<1>

CPU_COMP<0>

CPU_COMP<2> CPU_COMP<3>

PP1V05_S0

FSB_LOCK_L

CPU_INIT_L

FSB_A_L<3> FSB_A_L<4>

FSB_A_L<14>

FSB_A_L<16>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD_B2

TP_CPU_RSVD_V3

TP_CPU_RSVD_T2

TP_CPU_RSVD_N5

TP_CPU_RSVD_M4

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

CPU_THERMD_N

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

TP_CPU_RSVD_F6 TP_CPU_RSVD_D2 TP_CPU_RSVD_D22 TP_CPU_RSVD_D3

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26>

FSB_A_L<25>

FSB_A_L<27> FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_A20M_L CPU_FERR_L CPU_IGNNE_L

CPU_STPCLK_L

CPU_SMI_L

CPU_NMI

CPU_INTR

FSB_A_L<6>

9

12 75

1 9

12 75

9

12 75

9

12 75

9

12 75

25 75

75

6 7

10 11 12 13 16 17 19 21 22

23 35 61 65 66 67

75

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

2500 mA (after VCC stable)

4500 mA (before VCC stable)

(Socket-P KEY)

41 A (SV HFM)

130 mA

(CPU CORE POWER)

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

23 A (LV Design Target)

44 A (SV Design Target)

(BR1#)

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

30.4 A (SV LFM)

8

75

8

75

8

75

8

75

8

75

8

75

PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

R1101

1

2

8

75

61 75

PENRYN

OMIT

FCBGA

U1000

A7

A9

B9 B10

B12

B14 B15

B17

B18 B20

C9 C10

A10

C12

C13 C15

C17

C18

D9

D10

D12 D14

D15

A12

D17

D18

E7

E9

E10

E12 E13

E15

E17 E18

A13

E20

F7

F9

F10 F12

F14

F15 F17

F18

F20

A15

AA7

AA9

AA10

AA12

AA13 AA15

AA17

AA18 AA20

AB9

A17

AC10 AB10

AB12 AB14

AB15

AB17 AB18

AB20

AB7

AC7

A18

AC9

AC12

AC13 AC15

AC17 AC18

AD7

AD9 AD10

AD12

A20

AD14 AD15

AD17

AD18 AE9

AE10 AE12

AE13

AE15 AE17

B7

AE18

AE20 AF9 AF10

AF12

AF14 AF15

AF17

AF18 AF20

B26 C26

G21 V6

R21

R6

T21 T6

V21

W21

J6 K6

M6

J21 K21

M21

N21 N6

AF7

AD6 AF5

AE5

AF4 AE3

AF3

AE2

AE7

OMIT

PENRYN

FCBGA

U1000

A4 A8

B11

W1

W4 W23

W26 Y3

Y6 Y21

Y24

AA2 AA5

B13

AA8

AA11 AA14

AA16

AA19 AA22

AA25 AB1

AB4

AB8

B16

AB11

AB13

AB16 AB19

AB23

AB26 AC3

AC6

AC8

AC11

B19

AC14

AC16 AC19

AC21

AC24 AD2 AD5 AD8

AD11 AD13

B21

AD16

AD19 AD22

AD25

AE1

AE4 AE8

AE11

AE14 AE16

B24

AE19

AE23 AE26

A2 AF6

AF8

AF11 AF13

AF16

AF19

C5

AF21

A25

AF25

B1

C8

C11

C14

A11

C16

C19

C2 C22

C25

D1

D4

D8 D11

D13

A14

D16 D19

D23

D26

E3

E6

E8

E11 E14

E16

A16

E19

E21 E24

F5

F8 F11

F13 F16

F19

F2

A19

F22

F25

G4

G1

G23

G26

H3

H6 H21

H24

A23

J2

J5

J22

J25

K1

K4

K23 K26

L3

L6

AF2

L21

L24

M2

M5

M22 M25

N1

N4 N23

N26

B6

P3

P6

P21 P24

R2

R5 R22

R25 T1

T4

B8

T23 T26

U3 U6

U21 U24

V2

V5

V22 V25

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

R1100

1

2

8310

A

051-7903

SYNC_DATE=02/05/2009

SYNC_MASTER=K24_MLB

CPU Power & Ground

PPVCORE_S0_CPU

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

PP1V5_S0

PP1V05_S0

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

PPVCORE_S0_CPU

CPU_VCCSENSE_P

CPU_VCCSENSE_N

6 7

10 11 44 61

6 7

11 15 22 37 66 67 68 82

6 7 9

11 12 13 16 17 19 21 22

23 35 61 65 66 67

6 7

10 11 44 61

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACEMENT_NOTE (C1200-C1219):

1x 10uF, 1x 0.01uF

1x 330uF, 6x 0.1uF 0402

SYNC FROM T18 REMOVE NO STUFF CAPS C1220 TO C1231

CPU VCore HF and Bulk Decoupling

REMOVE C1244 & C1245 CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)

4X 330UF. 20X 22UF 0805

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

PLACEMENT_NOTE (C1240-C1243):

CRITICAL

CERM-X5R

6.3V

20%

22UF

Place inside socket cavity on secondary side.

805

C1206

1

2

2.0V

D2T-SM2

PLACEMENT_NOTE=Place C1260 between CPU & NB.

POLY-TANT

CRITICAL

330UF

20%

C1260

1

2 3

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1204

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1216

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1214

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1208

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1203

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1207

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1202

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1201

1

2

CRITICAL

Place inside socket cavity on secondary side.

22UF

805

20%

6.3V CERM-X5R

C1213

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1212

1

2

CERM-X5R

6.3V

20%

805

22UF

CRITICAL

Place inside socket cavity on secondary side.

C1211

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1219

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1200

1

2

CRITICAL

6.3V

Place inside socket cavity on secondary side.

CERM-X5R

20%

805

22UF

C1210

1

2

10V

402

0.1UF

20% CERM

C1261

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1205

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1209

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1215

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V CERM-X5R

C1217

1

2

10V

402

0.1UF

CERM

20%

C1262

1

2

10V

402

0.1UF

CERM

20%

C1263

1

2

10V

402

0.1UF

CERM

20%

C1264

1

2

0.1UF

CERM

10V

402

20%

C1265

1

2

10V

402

0.1UF

CERM

20%

C1266

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1218

1

2

PLACEMENT_NOTE=Place C1281 near CPU pin B26.

10%

402

CERM

16V

0.01UF

C1251

1

2

6.3V 603

X5R

20%

10uF

C1250

1

2

470UF-4MOHM

CRITICAL

Place on secondary side.

NOSTUFF

20%

D2T-SM

POLY-TANT

2.0V

C1240

1

23

470UF-4MOHM

CRITICAL

Place on secondary side.

D2T-SM

20%

2.0V POLY-TANT

C1241

1

23

CRITICAL

470UF-4MOHM

Place on secondary side.

D2T-SM

POLY-TANT

20%

2.0V

C1242

1

23

CRITICAL

Place on secondary side.

D2T-SM

470UF-4MOHM

2.0V

20%

POLY-TANT

C1243

1

23

CPU Decoupling

SYNC_DATE=02/05/2009

SYNC_MASTER=K24_MLB

8311

A

051-7903

PPVCORE_S0_CPU

PP1V5_S0

PP1V05_S0

6 7

10 44 61

6 7

10 15 22 37 66 67 68 82

6 7 9

10 12 13 16 17 19 21 22

23 35 61 65 66 67

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

BI BI

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MCP79-specific pinout

Use with 920-0620 adapter board to support CPU, MCP debugging.

OBSFN_A0 OBSFN_A1

OBSDATA_A0

OBSDATA_A2

OBSFN_B1

OBSDATA_B0 OBSDATA_B1 OBSDATA_D1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4 ITPCLK#/HOOK5

998-1571

Direction of XDP module

OBSFN_C1

OBSDATA_C2

OBSFN_B0

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

XDP_PRESENT#

OBSDATA_B3

OBSFN_D1

PWRGD/HOOK0

OBSDATA_B2

TCK1

OBSDATA_D0

TMS

HOOK1

HOOK2 HOOK3

TRSTn

SDA SCL

OBSFN_D0

RESET#/HOOK6

TDI

TDO

VCC_OBS_AB

NOTE: This is not the standard XDP pinout.

on even-numbered side of J1300

Please avoid any obstructions

DBR#/HOOK7

VCC_OBS_CD

Mini-XDP Connector

OBSDATA_C3

OBSDATA_C1

OBSDATA_C0

OBSFN_C0

OBSDATA_A1

OBSDATA_A3

TCK0

9

13 75

XDP

1K

MF-LF

402

5%

1/16W

R1399

1 2

20 26 27 43 78

20 26 43 78

XDP

54.9

MF-LF

402

1%

1/16W

R1315

1

2

XDP

0.1uF

X5R 402

10% 16V

C1300

1

2

XDP

0.1uF

X5R 402

10% 16V

C1301

1

2

9

75

9

75

9

75

9

13 75

PLACEMENT_NOTE=Place close to CPU to minimize stub.

XDP

1K

MF-LF

402

5%

1/16W

R1303

1 2

9

75

9

75

9

75

9

75

20

18 78

20

1

20

13 75

1 9

75

9

75

9

75

9

75

9

24

18

XDP_CONN

CRITICAL

LTH-030-01-G-D-NOPEGS

F-ST-SM

J1300

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

78 9

SYNC_DATE=02/05/2009

051-7903

SYNC_MASTER=K19_MLB

12

A

83

eXtended Debug Port(MiniXDP)

FSB_CPURST_L

CPU_PWRGD

XDP_TMS

XDP_TDO XDP_TRST_L XDP_TDI

FSB_CLK_ITP_N

FSB_CLK_ITP_P

MCP_DEBUG<5>

JTAG_MCP_TMS

MCP_DEBUG<3>

MCP_DEBUG<1>

JTAG_MCP_TRST_L

JTAG_MCP_TDOXDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<2>

XDP_BPM_L<1> XDP_BPM_L<0>

TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B0

XDP_PWRGD

TP_XDP_OBSDATA_B3

XDP_OBS20

PM_LATRIGGER_L JTAG_MCP_TCK

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

XDP_TCK

MCP_DEBUG<0>

XDP_DBRESET_L

XDP_CPURST_L

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<4>

JTAG_MCP_TDI

MCP_DEBUG<2>

TP_XDP_OBSDATA_B2

PP1V05_S0

PP3V3_S0

XDP_BPM_L<3>

TP_XDP_OBSFN_B0

75

6 7 9

10 11 13 16 17 19 21 22

23 35 61 65 66 67

6 7

17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

BI BI BI

BI

IN

BI

OUT

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

IN

BI BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28# CPU_A29# CPU_A30# CPU_A31# CPU_A32#

CPU_A22# CPU_A23# CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2# CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6# CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15# CPU_A16#

CPU_A19#

CPU_A17# CPU_A18#

CPU_A20# CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT# CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0# CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4# CPU_D5# CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17# CPU_D18#

CPU_D16#

CPU_D19# CPU_D20# CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24# CPU_D25# CPU_D26# CPU_D27# CPU_D28# CPU_D29# CPU_D30# CPU_D31# CPU_D32# CPU_D33# CPU_D34# CPU_D35# CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39# CPU_D40# CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44# CPU_D45# CPU_D46# CPU_D47#

CPU_D52# CPU_D53# CPU_D54# CPU_D55# CPU_D56# CPU_D57# CPU_D58# CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK# CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD +V_PLL_MCLK +V_PLL_FSB +V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY# CPU_DRDY#

CPU_REQ1#

FSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Loop-back clock for delay matching.

(MCP_BSEL<2>) (MCP_BSEL<1>) (MCP_BSEL<0>)

20 mA 29 mA 15 mA

206 mA270 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

8

9

75

9

12 75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

9

75

9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

6 9

75

9

75

9

75

9

75

6 9

75

9

75

6 9

75

6 9

75

9

75

9

75

9

75

9

75

9

75

9

75

12 75

9

75

9

75

9

75

9

75

9

75

9

75

9

75

9

75

9

12 75

9

75

9

75

9

75

9

75

9

61 75

8

9

41 61 75

9

41 75

9

75

9

75

49.9

1/16W

1%

402

MF-LF

R1436

1

2

1/16W

1%

402

MF-LF

49.9

R1431

1

2

49.9

MF-LF

402

1%

1/16W

R1430

1

2

49.9

1/16W

1%

402

MF-LF

R1435

1

2

NO STUFF

1K

402

5% 1/16W MF-LF

R1422

1

2

1K

NO STUFF

402

MF-LF

5%

1/16W

R1421

1

2

1K

5%

402

MF-LF

NO STUFF

1/16W

R1420

1

2

1/16W

402

MF-LF

62

5%

R1415

1

2

1/16W

402

MF-LF

54.9

1%

R1410

1

2

NO STUFF

150

1/16W 402

MF-LF

5%

R1440

1

2

OMIT

MCP79-TOPO-B

(1 OF 11)

BGA

U1400

AK41 AJ40

G41

G42

AL42

AL43

AK42

AL41

AM40

AM39

AF35 AG35 AG39 AE33 AG37 AG38 AG34 AN38 AL39 AG33 AL33

AF41

AJ33 AN36 AJ35 AJ37 AJ36 AJ38 AL37 AL34 AN37

AC34

AJ34 AL38 AL35 AN34 AR39 AN35

AE38 AE34 AC37 AE37 AE35 AB35

AD42

AE36 AK35

AD43

AA41

AE40 AL32

F41

D42

F42

AM42

AM43

Y43 W42

R42 T39 T42 T41 R41 T43 W35 AA37 W33 W34

Y40

AA36 AA34 AA38 AA35 U38 U36 U35 U33 U34 W38

W41

R33 U37 N34 N33 R34 R35 P35 R39 R37 R38

Y39

L37 L39 L38 N36 N38 J39 J38 J37 L42 M42

V42

P41 N41 N40 M40 H40 K42 H41 L41 H43 H42

Y41

K41 J40 H39 M43

Y42 P42 U41

V41

V35

N35

J41

AD39

AA40

AN32

AN33 AM32

AD41

U40

W37

L36

M41

T40

W39

N37

M39

AH40

AB42 AD40

AH39 AH42 AF42

AC43

AG41

E41

AJ41

AH43

AC38 AA33 AC39 AC33 AC35

H38

AC41 AB41 AC42

AM33

AH41

AG42

AG43

AE41

AG27

AH28

AG28

AH27

1/16W 402

MF-LF

62

5%

R1416

1

2

A

SYNC_DATE=02/05/2009

MCP CPU Interface

051-7903

8313

SYNC_MASTER=T18_MLB

PM_THRMTRIP_L

FSB_D_L<13>

MCP_BCLK_VML_COMP_GND

FSB_DPWR_L

CPU_DPSLP_L

FSB_D_L<38>

FSB_D_L<43>

FSB_D_L<45>

CPU_DPRSTP_L

CPU_STPCLK_L

FSB_CPUSLP_L

FSB_CPURST_L

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_A20M_L

FSB_CLK_MCP_P FSB_CLK_MCP_N

FSB_CLK_ITP_N

FSB_CLK_ITP_P

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_DEFER_L

FSB_BPRI_L

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<44>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<37>

FSB_D_L<36>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

FSB_D_L<32>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

MCP_CPU_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

FSB_RS_L<2>

FSB_RS_L<1>

CPU_PROCHOT_L

TP_CPU_PECI_MCP

FSB_TRDY_L

FSB_LOCK_L

FSB_HITM_L

FSB_HIT_L

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_ADSTB_L<1>

FSB_ADSTB_L<0>

FSB_A_L<35>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

FSB_A_L<16>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<12>

FSB_A_L<11>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<4>

FSB_A_L<3>

FSB_DINV_L<3>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

PP1V05_S0

PP1V05_S0_MCP_PLL_FSB

FSB_D_L<14>

FSB_D_L<7>

FSB_A_L<10>

FSB_A_L<25>

FSB_A_L<34>

FSB_A_L<33>

FSB_DBSY_L FSB_DRDY_L

FSB_BNR_L

FSB_RS_L<0>

CPU_FERR_L

FSB_BREQ0_L

FSB_ADS_L

FSB_BREQ1_L

PP1V05_S0

=MCP_BSEL<2>

=MCP_BSEL<0>

=MCP_BSEL<1>

75

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

22

75

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1 MCKE0A_0

MODT0A_1 MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8 MA0_7

MA0_9

MA0_10

MA0_11

MA0_13 MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2 MDQM0_1 MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4 MDQ0_3 MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15 MDQ0_14 MDQ0_13 MDQ0_12

MDQ0_16

MDQ0_21 MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25 MDQ0_24 MDQ0_23 MDQ0_22

MDQ0_26

MDQ0_29 MDQ0_28 MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35 MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40 MDQ0_39

MDQ0_42

MDQ0_47 MDQ0_46

MDQ0_43

MDQ0_45 MDQ0_44

MDQ0_51 MDQ0_50 MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55 MDQ0_54 MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61 MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60 MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56 MDQ1_55 MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51 MDQ1_50

MDQ1_48 MDQ1_47 MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42 MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36 MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31 MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26 MDQ1_25 MDQ1_24 MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11 MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6 MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4 MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N MDQS1_0_P MDQS1_0_N

MRAS1# MCAS1#

MWE1#

MBA1_2 MBA1_1 MBA1_0

MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6 MA1_5 MA1_4 MA1_3 MA1_2 MA1_1 MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1# MCS1A_0#

MCLK1A_0_N

MODT1A_1 MODT1A_0

MCKE1A_0

MCKE1A_1

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BGA

MCP79-TOPO-B

OMIT

(2 OF 11)

U1400

AR19

AT19

AN19

AW21

AN23

AU15

AR23

AU19

AV19

AN21

AR21

AP21

AU21

AR22

AV21

AW17

AP19

AP23

AP17

AT23

AU23

BC20

BB20

AY24

BA24

AV33

AW33

AR18

AT15

AP35

AR35

AV31

AT31

AW37

AV37

AR33

AU31

AN31

AV29

AN29

AV27

AW38

AR31

AP31

AR29

AP29

AR27

AP27

AR25

AP25

AU27

AT27

AV38

AU25

AR26

AU13

AR14

AT11

AR11

AW13

AV13

AV11

AU11

AR38

AV9

AU9

AY5

AW6

AP11

AW9

AU8

AU7

AV5

AU6

AR37

AR5

AN10

AW5

AV6

AR7

AR6

AN7

AN6

AL7

AL6

AV39

AN9

AP9

AL9

AL8

AW39

AU37

AT37

AR34

AV35

AW29

AN27

AN13

AR10

AU5

AN5

AT39

AU39

AU35

AT35

AU29

AU30

AW25

AV25

AR13

AP13

AW8

AW7

AR9

AR8

AL11

AL10

AV15

AP15

AV17

AR17

26 76

27 76

BGA

MCP79-TOPO-B

OMIT

(3 OF 11)

U1400

BA18

BB25

BA17

BC28

AW28

BA14

BA29

BA25

BB26

BA26

BA27

AY27

BA28

AY28

BB28

BB17

BB18

BB29

BA15

BB30

AY31

AY19

BA19

BA22

BB22

BB42

BA42

BB16

BB14

AP42

AR41

BC40

BA40

AV41

AV42

AW40

BB40

AY39

BA38

BB36

BA36

AU41

AY40

BA39

AW36

BC36

AY35

BA34

BB32

BA32

AY36

BA35

AU40

AW32

BC32

BA12

AY12

BB9

BB8

AW12

BB12

BB10

BA9

AN40

AY8

BA7

BC4

BB4

BC8

BA8

BA5

BB5

BB2

BA3

AP41

AW3

AW4

BC3

BB3

AY3

AY4

AU3

AU2

AR3

AR4

AT41

AV3

AV2

AT3

AT4

AT40

AW41

AW42

AR42

AY43

BB38

BB34

BA11

AY7

BA2

AT5

AT43

AT42

AY42

BA43

BA37

BB37

BA33

BB33

AY11

BA10

BA6

BB6

AY1

AY2

AT1

AT2

AY15

BB13

AW16

BA16

27 76

83

051-7903

A

14

SYNC_MASTER=T18_MLB

SYNC_DATE=02/05/2009

MCP Memory Interface

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_DQ<0>

MEM_B_DQ<1>

MEM_B_DQ<2>

MEM_B_DQ<3>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<9>

MEM_B_DQ<10>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<14>

MEM_B_DQ<15>

MEM_B_DQ<16>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<19>

MEM_B_DQ<20>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<25>

MEM_B_DQ<26>

MEM_B_DQ<27>

MEM_B_DQ<28>

MEM_B_DQ<29>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<38>

MEM_B_DQ<39>

MEM_B_DQ<40>

MEM_B_DQ<41>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_DQ<44>

MEM_B_DQ<45>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<49>

MEM_B_DQ<50>

MEM_B_DQ<51>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_A_DM<0>

MEM_A_DM<1>

MEM_A_DM<2>

MEM_A_DM<3>

MEM_A_DM<4>

MEM_A_DM<5>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQ<0>

MEM_A_DQ<1>

MEM_A_DQ<2>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<6>

MEM_A_DQ<7>

MEM_A_DQ<8>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<15>

MEM_A_DQ<16>

MEM_A_DQ<17>

MEM_A_DQ<18>

MEM_A_DQ<19>

MEM_A_DQ<20>

MEM_A_DQ<21>

MEM_A_DQ<22>

MEM_A_DQ<23>

MEM_A_DQ<24>

MEM_A_DQ<25>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<28>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<31>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<36>

MEM_A_DQ<37>

MEM_A_DQ<38>

MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<42>

MEM_A_DQ<43>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<49>

MEM_A_DQ<50>

MEM_A_DQ<51>

MEM_A_DQ<52>

MEM_A_DQ<53>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<59>

MEM_A_DQ<60>

MEM_A_DQ<61>

MEM_A_DQ<62>

MEM_A_DQ<63>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_CS_L<1>

MEM_B_CLK_N<0>

MEM_B_CLK_P<0>

MEM_B_CLK_N<1>

MEM_B_CLK_P<1>

TP_MEM_B_CLK2N

TP_MEM_B_CLK2P

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MEM_B_DQS_P<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CS_L<0>

MEM_A_CS_L<1>

MEM_A_CLK_N<0>

MEM_A_CLK_P<0>

MEM_A_CLK_N<1>

MEM_A_CLK_P<1>

NC_MEM_A_CLK2N

TP_MEM_A_CLK2P

MEM_A_A<0>

MEM_A_A<1>

MEM_A_A<2>

MEM_A_A<3>

MEM_A_A<4>

MEM_A_A<5>

MEM_A_A<6>

MEM_A_A<7>

MEM_A_A<8>

MEM_A_A<9>

MEM_A_A<10>

MEM_A_A<11>

MEM_A_A<12>

MEM_A_A<13>

MEM_A_A<14>

MEM_A_BA<0>

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_WE_L

MEM_A_CAS_L

MEM_A_RAS_L

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_N<3>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

MEM_A_DQS_P<5>

MEM_A_DQS_N<6>

MEM_A_DQS_P<6>

MEM_A_DQS_N<7>

MEM_A_DQS_P<7>

6

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55 GND56 GND57 GND58

GND60

GND59

GND61 GND62 GND63 GND64

GND52 GND53 GND54

GND51

GND49 GND50

GND48

GND47

GND46

GND44 GND45

GND43

GND42

GND41

GND39 GND40

GND38

GND37

GND36

GND35

GND33 GND34

GND32

GND31

GND30

GND28 GND29

GND27

GND26

GND25

GND24

GND18 GND19

GND17

GND16

GND15

GND13 GND14

GND10

GND12

GND11

GND8 GND9

GND7

GND6

GND5

GND2 GND3 GND4

GND1

MEM_COMP_VDD MEM_COMP_GND

MODT0B_0 MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0# MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE +V_VPLL

+VDD_MEM1 +VDD_MEM2 +VDD_MEM3 +VDD_MEM4 +VDD_MEM5 +VDD_MEM6 +VDD_MEM7 +VDD_MEM8

+VDD_MEM9 +VDD_MEM10 +VDD_MEM11

+VDD_MEM14 +VDD_MEM15 +VDD_MEM16 +VDD_MEM17 +VDD_MEM18 +VDD_MEM19 +VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23 +VDD_MEM24 +VDD_MEM25 +VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31 +VDD_MEM32 +VDD_MEM33 +VDD_MEM34

+VDD_MEM38 +VDD_MEM39 +VDD_MEM40 +VDD_MEM41

+VDD_MEM43 +VDD_MEM44 +VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22 GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

4771 mA (A01, DDR3)

17 mA 12 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

19 mA

TP or NC for DDR2.

39 mA

87 mA (A01)

1%

40.2

1/16W

402

MF-LF

R1610

1

2

MF-LF

402

1%

1/16W

40.2

R1611

1

2

(4 OF 11)

MCP79-TOPO-B

OMIT

BGA

U1400

AA22

AA39 AB22

AB7 AD22 AE20 AF24 AG24 AH35

AK7 AM28

AP12

AT25 AP30 AR36 AU10

F28 BC21

AY9

BC9

D34

F24

G30

G32

H31

K7

M38

M5 M6 M7 M9

N39

N8

P10

P33

P34

P37

P4

P40

P7 R36 R40 R43

R5

T10

T18 T20

AK11

T24 T26

T33 T34 T35 T37 T38

T6

T7 T9 U18 U20 U22

V10 V34

W5

AV23 AN25

BA30 BA31

BB21

BA21

BC24

BB24

AU34

AU33

AY20

BA20

BA23

AY23

BB41

BA41

AU17 AR15

BC16 BA13

AM41

AN41

AN17 AN15

AY16 BC13

AY32

U27

U28

T27

T28

AM17

AN20 AN24 AT17 AP16 AN22 AP20 AP24 AV16 AR16 AR20

AM19

AR24 AW15 AP22 AP18 AU16 AN18 AU24 AT21 AY29 AV24

AM21

AU20 AU22 AW27 BC17 AV20 AY17 AY18 AM15 AU18 AY25

AM23

AY26 AW19 AW24 BC25 AL30 AM31

AM25 AM27 AM29 AN16 BC29

28

MCP Memory Misc

15 83

A

051-7903

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

TP_MEM_B_CKE<3>

NC_MEM_B_CKE<2>

TP_MEM_B_CS_L<2>

MCP_MEM_RESET_L

PP1V5_S0

MCP_MEM_COMP_GND

TP_MEM_A_CLK4N NC_MEM_A_CLK3P

NC_MEM_A_ODT<2> NC_MEM_A_ODT<3>

NC_MEM_A_CKE<2> NC_MEM_A_CKE<3>

TP_MEM_A_CLK5P TP_MEM_A_CLK5N

NC_MEM_A_CLK4P

NC_MEM_A_CLK3N

TP_MEM_A_CS_L<2> NC_MEM_A_CS_L<3>

PP1V05_S0_MCP_PLL_CORE

TP_MEM_B_CLK5P NC_MEM_B_CLK5N

NC_MEM_B_CLK4P NC_MEM_B_CLK4N

NC_MEM_B_CLK3P TP_MEM_B_CLK3N

TP_MEM_B_CS_L<3>

NC_MEM_B_ODT<2> TP_MEM_B_ODT<3>

PP1V5_S0

MCP_MEM_COMP_VDD

6

6 7

10 11 15 22 37 66 67 68 82

76

6

22

6

6 7

10 11 15 22 37 66 67 68

82

76

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7 +AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N PE0_TX15_P

PE0_TX13_N PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N

PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N PE0_TX6_P

PE0_TX4_N PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16 PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17 PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18 PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

OUT

OUT OUT

OUT

IN IN

IN

IN IN

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

Minimum 1.025V for Gen2 supportMinimum 1.025V for Gen2 support

Int PU

84 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

Int PU

206 mA (A01, AVDD0 & 1)

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

57 mA (A01, DVDD0 & 1)

Int PU (S5)

MCP79-TOPO-B

(5 OF 11)

OMIT

BGA

U1400

Y12

AC12 AD12 V12 W12

AA12 AB12 M12 P12 R12 N12 T12 U12

M13 N13 P13

T17 W19 U17 V19 W16 W17 W18 U16

T19 U19

T16

C9 D11

E11

E7

F7

L8

L9

L6

L7

N10

N11

P9

N9

N6

N7

N4

N5

C7

D7

F6

E6

F5

E5

E3

E4

D3

C3

H5

G5

J6

J7

J4

J5

L10

L11

D4

C5

J1

H1

J3

J2

K3

K2

L3

L4

M3

M4

M1

M2

B4

C4

A3

A4

B2

B3

D1

C1

E1

D2

F2

E2

F4

F3

H4

G3

H2

H3

F11

G11

J9

K9

G9

H9

E9

F9

G7

H7

C8

D8

A8

B8

B7

A7

C6

B6

J10

J11

F13

G13

H13

J13

K14

L14

M14

N14

F17

D5 D9

E8

C10

M15 B10

L16 L18

M16

M18

M17 M19

A11

K11

8

77

8

77

8

6

29 77

6

29 77

8

35

6

29

34 77

8

77

8

77

29

8

29 77

34 77

8

77

8

77

29 77

8

77

8

77

8

2.37K

402

MF-LF

1% 1/16W

NO STUFF

PLACEMENT_NOTE=Place within 12.7mm of U1400

R1710

1

2

24 35

8

58

30

SYNC_MASTER=T18_MLB

MCP PCIe Interfaces

16 83

A

051-7903

SYNC_DATE=02/05/2009

CARDREADER_RESET

PCIE_WAKE_L

PCIE_MINI_D2R_N

MINI_CLKREQ_L

GND

PP1V05_S0

GND

PCIE_FW_D2R_N

NC_PEG_D2RP<0>

NC_PEG_D2RN<2>

PP1V05_S0_MCP_PLL_PEX

NC_PEG_D2RN<0>

NC_PEG_D2RP<2>

NC_PEG_D2RP<4>

NC_PEG_D2RP<6>

PCIE_MINI_PRSNT_L

NC_PCIE_PE4_R2D_CN

TP_PCIE_PE4_R2D_CP

NC_PCIE_EXCARD_R2DCN

PCIE_FW_R2D_C_N NC_PCIE_EXCARD_R2DCP

PCIE_MINI_R2D_C_N PCIE_FW_R2D_C_P

TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P

NC_PCIE_CLK100M_PE5N

NC_PCIE_CLK100M_PE5P

NC_PCIE_CLK100M_PE6P

NC_PCIE_CLK100M_PE4N

NC_PCIE_CLK100M_PE4P

NC_PCIE_CLK100M_EXCARDN

PCIE_CLK100M_FW_N

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

NC_PEG_CLK100MN

NC_PEG_CLK100MP

PCIE_CLK100M_MINI_P

NC_PEG_R2DCN<15>

NC_PEG_R2DCN<14> NC_PEG_R2DCP<15>

NC_PEG_R2DCN<13> NC_PEG_R2DCP<14>

NC_PEG_R2DCN<12>

NC_PEG_R2DCP<12>

NC_PEG_R2DCP<13>

NC_PEG_R2DCN<11>

NC_PEG_R2DCP<11>

NC_PEG_R2DCN<10>

NC_PEG_R2DCN<9> NC_PEG_R2DCP<10>

NC_PEG_R2DCN<8>

NC_PEG_R2DCP<8>

NC_PEG_R2DCP<9>

NC_PEG_R2DCN<7>

NC_PEG_R2DCP<7>

NC_PEG_R2DCN<6>

NC_PEG_R2DCN<5> NC_PEG_R2DCP<6>

NC_PEG_R2DCN<4> NC_PEG_R2DCP<5>

NC_PEG_R2DCN<3>

NC_PEG_R2DCP<3>

NC_PEG_R2DCP<4>

NC_PEG_R2DCN<2>

NC_PEG_R2DCP<2>

NC_PEG_R2DCN<0>

NC_PEG_R2DCN<1>

NC_PEG_R2DCP<1>

NC_PEG_R2DCP<0>

MCP_PEX_CLK_COMP

NC_PCIE_PE4_D2RN

TP_PCIE_PE4_D2RP

NC_PCIE_EXCARD_D2RN

PCIE_FW_D2R_P

NC_PCIE_EXCARD_D2RP

PCIE_MINI_D2R_P

TP_PEG_PRSNT_L

NC_PEG_D2RN<13> NC_PEG_D2RP<14>

NC_PEG_D2RP<15>

NC_PEG_D2RP<12>

NC_PEG_D2RP<11>

NC_PEG_D2RP<13>

NC_PEG_D2RN<11>

NC_PEG_D2RN<12>

NC_PEG_D2RN<10>

NC_PEG_D2RP<8>

NC_PEG_D2RP<9>

NC_PEG_D2RP<10>

NC_PEG_D2RN<8>

NC_PEG_D2RN<9>

NC_PEG_D2RN<5>

NC_PEG_D2RP<7>

NC_PEG_D2RN<6>

NC_PEG_D2RN<7>

NC_PEG_D2RP<3>

NC_PEG_D2RP<5>

NC_PEG_D2RN<3>

NC_PEG_D2RN<4>

NC_PEG_D2RP<1> NC_PEG_D2RN<1>

PCIE_FW_PRSNT_L

FW_CLKREQ_L

NC_PCIE_CLK100M_EXCARDP

TP_EXCARD_CLKREQ_L

TP_GMUX_JTAG_TCK_L

NC_PEG_D2RN<14>

NC_PEG_D2RN<15>

TP_GMUX_JTAG_TDO

PP1V05_S0_MCP_PEX_AVDD

NC_PE4_PRSNT_L

TP_PCIE_EXCARD_PRSNT_L

TP_PE4_CLKREQ_L

AUD_IP_PERIPHERAL_DET

6 7 9

10 11 12 13 17 19 21 22

23 35 61 65 66 67

22

6

77

6

7

22

6

IN

BI

OUT

IN IN IN IN

IN IN

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT

OUT OUT

IN IN

OUT OUT

OUT OUT OUT

OUT OUT

IN

OUT

IN IN IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P HDMI_TXD0_N/ML0_LANE2_N HDMI_TXD1_P/ML0_LANE1_P HDMI_TXD1_N/ML0_LANE1_N HDMI_TXD2_P/ML0_LANE0_P HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36 MII_COL/GPIO_20/MSMB_DATA MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44 TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1 +3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT

BI

OUT

BI

OUT

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

In MCP79 these pins have undocumented internal

GPIOs 57-59 (if LCD panel is used):

by default, pull-downs (1K or stronger) must be used.

pull-ups (~10K to 3.3V S0). To ensure pins are low

Alias to GMUX_INT for systems with GMUX. Alias to HPLUG_DET2 for other systems. Pull-down (20k) required in all cases.

=DVI_HPD_GMUX_INT: Alias to DVI_HPD for systems using IFP for DVI.

(See below)

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: 20K pull-down required on DP_HPD_DET.

level-shifters.

NOTE: HDMI port requires level-shifting. IFP interface can be used to provide HDMI or dual-channel TMDS without

Interface Mode

DP_IG_ML_P/N<0>

DP_IG_DDC_DATA DP_IG_HPD DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

131 mA (A01)

83 mA (A01)

MII, RGMII products will enable

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

RGB DAC Disable:

TV / Component

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

LVDS: Power +VDD_IFPx at 1.8V

95 mA (A01)

16 mA (A01)

8 mA

DP_IG_AUX_CH_P/N

=MCP_HDMI_HPD

TMDS_IG_HPD

=MCP_HDMI_DDC_DATA

=MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_TXD_P/N<1>

=MCP_HDMI_DDC_CLK

MCP Signal

=MCP_HDMI_TXD_P/N<0>

=MCP_HDMI_TXC_P/N

TMDS/HDMI TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<1> TMDS_IG_TXD_P/N<2>

TMDS_IG_DDC_DATA

TP_DP_IG_AUX_CHP/N

DP_IG_DDC_CLK

DP_IG_ML_P/N<2> DP_IG_ML_P/N<1>

DP_IG_ML_P/N<3>

DisplayPort

5 mA (A01)

RGB ONLY

avoids a leakage issue since

feature via software. This

NOTE: All Apple products set strap to

Network Interface Select

Interface

RGMII

MII

0

1

ENET_TXD<0>

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float all TV_DAC signals.

TV DAC Disable:

Y / Y

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float all RGB_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.

103 mA 103 mA

206 mA (A01)

Comp / Pb

MCP79 requires a S5 pull-up.

C / Pr

190 mA (A01, 1.8V)

22

31 79

32 79

31 79

23 77

8

72 73 74

8

69

8

73

70

70 71 82

70 77

8

70 71

23 77

1% 1/16W MF-LF

402

49.9

R1810

1

2

1/16W MF-LF

49.9

402

1%

R1811

1

2

70

23

8

17

8

17

8

17

(6 OF 11)

BGA

MCP79-TOPO-B

OMIT

U1400

E23

B31

C30

D31

A31

B30

E31

C43

D43

E16 B15

J31

E35

D35

F35

G35

G33

F33

H33

J33

J30

C31 F31

C35

B35

A32

B32

C32

D32

C33

D33

C34

B34

E32 G31

K31

L31

H29

J29

K29

L29

K30

L30

M30

N30

G39 E37 F40

B26

B27

C27

B22

J23

F23

E28

J24 K24

T23

U23 V23

M29

M28

J32 K32

T25

M27 M26

B40

A39

A40

B39

C39 B38

A41

J22

D21 C21

G23

A23 C22

C23 B23 E24 A24

D24 C26

B24 C24 C25 D25

C36

B36

D36

A36

E36 A35

C37

C38 D38

10K

402

1/16W

5% MF-LF

R1850

1

2

402

5%

100K

1/16W MF-LF

R1861

1

2

402

MF-LF

5%

1/16W

100K

R1860

1

2

42

5%

47K

402

MF-LF

1/16W

R1820

1

2

31 79

8

69 77

8

69 77

8

77

8

77

8

77

31 79

8

77

8

77

8

77

8

77

8

77

8

69 77

8

69 77

8

77

8

77

8

77

31 79

8

77

8

77

8

77

8

77

8

77

6 8

69

6 8

69

70

23 77

31 79

23 77

31 79

17 83

A

051-7903

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

MCP Ethernet & Graphics

MCP_HPLUG_DET2

LCD_BKLT_PWM

NC_MCP_CLK27M_XTALOUT

NC_MCP_RGB_DAC_RSET NC_MCP_RGB_DAC_VREF

LPCPLUS_GPIO

PP1V05_ENET

PP3V3_S5

PP3V3_ENET

PP3V3_S0

PP3V3_ENET

ENET_TXD<0> ENET_TXD<1> ENET_TXD<2> ENET_TXD<3>

ENET_CLK125M_TXCLK ENET_TX_CTRL

MCP_MII_VREF

NC_CRT_IG_VSYNC

NC_CRT_IG_HSYNC

NC_CRT_IG_B_COMP_PB

MCP_MII_PD

NC_ENET_PWRDWN_L

ENET_MDC

ENET_RESET_L

ENET_RXD<1> ENET_RXD<2>

ENET_CLK125M_RXCLK ENET_RX_CTRL

ENET_RXD<3>

NC_ENET_INTR_L

ENET_RXD<0>

NC_MCP_TV_DAC_RSET

MCP_IFPAB_VPROBE

MCP_IFPAB_RSET

DP_IG_DDC_CLK DP_IG_DDC_DATA

NC_LVDS_IG_B_DATAN<3>

NC_LVDS_IG_B_DATAP<3>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_N<1> LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_P<1>

LVDS_CONN_B_CLK_N

LVDS_CONN_B_CLK_P

LVDS_IG_A_DATA_N<2> NC_LVDS_IG_A_DATAP<3>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<0>

LVDS_CONN_A_CLK_P

NC_CRT_IG_G_Y_Y

NC_CRT_IG_R_C_PR

NC_MCP_RGB_VSYNC

NC_MCP_RGB_HSYNC

NC_MCP_RGB_BLUE

NC_MCP_RGB_GREEN

NC_MCP_RGB_RED

MCP_DDC_CLK0 MCP_DDC_DATA0

MCP_CLK25M_BUF0_R

ENET_MDIO

DP_HPD

DP_IG_AUX_CH_N

DP_IG_AUX_CH_P

NC_MCP_TV_DAC_VREF

LVDS_DDC_CLK LVDS_DDC_DATA

NC_MCP_CLK27M_XTALIN

DP_ML_N<0>

=MCP_HDMI_TXC_P

LVDS_BKL_ON LCD_PWR_EN

MCP_MII_COMP_VDD MCP_MII_COMP_GND

PP3V3_S0_MCP_DAC

PP1V8_S0

PP3V3_S0_MCP_VPLL

PP1V05_S0

PP1V05_ENET_MCP_PLL_MAC

DP_IG_CA_DET

MCP_HDMI_VPROBE

MCP_HDMI_RSET

NC_LVDS_IG_A_DATAN<3>

LVDS_CONN_A_CLK_N

DP_ML_P<0>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_N<0>

23

6 7

22 31 32

6 7

19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 22 31 32

6 7

12 18 20 21 22 23 26 27 35

37 41 43 45 46 47 49 53 57 58

61 66 67 68 69 71 72 82

6 7

17 22 31 32

6

23

79

23

6 7

23 53 66

23

6 7 9

10 11 12 13 16 19 21 22

23 35 61 65 66 67

22

OUT

BI BI BI BI

LPC PCIGND

PCI_INTW# PCI_INTX# PCI_INTY# PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0# LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5 PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10 PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15 PCI_AD16 PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21 PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66 GND67

GND69

GND68

GND70 GND71 GND72

GND74

GND73

GND75 GND76 GND77

GND79

GND78

GND80 GND81

GND84

GND83

GND82

GND85 GND86 GND87

GND89

GND88

GND90 GND91 GND92

GND94

GND93

GND95 GND96 GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR# PCI_STOP#

PCI_RESET0# PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105 GND106 GND107

GND109

GND108

GND110 GND111 GND112

GND115

GND114

GND113

GND116 GND117

GND120

GND119

GND118

GND121 GND122 GND123

GND125

GND124

GND126 GND127 GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR# PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS# PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0# PCI_REQ1#/FANRPM2

IN

BI

OUT

IN

OUT

BI BI BI BI BI BI BI BI

OUT

OUT OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU Int PU Int PU

Int PU (S5)

40 42 78

24 78

40 42 78

BGA

(7 OF 11)

MCP79-TOPO-B

OMIT

U1400

AB18 H34 AB20 AB21 AB23 AB24 AB25 AB26 AB27 AB28 AB34 AB37 AB4 AB40 AC22 AC36 AC40 AB33 AC5 AD16 AD17 AD18 AD19 AD20 AD24 AD25 AD26 AD27 AD28 AD33 AD34

U24 U26 U39

U4

U8 V16 V17 V18 V20 V22 V24 V26 V27 V28 V33 V37

V4 V40

V7 W20 W22 W24 W36 W40 W43 Y16 Y17 Y18 Y19 Y20 Y22 Y24 Y25

Y26 Y27

AD3 AD2 AD1 AD5

AE9

AE1

AE2

AD4 AE12

AE5

AE6

AC3

AE10

AC9

AC10 AC11

AA1 AA5

Y5

W3

W6

W4

W7

AC4

V3

W8

V2

W9

U3 W11

U2

U5

U1

U6

AE11

T5

U7

AB3 AC6 AB2 AC7 AC8 AA2

AA3 AA6 AA11 W10

R6 R7 R8

R9

AD11

AA9 Y4

R3 U10 R4 U11 P3

P2

N3

N2

N1

AA10 Y1 AB9

T1

T2

V9

T3

U9

T4

R10 R11

AA7 Y2

Y3

40 42

40 42 24 78

40 42

PLACEMENT_NOTE=Place close to pin R8

MF-LF 402

1/16W

5%

22

R1910

1

2

402

MF-LF1/16W

5%

8.2K

R1989

1 2

402

MF-LF1/16W

5%

8.2K

R1991

1 2

402

MF-LF1/16W

5%

8.2K

R1990

1 2

402

MF-LF1/16W

5%

8.2K

R1994

1 2

8.2K

5%

1/16W MF-LF

402

R1992

1 2

18

MF-LF 402

1/16W

5%

10K

R1961

1

2

1/16W MF-LF

402

22

5%

R1960

1 2

5%

1/16W MF-LF22402

R1950

1 2

5%

1/16W MF-LF22402

R1951

1 2

22

5%

1/16W MF-LF

402

R1952

1 2

402

MF-LF1/16W

5%

22

R1953

1 2

24

8

35

18

18 35

12

12 78

8

58

8

051-7903

A

8318

MCP PCI & LPC

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

NC_PCI_INTX_L

FW_PWR_EN

PCI_REQ1_L

PCI_REQ0_L

MCP_RS232_SOUT_L

LPC_AD<1>

LPC_AD<3>

LPC_AD<2>

LPC_FRAME_L

LPC_AD<0>

NC_PCI_GNT0_L NC_PCI_GNT1_L

MCP_RS232_SOUT_L

NC_PCI_C_BE_L<0> NC_PCI_C_BE_L<1> NC_PCI_C_BE_L<2> NC_PCI_C_BE_L<3>

NC_PCI_DEVSEL_L NC_PCI_FRAME_L NC_PCI_IRDY_L TP_PCI_PAR

NC_PCI_SERR_L NC_PCI_STOP_L

PM_LATRIGGER_L

NC_PCI_RESET1_L

NC_PCI_CLK0

LPC_AD_R<0> LPC_AD_R<1> LPC_AD_R<2> LPC_AD_R<3>

LPC_CLK33M_SMC_R

LPC_FRAME_R_L

LPC_RESET_L

LPC_PWRDWN_L

PCI_CLK33M_MCP_R

NC_PCI_CLK1

PCI_CLK33M_MCP

MEM_VTT_EN_R

NC_PCI_PERR_L

NC_PCI_AD<9>

NC_PCI_AD<11>

NC_PCI_AD<10>

NC_PCI_AD<8>

PCI_REQ1_L

PCI_REQ0_L

NC_PCI_AD<15>

TP_PCI_INTY_L

NC_PCI_TRDY_L

NC_PCI_INTW_L

NC_PCI_AD<31>

NC_PCI_AD<30>

NC_PCI_AD<29>

NC_PCI_AD<28>

NC_PCI_AD<27>

NC_PCI_AD<26>

NC_PCI_AD<25>

NC_PCI_AD<24>

NC_PCI_AD<23>

NC_PCI_AD<22>

NC_PCI_AD<21>

NC_PCI_AD<20>

NC_PCI_AD<19>

NC_PCI_AD<18>

NC_PCI_AD<17>

NC_PCI_AD<16>

NC_PCI_AD<14>

NC_PCI_AD<13>

NC_PCI_AD<12>

FW_PWR_EN AUD_IPHS_SWITCH_EN MCP_RS232_SIN_L

MCP_DEBUG<0> MCP_DEBUG<1> MCP_DEBUG<2> MCP_DEBUG<3> MCP_DEBUG<4> MCP_DEBUG<5> MCP_DEBUG<6> MCP_DEBUG<7>

MCP_RS232_SIN_L

PP3V3_S0

PM_CLKRUN_L

LPC_SERIRQ

NC_LPC_DRQ0_L

FW_PLUG_DET_L

NC_PCI_INTZ_L

TP_GMUX_JTAG_TMS TP_GMUX_JTAG_TDI

6

18 35

18 78

18

6

78

6

78

6 6

6

18 78

6

18

6 7

12 17 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

6

BI BI

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158 GND159

GND157

GND156

GND155

GND153 GND154

GND152

GND151

GND150

GND148 GND149

GND147

GND146

GND145

GND143 GND144

GND142

GND141

GND140

GND139

GND136

GND133 GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26 USB_OC2#/GPIO_27/MGPIO USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1 +DVDD0_SATA2 +DVDD0_SATA3 +DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1 +AVDD0_SATA2 +AVDD0_SATA3 +AVDD0_SATA4 +AVDD0_SATA5 +AVDD0_SATA6 +AVDD0_SATA7 +AVDD0_SATA8 +AVDD0_SATA9

+AVDD1_SATA1 +AVDD1_SATA2 +AVDD1_SATA3 +AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT OUT

IN

OUT OUT

IN IN

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ExpressCard

SD Card Reader

External C

Minimum 1.025V for Gen2 support

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

84 mA (A01)

43 mA (A01, DVDD0 & 1)

Minimum 1.025V for Gen2 support

19 mA (A01)

External B

IR

Bluetooth

Camera

External A

External D

AirPort (PCIe Mini-Card)

Geyser Trackpad/Keyboard

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

127 mA (A01, AVDD0 & 1)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

38 78

8

78

8

78

8

78

8

78

6

29 78

6

29 78

39 78

48 78

6

29 78

6

29 78

38 78

8

78

8

78

8

78

8

78

MF-LF

1% 1/16W

402

2.49K

R2010

1

2

806

MF-LF

1%

1/16W

402

R2060

1

2

5%

8.2K

MF-LF

1/16W 402

R2053

1

2

1/16W MF-LF

402

5%

8.2K

R2052

1

2

5%

8.2K

1/16W 402

MF-LF

R2051

1

2

8.2K

402

MF-LF

1/16W

5%

R2050

1

2

(8 OF 11)

MCP79-TOPO-B

OMIT

BGA

U1400

AD35 AD37 AD38 AE22 AE24 AE39 AE4 AD6 AF16 AF17 AF18 AF20 AF22 AF26 AF27 AF28 AF33 AF34 AF37 AF40 AG18 AG20 AG22 AG26 AG36 AG40 AH18 AH20 AH22 AH24

AJ12 AN11 AK12 AK13 AL12 AM11 AM12 AN12 AL13

AN14 AL14 AM13 AM14

AF19 AG16 AG17 AG19

AH17 AH19

AE16

L28

AJ5 AJ4

AJ6

AJ7

AJ9 AK9

AJ10

AJ11

AJ2 AJ1

AJ3

AK2

AL4 AK3

AL3

AM4

AM2 AM3

AM1

AN1

AN3 AN2

AP2

AP3

E12

AE3

D29

C29

G25

F25

L23

K23

D28

C28

B28

A28

G29

F29

L27

K27

J27

J26

G27

F27

E27

D27

L25

K25

J25

H25

L21 K21 J21 H21

A27

37 77

30 78

SYNC_MASTER=T18_MLB

MCP SATA & USB

051-7903

A

8319

SYNC_DATE=02/05/2009

GND

PP1V05_S0

SATA_ODD_D2R_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

SATA_HDD_D2R_N SATA_HDD_D2R_P

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

NC_SATA_C_D2RP

TP_SATA_C_D2RN

PP1V05_S0_MCP_PLL_SATA

USB_BT_P

USB_TPAD_N

USB_TPAD_P

USB_IR_N

USB_IR_P

USB_CAMERA_N

USB_CAMERA_P

NC_USB_EXTDN

NC_USB_EXTDP

NC_USB_MININ

USB_EXTA_N

USB_EXTA_P

MCP_SATA_TERMP

TP_SATA_F_D2RP

TP_SATA_F_D2RN

TP_SATA_F_R2D_CN

TP_SATA_E_D2RN

NC_SATA_C_R2D_CN

NC_SATA_C_R2D_CP

TP_MCP_SATALED_L

NC_SATA_D_D2RN

TP_SATA_E_R2D_CP TP_SATA_E_R2D_CN

TP_SATA_E_D2RP

NC_SATA_D_D2RP

GND

PP1V05_S0_MCP_SATA_AVDD

TP_SATA_F_R2D_CP

TP_SATA_D_R2D_CP

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

USB_EXTC_OC_L

PP3V3_S5

NC_USB_MINIP

TP_SATA_D_R2D_CN

USB_BT_N

USB_EXTA_OC_L

USB_CARDREADER_N

USB_CARDREADER_P

NC_USB_10P

EXCARD_OC_L

USB_EXTB_OC_L

SATA_ODD_D2R_N

NC_USB_EXTCP NC_USB_EXTCN

NC_USB_10N

NC_USB_EXCARDN

USB_EXTB_P USB_EXTB_N

NC_USB_EXCARDP

6 7 9

10 11 12 13 16 17 21 22

23 35 61 65 66 67

6

22

77

6

7

22

78

6 7

17 21 22 24 28 32 35 36 42

52 62 66 67 68 69 71 82

38

6

38

6

OUT

BI

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

IN IN

OUT

IN

IN IN IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID* LLB*

PWRBTN* RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10 SPI_CLK/GPIO_11

SPI_DI/GPIO_8 SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1 +V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN

OUT

IN

OUT

IN

OUT

IN

IN IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

HDA Output Caps

(MGPIO2)

(MGPIO3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PU

25 MHz

42 MHz

0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0 1

1

0

SPI_CLK

SPI_DO

0

1 1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0 SPI1

I/F HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by default, LPC+ debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PU

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

(MXM_OK for MXM systems)

SAFE mode: For ROMSIP recovery

USER mode: Normal

Connects to SMC for automatic recovery.

42 78

6

32 35 40 67 71

6

38 40 41 67

12 26 43 78

43 58 72 78

12 26 27 43 78

43 58 72 78

20 64

46 82

20 64

20 29 32

46 82

8

32

61 75

40

53 78

MF-LF

1/16W

1%

402

49.9K

R2121

1

2

1%

49.9K

MF-LF

402

1/16W

R2120

1

2

1K

MF-LF

1% 1/16W

402

R2190

1

2

24 78

40

MF-LF

402

5%

22

1/16W

R2170

1 2

MF-LF

5%

1/16W

402

22

R2171

1 2

5%

22

MF-LF

1/16W

402

R2173

1 2

402

5%

10K

MF-LF

1/16W

R2163

1

2

MF-LF

8.2K

5% 1/16W

402

R2160

1

2

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

R2180

1

2

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

R2181

1

2

402

5%

22

1/16W MF-LF

R2172

1 2

42

49.9

MF-LF

1/16W

1%

402

R2110

1

2

402

1/16W MF-LF

5%

10K

R2150

1

2

12

1

12

10PF

50V

5%

402

CERM

C2171

1

2

50V

10PF

5%

402

CERM

C2173

1

2

50V

10PF

5%

402

CERM

C2170

1

2

50V

10PF

5%

402

CERM

C2172

1

2

BGA

(9 OF 11)

MCP79-TOPO-B

OMIT

U1400

K13

AE7

M22

C17 D17

C18

A12

C12

B12

D12

L26

L24

E15

K17 L17

A15

K15

G15

J14

J15

F15

L15

B20

G19

E19 F19 J19 J18

L13

M25 M24

L20 M20 M21

J16 K16

AE18 AE17

L22

E20

C16

D20

D16

C20

C19

J17

G17

H17

M23

L19

G21

K19

F21

D13

C14

C15 B14

C13

B18

K22

C11

B11

A16

A19

B16

B19

37

20 58

24 24

32 35 40 41

20 26 27 40

402

1/16W MF-LF

5%

100K

R2147

1

2

10K

5% 1/16W

402

MF-LF

R2142

1

2

402

1/16W MF-LF

5%

10K

R2141

1

2

22K

5% MF-LF

1/16W 402

R2157

1

2

22K

5% MF-LF

1/16W 402

R2156

1

2

402

1/16W

22K

5% MF-LF

R2155

1

2

402

MF-LF

5% 1/16W

100K

R2151

1

2

1/16W MF-LF

5%

100K

402

R2154

2

1

MF-LF 402

1/16W

5%

10K

R2143

1

2

10K

5% MF-LF

1/16W 402

R2140

1

2

41

20 40 41

24

40

24

42 78

MCP HDA & MISC

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

20 83

A

051-7903

MCP_SPKR

PP3V3_S0

PM_SLP_S4_L

PM_SLP_S3_L

AUD_I2C_INT_L

HDA_SYNC_R

NC_MLB_RAM_SIZE

TP_MLB_RAM_VENDOR

SMC_ADAPTER_EN

SMC_IG_THROTTLE_L

MEM_EVENT_L

PP3V3_S0

SMC_WAKE_SCI_L

MEM_EVENT_L ODD_PWR_EN_L

HDA_RST_R_L

HDA_SYNC

ARB_DETECT

SM_INTRUDER_L

PM_RSMRST_L

JTAG_MCP_TRST_L

MCP_TEST_MODE_EN

JTAG_MCP_TMS

MCP_VID<1> MCP_VID<2>

HDA_BIT_CLK_R HDA_RST_R_L

HDA_SDOUT_R

HDA_SYNC_R

PP3V3_S0

PP3V42_G3H

HDA_SDOUT

HDA_BIT_CLK

HDA_RST_L

TP_MCP_KBDRSTIN_L

PM_SYSRST_DEBOUNCE_L

MCP_THMDIODE_N

SMBUS_MCP_0_CLK

SPI_MOSI_R

SPI_MISO

PM_CLK32K_SUSCLK_R

JTAG_MCP_TCK

MCP_CLK25M_XTALIN MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN RTC_CLK32K_XTALOUT

SPI_CS0_R_L

PP1V05_S0_MCP_PLL_NV

MCP_HDA_PULLDN_COMP

NC_SB_A20GATE

PM_SLP_RMGT_L

MCP_VID<1>

SMC_RUNTIME_SCI_L

SPI_CLK_R

SPIROM_USE_MLB

HDA_BIT_CLK_R

HDA_SDOUT_R

PM_BATLOW_L

SMBUS_MCP_0_DATA

MCP_VID<2>

AP_PWR_EN

SMBUS_MCP_1_DATA

JTAG_MCP_TDO

JTAG_MCP_TDI

MCP_PS_PWRGD

RTC_RST_L

PM_PWRBTN_L

TP_MCP_LID_L

SMBUS_MCP_1_CLK

MCP_THMDIODE_P

MCP_VID<0>

MCP_CPUVDD_EN

HDA_SDIN0

PM_DPRSLPVR

MCP_VID<0>

MCP_CPU_VLD

MCP_GPIO_4 AUD_I2C_INT_L

PP3V3_S3

AP_PWR_EN

MCP_GPIO_4

PP3V3_S0

ARB_DETECT

TP_MCP_BUF_SIO_CLK

SMC_IG_THROTTLE_L

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49

53 57 58 61 66 67 68 69 71

72 82

20 78

6

20 40 41

20 26 27 40

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

20 78

20

20 64

20 78

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49

53 57 58 61 66 67 68 69 71

72 82

6 7

21 24 38 40 41 42 43 45

48 59 60 67

22

78

6

20 78

20 64

20

20 58

6 7

25 29 30 43 48 50 68

20 29 32

20

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43

45 46 47 49 53 57 58 61 66 67

68 69 71 72

82

20

GND

GND161

GND165 GND166

GND164

GND163

GND162

GND167 GND168

GND171

GND170

GND169

GND172 GND173

GND176

GND175

GND174

GND177 GND178

GND181

GND180

GND179

GND182 GND183 GND184

GND187

GND186

GND185

GND188 GND189

GND192

GND191

GND190

GND193 GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206 GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213 GND214

GND217

GND216

GND215

GND218 GND219

GND222

GND221

GND220

GND223 GND224 GND225

GND228

GND227

GND226

GND229 GND230

GND233

GND232

GND231

GND234 GND235

GND238

GND237

GND236

GND239 GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331 GND332

GND330

GND329

GND328

GND326 GND327

GND325

GND324

GND323

GND321 GND322

GND320

GND319

GND318

GND316 GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305 GND306 GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285 GND286

GND284

GND283

GND282

GND280 GND281

GND279

GND278

GND277

GND275 GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264 GND265 GND266

GND263

GND262

GND259 GND260 GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1 +VDD_CORE2 +VDD_CORE3 +VDD_CORE4 +VDD_CORE5 +VDD_CORE6

+VDD_CORE13 +VDD_CORE14 +VDD_CORE15 +VDD_CORE16 +VDD_CORE17 +VDD_CORE18 +VDD_CORE19

+VDD_CORE21 +VDD_CORE22 +VDD_CORE23 +VDD_CORE24 +VDD_CORE25 +VDD_CORE26 +VDD_CORE27 +VDD_CORE28 +VDD_CORE29 +VDD_CORE30

+VDD_CORE32 +VDD_CORE33 +VDD_CORE34 +VDD_CORE35 +VDD_CORE36 +VDD_CORE37

+VDD_CORE39 +VDD_CORE40 +VDD_CORE41

+VDD_CORE47 +VDD_CORE48 +VDD_CORE49 +VDD_CORE50 +VDD_CORE51 +VDD_CORE52 +VDD_CORE53 +VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55 +VDD_CORE56 +VDD_CORE57 +VDD_CORE58 +VDD_CORE59 +VDD_CORE60 +VDD_CORE61 +VDD_CORE62 +VDD_CORE63 +VDD_CORE64 +VDD_CORE65 +VDD_CORE66 +VDD_CORE67 +VDD_CORE68 +VDD_CORE69 +VDD_CORE70 +VDD_CORE71 +VDD_CORE72 +VDD_CORE73 +VDD_CORE74 +VDD_CORE75 +VDD_CORE76 +VDD_CORE77 +VDD_CORE78 +VDD_CORE79 +VDD_CORE80 +VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1 +3.3V_DUAL2 +3.3V_DUAL3 +3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3 +3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1182 mA (A01)

450 mA (A01)

266 mA (A01)

16 mA

10 uA (G3)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

80 uA (S0)

23065 mA (A01, 1.2V) 16996 mA (A01, 1.0V)

250 mA

1139 mA

43 mA

105 mA (A01)

BGA

OMIT

MCP79-TOPO-B

(11 OF 11)

U1400

AH26 AH33 AH34 AH37 AH38 AJ39

AJ8 AK10 AK33 AK34 AK37

AK4 AK40 AL36 AL40

AL5 AM10 AM16 AM18 AM20 AM22 AM24 AM26 AM30 AM34 AM35 AM37 AM38

AM5

AM6

AM7

AM9 AP26 AN28 AN30 AN39

AN4

Y7 AP10 AU26 AP14 AU14 AP28 AP32 AP34 AP36 AP37

AP4

AP40

AP7 AW23 AR28 AR32 AR40 AT10 AR12 AT13 AT29 AT33

AT6

AT7

AT9 AY21 AY22

L12 AU12 AU28 AP33 AU32 AR30 AU36 AU38

AU4

G28

F20 AV28 AV32 AV36

AV4

AV7 AW11

G20 AR43 AW43 AY10 AV12 AY30 AY33 AY34 AY37 AY38 AY41

AV40 BA1 BA4 AW31 AY6 L35 BC33 BC37 BC41 AY14 BC5 C2 D10 D14 D15 D18 D19 D22 D23 D26 D30 D37 D6 E13 E17 E21 E25 E29 E33 F12 F16 F32 F8 G10 G12 G14 G16 BC12 G22 G24 AW20 G34 G4 G43 G6 G8 H11 H15 AW35 H23 AN8 G40 J12 J8 K10 K12 K18 K26 K37 K4 K40 K8 AU1 L40 L43 L5 M10 M34 M35 M37 Y28 Y33 Y34 Y35 Y37 Y38 AB17 AB16 AN26 AD7 M11 AA4 AB19 AY13 P11 Y6 T11 V11 Y11 AH16 T22

(10 OF 11)

BGA

MCP79-TOPO-B

OMIT

U1400

AD10 AE8 AB10 AD9 Y10 AB11 AA8 Y9

G18 H19 J20 K20

G26 H27 J28 K28

A20

T21 U21 V21

AA25

AA26 AA27 AA28 AC16 AC17 AC18 AC19 AC20 AC21 AA17

AC23

AC24 AC25 AC26 AC27 AC28 AD21 AD23

W27 V25

AA18

U25

AE19 AE21 AE23 AE25 AE26 AE27 AE28 AF10 AF11 AA19

AH12

AF2 AF21 AF23 AF25

AF3

AF4

AF7 AH23

AF9 AA20

AG10

AG11 AG12 AG21 AG23 AG25

AG3

AG4 AA21

AG6

AG7

AG5

AG8

AG9

AH1 AH10 AH11

W26

AH2 AA23

W28 AH25

Y21

AH21

AH3

AH4

AH5

AH6

AH7

AH9 AA24

W21

W23

Y23

W25 AF12

AA16

R32

P31 AF32 AE32 AH32 AJ32 AK31 AK32 AD32 AL31 AB32

AC32

B41 B42 C40 C41 C42 D39 D40 D41 E38 E39

E40

F37 F38 F39 G36 G37 G38 H35 H37 J34 J35

J36

K33 K34 K35 L32 L33 L34 M31 M32 M33 N31

N32

P32 Y32 AA32

T32 U32 V32 W32

AG32

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

051-7903

A

8321

MCP Power & Ground

PP1V05_S0

PPVCORE_S0_MCP

PP3V42_G3H

PP3V3_S0

PP1V05_S5

PP3V3_S5

6 7 9

10 11 12 13 16 17 19 22

23 35 61 65

66 67

6 7

22 44 64

6 7

20 24 38 40 41 42 43 45

48 59 60 67

6 7

12 17 18 20 22 23 26 27 35

37 41 43 45

46 47 49 53 57 58 61 66 67 68

69 71 72 82

6 7

22 32 66

6 7

17 19 22 24 28 32 35 36 42

52 62 66 67

68 69 71 82

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

19 mA (A01)

450 mA (A01)

57 mA (A01) 43 mA (A01)

127 mA (A01)

206 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

562 mA (A01)

37 mA (A01)

87 mA (A01)

84 mA (A01)

83 mA (A01)

131 mA (A01)105 mA (A01)

MCP PCIE (DVDD) Power

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

16996 mA (A01, 1.0V)

23065 mA (A01, 1.2V)

(No IG vs. EG data)

MCP 1.05V RMGT Power

270 mA (A01)

MCP 3.3V Ethernet Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP79 Ethernet VRef

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 3.3V AUX/USB Power

266 mA (A01)

MCP 3.3V/1.5V HDA Power

5 mA (A01)

MCP 1.05V AUX Power

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF) Apple: 5x 2.2uF 0402 (11 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP FSB (VTT) Power

MCP Memory Power

MCP 3.3V Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP Core Power

4771 mA (A01, DDR3)

333 mA (A01)

19 mA (A01)

7 mA (A01)

1182 mA (A01)

Apple: 4x 2.2uF 0402 (8.8 uF)

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

MCP SATA (DVDD) Power

5 mA (A01)

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF) Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

402

X5R

20%

4.7UF

4V

C2582

1

2

402

X5R

4V

4.7UF

20%

C2588

1

2

402

X5R

4V

20%

4.7UF

C2584

1

2

402

X5R

20%

4.7UF

4V

C2586

1

2

6.3V

2.2UF

20% 402-LF

CERM

C2555

1

2

402

X5R

20%

4V

4.7UF

C2502

1

2

10V

10%

1UF

402-1

X5R

C2507

1

2

10V

10%

1UF

402-1

X5R

C2506

1

2

10V

10%

1UF

402-1

X5R

C2505

1

2

10V

10%

1UF

402-1

X5R

C2504

1

2

10V 402

20% CERM

0.1UF

C2511

1

2

10V 402

20% CERM

0.1UF

C2510

1

2

10V 402

20% CERM

0.1UF

C2509

1

2

10V 402

20% CERM

0.1UF

C2508

1

2

10V 402

20% CERM

0.1UF

C2513

1

2

10V 402

20% CERM

0.1UF

C2512

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2536

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2535

1

2

CERM 402-LF

20%

6.3V

2.2UF

C2534

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2533

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2532

1

2

CERM 402-LF

6.3V

2.2UF

20%

C2531

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2530

1

2

10V

10%

1UF

402-1

X5R

C2517

1

2

10V

10%

1UF

402-1

X5R

C2516

1

2

402

X5R

20%

4V

4.7UF

C2515

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2572

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2571

1

2

402

X5R

20%

4.7UF

4V

C2520

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2570

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2574

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2573

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2576

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2575

1

2

CERM 402-LF

20%

6.3V

2.2UF

C2553

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2552

1

2

CERM 402-LF

20%

6.3V

2.2UF

C2551

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2550

1

2

10V 402

CERM

20%

0.1UF

C2549

1

2

10V 402

CERM

20%

0.1UF

C2548

1

2

10V 402

CERM

20%

0.1UF

C2547

1

2

10V 402

CERM

20%

0.1UF

C2546

1

2

10V 402

CERM

20%

0.1UF

C2545

1

2

10V 402

CERM

20%

0.1UF

C2544

1

2

10V 402

CERM

20%

0.1UF

C2543

1

2

10V 402

0.1UF

CERM

20%

C2542

1

2

10V 402

20% CERM

0.1UF

C2541

1

2

402

X5R

4V

4.7UF

20%

C2540

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2562

1

2

6.3V

2.2UF

20%

402-LF

CERM

C2564

1

2

402

X5R

4V

20%

4.7UF

C2580

1

2

30-OHM-5A

0603

L2570

1 2

0603

30-OHM-5A

L2575

1 2

0402

30-OHM-1.7A

L2582

1 2

0402

30-OHM-1.7A

L2584

1 2

0402

30-OHM-1.7A

L2588

1 2

30-OHM-1.7A

0402

L2586

1 2

30-OHM-1.7A

0402

L2555

1 2

402

X5R

20%

4V

4.7UF

C2500

1

2

402

X5R

20%

4V

4.7UF

C2501

1

2

0402

30-OHM-1.7A

L2580

1 2

10V 402

0.1uF

20% CERM

C2526

1

2

10V 402

0.1uF

20% CERM

C2525

1

2

CERM 402-LF

20%

2.2UF

6.3V

C2560

1

2

10V 402

20%

0.1UF

CERM

C2589

1

2

10V 402

20%

0.1UF

CERM

C2590

1

2

402

X5R

4V

4.7UF

20%

C2595

1

2

0402

30-OHM-1.7A

L2595

1 2

402

MF-LF

1%

1/16W

1.47K

R2590

1

2

10V 402

20% CERM

0.1UF

C2591

1

2

402

1.47K

1/16W

1%

MF-LF

R2591

1

2

17

10V 402

0.1uF

20% CERM

C2521

1

2

10V 402

CERM

20%

0.1uF

C2518

1

2

10V 402

20% CERM

0.1uF

C2519

1

2

10V 402

0.1UF

CERM

20%

C2581

1

2

10V 402

20%

0.1UF

CERM

C2583

1

2

10V 402

0.1UF

CERM

20%

C2585

1

2

10V 402

0.1UF

CERM

20%

C2587

1

2

10V 402

0.1UF

20% CERM

C2596

1

2

10V 402

0.1uF

20% CERM

C2529

1

2

402

X5R

4V

4.7uF

20%

C2528

1

2

402

X5R

20%

4V

4.7UF

C2503

1

2

83

051-7903

A

22

MCP Standard Decoupling

SYNC_MASTER=T18_MLB

SYNC_DATE=02/05/2009

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_NV

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_CORE

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PEX_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_USB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_PEX

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

PP1V05_ENET

PP3V3_ENET

MCP_MII_VREF

PP3V3_S0

PP3V3_S5

PP1V05_S0

PP1V5_S0

PP1V05_S5

PP1V05_ENET

PP3V3_S0

PPVCORE_S0_MCP

PP3V3_ENET

PP1V05_S0PP1V05_S0

PP1V05_S0_MCP_PLL_UF

20

15

7

19

7

16

19

16

19

13

17

6 7

17 22 31 32

6 7

17 22 31 32

6 7

12 17 18 20 21

22 23 26 27 35 37

41 43 45 46 47 49 53 57 58

61 66 67 68 69 71

72 82

6 7

12 17 18 20 21

22 23 26 27 35 37

41 43 45 46 47 49 53 57 58

61 66 67 68 69 71

72 82

6 7

17 19 21 24 28

32 35 36 42 52 62

66 67 68 69 71 82

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13

16 17 19 21 22 23

35 61 65 66 67

6 7

10 11 15 37 66

67 68 82

6 7

21 32 66

6 7

17 22 31 32

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49

53 57 58 61 66 67 68 69 71 72

82

6 7

21 44 64

6 7

17 22 31 32

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66 67

6 7 9

10 11 12 13

16 17 19 21 22 23

35 61 65 66 67

7

66

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

95 mA (A01)

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF) Apple: 1x 2.2uF 0402 (2.2 uF)

Current numbers from email Xiaowei Lin provided 11/12/2007 3:22pm (no official document number).

190 mA (A01, 1.8V)

16 mA (A01)

Apple: ???

16 mA (A01)

Apple: 2x 2.2uF 0402 (4.4 uF)

206 mA (A01)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

NO STUFF

0.1UF

CERM

402

20% 10V

C2620

1

2

NO STUFF

1K

MF-LF 402

1% 1/16W

R2630

1

2

NO STUFF

0.1UF

CERM

402

20% 10V

C2630

1

2

4.7UF

X5R 402

20%

4V

C2615

1

2

4.7UF

CERM

603

20%

6.3V

C2640

1

2

30-OHM-1.7A

0402

L2640

1 2

0.1uF

CERM 402

20% 10V

C2641

1

2

2.2UF

CERM 402-LF

20%

6.3V

C2616

1

2

0

MF-LF 402

5% 1/16W

R2651

1

2

1K

MF-LF 402

1% 1/16W

R2620

1

2

2.2UF

CERM 402-LF

20%

6.3V

C2610

1

2

051-7903

A

8323

MCP Graphics Support

SYNC_MASTER=K19_MLB

SYNC_DATE=02/05/2009

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_RED

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_R_C_PR

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_HSYNC

NC_MCP_RGB_RED NC_MCP_RGB_GREEN

NC_CRT_IG_B_COMP_PB

NC_MCP_CLK27M_XTALIN NC_MCP_CLK27M_XTALOUT

MCP_IFPAB_VPROBE

NC_MCP_TV_DAC_RSET NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

NC_MCP_RGB_DAC_VREF

MCP_HDMI_VPROBE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_BLUE NC_MCP_RGB_HSYNC NC_MCP_RGB_VSYNC

NC_MCP_RGB_BLUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_GREEN

NC_CRT_IG_R_C_PR

NC_MCP_RGB_DAC_RSET

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_VSYNCNC_CRT_IG_VSYNC

NC_CRT_IG_HSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_YNC_CRT_IG_G_Y_Y

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_RGB_DAC_RSET

PP1V8_S0

MCP_HDMI_RSET

PP3V3_S0

MCP_IFPAB_RSET

PP1V05_S0

PP3V3_S0_MCP_VPLL

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_MCP_DAC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

17 23

17 23 77

17 23

17 23 77

17 23

17 77

17 23 77

17 23 77 17 23 77

17 23

17 23 77

17 23

17 77

17 23

17 23 77

17 23

17 23 77 17 23 77

17 23 77

17 23 77 17 23 77

17 23

6 7

17 53 66

17 77

6 7

12 17 18 20 21 22 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

17 77

6 7 9

10 11 12 13 16 17 19 21

22 35 61 65 66 67

17

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

OUTY

B

A

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MCP S0 PWRGD & CPU_VLD

Platform Reset Connections

LPC Reset (Unbuffered)

RTC Power Source

10K pull-up to 3.3V S0 inside MCP

System Reset Circuit

PCIE Reset (Unbuffered)

RTC Crystal

MCP 25MHz Crystal

9

12 20

50V 402

CERM

5%

12pF

C2810

1 2

5%

50V

CERM

402

12pF

C2811

1 2

402

1/16W

0

5%

MF-LF

R2810

1 2

10M

402

5%

MF-LF

1/16W

NO STUFF

R2811

1

2

18 78

402

0

5%

MF-LF

1/16W

XDP

R2896

1 2

402

1/16W

5%

MF-LF

33

PLACEMENT_NOTE=Place close to U1400

R2883

1 2

402

PLACEMENT_NOTE=Place close to U1400

MF-LF

33

5%

1/16W

R2881

1 2

PLACEMENT_NOTE=Place R2897 on BOTTOM

0

5% 1/16W MF-LF

402

OMIT

SILK_PART=SYS RST

R2897

1

2

42

40

20

16 24 35

402

1/16W MF-LF

5%

33

PLACEMENT_NOTE=Place close to U1400

R2826

1 2

402

PLACEMENT_NOTE=Place close to U1400

1/16W MF-LF

33

5%

R2825

1 2

18 78

50V

5%

CERM

402

12pF

C2815

1 2

50V

5%

CERM

402

12pF

C2816

1 2

25.0000M

CRITICAL

SM-3.2X2.5MM

Y2815

2 4

1 3

402

5%

MF-LF

1/16W

0

R2815

1 2

1/16W

NO STUFF

MF-LF

402

5%

1M

R2816

1

2

20

40 78

22

1/16W

5%

MF-LF

402

PLACEMENT_NOTE=Place close to U1400

R2829

1 2

20 78

5%

MF-LF

402

33

1/16W

R2899

1 2

10%

402

NO STUFF

1UF

X5R

10V

C2899

1

2

16 24 35

8

63 68

MF-LF

1/16W

5%

402

33

R2870

1 2

18

40

42 78

40 78

32.768K

7X1.5X1.4-SM

CRITICAL

Y2810

1 4

402

1/16W MF-LF

5%

0

R2891

1 2

25

402

MF-LF

1/16W

5%

0

R2893

1 2

73

29

0

402

5%

MF-LF

1/16W

R2894

1 2

20

61

40 62 64 65 66 67

402

CERM

10V

20%

0.1UF

C2850

1

2

5%

MF-LF

1/16W

0

402

PLACEMENT_NOTE=Place close to U1400

R2850

1 2

20

TC7SZ08AFEAPE

SOT665

U2850

2

1

3

5

4

402

6.3V

20% X5R

4.7UF

C2801

1

2

10%

402

0.1UF

16V X5R

C2802

1

2

402

6.3V

4.7UF

20% X5R

C2800

1

2

30

0

5% 1/16W MF-LF

402

R2895

1 2

SYNC_DATE=01/06/2009

SYNC_MASTER=WFERRY_K19I

SB Misc

83

A

24

051-7903

RTC_CLK32K_XTALIN

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALIN

MCP_CLK25M_XTALOUT_R

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALOUT

PCIE_RESET_L

MAKE_BASE=TRUE

CARDREADER_PLT_RST_L

BKLT_PLT_RST_L

DEBUG_RESET_L

LPC_RESET_L

PCIE_RESET_L

PCA9557D_RESET_L

PM_SYSRST_L

LPC_CLK33M_SMC_R

MEM_VTT_EN

MEM_VTT_EN_R

MINI_RESET_L

PM_CLK32K_SUSCLK

PP3V42_G3H

MCP_CPU_VLD

SMC_LRESET_L

LPC_CLK33M_LPCPLUS

LPC_CLK33M_SMC

PM_CLK32K_SUSCLK_R

ALL_SYS_PWRGD

VR_PWRGOOD_DELAY

MCP_CPUVDD_EN

MCP_PS_PWRGD

PM_SYSRST_DEBOUNCE_L

PP3V3_S5

XDP_DBRESET_L

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

17 19 21 22 28 32 35 36

42 52 62 66 67 68 69 71 82

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0 A1 A2

SCL SDA

P0 P1 P2

P5 P6 P7

P3 P4

THRM

VCC

GND

PAD

NC NC

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

NC

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DAC channel A B A B C

Max DAC code 0x87 0x87 0x87 0x87 0x55

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Signal aliases required by this page:

- =PPVTT_S3_DDR_BUF

- =PP3V3_S5_VREFMRGN

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SDA

Min DAC code 0x00 0x00 0x00 0x00 0x00

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SCL

(per DAC LSB)

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

Place close to U1000.AD26

Place close to J3100.1

MEM A VREF CAMEM A VREF DQ

Page Notes

10mA max load

- =PP3V3_S3_VREFMRGN

Power aliases required by this page:

Place close to J3200.1

Place close to J3200.126

VREFMRGN

MEM B VREF DQ

ADDR=0x30(WR)/0x31(RD)

Required zero ohm resistors when no VREF margining circuit stuffed

ADDR=0x98(WR)/0x99(RD)

NO_VREFMRGN

BOM options provided by this page:

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

Place close to J3100.126

MEM B VREF CA

CPU FSB VREF

VREFMRGN

MAX4253

UCSP

U2903

C3

C2

C1

C4

B1

B4

VREFMRGN

MF-LF

1/16W

1%

100

402

R2904

1 2

100

1/16W

1%

402

VREFMRGN

MF-LF

R2906

1 2

VREFMRGN

100

1% 1/16W MF-LF

402

R2910

1 2

MF-LF

1/16W

VREFMRGN

1%

402

100

R2914

1 2

1/16W

VREFMRGN

1% MF-LF

100

402

R2912

1 2

VREFMRGN

MAX4253

UCSP

U2904

C3

C2

C1

C4

B1

B4

VREFMRGN

MAX4253

UCSP

U2904

A3

A2

A1

A4

B1

B4

VREFMRGN

0.1UF

20% 10V

402

CERM

C2902

1

2

MAX4253

VREFMRGN

UCSP

U2903

A3

A2

A1

A4

B1

B4

VREFMRGN

MAX4253

UCSP

U2902

C3

C2

C1

C4

B1

B4

MAX4253

VREFMRGN

UCSP

U2902

A3

A2

A1

A4

B1

B4

402

MF-LF

1/16W

200

1%

VREFMRGN

R2911

1 2

402

MF-LF

1/16W

200

1%

VREFMRGN

R2909

1 2

402

MF-LF

1/16W

200

1%

VREFMRGN

R2905

1 2

402

MF-LF

1/16W

200

1%

VREFMRGN

R2903

1 2

MF-LF

1/16W

100K

402

5%

VREFMRGN

R2902

1 2

1/16W

5%

100K

VREFMRGN

MF-LF

402

R2901

1 2

1/16W MF-LF

5%

402

VREFMRGN

100K

R2907

1 2

QFN

VREFMRGN

PCA9557

U2901

3 4 5

8

6 7 9 10 11 12 13 14

15

1 2

17

16

0.1UF

CERM 402

VREFMRGN

10V

20%

C2904

1

2

100K

MF-LF

5%

1/16W

402

VREFMRGN

R2908

1 2

24

25 37 40 43 81

VREFMRGN

DAC5574

MSOP

U2900

9

10

3

6

7

8

1

2

4

5

25 37 40 43 81

10V 402

VREFMRGN

0.1UF

20% CERM

C2901

1

2

VREFMRGN

2.2UF

402-LF

CERM

6.3V

20%

C2900

402

20% 10V

0.1UF

VREFMRGN

CERM

C2905

1

2

MF-LF

402

5%

100K

1/16W

VREFMRGN

R2913

1 2

0.1UF

20%

402

10V CERM

VREFMRGN

C2903

1

2

9

75

RES,MTL FILM,0,5%,0402,SM,LF

116S0004 1

NO_VREFMRGN

R2903 CRITICAL

RES,MTL FILM,0,5%,0402,SM,LF

R2909116S0004

NO_VREFMRGN

CRITICAL1

R2911

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

NO_VREFMRGN

1 CRITICAL

R2905

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

NO_VREFMRGN

1 CRITICAL

FSB/DDR3 Vref Margining

SYNC_MASTER=K24_MLB

051-7903

A

8325

SYNC_DATE=02/05/2009

VREFMRGN_CPUFSB

VREFMRGN_CPUFSB_BUF

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CPUFSB_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMB_EN

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

PCA9557D_RESET_L

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMM

CPU_GTLREF

PP3V3_S3

VREFMRGN_DQ_SODIMMB_BUF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

PPVTTDDR_S3

25

6 7

20 29 30 43 48 50 68

26

27

26

27

7

63

A6

A7

A11

A5

DQ33

VDD

A10/AP

VDD

VSS

SA1

VTT

VSS

DQS4* DQS4

VSS

DQ35

VSS

CK0*

SA0

VSS DQ58 DQ59

DM7

VSS

DQ57

DQ56

DQ50 DQ51

VSS

DQS6* DQS6

VSS

DQ49

DQ48

DQ43

VSS

DM5

VSS DQ42

SDA SCL

VTT

VSS

EVENT*

DQ62

VSS

DQ63

DQS7*

DQS7

DQ60 DQ61

VSS

DQ55

DQ54

DM6

VSS

DQ53

VSS

DQ52

DQ47

VSS

DQS5

VSS

DQ46

DQ41

VSS DQ40

DQ34

VSS

DQ32

TEST

VDD

S1*

A13

CAS*

WE*

BA0

VDD

VDD CK0

A1

A3

VDD

VDD A8

A9

A12/BC*

VDD

BA2

NC

VDD

CKE0

VSS

DQS5*

VSS DQ44 DQ45

DQ39

DQ38

VSS

DM4

VSS

DQ37

DQ36

VREFCA

VDD ODT1

NC

S0*

ODT0

BA1

RAS*

VDD

CK1*

VDD

A0

CK1

A2

VDD

A4

VDD

A14

A15

CKE1

VDD

VSS

VDDSPD

KEY

(SYMBOL 2 OF 2)

BI BIBI

BI

IN

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

DQ16

DM3

DQ26 DQ27

DQ4

DQ31

DQ30

DQS3

DQS3*

DQ29

DQ28

DQ23

DQ22

DM2

DQ21

DQ20

DQ15

DQ14

RESET*

DM1

DQ13

DQ12

DQ7

DQ6

DQS0

DQS0*

DQ5

DQ24 DQ25

DQ19

DQ18

DQS2

DQS2*

DQ17

DQ11

DQ10

DQS1

DQS1*

DQ8 DQ9

DM0

DQ0 DQ1

VREFDQ

DQ3

DQ2

VSS

KEY

VSS

(SYMBOL 1 OF 2)

IN

BI BI

BI

BI BI

BI

IN IN

IN

IN IN

IN

BI BI

IN

BI BI

IN

BI

IN

BI BI

BI

IN

BI BI

BI

OUT

BI IN

IN

IN IN

BI BI

BI

IN

BI

BI BI

IN

BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

516-0196

SPD ADDR=0xA0(WR)/0xA1(RD)

- =PP1V5_S0_MEM_A

- =PPSPD_S0_MEM_A (2.5 - 3.3V)

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

"Factory" (top) slot

- =I2C_SODIMMA_SDA

- =PP0V75_S0_MEM_VTT_A

- =I2C_SODIMMA_SCL

- =PP1V5_S3_MEM_A

BOM options provided by this page:

(NONE)

DDR3-SODIMM-DUAL-M97-3

F-RT-THB

J3100

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99 100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

203 204

113

14 76

0.1UF

CERM 402

20% 10V

C3131

1

2

2.2UF

CERM 402-LF

20%

6.3V

C3130

1

2

14 76

27 28

14 76

CRITICAL

DDR3-SODIMM-DUAL-M97-3

F-RT-THB

J3100

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

14 76

8

14 76

0.1UF

CERM 402

20% 10V

C3136

1

2

2.2UF

CERM 402-LF

20%

6.3V

C3135

1

2

14 76

20 27 40

12 20 43 78

12 20 27 43 78

14 76

10K

MF-LF 402

5% 1/16W

R3141

1

2

10K

MF-LF 402

5% 1/16W

R3140

1

2

2.2UF

CERM 402-LF

20%

6.3V

C3140

1

2

10UF

X5R 603

20%

6.3V

C3100

1

2

10UF

X5R 603

20%

6.3V

C3101

1

2

0.1UF

CERM 402

20% 10V

C3110

1

2

0.1UF

CERM 402

20% 10V

C3111

1

2

0.1UF

CERM 402

20% 10V

C3112

1

2

0.1UF

CERM 402

20% 10V

C3113

1

2

0.1UF

CERM 402

20% 10V

C3114

1

2

0.1UF

CERM 402

20% 10V

C3115

1

2

0.1UF

CERM 402

20% 10V

C3116

1

2

0.1UF

CERM 402

20% 10V

C3117

1

2

0.1UF

CERM 402

20% 10V

C3118

1

2

0.1UF

CERM 402

20% 10V

C3119

1

2

0.1UF

CERM 402

20% 10V

C3120

1

2

0.1UF

CERM 402

20% 10V

C3121

1

2

0.1UF

CERM 402

20% 10V

C3122

1

2

0.1UF

CERM 402

20% 10V

C3123

1

2

SYNC_MASTER=K19_MLB

SYNC_DATE=02/05/2009

DDR3 SO-DIMM Connector A

051-7903

A

8326

MEM_A_BA<2>

MEM_A_DQ<60>

MEM_A_DQ<58> MEM_A_DQ<59>

MEM_A_SA<0>

GND

MEM_A_DQ<3> MEM_A_DQ<2>

PP0V75_S3_MEM_VREFDQ_A

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DM<0>

MEM_A_DQ<13>

MEM_A_DQ<9>

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

MEM_A_DQ<11> MEM_A_DQ<14>

MEM_A_DQ<18>

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MEM_A_DQ<23> MEM_A_DQ<19>

MEM_A_DQ<30>

MEM_A_DQ<24>

MEM_A_DQ<5>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MEM_A_DQ<6> MEM_A_DQ<7>

MEM_A_DQ<8> MEM_A_DQ<12>

MEM_A_DM<1> MEM_RESET_L

MEM_A_DQ<15> MEM_A_DQ<10>

MEM_A_DQ<21> MEM_A_DQ<20>

MEM_A_DM<2>

MEM_A_DQ<17> MEM_A_DQ<22>

MEM_A_DQ<29> MEM_A_DQ<28>

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MEM_A_DQ<26> MEM_A_DQ<31>

MEM_A_DQ<4>

MEM_A_DM<3>

MEM_A_DQ<16>

PP3V3_S0

MEM_A_CKE<1>

NC_MEM_A_A<15> MEM_A_A<14>

MEM_A_A<4>

MEM_A_A<2>

MEM_A_CLK_P<1>

MEM_A_A<0>

MEM_A_CLK_N<1>

MEM_A_RAS_L

MEM_A_ODT<0>

MEM_A_ODT<1>

PP0V75_S3_MEM_VREFCA_A

MEM_A_DQ<36> MEM_A_DQ<37>

MEM_A_DM<4>

MEM_A_DQ<38> MEM_A_DQ<39>

MEM_A_DQ<40>

MEM_A_DQ<47>

MEM_A_DQS_N<5>

MEM_A_CKE<0>

MEM_A_A<12> MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<3> MEM_A_A<1>

MEM_A_CLK_P<0>

MEM_A_BA<0>

MEM_A_WE_L MEM_A_CAS_L

MEM_A_A<13> MEM_A_CS_L<1>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<44> MEM_A_DQ<41>

MEM_A_DQ<46>

MEM_A_DQS_P<5>

MEM_A_DQ<43>

MEM_A_DQ<48> MEM_A_DQ<53>

MEM_A_DM<6>

MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_DQ<56>

MEM_A_DQ<57>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_EVENT_L

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

MEM_A_DQ<45>

MEM_A_DM<5>

MEM_A_DQ<42>

MEM_A_DQ<52> MEM_A_DQ<51>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQ<54>

MEM_A_DQ<55>

MEM_A_DQ<61>

MEM_A_DM<7>

MEM_A_CLK_N<0>

MEM_A_DQ<35>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

PP0V75_S0_DDRVTT

MEM_A_SA<1>

MEM_A_A<10>

MEM_A_DQ<32>

MEM_A_A<5>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<6>

MEM_A_DQ<27> MEM_A_DQ<25>

PP1V5_S3

MEM_A_CS_L<0>

MEM_A_BA<1>

25

6 7

12 17 18 20

21 22 23 27 35 37 41 43

45 46 47 49 53

57 58 61 66 67 68 69 71

72 82

25

6 7

27 63 68

6 7

27 28 63 68

IN

BI

BI BI

OUT

BI

IN

IN IN

IN

IN IN

BI BI

BI

IN

BI BI

IN

BI BI

IN

VDD

A1

A3

VDD

A5

A8

VDD

A9

VDD

A12/BC*

VSS

DQ42 DQ43

DQ48 DQ49

VSS

DQ41

DQS4*

DM5

VDD

CKE1

A15 A14

VDD

A11

A7

A6

VDD

A4

A2

CK1

A0

VDD

CK1*

VDD

RAS*

BA1

ODT0

S0*

NC

ODT1

VDD

VREFCA

VDD

DQ36 DQ37

VSS

DM4

VSS

VSS DQ38 DQ39

DQ45

DQ44

VSS

DQS5*

VSS

CKE0

VDD NC

BA2

CK0

VDD

BA0

WE*

A13 S1*

VDD

TEST

DQ33

DQ32

VSS

DQ34

DQ40

VSS

DQ46

VSS

DQS5

VSS

DQ47

DQ52

VSS

DQ53

VSS

DM6

DQ54 DQ55

VSS

DQ61

DQ60

DQS7

DQS7*

DQ63

VSS DQ62

EVENT*

VSS

VTT

SCL

SDA

VSS

DQS6

DQS6*

VSS

DQ51

DQ50

A10/AP

VDD

CK0*

DQ35

VSS

DQS4

VSS

CAS*

VDD

DM7

VSS

DQ56

MTG PIN

MTG PIN MTG PIN MTG PIN MTG PIN

MTG PIN

VSS

DQ57

VTT

SA1

SA0

DQ58

VSS

DQ59

VSS

VDDSPD

MTG PIN

MTG PINS

KEY

(2 OF 2)

BI BI

IN

BI

IN

BI

BI BI

IN

BI BI

BI

DQ2 DQ3

VREFDQ

DQ1

DQ0

DM0

DQ9

DQ8

DQS1* DQS1

DQ10 DQ11

DQ17

DQS2* DQS2

DQ18 DQ19

DQ25

DQ24

DQ5

DQS0*

DQS0

DQ6 DQ7

DQ12 DQ13

DM1

RESET*

DQ14 DQ15

DQ20 DQ21

DM2

DQ22 DQ23

DQ28 DQ29

DQS3*

DQS3

DQ30 DQ31

DQ4

DQ27

DQ26

DM3

DQ16

(1 OF 2)

VSS

KEY

VSS

IN

BI BI

BI

BI BI

IN IN

IN

BI

IN

IN IN

BI BI

IN

BI BI

IN

BI BI

IN

BI

BI BI

BI

IN

BI

BI BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Power aliases required by this page:

- =PPSPD_S0_MEM_B (2.5 - 3.3V)

BOM options provided by this page:

- =PP1V5_S3_MEM_B

- =PP0V75_S0_MEM_VTT_B

Page Notes

516s0704

SPD ADDR=0xA2(WR)/0xA3(RD)

- =PP1V5_S0_MEM_B

"Expansion" (bottom) slot

(NONE)

Signal aliases required by this page:

DDR3 PLANE STITCHING CAPS (SPACE EVENLY ACROSS PLANE SPLIT)

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

14 76

20 26 40

43

12 20 26 43 78

0.1UF

CERM 402

20% 10V

C3231

1

2

14 76

2.2UF

CERM 402-LF

20%

6.3V

C3230

1

2

10K

MF-LF 402

5% 1/16W

R3241

1

2

10K

MF-LF 402

5% 1/16W

R3240

1

2

2.2UF

CERM 402-LF

20%

6.3V

C3240

1

2

10UF

X5R 603

20%

6.3V

C3200

1

2

10UF

X5R 603

20%

6.3V

C3201

1

2

0.1UF

CERM 402

20% 10V

C3210

1

2

0.1UF

CERM 402

20% 10V

C3211

1

2

0.1UF

CERM 402

20% 10V

C3212

1

2

0.1UF

CERM 402

20% 10V

C3213

1

2

14 76

0.1UF

CERM 402

20% 10V

C3214

1

2

0.1UF

CERM 402

20% 10V

C3215

1

2

0.1UF

CERM 402

20% 10V

C3216

1

2

0.1UF

CERM 402

20% 10V

C3217

1

2

0.1UF

CERM 402

20% 10V

C3218

1

2

0.1UF

CERM 402

20% 10V

C3219

1

2

0.1UF

CERM 402

20% 10V

C3220

1

2

0.1UF

CERM 402

20% 10V

C3221

1

2

0.1UF

CERM 402

20% 10V

C3222

1

2

0.1UF

CERM 402

20% 10V

C3223

1

2

14 76

DDR3-SODIMM

F-RT-BGA3

J3200

9897

107

8483

119

80

78

9695

9291

90

86

89

85

109

108

79

115

101 103

102 104

73 74

136

153

170

187

129 131

141 143

130 132

140 142

147 149

157 159

146 148

158 160

163 165

175 177

164 166

174 176

181 183

191 193

180 182

192 194

137

135

154

152

171

169

188

186

198

77

122

116

120

110

114

121

197

201 202

200

125

75 76

105 106

111 112

117 118

123 124

81 82

87 88

93 94

99 100

199

126

127 128

133 134

138

139

144

145

150

151

155 156

161 162

167 168

172

173

178

179

184

185

189 190

195 196

205 206 207 208 209 210 211 212

203 204

113

14 76

26 28

14 76

CRITICAL

DDR3-SODIMM

F-RT-BGA3

J3200

11

28

46

63

5 7

33 35

22 24

34 36

39 41

51 53

15

40 42

50 52

57 59

67 69

56 58

17

68 70

4 6

16 18

21 23

12

10

29

27

47

45

64

62

30

1 2 3

31 32

37 38

43 44

48

49

54

55

8

60

61

65 66

71 72

9

13 14

19 20

25 26

14 76

8

14 76

0.1UF

CERM 402

20% 10V

C3236

1

2

2.2UF

CERM 402-LF

20%

6.3V

C3235

1

2

14 76

SYNC_MASTER=K19_MLB

27 83

A

051-7903

SYNC_DATE=02/05/2009

DDR3 SO-DIMM Connector B

GND

MEM_B_DQ<9>

MEM_B_DQ<18> MEM_B_DQ<22>

MEM_B_DQ<4>

MEM_B_DQ<23>

MEM_B_DQ<19>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<16>

MEM_B_DQ<20>

MEM_B_DQ<11>

MEM_B_DQ<14>

MEM_B_DM<1>

MEM_B_DQ<12>

MEM_B_DQ<13>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_RESET_L

MEM_B_DM<3>

MEM_B_DQ<25>

MEM_B_DQ<29>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<5>

MEM_B_DQ<21> MEM_B_DQ<17>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQ<8>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQ<28>

MEM_B_DM<0>

MEM_B_DQ<0> MEM_B_DQ<1>

PP0V75_S3_MEM_VREFDQ_B

MEM_B_DQ<3>

MEM_B_DQ<2>

PP3V3_S0

MEM_B_DQ<59>

MEM_B_DQ<63>

MEM_B_SA<0>

MEM_B_SA<1>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DM<7>

MEM_B_CAS_L

MEM_B_DQS_P<4>

MEM_B_DQ<35>

MEM_B_CLK_N<0>

MEM_B_A<10>

MEM_B_DQ<52> MEM_B_DQ<51>

MEM_B_DQS_N<6> MEM_B_DQS_P<6>

=I2C_SODIMMB_SDA SMBUS_MCP_0_CLK

PP0V75_S0_DDRVTT

MEM_EVENT_L

MEM_B_DQ<58>

MEM_B_DQS_N<7> MEM_B_DQS_P<7>

MEM_B_DQ<60> MEM_B_DQ<61>

MEM_B_DQ<50>

MEM_B_DQ<53>

MEM_B_DM<6>

MEM_B_DQ<54>

MEM_B_DQ<48>

MEM_B_DQ<46>

MEM_B_DQS_P<5>

MEM_B_DQ<47>

MEM_B_DQ<41>

MEM_B_DQ<34>

MEM_B_DQ<32> MEM_B_DQ<37>

MEM_B_CS_L<1>

MEM_B_A<13>

MEM_B_WE_L

MEM_B_BA<0>

MEM_B_CLK_P<0>

MEM_B_BA<2>

MEM_B_DQS_N<5>

MEM_B_DQ<44> MEM_B_DQ<45>

MEM_B_DQ<39>

MEM_B_DM<4>

MEM_B_DQ<36>

MEM_B_DQ<33>

PP0V75_S3_MEM_VREFCA_B

MEM_B_ODT<1>

MEM_B_CS_L<0> MEM_B_ODT<0>

MEM_B_BA<1> MEM_B_RAS_L

MEM_B_A<0>

MEM_B_CLK_P<1>

MEM_B_A<2>

MEM_B_A<4>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<11>

MEM_B_A<14>

NC_MEM_B_A<15>

MEM_B_CKE<1>

MEM_B_DM<5>

MEM_B_DQS_N<4>

MEM_B_DQ<40>

MEM_B_DQ<55>

MEM_B_DQ<42>

MEM_B_DQ<43>

MEM_B_A<12> MEM_B_A<9>

MEM_B_A<8> MEM_B_A<5>

MEM_B_A<3> MEM_B_A<1>

PP1V5_S3

MEM_B_CKE<0>

MEM_B_DQ<24>

MEM_B_DQ<38>

MEM_B_DQ<49>

MEM_B_DQ<62>

MEM_B_DM<2>

MEM_B_CLK_N<1>

25

6 7

12 17 18 20 21

22 23 26 35 37 41 43 45 46

47 49 53 57 58 61

66 67 68 69 71 72 82

6 7

26 63 68

25

6 7

26 28 63 68

D

Q2

SG

Q1

B

C

E

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

rise to avoid glitch on MEM_RESET_L.

3.3V S5 is used because MEM_RESET

Required becaues MCP79 does not meet DDR3 spec power-up reset timing requirement.

must be high before 1.5V starts to

DDR3 RESET Support

DMB53D0UDW

SOT-363

Q3305

5

3

64

2 1

5% 1/16W MF-LF

402

100K

R3305

1

2

26 27

5%

402

MF-LF

1/16W

10K

R3300

1

2

10V

0.1UF

20% CERM

402

C3300

1

2

402

1/16W

20K

5%

MF-LF

R3301

1

2

402

0

1/16W MF-LF

5%

R3309

2 1

15

5% 1/16W MF-LF

402

1K

R3310

1

2

051-7903

A

8328

SYNC_MASTER=T18_MLB

SYNC_DATE=02/05/2009

DDR3 Support

PP3V3_S5

MEM_RESET

MEM_RESET_RC_L

MEM_RESET_L

MCP_MEM_RESET_L

PP1V5_S3

6 7

17 19 21 22 24 32 35 36 42

52 62 66 67 68 69 71 82

6 7

26 27 63 68

OUT

IN

BI

NC

IN

BI

OUT OUT

Y

B

A

IN

NC

SYM_VER-1

D

S G

D

S G

OUT

IN

OUT OUT

D

GS

S

G

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

14 mOhm @4.5V

5V S3 WLAN FET

0.8 A (EDP)

P-Channel

TPCP8102Part Type Rds(on) Loading

275 mA peak 206 mA nominal max

518S0610

CAMERA

ALS

AIRPORT

1000 mA peak 750 mA nominal max

BLUETOOTH

(C3420 & C3421)

PLACEMENT_NOTEs:

6

16

CRITICAL

20347-325E-12

F-RT-SM

J3401

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25

26 27 28 29

3

30

31

32

4 5 6 7 8 9

PLACEMENT_NOTE=Place close to J3401.

FERR-120-OHM-1.5A

0402-LF

L3405

12

32

6

40 43 49 81

6

40 43 49 81

0402-LF

FERR-120-OHM-1.5A

PLACEMENT_NOTE=Place close to J3401.

L3404

12

20% 10V CERM 402

0.1uF

C3452

1

2

10% 16V X5R 402

0.1uF

PLACEMENT_NOTE=Place close to J3401.

C3430

1 2

16 77

0.1uF

402

X5R

16V

10%

PLACEMENT_NOTE=Place close to J3401.

C3431

1 2

16 77

6

19 78

6

19 78

Place close to Q3450.

0.1uF

402

CERM

10V

20%

C3421

1

2

6

19 78

6

19 78

6

16 77

6

16 77

SOT665

TC7SZ08AFEAPE

U3401

2

1

3

5

4

24

74LVC1G17DRL

SOT-553

U3402

2

3 1

5

4

10V

10UF

805

X5R

20%

Place close to Q3450.

C3420

1

2

33K

5% 1/16W MF-LF

402

R3453

1

2

62K

5%

MF-LF

402

1/16W

R3454

1

2

1UF

402

CERM

6.3V

10%

C3453

1

2

90-OHM-100MA

DLP11S

CRITICAL

PLACEMENT_NOTE=Place close to J3401.

L3401

1 2

34

DLP0NS

90-OHM

PLACEMENT_NOTE=Place close to J3401.

CRITICAL

L3402

1 2

34

PLACEMENT_NOTE=Place close to J3401.

DLP0NS

90-OHM

CRITICAL

L3403

1 2

34

SOT563

SSM6N15FEAPE

Q3401

6

2

1

SOT563

SSM6N15FEAPE

Q3401

3

5

4

16

20 32

51 82

SSM3K15FV

SOD-VESM-HF

Q3455

3

1

2

MF-LF

1/16W

402

5%

1

R3455

1 2

0.1uF

10V

20%

402

CERM

C3462

1

2

FERR-120-OHM-1.5A

0402-LF

L3406

12

23V1K-SM

TPCP8102

CRITICAL

Q3450

5 6 7 8

4

1 2 3

SM

XW3450

1 2

SM

XW3451

1 2

SM

XW3452

1 2

0.1UF

402

X5R

16V

10%

C3450

1 2

0.033UF

402

X5R

16V

10%

C3451

1

2

402

5%

MF-LF

1/16W

100K

R3450

1 2

10K

5% 1/16W MF-LF 402

R3451

1

2

20% 10V CERM 402

0.1uF

C3422

1

2

SYNC_DATE=03/04/2009

SYNC_MASTER=K19_MLB

051-7903

A

8329

Right Clutch Connector

PP3V3_S3

ISNS_AIRPORT_N

ISNS_AIRPORT_P

VOLTAGE=5V

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=1 mm

PP5V_WLAN_RPP5V_WLAN_F

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm VOLTAGE=5V

P5VWLAN_SS

PP5V_S3

MINI_RESET_L

WLAN_SMIT_BUF

PCIE_MINI_R2D_C_N

PCIE_MINI_R2D_P

PCIE_MINI_PRSNT_L

AP_PWR_EN

MINI_CLKREQ_L

MINI_CLKREQ_Q_L

PM_WLAN_EN_L

WLAN_SMIT_RC

PCIE_CLK100M_MINI_P

PCIE_CLK100M_MINI_CONN_N

PCIE_CLK100M_MINI_N

WLAN_SMIT_DISCHRG

PCIE_MINI_R2D_C_P

USB_BT_N

USB_BT_P

USB_CAMERA_N

USB_CAMERA_P

CONN_USB2_BT_P CONN_USB2_BT_N

USB_CAMERA_CONN_P USB_CAMERA_CONN_N

SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL

PCIE_WAKE_L

PCIE_MINI_D2R_N

PCIE_MINI_D2R_P

MINI_RESET_CONN_L PP5V_WLAN

VOLTAGE=5V

MIN_LINE_WIDTH=1 mm MIN_NECK_WIDTH=0.5 mm

PP5V_S3

VOLTAGE=5V

MIN_NECK_WIDTH=0.25 mm

PP5V_S3_BTCAMERA_F

MIN_LINE_WIDTH=0.5 mm

PP3V3_S3

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_S3_BT_F

PCIE_MINI_R2D_N

PCIE_CLK100M_MINI_CONN_P

6 7

20 25 29 30 43 48 50 68

51

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6

77

82

6

82

6

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6

6 7

20 25 29 30 43 48 50 68

6

77

82

6

82

BI BI

VDD

WRITE_PROTECT_SW

CARD_DETECT_SW CARD_DETECT_GND

DAT6 DAT7

DAT1

CD/DAT3

DAT2

DAT4

DAT5

VSS

CLK CMD

DAT0

SHLD_PIN

SHLD_PIN SHLD_PIN

SHLD_PIN

DP

CS

AGND

DGND

PMOSO

D1

VDD5V

D3

D0

MS_INS

SK

DI

DO

RREF

D4

D2

D5 D6

DM

AVDD

GPIO2

D7

SD_CLK/MS_SCLK/SM_ALE

X1

GPIO3

VDD18O

X2

GPIO1

SD_CDZ

SM_CDZ

SD_CMD/SM_REZ

SD_WP/SM_WPDZ

SM_WPZ

XD_CDZ

SM_WEZ SM_RBZ

MS_BS/SM_CLE

SM_CE

EXTRSTZ*

TEST_MOD

DVDD

NC

NC NC NC NC NC

NC NC

D

SG

D

SG

IN

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(PDMOD)

PDMOD: POWER DOWN MODES

10K LOW = POWER SAVING MODE ENABLE 10K HIGH = REMOTE WAKE UP ENABLE

IPD/

NC = DISABLE (DEFAULT)

IPU/

/IPD

/IPU

MAX CURRENT = 250MA

IPD/ IPD/

IPU/

IPD/

/IPD

MF-LF 402

1/16W

5%

0

R3502

1

2

X5R

20%

603

6.3V

10UF

C3500

1

2

402

10V

20%

0.1UF

CERM

C3501

1

2

NO STUFF

402

MF-LF

1M

5%

1/16W

R3503

1 2

10V CERM

20%

0.1UF

402

C3505

1

2

10V

20% CERM

0.1UF

402

C3506

1

2

603

20% CERM1

6.3V

2.2UF

C3507

1

2

0.1UF

20% CERM

402

10V

C3508

1

2

0.1UF

CERM 402

10V

20%

C3502

1

2

0.1UF

CERM 402

20% 10V

C3503

1

2

402

0.1UF

10V CERM

20%

C3504

1

2

19 78

50V

CERM

5%

33PF

402

C3511

1 2

12.000M-100PPM

8X4.5X1.4-SM

CRITICAL

Y3500

1 2

402

50V

33PF

CERM

5%

C3512

1 2

SD-CARD-K19

OMIT

F-RT-TH

J3500

15

14

1

5 2 7 8 9

10 11 12 13

17 18 19 20

4

3 6

16

0.22UH

0805-1

L3500

1 2

GL137

LQFP

U3500

5

9

12

6

11

20

40 43 37 29 28 30 32 38

16

27

34

22

7

21

8

152635

18

48 47 46

33

24

36

10

23

39

41

3

19

2

31

44

42

45

17

4

25

13 14

1

6.3V X5R 603

10UF

20%

C3514

1

2

5% MF-LF

402

39K

1/16W

R3505

1

2

402

CERM

NO STUFF

0.1UF

20% 10V

C3513

1

2

715

1% 1/16W MF-LF 402

R3506

1

2

MF-LF

1/16W

10K

5%

402

R3507

1

2

1/16W

5%

10K

NO STUFF

402

MF-LF

R3508

1

2

5%

402

MF-LF

1/16W

10K

NO STUFF

R3509

1

2

5%

402

MF-LF

1/16W

10K

R3510

1

2

MF-LF

1/16W

0

5%

402

R3511

1 2

10K

5% MF-LF

402

1/16W

R3512

1

2

10K

1/16W MF-LF

5%

402

NO STUFF

R3513

1

2

5%

402

MF-LF

1/16W

0

R3504

1 2

NO STUFF

402-1

CERM

50V

5%

10PF

C3515

1

2

SSM6N15FEAPE

SOT563

Q3500

3

5

4

SSM6N15FEAPE

SOT563

Q3500

6

2

1

16

24

30 83

SYNC_DATE=03/23/2009

SYNC_MASTER=K19_MLB

SECUREDIGITAL CARD READER

A

051-7903

516-0225

J3500

CONN,SD CARD, OPTN B

CRITICAL

1

CARDREADER_GPIO1

CARDREADER_RESET

CARDREADER_RESET_L

PLACEMENT_NOTE=KEEP THIS NET AS SHORT AS POSSIBLE

VOLTAGE=3.3V

PP3V3_SW_SD_PWR

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

SD_WP

SD_CLK_R

USB_CARDREADER_P

SD_D<1>

SD_D<3>

SD_D<0>

CARDREADER_RREF

SD_D<4>

SD_D<2>

SD_D<5> SD_D<6>

USB_CARDREADER_N

PP3V3_S3_CARDREADER_AVDD

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.40MM

VOLTAGE=3.3V

PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

CARDREADER_GPIO2

SD_D<7>

CARDREADER_XTAL1

PP1V8_S3_CARDREADER

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

VOLTAGE=1.8V

CARDREADER_XTAL2

CARDREADER_GPIO1

SD_CD_L

CARDREADER_PDMOD

SD_CMD

CARDREADER_TEST_MOD

MIN_LINE_WIDTH=0.40MM

PLACEMENT_NOTE=PLACE 402 NEAR EACH PIN

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.20MM

PP3V3_S3_CARDREADER_DVDD

MIN_NECK_WIDTH=0.20MM

PP3V3_S3

MIN_LINE_WIDTH=0.40MM

VOLTAGE=3.3V

CARDREADER_GPIO2

PP3V3_S3_CARDREADER_DVDD

SD_CLK

CARDREADER_PLT_RST

CARDREADER_PLT_RST_L

30

6

82

6

82

6

82

6

82

6

82

6

82

6

82

30

6

82

30

6

82

30

6 7

20 25 29 43 48 50 68

30

6

82

TXD[2]

TXCTL

AVDD33

FB12

DVDD12

AVDD12

RXC

MDIO

GND

TXD[3]

RXD[0]

MDI+[0]

CKXTAL1 CKXTAL2

CLK125

RSET

PHYRSTB*

MDC

RXCTL

MDI-[2]

MDI+[2]

MDI+[3]

MDI+[1] MDI-[1]

ENSWREG

TXD[1]

TXD[0]

RXD[3]/AN1

RXD[1]/TXDLY

TXC

MDI-[3]

LED1/PHYAD1

LED2/RXDLY

LED0/PHYAD0

RXD[2]/AN0

MDI-[0]

REGOUT

VDDREG

DVDD33

REFERENCE

RGMII/MII

MEDIA DEPENDENT

MANAGEMENT

CLOCK

RESET

LED

IN IN IN IN

IN

BI

IN

BI

BI BI

OUT

OUT OUT OUT OUT

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Alias to =PP3V3_ENET_PHY for internal switcher. Alias to GND for external 1.05V supply.

( 7mA typ - Energy Detect)

Reserved for EMI per RealTek request.

If internal switcher is not used, VDDREG and REGOUT can float.

WF: Marvell numbers, update for Realtek

(43mA typ - 1000base-T) (19mA typ - Energy Detect)

(221mA typ - 1000base-T)

WF: Marvell numbers, update for Realtek

RXDLY = 0 (RXCLK transitions with data) TXDLY = 0 (No TXCLK Delay)

AN[1:0] = 11 (Full auto-negotiation)

PHYAD = 01 (PHY Address 00001)

Configuration Settings:

If internal switcher is used, must place 1x 22uF & 1x 0.1uF caps within 5mm of U3700 pins 44 & 45.

NOTE: VDDREG rise time must be >1ms to avoid damage to switcher.

of U3700, and 1x 22uF & 1x 0.1uF caps within 5mm of inductor.

If internal switcher is used, must place inductor within 5mm

402

1/16W

1%

MF-LF

2.49K

R3730

1

2

10K

MF-LF

5%

1/16W

402

R3720

1

2

CRITICAL FERR-120-OHM-1.5A

0402-LF

L3705

1

2

0.1UF

16V X5R 402

10%

C3705

1

2

CRITICAL

OMIT

RTL8211CLGR

TQFP

U3700

10

40

6

41

42 43

32

28

36

152137

39

3

7

203347

34 35 38

30

2

1

5

4

9

8

12

11

31

29

48

46

19

13

14 16 17 18

22

27

23 24 25 26

44

45

0.1UF

10% 16V X5R 402

C3706

1

2

0.1UF

16V X5R 402

10%

C3700

1

2

16V

0.1UF

X5R 402

10%

C3701

1

2

0.1UF

16V X5R 402

10%

C3702

1

2

17 79

32 79

33 79

MF-LF

5%

1/16W

22

402

R3790

1 2

402

MF-LF1/16W

5%

22

R3791

1 2

22

402

MF-LF1/16W

5%

R3792

1 2

402

22

MF-LF1/16W

5%

R3793

1 2

402

22

MF-LF1/16W

5%

R3794

1 2

402

22

MF-LF1/16W

5%

R3795

1 2

17 79

1/16W

402

4.7K

MF-LF

5%

R3755

1

2

402

4.7K

MF-LF

5%

1/16W

R3756

1

2

402

MF-LF

5%

4.7K

1/16W

R3752

1

2

402

4.7K

MF-LF

5% 1/16W

R3757

1

2

1/16W

5%

4.7K

MF-LF

402

R3750

1

2

MF-LF

4.7K

5% 1/16W

402

R3751

1

2

16V X5R 402

10%

0.1UF

C3715

1

2

16V

0.1UF

X5R 402

10%

C3716

1

2

FERR-120-OHM-1.5A

0402-LF

CRITICAL

L3715

1

2

0.1UF

16V X5R

10%

402

C3711

1

2

0.1UF

16V X5R 402

10%

C3710

1

2

16V

10% 402

X5R

0.1UF

C3714

1

2

402

5%

CERM

50V

10PF

NO STUFF

C3790

1

2

17 79

PLACEMENT_NOTE=Place R3796 close to U1400,pin D24

22

402

MF-LF

5%

1/16W

R3796

1 2

SYNC_MASTER=(K19I_MLB)

SYNC_DATE=02/05/2009

Ethernet PHY (RTL8211CL)

83

A

31

051-7903

RTL8211_RSET

ENET_RESET_L

ENET_RX_CTRL

ENET_RXD<3>

ENET_RXD<2>

ENET_RXD<1>

ENET_RXD<0>

ENET_CLK125M_RXCLK

PP1V05_ENET

ENET_MDI_N<1>

ENET_MDI_P<1>

ENET_MDI_P<3> ENET_MDI_N<3>

RTL8211_PHYAD1 RTL8211_RXDLY

ENET_MDI_P<2> ENET_MDI_N<2>

RTL8211_CLK125

TP_RTL8211_CKXTAL2

NC_RTL8211_REGOUT

ENET_MDC ENET_MDIO

ENET_TXD<1>

RTL8211_CLK25M_CKXTAL1

ENET_TXD<0>

ENET_TXD<3>

ENET_TX_CTRL

ENET_CLK125M_RXCLK_R

RTL8211_PHYAD0

ENET_MDI_N<0>

ENET_MDI_P<0>

ENET_RXCTL_R

ENET_RXD_R<1>

ENET_RXD_R<0>

VOLTAGE=1.05V

PP1V05_ENET_PHYAVDD

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_ENET

RTL8211_VDDREG

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_ENET_PHYAVDD

VOLTAGE=3.3V

ENET_TXD<2>

GND

ENET_RXD_R<2> ENET_RXD_R<3>

ENET_CLK125M_TXCLK_R

ENET_CLK125M_TXCLK

6 7

17 22 32

8

79

6 7

17 22 32

8

79

G

DS

IN

OUT

D

SG

IN

D

S G

IN

D

SG

D

SG

D

S

G

D

SG

IN

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1.8V Vgs

ARB for alternate power options.

=P3V3ENET_EN. Nets separated on

Recommend aliasing PM_SLP_RMGT_L and

1.05V ENET FET

WLAN Enable Generation

Recommend aliasing PM_SLP_RMGT_L and

"WLAN" = ("S3" && "AP_PWR_EN" && ("AC" || "S0"))

NOTE: S3 term is guaranteed by S3 pull-up on open-drain AP_PWR_EN signal.

RTL8211 25MHz Clock

=P1V05ENET_EN. Nets separated on

I(max) = 1.7A (85C)

3.3V ENET FET

Rds(on) = 90mOhm max

MOBILE:

@ 2.5V Vgs:

NOTE: MCP79 can provide 25MHz clock, but clock runs whenever RMGT rails are powered. Designs must ensure PHY is powered whenever RMGT rails are, or use separate crystal.

Non-ARB:

Pull-up is with power FET.

SOT-23-HF

NTR4101P

CRITICAL

Q3810

3

1

2

16V

10%

402

CERM

0.01UF

C3810

12

16V

10%

402

X5R

0.033UF

C3811

1

2

1/16W

5%

402

MF-LF

100K

R3810

1 2

17 79

1/16W

5%

402

MF-LF

22

PLACEMENT_NOTE=Place close to U1400

R3895

1 2

31 79

16V

10% 402

CERM

0.01UF

C3841

1

2

10V

20%

402

CERM

0.1UF

C3840

1

2

29

SOT563

SSM6N15FEAPE

Q3805

3

5

4

20 35 40 41

SOT563

SSM6N15FEAPE

Q3801

6

2

1

20 29

6

20 35 40 67 71

SOT563

SSM6N15FEAPE

Q3805

6

2

1

SOT563

SSM6N15FEAPE

Q3841

6

2

1

1/16W

1%

402

MF-LF

69.8K

R3842

1

2

SOT23

SI2312BDS

CRITICAL

Q3840

3

1

2

1/16W

5%

402

MF-LF

10K

R3800

1

2

SOT563

SSM6N15FEAPE

Q3801

3

5

4

8

20 32

SOT563

SSM6N15FEAPE

Q3841

3

5

4

8

20 32

1/16W

1%

402

MF-LF

10K

R3841

1 2

1/16W

5%

402

MF-LF

100K

R3840

1 2

SYNC_DATE=02/05/2009

SYNC_MASTER=K19_MLB

32 83

A

051-7903

Ethernet & AirPort Support

PM_WLAN_EN_L

P3V3ENET_EN_L

MCP_CLK25M_BUF0_R

RTL8211_CLK25M_CKXTAL1

P3V3ENET_SS

PP3V3_ENET

PP3V3_S5

AP_PWR_EN

AC_OR_S0_L

SMC_ADAPTER_EN

PM_SLP_S3_L

PM_SLP_RMGT_L

P1V05ENET_EN_L

P1V05ENET_SS

PP3V3_S5

P1V05ENET_EN_L_RC

PP1V05_ENET

PP1V05_S5

6 7

17 22 31

6 7

17 19 21 22 24 28 32 35

36 42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35

36 42 52 62 66 67 68 69 71 82

6 7

17 22 31

6 7

21 22 66

BI

RX

TX

BI

RX

TX

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BOM options provided by this page:

Power aliases required by this page: (NONE)

Page Notes

Place one of 0.1uf cap close to each centertap pin of transformer

(NONE)

Transformers should be

(NONE)

Signal aliases required by this page:

514-0636

sides of the board

mirrored on opposite

31 79

CRITICAL

TLA-6T213HF

SM

T3900

1

10

11

12

2

3

4

5

6 7

8

9

1/16W

5%

402

MF-LF

75

R3900

1

2

1/16W

5%

402

MF-LF

75

R3901

1

2

1/16W

5% 402

MF-LF

75

R3902

1

2

1/16W

5% MF-LF

75

402

R3903

1

2

2KV

10%

1206

CERM

1000PF

CRITICAL

C3908

1 2

31 79

0.1UF

10% 16V

402

X5R

C3906

1

2

16V

10% 402

X5R

0.1UF

C3904

1

2

16V

10% 402

X5R

0.1UF

C3902

1

2

SM

TLA-6T213HF

CRITICAL

T3901

1

10

11

12

2

3

4

5

6 7

8

9

16V

10% 402

X5R

0.1UF

C3900

1

2

F-RT-TH

CRITICAL

RJ45-M97-3

J3900

1

10

11 12

2 3 4 5 6 7 8

9

CRITICAL

402-1

10PF

50V

5% CERM

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

C3910

1

2

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

C3941

1

2

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

C3940

1

2

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

402-1

10PF

CERM

5% 50V

C3931

1

2

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

C3930

1

2

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

C3921

1

2

CRITICAL

CERM

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

5% 50V

402-1

C3920

1

2

31 79

CRITICAL

PLACEMENT_NOTE=Place on MDI lines so there are no stubs all 8 caps.

10PF

CERM

5% 50V

402-1

C3911

1

2

31 79

A

33

051-7903

83

Ethernet Connector

SYNC_DATE=03/13/2009

SYNC_MASTER=K19_MLB

ENET_MDI_N<0>

ENETCONN_CTAP

ENET_MDI_N<2>

ENET_MDI_P<0>

ENET_MDI_P<1>

ENET_MDI_P<3>

ENETCONN_P<0> ENETCONN_N<0>

ENETCONN_N<1>

ENET_MDI_N<3>

ENET_CTAP0

ENETCONN_N<3>

ENET_MDI_P<2>

ENET_CTAP3

ENET_CTAP2

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

ENET_BOB_SMITH_CAP

ENET_MDI_N<1>

ENET_CTAP1

ENETCONN_N<2>

ENETCONN_P<1>

ENETCONN_P<3>

ENETCONN_P<2>

82

DS2

ATBUSH ATBUSN

VP25

OCR_CTL_V10

VAUX_DETECT

TMS

TCK

REFCLKN

PCIE_TXD0P

TRST*

ATBUSB

TDI

DS1

TPA0N TPA0P

AVREG

CE

CLKREQN

FW_RESET*

FW620* JASI_EN

MODE_A

NAND_TREE

OCR_CTL_V12

PCIE_RXD0N PCIE_RXD0P PCIE_TXD0N

PERST*

R0

REFCLKP

REGCLT

REXT

SCIFCLK SCIFDAIN SCIFDOUT

SCIFMC

SCL SDA

SE SM

TDO

TPA1N

TPA2N TPA2P TPB0N TPB0P TPB1N TPB1P TPB2N TPB2P

TPBIAS0 TPBIAS1 TPBIAS2

TPCPS

VAUX_DISABLE

VBUF

VDDH

VP

VREG_PWR

WAKE*

XI

XO

DS0

TPA1P

VDD33

VDD10

VREG_VSS

VSS

SERIAL EEPROM

MISCELLANEOUS

CONTROLLER

POWER MANAGEMENT

TEST CONTROLLER

PCI EXPRESS PHY

CHIP RESET

SCIF

1394 PHY

NC NC NC

NC

IN IN

IN

OUT

IN IN IN

BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

IN

NC NC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

(IPD) NT-2

17 mA PCIe SerDes

0 mA VReg PWR

1394B physical plug detect.

135 mA

(OD)

NT-12 (IPD)

(IPD)

(IPD) NT-1

(IPU)

(IPD) (IPD)

(IPD) NT-11

NT-15 (IPD)

NT-14 (IPD)

NT-16 (IPD)

(IPD) NT-4

(IPD) NT-3

138 mA

7 mA I/O

114 mA FireWire PHY

25 mA PCIe SerDes

110 mA Digital Core

NT-7 NT-6

NT-5

NT-OUT

(Reserved)

NT-9

(IPU) NT-8

NOTE: NT-xx notes show NAND tree order.

NT-17

(IPU)

NT-19 (IPU)

NT-10 (IPD)

FIXME!!! - TYPO IN SYMBOL REGCTL

NT-20 (IPU)

NT-21 (IPU)

NT-13

- TP (or NC) PME#

- Gate CLKREQ# based on PHY power

isolated for systems that use

NOTE: FW_PME_L and FW_CLKREQ_L are

- Alias both signals to drop = prefix

NT-18 (IPU)

WITH PLUG DETECT:

WITHOUT PLUG DETECT:

191

1% 1/16W MF-LF 402

R4170

1

2

CERM-X5R

0.33UF

6.3V 402

10%

C4162

1

2

1/16W

5%

402

MF-LF

470K

R4162

1

2

BGA

CRITICAL

FW643E

OMIT

U4100

B13 A13 A11

A10

L13

L2

F12 E12 E13

D12

K13

D1

J2

K1

J12 J13

N8 N7 N5 N6

N4

B11

N9 N10

D13

L8

G2 G1 H1 F2

N12 M11

M13 N13

M4 N2 M1 M3

B8 A8 B5 A5 B3 A3 B9 A9 B6 A6 B4 A4

B7 C3 A2

B10

N1

E1 D2

H13

A1

B1

M12N3N11

B12

C13E2E10H2H12K2L1

C1

C12F1G12J1L3

L11M2A12D5D6D8L5

L10L6L9

K12

L12

B2

D4

F7

F8

F10

G4G6G7

G8

G10

H4

H6D7H7

H8

H10

J4J5J9

J10

K4K5K7D9K8K9L7

K6

K10

D10

E4E5E9F4F6

C2

G13

F13

CERM

22PF

5%

50V 402

C4151

1 2

50V

5%

22PF

CERM

402

C4150

1 2

1%

200K

MF-LF

1/16W

402

R4160

1

2

402

1/16W

1%

MF-LF

412

R4150

1 2

10K

MF-LF

5% 1/16W

402

R4163

1

2

1/16W

10K

MF-LF

5%

402

R4164

1

2

FW643_LDO

1/16W

5%

MF-LF

10K

402

R4165

1

2

10K

MF-LF

5% 1/16W

402

R4166

1

2

CERM

6.3V 402

1UF

10%

C4130

1

2

CERM

6.3V 402

1UF

10%

C4131

1

2

CERM

6.3V 402

1UF

10%

C4100

1

2

CERM

6.3V 402

1UF

10%

C4101

1

2

1UF

CERM

6.3V 402

10%

C4132

1

2

CERM

6.3V 402

1UF

10%

C4102

1

2

CERM

6.3V 402

1UF

10%

C4103

1

2

CERM

6.3V 402

1UF

10%

C4135

1

2

CERM

6.3V 402

1UF

10%

C4136

1

2

CERM

6.3V 402

1UF

10%

C4104

1

2

CERM

6.3V 402

1UF

10%

C4110

1

2

CERM

6.3V 402

1UF

10%

C4105

1

2

CERM

6.3V 402

1UF

10%

C4106

1

2

CERM

6.3V 402

1UF

10%

C4120

1

2

CERM

6.3V 402

1UF

10%

C4121

1

2

CERM

6.3V 402

1UF

10%

C4122

1

2

CERM

6.3V 402

1UF

10%

C4123

1

2

CERM

6.3V 402

1UF

10%

C4124

1

2

402

CERM

20% 10V

0.1UF

C4141

1

2

CERM

6.3V 402

1UF

10%

C4111

1

2

10% 402

6.3V CERM

1UF

C4140

1

2

16 77

8

35

1%

1/16W

402

2.94K

MF-LF

R4161

1

2

36

36 80

36

36 80

36

35 36

36

0402-LF

120-OHM-0.3A-EMI

L4130

1 2

120-OHM-0.3A-EMI

0402-LF

L4135

1 2

35

0402-LF

120-OHM-0.3A-EMI

L4110

1 2

24.576MHZ

SM-3.2X2.5MM

CRITICAL

Y4150

2 4

1 3

0.1UF

16V X5R 40210%

PLACEMENT_NOTE=Place C4170 close to U1400

C4170

1 2

16V X5R 402

0.1UF

10%

PLACEMENT_NOTE=Place C4171 close to U1400

C4171

1 2

16V X5R 402

0.1UF

10%

PLACEMENT_NOTE=Place C4175 close to U4100

C4175

1 2

0.1UF

16V X5R 40210%

PLACEMENT_NOTE=Place C4176 close to U4100

C4176

1 2

402

1/16W

1%

MF-LF

OMIT

0.2

R4100

1 2

1

CRITICAL

R4100

RES,549mOHM,1%,1/16W,0402

114S0556

FireWire LLC/PHY (FW643E)

SYNC_MASTER=T18_MLB

SYNC_DATE=02/05/2009

051-7903

A

8334

FW643_R0 FW643_TPCPS

FW_CLK24P576M_XO_R

PPVP_FW_CPS

TP_FW643_TCK TP_FW643_TDI

TP_FW643_VBUF

TP_FW643_JASI_EN

FW643_REXT

TP_FW643_SCIFDAIN

TP_FW643_TMS FW643_TRST_L

FW643_WAKE_L FW643_REGCTL FW643_VAUX_DETECT TP_FW643_VAUX_ENABLE

FW643_SCL

FW_RESET_L

FW643_PU_RST_L

NC_FW0_TPAN NC_FW0_TPAP

NC_FW0_TPBP

FW_P1_TPBIAS

FWPHY_DS1

PP3V3_FW

FWPHY_DS0

FWPHY_DS2

NC_FW2_TPBIAS

NC_FW0_TPBIAS

NC_FW2_TPBP

NC_FW2_TPBN

FW_PORT1_TPB_P

FW_PORT1_TPB_N

NC_FW0_TPBN

NC_FW2_TPAP

NC_FW2_TPAN

FW_PORT1_TPA_N FW_PORT1_TPA_P

TP_FW643_TDO

TP_FW643_SM

TP_FW643_SE

TP_FW643_SDA

TP_FW643_SCIFDOUT

PCIE_CLK100M_FW_P

TP_FW643_NAND_TREE

TP_FW643_MODE_A

TP_FW643_FW620_L

TP_FW643_CE

TP_FW643_AVREG

PCIE_CLK100M_FW_N

TP_FW643_OCR10_CTL

FW_CLK24P576M_XO

TP_FW643_SCIFMC

VOLTAGE=1.0V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_FWPHY_AVDD

FW_CLKREQ_PHY_L

TP_FW643_SCIFCLK

PCIE_FW_R2D_P

PCIE_FW_R2D_C_P

PCIE_FW_R2D_N

PCIE_FW_R2D_C_N

PCIE_FW_D2R_C_N

PCIE_FW_D2R_N

PCIE_FW_D2R_C_P

PCIE_FW_D2R_P

FW_CLK24P576M_XI

PP1V05_FW

PP3V3_FW_FWPHY_VP25

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_FW_FWPHY_VDDA

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP3V3_FW

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.0V

MIN_LINE_WIDTH=0.4 MM

PP1V0_FW_R

36

7

34 35 36

77

7

35

7

34 35 36

D

SG

IN

D

SG

V-

V+

E

Q2

C

BD

Q1

GS

G

D

S

G

D

S

IN

G

DS

D

SG

D

SG

D

SG

D

S

G

IN

D

SG

D

SG

OUT

IN

OUT

IN

G

D

S

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT OF

SIZE

D

1.05V FW FET

Enables port power when machine is running or on AC.

Rds(on) = 90mOhm max

(NONE)

PP1V05_FW PGOOD/FW_RESET_L

I(max) = 1.7A (85C)

@ 2.5V Vgs:

3.3V FW FET

FireWire Port Power Switch

2.91V when late Vg event and port power is off

3.08V when port power is on

FWLATEVG Hysteresis:

BOM options provided by this page:

Signal aliases required by this page:

- =PPVP_FW_SUMNODE (power passthru summation node)

- =PP3V3_FW_LATEVG_ACTIVE

- =PPBUS_S5_FWPWRSW (system supply for bus power)

Power aliases required by this page:

Page Notes

Late-VG Event Detection

CERM 402

0.1UF

20% 10V

C4210

1

2

MF-LF

200K

402

1%

1/16W

R4210

1 2

10K

MF-LF

402

5%

1/16W

R4211

1

2

100pF

CERM

402

5%

50V

C4211

1

2

1/16W MF-LF 402

1%

10K

R4212

1

2

MF-LF

1% 1/16W

402

80.6K

R4213

1

2

SOI-HF

NDS9407

CRITICAL

Q4260

5

6

7

8

4

1

2

3

10%

0.1UF

X5R

25V 402

C4260

1

2

SSM6N15FEAPE

SOT563

Q4261

3

5

4

20 32 40 41

6 20 32 40 67 71

SOT563

SSM6N15FEAPE

Q4261

6

2

1

5%

10K

MF-LF

402

1/16W

R4265

12

NOSTUFF

100

1%

402

1/16W MF-LF

R4263

1 2

470K

5% 1/16W MF-LF 402

R4260

1

2

MF-LF 402

330K

5% 1/16W

R4261

1

2

NOSTUFF

402-1

X5R

1UF

10% 10V

C4263

1

2

LMC7211

SM-HF

U4210

4

3

1

5

2

SOT-563

DMB54D0UV

CRITICAL

Q4262

5

3

6 4

21

CRITICAL

1.1A-24V

MINISMDC110H24

F4260

1 2

CRS08-1.5A-30V

CRITICAL

SM

D4260

1 2

CRITICAL

BC847CDXV6TXG SOT563

Q4270

2

6

1

CRITICAL

SOT563

BC847CDXV6TXG

Q4270

5

3

4

330K

1/16W 402

5% MF-LF

R4270

1

2

56K

MF-LF 402

5% 1/16W

R4271

1

2

5%

402

MF-LF

100K

1/16W

R4274

1

2

12K

402

MF-LF

1/16W

5%

R4273

1

2

1/16W

1K

5%

402

MF-LF

R4272

1

2

DMB53D0UV

CRITICAL

SOT-563

Q4275

6

2

1

CRITICAL

DMB53D0UV

SOT-563

Q4275

5

3

4

DMB53D0UV

SOT-563

CRITICAL

Q4299

6

2

1

402

5%

MF-LF

1/16W

10K

R4283

1 2

16 24

6.3V

1UF

10%

CERM

402

C4281

1

2

SOT-563

DMB53D0UV

CRITICAL

Q4299

5

3

4

10K

1/16W

1%

MF-LF

402

R4280

1 2

402

100K

5% MF-LF

1/16W

R4281

1

2

10K

5%

402

MF-LF

1/16W

R4290

1

2

MF-LF

100K

402

5%

1/16W

R4291

1 2

16V

10%

402

X5R

0.033UF

C4290

1

2

NTR4101P

SOT-23-HF

CRITICAL

Q4291

3

1

2

10% 16V

402

CERM

0.01UF

C4291

12

SSM6N15FEAPE

SOT563

Q4290

3

5

4

SSM6N15FEAPE

SOT563

Q4293

3

5

4

1/16W

10K

MF-LF

402

5%

R4295

1

2

1/16W

402

100K

MF-LF

5%

R4296

1 2

220K

1/16W MF-LF

402

5%

R4297

1 2

SOT563

SSM6N15FEAPE

Q4293

6

2

1

NOSTUFF

0.068UF

CERM 402

10% 10V

C4295

1

2

CRITICAL

SI2312BDS

SOT23

Q4295

3

1

2

34 35

SSM6N15FEAPE

SOT563

Q4264

6

2

1

SOT563

SSM6N15FEAPE

Q4264

3

5

4

8 16

16

16V X5R 402

0.1UF

10%

C4270

1

2

34 36

8 18 35

34

18 35

0.1UF

CERM

20% 10V

402

C4296

1

2

402

1K

5% MF-LF

1/16W

R4275

1

2

18 35

DMB53D0UV

CRITICAL

SOT-563

Q4276

5

3

4

CRITICAL

DMB53D0UV

SOT-563

Q4276

6

2

1

402

5% 1/16W MF-LF

100K

R4276

1

2

NOSTUFF

0.1UF

10% 16V X5R 402

C4276

1

2

10K

MF-LF

5%

1/16W

402

R4277

1

2

FireWire Port Power

SYNC_MASTER=K19_MLB

SYNC_DATE=03/18/2009

8335

051-7903

A

LATEVG_FAULT_EVENT_PNP

LATEVG_EVENT

SMC_ADAPTER_EN

P1V05_FW_EN_L

FW_PLUG_DET_L

FW_WAKE

PP3V3_FW

FW643_WAKE_L

FW_PWR_EN

PP3V3_S5

P2V4_FWLATEVG_RC

LATEVG_RETRY_RC

FWLATEGV_3V_REF

PPVP_FW

PP3V3_S0

PP1V05_FW

FW_RESET_L

P1V0_RESET_GATE

P1V0_FW_RC

PP3V3_FW

PM_SLP_S3_L

FWPWR_EN_L

PCIE_RESET_L

PP2V4_FW_LATEVG

FW_PLUG_DET_L

FW_PWR_EN

FW_P1_TPBIAS

FW_DET_EMIT

FW_P1_TPBIAS_R

FW_PLUG_DET

FW_DET_MIRROR

PP3V3_S0

P3V3FW_SS

P3V3FW_EN_L

MAKE_BASE=TRUE

PCIE_FW_PRSNT_L

FW_CLKREQ_L

PP1V05_S0

PP1V05_FW

P1V05FW_SS

P1V05_FW_EN_L_RC

PP3V3_FW

FW_CLKREQ_PHY_L

MAKE_BASE=TRUE

FW_CLKREQ_PHY_L

FW_PWR_EN

PP3V3_S5

FW_PWR_EN

PP1V05_S0

PPBUS_G3H

FWPWR_EN_L_DIV

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPBUS_FW_FWPWRSW_F

MIN_LINE_WIDTH=0.5 mm

PPBUS_FW_FWPWRSW_D

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

FW_PWR_EN_L

LATEVG_FAULT_EVENT

8 18 35

7 34 35 36

8 34

6 7 17 19 21

22 24 28 32

35 36 42 52

62 66 67 68

69 71 82

7 36

6 7 12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49

53 57 58 61 66 67 68 69 71 72

82

6 7 12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72

82

7 34 35

7 34 35 36

6 7 12 17 18 20 21 22 23 26 27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72

82

6 7 9 10 11 12 13 16 17 19 21 22 23 35 61 65 66 67

7 34 35

7 34 35 36

34

35

18 35 6 7 17 19 21 22 24

28 32 35 36 42 52 62

66 67 68 69 71 82

18 35

6 7 9 10 11 12 13 16 17 19 21 22 23 35 61 65 66 67

6 7 44 45 59 60 62 63 64 73

SC/NC

TPA+

TPA(R)

VG

VPTPB+

TPB(R)

TPB-

TPA-

CHASSIS

GND

SGD

(SYM-VER2)

G

S

(SYM-VER1)

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

constrained on this page. It is

provide the appropriate constraints

Configures PHY for:

"Snapback" & "Late VG" Protection

NOTE: This page is expected to contain

- 1-port Portable Power Class (0)

- Port "1" Bilingual (1394B)

Power aliases required by this page:

Page Notes

for snap-back diodes

Late-VG Protection Power

PP2V4_FWLATEVG needs to be biased to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin

assumed that FireWire PHY page will

to apply to entire TPA/TPB XNets.

Termination

FW spec calls out 0.33uF

Place close to FireWire PHY

TI PHYs require 1uF even though

- =PPVP_FW_PORT1

- =PP3V3_FW_LATEVG

514S0605

beta-only device, there is no DC path between them (to avoid ground offset issue)

BREF should be hard-connected to logic ground for speed signaling and connection

appropriate connectors and/or to

NOTE: FireWire TPA/TPB pairs are NOT

Cable Power

(GND_FW_PORT1_VG)

(FW_PORT1_BREF)

AREF needs to be isolated from all

INPUT

NC

TPB<R>

TPB-

TPA-

TPA+

ESD and late-VG rail

(Common to all ports)

(NONE)

OUTPUT

BILINGUAL

- =GND_CHASSIS_FW_EMI_R

(NONE)

FireWire Design Guide (FWDG 0.6, 5/14/03)

1394b implementation based on Apple

the necessary aliases to map the FireWire TPA/TPB pairs to their

- =GND_CHASSIS_FW_PORT1

PORT 1

Signal aliases required by this page:

BOM options provided by this page:

properly terminate unused signals.

R4390 should be 390 Ohms max for a 3.3V rail

FireWire PHY Config Straps

NC

VP

TPB+

VG

TPA<R>

When a bilingual device is connected to a

Note: Trace PPVP_FW_PORT1 must handle up to 5A

local grounds per 1394b spec

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

R4363

1

2

4.99K

MF-LF

402

1%

1/16W

R4364

1

2

SIGNAL_MODEL=EMPTY

56.2

MF-LF 402

1% 1/16W

R4362

1

2

220pF

CERM 402

5% 25V

C4364

1

2

SIGNAL_MODEL=EMPTY

56.2

MF-LF

402

1%

1/16W

R4361

1

2

0.33UF

CERM-X5R 402

10%

6.3V

C4360

1

2

SIGNAL_MODEL=EMPTY

56.2

MF-LF 402

1% 1/16W

R4360

1

2

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

0.1uF

X7R

603-1

10% 50V

C4319

1

2

1M

MF-LF 402

5% 1/16W

R4319

1

2

0.01UF

X7R 402

10% 50V

C4314

1

2

CRITICAL

FERR-250-OHM

SM

L4310

1 2

0.01uF

X7R 402

10% 50V

C4310

1

2

CRITICAL

BAV99DW-X-G

SOT-363

DP4310

1

2

6

0.01uF

X7R 402

10% 50V

C4311

1

2

CRITICAL

BAV99DW-X-G

SOT-363

DP4310

4

5

3

CRITICAL

BAV99DW-X-G

SOT-363

DP4311

1

2

6

CRITICAL

BAV99DW-X-G

SOT-363

DP4311

4

5

3

0.01uF

X7R 402

10% 50V

C4313

1

2

0.01uF

X7R 402

10% 50V

C4312

1

2

332

MF-LF

402

1%

1/16W

R4390

1 2

CRITICAL

MMBZ5227BLT1H

SOT23

D4390

1

3

CRITICAL

1394B-M97

F-RT-TH

J4310

1

10 11 12 13

2

3

4

5

6

7

8

9

10K

MF-LF

402

1%

1/16W

R4381

1

2

10K

MF-LF

402

1%

1/16W

R4382

1

2

10K

MF-LF

402

1%

1/16W

R4380

1

2

BSS8402DW

SOT-363

Q4300

3

5

4

BSS8402DW

SOT-363

Q4300

6

2

1

330K

MF-LF

402

5%

1/16W

R4312

1

2

470K

MF-LF

402

5%

1/16W

R4311

1

2

SYNC_DATE=02/05/2009

SYNC_MASTER=K19_MLB

FireWire Ports

051-7903

A

36 83

PPVP_FW_PORT1_F

VOLTAGE=33V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

FW_PORT1_TPA_P

FW_PORT1_AREF

PP2V4_FW_LATEVG

PPVP_FW_CPS

VOLTAGE=12.6V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

FW_P1_TPBIAS

FW_PORT1_TPB_P

MAKE_BASE=TRUE

NC_FW0_TPBN

MAKE_BASE=TRUE

NC_FW2_TPAP

MAKE_BASE=TRUE

NC_FW0_TPAN

MAKE_BASE=TRUE

NC_FW0_TPBIAS NC_FW2_TPBIAS NC_FW0_TPAN

NC_FW2_TPAP

NC_FW2_TPAN

MAKE_BASE=TRUE

NC_FW0_TPAP

MAKE_BASE=TRUE

NC_FW0_TPBIAS

MAKE_BASE=TRUE

NC_FW2_TPBIAS

MAKE_BASE=TRUE

NC_FW0_TPBN

NC_FW2_TPBN

FW_PORT1_TPB_P

NC_FW0_TPBP

FW_PORT1_TPA_N

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_N

MAKE_BASE=TRUE

PP2V4_FW_LATEVG

VOLTAGE=2.4V

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm

FW_PORT1_TPB_C

FW_PORT1_TPB_N

PP3V3_S5

PPVP_FW

FW_PORT1_TPA_P

FWPHY_DS1

MAKE_BASE=TRUE

FWPHY_DS2

MAKE_BASE=TRUE

FWPHY_DS0

MAKE_BASE=TRUE

FWPHY_DS2

FWPHY_DS1

FWPHY_DS0

PP3V3_FW

NC_FW0_TPBP

MAKE_BASE=TRUE

NC_FW2_TPAN

NC_FW0_TPAP

NC_FW2_TPBN

MAKE_BASE=TRUE

NC_FW2_TPBP NC_FW2_TPBP

MAKE_BASE=TRUE

FW_PORT1_TPA_N

PPVP_FW_CPS

PPVP_FW

PP3V3_FW

CPS_EN_L

CPS_EN_L_DIV

FW_PORT1_TPB_N

FW_PORT1_TPB_P

FW_PORT1_TPA_N

34 36 80

35 36

34 36

34 35

34 36 80

34 36

34 36 80

34 36

34 36 80

34 36

34 36 80

34 36

34 36 80

34 36

34 36 80

35 36

34 36 80

6 7

17 19 21 22 24 28 32 35

42 52 62 66 67 68 69 71 82

7

35 36

34 36 80

34 36

7

34 35 36

34 36 80

34 36

34 36 80

34 36

34 36 34 36

34 36 80

34 36

7

35 36

7

34 35 36 34 36 80

34 36 80

OUT

IN

BI

S

G

D

OUT

IN

SYM_VER-1

OUT

IN

D

SG

D

SG

SYM_VER-1

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SATA HDD Port

Indicates disc presence

516S0687

516S0616

NOTE: 3.3V must be S0 if 5V is S3 or S5 to ensure the drive is unpowered in S3/S5.

SATA ODD Port

ODD Power Control

10% 50V

0.001UF

CERM 402

C4531

1

2

4.7

402

1/16W

MF-LF

5%

R4531

12

6

39

25 40 43 81

CRITICAL

TPCP8102

23V1K-SM

Q4590

5 6 7 8

4

1 2 3

10% CERM

6.3V 402

1UF

C4503

1

2

FERR-220-OHM

0402

L4502

1 2

SM

XW4500

1 2

SM

XW4501

1 2

SM

XW4502

1 2

SM

XW4503

1 2

SM

XW4504

1 2

SM

XW4505

1 2

6

40

MF-LF

402

5%

1/16W

33K

R4590

1

2

F-ST-SM

54722-0164

CRITICAL

J4500

1

10 11 12 13 14 15 16

2

3 4 5 6 7 8 9

20

PLACEMENT_NOTE=Place FL4520 close to J4500

CRITICAL

90-OHM-100MA

DLP11S

FL4520

12

3 4

PLACEMENT_NOTE=Place FL4525 close to J4500

CRITICAL

90-OHM-100MA

DLP11S

FL4525

1 2

34

19 77

SOT563

SSM6N15FEAPE

Q4596

3

5

4

100K

MF-LF

5%

1/16W

402

R4597

1

2

SSM6N15FEAPE

SOT563

Q4596

6

2

1

100K

MF-LF

5%

1/16W

402

R4596

1

2

100K

MF-LF

402

5%

1/16W

R4595

1 2

0.068UF

CERM 402

10% 10V

C4595

1

2

10%

0.01UF

CERM

402

16V

C4596

1 2

0.01UF

CERM

40210% 16V

PLACEMENT_NOTE=PLACE C4521 NEXT TO C4520

C4521

1 2

0.01UF

CERM

40210% 16V

PLACEMENT_NOTE=PLACE C4520 CLOSE TO MCP79

C4520

1 2

PLACEMENT_NOTE=PLACE C4526 CLOSE TO J4500

CERM

10% 16V

0.01UF

402

C4526

1 2

0.01UF

40210% 16V

CERM

PLACEMENT_NOTE=PLACE C4525 NEXT TO C4526

C4525

1 2

0603

FERR-70-OHM-4A

CRITICAL

L4500

1 2

0.1UF

20% 10V CERM 402

C4501

1

2

CRITICAL

90-OHM-100MA

DLP11S

FL4501

12

3 4

402

0.1UF

CERM

20% 10V

C4502

1

2

DLP11S

CRITICAL

90-OHM-100MA

FL4502

1 2

34

19 77

0.01UF

CERM

40210% 16V

C4516

1 2

0.01UF

40210% 16V

CERM

C4510

1 2

0.01UF

40210% 16V

CERM

C4511

1 2

0.01UF

CERM

40210% 16V

C4515

1 2

51 82

54722-0224

F-ST-SM

J4501

1

10

11 12

13 14

15 16

17 18

19

2

20

21 22

3 4

5 6

7 8

9

MF-LF

1/16W

5%

10

402

R4532

12

0.1UF

16V

10%

402

X7R-CERM

C4532

1

2

051-7903

A

8337

SATA Connectors

SYNC_MASTER=K19_MLB

SYNC_DATE=03/23/2009

ODD_PWR_SS

PP5V_S3

IR_RX_OUT

SATA_HDD_D2R_C_N

PP5V_S3

SYS_LED_ANODE

PP3V3_S0

ODD_PWR_EN_L

SATA_HDD_D2R_UF_N

SATA_HDD_R2D_UF_P

SATA_ODD_D2R_UF_N

PP3V3_S0

ODD_PWR_EN

SATA_ODD_D2R_N

SATA_ODD_R2D_UF_P

ODD_PWR_EN_LS5V_L

SATA_HDD_D2R_UF_P

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_ODD_R2D_UF_N

SATA_ODD_D2R_UF_P

SATA_ODD_R2D_N

SATA_ODD_R2D_P

SATA_ODD_D2R_P

SATA_HDD_D2R_C_P

SATA_ODD_R2D_C_N

SATA_ODD_R2D_C_P

SATA_HDD_R2D_UF_N

SATA_ODD_D2R_C_P

SATA_ODD_D2R_C_N

SMC_ODD_DETECT

SATA_HDD_R2D_N

SATA_HDD_R2D_P

PP5V_S3_IR_R

SYS_LED_ANODE_R

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

PP1V5_S0

PP1V5_S0_HDD_FLT

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.3mm

VOLTAGE=1.5V

ISNS_HDD_N

ISNS_HDD_P

PP5V_S0_HDD_R

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm VOLTAGE=5V

PP5V_S0

ISNS_ODD_P

ISNS_ODD_N

PP5V_SW_ODD_R

VOLTAGE=5V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm

PP5V_SW_ODD

VOLTAGE=5V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.4mm

PP5V_S0_HDD_FLT

MIN_NECK_WIDTH=0.4mm

MIN_LINE_WIDTH=0.6mm VOLTAGE=5V

PLACEMENT_NOTE=PLACE C4503 CLOSE TO J4501

PLACEMENT_NOTE=PLACE L4500 CLOSE TO J4501

PLACEMENT_NOTE=PLACE C4501 CLOSE TO J4501

PLACEMENT_NOTE=Place FL4501 close to J4501

PLACEMENT_NOTE=PLACE C4502 CLOSE TO J4501

PLACEMENT_NOTE=PLACE FL4502 CLOSE TO J4501

PLACEMENT_NOTE=Place C4516 close to J4501

PLACEMENT_NOTE=Place C4510 close to MCP79 PLACEMENT_NOTE=Place C4511 next to C4510

PLACEMENT_NOTE=Place C4515 next to C4516

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6

77

6 7 8

29 37 38 39 41 49 51 53

62 63 68

41

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72

82

6

82

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72

82

6

82

6

77

6

77

6

77

82

6

77

6

77

6 6

6 7

10 11 15 22 66 67 68

82

6 7

42 47 49 61 64 65 67 68

70 72

6

51

6

OUT

BI

SYM_VER-1

IN OUT

IN

SYM_VER-1

BI

OUT

IOIONC

GND

VBUS

NC

IOIONC

GND

VBUS

NC

OUT2

TPAD

GND

OUT1

OC1*

EN2

EN1 OC2*

IN

VCC

GND

SELOE*

D+ D-

Y+ Y-

M+ M-

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

514-0606

We can add protection to 5V if we want, but leaving NC for now

Place L4600 and L4605 at connector pin

Left USB Port B

Port Power Switch

SEL=1 Choose USB

SEL=0 Choose SMC

Left USB Port A

USB/SMC Debug Mux

CRITICAL

FERR-220-OHM-2.5A

0603

L4605

1 2

CRITICAL

100UF

POLY-TANT CASE-B2-SM

20%

6.3V

C4696

1

2

10UF

X5R 603

20%

6.3V

C4695

1

2

0.1UF

CERM 402

20% 10V

C4691

1

2

19

19 78

SMC_DEBUG_YES

0.1UF

CERM

402

20% 10V

C4650

1

2

10K

MF-LF 402

5% 1/16W

R4650

1

2

CRITICAL

90-OHM-100MA

DLP11S

L4600

1 2

34

40 41 42

40

SMC_DEBUG_NO

0

MF-LF

402

5%

1/16W

R4651

1 2

SMC_DEBUG_NO

0

MF-LF

402

5%

1/16W

R4652

1 2

0.01uF

CERM

402

20% 16V

C4605

1

2

0.01uF

CERM 402

20% 16V

C4615

1

2

CRITICAL

FERR-220-OHM-2.5A

0603

L4615

1 2

CRITICAL

90-OHM-100MA

DLP11S

L4610

1 2

34

10UF

X5R 603

20%

6.3V

C4617

1

2

CRITICAL

100UF

POLY-TANT CASE-B2-SM

20%

6.3V

C4616

1

2

19 78

19

CRITICAL

RCLAMP0502N

SLP1210N6

D4600

1

5 42 3

6

CRITICAL

RCLAMP0502N

SLP1210N6

D4610

1

5 42 3

6

10UF

X5R 603

20%

6.3V

C4690

1

2

CRITICAL

USB

F-RT-TH-M97-4

J4600

1 2 3 4

5 6

7 8

CRITICAL

USB

F-RT-TH-M97-4

J4610

1 2 3 4

5 6

7 8

CRITICAL

TPS2064DGN

MSOP

Q4690

3

4

1

2

8

5

7

6

9

5.1K

MF-LF 402

5% 1/16W

R4690

1

2

0.47UF

X5R 402

10% 10V

C4692

1

2

SIGNAL_MODEL=USB_MUX

SMC_DEBUG_YES

CRITICAL

PI3USB102ZLE

TQFN

U4650

6

7

3

4

5

8

10

9

2

1

SYNC_DATE=02/05/2009

38 83

A

051-7903

External USB Connectors

SYNC_MASTER=K19_MLB

PP5V_S3_RTUSB_A_F

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm

USB2_LT1_N

USB2_LT1_P

USB_EXTB_OC_L

USB_EXTA_N

USB_EXTA_P

SMC_RX_L SMC_TX_L

PP3V42_G3H

USB_PWR_EN

PP5V_S3

PM_SLP_S4_L

USB_EXTB_N

USB_EXTB_P

PP5V_S3_RTUSB_A_ILIM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm

USB_EXTA_OC_L

USB_DEBUGPRT_EN_L

PP5V_S3_RTUSB_B_ILIM

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm

USB_LT2_N

USB_LT2_P

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_N

PP5V_S3_RTUSB_B_F

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.375 mm

82

6 7

20 21 24 40

41 42 43 45 48 59

60 67

6 7 8

29 37 39 41 49 51 53 62

63 68

6

20 40 41 67

82

BI BI

VCC

P1.0/D+ P1.1/DP1.2/VREG P1.3/SSEL P1.4/SCLK

P1.5/SMOSI

P1.6/SMISO

P0.0

P0.1 INT0/P0.2 INT1/P0.3

TIO1/P0.6

NC

TIO0/P0.5

INT2/P0.4

VSSPAD

THRML

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

IR SUPPORT

19 78

1UF

X5R 402-1

10% 10V

C4803

1

2

CY7C63803-LQXC

QFN

OMIT

CRITICAL

U4800

5 4 3

8

9 10 20 21 22 23 24

7 6

12 13 15 16 17 18 19

25

2 1

14

11

X7R-CERM

10%

0.1UF

402

16V

C4801

1

2

0.001UF

CERM 402

10% 50V

C4804

1

2

100

MF-LF

402

5%

1/16W

R4800

1 2

6

37

SYNC_MASTER=K19_MLB

SYNC_DATE=02/05/2009

39 83

A

051-7903

Front Flex Support

IR_RX_OUT_RC

IR_RX_OUT

USB_IR_P

DIFFERENTIAL_PAIR=USB2_IR

USB_IR_N

DIFFERENTIAL_PAIR=USB2_IR

IR_VREF_FILTER

PP5V_S3

P/N 338S0633

6 7 8

29 37 38 41 49 51 53 62

63 68

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT IN

OUT

BI

IN

OUT

BI

OUT

IN

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

BI

OUT

IN

OUT

NC

OUT

NC

NC NC NC

NC

NC NC

NC NC NC

NC

NC NC

NC

NC NC

IN

OUT

P13 P14 P15 P16 P66

P10 P11 P12

P17

P20 P21 P22 P23 P24 P25 P26 P27

P30 P31 P32 P33 P34

P36 P37

P40 P41 P42 P43 P44 P45 P46 P47

P50 P51 P52

P60 P61 P62 P63 P64 P65

P67

P70 P71 P72 P73 P74 P75 P76 P77

P80 P81

P84 P85 P86

P90 P91 P92 P93 P94 P95 P96 P97

P35

P83

P82

(1 OF 3)

PA5

PA4

PA0 PA1 PA2 PA3

PA6 PA7

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7

PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7

PD0 PD1 PD2 PD3 PD4 PD5 PD6 PD7

PE0 PE1 PE2 PE3 PE4 PF0

PF1 PF2 PF3 PF4 PF5 PF6 PF7

PG0 PG1 PG2 PG3 PG4 PG5 PG6 PG7

PH0 PH1 PH2 PH3 PH4 PH5

(2 OF 3)

RES*

NMI

VSS

VCLVCC

NC

MD2

MD1

ETRST

AVSS

AVREF

AVCC

EXTAL

XTAL

(3 OF 3)

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NOTE: P94 and P95 are shorted, P95 could be spare.

(OC) (OC)

If SMS interrupt is not used, pull up to SMC rail.

NOTE: SMS Interrupt can be active high or low, rename net accordingly.

pins designed as outputs can be left floating,

(OC)

(OC) (OC)

(DEBUG_SW_2)

(DEBUG_SW_1)

(OC)

(OC) (OC)

(OC)

NOTE: Unused pins have "SMC_Pxx" names. Unused

(See below)

SMC_PB3: SMC_IG_THROTTLE_L for MG systems.

Otherwise, TP/NC okay (was ISENSE_CAL_EN)

those designated as inputs require pull-ups.

22UF

805

CERM

20%

6.3V

C4902

1

2

18 42

41 42

41 48

10% 402

CERM-X5R

0.47UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

6.3V

C4907

1

2

10V 402

0.1UF

CERM

20%

C4903

1

2

10V 402

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

0.1UF

CERM

20%

C4920

1

2

402

MF-LF

5%

1/16W

4.7

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

R4999

1 2

10V 402

0.1UF

CERM

20%

C4904

1

2

SM

XW4900

12

20

61

10V 402

0.1UF

CERM

20%

C4905

1

2

20

67

24 62 64 65 66 67

41

10V 402

0.1UF

CERM

20%

C4906

1

2

45

44

41

45

44

45

41

41 59 60

38 40 41 42

6 8

62 67

25 37 43 81

402

1/16W

5%

MF-LF

10K

R4909

1

2

42

402

1/16W

5%

10K

MF-LF

R4901

1

2

402

10K

MF-LF

5% 1/16W

R4902

1

2

402

1/16W

5% MF-LF

0

NO STUFF

R4903

1

2

402

1/16W

5% MF-LF

10K

R4998

1

2

38

59

20

6

37

41

20

41

47

41

47

50

41 45

50

41 44

41 45

41 42

41

41 42

41 48 59

6

43 59 60 81

6

43 59 60 81

6

29 43 49 81

6

29 43 49 81

43 46 81

41

38 40 41 42

41

18 42

20 26 27

24

42

20

18 42

20 41

50

20 32 35 41

6

41 59

41

H8S2117

LGA-HF

OMIT

U4900

B12 A13 A12 B13 D11 C13 C12 D10

D13 E11 D12 F11 E13 E12 F13 E10

A9 D9 C8 B7 A8 D8 D7 D6

D4 A5 B4 A1 C2 B2 C1 C3

G2 F3 E4

L13 K12 K11 J12 K13 J10 J11 H12

N10 M11 L10 N11 N12 M13 N13 L12

A7 B6 C7 D5 A6 B5 C6

J4 G3 H2 G1 H4 G4 F4 F1

OMIT

LGA-HF

H8S2117

U4900

N3 N1 M3 M2 N2 L1 K3 L2

B8 C9

B9 A10 C10 B10 C11 A11

G11 G13 F12 H13 G10 G12 H11 J13

M10

N9 K10

L8

M9

N8

K9

L7

K1 J3 K2 J1 K4 K5

N5 M6 L5 M5 N4 L4 M4

M8 N7 K8 K7 K6 N6 M7 L6

E2 F2 J2 A4 B3 C4

OMIT

LGA-HF

H8S2117

U4900

M12

L11

L9

H3

A2

D1 H1

E5

E3

D3

B1M1H10

E1

D2

L3

F10

B11

C5

A3

18 42 78

24

24 78

49

43 46 51 81

6

20 32 35 67 71

6

20 38 40 41 67

6

20 38 40 41 67

24 78

43 46 51 81

25 37 43 81

41

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

051-7903

A

8340

SMC

PM_CLKRUN_L LPC_PWRDWN_L

SMC_LRESET_L

SMBUS_SMC_0_S0_SDA

PM_CLK32K_SUSCLK

PM_SLP_S4_L

PM_SLP_S3_L

SMC_BS_ALRT_L

SMC_BC_ACOK

SMC_ONOFF_L

SMBUS_SMC_MGMT_SCL

SMC_RX_L

SMC_TX_L

SMC_WAKE_SCI_L

TP_SMC_CPU_HI_ISENSE

SMC_BATT_ISENSE

SMC_PBUS_VSENSE

SMC_DCIN_ISENSE

TP_SMC_GPU_VSENSE

TP_SMC_GPU_ISENSE

SMC_CPU_VSENSE

SMC_CPU_ISENSE

SMC_BIL_BUTTON_L

SMC_ADAPTER_EN

SMC_PM_G2_EN

SMBUS_SMC_0_S0_SCL

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMC_IG_THROTTLE_L

SMS_PWRDN

SMBUS_SMC_MGMT_SDA

TP_SMC_P41

LPC_SERIRQ

LPC_CLK33M_SMC

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

SMC_BMON_MUX_SEL

TP_SMC_P24

TP_ESTARLDO_EN

PM_PWRBTN_L

ALL_SYS_PWRGD

TP_SMC_RSTGATE_L

TP_SMC_EXCARD_PWR_EN

SMC_PROCHOT_3_3_L

IMVP_VR_ON

PM_RSMRST_L

RSMRST_PWRGD

TP_ALS_GAIN

SMC_PH2

SMC_THRMTRIP

SMC_PROCHOT

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

SMS_INT_L

SMC_MCP_SAFE_MODE

SMC_LID

SMC_SYS_LED

SMC_TMS

SMC_TDO

SMC_TDI

SMC_TCK

SMC_CASE_OPEN

SMC_CPU_FSB_ISENSE

SMC_MCP_VSENSE

SMC_MCP_DDR_ISENSE

SMC_MCP_CORE_ISENSE

TP_SMC_GPU_1V8_ISENSE

SMS_Z_AXIS

SMS_Y_AXIS

SMS_X_AXIS

NC_SMC_FAN_3_TACH

NC_SMC_FAN_2_TACH

TP_SMC_FAN_1_TACH

SMC_FAN_0_TACH

NC_SMC_FAN_3_CTL

NC_SMC_FAN_2_CTL

TP_SMC_FAN_1_CTL

SMC_FAN_0_CTL

SMC_GFX_OVERTEMP_L

SMC_EXCARD_OC_L

SMC_EXCARD_CP

TP_SMC_PB3

SMC_ODD_DETECT

SMC_RUNTIME_SCI_L

PM_BATLOW_L

SYS_ONEWIRE

USB_DEBUGPRT_EN_L

PM_SYSRST_L

SMC_PA1

SMC_PA0

MEM_EVENT_L

SMC_PA5

SMC_NMI

SMC_KBC_MDE

SMC_MD1

SMC_TRST_L

GND_SMC_AVSS

SMC_XTAL SMC_EXTAL

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

PP3V3_S5_AVREF_SMC PP3V42_G3H

SMC_VCL

SMC_RESET_L

41

41 45

41

41 44 45

41

6

41

6 7

20 21 24 38 41 42 43 45

48 59 60 67

D

S G

CD

GND

NC

OUT

IN

OUT

IN

OUT

BI

IN

D

S G

GND

OUT

IN

02

D

SG

NC

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

E

Q2

C

BD

Q1

GS

OUT

G

D

S

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

SMC Crystal Circuit

SMC Reset "Button" / Brownout Detect

SMC AVREF Supply

SMC Pull-downs

Debug Power "Buttons"

SMC Pull-ups

PLACEMENT_NOTEs:

TO CPU

SMC Aliases

Unused Pins

System (Sleep) LED Circuit

SMC FSB to 3.3V Level Shifting

TO SMC

10V

20%

402

CERM

0.1uF

C5000

1

2

SSM6N15FEAPE

SOT563

Q5059

3

5

4

CERM-X5R

0.47UF

402

10%

6.3V

C5020

1

2

0.01UF

CERM 402

10% 16V

C5026

1

2

10uF

X5R 603

20%

6.3V

C5025

1

2

1/16W

5% 402

10K

MF-LF

R5070

1 2

1/16W

5% 402

MF-LF

100K

R5071

1 2

1/16W5%MF-LF

10K

402

R5072

1 2

10K

MF-LF

4025%

1/16W

R5073

1 2

100K

MF-LF

4025%

1/16W

R5074

1 2

MF-LF

402

100K

1/16W

5%

R5076

1 2

1/16W

5% 402

MF-LF

10K

R5077

1 2

1/16W

5% 402

MF-LF

10K

R5078

1 2

1/16W

5% 402

10K

MF-LF

R5079

1 2

1/16W

5% 402

MF-LF

10K

R5080

1 2

10K

4025%

MF-LF1/16W

R5085

1 2

10K

MF-LF

4025%

1/16W

R5086

1 2

10K

MF-LF

4025%

1/16W

R5088

1 2

NCP303LSN

SOT23-5-HF

CRITICAL

U5000

5

3

2

4

1

5%

1/16W

402

MF-LF

100K

R5090

1 2

40 42

40

9

13 75

1/10W

5%

603

MF-LF

0

OMIT

PLACEMENT_NOTE=Place R5001 on BOTTOM side

SILK_PART=SMC_RST

R5001

1

2

SILK_PART=PWR_BTN

OMIT

0

MF-LF 603

5% 1/10W

Place R5015 on BOTTOM side

R5015

1

2

1/16W

5%

402

MF-LF

3.3K

R5062

1 2

9

13 61 75

40

SSM6N15FEAPE

SOT563

Q5059

6

2

1

100K

MF-LF

4025%

1/16W

R5091

1 2

100K

MF-LF

4025%

1/16W

R5092

1 2

SOT23-3

REF3333

CRITICAL

VR5020

3

1 2

1/16W

5%

402

1K

MF-LF

R5000

1

2

1/16W

5% 402

MF-LF

10K

R5089

1 2

1/16W

5% 402

MF-LF

10K

R5081

1 2

5%

402

MF-LF

0

1/16W

R5010

1 2

5X3.2-SM

20.00MHZ

CRITICAL

Y5010

1

2

50V

5%

402

15pF

CERM

C5011

1 2

15pF

CERM

402

5%

50V

C5010

1 2

1/16W

5% 402

MF-LF

470K

R5087

1 2

SOT553-5

SN74LVC1G02

PLACEMENT_NOTE=Place next to U5000 (shares C5000)

U5001

1

2

3

5

4

SSM6N15FEAPE

SOT563

Q5032

3

5

4

4025%

1/16W MF-LF

10K

R5093

1 2

48

40 41 48

SILK_PART=PWR_BTN

0

MF-LF

603

5%

1/10W

Place R5014 on TOP side

OMIT

R5014

1

2

40 41

40 41 59 60 40 41 59 60

20 40 41 20 40 41

40 41

40 41 45 40 41 45

40 41 44

40 41 45

40 41

5%

1/16W

0

MF-LF

402

R5096

1 2

40 20

40 41

MF-LF

4025%

1/16W

10K

R5095

1 2

40 41

1/16W

5% 402

MF-LF

10K

R5094

1 2

40 41

40

402

1/16W

1%

MF-LF

1.47K

R5032

1

2

402

523

MF-LF

1%

1/16W

R5031

1

2

1/16W

20

1% MF-LF

402

R5030

1

2

DMB54D0UV

SOT-563

Q5030

5

3

6 4

21

37

DMB53D0UV

SOT-563

Q5060

5

3

4

402

100K

5% 1/16W MF-LF

R5061

1

2

DMB53D0UV

SOT-563

Q5060

6

2

1

MF-LF

10K

402

5% 1/16W

R5060

1

2

40

40 41 48

0.01UF

16V

10% 402

CERM

C5001

1

2

Intersil ISL60002-33

353S1912

ALL

353S1381

SYNC_DATE=(11/25/2008)

SYNC_MASTER=(K19_MLB)

A

8341

051-7903

SMC Support

SMC_SYS_LED

SMC_PROCHOT_3_3_L

PP3V3_S0

CPU_PROCHOT_BUF

CPU_PROCHOT_L_R

SMC_PROCHOT

PP5V_S3

SYS_LED_L

SYS_LED_L_VDIV

SYS_LED_ANODE

SYS_LED_ILIM

SMC_MCP_CORE_ISENSE

NC_SMC_FAN_3_CTL

TP_SMC_EXCARD_PWR_EN

MAKE_BASE=TRUE

TP_SMC_RSTGATE_L

TP_SMC_P24

TP_ALS_GAIN TP_ALS_GAIN

MAKE_BASE=TRUE

PM_SLP_S4_L

SMC_EXCARD_CP

SMC_CASE_OPEN

PM_SLP_S4_L

TP_SMC_FAN_1_TACH

NC_SMC_FAN_2_TACH

NC_SMC_FAN_3_TACH

TP_SMC_FAN_1_CTL TP_SMC_FAN_1_CTL

MAKE_BASE=TRUE

NC_SMC_FAN_2_CTL NC_SMC_FAN_2_CTL

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_3_CTL

MAKE_BASE=TRUE

SMC_BC_ACOK

SMC_MCP_DDR_ISENSE

SMC_BC_ACOK

SMC_MANUAL_RST_L

PP3V42_G3H

SMC_RESET_L

SMC_TPAD_RST

SMC_TPAD_RST_L

SMC_ONOFF_L

PP3V42_G3H

MIN_NECK_WIDTH=0.2 mm

PP3V3_S5_AVREF_SMC

MIN_LINE_WIDTH=0.4 mm VOLTAGE=3.3V

CPU_PROCHOT_L

PM_THRMTRIP_L

SMC_ONOFF_L

SMC_THRMTRIP

TP_SMC_FAN_1_TACH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_2_TACH

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_SMC_FAN_3_TACH

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

SMS_INT_L

SMC_IG_THROTTLE_L

SMC_MCP_SAFE_MODE

TP_SMC_CPU_HI_ISENSE TP_SMC_GPU_1V8_ISENSE TP_SMC_GPU_ISENSE

SMC_MCP_DDR_ISENSE

MAKE_BASE=TRUE

TP_SMC_CPU_HI_ISENSE

MAKE_BASE=TRUE

TP_SMC_GPU_1V8_ISENSE

MAKE_BASE=TRUE

TP_SMC_GPU_ISENSE

MAKE_BASE=TRUE

TP_SMC_GPU_VSENSE

MAKE_BASE=TRUE

MCP_SPKR

PP3V3_S0

SMC_PA0 SMC_PA1 SMC_PH2

SMC_LID

SMC_ONOFF_L

SMC_TMS SMC_TDO SMC_TDI

SMC_BC_ACOK

SMC_TX_L

SMC_BS_ALRT_L

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

GND_SMC_AVSS

SMC_ADAPTER_EN

SMC_RX_L

SMC_PA5

SMC_EXCARD_OC_L

SMC_GFX_OVERTEMP_L

SMS_INT_L

SMC_BIL_BUTTON_L

PP3V42_G3H

MAKE_BASE=TRUE

TP_SMC_PB3

TP_SMC_P41

MAKE_BASE=TRUE

TP_SMC_P24

MAKE_BASE=TRUE

TP_SMC_EXCARD_PWR_EN

TP_ESTARLDO_EN

MAKE_BASE=TRUE

TP_ESTARLDO_EN

TP_SMC_RSTGATE_L

TP_SMC_P41 TP_SMC_PB3

SMC_MCP_CORE_ISENSE

MAKE_BASE=TRUE

SMC_CPU_FSB_ISENSE

MAKE_BASE=TRUE

SMC_MCP_VSENSE

MAKE_BASE=TRUE

SMC_MCP_VSENSE SMC_CPU_FSB_ISENSE

TP_SMC_GPU_VSENSE

SMS_INT_L

MAKE_BASE=TRUE

SMC_BMON_MUX_SEL

MAKE_BASE=TRUE

SMC_IG_THROTTLE_L

SMC_XTAL

SMC_XTAL_R

SMC_EXTAL

SMC_TCK

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

6 7 8

29 37 38 39 49

51 53 62 63 68

40 41

6

20 38 40 41 67

40

6

20 38 40 41 67

40 41

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

20 21 24 38 40 41 42

43 45 48 59 60 67

6

40

40 41

40 41 45

40 41

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

40

40 48 59

40 41 48

40 42

40 41 59 60

38 40 42

40

40 44 45

20 32 35 40

38 40 42

40

40 41

6

40 59

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

40 41

40 41 45

40 41 44

40 41

40

40 42

IN

BI

IN OUT OUT OUT

BI BI

IN OUT IN OUT OUT IN OUT IN

OUT OUT OUT

OUT

IN

OUT

IN

OUT

IN

OUT OUT

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

BI

VCC

GND

SEL OE*

D+ D-

Y+ Y-

M+ M-

IN

OUT

IN

BI

IN

OUT

IN

OUT

IN

OUT

IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Pull-up on debug card

LPC+SPI Connector

SPI MUX BYPASS

SEL LOW OUTPUTS TO M (FRANKCARD ROM)

SEL HIGH OUTPUTS TO D (ON BOARD ROM)

Alternate SPI ROM Support

516S0573

42

18 40

40 41

M-ST-SM

55909-0374

CRITICAL

LPCPLUS

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

18 40 78

42

18 40 78

18 40

40 41

24

40 41

40

38 40 41

17

40

42

42 52

52

24 78

20K

MF-LF

402

5%

1/16W

R5144

1

2

42

42 52

LPCPLUS

0.1UF

CERM 402

20% 10V

C5114

1

2

LPCPLUS

CRITICAL

PI3USB102ZLE

TQFN

U5110

6

7

3

4

5

8

10

9

2

1

18 40 78

LPCPLUS

0.1UF

CERM 402

20% 10V

C5124

1

2

LPCPLUS

CRITICAL

PI3USB102ZLE

TQFN

U5120

6

7

3

4

5

8

10

9

2

1

10K

MF-LF

402

5%

1/16W

R5190

1

2

20 78

20 42 78

18 40 78

20 42 78

PLACEMENT_NOTE=PLACE NEXT TO U1400

LPCPLUS_NOT

0

MF-LF

402

5%

1/16W

R5146

1 2

LPCPLUS_NOT

0

MF-LF

402

5%

1/16W

R5157

1 2

LPCPLUS_NOT

0

MF-LF

402

5%

1/16W

R5156

1 2

LPCPLUS_NOT

0

MF-LF

402

5%

1/16W

R5158

1 2

20 42 78

10K

MF-LF

402

5%

1/16W

R5191

1

2

20 42

20 42 78

42 52

20 42

100K

MF-LF

402

5%

1/16W

R5140

1

2

42

SYNC_MASTER=K19_MLB

SYNC_DATE=02/05/2009

051-7903

42 83

A

LPC+SPI Debug Connector

SMC_TRST_L

DEBUG_RESET_L

LPC_FRAME_L

SPI_ALT_MOSI

LPC_AD<1>

LPC_AD<0>

SMC_MD1

SMC_TDO

SMC_TMS

PM_CLKRUN_L

SPI_ALT_MISO

LPCPLUS_GPIO

SMC_RX_L

SMC_NMI

SMC_RESET_L

SMC_TCK

SMC_TDI

LPC_PWRDWN_L

LPC_SERIRQ

SPI_ALT_CS_L

SPI_ALT_CLK

SPIROM_USE_MLB

LPC_AD<3>

LPC_AD<2>

LPC_CLK33M_LPCPLUS

PP5V_S0

PP3V42_G3H

SPI_MOSI_MUX

SPI_MLB_CS_L

SPIROM_USE_MLB

SPI_CS0_R_L

SPI_ALT_MISO

PP3V42_G3H

SPI_CLK_R

SPI_MOSI_R

SPI_ALT_CLK SPI_ALT_MOSI

SPI_ALT_CS_L

SPI_MISO_MUX

PP3V3_S5

SPI_MISO

SPI_MOSI_R

SPI_CLK_R

SPI_MISO

SPI_CLK_MUX

SPI_MISO_MUX

SPI_MOSI_MUX

PP3V3_S5

SPI_CLK_MUX

SPIROM_USE_MLB

MAKE_BASE=TRUE

PP3V42_G3H

SMC_TX_L

6 7

37 47 49 61 64 65 67 68

70 72

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

17 19 21 22 24 28 32 35 36

42 52 62 66 67 68 69 71 82

6 7

17 19 21 22 24 28 32 35

36 42 52 62 66 67 68 69 71 82

20

42

6 7

20 21 24 38

40 41 42 43 45 48

59 60 67

NBC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

HDD Margin Ctrl.

(Write: 0xXX Read: 0xXX)

J4501

SMC

Vref DACs

The bus formerly known as "Battery B"

(Write: 0x58 Read: 0x59)

U2900

(Write: 0x30 Read: 0x31)

U2901

(MASTER)

U4900

SMC

U5930

Sensor ADCs

SMC

(MASTER/SLAVE)

U6860

(Write: 0x90 Read: 0x91)

EMC1403-5: U5535

(MASTER)

TRACKPAD

J5800

J3401

ALS

(Write: 0x52 Read: 0x53)

EMC1403-5: U5515

CPU Temp

(Write: 0x98 Read: 0x99)

(MASTER)

U1400

SMC "A" SMBus Connections

NOTE: SMC RMT bus remains powered and may be active in S3 state

SMC

J3200

U1400

Battery Manager - (Write: 0x16 Read: 0x17)

U4900

Battery LED Driver - (Write: 0x36 Read: 0x37)

Battery

Mikey

U9700 (DEFAULT)

LP8543 (Bklt)

SO-DIMM "A"

J3100

(Write: 0xA2 Read: 0xA3)

SMC

U4900

MCP79

(WRITE: 0X72 READ: 0X73)

Battery Temp - (Write: 0x90 Read: 0x91)

(MASTER)

MCP79 SMBUS "0" CONNECTIONS

MCP79 SMBUS "1" CONNECTIONS

MCP79

SMC "Management" SMBus Connections

Margin Control

(Write: 0x98 Read: 0x99)

J6950 & J6955

U4900

SMC "Battery A" SMBus Connections

Battery Charger

ISL6258A - U7000

(Write: 0x10 Read: 0x11)

(Write: 0x12 Read: 0x13)

(Write: 0x98 Read: 0x99)

MCP Temp

SO-DIMM "B"

(Write: 0xA0 Read: 0xA1)

(MASTER)

U4900

SMC "0" SMBus Connections

SMC "B" SMBus Connections

BATTERY & BIL

(See Table)

1/16W

402

2.61K

1%

MF-LF

R5280

1

2

MF-LF

1/16W 402

2.61K

1%

R5281

1

2

4.7K

402

5% 1/16W MF-LF

R5261

1

2

4.7K

5%

MF-LF

1/16W

402

R5260

1

2

402

5% 1/16W

1K

MF-LF

R5271

1

2

402

5% 1/16W MF-LF

1K

R5270

1

2

4.7K

MF-LF

1/16W

5%

402

R5251

1

2

4.7K

1/16W

5%

402

MF-LF

R5250

1

2

402

5%

2.0K

1/16W MF-LF

R5231

1

2

5%

MF-LF

1/16W

402

2.0K

R5230

1

2

402

5%

MF-LF

4.7K

1/16W

R5290

1

2

MF-LF 402

1/16W

5%

4.7K

R5291

1

2

MF-LF

402

1/16W

5%

1K

R5200

1

2

MF-LF

1K

1/16W

5%

402

R5201

1

2

051-7903

8343

A

K19i SMBus Connections

SYNC_MASTER=WFERRY_K19I

SYNC_DATE=12/12/2008

PP3V3_S0

SMBUS_MCP_0_CLK

MAKE_BASE=TRUE

SMBUS_MCP_0_DATA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_0_S0_SDA

SMBUS_MCP_0_CLK SMBUS_MCP_0_DATA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

SMBUS_SMC_0_S0_SCLSMBUS_SMC_0_S0_SCL

MAKE_BASE=TRUE

PP3V3_S0

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

SMBUS_MCP_1_CLK

PP3V3_S0

SMBUS_SMC_MGMT_SDA

SMBUS_MCP_1_CLK

SMBUS_SMC_B_S0_SCL

MAKE_BASE=TRUE

SMBUS_MCP_1_DATA

SMBUS_SMC_MGMT_SCL

PP3V3_S3

SMBUS_MCP_1_CLK

PP3V42_G3H

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_A_S3_SCL

PP3V3_S0

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_MCP_0_CLK

PP3V3_S3

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

=I2C_SODIMMB_SDA

SMBUS_MCP_1_DATA

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_MGMT_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_BSA_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_MGMT_SCL

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72

82

12 20 26 27 43 78

12 20 26 43 78

6

40 43

59 60 81

40 43 46 51 81

12 20 26 27 43 78

12 20 26 43 78

40 43 46 51 81

40

43 46

51

81

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72

82

25 37 40 43 81

20 43 58 72 78

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72

82

25 37 40 43 81

20 43 58 72 78

40 43 46 81

20 43 58 72 78

25 37 40 43 81

6 7

20 25 29 30 43 48 50 68

20 43 58 72 78

6 7

20 21 24 38 40 41 42 45

48 59 60 67

6

29 40

43 49 81

6

29 40

43 49 81

6

29 40

43 49 81

6

29 40

43 49 81

40 43 46 51 81

40 43 46 81

40

43 46

81

40

43 46

81

6

29 40 43

49 81

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72

82

40 43 46 51 81

6

29 40 43

49 81

12 20 26 27 43 78

6 7

20 25 29 30 43 48 50 68

27

20 43 58 72 78

40 43 46 51 81

40

43 46

51 81

6

40 43

59 60 81

6

40 43

59 60 81

6

40 43 59

60 81

6

40 43 59

60 81

25 37 40 43 81

25

37 40

43

81

25

37 40

43 81

6

40 43

59 60 81

40 43 46 81

25 37 40 43 81

OUT

D

N-CHANNEL

P-CHANNEL

G

S

D

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Enables PBUS VSense

Place RC close to SMC

RTHEVENIN = 4573 OHMS

Place RC close to SMC

PBUS VOLTAGE SENSE ENABLE & FILTER

divider when high.

CPU Voltage Sense / Filter

MCP Voltage Sense / Filter

40 41

402

0.22UF

6.3V X5R

20%

C5359

1

2

1%

4.53K

1/16W MF-LF

402

R5359

1 2

SOT-963

NTUD3127CXXG

Q5315

6

3

2

5

1

4

67 68

1%

1/16W

402

100K

MF-LF

R5316

1

2

MF-LF

100K

402

1%

1/16W

R5315

1

2

40

402

6.3V

20%

X5R

0.22UF

C5385

1

2

1%

402

MF-LF

1/16W

27.4K

R5385

1

2

1% 1/16W MF-LF

402

5.49K

R5386

1

2

PLACEMENT_NOTE=Place near U1400 center

SM

XW5359

1 2

40

4.53K

1/16W

1%

402

MF-LF

R5309

1 2

402

0.22UF

20%

6.3V X5R

C5309

1

2

PLACEMENT_NOTE=Place near U1000 center

SM

XW5309

1 2

VOLTAGE SENSING

SYNC_MASTER=K24_MLB

SYNC_DATE=02/05/2009

A

44 83

051-7903

SMC_MCP_VSENSE

MCPVSENSE_IN

PPBUS_G3H

PBUSVSENS_EN_L_DIV

PPVCORE_S0_CPU

GND_SMC_AVSS

SMC_CPU_VSENSE

CPUVSENSE_IN

GND_SMC_AVSS

SMC_PBUS_VSENSE

GND_SMC_AVSS

PPVCORE_S0_MCP

PBUSVSENS_EN_L

PM_SLP_S3_L_BUF

VOLTAGE=18.5V

PPBUS_G3HRS5_VSENSE

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.20 mm

6 7

35 45 59 60 62 63 64 73

6 7

10 11 61

40 41 44 45

6 7

21 22 64

OUT

V+

REFIN+

IN-

OUT

GND

OUT

IN

V+

REFIN+

IN-

OUT

GND

IN

OUT

IN

OUT

VER 1

VCC

A

1

0

B1

GND

B0

SEL

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(For R and C)

MCP/CPU 1.05V AND CPU VCore High-Side Current Sense / Filter

Battery (BMON) Current Sense, MUX & Filter

PLACEMENT_NOTEs:

For production, stuff BMON_PROD

For engineering, stuff BMON_ENG

MCP VCore Current Sense Filter

(For R’s and C)

NOTE: Monitoring current from battery to PBUS (battery discharge) across R7008

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

DC-IN (AMON) Current Sense Filter

From charger

Battery side

Charger/Load side

(50V/V)

(For R and C)

PLACEMENT_NOTEs:

(For R and C)

PLACEMENT_NOTEs:

CPU VCore Load Side Current Sense / Filter

MCP MEM VDD Current Sense / Filter

40 41

0.22UF

X5R 402

20%

6.3V

Place close to SMC

C5472

1

2

0.1uF

CERM 402

20% 10V

C5417

1

2

SC70

INA213

U5402

2

5

4

6

1

3

40 41

0.22UF

X5R 402

20%

6.3V

Place close to SMC

C5436

1

2

40 60

4.53K

MF-LF

402

1%

1/16W

Place close to SMC

R5418

1 2

4.53K

MF-LF

402

1%

1/16W

Place close to SMC

R5416

1 2

0.1uF

CERM 402

20% 10V

BMON_ENG

C5418

1

2

INA213

SC70

PLACEMENT_NOTE=Place near sense resistor

BMON_ENG

U5403

2

5

4

6

1

3

60

402

0

MF-LF

5%

1/16W

PLACEMENT_NOTE=Place R5431 next to U5413

BMON_PROD

R5431

2 1

1/16W

5%

402

MF-LF

100K

BMON_ENG

R5423

1

2

10V

20% 402

CERM

0.1uF

BMON_ENG

C5459

1

2

Place close to SMC

4.53K

MF-LF

402

1%

1/16W

R5401

1 2

Place close to SMC

6.3V

20% 402

X5R

0.22UF

C5490

1

2

40

6.3V

20%

402

X5R

0.22UF

Place close to SMC

C5470

1

2

61

Place close to SMC

1/16W

1%

402

MF-LF

17.4K

R5480

1

2

Place close to SMC

6.19K

MF-LF

402

1%

1/16W

R5471

1 2

40

1/16W

1%

402

MF-LF

4.53K

Place close to SMC

R5481

1 2

0.22UF

X5R 402

20%

6.3V

Place close to SMC

C5487

1

2

SC70

NC7SB3157P6XG

BMON_ENG

U5413

43

1

2

6

5

40 41

60 82

64

118

MF-LF

402

1%

1/16W

R5412

1

2

SOD

2SA2154MFV-YAE

Q5401

1

3

2

68

0

MF-LF

402

5%

1/16W

R5410

1

2

16V

10%

402

X5R

0.1UF

C5434

1

2

402

0

MF-LF

5%

1/16W

R5411

2

1

CERM

402

20% 10V

0.1uF

C5400

1

2

Place close to SMC

4.53K

MF-LF

402

1%

1/16W

R5417

1 2

Place close to SMC

0.22UF

X5R

20%

6.3V 402

C5435

1

2

40 41

60 82

OPA348 SC70-5

U5400

3

1

4

2

5

0612-1

1W

0.5%

CRITICAL

MF

0.01

R5492

12

34

051-7903

83

A

Current Sensing

45

SYNC_MASTER=WFERRY_K19I

SYNC_DATE=12/16/2008

SMC_MCP_DDR_ISENSE

ISNS_CPUVTT_N

ISNS_CPUVTT_P

PPBUS_CPU_IMVP_ISNS

PPBUS_G3H

GND_SMC_AVSS

PP3V3_S0

BMON_AMUX_OUT

CHGR_BMON

PP3V42_G3H

SMC_CPU_FSB_ISENSE

SMC_BATT_ISENSE

SMC_BMON_MUX_SEL

CPUVTT_IOUT

BMON_INA_OUTCHGR_CSO_R_P

CHGR_CSO_R_N

GND_SMC_AVSS

SMC_CPU_ISENSE

GND_SMC_AVSS

SMC_MCP_CORE_ISENSE

MCPCORES0_IMON

IMVP6_IMON

SMC_DCIN_ISENSE

CHGR_AMON

PP3V3_S0

P1V5_S0_KELVIN

GND_SMC_AVSS

P1V5_S0_SENSE_B

P1V5_S0_SENSE_E

P1V5_S0_SENSE_AMP

P1V5_S0_SENSE_C

P1V5_S0_SENSE

82

7

61 65

6 7

35 44 59 60 62 63 64 73

40 41 44 45

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

6 7

20 21 24 38 40 41 42 43

48 59 60 67

40 41 44 45

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

40 41 44 45

BI

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

THRM_PAD

DN2/DP3

DP2/DN3

VDD

SMDATA

SMCLK

GND

DN1

DP1

THERM*/ADDR

ALERT*

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DETECT FIN-STACK TEMPERATURE

DETECT CPU DIE TEMPERATURE

PLACEMENT NOTE: PLACE U5515 NEAR CPU

CPU T-Diode Thermal Sensor

INTERNAL DIODE IN U5515 DETECTS CPU PROXIMITY TEMPERATURE

PLACEMENT NOTE: PLACE U5535 NEAR MCP

MCP T-Diode Thermal Sensor

DETECT MCP DIE TEMPERATURE

INTERNAL DIODE IN U5535 DETECTS MCP PROXIMITY TEMPERATURE

REPLACED 518S0521 WITH 518S0519

DETECT HEAT-PIPE TEMPERATURE

CERM

402

0.0022uF

10% 50V

NOSTUFF

SIGNAL_MODOL=EMPTY

C5540

1

2

40 43 81

402

10K

MF-LF

5% 1/16W

R5517

1

2

10K

MF-LF

1/16W

402

1%

R5516

1

2

402

1/16W

5%

MF-LF

10K

R5537

1

2

402

10K

1/16W MF-LF

1%

R5536

1

2

40 43 51 81

0.1uF

20%

402

CERM

10V

C5535

1

2

402

CERM

50V

10%

SIGNAL_MODOL=EMPTY

0.0022uF

C5521

1

2

SIGNAL_MODOL=EMPTY

CERM

10% 50V

0.0022uF

402

C5522

1

2

9

82

9

82

20 82

M-RT-SM

NOSTUFF

78171-0002

CRITICAL

J5590

3

4

1 2

SOT732-3

BC846BMXXH

Q5501

1

3

2

EMC1413

DFN

CRITICAL

U5515

83

5

2

4

6

10

9

7

11

1

CRITICAL

DFN

EMC1413

U5535

83

5

2

4

6

10

9

7

11

1

0.1uF

20%

402

CERM

10V

C5515

1

2

402

MF-LF

5%

1/16W

47

R5515

1 2

CERM

50V

10%

0.0022uF

402

SIGNAL_MODOL=EMPTY

C5520

1

2

47

1/16W

402

MF-LF

5%

R5535

1 2

051-7903

A

8346

Thermal Sensors

SYNC_MASTER=K24_MLB

SYNC_DATE=02/05/2009

MCPTHMSNS_D2_P

MCPTHMSNS_D2_N

MCP_THMDIODE_N

SMBUS_SMC_0_S0_SCL

SMBUS_SMC_0_S0_SDA

MCPTHMSNS_THERM_L

MCPTHMSNS_ALERT_L

MCP_THMDIODE_P

PP3V3_S0_MCPTHMSNS_R

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

PP3V3_S0

CPUTHMSNS_ALERT_L

CPUTHMSNS_D2_N

CPUTHMSNS_D2_P

MIN_LINE_WIDTH=0.25 mm VOLTAGE=3.3V

MIN_NECK_WIDTH=0.25 mm

PP3V3_S0_CPUTHMSNS_R

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

CPU_THERMD_N

CPU_THERMD_P

CPUTHMSNS_THERM_L

PP3V3_S0

82

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

82

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

D

GS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

518S0521

GND

MOTOR CONTROL

TACH

5V DC

47K

1/16W

5%

MF-LF

402

R5665

1 2

5%

402

MF-LF

1/16W

47K

R5660

1

2

5% 1/16W MF-LF

402

100K

R5661

1

2

SSM3K15FV

SOD-VESM-HF

Q5660

3

1

2

CRITICAL

78171-0004

M-RT-SM

J5601

5

6

1 2 3 4

051-7903

8347

A

Fan

SYNC_MASTER=K24_MLB

SYNC_DATE=02/05/2009

FAN_RT_PWM

PP5V_S0 PP3V3_S0

SMC_FAN_0_CTL

FAN_RT_TACH

SMC_FAN_0_TACH

6

6 7

37 42 49 61 64 65 67 68

70 72

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 49 53 57

58 61 66 67 68 69 71 72 82

40

6

40

D

G S

P2_4

P2_6

VDD

P0_4

P0_2

P2_0

P2_2

P0_0

P2_3 P2_1 P4_7 P4_5 P4_3 P4_1 P3_7 P3_5 P3_3 P3_1 P5_7 P5_5 P5_3 P5_1

P1_1

P1_3

P1_5

P1_7

P7_7

VSSD+D-

VDD

P7_0

P1_0

P1_2

P1_4

P1_6

P5_0

P5_2

P5_4

P5_6

P3_0

P3_2

P3_4

P4_0

P4_2

P4_4

P4_6

P3_6

P2_5

P2_7

P0_3

VSS

P0_5

P0_7

P0_6

PAD

THRML

(SYM-VER2)

P0_1

Y

C

B

A

IN

OUT

IN

Y

B

A

Y

B

A

Y

B

A

NC

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Alternate Parts

VDD PIN 22

TRACKPAD PICK BUTTONS KEYBOARD SCANNER

APN 311S0406

VDD

CLOSE TO U5701CLOSE TO U5701

PLACE C5701, C5702 & C5703

18V BOOSTER

PSOC

IC

PIN NAME

V+

VOUT

VIN

CURRENT

80UA

10UA

R_SNS

2.55 KOHM

10 OHM

1.5 OHM

V_SNS POWER

0.012 V

0.255E-6 W

294E-6 W

75.2E-6 W

USB INTERFACES TO MLB

TO MLB CONNECTOR

APN 518S0637

LID CLOSE => SMC_LID_LC < 0.50V

LID OPEN => SMC_LID_LC ~ 3.42V

WHEN THE LID IS CLOSED

THIS ASSUMES THERE’S A PP3V42_G3H PULL UP ON MLB

THE TPAD BUTTONS WILL BE DISABLE

U5701 CHIP DECOUPLING

PLACE THESE COMPONENTS CLOSE TO J5800

ISOLATION CIRCUIT

TPAD BUTTONS DISABLE

VDD PIN 49

PLACE C5704, C5705 & C5706

TMP102

SPI HOST TO Z2

0.204 V

0.6 V

0.0255 V

3V3 LDO

14MA (MAX)

60MA MAX

0.72E-3 W

36E-3 W

0.012 V

16.32E-6 W

96E-6 W

4MA (MAX)

4.7 OHM

0.0188 V

0.021 V

0.2 OHM

8MA (TYP)

VDD

60MA MAX

ISSP SDATA/I2C SDA

ISSP SCLK/I2C SCL

NC

SMC_MANUAL_RESET LOGIC

KEYBOARD CONNECTOR

APN 337S2983

PSOC USB CONTROLLER

SSM3K15FV

SOD-VESM-HF

Q5701

3

1

2

X7R-CERM

0.1UF

10%

402

16V

C5758

1

2

402

MF-LF

33K

5% 1/16W

R5771

1

2

33K

402

MF-LF

5%

1/16W

R5770

1

2

402

MF-LF

1/16W

5%

33K

R5769

1

2

4.7UF

20%

6.3V X5R 603

C5706

1

2

402

0.1UF

X7R-CERM

16V

10%

C5705

1

2

5%

100PF

50V CERM 402

C5704

1

2

0.1UF

10%

402

X7R-CERM

16V

C5703

1

2

402

CERM

50V

5%

100PF

C5702

1

2

20%

4.7UF

X5R 603

6.3V

C5701

1

2

24

402

5%

1/16W MF-LF

R5702

1 2

CRITICAL

MLF

CY8C24794

OMIT

U5701

20

21

45544653475248

51

25182617271628

15

41

2

42

1

435644

55

3310

34

9

35

8

36

7

37

6

38

5

39

4

40

3

2914

3013

3112

3211

24

235722 49

19

50

24

1/16W

5%

MF-LF

402

R5701

1 2

SC70

SN74LVC1G10

CRITICAL

U5703

2

1 3 6

4

5

MF-LF

5%

1.5

1/16W

402

R5704

1 2

40 41 59

402

10V

0.1UF

20%

PLACEMENT_NOTE=NEAR J5713

CERM

C5710

1

2

402

MF-LF

1/16W

5%

1K

R5710

1 2

1%

MF-LF

402

1/16W

470

R5714

1 2

1%

402

10K

MF-LF

1/16W

R5715

1 2

CRITICAL

FF14-30A-R11B-B-3H

F-RT-SM

J5713

31

32

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

4

5

6

7

8

9

CRITICAL

TC7SZ08AFEAPE

SOT665

U5726

2

1

3

5

4

CRITICAL

TC7SZ08AFEAPE

SOT665

U5727

2

1

3

5

4

402

CERM

10V

20%

0.1UF

C5727

12

402

0.1UF

20%

CERM

10V

C5726

12

CRITICAL

SOT665

TC7SZ08AFEAPE

U5725

2

1

3

5

4

402

10V

20%

CERM

0.1UF

C5725

12

48 83

051-7903

SYNC_MASTER=K24_MLB

SYNC_DATE=02/05/2009

A

WELLSPRING 1

311S0406 311S0447

ALL NXP PART AS ALTERNATE

WS_KBD13

WS_KBD12

WS_KBD8

WS_KBD23

Z2_RESET PSOC_MISO

WS_LEFT_OPTION_KEY

WS_LEFT_SHIFT_KEY

WS_LEFT_SHIFT_KBD

WS_LEFT_OPTION_KEY

USB_TPAD_R_N

DIFFERENTIAL_PAIR=USB2_TPAD

WS_KBD4

NC_P7_7

NC_ISSP_SDATA_P1_0

Z2_CLKIN

WS_KBD14

PP3V3_S3_PSOC

WS_KBD11

PICKB_L

PP3V3_S3

WS_KBD2 WS_KBD3 WS_KBD4

WS_LEFT_SHIFT_KEY

WS_CONTROL_KEY

PP3V42_G3H

PSOC_F_CS_L

WS_CONTROL_KBD

WS_KBD6

SMC_LID

BUTTON_DISABLE

WS_KBD17 WS_KBD16N

WS_KBD8

WS_KBD1 WS_KBD2

WS_KBD5 WS_KBD6

WS_KBD18

WS_KBD17

WS_KBD16_NUM

WS_KBD15_CAP

WS_KBD14

WS_KBD11

WS_KBD10

WS_KBD9

WS_KBD21

WS_KBD20

WS_KBD19

WS_KBD22

WS_LEFT_SHIFT_KBD

PP3V42_G3H

WS_LEFT_OPTION_KBD WS_CONTROL_KBD

WS_KBD7

Z2_SCLK

NC_PSOC_SDA

PP3V3_S3_PSOC

TP_PSOC_SCL

WS_KBD22

USB_TPAD_P

WS_KBD5

PP3V3_S3

WS_KBD15_C

WS_KBD12

WS_KBD10 WS_KBD9

WS_KBD3

NC_PSOC_P1_3

WS_KBD13

Z2_MOSI

WS_KBD23

WS_KBD21

WS_KBD19

WS_KBD7

WS_KBD16N

WS_KBD15_C

WS_KBD18

SMC_TPAD_RST_L

USB_TPAD_R_P

DIFFERENTIAL_PAIR=USB2_TPAD

PP3V42_G3H

WS_KBD20

WS_LEFT_OPTION_KBD

Z2_HOST_INTN

BUTTON_DISABLE

WS_KBD1

SMC_ONOFF_L

WS_KBD_ONOFF_L

WS_CONTROL_KEY

PP3V42_G3H

PP3V3_S3

WS_LEFT_OPTION_KBD

PP3V3_S3

USB_TPAD_N

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

PP3V3_S3_PSOC

NC_ISSP_SCLK_P1_1

Z2_DEBUG3

TP_P4_5

Z2_KEY_ACT_L

Z2_MISO

PSOC_SCLK

PSOC_MOSI

Z2_CS_L

WS_CONTROL_KBD

PP3V3_S3

WS_LEFT_SHIFT_KBD

6

48

6

48

6

48

6

48

6

49

6

49

48

6

48

6

48

6

49

6

48

6

48

6

49

6

48

6

48

6

48

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6

49

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6

48

6 7

20 21 24 38 40 41 42

43 45 48 59 60

67

6

48

6

48

6

48

6

49

6

48

6

48

19 78

6

48

6 7

20 25 29 30 43 48 50 68

48

6

48

6

48

6

48

6

48

6

48

6

49

6

48 6 48 6 48

6

48

6

48

41

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6

48

6

48

6

49

48

6

48

40 41

6

48

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

20 25 29 30 43 48 50 68

6

48

6 7

20 25 29 30 43 48 50 68

19 78

48

6

49

6

49

6

49

6

49

6

49

6

49

6

48

6 7

20 25 29 30 43 48 50 68

6

48

CTRL

PGND

THRML

L

VIN

DO

FB

SW

PAD

GND

VDD

VOUT

GND

CE

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

APN 516S0689

APN 518S0691

J5815 pin 1 is grounded

KBD BACKLIGHT CONNECTOR

on keyboard backlight flex

- POWER CONSUMPTION

- DROOP LINE REGULATION

TURNED ON FOR BEST MLB CONFIG

BOM OPTION: KBDLED_YES

HIGH= keyboard backlight not present

LOW = keyboard backlight present

tristate SMC_SYS_KBDLED:

R5853 ALWAYS PRESENT

To detect Keyboard backlight, SMC will

BOOSTER DESIGN CONSIDERATION:

- R5812,R5813,C5818 MODIFIED

- STARTUP TIME LESS THAN 2MS

- 100-300 KHZ CLEAN SPECTRUM

- RIPPLE TO MEET ERS

BOOSTER +18.5VDC FOR SENSORS

APN 371S0313

APN 152S0504

APN 353S1364

KEYBOARD BACKLIGHT DRIVNG AND DETECTION

APN 353S1401

IPD FLEX CONNECTOR

3V3 LDO FOR IPD

CRITICAL

55560-0228

M-ST-SM

J5800

1

10

1112 1314 1516 1718 19

2

20

2122

34 56 78 9

CRITICAL

SOD-323

B0520WSXG

D5802

603-1

10% 25V X5R

1UF

C5819

1

2

402

5%

0

MF-LF

1/16W

R5806

1 2

402

10%

X7R-CERM

16V

0.1UF

C5816

1

2

5%

1/16W

MF-LF

402

0

R5805

1 2

16V X5R 603

10%

2.2UF

C5817

1

2

QFN

TPS61045

CRITICAL

U5805

53

4

617

8

9

2

CRITICAL

VLF3010AT-SM-HF

3.3UH-870MA

L5801

100K

402

1/16W MF-LF

1%

R5811

1

2

603

2.2UF

10%

16V

X5R

C5853

1

2

MM3243DRRE

MLF

CRITICAL

VR5802

1

4

2

3

0.2

402-HF

MF

1/6W

1%

R5836

1

2

10%

16V

402

X7R-CERM

0.1UF

C5838

1

2

4.7UF

603

X5R

6.3V

20%

C5854

1

2

10

1/16W MF-LF

402

1%

R5873

1 2

40

KB_BL

402

4.7K

5% 1/16W MF-LF

R5854

1

2

402

470K

MF-LF

1/16W

5%

R5853

1

2

DFN

KB_BL

CRITICAL

LT3491

U5850

4

6

2

5

3

7

1

5%

MF-LF

402

10K

1/16W

NO STUFF

R5852

1

2

KB_BL

1UF

10% 10V X5R

402-1

C5850

1

2

KB_BL

10

1%

1/16W

MF-LF

402

R5855

1

2

KB_BL

CRITICAL

1098AS-SM

10UH-0.58A-0.35OHM

L5850

1 2

KB_BL

10% 35V

603

X5R

1UF

C5855

1

2

KB_BL

F-RT-SM

FF18-4A-R11AD-B-3H

CRITICAL

J5815

1 2 3 4

50V

5%

CERM 402

39PF

C5818

1

2

MF-LF

1/16W

1%

402

1M

R5812

1

2

71.5K

1/16W MF-LF

1%

402

R5813

1

2

PLACEMENT_NOTE=NEAR J5800

CERM 402

10V

20%

0.1UF

C5800

1

2

SYNC_DATE=02/25/2009

A

051-7903

49 83

SYNC_MASTER=K24_MLB

WELLSPRING 2

BOOST_FB

0.20MM

0.50MM

INPUT_SW

PP5V_S3

Z2_DEBUG3

Z2_MISO Z2_SCLK

Z2_HOST_INTN

Z2_CLKIN

0.20MM

PP18V5_S3

0.50MM

PP3V3_S3_LDO

0.50MM

0.20MM

SMBUS_SMC_A_S3_SDA

PICKB_L

Z2_KEY_ACT_L

Z2_MOSI

Z2_BOOST_EN

PSOC_MISO

Z2_CS_L

SMC_SYS_KBDLED

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.20MM

MIN_LINE_WIDTH=0.50MM

BOOST_SW

MIN_NECK_WIDTH=0.20MM

PP5V_S3_BOOSTER

MIN_LINE_WIDTH=0.50MM

PP18V5_S3_SW

MIN_LINE_WIDTH=0.50MM MIN_NECK_WIDTH=0.20MM

PP3V3_S3_LDO

KBDLED_SW

MIN_LINE_WIDTH=0.3 MM

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

KBDLED_ANODE

PP5V_S0

Z2_BOOST_EN

PSOC_F_CS_L

SMBUS_SMC_A_S3_SCL

PSOC_SCLK

PSOC_MOSI

PP18V5_S3

Z2_RESET

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

KBDLED_CAP

SMC_KDBLED_PRESENT_L

PP3V3_S3_LDO_R

PP3V3_S0

SMC_KDBLED_PRESENT_L

PP5V_S3

PP5V_S3_VR

0.50MM

0.20MM

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6

48

6

48

6

48

6

48

6

48

6

49

6

49

6

29 40 43 81

6

48

6

48

6

48

6

49

6

48

6

48

6

49

6

6 7

37 42 47 61 64 65 67 68

70 72

6

49

6

48

6

29 40 43 81

6

48

6

48

6

49

6

48

6

49

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 53 57

58 61 66 67 68 69 71 72 82

6

49

6 7 8

29 37 38 39 41 49 51 53

62 63 68

OUT

FS PD ST

RES RES

GND

NC

NC NC

NC

NC NC

VOUTX

VOUTY

VOUTZ

VDD

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

R5921 PULLS UP SMS_PWRDN TO TURN OFF SMS WHEN PIN IS NOT BEING DRIVEN BY SMC

Analog SMS

NC NC NC

NC

in correct orientation

placed on board top-side:

+Z (up)

Circle indicates pin 1 location when placed

Desired orientation when

Front of system

+X

+Y

NC

40

16V

10%

402

CERM

0.01UF

C5925

1

2

16V

10%

402

CERM

0.01UF

C5924

1

2

16V

10%

402

CERM

0.01UF

C5923

1

2

1/16W

5%

402

MF-LF

10K

R5921

1

2

LGA

AP344ALH

CRITICAL

U5920

1

7

3 6 9

11 13 16

5

15

4

2

14

12

10

8

1/16W

5%

402

MF-LF

10K

R5922

1

2

40 50

4V

20%

603

X5R

10UF

C5926

1

2

16V

10%

402

X5R

0.1UF

C5922

1

2

40

SYNC_DATE=02/05/2009

Sudden Motion Sensor (SMS)

051-7903

A

8350

SYNC_MASTER=K19_MLB

SMS_Z_AXIS

SMS_Y_AXIS

SMS_X_AXIS

MAKE_BASE=TRUE

SMS_PWRDN

SMS_SELFTEST

SMS_PWRDN

PP3V3_S3

40 50

6 7

20 25 29 30 43 48 68

COM

GND

THRM

DVDDAVDD

AD0 AD1

SDA SCL

CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7

VREF

REFCOMP

PAD

BI

IN

V+

REFIN+

IN-

OUT

GND

IN

THRM

V-

V+

IN

THRM

V-

V+

IN

THRM

V-

V+

THRM

V-

V+

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

GAIN: 273X

GAIN: 200X

LSB: 0.001V

ADC RANGE: 0V TO 4.096V

I2C ADDRESS: 0X10 / 0X11

GAIN: 1239X

GAIN: 561X

DIVIDER: ~ 2/5

DIVIDER: ~ 1/22

GAIN: 845X

DIVIDER: ~ 2/5

QFN

LTC2309

DEBUG_ADC

U6000

14 15

12

13

22 23 24

1 2 3 4 5

6

21

9

1011181920

8

16

17

25

7

40 43 46 81

DEBUG_ADC

402

1% 1/16W MF-LF

412

R6060

1 2

2.2UF

X5R

DEBUG_ADC

6.3V

10% 402

PLACEMENT_NOTE=PLACE RC NEAR U6000

C6074

1

2

226K

1/16W

DEBUG_ADC

402

MF-LF

1%

R6074

1 2

40 43 46 81

72 82

402

10V

20%

0.1UF

DEBUG_ADC

CERM

C6050

1

2

2.2UF

X5R

DEBUG_ADC

6.3V 402

10%

PLACEMENT_NOTE=PLACE RC NEAR U6000

C6082

1

2

DEBUG_ADC

226K

MF-LF

1/16W

402

1%

R6082

1 2

PLACEMENT_NOTE=PLACE NEAR D9701

SM

XW6080

1 2

DEBUG_ADC

10UF

X5R 603

20%

6.3V

C6005

1

2

402

MF-LF

1/16W

DEBUG_ADC

1M

1%

R6080

1

2

47.0K

DEBUG_ADC

1/16W MF-LF

1%

402

R6081

1

2

DEBUG_ADC

SC70

INA210

U6050

2

5

4

6

1

3

PLACEMENT_NOTE=PLACE CLOSE TO U4900

402

DEBUG_ADC

0

MF-LF

5%

1/16W

R6001

1 2

0

402

DEBUG_ADC

MF-LF

5%

1/16W

PLACEMENT_NOTE=PLACE CLOSE TO U4900

R6002

1 2

DEBUG_ADC

20%

6.3V X5R 603

10UF

C6003

1

2

DEBUG_ADC

10UF

X5R 603

20%

6.3V

C6001

1

2

SM

PLACEMENT_NOTE=PLACE NEAR Q3450

XW6010

1 2

PLACEMENT_NOTE=PLACE NEAR Q4590

SM

XW6020

1 2

1%

402

MF-LF

1/16W

1M

DEBUG_ADC

R6010

1

2

681K

MF-LF

1/16W

1%

402

DEBUG_ADC

R6011

1

2

226K

402

1% 1/16W MF-LF

DEBUG_ADC

R6012

1 2

2.2UF

X5R 402

10%

6.3V

DEBUG_ADC

PLACEMENT_NOTE=PLACE RC NEAR U6000

C6012

1

2

2.2UF

X5R

10%

402

DEBUG_ADC

PLACEMENT_NOTE=PLACE RC NEAR U6000

6.3V

C6022

1

2

226K

1/16W

1%

MF-LF

402

DEBUG_ADC

R6022

1 2

DEBUG_ADC

1M

MF-LF 402

1/16W

1%

R6020

1

2

681K

MF-LF 402

1% 1/16W

DEBUG_ADC

R6021

1

2

DEBUG_ADC

0.1UF

CERM 402

20% 10V

C6002

1

2

29 82

50V

10%

CERM

402

470PF

DEBUG_ADC

C6032

1

2

MF-LF 402

1% 1/16W

DEBUG_ADC

301K

R6032

1

2

470PF

CERM

10% 50V

402

DEBUG_ADC

C6033

1 2

243

1/16W

402

MF-LF

1%

DEBUG_ADC

R6031

1 2

243

402

1%

MF-LF

1/16W

DEBUG_ADC

R6030

1 2

1%

1/16W

402

MF-LF

DEBUG_ADC

301K

R6033

1 2

DFN

OPA2330

DEBUG_ADC

U6030

3

2

1

9

4

8

20% CERM

402

10V

DEBUG_ADC

0.1UF

C6030

1

2

29 82

PLACEMENT_NOTE=PLACE RC NEAR U6000

10% 402

DEBUG_ADC

2.2UF

X5R

6.3V

C6034

1

2

DEBUG_ADC

MF-LF

1%

402

1/16W

226K

R6034

1 2

DEBUG_ADC

0.1UF

CERM 402

20% 10V

C6004

1

2

PLACEMENT_NOTE=PLACE RC NEAR U6000

DEBUG_ADC

2.2UF

X5R

6.3V

10%

402

C6044

1

2

DEBUG_ADC

226K

MF-LF

1/16W

402

1%

R6044

1 2

DFN

OPA2330

U6030

5

6

7

9

4

8

DEBUG_ADC

1%

1M

1/16W MF-LF

402

R6043

1 2

402

50V

470PF

CERM

10%

DEBUG_ADC

C6043

1 2

DEBUG_ADC

1M

1% 1/16W MF-LF 402

R6042

1

2

DEBUG_ADC

10%

470PF

50V

CERM

402

C6042

1

2

DEBUG_ADC

1%

3.65K

1/16W MF-LF

402

R6040

1 2

DEBUG_ADC

3.65K

1/16W

1%

MF-LF

402

R6041

1 2

63 82

2.2UF

X5R

10%

PLACEMENT_NOTE=PLACE RC NEAR U6000

DEBUG_ADC

6.3V 402

C6054

1

2

2.2UF

X5R

DEBUG_ADC

402

10%

6.3V

PLACEMENT_NOTE=PLACE RC NEAR U6000

C6064

1

2

DEBUG_ADC

0.1UF

CERM 402

20% 10V

C6000

1

2

226K

DEBUG_ADC

1/16W

1%

402

MF-LF

R6054

1 2

DEBUG_ADC

0.1UF

CERM 402

10V

20%

C6040

1

2

226K

DEBUG_ADC

402

1% 1/16W MF-LF

R6064

1 2

280K

1/16W MF-LF

402

1%

DEBUG_ADC

R6053

1 2

DEBUG_ADC

470PF

10%

402

CERM

50V

C6053

1 2

280K

DEBUG_ADC

MF-LF 402

1% 1/16W

R6052

1

2

DEBUG_ADC

470PF

CERM

10% 50V

402

C6052

1

2

DEBUG_ADC

MF-LF

402

1%

1/16W

348K

R6063

1 2

50V 402

10%

CERM

470PF

DEBUG_ADC

C6063

1 2

DEBUG_ADC

MF-LF 402

1% 1/16W

348K

R6062

1

2

10% 50V

DEBUG_ADC

470PF

CERM

402

C6062

1

2

2.2UF

DEBUG_ADC

20%

6.3V CERM 402-LF

C6006

1

2

37 82

OPA2330

DFN

DEBUG_ADC

U6040

3

2

1

9

4

8

DFN

OPA2330

U6040

5

6

7

9

4

8

499

402

MF-LF

1/16W

1%

DEBUG_ADC

R6051

1 2

499

402

MF-LF

1/16W

1%

DEBUG_ADC

R6050

1 2

DEBUG_ADC

402

1/16W MF-LF

1%

412

R6061

1 2

051-7903

A

8351

SYNC_DATE=03/25/2009

SYNC_MASTER=K19_MLB

DEBUG SENSORS AND ADC

ISNS_HDD_IOUT

ISNS_HDD_N

ISNS_LCDBKLT_P

ISNS_LCDBKLT_N

ISNS_AIRPORT_P

ADC_CH6

PP5V_WLAN_F_DIV

ADC_CH0

PP5V_SW_ODD_DIV

ADC_CH1

ADC_CH3

PPVOUT_S0_LCDBKLT_XW

ADC_CH5

ISNS_ODD_R_N

PPVOUT_S0_LCDBKLT

ISNS_AIRPORT_N

ADC_CH3

PP5V_SW_ODD_XW

PP5V_SW_ODD

ISNS_ODD_N

ISNS_ODD_P

ISNS_ODD_R_P

ADC_CH4

PP5V_WLAN_F_XW

ADC_CH5

ADC_CH4

ADC_CH0

ADC_REFCOMP

PP5V_S3PP5V_S3

PP5V_WLAN_F

ADC_CH6 ADC_CH7

ADC_CH2

ADC_VREF

ISNS_ODD_IOUT

ADC_SDA ADC_SCL

ADC_CH2

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

ISNS_AIRPORT_IOUT

ADC_CH7

ISNS_HDD_R_N

ISNS_HDD_R_P

ISNS_HDD_P

ISNS_AIRPORT_R_N

PPVOUT_S0_LCDBKLT_DIV

ISNS_LCDBKLT_IOUT

ISNS_AIRPORT_R_P

ISNS_1V5_S3_IOUT

PP5V_S3

ISNS_1V5_S3_R_P

ISNS_1V5_S3_P

ISNS_1V5_S3_R_N

ISNS_1V5_S3_N

PP5V_S3

51

51 51

51

82

6

69 72 74

51

6

37

82

51

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7 8

29 37 38 39 41 49 51 53

62 63 68

29

51

82

6 7 8

29 37 38 39 41 49 51 53

62 63 68

82

6 7 8

29 37 38 39 41 49 51 53

62 63 68

IN

OUT

ININ

GND

VCC

WP*/ACC

CE*

SI/SIO0

HOLD*

SCLK

SO/SIO1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

42 MHz

1 MHz

25 MHz

31 MHz

1

0

1

0

1

0

1

0

MCP79 SPI Frequency Select

Frequency

SPI_MOSI

SPI_CLK

42

NO STUFF

10K

MF-LF 402

5% 1/16W

R6191

1

2

PLACEMENT_NOTE=PLACE CLOSE TO U6100

0

MF-LF

402

5%

1/16W

R6105

1 2

42

1/16W

5%

402

MF-LF

0

PLACEMENT_NOTE=PLACE CLOSE TO U6100

R6152

1 2

42 42

PLACEMENT_NOTE=PLACE CLOSE TO U6100

0

MF-LF

402

5%

1/16W

R6150

1 2

NO STUFF

10K

MF-LF

402

5%

1/16W

R6190

1

2

OMIT

CRITICAL

32MBIT

MX25L3205DM2I-12G

SOP

U6100

1

4

7

6

5

2

8

3

3.3K

MF-LF

402

5%

1/16W

R6100

1

2

3.3K

MF-LF 402

5% 1/16W

R6101

1

2

0.1UF

CERM

402

20% 10V

C6100

1

2

52 83

A

051-7903

SPI ROM

SYNC_MASTER=K19_MLB

SYNC_DATE=02/05/2009

SPI_MOSI_MUX

SPI_MOSI

SPI_MISO_R

PP3V3_S5

SPI_HOLD_L

SPI_WP_L

SPI_MLB_CS_L

SPI_CLK

SPI_CLK_MUX

SPI_MISO_MUX

25MHz is selected with R5190 and R5191

with R6190, R6191, R5190 and R5191

Any of the 4 frequencies can be selected

78

6 7

17 19 21 22 24 28 32 35

36 42 62 66 67 68 69 71 82

78

IN

OUT

IN

OUT

OUT OUT

OUT

IN

IN IN IN IN

VL_HD

SENSE_A

GPIO1/DMIC_SDA2

GPIO0/DMIC_SDA1

VHP_FILT+

GPIO2

RESET*

LINEOUT_L1-

VBIAS_DAC

FLYP

VA_REF

VD

GPIO3

VHP_FILT-

LINEOUT_R1-

LINEOUT_R1+

LINEOUT_R2-

SPDIF_OUT

LINEIN_C-

FLYC FLYN

SPDIF_IN

LINEOUT_L1+

THRM_PAD

VA_HP

HPOUT_R

HPREF

VCOM

AGND

VA

LINEIN_R+

LINEIN_L+

MICIN_L+ MICIN_L-

MICBIAS

SYNC

DGND

DMIC_SCL

HPOUT_L

SDI SDO

VL_IF

BITCLK

MICIN_R-

MICIN_R+

VREF+_ADC

LINEOUT_L2+ LINEOUT_L2LINEOUT_R2+

/SPDIF_OUT2

IN

OUT

IN

OUT

IN

OUT

OUT OUT

BP

NC

SHDN*

IN OUT

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

NC NC

AUDIO CODEC

DIFF FSINPUT= 2.45VRMS SE FSINPUT= 1.22VRMS

NC

NOTES ON CODEC I/O

DAC2/3 FSOUTPUTSE= 1.34VRMS

DAC1 FSOUTPUT= 1.34VRMS DAC2/3 FSOUTPUTDIFF= 2.67VRMS

APPLE P/N 353S2355

APPLE P/N 353S2234

4.5V POWER SUPPLY FOR CODEC

CRITICAL

6.3V 603-1

X5R

10UF

20%

C6221

1

2

SM

XW6201

1 2

CRITICAL

6.3V

20% CERM

2.2UF

402-LF

C6222

1

2

CRITICAL

2.2UF

20%

CERM

402-LF

6.3V

C6223

1

2

6.3V

20%

603-1

X5R

CRITICAL

10UF

C6220

1

2

TANT

1UF

0603-SM

16V

20%

CRITICAL

C6224

1

2

X5R

4.7UF

4V

20% 402

CRITICAL

C6210

1

2

20 78

58

56

55

56

58

54

58

CRITICAL

10UF

6.3V X5R 603

20%

C6213

1

2

CRITICAL

CS4206ACNZC

QFN

U6201

26

6

7

4

43 42

45

2 12 14 15

38 40

39

22

21

23

34

35

30

31

37

36

33

32

16

17

18

20

19

11

8

5

13

47 48

10

49

25

46

24

29

28

9

41

44

3

1

27

54

FERR-220-OHM

0402

CRITICAL

L6200

1 2

1/16W

1%

402

MF-LF

2.21K

R6200

1 2

0.1UF

X5R

16V

10% 402

C6215

1

2

10% 16V X5R

0.1UF

402

C6211

1

2

X5R

16V

10% 402

0.1UF

C6214

1

2

MF-LF 402

2.67K

1/16W

1%

R6210

1

2

1/16W

5%

100K

MF-LF 402

R6213

1

2

402

1/16W

5%

MF-LF

39

R6211

1 2

0.1UF

10% 16V

402

X5R

C6218

1

2

CRITICAL

10UF

TANT-POLY

20% 16V

2012-LLP

C6217

1

2

CRITICAL

10UF

2012-LLP

16V

20%

TANT-POLY

C6219

1

2

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49

53 57 58 61 66 67 68 69 71

72 82

57

6

53

6 7

17 23 66

6

53

57

6

53

57

402-1

CRITICAL

X5R

10V

10%

1UF

C6216

1

2

402

X7R-CERM

10%

0.1UF

16V

C6202

1 2

56

SM

XW6200

1 2

NOSTUFF

1/16W

5%

402

MF-LF

0

R6201

1 2

CRITICAL

FERR-220-OHM

0402

L6201

1 2

1/16W

5%

402

MF-LF

39

R6212

1 2

CRITICAL

UDFN

MAX8840-4.5V

U6200

4

2

1

5

6

3

10K

K19

1/16W MF-LF 402

5%

R6218

1

2

K19I

MF-LF

1/16W

5%

10K

402

R6219

1

2

10%

1UF

X5R

10V 402-1

C6200

1

2

10%

1UF

X5R 402-1

CRITICAL

10V

C6201

1

2

402-1

CRITICAL

10V X5R

10%

1UF

C6203

1

2

20% POLY-TANT

16V CASE-B2-SM

CRITICAL

10UF

C6225

1

2

53 83

A

051-7903

AUDIO: CODEC/REGULATOR

TP_AUD_GPIO_2

AUD_SENSE_A

AUD_GPIO_3

AUD_MIC_INN_L

TP_AUD_DMIC_CLK

AUD_MIC_INP_L

AUD_LI_REF

AUD_CODEC_MICBIAS

HDA_BIT_CLK

CS4206_VCOM

MIN_LINE_WIDTH=0.5MM VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

GND_AUDIO_CODEC

AUD_SPDIF_OUT_CHIP

HDA_SYNC

AUD_MIC_INN_R

AUD_LI_P_R

PP3V3_S0

AUD_LI_P_L

TP_AUD_GPIO_0

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM VOLTAGE=4.5V

PP4V5_AUDIO_ANALOG

AUD_SPDIF_OUT

HDA_RST_L

HDA_SDOUT

VOLTAGE=1.8V

PP1V8_S0_AUDIO_DIG

MIN_LINE_WIDTH=0.10MM MIN_NECK_WIDTH=0.10MM

AUD_GPIO_1

VOLTAGE=4.5V MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

PP4V5_AUDIO_ANALOG

PP5V_S3

GND_AUDIO_HP_AMP

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_R

PP1V8_S0

AUD_LO2_P_R

AUD_LO1_N_R

AUD_LO2_N_L

PP3V3_S0

MIN_NECK_WIDTH=0.20MM

AUD_HP_PORT_L

MIN_LINE_WIDTH=0.30MM

AUD_LO2_N_R

GND_AUDIO_HP_AMP

VOLTAGE=0V

MIN_NECK_WIDTH=0.10MM

MIN_LINE_WIDTH=0.15MM

AUD_MIC_INP_R

AUD_LO2_P_L

VBIAS_DAC

HDA_SDIN0

NC_AUD_LO1_P_L

CS4206_VREF_ADC

AUD_SPDIF_IN

CS4206_FN

PP3V3_S0

PP4V5_AUDIO_ANALOG

AUD_SDI_R

NC_AUD_LO1_N_L

AUD_HP_PORT_REF

MIN_LINE_WIDTH=0.30MM MIN_NECK_WIDTH=0.20MM

AUD_LO1_P_R

GND_AUDIO_HP_AMP

CS4206_FLYN

CS4206_FLYC

CS4206_FLYP

CS4206_FP

4V5_NR

PP5V_S3

4V5_REG_EN

VOLTAGE=5V

MIN_LINE_WIDTH=0.15MM MIN_NECK_WIDTH=0.10MM

4V5_REG_IN

VOLTAGE=0V

GND_AUDIO_CODEC

53 54 58

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

6 7 8

29 37 38 39 41 49 51 53

62 63 68

53 55 57

53 54 58

53 55 57

6

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69

71 72 82

6

53 55 57

53 54 58

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FC = 8 HZ

NET RIN = 20K OHMS VIN = 2VRMS, CODEC VIN = 1.21 VRMS

CODEC RIN = 20K OHMS

LINE INPUT VOLTAGE DIVIDER

57

53

CRITICAL

3.3UF

CERM-X5R

805-1

10% 10V

C6301

1 2

CRITICAL

3.3UF

10% 10V

CERM-X5R

805-1

C6302

1 2

3.3UF

CRITICAL

CERM-X5R

805-1

10% 10V

C6311

1 2

CRITICAL

3.3UF

CERM-X5R

805-1

10% 10V

C6312

1 2

CRITICAL NOSTUFF

15PF

CERM 402

5% 50V

C6303

1

2

CRITICAL NOSTUFF

15PF

CERM 402

5% 50V

C6313

1

2

53 58

402

MF-LF

1%

6.04K

1/16W

R6301

1 2

MF-LF

6.04K

402

1/16W

1%

R6311

1 2

16.5K

402

MF-LF

1/16W

1%

R6312

1

2

16.5K

402

MF-LF

1/16W

1%

R6302

1

2

1/16W MF-LF

1%

10

402

R6300

1

2

AUDIO: LINE INPUT FILTER

A

8354

051-7903

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_L

GND_AUDIO_CODEC

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_R

AUD_LI_L_DIV

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

MIN_NECK_WIDTH=.1MM

MIN_LINE_WIDTH=.1MM

AUD_LI_P_R

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_GND

AUD_LI_REF

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_P_L

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

AUD_LI_R_DIV

MIN_LINE_WIDTH=.1MM MIN_NECK_WIDTH=.1MM

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ZOBEL NETWORK & 1ST ORDER DAC FILTER PLACEHOLDER

NC

57

2.21K

MF-LF 402

1% 1/16W

R6502

1

2

2.21K

MF-LF 402

1% 1/16W

R6512

1

2

0.1UF

CRITICAL

X7R-CERM

402

10% 16V

C6500

1

2

402

39

MF-LF

5%

1/16W

R6500

1

2

CRITICAL

16V

10%

402

X7R-CERM

0.1UF

C6510

1

2

39

MF-LF

402

5%

1/16W

R6510

1

2

NO STUFF CRITICAL

0.0022UF

CERM

402

10% 50V

C6501

1

2

NO STUFF CRITICAL

0.0022UF

CERM

402

10% 50V

C6511

1

2

57

0

MF-LF

603

5%

1/10W

R6501

1 2

0

MF-LF

603

5%

1/10W

R6511

1 2

53

53 57

53

AUDIO: HEADPHONE FILTER

SYNC_MASTER=K19_MLB

SYNC_DATE=02/05/2009

8355

051-7903

A

AUD_HP_L

AUD_HP_PORT_L

AUD_HP_R

AUD_HP_ZOBEL_L

AUD_HP_ZOBEL_R

AUD_HP_PORT_R

GND_AUDIO_HP_AMP

IN

OUT

IN

OUT

IN

OUT

IN

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

SD*

OUT+

PVDD

GND

VDD

IN+

IN-

OUT_

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SPEAKER CHECKPOINTS

1ST ORDER FC (SUB) = 58HZ +/- 30%

PLACE C6630 CLOSE TO VDD PIN

1ST ORDER FC (L&R) = 120 HZ +/- 30%

3X MONO SPEAKER AMPLIFIERS (SSM2315)

PLACE C6610 CLOSE TO VDD PIN

APN: 353S2500

GAIN = 6DB

PLACE C6620 CLOSE TO VDD PIN

100K

1/16W

402

MF-LF

5%

R6601

1

2

CRITICAL

0.033UF

X5R 402

10% 16V

C6610

1 2

CRITICAL

0402

FERR-1000-OHM

L6601

1 2

53

CRITICAL

FERR-1000-OHM

0402

L6610

1 2

6

57 82

6

57 82

6

57 82

CRITICAL

0.033UF

402

X5R

16V

10%

C6611

1 2

X5R

0.1UF

402

16V

10%

CRITICAL

C6613

1

2

20%

6.3V

CASE-A4

TANT-POLY

CRITICAL

47UF

C6622

1

2

CRITICAL

10% 16V

402

X5R

0.1UF

C6623

1

2

402

0.033UF

X5R

10% 16V

CRITICAL

C6620

1 2

CRITICAL

FERR-1000-OHM

0402

L6620

1 2

53

0

402

5% 1/16W MF-LF

R6620

12

1/16W

0

MF-LF

402

5%

R6621

12

1/16W MF-LF

5%

402

0

R6611

12

6

57 82

1/16W

5%

402

MF-LF

0

R6610

12

20%

47UF

CASE-A4

TANT-POLY

CRITICAL

6.3V

C6612

1

2

TANT

CASE-AL1

20%

6.3V

100UF

CRITICAL

C6632

1

2

CRITICAL

0.068UF

CERM

402

10% 10V

C6630

1 2

CRITICAL

FERR-1000-OHM

0402

L6630

1 2

53

6

57 82

6

57 82

MF-LF

0

402

5% 1/16W

R6630

12

0

MF-LF

402

5% 1/16W

R6631

12

CRITICAL

FERR-1000-OHM

0402

L6611

1 2

53

0.033UF

X5R

10% 16V

402

CRITICAL

C6621

1 2

CRITICAL

0402

FERR-1000-OHM

L6621

1 2

53

0.068UF

CERM

402

10% 10V

CRITICAL

C6631

1 2

CRITICAL

FERR-1000-OHM

0402

L6631

1 2

53

CRITICAL

0.1UF

X5R 402

10% 16V

C6633

1

2

WLCSP

CRITICAL

SSM2315

U6610

A2

B3

C1 A1

A3

C3

B2

C2

B1

CRITICAL

SSM2315

WLCSP

U6620

A2

B3

C1 A1

A3

C3

B2

C2

B1

SSM2315

WLCSP

CRITICAL

U6630

A2

B3

C1 A1

A3

C3

B2

C2

B1

SYNC_DATE=02/05/2009

AUDIO:SPEAKER AMP

56 83

SYNC_MASTER=K19_MLB

A

051-7903

PP5V_S3_AUDIO_AMP

SSM2315L_N

SSM2315L_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_L_OUT_P

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L_OUT_N

SPKRAMP_L_OUT_P

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRCONN_S_OUT_P

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_S_OUT_P

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_L_OUT_P

SSM2315S_P

AUD_SPKRAMP_INP_SUB

SSM2315R_P

AUD_SPKRAMP_INP_R

SPKRAMP_R_OUT_P SPKRAMP_R_OUT_N

SSM2315R_N

PP5V_S3_AUDIO_AMP

SPKRAMP_S_OUT_P SPKRAMP_S_OUT_N

AUD_SPKRAMP_SHUTDOWN_L

SSM2315S_N

AUD_LO2_N_R

AUD_SPKRAMP_INN_SUB

AUD_LO2_P_R

AUD_LO2_P_L

AUD_SPKRAMP_INP_L

AUD_GPIO_3

AUD_LO1_N_R

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRAMP_R_OUT_N

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRCONN_R_OUT_P

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRCONN_S_OUT_N

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_S_OUT_N

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_R_OUT_N

AUD_LO1_P_R

AUD_LO2_N_L

MIN_LINE_WIDTH=0.30 mm MIN_NECK_WIDTH=0.20 MM

SPKRAMP_R_OUT_P

PP5V_S3_AUDIO_AMP

SPKRAMP_L_OUT_N

MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.30 mm

SPKRCONN_L_OUT_N

AUD_SPKRAMP_SHUTDOWN_L

AUD_SPKRAMP_INN_R

AUD_SPKRAMP_SHUTDOWN_L

AUD_SPKRAMP_INN_L

8

56

56 82

8

56

56 82

56

56 82

8

56

56 82

56

IN IN

OUT

OUT OUT OUT

IN

PINS

SHELL

SHIELD

POF

A - VDD B - GND

C - VOUT

OPERATING VOLTAGE 3.3

AUDIO

SWITCH

LEFT

RIGHT

GROUND

DETECT FOR PLUG TYPE

OUT

RIGHT

MIC

AUDIO

GND

LEFT

SWITCH

DETECT

B - VCC

POF

SHIELD

SHELL

PINS

C - GND

A - VIN

OPERATING VOLTAGE 3.3

BI

OUT

BI

OUT

IN

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AUDIO JACK 1 LO/HP JACK, SPDIF TX

APN: 514-0671

SPEAKER CONNECTOR

MIC CONNECTOR

GND PATCH

APN: 518S0519

APN: 518S0521

AUDIO JACK 2 LINE IN JACK, SPDIF RX

APN: 514-0635

APN: 518S0520

6

56 82

6

56 82

6

56 82

6

56 82

1/16W

5%

MF-LF

4.7

402

R6749

1 2

10% X5R

1UF

10V 402-1

C6750

1

2

FERR-220-OHM

0402

CRITICAL

L6751

1 2

CRITICAL

6.8V-100PF

402

DZ6701

1

2

402

6.8V-100PF

CRITICAL

DZ6751

1

2

402

6.8V-100PF

CRITICAL

DZ6758

1

2

0402

FERR-220-OHM

CRITICAL

L6758

1 2

402

CRITICAL

6.8V-100PF

DZ6700

1

2

402

6.8V-100PF

CRITICAL

DZ6706

1

2

402

6.8V-100PF

CRITICAL

DZ6704

1

2

402

6.8V-100PF

CRITICAL

DZ6754

1

2

53 55

0402

FERR-1000-OHM

CRITICAL

L6702

1 2

0402

CRITICAL

FERR-1000-OHM

L6703

1 2

402

6.8V-100PF

CRITICAL

DZ6703

1

2

6

58

6

58

6

58

FERR-1000-OHM

0402

CRITICAL

L6705

1 2

0402

FERR-1000-OHM

CRITICAL

L6752

1 2

10% 402

X5R

0.1UF

16V

C6700

1

2

M-RT-SM

78171-0004

CRITICAL

J6782

5

6

1 2 3 4

M-RT-SM

78171-0003

CRITICAL

J6780

4

5

1 2 3

M-RT-SM

78171-0002

CRITICAL

J6781

3

4

1 2

6

56 82

6

56 82

6.3V

20%

2.2UF

402-LF

CERM

C6701

1

2

1/16W

5%

402

MF-LF

0

R6701

1 2

FERR-1000-OHM

0402

CRITICAL

L6754

1 2

F-RT-TH5

AUDIO-RCVR-M97

J6750

5

7

4

10 11 12

9

1 3

2

6

8

50V

5%

402

CERM

33PF

CRITICAL

NOSTUFF

C6782

1

2

50V

5%

402

CERM

33PF

CRITICAL

NOSTUFF

C6781

1

2

50V

5% 402

CERM

33PF

CRITICAL

NOSTUFF

C6784

1

2

50V

5%

402

CERM

33PF

CRITICAL

NOSTUFF

C6783

1

2

58

0402

FERR-1000-OHM

CRITICAL

L6756

1 2

58

F-RT-TH

SPDIF-TXRX-K24

J6700

5

4

10 11 12 13

7 8 9

1

6

3

2

53

402

6.8V-100PF

CRITICAL

DZ6756

1

2

SM

XW6702

1 2

SM

XW6701

1 2

FERR-220-OHM

0402

CRITICAL

L6707

1 2

50V

5%

402

CERM

100PF

C6756

1

2

53

54

58

53

55

0603

FERR-220-OHM-2.5A

CRITICAL

L6701

1 2

FERR-220-OHM

0402

CRITICAL

L6704

1 2

CRITICAL

FERR-220-OHM

0402

L6706

1 2

58

1/16W

402

MF-LF

10K

5%

R6700

1 2

CERM

50V

5%

402

100PF

C6705

1

2

A

AUDIO: JACKS

051-7903

SYNC_MASTER=CASEYHARDY_K19

8357

SYNC_DATE=03/20/2009

AUD_HP_PORT_REF

GND_AUDIO_HP_AMP

AUD_HP_R

AUD_CONNJ1_SLEEVEDET

AUD_CONNJ1_SLEEVE

AUD_CONNJ1_RING

HS_MIC_LO

AUD_SPDIF_OUT

AUD_HP_L

AUD_CONNJ1_TIP

AUD_CONNJ1_TIPDET

AUD_J1_SLEEVEDET_R

HS_MIC_HI

AUD_CONNJ1_SLEEVE2

PP3V3_S0

GND_CHASSIS_AUDIO_JACK

MIN_NECK_WIDTH=0.10 MM VOLTAGE=0V

MIN_LINE_WIDTH=0.30 mm

GND_CHASSIS_AUDIO_JACK

BI_MIC_HI

AUD_J2_TIPDET_R

SPKRCONN_S_OUT_P

SPKRCONN_R_OUT_P SPKRCONN_R_OUT_N

SPKRCONN_S_OUT_N

AUD_LI_L

AUD_LI_R

AUD_LI_GND

PP3V3_S0

SPKRCONN_L_OUT_N

SPKRCONN_L_OUT_P

AUD_J1_TIPDET_R

BI_MIC_SHIELD

BI_MIC_LO

GND_CHASSIS_AUDIO_JACK

AUD_SPDIF_IN

AUD_CONNJ2_SLEEVE

AUD_CONNJ2_SLEEVEDET

AUD_CONNJ2_TIPDET

AUD_CONNJ2_RING

AUD_CONNJ2_TIP

AUD_J2_OPT_OUT

6 7

12 17 18 20

21 22 23 26 27 35 37 41

43 45 46 47 49

53 57 58 61 66 67 68 69

71 72 82

8

57

8

57

54

6 7

12 17 18

20 21 22 23 26

27 35 37 41

43 45 46 47 49

53 57 58 61

66 67 68 69 71

72 82

8

57

IN

OUT

IN

D

SG

D

SG

D

SG

D

SG

D

G S

OUT

IN

OUT

IN

OUT

IN

BI

IN

OUT

VDD

GND

MR*

RST*

D

SG

D

SG

IN

GND THM

ENABLE

AVDD

SDA

MICBIAS

DETECT

BYPASS

INT*

SCL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PORT A DETECT (HEADPHONES)

PORT B DETECT(SPDIF DELEGATE)

NC

APN:376S0613

0X0A (10)

GPIO_3

MUTE CONTROL

N/A GPIO_3

HP=80HZ

CODEC OUTPUT SIGNAL PATHS

0X04 (4)

N/A

0X0C (12,C)

PULLUPS ON MCP PAGE

APN:353S2256

PORT C DETECT (LINE-IN)

0X0C (12,C)

0X10 (16)

CONVERTER

DET ASSIGNMENT

N/A

MIKEY

MIC_BIAS (80%) MIKEY

VREF

N/A

PIN COMPLEX

0X06 (6)

0X07 (7)

0X05 (5)

0X08 (8)

0X03 (3)

0X04 (4)

0X02 (2)

N/A

VOLUME

CODEC INPUT SIGNAL PATHS

HP/LINE OUT SATELLITES

FUNCTION

SPDIF OUT

SUB

NC

0X02 (2)

PLACE L6800/C6800 CLOSE TO U6800

NC

APN:376S0612

HEADSET MIC

APN:353S2401

EXTRACTION NOTIFICATION

BUILT-IN MIC

SPDIF IN

LINE IN

FUNCTION

0X0F (15)

CONVERTER

HP=80HZ, LP=8.82KHZ

DRC MIKEY

PORT B LEFT(HEADSET MIC)

0X03 (03)

PORT B RIGHT(BUILT-IN MIC)

N/A

0X0D (13,B,RIGHT)

0X0B (11)

0X09 (9,A)

0X09 (A) N/A N/A 0X0C (B)

DET ASSIGNMENT

0X0D (13,V22,B,LEFT)

PIN COMPLEX

10V

20%

402

CERM

0.1UF

C6801

1

2

1/16W

5%

402

MF-LF

47K

R6802

1 2

1/16W

5%

402

MF-LF

220K

R6801

1

2

57 58

39.2K

1/16W

1%

402

MF-LF

R6806

1

2

1/16W

5%

402

MF-LF

220K

R6803

1 2

1/16W

5%

402

MF-LF

220K

R6804

1

2

16V

10%

402

CERM

0.01UF

C6802

1

2

53 58

57 58

1/16W

1%

402

MF-LF

10K

R6813

1

2

10V

20%

402

CERM

0.1UF

C6811

1

2

1/16W

5%

402

MF-LF

270K

R6811

1

2

1/16W

5%

402

MF-LF

47K

R6812

1 2

57

MF-LF

1/16W

1%

402

20.0K

R6805

1

2

SOT563

SSM6N15FEAPE

Q6800

3

5

4

SOT563

SSM6N15FEAPE

Q6800

6

2

1

SOT563

SSM6N15FEAPE

Q6801

3

5

4

SOT563

SSM6N15FEAPE

Q6801

6

2

1

SOD-VESM-HF

SSM3K15FV

Q6802

3

1

2

53 58

402-1

MF

2.4K

1/16W

1%

R6851

1 2

CERM

CRITICAL

50V

5%

402

27PF

C6854

1

2

0.1UF

CRITICAL

25V

10%

402

X5R

C6850

1 2

50V

10%

402

CERM

0.001UF

CRITICAL

C6853

1

2

100K

1/16W

5%

402

MF-LF

R6852

1

2

SM

XW6851

1 2

53

6

57

6

57

6

57

CRITICAL

6.3V

20%

402

TANT

2.2UF

C6852

1

2

FERR-1000-OHM

0402

L6851

1 2

FERR-1000-OHM

0402

L6850

1 2

57

1/16W

5%

402

MF-LF

2.2K

MIKEY

R6882

1

2

50V

5%

402

MIKEY

CERM

27PF CRITICAL

C6885

1

2

25V

10%

402X7R

0.0082UF

MIKEY

CRITICAL

C6884

1

2

1/16W

5%

402

MF-LF

100K

MIKEY

R6883

1

2

25V

10%

402

X5R

CRITICAL

MIKEY

0.1UF

C6883

1 2

SM

XW6880

1 2

53

MIKEY

1/16W

1%

402

MF-LF

1K

R6881

1

2

MIKEY

1/16W

5%

402

MF-LF

100K

R6880

1

2

16V

10%

402

CERM

0.01UF

MIKEY

C6881

1

2

MIKEY

0402

FERR-1000-OHM

CRITICAL

L6880

1 2

6.3V

20%

603 X5R

10UF

MIKEY

CRITICAL

C6880

1

2

6.3V

20% 402

TANT

2.2UF

CRITICAL

MIKEY

C6882

1

2

20

20 43 72 78

8

18

MIKEY

1/16W

5%

402

MF-LF

2.2K

R6884

1 2

25V

10%

402

X5R

0.1UF

CRITICAL

MIKEY

C6886

1 2

53

CRITICAL

25V

10%

402

X5R

0.1UF

C6851

1 2

402

100

1/16W

1%

MF-LF

R6850

1 2

402-1

1%

1/16W

MF

2.4K

R6853

1 2

16

SC-70-1

TPS3801E18DCK

EXTRACT_DEBOUNCE

U6860

1 2

5 3

4

SOT563

SSM6N15FEAPE

EXTRACT_BUFF

Q6803

6

2

1

1/16W

5%

402

MF-LF

100

R6861

1 2

10V

20%

402

CERM

0.1UF

C6861

1

2

0402

FERR-1000-OHM

CRITICAL

L6862

1 2

220K

MF-LF

402

5%

1/16W

EXTRACT_BUFF

R6864

1 2

1/16W

5%

402

MF-LF

100K

EXTRACT_BUFF

R6865

1 2

SOT563

SSM6N15FEAPE

EXTRACT_BUFF

Q6803

3

5

4

EXTRACT_BUFF

10V

20% CERM

0.1UF

402

C6860

1

2

EXTRACT_BUFF

1/16W

5%

402

MF-LF

15K

R6860

1 2

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49

53 57 58 61 66 67 68 69 71

72 82

DRC

CD3275

MIKEY

U6880

3

10

2

8

9

4

7

1

6

5

11

AUDIO: JACK TRANSLATORS

SYNC_MASTER=K19_MLB

051-7903

58 83

A

SYNC_DATE=03/17/2009

HS_MIC_HI_RC

MIC_BIAS_FILT

HS_RX_BP

HS_SW_DET

HS_MIC_BIAS

HS_MIC_LO

PP3V3_S0_AUDIO_F

AUD_J1_SLEEVEDET_INV

PP3V3_S0_AUDIO_F

GND_AUDIO_CODEC

AUD_CODEC_MICBIAS

BI_MIC_SHIELD

GND_AUDIO_CODEC

BI_MIC_LO

AUD_J2_TIPDET_R

GND_AUDIO_CODEC

AUD_J2_DET_RC

AUD_INJACK_INSERT_L

PP3V3_S0_AUDIO_F

PP3V3_S0

AUD_J1_TIPDET_R

AUD_IP_PERIPHERAL_DET

GND_AUDIO_CODEC

TIPDET_FILT

AUD_J1_TIPDET_R

AUD_J1_SLEEVEDET_R

AUD_J1_DET_RC

AUD_PORTA_DET_L

HS_MIC_HI

AUD_MIC_INN_L

GND_AUDIO_CODEC

AUD_MIC_INN_R

BI_MIC_HI

AUD_SENSE_A

AUD_MIC_INP_L

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.1MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1MM

PP3V3_S0_HS_RX

SMBUS_MCP_1_CLK

AUD_MIC_INP_R

AUD_J1_TIPDET_R

GND_AUDIO_CODEC

MIN_LINE_WIDTH=0.1MM

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.1MM PP3V3_S0_AUDIO_F

PP3V3_S0_AUDIO_F

AUD_PERPH_DET_R

AUD_J1_TIPDET_INV

PP3V3_S0

BI_MIC_LO_F

BI_MIC_HI_F

GND_AUDIO_CODEC

AUD_IPHS_SWITCH_EN

AUD_I2C_INT_L

SMBUS_MCP_1_DATA

AUD_OUTJACK_INSERT_L

AUD_J1_SLEEVEDET_R

AUD_SENSE_A

AUD_PORTB_DET_L

58

53 54 58

58

57 58

53 54 58

57 58

53 54 58

58

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

53 54 58

57 58

BI

NC

VCC

EXTINT

NC

GND

Y

B

A

IN

P3 P4 P5 P6 P7 P8

P1 P2

P9

SHLD_PIN SHLD_PIN SHLD_PIN SHLD_PIN

OUT

SW

BOOST

VIN

BIAS

SHDN*

GND

NC

FB

PAD

THRM

OUT

NC

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

NC

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

connected.

send transients onto ADAPTER_SENSE when AC is

PWR

SIG

GND

PWR

GND

250mA max output

Vout = 3.425

(Switcher limit)

NC

516S0523

<Ra>

NC

BATTERY CONNECTOR

518-0358

TO SMC

BIL CONNECTOR

MagSafe DC Power Jack

1-Wire OverVoltage Protection

The chassis ground will otherwise float and can

6AMP-24V

CRITICAL

1206-2

F6905

1 2

0.01UF

603

CERM

20% 50V

PLACEMENT_NOTE=Place near L6900

C6905

1

2

40

805

1/8W

5%

MF-LF

47

R6905

1 2

X5R 805

10UF

10% 25V

C6990

1

2

CRITICAL

CDPH4D19FHF-SM

33UH

L6995

1 2

22pF

50V

CERM

402

5%

C6995

1

2

1% 1/16W

402

MF-LF

200K

R6996

1

2

348K

1/16W

1%

402

MF-LF

R6995

1

2

6.3V

20%

603

X5R-CERM

22UF

C6999

1

2

SOT665

HN2D01JEAPE

D6905

1

3

5

4

2

0.22UF

402

20%

6.3V X5R

C6994

1

2

CRITICAL

78048-0573

M-RT-SM

J6900

1 2 3 4 5

SC70-5

MAX9940

CRITICAL

U6900

5

2

4

3

1

0.1UF

20% CERM

PLACEMENT_NOTE=PLACE NEAR U6900 and U6901

10V 402

C6908

1

2

TC7SZ08AFEAPE SOT665

U6901

2

1

3

5

4

40 41 60

CRITICAL

NO STUFF

SC-75

RCLAMP2402B

D6900

3

1

2

CRITICAL

RCLAMP2402B

SC-75

D6950

3

1

2

402

1/16W MF-LF

5%

10K

R6950

1

2

402

10%

0.1UF

X5R

25V

C6950

1

2

M-RT-TH

CRITICAL

BAT-K19

J6950

10 11 12 13

1 2 3 4 5 6 7 8 9

10%

402

50V

0.001UF

CERM

C6954

1

2

50V

CERM

47PF

402

5%

C6953

1

2

CERM

47PF

50V

5%

402

C6952

1

2

F-ST-SM

CPB6312-0101F

CRITICAL

J6955

1

10

1112

1314

1516

2

34 56 78 9

10%

0.1UF

402

25V X5R

C6951

1

2

50V

10%

402

CERM

0.001UF

C6955

1

2

5%

402

1/16W

100

MF-LF

R6961

12

40 41 48

LT3470A

DFN

CRITICAL

U6990

2

3

1

5

7

8 4

9

6

40 41

6

40 43 59 60

81

6

40 43

59

60 81

2.0K

5% 1/16W MF-LF 402

R6929

1

2

DC-In & Battery Connectors

59 83

051-7903

A

SYNC_MASTER=K19_MLB

SYNC_DATE=03/18/2009

ADAPTER_SENSE

SMC_BIL_BUTTON_L

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

PP3V42_G3H

SMC_BC_ACOK

SMC_LID_R

SMC_LID

SYS_DETECT_L

SMBUS_SMC_BSA_SCL

PPBUS_G3H

SMBUS_SMC_BSA_SDA

PP3V42_G3H

PPVBAT_G3H_CONN

GND_BATT_CHGND

PPDCIN_S5

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.20mm

MIN_LINE_WIDTH=1mm

PP18V5_DCIN_FUSE

PPDCIN_S5

SMC_BC_ACOK_VCC

SYS_ONEWIRE

P3V42G3H_BOOST

MIN_NECK_WIDTH=0.3 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.3 mm

PPVIN_G3H_P3V42G3H

VOLTAGE=18.5V

PPDCIN_S5_P3V42G3H

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

P3V42G3H_FB

PP3V42_G3H

DIDT=TRUE

MIN_NECK_WIDTH=0.25 mm

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 mm

P3V42G3H_SW

6

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6

40 43 59 60 81

6 7

35 44 45 60 62 63 64 73

6 40 43 59 60 81

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6

60

6 8

7

59 60

6

7

59 60

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

CSON

CSOP

VNEG

VCOMP

ICOMP

VREF ACIN

SDA

VHST SCL

VDDP

BGATE

VDD

ACOK

THRM_PAD

AGATE

AGND

AMON BMON

BOOT

CSIN

CSIP

DCIN

LGATE

PGND

PHASE

UGATE

TRKL*

NC

OUT

IN

BI

OUT

GND

VCC

D

S G

D

S G

D

G

S

D

G

S

D

G

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(CHGR_CSO_N)

(PPVBAT_G3H_CHGR_R)

(CHGR_AGATE)

Inrush Limiter

sparkitecture requirements

ACIN pin threshold

Reverse-Current Protection

3S Battery Default

2S Battery Default

32V/V

30mA max load

(OD)

20V/V

R7075 clamps CHGR_AMON when charger is

TO SYSTEM

not powered to counter TL331 bias current.

VREF = 3.2V, < 300uA

Divider sets ACIN

is 3.2V, +/- 50mV

Input impedance of ~40K meets

threshold at 13.07V

(CHGR_CSO_P)

(CHGR_DCIN)

FROM ADAPTER

(OD)

Max Current = 8.5A (L7030 limit) f = 400 kHz

152S0542

9.31K

1/16W MF-LF

402

1%

R7011

1

2

0.033UF

X5R 402

10% 16V

C7042

1

2

470PF

CERM 402

10% 50V

C7016

1

2

MF-LF

402

1%

1/16W

3.01K

R7016

1

2

0.001UF

CERM

402

10% 50V

C7015

1

2

56.2K

MF-LF 402

1% 1/16W

R7015

1

2

1UF

X5R

10% 10V

402-1

C7002

1

2

402-1

10V

10% X5R

1UF

C7000

1

2

4.7

MF-LF

402

5%

1/16W

R7001

1 2

SOD-723-HF

1SS418

D7005

1

2

30.1K

402

1% 1/16W MF-LF

R7010

1

2

X5R 402

10% 25V

0.1UF

C7060

1

2

MF-LF 402

5% 1/16W

470K

R7060

1

2

1.82K

MF-LF

402

1%

1/16W

R7071

1

2

57.6K

MF-LF

402

1%

1/16W

R7070

1

2

402

10% 16V

0.01uF

CERM

C7057

1

2

X5R 402

10% 16V

0.1UF

C7056

1

2

SM

XW7000

1 2

OMIT

QFN

CRITICAL

ISL6258A

U7000

3

14

1

6

26

9

16

15

25

27

28

17

18

2

5

21

22

23

11 10

29

13

24

7

19

20

12

8

4

X5R

10% 10V

1UF

402-1

C7001

1

2

0.1UF

X5R 402

25V

10%

C7021

1

2

10% X5R

25V 402

0.1UF

C7022

1

2

CERM

10%

0.047UF

402

10V

C7020

1

2

0.1UF

402

X5R

25V

10%

C7035

1

2

RJK0305DPB

CRITICAL

LFPAK-HF

Q7035

5

4

1 2 3

402

10

5% 1/16W MF-LF

R7022

1 2

5%

10

1/16W MF-LF

402

R7021

1 2

22UF

CASE-D2-SM

CRITICAL

POLY-TANT

20% 25V

C7030

1

2

CRITICAL

POLY-TANT CASE-D2-SM

22UF

20% 25V

C7031

1

2

1UF

603-1

X5R

10% 25V

C7032

1

2

20%

POLY-TANT

CASE-D2-SM

22UF

CRITICAL

25V

C7040

1

2

1206-2

8AMP-24V

CRITICAL

F7040

1

2

10

5%

1/16W

402

MF-LF

R7051

1 2

MF-LF

10

402

1/16W

5%

R7052

1 2

603-1

1UF

X5R

10% 25V

C7033

1

2

SOD-723-HF

NOSTUFF

1SS418

D7040

1 2

62K

MF-LF

402

5%

1/16W

R7066

1

2

MF-LF

100K

402

5%

1/16W

R7065

1

2

1UF

X5R

603-1

10% 25V

C7055

1

2

5% MF-LF

402

330K

1/16W

R7061

1

2

0.1UF

X5R

10% 25V

402

C7005

1

2

45

45 60

6

40 43 59 81

6

40 43 59 81

CERM 402

10% 16V

0.01UF

C7011

1

2

X5R 402

10% 16V

0.1uF

C7070

1

2

X5R 402

10% 16V

0.1uF

C7050

1

2

CERM 402

10% 50V

0.001UF

C7026

1

2

40 41 59

CRITICAL

0.01

1W

0.5% MF

0612-1

R7050

12 34

CRITICAL

0612-1

0.02

0.5% MF

1W

R7020

123

4

TL331

SOT23-5

U7070

1

3

4

5

2

FDA1254F-SM

CRITICAL

4.7UH-10.2A

L7030

1

2

3

SSM6N15FEAPE

SOT563

Q7074

3

5

4

1M

MF-LF 402

5% 1/16W

R7074

1

2

SSM6N15FEAPE

SOT563

Q7074

6

2

1

402

X7R

0.001UF

10% 50V

C7034

1

2

X7R 402

10% 50V

0.001UF

C7041

1

2

SI7137DP

CRITICAL

SO-8

Q7055

5

4

1 2 3

HAT1128R01

SOI

CRITICAL

Q7060

5 6 7 8

4

1 2 3

SOI

HAT1128R01

CRITICAL

Q7065

5 6 7 8

4

1 2 3

RJK0305DPB

LFPAK-HF

CRITICAL

Q7030

5

4

1 2 3

60 83

A

SYNC_DATE=03/18/2009

PBus Supply & Battery Charger

SYNC_MASTER=K19_MLB

051-7903

CRITICAL ISL6258A353S1832

1

U7000

IC,ISL6258A,BAT CHARGER,4X4MM,QFN28

CRITICAL

ISL6258

353S1811

1

IC,ISL6258,BAT CHARGER,28P,4X4,QFN,L

U7000

MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V

PPVBAT_G3H_CHGR_REG

MIN_NECK_WIDTH=0.4 mm

DIDT=TRUE

CHGR_UGATE

CHGR_BGATE

CHGR_CSI_N

CHGR_BOOT

PPDCIN_S5_FET_CHGR

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

SGATE_P0V1_VREF

CHGR_DCIN

PP5V1_CHGR_VDD

VOLTAGE=5.1V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PPDCIN_S5

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE DIDT=TRUE

CHGR_PHASE CHGR_LGATE

DIDT=TRUE

PPVBAT_G3H_CHGR_R

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

CHGR_CSI_P

PP5V1_CHGR_VDD

PP3V42_G3H

SMBUS_SMC_BSA_SCL

CHGR_ACIN

SMBUS_SMC_BSA_SDA

CHGR_ICOMP CHGR_VCOMP

MIN_NECK_WIDTH=0.4 mm VOLTAGE=18.5V

MIN_LINE_WIDTH=0.6 mm

PPDCIN_S5_CHGR_R

CHGR_CSI_R_N

CHGR_SGATE_DIV

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.3 mm

CHGR_AGATE_DIV

CHGR_AMON

AMON_CLAMP

CHGR_VCOMP_R

CHGR_VNEG_R

PPVBAT_G3H_CONN

MIN_NECK_WIDTH=0.4 mm VOLTAGE=12.6V

MIN_LINE_WIDTH=0.6 mm

PP3V42_G3H

CHGR_SGATE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.3 mm

PPBUS_G3H

CHGR_VNEG

CHGR_CSO_N

MIN_LINE_WIDTH=0.6 mm VOLTAGE=18.5V

MIN_NECK_WIDTH=0.4 mm

PPDCIN_S5_INRUSH

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

GND_CHGR_AGND

MIN_LINE_WIDTH=0.2 mm

CHGR_CSO_P

CHGR_CSO_R_P

CHGR_BMON

CHGR_AGATE

PP5V1_CHGR_VDDP

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5.1V

MIN_LINE_WIDTH=0.2 mm

TP_CHGR_TRKL

CHGR_CSO_R_N

SMC_BC_ACOK

CHGR_AMON

CHGR_CSI_R_P

81

60

7

59

81

60

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

82

45 60

6

59

6 7

20 21 24 38 40 41 42 43 45

48 59 60 67

6 7

35 44 45 59 62 63 64 73

81

45 82

45

82

IN

OUT

IN

OUT

IN

OUT OUT

IN

OUT

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT* NTC

VR_ON PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3 VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1 BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

S

G

D

G

S

G

D

G

S

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(IMVP6_PHASE1)

These caps are for Q7100 These caps are for Q7102

(IMVP6_ISEN2)

(IMVP6_PHASE2)

(IMVP6_ISEN1)

0

DPRSLPVR

1-Phase1

1

0 1-Phase

DPRSTP*

Place R7131 Between L7100,L7101 and CPU

1

2-Phase

DCM1-Phase

(IMVP6_FB)

(GND_IMVP6_SGND)

44A MAX CURRENT

Operation

(GND_IMVP6_SGND)

Place R7126 in hot

0 1

(IMVP6_VO)

Mode

CCM

PSI*

(GND)

(ISL9504A)

(IMVP6_VSUM)

CCM

1

0 0

0 1

(IMVP6_VO)

(GND)

(IMVP6_COMP)

(IMVP6_VW)

(IMVP6_NTC)

(PGD_IN)

DCM

spot of reg circuit.

LAYOUT NOTE:

10K

MF-LF

402

1%

1/16W

R7100

1 2

0.22UF

CERM

402

10% 10V

C7103

1 2

SM

XW7104

12

0.22UF

X5R 603

20% 25V

C7115

1

2

9

13 75

20 75

9

8

61

24

SM

XW7102

12

1/16W

10K

MF-LF

402

1%

R7105

1 2

0.22UF

CERM

402

10% 10V

C7104

1 2

0.22UF

603

20% 25V X5R

C7127

1

2

10

MF-LF

402

1%

1/16W

R7120

1 2

10

MF-LF

402

1%

1/16W

R7112

1 2

10

MF-LF

402

1%

1/16W

R7121

1 2

0.1uF

X5R 402

10% 16V

C7130

1

2

499

MF-LF

402

1%

1/16W

R7119

1 2

0.001UF

CERM

402

10% 50V

C7107

1

2

6.81K

MF-LF 402

1% 1/16W

R7110

1

2

4.7UF

X5R-CERM 402

20%

6.3V

C7135

1

2

0.01uF

CERM

402

10% 16V

C7110

1

2

1K

MF-LF

402

1%

1/16W

R7113

1

2

1K

MF-LF 402

1% 1/16W

R7109

1

2

220PF

X7R-CERM

402

10% 50V

C7113

1

2

97.6K

MF-LF

402

1%

1/16W

R7114

1

2

1

MF-LF 402

5% 1/16W

R7104

1

2

1

MF-LF 402

5% 1/16W

R7107

1

2

NO STUFF

0.001uF

CERM

402

10% 50V

C7116

1

2

1/16W

1%

402

MF-LF

4.12K

R7117

1 2

180pF

CERM 402

5% 50V

C7129

1

2

1K

MF-LF 402

1% 1/16W

R7118

1

2

2.61K

MF-LF

402

1%

1/16W

R7130

1

2

MF-LF

1% 1/16W

402

11K

R7115

1

2

0.22UF

CERM-X5R

402

10%

6.3V

C7128

1

2

0.068UF

CERM 402

10% 10V

C7134

1

2

MF-LF

402

5%

1/16W

0

R7122

1 2

0.01UF

CERM

402

10% 16V

C7131

1

2

NO STUFF

0.01uF

CERM 402

10% 16V

C7132

1

2

0

MF-LF

402

5%

1/16W

R7123

1 2

0.01uF

CERM

402

10% 16V

C7133

1

2

0.22UF

X5R 402

6.3V

20%

C7121

1

2

SM

XW7100

1 2

3.65K

MF-LF 603

1% 1/10W

R7101

1

2

3.65K

MF-LF 603

1% 1/10W

R7106

1

2

MPCG1040-SM

0.36UH-26A-1.05MOHM

CRITICAL

L7100

1 2

MPCG1040-SM

0.36UH-26A-1.05MOHM

CRITICAL

L7101

1 2

0.1UF

X5R 402

10% 16V

C7196

1

2

8

75

8

75

8

75

8

75

8

75

8

75

8

75

0.001UF

CERM 402

10% 50V

C7106

1

2

470PF

CERM 402

10% 50V

C7114

1

2

MF-LF

402

1%

1/16W

255

R7111

1

2

0.015UF

X7R 402

10% 16V

C7105

1

2

13.3K

MF-LF 402

1% 1/16W

R7116

1

2

1UF

X5R

10% 25V

603-1

C7109

1

2

CRITICAL

10KOHM-5%

0603-LF

R7131

1

2

147K

MF-LF 402

1% 1/16W

R7108

1

2

1/16W

4.02K

MF-LF

402

1%

R7127

1

2

10K

MF-LF 402

5% 1/16W

R7197

1

2

SM

XW7103

1 2

SM

XW7101

1 2

61

10 75

CRITICAL

470K

402

R7126

1

2

0

MF-LF

402

5%

1/16W

R7198

1 2

9

13 41 75

68

MF-LF 402

5% 1/16W

R7199

1

2

QFN

ISL9504BCRZ

U7100

48

36 26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

S1

IRF6710

CRITICAL

Q7100

1 2 5 64

3

IRF6795

CRITICAL

DIRECTFET-MX

Q7103

1 2 6 7

5

3 4

IRF6710

S1

CRITICAL

Q7102

1 2 5 64

3

CRITICAL

IRF6795

DIRECTFET-MX

Q7101

1 2 6 7

5

3 4

1UF

X5R 603-1

10% 25V

C7154

1

2

45

I848I849

0

MF-LF

402

5%

1/16W

R7160

1 2

0.001UF

X7R 402

10% 50V

C7108

1

2

0.001UF

X7R 402

10% 50V

C7152

1

2

0.001UF

X7R 402

10% 50V

C7156

1

2

0.001UF

X7R 402

10% 50V

C7157

1

2

X5R

10% 10V

402-1

1UF

C7126

1

2

20%

68UF

CASE-D2E-SM

POLY-TANT

16V

CRITICAL

C7117

1

2

20%

68UF

CASE-D2E-SM

POLY-TANT

16V

CRITICAL

C7155

1

2

20%

68UF

CASE-D2E-SM

POLY-TANT

16V

CRITICAL

C7153

1

2

IMVP6 CPU VCore Regulator

SYNC_MASTER=K19_MLB

051-7903

A

61 83

SYNC_DATE=02/05/2009

DIDT=TRUE

IMVP6_PHASE2

IMVP6_UGATE2

DIDT=TRUE

IMVP6_VSUM

IMVP6_ISEN1

MIN_NECK_WIDTH=0.20 MM

GND_IMVP6_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.50 MM

PP5V_S0_IMVP6_VDD

VOLTAGE=5V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_VID<3>

IMVP6_VID<4>

IMVP6_VID<5>

PPVIN_S5_IMVP6_VIN

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=12.6V

PP5V_S0

IMVP_VR_ON_R

IMVP6_ISEN2

IMVP6_VO IMVP6_DROOP

IMVP6_COMP

IMVP6_VSUM1

PPVCORE_S0_CPU

IMVP6_OCSET

IMVP6_DFB

IMVP6_BOOT1

IMVP6_VID<6>

IMVP6_DROOP

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_FB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VO_R

IMVP6_SOFT

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_COMP

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

PM_DPRSLPVR

IMVP6_PHASE2

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_BOOT2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_UGATE2

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPU_VCCSENSE_P

CPU_VCCSENSE_N

IMVP6_VO1

IMVP6_VSUM2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_VO1

MIN_NECK_WIDTH=0.25 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_LGATE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_PHASE1

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_FB2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VDIFF

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_RBIAS

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DFB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VO

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_OCSET

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_VSUM1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_UGATE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_ISEN1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_VSEN_P

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_VDIFF_RC

IMVP_VR_ON

IMVP6_VO2

IMVP6_VSEN_N

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_VO2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_ISEN2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_LGATE2

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_VW

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_NTC_R

TP_IMVP6_CLKEN_L

CPU_DPRSTP_L

IMVP6_VID<0>

IMVP6_VID<2>

PP1V05_S0

PP3V3_S0

IMVP6_FB2

IMVP6_VW

IMVP6_COMP_RC

IMVP6_RBIAS

IMVP6_NTC

IMVP6_VR_TT_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_IMVP6_3V3

IMVP_VR_ON_R

IMVP6_FB

IMVP6_VSEN_P

IMVP6_VSEN_N

IMVP6_VDIFF

IMVP6_SOFT

CPU_PROCHOT_L

IMVP6_VSUM2

IMVP6_BOOT2

IMVP6_IMON

CPU_PSI_L

IMVP_DPRSLPVR

IMVP6_VID<1>

VR_PWRGOOD_DELAY

IMVP6_LGATE1

DIDT=TRUE

IMVP6_LGATE2

DIDT=TRUE

IMVP6_BOOT1

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

IMVP6_UGATE1 IMVP6_PHASE1

DIDT=TRUE

PPBUS_CPU_IMVP_ISNS

61

6 7

37 42 47 49

64 65 67 68 70 72

61

6 7

10 11 44

61

61 75

40

61

61 75

61

6 7 9

10 11 12 13

16 17 19 21 22 23

35 65 66 67

6 7

12 17 18 20

21 22 23 26 27 35

37 41 43 45 46 47

49 53 57 58 66 67

68 69 71 72 82

61

61 75

61

75

61

7

45 65

OUT

Q1

Q2

SW

DRVH1

SKIPSEL

VBST1

GND

THRM_PAD

ENTRIP1

VFB1

VO1

DRVL1

LL1

EN0

VCLK

ENTRIP2

PGOOD

VO2

VFB2

DRVL2

LL2

DRVH2

VBST2

VREG5

VREG3

VREF

VIN

TONSEL

D

SG

D

SG

IN

IN IN

G

D

S

G

D

S

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

f=460KHz

(L7260 limit)

5.5A max output

Vout = 3.3V

(P5VS5_VO1)

(P3V3S5_V02)

One master PGOOD for both 5V and 3V3

f=365KHz

(Q7220 limit)

13A max output

Vout = 5.0V

25V

10%

603-1

X5R

1UF

C7200

1

2

CRITICAL

IHLP2525CZ

4.7UH-5.5A

L7260

1 2

10% X5R

1UF

25V 603-1

C7241

1

2

0.1UF

X7R

10% 50V

603-1

C7264

1

2

10UF

6.3V

20% X5R

603

C7290

1

2

603-1

50V

10% X7R

0.1UF

C7224

1

2

CRITICAL

POLY-TANT

20%

6.3V

NO STUFF

150UF

CASE-B2-SM

C7252

1

2

805

10UF

X5R

20% 10V

C7250

1

2

CRITICAL

20%

150UF-.025-OHM

CASE-B2-SM

TANT

6.3V

C7292

1

2

25V

10%

603-1

X5R

1UF

C7281

1

2

PCMB104E4R7-SM

CRITICAL

4.7UH-13A-15MOHM

L7220

1 2

1/16W

1%

402

MF-LF

86.6K

R7200

1

2

6.3V

20%

603

X5R

10UF

C7203

1

2

10UF

603

6.3V

20% X5R

C7205

1

2

75K

MF-LF 402

1% 1/16W

R7206

1

2

24 40 64 65 66 67

SM

PLACEMENT_NOTE=Place XW7260 next to L7260.

XW7260

1

2

SM

PLACEMENT_NOTE=Place XW7220 next to L7220.

XW7220

1

2

NO STUFF

25V

5%

402

CERM

220PF

C7208

1

2

SM

PLACEMENT_NOTE=Place XW7200 next to U7200 pin 15.

XW7200

1 2

MLP

FDMS9600S

CRITICAL

Q7260

2349

1

8

56

7

10

QFN

TPS51125

U7201

21 10

19 12

13

1 6

15

20 11

23

14

25

4

22 9

18

2 5

16

24 7

3

8

17

402

CERM

10%

0.22UF

10V

C7201

1

2

6.49K

MF-LF

402

1%

1/16W

R7260

1

2

10K

MF-LF

402

1%

1/16W

R7261

1

2

5%

402

MF-LF

1/16W

15K

R7220

1

2

10K

MF-LF 402

1% 1/16W

R7221

1

2

SSM6N15FEAPE

SOT563

Q7210

3

5

4

SOT563

SSM6N15FEAPE

Q7210

6

2

1

5%

10

1/16W

402

MF-LF

NO STUFF

R7222

1

2

CERM

402

50V

5%

100PF

NO STUFF

C7222

1

2

10

MF-LF

402

5%

1/16W

NO STUFF

R7262

1

2

50V

5% 402

CERM

100PF

NO STUFF

C7262

1

2

MF-LF

1/16W

5%

0

402

R7264

2

1

0

5% 1/16W MF-LF

402

R7224

2

1

0.001UF

CERM

50V

10%

402

C7243

1

2

10% 50V CERM

0.001UF

402

C7282

1

2

50V CERM

10%

0.001UF

402

C7251

1

2

0.001UF

50V

10%

402

CERM

C7291

1

2

402

MF-LF

1/16W

5%

100K

R7273

2

1

150UF

CRITICAL

20%

CASE-B2-SM

POLY-TANT

6.3V

C7253

1

2

6 8

40 67

67 67

CRITICAL

STL11NH3LL

PWRFLAT-SM

Q7220

5

4

123

STL15N3LLH5

CRITICAL

PWRFLAT-SM

Q7225

5

4

123

16V POLY-TANT CASE-D2E-SM

68UF

20%

CRITICAL

C7280

1

2

CRITICAL

16V POLY-TANT CASE-D2E-SM

68UF

20%

C7240

1

2

SYNC_DATE=01/13/2009

051-7903

A

8362

SYNC_MASTER=WFERRY_K19I

5V / 3.3V Power Supply

152S0778 152S0693

ALL

Cyntec alternate to MagLayers

PPBUS_G3H

PP5V_S3

P5VS5_VFB

P5VS5_REG_XW

P5VP3V3_VREG5

P5VP3V3_VREF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GATE_NODE=TRUE

P5VS5_DRVL

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

P3V3S5_LL

SWITCH_NODE=TRUE

PP3V3_S5

P3V3S5_VFB

ALL_SYS_PWRGD

P5VS5_ENTRIP

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_P5VP3V3_SGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_VBST

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P3V3S5_DRVH

DIDT=TRUE

GATE_NODE=TRUE

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

P3V3S5_DRVL

P5VS5_DRVH

MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE MIN_NECK_WIDTH=0.2 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_LL

SWITCH_NODE=TRUE

DIDT=TRUE

PM_SLP_S3_L_INVERT

PM_G2_P3V3S5_EN_L

P3V3S5_ENTRIP

P5V3V3_EN0

SMC_PM_G2_EN

P5VP3V3_VREG3

P5VS5_RC

P3V3S5_REG_XW

P3V3S5_RC

P3V3S5_VBST_R

P5VS5_VBST

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P5VS5_VBST_R

6 7

35 44 45 59 60 63 64 73

6 7 8

29 37 38 39 41 49 51 53

63 68

6 7

17 19 21 22 24 28 32 35 36

42 52 66 67 68 69 71 82

MODE

VDDQSNS

COMP

NC0 NC1

VTTSNS

VTT

VTTREF

PGOOD

S3 S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN IN OUT

NC NC

S

D

G

OUT

S

D

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 0.75V * (1 + Ra / Rb)

<Rb>

(DDRREG_VDDQSNS)

Vout = VDDQSNS/2

Vout = VTTREF

(DDRREG_DRVH)

(DDRREG_VBST)

(DDRREG_LL)

VTT Enable VDDQ/VTTREF Enable VDDQ PGOOD

(DDRREG_FB)

<Ra>

f = 400 kHz

(Q7335 limit)

15A max output

Vout = 1.5V

10mA max load

(DDRREG_DRVL)

(DDRREG_CSGND)

0.1UF

X7R

603-1

10% 50V

C7325

1 2

402

1/16W

15.0K

MF-LF

1%

R7320

1

2

MF-LF 402

15.0K

1% 1/16W

R7321

1

2

1UF

X5R 603-1

10% 25V

C7332

1

2

NO STUFF

100PF

CERM

402

5%

50V

C7320

1

2

CRITICAL

TPS51116

QFN

U7300

6

16

17

21

19

3

20

4

7

12

18

13

10 11

25

14

15

22

9

8

23

24

1

5

2

4.7

5% 1/16W MF-LF

402

R7305

1 2

22UF

20%

6.3V 603

X5R-CERM

CRITICAL

C7361

1

2

CRITICAL

22UF

X5R-CERM

603

20%

6.3V

C7360

1

2

SM

PLACEMENT_NOTE=Place next to C7360

XW7360

1 2

SM

PLACEMENT_NOTE=Place next to Q7335

XW7335

1 2

X5R

10% 16V

402

0.033UF

C7350

1

2

8

24 68

4.7UF

CERM

603

20%

6.3V

C7300

1

2

67

10K

MF-LF

402

1%

1/16W

R7310

1

2

67

22UF

20% 25V

CRITICAL

POLY-TANT

CASE-D2-SM

C7330

1

2

22UF

20% 25V

CASE-D2-SM

POLY-TANT

CRITICAL

C7331

1

2

1.0UH-13A-5.6MOHM

PCMB065T-SM

CRITICAL

L7330

1 2

PLACEMENT_NOTE=Place next to C7345

SM

XW7345

1

2

10UF

X5R 603

20%

6.3V

C7355

1

2

SM

XW7300

1

2

CRITICAL

270UF

CASE-B4-SM

2V

TANT

20%

C7341

1

2

270UF

20% TANT

CASE-B4-SM

2V

CRITICAL

C7340

1

2

20%

10UF

X5R 603

6.3V

C7345

1

2

0.001UF

X7R 402

10% 50V

C7333

1

2

0.001UF

X7R 402

10% 50V

C7346

1

2

PWRPK-1212-8-HF

SI7110DN

CRITICAL

Q7330

51 82

PWRPK-1212-8-HF

CRITICAL

SI7108DN

Q7335

402-1

X5R

10V

10%

1UF

C7305

1

2

SM

XW7330

1 2

SM

XW7331

1 2

SM

XW7332

1 2

SYNC_MASTER=K19_MLB

A

8363

051-7903

SYNC_DATE=02/04/2009

1.5V DDR3 Supply

ISNS_1V5_S3_N

ISNS_1V5_S3_P

PP1V5_S3

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

DDRREG_DRVL

GATE_NODE=TRUE

PP5V_S3

VOLTAGE=5V

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S3_DDRREG_V5FILT

MEM_VTT_EN DDRREG_EN TP_DDRREG_PGOOD

PPBUS_G3H

MIN_NECK_WIDTH=0.17 mm

DDRREG_VBST

MIN_LINE_WIDTH=0.6 mm

DDRREG_CSGND

MIN_NECK_WIDTH=0.1 mm

MIN_LINE_WIDTH=0.1 mm

PP1V5_S3

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6 mm

DDRREG_LL

DIDT=TRUE

MIN_NECK_WIDTH=0.17 mm

MIN_LINE_WIDTH=0.6 mm

DIDT=TRUE

DDRREG_DRVH

GATE_NODE=TRUE

DDRREG_VTTSNS

PPVTTDDR_S3

MIN_LINE_WIDTH=2 mm

MIN_NECK_WIDTH=0.17 mm

PP0V75_S0_DDRVTT

DDRREG_CS

MIN_NECK_WIDTH=0.1 MM

PPDDR_S3_REG_R

MIN_LINE_WIDTH=0.8 MM

VOLTAGE=1.5V

DDRREG_FB

DDRREG_VDDQSNS

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.17 mm

MIN_NECK_WIDTH=0.17 mm

GND_DDRREG_SGND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

6 7

26 27 28 63 68

6 7 8

29 37 38 39 41 49 51 53

62 68

6 7

35 44

45 59 60 62

64 73

6 7

26 27 28 63 68

7

25

6 7

26 27 68

IN

OUT

OCSET

ICOMP

RBIAS

LGATE

THRM_PAD

FDE

IMON

PVCC

PHASE

UGATE

BOOT

VDD

VSS

VIN

VO

VSEN

VDIFF

FB

COMP

VW

SOFT

PGND

ISN

ISP

RTN

PGOOD

AF_EN

VR_ON

OFFSET1

OFFSET0

VID2

VID1

VID0

G

D

S

D

S

G

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(MCPCORES0_PHASE)

(Q7560 Limit)

101 0.80V 110 0.75V

(MCPCORES0_VW)

(MCPCORES0_ISN)

OF MCP

PLACE XW NEAR THE MCP,

(MCPCORES0_VDIFF)

CONNECT SENSE LINES TO CLOSEST

(MCPCORES0_RTN)

(MCPCORES0_VSEN)

(MCPCORES0_ICOMP)

VID<2:0> VOLTAGE

001 1.00V 010 0.95V 011 0.90V 100 0.85V

(MCPCORES0_VO)

000 1.05V

(MCPCORES0_LGATE)

MAX CURRENT: 15.5A

f = 300 kHz

(MCPCORES0_COMP)

(MCPCORES0_FB)

111 0.70V

MCPCORE AND GND BALL

(MCPCORES0_UGATE)

SM

OMIT

XW7563

1 2

OMIT

SM

XW7562

1 2

20

1/16W MF-LF

1%

402

R7568

1 2

20

1% 1/16W MF-LF

402

R7566

1 2

0.001UF

402

X7R

10% 50V

C7570

1

2

1/16W MF-LF

1%

402

100

R7563

1

2

1/16W

1%

402

MF-LF

20.0K

R7582

1

2

1/16W

1%

402

MF-LF

20.0K

R7583

1

2

5%

1/16W

402

MF-LF

0

R7592

1 2

1/16W

1% MF-LF

20.0K

NOSTUFF

402

R7580

1

2

1%

402

NOSTUFF

1/16W

20.0K

MF-LF

R7581

1

2

0

1/16W

5%

402

MF-LF

R7591

1 2

16V 402

10%

0.1UF

X7R-CERM

C7576

1

2

150K

MF-LF 402

1% 1/16W

R7572

1

2

67

24 40

62

65

66

67

5%

402

1/16W MF-LF

0

R7590

1 2

1K

1/16W

5%

402

MF-LF

R7561

1

2

ISL6263D

QFN

U7500

30

17

5

6

32

10

28

11

13

21

3

23 24

20

31 19

22

1

9

2

33

18

16

7

25 26 27

14

12

29

8

15

4

SM

XW7561

1 2

MF-LF 402

1% 1/16W

47.0K

R7575

1

2

1%

10K

402

MF-LF

1/16W

R7573

1

2

1% 1/16W MF-LF

402

11.3K

R7569

1 2

0

5% 1/10W MF-LF

603

R7565

1 2

CERM-X7R

10V

5%

603

0.22UF

C7564

1 2

16V

1UF

402

10% X5R

C7550

1

2

2.2

1/10W

5%

603

MF-LF

R7560

1 2

1UF

402

X5R

16V

10%

C7562

1

2

MF-LF

1/16W

1%

402

100

R7578

1 2

1/16W

1%

402

MF-LF

2.21K

R7579

1 2

1%

402

MF-LF

133K

1/16W

R7577

1 2

50V

5%

402-1

CERM

68PF

C7580

1 2

50V

10%

402

CERM

560PF

C7581

1 2

1%

100

1/16W 402

MF-LF

R7571

1

2

50V

10%

402

CERM

560PF

C7582

1 2

10% 50V

402

X7R

0.001UF

C7579

1

2

1/16W

1%

402

MF-LF

6.98K

R7576

1

2

NO STUFF

MF-LF

1

1/10W 603

5%

R7589

1

2

NO STUFF

50V

10%

0.001UF

402

X7R

C7589

1

2

X5R

20% 603

4V

10UF

C7566

1

2

CASE-B4-SM

2V TANT

270UF

20%

CRITICAL

C7568

1

2

10%

402

50V X7R

0.001UF

C7569

1

2

270UF

20% 2V TANT CASE-B4-SM

CRITICAL

C7565

1

2

20% X5R

10UF

603

4V

C7567

1

2

1UF

X5R 603-1

10% 25V

C7561

1

2

0.001UF

X7R 402

10% 50V

C7563

1

2

100

402

MF-LF

1/16W

1%

R7500

1 2

47PF

50V

CERM

5%

402

C7573

1

2

47PF

5% CERM

402

50V

C7575

1

2

0

MF-LF

402

5%

1/16W

R7593

1 2

CRITICAL

0.001

1% 1W MF

0612

R7525

1 2 3 4

POWER33-SM

FDMC8676

CRITICAL

Q7560

5

4

1 2 3

MICROFET3X3

FDMC8678S

CRITICAL

Q7565

5

4

1 2 3

1.0UH-17A-5M-OHM

HAHF651R0AP-SM

CRITICAL

L7560

1 2

16V

20% POLY-TANT

CRITICAL

68UF

CASE-D2E-SM

C7540

1

2

20%

68UF

CASE-D2E-SM

POLY-TANT

16V

CRITICAL

C7560

1

2

MCP CORE REGULATOR

SYNC_DATE=02/03/2009

64 83

A

051-7903

SYNC_MASTER=K19_MLB

MIN_NECK_WIDTH=0.2 MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM

MCPCORES0_UGATE

MCPCORE_SNUBBER

MCPCORES0_RTN MCPCORES0_VW

PPVCORE_S0_MCP

PPBUS_G3H

MCPCORES0_VDIFF

5V_S0_MCPREG_VIN

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=5V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1V

PPMCPCORE_S0_R

MCPCORES0_PHASE

DIDT=TRUE

MIN_NECK_WIDTH=0.2 MM

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.5 MM

SWITCHNODE

MCP_VID<2>

MCPCORES0_OCSET

MIN_NECK_WIDTH=0.2 MM

GATE_NODE=TRUE

MCPCORES0_LGATE

MIN_LINE_WIDTH=0.5 MM

DIDT=TRUE

MCP_VID2_R

MCPCORES0_FDE

0.25 MM

0.2 MM

MCPCORES0_BOOT

MCP_VID<1>

MCP_VID<0>

MCPCORES0_RSEN_P

MCPCORES0_EN

ALL_SYS_PWRGD

MCPCORES0_RSEN_N

PPVCORE_S0_MCP

MCPCORES0_COMP_C

MCPCORES0_VDIF_C

0.2 MM

0.25 MM

MCPCORES0_BOOT_R

MCPCORES0_IMON

PP5V_S0

MCPCORES0_COMP

MCPCORES0_OS0

MCPCORES0_ICOMP

MCPCORES0_ISN

MCPCORES0_RBIAS

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=0V

GND_MCPCORES0_AGND

MCPCORES0_FB

MCPCORES0_ISP

MCPCORES0_VO

MCPCORES0_ISP_R

MCPCORES0_VSEN

MCPCORES0_OS1

PPVCORE_S0_MCP

MCP_VID1_R

MCP_VID0_R

MCPCORES0_IMON_R

MCPCORES0_SOFT

6 7

21 22 44 64

6 7

35 44 45 59 60 62 63 73

6

82

6 7

21 22 44 64

45

6 7

37 42 47 49 61 65 67 68

70 72

6 7

21 22 44 64

Q1

Q2

SW

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 1.052V

M99 differences from last sync on 12/03/07 to T18 MLB:

1. Tied THERMAL_PAD to PGND. GND and THERMAL_PAD disconnected.

8A max output (Q7660 limit?)

Vout = 0.75V * (1 + Ra / Rb)

f = 360 kHz

(GND)

(CPUVTTS0_VFB)

(=PPCPUVTT_S0_REG)

<Rb>

<Ra>

(=PPCPUVTT_S0_REG)

X5R

20%

603

6.3V

10UF

C7665

1

2

1UF

X5R

10% 25V

603-1

C7695

1

2

MF-LF 402

1/16W

1%

8.06K

R7670

1

2

MF-LF 402

1% 1/16W

20.0K

R7671

1

2

2.0V

330UF

B2-SM

20%

POLY-TANT

CRITICAL

C7660

1

2

CRITICAL

PCMB065T-SM

2.2UH-8.0A

L7660

1 2

X7R

603-1

50V

10%

0.1UF

C7680

1

2

CRITICAL

22UF

POLY-TANT

20% 25V

CASE-D2-SM

C7690

1

2

FDMS9600S

CRITICAL

MLP

Q7660

2349

1

8

56

7

10

SM

PLACEMENT_NOTE=Place XW7665 next to L7660

XW7665

1

2

200

MF-LF

402

1%

1/16W

R7601

1 2

SM

XW7600

1 2

MF-LF 402

1% 1/16W

8.87K

R7685

1

2

24 40 62 64 66 67

67

CRITICAL

QFN

TPS51117RGY_QFN14

U7600

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

2.2UF

10%

603

16V X5R

C7601

1

2

1/16W

1%

402

MF-LF

226K

R7679

1

2

1UF

10% 10V X5R 402-1

C7600

1

2

SYNC_DATE=(12/05/2008)

SYNC_MASTER=(K19_MLB)

A

051-7903

8365

CPU VTT Power Supply

PP1V05_S0

SWITCH_NODE=TRUE

CPUVTTS0_LL

MIN_NECK_WIDTH=0.2MM

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM

DIDT=TRUE

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

CPUVTTS0_DRVH

MIN_LINE_WIDTH=0.6MM

CPUVTTS0_DRVL

DIDT=TRUE

MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

GATE_NODE=TRUE

CPUVTTS0_VSNS

PPBUS_CPU_IMVP_ISNS

CPUVTTS0_VFB

ALL_SYS_PWRGD

CPUVTTS0_TRIP

MIN_NECK_WIDTH=0.2MM

CPUVTTS0_VBST

MIN_LINE_WIDTH=0.6MM

MIN_NECK_WIDTH=0.2 mm

PP5V_S0_CPUVTTS0_V5FILT

VOLTAGE=5V

MIN_LINE_WIDTH=0.6 mm

CPUVTTS0_EN

PP5V_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_CPUVTTS0_SGND

VOLTAGE=0V

CPUVTTS0_TON

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 66 67

7

45 61

6 7

37 42 47 49 61 64 67 68

70 72

VI

SW

EN

FB

GND

IN

VIN

LX

VFB

RSI

EN

POR

SKIP

GND

THRM_PAD

SS

IN0 IN1

THRML_PAD

EN FB

BIAS

OUT0 OUT1

GND

PG

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 1.05V

<Rb>

1.05V S0 PLL LDO

1.8V S0 SWITCHER

MAX CURRENT = 0.5A

Vout = 1.05V

MCP 1.05V S5 (AUXC) SUPPLY

<Ra>

MAX CURRENT = 0.8A

<Rb>

FREQ = 1.6MHZ

MAX CURRENT = 200MA

VOUT = 0.8V * (1 + RA / RB)

<Ra>

PCAA031B-SM

CRITICAL

10UH-0.55A-330MOHM

L7760

1 2

X5R

10uF

603

20%

6.3V

C7762

1

2

603

X5R

10uF

20%

6.3V

C7760

1

2

TPS62202

SOT23-5

CRITICAL

U7760

3

4

2

5

1

CERM 805

22UF

20%

6.3V

CRITICAL

C7771

1

2

6.3V

20%

22UF

805

CERM

CRITICAL

C7750

1

2

255K

402

MF-LF

1/16W

1%

R7780

1

2

MF-LF 402

1/16W

1%

806K

R7781

1

2

50V 402

5%

CERM

47PF

C7776

1

2

CRITICAL

IHLP1616BZ-SM

1V05S5_SW

2.2UH-3.25A

L7770

1 2

67

ISL8009B

DFN

CRITICAL

U7750

2

7

8

3

54

9

6

1

0.0022UF

CERM

10%

402

50V

LDO_YES

C7743

1

2

TPS74701

SON

LDO_YES

CRITICAL

U7740

4

5 8

6

1 2

9 10

37

11

402

4.42K

1% 1/16W MF-LF

LDO_YES

R7747

1

2

6.3V 402

10%

1UF

CERM

LDO_YES

C7741

1

2

100

5% 1/16W MF-LF

LDO_YES

402

R7743

1 2

6.3V 402

CERM

10%

1UF

LDO_YES

C7740

1

2

402

1% 1/16W MF-LF

LDO_YES

1.37K

R7746

1

2

4.7UF

X5R

20% 4V

LDO_YES

402

C7742

1

2

LDO_YES

5%

402

MF-LF

1/16W

0

R7744

1 2

MF-LF

0

5%

1/16W

402

LDO_NO

R7745

1 2

0

1/16W MF-LF

402

5%

LDO_YES

R7748

1 2

A

051-7903

66 83

SYNC_MASTER=K24_MLB

SYNC_DATE=02/25/2009

MISC POWER SUPPLIES

DIDT=TRUE

P1V8S0_SW

1V05S5_FB

PP1V8_S0

P1V8S0_EN

PP3V3_S5

P1V05_S5_PGOOD

PM_G2_P1V05S5_EN

PP3V3_S0

PP1V5_S0

P1V05S0_LDO_SS

PP3V3_S0

PP1V05_S0_MCP_PLL_UF

PP1V05_S0

P1V05S0_LDO_FB

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

DIDT=TRUE

PP1V05_S0_MCP_PLL_UF_LDO

PP3V3_S0_MCP_PLL_VLDO_BIAS

ALL_SYS_PWRGD

PP1V05S0_PGOOD

PP1V05_S5

6 7

17 23 53 67

6 7

17 19 21 22 24 28 32 35

36 42 52 62 67 68 69 71 82

67

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

6 7

10 11 15 22 37 67 68 82

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 72 82

7

22

6 7 9

10 11 12 13 16 17 19

21 22 23 35 61 65 67

24 40 62 64 65 67

6 7

21 22 32

OUT

D

G S

D

G S

OUT

SENSE

CT

VDD

GND

RESET*

MR*

IN

OUT

VDD

MR*

RST*V4MON

V3MON

V2MON

GND

THRM_PAD

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.3V 1.05V AND 1.5V S0 RAILS MONITOR CIRCUIT

PM_SLP_S4_L

Power Control Signals

3.3V_S0, 1.8V_S0 ENABLE

Soft-Off (S5)

Battery Off (G3Hot)

1

353S2310

State

0 0

1 0

0

Unused PGOOD signal

VOLTAGE MONITOR

Sleep (S3)

Run (S0)

1

PM_SLP_S3_L

0

1

SMC_PM_G2_ENABLE

1.5V S0 AND 1.05V S0 ENABLE

MCPDDR, CPUVTT,MCPCORES0 ENABLE

(S0PGOOD_PWROK)

(PM_SLP_S3_L)

S3 ENABLE

3.3V 1.05V S5 ENABLE

(PM_S4_STATE_L)

TPS3808 MR* HAS INTERNAL PULLUP

NC

V2MON THRESHOLD IS 2.866V

V3MON THRESHOLD IS 0.6V V4MON THRESHOLD IS 0.6V

OTHER S0 RAILS PGOOD

62 67

SSM3K15FV

SOD-VESM-HF

Q7813

3

1

2

SSM3K15FV

SOD-VESM-HF

Q7800

3

1

2

MF-LF

402

5%

100K

1/16W

R7802

12

24 40 62 64 65 66 67

5%

MF-LF

68K

402

1/16W

R7813

12

NO STUFF

10V

402

0.068UF

CERM

10%

C7813

1

2

0.068UF

402

10V CERM

NO STUFF

10%

C7802

1

2

5.1K

MF-LF

5%

402

1/16W

R7801

12

66 67

1/16W MF-LF

5%

402

0

R7812

1 2

CERM-X5R

6.3V

402

0.47UF

10%

NO STUFF

C7812

1 2

MF-LF

5%

100K

402

1/16W

R7840

1

2

SOT23-6

TPS3808G33DBVRG4

U7840

4

2

3

15

6

402

20%

CERM

10V

0.1uF

C7840

1

2

402

50V

CERM

20%

0.001UF

C7841

1

2

402

6.3V

10%

0.47UF

CERM-X5R

C7801

1

2

24 40 62 64 65 66 67

0.1uF

10V

20%

CERM

402

C7870

1

2

62 67

63 67

MF-LF

1/16W

5%

402

100

R7859

12

67 68

ISL88042IRTEZ

TDFN

U7870

4

1

8

9

3 5 6

2

7

5.1K

5% 1/16W MF-LF

402

R7884

1 2

6.3V

402

10%

CERM-X5R

0.47UF

C7884

1

2

67 68

1%

MF-LF

402

1/16W

10K

R7870

1

2

1%

20.0K

MF-LF

1/16W

402

R7871

1

2

24 40 62 64 65 66 67

44 67 68

100K

1/16W

402

MF-LF

5%

R7800

1

2

6 8

40 62

6

20 38 40 41

402

5.1K

5%

MF-LF

1/16W

R7811

1 2

6.3V

10%

0.47UF

402

CERM-X5R

C7810

1 2

63 67

44 67 68

MF-LF

402

100K

1/16W

5%

R7810

1

2

66 67

10K

5%

1/16W MF-LF

402

R7883

1

2

5%

1/16W MF-LF

0

402

R7882

1

2

1/16W

5%

MF-LF

402

33K

R7881

1

2

22K

MF-LF

1/16W

5%

402

R7880

1

2

402

CERM-X5R

10%

6.3V

0.47UF

C7883

1

2

6.3V

NO STUFF

0.47UF

CERM-X5R

10%

402

C7882

1

2

402

6.3V

10%

0.47UF

CERM-X5R

C7881

1

2

402

0.47UF

CERM-X5R

6.3V

10%

C7880

1

2

65 67

6

20 32 35 40 71

402

100K

MF-LF

5%

1/16W

R7879

1

2

64 67

10K

1/16W

402

5%

MF-LF

R7820

1

2

24 40 62 64 65 66 67

67 68

SYNC_DATE=02/05/2009

SYNC_MASTER=K24_MLB

POWER SEQUENCING

051-7903

83

A

67

ALL_SYS_PWRGD

PP5V_S0

PM_SLP_S3_L_INVERT

MAKE_BASE=TRUE

PP3V3_S0

MAKE_BASE=TRUE

P3V3S3_EN

RSMRST_PWRGD

TP_DDRREG_PGOOD

PP3V3_S5

CT

PM_G2_P3V3S5_EN_L

MAKE_BASE=TRUE

PM_G2_P3V3S5_EN_L

PM_SLP_S3_L

PM_SLP_S3_L_BUF

MAKE_BASE=TRUE

MCPDDR_EN

PP3V42_G3H

PM_SLP_S3_L_BUF

P1V8S0_EN

MAKE_BASE=TRUE

PM_G2_P1V05S5_EN

CPUVTTS0_EN

MCPDDR_EN

PP3V42_G3H

PM_SLP_S3_L_INVERT

PP3V42_G3H

MAKE_BASE=TRUE

DDRREG_EN

PM_G2_P1V05S5_EN

P3V3S3_EN

MAKE_BASE=TRUE

TP_DDRREG_PGOOD

PP1V05_S0

PP1V5_S0

PP3V3_VMON_VDD

ALL_SYS_PWRGD

PP3V3_S0

ALL_SYS_PWRGD

MCPCORES0_EN

MAKE_BASE=TRUE

P3V3S0_ENP3V3S0_EN

MAKE_BASE=TRUE

P1V8S0_EN

MAKE_BASE=TRUE

SMC_PM_G2_EN

ALL_SYS_PWRGD

MAKE_BASE=TRUE

ALL_SYS_PWRGD

MCPCORES0_EN

CPUVTTS0_EN

MAKE_BASE=TRUE

P1V05_S5_PGOOD

MAKE_BASE=TRUE

PM_SLP_S4_L

24 40 62 64 65 66 67

6 7

37 42 47 49 61 64 65 68 70

72

62 67

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 68 69 71 72 82

67 68

40

63 67

6 7

17 19 21 22 24 28 32 35

36 42 52 62 66 68 69 71 82

62 67

44 67 68

67 68

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

6 7

20 21 24 38 40 41 42 43

45 48 59 60 67

63

67

63 67

6 7 9

10 11 12 13 16 17 19 21

22 23 35 61 65 66

6 7

10 11 15 22 37 66 68 82

6 7

12 17 18 20 21 22 23

26 27 35 37 41 43 45 46 47

49 53 57 58 61 66 67 68

69 71 72 82

64 67

67

68

66 67

65 67

66

IN

D

SG

D

SG

IN

D

G S

D

G S

SGD

IN

D

SG

D

SG

D

S

KELVIN

NC

GND

SENSE

G

OUT

D

G S

IN

S

G

D

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1.7 A (EDP)

Loading

Rds(on)

Type

Part TPCP8102

P-Channel 14 mOhm @4.5V

5.0V S0 FET

NVIDIA RECOMMENDS UNPOWERING DURING SLEEP.

BEFORE RAIL IS TURNED OFF, AND REMAINS LOW

WILL EXIT SELF-REFRESH PREMATURELY.

LOW THROUGH VTT TERMINATION RESISTORS.

ON VTT RAIL, WHICH PULLS ALL CKE SIGNALS

UNTIL AFTER RAIL TURNS BACK ON OR DIMMS

MEM_VTT_EN OUTPUT FROM MCP79 USED TO ENABLE CLAMP

.

5.0V S0 FET

26 MOHM @4.5V

P-TYPE

FDC606P

1.431 A (EDP)

3.3V S0 FET

RDS(ON)

MOSFET

CHANNEL

LOADING

3.3V S0 FET

1.5V S0 FET

Rome SenseFET

6.3 mOHM @4.5V VGS

5A (EDP)

N-TYPE

LOADING

MOSFET

RDS(ON)

CHANNEL

1.5V S0 FET

(1.5V S0 FET FOR DDR3 MEM, MCP79 AND CPU)

3.3V S3 FET

.

0.182 A (EDP)

48 mOhm @4.5V

P-TYPE

FDC638P

3.3V S3 FET

RDS(ON)

CHANNEL

MOSFET

LOADING

CKT FROM T18

81mW max power

90mA max load @ 0.9V

IN ORDER TO SUPPORT UNPOWERING RAIL, HARDWARE MUST GUARANTEE MEM_CKE SIGNALS ARE LOW

MCP79 DDRVTT FET

MCP79 DDR PAD LEAKAGE IS HIGH ENOUGH THAT

376S0778

CRITICAL

FDC638P_G

SM

Q7910

1

2

5

6

3

4

402

10%

X5R

16V

0.033UF

C7911

1

2

402

1/16W

5%

47K

MF-LF

R7910

1 2

402

10K

1/16W MF-LF

5%

R7912

1

2

0.01UF

402

CERM

16V

10%

C7930

1 2

0.033UF

10%

402

X5R

16V

C7931

1

2

1/16W MF-LF

402

47K

5%

R7930

1 2

402

100K

MF-LF

1/16W

5%

R7932

1

2

67

SOT563

SSM6N15FEAPE

Q7975

6

2

1

CERM

50V

20%

402

0.001UF

NO STUFF

C7976

1

2

1/10W

5%

10

603

MF-LF

R7975

12

5%

1/16W

402

MF-LF

100K

R7976

1

2

SOT563

SSM6N15FEAPE

Q7975

3

5

4

8

24 63

SOD-VESM-HF

SSM3K15FV

Q7903

3

1

2

SOD-VESM-HF

SSM3K15FV

Q7905

3

1

2

FDC606P_G

SOT-6

CRITICAL

Q7930

1 2 5 6

3

4

67

SOT563

SSM6N15FEAPE

Q7971

3

5

4

MF-LF

1/16W

5%

47K

402

R7971

1 2

SOT563

SSM6N15FEAPE

Q7971

6

2

1

10% 10V

0.068UF

402

CERM

C7903

1

2

402

MF-LF

100K

5%

1/16W

R7903

1

2

5%

10K

402

1/16W MF-LF

R7901

1 2

0.1UF

10V

20%

402

CERM

C7902

1

2

CRITICAL

ROME

DFN

Q7901

9

4

5

6

8

1 2 37

45 45

10% 16V

0.01UF

CERM

402

C7940

1 2

402

X5R

16V

10%

0.033UF

C7941

1

2

16V

CERM

10%

0.01UF

402

C7910

1 2

47K

402

1/16W

5%

MF-LF

R7940

1 2

47K

1/16W MF-LF

402

5%

R7942

1

2

SSM3K15FV

SOD-VESM-HF

Q7945

3

1

2

44 67

CRITICAL

TPCP8102

23V1K-SM

Q7940

5 6 7 8

4

1 2 3

POWER FETS

A

8368

051-7903

SYNC_DATE=03/12/2009

SYNC_MASTER=K24_MLB

P5V0S0_SS

PP5V_S3

P5V0S0_EN_L

P3V3S3_EN

MEM_VTT_EN

PP0V75_S0_DDRVTT

VTTCLAMP_L

VTTCLAMP_EN

PP5V_S3

P3V3S3_EN_L

P3V3S3_SS

PP3V3_S3

PP3V3_S5

MCPDDR_EN

MCPDDR_EN_L

P1V5_S0_KELVIN

PP1V5_S3

PP1V5_S0

MCPDDR_EN_L_RC

PP5V_S3

MCPDDR_SS

P1V5_S0_SENSE

P3V3S0_EN

P3V3S0_SS

PP3V3_S0

P3V3S0_EN_L

PM_SLP_S3_L_BUF

PP3V3_S5

PP5V_S0

6 7 8

29 37 38

39 41 49 51 53 62 63 68

6 7

26 27 63

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7

20 25 29 30 43 48 50

6 7

17 19 21

22 24 28 32 35

36 42 52 62 66

67 68 69 71 82

6 7

26 27 28 63

6 7

10 11 15 22 37 66 67 82

6 7 8

29 37 38 39 41 49 51 53

62 63 68

6 7

12 17 18 20 21 22 23 26 27

35 37 41 43 45 46 47 49 53 57

58 61 66 67 69 71 72 82

6 7

17 19 21

22 24 28 32 35

36 42 52 62 66

67 68 69 71 82

6 7

37

42 47

49 61 64 65 67 70 72

IN

SYM_VER-1

NC

GND

THRM

ON

VIN_1

VIN_2

VOUT_1

VOUT_2

PAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Place close to the connector

LCD (LVDS) INTERFACE

518S0651

Panel has 2K pull-ups

no-panel case (development).

100K pull-ups are for

Place close to the connector

0.001UF

50V

10%

402

X7R

C9010

1

2

16V

10% 402

X5R

0.1UF

C9001

1

2

CRITICAL

FERR-250-OHM

SM

L9000

1 2

10K

402

5% 1/16W MF-LF

R9094

1

2

402

1/16W

5% MF-LF

100K

R9011

1

2

100K

1/16W

5%

402

MF-LF

R9010

1

2

8

17

DLP11S

CRITICAL

90-OHM-100MA

L9010

1 2

34

CRITICAL

DLP11S

90-OHM-100MA

L9011

1 2

34

F-RT-SM

20474-040E-11

CRITICAL

J9000

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30 31 32 33 34 35 36 37 38 39

4

40

41 42

43 44

5 6 7 8 9

50V

10% 402

X7R

0.001UF

C9002

1

2

10%

402

16V X5R

0.1UF

C9009

1

2

CRITICAL

MFET-2X2

FPF1009

U9000

617

2

3

4

5

402

16V

10%

0.1UF

X5R

C9011

1

2

603

X5R

6.3V

20%

10UF

C9012

1

2

LVDS Display Connector

SYNC_DATE=02/05/2009

SYNC_MASTER=K19_MLB

69 83

A

051-7903

LCD_PWR_EN

PP3V3_S5

PP3V3_SW_LCD_UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_SW_LCD

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_S0

LVDS_CONN_A_CLK_F_N

LVDS_DDC_DATA

LVDS_DDC_CLK

LED_RETURN_1

LED_RETURN_2

LED_RETURN_3

LED_RETURN_4

LED_RETURN_5

LED_RETURN_6

LVDS_CONN_B_CLK_F_P

LVDS_CONN_A_DATA_P<0>

LVDS_CONN_A_DATA_P<1>

LVDS_CONN_A_DATA_N<2>

LVDS_CONN_A_CLK_F_P

LVDS_CONN_B_DATA_P<0>

LVDS_CONN_B_DATA_P<1>

LVDS_CONN_A_DATA_N<1>

LVDS_CONN_A_DATA_P<2>

LVDS_CONN_B_DATA_N<0>

LVDS_CONN_A_DATA_N<0>

LVDS_CONN_B_DATA_P<2>

LVDS_CONN_B_DATA_N<2>

LVDS_CONN_B_DATA_N<1>

PPVOUT_S0_LCDBKLT

LVDS_CONN_A_CLK_P

LVDS_CONN_B_CLK_P

LVDS_CONN_B_CLK_N

LVDS_CONN_A_CLK_N

LVDS_CONN_B_CLK_F_N

6 7

17 19 21 22 24 28 32 35

36 42 52 62 66 67 68 71 82

6

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 71 72 82

6

82

6 8

17

6 8

17

6

72 74

6

72 74

6

72 74

6

72 74

6

72 74

6

72 74

6

82

6 8

6

82

6 8

6

51 72 74

8

17 77

8

17 77

8

17 77

8

17 77

6

82

D

SG

D

GS

BI

D

S G

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AUX CH has 100K pull up/down on the MLB)..

Display Port Interoperability spec says that sources

external adapter for pull ups on DDC lines (since DP

or sinks which do both DP and DVI must depend on the

SSM6N15FEAPE

SOT563

SIGNAL_MODEL=DP_AUXCH_FET

Q9300

6

2

1

1/16W

402

MF-LF

5%

33

R9301

1 2

MF-LF

402

33

5%

1/16W

R9300

1 2

402

16V

10% X5R

0.1UF

C9300

1 2

SOD-VESM-HF

SSM3K15FV

Q9301

3

1

2

17 70

17 77

71 82

SOT563

SSM6N15FEAPE

SIGNAL_MODEL=DP_AUXCH_FET

Q9300

3

5

4

71

17

0.1UF

X5R

16V

10%

402

C9301

1 2

100K

402

MF-LF

1/16W

5%

R9302

1

2

1K

5%

MF-LF

402

1/16W

R9306

1

2

SYNC_DATE=12/19/2008

SYNC_MASTER=K24_MLB

051-7903

A

70 83

DISPLAYPORT SUPPORT

PP5V_S0

DP_IG_CA_DET

DP_CA_DET

DDC_CA_DET_LS5V_L

MAKE_BASE=TRUE

DP_IG_DDC_DATA

MAKE_BASE=TRUE

DP_IG_DDC_CLK

DP_IG_DDC_DATA

DP_ML_N<1>

MAKE_BASE=TRUE

DP_ML_P<0>

MAKE_BASE=TRUE

=MCP_HDMI_TXC_N

MAKE_BASE=TRUE

DP_ML_P<3> DP_ML_N<3>

MAKE_BASE=TRUE

=MCP_HDMI_TXD_N<1> DP_ML_P<0> DP_ML_N<0> DP_ML_N<0>

MAKE_BASE=TRUE

DP_ML_P<1>

MAKE_BASE=TRUE

DP_ML_N<2>

MAKE_BASE=TRUE

DP_ML_P<2>

MAKE_BASE=TRUE

DP_HPD

MAKE_BASE=TRUE

DP_HPD

DP_IG_DDC_CLK

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXC_P

DP_AUX_CH_C_P

DP_AUX_CH_SW_P

DP_IG_AUX_CH_P

DP_AUX_CH_SW_N

DP_AUX_CH_C_N

DP_IG_DDC_CLK

DP_IG_AUX_CH_N

DP_IG_DDC_DATA

6 7

37 42 47 49 61 64

65 67 68 72

17 70

71 82

17 70 71 82

17

71 82

17

17 70 71 82

17 70 71 82 17 70 71 82

71 82

17 70 71 17 70 71

17 70

17

82

BI

IN

IO NC NC

IO

GND

OUT

IO NC NC

IO

GND

ML_LANE0N

ML_LANE0P

ML_LANE1P

GND

ML_LANE1N

GND

DP_PWR

ML_LANE2P

AUX_CHP

RETURN

HOT_PLUG_DETECT

AUX_CHN

ML_LANE3P ML_LANE3N

ML_LANE2N

CONFIG1 CONFIG2

BOT ROW TOP ROW

TH PINS SM PINS

SHIELD PINS

IO NC NC

IO

GND

IO NC NC

IO

GND

IN

G

D

S

G

D

S

SYM_VER-2

OUT

G

D

S

G

D

S

BI

IN

OC*

OUT

EN

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(CA) has 100k

DP to DVI/HDMI Cable Adapter

pull-up to DP_PWR.

Q9440 must have Drain to Gate leakage of <500nA and Gate to Source resistance of >5MOhm

to 100K (DPv1.1a).

greater than or equal

down HPD input with

DP Source must pull

Port Power Switch

70 82

100K

MF-LF

402

5%

1/16W

R9421

1

2

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

D9411

3

2 1 9 10

0.1uF

X5R 40210% 16V

C9415

1 2

0.1uF

X5R 40210% 16V

C9414

1 2

70

0.1uF

X5R 40210% 16V

C9411

1 2

0.1uF

X5R 40210% 16V

C9410

1 2

100K

MF-LF

402

5%

1/16W

R9420

1

2

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

D9410

3

2 1 9 10

DP_ESD

CRITICAL

RCLAMP0504F

SC70-6-1

D9400

1

3

4

6

2 5

CRITICAL

DSPLYPRT-M97-1

F-RT-THSM

J9400

18

16

4 6

20

1

78

1314

2

2122

5

3

11

9

17

15

12

10

19

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

D9411

3

5 4 6 7

1M

MF-LF 402

5% 1/16W

R9425

1

2

DP_ESD

CRITICAL

RCLAMP0524P

SLP2510P8

D9410

3

5 4 6 7

0.1uF

X5R 40210% 16V

C9417

1 2

0.1uF

X5R 40210% 16V

C9416

1 2

0.1uF

X5R 40210% 16V

C9413

1 2

0.1uF

X5R 40210% 16V

C9412

1 2

70 82

0.01UF

CERM 603

20% 50V

C9400

1

2

FERR-120-OHM-3A

0603

L9400

1 2

17 70 82

2N7002DW-X-G

SOT-363

Q9440

3

5

4

2N7002DW-X-G

SOT-363

Q9440

6

2

1

100K

MF-LF

402

5%

1/16W

R9443

1

2

100K

MF-LF

402

5%

1/16W

R9442

1

2

12-OHM-100MA

TCM1210-4SM

FL9403

1

23

4

12-OHM-100MA

TCM1210-4SM

FL9402

1

2 3

4

12-OHM-100MA

TCM1210-4SM

FL9401

1

2 3

4

12-OHM-100MA

TCM1210-4SM

FL9400

1

2 3

4

NO STUFF

0

MF-LF

4025%

1/16W

R9403

1 2

NO STUFF

0

MF-LF

4025%

1/16W

R9413

1 2

NO STUFF

0

MF-LF

4025%

1/16W

R9402

1 2

NO STUFF

0

MF-LF

4025%

1/16W

R9432

1 2

NO STUFF

0

MF-LF

4025%

1/16W

R9401

1 2

NO STUFF

0

MF-LF

4025%

1/16W

R9431

1 2

NO STUFF

0

MF-LF

4025%

1/16W

R9400

1 2

NO STUFF

0

MF-LF

4025%

1/16W

R9430

1 2

17 70

2N7002DW-X-G

SOT-363

Q9441

6

2

1

2N7002DW-X-G

SOT-363

Q9441

3

5

4

1M

MF-LF

402

5%

1/16W

R9422

1

2

10K

MF-LF

402

5%

1/16W

R9445

1

2

10K

MF-LF

402

5%

1/16W

R9444

1

2

100K

MF-LF

402

5%

1/16W

R9423

1

2

70 82

6

20 32 35 40 67

10UF

X5R 603

20%

6.3V

C9480

1

2

0.1UF

CERM 402

20% 10V

C9481

1

2

CRITICAL

22UF

X5R-CERM 603

20%

6.3V

C9486

1

2

CRITICAL

TPS2051B

SOT23

U9480

4

2

5

3

1

0.1UF

CERM

402

20% 10V

C9485

1

2

71 83

A

051-7903

SYNC_DATE=02/05/2009

SYNC_MASTER=K19_MLB

DisplayPort Connector

DP_ML_CONN_N<2>

DP_ML_CONN_N<1>

DP_ML_CONN_P<1>

DP_ML_CONN_P<0> DP_ML_CONN_N<0>

PP3V3_S0_DPILIM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

DP_AUX_CH_C_N

DP_ML_CONN_P<3>

DP_AUX_CH_C_P

PP3V3_S5

PM_SLP_S3_L

TP_DPPWR_OC_L

DP_HPD

DP_HPD_L_Q

PP3V3_S0

DP_ML_C_P<0>

DP_ML_C_N<1>

DP_ML_C_P<2>

DP_ML_C_N<2>

DP_ML_C_P<3>

DP_ML_C_N<3>

DP_ML_P<3>

DP_ML_N<2>

DP_ML_P<2>

DP_ML_N<1>

DP_ML_P<1>

DP_ML_N<0>

DP_ML_P<0>

DP_CA_DET_L_Q

DP_CA_DET

DP_ML_N<3> DP_ML_CONN_N<3>

DP_ML_CONN_P<2>

PP3V3_S0

DP_ML_C_N<0>

DP_ML_C_P<1>

DP_HPD_Q

PP3V3_S0_DPPWR

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.38 MM MIN_NECK_WIDTH=0.20 MM

DP_CA_DET_Q

HDMI_CEC

82

6 7

17 19 21 22 24 28 32

35 36 42 52 62 66 67 68 69

82

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46

47 49 53 57 58 61 66

67 68 69 71 72 82

6

82

6

82

82 82

82

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47

49 53 57 58 61 66 67 68

69 71 72 82

82

6

82

OUT

NC

ALSI

ALSO

ADR

IF_SEL

PWM

EN

FAULT

THRM

GND_L

GND_SW

OUT6

VIN

VDDIO VLDO

FB

SW

OUT1

OUT2

OUT4

OUT5

OUT7

OUT3SCLK

SDA

GND_S

PAD

NC

IN

OUT

G

S

D

S

G

N-CHN

P-CHN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

R9704 SHOULD BE 47K IF RC FILTER IS USED

IF_SEL=1 FOR SMBUS

*PPVOUT_S0_LCDBKLT_SW SHOULD BE KEPT AS SHORT AS POSSIBLE.

* LVDS_IG_BKL_PWM SHOULD BE AWAY FROM BOOST CIRCUIT

*L9701, D9701, C9796, C9797, C9799, C9712 AND C9713 SHOULD ALL BE PLACED NEAR EACHOTHER.

PLACE XW9700 CLOSE TO C9712 AND C9713

402

1/16W

5%

0

MF-LF

R9757

1 2

25V

10% X5R

CRITICAL

10UF

805

C9712

1

2

0.1UF

25V 402

10% X5R

C9713

1

2

CRITICAL

IHLP2525CZ-SM

22UH-2.5A

L9701

1 2

50V

10%

220PF

X7R-CERM 402

C9796

1

2

100V

10%

2.2UF

X7R 1210

C9799

1

2

100V

10% 1210

X7R

2.2UF

C9797

1

2

SOD-123

CRITICAL

RB160M-60G

D9701

1 2

1/16W

0.1%

402

10.2

TF

R9722

1 2

1/16W

0.1%

402

TF

10.2

R9721

1 2

402

TF

0.1%

1/16W

10.2

R9720

1 2

6

69 74

6

69 74

402

1/16W

5%

0

MF-LF

R9753

1 2

6

69 74

6

69 74

6

69 74

6

69 74

1/16W

0.1%

TF

402

10.2

R9718

1 2

0.1%

402

TF

10.2

1/16W

R9719

1 2

1/16W

0.1%

402

TF

10.2

R9717

1 2

1%

402

MF-LF

100K

1/16W

R9715

1 2

301K

1/16W MF-LF

1%

402

R9731

1 2

25V

10% 402

X5R

0.1UF

NO STUFF

C9723

1

2

25V

10%

603-1

X5R

1UF

C9710

1

2

X5R 402

10% 16V

0.1UF

C9711

1

2

SM

XW9710

1 2

CRITICAL

LLP

LP8543SQX

OMIT

U9701

20

5

6

4

7

21

15

9

1

3

12

13

14

16

17

18

19

2

10

11

24

25

82322

100K

1/16W

5%

MF-LF

402

R9716

1

2

16V

10%

402

CERM

0.01UF

C9714

1

2

1/16W

5% MF-LF

0

402

NO STUFF

R9703

1

2

1/16W 402

MF-LF

0

5%

R9702

1

2

8

17 73 74

5%

402

MF-LF

0

1/16W

R9704

1 2

5% 402

CERM

33PF

50V

NO STUFF

C9704

1

2

51 82

402

MF-LF

1/16W

5%

100K

NO STUFF

R9714

1

2

402

MF-LF

1/16W

1%

100K

R9735

1 2

MF-LF

5%

1/16W

0

402

R9701

1 2

CRITICAL

SOT-563-HF

NTZD3155C

Q9701

3

6

5

2

4

1

SM

XW9720

1 2

SM

XW9721

1 2

SM

XW9722

1 2

353S2670

U9701

IC,LP8543,WHT LED BKLT,PROD

CRITICAL

1

051-7903

A

83

LCD BACKLIGHT DRIVER

SYNC_DATE=02/10/2009

SYNC_MASTER=K19_MLB

72

BKL_VLDO

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=5V

MIN_LINE_WIDTH=0.4 MM

BKL_ISEN6

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

VOLTAGE=6V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPVIN_BKL

PP3V3_S0

BKL_SGND

BKL_ISEN5

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_SCL

TP_BKL_FAULT

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_ISEN3

PPBUS_S0_LCDBKLT_PWR

ISNS_LCDBKLT_N

ISNS_LCDBKLT_P

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_3

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

BKL_VLDO_EN_L

BKLT_EN_R

LCD_BKLT_PWM

PPBUS_S0_LCDBKLT_PWR

SMBUS_MCP_1_DATA

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_4

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_1

BKLT_EN

PPVIN_BKL_R

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP5V_S0

BKL_IF_SEL

SMBUS_MCP_1_CLK

BKL_ISEN2

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

VOLTAGE=50V

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM

SWITCH_NODE=TRUE

PPBUS_S0_LCDBKLT_PWR_SW

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=50V

PPVOUT_S0_LCDBKLT

BKL_SDA

LVDS_BKL_PWM_RC

BKLT_EN

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_ISEN1

6

74

6 7

12 17 18 20 21 22 23 26

27 35 37 41 43 45 46 47 49 53

57 58 61 66 67 68 69 71 82

6

72 73

20 43 58 78

72

6 7

37 42 47 49 61 64 65 67 68

70

20 43 58 78

6

51 69 74

72

6

OUT

IN

D

SG

D

SG

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LOADING 0.4 A (EDP)

43 mOhm @4.5V

P-TYPE

FDC638APZ

RDS(ON)

.

MOSFET

CHANNEL

PPBUS S0 LCDBkLT FET

MCP HAS INTERNAL 10K PULL-UP FOR THESE SIGNALS

0402-HF

2AMP-32V

F9800

1 2

72

402

1%

301K

MF-LF

1/16W

R9808

1

2

402

1/16W MF-LF

1%

147K

R9809

1

2

402

0.1UF

X5R

10% 16V

C9802

1

2

6 7

35 44 45 59 60 62 63 64

SSOT6-HF

FDC638APZ_SBMS001

CRITICAL

Q9806

1 2 5 6

3

4

402

1K

1/16W MF-LF

5%

R9841

1

2

402

MF-LF

1/16W

5%

1K

R9840

1

2

24

SSM6N15FEAPE

SOT563

Q9807

6

2

1

SOT563

SSM6N15FEAPE

Q9807

3

5

4

8

17 73

051-7903

A

8373

SYNC_DATE=03/16/2009

SYNC_MASTER=K24_MLB

LCD Backlight Support

LVDS_BKL_ON

PPBUS_G3H

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

BKLT_EN_L

BKLT_PLT_RST_L

PPBUS_S0_LCDBKLT_PWR

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

LCD_BKLT_PWM

PPBUS_S0_LCDBKLT_FUSED

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_S0_LCDBKLT_EN_DIV

PPBUS_S0_LCDBKLT_EN_L

8

17 73

8

17 72 74

IN

VIN

VDC2

VDC1

EN

WAKE

PWM

COMP

OVP

VOUT

SWB

SWA

FAIL

THRM

PGNDB

PGNDA

GND

ISET

CH1

CH2

CH3

CH4

CH5

CH6

PAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

<Rb>

OVP = Vovp * (1 + Ra/Rb)

(SGND)

(C9921-C9926)

PLACEMENT_NOTEs:

Actual: ISET = 23mA, OVP = 35.2V

Target: ISET = 23mA, OVP = 40V Actual: ISET = 23mA, OVP = 40.5V

WF: Need 6.80K 0.1% resistor?

Actual: ISET = 22.47mA, OVP = 49.8V

Target: ISET = 22.5mA, OVP = 50V

Target: ISET = 23mA, OVP = 35V

Vovp = 6.5V +/- 0.35V

(PGND)

f = 600kHz

WF: C9911 and C9917 not in ref schematic.

WF: Need 6.65K 0.1% resistor?

ISET = 153mA / <Riset>

13.3 Inch Panel (9 LEDs per string)

<Riset>

(C9910-C9911)

PLACEMENT_NOTEs:

17 Inch Panel (14 LEDs per string)

15.4 Inch Panel (10/11 LEDs per string)

WF: Need 6.65K 0.1% resistor?

<Ra>

402

50V

5%

Place near U9900

CERM

100PF

NO STUFF

C9922

1

2

CERM

402

50V

Place near U9900

5%

100PF

NO STUFF

C9924

1

2

CERM

50V

100PF

5%

Place near U9900

402

NO STUFF

C9923

1

2

CERM

402

50V

100PF

5%

Place near U9900

NO STUFF

C9926

1

2

402

50V

100PF

5%

Place near U9900

CERM

NO STUFF

C9925

1

2

SM

XW9900

1 2

402

TF

1/16W

0.1%

10.2

R9917

1 2

402

1/16W

TF

10.2

0.1%

R9918

1 2

402

0.1%

10.2

1/16W

TF

R9920

1 2

402

10.2

TF

1/16W

0.1%

R9921

1 2

402

10.2

0.1%

1/16W

TF

R9922

1 2

402

TF

10.2

0.1%

1/16W

R9919

1 2

NO STUFF

805

MF-LF

1/8W

5%

0

R9901

1 2

0

5% 1/16W MF-LF

402

NO STUFF

R9902

1

2

5% MF-LF

402

1/16W

BKLT_FS

10

LCDBKLT_VIN

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

R9930

1

2

IHLP2020BZ11-SM

CRITICAL

10UH-2.1A

BKLT_FS

L9910

1 2

BKLT_FS

2.2UF

X7R

100V

10%

1210

C9915

1

2

2.2UF

1210

X7R

100V

10%

BKLT_FS

C9916

1

2

NO STUFF

SOD-123

RB160M-60G

CRITICAL

PLACEMENT_NOTE=Place near L9910

D9910

1 2

6

69 72

6

69 72

6

69 72

6

69 72

6

69 72

6

69 72

Place near L9910 & pin1 of U9900

10% X5R

805

CRITICAL

25V

10UF

BKLT_FS

C9910

1

2

402

20%

2.2UF

X5R-CERM

10V

BKLT_FS

C9900

1

2

402

10V X5R-CERM

20%

2.2UF

BKLT_FS

C9901

1

2

OMIT

NONE

402

NONE

NOSTUFF

R9916

1

2

1%

1/16W

BKLT_FS

1M

MF-LF

402

R9915

1

2

X5R 402

25V

BKLT_FS

0.1UF

10%

C9911

1

2

OMIT

NOSTUFF

NONE NONE

402

NONE

R9910

1

2

56PF

50V

CERM

5%

BKLT_FS

402

C9906

1

2

6.8K

5% 1/16W MF-LF

402

BKLT_FS

R9905

1

2

8

17 72 73

0.0022UF

50V

10%

BKLT_FS

CERM 402

C9905

1

2

200PF

1206

CERM

100V

5%

BKLT_FS

C9917

1

2

NO STUFF CRITICAL

MC34845

LLP

MIN_LINE_WIDTH=0.5 mm

U9900

7

8

9

10

11

12

17

6

14

131921

15

22

5

2

16

4 3

25

20

23

1

24

18

CERM

50V

5%

Place near U9900

402

100PF

NO STUFF

C9921

1

2

?R9916

RES,MTL FILM,1/16W,226K,1,0402,SMD,LF

1114S0445

LCD_13INCH

?

LCD_15INCH

1114S0298

RES,MTL FILM,1/16W,6.65K,1,0402,SMD,LF

R9910

?1 R9916

LCD_15INCH

114S0438

RES,MTL FILM,1/16W,191K,1,0402,SMD,LF

SYNC_DATE=02/09/2009

SYNC_MASTER=VEMURI_K19I

LCD Backlight Driver (MC34845)

74 83

A

051-7903

R99101

RES,MTL FILM,1/16W,6.65K,1,0402,SMD,LF

114S0298 ?

LCD_13INCH

114S0299

RES,MTL FILM,1/16W,6.81K,1,0402,SMD,LF

LCD_17INCH

1 ?R9910

RES,MTL FILM,1/16W,150K,1,0402,SMD,LF

114S0428

LCD_17INCH

R99161 ?

BKL_MC_CH1

MIN_NECK_WIDTH=0.20 mm

VOLTAGE=50V

MIN_NECK_WIDTH=0.375 MM

MIN_LINE_WIDTH=0.5 MM

PPVOUT_S0_LCDBKLT

LCDBKLT_OVP

GND_LCDBKLT

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

BKL_MC_CH6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_MC_CH5

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_MC_CH4

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

BKL_MC_CH3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

BKL_MC_CH2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LCDBKLT_FAIL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.38 MM VOLTAGE=9V

PPVIN_BKL_U9900

MIN_LINE_WIDTH=0.2 MM

LCDBKLT_COMP

PPVIN_BKL

VOLTAGE=50V SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.38 MM

MIN_LINE_WIDTH=0.5 MM

PPVOUT_S0_LCDBKLT_SW

LCDBKLT_COMP_RC

LCD_BKLT_PWM

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_1

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_6

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.5 mm

LED_RETURN_5

LED_RETURN_4

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_2

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

LED_RETURN_3

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.20 mm

VOLTAGE=5.5V

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.2 MM

PP5V5_S0_LCDBKLT

MIN_LINE_WIDTH=0.2 MM

LCDBKLT_ISET

VOLTAGE=2.5V

PP2V5_S0_LCDBKLT

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

6

51 69 72 72

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Signals within each 1x group should be matched to CPU clock, +0/-1000 mils.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.5

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2.4

CPU Signal Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.5 (#22294), Sections 4.2 & 4.3

Intel Design Guide recommends FSB signals be routed only on internal layers. NOTE: Intel Design Guide allows closer spacing if signal lengths can be shortened.

Design Guide recommends each strobe/signal group is routed on the same layer.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

MCP FSB COMP Signal Constraints

Some signals require 27.4-ohm single-ended impedance.

FSB Clock Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended.

SOURCE: MCP79 Interface DG (DG-03328-001_v01), Section 2.2

SR DG recommends at least 25 mils, >50 mils preferred

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target impedance.

All 4x/2x/1x FSB signals with impedance requirements are 50-ohm single-ended.

Signals within each 2x group should be matched within 20 ps. ADTSB#s should be matched +/- 300 ps.

Spacing is 2x dielectric between DATA#, DINV# signals, with 3x dielectric spacing to the DSTB#s.

PHYSICAL

FSB 2X

FSB 4X Signal Groups

ELECTRICAL_CONSTRAINT_SET

FSB 1X Signals

SPACING

NET_TYPE

Signals

(See above)

(FSB_CPURST_L)

(CPU_VCCSENSE)

CPU / FSB Net Properties

FSB (Front-Side Bus) Constraints

DSTB# complementary pairs should be matched within 1 ps of each other, all DSTB#s matched to +/- 300 ps.

DSTB# complementary pairs are spaced normally and are NOT routed as differential pairs.

FSB 4X signals / groups shown in signal table on right. Signals within each 4x group should be matched within 5 ps of strobe.

FSB 2X signals / groups shown in signal table on right.

Spacing is 1x dielectric between ADDR#, REQ# signals, with 2x dielectric spacing to ADSTB#. FSB 1X signals shown in signal table on right.

FSB_ADSTB

?

*

=2x_DIELECTRIC

=STANDARD

FSB_1X

?

*

=STANDARD

*

FSB_ADDR

?

FSB_DSTB

*

=3x_DIELECTRIC

FSB_DATA

*

?

=2x_DIELECTRIC

FSB_1X

TOP,BOTTOM?=3x_DIELECTRIC

FSB_ADDR

TOP,BOTTOM?=3x_DIELECTRIC

TOP,BOTTOM

FSB_DSTB

?

=5x_DIELECTRIC

TOP,BOTTOM

?

FSB_DATA

=4x_DIELECTRIC

=50_OHM_SE

* =STANDARD

FSB_50S

=50_OHM_SE =50_OHM_SE

=STANDARD

=50_OHM_SE

TOP,BOTTOM

FSB_ADSTB

?

=4x_DIELECTRIC

=50_OHM_SE=50_OHM_SE=50_OHM_SE

=50_OHM_SE

FSB_DSTB_50S

=1:1_DIFFPAIR=1:1_DIFFPAIR

*

75 83

A

051-7903

CPU/FSB Constraints

SYNC_MASTER=T18_MLB

SYNC_DATE=02/05/2009

CPU_AGTL

?

TOP,BOTTOM

=2x_DIELECTRIC

=4x_DIELECTRICCLK_FSB

?

TOP,BOTTOM

* =STANDARD =STANDARD

CPU_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE =50_OHM_SE

=27P4_OHM_SE

=27P4_OHM_SE*

=27P4_OHM_SE =27P4_OHM_SE

7 MIL7 MIL

CPU_27P4S

CPU_AGTL

?

*

=STANDARD

8 MIL

CPU_8MIL

?

*

?

CPU_COMP

*

25 MIL

CPU_ITP

*

?

=2:1_SPACING

25 MIL

CPU_GTLREF

*

?

*

CPU_VCCSENSE

?

25 MIL

=50_OHM_SE

MCP_50S

=50_OHM_SE =50_OHM_SE=50_OHM_SE

* =STANDARD =STANDARD

8 MIL

*

?

MCP_FSB_COMP

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

CLK_FSB_100D

=3x_DIELECTRIC

?

CLK_FSB

*

FSB_DATA

FSB_D_L<15..0>

FSB_50S

FSB_DATA_GROUP0

FSB_DSTB_L_P<0>

FSB_DSTB0

FSB_DSTBFSB_DSTB_50S

FSB_DSTB_L_N<0>

FSB_DSTB

FSB_DSTB0

FSB_DSTB_50S

FSB_DATA

FSB_D_L<31..16>

FSB_DATA_GROUP1

FSB_50S

FSB_DATA

FSB_DINV_L<1>

FSB_DATA_GROUP1

FSB_50S

FSB_DSTB_L_P<1>

FSB_DSTB

FSB_DSTB1

FSB_DSTB_50S

FSB_DATA

FSB_DINV_L<2>

FSB_DATA_GROUP2

FSB_50S

FSB_DSTB2

FSB_DSTB

FSB_DSTB_L_P<2>

FSB_DSTB_50S

FSB_DSTB_L_N<2>

FSB_DSTB2

FSB_DSTBFSB_DSTB_50S

FSB_DATA

FSB_DATA_GROUP3

FSB_D_L<63..48>

FSB_50S

FSB_DATA

FSB_DINV_L<3>

FSB_DATA_GROUP3

FSB_50S

FSB_DSTB3

FSB_DSTB

FSB_DSTB_L_P<3>

FSB_DSTB_50S

FSB_DSTB_L_N<3>

FSB_DSTB3

FSB_DSTBFSB_DSTB_50S

FSB_50S

FSB_A_L<16..3>

FSB_ADDR_GROUP0

FSB_ADDR

FSB_50S

FSB_ADDR

FSB_REQ_L<4..0>

FSB_ADDR_GROUP0

FSB_A_L<35..17>

FSB_ADDR

FSB_ADDR_GROUP1

FSB_50S FSB_50S

FSB_ADSTB

FSB_ADSTB1

FSB_ADSTB_L<1> FSB_ADS_L

FSB_1XFSB_1X

FSB_50S

FSB_1X

FSB_BREQ0_L

FSB_50S

FSB_1X

FSB_BREQ1_L

FSB_50S

FSB_BNR_L

FSB_1XFSB_1X

FSB_50S

FSB_BPRI_L

FSB_1XFSB_1X

FSB_50S

FSB_1X

FSB_DBSY_L

FSB_1X

FSB_50S

FSB_1X

FSB_DEFER_L

FSB_1X

FSB_50S

FSB_1X

FSB_DRDY_L

FSB_1X

FSB_50S

FSB_1X

FSB_HIT_L

FSB_1X

FSB_50S

FSB_HITM_L

FSB_1XFSB_1X

FSB_50S

FSB_1X

FSB_CPURST_L

FSB_50S

FSB_1X

FSB_RS_L<2..0>

FSB_1X

FSB_50S

FSB_1X

FSB_TRDY_L

FSB_1X

FSB_50S

CPU_AGTL

CPU_BSEL<2..0>

CPU_BSEL

CPU_50S

CPU_8MIL

CPU_FERR_L

CPU_50S

CPU_AGTL

CPU_IGNNE_L

CPU_ASYNC

CPU_50S

CPU_AGTL

CPU_INIT_L

CPU_50S

CPU_AGTL

CPU_INTR

CPU_ASYNC_R

CPU_50S

CPU_AGTL

CPU_NMI

CPU_ASYNC_R

CPU_50S

CPU_AGTL

CPU_PROCHOT_L

CPU_50S

CPU_AGTL

CPU_PWRGD

CPU_50S

CPU_AGTL

CPU_SMI_L

CPU_ASYNC

CPU_50S

CPU_AGTL

CPU_STPCLK_L

CPU_ASYNC

CPU_50S

CPU_8MIL

PM_THRMTRIP_L

CPU_50S

CPU_AGTL

FSB_CPUSLP_L

CPU_50S

CPU_AGTL

CPU_DPSLP_L

CPU_FROM_SB

CPU_50S

CPU_AGTL

CPU_DPRSTP_L

CPU_50S

CPU_AGTL

FSB_DPWR_L

CPU_ASYNC

CPU_50S MCP_50S

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP MCP_FSB_COMP

MCP_50S

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP MCP_FSB_COMP

MCP_50S

MCP_CPU_COMP_VCC

MCP_CPU_COMP MCP_FSB_COMP

MCP_50S

MCP_CPU_COMP_GND

MCP_CPU_COMP MCP_FSB_COMP

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_P

FSB_CLK_CPU

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_N

FSB_CLK_CPU

FSB_CLK_ITP_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_ITP

FSB_CLK_ITP_N

CLK_FSB

CLK_FSB_100D

FSB_CLK_ITP

FSB_CLK_MCP_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_MCP

FSB_CLK_MCP_N

CLK_FSB_100D

CLK_FSB

FSB_CLK_MCP

CPU_IERR_L

CPU_50S

CPU_IERR_L

PM_DPRSLPVR

CPU_AGTL

PM_DPRSLPVR

CPU_50S

IMVP_DPRSLPVR

CPU_AGTL

CPU_50S

CPU_GTLREF

CPU_50S

CPU_GTLREF

CPU_COMP

CPU_COMP<3>

CPU_50S

CPU_COMP

CPU_27P4S

CPU_COMP<2>

CPU_COMP

CPU_50S

CPU_COMP<1>

CPU_COMP

CPU_COMP<0>

CPU_27P4S

CPU_COMPCPU_COMP

XDP_TDI

CPU_ITPCPU_50SXDP_TDI

XDP_TDO

CPU_ITPCPU_50SXDP_TDO

XDP_TMS

CPU_ITPCPU_50SXDP_TMS

XDP_TCK

CPU_ITPCPU_50SXDP_TCK

XDP_TRST_L

CPU_ITPCPU_50S

XDP_TRST_L

CPU_ITP

XDP_BPM_L<4..0>

CPU_50S

XDP_BPM_L

XDP_BPM_L<5>

CPU_ITPCPU_50S

XDP_BPM_L5

CPU_50S CPU_ITP

XDP_CPURST_L

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_27P4S

IMVP6_VSEN_N

CPU_VCCSENSE

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S

CPU_8MIL

IMVP6_VID<6..0>

CPU_50S

CPU_8MIL

CPU_50S

CPU_VID<6..0>

FSB_ADSTB0

FSB_ADSTB_L<0>

FSB_50S

FSB_ADSTB

FSB_DSTB1

FSB_DSTBFSB_DSTB_50S

FSB_DSTB_L_N<1> FSB_D_L<47..32>

FSB_DATA_GROUP2

FSB_DATA

FSB_50S

CPU_AGTL

CPU_A20M_L

CPU_ASYNC

CPU_50S

FSB_LOCK_L

FSB_1XFSB_1X

FSB_50S

FSB_DATA

FSB_DINV_L<0>

FSB_50S

FSB_DATA_GROUP0

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

6 9

13

9

13

9

13

9

13

9

13

9

13

9

13

6 9

13

6 9

13

9

12 13

9

13

9

13

8 9

9

13

9

13

9

13

9

13

9

13

9

13 41 61

9

12 13

9

13

9

13

9

13 41

9

13

9

13

9

13 61

9

13

9

13

9

13

12 13

13

9

20 61

61

9

25

9

12

1 9

12

9

12

9

12

9

12

9

12

9

12

10 61

61

8

61

8

10

6 9

13

6 9

13

6 9

13

9

13

6 9

13

6 9

13

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

Memory Net Properties

DQ signals should be matched within 20 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, no inter-pair matching requirement. All DQS pairs should be matched within 100 ps of clocks. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 140 ps. A/BA/cmd signals should be matched within 75 ps, no CLK matching requirement.

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

Memory Bus Constraints

All memory signals maximum length is 1.005 ps. CLK minimum length is 594 ps (lengths include substrate).

Memory Bus Spacing Group Assignments

Need to support MEM_*-style wildcards!

DQ/A/BA/cmd signal spacing is 3x dielectric, DQS/CLK is 4x dielectric.

DQ signals should be matched within 5 ps of associated DQS pair. DQS intra-pair matching should be within 1 ps, inter-pair matching shoulw be within 180 ps No DQS to clock matching requirement. CLK intra-pair matching should be within 1 ps, inter-pair matching should be within 2 ps. A/BA/cmd signals should be matched within 5 ps of CLK pairs.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3.4

MCP MEM COMP Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.3 SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

DDR3:

DDR2:

?

*

8 MIL

MCP_MEM_COMP

=STANDARD=STANDARD*

MCP_MEM_COMP

Y

7 MIL 7 MIL

=STANDARD

*

MEM_DQS2MEM

MEM_DQS MEM_DQS

MEM_DQS

MEM_DQS2MEM

*

MEM_DATA

MEM_CTRL

MEM_CTRL2MEM

*

MEM_CMD

MEM_CTRL2MEM

*

MEM_CTRL

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL

*

MEM_CTRL

MEM_CTRL2CTRL

*

MEM_CLK

MEM_CTRL2MEM

MEM_CTRL

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

*

MEM_CLK2MEM

MEM_CTRL

MEM_CLK

*

MEM_CLK2MEM

MEM_CLKMEM_CLK

**

MEM_DATA

MEM_2OTHER

* *

MEM_CMD

MEM_2OTHER

* *

MEM_DQS

MEM_2OTHER

**

MEM_CTRL

MEM_2OTHER

* *

MEM_CLK

MEM_2OTHER

MEM_CMD

*

MEM_DATA

MEM_DATA2MEM

*

MEM_DATA

MEM_DATA2DATA

MEM_DATA

MEM_DQS

*

MEM_DATA

MEM_DATA2MEM

MEM_CTRL

MEM_DATA2MEM

*

MEM_DATA

MEM_CLK

MEM_DATA

MEM_DATA2MEM

*

MEM_DQS

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

MEM_CMD2MEM

MEM_CMD

*

MEM_CMD2CMD

MEM_CMDMEM_CMD

*

MEM_CTRL

MEM_CMD2MEM

MEM_CMD

*

MEM_CLK

MEM_CMD2MEM

*

MEM_CMD

*

MEM_DQS2MEM

=3:1_SPACING

? ?

*

MEM_2OTHER

25 MIL

?

*

=3:1_SPACINGMEM_DATA2MEM

=3:1_SPACING

?

*

MEM_CMD2MEM

=1.5:1_SPACING

?

*

MEM_DATA2DATA

=2.5:1_SPACING

?

*

MEM_CTRL2MEM

=4:1_SPACING

?

*

MEM_CLK2MEM

?

*

=2:1_SPACING

MEM_CTRL2CTRL

?

*

MEM_CMD2CMD

=1.5:1_SPACING

=40_OHM_SE

=STANDARD* =STANDARD

=40_OHM_SE =40_OHM_SE =40_OHM_SE

MEM_40S_VDD

=40_OHM_SE=40_OHM_SE=40_OHM_SE=40_OHM_SE

=STANDARD* =STANDARD

MEM_40S

MEM_70D_VDD

=70_OHM_DIFF

=70_OHM_DIFF =70_OHM_DIFF

* =70_OHM_DIFF =70_OHM_DIFF

MEM_70D

=70_OHM_DIFF=70_OHM_DIFF*

=70_OHM_DIFF=70_OHM_DIFF

=70_OHM_DIFF

*

MEM_DQS2MEM

MEM_DQS MEM_CMD

MEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

MEM_DQS

MEM_DQS2MEM

*

MEM_CLK

051-7903

A

8376

Memory Constraints

SYNC_MASTER=T18_MLB

SYNC_DATE=02/05/2009

MEM_B_CKE<3..0>

MEM_B_CNTL

MEM_CTRL

MEM_40S_VDD

MEM_70D_VDD

MEM_A_CLK_P<5..0>

MEM_A_CLK

MEM_CLK

MEM_A_CKE<3..0>

MEM_CTRL

MEM_A_CNTL

MEM_40S_VDD

MEM_70D_VDD

MEM_A_CLK_N<5..0>

MEM_A_CLK

MEM_CLK

MEM_CTRL

MEM_A_ODT<3..0>

MEM_A_CNTL

MEM_40S_VDD

MEM_CTRL

MEM_A_CS_L<3..0>

MEM_A_CNTL

MEM_40S_VDD

MEM_A_DM<2>

MEM_DATA

MEM_A_DQ_BYTE2 MEM_40S

MEM_DATA

MEM_A_DM<3>

MEM_A_DQ_BYTE3 MEM_40S

MEM_A_DM<4>

MEM_DATA

MEM_A_DQ_BYTE4 MEM_40S

MEM_A_DM<5>

MEM_DATA

MEM_A_DQ_BYTE5 MEM_40S

MEM_DATA

MEM_A_DM<6>

MEM_A_DQ_BYTE6 MEM_40S

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_DQSMEM_70D

MEM_DATA

MEM_A_DM<1>

MEM_A_DQ_BYTE1 MEM_40S

MEM_A_DQS0

MEM_A_DQS_N<0>

MEM_DQSMEM_70D

MEM_A_DQS1

MEM_A_DQS_N<1>

MEM_DQSMEM_70D

MEM_70D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQS

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_DQSMEM_70D

MEM_70D

MEM_A_DQS2

MEM_A_DQS_N<2>

MEM_DQS

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_DQSMEM_70D

MEM_A_DQS3

MEM_A_DQS_N<3>

MEM_DQSMEM_70D

MEM_A_DQS5

MEM_A_DQS_N<5>

MEM_DQSMEM_70D

MEM_70D

MEM_A_DQS4

MEM_A_DQS_N<4>

MEM_DQS

MEM_70D

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_DQS

MEM_70D

MEM_A_DQS7

MEM_A_DQS_N<7>

MEM_DQS

MEM_A_BA<2..0>

MEM_A_CMD

MEM_CMD

MEM_40S_VDD

MEM_DATA

MEM_A_DM<0>

MEM_A_DQ_BYTE0 MEM_40S

MEM_DATA

MEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_40S

MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_DATA

MEM_40S

MEM_A_CAS_L

MEM_CMD

MEM_A_CMD

MEM_40S_VDD

MEM_DATA

MEM_A_DQ<31..24>

MEM_A_DQ_BYTE3 MEM_40S

MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_40S_VDD

MEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_DATA

MEM_40S

MEM_DATA

MEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_40S

MEM_A_CMD

MEM_A_RAS_L

MEM_CMD

MEM_40S_VDD

MEM_A_DQ<39..32>

MEM_DATA

MEM_A_DQ_BYTE4 MEM_40S

MEM_A_DQ<47..40>

MEM_DATA

MEM_A_DQ_BYTE5 MEM_40S

MEM_B_DQ_BYTE5

MEM_B_DQ<47..40>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE4 MEM_40S

MEM_B_DQ<39..32>

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_40S

MEM_DATA

MEM_B_CMD

MEM_B_WE_L

MEM_CMD

MEM_40S_VDD

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE0

MEM_B_DM<0>

MEM_40S

MEM_DATA

MEM_B_CMD

MEM_B_BA<2..0>

MEM_CMD

MEM_40S_VDD

MEM_B_DQS6

MEM_B_DQS_N<6>

MEM_70D MEM_DQS

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_70D MEM_DQS

MEM_B_DQ_BYTE7

MEM_B_DM<7>

MEM_40S

MEM_DATA

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_70D MEM_DQS

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_70D MEM_DQS

MEM_B_DQS4

MEM_70D

MEM_B_DQS_N<4>

MEM_DQS

MEM_B_DQS5

MEM_B_DQS_N<5>

MEM_70D MEM_DQS

MEM_B_DQS3

MEM_B_DQS_N<3>

MEM_70D MEM_DQS

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_70D MEM_DQS

MEM_B_DQS2

MEM_B_DQS_N<2>

MEM_70D MEM_DQS

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_70D MEM_DQS

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_70D MEM_DQS

MEM_B_DQS1

MEM_B_DQS_N<1>

MEM_70D MEM_DQS

MEM_B_DQS0

MEM_B_DQS_N<0>

MEM_70D MEM_DQS

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_70D MEM_DQS

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_70D MEM_DQS

MEM_B_DQ_BYTE6

MEM_B_DM<6>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DM<5>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DM<3>

MEM_40S

MEM_DATA

MEM_B_DQS7

MEM_B_DQS_N<7>

MEM_70D MEM_DQS

MEM_B_DQ_BYTE4

MEM_B_DM<4>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DM<2>

MEM_40S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DM<1>

MEM_40S

MEM_DATA

MEM_B_ODT<3..0>

MEM_B_CNTL

MEM_CTRL

MEM_40S_VDD

MEM_B_CS_L<3..0>

MEM_B_CNTL

MEM_CTRL

MEM_40S_VDD

MEM_70D_VDD

MEM_CLK

MEM_B_CLK_N<5..0>

MEM_B_CLK

MEM_70D_VDD

MEM_B_CLK_P<5..0>

MEM_CLK

MEM_B_CLK

MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP

MCP_MEM_COMP_VDD

MCP_MEM_COMP MCP_MEM_COMP MCP_MEM_COMP

MCP_MEM_COMP_GND

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_DQSMEM_70D

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_DQSMEM_70D

MEM_B_CMD

MEM_B_CAS_L

MEM_CMD

MEM_40S_VDD

MEM_B_CMD

MEM_B_RAS_L

MEM_CMD

MEM_40S_VDD

MEM_B_CMD

MEM_CMD

MEM_B_A<14..0>

MEM_40S_VDD

MEM_A_CMD

MEM_CMD

MEM_A_A<14..0>

MEM_40S_VDD

MEM_DATA

MEM_A_DM<7>

MEM_A_DQ_BYTE7 MEM_40S

MEM_A_DQS0

MEM_DQSMEM_70D

MEM_A_DQS_P<0>

MEM_70D

MEM_A_DQS6

MEM_A_DQS_N<6>

MEM_DQS

14 27

14 26

14 27

15

14 26

14 27

14 26

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

PCI-Express

PHYSICAL

SPACING

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.4

Analog Video Signal Constraints

R/G/B signals should be matched as close as possible and < 10 inches. SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.1 & 2.5.2.

LVDS intra-pair matching should be 5 mils. Pairs should be within 100 mils of clock length.

Max length of LVDS/DisplayPort/TMDS traces: 12 inches.

DIsplayPort AUX CH intra-pair matching should be 5 ps. No relationship to other signals.

DisplayPort/TMDS intra-pair matching should be 5 ps. Inter-pair matching should be within 150 ps.

- 75-ohm from output of three-pole filter to connector (if possible).

SATA Interface Constraints

- 37.5-ohm from MCP to first termination resistor.

CRT signal single-ended impedence varies by location:

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Sections 2.5.3 & 2.5.4.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.7.1.

- 50-ohm from first to second termination resistor.

Digital Video Signal Constraints

*

Y

20 MIL 20 MIL

=STANDARD

=STANDARD =STANDARD

MCP_DV_COMP

MCP_DAC_COMP

*

?

=2:1_SPACING

CRT_SYNC

?

*

16 MIL

*

?

CRT_2SWITCHER

250 MIL

?

=4x_DIELECTRIC

SATA

*

=3x_DIELECTRIC

*

?

DISPLAYPORT

?

*

LVDS

=3x_DIELECTRIC

CRT_50S

=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE=50_OHM_SE =50_OHM_SE

CRT_2CRT

*

CRTCRT

=100_OHM_DIFF

*

=100_OHM_DIFF

DP_100D

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

LVDS_100D

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

*

?

SATA_TERMP 8 MIL

SATA_100D

=100_OHM_DIFF

=100_OHM_DIFF*=100_OHM_DIFF

=100_OHM_DIFF

SATA

?

TOP,BOTTOM

=3x_DIELECTRIC

=100_OHM_DIFF

*

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFFCLK_PCIE_100D

=100_OHM_DIFF

?

*

CRT_2CLK

50 MIL

TOP,BOTTOM

=4x_DIELECTRIC

?

DISPLAYPORT

?

LVDS

=4x_DIELECTRIC

TOP,BOTTOM

=4:1_SPACING

CRT

*

?

=STANDARD

CRT_2CRT

?

*

?

=3X_DIELECTRIC

PCIE

*

?

MCP_PEX_COMP

8 MIL

*

?

CLK_PCIE

20 MIL

=4X_DIELECTRIC

TOP,BOTTOM

?

PCIE

=90_OHM_DIFF

* =90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

PCIE_90D

MCP Constraints 1

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

051-7903

A

8377

DP_IG_AUX_CH_N

DP_100D

DP_AUX_CH

DISPLAYPORT

DP_100D

DP_ML

DP_IG_ML_N<3..0>

DISPLAYPORT

TMDS_IG_TXD

DP_100D

DISPLAYPORT

TMDS_IG_TXD_P<2..0>

PCIE

NC_PCIE_EXCARD_R2DCN

PCIE_90D

NC_PCIE_EXCARD_R2DCP

PCIE_90D PCIE

PCIE_EXCARD_R2D

PCIE

NC_PCIE_EXCARD_D2RN

PCIE_90D

CLK_PCIE

MCP_PE0_REFCLK

CLK_PCIE_100D

NC_PEG_CLK100MP

CLK_PCIE_100D

NC_PEG_CLK100MN

CLK_PCIE

MCP_IFPAB_RSET

MCP_DV_COMP

MCP_IFPAB_VPROBE

SATA_100D

SATA

SATA_HDD_R2D_C_N

SATA_HDD_R2D_C_P

SATA

SATA_100D

SATA_HDD_R2D

SATA_100D

SATA

SATA_HDD_R2D_N

SATA_HDD_R2D_P

SATA_100D

SATA

SATA_100D

SATA

SATA_HDD_D2R_P

SATA_HDD_D2R

SATA_100D

SATA

SATA_HDD_D2R_C_P

SATA_100D

SATA

SATA_HDD_D2R_N

SATA_100D

SATA

SATA_ODD_R2D_C_P

SATA_ODD_R2D

SATA_100D

SATA

SATA_HDD_D2R_C_N

SATA_100D

SATA

SATA_ODD_R2D_C_N

SATA

SATA_ODD_R2D_N

SATA_100D

SATA

SATA_ODD_R2D_P

SATA_100D

SATA

SATA_ODD_D2R_N

SATA_100D

SATA_ODD_D2R_P

SATA

SATA_100D

SATA_ODD_D2R

SATA

SATA_ODD_D2R_C_P

SATA_100D SATA_100D

SATA

SATA_ODD_D2R_C_N MCP_SATA_TERMP

SATA_TERMP

MCP_SATA_TERMP

DISPLAYPORT

DP_100D

DP_AUX_CH

DP_IG_AUX_CH_P

LVDS_CONN_B_CLK_N

LVDS

LVDS_100D

LVDS_IG_B_CLK

LVDS

LVDS_100D

LVDS_IG_B_DATA3

NC_LVDS_IG_B_DATAP<3>

LVDS

LVDS_100D

LVDS_IG_B_DATA3

NC_LVDS_IG_B_DATAN<3>

LVDS

LVDS_100D

LVDS_IG_A_DATA3

NC_LVDS_IG_A_DATAP<3>

LVDS

LVDS_100D

LVDS_IG_A_DATA3

NC_LVDS_IG_A_DATAN<3>

LVDS_IG_A_DATA

LVDS_100D

LVDS

LVDS_IG_A_DATA_N<2..0>

LVDS_IG_A_DATA

LVDS_100D

LVDS

LVDS_IG_A_DATA_P<2..0>

LVDS_100D

LVDS_IG_B_DATA

LVDS

LVDS_IG_B_DATA_N<2..0>

LVDS

LVDS_100D

LVDS_IG_B_DATA

LVDS_IG_B_DATA_P<2..0>

LVDS_CONN_B_CLK_P

LVDS

LVDS_100D

LVDS_IG_B_CLK

CLK_PCIE_100D

PCIE_CLK100M_MINI_N

CLK_PCIE

PCIEPCIE_90D

PCIE_FW_R2D_C_N

PCIEPCIE_90D

PEG_D2R_C_N<15..0>

MCP_DV_COMP

MCP_HDMI_VPROBE

CRT_SYNC

NC_CRT_IG_HSYNC

CRT_50S

CRT_SYNC

PCIEPCIE_90D

PCIE_MINI_R2D_N PCIE_MINI_R2D_C_P

PCIE

PCIE_MINI_R2D

PCIE_90D

LVDS

LVDS_100D

LVDS_IG_A_CLK

LVDS_CONN_A_CLK_N

MCP_HDMI_RSET

MCP_DV_COMP

MCP_HDMI_RSET

DP_100D

DP_ML

DISPLAYPORT

DP_IG_ML_P<3..0>

TMDS_IG_TXD

TMDS_IG_TXD_N<2..0>

DISPLAYPORT

DP_100D

MCP_DAC_VREF MCP_DAC_COMP

NC_MCP_TV_DAC_VREF

MCP_DAC_RSET MCP_DAC_COMP

NC_MCP_TV_DAC_RSET

CRT_SYNC

CRT_50S

CRT_SYNC

NC_CRT_IG_VSYNC

CRT_50S

CRT

CRT_BLUE

NC_CRT_IG_B_COMP_PB

CRT

NC_CRT_IG_G_Y_Y

CRT_50S

CRT_GREEN

CRT_50S

CRT

NC_CRT_IG_R_C_PR

CRT_RED

PCIE

PCIE_MINI_R2D_C_N

PCIE_90D

PCIE_FW_R2D_P

PCIEPCIE_90D

PCIE_FW_D2R_C_P

PCIEPCIE_90D

PCIE_CLK100M_MINI_P

CLK_PCIE

MCP_PE1_REFCLK

CLK_PCIE_100D

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_FW_P

MCP_PE2_REFCLK

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_FW_N

PCIE

NC_PCIE_EXCARD_D2RP

PCIE_EXCARD_D2R

PCIE_90D

PCIE_FW_D2R_C_N

PCIEPCIE_90D

PCIE_FW_D2R_N

PCIEPCIE_90D

PCIE_FW_D2R

PCIE_FW_D2R_P

PCIEPCIE_90D

PCIE_FW_R2D

PCIE_FW_R2D_C_P

PCIEPCIE_90D

PCIE_FW_R2D_N

PCIEPCIE_90D

PEG_R2D_N<15..0>

PCIEPCIE_90D

PEG_D2R

PCIEPCIE_90D

PEG_D2R_P<15..0>

PCIEPCIE_90D

PEG_D2R_C_P<15..0>

PCIE

PEG_R2D

PCIE_90D

PEG_R2D_C_P<15..0>

PCIEPCIE_90D

PCIE_MINI_R2D_P

PEG_R2D_C_N<15..0>

PCIEPCIE_90D

PCIE

PCIE_MINI_D2R_P

PCIE_MINI_D2R

PCIE_90D

PCIEPCIE_90D

PCIE_MINI_D2R_N

PEG_D2R_N<15..0>

PCIEPCIE_90D

PEG_R2D_P<15..0>

PCIEPCIE_90D

PCIE_EXCARD_R2D_N

PCIE_90D PCIE

PCIEPCIE_90D

PCIE_EXCARD_R2D_P

NC_PCIE_CLK100M_EXCARDP

MCP_PE3_REFCLK

CLK_PCIE_100D

CLK_PCIE

MCP_PEX_CLK_COMP

MCP_PEX_COMP

MCP_PEX_CLK_COMP

TMDS_IG_TXC DISPLAYPORT

DP_100D

TMDS_IG_TXC_N

LVDS

LVDS_100D

LVDS_IG_A_CLK

LVDS_CONN_A_CLK_P

TMDS_IG_TXC

DP_100D

DISPLAYPORT

TMDS_IG_TXC_P

CLK_PCIE_100D

CLK_PCIE

NC_PCIE_CLK100M_EXCARDN

17 70

8

16

8

16

8

16

8

16

8

16

17 23

19 37

6

37

6

37

19 37

6

37

19 37

6

37

19 37

6

37

6

37

19 37

6

37

6

37

19

17 70

8

17 69

8

17

8

17

8

17

8

17

8

17

8

17

8

17

8

17

8

17 69

16 29

16 34

17 23

6

29 82

16 29

8

17 69

17 23

16 29

34

16 29

16 34

8

16

34

16 34

34

6

29 82

6

16 29

6

16 29

8

16

8

17 69

8

16

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.10.1.

SMBus Interface Constraints

HD Audio Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.12.1.

SIO Signal Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.13.

SPI Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.8.

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.14.

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.11.1.

USB 2.0 Interface Constraints

SOURCE: MCP79 Interface DG (DG-03328-001_v0D), Section 2.9.1.

LPC Bus Constraints

PCI Bus Constraints

=STANDARD

=55_OHM_SE

*

CLK_PCI_55S

=STANDARD

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

CLK_LPC_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD=STANDARD

6 MIL

LPC

?

*

CLK_LPC

8 MIL

*

?

MCP Constraints 2

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

78 83

A

051-7903

=55_OHM_SE

SPI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

* =STANDARD =STANDARD

8 MIL

?

SPI

*

=55_OHM_SE =55_OHM_SE=55_OHM_SE=55_OHM_SE

HDA_55S

=STANDARD =STANDARD*

*

=55_OHM_SE=55_OHM_SE=55_OHM_SE=55_OHM_SE

CLK_SLOW_55S

=STANDARD=STANDARD

=55_OHM_SE

PCI_55S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD* =STANDARD

8 MIL

CLK_PCI

?

*

=STANDARD

PCI

?

*

=55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE=55_OHM_SE

LPC_55S

* =STANDARD

=4x_DIELECTRIC

TOP,BOTTOM

?

USB

8 MIL

?

CLK_SLOW

*

MCP_HDA_COMP

8 MIL

*

?

*

HDA

=2x_DIELECTRIC

SMB

*

?

=2x_DIELECTRIC

=55_OHM_SE=55_OHM_SE=55_OHM_SE

SMB_55S

=STANDARD=STANDARD*

=55_OHM_SE

=90_OHM_DIFF

* =90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF

USB_90D

* =STANDARD=STANDARD

=STANDARD =STANDARD

8 MIL8 MIL

MCP_USB_RBIAS

=2x_DIELECTRIC

USB

?

*

USB_CARDREADER

USB_CARDREADER_P

USB_90D

USB

USB_90D

NC_USB_EXCARDN

PCI_55S

PCI

PCI_AD<31..25>

PCI_AD

PCI_DEVSEL_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI

PCI_AD

PCI_AD<23..8>

PCI_55S

PCI

MCP_DEBUG

MCP_DEBUG<7..0>

USB_EXCARD

USB_90D

USB

NC_USB_EXCARDP

USB_90D

USB

USB_IR_N

USB

NC_USB_EXTDN

USB_90D

USB_EXTD

USB

NC_USB_EXTDP

USB_90D

USB

USB_EXTA_N

USB_90D

CLK_LPC

CLK_LPC_55S

LPC_CLK33M_LPCPLUS

USB_EXTA

USB

USB_90D

USB_EXTA_P

CLK_LPC

CLK_LPC_55S

LPC_CLK33M_SMC

MCP_LPC_CLK0

CLK_LPC

CLK_LPC_55S

LPC_CLK33M_SMC_R

LPC_RESET_L

LPC

LPC_RESET_L

LPC_55S

LPC_AD<3..0>

LPC

LPC_AD

LPC_55S

LPC_FRAME_L

LPC

LPC_55S

CLK_PCI

CLK_PCI_55S

PCI_CLK33M_MCP_R

MCP_PCI_CLK2

CLK_PCI

CLK_PCI_55S

PCI_CLK33M_MCP

PCI

PCI_55S

PCI_INTY_L

PCI_55S

PCI_INTZ_L

PCI

PCI_INTZ_L

PCI_55S

PCI_INTW_L

PCI

PCI_INTW_L PCI_INTX_L

PCI_55S

PCI_INTX_L

PCI

PCI_55S

PCI_GNT1_L

PCI

PCI_GNT0_L

PCI_55S

PCI_GNT0_L

PCI

PCI_55S

PCI_REQ1_L

PCI

PCI_55S

PCI_FRAME_L

PCI_CNTL

PCI

PCI_55S

PCI_REQ0_L

PCI

PCI_REQ0_L

PCI_TRDY_L

PCI_55S

PCI

PCI_CNTL

PCI_55S

PCI_SERR_L

PCI

PCI_CNTL

PCI_STOP_L

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_PERR_L

PCI

PCI_CNTL

PCI_55S

PCI_IRDY_L

PCI

PCI_CNTL

PCI_55S

PCI_PAR

PCI_AD

PCI

PCI_C_BE_L

PCI_55S

PCI_C_BE_L<3..0>

PCI

PCI_55S

PCI_AD<24>

PCI

PCI_AD24

USB_90D

USB

USB_EXTA_MUXED_N

USB

USB_90D

USB_MINI

NC_USB_MINIP

USB_IR_P

USB

USB_90D

USB_IR

USB_90D

USB

USB_EXTB

USB_EXTB_P

USB_90D

USB

USB_EXTB_N

USB

USB_90D

USB_BT

USB_BT_P

USB_90D

USB_CAMERA

USB

USB_CAMERA_P

NC_USB_MININ

USB

USB_90D

USB

USB_90D

USB_EXTA_MUXED_P

USB

USB_90D

USB_TPAD_N

USB

USB_90D

USB_TPAD_P

USB_TPAD

USB

USB_90D

USB_BT_N

USB

USB_90D

USB_CAMERA_N

MCP_USB_RBIAS_GND

MCP_USB_RBIASMCP_USB_RBIAS

SMB

SMBUS_MCP_0_CLK

SMB_55S

SMB

SMBUS_MCP_0_DATA

SMB_55S

SMBUS_MCP_1_CLK

SMB

SMB_55S

SMBUS_MCP_1_DATA

SMB

SMB_55S

HDA_BIT_CLK

HDA

HDA_55S

HDA_BIT_CLK_R

HDA

HDA_55S

HDA_SYNC

HDA

HDA_SYNC

HDA_55S

HDA_SYNC_R

HDA

HDA_55S

HDA_RST_R_L

HDA

HDA_55S

HDA_RST_L

HDA

HDA_55S

HDA_SDIN0

HDA

HDA_55S

HDA_SDIN0

HDA

HDA_55S

HDA_SDIN_CODEC HDA_SDOUT

HDA

HDA_SDOUT

HDA_55S

HDA_SDOUT_R

HDA

HDA_55S

MCP_HDA_COMP

MCP_HDA_PULLDN_COMP

MCP_SUS_CLK

CLK_SLOW_55S CLK_SLOW

PM_CLK32K_SUSCLK_R

CLK_SLOWCLK_SLOW_55S

PM_CLK32K_SUSCLK SPI_CLK_R

SPI

SPI_CLK SPI_55S

SPI

SPI_CLK

SPI_55S

SPI_MOSI_R

SPI_MOSI

SPI

SPI_55S

SPI_MOSI

SPI

SPI_55S

SPI

SPI_MISO

SPI_55S

SPI_MISO

SPI

SPI_55S

SPI_MISO_R

SPI

SPI_55SSPI_CS0

SPI_CS0_R_L

SPI

SPI_55S

SPI_CS0_L

NC_USB_EXTCP

USB_EXTC

USB

USB_90D USB_90D

NC_USB_EXTCN

USB

USB_CARDREADER_N

USB

USB_90D

19 30

8

19

12 18

8

19

19 39

8

19

8

19

19 38

24 42

19 38

24 40

18 24

18 40 42

18

8

19

19 39

19 38

6

19 29

6

19 29

8

19

19 48

6

19 29

6

19 29

19

12 20 26 27 43

12 20 26 43

20 43 58 72

20 53

20

20 53

20

20 53

20

20 24

24 40

20 42

52

20 42

52

20 42

52

20 42

8

19

8

19

19 30

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Section 2.7.4

SOURCE: MCP73 Interface DG (DG-02974-001_v01), Sections 2.7.2 & 2.7.4

88E1116R (Ethernet PHY) Constraints

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

MCP RGMII (Ethernet) Constraints

SPACING

SYNC_DATE=02/05/2009

SYNC_MASTER=T18_MLB

Ethernet Constraints

79 83

A

051-7903

?

*

ENET_MII

12 MIL

=3:1_SPACING

*

?

MCP_BUF0_CLK

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=55_OHM_SE

ENET_MII_55S

=STANDARD =STANDARD*

7.5 MIL

=STANDARD

=STANDARD =STANDARD

7.5 MIL

=STANDARD*

MCP_MII_COMP

ENET_MDI_100D

=100_OHM_DIFF

*

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

25 MIL

?

*

ENET_MDI

MCP_MII_COMP

MCP_MII_COMP_VDD

MCP_MII_COMP

ENET_RXD_R<3..0>

ENET_MII_55S ENET_MII

ENET_CLK125M_RXCLK

ENET_MII_55S ENET_MII

ENET_RXCLK

ENET_CLK125M_RXCLK_R

ENET_MIIENET_MII_55S

MCP_CLK25M_BUF0

MCP_CLK25M_BUF0_R

MCP_BUF0_CLKENET_MII_55S

MCP_MII_COMP

MCP_MII_COMP_GND

MCP_MII_COMP

ENET_RXD

ENET_RX_CTRL

ENET_MII_55S ENET_MII

ENET_CLK125M_TXCLK

ENET_MII_55S ENET_MII

ENET_TXCLK

ENET_TXD<3..1>

ENET_MIIENET_MII_55SENET_TXD

ENET_TXD<0>

ENET_MII_55S ENET_MII

ENET_TXD0

ENET_MIIENET_MII_55S

ENET_RESET_L

ENET_MII_55S ENET_MII

ENET_TX_CTRL

ENET_TXD

ENET_MDI

ENET_MDI_N<3..0>

ENET_MDI_100D

ENET_MDI

ENET_MDI_P<3..0>

ENET_MDI_100D

ENET_MDI

ENET_RXD_STRAP

ENET_RXD<3..1>

ENET_MII_55S ENET_MII

ENET_RXD

ENET_RXD<0>

ENET_MII_55S ENET_MII

ENET_MII

ENET_MDIO

ENET_MII_55S

ENET_PWRDWN_L

ENET_MII_55S ENET_MII

ENET_MDC

ENET_MDC ENET_MIIENET_MII_55S

ENET_INTR_L

ENET_MII_55S

ENET_INTR_L

ENET_MII

RTL8211_CLK25M_CKXTAL1

MCP_BUF0_CLKENET_MII_55S

17

31

17 31

31

17 32

17

17 31

31 33

17 31

31 32

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Port 2 Not Used

PHYSICAL

FireWire Interface Constraints

NET_TYPE

SPACING

FireWire Net Properties

ELECTRICAL_CONSTRAINT_SET

051-7903

A

8380

FireWire Constraints

SYNC_MASTER=T18_MLB

SYNC_DATE=02/05/2009

*

=3:1_SPACING

?

FW_TP

=110_OHM_DIFF=110_OHM_DIFF

FW_110D

=110_OHM_DIFF=110_OHM_DIFF

=110_OHM_DIFF

*

=110_OHM_DIFF

FW_P0_TPA

NC_FW0_TPAP

FW_110D

FW_TP

FW_P0_TPA

NC_FW0_TPAN

FW_TP

FW_110D

FW_P0_TPB

NC_FW0_TPBP

FW_TP

FW_110D

FW_P0_TPB

NC_FW0_TPBN

FW_TP

FW_110D

FW_P1_TPB

FW_TP

FW_110D

FW_PORT1_TPB_N

FW_P1_TPB

FW_TP

FW_110D

FW_PORT1_TPB_P

FW_P1_TPA

FW_TP

FW_110D

FW_PORT1_TPA_N

FW_P1_TPA

FW_TP

FW_110D

FW_PORT1_TPA_P

34 36

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

SPACING

SMC SMBus Net Properties

SPACING

PHYSICAL

NET_TYPE

ELECTRICAL_CONSTRAINT_SET

SMBus Charger Net Properties

051-7903

A

8381

SMC Constraints

SYNC_MASTER=T18_MLB

SYNC_DATE=02/05/2009

=STANDARD =STANDARD

0.1 MM 0.1 MM*

=STANDARD=STANDARD

1TO1_DIFFPAIR

CHGR_CSO_N

1TO1_DIFFPAIR

CHGR_CSO_P

1TO1_DIFFPAIR

CHGR_CSO

CHGR_CSI_P

1TO1_DIFFPAIR

CHGR_CSI

CHGR_CSI_N

1TO1_DIFFPAIR

SMB_55S

SMBUS_SMC_A_S3_SCL

SMB

SMB_55S

SMBUS_SMC_A_S3_SDA

SMB

SMBUS_SMC_BSA_SDA

SMB

SMB_55S

SMB

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

SMBUS_SMC_MGMT_SCL

SMB_55S

SMBUS_SMC_MGMT_SCL

SMB

SMBUS_SMC_BSA_SCL

SMB_55S

SMBUS_SMC_0_S0_SDA

SMB

SMB_55S

SMBUS_SMC_0_S0_SCL

SMB

SMB_55S

SMB

SMBUS_SMC_B_S0_SDA

SMB_55S

SMB

SMBUS_SMC_B_S0_SCL

SMB_55S

60

6

29 40 43 49

6

29 40 43 49

6

40 43 59 60

25 37 40 43

6

40 43 59 60

40 43 46 51

40 43 46

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

K19i Specific Graphics Net Properties

SD Card Interface Constraints

ELECTRICAL_CONSTRAINT_SET

SD Card Net Properties

NET_TYPE

PHYSICAL

SPACING

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

NET_TYPE

SPACING

(USB_TPAD)

MCP Fanout Constraint Relaxations

Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

K19i Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

(PCIE_MINI) (PCIE_MINI)

(USB_CAMERA)

(USB_EXTA)

(USB_EXTA) (USB_EXTA)

(USB_EXTA)

ELECTRICAL_CONSTRAINT_SET

K19i Specific Net Properties

PHYSICAL

NET_TYPE

SPACING

NET_TYPE

SPACING

PHYSICAL

PWR_P2MM

*

SB_POWER

USB

GND_P2MM

GND

*

LVDS

MEM_70D

BOTTOM

6.35 MM

0.127 MM

GND

*

GND_P2MMENET_MDI

GND_P2MM

GND

*

CPU_VCCSENSE

FSB_DSTB

*

GND_P2MMFSB_DSTB

GND_P2MM

*

GND

CPU_GTLREF

GND_P2MM

CLK_FSB

*

GND

*

GND_P2MM

GND

CPU_COMP

*

GND_P2MM

MEM_DQS

GND

=1:1_DIFFPAIR

SENSE_1TO1_55S

=55_OHM_SE

=1:1_DIFFPAIR

=55_OHM_SE

*

=1:1_DIFFPAIR

=55_OHM_SE

25 MILS

* ?

ENETCONN

?

THERM

*

=2:1_SPACING

THERM_1TO1_55S

=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

DIFFPAIR

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

* ?

SENSE

=2:1_SPACING

?

*

=2:1_SPACING

AUDIO

=STANDARDGND

?*

=STANDARDPP1V8_MEM

* ?

GND_P2MM

1000

*

0.20 MM

1000

0.20 MM

*

PWR_P2MM

GND_P2MM

GND

MEM_CLK

*

GND

GND_P2MM

*

MEM_CMD

GND_P2MM

GND

MEM_CTRL

*

GND_P2MM

*

GND

MEM_DATA

GND_P2MM

*

CLK_PCIE

GND

GND_P2MM

*

GNDUSB

GND_P2MM

*

SATA

GND

PWR_P2MM

*

CLK_PCIE SB_POWER

PWR_P2MM

*

SB_POWER

SATA

MEM_40S

*

0.09 MM

5.8 MM

*

MEM_40S_VDD

0.09 MM

5.8 MM

*

0.09 MM

5.8 MM

MEM_70D

*

0.09 MM 100 MIL

MEM_70D_VDD

PCIE_90D

100 MIL0.09 MM

*

0.1 MM

500 MIL

TOP

MCP_DV_COMP

500 MIL

TOP

USB_90D 0.09 MM

0.1 MM

500 MIL

TOP

MCP_MEM_COMP

MCP_DV_COMP

250 MIL

*

0.25 MM

MCP_USB_RBIAS

0.1 MMTOP

500 MIL

0.1 MM

500 MIL

MCP_MII_COMP

TOP

GND_P2MM

*

PCIE

GND

?

=3X_DIELECTRIC

*

SD_INTERFACE

=55_OHM_SE

*

=55_OHM_SE=55_OHM_SE

SD_55S

=55_OHM_SE

=STANDARD =STANDARD

K19i Specific Constraints

SYNC_DATE=01/08/2009

SYNC_MASTER=WFERRY_K19I

82 83

A

051-7903

SPKRAMP_L_OUT_P

DIFFPAIR

AUDIO

SPKRCONN_R_OUT_N

DIFFPAIR

AUDIO

SPKRAMP_L_OUT_N

DIFFPAIR

AUDIO

SPKRAMP_R_OUT_P

DIFFPAIR

AUDIO

SPKRAMP_S_OUT_P

DIFFPAIR

AUDIO

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_CONN_P

1TO1_DIFFPAIR

CHGR_CSI_R_N

USB_90D

USB2_EXTA_MUXED_P

USB

ENET_MDI_100D

ENETCONN

ENETCONN_P<3..0>

SATA_100D

SATA

SATA_ODD_D2R_UF_P

SATA_HDD_D2R_UF_N

SATA_100D

SATA

SPKRAMP_S_OUT_N

DIFFPAIR

AUDIO

SPKRAMP_R_OUT_N

DIFFPAIR

AUDIO

SPKRCONN_S_OUT_N

DIFFPAIR

AUDIO

SPKRCONN_S_OUT_P

SPK_OUT

DIFFPAIR

AUDIO

SPKRCONN_L_OUT_N

AUDIO

DIFFPAIR

SPKRCONN_L_OUT_P

SPK_OUT

DIFFPAIR

AUDIO

DP_AUX_CH_SW_N

DISPLAYPORT

DP_100D

DP_AUX_CH_SW_P

DISPLAYPORT

DP_100D

USB_LT2_P

USB_90D

USB

CONN_USB2_BT_P

USB_90D

USB

CONN_USB2_BT_N

USB_90D

USB

USB_CAMERA_CONN_N

USB_90D

USB

USB_90D

USB2_LT1_N

USB

USB_90D

USB2_LT1_P

USB

USB_90D

USB2_EXTA_MUXED_N

USB

1TO1_DIFFPAIR

CHGR_CSO_R_P

1TO1_DIFFPAIR

CHGR_CSO_R_N

1TO1_DIFFPAIR

CHGR_CSI_R_P

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_CONN_N

PCIE_90D

PCIE_MINI_R2D_P

PCIE

PCIE_90D

PCIE_MINI_R2D_N

PCIE

SATA_100D

SATA

SATA_ODD_D2R_UF_N SATA_HDD_D2R_UF_P

SATA_100D

SATA

SATA_100D

SATA

SATA_HDD_R2D_UF_P

SATA

SATA_100D

SATA_ODD_R2D_UF_N

SATA_100D

SATA

SATA_ODD_R2D_UF_P

ENET_MDI_100D

ENETCONN

ENETCONN_N<3..0>

SATA_100D

SATA

SATA_HDD_R2D_UF_N

USB_TPAD_R_P

USB_90D

USB

USB_TPAD_R_N

USB_90D

USB

USB_CAMERA_CONN_P

USB_90D

USB

USB_LT2_N

USB_90D

USB

SPKRCONN_R_OUT_P

SPK_OUT

DIFFPAIR

AUDIO

CPUTHMSNS_D2_P

THERM

THERM_1TO1_55S

CPUTHMSNS_D2

CPUTHMSNS_D2_N

THERM

THERM_1TO1_55S

CPU_THERMD_P

THERM

THERM_1TO1_55S

CPU_THERMD

CPU_THERMD_N

THERM

THERM_1TO1_55S

THERM

THERM_1TO1_55S

MCPTHMSNS_D2_N

THERM

THERM_1TO1_55S

MCPTHMSNS_D2_P

MCPTHMSNS_D2

MCP_THMDIODE

THERM

THERM_1TO1_55S

MCP_THMDIODE_P MCP_THMDIODE_N

THERM

THERM_1TO1_55S

ISNS_1V5_S3_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_1V5_S3_R_P

SENSE

SENSE_1TO1_55S

ISNS_1V5_S3_N

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_1V5_S3_R_N

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_N

SENSE

SENSE_1TO1_55S

ISNS_AIRPORT_R_N

SENSE_1TO1_55S

SENSE

ISNS_AIRPORT_R_P

SENSE

SENSE_1TO1_55S

ISNS_HDD_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_HDD_R_P

SENSE

SENSE_1TO1_55S

ISNS_HDD_N

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_HDD_R_N

SENSE_1TO1_55S

SENSE

ISNS_LCDBKLT_N

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_R_P

SENSE

SENSE_1TO1_55S

ISNS_LCDBKLT_R_N

SENSE_1TO1_55S

SENSE

ISNS_ODD_N

SENSE

SENSE_1TO1_55S

ISNS_ODD_R_P

SENSE

SENSE_1TO1_55S

ISNS_CPUVTT_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

ISNS_ODD_R_N

SENSE_1TO1_55S

SENSE

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

MCPCORES0_RSEN_P

ISNS_CPUVTT_N

SENSE

SENSE_1TO1_55S

SENSE

MCPCORES0_RSEN_N PP3V3_S5

SB_POWER

PP1V5_S0

ISNS_ODD_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

LVDS_100D

LVDS_CONN_A_CLK_F_N

LVDS

LVDS_100D

LVDS_CONN_A_CLK_F_P

LVDS

LVDS_100D

LVDS_CONN_B_CLK_F_P

LVDS LVDS

LVDS_CONN_B_CLK_F_N

LVDS_100D

DP_ML_C_N<3..0>

DISPLAYPORT

DP_100D

DP_ML_P<3..0>DP_ML_P<3..0>

DP_ML

DISPLAYPORT

DP_100D

DP_ML_N<3..0>DP_ML_N<3..0>

DISPLAYPORT

DP_100D

DP_ML_CONN_P<3..0>

DP_ML

DISPLAYPORT

DP_100D

DP_ML_CONN_N<3..0>

DISPLAYPORT

DP_100D

DP_AUX_CH_C_P

DP_AUX_CH

DISPLAYPORT

DP_100D

DP_AUX_CH_C_N

DP_AUX_CH

DISPLAYPORT

DP_100D

SB_POWER

PP3V3_S0

DP_ML_C_P<3..0>

DP_ML

DISPLAYPORT

DP_100D

SD_INTERFACE

SD_55S

SD_D<0>

SD_DATA

SD_INTERFACE

SD_55S

SD_D<1>

SD_DATA

SD_INTERFACE

SD_55S

SD_D<2>

SD_DATA

SD_INTERFACE

SD_55S

SD_D<3>

SD_DATA

SD_INTERFACE

SD_55S

SD_D<4>

SD_DATA

SD_INTERFACE

SD_55S

SD_D<6>

SD_DATA

SD_INTERFACE

SD_55S

SD_D<5>

SD_DATA

SD_INTERFACE

SD_55S

SD_D<7>

SD_DATA

SD_INTERFACE

SD_55S

SD_CLK

SD_INTERFACE

SD_55S

SD_CMD

GND

56

6

56 57

56

6

29

60

38

33

6

37

56

6

56 57

6

56 57

6

56 57

6

56 57

70

38

6

29

6

29

6

29

38

45 60

60

6

29

6

29 77

6

29 77

6

37

33

37

48

6

29

38

6

56 57

46

9

46

9

46

20 46

51 63

51

51 63

29 51

51

29 51

51

37 51

51

37 51

51 72

51

51 72

37 51

51

45

51

64

45

64

6 7

17 19 21 22 24 28

32 35 36 42 52 62 66 67

68 69 71

6 7

10 11 15 22 37 66

67 68

37 51

6

69

6

69

6

69

6

69

71

17 70 71

71

70 71

6 7

12 17 18 20 21 22

23 26 27 35 37 41 43 45

46 47

49 53 57 58 61 66 67 68 69 71 72

6

71

6

30

6

30

6

30

6

30

6

30

6

30

6

30

6

30

6

30

6

30

TABLE_SPACING_ASSIGNMENT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

K19i Board-Specific Physical & Spacing Constraints

0.220 MM0.220 MM

0.112 MM

90_OHM_DIFF

Y

0.112 MM

TOP,BOTTOM

0.234 MM0.234 MM

0.095 MM

90_OHM_DIFF

Y

0.095 MM

ISL3,ISL4,ISL9,ISL10

=STANDARD=STANDARD

=STANDARD =STANDARD

90_OHM_DIFF

N

=STANDARD

*

0.200 MM0.200 MM

0.185 MM

70_OHM_DIFF

Y

0.185 MM

TOP,BOTTOM

0.224 MM0.224 MM

0.151 MM

=STANDARD

70_OHM_DIFF

Y

0.151 MM

ISL3,ISL4,ISL9,ISL10

=STANDARD=STANDARD

=STANDARD =STANDARD

70_OHM_DIFF

N

=STANDARD

*

=STANDARD=STANDARD

0.222 MM

=STANDARD

27P4_OHM_SE

Y

0.222 MM

*

0.310 MM

27P4_OHM_SE

Y

0.310 MM

TOP,BOTTOM

=STANDARD=STANDARD

0.100 MM

=STANDARD40_OHM_SE

Y

0.126 MM

*

0.100 MM

40_OHM_SE

Y

0.165 MM

TOP,BOTTOM

=STANDARD=STANDARD

0.076 MM

=STANDARD50_OHM_SE

Y

0.076 MM

*

=STANDARD=STANDARD

0.076 MM

=STANDARD55_OHM_SE

Y

0.076 MM

*

=DEFAULT=DEFAULT

=DEFAULT

12.7 MM

STANDARD

Y

=DEFAULT

*

0 MM0 MM

0.080 MM

12.7 MMDEFAULT

Y

=50_OHM_SE

*

5X_DIELECTRIC

*

0.315 MM

?

4X_DIELECTRIC

*

0.252 MM

?

3X_DIELECTRIC

*

0.189 MM

?

2X_DIELECTRIC

*

0.126 MM

?

5X_DIELECTRIC

TOP,BOTTOM

0.350 MM

?

4X_DIELECTRIC

TOP,BOTTOM

0.280 MM

?

3X_DIELECTRIC

TOP,BOTTOM

0.210 MM

?

2X_DIELECTRIC

TOP,BOTTOM

0.140 MM

?

4:1_SPACING

*

0.4 MM

?

3:1_SPACING

*

0.3 MM

?

2.5:1_SPACING

*

0.25 MM

?

2:1_SPACING

*

0.2 MM

?

1.5:1_SPACING

*

0.15 MM

?

BGA_P1MM

*

0.1 MM

?

STANDARD

*

=DEFAULT

?

BGA

MEM_40S_VDD

STANDARD

BGA

MEM_40S

STANDARD

*

BGA

BGA_P1MM

*

BGA

BGA_P2MM

MEM_CLK

*

BGA

BGA_P2MMCLK_PCIE

*

BGA

BGA_P2MMCLK_SLOW

FSB_DSTB

BGA

BGA_P3MMFSB_DSTB

0.1 MM0.1 MM

=STANDARD =STANDARD

1:1_DIFFPAIR

Y

=STANDARD

*

0.330 MM0.330 MM

0.077 MM

110_OHM_DIFF

Y

0.077 MM

TOP,BOTTOM

0.330 MM0.330 MM

0.075 MM

110_OHM_DIFF

Y

0.075 MM

ISL3,ISL4,ISL9,ISL10

=STANDARD=STANDARD

=STANDARD =STANDARD

110_OHM_DIFF

N

=STANDARD

*

=STANDARD=STANDARD

=STANDARD =STANDARD

N

=STANDARD

*

100_OHM_DIFF_HDD

0.400 MM0.400 MM

0.083 MM

Y

0.083 MM

ISL3,ISL4,ISL9,ISL10

100_OHM_DIFF_HDD

0.400 MM0.400 MM

0.095 MM

Y

0.095 MM

TOP,BOTTOM

100_OHM_DIFF_HDD

0.230 MM0.230 MM

0.091 MM

100_OHM_DIFF

Y

0.091 MM

TOP,BOTTOM

0.244 MM0.244 MM

0.075 MM

100_OHM_DIFF

Y

0.075 MM

ISL3,ISL4,ISL9,ISL10

=STANDARD=STANDARD

=STANDARD =STANDARD

100_OHM_DIFF

N

=STANDARD

*

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

NO_TYPE,BGA

MM

15.2

0.090 MM

55_OHM_SE

Y

0.090 MM

TOP,BOTTOM

0.115 MM

50_OHM_SE

Y

0.115 MM

TOP,BOTTOM

BGA_P3MM

*

0.3 MM

?

BGA_P2MM

*

0.2 MM

?

DEFAULT

*

0.1 MM

?

051-7903

A

8383

SYNC_MASTER=WFERRY_K19I

SYNC_DATE=12/12/2008

K19i PCB Rule Definitions

*

BGA

BGA_P2MM

CLK_PCI

*

BGA

BGA_P2MM

CLK_LPC

*

BGA

BGA_P2MM

CLK_FSB

Apple A1286 Schematic RevA

Specifications and Main Features

Frequently Asked Questions

User Manual