Apple A1278 Schematic RevA.13.0

TABLE_TABLEOFCONTENTS_ITEM

DRAWING

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_ITEMTABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

TABLE_TABLEOFCONTENTS_ITEM

Schematic / PCB #’s

SCHEM,MLB_LDO,K6

PVT, 3/18/10

1 OF 80

051-8563

A.13.0

1 OF 109

2010-03-18

LAST_MODIFIED=Thu Mar 18 17:53:39 2010

FireWire Constraints

Ethernet Constraints

MCP Constraints 2

K69_MLB

48

WELLSPRING 2

AUDIO: CODEC/REGULATOR

55

FSB/DDR3 Vref Margining

31

FireWire LLC/PHY (FW643E) FireWire Port & PHY Power

34

SATA Connectors

Internal USB Support

SecureDigital Card Reader

41

BOM Configuration

K69_MLB

T27_MLB

SCHEM,MLB_LDO,K6

08/27/2009

Thermal Sensors

55

45

T27_MLB

09/30/2009

Current Sensing

54

44

T27_MLB

08/27/2009

Voltage Sensing

53

43

T27_MLB

08/21/2009

K6 SMBUS CONNECTIONS

52

42

T27_MLB

08/27/2009

LPC+SPI Debug Connector

51

41

T27_MLB

09/02/2009

SMC Support

50

40

T27_MLB

09/02/2009

SMC

49

39

T27_MLB

08/27/2009

48

38

T27_MLB

08/27/2009

External USB Connectors

46

37

T27_MLB

08/06/2009

45

36

T27_MLB

07/28/2009

FireWire Connector

43

35

T27_MLB

12/15/2009

42

T27_MLB

07/20/2009

33

T27_MLB

07/28/2009

Ethernet Connector

40

32

T27_MLB

08/20/2009

Ethernet PHY (Caesar II/IV)

39

T27_MLB

09/30/2009

35

30

T27_MLB

07/28/2009

RIGHT CLUTCH CONNECTOR

34

29

T27_MLB

09/29/2009

33

28

T27_MLB

06/19/2009

DDR3 BYTE/BIT SWAPS-K6

32

27

K18_MLB

07/28/2009

DDR3 SO-DIMM Connector B

31

26

T27_MLB

07/28/2009

DDR3 SO-DIMM Connector A

29

25

T27_MLB

07/28/2009

SB Misc

28

24

T27_MLB

08/06/2009

MCP Graphics Support

26

23

T27_MLB

08/15/2009

MCP Standard Decoupling

25

22

T27_MLB

11/23/2009

MCP89 GFX Core Rail Gating

24

21

T27_MLB

11/23/2009

MCP89 Memory Rail Gating

23

20

T27_MLB

08/06/2009

MCP Power & Ground

20

19

T27_MLB

11/23/2009

MCP HDA, LPC & MISC

19

18

T27_MLB

11/23/2009

MCP SATA, USB & Ethernet

18

17

11/05/2009

MCP Graphics

17

16

T27_MLB

11/05/2009

MCP PCIe Interfaces

16

15

T27_MLB

08/06/2009

MCP Memory Interface

15

14

T27_MLB

11/05/2009

MCP CPU Interface

14

13

T27_MLB

07/28/2009

eXtended Debug Port (mini-XDP)

13

12

T27_MLB

11/23/2009

CPU Decoupling

12

11

T27_MLB

07/20/2009

CPU Power & Ground

11

10

T27_MLB

08/27/2009

CPU FSB

10

9

T27_MLB

07/20/2009

SIGNAL ALIAS

9

8

K24_MLB

07/22/2009

Power Aliases

8

7

K24_MLB

07/20/2009

FUNC TEST

7

6

K24_MLB

07/20/2009

Revision History

5

K24_MLB

07/20/2009

4

K24_MLB

08/19/2009

Power Block Diagram

3

08/19/2009

System Block Diagram

2

K69_MLB

109

T27_MLB

08/06/2009

K6/K69 PCB Rule Definitions

80

108

T27_MLB

09/08/2009

K6/K69 Specific Constraints

79

106

T27_MLB

07/28/2009

SMC Constraints

78

105

T27_MLB

07/20/2009

77

104

T27_MLB

11/23/2009

76

103

T27_MLB

08/27/2009

75

102

T27_MLB

08/03/2009

MCP Constraints 1

74

101

T27_MLB

08/03/2009

Memory Constraints

73

100

T27_MLB

08/03/2009

CPU/FSB Constraints

72

98

T27_MLB

07/28/2009

LCD Backlight Support

71

97

08/27/2009

LCD Backlight Driver

70

94

K24_MLB

07/20/2009

DisplayPort Connector

69

93

K69_MLB

08/12/2009

DISPLAYPORT SUPPORT

68

90

K24_MLB

07/20/2009

LVDS CONNECTOR

67

79

T27_MLB

08/27/2009

Power FETs

66

78

T27_MLB

11/24/2009

Power Sequencing

65

77

T27_MLB

09/30/2009

Misc Power Supplies

64

76

K24_MLB

07/20/2009

CPU VTT(1.05V) SUPPLY

63

75

T27_MLB

08/18/2009

MCP VCore Regulator

62

74

K24_MLB

07/20/2009

IMVP6 CPU VCore Regulator

61

73

T27_MLB

08/06/2009

1.5V/1.35V LVDDR3 Supply

60

72

K24_MLB

07/20/2009

5V/3.3V SUPPLY

59

70

T27_MLB

07/29/2009

PBus Supply & Battery Charger

58

69

K24_MLB

07/20/2009

DC-In & Battery Connectors

57

68

AUDIO

08/27/2009

AUDIO: JACK TRANSLATORS

56

67

AUDIO

08/25/2009

AUDIO: JACK

66

AUDIO

07/17/2009

AUDI0: SPEAKER AMP

54

65

AUDIO

07/17/2009

AUDIO: HEADPHONE FILTER

53

63

AUDIO

07/17/2009

AUDIO: LINE INPUT FILTER

52

62

AUDIO

08/31/2009

51

61

T27_MLB

10/21/2009

SPI ROM50

59

T27_MLB

07/20/2009

Sudden Motion Sensor (SMS)

49

58

T27_MLB

08/03/2009

57

T27_MLB

08/15/2009

WELLSPRING 1

47

56

K24_MLB

07/20/2009

Fan46

SCHEM,MLB_LDO,K6

051-8563

SCH1

CRITICAL

05/20/2009

Table of Contents

1

K17_MLB

Sync

Contents

(.csa)

Date

TITLE=MLB ABBREV=DRAWING

PCBF,MLB_LDO,K6

820-2879

1

CRITICAL

PCB

Page

Contents

(.csa)

Date

SyncPage

3

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PG 17

USB

(UP TO 12 DEVICES)

6

J1300

J6750,6700

PG 56

U6633, U6623, U6613

PG 55PG 53

Mic

U6880

PG 54

Filter

PG 53

Filter

PG 52

Amps

PG 15

DISPLAY PORT

J3401

AIR PORT

PG 29

PG 70

J9400

J4501

PG 38

PG 68

PG 29

PG 32

J4000

E-NET

BMC5764M

U3900

PG 18

PG 15,18

PG 17

PG 16

MAC

PG 18

PG 12

Connectors

PG 37PG 29

IR

PG 38PG 47 PG30 PG38

7

USB

EXTERNAL

J4600, J4610

8

10

RGB OUT

11

9

HDMI OUT

Card reader

J4890

Blue Ray dec

KEYBOARD

J3500U5701J3401 J4890

PG 29

LPC+SPI Conn

PG 46

J5601

PG 50

U5535,U5515

PG 45

PG 58,59

J6950,U7000

DC/BATT

Conns

Line In

HEADPHONE

Amp

Audio

PG 18

DDR3-1067/1333MHZ

MEMORY

1067/1333 MHz

PG 10

XDP CONN

J1300

PENRYN

PG 12

64-Bit

2.X OR 3.X GHZ

INTEL CPU

U1000

PG 9

2 UDIMMs

J9000

CONN

LVDS

CONN

Conn

4

TMDS OUT

2

CLK

SATA

PCI

LPC

3

SATA

Audio

Codec

FSB

POWER SUPPLY

Conn

PG 31

GB

Speaker

HD

ODD

Conn

SYNTH

SPI

PG 18

MAIN

J2900

DIMM

PG 25,26

J5100

Ser

FanADC

B,0 BSB

PWR

Misc

PG 14

GPIOs

1.05V/3GHZ.

PG 38

FSB INTERFACE

SMB

HDA

NVIDIA

SMB

10 5

U1400

DVI OUT

PCI-E

UP TO 20 LANES3

PG 17

LVDS OUT

DP OUT

AirPort

CONN

SATA

J4500

MCP

U6100

SMC

PG 39

SPI

U4900

Boot ROM

Prt

PG 51

FAN CONN AND CONTROL

POWER SENSE

CPU,MCP,TEMP SENSOR

CAMERA

TRACKPAD/

Bluetooth

CTRL

J3401

PCI-E

U6201

SYNC_MASTER=K69_MLB

SYNC_DATE=08/19/2009

System Block Diagram

2 OF 109

A.13.0

051-8563

2 OF 80

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MAX8840

PP1V05_S0_MCP_PLL_REG

MCP89

K6 POWER SYSTEM ARCHITECTURE

CHGR_BGATE

BATTERY CHARGER

DELAY

RC

DELAY

RC

DELAY

RC

P1V8S0_EN

MCPCORES0_EN

CPUVTTS0_EN

P1V5S0_EN

DDRVTT_EN

16-5

16-6

PM_SLP_S3_L

16-3

16-4

AP_PWR_EN

Q7890

(9 TO 12.6V)

3S2P

PM_SLP_S3_L

U1400

PM_SLP_S4_L

MCP89

11

15

DELAY

RC

11-2

RC DELAY

11-3

11-1

J6950

SMC_ADAPTER_EN

PM_SLP_S3_L

SMC_DCIN_ISENSE

PBUSVSENSE_EN

PPVBAT_G3H_CONN

P5VS0_EN

DELAY

PM_WLAN_EN_L

Q7890,Q7891

RC

P3V3S0_EN

(S0)

16-2

16-1

16

04-1

=DDRREG_EN

=DDTVTT_EN

S5 S3

U7300

MCPCORES0_EN

VOUT2

TPS51116

0.75V

VOUT1

02

VIN

14

EN

VIN

02

1.5V

P5VS3_EN_L

P3V3S3_EN

DDRREG_EN

BKLT_EN

U4900

SMC

Q7055

PBUS SUPPLY/

ISL6259

U7000

P60

P16

PPVBAT_G3H_CHGR_R

ENA

VIN

02

LP8545

U9701

(S5)

04

SMC_PM_G2_EN

VOUT

U7840

01

PPBUS_G3H

A

R7020

ADAPTER

AC

IN

DCIN(16.5V)

F6905

6A FUSE

01

A

VIN

ENABLES

(S5)

CHGR_EN

PP18V5_DCIN_CONN

VOUT

PPVBAT_G3H_CHGR_REG

R7050

Q7085

Q7080

P3V3S5_EN_L

PPVOUT_SW_LCDBKLT

MCP_CORE

ISL9563A

MCPDDROUT

Q7930

SMC_BATT_ISENSE

P5VS3_EN_L

IMVP_VR_ON_R

25

02

U7500

8A FUSE

F7040

VOUT

(1A MAX CURRENT)

PP0V75_S0_REG

(25A MAX CURRENT)

PPMCPCORE_S0_R

(12A MAX CURRENT)

20

PP1V5_S3_REG

EN

U7750

ISL8009B

PP1V5R1V35_SW_MCP

VIN

21

VOUT

R7525

PP0V9_S5_REG

PPMCPCORE_S0_REG

P3V3S0_EN

Q7930

U7720

ST1S12G12R

1.2V

U7710

ISL8009B

U7740

1.8V

TPS62202

U7760

1.5V

EN2

05

VIN

EN1

02

3.3V

TPS51125

P5V3V3_PGOOD

PGOOD1,2

U7201

(RT)

5V

VREG3

(5.5A MAX

VOUT2

VOUT1

VR_ON

U7100

VIN

PGOOD

ISL9504B

VOUT

CPU VCORE

SMC_CPU_ISENSE

PP3V3_S5_REG

PP5V_S3_REG

(13A MAX CURRENT)

VR_PWRGOOD_DELAY

CURRENT)

P3V3S3_EN

Q7910

28

V

PGOOD

PPVCORE_S0_CPU

SMC_CPU_VSENSE

CPUVTTS0_PGOOD

PP1V2_ENET_REG

PP3V3_S0_FET

PP1V8_S0_REG

1.05V

PP1V5_S0_REG

(44A MAX CURRENT)

TPS7470

PP3V3_S0 PP1V5_S0 PP1V05_S0

V3

V2

V1

RST*

ISL88042

U7870

18

S0PGOOD_RST_L

MCPPLLDO_PGOOD

P1V5S0_PGOOD

P5V3V3_PGOOD

MCPCORES0_PGOOD

CPUVTTS0_PGOOD

SLP_S5_L SLP_S4_L SLP_S3_L

09

ALL_SYS_PWRGD

05

SMC_ONOFF_L

RSMRST_PWRGD

SLP_S4_L(P94) SLP_S3_L(P93)

SLP_S5_L(P95)

U4900

PWRGD(P12)

PWR_BUTTON(P90)

RSMRST_IN(P13)

99ms DLY

Q3450

PP3V3_S3_FET

P3V3ENET_EN_L

P3V3_S3_WLAN

26

VIN

EN

U6200

VOUT

4.5V AUDIO

PP4V5_AUDIO_ANALOG

13

24

07

17

Q7940

P5VS0_EN

PP5V_S0_FET

SMC

U2850

29

MCP_PS_PWRGD

U1000

CPU

U1400

PWRGD

PPBUS_G3H

PPDCIN_G3H_OR_PBUS

(S0)

V

PBUS_VSENSE

02

CPUVTTS0_EN

Q5315

02

CPUVTT

(1.05V)

TPS51117

U7600

EN_PSV

VOUT

VIN

LT3470

ENABLE

U6990

VOUT

3.425V G3HOT

PBUS_G3H_VSENSE

PP1V05_S0

(8A MAX CURRENT)

PP3V42_G3H_REG

03

RN5VD30A-F

SMC PWRGD

U5010

04

RST*

P17(BTN_OUT)

IMVP_VR_ON(P16)

RSMRST_OUT(P15)

PLT_RST*

CPU_RESET#

PWRBTN*

PLTRST*

RESET*

CPUPWRGD(GPIO49)

PWRGOOD

RSMRST*

IMVP_VR_ON_R

PM_PWRBTN_L SMC_RESET_L

25

PM_RSMRST_L

32

10

FSB_CPURST_L

30

CPU_PWRGD

LPC_RESET_L

31

06-1

Power Block Diagram

SYNC_MASTER=K69_MLB

SYNC_DATE=08/19/2009

3 OF 109

A.13.0

051-8563

3 OF 80

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_ALT_ITEM

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

TABLE_ALT_ITEM

Top

GROUND

SIGNAL(High Speed)

Bar Code Labels / EEE #’s

POWER

SIGNAL(High Speed)

11

POWER

10

9

8

GROUND

6

5

4

3

2

GROUND

SIGNAL

SIGNAL(High Speed)

K6 BOARD STACK-UP

Module Parts

BOM Variants

SIGNAL

GROUND

7

Alternate Parts

DEVELOPMENT BOM

BOTTOM

BOM Groups

Programmable Parts

SYNC_MASTER=K24_MLB

BOM Configuration

152S0778152S0693

CYNTEC AS ALTERNATE

ALL

152S0685152S0796

CYNTEC AS ALTERNATE

ALL

157S0055157S0058

DELTA AS ALTERNATE

ALL

152S0874 152S0516

MAGLAYERS AS ALTERNATE

ALL

152S1024

ALL

152S1025

TOKO AS ALTERNATE

337S3769

ALL

516S0790

MOLEX AS ALTERNATE

516-0201

ALL

152S1135

ALL

152S0586152S0847

ALL

MAGLAYERS AS ALTERNATE

128S0218128S0093

ALL

KEMET AS ALTERNATE

104S0023104S0018

DALE/VISHAY AS ALTERNATE

ALL

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

CRITICAL

U5701

337S2983

WELLSPRING:BLANK

1

IC,ENCORE II,CY7C63803-LQXC

CRITICAL

IR:PROG

341S2384

1

U4800

U5701

CRITICAL

WELLSPRING:PROG

1

341S2616

IC,TP PSOC,K17,K18

CRITICAL

U4800

338S0633

IR:BLANK

1

U6100

EFI UNLOCKED,K6/K69

1

341T0238

BOOTROM:UNLOCKED

CRITICAL

IC,EFI,LOCKED,K6

341S2589

BOOTROM:LOCKED

CRITICAL

1

U6100

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

335S0610 CRITICAL

BOOTROM:BLANK

1

SMC EXTERNAL,K6

1

U4900

CRITICAL

SMC:PROG

341T0240

SMC:BLANK

1

U4900

IC,SMC,HS8/2117,9X9MM,TLP,HF

IC,LP8545,LED BKLT CTRLR,LLP24

1

353S2896

U9701

CRITICAL

U3900

IC,ASIC,BCM5764M,ENET CONTROLLER, 8x8, 64QFN

1

CRITICAL343S0493 BCM5764M

PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA

337S3761

1

CRITICAL

U1000

CPU:2.66GHZ

CPU:2.4GHZ

PDC,LGDZ,PRQ,2.40,25W,1066,R0,3M,BGA

337S3680

U1000

1

CPU:2.26GHZ

PDC,SLGVT,PRQ,2.26,25W,1066,R0,3M,BGA,P7550

U1000

337S3769

1

K6_DEBUG:PVT

K6_DEBUG:ENG

LPCPLUS,XDP_CONN

K6_DEVEL:PVT

K6_DEVEL:ENG

K6_PROGPARTS

K6_DEBUG:PROD

K6_COMMON

K6_MISC

PCBA,MLB_LDO,BETTER,K6

PCBA,MLB_LDO,BEST,K6

085-1634

K6_DEVEL:PVT

U1000

1

337S3756

CPU:2.53GHZ

PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA

MCP89M:A01

1

337S3797 CRITICAL

IC,MCP89M-A01,31X31MM,BGA1168

U1400

U3990

1

BCM5764MCRITICAL341S2731

IC,1MBIT,SPI FLASH,K17/18

IC,FW643-E2,1394B PHY/OHCI LINK/PCI-E,12

338S0753

1

U4100

CRITICAL

[EEEE_DD23]

EEEE:DD23

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

[EEEE_DD24]

EEEE:DD24

CRITICAL

1

826-4393

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL

1

337S3866

MCP89M:A02

IC,MCP89M-A01,31X31MM,BGA1168

U1400

DEVEL_BOM

CRITICAL

DEVEL

1

085-1634

K6 MLB_LDO DEVELOPMENT BOM

CRITICAL

639-1120 639-1119

DEVEL_BOM,SMC_DEBUG:YES,XDP

CRITICAL

K6_COMMON,CPU:2.66GHZ,MCP89M:A02,EEEE:DD23

K6_COMMON,CPU:2.4GHZ,MCP89M:A02,EEEE:DD24

COMMON,ALTERNATE,K6_MISC,K6_DEBUG:PROD,KB_BL,K6_PROGPARTS,RDRV:NO,SPI:25MHZ,CPU_CAP:15

BOOTROM:UNLOCKED,SMC:PROG,IR:PROG,WELLSPRING:PROG

DP_ESD,MIKEY,BCM5764M,GL137,ENET_ESD,VFRQ:SLPS3,LVDDR3:YES,MCPPLL_R:REG,S0PGOOD_BJT,BOOST_VOL:LOW,HDA:1.5V

K6 MLB_LDO DEVELOPMENT BOM

DEVEL_BOM,BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO

BKLT:ENG,BMON:ENG,XDP_CONN,LPCPLUS,VREFMRGN:YES,EFI_DEBUG,S0PGOOD_ISL,RDRV:IN_DEVEL

BKLT:PROD,BMON:PROD,SMC_DEBUG:YES,XDP,VREFMRGN:NO,LPCPLUS,MCPHVDD:P2V5,LDO:FIXED,HTOL_SENSE:YES

IC,CYPRS,CY7C63803-LQXC,4X4MM,USB,24-QFN

338S0563

516-0213

516S0706

MOLEX AS ALTERNATE

TOKO AS ALTERNATE

INTEL P7550 CPU AS ALTERNATE

152S0586

337S3704

ALL

SSM6P15FE AS ALTERNATE

376S0360376S0699

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II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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PAGE TITLE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

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C

345678

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8 7 5 4 2 1

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

Revision History

SYNC_MASTER=K24_MLB

5 OF 109

A.13.0

051-8563

5 OF 80

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

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8 7 5 4 2 1

(NEED TO ADD 6 GND TP)

(NEED 3 TP)

KBD BACKLIGHT CONN

(NEED TO ADD 2 GND TP)

(NEED 4 TP)

(NEED TO ADD 6 GND TP)

(NEED 3 TP)

BATT POWER CONN

(NEED TO ADD 4 GND TP)

(NEED TO ADD 5 GND TP)

(NEED TO ADD 2 GND TP)

T57 CONN

(NEED TO ADD 1 GND TP)

RIGHT CLUTCH CONN

(NEED TO ADD 4 GND TP)

IPD_FLEX_CONN

(NEED 3 TP)

(NEED TO ADD 5 GND TP)

BIL CONN

SATA HDD/IR/SIL

SATA ODD CONN

SPEAKER FUNC_TEST

LVDS FUNC_TEST

(NEED TO ADD 4 GND TP)

(NEED 2 TP)

Fan Connectors

DEBUG VOLTAGE

(NEED TO ADD 5 GND TP)

Functional Test Points

KEYBOARD CONN

DC POWER CONN

(NEED TO ADD 4 GND TP)

FSB SIGNALS WITH NOTEST

(NEED TO ADD 3 GND TP)

MIC FUNC_TEST

(NEED 2 TP)

SPI DEBUG CONN

I12

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FUNC TEST

SYNC_MASTER=K24_MLB

FSB_REQ_L<4..0>

NO_TEST=TRUE

FSB_LOCK_L

NO_TEST=TRUE

FSB_DSTB_L_P<3..0>

NO_TEST=TRUE

FSB_DSTB_L_N<3..0>

TRUE

PM_SLP_S4_L

SMC_PM_G2_EN

TRUE

PP1V5R1V35_S3

TRUE

PP4V5_AUDIO_ANALOG

TRUE

PP3V3_S0_LCD_F

TRUE

PP3V3_LCDVDD_SW_F

TRUE

PP18V5_S3

TRUE

PP5V_S0_HDD_FLT

TRUE

PPBUS_G3H

TRUE

PP3V42_G3H

TRUE

PP1V5_S0

TRUE

PP3V3_S3

TRUE

WS_KBD3

TRUE

WS_KBD6 WS_KBD7

TRUE

PCIE_AP_D2R_N

PCIE_CLK100M_AP_CONN_P

TRUE

USB_CAMERA_CONN_P

USB_BT_CONN_N

TRUE

AP_RESET_CONN_L

TRUE

PP3V3_S3

TRUE

PP18V5_S3

TRUE

Z2_CS_L

TRUE

Z2_DEBUG3

TRUE

Z2_RESET

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

PP5V_WLAN

TRUE

PP3V3_ENET

SPI_CLK

TRUE TRUE

SPI_MOSI

TRUE

PP5V_S0

TRUE

FAN_RT_PWM FAN_RT_TACH

TRUE

WS_KBD2

TRUE

SPIROM_USE_MLB

TRUE

SPI_MISO

TRUE

PP5V_SW_ODD

PP5V_WLAN

TRUE

WS_KBD1

TRUE

PSOC_SCLK

TRUE

Z2_CLKIN

Z2_HOST_INTN

TRUE

Z2_SCLK

Z2_MISO

TRUE

Z2_MOSI

TRUE

Z2_BOOST_EN

TRUE

PSOC_F_CS_L

WS_KBD11

TRUE

WS_KBD13

TRUE

WS_KBD4

TRUE

WS_KBD5

TRUE

PP3V3_S5

TRUE

PP5V_S3 PP0V9_S5

TRUE

PP3V3_S3

TRUE

PP1V8_S0 PP3V3_S0

TRUE

WS_KBD_ONOFF_L

TRUE

PP1V05_S0

TRUE

WS_KBD20

TRUE

WS_KBD22

TRUE

WS_KBD18

TRUE

BI_MIC_LO

TRUE

WS_KBD14

TRUE

WS_KBD16_NUM

WS_KBD15_CAP

TRUE

WS_KBD17

TRUE

IR_RX_OUT

TRUE

WS_LEFT_OPTION_KBD

WS_KBD21

TRUE

SPKRAMP_R_N_OUT

TRUE

SPKRAMP_L_N_OUT

TRUE

BI_MIC_HI BI_MIC_SHIELD

TRUE

PP5V_SW_ODD

TRUE

SATA_HDD_D2R_C_P

TRUE

SMC_ODD_DETECT

TRUE TRUE

SATA_ODD_D2R_UF_P

SATA_ODD_D2R_UF_N

TRUE

SATA_ODD_R2D_N

TRUE

PP5V_S0_HDD_FLT

TRUE

SATA_HDD_R2D_N

TRUE

SATA_HDD_D2R_C_N

TRUE

PP5V_S3_IR_R

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD23

WS_KBD19

TRUE

PCIE_WAKE_L

TRUE

SPKRAMP_SUB_P_OUT

SPKRAMP_SUB_N_OUT

TRUE

SPKRAMP_R_P_OUT

TRUE

LVDS_IG_A_DATA_P<1>

TRUE

SYS_DETECT_L

TRUE

SMBUS_SMC_BSA_SCL

TRUE

PP3V3_LCDVDD_SW_F

TRUE

LED_RETURN_1

TRUE

SMBUS_SMC_A_S3_SDA

WS_CONTROL_KBD

TRUE

LVDS_IG_A_DATA_N<2>

TRUE

LVDS_CONN_A_CLK_F_P

USB_T57_P

TRUE

T57_RESET

PP5V_S3_BTCAMERA_F

TRUE

SPKRAMP_L_P_OUT

TRUE

SMBUS_SMC_A_S3_SCL

PCIE_AP_D2R_P

TRUE

PPVCORE_S0_CPU

PCIE_AP_R2D_P

TRUE

PCIE_AP_R2D_N

TRUE

PPVCORE_S0_MCP

TRUE

PP1V2_ENET

TRUE

PP5V_S0

TRUE

LVDS_CONN_A_CLK_F_N

TRUE

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_N<0>

TRUE

LVDS_DDC_CLK

TRUE

BKL_VSYNC

TRUE

PPVOUT_SW_LCDBKLT

TRUE

PP3V3_S0_LCD_F

TRUE

LVDS_IG_A_DATA_P<0>

LVDS_DDC_DATA

TRUE

BKL_ISEN2

TRUE

Z2_KEY_ACT_L

TRUE

PP5V_S3

TRUE

T57_PWR_EN

TRUE

PP3V3_S3

TRUE

PICKB_L

TRUE

PSOC_MISO

TRUE

PSOC_MOSI

TRUE

SMBUS_SMC_A_S3_SCL

USB_T57_N

TRUE

PPVBAT_G3H_CONN

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SMC_LID_R

TRUE

SMC_BIL_BUTTON_L

TRUE

SMBUS_SMC_BSA_SDA

TRUE

SMBUS_SMC_BSA_SCL

TRUE

PP3V42_G3H

TRUE

PCIE_CLK100M_AP_CONN_N

TRUE

USB_CAMERA_CONN_N

TRUE

USB_BT_CONN_P

TRUE

AP_CLKREQ_Q_L

LVDS_IG_A_DATA_N<1>

TRUE

SYS_LED_ANODE_R

TRUE

SATA_HDD_R2D_P

TRUE

SATA_ODD_R2D_P

TRUE

PP3V42_G3H

TRUE

BKL_ISEN3 LED_RETURN_4

TRUE

LED_RETURN_5

TRUE TRUE

LED_RETURN_6

WS_KBD12

TRUE

KBDLED_ANODE

TRUE

SMC_KDBLED_PRESENT_L

TRUE

SPI_CS0_L

WS_KBD10

TRUE

WS_KBD9

TRUE

WS_KBD8

TRUE

PP3V42_G3H

TRUE

PM_SLP_S3_L

TRUE

PP18V5_DCIN_FUSE

TRUE

ADAPTER_SENSE

FSB_HITM_L

NO_TEST=TRUE

FSB_HIT_L

NO_TEST=TRUE

FSB_DINV_L<3..0>

NO_TEST=TRUE

FSB_D_L<63..0>

NO_TEST=TRUE

FSB_ADSTB_L<1..0>

FSB_ADS_L

NO_TEST=TRUE

FSB_A_L<35..3>

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9

13 72

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39 65

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79

51

6

67

6

67

6

48

6

36

7

43

6 7

7

65 79

6 7

47

15 29 74

29 79

29

6 7

6

48

47 48

6

42 78

6

29

7

41 75

6 7

65

46

47

18 41 50

18 41 75

6 8

6

29

47

47 48

48

47 48

47

7

65 79

6 7

7

6 7

7

65 79

47

7

65

47

55 56

47

36 38

47

54 55

55 56

6 8

36 74

36 39

36 79

36 74

6

36

36 74

36

47

15 24 29

54 55

8

67 74

57

6

42 78

6

67

67 70

6

42 78

47

8

67 74

67 79

38 75

18

29

54 55

6

42 78

15 29 74

7

43

29 74

7

43

7

6 7

65

67 79

8

67 74

8

67 74

8

67

67 70

6

67

8

67 74

8

67

70

47 48

6 7

18

6 7

47 48

6

42 78

38 75

57 58

6

42 78

57

39 40 57

6

42 78

6

42 78

6 7

29 79

29

8

67 74

36

36 74

6 7

70

67 70

47

48

41 75

47

6 7

18 39 65 69

57

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

9

13 72

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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PAGE TITLE

C

A

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

(CPU VCORE PWR)

"S0,S0M" RAILS

(MCP VCORE AFTER SENSE RES)

700 mA max output

"FIREWIRE" RAILS

"S5" RAILS

(BEFORE HIGH SIDE SENSING RES.)

139 mA/ 0 mA

105 mA/241 mA

LVDDR VRef/VTT (0.75V/0.675V) Rails

"ENET" RAILS

(SINCE PE0[3:0] IS NOT USED ON K6)

"S3" RAILS

LVDDR (1.5V/1.35V) Rails

4250 mA

(CONNECTS TO MCP BALLS)

& CPU VTT SENSING RES.)

(AFTER HIGH SIDE CPU VCORE

0.9V Rails

(BCM5764M)

"G3H" RAILS

(OR 1.35V)

0 mA

~400mA

(CONNECTS TO MCP BALLS)

(BCM57765)

(CONNECTS TO THE DECAPS)

UNUSED MCP PE0[3:0] AVDD/DVDD

(CONNECTS TO THE DECAPS)

400mA

~100mA

300mA

I1086

Power Aliases

SYNC_MASTER=K24_MLB

SYNC_DATE=07/22/2009

=PP3V3_S0_OPA333

=PP3V3_S0_XDP =PP3V3_S0_MCP

=PP3V3_S0_IMVP

=PP3V3_S0_CPUTHMSNS

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0_MCP_PLL_UF

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

MIN_LINE_WIDTH=0.4 mm

PP1V2_ENET

MAKE_BASE=TRUE

=PP1V2_ENET_PHY

=PP3V3_ENET_FET_R

=PP3V3_ENET_MCP_RMGT

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 MM

PP1V8_S0

=PP0V9_ENET_MCP_RMGT

=PP3V3_ENET_MCP_PLL_MAC

=PP3V3_S5_REG

=PP3V3_S5_P0V9S5

=PP3V3_S5_ROM =PP3V3_S5_LCD

=PP5V_S3_T57

=PP5V_S0_CPU_IMVP

=PPVCORE_S0_MCPGFXFET

=PPVCORE_S0_MCP

=PP5V_S3_WLAN

=PP5V_S3_TPAD

=PP5V_S3_SYSLED

=PP3V3_S3_SMBUS_SMC_A_S3

=PPVCORE_S0_CPU

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_SW_MCP_FSB

=PP1V05_S0_MCP_M2CLK_DLL

=PPLVDDR_S3_MEM_B

=PP1V05_FW_P1V0FWFET

=PP1V05_S0_MCP_PLL_UF_R

=PP1V5_S0_REG

=PP1V05_S0_MCP_DP0_VDD

=PP1V05_S0_FWPWRCTL

=PP1V05_S0_MCP_PLL_IFP

=PPBUS_S5_CPUREGS_ISNS_R

=PP1V05_S0_MCP_PE_AVDD0

=PP1V8_S0_AUDIO

=PP1V2_ENET_PHY_REG

=PP1V05_S0_MCP_PE_DVDD

=PP1V05_S0_MCP_PLL_UF

=PP3V3_S3_PDCISENS

=PPVIN_S0_CPUVTTS0

=PP1V5R1V35_S0_MCPDDRFET =PPVIN_S0_DDRREG_LDO

=PPVIN_S5_3V3S5 =PPVIN_S3_5VS3

=PPDCIN_S5_CHGR

=PPVP_FW_PHY_CPS_FET

=PP1V2_ENET_REG

=PP1V5R1V35_S3_MCP_MEM

=PP3V42_G3H_REG

=PPLVDDR_S3_MEM_A

=PPBUS_FW_FET

=PPBUS_S5_CPUREGS_ISNS

=PPVIN_S5_CPU_IMVP

=PP1V0_FW_FET_R

=PP3V3_FW_FWPHY

=PPVP_FW_PORT1

=PP3V42_G3H_BMON_ISNS

=PPDDR_S3_REG

=PP3V3_S5_P3V3S0FET

=PP0V9_ENET_FET

=PP3V3R1V8_S0_MCP_IFP_VDD

=PPBUS_S0_LCDBKLT

=PPBUS_G3H

=PP5V_S3_REG

=PP0V9_S5_REG

=PP0V9_ENET_P0V9ENETFET

=PP0V9_S5_MCP_VDD_AUXC

=PP1V0_FW_FWPHY

=PP5V_S3_BTCAMERA

=PP3V3_FW_FET

=PP1V05_S0_MCP_PLL_OR

=PPMCPCORE_S0_REG

=PP5V_S3_MCPDDRFET

=PP3V3_S5_MCPPWRGD

=PP3V3_FW_P3V3FWFET

=PP3V3_S5_P3V3ENETFET =PP3V3_S5_DP_PORT_PWR

=PP3V3_S5_MCP

=PP1V05_S0_MCP_PE_DVDD0

=PP1V05_S0_MCP_PE_DVDD

=PPVTT_S0_DDR_LDO

=PPDDRVTT_S0_MEM_A

=PP1V8_S0_REG

=PPVTT_S3_DDR_BUF

=PP3V3_S3_FET

=PP5V_S0_FET

MIN_NECK_WIDTH=0.3 MM

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=12.6V

PPBUS_S5_IMVP_VTT_ISNS

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V5R1V35_S3

PPVP_FW

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=12.6V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_FW

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

PP1V05_FW

VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

PPDDRVREF_S3

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.75V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.3 mm

PP1V05_S0_MCP_PE_AVDD

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=0.9V

PP0V9_S5

MIN_LINE_WIDTH=0.4 mm

=PP3V3_S0_TPAD

=PP18V5_DCIN_CONN

=PP5V_S3_IR

=PP5V_S3_DDRREG

MIN_NECK_WIDTH=0.2 mm

PP3V3_ENET

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_ENET_PHY =PP3V3_ENET_PWRCTL

=PP5V_S3_AUDIO

=PP3V3_S0_P1V5S0 =PP3V3_S0_DEBUGROM

=PP3V3_S0_DPCONN =PPSPD_S0_MEM_A

=PP3V3_S0_CPUVTTISNS

=PP3V3_S0_FWLATEVG

=PPDDRVTT_S0_MEM_B

PPDDRVTT_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=0.75V MAKE_BASE=TRUE

=PP3V3_S0_PWRCTL

=PP3V3_S0_MCP_PLL_UF

=PP3V3_S0_MCP_HVDD =PP3V3_S0_SMC =PP3V3_S0_MCPTHMSNS

=PP1V5_S0_SATARDRVR

=PP1V8R1V5_S0_AUDIO

=PP1V5_S0_CPU

=PP1V5_S0_MCP_PLL_VLDO

MAKE_BASE=TRUE

PP1V5_S0

MIN_LINE_WIDTH=0.6 MM MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V

=PP1V5_S0_MCP_HDA_R

=PP3V3_S0_MCPCOREISNS

=PP1V5_S0_AUDIO_R

=PP3V3_S0_MCP_HDA_R

=PP3V3_S0_ENETPHY

=PP3V3_S0_ODD

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_SMBUS_MCP_1 =PP3V3_S0_P1V8S0

=PP3V3_S0_MCPDDRISNS =PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_SMBUS_MCP_0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.3 MM

PPBUS_G3H

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

=PP3V42_G3H_BATT

=PP3V42_G3H_TPAD

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_ONEWIRE

=PPVIN_S0_MCPCORE =PPVIN_S3_DDRREG

=PPBUS_S5_FWPWRSW

=PP5V_S3_AUDIO_AMP =PP5V_S3_P5VS0FET =PP5V_S0_ODD

=PP3V3_S5_MCP_GPIO

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_P0V9ENETFET

=PP3V3_S5_VMON =PP3V3_S5_SMBUS_SMC_MGMT

=PP3V3_S0_MCP_GPIO

=PP3V3_S0_LCD

=PP5V_S3_RTUSB

PP5V_S3

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_S5

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_S3

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

=PP3V3_S3_VREFMRGN =PP3V3_S3_WLAN =PP3V3_S3_MCP_GPIO =PP3V3_S3_TPAD =PP3V3_S3_SMS =PP3V3_S3_CARDREADER =PP3V3_S3_T57 =PP3V3_ENET_P1V2ENET

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_SMBUS_SMC_0_S0

=PPSPD_S0_MEM_B

=PP3V3_S0_AUDIO_R

=PP3V3_S0_SDCONN

=PP3V3_S0_FWPWRCTL

=PP5V_S0_HDD

=PP5V_S0_KBDLED =PP5VR3V3_S0_DPCADET =PP5V_S0_CPUVTTS0

=PP5V_S0_MCPREG =PP5V_S0_MCPFSBFET

=PP3V3_S0_AUDIO

=PP3V3_S0_FAN_RT

MAKE_BASE=TRUE

PP3V3_S0

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PP3V3_S0_FET

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_FSB

PPVCORE_S0_MCP

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.3 MM

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=1.25V

=PPVCORE_S0_CPU_REG

=PPCPUVTT_S0_REG

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V05_S0

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=1.05V

=PP1V05_S0_CPU

=PP1V05_S0_MCP_PE_DVDD1

=PP1V05_S0_MCP_PE_AVDD1

MIN_NECK_WIDTH=0.2 mm MAKE_BASE=TRUE

VOLTAGE=0.9V

PP0V9_ENET

MIN_LINE_WIDTH=0.4 mm

=PP5V_S0_LPCPLUS =PP5V_S0_FAN_RT

=PP5V_S0_BKL

PP5V_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

VOLTAGE=5V

=PP3V42_G3H_PWRCTL

=PP3V42_G3H_SMBUS_SMC_BSA

=PPVIN_S5_SMCVREF

=PP3V3_S5_LPCPLUS

=PP3V3_S5_SMC

=PP3V42_G3H_CHGR

PP3V3_G3_RTC

PP3V42_G3H

VOLTAGE=3.42V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

=PP3V42_G3H_OPA330

PPDCIN_S5_S5

MIN_LINE_WIDTH=0.6 MM

VOLTAGE=18.5V

MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

8 OF 109

A.13.0

051-8563

7 OF 80

22

12

19 22

61

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19 22

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64

50

67

38

61

21

19 22

29

48

40

42

10 11

19 22

14 22

26

34

64

16 23

34

16 23

44

19

64

7 22

22

60

63

20

60

59

58

35

64

14

57

25

34

44

61

34

33 34 35

35

44

60

66

16 23

71

58

59

64

66

19 22

33 34

29

34

64

62

20

24

34

66

69

19 22

19

7

22

60

25

64

28 60

66

6

79

22

6

48

57

36 38

60

6

24 31 64

65

51 53 55

64

41

69

25

44

34 35

26

65

22

19 22

40

45

36

51

10 11

6

65 79

8

44

8

31

36

70

42

64

44

42

6

43

57

47

37

57

62

60

34

54

66

36

17 18

66

65

42

16 17 18

67

37

6

65 79

6

28

29

18

47 48

49

30

38

64

42

26

8

30

34

36

48

69

63

62

21

51 55 56

46

6

65 79 66

22

13 19 22

6

43

6

43 61

63

6

65

9

10 11 12 61

19

41

46

70

6

65

42

40

41

39 40

58 65

18 19 22

6

22

OUT OUT OUT OUT

OUT

BI

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DISPLAY PORT ALIASES

AUDIO ALIASES

MCPCOREISNS SIGNAL

LEFT OF CPU

BACKLIGHT CONTROLLER ALIASES

5V ODD ALIASES

BELOW CPU

CPU ALIASES

266

UNUSED GPU LANES

BELOW MCP

ABOVE CPU

FAN STANDOFF

PCI-E ALIASES

EMI TALL POGO PINS

FSB MHZ

200

133

BSEL<2..0>

0 0 1

0 0 0

(RSVD)

100

(400)1 1 0

1 0 1

1 0 0

333

0 1 0 0 1 1 (166)

USB ALIASES

1 1 1

EMI IO (SHORT) POGO PINS

MCP89 ALIASES

UNUSED USB PORTS

MLB MOUNTING (TO TOPCASE) SCREW HOLES

HEATSINK STANDOFFS

ETHERNET ALIASES

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

DACS ALIASES

LVDS ALIASES

UNUSED CRT & TV-OUT INTERFACE

CHARGER SIGNAL

17 76

17

5%

10K

1/16W MF-LF

R0984

402

MF-LF 402

10K

5% 1/16W

R0983R0982

MF-LF

1/16W

5%

10K

402

R0981

10K

402

5% 1/16W MF-LF

R0980

MF-LF

1/16W

5%

402

10K

39 40 57 58

PLACE_NEAR=L9701.1:5MM

402

MF-LF

5%

0

R0910

1/16W

100K

R0920

1/16W

MF-LF

5%

402

R0911

0

5%

MF-LF

1/16W

402

PLACE_NEAR=U7980.A1:5MM

7

HDA:1.5V

40205%

MF-LF1/16W

R0912

402

5%

MF-LF

0

1/16W

HDA:3.3V

R0913

0

4025%1/16W MF-LF

HDA:1.5V

R0914

HDA:3.3V

402

1/16W MF-LF

0

5%

R0915

402

MF-LF

1/16W

10K

5%

R0986

NO STUFF

18 31

OMIT

3R2P5

Z0912

3R2P5

Z0909

OMIT

Z0911

3R2P5

OMIT

Z0908

3R2P5

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0901

Z0904

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0902

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0903

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0905

3R2P5

OMIT

Z0910

SM

ZS0905

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0906

SM

2.0DIA-TALL-EMI-MLB-M97-M982.0DIA-TALL-EMI-MLB-M97-M98

ZS0904

SM

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0907

SM

Z0907

3R2P5

OMITOMIT

3R2P5

Z0906

1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0900

SM SM

1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0901 ZS0902

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

1.4DIA-SHORT-EMI-MLB-K19-K24

SM

ZS0903 ZS0908

1.4DIA-SHORT-EMI-MLB-K19-K24

SM SM

1.4DIA-SHORT-EMI-MLB-K19-K24

ZS0909

SIGNAL ALIAS

SYNC_MASTER=K24_MLB

ENET_RXD<2>

ENET_RX_CTRL

ENET_RXD_PD

MAKE_BASE=TRUE

DP_EXT_HPD

MAKE_BASE=TRUE

DP_IG_HPD0

DP_IG_ML0_N<0..3>

DP_IG_ML0_P<0..3>

DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N

=MCP_IFPAB_DDC_CLK

LCD_IG_BKLT_PWM

=MCP_IFPB_TXD_N<0..3>

=MCP_IFPA_TXD_N<3>

=MCP_IFPA_TXC_N

CRT_IG_HSYNC

MCP_CLK27M_XTALIN

MCP_TV_DAC_VREF

MCP_TV_DAC_RSET

CRT_IG_R_C_PR

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_HSYNC

=MCP_IFPA_TXD_N<0..2>

=MCP_IFPB_TXC_P

=MCP_IFPAB_DDC_DATA

DP_IG_ML1_N<0..3> DP_IG_AUX_CH1_P DP_IG_AUX_CH1_N

TP_DP_IG_AUX_CH1P

MAKE_BASE=TRUE

TP_DP_IG_ML1P<0..3>

MAKE_BASE=TRUE

DP_CA_DET

DP_AUX_CH_C_P

LCD_IG_BKLT_EN

=MCP_IFPB_TXC_N

TP_PEG_CLKREQ_L

MAKE_BASE=TRUE

=PP3V3_ENET_FET_R

TP_DP_IG_AUX_CH1N

MAKE_BASE=TRUE

DP_EXT_AUX_CH_C_P

DP_IG_AUX_CH_N

MAKE_BASE=TRUE

USB_EXTC_N

TP_MCP_RGB_RED TP_MCP_RGB_GREEN TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC

TP_MCP_RGB_DAC_RSET

PPBUS_SW_LCDBKLT_PWR

USB_EXTD_P

TP_MCP_RGB_VSYNC

=PP5V_SW_ODD_FET

TP_MCP_RGB_DAC_VREF

CPU_PECI_MCP

MCP_CLK27M_XTALOUT

=PEG_R2D_C_P<3:0>

=PEG_D2R_P<3:0> =PEG_R2D_C_N<3:0>

PEG_CLK100M_P PEG_CLK100M_N

CRT_IG_VSYNC

USB_WM_N

USB_MINI_P

USB_EXTD_N USB_WM_P

USB_EXTC_P

PEG_CLKREQ_L

CRT_IG_G_Y_Y

=PEG_D2R_N<3:0>

=MCP_BSEL<0:2>

=PPBUS_SW_BKL

=PP5V_SW_ODD

=MCP_IFPA_TXD_P<0..2>

=MCP_IFPA_TXC_P

=MCP_IFPA_TXD_P<3>

=MCP_IFPB_TXD_P<0..3>

CRT_IG_B_COMP_PB

NC_MCP_CLK27M_XTALIN

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_N<0..2>

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

LCD_BKLT_PWM

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATAN<0..3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_B_CLKN

NO_TEST=TRUE

MAKE_BASE=TRUE

LCD_BKLT_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_IG_A_DATAP<3>

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_CLK27M_XTALOUT NC_CRT_IG_R_C_PR

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_RED

MAKE_BASE=TRUE

DP_IG_AUX_CH_P

MAKE_BASE=TRUE

DP_EXT_AUX_CH_C_N

DP_EXT_CA_DET

MAKE_BASE=TRUE

DP_EXT_ML_P<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_BLUE

NC_MCP_RGB_GREEN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_R2D_C_P<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_USB_WMP

MAKE_BASE=TRUE

NC_MCP_TV_DAC_RSET

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_VSYNC

MAKE_BASE=TRUE

NC_PEG_R2D_C_N<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_P<3:0>

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

MAKE_BASE=TRUE

TP_PEG_CLK100M_P

MAKE_BASE=TRUE

TP_PEG_CLK100M_N

MAKE_BASE=TRUE

TP_USB_WMN

MAKE_BASE=TRUE

TP_USB_MINIP

MAKE_BASE=TRUE

TP_USB_EXTDN

TP_USB_EXTCN

MAKE_BASE=TRUE

TP_USB_EXTCP

MAKE_BASE=TRUE

TP_USB_EXTDP

MAKE_BASE=TRUE

NC_MCP_RGB_VSYNC

NO_TEST=TRUE

NC_MCP_RGB_DAC_RSET

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_A_DATA_P<0..2>

MAKE_BASE=TRUE

LVDS_IG_A_CLK_N

CPU_BSEL<0:2>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_DAC_VREF

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_MCP_RGB_HSYNC

MAKE_BASE=TRUE

NC_PEG_D2R_N<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

VOLTAGE=5V

MIN_NECK_WIDTH=0.4 MM

MIN_LINE_WIDTH=0.6 MM

PP5V_SW_ODD

MAKE_BASE=TRUE

TP_DP_IG_ML1N<0..3>

MAKE_BASE=TRUE

DP_EXT_ML_N<0..3>

NC_LVDS_IG_B_DATAP<0..3>

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_DDC_CLK

MAKE_BASE=TRUE

LVDS_DDC_DATA

MAKE_BASE=TRUE

USB_MINI_N

TP_USB_MININ

MAKE_BASE=TRUE

PPBUS_SW_BKL

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.375 MM VOLTAGE=12.6V

ENET_MDIO

ENET_RXD<1>

ENET_RXD<3>

MAKE_BASE=TRUE

ENET_RXCLK_PD

ENET_CLK125M_RXCLK

=PP3V3_ENET_FET

ENET_RXD<0>

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM VOLTAGE=3.3V

MIN_LINE_WIDTH=0.6 MM

PP3V3_ENET_FET

=MCPCOREISNS_P

=MCPCOREISNS_N

SMC_BC_ACOK

MAKE_BASE=TRUE

MCPCOREISNS_N

MAKE_BASE=TRUE

MCPCORES0_VO

MCPCOREISNS_P

MAKE_BASE=TRUE

MCPCORES0_ISP_R

=CHGR_ACOK

DP_IG_HPD1

=PP3V3R1V5_S0_MCP_HDA

=PP3V3R1V5_S0_AUDIO

VOLTAGE=1.5V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_MCP_HDA_R

=PP1V5_S0_AUDIO_R

=PP3V3_S0_AUDIO_R

=PP1V5_S0_MCP_HDA_R

DP_IG_ML1_P<0..3>

DP_AUX_CH_C_N

DP_IG_ML_N<0..3>

DP_IG_ML_P<0..3>

VOLTAGE=1.5V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.6mm

PP3V3R1V5_S0_AUDIO

ENET_LOW_PWR

MCP_RGMII_VREF

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

9 OF 109

A.13.0

051-8563

8 OF 80

1

2

121

2

121

2

1 2

1

1 11 1

11

1 1 1

69 16

16

74

16

68

16

69 79

68 74

17 75

16

70 71

17 75

16

36

16

13

15

15 74

74

17 75

15

74

15

13

70

36

16

74

67 74

6

67 74

70

71

68 74

69 79

69

69 79

6

67 74

9

72

6

69 79

6

67

6

67

17 75

66

44

44 62

62

16

18 22

51

7

16

68

74

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPU JTAG Support

R1023.1:

R1020.1: R1021.1: R1022.1:

PLACE_NEARs:

R1006.1: C1014.1:

R1005.2:

R1000

402

MF-LF

1/16W

1%

54.9

R1002

402

MF-LF

1/16W

5%

68

R1005

U1000.AD26:12.7 mm

402

MF-LF

1/16W

1%

1K

R1006

U1000.AD26:12.7 mm

402

MF-LF

1/16W

1%

2.0K

R1023

U1000.Y1:12.7 mm

54.9

1/16W

402

MF-LF

1%

R1022

U1000.AA1:12.7 mm

402

MF-LF

1/16W

1%

27.4

R1021

U1000.U26:12.7 mm

402

MF-LF

1/16W

1%

54.9

R1020

U1000.R26:12.7 mm

27.4

1/16W 402

MF-LF

1%

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

13 61 72

13 72

61

12 13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

8

72

8

72

8

72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

6

13 72

12 72

9

12 72

12 24

13 40 61 72

45 79

13 40 72

13 72

12 13 72

13 72

9

12 72

9

12 72

9

12 72

9

12 72

45 79

13 72

R1010

1/16W

NO STUFF

0

MF-LF

5%

402

R1011

NO STUFF

402

MF-LF

1/16W

5%

1K

R1001

402

MF-LF

1/16W

1%

54.9

R1090

54.9

1/16W MF-LF

1%

402

R1091

54.9

1/16W MF-LF

1%

402

R1093

54.9

1/16W MF-LF

1%

402

6

13 72

6

13 72

6

13 72

6

13 72

R1094

649

1/16W MF-LF

1%

402

R1012

NO STUFF

402

MF-LF

1/16W

5%

1K

C1014

16V X5R

U1000.AF26:12.7 mm

NO STUFF

10%

402

0.1uF

U1000

FCBGA

PENRYN

OMIT

R1092

PLACE_NEAR=J1300.51:12.7 mm

1/16W MF-LF

54.9

1%

402

U1000

OMIT

PENRYN

FCBGA

CPU FSB

SYNC_MASTER=T27_MLB

SYNC_DATE=08/27/2009

FSB_D_L<16>

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<1>

FSB_D_L<63>

CPU_COMP<0>

TP_CPU_RSVD_D3

TP_CPU_RSVD_D22

TP_CPU_RSVD_D2

TP_CPU_RSVD_F6

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_IGNNE_L

CPU_THERMD_N

FSB_A_L<25>

FSB_A_L<11>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<20>

FSB_BPRI_L

FSB_A_L<12> FSB_A_L<13>

FSB_ADSTB_L<0>

FSB_A_L<17> FSB_A_L<18> FSB_A_L<19>

FSB_A_L<28> FSB_A_L<29> FSB_A_L<30> FSB_A_L<31> FSB_A_L<32> FSB_A_L<33> FSB_A_L<34> FSB_A_L<35> FSB_ADSTB_L<1>

CPU_FERR_L

CPU_STPCLK_L CPU_INTR CPU_NMI CPU_SMI_L

TP_CPU_RSVD_M4 TP_CPU_RSVD_N5 TP_CPU_RSVD_T2 TP_CPU_RSVD_V3 TP_CPU_RSVD_B2

FSB_BNR_L

FSB_DEFER_L FSB_DRDY_L FSB_DBSY_L

FSB_BREQ0_L

FSB_CPURST_L FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2> FSB_TRDY_L

FSB_HIT_L FSB_HITM_L

XDP_BPM_L<1> XDP_BPM_L<2> XDP_BPM_L<3> XDP_BPM_L<4>

XDP_TCK XDP_TDI XDP_TDO XDP_TMS XDP_TRST_L XDP_DBRESET_L

CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_A_L<16>

FSB_A_L<14>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<6>

CPU_A20M_L

CPU_INIT_L

FSB_LOCK_L

FSB_D_L<10>

FSB_D_L<15> FSB_DSTB_L_N<0>

FSB_D_L<3> FSB_D_L<4>

FSB_D_L<17>

CPU_PSI_L

FSB_CPUSLP_L

CPU_PWRGD

FSB_DPWR_L

CPU_DPSLP_L

CPU_DPRSTP_L

FSB_DINV_L<3>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<48>

FSB_DINV_L<2>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_D_L<47>

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<44>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<39>

FSB_D_L<38>

FSB_D_L<37>

FSB_D_L<35>

FSB_D_L<34>

FSB_D_L<33>

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

TP_CPU_TEST5

TP_CPU_TEST3

FSB_DSTB_L_N<1>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<5>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<32>

FSB_D_L<0>

FSB_D_L<18> FSB_D_L<19>

FSB_D_L<6> FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<25>

FSB_D_L<30> FSB_D_L<31>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

TP_CPU_TEST6

TP_CPU_TEST7

CPU_IERR_L

XDP_BPM_L<5>

CPU_PROCHOT_L

XDP_TMS

XDP_TDI

CPU_GTLREF

XDP_TCK

XDP_TRST_L

=PP1V05_S0_CPU

XDP_BPM_L<0>

FSB_CLK_CPU_N

XDP_TDO

CPU_TEST2

CPU_TEST1

CPU_TEST4

FSB_D_L<43>

FSB_D_L<36>

10 OF 109

A.13.0

051-8563

9 OF 80

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1 2

1

2

1

2

1 2

1

2

1

C3

A26

M26 N24

N25

T25

P23

J23 H22 F26 K22

H26 H25

G24

K24

E23

E25

R23

P26

E22

Y22 F24 E26

G25

N22

L23 M24 L22 M23 P25

P22 T24 R24 L25

L26

AD26

C24

AF26

AF1

B22 B23 C21

AB24

V24

V26

V23

T22

U25

U23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

Y26

AA26

U22

AE24

AD24

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

AC22

AD23

AF22

AC23

AE25

AF24

AC20

R26

U26

AA1

Y1

E5

B5

D24

D6

D7

AE6

K25

F23

G22

J26

H23

J24

D25

C23

1 2

H4

B3

A6

K5

J4 L5

P4

R1

K3 H2 K2 J3 L1

A21

A22

C7

A24

D21

C20

AB6

AB5

AB3

AA6

AC5

AC1

AC2

AC4

AD1

AD3

AD4

E4

G6

G2

G3

F4

F3

C1

D20

F1

E1

F21

H5

E2

B2

V3

T2

N5

M4

A3

B4

C6

D5

A5

V1

AA3

AB2

AA4

W3

V4

U2

Y4

W5

R3

U5

Y2

M1

L2

P2

G5

W6 U4 Y5 U1 R4

T3 W2

J1

N2

M3

P5

T5

B25

C4

H1

N3

P1

L4

F6 D2

D22

D3

72

9

12 72

9

12 72

28 72

9

12 72

9

12 72

7

10 11 12 61

9

12 72

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

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R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

(Socket-P KEY)

(CPU CORE POWER)

44 A (SV Design Target) 41 A (SV HFM)

30.4 A (SV LFM) 23 A (LV Design Target)

(CPU IO POWER 1.05V)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

(CPU INTERNAL PLL POWER 1.5V)

130 mA

(BR1#)

61 72

MF-LF 402

100

1% 1/16W

PLACE_NEAR=U1000.AE7:25.4 mm

R1101

61 72

OMIT

PENRYN

FCBGA

U1000

OMIT

PENRYN

FCBGA

U1000

100

1% 1/16W MF-LF 402

PLACE_NEAR=U1000.AF7:25.4 mm

R1100

SYNC_DATE=07/20/2009

SYNC_MASTER=T27_MLB

CPU Power & Ground

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

=PP1V5_S0_CPU

=PP1V05_S0_CPU

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

CPU_VCCSENSE_N

=PPVCORE_S0_CPU

11 OF 109

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051-8563

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1

2

AD15

AD17

AD18

C15

A7

A10

A13

A17

B15

B17

B20

C17

C18

D9

D12 D14

D18

E7 E9

E10

E12 E13

E15

E17 E18

E20

F7

F9

F10 F12

F14

F15

F18

F20 AA7

AA9 AA10

AA12

AA13 AA15

AA17

AA18 AA20

AB9

AC10 AB10

AB12 AB14

AB15

AB17 AB18

AB20

AB7

AC7 AC9

AC12

AC13 AC15

AC17 AC18

AD7

AD9 AD10

AD12

AD14

AE9

AE10 AE12

AE13

AE15 AE17

AE18

AE20 AF9 AF10

AF12

AF14 AF15

AF17

AF18 AF20

G21 V6

J6 K6

M6

J21 K21

M21

N21 N6

R21

R6

T21 T6

V21

W21

B26 C26

AD6 AF5

AE5

AF4 AE3

AF3

AE2

AF7

AE7

A9

A12

A15

B14

B18

C9 C10

C12

C13

D10

D15 D17

B12

B10

B7

A18

F17

B9

A20

N23

N26

B1

P3

E19

B19

A23

D16

D11

D4

D1

C25

C22

C2

T4

B8

A4 A8

A11 A14

A16

A19

AF2

B11

B13 B16

B21

B24

C5 C8

C11

C14 C16

C19

D8

D13

D26

E3 E6

E11 E14

E16

E24

F5

F8 F11

F13 F16

F19

F2 F22

F25

G4

G1

G23

G26

H3

H6 H21

H24

J2

J5

J22

J25

K1

K4

K23 K26

L3

L21

L24

M2

M5

M22 M25

N1

N4

P6

P21 P24

R2

R5 R22

R25 T1

T23 T26

U3 U6

U21 U24

V2

V5

V22 V25

W1

W4 W23

W26 Y3

Y6 Y21

Y24

AA2 AA5

AA8

AA11 AA14

AA16

AA19 AA22

AA25 AB1

AB4

AB8 AB11

AB13

AB16 AB19

AB23

AB26 AC3

AC6

AC8

AC11 AC14

AC16 AC19

AC21

AC24 AD2 AD5 AD8

AD11 AD13

AD16

AD19 AD22

AD25

AE1

AE4 AE8

AE11

AE14 AE16

AE19

AE23 AE26

A2 AF6

AF8

AF11 AF13

AF16

AF19 AF21

A25

AF25

E8

E21

L6

D23

D19

B6

1

2

7

11

7 9

11 12 61

7

10 11

7

10 11

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

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D

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

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8 7 5 4 2 1

PLACEMENT_NOTE (C1240-C1243):

1x 330uF, 6x 0.1uF 0402

PLACEMENT_NOTE (C1200-C1219):

4X 330UF. 20X 22UF 0805

CPU VCore HF and Bulk Decoupling

VCCA (CPU AVdd) DECOUPLING

VCCP (CPU I/O) DECOUPLING

1x 10uF, 1x 0.01uF

C1260

20%

2.0V

POLY-TANT

D2T-SM2

330UF

CRITICAL

PLACEMENT_NOTE=Place C1260 between CPU & NB.

20% X5R-CERM

NO STUFF

C1209

CRITICAL 22UF

6.3V 603

CPU_CAP:15&CPU_CAP:12

C1219

22UF

CRITICAL

X5R-CERM

6.3V

20%

603

CRITICAL

NO STUFF

6.3V

20% X5R-CERM

603

22UF

C1208

6.3V

CRITICAL

CPU_CAP:15&CPU_CAP:12

603

X5R-CERM

20%

22UF

C1218

NO STUFF

603

X5R-CERM

20%

6.3V

22UF

CRITICAL

C1207

CPU_CAP:15&CPU_CAP:12

22UF

C1217

CRITICAL

6.3V

20% X5R-CERM

603

X5R-CERM

CPU_CAP:15&CPU_CAP:12

CRITICAL

603

20%

6.3V

22UF

C1206

CRITICAL

603

X5R-CERM

22UF

C1216

CPU_CAP:15

6.3V

20%

22UF

C1205

6.3V X5R-CERM 603

CRITICAL

CPU_CAP:15

20%

CRITICAL

CPU_CAP:15&CPU_CAP:12

6.3V 603

20%

C1215

X5R-CERM

22UF

603

NO STUFF CRITICAL

X5R-CERM

22UF

C1204

6.3V

20%

6.3V

CPU_CAP:15&CPU_CAP:12

22UF

20%

603

X5R-CERM

C1214

CRITICAL

C1243

D2T-SM

POLY-TANT

2.0V

20%

Place on secondary side.

470UF-4MOHM

C1213

CRITICAL

CPU_CAP:15&CPU_CAP:12

X5R-CERM

6.3V

22UF

20%

603

NO STUFF

C1203

20% X5R-CERM

6.3V

22UF

603

CRITICAL

C1242

CRITICAL

POLY-TANT

Place on secondary side.

2.0V D2T-SM

20%

470UF-4MOHM

CPU_CAP:15&CPU_CAP:12

22UF

X5R-CERM

CRITICAL

6.3V

C1202

603

20%

CPU_CAP:15&CPU_CAP:12

C1212

6.3V

CRITICAL

603

20% X5R-CERM

22UF

X5R-CERM

20%

NO STUFF CRITICAL

22UF

C1201

603

6.3V

NO STUFF CRITICAL

C1211

20%

6.3V 603

22UF

X5R-CERM

C1241

CRITICAL

POLY-TANT

2.0V D2T-SM

20%

470UF-4MOHM

Place on secondary side.

Place inside socket cavity on secondary side.

CPU_CAP:15&CPU_CAP:12

CRITICAL

C1200

22UF

6.3V

20%

603

X5R-CERM

CPU_CAP:15&CPU_CAP:12

603

C1210

CRITICAL

22UF

X5R-CERM

6.3V

20%

2.0V POLY-TANT D2T-SM

Place on secondary side.

CRITICAL NO STUFF

C1240

470UF-4MOHM

CPU_CAP:15

C1222

20% X5R-CERM

603

22UF

6.3V

CRITICAL

CPU_CAP:15&CPU_CAP:12

CRITICAL

20%

6.3V X5R-CERM 603

22UF

C1221

NO STUFF

603

20%

6.3V

22UF

X5R-CERM

C1220

CRITICAL

C1261

20% 10V CERM 402

0.1UF

C1262

20% 10V CERM 402

0.1UF

C1263

20% 10V CERM 402

0.1UF

C1264

20% 10V CERM 402

0.1UF

C1265

20% 10V CERM 402

0.1UF

C1266

20% 10V CERM 402

0.1UF

BYPASS=U1000.B26::4 mm

10% CERM

16V 402

0.01UF

C1251C1250

20%

6.3V X5R 603

10uF

CPU Decoupling

SYNC_DATE=11/23/2009

SYNC_MASTER=T27_MLB

=PPVCORE_S0_CPU

=PP1V05_S0_CPU

=PP1V5_S0_CPU

12 OF 109

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11 OF 80

32

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

3 2

1

2

1

2

1

3 2

1

2

1

2

1

2

1

2

1

3 2

1

2

1

2

1

3 2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

7

10

7 9

10 12 61

7

10

IN

BI

BI BI

OUT

IN

BI

IN

IN IN

OUT

OUT OUT

OUT

IN

IN IN

IN OUT OUT OUT

OUT

NC

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

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REVISION

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SIZE

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PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

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NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

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8 7 5 4 2 1

OBSDATA_C1

OBSFN_C0

MCP89-specific pinout

Mini-XDP Connector

ITPCLK#/HOOK5

VCC_OBS_CD

XDP_PRESENT#

Use with 920-0620 adapter board to support CPU, MCP debugging.

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSDATA_B1

OBSDATA_D2 OBSDATA_D3

ITPCLK/HOOK4

OBSFN_C1

OBSDATA_C2

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

OBSDATA_B3

OBSFN_D1

PWRGD/HOOK0

OBSDATA_B2

TCK1

TMS

HOOK1

HOOK3

TRSTn

SDA

SCL

OBSFN_D0

RESET#/HOOK6

TDI

TDO

VCC_OBS_AB

NOTE: This is not the standard XDP pinout.

on even-numbered side of J1300

Please avoid any obstructions

DBR#/HOOK7

OBSDATA_C3

OBSDATA_C0

OBSDATA_A1

TCK0

Direction of XDP module

OBSDATA_D1

OBSDATA_D0

OBSFN_B1

OBSDATA_B0

OBSFN_B0

OBSDATA_A2

OBSDATA_A3

HOOK2

998-1571

9

13 72

R1399

1K

1/16W

5%

402

MF-LF

XDP

18 42 75

R1315

1/16W

1%

402

MF-LF

54.9

XDP

C1300

16V

10%

402

X5R

0.1uF

XDP

C1301

402

XDP

16V

10% X5R

0.1uF

9

72

9

72

9

72

9

13 72

R1303

1/16W

5%

402

MF-LF

1K

XDP

PLACEMENT_NOTE=Place close to CPU to minimize stub.

9

72

9

72

9

72

9

72

18

13 72

9

72

9

72

9

72

9

72

9

24

18

J1300

CRITICAL

F-ST-SM

LTH-030-01-G-D-NOPEGS

XDP_CONN

eXtended Debug Port (mini-XDP)

SYNC_MASTER=T27_MLB

SYNC_DATE=07/28/2009

FSB_CPURST_L

CPU_PWRGD

XDP_TMS

XDP_TDO XDP_TRST_L XDP_TDI

XDP_DBRESET_L

XDP_CPURST_L

FSB_CLK_ITP_N

TP_XDP_OBSDATA_D2

TP_XDP_OBSDATA_D0 TP_XDP_OBSDATA_D1

JTAG_MCP_TDI

TP_XDP_OBSDATA_C2

XDP_BPM_L<5> XDP_BPM_L<4>

XDP_BPM_L<3> XDP_BPM_L<2>

XDP_BPM_L<1> XDP_BPM_L<0>

TP_XDP_OBSFN_B0 TP_XDP_OBSFN_B1

TP_XDP_OBSDATA_B1

TP_XDP_OBSDATA_B0

TP_XDP_OBSDATA_B2

XDP_PWRGD

TP_XDP_OBSDATA_B3

XDP_OBS20

=PP1V05_S0_CPU

PM_LATRIGGER_L JTAG_MCP_TCK

SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA

XDP_TCK

FSB_CLK_ITP_P

TP_XDP_OBSDATA_D3

JTAG_MCP_TMS

TP_XDP_OBSDATA_C3

=PP3V3_S0_XDP

TP_XDP_OBSDATA_C1

TP_XDP_OBSDATA_C0

JTAG_MCP_TRST_L

JTAG_MCP_TDO

13 OF 109

A.13.0

051-8563

12 OF 80

1 2

1

2

1

2

1

1 2

60

58

52

54

56

50

48

46

44

42

36

40

38

32

34

28 30

26

24

22

18

16

20

14

12

10

8

6

2

4 3

1

5 7

9

11 13

19

15 17

23

21

29

27

25

33

31

37 39

35

43

41

45

49

47

55

53

51

57

59

72

7 9

10 11 61

7

IN IN IN

IN

OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI

BI BI

BI

IN BI

OUT OUT OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT OUT OUT

OUT OUT

IN

BI BI

CPU_A18*

CPU_D35*

CPU_D37*

CPU_A10*

CPU_A9*

CPU_D48*

CPU_A16*

CPU_D33*

CPU_RS2*

CPU_RS1*

CPU_RS0*

CPU_BSEL2 CPU_BSEL1

CPU_THERMTRIP*

CPU_PECI CPU_PROCHOT*

CPU_DBSY*

CPU_ADSTB1*

CPU_REQ1*

CPU_REQ4*

CPU_BR0*

CPU_BNR*

CPU_ADS*

CPU_REQ2* CPU_REQ3*

CPU_REQ0*

CPU_ADSTB0*

CPU_A31* CPU_A32*

CPU_A30*

CPU_A28*

CPU_A26* CPU_A27*

CPU_A23* CPU_A24* CPU_A25*

CPU_A21* CPU_A22*

CPU_A19* CPU_A20*

CPU_A13* CPU_A14*

CPU_A12*

CPU_A11*

CPU_A8*

CPU_A5* CPU_A6* CPU_A7*

CPU_A3* CPU_A4*

CPU_DSTBN0* CPU_DBI0*

CPU_DSTBP1* CPU_DSTBN1* CPU_DBI1*

CPU_DSTBP2* CPU_DSTBN2* CPU_DBI2*

CPU_DSTBP3* CPU_DSTBN3* CPU_DBI3*

CPU_BSEL0

CPU_COMP_GND

BCLK_VML_COMP_VDD

CPU_COMP_VCC

BCLK_VML_COMP_GND

CPU_D1* CPU_D2* CPU_D3* CPU_D4* CPU_D5* CPU_D6*

CPU_D9*

CPU_D11* CPU_D12* CPU_D13* CPU_D14* CPU_D15* CPU_D16* CPU_D17* CPU_D18* CPU_D19* CPU_D20* CPU_D21* CPU_D22* CPU_D23* CPU_D24* CPU_D25* CPU_D26* CPU_D27* CPU_D28* CPU_D29* CPU_D30* CPU_D31* CPU_D32*

CPU_D34*

CPU_D36*

CPU_D38* CPU_D39* CPU_D40* CPU_D41* CPU_D42*

CPU_D45* CPU_D46* CPU_D47*

CPU_D49* CPU_D50* CPU_D51* CPU_D52* CPU_D53* CPU_D54* CPU_D55* CPU_D56* CPU_D57* CPU_D58* CPU_D59* CPU_D60* CPU_D61* CPU_D62* CPU_D63*

CPU_A20M*

CPU_IGNNE*

CPU_INIT*

CPU_INTR

CPU_NMI

CPU_SMI*

CPU_PWRGD

CPU_RESET*

CPU_DPRSLPVR

CPU_SLP*

CPU_D10*

CPU_D8*

CPU_D7*

CPU_A33* CPU_A34* CPU_A35*

CPU_D44*

CPU_D43*

CPU_DSTBP0*

CPU_TRDY*

CPU_LOCK*

CPU_HIT*

CPU_DRDY*

CPU_HITM*

CPU_DPRSTP*

CPU_D0*

CPU_DPSLP*

CPU_DPWR*

CPU_STPCLK*

CPU_A15*

CPU_A17*

CPU_A29*

CPU_BPRI*

CPU_DEFER*

CPU_FERR*

BCLK_OUT_CPU_P

BCLK_OUT_CPU_N

BCLK_OUT_ITP_P

BCLK_OUT_ITP_N

BCLK_OUT_NB_N

BCLK_IN_N

BCLK_IN_P

BCLK_OUT_NB_P

(1 OF 11)

FSB

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Loop-back clock for delay matching.

8

9

72

9

12 72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

6 9

72

9

72

9

72

9

72

9

72

9

72

9

72

12 72

9

72

9

72

9

72

9

72

9

72

9

72

9

72

9

72

9

12 72

9

72

9

72

9

72

9

72

9

61 72

8

9

40 61 72

9

40 72

6 9

72

6 9

72

1% 1/16W MF-LF 402

49.9

R1436

49.9

MF-LF

402

1%

1/16W

R1431

1/16W

1%

402

MF-LF

49.9

R1430

402

MF-LF

1% 1/16W

49.9

R1435

5%

62

MF-LF 402

1/16W

R1415

1%

54.9

MF-LF

402

1/16W

R1410

150

1/16W

NO STUFF

402

MF-LF

5%

R1440

OMIT

MCP89M-A01

FBGA

U1400

61 72

6 9

72

6 9

72

9

72

9

72

9

72

9

72

6 9

72

MCP CPU Interface

SYNC_MASTER=T27_MLB

SYNC_DATE=11/05/2009

FSB_D_L<46>

FSB_D_L<45>

FSB_D_L<39>

FSB_D_L<36>

FSB_D_L<33>

FSB_D_L<31>

FSB_D_L<0>

FSB_D_L<7> FSB_D_L<8>

FSB_D_L<10>

CPU_DPRSTP_L

CPU_STPCLK_L

FSB_DPWR_L

CPU_DPSLP_L

FSB_CPUSLP_L

PM_DPRSLPVR

FSB_CPURST_L

CPU_PWRGD

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_A20M_L

FSB_CLK_MCP_N FSB_CLK_MCP_P

FSB_CLK_ITP_P

FSB_CLK_ITP_N

FSB_CLK_CPU_N FSB_CLK_CPU_P

FSB_BPRI_L FSB_DEFER_L

FSB_D_L<63>

FSB_D_L<62>

FSB_D_L<61>

FSB_D_L<60>

FSB_D_L<59>

FSB_D_L<58>

FSB_D_L<57>

FSB_D_L<56>

FSB_D_L<55>

FSB_D_L<54>

FSB_D_L<53>

FSB_D_L<52>

FSB_D_L<51>

FSB_D_L<50>

FSB_D_L<49>

FSB_D_L<47>

FSB_D_L<44>

FSB_D_L<43>

FSB_D_L<42>

FSB_D_L<41>

FSB_D_L<40>

FSB_D_L<38>

FSB_D_L<34>

FSB_D_L<32>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<9>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

MCP_BCLK_VML_COMP_GND

MCP_CPU_COMP_VCC

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP_GND

=MCP_BSEL<0>

FSB_DINV_L<3>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<2>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<1>

FSB_DSTB_L_N<1>

FSB_DSTB_L_P<1>

FSB_DINV_L<0>

FSB_DSTB_L_N<0>

FSB_DSTB_L_P<0>

FSB_A_L<4>

FSB_A_L<3>

FSB_A_L<7>

FSB_A_L<6>

FSB_A_L<5>

FSB_A_L<8>

FSB_A_L<11> FSB_A_L<12>

FSB_A_L<15>

FSB_A_L<14>

FSB_A_L<13>

FSB_A_L<17>

FSB_A_L<20>

FSB_A_L<19>

FSB_A_L<22>

FSB_A_L<21>

FSB_A_L<25>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<27>

FSB_A_L<26>

FSB_A_L<28>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<35>

FSB_A_L<34>

FSB_ADSTB_L<0>

FSB_REQ_L<0>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_ADS_L FSB_BNR_L FSB_BREQ0_L

FSB_REQ_L<4>

FSB_REQ_L<1>

FSB_ADSTB_L<1>

FSB_DBSY_L FSB_DRDY_L

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_LOCK_L

CPU_PROCHOT_L

CPU_PECI_MCP

CPU_FERR_L

PM_THRMTRIP_L

=MCP_BSEL<1>

=MCP_BSEL<2>

FSB_RS_L<0> FSB_RS_L<1> FSB_RS_L<2>

FSB_A_L<16>

FSB_D_L<48>

FSB_A_L<9> FSB_A_L<10>

FSB_D_L<37>

FSB_D_L<35>

FSB_A_L<18>

=PP1V05_S0_MCP_FSB

14 OF 109

A.13.0

051-8563

13 OF 80

121

2

121

2

1

2

1

2

1

2

AB35

L31

P32

Y38

T37

C37

Y35

G34

AC31

AC33

AB29

B34 C34

W33

AH34

U28

AE29

AB34

T36

T35

AE30

AE32

AE31

U37 T38

U36

W36

AC35 AE37

AC37

AE36

AB37 AC34

AC38 AB36 AB38

AC36 AF36

Y34

AE38

U33 W34

Y36

W35

W38

U35 T34 W37

U38 U34

K35 L37

T31 T30 P28

K33 K32 N35

C36 D36 A35

A34

AH35

AH37

AH36

AH38

N36 P36 L36 N34 L35 P37

L34

K36 K38 N37 H37 L38 N28 U30 N29 P34 T29 T32 U32 T33 P31 P30 N30 P33 N31 T28 P35 P29 H33

L30

L33

N32 N33 H35 K31 H34

G33 H32 G35

D37 H38 G38 G37 G36 B35 E35 B36 E36 C35 D34 E38 D38 E34 E37

W30 AB30 AB28 W31 AC30 AC28 Y32 AE28 G1 Y33

K37

H36

P38

AE35 AE33 AE34

L32

K30

K34

AC29

AC32

W32

U29

AB31

W29

N38

AB33 U31 Y29

Y37

AF38

AF37

Y31 Y30

AB32

AF33

AF32

AF34

AF35

AF28

AF31

AF30

AF29

72

7

13 19 22

7

13 19 22

OUT

OUT OUT OUT OUT OUT OUT

BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT OUT

OUT OUT

BI BI

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT OUT

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI BI BI

BI

OUT

BI

OUT OUT OUT OUT OUT OUT OUT

OUT OUT

MDQS0_7_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_5_N

MDQS0_5_P

MDQS0_4_P MDQS0_4_N MDQS0_3_P

MDQS0_2_P MDQS0_2_N MDQS0_1_P MDQS0_1_N MDQS0_0_P MDQS0_0_N

MRAS0* MCAS0*

MWE0*

MBA0_2 MBA0_1 MBA0_0

MA0_14

MA0_15

MA0_13 MA0_12 MA0_11

MA0_9

MA0_10

MA0_8 MA0_7 MA0_6

MA0_3

MA0_4

MA0_1

MA0_2

MA0_0

+VIO_M2CLK_DLL_1 +VIO_M2CLK_DLL_2

+VIO_PLL_MEM_2

+VIO_PLL_MEM_1

+VIO_PLL_FSB_1 +VIO_PLL_FSB_2

MCLK0A_1_P MCLK0A_1_N

MCLK0A_0_P MCLK0A_0_N

MCS0A_1* MCS0A_0*

MODT0A_0

MODT0A_1

MCKE0A_1 MCKE0A_0

MDQ0_63 MDQ0_62 MDQ0_61

MDQ0_58

MDQ0_59

MDQ0_55

MDQ0_57 MDQ0_56

MDQ0_53

MDQ0_54

MDQ0_50

MDQ0_52 MDQ0_51

MDQ0_48

MDQ0_49

MDQ0_45

MDQ0_46

MDQ0_47

MDQ0_43

MDQ0_44

MDQ0_41 MDQ0_40 MDQ0_39

MDQ0_37

MDQ0_38

MDQ0_36 MDQ0_35 MDQ0_34 MDQ0_33 MDQ0_32 MDQ0_31 MDQ0_30 MDQ0_29

MDQ0_27

MDQ0_28

MDQ0_26 MDQ0_25 MDQ0_24

MDQ0_22

MDQ0_23

MDQ0_19

MDQ0_21 MDQ0_20

MDQ0_17

MDQ0_18

MDQ0_16

MDQ0_14

MDQ0_15

MDQ0_12

MDQ0_13

MDQ0_11 MDQ0_10 MDQ0_9 MDQ0_8 MDQ0_7

MDQ0_5

MDQ0_6

MDQ0_4

MDQ0_2

MDQ0_3

MDQ0_1 MDQ0_0

MDQM0_7 MDQM0_6 MDQM0_5 MDQM0_4

MDQM0_2

MDQM0_3

MDQM0_0

MDQM0_1

MDQ0_42

MA0_5

+VIO_PLL_CPU_4

+VIO_PLL_CPU_3

+VIO_PLL_CPU_2

+VIO_PLL_CPU_1

MDQS0_3_N

MDQ0_60

MEMORY PARTITION 0

(2 OF 11)

MDQ1_51

MDQ1_13

MDQ1_25

MDQ1_39

MEM_COMP_VDD

MEM_COMP_GND

MDQM1_1

MDQ1_44 MDQ1_43 MDQ1_42 MDQ1_41 MDQ1_40

MDQ1_38

MDQ1_10

MDQ1_16

MDQ1_14

MDQ1_3 MDQ1_2 MDQ1_1

MDQM1_2

MDQM1_3

MDQM1_4

MDQM1_5

MDQM1_6

MDQM1_7

MDQS1_6_N

MDQS1_7_N

MDQS1_7_P

MDQ1_0

MDQ1_4

MDQ1_5

MDQ1_6

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_11

MDQ1_12

MDQ1_15

MDQ1_17

MDQ1_18

MDQ1_21

MDQ1_22

MDQ1_23

MDQ1_24

MDQ1_26

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_30

MDQ1_31

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_35

MDQ1_36

MDQ1_37

MDQ1_46

MDQ1_47

MDQ1_48

MDQ1_52

MDQ1_53

MDQ1_54

MDQ1_56

MDQ1_57

MDQ1_58

MDQ1_59

MDQ1_60

MDQ1_61

MDQ1_62

MDQ1_49

MDQS1_6_P

MDQ1_63

MDQ1_50

MDQM1_0

MDQ1_45

MDQ1_55

MDQS1_5_P MDQS1_5_N MDQS1_4_P MDQS1_4_N MDQS1_3_P MDQS1_3_N MDQS1_2_P MDQS1_2_N MDQS1_1_P MDQS1_1_N

MDQS1_0_N

MDQS1_0_P

MRAS1* MCAS1*

MWE1*

MBA1_2 MBA1_1 MBA1_0

MA1_15 MA1_14 MA1_13 MA1_12 MA1_11 MA1_10

MA1_9 MA1_8 MA1_7 MA1_6

MA1_4

MA1_5

MA1_3

MRESET0*

MCLK1A_1_P MCLK1A_1_N

MCLK1A_0_P MCLK1A_0_N

MCS1A_1* MCS1A_0*

MODT1A_1 MODT1A_0

MCKE1A_1 MCKE1A_0

MA1_1 MA1_0

MA1_2

MDQ1_19

MDQ1_20

MEMORY PARTITION 1

(3 OF 11)

OUT OUT

OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

20 mA

25 mA

70 mA

550 mA

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

27 73

25 73

20 25 73

27 73

26 73

27 73

25 73 26 73

20 26 73

MCP89M-A01

FBGA

OMIT

U1400

FBGA

MCP89M-A01

OMIT

U1400

26 73

25 26

1K

MF-LF

1/16W 402

5%

R1520

MF-LF

40.2

1/16W

1%

402

R1511

1%

40.2

1/16W

402

MF-LF

R1510

MCP Memory Interface

SYNC_MASTER=T27_MLB

SYNC_DATE=08/06/2009

MEM_A_DQS_N<6>

MEM_A_A<7>

PP1V05_S0_MCP_PLL_FSBMEM

=PP1V05_S0_MCP_M2CLK_DLL

MEM_B_DQ<9>

MEM_B_DQ<29>

MEM_A_A<5>

MEM_A_A<6>

MEM_B_DQ<27>

MEM_A_DQ<39>

MEM_A_WE_L

MEM_RESET_L

MEM_B_CLK_P<1> MEM_B_CLK_N<1>

MEM_B_CLK_P<0>

MEM_B_DQ<51>

MEM_B_DQ<13>

MEM_B_CS_L<1>

MEM_B_DQ<25>

MEM_B_DQ<39>

MCP_MEM_COMP_VDD

MCP_MEM_COMP_GND

MEM_B_DM<1> MEM_B_DM<0>

MEM_B_DQ<45> MEM_B_DQ<44> MEM_B_DQ<43> MEM_B_DQ<42> MEM_B_DQ<41> MEM_B_DQ<40>

MEM_B_DQ<38>

MEM_B_BA<0>

MEM_B_BA<1>

MEM_B_BA<2>

MEM_B_WE_L

MEM_B_CAS_L

MEM_B_RAS_L

MEM_B_A<0>

MEM_B_A<1>

MEM_B_A<2>

MEM_B_A<3>

MEM_B_A<4>

MEM_B_A<5>

MEM_B_A<6>

MEM_B_A<7>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<10>

MEM_B_A<11>

MEM_B_A<12>

MEM_B_A<13>

MEM_B_A<14>

MEM_B_A<15>

MEM_B_DQ<10>

MEM_B_DQ<20> MEM_B_DQ<19>

MEM_B_DQ<16>

MEM_B_DQ<14>

MEM_B_DQ<3> MEM_B_DQ<2> MEM_B_DQ<1>

MEM_B_DM<2>

MEM_B_DM<3>

MEM_B_DM<4>

MEM_B_DM<5>

MEM_B_DM<6>

MEM_B_DM<7>

MEM_B_CKE<0>

MEM_B_CKE<1>

MEM_B_ODT<0>

MEM_B_ODT<1>

MEM_B_CS_L<0>

MEM_B_CLK_N<0>

MEM_B_DQS_N<0>

MEM_B_DQS_P<0>

MEM_B_DQS_N<1>

MEM_B_DQS_P<1>

MEM_B_DQS_N<2>

MEM_B_DQS_P<2>

MEM_B_DQS_N<3>

MEM_B_DQS_P<3>

MEM_B_DQS_N<4>

MEM_B_DQS_P<4>

MEM_B_DQS_N<5>

MEM_B_DQS_P<5>

MEM_B_DQS_N<6>

MEM_B_DQS_N<7>

MEM_B_DQS_P<7>

MEM_B_DQ<0>

MEM_B_DQ<4>

MEM_B_DQ<5>

MEM_B_DQ<6>

MEM_B_DQ<7>

MEM_B_DQ<8>

MEM_B_DQ<11>

MEM_B_DQ<12>

MEM_B_DQ<17>

MEM_B_DQ<18>

MEM_B_DQ<21>

MEM_B_DQ<22>

MEM_B_DQ<23>

MEM_B_DQ<24>

MEM_B_DQ<26>

MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_DQ<31>

MEM_B_DQ<32>

MEM_B_DQ<33>

MEM_B_DQ<34>

MEM_B_DQ<35>

MEM_B_DQ<36>

MEM_B_DQ<37>

MEM_B_DQ<46>

MEM_B_DQ<47>

MEM_B_DQ<48>

MEM_B_DQ<50>

MEM_B_DQ<52>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<55>

MEM_B_DQ<56>

MEM_B_DQ<57>

MEM_B_DQ<58>

MEM_B_DQ<59>

MEM_B_DQ<60>

MEM_B_DQ<61>

MEM_B_DQ<62>

MEM_B_DQ<63>

MEM_B_DQ<49>

MEM_B_DQS_P<6>

MEM_A_DQS_P<7> MEM_A_DQS_N<7> MEM_A_DQS_P<6>

MEM_A_DQS_P<5>

MEM_A_DQS_P<3>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<1>

MEM_A_DQS_P<1>

MEM_A_DQS_N<0>

MEM_A_DQS_P<0>

MEM_A_RAS_L MEM_A_CAS_L

MEM_A_BA<1>

MEM_A_BA<2>

MEM_A_BA<0>

MEM_A_A<13>

MEM_A_A<15> MEM_A_A<14>

MEM_A_A<12>

MEM_A_A<10>

MEM_A_A<4>

MEM_A_A<2> MEM_A_A<1>

MEM_A_CLK_P<1> MEM_A_CLK_N<1>

MEM_A_CLK_P<0> MEM_A_CLK_N<0>

MEM_A_CS_L<1> MEM_A_CS_L<0>

MEM_A_ODT<0>

MEM_A_ODT<1>

MEM_A_CKE<0>

MEM_A_CKE<1>

MEM_A_DQ<31>

MEM_A_DQ<9>

MEM_A_DQ<10>

MEM_A_DQ<63>

MEM_A_DM<0>

MEM_A_DM<3> MEM_A_DM<2> MEM_A_DM<1>

MEM_A_DM<5> MEM_A_DM<4>

MEM_A_DM<6>

MEM_A_DM<7>

MEM_A_DQ<0>

MEM_A_DQ<2> MEM_A_DQ<1>

MEM_A_DQ<3>

MEM_A_DQ<4>

MEM_A_DQ<5>

MEM_A_DQ<7> MEM_A_DQ<6>

MEM_A_DQ<8>

MEM_A_DQ<11>

MEM_A_DQ<12>

MEM_A_DQ<15>

MEM_A_DQ<13>

MEM_A_DQ<14>

MEM_A_DQ<17> MEM_A_DQ<16>

MEM_A_DQ<20> MEM_A_DQ<19> MEM_A_DQ<18>

MEM_A_DQ<22> MEM_A_DQ<21>

MEM_A_DQ<23>

MEM_A_DQ<25> MEM_A_DQ<24>

MEM_A_DQ<28>

MEM_A_DQ<26>

MEM_A_DQ<27>

MEM_A_DQ<29>

MEM_A_DQ<30>

MEM_A_DQ<32>

MEM_A_DQ<33>

MEM_A_DQ<34>

MEM_A_DQ<35>

MEM_A_DQ<38> MEM_A_DQ<37> MEM_A_DQ<36>

MEM_A_DQ<40>

MEM_A_DQ<41>

MEM_A_DQ<43> MEM_A_DQ<42>

MEM_A_DQ<44>

MEM_A_DQ<45>

MEM_A_DQ<46>

MEM_A_DQ<47>

MEM_A_DQ<48>

MEM_A_DQ<51> MEM_A_DQ<50> MEM_A_DQ<49>

MEM_A_DQ<53> MEM_A_DQ<52>

MEM_A_DQ<56> MEM_A_DQ<55> MEM_A_DQ<54>

MEM_A_DQ<57>

MEM_A_DQ<58>

MEM_A_DQ<61> MEM_A_DQ<60> MEM_A_DQ<59>

MEM_A_DQ<62>

MEM_A_DQS_N<2>

MEM_A_DQS_P<2>

MEM_A_DQS_P<4>

MEM_A_DQS_N<5>

=PP1V5R1V35_S3_MCP_MEM

MEM_A_A<0>

MEM_A_A<11>

MEM_A_A<9>

MEM_B_DQ<15>

MEM_A_A<3>

=PP1V5R1V35_SW_MCP_MEM

MEM_A_A<8>

15 OF 109

A.13.0

051-8563

14 OF 80

AN7

AM10

AN10

AM7

AM13

AN13

AL16 AK16 AH28

AM29 AN29 AP34 AP35 AH31 AG31

AN19 AL19 AL20

AL25 AN20 AM19

AK25

AK26

AJ20 AJ26 AH25

AH26

AM20

AN23 AJ25 AM22

AL23

AN22

AK23

AK22

AL22

AF24 AG25

AG26

AF25

AF26 AG28

AH23 AJ23

AJ22 AH22

AH19 AK20

AK19

AH20

AL26 AN25

AP5 AP7 AR8

AR5

AR4

AK11

AM8 AN8

AH13

AL11

AK10

AH14 AL10

AJ13

AN11

AJ16

AK14

AK13

AJ14

AH16

AM14 AN14 AK17

AN17

AL17

AJ19 AH17 AJ17 AM16 AM17 AN26 AH29 AK29

AM25

AL29

AM26 AL28 AK28

AP29

AM28

AP28

AL31 AN32

AN31

AN28

AM31

AM32

AR34

AL35

AL33

AP32 AP33 AM35 AL32 AJ35

AH32

AJ31

AH33

AL34

AJ34

AJ33 AJ32

AR7 AM11 AL14 AN16

AP31

AJ29

AJ30

AM34

AL13

AM23

AF27

AE26

AD26

AC26

AJ28

AP8

AV5

AR37

AV28

AV14

AG22

AG23

AT37

AR14 AR11 AP11 AT11 AP13

AU14

AU35

AT32

AT35

AP37 AP36 AJ38

AV32

AR28

AT14

AV10

AU7

AT2

AV8

AR1

AR2

AJ37

AL36

AJ36

AM37

AM36

AR38

AR36

AV34

AP38

AV35

AU32

AR31

AT34

AR32

AT31

AV29

AV26

AV25

AT29

AU29

AT26

AU26

AR16

AP16

AT13

AP14

AP17

AR17

AU10

AT10

AT8

AR10

AU8

AT7

AT4

AU3

AP2

AP3

AU4

AV4

AR3

AP10

AV7

AP1

AU5

AM38

AR13

AT5

AU11 AV11 AU13 AV13 AT28 AU28 AU31 AV31 AU36 AT36

AL37

AL38

AR19 AU17 AT17

AR25 AT19 AR20

AP26 AR26 AV16 AP25 AT23 AP20 AU23 AV22 AV23 AT22

AP23

AU22

AR23

AP4

AU20 AV20

AU19 AV19

AU16 AP19

AT16 AV17

AU25 AT25

AR22 AT20

AP22

AR29

AU34

1

2

1

2

1

2

22

7

22

73

7

19 20 22

IN IN

IN

IN IN

IN

OUT OUT

OUT

OUT OUT

OUT

PE0_REFCLK_P PE0_REFCLK_N

PE1_REFCLK_P

PE2_REFCLK_P

PE1_REFCLK_N

PE3_REFCLK_P

PE2_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE5_REFCLK_P

PE4_REFCLK_N

PE5_REFCLK_N

PE0_TX0_P PE0_TX0_N

PE0_TX1_P PE0_TX1_N

PE0_TX2_P

PE0_TX3_P

PE0_TX2_N

PE0_TX4_P

PE0_TX3_N

PE0_TX5_P

PE0_TX4_N

PE0_TX5_N

PE1_TX0_N

PE1_TX0_P

PE1_TX1_P PE1_TX1_N

PEX_RST*

PEX0_TERM_P

PEA_CLKREQ*/GPIO_49

PEB_CLKREQ*/GPIO_50

PEC_CLKREQ*/GPIO_51

PEE_CLKREQ*/GPIO_53

PED_CLKREQ*/GPIO_52

PEF_CLKREQ*/GPIO_54

PE_WAKE*

PE0_RX0_P PE0_RX0_N

PE0_RX1_P PE0_RX1_N

PE0_RX3_P

PE0_RX4_P

PE0_RX3_N

PE0_RX4_N

PE0_RX5_P PE0_RX5_N

PE1_RX0_P PE1_RX0_N

PE1_RX1_N

PE1_RX1_P

+3.3V_PLL_HVDD_1 +3.3V_PLL_HVDD_2

+VIO_PLL_PE

+VIO_PLL_XREF_XS_1 +VIO_PLL_XREF_XS_2

+VIO_PLL_SATA_1

+VIO_PLL_XREF_XS_3

+VIO_PLL_SATA_2

+VIO_PLL_H

PE0_RX2_N

PE0_RX2_P

PCI EXPRESS

(4 OF 11)

OUT

IN

OUT OUT

IN

IN IN

OUT OUT

IN

OUT OUT

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(IPU)

PE1 ports are Gen1-only. 2 RCs: x1, x1

PE0 ports are Gen2-capable. 4 RCs: 4x, x2, x1, x1

+VIO_PE_AVDD1 and +VIO_PE_DVDD1 can be GND

If PE0[3:0] are not used, +VIO_PE_AVDD0 and +VIO_PE_DVDD0 can be GND

If PE0[4:5] and PE1[0:1] are not used,

(IPU-S5)

50 mA

100 mA

120 mA

25 mA

80 mA

325 mA

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

(IPU)

(IPD)

R1610

2.49K

1% 1/16W MF-LF

402

PLACE_NEAR=U1400.U2:12.7 mm

31 74

6

29 74

6

29 74

6

24 29

34

29

8

29 74

18 24

33 74

29 74

8

74

8

74

8

U1400

OMIT

MCP89M-A01

FBGA

34

8

31 74

31

33 74

34

31 74

R1600

10K

5%

402

MF-LF

1/16W

NO STUFF

SYNC_DATE=11/05/2009

SYNC_MASTER=T27_MLB

MCP PCIe Interfaces

=PEG_D2R_N<2> =PEG_D2R_P<3>

=PEG_D2R_N<3>

TP_PCIE_PE4_D2RP

PCIE_FW_R2D_C_N

PCIE_CLK100M_ENET_N

PCIE_CLK100M_AP_N

=PEG_R2D_C_P<1>

PP3V3_S0_MCP_PLL_HVDD

PCIE_ENET_D2R_N

PCIE_FW_D2R_P

PCIE_WAKE_L

=PEG_R2D_C_P<0>

TP_PCIE_CLK100M_PE4N

FW_CLKREQ_L

MCP_PEX0_TERMP

PCIE_AP_R2D_C_P

=PEG_R2D_C_P<2>

TP_PCIE_CLK100M_PE5P

PCIE_CLK100M_FW_P

PCIE_ENET_D2R_P

TP_PCIE_PE4_D2RN

=PEG_D2R_P<2>

=PEG_D2R_N<1>

=PEG_D2R_P<1>

=PEG_D2R_N<0>

=PEG_D2R_P<0>

PEG_CLKREQ_L

TP_PCIE_PE4_R2D_CP

PCIE_ENET_R2D_C_P

TP_PCIE_PE4_R2D_CN

PEG_CLK100M_P PEG_CLK100M_N

AP_CLKREQ_L

PCIE_FW_D2R_N

PCIE_FW_R2D_C_P

FW_PME_L

PCIE_AP_D2R_P

TP_PCIE_CLK100M_PE4P

PCIE_AP_D2R_N

PP1V05_S0_MCP_PLL_PEXSATA

=PEG_R2D_C_N<2>

=PEG_R2D_C_N<3>

=PEG_R2D_C_N<1>

ENET_CLKREQ_L

=PEG_R2D_C_N<0>

=PEG_R2D_C_P<3>

PCIE_CLK100M_FW_N

FW_PWR_EN

PCIE_CLK100M_AP_P

PCIE_CLK100M_ENET_P

TP_PCIE_CLK100M_PE5N

PCIE_AP_R2D_C_N

PCIE_ENET_R2D_C_N

PCIE_RESET_L

16 OF 109

A.13.0

051-8563

15 OF 80

1

2

Y1 W1

W3

U4

W2

U7

U5

U9

U6

W10

U8

W11

AC3 AC2

AB2 AB3

AC6

AC8

AC7

AB4

AC9

Y5

AB5

Y4

Y6

Y7

Y9 Y8

U1

U2

W4

W5

W7

W6

W8

W9

U3

AC1 AB1

AC5 AC4

AB7

AB9

AB6

AB8

Y2 Y3

AB11 AB10

Y11

Y10

V11 V13

AH10

AG11 AF12

AH8

AF13

AH9

AH11

AC11

AC10

1

2

22

74

22

OUT

IN

BI

OUT

BI

OUT

FLAT PANEL

RGB

(5 OF 11)

+3.3V_RGBDAC

DDC_DATA0/GPIO_39

DDC_CLK0/GPIO_38

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_HSYNC

RGB_DAC_BLUE

RGB_DAC_VSYNC

RGB_DAC_RSET RGB_DAC_VREF

IFPA_TXC_P

IFPA_TXD0_P

IFPA_TXC_N

IFPA_TXD0_N

DP0_3_P/TMDS0_TXC_P DP0_3_N/TMDS0_TXC_N

DP0_2_N/TMDS0_TX0_N

DDC_CLK3/DP_AUX_CH1_P DDC_DATA3/DP_AUX_CH1_N

DP0_1_P/TMDS0_TX1_P DP0_1_N/TMDS0_TX1_N DP0_0_P/TMDS0_TX2_P DP0_0_N/TMDS0_TX2_N

DP1_3_P/TMDS0B_TXC_P DP1_3_N/TMDS0B_TXC_N

DP1_2_P/TMDS0_TX3_P DP1_2_N/TMDS0_TX3_N DP1_1_P/TMDS0_TX4_P DP1_1_N/TMDS0_TX4_N DP1_0_P/TMDS0_TX5_P DP1_0_N/TMDS0_TX5_N

HPLUG_DET0/GPIO_20 HPLUG_DET1/GPIO_21 HPLUG_DET2/GPIO_22

DDC_CLK2/DP_AUX_CH0_P DDC_DATA2/DP_AUX_CH0_N

+3.3V_PLL_DP0_1

+VIO_PLL_IFPAB_1

+3.3V_PLL_USB_2

+VIO_PLL_IFPAB_2

+VIO_PLL_SPPLL0_1

+VIO_PLL_CORE_LEG

+VIO_PLL_SPPLL0_2

+VIO_PLL_NV_1

+VIO_PLL_V

+VDD_IFPA

+VIO_PLL_NV_2

+VDD_IFPB

+VIO_DP0_1 +VIO_DP0_2 +VIO_DP0_3

IFPA_TXD1_P IFPA_TXD1_N IFPA_TXD2_P IFPA_TXD2_N IFPA_TXD3_P IFPA_TXD3_N

IFPB_TXC_P IFPB_TXC_N

IFPB_TXD4_P IFPB_TXD4_N IFPB_TXD5_P IFPB_TXD5_N IFPB_TXD6_P IFPB_TXD6_N IFPB_TXD7_P IFPB_TXD7_N

DDC_CLK1/GPIO_40

DDC_DATA1/GPIO_41

TMDS0_RSET

TMDS0_VPROBE

IFPAB_RSET

IFPAB_VPROBE

+3.3V_PLL_USB_1

+3.3V_PLL_DP0_2

DP0_2_P/TMDS0_TX0_P

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

OUT OUT OUT

OUT

OUT OUT OUT OUT

BI

BI BI

OUT

OUT OUT

OUT

OUT OUT OUT OUT

IN IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

140 mA

LVDS: Power +VDD_IFPx at 1.8V

=MCP_IFPAB_DDC_DATA

=MCP_IFPA_TXC_P/N

=MCP_IFPAB_DDC_CLK

=MCP_IFPB_TXD_P/N<3>

=MCP_IFPB_TXD_P/N<2>

=MCP_IFPB_TXD_P/N<1>

=MCP_IFPB_TXD_P/N<0>

=MCP_IFPB_TXC_P/N

=MCP_IFPA_TXD_P/N<3>

=MCP_IFPA_TXD_P/N<2>

=MCP_IFPA_TXD_P/N<1>

=MCP_IFPA_TXD_P/N<0>

(UNUSED)

MCP Signal

TMDS/HDMI

TMDS_IG_DDC_CLK TMDS_IG_DDC_DATA

TMDS_IG_TXD_P/N<5>

TMDS_IG_TXD_P/N<4>

TMDS_IG_TXD_P/N<3>

TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<2>

TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<0>

Interface Mode

LVDS_IG_A_CLK_P/N LVDS_IG_A_DATA_P/N<0> LVDS_IG_A_DATA_P/N<1> LVDS_IG_A_DATA_P/N<2> LVDS_IG_A_DATA_P/N<3> LVDS_IG_B_CLK_P/N LVDS_IG_B_DATA_P/N<0> LVDS_IG_B_DATA_P/N<1> LVDS_IG_B_DATA_P/N<2> LVDS_IG_B_DATA_P/N<3>

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

LVDS

NOTE: No Composite/S-Video/Component Video support on MCP89

Okay to float all RGB_DAC signals. DDC_CLK0/DDC_DATA0 pull-ups still required (or use as GPIOs).

(GMUX_INT)

160 mA

Connect +3.3V_RGBDAC pin to GND.

RGB DAC Disable:

TMDS: Power +VDD_IFPx at 3.3V

180 mA

30 mA

210 mA

60 mA

40 mA 60 mA

40 mA 20 mA

180 mA

NOTE: 100K pull-downs required if HPLUG_DET0/HPLUG_DET1 are not used.

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

GPIO Pull-Ups

DDC Mode Pull-downs

NOTE: DP_AUX_CH1 also requires pull-downs if used for dual-mode DisplayPort (DP++). If unused no pulls are necessary, if used for TMDS/HDMI only then only pull-ups are necessary.

160 mA

16 36

8

16

8

23 74

8

FBGA

MCP89M-A01

OMIT

U1400

8

67

23 74

8

16

8

16 56

16

5%

1/16W

402

MF-LF

10K

R1782

10K

MF-LF

402

1/16W

5%

R1781

10K

MF-LF

402

1/16W

5%

R1780

MF-LF

402

1/16W

5%

100K

R1711

MF-LF

402

1/16W

5%

100K

R1710

MCP Graphics

SYNC_MASTER=T27_MLB

SYNC_DATE=11/05/2009

DP_IG_ML0_P<3>

DP_IG_AUX_CH0_P DP_IG_AUX_CH0_N

SATARDRVR_A_EN AUD_IP_PERIPHERAL_DET

=PP3V3_S0_MCP_GPIO

MIKEY_MIC_LOAD_DET

DP_IG_AUX_CH0_N

DP_IG_AUX_CH0_P

DP_IG_AUX_CH1_P

SATARDRVR_A_EN

DP_IG_HPD1

TP_MCP_RGB_VSYNC

=MCP_IFPA_TXD_P<0>

DP_IG_ML1_P<0>

DP_IG_ML0_N<0>

PP3V3_S0_MCP_DAC

=PP1V05_S0_MCP_PLL_IFP

PP1V05_S0_MCP_PLL_CORE

=PP3V3R1V8_S0_MCP_IFP_VDD

DP_IG_HPD0

=MCP_IFPAB_DDC_DATA

MCP_IFPAB_VPROBE

=MCP_IFPB_TXD_P<0>

TP_MCP_RGB_DAC_VREF

DP_IG_ML0_N<3>

DP_IG_ML0_N<2>

DP_IG_ML0_N<1>

DP_IG_ML0_P<2>

DP_IG_ML1_P<2>

DP_IG_ML1_P<1>

DP_IG_ML1_N<2>

DP_IG_ML1_P<3>

TP_MCP_RGB_RED

TP_MCP_RGB_HSYNC

TP_MCP_RGB_GREEN

LCD_IG_BKLT_EN

=MCP_IFPB_TXD_N<3>

=MCP_IFPB_TXD_N<0> =MCP_IFPB_TXD_P<1>

=MCP_IFPB_TXC_P

=MCP_IFPA_TXD_N<3>

=MCP_IFPA_TXD_P<3>

=MCP_IFPA_TXD_N<2>

=MCP_IFPA_TXD_P<2>

=MCP_IFPA_TXC_P =MCP_IFPA_TXC_N

MIKEY_MIC_LOAD_DET

AUD_IP_PERIPHERAL_DET

MCP_IFPAB_RSET

MCP_TMDS0_RSET

DP_IG_ML1_N<1>

MCP_TMDS0_VPROBE

=MCP_IFPB_TXD_P<3>

=MCP_IFPAB_DDC_CLK

DP_IG_ML1_N<3>

DP_IG_ML0_P<1>

DP_IG_ML0_P<0>

=PP1V05_S0_MCP_DP0_VDD

LCD_IG_BKLT_PWM

LCD_IG_PWR_EN

=MCP_IFPB_TXC_N

=MCP_IFPB_TXD_N<1> =MCP_IFPB_TXD_P<2> =MCP_IFPB_TXD_N<2>

=MCP_IFPA_TXD_N<0>

=MCP_IFPA_TXD_N<1>

TP_MCP_RGB_BLUE

=MCP_IFPA_TXD_P<1>

DP_IG_ML1_N<0>

DP_IG_AUX_CH1_N PP3V3_S0_MCP_PLL_DP_USB

TP_MCP_RGB_DAC_RSET

17 OF 109

A.13.0

051-8563

16 OF 80

B29

H25

F29

C31 B31

D31

A31

E31

C29 D29

K22

C22

L22

B22

D26 E26

F26

K25 K26

F25 G25 E25 D25

F28 G28

E28 D28 A28 A29 C28 B28

H26 J26 J25

L28 K28

M23

N23

M22

L24

N25

M25

L26

N24

M26

A22

L25

A23

A26 B26 C26

E22 D22 F22 G22 H22 J22

B23 C23

L23 K23 J23 H23 G23 F23 D23 E23

J28 G29

F31

H28

K20

L20

N21

N22

G26

C25

B25

A25

1 2

8

16

8

16

16 36

16 56

7

17 18

16

8

23

7

23

22

7

23

8

7

23

8

22

8

IN

BI

IN IN IN IN

IN IN

USB0_N USB0_P

SATA_A0_RX_N

SATA_A1_TX_P SATA_A1_TX_N

USB4_N

SATA_A0_RX_P

USB1_P USB1_N

USB2_P USB2_N

USB3_N

USB3_P

USB4_P

USB5_P USB5_N

USB6_P USB6_N

USB7_P USB7_N

USB8_N

USB9_N

USB9_P

USB10_N

USB10_P

USB_OC3*/GPIO_28_MGPIO_1

USB_RBIAS_GND

RGMII_VREF

RGMII_TXD1

RGMII_TXD0

RGMII_TXD3

RGMII_TXD2

RGMII_TXCLK RGMII_TXCTL

RGMII_MDC

RGMII_MDIO

BUF_25MHZ

RGMII_RESET*

SATA_A0_TX_P SATA_A0_TX_N

SATA_A1_RX_P

SATA_A1_RX_N

SATA_B0_TX_P SATA_B0_TX_N

SATA_B0_RX_N SATA_B0_RX_P

SATA_B1_TX_P SATA_B1_TX_N

SATA_B1_RX_N SATA_B1_RX_P

SATA_LED*/GPIO_30

SATA_TERMP

NC_1 NC_2

NC_4

NC_3

RGMII_RXD1

RGMII_RXD0

RGMII_RXD2 RGMII_RXD3

RGMII_RXCLK RGMII_RXCTL

RGMII_INTR/GPIO_35

+3.3V_PLL_MAC_DUAL

RGMII_COMP_VDD RGMII_COMP_GND

USB8_P

USB_OC2*/GPIO_27_MGPIO_0

USB_OC1*/GPIO_26

USB_OC0*/GPIO_25

USB11_P

USB11_N

LAN

SATA

USB

(6 OF 11)

BI

IN

OUT

IN

OUT

NC NC NC NC

IN

BI

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Connect RGMII_INTR to 10K pull-down (if not used as GPIO).

Internal MAC Disable:

+3.3V_PLL_MAC_DUAL must remain connected to 3.3V RMGT rail. RGMII_COMP_VDD/_GND must remain connected as shown.

Connect RGMII_MDIO to 10K pull-down.

Connect RGMII_RXCTL to 10K pull-down.

20 mA

External A

Bluetooth

IR

All other pins can be left TP or NC.

Connect RGMII_VREF to 10K pull-down.

Connect RGMII_RXCLK to 10K pull-down.

T57

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

Connect RGMII_RXD<0:3> together to 10K pull-down.

OC2# Also for EXTE OC3# Also for EXCARD

External B

External D

OHCI0/EHCI0OHCI1/EHCI1

USB JTAG in S3/S4/S5.

Only USB8-11 support nV

Geyser Trackpad/Keyboard

Watermelon

SD Card/ExpressCard

Camera/External E

AirPort (PCIe Mini-Card)

Internal 19.5K Pull-Downs on all USB pairs

External C

8

76

8

76

8

76

8

76

8

76

8

76

8

76

R1810

1% 1/16W MF-LF

402

49.9

R1811

1%

402

49.9

MF-LF

1/16W

MCP89M-A01

FBGA

U1400

OMIT

29 75

37 75

47 75

8

75

8

75

30 75

MF-LF

R1850

402

5%

8.2K

1/16W

R1851

1/16W

5%

8.2K

402

MF-LF

R1852

1/16W MF-LF

402

5%

8.2K

R1853

5% MF-LF

1/16W 402

8.2K

29 75

8

75

8

75

8

75

8

75

8

75

8

75

37 75

887

1/16W

1% MF-LF

402

R1860

36 74

R1805

MF-LF

1%

402

1/16W

2.49K

31

38 75

R1800

5%

100K

402

MF-LF

1/16W

SYNC_MASTER=T27_MLB

SYNC_DATE=11/23/2009

MCP SATA, USB & Ethernet

NC_USB_T57_P NC_USB_T57_N

USB_EXTC_P

USB_WM_P USB_WM_N

USB_CAMERA_N

USB_CAMERA_P

USB_EXTA_P

USB_EXTA_N

USB_MINI_N

USB_EXTC_N

USB_EXTA_OC_L

USB_EXTD_OC_L

USB_EXTB_OC_L

MCP_USB_RBIAS_GND

TP_SATA_C_D2RP

TP_SATA_C_R2D_CN

TP_SATA_C_R2D_CP

SATA_HDD_D2R_N

SATA_ODD_R2D_C_P SATA_ODD_R2D_C_N

SATA_HDD_D2R_P

USB_MINI_P

USB_SDCARD_P USB_SDCARD_N

USB_EXTD_P USB_EXTD_N

USB_TPAD_N

USB_EXTB_N

USB_EXTB_P

USB_IR_N

USB_IR_P

MCP_RGMII_VREF

TP_ENET_TXD<1>

TP_ENET_TXD<0>

TP_ENET_TXD<3>

TP_ENET_TXD<2>

TP_ENET_CLK125M_TXCLK TP_ENET_TX_CTRL

TP_ENET_MDC ENET_MDIO

TP_MCP_CLK25M_BUF0_R

TP_ENET_RESET_L

SATA_HDD_R2D_C_P SATA_HDD_R2D_C_N

SATA_ODD_D2R_P

SATA_ODD_D2R_N

TP_SATA_C_D2RN

TP_SATA_D_R2D_CP TP_SATA_D_R2D_CN

TP_SATA_D_D2RN TP_SATA_D_D2RP

MXM_GOOD_L

MCP_SATA_TERMP

ENET_RXD<1>

ENET_RXD<0>

ENET_RXD<2> ENET_RXD<3>

ENET_CLK125M_RXCLK ENET_RX_CTRL

ENET_ENERGY_DET PP3V3_ENET_MCP_PLL_MAC

MCP_MII_COMP_VDD MCP_MII_COMP_GND

USB_TPAD_P

USB_EXTC_OC_L

USB_BT_P

USB_BT_N

=PP3V3_S5_MCP_GPIO

=PP3V3_S0_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

18 OF 109

A.13.0

051-8563

17 OF 80

1

2

1

2

C20 B20

AJ4

AJ3 AJ2

D20

AJ5

J20 H20

C19 B19

F20

G20

E20

E19 D19

G19 F19

J17 H17

H19

B17

C17

D17

E17

K19

L19

C13

H13

G13

D14

F14

G14 E14

F13 K13

J13

J14

AH4 AH5

AH3

AH2

AJ6 AJ7

AH7 AH6

AL4 AL3

AL1 AL2

AH1

AJ1

G4 E7

F4

F7

C14

B14

D16 F16

E16 A14

H14

M16

D13 E13

J19

K17

L17

A17

F17

G17

1

2

1

2

1

2

1

2

1

2

1

2

1

2

37

75

74

22

76

7

18

7

16 18

7

19 22

OUT

IN

OUT

HDA_SDATA_OUT

HDA_BITCLK

HDA_RESET*

HDA_SYNC

LPC_SERIRQ

LPC_FRAME*

LPC_RESET*

LPC_CLK0

MISC_VDDEN0/GPIO_47 MISC_VDDEN1/GPIO_48

MISC_VDDEN4/GPIO_19

MISC_VDDEN3/GPIO_18

MISC_VDDEN2/GPIO_17

MEM_VDD_SEL/GPIO_46

FANCTL0/GPIO_61

FANRPM0/GPIO_60/MGPIO_2

FANCTL1/GPIO_62

SLP_S3*

FANRPM1/GPIO_63/MGPIO_3

SLP_S5*

SLP_RMGT*

MCP_VID0/GPIO_13

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

SPI_CS0*/GPIO_10

SPI_DI/GPIO_08 SPI_DO/GPIO_09

SPI_CLK/GPIO_11

SPKR/GPIO_1

THERM_DIODE_N

THERM_DIODE_P

SMB_DATA0

SMB_CLK1/MSMB_CLK

SMB_CLK0

SMB_ALERT*/GPIO_64

SMB_DATA1/MSMB_DATA

SUS_CLK/GPIO_34

BUF_SIO_CLK/GPIO_33

PKG_TEST

TEST_MODE_EN

PKG_TEST2

+VDD_HDA

HDA_SDATA_IN0

HDA_PULLDN_COMP

HDA_SDATA_IN1/GPIO_2

LPC_AD1

LPC_AD0

LPC_DRQ0*/GPIO_43

LPC_AD3

LPC_AD2

LPC_CLKRUN*/GPIO_42

EXT_SMI*/GPIO_32

SIO_PME*/GPIO_31

A20GATE/GPIO_55 KBRDRSTIN*/GPIO_56

RSTBTN*

PWRBTN*

RTC_RST*

PWRGD_SB PWRGD

MCP_WAKE_REQ*

MCP_MEMVDD_EN/GPIO_44

MEMVTT_EN/GPIO_45

INTRUDER*

MGPU_PIO1/GPIO_7

MGPU_PIO0/GPIO_6

MGPU_PIO3/GPIO_24

MGPU_PIO2/GPIO_23

JTAG_TDO

JTAG_TDI

JTAG_TRST* JTAG_TCK

JTAG_TMS

XTALIN

XTALIN_RTC

XTALOUT

XTALOUT_RTC

MCP_VID3/GPIO_16

MCP_WAKE_DIS*

MISC LPC

(7 OF 11)

HDA

OUT

IN

IN OUT

IN

OUT

IN

OUT OUT OUT

OUT

OUT OUT

OUT

IN

OUT OUT

OUT

BI

OUT

BI

IN

OUT IN

IN

OUT

BI

OUT

BI

OUT

IN

BI

OUT

IN

OUT

IN

BI

OUT

BI

IN

OUT

IN

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

not use LPC for BootROM override.

LPC ROMs. So Apple designs will

NOTE: MCP89 does not support FWH, only

these pins.

NOTE: MCP89 A01 has strong (~10K) pull-downs on these pins.

HDA Output Caps

(IPD)

Current numbers from MCP89 A01 Bring-Up Support document (MCP89_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

For EMI Reduction on HDA interface

Confirmed OK for this signal.

(IPD)

(IPU-S5)

(IPU)

Platform-Specific Connections

(IPD)

MCP_SPKR: 0 = USER mode (Normal boot mode)

1 = SAFE mode (For ROMSIP recovery)

70 mA

behavior of Intel’s SLP_S4# signal.

NOTE: MCP SLP_S5# signal has the

(IPU)

SPI

1

(IPU-S5)

BUF_SIO_CLK Frequency

SPI_CLK

I/F

HDA_SYNC

1

0

(IPU)

(IPD)

(IPU)

(IPU-S5)

LPC

LPC_FRAME#

0

BIOS Boot Select

Frequency0SPI_DO

1

SPI Frequency Select

1

0

14.31818 MHz

24 MHz

Frequency

0

1

(IPU)

(IPD)

70 mA

(IPD)

(IPU)

(IPU-S5)

pull-downs on

strong (~10K)

(IPU)

NOTE: MCP89 A01 has

Connects to SMC for automatic recovery.

25.0 MHz

31.2 MHz

42.7 MHz

62.5 MHz

NOTE: 42 & 62 MHz use FAST_READ command. Straps not provided on this page.

Output limited to +VDD_HDA.

GPIO Pull-Ups/Downs

39 41 75

18 24 75

39 41 24 75

1

2

R1961

MF-LF

1/16W

5%

10K

402

OMIT

U1400

FBGA

MCP89M-A01

R1953

22

5%

402

1/16W MF-LF

51 75

R1952

22

1/16W

5%

402

MF-LF

R1951

5%

22

1/16W MF-LF

402

R1950

1/16W

22

402

5%

MF-LF

51 75

R1900

49.9

MF-LF

1/16W

1%

402

51 75

24

39

12

24

18 62

45 79

6

18 39 40 65

65

6

39 65 69

41 75

6

18 41 75

41 75

R1970

402

5%

10K

MF-LF

1/16W

40

R1959

10K

402

5% MF-LF

1/16W

R1975

402

1/16W

1% MF-LF

1K

24 75

18 29 65

42 75

12 42 75

R1930

402

1/16W MF-LF

5%

10K

R1931

402

5% 1/16W MF-LF

100K

12

24

39

40

R1920

1/16W

402

MF-LF

49.9K

1%

R1921

49.9K

402

1% 1/16W MF-LF

C1951

10PF

CERM 402

5% 50V

C1950

402

5%

10PF

50V

CERM

C1953

CERM 402

5%

10PF

50V

402

C1952

50V

CERM

5%

10PF

39 41

20

20 65

R1960

1/16W

22

402

5%

MF-LF

R1910

402

22

5%

1/16W MF-LF

R1912

5%221/16W MF-LF

402

R1911

402

MF-LF1/16W

22

5%

R1913

5%221/16W MF-LF

402

39 41 75

56

39

56

6

18 41 50

18 21

6

18

18 25 26 39

18 30

18 36

8

18 31

39 40 65

6

18

60

18 40

R1985

402

100K

1/16W MF-LF

5%

R1996

5%

1/16W

402

MF-LF

10K

R1988

10K

MF-LF1/16W

5% 402

10K

R1980

MF-LF

5%

1/16W

402

R1987

5%

1/16W

402

MF-LF

100K

R1990

10K

5%

1/16W MF-LF

402

R1991

10K

1/16W MF-LF

4025%

R1989

5%

1/16W

402

MF-LF

10K

R1997

100K

5%

1/16W

402

MF-LF

R1981

10K

MF-LF

402

1/16W

5%

R1992

100K

4025%

1/16W MF-LF

R1993

4025%

1/16W MF-LF

100K

R1994

4025%

1/16W MF-LF

100K

R1995

100K

MF-LF1/16W

5% 402

R1984

5%

1/16W MF-LF

10K

402

100K

R1986

402

MF-LF1/16W

5%

18 41

6

18 39 40 65 39

39 41 18 24 75

R1965

402

5%

MF-LF

1/16W

33

R1966

NO STUFF

10K

5% 1/16W

402

MF-LF

R1983

5%

1/16W MF-LF

10K

402

R1998

20K

MF-LF1/16W

5% 402

100K

R1999

5%

1/16W MF-LF

402

MCP HDA, LPC & MISC

SYNC_DATE=11/23/2009

SYNC_MASTER=T27_MLB

MCP_VID<0>

LPC_RESET_L

RTC_RST_L

SMC_IG_THROTTLE_L

MCP_CLK25M_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALIN

JTAG_MCP_TCK

SM_INTRUDER_L

=PP3V3R1V5_S0_MCP_HDA

PCIE_RESET_L

=PP3V3_S3_MCP_GPIO

=PP3V3_S5_MCP_GPIO

=PP3V3_S0_MCP_GPIO

ENET_LOW_PWR SMC_IG_THROTTLE_L

HDA_BIT_CLK_R

SMBUS_MCP_1_DATA

HDA_SDIN0

AUD_IPHS_SWITCH_EN

PM_BATLOW_L

MCP_PS_PWRGD

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

GFXVCORE_PWR_EN

T57_RESET

JTAG_MCP_TMS

LPC_AD<2>

MCP_MEM_VTT_EN

JTAG_MCP_TDI

LPC_PWRDWN_L

PM_SLP_S5_L

LPC_RESET_L

MAKE_BASE=TRUE

PM_SLP_S4_L

MCP_WAKE_REQ_L

JTAG_MCP_TDO

HDA_SDOUT

HDA_RST_R_L

HDA_RST_L

HDA_BIT_CLK_R

HDA_BIT_CLK

=PP3V3_S0_MCP_GPIO

LPC_FRAME_L

HDA_SDOUT_R

ARB_DETECT_L

SPI_MISO SPI_MOSI_R

MCP_THMDIODE_N SMBUS_MCP_0_CLK

SMBUS_MCP_0_DATA SMBUS_MCP_1_CLK

AP_PWR_EN

PM_CLK32K_SUSCLK_R

SPIROM_USE_MLB

HDA_SYNC

LPC_FRAME_R_L

MCP_CPU_VTT_EN_L

SMC_RUNTIME_SCI_L

LPC_SERIRQ

AUD_I2C_INT_L

MCP_HDA_PULLDN_COMP

LPC_AD_R<1>

LPC_AD_R<0>

PM_CLKRUN_L

LPC_AD_R<3>

LPC_AD_R<2>

TP_MLB_RAM_SIZE

PM_LATRIGGER_L

PM_PWRBTN_L PM_SYSRST_DEBOUNCE_L

PM_SLP_S3_L PM_SLP_RMGT_L

MCP_VID<2>

MCP_THMDIODE_P

HDA_SYNC_R

MCP_TEST_MODE_EN

RTC_CLK32K_XTALOUT

PM_RSMRST_L

JTAG_MCP_TRST_L

SPIROM_USE_MLB

MCP_CPU_VTT_EN_L MLB_RAM_VENDOR T57_PWR_EN LPCPLUS_GPIO

ODD_PWR_EN_L MEM_EVENT_L

MCP_VID<0> MCP_VID<1> MCP_VID<2>

AP_PWR_EN ARB_DETECT_L

HDA_RST_R_L HDA_SYNC_R

MCP_VID<3>

SPI_MISO

HDA_SDOUT_R

SMC_WAKE_SCI_L

PP3V3_G3_RTC

SDCARD_RESET T57_RESET GFXVCORE_PWR_EN

SPI_CS0_R_L SPI_CLK_R

MCP_SPKR

MCP_MEM_VDD_EN

LPC_CLK33M_SMC_R

ODD_PWR_EN_L

MCP_VID<3>

MCP_VID<1>

PM_SLP_S4_L

SDCARD_RESET

ENET_LOW_PWR

MEM_EVENT_L

LPCPLUS_GPIO

MLB_RAM_VENDOR T57_PWR_EN SMC_ADAPTER_EN

MCP_MEM_VDD_SEL_1V5

19 OF 109

A.13.0

051-8563

18 OF 80

E1

E4

D1

D2

L8

L7

K7

L5

K10 C8

G8

D8

A8

C7

H7 H6 G6

C4

H4

D5

K9

K3

K5

K4

E11

F11 B8

D7

H3

G2

G3

B4 A5

A4

C5

B5

H11

H1

L16

D4

K16

D6

E2

D3

E3

L1

K1

K2

L3

L2

L6

G11

D11

B3 H2

F10

J10

G16

C11

C2

H16

B7

G10

J16

H5

G5

J11

H10

D10

C10

E10 A10

B10

A11

B16

B11

C16

K6

A7

1 2

1

2

1

2

1

2

1

2

121

2

121

2

1

2

1

2

1

2

1

1 2

1 2 1 2

1 2

1 2 1 2 1 2 1 2

1 2

1

2

1 2

8

22

15 24

7

17

7

16 17 18

8

18 31

18 40

18 75

7

16 17 18

18 75

18

75 18 75

6

18 41 50

18

6

18

18 41

18 36

18 25 26 39

18 62

18 29 65

18

18 75

18 62

6

18 41 75

18 75

7

19 22

18 30

6

18

18 21

18

+VDD_MEM_30 +VDD_MEM_31

+VDD_MEM_28 +VDD_MEM_29

+VDD_MEM_25 +VDD_MEM_26 +VDD_MEM_27

+VDD_MEM_23 +VDD_MEM_24

+VDD_MEM_22

+VDD_MEM_20 +VDD_MEM_21

+VDD_MEM_17 +VDD_MEM_18 +VDD_MEM_19

+VDD_MEM_15 +VDD_MEM_16

+VDD_MEM_12 +VDD_MEM_13 +VDD_MEM_14

+VDD_MEM_10 +VDD_MEM_11

+VDD_MEM_8 +VDD_MEM_9

+VDD_MEM_7

+VDD_MEM_5 +VDD_MEM_6

+VDD_MEM_4

+VDD_MEM_3

+VDD_MEM_2

+VDD_MEM_1

+VTT_CPU2_1 +VTT_CPU2_2 +VTT_CPU2_3 +VTT_CPU2_4

+VTT_CPU_27

+VTT_CPU_24 +VTT_CPU_25 +VTT_CPU_26

+VTT_CPU_23

+VTT_CPU_22

+VTT_CPU_21

+VTT_CPU_20

+VTT_CPU_19

+VTT_CPU_18

+VTT_CPU_16 +VTT_CPU_17

+VTT_CPU_14 +VTT_CPU_15

+VTT_CPU_11 +VTT_CPU_12 +VTT_CPU_13

+VTT_CPU_9 +VTT_CPU_10

+VTT_CPU_8

+VTT_CPU_1

+VTT_CPU_7

+VTT_CPU_6

+VTT_CPU_5

+VTT_CPU_4

+VTT_CPU_3

+VTT_CPU_2

(8 OF 11)

POWER I

POWER II

(9 OF 11)

+VDD_COREB_1

+VDD_COREB_3

+VDD_COREB_2

+VDD_COREB_4 +VDD_COREB_5 +VDD_COREB_6

+VDD_COREB_8

+VDD_COREB_7

+VDD_COREB_9 +VDD_COREB_10 +VDD_COREB_11

+VDD_COREB_13

+VDD_COREB_12

+VDD_COREB_14 +VDD_COREB_15 +VDD_COREB_16

+VDD_COREB_18

+VDD_COREB_17

+VDD_COREB_19 +VDD_COREB_20 +VDD_COREB_21 +VDD_COREB_22 +VDD_COREB_23 +VDD_COREB_24

+VDD_COREB_26

+VDD_COREB_25

+VDD_COREB_27 +VDD_COREB_28 +VDD_COREB_29

+VDD_COREB_31

+VDD_COREB_30

+VDD_COREB_32 +VDD_COREB_33 +VDD_COREB_34

+VDD_COREB_36

+VDD_COREB_35

+VDD_COREB_37 +VDD_COREB_38 +VDD_COREB_39 +VDD_COREB_40 +VDD_COREB_41 +VDD_COREB_42

+VDD_COREB_SENSE

GND_COREB_SENSE

+VIO_SATA_AVDD_1

+VIO_SATA_AVDD_3

+VIO_SATA_AVDD_2

+VIO_SATA_AVDD_4 +VIO_SATA_AVDD_5

+VIO_SATA_DVDD_1 +VIO_SATA_DVDD_2 +VIO_SATA_DVDD_3 +VIO_SATA_DVDD_4 +VIO_SATA_DVDD_5 +VIO_SATA_DVDD_6 +VIO_SATA_DVDD_7 +VIO_SATA_DVDD_8

+VIO_SATA_DVDD_9 +VIO_SATA_DVDD_10 +VIO_SATA_DVDD_11 +VIO_SATA_DVDD_12

+VDD_DUAL_RMGT_1

+VDD_DUAL_RMGT_2

+3.3V_DUAL_RMGT_1

+3.3V_DUAL_USB_1

+3.3V_DUAL_RMGT_2

+3.3V_DUAL_USB_2

+3.3V_DUAL_1 +3.3V_DUAL_2

+3.3V_HVDD_3

+3.3V_HVDD_1 +3.3V_HVDD_2

+3.3V_5

+3.3V_3 +3.3V_4

+3.3V_2

+3.3V_1

+VDD_DUAL_AUXC_2

+VDD_DUAL_AUXC_1

+VDD_DUAL_AUXC_3

+3.3V_VBAT

+VIO_PE_AVDD1_4 +VIO_PE_AVDD1_5

+VIO_PE_AVDD1_1

+VIO_PE_AVDD1_3

+VIO_PE_AVDD1_2

+VIO_PE_AVDD0_5 +VIO_PE_AVDD0_6

+VIO_PE_AVDD0_3 +VIO_PE_AVDD0_4

+VIO_PE_AVDD0_2

+VIO_PE_AVDD0_1

+VIO_PE_DVDD1_2 +VIO_PE_DVDD1_3

+VIO_PE_DVDD1_1

+VIO_PE_DVDD0_3 +VIO_PE_DVDD0_4

+VIO_PE_DVDD0_2

+VIO_PE_DVDD0_1

+VDD_COREA_32 +VDD_COREA_33

+VDD_COREA_30 +VDD_COREA_31

+VDD_COREA_29

+VDD_COREA_28

+VDD_COREA_27

+VDD_COREA_25

+VDD_COREA_24

+VDD_COREA_26

+VDD_COREA_22 +VDD_COREA_23

+VDD_COREA_21

+VDD_COREA_19 +VDD_COREA_20

+VDD_COREA_18

+VDD_COREA_16 +VDD_COREA_17

+VDD_COREA_15

+VDD_COREA_14

+VDD_COREA_11 +VDD_COREA_12 +VDD_COREA_13

+VDD_COREA_9 +VDD_COREA_10

+VDD_COREA_6 +VDD_COREA_7 +VDD_COREA_8

+VDD_COREA_4 +VDD_COREA_5

+VDD_COREA_1

+VDD_COREA_3

+VDD_COREA_2

GND_COREA_SENSE

+VDD_COREA_SENSE

(10 OF 11)

GND

GND_28 GND_29

GND_27

GND_97 GND_98

GND_69

GND_68

GND_71

GND_70

GND_72

GND_74

GND_73

GND_75 GND_76 GND_77 GND_78 GND_79 GND_80 GND_81 GND_82

GND_84

GND_83

GND_85 GND_86 GND_87

GND_89

GND_88

GND_90

GND_92

GND_91

GND_94

GND_93

GND_95 GND_96

GND_99

GND_102

GND_100 GND_101

GND_103 GND_104 GND_105

GND_107

GND_106

GND_109

GND_108

GND_110

GND_112

GND_111

GND_113 GND_114 GND_115

GND_117

GND_116

GND_118 GND_119 GND_120

GND_122

GND_121

GND_123 GND_124 GND_125 GND_126 GND_127 GND_128

GND_130

GND_129

GND_131

GND_133

GND_132

GND_134

GND_2

GND_1

GND_4

GND_3

GND_6 GND_7

GND_5

GND_8 GND_9

GND_12

GND_11

GND_10

GND_14

GND_13

GND_15 GND_16 GND_17

GND_19

GND_18

GND_20 GND_21 GND_22 GND_23 GND_24 GND_25 GND_26

GND_30 GND_31 GND_32

GND_35

GND_34

GND_33

GND_37

GND_36

GND_38

GND_40

GND_39

GND_43

GND_41 GND_42

GND_45

GND_44

GND_47 GND_48

GND_46

GND_50

GND_49

GND_53

GND_52

GND_51

GND_55

GND_54

GND_56 GND_57 GND_58

GND_60

GND_59

GND_61 GND_62 GND_63 GND_64 GND_65 GND_66 GND_67

(11 OF 11)

GND

GND_157 GND_158

GND_199

GND_198

GND_197

GND_196

GND_195

GND_194

GND_193

GND_192

GND_191

GND_188

GND_190

GND_189

GND_187

GND_186

GND_183 GND_184 GND_185

GND_182

GND_181

GND_179 GND_180

GND_178

GND_177

GND_176

GND_175

GND_173 GND_174

GND_170

GND_172

GND_171

GND_169

GND_168

GND_166

GND_165

GND_167

GND_164

GND_163

GND_161

GND_160

GND_162

GND_159

GND_156

GND_155

GND_154

GND_153

GND_152

GND_150 GND_151

GND_147

GND_149

GND_148

GND_146

GND_145

GND_142 GND_143 GND_144

GND_140 GND_141

GND_138 GND_139

GND_137

GND_136

GND_135

GND_264

GND_263

GND_262

GND_261

GND_259

GND_258

GND_260

GND_256 GND_257

GND_254

GND_253

GND_255

GND_252

GND_251

GND_250

GND_249

GND_248

GND_246 GND_247

GND_245

GND_244

GND_243

GND_241 GND_242

GND_240

GND_239

GND_238

GND_236

GND_235

GND_237

GND_233 GND_234

GND_232

GND_230 GND_231

GND_228 GND_229

GND_227

GND_225 GND_226

GND_223 GND_224

GND_220

GND_222

GND_221

GND_219

GND_218

GND_217

GND_215 GND_216

GND_213

GND_212

GND_214

GND_211

GND_210

GND_209

GND_208

GND_207

GND_205 GND_206

GND_203 GND_204

GND_202

GND_200 GND_201

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

500 mA (AVDD0 & AVDD1)

200 mA (DVDD0 & DVDD1)

30 mA

150 mA

5 mA (S0)

140 mA

240 mA

40 mA

200 mA

300 mA

100 mA

300 mA

15350 mA (0.85V)

8450 mA (0.85V)

200 mA

2000 mA 4300 mA

Instead connect regulator sense point

COREA/COREB are powered by separate regulators.

as close to COREB FET as possible.

(PE0[3:0])

(PE0[5:4], PE1[1:0])

NOTE: VDD_COREx_SENSE signals should NOT be used for remote sensing unless

(PE0[3:0])

(PE0[5:4], PE1[1:0])

250 mA

?? uA (G3)

NOTE: "SW" rails are dynamically switched in the S0 state as needed, controlled by MCP89 GPIOs.

U1400

MCP89M-A01

OMIT

FBGA

U1400

FBGA

MCP89M-A01

OMIT

U1400

MCP89M-A01

OMIT

FBGA

U1400

FBGA

OMIT

MCP89M-A01

SYNC_MASTER=T27_MLB

SYNC_DATE=08/06/2009

MCP Power & Ground

=PP3V3_ENET_MCP_RMGT

=PP0V9_ENET_MCP_RMGT

=PP1V05_S0_MCP_FSB

=PP1V5R1V35_SW_MCP_MEM

=PP0V9_S5_MCP_VDD_AUXC

PP3V3_G3_RTC

TP_MCP_VDDCOREA_SENSEP

=PP1V05_SW_MCP_FSB

=PP3V3_S0_MCP

TP_MCP_VDDCOREB_SENSEN

=PP1V05_S0_MCP_PE_AVDD0

=PPVCORE_SW_MCP_GFX

PP1V05_S0_MCP_SATA_AVDD

=PP1V05_S0_MCP_SATA_DVDD

=PPVCORE_S0_MCP

TP_MCP_VDDCOREA_SENSEN =PP1V05_S0_MCP_PE_DVDD0

=PP1V05_S0_MCP_PE_DVDD1

=PP3V3_S0_MCP_HVDD

TP_MCP_VDDCOREB_SENSEP

=PP3V3_S5_MCP

=PP1V05_S0_MCP_PE_AVDD1

20 OF 109

A.13.0

051-8563

19 OF 80

AJ10 AF20

AJ8 AF14

AL8 AF17 AJ11

AM3 AL5

AF15

AH12 AM2

AG17 AL6 AG16

AJ9 AF19

AM5 AG19 AF23

AF22 AG20

AG13 AF16

AK8

AM1 AM4

AF21

AF18

AL7

AG14

W27 W28 Y27 Y28

N26

H31 B32 R26

T26

U26

H30

M28

E32

C32

U27 G31

H29 W26

P26 F32 A32

J29 N27

T27

G32

P27

V26

Y26

L29

D32

K29

M4

P4

M2

N12 N4 N14

N10

V20

P3 P1 N11

P6

N6

N2 N9 N8

N3

M10

N1 M5 M7 P2 M8 M11

N7

V19

N16 P5 N5

N15

N13

P9 V17 V18

M13

M14

Y19 Y20 Y17 Y18 P7 P8

U10 T10

AE1

AE3

AE2

AE4 AE5

AF1 AF2 AF3 AF4 AF5 AF6 AF9 AF10 AF11 AE11 AE12 AE13

L12 L13

A13

A20

B13

A19

F8 E8

U13

T11 T12

E5

F5

E29

U12

U11

M17

L11

M20

A16

W12 W13

Y12

AA13

Y13

AD13 AB13

AC12 AD11

AB12

AC13

AE7 AE8

AE6

AE9

AE10

AF8

AF7

P10 P11

AA22

P12

Y22

W22

V22

T9

T5

U22

R5 T7

T4

T8 R8

R2

AB19

P13

R4

AB21

AB18

T1 T2

AB17

R10

T6 T13 R11

R13

R7

T3

AB20

AB22

L9

L10

M32

B2

B18

AM27 AP27

B12

AD7

E12

D12

G12

AL12

A2

AM6 AD37 AG32 H12 AR35 H9 G24 V10

AL30

V5

G7 V29 AP15

AJ12

AN2

AR15

D21

N20

G21

E21

H21 AR27

AM15

AH24

AA31 AM9

K12 J31 E30

V7

AK7

AU12

M31

AP6

A36

B37

F35 L27 D35

AP30

AL24

AH15 B21 AV3

B38

AT38

AA21 AD4 A37 AP18 AN4 B24

V4

D30

AA7

AK4

AD34

R37

M37

AP21

AU37

AM21

D18

B1

AC27

AD5

J2

C1

AM30

AT1

AP24

AT3

AM33 AE27 AJ24

AA8

AH18

AM18

B6

J32 AJ21 AK35

H15

D33

E6 J5

K18

F34

AD10

AN34

R35

V8

AR9

AA10

AA2

H8

R32 AG29

AM12

AP12

V32 AR33

AH21

AA32

J7

K24

AK37

AG34

J8

K21

AG8

AN5

V2

AD2

AD32

D15

AG2

L15 AK32 AR12 AN35 AN37

AH27

E18

H27

N19

L4

D9

AV37

AL27

G15

A3

L18

B15

AJ15

AA4

H18

AU38

E9 E27 L21

AG10

AU1

J4

AU27

AH30

J34

AU33

AR30

AK34

E15

D27

J35

R34

C38

V28

M34

AA11

B27

AL21

V34

K11

AK31

AU21

AA34

M19

K15

E24

N18

AK5

D24

AU30

H24

AR21

B30

AM24

AU9

AA5 G18

B9

AL18 AR24

AD35 AJ18

AG5

AU15

AU24

U21

AA20

AA19

AA18

AB27

AA26

AA17

W19 W20

AD29

AD28

AG4

N17

AA29

AA28

V21

W17

W18 U20

U19

W21

U18

Y21 V31

K8

U17

R31

R28

G30

R29

AB26 M29

AL9

F2 K27

L14 K14

AR18

AG37 AL15

V37 AA37

AU2

AD31

AP9

AD8

AG7

AG35

AJ27 G9

AV36

AR6

B33

AU18

AA35

G27

V35

J37

F37 C3

AK2 AU6

AV2

E33 M35

7

17 22

7

22

7

13 22

14 20 22

7

22

7

18 22

7

22

7

22

7

21 23

22

7

22

7

22

7

22

7

22

7

NC

OUT

IN

BI

D

G S

IN

VCC

D

DONE

G

GND

THRM

S

EN

CNFG

PAD

NC

K1

G

S

SENSE

D

KELVIN

D

G

D

S

D

G

D

S

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NV Requirements:

Q2355/Q2356 chosen for low output capacitance.

CKE must be held low to keep memory in self-refresh.

Clamps also discharge VTT rail via termination resistor on each CKE signal on DIMM.

Clamps release after MCP89 MEMVDD is up and CKEs are driven by MCP89.

Clamps enable before MCP89 MEMVDD rail switched off.

NO STUBS on CKE signals!

DIMM CKE Clamps

<R1>

Approx. Ramp Time (EN to 1.35V, uS): 7.91 + 0.0678 * R1(Kohms)

(G driven to VCC)

Gated Rail Savings: 120mW

NOTE: nVidia recommends Infineon BSC030N03MS for Q2300.

- Min Ramp-Up Time: 20 uS (10% to 90%)

- Max Ramp-Up Time: 65 uS (ENABLE to 90%)

- FET Ron <= 3.8 mOhms

4250 mA

(OR 1.35V)

Q2300

Loading

Rds(on)

Type

Part

N-Channel

4.3 A (EDP)

10 mOhm @3.2V

STMFS4854N

C2300 helps reduce input rail droop during Q2300 turn-on.

44

R2305

MF

560K

402

1/16W

1%

18 65

C2305

0.1UF

402

CERM

10V

20%

C2300

CRITICAL

PLACE_NEAR=Q2300.9:2 mm

1206-1

CERM-X5R

6.3V

20%

100UF

14 26 73

14 25 73

Q2350

SSM3K15FV

SOD-VESM-HF

18

R2350

5%

1/16W

10K

402

MF-LF

U2305

CRITICAL

TDFN

SLG5AP031

Q2300

CRITICAL

DFN

STMFS485NST1G

CRITICAL

NTUD3170NZXXG

SOT-963

Q2355

CRITICAL

NTUD3170NZXXG

Q2356

SOT-963

MCP89 Memory Rail Gating

SYNC_DATE=11/23/2009

SYNC_MASTER=T27_MLB

MCPDDRFET_KELVIN

MCPDDRFET_SENSE

MCP_MEM_VDD_EN

MCPMEM_CNFG

TP_MCPMEM_DONE

=PP1V5R1V35_S0_MCPDDRFET

PP1V5R1V35_SW_MCP

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

=PP5V_S3_MCPDDRFET

MCPMEM_GATE

=PP5V_S3_MCPDDRFET

=PP1V5R1V35_SW_MCP_MEM

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_B_CKE<1>

MEMVTT_EN_L

MEM_B_CKE<0>

MCP_MEM_VTT_EN

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14 19 22

OUT

S

D

G

IN

CNFG

EN

S

THRM

GND

G

DONE

D

VCC

PAD

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

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345678

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<C1>

Approx. Ramp Time (EN to 1V, uS): 43.9 + 0.6943 * C1(pF)

(G driven to VCC)

- Max Ramp-Up Time: 1500 uS (ENABLE to 90%)

Q2400

15.35 A (EDP)

NOTE: nVidia recommends Infineon BSC020N03MS for Q2400.

droop during Q2400 turn-on.

C2400 helps reduce input rail

N-Channel

Si4838BDY

3.2 mOhm @2.5V

- Min Ramp-Up Time: 100 uS (10% to 90%)

- FET Ron <= 2.5 mOhms

Gated Rail Savings: 860mW

NV Requirements:

Type

Part

Loading

Rds(on)

XW2401

PLACE_NEAR=C2400.2:1 mm

SM

XW2400

SM

PLACE_NEAR=C2400.1:1 mm

62 79

Q2400

CRITICAL

SI4838BDY

SO-8

18

C2405

20% 10V CERM 402

0.1UF

C2400

100UF

PLACE_NEAR=Q2400.5:2 mm

CRITICAL

1206-1

CERM-X5R

6.3V

20%

C2406

10% CERM

820PF

402

50V

U2405

SLG5AP033

TDFN

CRITICAL

SYNC_DATE=11/23/2009

SYNC_MASTER=T27_MLB

MCP89 GFX Core Rail Gating

=PPVCORE_SW_MCP_GFX

MCPCORES0_VSEN_N

MCPCORES0_VSEN_P

MCPGFX_GATE

=PPVCORE_S0_MCPGFXFET

MCPGFX_CNFG

GFXVCORE_PWR_EN

VOLTAGE=0.9V

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

MAKE_BASE=TRUE

PPVCORE_SW_MCP_GFX

TP_MCPGFX_DONE

=PP5V_S0_MCPFSBFET

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19 23

7

NC

VOUT

EN

VIN

GND

IN

OUT

+IN

-IN

V+

V-

+IN

-IN

V+

V-

D

S

G

D

S

G

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

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REVISION

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SIZE

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PAGE TITLE

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2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

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345678

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(For R and C)

PLACEMENT_NOTEs:

MCP 1.05V SATA Digital Power

200 mA

MCP 3.3V DP & USB PLL Power

210 mA

MCP 3.3V PCIe/SATA I/O PLL Power

MCP 3.3V/1.5V HDA Power

100 mA

260 mA

50 mA

MCP 1.05V PCIe/SATA PLL Power

70 mA

555 mA

MCP 1.05V CPU/FSB/MEM PLL Power

MCP 1.05V SATA Analog Power

300 mA

MCP 0.9V MAC/SMU Power

MCP 2.0V-3.3V RTC Power

8450 mA (0.85V)

MCP 3.3V AUX/USB Power

MCP Non-GFX Core Power

800 mA 500 mA

240 mA

300 mA

5 mA (S0)

30 mA

550 mA

140 mA150 mA

200 mA

2000 mA

4300 mA (1.5V)

MCP 1.05V PCIe Analog Power

MCP 3.3V I/O Power

MCP S0 FSB (VTT) Power

250 mA

? uA (G3)

MCP 1.05V Memory DLL Power

20 mA

MCP 3.3V MAC PLL Power

20 mA

MCP CPU FSB (VTT) Power

325 mA

160 mA

MCP Memory Power

MCP 0.9V AUX Core Power

MCP 1.05V PCIE Digital Power

MCP 3.3V MAC/SMU Power

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

70 mA

MCP 3.3V PLL Power

MCP 1.05V Core/Misc PLL Power

C2504

HTOL_SENSE:YES

MCPHVDD:P3V3

SMC_P_FOLLOW

OPA330

SC70-5

Place close to SMC

HTOL_SENSE:YES

SOT-563-HF

NTZD3152P

CRITICAL

Q2592

HTOL_SENSE:YES

SOT-563-HF

NTZD3152P

CRITICAL

Q2592

HTOL_SENSE:YES

4.53K

20%

HTOL_SENSE:YES

0.1UF

L2590

FERR-240-OHM-200MA

C2591

PLACE_NEAR=R2575.1:50 mil

HTOL_SENSE:YES

10V

SMC_N_MIRROR

1/16W

402

C2594

HTOL_SENSE:YES

PP3V3_S0_MCP_HVDD

603

C2580

4.7UF

PLACE_NEAR=R2580.1:50 mil

C2599

0.1UF

LDO:ADJ

C2582

402

MF-LF

HTOL_SENSE:YES

R2590

100K

1%

CERM

CRITICAL

LDO:ADJ

C2597

MIN_LINE_WIDTH=0.4 MM

0.1uF

20% 10V

CRITICAL

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_HVDD

HTOL_SENSE:YES

U2594

20%

402

CERM

R2597

1/16W

402

MF-LF

1%

1K

U2593

SC70-5

OPA330

402

20% 10V

CRITICAL

MF-LF

1/16W

1%

402

R2598

Place close to SMC

HTOL_SENSE:YES

402

C2598

0.22UF

20%

6.3V X5R

100K

5% 1/16W MF-LF

402

HTOL_SENSE:YES

R2599

1/16W

5%

402

MF-LF

0

R2593

MF-LF

1/16W

1%

1K

R2596

402

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 MM

PP3V3_S0_LDO_R

MIN_NECK_WIDTH=0.2 MM

MCPHVDD:P2V5

C2596

SYNC_DATE=08/15/2009

PP3V3_S0_MCP_PLL_DP_USB

1/16W

10K

402

MF-LF

5%

1/16W

5%

10K

R2594

LDO:ADJ

MF-LF

C2595

4.7UF

CERM

SMC_N_FOLLOW

4.7UF

MCP Standard Decoupling

SYNC_MASTER=T27_MLB

6.3V

C2590

10%

U2592

402

1UF

10V X5R 402

C2593

MCPHVDD:P2V5

402

R2592

MF-LF

1/16W

5%

10K

U2592

SC70

MIC5365-2.5V

CRITICAL

OMIT_TABLE

10% 10V

1UF

402

X5R

C2592

CERM

SMC_P10

L2595

220-OHM-2.2A

0603

PLACE_NEAR=R2595.1:50 mil

GND_MCP_PLL_DP_USB

0402

SMC_NB_MISC_ISENSE

VOLTAGE=3.3V

R2595

MIN_NECK_WIDTH=0.25 MM

=PP3V3_S0_OPA333

MIN_LINE_WIDTH=0.4 MM

39

LDO_ADJMCP_PLL_LD0_EN

4.7UF

=PP3V3_S0_MCP_HVDD

4.7UF

MIN_NECK_WIDTH=0.2 MM

1

353S2979

IC,LDO,TPS717,ADJ,150MA,3%,SC70,HFLF

IC,LDO,MIC5365,2.5V,150MA,2%,SC70-5,HFLF

353S2971

1

MIN_LINE_WIDTH=0.25 MM VOLTAGE=0V

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 MM

603

6.3V

20%

CERM

MF

5%

0.33

1/16W

0402

10V

0.1UF

CERM

20%

402

10V CERM

0.1uF

20%

VOLTAGE=3.3V

CRITICAL

20%

402

CERM

10V

20%

0.1UF

39

PP1V05_S0_MCP_PLL_CORE

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_PEXSATA

CRITICAL

220-OHM-2.2A

L2580

0603

CRITICAL

220-OHM-2.2A

0603

L2575

402

20%

4V

X5R

10V

C2581

CERM 402

0.1UF

402

CERM

C2575

402

4.7UF

20% X5R

4V

C2576

402

CERM

10V

20%

0.1UF

C2577

20% 10V CERM

0.1uF

402

0.1UF

10V

C2583

20%

20% 10V

402

C2584

0.1UF

20% 10V CERM

C2578

402

0.1UF

402

CERM

10V

20%

C2579

=PP1V05_S0_MCP_PLL_UF

VOLTAGE=0V

GND_MCP_PLL_FSB

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_FSBMEM

L2570

CRITICAL

0603

220-OHM-2.2A

PLACE_NEAR=R2570.1:50 mil

C2570

20%

4V

4.7UF

402

X5R

1/16W

5%

0402

0.33

R2570

MF

CERM

0.1UF

20%

402

10V

C2571 C2572

10V

0.1uF

402

CERM

20%

C2573

0.1UF

20% 10V CERM 402

PP1V05_S0_MCP_SATA_AVDD

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

L2567

0603

30-OHM-5A

X5R

603-1

10UF

6.3V

C2567

20% 20%

4V X5R

C2568

4.7UF

402

0.1UF

402

CERM

10V

20%

C2569

=PP3V3R1V5_S0_MCP_HDA

=PP1V05_S0_MCP_SATA_DVDD

=PP0V9_ENET_MCP_RMGT

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_PE_DVDD

=PP1V05_SW_MCP_FSB

=PP3V3_ENET_MCP_PLL_MAC

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP3V3_ENET_MCP_PLL_MAC

VOLTAGE=3.3V

=PP3V3_S0_MCP

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_M2CLK_DLL

=PP0V9_S5_MCP_VDD_AUXC

=PP1V5R1V35_SW_MCP_MEM

=PP3V3_S5_MCP

=PPVCORE_S0_MCP

PP3V3_G3_RTC

=PP1V05_S0_MCP_FSB

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PE_AVDD

CRITICAL

0402

FERR-240-OHM-200MA

L2555

4.7UF

CERM

20%

6.3V 603

C2552

20%

CERM

6.3V 603

C2541

10V CERM 402

0.1uF

20%

C2542C2540

4V

4.7UF

402

X5R

20%

C2566

0.1UF

402

CERM

10V

20%

C2565

0.1UF

402

CERM

10V

20%

C2564

402

CERM

10V

20%

0.1UF

C2563

402-1

1UF

X5R

10V

10%

402-1

10V

10%

1UF

X5R

C2562C2561

4V

4.7UF

402

X5R

20%

10UF

X5R

20%

603-1

C2560

6.3V

4.7UF

CERM

20%

6.3V 603

C2555

4.7UF

402

X5R

20%

4V

C2524

1UF

X5R

10V

10%

402-1

C2525C2523

10% 10V

402-1

X5R

1UF

C2522

10% 10V X5R 402-1

1UF

C2521

4V

4.7UF

402

X5R

20%

C2520

6.3V

20% X5R

603-1

10UF

C2547

20% 10V

402

0.1uF

CERM

C2546

402

CERM

10V

20%

0.1uF

C2545

0.1uF

402

10V

20% CERM

C2544

0.1uF

402

CERM

10V

20%

C2543

603

6.3V

4.7uF

CERM

20%

C2550

603

6.3V

4.7uF

CERM

20%

C2551

0.1uF

402

CERM

10V

20%

C2553

603

6.3V

20%

CERM

4.7uF

C2554

20% 10V CERM 402

0.1uF

402

CERM

10V

20%

0.1uF

C2535

C2548

20%

CERM

4.7UF

6.3V 603 402

CERM

20% 10V

0.1uF

C2549

402

X5R

4V

C2528

20%

4.7uF

20% CERM

402

0.1uF

C2529

10V

0.1UF

20% 10V CERM 402

C2556

C2534

20%

402

CERM

10V

0.1uF

C2533

0.1uF

402

CERM

10V

20%

0.1uF

CERM

20%

402

10V

C2537

C2526

0.1uF

402

CERM

10V

20%

C2527

0.1uF

402

CERM

20% 10V

C2501

4.7UF

402

4V

20% X5R

603-1

6.3V

10UF

C2500

30-OHM-5A

0603

L2560

20%

C2510

4V

4.7UF

X5R 402

C2511

402

10V

20%

0.1UF

CERM

C2512

CERM

10V

20%

0.1UF

C2513

0.1UF

402

CERM

10V

20%

C2514

0.1UF

402

10V

20% CERM

C2515

0.1UF

402

CERM

10V

20%

C2516

0.1UF

402

CERM

10V

20%

C2517

20%

0.1UF

402

CERM

10V

C2518

0.1UF

402

CERM

10V

20%

C2519

20% CERM

10V

0.1UF

402

20%

4V

402

X5R

C2536C2530

4V

4.7UF

X5R

20%

402

C2531

402-1

X5R

10V

10%

1UF 1UF

10V 402-1

X5R

10%

C2532

20% 10V CERM 402

0.1UF

C2508

402

CERM

20% 10V

0.1UF

C2505

20%

402

0.1UF

10V CERM

C2506

20% 10V CERM 402

0.1UF

C2507

20% CERM

402

0.1UF

10V

C2502

1UF

10% 10V X5R 402-1

C2503

6.3V

20% X5R

402

0.22UF

R2591

402

=PP3V42_G3H_OPA330

=PP3V3_S0_MCP_PLL_UF

MCPHVDD:P2V5

LDO:FIXED CRITICAL CRITICAL

HTOL_SENSE:NO

RES,0402,0,5%,1/16W

116S0004

1

R2596

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7

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7

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

140 mA

180 mA (1.8V LVDS)

60 mA

15350 mA (0.85V)

If RGBDAC is used, requires ferrite (155S0382) plus 1x 4.7uF 0603 & 1x 0.1uF 0402 cap.

If RGBDAC is not used, tie to GND.

MCP 3.3V RGBDAC Power

MCP GFX Core Power

160 mA

MCP 1.05V DisplayPort Power

MCP 1.05V IFP PLL Power

MCP 3.3V/1.8V IFP Interface Power

Current numbers from MCP89 A01 Bring-Up Support document (MCP80_TDP_EDP_Bringup_Targets_Apple.pdf, dated August 5, 2009). K6/K69 EDP currents used.

C2650

402

CERM

10V

20%

0.1UF

NO STUFF

R2655

1/16W

1%

402

MF-LF

1K

NO STUFF

C2655

NO STUFF

0.1UF

CERM

402

20% 10V

C2640

4V X5R 402

20%

4.7UF

R2670

0

MF-LF

402

5%

1/16W

C2620

20%

4.7uF

6.3V CERM

603

C2621

10V 402

0.1uF

20% CERM

C2631

CERM

20%

0.1uF

402

10V

C2630

20%

4.7uF

4V X5R 402

C2600

603-1

10UF

20% X5R

6.3V

C2601

20% 4V X5R 402

4.7UF

C2602

10% 10V X5R 402-1

1UF

C2603

10% 10V X5R 402-1

1UF

C2604

0.22UF

20%

6.3V X5R 402

C2605

20%

6.3V X5R 402

0.22UF

C2606

402

CERM

20% 10V

0.1UF

C2607

20% 10V CERM 402

0.1UF

C2608

20% 10V CERM 402

0.1UF

C2609

20% 10V CERM 402

0.1UF

C2610

20% 10V CERM 402

0.1UF

C2611

20% 10V CERM 402

0.1UF

C2612

20% 10V CERM 402

0.1UF

C2641

10V 402

0.1uF

20% CERM

R2650

1K

402

MF-LF

1/16W

1%

SYNC_MASTER=T27_MLB

MCP Graphics Support

SYNC_DATE=08/06/2009

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=0V

GND_MCP_DAC_P3V3

MAKE_BASE=TRUE

=PP1V05_S0_MCP_DP0_VDD

=PP3V3R1V8_S0_MCP_IFP_VDD

MCP_IFPAB_RSET

MCP_TMDS0_VPROBE

MCP_TMDS0_RSET

=PP1V05_S0_MCP_PLL_IFP

MCP_IFPAB_VPROBE

PP3V3_S0_MCP_DAC

=PPVCORE_SW_MCP_GFX

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1

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2

1

2

1

2

1

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1

2

1

2

1

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1

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1

2

7

16

7

16

16 74

7

16

16 74

16

19 21

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

NC NC

OUT

IN

OUT

IN

OUT

IN

D

GS

IN

NC

OUT

B

Y

A

II NOT TO REPRODUCE OR COPY IT III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER

SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MCP S0 PWRGD & CPU_VLD

Ethernet WAKE# Isolation

LPC Reset (Unbuffered)

Platform Reset Connections

10K pull-up to 3.3V S0 inside MCP

System Reset Circuit

PCIE Reset (Unbuffered)

RTC Crystal

MCP 25MHz Crystal

Caesar II (ENET) 25MHz Crystal

9

12 18

C2810

12pF

5%

CERM

402

50V

C2811

5%

50V

CERM

402

12pF

R2810

MF-LF

5%

0

1/16W

402

R2811

NO STUFF

1/16W MF-LF

5%

402

10M

18 75

R2896

XDP

1/16W MF-LF

5%

0

402

R2883

33

MF-LF

5%

1/16W

402

PLACEMENT_NOTE=Place close to U1400

R2881

1/16W

5%

33

MF-LF

402

PLACEMENT_NOTE=Place close to U1400

R2897

OMIT

SILK_PART=SYS RST

402

MF-LF

1/16W

5%

0

PLACEMENT_NOTE=Place R2897 on BOTTOM

41

39

18

15 18

R2826

PLACEMENT_NOTE=Place close to U1400

33

5%

MF-LF

1/16W

402

R2825

402

1/16W MF-LF

33

5%

PLACEMENT_NOTE=Place close to U1400

18 75

C2815

50V

5%

CERM

402

12pF

C2816

12pF

402

CERM

5%

50V

Y2815

SM-3.2X2.5MM

CRITICAL

25.0000M

R2815

402

5%

MF-LF

1/16W

0

R2816

1/16W

NO STUFF

MF-LF

402

5%

1M

18

39 75

R2829

PLACEMENT_NOTE=Place close to U1400

402

MF-LF

5%

1/16W

22

18 75

R2899

1/16W

402

MF-LF

5%

33

C2899

NO STUFF

402

10V X5R

1UF

10%

34

39

41 75

39 75

Y2810

32.768K

7X1.5X1.4-SM

CRITICAL

R2891

0

5%

MF-LF

1/16W

402

28

R2893

0

5% 1/16W MF-LF

402

71

29

R2894

0

402

5%

MF-LF

1/16W

61

39 65

C2850

402

CERM

10V

20%

0.1UF

18

30

R2895

0

5% 1/16W MF-LF

402

6

15 29

31

Q2830

SOD-VESM-HF

SSM3K15FV

31

R2821

10M

MF-LF

5%

1/16W

NO STUFF

402

R2830

MF-LF

1/16W

402

5%

10K

R2820

200

MF-LF

5%

1/16W

402

Y2820

SM-3.2X2.5MM

25.0000M

CRITICAL

C2821

27pF

402

CERM

50V

5%

C2820

27pF

402

5%

50V

CERM

31 76

R2892

1/16W MF-LF

5%

402

0

74LVC1G08GW

SOT353

U2850

SB Misc

SYNC_DATE=07/28/2009

SYNC_MASTER=T27_MLB

PCIE_RESET_L

MAKE_BASE=TRUE

ENET_WAKE_L

MAKE_BASE=TRUE

BCM5764_CLK25M_XTALO

MCP_CLK25M_XTALOUT

BCM5764_CLK25M_XTALO_R

MCP_CLK25M_XTALOUT_R

RTC_CLK32K_XTALOUT

RTC_CLK32K_XTALOUT_R

BCM5764_CLK25M_XTALI

MCP_CLK25M_XTALIN

ENET_RESET_L

SDCARD_PLT_RST_L

AP_RESET_L

PM_SYSRST_L

PM_SYSRST_DEBOUNCE_L

LPCPLUS_RESET_L

LPC_RESET_L

PCA9557D_RESET_L

PM_CLK32K_SUSCLK

PM_CLK32K_SUSCLK_R

XDP_DBRESET_L

SMC_LRESET_L

BKLT_PLT_RST_L

=FW_RESET_L

=PP3V3_ENET_PHY

PCIE_WAKE_L

=ENET_WAKE_L

LPC_CLK33M_SMC_R

LPC_CLK33M_SMC

LPC_CLK33M_LPCPLUS

RTC_CLK32K_XTALIN

=PP3V3_S5_MCPPWRGD

VR_PWRGOOD_DELAY

MCP_PS_PWRGD

ALL_SYS_PWRGD

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1

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1

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1

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1 2

31

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1 2

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3

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5

7

31 64

7