Name: Apple A1278
Brand: Apple
SKU: 8201450
Rating: 5 (1 reviews)

TABLE_TABLEOFCONTENTS_ITEM

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

8

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

II NOT TO REPRODUCE OR COPY IT

3

B

7

ECNREV

BRANCH

DRAWING NUMBER

REVISION

SIZE

D

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

DRAWING TITLE

THE POSESSOR AGREES TO THE FOLLOWING:

Apple Inc.

SHEET

R

DATE

D

A

C

THE INFORMATION CONTAINED HEREIN IS THE

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

C

3456

D

B

8 7 6 5 4 2 1

12

APPD

CK

DESCRIPTION OF REVISION

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEADTABLE_TABLEOFCONTENTS_HEAD TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

6/12/2009

Schematic / PCB #’s

K24 MLB SCHEMATIC

1 OF 81

0000734528

C

051-7898

C.0.0

1 OF 109

PRODUCTION RELEASED

2009-06-04

FireWire Port Power

12/22/2008

35

YUN_K19_MLB

42

FireWire LLC/PHY (FW643)

11/02/2008

34

K19_MLB

41

ETHERNET CONNECTOR

04/04/2008

33

SUMA

39

Ethernet & AirPort Support

07/01/2008

32

SUMA

38

Ethernet PHY (RTL8211CL)

05/23/2008

31

SUMA

37

SECUREDIGITAL CARD READER

01/30/2009

VEMURI

35

Right Clutch Connector

04/22/2008

YITE

34

DDR3 Support

04/04/2008

T18_MLB

33

DDR3 SO-DIMM Connector B

05/09/2008

BEN

32

DDR3 SO-DIMM Connector A

06/30/2008

26

BEN

31

FSB/DDR3 Vref Margining

03/31/2008

25

BEN

29

SB Misc

04/05/2008

24

RAYMOND

MCP Graphics Support

12/12/2007

23

T18_MLB

26

MCP Standard Decoupling

04/04/2008

22

T18_MLB

25

MCP Power & Ground

04/04/2008

21

T18_MLB

22

MCP HDA & MISC

06/26/2008

20

T18_MLB

21

MCP SATA & USB

04/04/2008

19

T18_MLB

04/04/2008

18

T18_MLB

19

MCP Ethernet & Graphics

04/04/2008

17

T18_MLB

18

MCP PCIe Interfaces

04/04/2008

16

T18_MLB

17

MCP Memory Misc

04/04/2008

15

T18_MLB

16

MCP Memory Interface

04/04/2008

14

T18_MLB

15

MCP CPU Interface

04/04/2008

13

T18_MLB

14

eXtended Debug Port(MiniXDP)

11/07/2008

12

K19_MLB

13

CPU Decoupling

03/31/2008

11

RAYMOND

12

CPU Power & Ground

12/12/2007

10

T18_MLB

11

CPU FSB

12/12/2007

9

T18_MLB

10

SIGNAL ALIAS

8

M97_MLB

9

Power Aliases

04/21/2008

7

BEN

8

FUNC TEST

6

M97_MLB

7

Revision History

5

M97_MLB

5

BOM Configuration

4

M97_MLB

4

Power Block Diagram

03/13/2008

3

DRAGON

3

System Block Diagram

12/12/2007

2

T18_MLB

2

94

70

06/30/2008

AMASON

93

69

04/18/2008

AMASON

90

68

LVDS CONNECTOR

04/04/2008

NMARTIN

79

67

POWER FETS

12/11/2008

YUAN.MA

78

66

POWER SEQUENCING

12/11/2008

YUAN.MA

77

65

MISC POWER SUPPLIES

01/23/2008

RAYMOND

76

64

CPU VTT(1.05V) SUPPLY

02/08/2008

RAYMOND

75

63

MCP CORE REGULATOR

12/10/2008

K19_MLB

74

62

01/31/2008

RAYMOND

73

61

01/31/2008

RAYMOND

72

60

5V/3.3V SUPPLY

02/08/2008

RAYMOND

70

59

PBUS Supply/Battery Charger

01/31/2008

RAYMOND

69

58

DC-In & Battery Connectors

12/11/2008

YUNWU

68

57

AUDIO: JACK TRANSLATORS

03/20/2009

AUDIO

67

56

AUDIO: JACK

03/20/2009

AUDIO

66

55

AUDI0: SPEAKER AMP

12/18/2008

AUDIO

65

54

AUDIO: HEADPHONE FILTER

02/03/2009

AUDIO

63

53

AUDIO: LINE INPUT FILTER

01/31/2009

AUDIO

62

52

AUDIO: CODEC/REGULATOR

03/04/2009

AUDIO

61

51 SPI ROM

05/02/2008

CHANGZHANG

59

50 SMS

06/26/2008

YUNWU

58

49

WELLSPRING 2

05/09/2008

YUAN.MA

57

48

WELLSPRING 1

04/22/2008

YUAN.MA

56

47 Fan

01/18/2008

CHANGZHANG

55

46

Thermal Sensors

03/20/2008

YUNWU

54

45

Current Sensing

12/17/2008

YUNWU

53

44

VOLTAGE SENSING

02/04/2008

YUNWU

52

43

K24 SMBUS CONNECTIONS

04/21/2008

BEN

51

42

LPC+SPI Debug Connector

05/09/2008

CHANGZHANG

50

41

SMC Support

05/28/2008

YUAN.MA

49

40 SMC

06/26/2008

T18_MLB

48

39

Front Flex Support

05/28/2008

YUAN.MA

46

38

External USB Connectors

01/18/2008

YUAN.MA

45

37

SATA Connectors

12/04/2008

K19_MLB

81

K24 RULE DEFINITIONS

109

M97_MLB

80

K24 SPECIAL CONSTRAINTS

107

M97_MLB

01/04/2008

79

SMC Constraints

106

T18_MLB

12/01/2008

78

FireWire Constraints

105

K19_MLB

03/19/2008

77

Ethernet Constraints

104

T18_MLB

12/14/2007

76

MCP Constraints 2

103

T18_MLB

01/04/2008

75

MCP Constraints 1

102

T18_MLB

01/04/2008

74

Memory Constraints

101

T18_MLB

01/04/2008

73

CPU/FSB Constraints

100

T18_MLB

06/30/2008

72

LCD Backlight Support

98

YITE

SCHEM,MLB,K24

PCBF,MLB,K24 CRITICAL820-2530

PCB1

051-7898 CRITICAL

1

SCHEM,MLB,K24

SCH

12/05/2008

71

LCD BACKLIGHT DRIVER

97

KIRAN

Contents

Page

Date

(.csa)

Sync

Table of Contents

08/22/2007

1

T17_MLB

1

Page

(.csa)

Sync

Date

Contents Contents

Sync

(.csa)

Date

Page

43

36

FireWire Ports

11/02/2008

K19_MLB

MCP PCI & LPC

28

27

28

29

30

20

DisplayPort Connector

DISPLAYPORT SUPPORT

IMVP6 CPU VCore Regulator

1.5V/0.75V DDR3 SUPPLY

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

J9000

CONN

Conn

J4520

PG 17

Line Out

2

CTRL

CLK

J6800,6801,6802,6803

PG 41

PG 19

LPC

SATA

U6301 U6500U6400

PG 56PG 55

HEADPHONE

Audio

Codec

FSB

64-Bit

2 UDIMMs

XDP CONN

POWER SUPPLY

U3900

PG 33

Conn

PG 31

GB

E-NET

Amp

Speaker

Amps

PG 54

PG 53

PG 57

U4900

J6950

PG 12

U1000

U1300

J4510

U6600,6605,6610,6620

HD

E-NET

ODD

U6100

USB

PG 45

POWER SENSE

J5650,5600,5610,5611,5660,5720,5730,5750

PG 48,49

J4900

DC/BATT

PENRYN

2.X OR 3.X GHZ

INTEL CPU

SPI

PG 20

PG 18

MEMORY

MAIN

DDR2-800MHZ

DDR3-1067/1333MHZ

J2900

DIMM

PG 25,26

SPI

TEMP SENSOR

FAN CONN AND CONTROL

J5100

PG 43

Ser

B,0

Prt

BSB

PWR

Misc

Port80,serial

LPC Conn

GPIOs

1.05V/3GHZ.

RGB OUT

PG 38

PG 13

FSB INTERFACE

PG 24

PG 20

HDA

NVIDIA

PG 41

1 6

PG 52

Boot ROM

U1400

DVI OUT

PG 17

LVDS OUT

HDMI OUT

RGMII

U3700

Line In

Amp Amp

PG 60

PG 9

PG 71

DP OUT

LVDS

PG 34

J4310

J9400

PG 34

FIREWIRE PORT

FW643

CONN

RTL8211CL

PG 56

EXTERNAL

J3900,4635,4655

USB

Connectors

PG 39

J4710

PG 40

J4710

TRACKPAD/

PG 40

J4720

PG 40

MCP79

J3500

PCI-E

PG 34

UP TO 20 LANES3

PG 16

CONN

DISPLAY PORT

Conn

SATA

PG 44

Conns

3

PCI

(UP TO FOUR PORTS)

PG 18

SMB

J4700

IR

SD CARD READER

PG 30

TMDS OUT

PG 71

PG 40

KEYBOARD

U6200

CONN

CAMERA

Bluetooth

DIMM’s

0

SMB

PG 20

J3400

Mini PCI-E

AirPort

PG 28

SYNTH

800/1067/1333 MHz

PG 14

4 5

(UP TO 12 DEVICES)

7

11

SMC

ADC

Fan

PG 38

SATA

051-7898

C.0.0

2 OF 109

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_MASTER=T18_MLB

SYNC_DATE=12/12/2007

System Block Diagram

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CPUVTT

(1.05V)

TPS51117

U7600

PPVCORE_S0_CPU

PP1V05_ENET_FET

PP5V_S0_FET

PP5V_S3_REG

ISL8009

PP5V_S3_REG

VR_ON

SMC_CPU_ISENSE

(44A MAX CURRENT)

(8A MAX CURRENT)

1.05V (S5)

P5VS0_EN

Q7940

P3V3S3_EN

Q7910

P1V05ENET_EN

P1V05_S5_EN

P5VRTS0_EN_L

3.3V

Q7930

06

VOUT

08

04

P5V3V3_PGOOD

VR_PWRGOOD_DELAY

PP1V05_S5_REG

PGOOD

U7400

Q3802

BATT_POS_F

01

PP18V5_DCIN_CONN

U4900

LP8543

VIN

Q7050

V

(S0)

PGOOD

EN_PSV

PPBUS_G3H_CPU_ISNS_R

PPBUS_G3H_CPU_ISNS

PP5V_S0_CPUVTTS0

F6905

J6950

SMC_PM_G2_EN

Q7800

05

U1400

SLP_S3#

PM_SLP_S4_L

VIN

VOUT1

VOUT2

ISL6236

5V (LT)

U7000

ISL6258A

VIN

PM_ENET_EN_L

Q3810

RC

DELAY

VOUT

ENA

VOUT1

(RT)

FETS

RC

DELAY

P5VLTS3_EN

DDRREG_EN

P3V3S0_EN

VOUT2

D6905

PP3V3_S5_REG

MCP79

V2

A

(S5)

AC

IN

99ms DLY

PM_PWRBTN_L

SMC_RESET_L

IMVP_VR_ON

PWRGD(P12)

SLP_S5_L(P95)

7A FUSE

CPU_PWRGD

VIN

EN2

EN1

VOUT1

MCPCORES0_EN

P3V3_ENET_FET

P1V8S0_EN

MCPCORES0_EN

PBUSVSENS_EN

P3V3S0_EN

(S0)

RC

DELAY

WOL_EN

V3

SMC

CHGR_BGATE

P5VRTS0_EN_L

P1V05S0_EN

CPUVTTS0_PGOOD

P5V_LT_S3_PGOOD

(25A MAX CURRENT)

FETS

S3 TO S0

PWRBTN*

ENABLES

01

D6905

02

26

06

3S2P

11

11-1

RC

DELAY

11-3

15

16-2

16-4

16-2

16-1

04-1

16

02

21

20

16-2

18

24

09

10

16-2

03

16-3

17

06-1

PBUS SUPPLY/

BATTERY CHARGER

VIN

02

25

VOUT

PP3V3_S0_FET

SMC

25

ALL_SYS_PWRGD

PM_RSMRST_L

SLP_S4_L(P94)

PP1V8_S0_REG

P3V3ENET_EN_L

28

IMVP_VR_ON

RSMRST_PWRGD

P5V3V3_PGOOD

MCPCORESO_PGOOD

U4900

SLP_S3_L(P93)

S0PGOOD_PWROK

19-1

PP3V3_S0

PP1V05_S0

PLT_RST*

RSMRST_IN(P13)

RSMRST_OUT(P15)

ADAPTER

TPS51116

PPVBAT_G3H_CHGR_OUT

U7760

CHGR_EN

02

DELAY

F7000

14

=DDTVTT_EN

S5

MCP79

PM_SLP_S3_L

16-3

MCPDDR_EN

CPUVTTS0_EN

1.8V LDO

PP1V5_S0

V1

RST*

MCP_CORE

S3

U7300

PM_SLP_S3_L

DCIN(16.5V)

6A FUSE

U7870

LTC2909

SLP_S5_L

SMC_ONOFF_L

PWR_BUTTON(P90)

RST*

P17(BTN_OUT)

PP1V5_S3_REG

(Q7901 & Q7971)

PP0V75_S0_REG

PPVCORE_S0_MCP_REG_R

SMC_ADAPTER_EN

PCI_RESET0#

P3V3S3_EN

15-1

Q3801

11-2

U9701

0.75V

5V

PP1V5_S0_FET

U7500

EN2

PPVCORE_S0_MCP

(1A MAX CURRENT)

(12A MAX CURRENT)

(9 TO 12.6V)

SMC_PM_G2_EN

P3V3S5_EN_L

30

PLTRST*

EN

VIN

U7750

U5000

RN5VD30A-F

PPVIN_G3H_P3V42G3H

32

RESET*

CPU

U1000

U1400

29

07

13

CPU_RESET#

VOUT

PS_PWRGD

ISL9504B

VOUT

LPC_RESET_L

31

FSB_CPURST_L

02

PPVBAT_G3H_CHGR_REG

CPUPWRGD(GPIO49)

ENABLE

LT3470

U6990

PP3V3_S3_FET

04

SMC PWRGD

PP3V42_G3H_REG

CPU VCORE

VIN

VOUT

V

PPBUS_G3H

PP3V3_S5

MCP_PS_PWRGD

Q5315

3.425V G3HOT

SMC_CPU_VSENSE

R5492

23

U2850

VOUT

PP1V05_S0

VIN

02

K24 POWER SYSTEM ARCHITECTURE

VREG3

VOUT2

PGOOD1,2

1.05V SO

PP1V5_S0

BKLT_EN

P60

P16

(S5)

PPVOUT_S0_LCDBKLT

05

SLP_S4_L

SLP_S3_L

IMVP_VR_ON(P16)

PBUS_VSENSE

CPUVTTS0_EN

PWRGOOD

22

RSMRST*

CPUVTTS0_PGOOD

(Q3841)

PPBUS_G3H

U6200

4.5V AUDIO

TPS7174S

PP4V5_AUDIO_ANALOG

PP5V_S3

(4A MAX CURRENT)

U5403

SMC_BATT_ISENSE

EN1

CURRENT)

(4A MAX

TPS51125

U7200

TPS62202

1.5V

R7572

=DDRREG_EN

3 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_MASTER=DRAGON

SYNC_DATE=03/13/2008

Power Block Diagram

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

PART NUMBER

ALTERNATE FORPART NUMBER BOM OPTION REF DES COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

TABLE_BOMGROUP_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

Module Parts

BOM Groups

LOCKED BOOTROM APN IS 341S2443

Programmable Parts

Alternate Parts

BOM Variants

K24 BOARD STACK-UP

SIGNAL(High Speed)

SIGNAL

GROUND

BOTTOM

POWER

GROUND

Top

2

3

4

5

6

7

GROUND

SIGNAL

8

9

10

11

DEVELOPMENT BOM

SIGNAL(High Speed)

POWER

Bar Code Labels / EEE #’s

4 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

152S0778

152S0796

157S0058

152S1024

INTERSIL AS ALTERNATE

353S2310353S2718

337S3769

ALL

337S3704

INTEL P7550 CPU AS ALTERNATE

152S1025

152S0847

152S0516

MCP_B03,BOOT_MODE_USER,MCPSEQ_SMC

BMON_PROD,SMC_DEBUG_YES,XDP,LPCPLUS_NOT,NO_VREFMRGN

BMON_ENG,XDP_CONN,LPCPLUS,VREFMRGN,FWPHY_WAKE_YES

DEVEL_BOM,BMON_PROD,SMC_DEBUG_YES,XDP,NO_VREFMRGN

K24_DEBUG_PROD

K24_DEVEL_PVT

1

PDC,SLB4N,PRQ,2.4,25W,1066,M0,3M,BGA

PDC,SLGFG,PRQ,2.53,25W,1066,R0,3M,BGA

CPU_2_66GHZ

COMMON,ALTERNATE,K24_MCP,K24_MISC,K24_DEBUG_PROD,K24_PROGPARTS

SMC_PROG

CRITICAL

IC,PRGRM,WELLSPRING CONTROLLER

1

335S0610

338S0563

PDC,SLG8E,PRQ,2.0,25W,1066,M0,3M,BGA

U1000

CRITICAL

337S2983

IC,FLASH,SPI,32MBIT,3.3V,86MHZ,8-SOP

CRITICAL

U1000

CRITICAL

CPU_2_26GHZ

337S3639

1

U1400

341S2093

337S3646

337S3704

337S3756

338S0710

337S3761

IC,GMCP,MCP79,35X35MM,BGA1437,B03

IC,SMC,HS8/2117,9X9MM,TLP,HF

TOKO AS ALTERNATE

ALL

341S2503

338S0375

PDC,SLGE2,PRQ,2.26,25W,1066,R0,3M,BGA

CRITICAL

PDC,SLGLA,PRQ,2.66,25W,1066,E0,3M,BGA

IC,PRGRM,EFI BOOTROM,UNLOCK,K24

IC,CY7C63833,ENCORE II,USB CONTROLLER

IC,PSOC+ W/ USB,56 PIN,MLF,CY8C24794

MAGLAYERS AS ALTERNATE

ALL

IC,IR CONTROLLER,M97

CPU_2_0GHZ

U1000

1

CRITICAL

1

MCP_B03

PCBA,MLB,BEST,K24

PCBA,MLB,BETTER,K24

IC,SMC,K24

K24_COMMON

SYNC_MASTER=M97_MLB

BOM Configuration

ALL

152S0693

CYNTEC AS ALTERNATE

152S0685

CYNTEC AS ALTERNATE

DALE/VISHAY AS ALTERNATE

ALL

104S0023104S0018

ALL

DELTA AS ALTERNATE

157S0055

152S0874

ALL

CRITICAL

U5701 WELLSPRING_PROG

1

CRITICAL

U5701

WELLSPRING_BLANK

1

IR_PROG

U4800

U4900

1

SMC_BLANK

K24_MCP

K24_MISC

ONEWIRE_PU,DP_ESD,MIKEY,BKLT_PROD,SUPERCAP_NO,LDO_NO

K24_PROGPARTS

BOOTROM_PROG,SMC_PROG,IR_PROG,WELLSPRING_PROG

K24_DEBUG_ENG

DEVEL_BOM,SMC_DEBUG_YES,XDP

K24_DEBUG_PVT

K24_DEVEL_ENG

1

CRITICAL

U4900

341S2445

1

CRITICAL IR_BLANK

U4800

KEMET AS ALTERNATE

ALL

128S0218128S0093

MAGLAYERS AS ALTERNATE

ALL

152S0586

1

BOOTROM_PROG

CRITICAL

U6100

341S2441

CPU_2_4GHZ

1

CRITICAL

1

U1000

1

CRITICAL

U6100

BOOTROM_BLANK

826-4393 CRITICAL

1

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:6GD]

EEE_6GD

K24 MLB DEVELOPMENT BOM

085-0741

DEVEL_BOM

DEVEL

CRITICAL

1

826-4393 CRITICAL

1

[EEE:6G4]

EEE_6G4

LBL,P/N LABEL,PCB,28MM X 6 MM

826-4393

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

[EEE:6GC]

EEE_6GC

CPU_2_53GHZ

LPCPLUS

K24_COMMON,CPU_2_53GHZ,EEE_6GD,KB_BL

630-9924

K24_COMMON,CPU_2_26GHZ,EEE_6GC,KB_BL

630-9923

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Revision History

NOTE: All page numbers are .csa, not PDF. See page 1 for .csa -> PDF mapping.

5 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SYNC_MASTER=M97_MLB

Revision History

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(NEED 3 TP)

(NEED 2 TP)

MIC FUNC_TEST

THERMAL FUNC_TEST

(NEED TO ADD 4 GND TP)

Functional Test Points

DC POWER CONN

KEYBOARD CONN

LVDS FUNC_TEST

SPEAKER FUNC_TEST

(NEED TO ADD 3 GND TP)

RIGHT CLUTCH CONN

Fan Connectors

(NEED TO ADD 6 GND TP)

IPD_FLEX_CONN

(NEED TO ADD 5 GND TP)

BATT SIGNAL CONN

(NEED TO ADD 5 GND TP)

(NEED TO ADD 1 GND TP)

(NEED 2 TP)

(NEED 3 TP)

DEBUG VOLTAGE

(NEED TO ADD 4 GND TP)

(NEED TO ADD 2 GND TP)

(NEED 3 TP)

(NEED 4 TP)

BATT POWER CONN

(NEED 3 TP)

(NEED TO ADD 3 GND TP)

SATA ODD CONN

(NEED TO ADD 4 GND TP)

SATA HDD/IR/SIL

KBD BACKLIGHT CONN

7 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TRUE

LED_RETURN_6

WS_KBD4

PPVOUT_S0_LCDBKLT

TRUE

CONN_USB2_BT_N

TRUE

MINI_CLKREQ_Q_L

TRUE

MINI_RESET_CONN_L

PCIE_MINI_R2D_N

TRUE

PCIE_WAKE_L

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

SMBUS_SMC_A_S3_SDA

TRUE

Z2_MOSI

TRUE

WS_KBD5

TRUE

Z2_SCLK

PSOC_MISO

TRUE

Z2_KEY_ACT_L

TRUE

Z2_RESET

TRUE

Z2_CLKIN

Z2_BOOST_EN

TRUE

Z2_MISO

CONN_USB2_BT_P

TRUE

USB_CAMERA_CONN_N

TRUE

PCIE_CLK100M_MINI_CONN_P

TRUE

PCIE_MINI_D2R_P

TRUE

PP5V_S3_BTCAMERA_F

TRUE

PCIE_CLK100M_MINI_CONN_N

PCIE_MINI_R2D_P

TRUE

PCIE_MINI_D2R_N

TRUE

SPKRAMP_SUB_P_OUT

TRUE

SPKRAMP_SUB_N_OUT

TRUE

SPKRAMP_R_P_OUT

TRUE

ADAPTER_SENSE

LVDS_IG_DDC_CLK

TRUE

LVDS_IG_DDC_DATA

TRUE

LVDS_IG_A_DATA_P<0>

TRUE

LVDS_IG_A_DATA_N<0>

TRUE

LVDS_IG_A_DATA_P<2>

TRUE

LVDS_IG_A_DATA_N<1>

TRUE

BI_MIC_HI

TRUE

BI_MIC_SHIELD

PP3V3_S0_LCD_F

TRUE

PP5V_S0

TRUE

LVDS_IG_A_DATA_P<1>

PP3V3_LCDVDD_SW_F

TRUE

PP5V_WLAN

TRUE

LED_RETURN_3

TRUE

WS_KBD10

TRUE

PP18V5_DCIN_FUSE

TRUE

FAN_RT_PWM

TRUE

PSOC_MOSI

TRUE

Z2_CS_L

BI_MIC_LO

TRUE

FAN_RT_TACH

SPKRAMP_R_N_OUT

TRUE

SPKRAMP_L_P_OUT

TRUE

SPKRAMP_L_N_OUT

TRUE

WS_KBD8

WS_KBD14

TRUE

WS_KBD6

TRUE

WS_KBD7

TRUE

LVDS_IG_A_DATA_N<2>

WS_KBD9

TRUE

Z2_HOST_INTN

TRUE

Z2_DEBUG3

PP18V5_S3

TRUE

USB_CAMERA_CONN_P

TRUE

PP3V3_S3_LDO

TRUE

PICKB_L

TRUE

PSOC_F_CS_L

TRUE

SMBUS_SMC_A_S3_SCL

TRUE

PSOC_SCLK

TRUE

SMBUS_SMC_A_S3_SDA

SYS_DETECT_L

TRUE

PP3V42_G3H

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMBUS_SMC_BSA_SCL

TRUE

SMC_BIL_BUTTON_L

SMC_LID_R

TRUE

LVDS_IG_A_CLK_F_P

TRUE

LVDS_IG_A_CLK_F_N

TRUE

LED_RETURN_2

TRUE

LED_RETURN_1

TRUE

MCPTHMSNS_D2_P

TRUE

MCPTHMSNS_D2_N

PPVCORE_S0_CPU

TRUE

PPVCORE_S0_MCP

TRUE

PP1V05_S0

TRUE

PP0V75_S0

TRUE

PP1V5_S0

TRUE

PP5V_S0

PP1V8_S0

TRUE

PP1V5_S3

TRUE

PP3V3_S0

TRUE

PP3V3_S3

TRUE

PP5V_S3

PP1V1R1V05_S5

TRUE

PP3V3_S5

TRUE

PP1V2R1V05_ENET

TRUE

PP3V42_G3H

TRUE

PPBUS_G3H

TRUE

PP3V3_ENET_PHY

PP3V3_G3_RTC

TRUE

PP5V_WLAN

TRUE

PP5V_SW_ODD

TRUE

PP5V_S0_HDD_FLT

TRUE

PP3V3_S5_AVREF_SMC

TRUE

PP18V5_S3

TRUE

PP4V5_AUDIO_ANALOG

TRUE

PP3V3_S3_LDO

TRUE

PP3V3_LCDVDD_SW_F

PPVOUT_S0_LCDBKLT

TRUE

SMC_PM_G2_EN

PM_SLP_S4_L

TRUE

PM_SLP_S3_L

TRUE

BATT_POS_F

TRUE

SATA_ODD_D2R_C_N

TRUE

WS_KBD3

TRUE

WS_KBD2

TRUE

WS_KBD1

TRUE

PP3V42_G3H

TRUE

PP3V3_S3

TRUE

LED_RETURN_4

LED_RETURN_5

SATA_ODD_R2D_N

TRUE

TP_BKL_SYNC

TRUE

WS_KBD12

WS_KBD11

TRUE

WS_KBD13

SATA_HDD_R2D_N

TRUE

WS_KBD16_NUM

TRUE

WS_KBD15_CAP

TRUE

WS_KBD17

TRUE

PP5V_S0_HDD_FLT

SATA_HDD_D2R_C_P

TRUE

SATA_HDD_D2R_C_N

TRUE

SMBUS_SMC_BSA_SCL

SMBUS_SMC_BSA_SDA

TRUE

SATA_ODD_R2D_P

TRUE

SATA_ODD_D2R_C_P

TRUE

SMC_ODD_DETECT

TRUE

SYS_LED_ANODE_R

TRUE

PP5V_S3_IR_R

TRUE

IR_RX_OUT

TRUE

PP5V_SW_ODD

TRUE

WS_KBD20

TRUE

WS_KBD18

TRUE

WS_KBD23

TRUE

SMC_KDBLED_PRESENT_L

KBDLED_ANODE

TRUE

WS_LEFT_OPTION_KBD

TRUE

WS_LEFT_SHIFT_KBD

TRUE

WS_KBD_ONOFF_L

TRUE

WS_KBD21

TRUE

WS_CONTROL_KBD

TRUE

WS_KBD19

TRUE

WS_KBD22

SATA_HDD_R2D_P

TRUE

SYNC_MASTER=M97_MLB

FUNC TEST

I395

I394

I393

I392

I391

I390

I389

I388

I387

I386

I385

I383

I382

I381

I380

I379

I378

I377

I376

I375

I374

I372

I371

I370

I369

I368

I366

I365

I364

I363

I362

I361

I360

I359

I358

I357

I356

I355

I354

I353

I352

I351

I350

I349

I348

I347

I346

I345

I344

I343

I342

I341

I340

I339

I338

I337

I336

I335

I334

I333

I332

I331

I330

I329

I328

I327

I326

I325

I324

I323

I322

I321

I320

I319

I318

I317

I315

I314

I313

I312

I311

I309

I308

I307

I305

I304

I303

I302

I301

I300

I299

I298

I297

I296

I295

I294

I293

I292

I291

I290

I289

I288

I287

I285

I284

I283

I282

I281

I280

I279

I278

I276

I275

I274

I273

I272

I271

I270

I269

I268

I267

I266

I265

I264

I262

I261

I260

I259

I258

I257

I256

I255

I254

I253

I252

I251

I250

I249

I248

I247

I246

I245

I239

I238

I237

I233

I232

I231

I230

I229

I228

I227

I226

I16

I15

I12

68C2

6C3 68B2 71C1

29B7 76B3

29C7

29A7

29C7 75D3

16B6 29C7

6C5 43D2 79D3

48C8 49C3

48C6 48D2

48C8 49C3

48C8 49C1

48C6 49C3

49C3 49C5

48C8 49C3

29B7 76C3

29C7 75D3

16B6 29C7 75D3

29C7

29C7 75D3

16B6 29C7 75D3

55C2 56B2

55B2 56B2

55C2 56B2

58D7

17B3 68C5

17A3 68C5

17B3 68C2 75B3

56C2 57B1

68C3

6D3 7D5

17B3 68C2 75B3

6C3 68C2

6C3

29C5

68B3 71B1

48C6 48D2

58D6

47B4

48C8 49C1

48C8 49C3

56C2 57B1

47C4

55C2 56A2

55B2 56B2

55A2 56B2

48C6 48D2

48C2 48C6

48C6 48D2

48D2 48C6

17B3 68C2 75B3

48C6 48D2

48D8 49C3

48C8 49C3

6C3 49C1 49D3

29B7 76C3

6C3 49B4 49C3

48D8 49C1

48C8 49C1

6D5 43D2 79D3

48C8 49C1

6D5 43D2 79D3

58A8

6B5 6D3 7D1

6A7 43C5 79D3

40C5 58C4

58C2

68C2 75B3

68B3 71B1

46B5 80D3

7D7

7C7

7D7

7C7

7C6

6D7 7D5

7B6

7D3

7D5

6B5 7D3

7C3

7B3

7B5

6A7 6B5 7D1

7C1

7B5

20C8 21A5 24D4

6D5 29C5

6B7 37D3

6B7 37B6

40D4 41C6

6C5 49C1 49D3

52A5 52D2 52D7

6C5 49B4 49C3

6C7 68C2

6C7 68B2 71C1

40D5 60C5 66D8

20C3 40C5 41A2 66C8

20C3 32B7 35A5 40C5 66D5 70D8

58B8 59A3 58A7

75A3 37C6

68B3 71A1

48C6 48D2

6A7 6D3 7D1

6D3 7D3

68B3 71B1

6A7 37C6 75A3

48C6 48D2

48D2 48C6

48C6 48D2

75A3 37A5

48C2

48C2 48D6

37B6 6C3

75A3 37B5

6A7 79D3 43C5

79D3 43C5

37C6 75A3

75A3 37C6

40B8 37C7

37A7

39D4 37A7

6C3 37D3

48C2 48D7

49A4 49A6

49A4

48B3 48B5 48C2

48C2

48C2 48D7

48B3 48B5 48C2

48C2 48D7

75A3 37A5

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PEX & SATA AVDD/DVDD aliases

(MCP VCORE AFTER SENSE RES)

"G3H" RAILS

43 mA (A01)

"FIREWIRE" RAILS

"S3" RAILS

"S0,S0M" RAILS

(CPU VCORE PWR)

127 mA (A01)

(AFTER HIGH SIDE CPU VCORE

127 mA (A01)

(BEFORE HIGH SIDE SENSING RES.)

& CPU VTT SENSING RES.)

127 mA (A01)

206 mA (A01)

57 mA (A01)

206 mA (A01)

"ENET" RAILS

"S5" RAILS

8 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP1V05_S0_MCP_PEX_DVDD0

PP3V42_G3H

VOLTAGE=3.42V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

=PP3V42_G3H_SMCUSBMUX

=PP3V42_G3H_PWRCTL

=PPVIN_S5_SMCVREF

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.6 mm

PP1V5_S3

=PP1V5_S3_MEM_A

=PP1V5_S3_HDD

=PP3V3_S3_FET

=PP3V3_S3_SMBUS_SMC_A_S3

=PP3V3_S3_PDCISENS

=PP3V3_S3_SMBUS_SMC_MGMT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=3.3V

PP3V3_S3

=PP3V3_S3_WLAN

=PP3V3_S3_VREFMRGN

=PP1V5_S3_MEM_B

=PP3V3_S3_TPAD

=PP3V3_S3_CARDREADER

=PP5V_S0_MCPREG

=PP5V_S0_HDD

=PP5V_S0_CPU_IMVP

=PP5V_S3_P5VS0FET

=PP5V_S3_ODD

=PP5V_S3_AUDIO_AMP

=PP5V_S3_AUDIO

=PP5V_S3_1V5S30V75S0

=PP5V_S3_TPAD

=PP5V_S3_WLAN

=PP5V_S3_VTTCLAMP

=PP5V_S3_MCPDDRFET

=PP5V_S3_SYSLED

=PP5V_S3_IR

=PP5V_S3_BTCAMERA

=PP5V_S3_EXTUSB

=PP5V_S3_REG

=PP3V3_S3_SMS

=PP3V3_S3_MCP_GPIO

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S3

VOLTAGE=5V

MAKE_BASE=TRUE

=PP1V5_S3_P1V5S0FET

=PP5V_S0_DP_AUX_MUX

=PP1V05_S0_CPU

=PP3V3_S5_P1V05FWFET

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_S5

=PPVTT_S3_DDR_BUF

=PP3V3_S0_FET

=PP1V05_S0_SMC_LS

=PP1V05_S0_MCP_PEX_DVDD

=PP1V05_S0_MCP_AVDD_UF

PP1V05_S0

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

=PP1V05_S0_VMON

=PP3V3_S0_MCP

=PP3V3_S0_SMBUS_MCP_0

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_DAC_UF

PP3V3_S0

VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

=PP5V_S0_FET

=PP1V05_S0_MCP_SATA_DVDD

=PP1V5_S3_REG

=PP3V3_S0_MCP_GPIO

=PP3V3_FW_LATEVG_ACTIVE

=PP3V3_S0_FWPWRCTL

=PP3V3_S0_P3V3FWFET

=PP3V3_S0_MCPDDRISNS

=PP3V3_S0_MCP_PLL_VLDO

=PP3V3_S0_BKL_VDDIO

=PP3V3_S0_P1V8S0

=PP3V3_S0_SMBUS_MCP_1

=PP3V3_S0_TPAD

=PP3V3_S0_CPUVTTISNS

=PP3V3_S0_VMON

=PPSPD_S0_MEM_B

=PP3V3_S0_PWRCTL

=PP3V3_S0_DPCONN

=PPSPD_S0_MEM_A

=PP3V3_S0_CPUTHMSNS

=PP3V3_S0_SMC

=PP3V3_S0_MCPTHMSNS

=PP3V3_S0_MCP_PLL_UF

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S0_IMVP

=PP3V3_S0_LCD

=PP3V3_S0_FAN_RT

=PP3V3_S0_AUDIO

=PP3V3_S0_SMBUS_SMC_0_S0

=PP3V3_S0_SMBUS_SMC_B_S0

=PP3V3_S0_ODD

=PP3V3_S0_XDP

PP5V_S0

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=5V

MAKE_BASE=TRUE

=PP1V0_FW_FWPHY

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

PP3V3_FW

VOLTAGE=3.3V

=PP3V3_S0_P1V05FWFET

=PP3V3_FW_FWPHY

=PP3V3_FW_FET

=PPBUS_S5_FW_FET

=PPVP_FW_PHY_CPS_FET

=PP3V3_S5_P3V3S0FET

=PP3V3_S5_P1V05S5

=PP3V3_S5_P3V3ENETFET

=PP3V3_S5_P3V3S3FET

=PP3V3_S5_PWRCTL

=PP3V3_S5_LCD

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

PP1V1R1V05_S5

MIN_LINE_WIDTH=0.6 MM

MAKE_BASE=TRUE

=PP3V3_S5_P1V05ENETFET

=PP3V3_S5_MCP

=PP3V3_S5_MEMRESET

=PP3V3_S5_MCPPWRGD

=PP1V05_ENET_P1V05ENETFET

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S5_REG

=PP1V05_ENET_PHY

=PP3V3_S5_DP_PORT_PWR

=PP3V3_FW_LATEVG

=PP1V5_S0_CPU

=PP1V8_S0_AUDIO

=PPVCORE_S0_CPU

=PPVCORE_S0_CPU_VSENSE

=PP1V05_S0_MCP_HDMI_VDD

=PPCPUVTT_S0_REG

=PP1V05_S0_MCP_SATA_DVDD0

=PPVCORE_S0_MCP_VSENSE

=PP0V75_S0_REG

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

PPVCORE_S0_CPU

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.3 MM

=PP5V_S0_VMON

=PP5V_S0_CPUVTTS0

=PP5V_S0_KBDLED

=PP5V_S0_LPCPLUS

=PP5V_S0_FAN_RT

=PP5V_S0_BKL

=PP1V05_S0_MCP_SATA_DVDD

=PP1V05_S0_MCP_PEX_DVDD

=PPVCORE_S0_MCP

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP1V8_S0_REG

VOLTAGE=1.8V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V8_S0

MIN_LINE_WIDTH=0.5 MM

=PP1V05_S0_MCP_PLL_UF

PP1V05_S0_MCP_PEX_AVDD

MAKE_BASE=TRUE

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PPVTT_S3_DDR_BUF

=PP1V05_S0_MCP_SATA_AVDD0

=PPVIN_S5_1V5S30V75S0

=PPBUS_S0_LCDBKLT

=PPCPUVCORE_VTT_ISNS_R

=PPBUS_G3HRS5

=PPBUS_S5_FWPWRSW

=PPVIN_S3_5VS3

=PPVIN_S5_3V3S5

MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

VOLTAGE=12.6V

PPBUS_G3H

=PPCPUVCORE_VTT_ISNS

=PPBUS_G3H

=PPVIN_S0_MCPCORE

=PPVIN_S0_CPUVTTS0

=PPVIN_S5_CPU_IMVP

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.3 MM

MAKE_BASE=TRUE

VOLTAGE=12.6V

PPBUS_G3H_CPU_ISNS

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD1

=PP1V05_S0_MCP_PEX_DVDD1

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_AVDD0

MAKE_BASE=TRUE

PP1V05_S0_MCP_SATA_AVDD

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.3 MM

VOLTAGE=18.5V

PP18V5_G3H

=PP18V5_DCIN_CONN

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_UF

MIN_LINE_WIDTH=0.6 MM

=PPVCORE_S0_CPU_REG

=PP1V5_S0_FET

=PP1V8R1V5_S0_MCP_MEM

=PP1V5_S0_VMON

=PP0V75_S0_MEM_VTT_B

=PP0V75_S0_MEM_VTT_A

=PPVTT_S0_VTTCLAMP

=PP3V3_ENET_FET

=PP1V05_ENET_FET

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

PP3V3_ENET_PHY

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

=PP1V05_ENET_MCP_RMGT

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

VOLTAGE=1.05V

PP1V2R1V05_ENET

=PP1V05_ENET_MCP_PLL_MAC

=PP3V3_S5_MCP_GPIO

=PP3V3_S5_ROM

=PP1V0_FW_FET

PP1V05_FW

VOLTAGE=1.05V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.6 MM

=PPVP_FW_PORT1

PPVP_FW

MIN_LINE_WIDTH=0.4 mm

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=12.6V

MAKE_BASE=TRUE

=PP3V3_S5_REG

=PP3V3_ENET_PHY

=PP3V3_ENET_MCP_RMGT

=PP1V5_S0_MCP_PLL_VLDO

=PP1V5_S0_MEM_MCP

MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5 mm

PP1V5_S0

MAKE_BASE=TRUE

PP0V75_S0

MIN_LINE_WIDTH=0.4 mm

VOLTAGE=0.75V

MIN_NECK_WIDTH=0.2 mm

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.6 MM

MIN_NECK_WIDTH=0.2 MM

PPVCORE_S0_MCP

MAKE_BASE=TRUE

=PPMCPCORE_S0_REG

=PP1V05_FW_P1V05FWFET

=PP1V05_FWPWRCTL

=PP1V05_S0_MCP_PLL_UF_R

=PP1V05_S0_MCP_FSB

=PP1V5_S3_MEMRESET

=PP3V42_G3H_REG

=PP3V42_G3H_CHGR

=PP3V42_G3H_SMBUS_SMC_BSA

=PP3V42_G3H_TPAD

=PP3V42_G3H_BATT

=PP3V3_S5_SMC

=PP3V3_S5_LPCPLUS

=PP3V42_G3H_RTC_D

=PP3V42_G3H_BMON_ISNS

=PP3V42_G3H_ONEWIRE

=PP18V5_G3H_CHGR

=PP3V42_G3H_AUDIO

Power Aliases

SYNC_MASTER=BEN

SYNC_DATE=04/21/2008

16B6

6A7 6B5 6D3

38B8

66B3 66C8 66D8

41C8

6D3

26D7

37B8

67D6

43D3

61B3

43B5

6D3 6B5

29A6

25D8

27D7

48A6 48B5 48C5 48D2

30D7

63D4

37B3

62D8

67B8

37D5

55B7 55C7 55D7

52A8 52D2 54D5 56B6

61C5

49B6 49D7

29C1

67A3

67D4

41B8

37A8 39D7

29C3

38C7

60B8

50B7

20A3

6D3

67D3

69B6

9D5 10C6 11B6 12D6

35C7

6D3

25D3 61D8

67C6

7A8 22D8

22D4

6D3

66A8

20C2 21B3 22B8

43D8

23C7

23D4

6D3

67B6

7A8 22D6

61C1

17C1 18D1 20A4

35A8

35B1 35D2

35D6

45D8

65C6

71C7

65D8

43C8

49A6

45C7

66A8

27A8

66A5

70B8 70C8

26A8

46D6

41A1 41D3

46B6

22B6

20D3 20D8 22A8

62D8

68C5

47C5

52A8 52D2 56D8 57B8 57D3

43D5

43C3

37C7 37D6

12D6

6D3 6D7

34D8

35D3

35C7

34B1

34D2

35D8

36B6

36D5

35D4

35B1

36C6

67C8

65B8

32D5

67D8

66B3

68C8

6D3

32C5

21B3 22B8

28C4

24B8

32C4

21A3 22D8

65A5

31D2

70D8

36A7

10B6 11B6

52D7

10B5 10D6 11D6

44D8

17A6 23D7

64C2

19B6

44D8

61C8

6D3

66B5

64C8

49A5

42D5

47C5

71D4

7D7 22D6

7D7 22D8

21D5 22D8

17B6 23D7

65C5 6D3

22C4 65B1

22D1

19B6

61C2

72D8

45B8

44B8

35B7

60C6 60C7

60C3

6C3

45B7

59C1

63D5

64C6

62C3 62D4 62D8

19B6

16A6

16A3

16B3

22D2

58C8 58D1

62D1

67D1

15C3 15C7 22C8

66A8

27A4

26A4

67B3

32D2

32B2

6C3

17D3 22D6

6C3

22A8

17C7 19C1

42B5 42C7 51C6

35C5

36C3

60B1

31D7

17D3 17D7 22A5 22B6

65B6

27B3

6D3

6D3 63B8 63C1 63C7

35C6

35B4

65B3

13A2 13B7 21D3 22C8

28C6

58B4

59A8 59C6 59D5

43C5

48B5 48C2 48C3

48C5

58C2 58C4

40D4 41C1

41C7

41C3

41D8

42C7 42D5 42C8

24D8

45B8

58D2

59D8

56B6

OUT

IN

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

EMI POGO PINS

ABOVE CPU

EMI IO POGO PINS

PCI-E ALIASES

HEATSINK STANDOFFS

MLB MOUNTING (TO C. BRACKET) SCREW HOLES

FIREWIRE PRESENT SIGNALS

BELOW CPU

USB ALIASES

UNUSED USB PORTS

DP HOTPLUG PULL-DOWN

UNUSED GPU LANES

ETHERNET ALIASES

UNUSED ADDRESS PINS

SO-DIMM ALIASES

UNUSED EXPRESS CARD LANE

LEFT OF CPU

BELOW MCP

DACS ALIASES

UNUSED CRT & TV-OUT INTERFACE

266

(RSVD)

100

133

333

200

(166)

(400)

FSB MHZ

0 0 1

1 1 1

0 1 0

0 0 0

0 1 1

1 0 0

1 0 1

1 1 0

BSEL<2..0>

CPU FSB FREQUENCY STRAPS

FW ALIASES

LAN ALIASES

UNUSED LVDS SIGNALS

LVDS ALIASES

MISC MCP79 ALIASES

FAN STANDOFF

MLB MOUNTING (TO TOPCASE) SCREW HOLES

9 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

STDOFF-4.5OD.98H-1.1-3.48-TH

MF-LF

TP_USB_EXTC_N

1

OMIT

3R2P5

Z0912

3R2P5

Z0909

1

OMIT

1

OMIT

Z0911

3R2P5

1

3R2P5

OMIT

Z0908

1

Z0901

1

Z0904

1

Z0902

1

Z0903

47K

R0930

402

MF-LF

5%

1/16W

2

1

13A7 73C3 9B4

R0940

1

2

MF-LF

5%

1/16W

20K

402

1

Z0905

STDOFF-4.5OD.98H-1.1-3.48-TH

Z0910

1

3R2P5

OMIT

1

3R2P5

OMIT

Z0907

OMIT

1

3R2P5

Z0906

2

402

1/16W

5%

0

1

R0950

NOSTUFF

402

MF-LF

5%

1/16W

2

1

22

R0931

SYNC_MASTER=M97_MLB

SIGNAL ALIAS

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

VOLTAGE=0V

MAKE_BASE=TRUE

LVDS_IG_B_DATA_P<3:0>

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_N<3:0>

NO_TEST=TRUE

TP_RTL8211_CLK125

USB_EXTC_N

=DVI_HPD_GMUX_INT

LVDS_IG_B_CLK_N

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

TP_USB_EXTC_P

USB_MINI_N

USB_MINI_P

TP_USB_MINI_N

MAKE_BASE=TRUE

LVDS_IG_A_DATA_N<3>

LVDS_IG_A_DATA_P<3>

TP_GMUX_JTAG_TCK_L

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDO

MAKE_BASE=TRUE

TP_GMUX_JTAG_TDI

TP_GMUX_JTAG_TMS

MAKE_BASE=TRUE

GMUX_JTAG_TMS

LVDS_IG_B_CLK_P

PCIE_FW_PRSNT_L

USB_EXTC_P

=PEG_R2D_C_N<15:0>

PEG_PRSNT_L

PEG_CLK100M_N

=PEG_D2R_P<15:0>

NO_TEST=TRUE

NC_PEG_D2R_N<15:0>

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

TP_PCIE_EXCARD_D2R_N

MAKE_BASE=TRUE

=MCP_MII_CRS

MAKE_BASE=TRUE

HPLUG_DET2

MCP_MII_PD

MAKE_BASE=TRUE

GMUX_JTAG_TCK_L

MCP_CLK27M_XTALIN

NC_MCP_CLK27M_XTALOUT

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_CRT_IG_B_COMP_PB

NO_TEST=TRUE

TP_PEG_PRSNT_L

MAKE_BASE=TRUE

=RTL8211_ENSWREG

NC_RTL8211_REGOUT

MAKE_BASE=TRUE

=PP3V3_ENET_PHY_VDDREG

MAKE_BASE=TRUE

TP_PP3V3_ENET_PHY_VDDREG

=P1V05ENET_EN

=P3V3ENET_EN

NO_TEST=TRUE

NC_MCP_CLK27M_XTALIN

MAKE_BASE=TRUE

NC_CRT_IG_G_Y_Y

NO_TEST=TRUE

CRT_IG_VSYNC

MEM_A_A<15>

MCP_CLK27M_XTALOUT

MCP_TV_DAC_VREF

NC_PEG_R2D_C_N<15:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_MEM_B_A15

MAKE_BASE=TRUE

TP_MEM_A_A15

NC_PEG_R2D_C_P<15:0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_PEG_D2R_P<15:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

PEG_CLK100M_P

=RTL8211_REGOUT

PM_SLP_RMGT_L

MAKE_BASE=TRUE

MEM_B_A<15>

=MCP_MII_COL

TP_PEG_CLK100M_P

MAKE_BASE=TRUE

TP_PEG_CLK100M_N

NC_LVDS_IG_B_CLK_N

NO_TEST=TRUE

MAKE_BASE=TRUE

LVDS_IG_B_DATA_N<3:0>

NC_CRT_IG_R_C_PR

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_C_P

TP_PCIE_EXCARD_PRSNT_L

MAKE_BASE=TRUE

TP_EXCARD_CLKREQ_L

EXCARD_CLKREQ_L

MAKE_BASE=TRUE

NC_LVDS_IG_B_DATA_P<3:0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_B_CLK_P

NO_TEST=TRUE

MAKE_BASE=TRUE

TP_PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_PRSNT_L

PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

TP_PCIE_EXCARD_D2R_P

MAKE_BASE=TRUE

TP_USB_EXTD_P

USB_EXTD_P

MAKE_BASE=TRUE

TP_USB_EXCARD_P

MAKE_BASE=TRUE

TP_USB_EXTD_N

USB_EXTD_N

=MCP_MII_RXER

NC_MCP_TV_DAC_RSET

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_MCP_TV_DAC_VREF

NO_TEST=TRUE

MAKE_BASE=TRUE

MCP_TV_DAC_RSET

=MCP_BSEL<0:2>

MAKE_BASE=TRUE

CPU_BSEL<0:2>

GMUX_JTAG_TDI

GMUX_JTAG_TDO

CPU_PECI_MCP

TP_PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_N3

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_IG_A_DATA_P3

MAKE_BASE=TRUE

NO_TEST=TRUE

TP_PCIE_CLK100M_EXCARD_N

MAKE_BASE=TRUE

FW_PME_L

FW_PLUG_DET_L

MAKE_BASE=TRUE

TP_CPU_PECI_MCP

=FW_PME_L FW643_WAKE_L

MAKE_BASE=TRUE

NC_CRT_IG_VSYNC

NO_TEST=TRUE

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_CRT_IG_HSYNC

MAKE_BASE=TRUE

CRT_IG_HSYNC

CRT_IG_B_COMP_PB

CRT_IG_G_Y_Y

CRT_IG_R_C_PR

MAKE_BASE=TRUE

TP_USB_MINI_P

TP_USB_EXCARD_N

MAKE_BASE=TRUE

USB_EXCARD_P

=PEG_R2D_C_P<15:0>

=PEG_D2R_N<15:0>

ZS0900,ZS0901,ZS0902,ZS0903,ZS0908,ZS0909

POGO PIN,SHORT,EMI,MLB,K19/K24

CRITICAL870-1801

6

ZS0909

1.4DIA-SHORT-EMI-MLB-M97-M98

OMIT

1

SMSM

1.4DIA-SHORT-EMI-MLB-M97-M98

OMIT

ZS0908

1

SM

OMIT

ZS0903

1

SM

1

ZS0907

2.0DIA-TALL-EMI-MLB-M97-M98

1.4DIA-SHORT-EMI-MLB-M97-M98

SM

OMIT

1

ZS0902

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0906

SM

1

OMIT

1.4DIA-SHORT-EMI-MLB-M97-M98

ZS0901

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0905

SM

1

1.4DIA-SHORT-EMI-MLB-M97-M98

ZS0900

OMIT

SM

1

2.0DIA-TALL-EMI-MLB-M97-M98

ZS0904

SM

1

STDOFF-4.5OD.98H-1.1-3.48-TH

1.4DIA-SHORT-EMI-MLB-M97-M98

USB_EXCARD_N

16D6 16C6

17B3

31B6

19C3

17B6

17B3

16C3

19D3

17B3

18D4

17B3

35D3 16C6

19C3

16D3 16C3

16C6

16C3

16D6 16C6

16B6

17D6

16B6

17C6

31C6

31C2

32B5

16D3 16C3

32C5

17C3

26D5

17C6

16C3

31C2

20C3

27D5

17D6

17B3

16C6

16B3

16C6

16B6

19D3

17D6

19C3

17C6

18D4

16B6

13B6

18B7 35D7 35B1

35C8 34B2

17C3

19C3

BI

IN

OUT

IN

BI

OUT

BI

OUT

IN

OUT

IN

OUT

BI

TEST7

TEST6

DSTBP1*

DINV1*

D31*

D30*

D25*

D11*

D12*

D13*

D14*

DSTBP0*

DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32*

D1*

D2*

D5*

D16*

D20*

D21*

D22*

D23*

D24*

D26*

D27*

D28*

D29*

DSTBN1*

GTLREF

TEST3

TEST4

TEST5

BSEL0

BSEL1

BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2*

DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3*

DSTBP3*

DINV3*

COMP0

COMP1

COMP2

COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

LOCK*

INIT*

A20M*

A6*

A3*

A4*

A14*

A16*

REQ0*

REQ1*

REQ2*

REQ3*

REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20*

A21*

A22*

A23*

A24*

A26*

A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5

RSVD6

RSVD7

RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

CPU JTAG Support

PLACEMENT_NOTE (all 4 resistors):

10 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

FSB_A_L<6>

CPU_INTR

CPU_NMI

CPU_SMI_L

CPU_STPCLK_L

CPU_IGNNE_L

CPU_FERR_L

CPU_A20M_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<27>

FSB_A_L<25>

FSB_A_L<26>

FSB_A_L<24>

FSB_A_L<23>

FSB_A_L<22>

FSB_A_L<20>

FSB_A_L<21>

FSB_A_L<19>

FSB_A_L<18>

FSB_A_L<17>

TP_CPU_RSVD_D3

TP_CPU_RSVD_D22

TP_CPU_RSVD_D2

TP_CPU_RSVD_F6

FSB_A_L<5>

FSB_A_L<15>

FSB_A_L<10>

FSB_ADS_L

CPU_THERMD_N

FSB_A_L<11>

FSB_A_L<7>

FSB_A_L<8>

FSB_A_L<9>

FSB_BPRI_L

FSB_A_L<12>

FSB_A_L<13>

FSB_ADSTB_L<0>

TP_CPU_RSVD_M4

TP_CPU_RSVD_N5

TP_CPU_RSVD_T2

TP_CPU_RSVD_V3

TP_CPU_RSVD_B2

FSB_BNR_L

FSB_DEFER_L

FSB_DRDY_L

FSB_DBSY_L

FSB_BREQ0_L

CPU_IERR_L

FSB_CPURST_L

FSB_RS_L<0>

FSB_RS_L<1>

FSB_RS_L<2>

FSB_TRDY_L

FSB_HIT_L

FSB_HITM_L

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<2>

XDP_BPM_L<3>

XDP_BPM_L<4>

XDP_BPM_L<5>

XDP_TCK

XDP_TDI

XDP_TDO

XDP_TMS

XDP_TRST_L

XDP_DBRESET_L

CPU_PROCHOT_L

CPU_THERMD_P

PM_THRMTRIP_L

FSB_CLK_CPU_P

FSB_CLK_CPU_N

FSB_REQ_L<4>

FSB_REQ_L<3>

FSB_REQ_L<2>

FSB_REQ_L<1>

FSB_REQ_L<0>

FSB_A_L<16>

FSB_A_L<14>

FSB_A_L<4>

FSB_A_L<3>

CPU_INIT_L

FSB_LOCK_L

=PP1V05_S0_CPU

CPU_COMP<3>

CPU_COMP<2>

CPU_COMP<0>

CPU_COMP<1>

CPU_TEST4

CPU_TEST2

CPU_TEST1

CPU_GTLREF

XDP_TCK

XDP_TRST_L

FSB_D_L<32>

FSB_D_L<33>

FSB_D_L<34>

FSB_D_L<35>

FSB_D_L<36>

FSB_D_L<37>

FSB_D_L<38>

FSB_D_L<39>

FSB_D_L<40>

FSB_D_L<41>

FSB_D_L<42>

FSB_D_L<43>

FSB_D_L<44>

FSB_D_L<45>

FSB_D_L<46>

FSB_D_L<47>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<2>

FSB_D_L<48>

FSB_D_L<49>

FSB_D_L<50>

FSB_D_L<51>

FSB_D_L<52>

FSB_D_L<53>

FSB_D_L<54>

FSB_D_L<55>

FSB_D_L<56>

FSB_D_L<57>

FSB_D_L<58>

FSB_D_L<59>

FSB_D_L<60>

FSB_D_L<61>

FSB_D_L<62>

FSB_D_L<63>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_DINV_L<3>

CPU_DPRSTP_L

CPU_DPSLP_L

FSB_DPWR_L

CPU_PWRGD

CPU_PSI_L

FSB_CPUSLP_L

TP_CPU_TEST7

TP_CPU_TEST6

TP_CPU_TEST3

TP_CPU_TEST5

CPU_BSEL<2>

CPU_BSEL<1>

CPU_BSEL<0>

FSB_DINV_L<1>

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<29>

FSB_D_L<28>

FSB_D_L<27>

FSB_D_L<26>

FSB_D_L<25>

FSB_D_L<24>

FSB_D_L<23>

FSB_D_L<22>

FSB_D_L<21>

FSB_D_L<20>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<17>

FSB_D_L<16>

FSB_DINV_L<0>

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<14>

FSB_D_L<13>

FSB_D_L<12>

FSB_D_L<11>

FSB_D_L<10>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<1>

FSB_D_L<0>

XDP_TMS

XDP_TDO

XDP_TDI

SYNC_DATE=12/12/2007

SYNC_MASTER=T18_MLB

CPU FSB

U1000

N3

P5

P2

L2

P4

P1

R1

Y2

U5

R3

W6

A6

U4

Y5

U1

R4

T5

T3

W2

W5

Y4

J4

U2

V4

W3

AA4

AB2

AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22

A21

E2

AD4

AD3

AD1

AC4

G5

F1

C20

E1

H5

F21

A5

G6

E4

D20

C4

B3

C6

B4

H4

AC2

AC1

D21

K3

H2

K2

J3

L1

C1

F3

F4

G3

M4

N5

T2

V3

B2

F6

D2

D22

D3

A3

D5

AC5

AA6

AB3

A24

B25

C7

AB5

G2

AB6

FCBGA

OMIT

PENRYN

R1092

1 2

PLACEMENT_NOTE=Place R1092 near ITP connector (if present)

54.9

1/16W

MF-LF

1%

402

U1000

B22

B23

C21

R26

U26

AA1

Y1

E22

F24

J24

J23

H22

F26

K22

H23

N22

K25

P26

R23

E26

L23

M24

L22

M23

P25

P23

P22

T24

R24

L25

G22

T25

N25

Y22

AB24

V24

V26

V23

T22

U25

U23

F23

Y25

W22

Y23

W24

W25

AA23

AA24

AB25

AE24

AD24

G25

AA21

AB22

AB21

AC26

AD20

AE22

AF23

AC25

AE21

AD21

E25

AC22

AD23

AF22

AC23

E23

K24

G24

H25

N24

U22

AC20

E5

B5

D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6

D7

C23

D25

C24

AF26

AF1

A26

C3

FCBGA

PENRYN

OMIT

C1014

1

2

PLACEMENT_NOTE=Place C1014 within 12.7mm of CPU.

NO STUFF

X5R

0.1uF

10%

16V

402

R1012

1

2

402

MF-LF

1K

5%

1/16W

NO STUFF

R1094

1 2

1%

MF-LF

1/16W

649

402

13C6 73C3

R1093

1 2

1%

MF-LF

1/16W

54.9

402

R1091

1 2

1%

MF-LF

1/16W

54.9

402

R1090

1 2

54.9

1/16W

MF-LF

1%

402

R1001

1

2

54.9

402

MF-LF

1%

1/16W

R1011

1

2

NO STUFF

1/16W

5%

MF-LF

1K

402

R1010

1 2

NO STUFF

5%

MF-LF

1/16W

0

402

13B7 73C3

13A3 73B3

13A3 73C3

13B3 73B3

46D5 80D3

9A6 12B3 73A3

9B6 12B3 73A3

9A6 12B6 73A3

13B6 73C3

13A6 73C3

12C2 13A3 73C3

13A3 73C3

13B7 41C4 73B3

46D5 80D3

13B6 41D4 62C8 73C3

12B3 24A3

9B6 12B3 73A3

12C6 73A3

13B6 73C3

13B3 73C3

13B6 73C3

13C6 73C3

13B6 73D3

13C6 73D3

13D6 73D3

8B2 73C3

13D6 73D3

13C3 73D3

13D3 73D3

13D6 73D3

13D3 73D3

12C7 13A3 73C3

62C7

13A3 73B3

13A3 62C7 73B3

13D6 73D3

13B3 73D3

13D6 73D3

13B3 73D3

13C3 73D3

R1020

1

2

Place within 12.7mm of CPU

27.4

1%

1/16W

MF-LF

402

R1021

1

2

Place within 12.7mm of CPU

402

MF-LF

1/16W

1%

54.9

R1022

1

2

Place within 12.7mm of CPU

27.4

1%

1/16W

MF-LF

402

R1023

1

2

Place within 12.7mm of CPU

54.9

1%

1/16W

MF-LF

402

R1006

1

2

PLACEMENT_NOTE=Place R1006 within 12.7mm of CPU.

1%

MF-LF

2.0K

1/16W

402

R1005

1

2

PLACEMENT_NOTE=Place R1005 within 12.7mm of CPU.

402

1K

MF-LF

1%

1/16W

R1002

1

2

68

5%

1/16W

MF-LF

402

R1000

1

2

1%

1/16W

54.9

MF-LF

402

73B3

7D7 10C6 11B6 12D6

73B3

73A3

73B3

25B1 73B3

9C6 12B6 73A3

9C6 12B3 73A3

OUT

VCC

VCCP

VCCA

VID0

VID1

VID2

VID3

VID4

VID5

VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

2500 mA (after VCC stable)

4500 mA (before VCC stable)

(Socket-P KEY)

41 A (SV HFM)

130 mA

(CPU CORE POWER)

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

23 A (LV Design Target)

44 A (SV Design Target)

(BR1#)

CHANGE CPU FROM SOCKET TO BGA SYMBOL

SYNC FROM T18

Current numbers from Merom for Santa Rosa EMTS, doc #20905.

30.4 A (SV LFM)

11 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

CPU_VCCSENSE_N

CPU_VCCSENSE_P

=PPVCORE_S0_CPU

CPU_VID<0>

CPU_VID<1>

CPU_VID<2>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

CPU_VID<3>

CPU_VID<4>

CPU_VID<5>

CPU_VID<6>

=PPVCORE_S0_CPU

SYNC_DATE=12/12/2007

SYNC_MASTER=T18_MLB

CPU Power & Ground

PLACEMENT_NOTE=Place R1100 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

2

1

R1100

OMIT

PENRYN

FCBGA

V25

V22

V5

V2

U24

U21

U6

U3

T26

T23

B8

T4

T1

R25

R22

R5

R2

P24

P21

P6

P3

B6

N26

N23

N4

N1

M25

M22

M5

M2

L24

L21

AF2

L6

L3

K26

K23

K4

K1

J25

J22

J5

J2

A23

H24

H21

H6

H3

G26

G23

G1

G4

F25

F22

A19

F2

F19

F16

F13

F11

F8

F5

E24

E21

E19

A16

E16

E14

E11

E8

E6

E3

D26

D23

D19

D16

A14

D13

D11

D8

D4

D1

C25

C22

C2

C19

C16

A11

C14

C11

C8

B1

AF25

A25

AF21

C5

AF19

AF16

AF13

AF11

AF8

AF6

A2

AE26

AE23

AE19

B24

AE16

AE14

AE11

AE8

AE4

AE1

AD25

AD22

AD19

AD16

B21

AD13

AD11

AD8

AD5

AD2

AC24

AC21

AC19

AC16

AC14

B19

AC11

AC8

AC6

AC3

AB26

AB23

AB19

AB16

AB13

AB11

B16

AB8

AB4

AB1

AA25

AA22

AA19

AA16

AA14

AA11

AA8

B13

AA5

AA2

Y24

Y21

Y6

Y3

W26

W23

W4

W1

B11

A8

A4

U1000

PENRYN

OMIT

FCBGA

AE7

AE2

AF3

AE3

AF4

AE5

AF5

AD6

AF7

N6

N21

M21

K21

J21

M6

K6

J6

W21

V21

T6

T21

R6

R21

V6

G21

C26

B26

AF20

AF18

AF17

AF15

AF14

AF12

AF10

AF9

AE20

AE18

B7

AE17

AE15

AE13

AE12

AE10

AE9

AD18

AD17

AD15

AD14

A20

AD12

AD10

AD9

AD7

AC18

AC17

AC15

AC13

AC12

AC9

A18

AC7

AB7

AB20

AB18

AB17

AB15

AB14

AB12

AB10

AC10

A17

AB9

AA20

AA18

AA17

AA15

AA13

AA12

AA10

AA9

AA7

A15

F20

F18

F17

F15

F14

F12

F10

F9

F7

E20

A13

E18

E17

E15

E13

E12

E10

E9

E7

D18

D17

A12

D15

D14

D12

D10

D9

C18

C17

C15

C13

C12

A10

C10

C9

B20

B18

B17

B15

B14

B12

B10

B9

A9

A7

U1000

62A5 73A3

62C7 73A3

PLACEMENT_NOTE=Place R1101 within 25.4mm of CPU, no stubs.

1/16W

1%

100

402

MF-LF

2

1

R1101

62C7 73A3

7D7 10D6 11D6

7D7 9D5 11B6 12D6

7B6 11B6

7D7 10B5 11D6

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACEMENT_NOTE (C1200-C1219):

1x 10uF, 1x 0.01uF

1x 330uF, 6x 0.1uF 0402

SYNC FROM T18

REMOVE NO STUFF CAPS C1220 TO C1231

CPU VCore HF and Bulk Decoupling

REMOVE C1244 & C1245

CHANGE C1240-C1243 AND C1260 FROM 128S0241(9 MILLI-OHM) TO 128S0231(6 MILLI-OHM)

4X 330UF. 20X 22UF 0805

VCCP (CPU I/O) DECOUPLING

VCCA (CPU AVdd) DECOUPLING

PLACEMENT_NOTE (C1240-C1243):

12 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP1V05_S0_CPU

=PP1V5_S0_CPU

=PPVCORE_S0_CPU

CPU Decoupling

SYNC_DATE=03/31/2008

SYNC_MASTER=RAYMOND

CRITICAL

Place on secondary side.

3 2

1

D2T-SM

470UF-4MOHM

2.0V

20%

POLY-TANT

C1243

CRITICAL

C1242

470UF-4MOHM

Place on secondary side.

3 2

1

D2T-SM

POLY-TANT

20%

2.0V

470UF-4MOHM

CRITICAL

Place on secondary side.

D2T-SM

20%

2.0V

POLY-TANT

3 2

1

C1241

470UF-4MOHM

CRITICAL

Place on secondary side.

NOSTUFF

20%

1

C1240

3 2

D2T-SM

POLY-TANT

2.0V

6.3V

603

X5R

20%

10uF

C1250

1

2

PLACEMENT_NOTE=Place C1281 near CPU pin B26.

10%

402

CERM

16V

0.01UF

C1251

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1218

1

2

10V

402

0.1UF

CERM

20%

C1266

1

2

0.1UF

CERM

10V

402

20%

C1265

1

2

10V

402

0.1UF

CERM

20%

C1264

1

2

C1263

10V

402

0.1UF

CERM

20%

1

2

10V

402

0.1UF

CERM

20%

C1262

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CERM-X5R

C1217

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CERM-X5R

C1215

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CERM-X5R

C1209

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CERM-X5R

C1205

1

2

10V

402

0.1UF

20%

C1261

1

CERM

2

C1210

CRITICAL

6.3V

Place inside socket cavity on secondary side.

CERM-X5R

20%

805

1

2

22UF

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1200

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CERM-X5R

C1219

1

2

CERM-X5R

6.3V

20%

805

22UF

CRITICAL

Place inside socket cavity on secondary side.

C1211

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

22UF

C1212

1

2

CRITICAL

Place inside socket cavity on secondary side.

22UF

805

20%

6.3V

CERM-X5R

C1213

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CERM-X5R

1

2

C1201

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

C1202

1

2

22UF

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CERM-X5R

C1207

1

2

CRITICAL

Place inside socket cavity on secondary side.

805

22UF

20%

6.3V

CERM-X5R

C1203

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1208

1

2

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

805

C1214

1

2

22UF

CRITICAL

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1216

1

2

CRITICAL

2

Place inside socket cavity on secondary side.

CERM-X5R

6.3V

20%

22UF

805

C1204

1

2.0V

D2T-SM2

PLACEMENT_NOTE=Place C1260 between CPU & NB.

POLY-TANT

CRITICAL

330UF

20%

C1260

1

2 3

CRITICAL

CERM-X5R

6.3V

20%

22UF

C1206

1

2

Place inside socket cavity on secondary side.

805

7D7 9D5 10C6 12D6

7B6 10B6

7D7 10B5 10D6

IN

BI

OUT

IN

BI

IN

OUT

BI

OUT

IN

OUT

NC

IN

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

MCP79-specific pinout

OBSDATA_C2

TRSTn

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

DBR#/HOOK7

TDO

RESET#/HOOK6

HOOK2

OBSDATA_D0

OBSDATA_C3

VCC_OBS_CD

ITPCLK#/HOOK5

Direction of XDP module

OBSDATA_A2

OBSDATA_A1

OBSDATA_B0

Use with 920-0620 adapter board to support CPU, MCP debugging.

OBSFN_A0

OBSFN_A1

OBSDATA_A0

OBSFN_B1

OBSDATA_B1 OBSDATA_D1

OBSDATA_D2

OBSDATA_D3

ITPCLK/HOOK4

998-1571

OBSFN_C1

OBSFN_B0

XDP_PRESENT#

OBSDATA_B3

OBSFN_D1

OBSDATA_B2

TMS

HOOK1

HOOK3

SDA

SCL

OBSFN_D0

VCC_OBS_AB

NOTE: This is not the standard XDP pinout.

on even-numbered side of J1300

Please avoid any obstructions

Mini-XDP Connector

OBSDATA_C0

OBSFN_C0

OBSDATA_A3

TCK0

TCK1

PWRGD/HOOK0

OBSDATA_C1

TDI

13 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MCP_DEBUG<4>

XDP_TDO

JTAG_MCP_TDO

XDP_BPM_L<0>

XDP_BPM_L<1>

XDP_BPM_L<3>

MCP_DEBUG<3>

=PP3V3_S0_XDP

XDP_CPURST_L

FSB_CLK_ITP_P

FSB_CLK_ITP_N

XDP_DBRESET_L

XDP_TRST_L

XDP_TDI

XDP_TMS

JTAG_MCP_TMS

MCP_DEBUG<2>

JTAG_MCP_TDI

MCP_DEBUG<5>

MCP_DEBUG<6>

MCP_DEBUG<7>

JTAG_MCP_TRST_L

FSB_CPURST_L

MCP_DEBUG<1>

MCP_DEBUG<0>

XDP_TCK

SMBUS_MCP_0_DATA

JTAG_MCP_TCK

PM_LATRIGGER_L

=PP1V05_S0_CPU

XDP_OBS20

TP_XDP_OBSDATA_B3

XDP_PWRGD

TP_XDP_OBSDATA_B2

TP_XDP_OBSDATA_B1

TP_XDP_OBSFN_B1

TP_XDP_OBSFN_B0

XDP_BPM_L<2>

XDP_BPM_L<4>

CPU_PWRGD

SMBUS_MCP_0_CLK

TP_XDP_OBSDATA_B0

XDP_BPM_L<5>

eXtended Debug Port(MiniXDP)

SYNC_MASTER=K19_MLB

SYNC_DATE=11/07/2008

20B7

9B6 9C6 73A3

2

51

49

47

45

44

15

17

19

54

12

53

LTH-030-01-G-D-NOPEGS

XDP_CONN

CRITICAL

J1300

F-ST-SM

59

57

55

41

43

35

39

37

31

33

25

27

29

21

23

13

11

9

7

5

1

34

6

8

10

14

20

16

18

22

24

26

30

28

34

32

38

40

36

42

46

48

50

56

52

58

60

18C4

9C6 24A3

9B6 9C6 73A3

9A6 9C6 73A3

13B3 73B3

20B7

18D7 76D3

20B7

9C6 73A3

402

MF-LF

1/16W

5%

1K

R1303

PLACEMENT_NOTE=Place close to CPU to minimize stub.

XDP

1 2

9D6 13A3 73C3

9A6 9C6 73A3

9C6 73A3

9C5 73A3

C1301

1

2

402

16V

XDP

0.1uF

10%

X5R

C1300

1

2

X5R

10%

16V

XDP

0.1uF

402

R1315

1

2

XDP

402

1%

1/16W

54.9

MF-LF

20C3 43D8 76B3

R1399

1 2

1/16W

5%

XDP

MF-LF

402

1K

9B2 13A3 73C3

7C5

73A3

7D7 9D5 10C6 11B6

IN

OUT

BI

IN

BI

OUT

IN

BI

CPU_BR0#

CPU_BNR#

BCLK_OUT_NB_N

CPU_BR1#

CPU_REQ4#

CPU_ADS#

CPU_A27#

CPU_A26#

CPU_A25#

CPU_A34#

CPU_D62#

CPU_D61#

CPU_D60#

CPU_A28#

CPU_A29#

CPU_A30#

CPU_A31#

CPU_A32#

CPU_A22#

CPU_A23#

CPU_A24#

CPU_REQ3#

CPU_REQ2#

CPU_DBI3#

CPU_D14#

CPU_D13#

CPU_D12#

CPU_D11#

CPU_D10#

CPU_DPWR#

CPU_RS1#

BCLK_VML_COMP_GND

CPU_COMP_VCC

CPU_TRDY#

CPU_PROCHOT#

CPU_BSEL0

CPU_RS2#

CPU_BSEL1

BCLK_IN_P

BCLK_OUT_CPU_N

CPU_PWRGD

CPU_DSTBP0#

CPU_DSTBP1#

CPU_DBI1#

CPU_DBI0#

CPU_DSTBN1#

CPU_DSTBN0#

CPU_DBI2#

CPU_DSTBP2#

CPU_DSTBN2#

CPU_DSTBP3#

CPU_A4#

CPU_DSTBN3#

CPU_A3#

CPU_A5#

CPU_A9#

CPU_A8#

CPU_A6#

CPU_A7#

CPU_A12#

CPU_A14#

CPU_A13#

CPU_A11#

CPU_A15#

CPU_A16#

CPU_A19#

CPU_A17#

CPU_A18#

CPU_A20#

CPU_A21#

CPU_A35#

CPU_A33#

CPU_ADSTB0#

CPU_REQ0#

CPU_LOCK#

CPU_HIT#

CPU_HITM#

CPU_FERR#

CPU_THERMTRIP#

CPU_PECI

CPU_COMP_GND

CPU_D0#

CPU_D1#

CPU_D3#

CPU_D2#

CPU_D4#

CPU_D5#

CPU_D6#

CPU_D8#

CPU_D7#

CPU_D9#

CPU_D15#

CPU_D17#

CPU_D18#

CPU_D16#

CPU_D19#

CPU_D20#

CPU_D21#

CPU_D23#

CPU_D22#

CPU_D24#

CPU_D25#

CPU_D26#

CPU_D27#

CPU_D28#

CPU_D29#

CPU_D30#

CPU_D31#

CPU_D32#

CPU_D33#

CPU_D34#

CPU_D35#

CPU_D36#

CPU_D38#

CPU_D37#

CPU_D39#

CPU_D40#

CPU_D41#

CPU_D43#

CPU_D42#

CPU_D44#

CPU_D45#

CPU_D46#

CPU_D47#

CPU_D52#

CPU_D53#

CPU_D54#

CPU_D55#

CPU_D56#

CPU_D57#

CPU_D58#

CPU_D59#

CPU_D63#

CPU_BPRI#

CPU_DEFER#

BCLK_OUT_CPU_P

BCLK_OUT_ITP_P

BCLK_OUT_ITP_N

BCLK_OUT_NB_P

BCLK_IN_N

CPU_A20M#

CPU_NMI

CPU_INTR

CPU_SMI#

CPU_RESET#

CPU_SLP#

CPU_DPSLP#

CPU_STPCLK#

CPU_DPRSTP#

CPU_D51#

CPU_D50#

CPU_D49#

CPU_D48#

CPU_ADSTB1#

CPU_IGNNE#

CPU_INIT#

BCLK_VML_COMP_VDD

CPU_RS0#

+V_DLL_DLCELL_AVDD

+V_PLL_MCLK

+V_PLL_FSB

+V_PLL_CPU

CPU_A10#

CPU_BSEL2

CPU_DBSY#

CPU_DRDY#

CPU_REQ1#

FSB

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Loop-back clock for delay matching.

(MCP_BSEL<2>)

(MCP_BSEL<1>)

(MCP_BSEL<0>)

20 mA

29 mA

15 mA

206 mA

270 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

14 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=MCP_BSEL<1>

=MCP_BSEL<0>

=MCP_BSEL<2>

=PP1V05_S0_MCP_FSB

FSB_BREQ1_L

FSB_ADS_L

FSB_BREQ0_L

CPU_FERR_L

FSB_RS_L<0>

FSB_BNR_L

FSB_DRDY_L

FSB_DBSY_L

FSB_A_L<33>

FSB_A_L<34>

FSB_A_L<25>

FSB_A_L<10>

FSB_D_L<7>

FSB_D_L<14>

PP1V05_S0_MCP_PLL_FSB

=PP1V05_S0_MCP_FSB

FSB_DSTB_L_P<0>

FSB_DSTB_L_N<0>

FSB_DINV_L<0>

FSB_DSTB_L_P<1>

FSB_DSTB_L_N<1>

FSB_DINV_L<1>

FSB_DSTB_L_P<2>

FSB_DSTB_L_N<2>

FSB_DINV_L<2>

FSB_DSTB_L_P<3>

FSB_DSTB_L_N<3>

FSB_DINV_L<3>

FSB_A_L<3>

FSB_A_L<4>

FSB_A_L<5>

FSB_A_L<6>

FSB_A_L<7>

FSB_A_L<8>

FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<12>

FSB_A_L<13>

FSB_A_L<14>

FSB_A_L<15>

FSB_A_L<16>

FSB_A_L<17>

FSB_A_L<18>

FSB_A_L<19>

FSB_A_L<20>

FSB_A_L<21>

FSB_A_L<22>

FSB_A_L<23>

FSB_A_L<24>

FSB_A_L<26>

FSB_A_L<27>

FSB_A_L<28>

FSB_A_L<29>

FSB_A_L<30>

FSB_A_L<31>

FSB_A_L<32>

FSB_A_L<35>

FSB_ADSTB_L<0>

FSB_ADSTB_L<1>

FSB_REQ_L<0>

FSB_REQ_L<1>

FSB_REQ_L<2>

FSB_REQ_L<3>

FSB_REQ_L<4>

FSB_HIT_L

FSB_HITM_L

FSB_LOCK_L

FSB_TRDY_L

CPU_PECI_MCP

CPU_PROCHOT_L

FSB_RS_L<1>

FSB_RS_L<2>

MCP_BCLK_VML_COMP_VDD

MCP_CPU_COMP_VCC

MCP_CPU_COMP_GND

FSB_D_L<0>

FSB_D_L<1>

FSB_D_L<2>

FSB_D_L<3>

FSB_D_L<4>

FSB_D_L<5>

FSB_D_L<6>

FSB_D_L<8>

FSB_D_L<9>

FSB_D_L<10>

FSB_D_L<11>

FSB_D_L<12>

FSB_D_L<15>

FSB_D_L<16>

FSB_D_L<17>

FSB_D_L<18>

FSB_D_L<19>

FSB_D_L<20>

FSB_D_L<21>

FSB_D_L<22>

FSB_D_L<23>

FSB_D_L<24>

FSB_D_L<25>

FSB_D_L<26>

FSB_D_L<27>

FSB_D_L<28>

FSB_D_L<29>

FSB_D_L<30>

FSB_D_L<31>

FSB_D_L<32>

FSB_D_L<33>

FSB_D_L<34>

FSB_D_L<35>

FSB_D_L<36>

FSB_D_L<37>

FSB_D_L<39>

FSB_D_L<40>

FSB_D_L<41>

FSB_D_L<42>

FSB_D_L<44>

FSB_D_L<46>

FSB_D_L<47>

FSB_D_L<48>

FSB_D_L<49>

FSB_D_L<50>

FSB_D_L<51>

FSB_D_L<52>

FSB_D_L<53>

FSB_D_L<54>

FSB_D_L<55>

FSB_D_L<56>

FSB_D_L<57>

FSB_D_L<58>

FSB_D_L<59>

FSB_D_L<60>

FSB_D_L<61>

FSB_D_L<62>

FSB_D_L<63>

FSB_BPRI_L

FSB_DEFER_L

FSB_CLK_CPU_P

FSB_CLK_CPU_N

FSB_CLK_ITP_P

FSB_CLK_ITP_N

FSB_CLK_MCP_N

FSB_CLK_MCP_P

CPU_A20M_L

CPU_IGNNE_L

CPU_INIT_L

CPU_INTR

CPU_NMI

CPU_SMI_L

CPU_PWRGD

FSB_CPURST_L

FSB_CPUSLP_L

CPU_STPCLK_L

CPU_DPRSTP_L

FSB_D_L<45>

FSB_D_L<43>

FSB_D_L<38>

CPU_DPSLP_L

FSB_DPWR_L

MCP_BCLK_VML_COMP_GND

FSB_D_L<13>

PM_THRMTRIP_L

SYNC_MASTER=T18_MLB

MCP CPU Interface

SYNC_DATE=04/04/2008

2

1

R1416

5%

62

MF-LF

402

1/16W

AH27

AG28

AH28

AG27

AE41

AG43

AG42

AH41

AM33

AC42

AB41

AC41

H38

AC35

AC33

AC39

AA33

AC38

AH43

AJ41

E41

AG41

AC43

AF42

AH42

AH39

AD40

AB42

AH40

M39

N37

W39

T40

M41

L36

W37

U40

AD41

AM32

AN33

AN32

AA40

AD39

J41

N35

V35

V41

U41

P42

Y42

M43

H39

J40

K41

Y41

H42

H43

L41

H41

K42

H40

M40

N40

N41

P41

V42

M42

L42

J37

J38

J39

N38

N36

L38

L39

L37

Y39

R38

R37

R39

P35

R35

R34

N33

N34

U37

R33

W41

W38

U34

U33

U35

U36

U38

AA35

AA38

AA34

AA36

Y40

W34

W33

AA37

W35

T43

R41

T41

T42

T39

R42

W42

Y43

AM43

AM42

F42

D42

F41

AL32

AE40

AA41

AD43

AK35

AE36

AD42

AB35

AE35

AE37

AC37

AE34

AE38

AN35

AR39

AN34

AL35

AL38

AJ34

AC34

AN37

AL34

AL37

AJ38

AJ36

AJ37

AJ35

AN36

AJ33

AF41

AL33

AG33

AL39

AN38

AG34

AG38

AG37

AE33

AG39

AG35

AF35

AM39

AM40

AL41

AK42

AL43

AL42

G42

G41

AJ40

AK41

U1400

BGA

(1 OF 11)

MCP79-TOPO-B

OMIT

2

1

R1440

5%

MF-LF

402

1/16W

150

NO STUFF

2

1

R1410

1%

54.9

MF-LF

402

1/16W

2

1

R1415

5%

62

MF-LF

402

1/16W

2

1

R1420

1/16W

NO STUFF

MF-LF

402

5%

1K

2

1

R1421

1/16W

5%

MF-LF

402

NO STUFF

1K

2

1

R1422

MF-LF

1/16W

5%

402

1K

NO STUFF

2

1

R1435

MF-LF

402

1%

1/16W

49.9

2

1

R1430

1/16W

1%

402

MF-LF

49.9

2

1

R1431

49.9

MF-LF

402

1%

1/16W

2

1

R1436

MF-LF

402

1%

1/16W

49.9

9C8 73C3

9C6 41C4 73B3

9C5 41D4 62C8 73C3

8C4

9B2 62C7 73B3

9C8 73B3

9B2 73B3

9B2 12C7 73C3

9B8 73B3

9B8 73C3

9C8 73C3

9D6 73C3

9C8 73C3

9D6 73C3

12C3 73B3

9B6 73B3

9D6 73C3

9D8 73D3

9C8 73C3

9D8 73D3

9B2 73D3

9C2 73D3

9B4 73D3

9C4 73D3

9C8 73C3

9D8 73C3

9D8 73D3

9B2 73D3

9C2 73D3

9B4 73D3

9C4 73D3

9B2 73D3

9D6 12C2 73C3

9C8 73C3

8B1

7D7 13A2 21D3 22C8

73C3

22C2 7D7 13B7 21D3 22C8

73B3

0A

MEMORY

MEMORY PARTITION 0

CONTROL

MCKE0A_1

MCKE0A_0

MODT0A_1

MODT0A_0

MCS0A_0#

MCS0A_1#

MCLK0A_0_N

MCLK0A_0_P

MCLK0A_1_N

MCLK0A_2_N

MCLK0A_1_P

MCLK0A_2_P

MA0_0

MA0_1

MA0_2

MA0_3

MA0_4

MA0_5

MA0_6

MA0_8

MA0_7

MA0_9

MA0_10

MA0_11

MA0_13

MA0_12

MA0_14

MBA0_2

MBA0_0

MBA0_1

MWE0#

MCAS0#

MRAS0#

MDQS0_0_P

MDQS0_0_N

MDQS0_1_P

MDQS0_2_N

MDQS0_1_N

MDQS0_2_P

MDQS0_3_N

MDQS0_4_P

MDQS0_3_P

MDQS0_4_N

MDQS0_5_N

MDQS0_5_P

MDQS0_6_N

MDQS0_6_P

MDQS0_7_N

MDQS0_7_P

MDQM0_2

MDQM0_1

MDQM0_0

MDQM0_3

MDQM0_4

MDQ0_0

MDQM0_7

MDQM0_5

MDQM0_6

MDQ0_1

MDQ0_4

MDQ0_3

MDQ0_2

MDQ0_5

MDQ0_6

MDQ0_9

MDQ0_8

MDQ0_7

MDQ0_10

MDQ0_11

MDQ0_15

MDQ0_14

MDQ0_13

MDQ0_12

MDQ0_16

MDQ0_21

MDQ0_20

MDQ0_18

MDQ0_19

MDQ0_17

MDQ0_25

MDQ0_24

MDQ0_23

MDQ0_22

MDQ0_26

MDQ0_29

MDQ0_28

MDQ0_27

MDQ0_30

MDQ0_31

MDQ0_35

MDQ0_34

MDQ0_32

MDQ0_36

MDQ0_33

MDQ0_41

MDQ0_37

MDQ0_38

MDQ0_40

MDQ0_39

MDQ0_42

MDQ0_47

MDQ0_46

MDQ0_43

MDQ0_45

MDQ0_44

MDQ0_51

MDQ0_50

MDQ0_49

MDQ0_52

MDQ0_48

MDQ0_55

MDQ0_54

MDQ0_53

MDQ0_56

MDQ0_57

MDQ0_61

MDQ0_60

MDQ0_58

MDQ0_59

MDQ0_62

MDQ0_63

OUT

BI

OUT

BI

OUT

MEMORY

CONTROL

1A

MEMORY PARTITION 1

MDQ1_63

MDQ1_60

MDQ1_59

MDQ1_62

MDQ1_58

MDQ1_61

MDQ1_57

MDQ1_53

MDQ1_56

MDQ1_55

MDQ1_54

MDQ1_52

MDQ1_49

MDQ1_51

MDQ1_50

MDQ1_48

MDQ1_47

MDQ1_46

MDQ1_43

MDQ1_44

MDQ1_45

MDQ1_42

MDQ1_41

MDQ1_37

MDQ1_38

MDQ1_39

MDQ1_36

MDQ1_35

MDQ1_32

MDQ1_33

MDQ1_34

MDQ1_31

MDQ1_30

MDQ1_27

MDQ1_28

MDQ1_29

MDQ1_22

MDQ1_26

MDQ1_25

MDQ1_24

MDQ1_23

MDQ1_17

MDQ1_19

MDQ1_20

MDQ1_18

MDQ1_21

MDQ1_16

MDQ1_12

MDQ1_13

MDQ1_14

MDQ1_15

MDQ1_11

MDQ1_10

MDQ1_7

MDQ1_8

MDQ1_9

MDQ1_3

MDQ1_6

MDQ1_2

MDQ1_4

MDQ1_5

MDQ1_1

MDQM1_6

MDQM1_5

MDQ1_0

MDQM1_7

MDQM1_4

MDQM1_3

MDQM1_0

MDQM1_1

MDQM1_2

MDQ1_40

MDQS1_7_P

MDQS1_6_N

MDQS1_6_P

MDQS1_7_N

MDQS1_5_N

MDQS1_5_P

MDQS1_4_P

MDQS1_3_P

MDQS1_4_N

MDQS1_2_P

MDQS1_3_N

MDQS1_1_P

MDQS1_2_N

MDQS1_1_N

MDQS1_0_P

MDQS1_0_N

MRAS1#

MCAS1#

MWE1#

MBA1_2

MBA1_1

MBA1_0

MA1_14

MA1_13

MA1_12

MA1_11

MA1_10

MA1_9

MA1_8

MA1_7

MA1_6

MA1_5

MA1_4

MA1_3

MA1_2

MA1_1

MA1_0

MCLK1A_2_P

MCLK1A_1_P

MCLK1A_2_N

MCLK1A_0_P

MCLK1A_1_N

MCS1A_1#

MCS1A_0#

MCLK1A_0_N

MODT1A_1

MODT1A_0

MCKE1A_0

MCKE1A_1

BI

OUT

BI

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

15 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MEM_A_A<5>

MEM_A_DQS_P<7>

MEM_A_DQS_N<7>

MEM_A_DQS_P<6>

MEM_A_DQS_N<6>

MEM_A_DQS_P<5>

MEM_A_DQS_N<5>

MEM_A_DQS_P<4>

MEM_A_DQS_N<4>

MEM_A_DQS_P<3>

MEM_A_DQS_N<3>

MEM_A_DQS_P<2>

MEM_A_DQS_N<2>

MEM_A_DQS_P<1>

MEM_A_DQS_N<1>

MEM_A_DQS_P<0>

MEM_A_DQS_N<0>

MEM_A_RAS_L

MEM_A_CAS_L

MEM_A_WE_L

MEM_A_BA<2>

MEM_A_BA<1>

MEM_A_BA<0>

MEM_A_A<14>

MEM_A_A<13>

MEM_A_A<12>

MEM_A_A<11>

MEM_A_A<10>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<7>

MEM_A_A<6>

MEM_A_A<4>

MEM_A_A<3>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

TP_MEM_A_CLK2P

TP_MEM_A_CLK2N

MEM_A_CLK_P<1>

MEM_A_CLK_N<1>

MEM_A_CLK_P<0>

MEM_A_CLK_N<0>

MEM_A_CS_L<1>

MEM_A_CS_L<0>

MEM_A_ODT<1>

MEM_A_ODT<0>

MEM_A_CKE<1>

MEM_A_CKE<0>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQS_P<4>

MEM_B_DQS_N<4>

MEM_B_DQS_P<3>

MEM_B_DQS_N<3>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQS_P<1>

MEM_B_DQS_N<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_RAS_L

MEM_B_CAS_L

MEM_B_WE_L

MEM_B_BA<2>

MEM_B_BA<1>

MEM_B_BA<0>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<12>

MEM_B_A<11>

MEM_B_A<10>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_A<6>

MEM_B_A<5>

MEM_B_A<4>

MEM_B_A<3>

MEM_B_A<2>

MEM_B_A<1>

MEM_B_A<0>

TP_MEM_B_CLK2P

TP_MEM_B_CLK2N

MEM_B_CLK_P<1>

MEM_B_CLK_N<1>

MEM_B_CLK_P<0>

MEM_B_CLK_N<0>

MEM_B_CS_L<1>

MEM_B_CS_L<0>

MEM_B_ODT<1>

MEM_B_ODT<0>

MEM_B_CKE<1>

MEM_B_CKE<0>

MEM_A_DQ<63>

MEM_A_DQ<62>

MEM_A_DQ<61>

MEM_A_DQ<60>

MEM_A_DQ<59>

MEM_A_DQ<58>

MEM_A_DQ<57>

MEM_A_DQ<56>

MEM_A_DQ<55>

MEM_A_DQ<54>

MEM_A_DQ<53>

MEM_A_DQ<52>

MEM_A_DQ<51>

MEM_A_DQ<50>

MEM_A_DQ<49>

MEM_A_DQ<48>

MEM_A_DQ<47>

MEM_A_DQ<46>

MEM_A_DQ<45>

MEM_A_DQ<44>

MEM_A_DQ<43>

MEM_A_DQ<42>

MEM_A_DQ<41>

MEM_A_DQ<40>

MEM_A_DQ<39>

MEM_A_DQ<38>

MEM_A_DQ<37>

MEM_A_DQ<36>

MEM_A_DQ<35>

MEM_A_DQ<34>

MEM_A_DQ<33>

MEM_A_DQ<32>

MEM_A_DQ<31>

MEM_A_DQ<30>

MEM_A_DQ<29>

MEM_A_DQ<28>

MEM_A_DQ<27>

MEM_A_DQ<26>

MEM_A_DQ<25>

MEM_A_DQ<24>

MEM_A_DQ<23>

MEM_A_DQ<22>

MEM_A_DQ<21>

MEM_A_DQ<20>

MEM_A_DQ<19>

MEM_A_DQ<18>

MEM_A_DQ<17>

MEM_A_DQ<16>

MEM_A_DQ<15>

MEM_A_DQ<14>

MEM_A_DQ<13>

MEM_A_DQ<12>

MEM_A_DQ<11>

MEM_A_DQ<10>

MEM_A_DQ<9>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<6>

MEM_A_DQ<5>

MEM_A_DQ<4>

MEM_A_DQ<3>

MEM_A_DQ<2>

MEM_A_DQ<1>

MEM_A_DQ<0>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<1>

MEM_A_DM<0>

MEM_B_DQ<63>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DQ<60>

MEM_B_DQ<59>

MEM_B_DQ<58>

MEM_B_DQ<57>

MEM_B_DQ<56>

MEM_B_DQ<55>

MEM_B_DQ<54>

MEM_B_DQ<53>

MEM_B_DQ<52>

MEM_B_DQ<51>

MEM_B_DQ<50>

MEM_B_DQ<49>

MEM_B_DQ<48>

MEM_B_DQ<47>

MEM_B_DQ<46>

MEM_B_DQ<45>

MEM_B_DQ<44>

MEM_B_DQ<43>

MEM_B_DQ<42>

MEM_B_DQ<41>

MEM_B_DQ<40>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DQ<37>

MEM_B_DQ<36>

MEM_B_DQ<35>

MEM_B_DQ<34>

MEM_B_DQ<33>

MEM_B_DQ<32>

MEM_B_DQ<31>

MEM_B_DQ<30>

MEM_B_DQ<29>

MEM_B_DQ<28>

MEM_B_DQ<27>

MEM_B_DQ<26>

MEM_B_DQ<25>

MEM_B_DQ<24>

MEM_B_DQ<23>

MEM_B_DQ<22>

MEM_B_DQ<21>

MEM_B_DQ<20>

MEM_B_DQ<19>

MEM_B_DQ<18>

MEM_B_DQ<17>

MEM_B_DQ<16>

MEM_B_DQ<15>

MEM_B_DQ<14>

MEM_B_DQ<13>

MEM_B_DQ<12>

MEM_B_DQ<11>

MEM_B_DQ<10>

MEM_B_DQ<9>

MEM_B_DQ<8>

MEM_B_DQ<7>

MEM_B_DQ<6>

MEM_B_DQ<5>

MEM_B_DQ<4>

MEM_B_DQ<3>

MEM_B_DQ<2>

MEM_B_DQ<1>

MEM_B_DQ<0>

MEM_B_DM<7>

MEM_B_DM<6>

MEM_B_DM<5>

MEM_B_DM<4>

MEM_B_DM<3>

MEM_B_DM<2>

MEM_B_DM<1>

MEM_B_DM<0>

MCP Memory Interface

SYNC_DATE=04/04/2008

SYNC_MASTER=T18_MLB

27C4 74B3

27C2 74B3

27B4 74B3

27B5 74B3

27B7 74B3

27B5 74B3

27D4 74B3

27A7 74B3

27C2 74B3

27D4 74B3

27C4 74B3

27D2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27C2 74B3

27C4 74B3

27B4 74B3

27B2 74B3

27C4 74B3

27C2 74B3

27B2 74B3

27B4 74B3

27B5 74B3

27B7 74B3

27B5 74B3

27B7 74B3

27C5 74B3

27B5 74B3

27C7 74B3

27B7 74B3

27B5 74B3

27B7 74B3

27B5 74B3

27B7 74B3

BA16

AW16

BB13

AY15

AT2

AT1

AY2

AY1

BB6

BA6

BA10

AY11

BB33

BA33

BB37

BA37

BA43

AY42

AT42

AT43

AT5

BA2

AY7

BA11

BB34

BB38

AY43

AR42

AW42

AW41

AT40

AT4

AT3

AV2

AV3

AT41

AR4

AR3

AU2

AU3

AY4

AY3

BB3

BC3

AW4

AW3

AP41

BA3

BB2

BB5

BA5

BA8

BC8

BB4

BC4

BA7

AY8

AN40

BA9

BB10

BB12

AW12

BB8

BB9

AY12

BA12

BC32

AW32

AU40

BA35

AY36

BA32

BB32

BA34

AY35

BC36

AW36

BA39

AY40

AU41

BA36

BB36

BA38

AY39

BB40

AW40

AV42

AV41

BA40

BC40

AR41

AP42

BB14

BB16

BA42

BB42

BB22

BA22

BA19

AY19

AY31

BB30

BA15

BB29

BB18

BB17

BB28

AY28

BA28

AY27

BA27

BA26

BB26

BA25

BA29

BA14

AW28

BC28

BA17

BB25

BA18

U1400

(3 OF 11)

OMIT

MCP79-TOPO-B

BGA

27D7 74B3

27D5 74B3

27C5 74B3

27C7 74B3

27C7 74C3

27C5 74C3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27C7 74B3

27C5 74B3

27B5 74B3

27B7 74B3

27B5 74B3

27B7 74B3

27A5 74B3

27A7 74B3

27B5 74B3

27A7 74B3

27A5 74B3

27B5 74B3

27D2 74A3

27C2 74A3

27C4 74A3

27C2 74A3

27B7 74A3

27B2 74A3

27B7 74A3

27B5 74A3

27B7 74A3

27A5 74A3

26C2 74C3

26D2 74C3

26C4 74C3

26B2 74C3

26C2 74C3

26C4 74C3

26B7 74C3

26B5 74C3

26B7 74C3

26A5 74C3

26D7 74D3

26D5 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26C7 74D3

26C5 74D3

26D4 74D3

26C2 74D3

26D2 74D3

26C4 74D3

26C2 74D3

26C4 74D3

26C2 74D3

26C4 74D3

26C2 74D3

26C4 74D3

26B4 74D3

26C2 74D3

26B2 74D3

26C4 74D3

26B2 74D3

26B4 74D3

26C4 74D3

26C2 74D3

26C4 74D3

26C2 74D3

26C7 74D3

26B7 74D3

26B5 74D3

26C5 74D3

26B7 74D3

26B5 74D3

26B7 74D3

26B5 74D3

26B7 74D3

26B5 74D3

26B7 74D3

26B5 74D3

26B7 74D3

26B5 74D3

26A7 74D3

26B7 74D3

26A5 74D3

26D4 74D3

26C4 74D3

26C2 74C3

26B4 74C3

26C2 74C3

26B5 74C3

26B7 74C3

26A7 74C3

26B5 74C3

AR17

AV17

AP15

AV15

AL10

AL11

AR8

AR9

AW7

AW8

AP13

AR13

AV25

AW25

AU30

AU29

AT35

AU35

AU39

AT39

AN5

AU5

AR10

AN13

AN27

AW29

AV35

AR34

AT37

AU37

AW39

AL8

AL9

AP9

AN9

AV39

AL6

AL7

AN6

AN7

AR6

AR7

AV6

AW5

AN10

AR5

AR37

AU6

AV5

AU7

AU8

AW9

AP11

AW6

AY5

AU9

AV9

AR38

AU11

AV11

AV13

AW13

AR11

AT11

AR14

AU13

AR26

AU25

AV38

AT27

AU27

AP25

AR25

AP27

AR27

AP29

AR29

AP31

AR31

AW38

AV27

AN29

AV29

AN31

AU31

AR33

AV37

AW37

AT31

AV31

AR35

AP35

AT15

AR18

AW33

AV33

BA24

AY24

BB20

BC20

AU23

AT23

AP17

AP23

AP19

AW17

AV21

AR22

AU21

AP21

AR21

AN21

AV19

AU19

AR23

AU15

AN23

AW21

AN19

AT19

AR19

U1400

(2 OF 11)

OMIT

MCP79-TOPO-B

BGA

MCLK1B_2_P

MCLK1B_1_N

MCLK1B_0_P

MCLK1B_1_P

MCLK1B_2_N

MCS1B_1#

MCS1B_0#

MCLK1B_0_N

MODT1B_0

MCKE1B_1

MCKE1B_0

MODT1B_1

MRESET0#

GND55

GND56

GND57

GND58

GND60

GND59

GND61

GND62

GND63

GND64

GND52

GND53

GND54

GND51

GND49

GND50

GND48

GND47

GND46

GND44

GND45

GND43

GND42

GND41

GND39

GND40

GND38

GND37

GND36

GND35

GND33

GND34

GND32

GND31

GND30

GND28

GND29

GND27

GND26

GND25

GND24

GND18

GND19

GND17

GND16

GND15

GND13

GND14

GND10

GND12

GND11

GND8

GND9

GND7

GND6

GND5

GND2

GND3

GND4

GND1

MEM_COMP_VDD

MEM_COMP_GND

MODT0B_0

MODT0B_1

MCKE0B_1

MCKE0B_0

MCLK0B_0_N

MCS0B_0#

MCS0B_1#

MCLK0B_2_N

MCLK0B_1_P

MCLK0B_0_P

MCLK0B_1_N

MCLK0B_2_P

+V_PLL_XREF_XS

+V_PLL_CORE

+V_VPLL

+VDD_MEM1

+VDD_MEM2

+VDD_MEM3

+VDD_MEM4

+VDD_MEM5

+VDD_MEM6

+VDD_MEM7

+VDD_MEM8

+VDD_MEM9

+VDD_MEM10

+VDD_MEM11

+VDD_MEM14

+VDD_MEM15

+VDD_MEM16

+VDD_MEM17

+VDD_MEM18

+VDD_MEM19

+VDD_MEM20

+VDD_MEM22

+VDD_MEM21

+VDD_MEM23

+VDD_MEM24

+VDD_MEM25

+VDD_MEM26

+VDD_MEM30

+VDD_MEM27

+VDD_MEM29

+VDD_MEM31

+VDD_MEM32

+VDD_MEM33

+VDD_MEM34

+VDD_MEM38

+VDD_MEM39

+VDD_MEM40

+VDD_MEM41

+VDD_MEM43

+VDD_MEM44

+VDD_MEM45

+VDD_MEM42

+V_PLL_DP

+VDD_MEM13

+VDD_MEM12

+VDD_MEM28

+VDD_MEM37

+VDD_MEM36

+VDD_MEM35

GND21

GND20

GND22

GND23

MEMORY CONTROL 0B

MEMORY CONTROL 1B

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

4771 mA (A01, DDR3)

17 mA

12 mA

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

19 mA

TP or NC for DDR2.

39 mA

87 mA (A01)

16 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

MCP_MEM_COMP_VDD

=PP1V8R1V5_S0_MCP_MEM

TP_MEM_B_ODT<3>

TP_MEM_B_ODT<2>

TP_MEM_B_CS_L<3>

TP_MEM_B_CLK3N

TP_MEM_B_CLK3P

TP_MEM_B_CLK4N

TP_MEM_B_CLK4P

TP_MEM_B_CLK5N

TP_MEM_B_CLK5P

PP1V05_S0_MCP_PLL_CORE

TP_MEM_A_CS_L<3>

TP_MEM_A_CS_L<2>

TP_MEM_A_CLK3N

TP_MEM_A_CLK4P

TP_MEM_A_CLK5N

TP_MEM_A_CLK5P

TP_MEM_A_CKE<3>

TP_MEM_A_CKE<2>

TP_MEM_A_ODT<3>

TP_MEM_A_ODT<2>

TP_MEM_A_CLK3P

TP_MEM_A_CLK4N

MCP_MEM_COMP_GND

=PP1V8R1V5_S0_MCP_MEM

MCP_MEM_RESET_L

TP_MEM_B_CS_L<2>

TP_MEM_B_CKE<2>

TP_MEM_B_CKE<3>

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

MCP Memory Misc

28C6

BC29

AN16

AM29

AM27

AM25

AM31

AL30

BC25

AW24

AW19

AY26

AM23

AY25

AU18

AM15

AY18

AY17

AV20

BC17

AW27

AU22

AU20

AM21

AV24

AY29

AT21

AU24

AN18

AU16

AP18

AP22

AW15

AR24

AM19

AR20

AR16

AV16

AP24

AP20

AN22

AP16

AT17

AN24

AN20

AM17

T28

T27

U28

U27

AY32

BC13

AY16

AN15

AN17

AN41

AM41

BA13

BC16

AR15

AU17

BA41

BB41

AY23

BA23

BA20

AY20

AU33

AU34

BB24

BC24

BA21

BB21

BA31

BA30

AN25

AV23

W5

V34

V10

U22

U20

U18

T9

T7

T6

T38

T37

T35

T34

T33

T26

T24

AK11

T20

T18

T10

R5

R43

R40

R36

P7

P40

P4

P37

P34

P33

P10

N8

N39

M9

M7

M6

M5

M38

K7

H31

G32

G30

F24

D34

BC9

AY9

BC21

F28

AU10

AR36

AP30

AT25

AP12

AM28

AK7

AH35

AG24

AF24

AE20

AD22

AB7

AB22

AA39

AA22

U1400

BGA

OMIT

MCP79-TOPO-B

(4 OF 11)

2

1

R1611

40.2

1/16W

1%

402

MF-LF

2

1

R1610

MF-LF

402

1/16W

40.2

1%

74A3

7B6 15C3 22C8

22B2

74A3

7B6 15C7 22C8

PE0_RX0_P

PE0_RX2_N

+AVDD0_PEX11

+AVDD0_PEX7

+AVDD0_PEX8

+AVDD1_PEX3

+AVDD1_PEX2

+AVDD1_PEX1

+AVDD0_PEX13

+AVDD0_PEX12

+AVDD0_PEX10

+AVDD0_PEX9

+AVDD0_PEX6

+AVDD0_PEX5

+AVDD0_PEX4

+AVDD0_PEX3

+AVDD0_PEX2

+AVDD0_PEX1

+V_PLL_PEX

+DVDD1_PEX2

+DVDD1_PEX1

+DVDD0_PEX8

+DVDD0_PEX7

+DVDD0_PEX6

+DVDD0_PEX5

+DVDD0_PEX4

+DVDD0_PEX3

+DVDD0_PEX2

+DVDD0_PEX1

PE0_RX0_N

PE0_RX2_P

PE0_RX4_P

PE0_RX6_P

PEB_PRSNT#

PE1_TX3_N

PE1_TX3_P

PE1_TX2_N

PE1_TX1_N

PE1_TX2_P

PE1_TX0_N

PE1_TX1_P

PE6_REFCLK_N

PEX_RST0#

PE1_TX0_P

PE5_REFCLK_N

PE5_REFCLK_P

PE6_REFCLK_P

PE4_REFCLK_N

PE4_REFCLK_P

PE3_REFCLK_N

PE2_REFCLK_N

PE1_REFCLK_N

PE2_REFCLK_P

PE0_REFCLK_N

PE0_REFCLK_P

PE1_REFCLK_P

PE0_TX15_N

PE0_TX14_N

PE0_TX15_P

PE0_TX13_N

PE0_TX14_P

PE0_TX12_N

PE0_TX12_P

PE0_TX13_P

PE0_TX11_N

PE0_TX11_P

PE0_TX10_N

PE0_TX9_N

PE0_TX10_P

PE0_TX8_N

PE0_TX8_P

PE0_TX9_P

PE0_TX7_N

PE0_TX7_P

PE0_TX6_N

PE0_TX5_N

PE0_TX6_P

PE0_TX4_N

PE0_TX5_P

PE0_TX3_N

PE0_TX3_P

PE0_TX4_P

PE0_TX2_N

PE0_TX2_P

PE0_TX0_N

PE0_TX1_N

PE0_TX1_P

PE0_TX0_P

PEX_CLK_COMP

PE1_RX3_N

PE1_RX3_P

PE1_RX2_N

PE1_RX0_N

PE1_RX1_P

PE1_RX2_P

PE1_RX1_N

PE_WAKE#

PE1_RX0_P

PE0_PRSNT_16#

PE0_RX13_N

PE0_RX14_P

PE0_RX15_P

PE0_RX14_N

PE0_RX15_N

PE0_RX12_P

PE0_RX11_P

PE0_RX13_P

PE0_RX11_N

PE0_RX12_N

PE0_RX10_N

PE0_RX8_P

PE0_RX9_P

PE0_RX10_P

PE0_RX8_N

PE0_RX9_N

PE0_RX5_N

PE0_RX7_P

PE0_RX6_N

PE0_RX7_N

PE0_RX3_P

PE0_RX5_P

PE0_RX3_N

PE0_RX4_N

PE0_RX1_P

PE0_RX1_N

PEC_PRSNT#

PEC_CLKREQ#/GPIO_50

PE3_REFCLK_P

PED_CLKREQ#/GPIO_51

PED_PRSNT#

PEB_CLKREQ#/GPIO_49

PEE_CLKREQ#/GPIO_16

PEE_PRSNT#/GPIO_46

PEF_CLKREQ#/GPIO_17

PEF_PRSNT#/GPIO_47

PEG_CLKREQ#/GPIO_18

PEG_PRSNT#/GPIO_48

PCI EXPRESS

OUT

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Int PU (S5)

If PE1 interface is not used, ground DVDD1_PEX and AVDD1_PEX.

If PE0 interface is not used, ground DVDD0_PEX and AVDD0_PEX.

206 mA (A01, AVDD0 & 1)

Int PU

84 mA (A01)

Int PU

57 mA (A01, DVDD0 & 1)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

17 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PEG_R2D_C_P<11>

=PEG_R2D_C_N<11>

=PEG_R2D_C_N<9>

=PEG_R2D_C_P<8>

=PEG_R2D_C_P<13>

PCIE_EXCARD_PRSNT_L

MINI_CLKREQ_L

=PP1V05_S0_MCP_PEX_AVDD1

=PP1V05_S0_MCP_PEX_AVDD0

=PP1V05_S0_MCP_PEX_DVDD1

=PEG_D2R_P<0>

=PEG_D2R_N<2>

PP1V05_S0_MCP_PLL_PEX

=PEG_D2R_N<0>

=PEG_D2R_P<2>

=PEG_D2R_P<4>

=PEG_D2R_P<6>

TP_PCIE_PE4_R2D_CN

TP_PCIE_PE4_R2D_CP

PCIE_EXCARD_R2D_C_N

PCIE_FW_R2D_C_N

PCIE_EXCARD_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_FW_R2D_C_P

TP_PCIE_CLK100M_PE6N

PCIE_RESET_L

PCIE_MINI_R2D_C_P

TP_PCIE_CLK100M_PE5N

TP_PCIE_CLK100M_PE5P

TP_PCIE_CLK100M_PE6P

TP_PCIE_CLK100M_PE4N

TP_PCIE_CLK100M_PE4P

PCIE_CLK100M_EXCARD_N

PCIE_CLK100M_FW_N

PCIE_CLK100M_MINI_N

PCIE_CLK100M_FW_P

PEG_CLK100M_N

PEG_CLK100M_P

PCIE_CLK100M_MINI_P

=PEG_R2D_C_N<15>

=PEG_R2D_C_N<14>

=PEG_R2D_C_P<15>

=PEG_R2D_C_N<13>

=PEG_R2D_C_P<14>

=PEG_R2D_C_N<12>

=PEG_R2D_C_P<12>

=PEG_R2D_C_N<10>

=PEG_R2D_C_P<10>

=PEG_R2D_C_N<8>

=PEG_R2D_C_P<9>

=PEG_R2D_C_N<7>

=PEG_R2D_C_P<7>

=PEG_R2D_C_N<6>

=PEG_R2D_C_N<5>

=PEG_R2D_C_P<6>

=PEG_R2D_C_N<4>

=PEG_R2D_C_P<5>

=PEG_R2D_C_N<3>

=PEG_R2D_C_P<3>

=PEG_R2D_C_P<4>

=PEG_R2D_C_N<2>

=PEG_R2D_C_P<2>

=PEG_R2D_C_N<0>

=PEG_R2D_C_N<1>

=PEG_R2D_C_P<1>

=PEG_R2D_C_P<0>

MCP_PEX_CLK_COMP

PEG_PRSNT_L

=PEG_D2R_N<13>

=PEG_D2R_P<14>

=PEG_D2R_P<15>

=PEG_D2R_N<14>

=PEG_D2R_N<15>

=PEG_D2R_P<12>

=PEG_D2R_P<11>

=PEG_D2R_P<13>

=PEG_D2R_N<11>

=PEG_D2R_N<12>

=PEG_D2R_N<10>

=PEG_D2R_P<8>

=PEG_D2R_P<9>

=PEG_D2R_P<10>

=PEG_D2R_N<8>

=PEG_D2R_N<9>

=PEG_D2R_N<5>

=PEG_D2R_P<7>

=PEG_D2R_N<6>

=PEG_D2R_N<7>

=PEG_D2R_P<3>

=PEG_D2R_P<5>

=PEG_D2R_N<3>

=PEG_D2R_N<4>

=PEG_D2R_P<1>

=PEG_D2R_N<1>

PCIE_CLK100M_EXCARD_P

EXCARD_CLKREQ_L

AUD_IP_PERIPHERAL_DET

GMUX_JTAG_TCK_L

=PP1V05_S0_MCP_PEX_DVDD0

PCIE_EXCARD_D2R_N

PCIE_EXCARD_D2R_P

TP_PCIE_PE4_D2RN

TP_PCIE_PE4_D2RP

PCIE_FW_D2R_N

PCIE_FW_D2R_P

PCIE_MINI_D2R_N

PCIE_MINI_D2R_P

PCIE_WAKE_L

GMUX_JTAG_TDO

CARDREADER_RESET

PCIE_FW_PRSNT_L

TP_PE4_PRSNT_L

TP_PE4_CLKREQ_L

FW_CLKREQ_L

PCIE_MINI_PRSNT_L

SYNC_DATE=04/04/2008

MCP PCIe Interfaces

SYNC_MASTER=T18_MLB

30B7

8C4

24C4

2

1

R1710

PLACEMENT_NOTE=Place within 12.7mm of U1400

NO STUFF

1/16W

1%

MF-LF

402

2.37K

8D6

29C5 75D3

8C6

8D6

34C2

34C1 75D3

29C5 75D3

8D6

29D7

8D6

34C1 75D3

6D5 29C7

35D3

8C6 35D3

6D5 29C7 75D3

8D6

K11

A11

M19

M17

M18

M16

L16

B10

M15

C10

E8

D9

D5

F17

N14

M14

L14

K14

J13

H13

G13

F13

J11

J10

B6

C6

A7

B7

B8

A8

D8

C8

H7

G7

F9

E9

H9

G9

K9

J9

G11

F11

H3

H2

G3

H4

F3

F4

E2

F2

D2

E1

C1

D1

B3

B2

A4

A3

C4

B4

M2

M1

M4

M3

L4

L3

K2

K3

J2

J3

H1

J1

C5

D4

L11

L10

J5

J4

J7

J6

G5

H5

C3

D3

E4

E3

E5

F5

E6

F6

D7

C7

N5

N4

N7

N6

N9

P9

N11

N10

L7

L6

L9

L8

F7

E7

E11

D11

C9

T16

U19

T19

U16

W18

W17

W16

V19

U17

W19

T17

P13

N13

M13

U12

T12

R12

P12

M12

AB12

AA12

W12

V12

AD12

AC12

Y12

U1400

BGA

OMIT

(5 OF 11)

MCP79-TOPO-B

N12

L18

7A6

22C2

75C3

57A4

7A6

IN

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

GPIO_7/NFERR*/IGPU_GPIO_7

+V_DUAL_MACPLL

+VDD_HDMI

+V_PLL_HDMI

+V_PLL_IFPAB

+VDD_IFPB

+VDD_IFPA

+V_TV_DAC

+V_RGB_DAC

+V_DUAL_RMGT2

MII_COMP_GND

MII_COMP_VDD

LCD_PANEL_PWR/GPIO_58

LCD_BKL_ON/GPIO_59

LCD_BKL_CTL/GPIO_57

XTALOUT_TV

GPIO_6/FERR*/IGPU_GPIO_6

HDMI_TXC_P/ML0_LANE3_P

HDMI_TXC_N/ML0_LANE3_N

HDMI_TXD0_P/ML0_LANE2_P

HDMI_TXD0_N/ML0_LANE2_N

HDMI_TXD1_P/ML0_LANE1_P

HDMI_TXD1_N/ML0_LANE1_N

HDMI_TXD2_P/ML0_LANE0_P

HDMI_TXD2_N/ML0_LANE0_N

HPLUG_DET2/GPIO_22

IFPA_TXC_N

XTALIN_TV

DDC_DATA2/GPIO_24

DDC_CLK2/GPIO_23

RGB_DAC_RSET

RGB_DAC_VREF

TV_DAC_VREF

DP_AUX_CH0_P

DP_AUX_CH0_N

HPLUG_DET3

HDMI_RSET

HDMI_VPROBE

RGMII_MDIO

BUF_25MHZ

DDC_DATA0

DDC_CLK0

RGB_DAC_RED

RGB_DAC_GREEN

RGB_DAC_BLUE

RGB_DAC_HSYNC

RGB_DAC_VSYNC

TV_DAC_RED

TV_DAC_GREEN

IFPA_TXC_P

IFPA_TXD0_P

IFPA_TXD0_N

IFPA_TXD2_P

IFPA_TXD1_P

IFPA_TXD1_N

IFPA_TXD3_P

IFPA_TXD2_N

IFPB_TXC_P

IFPB_TXC_N

IFPB_TXD5_P

IFPB_TXD4_P

IFPB_TXD4_N

IFPB_TXD6_P

IFPB_TXD5_N

IFPB_TXD6_N

IFPB_TXD7_P

IFPB_TXD7_N

DDC_DATA3

DDC_CLK3

IFPAB_RSET

IFPAB_VPROBE

TV_DAC_RSET

RGMII_RXD0

RGMII_INTR/GPIO_35

RGMII_RXD3

RGMII_RXCTL/MII_RXDV

RGMII_RXC/MII_RXCLK

RGMII_RXD2

RGMII_RXD1

MII_RESET#

RGMII_MDC

RGMII_PWRDWN/GPIO_37

MII_RXER/GPIO_36

MII_COL/GPIO_20/MSMB_DATA

MII_CRS/GPIO_21/MSMB_CLK

TV_DAC_BLUE

TV_DAC_HSYNC/GPIO_44

TV_DAC_VSYNC/GPIO_45

+V_DUAL_RMGT1

MII_VREF

RGMII_TXCTL/MII_TXEN

RGMII_TXC/MII_TXCLK

RGMII_TXD3

RGMII_TXD2

RGMII_TXD1

RGMII_TXD0

+3.3V_DUAL_RMGT1

+3.3V_DUAL_RMGT2

IFPA_TXD3_N

LAN

DACS

FLAT PANEL

BI

OUT

BI

OUT

BI

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

In MCP79 these pins have undocumented internal

GPIOs 57-59 (if LCD panel is used):

by default, pull-downs (1K or stronger) must be used.

pull-ups (~10K to 3.3V S0). To ensure pins are low

Alias to GMUX_INT for systems with GMUX.

Alias to HPLUG_DET2 for other systems.

Pull-down (20k) required in all cases.

=DVI_HPD_GMUX_INT:

Alias to DVI_HPD for systems using IFP for DVI.

(See below)

NOTE: 1K pull-down required on DP_IG_AUX_CH_N if DP is used.

NOTE: 20K pull-down required on DP_HPD_DET.

level-shifters.

NOTE: HDMI port requires level-shifting. IFP interface can

be used to provide HDMI or dual-channel TMDS without

Interface Mode

DP_IG_ML_P/N<0>

DP_IG_DDC_DATA

DP_IG_HPD

DP_IG_AUX_CH_P/N

NOTE: 1M pull-down required on DP_IG_CA_DET if DP not used.

Dual-channel TMDS: Power +VDD_IFPx at 3.3V

131 mA (A01)

83 mA (A01)

MII, RGMII products will enable

WF: IFP is capable of LVDS (1.8V) or TMDS (3.3V), need aliases

RGB DAC Disable:

TV / Component

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

LVDS: Power +VDD_IFPx at 1.8V

95 mA (A01)

16 mA (A01)

8 mA

DP_IG_AUX_CH_P/N

=MCP_HDMI_HPD

TMDS_IG_HPD

=MCP_HDMI_DDC_DATA

=MCP_HDMI_TXD_P/N<2>

=MCP_HDMI_TXD_P/N<1>

=MCP_HDMI_DDC_CLK

MCP Signal

=MCP_HDMI_TXD_P/N<0>

=MCP_HDMI_TXC_P/N

TMDS/HDMI

TMDS_IG_TXC_P/N

TMDS_IG_TXD_P/N<0>

TMDS_IG_DDC_CLK

TMDS_IG_TXD_P/N<1>

TMDS_IG_TXD_P/N<2>

TMDS_IG_DDC_DATA

TP_DP_IG_AUX_CHP/N

DP_IG_DDC_CLK

DP_IG_ML_P/N<2>

DP_IG_ML_P/N<1>

DP_IG_ML_P/N<3>

DisplayPort

5 mA (A01)

RGB ONLY

avoids a leakage issue since

feature via software. This

NOTE: All Apple products set strap to

Network Interface Select

Interface

RGMII

MII 0

1

ENET_TXD<0>

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float all TV_DAC signals.

TV DAC Disable:

Y / Y

DDC_CLK0/DDC_DATA0 pull-ups still required.

Okay to float all RGB_DAC signals.

Okay to float XTALIN_TV and XTALOUT_TV.

103 mA

206 mA (A01)

Comp / Pb

MCP79 requires a S5 pull-up.

C / Pr

190 mA (A01, 1.8V)

18 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=MCP_HDMI_TXD_N<0>

=MCP_HDMI_TXC_N

=MCP_HDMI_TXD_P<0>

=MCP_HDMI_TXD_P<1>

=MCP_HDMI_TXD_N<1>

=MCP_HDMI_TXD_P<2>

LVDS_IG_A_CLK_N

LVDS_IG_A_DATA_N<3>

MCP_HDMI_RSET

MCP_HDMI_VPROBE

DP_IG_CA_DET

PP1V05_ENET_MCP_PLL_MAC

=PP1V05_S0_MCP_HDMI_VDD

PP3V3_S0_MCP_VPLL

=PP3V3R1V8_S0_MCP_IFP_VDD

PP3V3_S0_MCP_DAC

MCP_MII_COMP_GND

MCP_MII_COMP_VDD

LVDS_IG_PANEL_PWR

LVDS_IG_BKL_ON

=MCP_HDMI_TXC_P

=MCP_HDMI_TXD_N<2>

MCP_CLK27M_XTALIN

LVDS_IG_DDC_DATA

LVDS_IG_DDC_CLK

MCP_TV_DAC_VREF

DP_IG_AUX_CH_P

DP_IG_AUX_CH_N

=MCP_HDMI_HPD

ENET_MDIO

MCP_CLK25M_BUF0_R

MCP_DDC_DATA0

MCP_DDC_CLK0

TP_MCP_RGB_RED

TP_MCP_RGB_GREEN

TP_MCP_RGB_BLUE

TP_MCP_RGB_HSYNC

TP_MCP_RGB_VSYNC

CRT_IG_R_C_PR

CRT_IG_G_Y_Y

LVDS_IG_A_CLK_P

LVDS_IG_A_DATA_P<0>

LVDS_IG_A_DATA_N<0>

LVDS_IG_A_DATA_P<2>

LVDS_IG_A_DATA_P<1>

LVDS_IG_A_DATA_N<1>

LVDS_IG_A_DATA_P<3>

LVDS_IG_A_DATA_N<2>

LVDS_IG_B_CLK_P

LVDS_IG_B_CLK_N

LVDS_IG_B_DATA_P<1>

LVDS_IG_B_DATA_P<0>

LVDS_IG_B_DATA_N<0>

LVDS_IG_B_DATA_P<2>

LVDS_IG_B_DATA_N<1>

LVDS_IG_B_DATA_N<2>

LVDS_IG_B_DATA_P<3>

LVDS_IG_B_DATA_N<3>

=MCP_HDMI_DDC_DATA

=MCP_HDMI_DDC_CLK

MCP_IFPAB_RSET

MCP_IFPAB_VPROBE

MCP_TV_DAC_RSET

ENET_RXD<0>

TP_ENET_INTR_L

ENET_RXD<3>

ENET_RX_CTRL

ENET_CLK125M_RXCLK

ENET_RXD<2>

ENET_RXD<1>

ENET_RESET_L

ENET_MDC

TP_ENET_PWRDWN_L

=MCP_MII_RXER

=MCP_MII_COL

=MCP_MII_CRS

CRT_IG_B_COMP_PB

CRT_IG_HSYNC

CRT_IG_VSYNC

MCP_MII_VREF

ENET_TX_CTRL

ENET_CLK125M_TXCLK

ENET_TXD<3>

ENET_TXD<2>

ENET_TXD<1>

ENET_TXD<0>

=PP3V3_ENET_MCP_RMGT

=PP3V3_S0_MCP_GPIO

=PP3V3_ENET_MCP_RMGT

=PP3V3_S5_MCP_GPIO

=PP1V05_ENET_MCP_RMGT

LPCPLUS_GPIO

TP_MCP_RGB_DAC_VREF

TP_MCP_RGB_DAC_RSET

MCP_CLK27M_XTALOUT

LVDS_IG_BKL_PWM

=DVI_HPD_GMUX_INT

MCP Ethernet & Graphics

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

31B6 77D3

31B6 77C3

31C8 77D3

23C6 75B3

31C6 77D3

23C6 75B3

69D3

6C7 68C5

8C4

31C6 77D3

8C4

8D4

6C7 68C2 75B3

31C6 77D3

6C7 68C2 75B3

68B3 75B3

31C6 77D3

2

1

R1820

1/16W

MF-LF

402

47K

5%

42C3

2

1

R1860

100K

1/16W

5%

MF-LF

402

2

1

R1861

MF-LF

1/16W

100K

5%

402

2

1

R1850

MF-LF

5%

1/16W

402

10K

D38

C38

C37

A35

E36

A36

D36

B36

C36

D25

C25

C24

B24

C26

D24

A24

E24

B23

C23

C22

A23

G23

C21

D21

J22

A41

B38

C39

B39

A40

A39

B40

M26

M27

T25

K32

J32

M28

M29

V23

U23

T23

K24

J24

E28

F23

J23

B22

C27

B27

B26

F40

E37

G39

N30

M30

L30

K30

L29

K29

J29

H29

L31

K31

G31

E32

B34

C34

D33

C33

D32

C32

B32

A32

B35

C35

F31

C31

J30

J33

H33

F33

G33

G35

F35

D35

E35

J31

B15

E16

D43

C43

E31

B30

A31

D31

C30

B31

E23

U1400

OMIT

MCP79-TOPO-B

BGA

(6 OF 11)

8C4

8D4

69A5

2

1

R1811

1%

402

49.9

MF-LF

1/16W

2

1

R1810

49.9

402

MF-LF

1/16W

1%

8D4

23C7 75B3

69D3

8B4

69C7 75B3

69D3

72B7 72C8

68C8

71A7 72B7

8D4

31B7 77C3

31B1 77D3

31C1 77D3

32A5 77D3

31B6 77D3

22A4

22A6

7D7 23D7

23C5

7B6 23D7

23D2

77D3

7B5 17D7 22A5 22B6

7C5 18D1 20A4

7B5 17D3 22A5 22B6

7A3 19C1

7A5 22D6

OUT

BI

LPC PCIGND

PCI_INTW#

PCI_INTX#

PCI_INTY#

PCI_INTZ#

GND65

LPC_DRQ1#/GPIO_19

LPC_PWRDWN#/GPIO_54/EXT_NMI#

PCI_TRDY#

LPC_DRQ0#

LPC_SERIRQ

PCI_AD4

PCI_AD0

PCI_AD3

PCI_AD2

PCI_AD1

PCI_AD5

PCI_AD6

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD10

PCI_AD11

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD15

PCI_AD16

PCI_AD17

PCI_AD20

PCI_AD19

PCI_AD18

PCI_AD21

PCI_AD22

PCI_AD25

PCI_AD23

PCI_AD26

PCI_AD29

PCI_AD31

GND66

GND67

GND69

GND68

GND70

GND71

GND72

GND74

GND73

GND75

GND76

GND77

GND79

GND78

GND80

GND81

GND84

GND83

GND82

GND85

GND86

GND87

GND89

GND88

GND90

GND91

GND92

GND94

GND93

GND95

GND96

GND97

PCI_GNT0#

PCI_CBE2#

PCI_CBE0#

PCI_CBE3#

PCI_IRDY#

PCI_FRAME#

PCI_DEVSEL#

PCI_PAR

PCI_SERR#

PCI_STOP#

PCI_RESET0#

PCI_RESET1#

PCI_CLK2

PCI_CLK1

PCI_CLK0

PCI_CLKIN

LPC_FRAME#

LPC_AD1

LPC_AD0

LPC_RESET0#

LPC_CLK0

LPC_AD3

LPC_AD2

GND99

GND98

GND100

GND102

GND101

GND104

GND103

GND105

GND106

GND107

GND109

GND108

GND110

GND111

GND112

GND115

GND114

GND113

GND116

GND117

GND120

GND119

GND118

GND121

GND122

GND123

GND125

GND124

GND126

GND127

GND128

GND130

GND129

PCI_AD30

PCI_AD27

PCI_AD24

PCI_CLKRUN#/GPIO_42

PCI_AD28

PCI_GNT2#/GPIO_41/RS232_DTR#

PCI_GNT3#/GPIO_39/RS232_RTS#

PCI_GNT4#/GPIO_53/RS232_SOUT#

PCI_GNT1#/FANCTL2

PCI_CBE1#

PCI_PERR#/GPIO_43/RS232_DCD#

PCI_REQ3#/GPIO_38/RS232_CTS#

PCI_REQ4#/GPIO_52/RS232_SIN#

PCI_PME#/GPIO_30

PCI_REQ2#/GPIO_40/RS232_DSR#

PCI_REQ0#

PCI_REQ1#/FANRPM2

IN

BI

OUT

IN

OUT

BI

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Strap for Boot ROM Selection (See HDA_SDOUT)

Int PU

Int PU (S5)

19 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TP_PCI_AD<14>

TP_PCI_AD<21>

TP_PCI_INTX_L

TP_PCI_TRDY_L

LPC_SERIRQ

TP_PCI_AD<20>

TP_PCI_AD<15>

TP_PCI_AD<9>

MCP_DEBUG<5>

MCP_DEBUG<4>

TP_PCI_AD<23>

TP_PCI_AD<24>

TP_PCI_AD<26>

PM_LATRIGGER_L

TP_PCI_AD<11>

TP_PCI_AD<13>

GMUX_JTAG_TDI

GMUX_JTAG_TMS

TP_PCI_INTZ_L

FW_PME_L

TP_LPC_DRQ0_L

PM_CLKRUN_L

=PP3V3_S0_MCP_GPIO

MCP_RS232_SIN_L

MCP_DEBUG<7>

MCP_DEBUG<6>

MCP_DEBUG<3>

MCP_DEBUG<2>

MCP_DEBUG<1>

MCP_DEBUG<0>

MCP_RS232_SIN_L

AUD_IPHS_SWITCH_EN

FW_PWR_EN

TP_PCI_AD<12>

TP_PCI_AD<16>

TP_PCI_AD<17>

TP_PCI_AD<18>

TP_PCI_AD<19>

TP_PCI_AD<22>

TP_PCI_AD<25>

TP_PCI_AD<27>

TP_PCI_AD<28>

TP_PCI_AD<29>

TP_PCI_AD<30>

TP_PCI_AD<31>

TP_PCI_INTW_L

TP_PCI_INTY_L

PCI_REQ0_L

PCI_REQ1_L

TP_PCI_AD<8>

TP_PCI_AD<10>

TP_PCI_PERR_L

MEM_VTT_EN_R

PCI_CLK33M_MCP

TP_PCI_CLK1

PCI_CLK33M_MCP_R

LPC_PWRDWN_L

LPC_RESET_L

LPC_FRAME_R_L

LPC_CLK33M_SMC_R

LPC_AD_R<3>

LPC_AD_R<2>

LPC_AD_R<1>

LPC_AD_R<0>

TP_PCI_CLK0

TP_PCI_RESET1_L

TP_PCI_STOP_L

TP_PCI_SERR_L

TP_PCI_PAR

TP_PCI_IRDY_L

TP_PCI_FRAME_L

TP_PCI_DEVSEL_L

TP_PCI_C_BE_L<3>

TP_PCI_C_BE_L<2>

TP_PCI_C_BE_L<1>

TP_PCI_C_BE_L<0>

MCP_RS232_SOUT_L

TP_PCI_GNT1_L

TP_PCI_GNT0_L

LPC_AD<0>

LPC_FRAME_L

LPC_AD<2>

LPC_AD<3>

LPC_AD<1>

MCP_RS232_SOUT_L

PCI_REQ0_L

PCI_REQ1_L

FW_PWR_EN

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

MCP PCI & LPC

8C4

57D3

12C3 76D3

12C6

18D2 35A4 35C4 35C7 35D6

18D2

8C2

24C4

21

R1953

22

5%

1/16W MF-LF

402

21

R1952

402

MF-LF1/16W

5%

22

21

R1951

402

22

MF-LF1/16W

5%

21

R1950

402

22

MF-LF1/16W

5%

21

R1960

5%

22

402

MF-LF1/16W

2

1

R1961

10K

5%

1/16W

402

MF-LF

18D2

21

R1992

402

MF-LF1/16W

5%

8.2K

21

R1994

8.2K

5%

1/16W MF-LF

402

21

R1990

8.2K

5%

1/16W MF-LF

402

21

R1991

8.2K

5%

1/16W MF-LF

402

21

R1989

8.2K

5%

1/16W MF-LF

402

2

1

R1910

22

5%

1/16W

402

MF-LF

PLACEMENT_NOTE=Place close to pin R8

40C5 42D3

24B4 76C3 40C8 42D3

40C5 42D5

Y3

Y2

AA7

R11

R10

T4

U9

T3

V9

T2

T1

AB9

Y1

AA10

N1

N2

N3

P2

P3

U11

R4

U10

R3

Y4

AA9

AD11

R9

R8

R7

R6

W10

AA11

AA6

AA3

AA2

AC8

AC7

AB2

AC6

AB3

U7

T5

AE11

U6

U1

U5

U2

W11

U3

W9

V2

W8

V3

AC4

W7

W4

W6

W3

Y5

AA5

AA1

AC11

AC10

AC9

AE10

AC3

AE6

AE5

AE12

AD4

AE2

AE1

AE9

AD5

AD1

AD2

AD3

Y27

Y26

Y25

Y24

Y22

Y20

Y19

Y18

Y17

Y16

W43

W40

W36

W24

W22

W20

V7

V40

V4

V37

V33

V28

V27

V26

V24

V22

V20

V18

V17

V16

U8

U4

U39

U26

U24

AD34

AD33

AD28

AD27

AD26

AD25

AD24

AD20

AD19

AD18

AD17

AD16

AC5

AB33

AC40

AC36

AC22

AB40

AB4

AB37

AB34

AB28

AB27

AB26

AB25

AB24

AB23

AB21

AB20

H34

AB18

U1400

OMIT

MCP79-TOPO-B

(7 OF 11)

BGA

40C8 42D3 76C3

40C8 42D5 76C3

24D4 76C3

40C8 42D5 76C3

7C5 17C1 20A4

18D7

18D2 76D3

76C3

18D4

18D7 76D3

18D7 35A4 35C4 35C7 35D6

BI

IN

SATA_B0_RX_N

SATA_A0_RX_P

SATA_A1_TX_P

GND160

GND158

GND159

GND157

GND156

GND155

GND153

GND154

GND152

GND151

GND150

GND148

GND149

GND147

GND146

GND145

GND143

GND144

GND142

GND141

GND140

GND139

GND136

GND133

GND134

GND132

GND131

USB_RBIAS_GND

USB11_N

USB11_P

USB10_N

USB10_P

USB9_N

USB9_P

USB7_N

USB8_N

USB8_P

USB7_P

USB6_N

USB6_P

USB5_N

USB4_N

USB4_P

USB5_P

USB2_N

USB2_P

USB0_N

USB1_N

USB1_P

USB0_P

SATA_TERMP

SATA_LED#

SATA_C1_RX_N

SATA_C1_RX_P

SATA_C0_TX_P

SATA_B1_RX_N

SATA_B1_RX_P

SATA_B1_TX_N

SATA_B1_TX_P

SATA_B0_TX_N

SATA_B0_RX_P

SATA_B0_TX_P

SATA_A1_RX_N

SATA_A1_RX_P

SATA_A1_TX_N

SATA_A0_TX_P

GND138

GND137

GND135

USB3_P

USB3_N

USB_OC0#/GPIO_25

USB_OC1#/GPIO_26

USB_OC2#/GPIO_27/MGPIO

USB_OC3#/GPIO_28/MGPIO

SATA_A0_RX_N

SATA_A0_TX_N

SATA_C1_TX_N

SATA_C1_TX_P

SATA_C0_RX_P

SATA_C0_RX_N

SATA_C0_TX_N

+V_PLL_USB

+V_PLL_SATA

+DVDD0_SATA1

+DVDD0_SATA2

+DVDD0_SATA3

+DVDD0_SATA4

+DVDD1_SATA2

+AVDD0_SATA1

+AVDD0_SATA2

+AVDD0_SATA3

+AVDD0_SATA4

+AVDD0_SATA5

+AVDD0_SATA6

+AVDD0_SATA7

+AVDD0_SATA8

+AVDD0_SATA9

+AVDD1_SATA1

+AVDD1_SATA2

+AVDD1_SATA3

+AVDD1_SATA4

+DVDD1_SATA1

SATA

USB

OUT

IN

OUT

IN

BI

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

Geyser Trackpad/Keyboard

AirPort (PCIe Mini-Card)

19 mA (A01)

84 mA (A01)

IR

Camera

External A

External D

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

43 mA (A01, DVDD0 & 1)

127 mA (A01, AVDD0 & 1)

If all SATA_Ax & Bx pins are not used, ground DVDD0_SATA and AVDD0_SATA.

If all SATA_Cx pins are not used, ground DVDD1_SATA and AVDD1_SATA.

External C

External B

Bluetooth

ExpressCard

20 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

TP_USB_10N

USB_BT_N

USB_IR_P

USB_CAMERA_N

USB_CAMERA_P

USB_EXTD_P

USB_MINI_N

USB_MINI_P

USB_EXTA_N

USB_EXTA_P

TP_SATA_D_D2RP

TP_SATA_E_R2D_CN

TP_SATA_E_D2RN

TP_SATA_E_D2RP

PP3V3_S0_MCP_PLL_USB

MCP_USB_RBIAS_GND

TP_MCP_SATALED_L

TP_SATA_C_R2D_CP

TP_SATA_C_R2D_CN

TP_SATA_D_R2D_CP

TP_SATA_D_R2D_CN

TP_SATA_D_D2RN

TP_SATA_E_R2D_CP

TP_SATA_F_R2D_CP

TP_SATA_F_R2D_CN

TP_SATA_F_D2RN

TP_SATA_F_D2RP

MCP_SATA_TERMP

USB_EXTD_N

USB_IR_N

USB_TPAD_P

PP1V05_S0_MCP_PLL_SATA

TP_SATA_C_D2RN

TP_SATA_C_D2RP

SATA_HDD_R2D_C_P

SATA_HDD_R2D_C_N

SATA_HDD_D2R_P

SATA_HDD_D2R_N

SATA_ODD_R2D_C_P

SATA_ODD_R2D_C_N

SATA_ODD_D2R_N

SATA_ODD_D2R_P

=PP1V05_S0_MCP_SATA_DVDD0

=PP1V05_S0_MCP_SATA_DVDD1

=PP1V05_S0_MCP_SATA_AVDD0

=PP1V05_S0_MCP_SATA_AVDD1

=PP3V3_S5_MCP_GPIO

USB_TPAD_N

USB_BT_P

USB_EXTC_OC_L

EXCARD_OC_L

USB_EXTB_OC_L

USB_EXTA_OC_L

USB_EXTB_N

USB_EXTB_P

USB_EXCARD_P

USB_EXCARD_N

TP_USB_10P

USB_EXTC_N

USB_EXTC_P

USB_CARDREADER_P

USB_CARDREADER_N

SYNC_DATE=04/04/2008

MCP SATA & USB

SYNC_MASTER=T18_MLB

30C7 76B3

37C3 75A3

37B2 75A3

37A2 75A3

D27

F27

G27

J25

H25

K23

G25

U1400

MCP79-TOPO-B

BGA

(8 OF 11)

A27

H21

J21

K21

L21

K25

L25

E27

J26

J27

K27

L27

F29

G29

A28

B28

C28

D28

L23

F25

C29

D29

AE3

E12

AP3

AP2

AN2

AN3

AN1

AM1

AM3

AM2

AM4

AL3

AK3

AL4

AK2

AJ3

AJ1

AJ2

AJ11

AJ10

AK9

AJ9

AJ7

AJ6

AJ4

AJ5

L28

AE16

AH19

AH17

AG19

AG17

AG16

AF19

AM14

AM13

AL14

AN14

AL13

AN12

AM12

AM11

AL12

AK13

AK12

AN11

AJ12

AH24

AH22

AH20

AH18

AG40

AG36

AG26

AG22

AG20

AG18

AF40

AF37

AF34

AF33

AF28

AF27

AF26

AF22

AF20

AF18

AF17

AF16

AD6

AE4

AE39

AE24

AE22

AD38

AD37

AD35

OMIT

2

1

R2050

8.2K

5%

MF-LF

1/16W

402

2

1

R2051

MF-LF

402

1/16W

8.2K

5%

2

1

R2052

8.2K

5%

MF-LF

1/16W

402

2

1

R2053

402

1/16W

MF-LF

8.2K

5%

2

1

R2060

402

1/16W

1%

MF-LF

806

2

1

R2010

2.49K

402

1/16W

1%

MF-LF

41C4

38C7

8C6

38B4 76B3

38A4 76B3

29B5 76C3

48B8 76B3

39D7 76B3

29B5 76C3

8C6

38A8 76C3

22B4

76B3

75A3

22B2

7A6

7A3 17C7

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

HDA_SDATA_IN2_GPIO_3/PS2_KB_DATA

SLP_S3*

HDA_DOCK_EN*_GPIO_4/PS2_MS_CLK

SLP_RMGT*

HDA_BITCLK

HDA_SDATA_OUT

THERM_DIODE_N

THERM_DIODE_P

HDA_RESET*

HDA_PULLDN_COMP

HDA_SDATA_IN1_GPIO_2/PS2_KB_CLK

MCP_VID2/GPIO_15

MCP_VID1/GPIO_14

MCP_VID0/GPIO_13

EXT_SMI/GPIO_32*

FANCTL1/GPIO_62

FANRPM1/GPIO_63

FANCTL0/GPIO_61

FANRPM0/GPIO_60

SIO_PME*

KBRDRSTIN*

PKG_TEST

TEST_MODE_EN

BUF_SIO_CLK

CPUVDD_EN

SMB_DATA0

SMB_CLK0

SPKR

HDA_SYNC

XTALIN_RTC

XTALOUT

XTALOUT_RTC

JTAG_TRST*

XTALIN

JTAG_TCK

JTAG_TMS

CPU_VLD

JTAG_TDI

JTAG_TDO

RTC_RST*

PS_PWRGD

PWRGD_SB

INTRUDER*

LID*

LLB*

PWRBTN*

RSTBTN*

CPU_DPRSLPVR

SLP_S5*

HDA_SDATA_IN0

SMB_CLK1/MSMB_CLK

SMB_DATA1/MSMB_DATA

SMB_ALERT*/GPIO_64

SPI_CS0/GPIO_10

SPI_CLK/GPIO_11

SPI_DI/GPIO_8

SPI_DO/GPIO_9

SUS_CLK/GPIO_34

+V_DUAL_HDA1

+V_DUAL_HDA2

HDA_DOCK_RST*_GPIO_5/PS2_MS_DATA

GPIO_1/PWRDN_OK/SPI_CS1

A20GATE

GPIO_12_SUS_STAT_ACCLMTR_EXT_TRIG_L

+V_PLL_SP_SPREF

+V_PLL_NV_H

MISC

HDA

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

(MGPIO2)

(MGPIO3)

Int PU (S5)

17 mA

20 mA

37 mA (A01)

7 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

HDA Output Caps

For EMI Reduction on HDA interface

PCI

not use LPC for BootROM override.

LPC_FRAME# high for SPI1 ROM override.

SPI0 = SPI_CS0_L, SPI1 = SPI_CS1_L

Int PU

Int PU (S5)

Int PU

25 MHz

42 MHz

0

LPC ROMs. So Apple designs will

0

1

HDA_SYNC

24 MHz

0

1

0

SPI_CLK

SPI_DO

0

1

14.31818 MHz

BUF_SIO_CLK Frequency

Frequency

31 MHz

NOTE: Straps not provided on this page.

1 MHz

SPI Frequency Select

Frequency

NOTE: MCP79 does not support FWH, only

LPC

SPI0

SPI1

I/F

HDA_SDOUT

BIOS Boot Select

R1961 and R2160 selects SPI0 ROM by

default, LPC+ debug card pulls

1

0

LPC_FRAME#

0

1

0

1

Int PU

Int PD

Int PU (S5)

NOTE: MCP79 rev A01 does not support

SPI1 option. Rev B01 will.

Int PU

Int PU (S5)

(MXM_OK for MXM systems)

SAFE mode: For ROMSIP

recovery

USER mode: Normal

Connects to SMC for

automatic recovery.

21 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

SMC_IG_THROTTLE_L

TP_MCP_BUF_SIO_CLK

ARB_DETECT

=PP3V3R1V5_S0_MCP_HDA

MCP_GPIO_4

AP_PWR_EN

=PP3V3_S3_MCP_GPIO

AUD_I2C_INT_L

MCP_GPIO_4

MCP_CPU_VLD

MCP_VID<0>

PM_DPRSLPVR

HDA_SDIN0

MCP_CPUVDD_EN

MCP_VID<0>

MCP_THMDIODE_P

SMBUS_MCP_1_CLK

TP_MCP_LID_L

PM_PWRBTN_L

RTC_RST_L

MCP_PS_PWRGD

JTAG_MCP_TDI

JTAG_MCP_TDO

SMBUS_MCP_1_DATA

AP_PWR_EN

MCP_VID<2>

SMBUS_MCP_0_DATA

PM_BATLOW_L

HDA_SDOUT_R

HDA_BIT_CLK_R

=SPI_CS1_R_L_USE_MLB

SPI_CLK_R

SMC_RUNTIME_SCI_L

MCP_VID<1>

PM_SLP_RMGT_L

TP_SB_A20GATE

MCP_HDA_PULLDN_COMP

PP1V05_S0_MCP_PLL_NV

SPI_CS0_R_L

RTC_CLK32K_XTALOUT

RTC_CLK32K_XTALIN

MCP_CLK25M_XTALOUT

MCP_CLK25M_XTALIN

JTAG_MCP_TCK

PM_CLK32K_SUSCLK_R

SPI_MISO

SPI_MOSI_R

SMBUS_MCP_0_CLK

MCP_THMDIODE_N

PM_SYSRST_DEBOUNCE_L

TP_MCP_KBDRSTIN_L

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

PP3V3_G3_RTC

=PP3V3R1V5_S0_MCP_HDA

HDA_SYNC_R

HDA_SDOUT_R

HDA_RST_R_L

HDA_BIT_CLK_R

MCP_VID<2>

MCP_VID<1>

JTAG_MCP_TMS

MCP_TEST_MODE_EN

JTAG_MCP_TRST_L

PM_RSMRST_L

SM_INTRUDER_L

ARB_DETECT

HDA_SYNC

HDA_RST_R_L

ODD_PWR_EN_L

MEM_EVENT_L

SMC_WAKE_SCI_L

=PP3V3_S0_MCP_GPIO

MEM_EVENT_L

SMC_IG_THROTTLE_L

SMC_ADAPTER_EN

TP_MLB_RAM_VENDOR

TP_MLB_RAM_SIZE

HDA_SYNC_R

AUD_I2C_INT_L

PM_SLP_S3_L

PM_SLP_S4_L

=PP3V3_S0_MCP

MCP_SPKR

MCP HDA & MISC

SYNC_DATE=06/26/2008

SYNC_MASTER=T18_MLB

42B7 76A3

42A5 42C7 76A3

42A5 42B7 76A3

24A1

40C8

40D8

24A5

24C8

24B8

24C8

20A4 41D4

41C5

2

1

R2140

10K

5%

MF-LF

1/16W

402

2

1

R2143

MF-LF

402

1/16W

5%

10K

1

2

R2154

1/16W

MF-LF

5%

100K

402

2

1

R2151

402

MF-LF

5%

1/16W

100K

2

1

R2155

402

1/16W

22K

5%

MF-LF

2

1

R2156

22K

5%

MF-LF

1/16W

402

2

1

R2157

22K

5%

MF-LF

1/16W

402

2

1

R2141

402

1/16W

MF-LF

5%

10K

2

1

R2142

10K

5%

1/16W

402

MF-LF

2

1

R2147

402

1/16W

MF-LF

5%

100K

20A4 26A5 27A5 40B8

32B7 35B5 40D5 41B2

24A8 24A5

20A4 57D3

37D6

B19

B16

A19

A16

B11

C11

K22

B18

C13

B14

C15

C14

D13

F21

K19

G21

L19

M23

H17

G17

J17

C19

C20

D16

D20

C16

E20

L22

AE17

AE18

K16

J16

M21

M20

L20

M24

M25

L13

J18

J19

F19

E19

G19

B20

L15

F15

J15

J14

G15

K15

A15

L17

K17

E15

L24

L26

D12

B12

C12

A12

C18

D17C17

M22

AE7

K13

U1400

BGA

(9 OF 11)

MCP79-TOPO-B

OMIT

2

1

C2172

50V

10PF

5%

402

CERM

2

1

C2170

50V

10PF

5%

402

CERM

2

1

C2173

50V

10PF

5%

402

CERM

2

1

C2171

10PF

50V

5%

402

CERM

12C3

12B6

12C3

2

1

R2150

402

1/16W

MF-LF

5%

10K

2

1

R2110

49.9

MF-LF

1/16W

1%

402

42B8

21

R2172

402

5%

22

1/16W

MF-LF

2

1

R2181

5%

10K

402

MF-LF

BOOT_MODE_USER

1/16W

2

1

R2180

5%

10K

MF-LF

BOOT_MODE_SAFE

402

1/16W

2

1

R2160

MF-LF

8.2K

5%

1/16W

402

2

1

R2163

402

5%

10K

MF-LF

1/16W

21

R2173

5%

22

MF-LF

1/16W

402

21

R2171

MF-LF

5%

1/16W

402

22

21

R2170

MF-LF

402

5%

22

1/16W

40B8

40C5

24B4 76A3

2

1

R2190

1K

MF-LF

1%

1/16W

402

2

1

R2120

1%

49.9K

MF-LF

402

1/16W

2

1

R2121

MF-LF

1/16W

1%

402

49.9K

52C7 76A3

52C7 76B3

52C7 76A3

52C7 76B3

52C7 76A3

40B8

62D8 73B3

8D1

46B5 80D3

20A3 29D5 32C7

20A3 63C8

46B5 80D3

20A3 63D8

43B8 76B3

12B6 43D8 76B3

43B8 76B3

12B6 43D8 76B3

6C3 40C5 41A2 66C8

6C3 32B7 35A5 40C5 66D5 70D8

42A5 42C8 76A3

20A4

7C5 20D8 22A8

20A4

20C3 29D5 32C7

7D3

20C3 57D3

20C3

20C3 63D8

20A7 76A3

20A7 76B3

76A3

22A2

6C3 21A5 24D4

7C5 20D3 22A8

20D4 76B3

20D4 76A3

20D4 76B3

20C3 63C8

20B3

20A7 76A3

7C5 17C1 18D1

20B3 26A5 27A5 40B8

20B3 41D4

20A7 76B3

7C5 21B3 22B8

GND

GND161

GND165

GND166

GND164

GND163

GND162

GND167

GND168

GND171

GND170

GND169

GND172

GND173

GND176

GND175

GND174

GND177

GND178

GND181

GND180

GND179

GND182

GND183

GND184

GND187

GND186

GND185

GND188

GND189

GND192

GND191

GND190

GND193

GND194

GND197

GND196

GND195

GND198

GND202

GND201

GND200

GND199

GND203

GND206

GND207

GND205

GND204

GND208

GND212

GND211

GND210

GND209

GND213

GND214

GND217

GND216

GND215

GND218

GND219

GND222

GND221

GND220

GND223

GND224

GND225

GND228

GND227

GND226

GND229

GND230

GND233

GND232

GND231

GND234

GND235

GND238

GND237

GND236

GND239

GND240

GND243

GND242

GND241

GND244

GND248

GND247

GND246

GND245

GND249

GND252

GND251

GND250 GND342

GND341

GND343

GND340

GND339

GND338

GND337

GND336

GND335

GND334

GND333

GND331

GND332

GND330

GND329

GND328

GND326

GND327

GND325

GND324

GND323

GND321

GND322

GND320

GND319

GND318

GND316

GND317

GND315

GND314

GND313

GND311

GND310

GND312

GND309

GND308

GND305

GND306

GND307

GND304

GND303

GND301

GND300

GND302

GND299

GND298

GND296

GND295

GND297

GND294

GND293

GND292

GND291

GND290

GND289

GND288

GND287

GND285

GND286

GND284

GND283

GND282

GND280

GND281

GND279

GND278

GND277

GND275

GND276

GND274

GND273

GND272

GND270

GND269

GND271

GND268

GND267

GND264

GND265

GND266

GND263

GND262

GND259

GND260

GND261

GND258

GND257

GND255

GND254

GND256

GND253

+VTT_CPUCLK

+VDD_CORE42

+3.3V_DUAL_USB2

+VTT_CPU17

+VTT_CPU16

+VTT_CPU15

+VTT_CPU14

+VTT_CPU13

+VTT_CPU12

+VTT_CPU11

+VTT_CPU10

+VTT_CPU1

+VDD_CORE7

+VDD_CORE1

+VDD_CORE2

+VDD_CORE3

+VDD_CORE4

+VDD_CORE5

+VDD_CORE6

+VDD_CORE13

+VDD_CORE14

+VDD_CORE15

+VDD_CORE16

+VDD_CORE17

+VDD_CORE18

+VDD_CORE19

+VDD_CORE21

+VDD_CORE22

+VDD_CORE23

+VDD_CORE24

+VDD_CORE25

+VDD_CORE26

+VDD_CORE27

+VDD_CORE28

+VDD_CORE29

+VDD_CORE30

+VDD_CORE32

+VDD_CORE33

+VDD_CORE34

+VDD_CORE35

+VDD_CORE36

+VDD_CORE37

+VDD_CORE39

+VDD_CORE40

+VDD_CORE41

+VDD_CORE47

+VDD_CORE48

+VDD_CORE49

+VDD_CORE50

+VDD_CORE51

+VDD_CORE52

+VDD_CORE53

+VDD_CORE54

+VTT_CPU51

+VTT_CPU50

+VTT_CPU47

+VTT_CPU46

+VTT_CPU45

+VTT_CPU43

+VTT_CPU42

+VTT_CPU41

+VTT_CPU40

+VTT_CPU39

+VTT_CPU38

+VTT_CPU37

+VTT_CPU36

+VTT_CPU35

+VTT_CPU34

+VTT_CPU32

+VTT_CPU31

+VTT_CPU30

+VTT_CPU29

+VTT_CPU28

+VTT_CPU26

+VTT_CPU25

+VTT_CPU24

+VTT_CPU23

+VTT_CPU22

+VTT_CPU21

+VTT_CPU20

+VTT_CPU19

+VTT_CPU18

+VTT_CPU9

+VTT_CPU8

+VTT_CPU7

+VTT_CPU6

+VTT_CPU5

+VTT_CPU4

+VTT_CPU3

+VDD_CORE38

+VTT_CPU33

+VTT_CPU27

+VDD_CORE55

+VDD_CORE56

+VDD_CORE57

+VDD_CORE58

+VDD_CORE59

+VDD_CORE60

+VDD_CORE61

+VDD_CORE62

+VDD_CORE63

+VDD_CORE64

+VDD_CORE65

+VDD_CORE66

+VDD_CORE67

+VDD_CORE68

+VDD_CORE69

+VDD_CORE70

+VDD_CORE71

+VDD_CORE72

+VDD_CORE73

+VDD_CORE74

+VDD_CORE75

+VDD_CORE76

+VDD_CORE77

+VDD_CORE78

+VDD_CORE79

+VDD_CORE80

+VDD_CORE81

+VBAT

+3.3V_1

+3.3V_8

+3.3V_DUAL1

+3.3V_DUAL2

+3.3V_DUAL3

+3.3V_DUAL4

+3.3V_DUAL_USB1

+3.3V_DUAL_USB3

+3.3V_DUAL_USB4

+VDD_AUXC1

+VDD_AUXC3

+VDD_AUXC2

+VDD_CORE43

+VTT_CPU2

+VDD_CORE46

+VDD_CORE45

+VDD_CORE44

+VTT_CPU52

+VDD_CORE31

+VTT_CPU49

+VTT_CPU48

+VTT_CPU44

+3.3V_7

+3.3V_6

+3.3V_5

+3.3V_4

+3.3V_3

+3.3V_2

+VDD_CORE20

+VDD_CORE12

+VDD_CORE11

+VDD_CORE10

+VDD_CORE9

+VDD_CORE8

POWER

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

1182 mA (A01)

450 mA (A01)

266 mA (A01)

16 mA

10 uA (G3)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

80 uA (S0)

23065 mA (A01, 1.2V)

16996 mA (A01, 1.0V)

250 mA

1139 mA

43 mA

105 mA (A01)

22 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP3V3_S5_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP3V3_S0_MCP

PP3V3_G3_RTC

=PPVCORE_S0_MCP

=PP1V05_S0_MCP_FSB

MCP Power & Ground

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

AG32

W32

V32

U32

T32

AA32

Y32

P32

N32

N31

M33

M32

M31

L34

L33

L32

K35

K34

K33

J36

J35

J34

H37

H35

G38

G37

G36

F39

F38

F37

E40

E39

E38

D41

D40

D39

C42

C41

C40

B42

B41

AC32

AB32

AL31

AD32

AK32

AK31

AJ32

AH32

AE32

AF32

P31

R32

AA16

AF12

W25

Y23

W23

W21

AA24

AH9

AH7

AH6

AH5

AH4

AH3

AH21

Y21

AH25

W28

AA23

AH2

W26

AH11

AH10

AH1

AG9

AG8

AG5

AG7

AG6

AA21

AG4

AG3

AG25

AG23

AG21

AG12

AG11

AG10

AA20

AF9

AH23

AF7

AF4

AF3

AF25

AF23

AF21

AF2

AH12

AA19

AF11

AF10

AE28

AE27

AE26

AE25

AE23

AE21

AE19

U25

AA18

V25

W27

AD23

AD21

AC28

AC27

AC26

AC25

AC24

AC23

AA17

AC21

AC20

AC19

AC18

AC17

AC16

AA28

AA27

AA26

AA25

V21

U21

T21

A20

K28

J28

H27

G26

K20

J20

H19

G18

Y9

AA8

AB11

Y10

AD9

AB10

AE8

AD10

U1400

OMIT

MCP79-TOPO-B

BGA

(10 OF 11)

T22

AH16

Y11

V11

T11

Y6

P11

AY13

AB19

AA4

M11

AD7

AN26

AB16

AB17

Y38

Y37

Y35

Y34

Y33

Y28

M37

M35

M34

M10

L5

L43

L40

AU1

K8

K40

K4

K37

K26

K18

K12

K10

J8

J12

G40

AN8

H23

AW35

H15

H11

G8

G6

G43

G4

G34

AW20

G24

G22

BC12

G16

G14

G12

G10

F8

F32

F16

F12

E33

E29

E25

E21

E17

E13

D6

D37

D30

D26

D23

D22

D19

D18

D15

D14

D10

C2

BC5

AY14

BC41

BC37

BC33

L35

AY6

AW31

BA4

BA1

AV40

AY41

AY38

AY37

AY34

AY33

AY30

AV12

AY10

AW43

AR43

G20

AW11

AV7

AV4

AV36

AV32

AV28

F20

G28

AU4

AU38

AU36

AR30

AU32

AP33

AU28

AU12

L12

AY22

AY21

AT9

AT7

AT6

AT33

AT29

AT13

AR12

AT10

AR40

AR32

AR28

AW23

AP7

AP40

AP4

AP37

AP36

AP34

AP32

AP28

AU14

AP14

AU26

AP10

Y7

AN4

AN39

AN30

AN28

AP26

AM9

AM7

AM6

AM5

AM38

AM37

AM35

AM34

AM30

AM26

AM24

AM22

AM20

AM18

AM16

AM10

AL5

AL40

AL36

AK40

AK4

AK37

AK34

AK33

AK10

AJ8

AJ39

AH38

AH37

AH34

AH33

AH26

U1400

(11 OF 11)

MCP79-TOPO-B

OMIT

BGA

7A3 22B8

7B3 22D8

7C5 20C2 22B8

6C3 20C8 24D4

7C6 22D8 7D7 13A2 13B7 22C8

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

Apple: 7x 2.2uF 0402 (15.4 uF)

MCP 1.05V RMGT Power

NV: 1x 4.7uF 0603, 4x 0.1uF 0402 (5.1 uF)

5 mA (A01)

562 mA (A01)

57 mA (A01)

16996 mA (A01, 1.0V)

Apple: 4x 2.2uF 0402 (8.8 uF)

Apple: 4x 4.7uF 0402, 4x 1uF 0402, 6x 0.1uF 0402 (23.4 uF)

NV: 1x 10uF 0805, 2x 4.7uF 0402, 3x 1uF 0402, 9x 0.1uF 0402 (23.3 uF)

MCP SATA (DVDD) Power

1182 mA (A01)

7 mA (A01)

19 mA (A01)

333 mA (A01)

4771 mA (A01, DDR3)

MCP Core Power

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Power

MCP Memory Power

MCP FSB (VTT) Power

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

Apple: 5x 2.2uF 0402 (11 uF)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 1uF 0402, 2x 0.1uF 0402 (16.9 uF)

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP 1.05V AUX Power

5 mA (A01)

MCP 3.3V/1.5V HDA Power

266 mA (A01)

MCP 3.3V AUX/USB Power

Apple: 1x 2.2uF 0402 (2.2 uF)

MCP79 Ethernet VRef

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

MCP 3.3V Ethernet Power

270 mA (A01)

(No IG vs. EG data)

23065 mA (A01, 1.2V)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

MCP PCIE (DVDD) Power

105 mA (A01) 131 mA (A01)

83 mA (A01)

84 mA (A01)

87 mA (A01)

37 mA (A01)

NV: 1x 10uF 0805, 1x 4.7uF 0402, 2x 0.1uF 0402 (14.9 uF)

206 mA (A01)

127 mA (A01)

43 mA (A01)

450 mA (A01)

19 mA (A01)

25 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PP1V05_S0_MCP_PEX_DVDD

=PPVCORE_S0_MCP

=PP1V05_S5_MCP_VDD_AUXC

=PP1V05_S0_MCP_PLL_UF PP1V05_S0_MCP_PLL_FSB

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_PEX

VOLTAGE=1.05V

PP1V05_S0_MCP_PLL_NV

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V05_S0_MCP_PLL_CORE

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_SATA_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PEX_AVDD

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

PP3V3_S0_MCP_PLL_USB

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

PP1V05_S0_MCP_PLL_SATA

VOLTAGE=1.05V

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.05V

MIN_LINE_WIDTH=0.4 MM

PP1V05_ENET_MCP_PLL_MAC

=PP1V05_ENET_MCP_PLL_MAC

=PP3V3_ENET_MCP_RMGT

MCP_MII_VREF

=PP3V3_S0_MCP

=PP3V3R1V5_S0_MCP_HDA

=PP3V3_S5_MCP

=PP1V05_S0_MCP_AVDD_UF

=PP1V05_S0_MCP_FSB

=PP1V8R1V5_S0_MCP_MEM

=PP1V05_ENET_MCP_RMGT

=PP3V3_S0_MCP_PLL_UF

=PP3V3_ENET_MCP_RMGT

=PP1V05_S0_MCP_SATA_DVDD

MCP Standard Decoupling

SYNC_MASTER=T18_MLB

SYNC_DATE=04/04/2008

X5R-1

4.7UF

4V

20%

402

C2503

1

2

C2592

603

X5R

6.3V

20%

10UF

2

1

4.7UF

X5R-1

20%

4V

402

C2528

1

2 2

1

C2529

10V

402

0.1uF

20%

CERM

2

1

C2596

10V

402

0.1UF

20%

CERM

C2587

2

1

10V

402

0.1UF

CERM

20%

C2585

2

1

10V

402

0.1UF

CERM

20%

C2583

0.1UF

2

1

10V

402

20%

CERM

20%

CERM

0.1UF

402

10V

C2581

1

2

1

C2519

10V

402

20%

CERM

0.1uF

C2518

2

1

10V

402

CERM

20%

0.1uF

2

1

C2521

10V

402

0.1uF

20%

CERM

17D3

2

1

R2591

402

1.47K

1/16W

1%

MF-LF

2

1

C2591

10V

402

20%

CERM

0.1UF

2

1

R2590

402

MF-LF

1%

1/16W

1.47K

21

L2595

0402

30-OHM-1.7A

X5R-1

20%

4.7UF

4V

402

C2595

1

2

1

C2590

10V

402

20%

0.1UF

CERM

C2589

0.1UF

2

1

10V

402

20%

CERM

C2560

2

1

CERM

402-LF

20%

2.2UF

6.3V

2

1

C2525

10V

402

0.1uF

20%

CERM CERM

20%

2

1

C2526

10V

402

0.1uF

0402

L2580

30-OHM-1.7A

21

X5R-1

4.7UF

4V

402

C2501

1

2

20%

X5R-1

4V

20%

402

C2500

1

2

4.7UF

0402

21

L2555

30-OHM-1.7A

21

L2586

30-OHM-1.7A

0402

21

L2588

0402

30-OHM-1.7A

21

L2584

0402

30-OHM-1.7A

L2582

21

0402

30-OHM-1.7A

21

L2575

0603

30-OHM-5A

21

L2570

30-OHM-5A

0603

X5R-1

4.7UF

20%

4V

402

C2580

1

2

1

C2564

6.3V

2.2UF

20%

402-LF

CERM

2

1

C2562

CERM

402-LF

20%

2.2UF

6.3V

X5R-1

20%

4.7UF

4V

402

C2540

1

2

0.1UF

2

1

C2541

10V

402

20%

CERM

0.1UF

C2542

2

1

10V

402

CERM

20%

2

1

C2543

10V

402

CERM

20%

0.1UF 0.1UF

2

1

C2544

10V

402

CERM

20%

2

1

C2545

10V

402

CERM

20%

0.1UF

2

1

C2546

10V

402

CERM

20%

0.1UF

2

1

C2547

10V

402

CERM

20%

0.1UF

2

1

C2548

10V

402

CERM

20%

0.1UF

2

1

C2549

10V

402

CERM

20%

0.1UF

2

1

C2550

CERM

402-LF

20%

2.2UF

6.3V

2

1

C2551

CERM

402-LF

20%

6.3V

2.2UF

2

1

C2552

CERM

402-LF

20%

2.2UF

6.3V

2

1

C2553

CERM

402-LF

20%

6.3V

2.2UF

402-LF

2

1

C2575

CERM

20%

2.2UF

6.3V

2

1

C2576

6.3V

2.2UF

20%

402-LF

CERM

2

1

C2573

CERM

402-LF

20%

2.2UF

6.3V

2

1

C2574

CERM

402-LF

20%

2.2UF

6.3V

2

1

C2570

CERM

402-LF

20%

2.2UF

6.3V

X5R-1

4V

4.7UF

20%

402

C2520

1

2 2

1

C2571

CERM

402-LF

20%

2.2UF

6.3V

2

1

C2572

CERM

402-LF

20%

2.2UF

6.3V

X5R-1

4.7UF

4V

20%

C2515

1

2

402

C2516

2

1

10V

10%

1UF

402-1

X5R

C2517

2

1

10V

10%

1UF

402-1

X5R

2

1

C2530

CERM

402-LF

20%

2.2UF

6.3V

2

1

C2531

CERM

402-LF

6.3V

2.2UF

20%

2.2UF

C2532

2

1

CERM

402-LF

20%

6.3V

402-LF

C2533

2

1

CERM

20%

2.2UF

6.3V

2

1

C2534

CERM

402-LF

20%

6.3V

2.2UF

2

1

C2535

CERM

402-LF

20%

2.2UF

6.3V 6.3V

2

1

C2536

CERM

402-LF

20%

2.2UF

2

1

C2512

10V

402

20%

CERM

0.1UF

2

1

C2513

10V

402

20%

CERM

0.1UF

2

1

C2508

10V

402

20%

CERM

0.1UF

2

1

C2509

10V

402

20%

CERM

0.1UF

2

1

C2510

10V

402

20%

CERM

0.1UF

2

1

C2511

10V

402

20%

CERM

0.1UF

2

1

C2504

10V

10%

1UF

402-1

X5R

2

1

C2505

10V

10%

1UF

402-1

X5R

2

1

C2506

10V

10%

1UF

402-1

X5R

2

1

C2507

10V

10%

1UF

402-1

X5R

X5R-1

4.7UF

4V

20%

402

C2502

1

2

1

C2555

6.3V

2.2UF

20%

402-LF

CERM

X5R-1

4V

4.7UF

20%

402

C2586

1

2

X5R-1

4.7UF

20%

4V

402

C2584

1

2

X5R-1

20%

4.7UF

4V

402

C2588

1

2

X5R-1

4V

4.7UF

20%

402

C2582

1

2

7A8 7D7

7C6 21D5

7B3 21A3

7B8 65B1 13A6

16A6

20C7

15C6

7A8

19C3

19B6

17C6 7B5

7B5 17D3 17D7 22B6

7C5 20C2 21B3

7C5 20D3 20D8

7A3 21B3

7D7

7D7 13A2 13B7 21D3

7B6 15C3 15C7

7A5 17D3

7C5

7B5 17D3 17D7 22A5

7A8 7D7

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

Apple: ???

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

190 mA (A01, 1.8V)

95 mA (A01)

16 mA (A01)

Apple: 1x 2.2uF 0402 (2.2 uF)

NV: 1x 4.7uF 0603, 2x 0.1uF 0402 (4.9 uF)

Apple: 2x 2.2uF 0402 (4.4 uF)

NV: 1x 4.7uF 0603, 1x 0.1uF 0402 (4.8 uF)

16 mA (A01)

206 mA (A01)206 mA (A01)

Current numbers from email Poonacha Kongetira provided 11/30/2007 4:04pm (no official document number).

NOSTUFF PP3V3_S0_MCP_DAC RAIL COMPONENTS (L2650 AND C2650)

REMOVE MCP 27MHZ CRYSTAL CRICUIT SINCE NOT SUPPORTING TV-OUT

SYNC FROM T18

CHANGE C2651 TO R2651 TO GND PP3V3_S0_MCP_DAC

REMOVE HDCP ROMS

REMOVE DAC TERMINATIONS R2665,C2665 AND R2670 TO R2672

WF: Checklist says 0-ohm resistor placeholder for ferrite bead.

26 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

VOLTAGE=3.3V

PP3V3_S0_MCP_DAC

MIN_LINE_WIDTH=0.4 MM

MIN_NECK_WIDTH=0.2 MM

MCP_IFPAB_VPROBE

PP3V3_S0_MCP_VPLL

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM

MCP_HDMI_VPROBE

=PP3V3R1V8_S0_MCP_IFP_VDD

=PP3V3_S0_MCP_VPLL_UF

=PP3V3_S0_MCP_DAC_UF

MCP_HDMI_RSET

MCP_IFPAB_RSET

=PP1V05_S0_MCP_HDMI_VDD

SYNC_DATE=12/12/2007

SYNC_MASTER=T18_MLB

MCP Graphics Support

CERM

402-LF

20%

2.2UF

6.3V

2

1

C2610

402

1/16W

1%

1K

MF-LF

2

1

R2620

402

2

1

R2651

0

5%

1/16W

MF-LF

402

20%

CERM

0.1UF

10V

2

1

C2616

10V

20%

402

CERM

0.1uF

2

1

C2641

30-OHM-1.7A

0402

21

L2640

CERM

4.7UF

6.3V

20%

603

2

1

C2640

X5R-1

C2615

1

2

402

4V

4.7UF

20%

402

CERM

NO STUFF

10V

0.1UF

2

1

C2630

1

2

R2630

MF-LF

1/16W

1%

1K

402

NO STUFF

CERM

10V

20%

0.1UF

NO STUFF

402

2

1

C2620

30-OHM-1.7A

0402

21

L2650

NO STUFF

6.3V

2.2UF

20%

402-LF

CERM

2

1

C2650

NO STUFF

17C3

17A3 75B3

17B6

17A6 75B3

7B6 17B6

7C5

17A6 75B3 17A3 75B3

7D7 17A6

IN

OUT

IN

OUT

IN

OUT

IN

NC

OUT

IN

OUT

IN

OUT

Y

B

A

IN

OUT

VIN

GND

VOUT

EN

NC

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

PLACE C2800 AT COOLEST SPOT ON MLB

RTC Power Sources

MCP 25MHz Crystal

Platform Reset Connections

CHANGE RTC COIN CELL TO LDO & SUPERCAP

NOTE: If CPU_VLD deasserts during S0 MCP79 will take system to S5 immediately.

CPUVDD_EN (which is 40-100ms after PS_PWRGD assertion).

VR_PWRGOOD_DELAY should guarantee CPU_VLD does not go high before

results in earlier ROMSIP and MCP FSB I/O interface initialization.

MCPSEQ_SMC represents MCP79 ’MLB’ power sequencing connections,

SYNC FROM T18

CHANGE RESET BUTTOM TO RESET PADS

ALIAS MEM_VTT_EN TO =DDRVTT_EN

REMOVE UNUSED PCIE RESET SIGNALS

CHANGE Y2810 AND U2850 TO SMALLER PARTS

REMOVE R2824 AND NET PCI_CLK33M_SLOT_A

LPC Reset (Unbuffered)

but results in MCP79 ROMSIP sequence happening after CPU powers up.

Reset Button

10K pull-up to 3.3V S0 inside MCP

MCP S0 PWRGD & CPU_VLD

RTC Crystal

SMC 99ms delay from ALL_SYS_PWRGD to IMVP_VR_ON plus IMVP6 delay for

MCPSEQ_MIX is cross between MLB and internal power sequencing, which

PLACE C2819 CLOSE TO MCP79

PCIE Reset (Unbuffered)

28 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

CARDREADER_PLT_RST_L

MINI_RESET_L

PCIE_RESET_L

MAKE_BASE=TRUE

=FW_RESET_L

PCA9557D_RESET_L

BKLT_PLT_RST_L

LPC_CLK33M_LPCPLUS

RTC_CLK32K_XTALOUT

=PP3V42_G3H_RTC_D

MAKE_BASE=TRUE

MEM_VTT_EN

LPC_CLK33M_SMC_R

RTC_CLK32K_XTALOUT_R

MCP_CLK25M_XTALOUT_R

MCP_CLK25M_XTALIN

MCP_CLK25M_XTALOUT

PP3V3_G3_SUPERCAP

SMC_LRESET_L

=PP3V3_S5_MCPPWRGD

VR_PWRGOOD_DELAY

S0_AND_IMVP_PGOOD

ALL_SYS_PWRGD

MCP_CPUVDD_EN

MCP_CPU_VLD

MCP_PS_PWRGD

XDP_DBRESET_L

PM_SYSRST_DEBOUNCE_L

PM_SYSRST_L

DEBUG_RESET_L

RTC_CLK32K_XTALIN

=DDRVTT_EN

LPC_CLK33M_SMC

PM_CLK32K_SUSCLK

MEM_VTT_EN_R

PM_CLK32K_SUSCLK_R

LPC_RESET_L

MIN_LINE_WIDTH=0.3 mm

PP3V3_G3_RTC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

SB Misc

SYNC_MASTER=RAYMOND

SYNC_DATE=04/05/2008

30A7

2

1/16W

1

5%

0

MF-LF

402

R2895

21

402

0

1/16W

MF-LF

5%

R2820

SUPERCAP_NO

35D1

PLACEMENT_NOTE=PLACE C2819 CLOSE TO MCP79

10%

1UF

1

402

CERM

6.3V

C2819

2

1

10%

10V

X5R

402

SUPERCAP_YES

0.47UF

C2871

1

2

3

4

U2801

5

CRITICAL

TSOT-23-5

MIC5232-2.8YD5

SUPERCAP_YES

C2870

1UF

X5R

10%

2

1

402

10V

1 2

MF-LF

402

R2819

100

SUPERCAP_YES

20B7

21

R2853

MF-LF

5%

1/16W

0

402

MCPSEQ_SMC

21

R2852

MF-LF

5%

1/16W

0

402

MCPSEQ_MIX

20B7

21

R2850

402

0

1/16W

5%

MF-LF

PLACEMENT_NOTE=Place close to U1400

MCPSEQ_SMC

2

1

C2850

402

20%

CERM

0.1UF

MCPSEQ_SMC

10V

21

R2851

402

0

1/16W

5%

MF-LF

MCPSEQ_MIX

40D8 66A4

62C7

20B3

3

5

1

4

2

SOT665

TC7SZ08AFEAPE

U2850

2

1

0

5%

1/16W

MF-LF

402

R2810

R2815

1/16W

MF-LF

402

5%

0

2

1

2%

XHHG

3.3V

SM

2

SUPERCAP_YES

0.08F

C2800

1

Y2810

1 4

CRITICAL

7X1.5X1.4-SM

32.768K

402

MF-LF

0

5%

1

1/16W

2

R2871

25A5

9C6 12B3

40B8

R2898

1 2

402

5%

1/16W

MF-LF

XDP

0

NO STUFF

0

MF-LF

1/16W

5%

402

SILK_PART=SYS RST

2

1

R2890

33

402

MF-LF

1/16W

5%

21

R2899

X5R

10%

1UF

10V

402

NO STUFF

2

1

C2899

20C7

40C8 76C3

42D3 76C3

18C4

R2870

33

402

5%

1/16W

MF-LF

21

61C8 67A3

R2892

2

1/16W

MF-LF

5%

0

1

402

72C8

20B3 76A3

R2829

1 2

PLACEMENT_NOTE=Place close to U1400

402

MF-LF

5%

1/16W

22

40C5 76A3

20B7

1

2

402

1M

NO STUFF

R2816

1/16W

5%

MF-LF

25.0000M

Y2815

CRITICAL

3

2 4

1

SM-3.2X2.5MM

12pF

C2816

1 2

5%

50V

CERM

402

CERM

50V

12pF

21

5%

C2815

18B3 76C3

PLACEMENT_NOTE=Place close to U1400

R2825

1 2

MF-LF

5%

1/16W

33

402

R2826

1 2

PLACEMENT_NOTE=Place close to U1400

402

5%

1/16W

MF-LF

33

16B3

20B7

29A6

40C8

42D5

R2891

2

0

MF-LF

402

5%

1/16W

1

PLACEMENT_NOTE=Place close to U1400

R2881

1 2

33

5%

1/16W

MF-LF

402

R2883

1 2

33

MF-LF

5%

1/16W

402

PLACEMENT_NOTE=Place close to U1400

18C3 76C3

1

2

NO STUFF

R2811

10M

402

MF-LF

5%

1/16W

402

C2811

1 2

12pF

5%

50V

CERM

12pF

402

5%

50V

21

CERM

C2810

7D1

7A3

6C3 20C8 21A5

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

V-

V+

RESET*

A0

A1

A2

SCL

SDA

P0

P1

P2

P5

P6

P7

P3

P4

THRM

VCC

GND

PAD

NC

IN

BI

VDD

VOUTD

VOUTC

VOUTB

VOUTA

SCL

SDA

A0

A1

GND

IN

BI

NC

OUT

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE

THE POSESSOR AGREES TO THE FOLLOWING:

THE INFORMATION CONTAINED HEREIN IS THE

36

BRANCH

REVISION

DRAWING NUMBER SIZE

D

R

SHEET

PAGE TITLE

C

A

D

2 1

PROPRIETARY PROPERTY OF APPLE COMPUTER, INC.

Apple Inc.

PAGE

NOTICE OF PROPRIETARY PROPERTY:

A

B

C

345678

D

B

8 7 5 4 2 1

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DAC channel A B A B C

Max DAC code 0x87 0x87 0x87 0x87 0x55

Max source I 5 mA 5 mA 5 mA 5 mA 0.52 mA

Min Vref 0.375 V 0.375 V 0.375 V 0.375 V 0.091 V

Max Vref 1.250 V 1.250 V 1.250 V 1.250 V 1.044 V

Vref Stepping 6.5 mV 6.5 mV 6.5 mV 6.5 mV 11.2 mV

Signal aliases required by this page:

- =PPVTT_S3_DDR_BUF

- =PP3V3_S5_VREFMRGN

- =I2C_VREFDACS_SDA

- =I2C_PCA9557D_SDA

Min DAC code 0x00 0x00 0x00 0x00 0x00

- =I2C_PCA9557D_SCL

- =I2C_VREFDACS_SCL

(per DAC LSB)

Max sink I -3.75 mA -3.75 mA -3.75 mA -3.75 mA -0.91 mA

Nominal Vref 0.75 V 0.75 V 0.75 V 0.75 V 0.70 V

Place close to U1000.AD26

Place close to J3100.1

MEM A VREF CAMEM A VREF DQ

Page Notes

10mA max load

- =PP3V3_S3_VREFMRGN

Power aliases required by this page:

Place close to J3200.1

Place close to J3200.126

VREFMRGN

MEM B VREF DQ

ADDR=0x30(WR)/0x31(RD)

Required zero ohm resistors when no VREF margining circuit stuffed

ADDR=0x98(WR)/0x99(RD)

NO_VREFMRGN

BOM options provided by this page:

SO-DIMM A and SO-DIMM B Vref settings should be margined separately

(i.e. not simultaneously) due to current limitation of TPS51116 regulator.

Place close to J3100.126

MEM B VREF CA

CPU FSB VREF

29 OF 109

051-7898

C.0.0

<CURRENT_DESIGN_SHEET> OF <TOTAL_DESIGN_SHEETS>

=PPVTT_S3_DDR_BUF

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFCA_A

MIN_LINE_WIDTH=0.3 mm

MIN_NECK_WIDTH=0.2 mm

PP0V75_S3_MEM_VREFDQ_B

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP0V75_S3_MEM_VREFDQ_A

VREFMRGN_DQ_SODIMMB_BUF

=PP3V3_S3_VREFMRGN

CPU_GTLREF

VREFMRGN_CA_SODIMM

VREFMRGN_DQ_SODIMMA_BUF

VREFMRGN_CA_SODIMMA_BUF

VREFMRGN_CA_SODIMMB_BUF

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMM

VREFMRGN_DQ_SODIMMA_EN

PCA9557D_RESET_L

=I2C_VREFDACS_SCL

=I2C_VREFDACS_SDA

=I2C_PCA9557D_SDA

=I2C_PCA9557D_SCL

VREFMRGN_CA_SODIMMB_EN

VREFMRGN_DQ_SODIMMB_EN

VREFMRGN_DQ_SODIMMA_EN

VREFMRGN_CPUFSB_EN

VREFMRGN_CA_SODIMMA_EN

VREFMRGN_CPUFSB_BUF

VREFMRGN_CPUFSB

FSB/DDR3 Vref Margining

SYNC_MASTER=BEN

SYNC_DATE=03/31/2008

R2905

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

NO_VREFMRGN

1

CRITICAL

R2911

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

NO_VREFMRGN

1

CRITICAL

RES,MTL FILM,0,5%,0402,SM,LF

R2909

116S0004

NO_VREFMRGN

CRITICAL

1

RES,MTL FILM,0,5%,0402,SM,LF

116S0004

1

NO_VREFMRGN

R2903

CRITICAL

9B4 73B3

0.1UF

20%

2

1

402

10V

CERM

C2903

VREFMRGN

MF-LF

402

5%

R2913

1 2

100K

1/16W

VREFMRGN

402

2

1

C2905

20%

10V

0.1UF

VREFMRGN

CERM

VREFMRGN

C2900

2.2UF

402-LF

CERM

6.3V

20%

2

1

C2901

10V

402

VREFMRGN

0.1UF

20%

CERM

43B3

U2900

3

7

VREFMRGN

1

2

4

10

5

8

6

9

DAC5574

MSOP

43A3

24C1

R2908

100K

MF-LF

21

5%

1/16W

402

VREFMRGN

0.1UF

CERM

402

2

1

C2904

VREFMRGN

10V

20%

15

3

4

5

1

2

6

7

9

12

13

14

16

10

11

17

8

QFN

VREFMRGN

PCA9557

U2901

1/16W

MF-LF

21

5%

402

VREFMRGN

100K

R2907

21

1/16W

5%

100K

VREFMRGN

MF-LF

402

R2901

MF-LF

21

1/16W

100K

402

5%

VREFMRGN

R2902

402

21

R2903

MF-LF

1/16W

200

1%

VREFMRGN

402

21

R2905

MF-LF

1/16W

200

1%

VREFMRGN

402

21

R2909

MF-LF

1/16W

200

1%

VREFMRGN

402

21

R2911

MF-LF

1/16W

200

1%

VREFMRGN

MAX4253

VREFMRGN

UCSP

U2902

A3

A2

A1

A4

B1

B4

VREFMRGN

MAX4253

UCSP

U2902

C3

C2

C1

C4

B1

B4

MAX4253

VREFMRGN

UCSP

U2903

A3

A2

A1

A4

B1

B4

C2902

VREFMRGN

0.1UF

2

20%

10V

1

402

CERM

A4

VREFMRGN

MAX4253

UCSP

U2904

A3

A2

A1

B1

B4

U2904

VREFMRGN

MAX4253

UCSP

C3

C2

C1

C4

B1

B4

1/16W

VREFMRGN

1%

MF-LF

100

402

R2912

1 2

MF-LF

1/16W

VREFMRGN

1%

402

100

R2914

1 2

VREFMRGN

100

1%

1/16W

MF-LF

402

R2910

1 2

100

1/16W

1%

402

VREFMRGN

MF-LF

R2906

1 2

VREFMRGN

MF-LF

1/16W

1%

100

402

R2904

1 2

VREFMRGN

MAX4253

UCSP

U2903

C3

C2

C1

C4

B1

B4

7C4 61D8

27B3

26B3

27D5

26D5

7D3

25B5

25A5

25B5

25A5

25B3

25C3

25D3

25B3

25C3

Apple A1278 Schematic RevC.0.0