Texas Instruments CD74HCT368M96, CD74HCT368M, CD74HCT368E, CD74HCT367M96, CD74HCT367M Datasheet
...
Data sheet acquired from Harris Semiconductor
/
j
SCHS181
November 1997
CD74HC367, CD74HCT367,
CD74HC368, CD74HCT368
High Speed CMOS Logic Hex Buffer/Line Driver,
Three-State Non-Inverting and Inverting
[ /Title
(CD74
HC367
,
CD74
HCT36
7,
CD74
HC368
,
CD74
HCT36
8)
Subect
(High
Speed
Features
• Buffered Inputs
• High Current Bus Driver Outputs
• Two Independent Three-State Enable Controls
• TypicalPropagation Delay t
C
= 15pF, TA = 25oC
L
PLH,tPHL
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 8ns at VCC=5V,
≤ 1µA at VOL, V
l
o
C to 125oC
OH
Description
The Harris CD74HC367, CD74HCT367, CD74HC368, and
CD74HCT368 silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers.
They have high drive current outputs which enable high speed
operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet
have speeds comparable to low power Schottky TTL circuits.
Both circuits are capable of driving up to 15 lowpower Schottky
inputs.
The CD74HC367 and CD74HCT367 are non-inverting buffers,
whereas the CD74HC368 and CD74HCT368 are inverting buffers. These devices havetwo output enables, one enable (OE1)
controls 4 gates and the other (OE2) controls the remaining 2
gates.
The CD74HCT367 and CD74HCT368 logic families are speed,
function and pin compatible with the standard 74LS logic family .
Ordering Information
CC
PART NUMBER
CD74HC367E -55 to 125 16 Ld PDIP E16.3
CD74HCT367E -55 to 125 16 Ld PDIP E16.3
CD74HCT368E -55 to 125 16 Ld PDIP E16.3
CD74HC367M -55 to 125 16 Ld SOIC M16.15
CD74HCT367M -55 to 125 16 Ld SOIC M16.15
CD74HC368M -55 to 125 16 Ld SOIC M16.15
CD74HCT368M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
TEMP. RANGE
(oC) PACKAGE PKG. NO.
Pinouts
CD74HC367, CD74HCT367 (PDIP, SOIC)
TOP VIEW
V
1
OE1
2
1A
1Y
3
2A
4
5
2Y
3A
6
7
3Y
GND
8
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
16
CC
15
OE2
14
6A
13
6Y
12
5A
5Y
11
10
4A
4Y
9
1
CD74HC368, CD74HCT368 (PDIP, SOIC)
1
OE1
2
1A
3
1Y
4
2A
5
2Y
3A
6
7
3Y
GND
8
TOP VIEW
V
16
CC
15
OE2
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
File Number 1538.1
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
Functional Diagrams
CD74HC367, CD74HCT367 CD74HC368, CD74HCT368
OE1
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
8
16
V
CC
15
OE2
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
OE1
1A
1Y
2A
2Y
3A
3Y
GND
1
2
3
4
5
6
7
8
16
V
CC
15
OE2
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
TRUTH TABLE
OUTPUTS
INPUTS
(Y)
OE A HC/HCT367 HC/HCT368
LLLH
LHHL
H X (Z) (Z)
NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance (OFF) State
2
Logic Diagram
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
V
CC
16
ONE OF SIX IDENTICAL CIRCUITS
2
1A
3
1Y
8
OE1
OE2
(NOTE)
GND
1
4
15
2A
3A
4A
5A
6A
6
10
12
14
5
2Y
7
3Y
9
4Y
11
5Y
13
6Y
NOTE: Inverter not included in HC/HCT367.
FIGURE 1. LOGIC DIAGRAM FOR THE HC/HCT367 AND HC/HCT368 (OUTPUTS FOR HC/HCT367 ARE COMPLEMENTS OF
THOSE SHOWN, i.e., 1Y, 2Y, ETC.)
3
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
PARAMETER SYMBOL
HC TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
V
IH
V
IL
V
OH
V
OL
I
I
I
CC
TEST
CONDITIONS
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
VCC (V)
o
C -40oC TO 85oC -55oC TO 125oC
25
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
VIH or
V
-0.02 2 1.9 - - 1.9 - 1.9 - V
IL
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
-6 4.5 3.98 - - 3.84 - 3.7 - V
-7.8 6 5.48 - - 5.34 - 5.2 - V
VIH or
V
0.02 2 - - 0.1 - 0.1 - 0.1 V
IL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
6 4.5 - - 0.26 - 0.33 - 0.4 V
7.8 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
UNITSV
4
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
DC Electrical Specifications (Continued)
TEST
CONDITIONS
PARAMETER SYMBOL
Three-State Leakage
I
OZ
Current
HCT TYPES
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IH
V
IL
V
OH
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
V
OL
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
Current
Additional Quiescent
Device Current Per
I
I
I
CC
∆I
CC
Input Pin: 1 Unit Load
(Note 4)
Three-State Leakage
Current
I
OZ
NOTE:
4. For dual-supply systems theoretical worst case (V
HCT Input Loading Table
INPUT UNIT LOADS
OE1 0.6
All Others 0.55
NOTE: Unit Load is ∆I
Specifications table, e.g., 360µA max at 25oC.
limit specified in DC Electrical
CC
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
VIL or
V
VO =
VCC or
IH
GND
- - 4.5 to
- - 4.5 to
VIH or
V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
IL
-4 4.5 3.98 - - 3.84 - 3.7 - V
VIH or
V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
IL
4 4.5 - - 0.26 - 0.33 - 0.4 V
VCC to
0 5.5 - - ±0.1 - ±1-±1µA
GND
VCC or
0 5.5 - - 8 - 80 - 160 µA
GND
V
CC
- 4.5 to
-2.1
VIL or
V
VO =
VCC or
IH
GND
o
C -40oC TO 85oC -55oC TO 125oC
25
(V)
V
CC
6--±0.5 - ±5.0 - ±10 µA
2-- 2 - 2 - V
5.5
- - 0.8 - 0.8 - 0.8 V
5.5
- 100 360 - 450 - 490 µA
5.5
5.5 - - ±0.5 - ±5.0 - ±10 µA
= 2.4V, VCC = 5.5V) specification is 1.8mA.
I
UNITSV
Switching Specifications Input t
PARAMETER SYMBOL
HC TYPES
Propagation Delay,
Data to Outputs
HC/HCT367
t
PLH
, t
PHLCL
, tf = 6ns
r
-55oC TO
TEST
o
25
C -40oC TO 85oC
CONDITIONS VCC (V)
= 50pF 2 - 105 130 160 ns
4.5 - 21 26 32 ns
6 - 18 24 27 ns
= 15pF 5 8 - - - ns
C
L
5
125oC
UNITSTYP MAX MAX MAX
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
Switching Specifications Input t
PARAMETER SYMBOL
Propagation Delay,
Data to Outputs
HC/HCT368
Propagation Delay,
Output Enable and Disable
to Outputs
Output Transition Time t
Input Capacitance C
Three-State Output
Capacitance
Power Dissipation
Capacitance
(Notes 5, 6)
HCT TYPES
Propagation Delay,
Data to Outputs
HC/HCT367
Propagation Delay,
Data to Outputs
HC/HCT368
Propagation Delay,
Output Enable and Disable
to Outputs
Output Transition Time t
Input Capacitance C
Three-State Capacitance C
Power Dissipation
Capacitance
(Notes 5, 6)
NOTES:
is used to determine the dynamic power consumption, per buffer.
5. C
PD
6. PD= V
2
fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CC
t
PLH
t
PLH
TLH
t
PLH
t
PLH
t
PLH
TLH
, t
PHLCL
, t
PHLCL
, t
THLCL
I
C
O
C
PD
, t
PHLCL
, t
PHLCL
, t
PHLCL
, t
THLCL
IN
O
C
PD
, tf = 6ns (Continued)
r
-55oC TO
TEST
CONDITIONS V
CC
(V)
o
C -40oC TO 85oC
25
= 50pF 2 - 105 130 160 ns
4.5 - 21 26 32 ns
6 - 18 24 27 ns
= 15pF 5 9 - - - ns
C
L
= 50pF 2 - 150 190 225 ns
4.5 - 30 38 45 ns
6 - 26 33 38 ns
= 15pF 5 12 - - - ns
C
L
= 50pF 2 - 60 75 90 ns
4.5 - 12 15 18 ns
6 - 10 13 15 ns
---1010 10pF
---2020 20pF
- 5 40 - - - pF
= 50pF 4.5 - 25 31 38 ns
C
= 15pF 5 9 - - - ns
L
= 50pF 4.5 - 30 38 45 ns
= 15pF 5 11 - - - ns
C
L
= 50pF 4.5 - 35 44 53 ns
= 15pF 5 14 - - - ns
C
L
= 50pF 4.5 - 12 15 18 ns
---1010 10pF
---2020 20pF
- 5 42 - - - pF
125oC
UNITSTYP MAX MAX MAX
6
CD74HC367, CD74HCT367, CD74HC368, CD74HCT368
Test Circuits and Waveforms
tr = 6ns tf = 6ns
INPUT
90%
50%
10%
V
CC
GND
tr = 6ns
INPUT
2.7V
1.3V
0.3V
= 6ns
t
f
3V
GND
t
INVERTING
OUTPUT
THL
t
PHL
t
PLH
90%
50%
10%
t
TLH
FIGURE 2. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
6ns 6ns
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
50%
t
t
OUTPUTS
ENABLED
PLZ
PHZ
10%
90%
90%
10%
t
PZL
t
PZH
OUTPUTS
DISABLED
50%
50%
FIGURE 4. HCTHREE-STATE PROPAGATIONDELAY
WAVEFORM
V
CC
GND
OUTPUTS
ENABLED
t
INVERTING
OUTPUT
THL
t
PHL
t
PLH
1.3V
10%
90%
t
TLH
FIGURE 3. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
0.3
t
t
6ns
PZL
1.3V
PZH
1.3V
OUTPUTS
ENABLED
t
r
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
t
t
OUTPUTS
ENABLED
6ns t
PLZ
PHZ
10%
90%
f
2.7
1.3
OUTPUTS
DISABLED
FIGURE 5. HCTTHREE-STATE PROPAGATION DELAY
WAVEFORM
3V
GND
NOTE: Open drain waveforms t
VCC, CL = 50pF.
FIGURE 6. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT
TIED HIGH
and t
PLZ
OTHER
INPUTS
OR LOW
OUTPUT
DISABLE
PZL
IC WITH
THREE-
STATE
OUTPUT
OUTPUT
= 1kΩ
R
L
C
L
50pF
VCC FOR t
GND FOR t
PLZ
PHZ
AND t
AND t
PZL
PZH
are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto
7
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