Sony ICX086AK Datasheet

ICX086AK

Diagonal 4.5mm (Type 1/4) CCD Image Sensor for NTSC Color Video Cameras

Description
The ICX086AK is an interline CCD solid-state image				14 pin DIP (Plastic)
sensor suitable for NTSC color video cameras. High
sensitivity is achieved through the use of Ye, Cy, Mg,
and G complementary color mosaic filters and through
the adoption of HAD (Hole-Accumulation Diode)
sensors.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
The package is a 10mm-square 14-pin DIP (Plastic).					Pin 1
					1
Features
• High sensitivity and low dark current				V
• Horizontal register:	3.3 to 5.0V drive
• No voltage adjustment					12
(Reset gate and substrate bias are not adjusted.)				2
					25
• Low smear				H
				Pin 8
• Excellent antiblooming characteristics
• Continuous variable-speed shutter				Optical black position
• Ye, Cy, Mg, and G complementary color mosaic filters on chip				(Top View)
Device Structure
• Interline CCD image sensor
• Image size:		Diagonal 4.5mm (Type 1/4)
• Number of effective pixels:		510 (H) × 492 (V) approx. 250K pixels
• Total number of pixels:		537 (H) × 505 (V) approx. 270K pixels
• Chip size:		4.47mm (H) × 3.80mm (V)
• Unit cell size:		7.15µm (H) × 5.55µm (V)
• Optical black:		Horizontal (H) direction: Front		2 pixels, rear 25 pixels
		Vertical (V) direction:	Front 12 pixels, rear 1 pixel
• Number of dummy bits:		Horizontal 16
		Vertical 1 (even fields only)
• Substrate material:		Silicon

Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.

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E94820E99

ICX086AK

Block Diagram and Pin Configuration

(Top View)

Pin Description

VOUT	DNG		CN	φV1	φV2	φV3	φV4
7	6		5	4	3	2	1
		rReegsti	Cy	Ye	Cy	Ye
			G	Mg	G	Mg
		leacrtiV	Cy	Ye	Cy	Ye
			G	Mg	G	Mg
			Cy	Ye	Cy	Ye
			Mg	G	Mg	G	Note)
				Horizontal Register
							Note)	: Photo sensor
8	9		10	11	12	13	14
VDD	DNG		BUS φ	VL	GR	φH1	φH2

Pin No.	Symbol	Description	Pin No.	Symbol	Description
1	Vφ4	Vertical register transfer clock	8	VDD	Supply voltage
2	Vφ3	Vertical register transfer clock	9	GND	GND
3	Vφ2	Vertical register transfer clock	10	φSUB	Substrate clock
4	Vφ1	Vertical register transfer clock	11	VL	Protective transistor bias
5	NC		12	RG	Reset gate clock
6	GND	GND	13	Hφ1	Horizontal register transfer clock
7	VOUT	Signal output	14	Hφ2	Horizontal register transfer clock

Absolute Maximum Ratings

	Item	Ratings	Unit Remarks
Substrate clock φSUB – GND		–0.3 to +40	V
Supply voltage	VDD, VOUT – GND	–0.3 to +18	V
	VDD, VOUT – φSUB	–30 to +9	V
Clock input voltage	Vφ1, Vφ2, Vφ3, Vφ4 – GND	–15 to +16	V
	Vφ1, Vφ2, Vφ3, Vφ4 – φSUB	to +10	V
Voltage difference between vertical clock input pins		to +15	V	1
Voltage difference between horizontal clock input pins		to +16	V
Hφ1, Hφ2 – Vφ4		–16 to +16	V
Hφ1, Hφ2 – GND		–10 to +15	V
Hφ1, Hφ2 – φSUB		–55 to +10	V
VL – φSUB		–65 to +0.3	V
Vφ1, Vφ3, VDD, VOUT – VL		–0.3 to +27.5	V
RG – GND		–0.3 to +20.5	V
Vφ2, Vφ4, Hφ1, Hφ2, GND – VL		–0.3 to +17.5	V
Storage temperature		–30 to +80	°C
Operating temperature		–10 to +60	°C

1 +24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.

– 2 –

ICX086AK

Bias Conditions

Item	Symbol	Min.	Typ.	Max.	Unit Remarks
Supply voltage	VDD	14.55	15.0	15.45	V
Protective transistor bias	VL		1
Substrate clock	φSUB		2

1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used.

2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.

DC Characteristics

Item

Symbol

Min.

Typ.

Max.

Unit

Remarks

Supply current

IDD

4

6

mA

Clock Voltage Conditions

Item

Symbol

Min.

Typ.

Max.

Unit

Waveform

Remarks

diagram

Readout clock voltage

VVT

14.55

15.0

15.45

V

1

VVH1, VVH2

–0.05

0

0.05

V

2

VVH = (VVH1 + VVH2)/2

VVH3, VVH4

–0.2

0

0.05

V

2

VVL1, VVL2,

–8.0

–7.5

–7.0

V

2

VVL = (VVL3 + VVL4)/2

VVL3, VVL4

VφV

6.8

7.5

8.05

V

2

VφV = VVHn – VVLn (n = 1 to 4)

Vertical transfer clock

VVH3 – VVH

–0.25

0.1

V

2

voltage

VVH4 – VVH

–0.25

0.1

V

2

VVHH

0.3

V

2

High-level coupling

VVHL

0.3

V

2

High-level coupling

VVLH

0.3

V

2

Low-level coupling

VVLL

0.3

V

2

Low-level coupling

Horizontal transfer

VφH

3.0

5.0

5.25

V

3

clock voltage

VHL

–0.05

0

0.05

V

3

VφRG

4.5

5.0

5.5

V

4

Input through 0.01µF

capacitance

Reset gate clock

VRGLH – VRGLL

0.8

V

4

Low-level coupling

voltage

VRGH

VDD +

VDD +

VDD +

V

4

0.3

0.6

0.9

Substrate clock voltage

VφSUB

21.5

22.5

23.5

V

5

– 3 –

ICX086AK

Clock Equivalent Circuit Constant

Item

Symbol

Min.

Typ.

Max.

Unit

Remarks

Capacitance between vertical transfer

CφV1, CφV3

680

pF

clock and GND

CφV2, CφV4

820

pF

CφV12, CφV34

180

pF

Capacitance between vertical transfer

CφV23, CφV41

150

pF

clocks

CφV13, CφV24

62

pF

Capacitance between horizontal

CφH1, CφH2

30

pF

transfer clock and GND

Capacitance between horizontal

CφHH

18

pF

transfer clocks

Capacitance between reset gate clock

CφRG

3

pF

and GND

Capacitance between substrate clock

CφSUB

190

pF

and GND

Vertical transfer clock series resistor

R1, R2, R3, R4

33

Ω

Vertical transfer clock ground resistor

RGND

15

Ω

Horizontal transfer clock series resistor

RφH

24

Ω

Reset gate clock series resistor

RφRG

40

Ω

Vφ1

Vφ2

CφV12

R2

R1

RφH

RφH

Hφ1

Hφ2

CφV1

CφV2

CφHH

CφV41

CφV23

CφH1

CφH2

CφV24

CφV4 RGND CφV3

CφV13

R4

R3

CφV34

Vφ4

Vφ3

Vertical transfer clock equivalent circuit

Horizontal transfer clock equivalent circuit

RφRG

RGφ

CφRG

Reset gate clock equivalent circuit

– 4 –

ICX086AK

Drive Clock Waveform Conditions

(1) Readout clock waveform

100%
90%
	II		II
				φM
		VVT		φM
10%				2
0%	tr	twh	tf	0V

(2) Vertical transfer clock waveform

Vφ1

VVH1	VVHH	VVH	VVHH
		VVHL

VVHL

VVL1

VVLH

VVLL

VVL

Vφ2

VVHH VVHH

VVH

VVHL

VVH2 VVHL

VVLH

VVL2

VVLL

VVL

VVH = (VVH1 + VVH2)/2

VVL = (VVL3 + VVL4)/2

VφV = VVHn – VVLn (n = 1 to 4)

Vφ3

VVHH

VVHH

VVH

VVHL

VVHL

VVH3

VVL3

VVLH

VVLL

VVL

Vφ4

VVHH VVHH

VVH

VVHL	VVHL
	VVH4

VVLH

	VVLL
VVL4	VVL

– 5 –

ICX086AK

(3) Horizontal transfer clock waveform

tr

twh

tf

90%

VφH

twl

10%

VHL

(4) Reset gate clock waveform

tr

twh

tf

VRGH

twl

Point A

RG waveform

VφRG

VRGL + 0.5V

VRGLH

VRGL

VRGLL

Hφ1 waveform

10%

VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and

VRGLL.

VRGL = (VRGLH + VRGLL)/2

Assuming VRGH is the minimum value during the interval twh, then:

VφRG = VRGH – VRGL

(5) Substrate clock waveform

100%

90%

				VφSUB
		10%
	VSUB	0%	tr	twh	tf
	(A bias generated within the CCD)

φM

φM

2

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