Motorola SN54LS164J, SN74LS164N, SN74LS164D Datasheet
5-1
FAST AND LS TTL DATA
SERIAL-IN PARALLEL-OUT
SHIFT REGISTER
The SN54/74LS164 is a high speed 8-Bit Serial-In Parallel-Out Shift Register. Serial data is entered through a 2-Input AND gate synchronous with the
LOW to HIGH transition of the clock. The device features an asynchronous
Master Reset which clears the register setting all outputs LOW independent of
the clock. It utilizes the Schottky diode clamped process to achieve high
speeds and is fully compatible with all Motorola TTL products.
• Typical Shift Frequency of 35 MHz
• Asynchronous Master Reset
• Gated Serial Data Input
• Fully Synchronous Data Transfers
• Input Clamp Diodes Limit High Speed Termination Effects
• ESD > 3500 Volts
CONNECTION DIAGRAM DIP (TOP VIEW)
14 13 12 11 10 9
1 2 3 4 5 6
8
7
V
CCQ7Q6Q5Q4
MR
CP
A B Q0Q1Q2Q3GND
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
PIN NAMES LOADING (Note a)
HIGH
LOW
A, B
CP
MR
Q0–Q
7
Data Inputs
Clock (Active HIGH Going Edge) Input
Master Reset (Active LOW) Input
Outputs (Note b)
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 (2.5) U.L.
NOTES:
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW.
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74)
Temperature Ranges.
SN54/74LS164
SERIAL-IN PARALLEL-OUT
SHIFT REGISTER
LOW POWER SCHOTTKY
J SUFFIX
CERAMIC
CASE 632-08
N SUFFIX
PLASTIC
CASE 646-06
14
1
14
1
ORDERING INFORMATION
SN54LSXXXJ Ceramic
SN74LSXXXN Plastic
SN74LSXXXD SOIC
14
1
D SUFFIX
SOIC
CASE 751A-02
LOGIC SYMBOL
1
2
8
9 3 4 5 6 10 11 12 13
A
B
CP
LS164
8-BIT SHIFT REGISTER
MR Q0Q1Q2Q3Q4Q5Q6Q
7
VCC = PIN 14
GND = PIN 7
5-2
FAST AND LS TTL DATA
SN54/74LS164
LOGIC DIAGRAM
Q
6
Q
7
A
B
Q
0
Q
1
Q
3
Q
2
Q
5
Q
4
MR
CP
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
D Q
C
D
63 4 5 11 1210 13
VCC = PIN 14
GND = PIN 7
= PIN NUMBERS
1
2
8
9
FUNCTIONAL DESCRIPTION
The LS164 is an edge-triggered 8-bit shift register with serial data entry and an output from each of the eight stages. Data
is entered serially through one of two inputs (A or B); either of
these inputs can be used as an active HIGH Enable for data
entry through the other input. An unused input must be tied
HIGH, or both inputs connected together.
Each LOW-to-HIGH transition on the Clock (CP) input shifts
data one place to the right and enters into Q0 the logical AND
of the two data inputs (A•B) that existed before the rising clock
edge. A LOW level on the Master Reset (MR
) input overrides
all other inputs and clears the register asynchronously , forcing
all Q outputs LOW.
MODE SELECT — TRUTH TABLE
OPERATING
INPUTS OUTPUTS
MODE
MR A B Q
0
Q1–Q
7
Reset (Clear) L X X L L – L
H I I L q0– q
6
Shift H I h L q0– q
6
H h I L q0– q
6
H h h H q0– q
6
L (l) = LOW Voltage Levels
H (h) = HIGH Voltage Levels
X = Don’t Care
qn = Lower case letters indicate the state of the referenced input or output one
qn = set-up time prior to the LOW to HIGH clock transition.
GUARANTEED OPERATING RANGES
Symbol Parameter Min Typ Max Unit
V
CC
Supply Voltage 54
74
4.5
4.75
5.0
5.0
5.5
5.25
V
T
A
Operating Ambient Temperature Range 54
74
–55
0
25
25
125
70
°C
I
OH
Output Current — High 54, 74 –0.4 mA
I
OL
Output Current — Low 54
74
4.0
8.0
mA
Loading...