Name: Compal LA-7322P PBL60
Brand: Compal
SKU: 3831688
Rating: 4 (1 reviews)

A

1 1

B

C

D

E

Compal Confidential

2 2

PBL60 Schematics Document

AMD APU Zacate-FT1 + FCH Hudson-M1 + GPU Seymour XT-M2

3 3

2010-02-15

REV:1.0

4 4

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

P01-Cover Page

LA-7322P

147Thursday, February 17, 2011

E

1.0

of

A

B

C

D

E

Compal confidential

File Name : LA-7322P

AMD Seymour-XT

DDR3 VRAM

1 1

512M/1G 64*16/128*16 *4

page 17 ~ 24

LVDS Conn.

HDMI Conn.

CRT Conn.

page 10

page 11

page 10

PCI-E GPP x4 GEN2

LVDS(UMA & PX)

HDMI(UMA & PX)

CRT(UMA & PX)

AMD Brazos APU

FT1 BGA 413-Ball 19mm x 19mm

page 5,6,7

Memory BUS(DDRIII)

Single Channel

1.5V DDRIII

204pin DDRIII-SO-DIMM X2

BANK 0, 1, 2, 3

page 8,9

UMI Gen.1 x4

2.5GT/s per lane

SATA

2 2

PCI-E 2.0 x1

Hudson M1

BGA 605-Ball 23mm x 23mm

Port 0Port 1

Mini Card-1 WLAN (With Bluetooth)

page 28

3 3

LAN(GbE) RTL8111E

page 25

RJ45

page 25

page 12 ~ 16

LPC BUS

AZALIA

USB2.0

ENE KB930

page 30

LS-7326P Power BD

page 31 page 31page 30 page 27

SPI ROM

Int.KBDTouch Pad

Port 0

Port 1

Audio Codec ALC269

page 26

Port 0

Port 1

Port 5

Port 2

Port 3

Port 4

SATA HDD Conn.

SATA ODD Conn.

USB Conn.

page 32

USB Conn. (LS-7322P)

Camera

page 10

Mini Card WLAN (With Bluetooth)

page 28

Card Reader RTS5137

page 29

2Channel Speaker

page 26

Audio Jacks X 2 (Headphone, MIC)

page 26

DMIC

page 10

LS-7322P Audio BD

4 4

Thermal Sensor

page 18

A

B

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

Compal Electronics, Inc.

P02-Block Diagrams

LA-7322P

247Thursday, February 17, 2011

E

of

1.0

A

Voltage Rails

Power Plane Description

VIN

B+

+APU_CORE

1 1

2 2

+APU_CORE_NB 1.0V switched power rail ON OFF

+1.5V

+0.75VS 0.75VS swit ched power rail for DDR termina tor

+1.0VS

+1.1VS 1.1VS switched power rail ON OFF OFF

+1.8VS 1.8V switched power rail

+3VALW

+3V_LAN 3.3V power ra il for LAN ON ON(WOL) OFF

+3VS

+5VALW

+5VS

+VSB VSB always on power rail ON ON*

+RTCVCC RTC power

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OF F.

SMBUS Control Table

EC_SMB_CK1 EC_SMB_DA1

EC_SMB_CK2 EC_SMB_DA2

FCH_SMCLK0 FCH_SMDAT0

FCH_SMCLK3 FCH_SMDAT3

Adapter power supply ( 19V)

AC or battery power rail for power circuit.

Core voltage for CPU (0.7-1.2V)

1.5V power rail for CPU VDDIO and DDRIII

1.0V switched power rail for NB VDDC & VGA

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

SOURCE

KB930

FCH (+3VS)

FCH (+3VALW)

MIINI1 BATT SODIMM

X

V

X

V

XX

APU FCH

X

VV

V

B

S1 S3 S5

N/A N/A N/A

ON OFF

OFF

ON

OFF

ON OFF OFF

OFF

ON

ON ON*

ON

OFF

ON

OFF

ON

ON ON*ON+1.1VALW 1.1V always on power rail

XX

X

XX

V

X

N/AN/AN/A

OFF

ON*

OFFON

ONON

VRAM

X

V

X

XX

C

FCH Hudson-M1 USB Port List

USB1.1

Port0

Port1

USB2.0

Port0

Port1

Port2

Port3

Port4

Port5

Port6

Port7

Port8

Port9

Port10

Port11

Port12

Port13

SCL0, SDA0 (Primary SMBUS in the S0 domain) SCL1, SDA1 (Secondary SMBUS supporting ASF) SCL2, SDA2 (Primary SMBUS in the S5 domain) SCL3, SDA3 (Primary low-voltage SBMBUS for Processor TSI) SCL4, SDA4 (Primary SMBUS in the S5 domain)

NC

JUSB1

JUSB2

Camera

JMINI(WLAN)

Card Reader

JUSB3

NC

Brazos PCIE Port List

PCIE0

APUFCH

PCIE1

PCIE2

PCIE3

PCIE0

PCIE1

PCIE2

PCIE3

GPU PCIE x4

LAN

WLAN

NC

D

E

FCH Hudson-M1 SATA Port List

SATA0

SATA1

SATA2

SATA3

SATA4

SATA5

HDD

ODD

NC

3 3

L01 :

L02 :

L03 :

L04 :

Symbol Note :

BOM Structure

15G@: 1.5G CPU (E240) 16G@: 1.6G CPU (E350) 1G@ : 1G CPU (C50) UMA@ : APU output.

4 4

VGA@ : GPU used. LS@ : Level shift used.

: means Digital Ground

: means Analog Ground

L05 :

L06 :

L07 :

L08 :

L09 :

16G@/VGA@/LS@/X76@L03

16G@/UMA@/LS@

15G@/VGA@/LS@/X76@L03

15G@/UMA@/LS@

16G@/VGA@/LS@/X76@L01

15G@/VGA@/LS@/X76@L01

1G@/VGA@/LS@/X76@L03

1G@/UMA@/LS@

1G@/VGA@/LS@/X76@L01

X76@L01 :VRAM 1G. X76@L03 :VRAM 512M.

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

P03-Notes List

LA-7322P

347Thursday, February 17, 2011

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5

Power-Up/Down Sequence

1. All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up sequence, though a shorter ramp-up duration is preferred.

2. VDDR3 should ramp-up before or simultaneously with VDDC.

3. For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before

D D

DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.

4. The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and VDD_CT have ramped up.

5.VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to ramp-up (or vice versa).)

4

3

2

1

tŝƚŚŽƵƚKŽƉƚŝŽŶ

Wͺ'W/KϬ>ŽǁͲхZĞƐĞƚĚ'Wh,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ Wͺ'W/Kϭ>ŽǁͲхĚ'WhWŽǁĞƌK&&,ŝŐŚͲхĚ'WhWŽǁĞƌKE

KŽƉƚŝŽŶ

Wͺ'W/KϬ,ŝŐŚͲхEŽƌŵĂůŽƉĞƌĂƚŝŽŶ;Ě'WhŝƐŶŽƚƌĞƐĞƚŽŶKŵŽĚĞͿ Wͺ'W/Kϭ>ŽǁͲхĚ'WhWŽǁĞƌK&&,ŝŐŚͲхĚ'WhWŽǁĞƌKE;ĂůǁĂǇƐ,ŝŐŚͿ

Ě'WhWŽǁĞƌWŝŶƐ DĂǆĐƵƌƌĞŶƚ

W/ͺWsW/ͺsZd^ssZϰsͺd WͺWsW΀&΁ͺsϭϴW΀΁ͺWs W΀΁ͺsϭϴssϭ/ϮsYsϮ/ W>>ͺWsDWsϭϴĂŶĚ^Wsϭϴ

W΀&΁ͺsϭϬW΀΁ͺsϭϬW>>ͺsĂŶĚ

sŽůƚĂŐĞ

ϭϴs

ϭϬs

WyϯϬ

K&&

KDŽĚĞ

KE

ϭϲϳϵŵ

ϱϳϱŵ

^WsϭϬ

VDDR3(3.3VSG)

Note: Do not drive any IOs before VDDR3 is ramped up.

W/ͺs

sZϯĂŶĚϮs

/&ͺs;ĐƵƌƌĞŶƚĐŽŶƐƵŵƉƚŝŽŶсϱϱŵΛϭϬsŝŶ

PCIE_VDDC(1.0V)

KŵŽĚĞͿ

sZϭ

C C

VDDR1(1.5VSG)

ss/

ϭϬs

ϯϯs

^ĂŵĞĂƐ s

ϭϱs

ϭϭϮs

K&&

KE

KE ^ĂŵĞĂƐ W/ͺs

K&&

Ϯ

ϭϵϬŵ

ϳϬŵ

Ϯϴ

ϭϮϵ

VDDC/VDDCI(1.12V)

VDD_CT(1.8V)

ŝ'Wh

PERSTb

REFCLK

B B

Straps Reset

Straps Valid

PE_GPIO0 PE_EN

Ě'Wh

BIF_VDDC

PE_GPIO1

нϯϯs>t

нϭϬs

MOS

Regulator

нϯϯs^'

ϭ

нϭϬs^'

Ϯ

PX_mode

нϭϱs

K^ǁŝƚĐŚ

SI4800

нϭϱs^'

ϯ

Global ASIC Reset

н

нϭϴs

T4+16clock

A A

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

2010/06/30 2012/06/30

3

Compal Secret Data

Deciphered Date

SI4800

2

нϭϴs^'

ϱ

Compal Electronics, Inc.

Title

Size Document Number Rev

B

Date: Sheet of

Compal Electronics, Inc.

LA-7322P

Regulator

P04-dGPU Block Diagram

ϰ

1

нs'ͺKZ

PWRGOOD

447Thursday, February 17, 2011

1.0

5

4

3

2

1

+1.8VS

APU_HDMI_TX2P11

APU_RST#12 APU_PWRGD12

APU_HDMI_TX2N11

APU_HDMI_TX1P11

APU_HDMI_TX1N11

APU_HDMI_TX0P11

APU_HDMI_TX0N11

APU_HDMI_CLKP11

APU_HDMI_CLKN11

APU_TXOUT2+10 APU_TXOUT2-10

APU_TXOUT1+10 APU_TXOUT1-10

APU_TXOUT0+10 APU_TXOUT0-10

APU_TXCLK+10 APU_TXCLK-10

T93PADT93PAD T94PADT94PAD

Close to APU

APU_SIC APU_SID

APU_PROCHOT# APU_THERMTRIP# APU_ALERT#_R

APU_TDI APU_TDO APU_TCK APU_TMS APU_TRST# APU_DBRDY APU_DBREQ#

T77PADT77PAD

U22

16G@U22

16G@

ZACATE ZM161032B2238 1.6G BGA 413P

U22

1G@U22

1G@

ONTARIO CMC50AFPB22GT 1G

R399 1K_0402_5%R399 1K_0402_5%

1 2

R400 1K_0402_5%R400 1K_0402_5%

D D

C C

B B

1 2

R142 300_0402_5%

R142 300_0402_5% R401 300_0402_5%R401 300_0402_5% R402 510_0402_1%R402 510_0402_1% R141 1K_0402_5%R141 1K_0402_5%

+3VS

R410 1K_0402_5%R410 1K_0402_5%

R411 1K_0402_5%R411 1K_0402_5%

R143 1K_0402_5%R143 1K_0402_5%

R414 1K_0402_5%R414 1K_0402_5%

APU_THERMTRIP#

If FCH internal pull-up disabled, level-shifter could be deleted. Need BIOS to disable internal pull-up!!

1 2 1 2

C237 0.01U_0402_25V7K@C237 0.01U_0402_25V7K@

1 2

C238 0.01U_0402_25V7K@C238 0.01U_0402_25V7K@

1 2

1K_0402_5%

12 12

R425

APU_SVC APU_SVD APU_RST# APU_PWRGD TEST_25_L TEST36

APU_RST#

APU_PWRGD

APU_PROCHOT#

APU_ALERT#_R

APU_SIC

APU_SID

+3VS

12

R424

R424 10K_0402_5%

10K_0402_5%

@

B

2

1 2

R427 0_0402_5%R427 0_0402_5%

Q79

E

3 1

C

MMBT3904_NL_SOT23-3

1 2

EC_THERM#30

FCH_PROCHOT#12

H_THERMTRIP# 13

APU_CLKP12 APU_CLKN12

APU_DISP_CLKP12 APU_DISP_CLKN12

APU_SVC43

APU_SVD43

R169 0_0402_5%R169 0_0402_5%

1 2

R168 0_0402_5%@R168 0_0402_5%@

1 2

APU_VDDNB_RUN_FB_H43 APU_VDD0_RUN_FB_H43

APU_VDD0_RUN_FB_L43

CPU TSI interface level shift

@

C236 0.1U_0402_10V7K

@

R428

1 2

+3VS

31.6K_0402_1%

A A

1 2

@

R160

1 2

30K_0402_1%

G

2

EC_SMB_DAAPU_SID

13

D

S

D

S

@

Q22

BSH111 1N_SOT23-3

R431 0_0402_5%R431 0_0402_5%

1 2

G

2

EC_SMB_CKAPU_SIC

13

D

S

D

S

@

Q23

BSH111 1N_SOT23-3

R434 0_0402_5%R434 0_0402_5%

1 2

5

BSH111, the Vgs is: min = 0.4V Typ = 1.0V Max = 1.3V

1.607V for Gate

@

1 2

R429 0_0402_5%

1 2

R430 0_0402_5%R430 0_0402_5%

@

1 2

R432 0_0402_5%

1 2

R433 0_0402_5%R433 0_0402_5%

FDV301N, the Vgs is: min = 0.65V Typ = 0.85V Max = 1.5V

If use level shift, EC_SMB need pull up (pop R747 & R748)

FCH_SID

EC_SMB_DA2

FCH_SIC

EC_SMB_CK2

FCH_SID 13

EC_SMB_DA2 18,30

FCH_SIC 13

EC_SMB_CK2 18,30

4

T0 FCH

TO EC

T0 FCH

TO EC

U22B

A8

TDP1_TXP0

B8

TDP1_TXN0

B9

TDP1_TXP1

A9

TDP1_TXN1

D10

TDP1_TXP2

C10

TDP1_TXN2

A10

TDP1_TXP3

B10

TDP1_TXN3

B5

LTDP0_TXP0

A5

LTDP0_TXN0

D6

LTDP0_TXP1

C6

LTDP0_TXN1

A6

LTDP0_TXP2

B6

LTDP0_TXN2

D8

LTDP0_TXP3

C8

LTDP0_TXN3

V2

CLKIN_H

V1

CLKIN_L

D2

DISP_CLKIN_H

D1

DISP_CLKIN_L

J1

SVC

J2

SVD

P3

SIC

P4

SID

T3

RESET_L

T4

PWROK

U1

PROCHOT_L

U2

THERMTRIP_L

T2

ALERT_L

N2

TDI

N1

TDO

P1

TCK

P2

TMS

M4

TRST_L

M3

DBRDY

M1

DBREQ_L

F4

VDDCR_NB_SENSE

G1

VDDCR_CPU_SENSE

F3

VDDIO_MEM_S_SENSE

F1

VSS_SENSE

B4

RSVD_1

W11

RSVD_2

V5

RSVD_3

ONTARIO-2M161000-1.6G_BGA413

15G@

DISPLAYPORT 1

DISPLAYPORT 0

CLK

SER

JTAG CTRL

DP MISC

VGA DAC

TEST

DP_ZVSS

DP_BLON

DP_DIGON

DP_VARY_BL

TDP1_AUXP

TDP1_AUXN

TDP1_HPD

LTDP0_AUXP LTDP0_AUXN

LTDP0_HPD

DAC_RED

DAC_REDB

DAC_GREEN

DAC_GREENB

DAC_BLUE

DAC_BLUEB

DAC_HSYNC DAC_VSYNC

DAC_SCL DAC_SDA

DAC_ZVSS

TEST4 TEST5

TEST6 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19

TEST25_H

TEST25_L

TEST28_H

TEST28_L

TEST31

TEST33_H

TEST33_L

TEST34_H

TEST34_L

TEST35 TEST36 TEST37

TEST38

DMAACTIVE_L

R398 150_0402_1%R398 150_0402_1%

1 2

H3

G2 H2 H1

APU_HDMI_CLK

B2

APU_HDMI_DATA

C2

C1

APU_LCD_CLK

A3

APU_LCD_DATA

B3

R406 100K_0402_5%R406 100K_0402_5%

D3

1 2

C12

R407 150_0402_1%R407 150_0402_1%

D13 A12 B12 A13 B13

E1 E2

F2 D4

D12

R1 R2 R6 T5 E4 K4 L1 L2 M2 K1 K2 L5 M5 M21 J18 J19 U15 T15 H4 N5 R5

K3 T1

1 2

R408 150_0402_1%R408 150_0402_1%

1 2

R409 150_0402_1%R409 150_0402_1%

1 2

R144 499_0402_1%R144 499_0402_1%

1 2

T66

PAD

T67

PAD

T68

PAD

TEST15

TEST18 TEST19 TEST25_H TEST_25_L

TEST31 TEST33_H TEST33_L

TEST35 TEST36 TEST37

C639 0.1U_0402_16V4Z

PAD

R415 1K_0402_5%@R415 1K_0402_5%@

R416 1K_0402_5%R416 1K_0402_5% R417 1K_0402_5%R417 1K_0402_5% R418 510_0402_1%R418 510_0402_1%

T73

PAD

C516 0.1U_0402_16V4ZC516 0.1U_0402_16V4Z

1 2

C517 0.1U_0402_16V4ZC517 0.1U_0402_16V4Z

Delete Test point for layout limitation 20100917

1 2

@

R423 1K_0402_5%R423 1K_0402_5%

1 2

R422 1K_0402_5%@R422 1K_0402_5%@

R958 1K_0402_5%R958 1K_0402_5%

T76

PAD

1 2

1 2 1 2 1 2

1 2

AMD Debug

+1.8VS +1.8VS

R842

1K_0402_5%

1 2

APU_TRST#

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30 2012/06/30

R846

R847 10K_0402_5%R847 10K_0402_5%

R176 10K_0402_5%R176 10K_0402_5%

R177 10K_0402_5%R177 10K_0402_5%

APU_TRST#_R

1 2

0_0402_5%

12

Compal Secret Data

Deciphered Date

JHDT1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

SAMTE_ASP-136446-07-B

CONN@

2

APU_ENBKL 10 APU_ENVDD 10 APU_BLPWM 10

APU_HDMI_CLK 11

APU_HDMI_DATA 11

APU_HDMI_HPD 11

APU_LCD_CLK 10 APU_LCD_DATA 10

+5VS

APU_CRT_R 10

APU_CRT_G 10

APU_CRT_B 10

APU_CRT_HSYNC 10 APU_CRT_VSYNC 10

APU_CRT_DDC_SCL 10 APU_CRT_DDC_SDA 10

Close to U22

ALLOW_STOP# 12

+1.8VS

2

4

6

8

10

12

14

16

18

20

R420 51_0402_1%R420 51_0402_1%

1 2

R421 51_0402_1%R421 51_0402_1%

1 2

+1.8VS

APU_TCK

APU_TMS

APU_TDI

APU_TDO

APU_PWRGD

APU_RST#

APU_DBRDY

APU_DBREQ#

J108_PLLTST0

J108_PLLTST1

R843 1K_0402_5%R843 1K_0402_5%

R840 1K_0402_5%R840 1K_0402_5%

R798 1K_0402_5%R798 1K_0402_5%

R178 300_0402_5%R178 300_0402_5%

R799 0_0402_5%R799 0_0402_5%

R863 0_0402_5%R863 0_0402_5%

12

1 2

+1.8VS

TEST19

TEST18

Please be noted about TEST_18 and TEST_19

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

P05-FT1 CTRL/DP/CRT

LA-7322P

547Thursday, February 17, 2011

1

of

1.0

A

U22E

DDR_A_MA0 DDR_A_MA1 DDR_A_MA2 DDR_A_MA3 DDR_A_MA4 DDR_A_MA5 DDR_A_MA6

4 4

3 3

2 2

DDR_A_MA7 DDR_A_MA8 DDR_A_MA9 DDR_A_MA10 DDR_A_MA11 DDR_A_MA12 DDR_A_MA13 DDR_A_MA14 DDR_A_MA15

DDR_A_BS08,9 DDR_A_BS18,9 DDR_A_BS28,9

DDR_A_DQS08,9

DDR_A_DQS#08,9

DDR_A_DQS18,9

DDR_A_DQS#18,9

DDR_A_DQS28,9

DDR_A_DQS#28,9

DDR_A_DQS38,9

DDR_A_DQS#38,9

DDR_A_DQS48,9

DDR_A_DQS#48,9

DDR_A_DQS58,9

DDR_A_DQS#58,9

DDR_A_DQS68,9

DDR_A_DQS#68,9

DDR_A_DQS78,9

DDR_A_DQS#78,9

DDR_A_CLK09 DDR_A_CLK#09 DDR_A_CLK19 DDR_A_CLK#19 DDR_B_CLK28 DDR_B_CLK#28 DDR_B_CLK38 DDR_B_CLK#38

DDR_RST#8,9

DDR_EVENT#8,9

DDR_CKE08,9 DDR_CKE18,9

DDR_A_ODT09 DDR_A_ODT19 DDR_B_ODT08 DDR_B_ODT18

DDR_CS0_DIMMA#9 DDR_CS1_DIMMA#9 DDR_CS0_DIMMB#8 DDR_CS1_DIMMB#8

DDR_A_RAS#8,9 DDR_A_CAS#8,9 DDR_A_WE#8,9

DDR_A_DM0 DDR_A_DM1 DDR_A_DM2 DDR_A_DM3 DDR_A_DM4 DDR_A_DM5 DDR_A_DM6 DDR_A_DM7

DDR_A_DQS0 DDR_A_DQS#0 DDR_A_DQS1 DDR_A_DQS#1 DDR_A_DQS2 DDR_A_DQS#2 DDR_A_DQS3 DDR_A_DQS#3 DDR_A_DQS4 DDR_A_DQS#4 DDR_A_DQS5 DDR_A_DQS#5 DDR_A_DQS6 DDR_A_DQS#6 DDR_A_DQS7 DDR_A_DQS#7

DDR_A_CLK0 DDR_A_CLK#0 DDR_A_CLK1 DDR_A_CLK#1 DDR_B_CLK2 DDR_B_CLK#2 DDR_B_CLK3 DDR_B_CLK#3

DDR_RST# DDR_EVENT#

DDR_CKE0 DDR_CKE1

DDR_A_ODT0 DDR_A_ODT1 DDR_B_ODT0 DDR_B_ODT1

DDR_CS0_DIMMA# DDR_CS1_DIMMA# DDR_CS0_DIMMB# DDR_CS1_DIMMB#

DDR_A_RAS# DDR_A_CAS# DDR_A_WE#

U22E

R17

M_ADD0

H19

M_ADD1

J17

M_ADD2

H18

M_ADD3

H17

M_ADD4

G17

M_ADD5

H15

M_ADD6

G18

M_ADD7

F19

M_ADD8

E19

M_ADD9

T19

M_ADD10

F17

M_ADD11

E18

M_ADD12

W17

M_ADD13

E16

M_ADD14

G15

M_ADD15

R18

M_BANK0

T18

M_BANK1

F16

M_BANK2

D15

M_DM0

B19

M_DM1

D21

M_DM2

H22

M_DM3

P23

M_DM4

V23

M_DM5

AB20

M_DM6

AA16

M_DM7

A16

M_DQS_H0

B16

M_DQS_L0

B20

M_DQS_H1

A20

M_DQS_L1

E23

M_DQS_H2

E22

M_DQS_L2

J22

M_DQS_H3

J23

M_DQS_L3

R22

M_DQS_H4

P22

M_DQS_L4

W22

M_DQS_H5

V22

M_DQS_L5

AC20

M_DQS_H6

AC21

M_DQS_L6

AB16

M_DQS_H7

AC16

M_DQS_L7

M17

M_CLK_H0

M16

M_CLK_L0

M19

M_CLK_H1

M18

M_CLK_L1

N18

M_CLK_H2

N19

M_CLK_L2

L18

M_CLK_H3

L17

M_CLK_L3

L23

M_RESET_L

N17

M_EVENT_L

F15

M_CKE0

E15

M_CKE1

W19

M0_ODT0

V15

M0_ODT1

U19

M1_ODT0

W15

M1_ODT1

T17

M0_CS_L0

W16

M0_CS_L1

U17

M1_CS_L0

V16

M1_CS_L1

U18

M_RAS_L

V19

M_CAS_L

V17

M_WE_L

ONTARIO-2M161000-1.6G_BGA413

15G@

DDR SYSTEM MEMORY

B

M_DATA0 M_DATA1 M_DATA2 M_DATA3 M_DATA4 M_DATA5 M_DATA6 M_DATA7

M_DATA8

M_DATA9 M_DATA10 M_DATA11 M_DATA12 M_DATA13 M_DATA14 M_DATA15

M_DATA16 M_DATA17 M_DATA18 M_DATA19 M_DATA20 M_DATA21 M_DATA22 M_DATA23

M_DATA24 M_DATA25 M_DATA26 M_DATA27 M_DATA28 M_DATA29 M_DATA30 M_DATA31

M_DATA32 M_DATA33 M_DATA34 M_DATA35 M_DATA36 M_DATA37 M_DATA38 M_DATA39

M_DATA40 M_DATA41 M_DATA42 M_DATA43 M_DATA44 M_DATA45 M_DATA46 M_DATA47

M_DATA48 M_DATA49 M_DATA50 M_DATA51 M_DATA52 M_DATA53 M_DATA54 M_DATA55

M_DATA56 M_DATA57 M_DATA58 M_DATA59 M_DATA60 M_DATA61 M_DATA62 M_DATA63

M_VREF

M_ZVDDIO_ME M_S

B14 A15 A17 D18 A14 C14 C16 D16

C18 A19 B21 D20 A18 B18 A21 C20

C23 D23 F23 F22 C22 D22 F20 F21

H21 H23 K22 K21 G23 H20 K20 K23

N23 P21 T20 T23 M20 P20 R23 T22

V20 V21 Y23 Y22 T21 U23 W23 Y21

Y20 AB22 AC19 AA18 AA23 AA20 AB19 Y18

AC17 Y16 AB14 AC14 AC18 AB18 AB15 AC15

M23

M22

DDR_A_D0 DDR_A_D1 DDR_A_D2 DDR_A_D3 DDR_A_D4 DDR_A_D5 DDR_A_D6 DDR_A_D7

DDR_A_D8 DDR_A_D9 DDR_A_D10 DDR_A_D11 DDR_A_D12 DDR_A_D13 DDR_A_D14 DDR_A_D15

DDR_A_D16 DDR_A_D17 DDR_A_D18 DDR_A_D19 DDR_A_D20 DDR_A_D21 DDR_A_D22 DDR_A_D23

DDR_A_D24 DDR_A_D25 DDR_A_D26 DDR_A_D27 DDR_A_D28 DDR_A_D29 DDR_A_D30 DDR_A_D31

DDR_A_D32 DDR_A_D33 DDR_A_D34 DDR_A_D35 DDR_A_D36 DDR_A_D37 DDR_A_D38 DDR_A_D39

DDR_A_D40 DDR_A_D41 DDR_A_D42 DDR_A_D43 DDR_A_D44 DDR_A_D45 DDR_A_D46 DDR_A_D47

DDR_A_D48 DDR_A_D49 DDR_A_D50 DDR_A_D51 DDR_A_D52 DDR_A_D53 DDR_A_D54 DDR_A_D55

DDR_A_D56 DDR_A_D57 DDR_A_D58 DDR_A_D59 DDR_A_D60 DDR_A_D61 DDR_A_D62 DDR_A_D63

+MEM_VREF

R437

39.2_0402_1%

15 mils

12

C

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

PCIE_GTX_C_FRX_P017 PCIE_GTX_C_FRX_N017

PCIE_GTX_C_FRX_P117 PCIE_GTX_C_FRX_N117

PCIE_GTX_C_FRX_P217 PCIE_GTX_C_FRX_N217

PCIE_GTX_C_FRX_P317 PCIE_GTX_C_FRX_N317

+1.5V

+1.05VS

UMI_RX0P12 UMI_RX0N12

UMI_RX1P12 UMI_RX1N12

UMI_RX2P12 UMI_RX2N12

UMI_RX3P12 UMI_RX3N12

R435 2K_0402_1%R435 2K_0402_1%

Less than 1"

1 2

DDR_A_D[0..63] 8,9

DDR_A_MA[0..15] 8,9

DDR_A_DM[0..7] 8,9

PCIE_GTX_C_FRX_P0 PCIE_GTX_C_FRX_N0

PCIE_GTX_C_FRX_P1 PCIE_GTX_C_FRX_N1

PCIE_GTX_C_FRX_P2 PCIE_GTX_C_FRX_N2

PCIE_GTX_C_FRX_P3 PCIE_GTX_C_FRX_N3

P_ZVDD_10

U22A

AA6

P_GPP_RXP0

Y6

P_GPP_RXN0

AB4

P_GPP_RXP1

AC4

P_GPP_RXN1

AA1

P_GPP_RXP2

AA2

P_GPP_RXN2

Y4

P_GPP_RXP3

Y3

P_GPP_RXN3

Y14

P_ZVDD_10

AA12

P_UMI_RXP0

Y12

P_UMI_RXN0

AA10

P_UMI_RXP1

Y10

P_UMI_RXN1

AB10

P_UMI_RXP2

AC10

P_UMI_RXN2

AC7

P_UMI_RXP3

AB7

P_UMI_RXN3

ONTARIO-2M161000-1.6G_BGA413

15G@

P_GPP_TXP0 P_GPP_TXN0

P_GPP_TXP1 P_GPP_TXN1

P_GPP_TXP2 P_GPP_TXN2

P_GPP_TXP3

PCIE I/F

P_GPP_TXN3

UMI I/F

P_ZVSS

P_UMI_TXP0 P_UMI_TXN0

P_UMI_TXP1 P_UMI_TXN1

P_UMI_TXP2 P_UMI_TXN2

P_UMI_TXP3 P_UMI_TXN3

D

PCIE_FTX_GRX_P0

AB6

PCIE_FTX_GRX_N0

AC6

PCIE_FTX_GRX_P1

AB3

PCIE_FTX_GRX_N1

AC3

PCIE_FTX_GRX_P2

Y1

PCIE_FTX_GRX_N2

Y2

PCIE_FTX_GRX_P3

V3

PCIE_FTX_GRX_N3

V4

P_ZVSS

AA14

AB12 AC12

AC11 AB11

AA8 Y8

AB8 AC8

C518 0.1U_0402_16V7KVGA@C518 0.1U_0402_16V7KVGA@ C519 0.1U_0402_16V7KVGA@C519 0.1U_0402_16V7KVGA@

C520 0.1U_0402_16V7KVGA@C520 0.1U_0402_16V7KVGA@ C521 0.1U_0402_16V7KVGA@C521 0.1U_0402_16V7KVGA@

C522 0.1U_0402_16V7KVGA@C522 0.1U_0402_16V7KVGA@ C523 0.1U_0402_16V7KVGA@C523 0.1U_0402_16V7KVGA@

C524 0.1U_0402_16V7KVGA@C524 0.1U_0402_16V7KVGA@ C525 0.1U_0402_16V7KVGA@C525 0.1U_0402_16V7KVGA@

R436 1.27K_0402_1%R436 1.27K_0402_1%

1 2

Less than 1"

UMI_TX0P_C UMI_TX0N_C

UMI_TX1P_C UMI_TX1N_C

UMI_TX2P_C UMI_TX2N_C

UMI_TX3P_C UMI_TX3N_C

C526 0.1U_0402_16V7KC526 0.1U_0402_16V7K C527 0.1U_0402_16V7KC527 0.1U_0402_16V7K

C528 0.1U_0402_16V7KC528 0.1U_0402_16V7K C529 0.1U_0402_16V7KC529 0.1U_0402_16V7K

C530 0.1U_0402_16V7KC530 0.1U_0402_16V7K C531 0.1U_0402_16V7KC531 0.1U_0402_16V7K

C532 0.1U_0402_16V7KC532 0.1U_0402_16V7K C533 0.1U_0402_16V7KC533 0.1U_0402_16V7K

1 2 1 2

E

PCIE_FTX_C_GRX_P0 17 PCIE_FTX_C_GRX_N0 17

PCIE_FTX_C_GRX_P1 17 PCIE_FTX_C_GRX_N1 17

PCIE_FTX_C_GRX_P2 17 PCIE_FTX_C_GRX_N2 17

PCIE_FTX_C_GRX_P3 17 PCIE_FTX_C_GRX_N3 17

UMI_TX0P 12 UMI_TX0N 12

UMI_TX1P 12 UMI_TX1N 12

UMI_TX2P 12 UMI_TX2N 12

UMI_TX3P 12 UMI_TX3N 12

DDR_CKE0

DDR_CKE1

+1.5V

R149

1 2

1K_0402_5%

1 1

DDR_EVENT#

A

R438

1K_0402_1%

R439

1K_0402_1%

1 2

1

C534

1000P_0402_50V7K

2

1 2

Place within 1000 mils to APU 20100526

B

C535

+MEM_VREF

1

0.1U_0402_16V4Z

2

For AMD recommend to fix S3 issue.

Security Classification

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETARY PR OPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D

AND TRADE SECRET INF ORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CU STODY OF THE COMPET ENT DIVISION OF R&D DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONT AINS

DEPARTMENT EXCEPT AS AU THORIZED BY COMPAL ELECTRON ICS, INC. NEITHER THIS SHEET NO R THE INFORMATION IT CONT AINS MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITH OUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY T HIRD PARTY WITH OUT PRIOR WRIT TEN CONSENT OF CO MPAL ELECTRONICS, INC.

R1705

68_0402_5%

Issued Date

C

12

R1706

R1706 68_0402_5%

68_0402_5%

Compal Secret Data

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

D

Custom

Compal Electronics, Inc.

Title

Size Document Number Rev

Date: Sheet

P06-FT1 DDRIII/UMI/PCIE

LA-7322P

E

647Thursday, February 17, 2011

of

1.0

5

4

3

2

1

+APU_CORE

U22C

11A

E5

VDDCR_CPU_1

E6

VDDCR_CPU_2

F5

VDDCR_CPU_3

F7

VDDCR_CPU_4

G6

VDDCR_CPU_5

G8

VDDCR_CPU_6

H5

VDDCR_CPU_7

H7

VDDCR_CPU_8

J6

VDDCR_CPU_9

J8

VDDCR_CPU_10

L7

VDDCR_CPU_11

M6

VDDCR_CPU_12

M8

VDDCR_CPU_13

N7

VDDCR_CPU_14

R8

VDDCR_CPU_15

10A

E8

VDDCR_NB_1

E11

VDDCR_NB_2

E13

VDDCR_NB_3

F9

VDDCR_NB_4

F12

VDDCR_NB_5

G11

VDDCR_NB_6

G13

VDDCR_NB_7

H9

VDDCR_NB_8

H12

VDDCR_NB_9

K11

VDDCR_NB_10

K13

VDDCR_NB_11

L10

VDDCR_NB_12

L12

VDDCR_NB_13

L14

VDDCR_NB_14

M11

VDDCR_NB_15

M12

VDDCR_NB_16

M13

VDDCR_NB_17

N10

VDDCR_NB_18

N12

VDDCR_NB_19

N14

VDDCR_NB_20

P11

VDDCR_NB_21

P13

VDDCR_NB_22

2A

G16

VDDIO_ MEM_S_1

G19

VDDIO_ MEM_S_2

E17

VDDIO_ MEM_S_3

J16

VDDIO_ MEM_S_4

L16

VDDIO_ MEM_S_5

L19

VDDIO_ MEM_S_6

N16

VDDIO_ MEM_S_7

R16

VDDIO_ MEM_S_8

R19

VDDIO_ MEM_S_9

W18

VDDIO_ MEM_S_10

U16

VDDIO_ MEM_S_11

ONTARIO-2M161000-1.6G_BGA413

15G@

+1.5V

C589

10U_0603_6.3V6M

C595

1U_0402_6.3V6K

C599

0.1U_0402_16V7K

+1.5V

2

1

2

1

2

1

2

C101

0.1U_0402_16V7K

1

C590

10U_0603_6.3V6M

2

1

C596

1U_0402_6.3V6K

2

1

C600

0.1U_0402_16V7K

2

180PF Qt'y follow the distance between CPU socket and DIMM0. <2.5inch>

2

1

C102

0.1U_0402_16V7K

GPU AND NB CORE

DDR3

1

C597

1U_0402_6.3V6K

2

1

C601

0.1U_0402_16V7K

2

TSense/PLL/DP/PCIE/IO

VDD_18_1 VDD_18_2 VDD_18_3 VDD_18_4 VDD_18_5 VDD_18_6

CPU CORE

VDD_18_7

DAC

VDD_18_DAC

POWER

DIS PLL

VDDPL_10

PCIE/IO/DDR3 Phy

VDD_10_1 VDD_10_2 VDD_10_3 VDD_10_4

DP Phy/IO

180P_0402_50V8J

1

C103

C103 180P_0402_50V8J

180P_0402_50V8J

2

POWER POWER

1

C685

2

10U_0603_6.3V6M

1

+

C625

C624

@

10U_0603_6.3V6M

2

10U_0603_6.3V6M

2

390U_2.5V_10M

Near CPU Socket

+

+APU_CORE

+APU_CORE_NB

+1.5V

1

C623

10U_0603_6.3V6M

2

C543

10U_0603_6.3V6M

C563

C579

C586

1U_0402_6.3V6K

1

+

C1105

390U_2.5V_10M

2

1

2

10U_0603_6.3V6M

180P_0402_50V8J

1

0.1U_0402_16V7K

2

1

10U_0603_6.3V6M

2

1

2

POWER

10U_0603_6.3V6M

1

C616

@

2

1

C544

2

1

C554

2

1

C587

180P_0402_50V8J

2

1

C540

10U_0603_6.3V6M

2

1

C555

180P_0402_50V8J

2

1

C588

180P_0402_50V8J

2

+1.5V +1.8VS

1

C622

390U_2.5V_10M

2

1

C539

D D

10U_0603_6.3V6M

2

1

C550

1U_0402_6.3V6K

2

1

C559

0.1U_0402_16V7K

2

+APU_CORE_NB

C C

C575

10U_0603_6.3V6M

C582

1U_0402_6.3V6K

C591

0.1U_0402_16V7K

B B

POWER

10U_0603_6.3V6M

+APU_CORE

C605

@

330U_D2E_2.5VM_R9M

+APU_CORE_NB

A A

C617

390U_2.5V_10M

@

10U_0603_6.3V6M

1U_0402_6.3V6K

0.1U_0402_16V7K

1

10U_0603_6.3V6M

2

1

1U_0402_6.3V6K

2

1

0.1U_0402_16V7K

2

1

C620

@

2

330U_D2E_2.5VM_R9M

1

+

2

1

+

2

C536

C551

C560

C576

C583

C592

C606

1

2

1

2

1

2

1

2

1

2

1

2

C621

@

390U_2.5V_10M

1

+

@

2

C541

10U_0603_6.3V6M

C552

1U_0402_6.3V6K

C561

0.1U_0402_16V7K

C577

10U_0603_6.3V6M

C584

1U_0402_6.3V6K

C593

0.1U_0402_16V7K

+1.05VS

1

+

2

390U_2.5V_10M

390U_2.5V_10M C607

C607

1

+

C618

390U_2.5V_10M

2

1

2

1

2

1

2

1

2

1

2

1

2

1

+

2

1

C542

2

10U_0603_6.3V6M

1

C553

1U_0402_6.3V6K

2

1

C562

0.1U_0402_16V7K

2

1

C578

10U_0603_6.3V6M

2

1

C585

1U_0402_6.3V6K

2

1

C594

0.1U_0402_16V7K

2

1

390U_2.5V_10M

+

C1104

2

Near CPU Socket

1

C619

10U_0603_6.3V6M

2

Near CPU Socket Near CPU Socket

(390uF_2.5V_6.3x5.7_ESR10m)*1=(SF000002O00)

5

4

U8 W8 U6 U9 W6 T7 V7

W9

U11

U13 W13 V12 T12

A4

VDD_33

1

C598

1U_0402_6.3V6K

2

1

C602

2

2A

0.15A

0.2A

5.5A

0.5A

+VDD_18

C545

+VDD_18_DAC

C556

+VDDL_10

C564

+VDD_10

C568

C580

1

C537

2

180P_0402_50V8J

1

C557

2

180P_0402_50V8J

1

C565

2

180P_0402_50V8J

1

C569

2

180P_0402_50V8J

1

C581

2

0.1U_0402_16V7K

1

2

1

2

1

2

1

2

1

2

1

C546

C538

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C604

C558

2

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C566

C567

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C570

C571

2

0.1U_0402_16V7K

+3VS

Power Cap. Summary

APU

S POLY C 330U 2.5V M D2E TPE LESR9M H1.8 --->+APU_CORE(Qty : 3) Unpop:2

1U_0402_6.3V6K

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+APU_CORE(Qty : 2)

S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->+APU_CORE_NB(Qty : 1)

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU--->+APU_CORE_NB(Qty : 1)

1

1U_0402_6.3V6K

10U_0603_6.3V6M

1U_0402_6.3V6K

1

C547

2

1 @

@

C684

2

1

C572

2

1

C548

C549

2

1U_0402_6.3V6K

L30

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

10U_0603_6.3V6M

FBMA-L11-201209-221LMA30T_0805

1

C574

C573

2

1U_0402_6.3V6K

10U_0603_6.3V6M

L31

10U_0603_6.3V6M

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5V(Qty : 1)

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->1.05VS(Qty : 1)

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.8VS(Qty : 1)

DDR3 Socket

S POLY C 330U 2V M X LESR6M SX H1.9 --->1.5V(Qty : 1)

FCH

S POLY C 330U 2.5V Y D2 LESR9M EEFS H1.9 --->1.1VS(Qty : 1) UMA unpop

1

C603

180P_0402_50V8J

2

GPU

S POLY C 330U 2V M X LESR6M SX H1.9 --->VGA_CORE(Qty : 2) Unpop:1

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+VGA_CORE(Qty : 1)

S_A-P_CAP 390U 2.5V M 6.3X5.7 LESR10M VU --->+1.5VSG(Qty : 1)

USB

1

C104

C104 180P_0402_50V8J

180P_0402_50V8J

2

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

S_A-P_CAP 220U 6.3V M C45 R17M SVPE H4.4 --->+USB_VCCA(Qty : 1)

Compal Secret Dat a

2010/06/30 2012/06/30

Compal Secret Dat a

Deciphered Dat e

+1.8VS

L29

12

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

+1.8VS

12

+1.05VS

12

L32

12

FBMA-L11-201209-221LMA30T_0805

Change from SM010014520 to SD002000080 20100816

By case (Along split plane)

+1.5V

1

C608

@

2

U22D

A7

VSS_1

B7

VSS_2

B11

VSS_3

B17

VSS_4

B22

VSS_5

C4

VSS_6

D5

VSS_7

D7

VSS_8

D9

VSS_9

D11

VSS_10

D14

VSS_11

B15

VSS_12

D17

VSS_13

D19

VSS_14

E7

VSS_15

E9

VSS_16

E12

VSS_17

E20

VSS_18

F8

VSS_19

F11

VSS_20

F13

VSS_21

G4

VSS_22

G5

VSS_23

G7

VSS_24

G9

VSS_25

G12

VSS_26

G20

VSS_27

G22

VSS_28

H6

VSS_29

H11

VSS_30

H13

VSS_31

J4

VSS_32

J5

VSS_33

J7

VSS_34

J20

VSS_35

K10

VSS_36

K14

VSS_37

L4

VSS_38

L6

VSS_39

L8

VSS_40

L11

VSS_41

L13

VSS_42

L20

VSS_43

L22

VSS_44

M7

VSS_45

N4

VSS_46

N6

VSS_47

N8

VSS_48

N11

VSS_49

ONTARIO-2M161000-1.6G_BGA413

15G@

1

C609

@

2

0.1U_0402_16V7K

C611

C610

@

2

0.1U_0402_16V7K

Title

Size Document Number Rev

C

Date: Sheet

N13

VSS_50

N20

VSS_51

N22

VSS_52

P10

VSS_53

P14

VSS_54

R4

VSS_55

R7

VSS_56

R20

VSS_57

T6

VSS_58

T9

VSS_59

T11

VSS_60

T13

VSS_61

U4

VSS_62

U5

VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84 VSS_85 VSS_86 VSS_87 VSS_88 VSS_89 VSS_90 VSS_91 VSS_92 VSS_93 VSS_94 VSS_95 VSS_96 VSS_97

VSSBG_DAC

U7 U12 U20 U22 V8 V9 V11 V13 W1 W2 W4 W5 W7 W12 W20 Y5 Y7 Y9 Y11 Y13 Y15 Y17 Y19 AA4 AA22 AB2 AB5 AB9 AB13 AB17 AB21 AC5 AC9 AC13 A11

GND

+APU_CORE

+APU_CORE_NB

+1.5V

+1.05VS

+1.8VS

+1.5V

+1.1VS

+GPU_CORE

+1.5VSG

+USB_VCCA

FOR EMI PURPOSE

C612

@

1

C613

@

2

180P_0402_50V8J

1

C614

@

2

180P_0402_50V8J

1

2

180P_0402_50V8J

1

2

0.1U_0402_16V7K

Compal Electronics, Inc.

P07-FT1 PWR/VSS

LA-7322P

1

747Thursday, February 17, 2011

C615

@

1

2

180P_0402_50V8J

of

1.0

5

4

3

2

1

+1.5V

JDIMM1

+VREF_DQ

1

C680

0.1U_0402_16V4Z

+3VS

0.1U_0402_16V4Z

DDR_CS1_DIMMB#6

1

C667

2

2.2U_0603_6.3V4Z

D D

C C

B B

A A

C681

1000P_0402_50V7K

2

DDR_A_DQS#16,9 DDR_A_DQS16,9

DDR_A_DQS#26,9 DDR_A_DQS26,9

DDR_CKE06,9

DDR_A_BS26,9

DDR_B_CLK26 DDR_B_CLK#26

DDR_A_BS06,9

DDR_A_WE#6,9

DDR_A_CAS#6,9

DDR_A_DQS#46,9 DDR_A_DQS46,9

DDR_A_DQS#66,9 DDR_A_DQS66,9

1 2

R155 10K_0402_5%

+3VS

1

C668

2

0.1U_0402_16V4Z

R152 10K_0402_5%

5

1

2

1 2

@

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48

DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

@

1 2

R150 10K_0402_5%

12

R151

10K_0402_5%

JDIMM1

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1 VDD999VDD10

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013289-1

DQS#0

DQS0

DQ12 DQ13

VSS10

DQ14 DQ15

DQ20 DQ21

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD12

RAS#

VDD14

ODT0

VDD16

ODT1

VDD18

VREF_CA

VSS28

DQ36 DQ37

VSS30

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35

DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47

DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

DQ4 DQ5

VSS3

VSS6

DQ6 DQ7

VSS8

DM1

DM2

CK1

CK1#

BA1

NC2

DM4

DM6

SDA SCL

VTT2

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8 10 12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60 62 64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

DDR3 SO-DIMM A H:5.2mm Standard Typ

4

+0.75VS

DDR_A_DQS#0 6,9 DDR_A_DQS0 6,9

DDR_RST# 6,9

DDR_A_DQS#3 6,9 DDR_A_DQS3 6,9

DDR_CKE1 6,9

DDR_B_CLK3 6 DDR_B_CLK#3 6

DDR_A_BS1 6,9 DDR_A_RAS# 6,9

DDR_CS0_DIMMB# 6 DDR_B_ODT0 6

DDR_B_ODT1 6

C665

0.1U_0402_16V4Z

DDR_A_DQS#5 6,9 DDR_A_DQS5 6,9

DDR_A_DQS#7 6,9 DDR_A_DQS7 6,9

DDR_EVENT# 6,9

FCH_SMDAT0 9,13,28 FCH_SMCLK0 9,13,28

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.5V

0.1U_0402_16V4Z

2

1

0.1U_0402_16V4Z

+VREF_CA

1

2

1

C666

1000P_0402_50V7K

2

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

C45

C44

1

0.1U_0402_16V4Z

2010/06/30 2012/06/30

DDR_A_D[0..63] 6,9

DDR_A_MA[0..15] 6,9

DDR_A_DM[0..7] 6,9

0.1U_0402_16V4Z

2

C652

C653

1

Compal Secret Data

C653

1

0.1U_0402_16V4Z

Deciphered Date

2

C654

1

0.1U_0402_16V4Z

2

C655

1

2

C682

1

0.1U_0402_16V4Z

2

C46

1

0.1U_0402_16V4Z

2

C683

1

0.1U_0402_16V4Z

2

C47

1

0.1U_0402_16V4Z

2

C48

1

CRB 0.1u X1 4,7uX1

+0.75VS

2

C50

C51

@

0.1U_0402_16V4Z

1

Place near JDIMM2

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

P08-DDR3 SODIMM-I Socket

LA-7322P

2

1

C664

4.7U_0603_6.3V6K

2

1

C49

0.1U_0402_16V4Z

847Thursday, February 17, 2011

1.0

of

5

+1.5V

JDIMM2

+VREF_DQ

1

C626

0.1U_0402_16V4Z

2

D D

DDR_A_DQS#16,8 DDR_A_DQS16,8

DDR_A_DQS#26,8 DDR_A_DQS26,8

C C

DDR_CS1_DIMMA#6

B B

For DRAM strap pin reservation 20100817

A A

+3VS

DDR_A_DQS#46,8 DDR_A_DQS46,8

DDR_A_DQS#66,8 DDR_A_DQS66,8

R961 10K_0402_5%@R961 10K_0402_5%@ R153 10K_0402_5% R153 10K_0402_5%

C646

2.2U_0603_6.3V4Z

CRB only one 4.7k

1000P_0402_50V7K

DDR_CKE06,8

DDR_A_BS26,8

DDR_A_CLK06 DDR_A_CLK#06

DDR_A_BS06,8

DDR_A_WE#6,8

DDR_A_CAS#6,8

1 2 1 2

1

2

5

1

C627

2

1

C647

0.1U_0402_16V4Z

2

DDR_A_D0 DDR_A_D1

DDR_A_DM0

DDR_A_D2 DDR_A_D3

DDR_A_D8 DDR_A_D9

DDR_A_D10 DDR_A_D11

DDR_A_D16 DDR_A_D17

DDR_A_D18 DDR_A_D19

DDR_A_D24 DDR_A_D25

DDR_A_DM3

DDR_A_D26 DDR_A_D27

DDR_A_MA12 DDR_A_MA9

DDR_A_MA8 DDR_A_MA5

DDR_A_MA3 DDR_A_MA1

DDR_A_MA10

DDR_A_MA13

DDR_A_D32 DDR_A_D33

DDR_A_D34 DDR_A_D35

DDR_A_D40 DDR_A_D41

DDR_A_DM5

DDR_A_D42 DDR_A_D43

DDR_A_D48 DDR_A_D49

DDR_A_D50 DDR_A_D51

DDR_A_D56 DDR_A_D57

DDR_A_DM7

DDR_A_D58 DDR_A_D59

@

1 2

R154

10K_0402_5%

R962

10K_0402_5%

1 2

For DRAM strap pin reservation 20100817

JDIMM2

VREF_DQ1VSS1

3

VSS2

5

DQ0

7

DQ1

9

VSS4

11

DM0

13

VSS5

15

DQ2

17

DQ3

19

VSS7

21

DQ8

23

DQ9

25

VSS9

27

DQS#1 DQS129RESET# VSS1131VSS12

33

DQ10

35

DQ11 VSS1337VSS14

39

DQ16

41

DQ17 VSS1543VSS16

45

DQS#2

47

DQS2

49

VSS18

51

DQ18

53

DQ19

55

VSS20

57

DQ24

59

DQ25 VSS2261DQS#3

63

DM3 VSS2365VSS24

67

DQ26

69

DQ27 VSS2571VSS26

73

CKE0

75

VDD1

77

NC1

79

BA2

81

VDD3

83

A12/BC#

85

A9

87

VDD5

89

A8

91

A5

93

VDD7

95

A3

97

A1

99

VDD9

101

CK0

103

CK0#

105

VDD11

107

A10/AP

109

BA0

111

VDD13

113

WE#

115

CAS#

117

VDD15

119

A13

121

S1#

123

VDD17

125

NCTEST

127

VSS27

129

DQ32

131

DQ33

133

VSS29

135

DQS#4

137

DQS4

139

VSS32

141

DQ34

143

DQ35

145

VSS34

147

DQ40

149

DQ41

151

VSS36

153

DM5

155

VSS37

157

DQ42

159

DQ43

161

VSS39

163

DQ48

165

DQ49

167

VSS41

169

DQS#6

171

DQS6

173

VSS44

175

DQ50

177

DQ51

179

VSS46

181

DQ56

183

DQ57

185

VSS48

187

DM7

189

VSS49

191

DQ58

193

DQ59

195

VSS51

197

SA0

199

VDDSPD

201

SA1

203

VTT1

205

G1

TYCO_2-2013310-1

VREF_CA

DQ4 DQ5

VSS3

DQS#0

DQS0 VSS6

DQ6

DQ7 VSS8 DQ12 DQ13

VSS10

DM1

DQ14 DQ15

DQ20 DQ21

DM2

VSS17

DQ22 DQ23

VSS19

DQ28 DQ29

VSS21

DQS3

DQ30 DQ31

CKE1 VDD2

VDD4

VDD6

VDD8

VDD10

CK1 CK1#

VDD12

BA1 RAS#

VDD14

ODT0

VDD16

ODT1

NC2

VDD18

VSS28

DQ36 DQ37

VSS30

DM4

VSS31

DQ38 DQ39

VSS33

DQ44 DQ45

VSS35 DQS#5

DQS5

VSS38

DQ46 DQ47

VSS40

DQ52 DQ53

VSS42

DM6

VSS43

DQ54 DQ55

VSS45

DQ60 DQ61

VSS47 DQS#7

DQS7

VSS50

DQ62 DQ63

VSS52

EVENT#

SDA

SCL

VTT2

4

+1.5V

2

DDR_A_D4

4

DDR_A_D5

6 8 10 12 14

DDR_A_D6

16

DDR_A_D7

18 20

DDR_A_D12

22

DDR_A_D13

24 26

DDR_A_DM1

28 30 32

DDR_A_D14

34

DDR_A_D15

36 38

DDR_A_D20

40

DDR_A_D21

42 44

DDR_A_DM2

46 48

DDR_A_D22

50

DDR_A_D23

52 54

DDR_A_D28

56

DDR_A_D29

58 60 62 64 66

DDR_A_D30

68

DDR_A_D31

70 72

74 76

DDR_A_MA15

78

A15 A14

A11

A7

A6 A4

A2 A0

S0#

G2

DDR_A_MA14

80 82

DDR_A_MA11

84

DDR_A_MA7

86 88

DDR_A_MA6

90

DDR_A_MA4

92 94

DDR_A_MA2

96

DDR_A_MA0

98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 202 204

206

DDR_A_D36 DDR_A_D37

DDR_A_DM4

DDR_A_D38 DDR_A_D39

DDR_A_D44 DDR_A_D45

DDR_A_D46 DDR_A_D47

DDR_A_D52 DDR_A_D53

DDR_A_DM6

DDR_A_D54 DDR_A_D55

DDR_A_D60 DDR_A_D61

DDR_A_D62 DDR_A_D63

DDR3 SO-DIMM B H:9.2mm Standard Type

4

+0.75VS

DDR_A_DQS#0 6,8 DDR_A_DQS0 6,8

DDR_RST# 6,8

DDR_A_DQS#3 6,8 DDR_A_DQS3 6,8

DDR_CKE1 6,8

DDR_A_CLK1 6 DDR_A_CLK#1 6

DDR_A_BS1 6,8 DDR_A_RAS# 6,8

DDR_CS0_DIMMA# 6 DDR_A_ODT0 6

DDR_A_ODT1 6

1

C645

1000P_0402_50V7K

2

DDR_A_DQS#5 6,8 DDR_A_DQS5 6,8

DDR_A_DQS#7 6,8 DDR_A_DQS7 6,8

DDR_EVENT# 6,8

FCH_SMDAT0 8,13,28 FCH_SMCLK0 8,13,28

1

C644

0.1U_0402_16V4Z

2

3

DDR_A_D[0..63]

DDR_A_MA[0..15]

DDR_A_DM[0..7]

+1.5V

2

C628

1

0.1U_0402_16V4Z

2

C629

1

DDR_A_D[0..63] 6,8

DDR_A_MA[0..15] 6,8

DDR_A_DM[0..7] 6,8

0.1U_0402_16V4Z

2

C630

1

0.1U_0402_16V4Z

2

C631

1

2

C632

1

0.1U_0402_16V4Z

CRB 0.1u X1 4.7u X1

+0.75VS

+VREF_CA

C640

@

0.1U_0402_16V4Z

Place near JDIMM1

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

2

C641

0.1U_0402_16V4Z

1

2

1

2

C633

1

0.1U_0402_16V4Z

1

C642

4.7U_0603_6.3V6K

2

1

+1.5V

R145

R145 1K_0402_1%

2

C635

1

0.1U_0402_16V4Z

1K_0402_1%

1 2

R147

R147 1K_0402_1%

1K_0402_1%

1 2

2

1

0.1U_0402_16V4Z

2

C636

1

+VREF_CA

2

C637

1

0.1U_0402_16V4Z

C638

15mil 15mil

+VREF_DQ

0.1U_0402_16V4Z

2

C634

1

CRB 100U X2

+1.5V

1

+

C1102

C1102 330U_D2E_2.5VM_R9M

330U_D2E_2.5VM_R9M

2

330U ESR:9m H:2 P/N:SGA20331E10

+1.5V

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet of

2

1

C643

C675

1

Compal Electronics, Inc.

P09-DDR3 SODIMM-II Socket

LA-7322P

0.1U_0402_16V4Z

2

C676

1

0.1U_0402_16V4Z

+1.5V

R146

R146 1K_0402_1%

1K_0402_1%

1 2

R148

R148 1K_0402_1%

1K_0402_1%

1 2

0.1U_0402_16V4Z

2

C110

1

2

C678

1

947Thursday, February 17, 2011

1.0

5

C R T

D D

R1634

1 2

1K_0402_5%

CRT_HSYNC_D

1 2

1K_0402_5%

CRT_VSYNC_D

C1585

4.7U_0805_10V4Z

0.047U_0402_16V7K

12

1 2

R1635

1 2

R1636

1 2

+LCDVDD

APU_CRT_R5

APU_CRT_G5

APU_CRT_B5

+CRT_VCC

C1578

1 2

0.1U_0402_16V4Z

C1579

1 2

0.1U_0402_16V4Z

R1641

APU_CRT_HSYNC_R

APU_CRT_HSYNC5

C C

APU_CRT_VSYNC5

12

0_0402_5%

R1651

APU_CRT_VSYNC_R VSYNC_L

12

0_0402_5%

+CRT_VCC

5

P

A2Y

G

3

5

P

A2Y

G

3

R1640

1

4

OE#

U87

74AHCT1G125GW_SOT353-5

R1648

1

4

OE#

U88

74AHCT1G125GW_SOT353-5

Close to APU

+LCDVDD

1

C1587

C1588

B B

0.1U_0402_16V4Z

A A

C1588

0.1U_0402_16V4Z

2

APU_ENVDD5

R1652

100_0805_5%

R1659

12

61

1 2

LCD POWER CIRCUIT

+5VALW

12

R1653

R1653 47K_0402_5%

47K_0402_5%

2

2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6 Q99A

Q99A

0_0402_5%

12

R1660

100K_0402_5%

3

5

4

Q99B

Q99B 2N7002DW-7-F_SOT363-6

2N7002DW-7-F_SOT363-6

R1656

220K_0402_1%

C1589

1

2

W=60mils

4

0_0402_5%

R1643

R1650

SI2301BDS-T1-E3_SOT23-3

R1637

1 2

Q93

1 3

D

2

12

0_0603_5%

S

G

R1638

150_0402_1%

C1583

C1586

+CRT_VCC

12

1

2

+3VS

1

2

APU_ENBKL5

BLUE

GREEN

RED

CRT_R_R

CRT_G_R

R1639

150_0402_1%

C1584

15P_0402_50V8J

4.7U_0805_10V4Z

12

150_0402_1%

HSYNC_L

1

2

15P_0402_50V8J

APU_BLPWM5

INVT_PWM30

APU_ENBKL

BKOFF#30

D1

2

1

3

YSDA0502C 3P C/A SOT-23

@

D2

2

1

3

YSDA0502C 3P C/A SOT-23

@

C1572

R1663

1 2

BKOFF#

1

2

APU_CRT_DDC_SDA5

APU_CRT_DDC_SCL5

R1654

R1655

100K_0402_1%

R1672

C1573

6.8P_0402_50V8J

R1654

1 2

@R1655

@

1 2

0_0402_5%

R1664

1 2

D5 RB751V40_SC76-2@D5 RB751V40_SC76-2@

3

1

C1574

2

6.8P_0402_50V8J

1 2

HSYNC_L

VSYNC_L

VGA_DDC_DATA_C

VGA_DDC_CLK_C

L116

1 2

NBQ160808T-800Y-N 0603

L117

1 2

NBQ160808T-800Y-N 0603

L118

1 2

NBQ160808T-800Y-N 0603

1

2

0_0402_5%

12

For EMI

6.8P_0402_50V8J

R1647

1 2

0_0402_5%

R1649

R1677

R1677 10K_0402_5%

10K_0402_5%

CRT_CLK

1 2

0_0402_5%

CRT_DATA

R4

12

R1657

R1657 10K_0402_5%

10K_0402_5%

ENBKL 30

+3VS

12

R1670

@

10K_0402_5%

R31

INVTPWM

APU_LCD_CLK5 APU_LCD_DATA5

DISPOFF#

1 2

CRT_CLK VGA_DDC_CLK_C

1

C1575

2

12

R1644

12

R1645

CRT_DATA

2.2K_0402_5%

@R4

@

0_0402_5%

@R31

@

0_0402_5%

For EMI, close to JLVDS1.

DMIC_CLK26 DMIC_DATA26

R1661

D3

2

1

3

@

YSDA0502C 3P C/A SOT-23

D6

2

1

3

YSDA0502C 3P C/A SOT-23

@

ESD

1

C1576

6.8P_0402_50V8J

2.2K_0402_5%

5

Q101B DMN66D0LDW-7_SOT363-6

VGA_DDC_DATA_C

For AMD check list

12

2.2K_0402_5%

AZC199-02SPR7G_SOT23-3

1

C1577

2

6.8P_0402_50V8J

12

R1646

2

61

Q101A

Q101A DMN66D0LDW-7_SOT363-6

DMN66D0LDW-7_SOT363-6

34

1

C9

2

@

22P_0402_50V8J

+3VS

12

R1662

2.2K_0402_5%

D30

@D30

@

ESD

6.8P_0402_50V8J

+CRT_VCC+3VS

2.2K_0402_5%

B+

APU_TXOUT0-5 APU_TXOUT0+5

APU_TXOUT1-5 APU_TXOUT1+5

APU_TXOUT2-5 APU_TXOUT2+5

APU_TXCLK-5 APU_TXCLK+5

USB20_N213 USB20_P213

2

RED

GREEN

BLUECRT_B_R

12

R1642

2.2K_0402_5%

VGA_DDC_DATA_C

VGA_DDC_CLK_C

L119

1 2

FBMA-L11-201209-221LMA30T_0805

USB20_N2

USB20_P2

W=60mils

+LCDVDD

+3VS

@

1

C1590

2

0.1U_0402_16V4Z

3

223

D29

@ D29

@

1

AZC199-02SPR7G_SOT23-3

1

Camera

3

1

+5VS

2

3

C1580

W=60mils

B+_L

INVTPWM DISPOFF#

223

W=40mils

D4

RB491D_SOT23-3

DDC_MD2

1

2

100P_0402_50V8J

1 2

C1581

@

C122680P_0402_50V7K @ C122680P_0402_50V7K @

Q92

1

VIN

VOUT

GND

@

2

AP2230_SOT23-3

L115

+5VS_CRTVCC

1

2

21

SMD1812P075TF .75A 13.2V

C1570

+CRT_VCC

RED

GREEN

HSYNC_L BLUE

VSYNC_L

VGA_DDC_DATA_C

VGA_DDC_CLK_C

1

C1582

C1582 100P_0402_50V8J

100P_0402_50V8J

@

2

100P_0402_50V8J

1

2

T69

For EMI, close to JLVDS1.

JLVDS1

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36 37 38 39 40

41

36

G1

42

37

G2

43

38

G3

44

39

G4

45

40

G5

HONDA_LVD-A40SFYG+

CONN@

3

W=40mils

0.1U_0402_16V4Z

PAD

1

+CRT_VCC

1

C1571

@

2

0.1U_0402_16V4Z

JCRT1

6

11

1 7

12

2 8

13

3 9

14

4 10 15

5

SUYIN_070546FR015S263ZR

CONN@

16

G

17

G

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

5

4

MAY BE USED BY OR DISCLOSED TO ANY TH IRD PARTY WITHOUT PRIOR WR ITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2010/06/30 2012/06/30

Compal Secret Dat a

Deciphered Dat e

2

Compal Electronics, Inc.

Title

Size Document Number Rev

C

Date: Sheet

P10-LVDS/CRT CONN

LA-7322P

1

10 47Thursday, February 17, 2011

of

1.0

5

4

3

2

1

+3VS

+VSB

3

2

1

12

13

D

S

+5VS

@

1

C1591

2

470K_0402_5%

Q96

Q96 SSM3K7002FU_SC70-3

SSM3K7002FU_SC70-3

SCLK

Q94

close to U10VCC (+3VS) pins (one Pin one Capacitor)

+3VS

APU_HDMI_CLK

APU_HDMI_DATA

9





8



7

6



+3VS

12

R205

R202

2.2K_0402_5%

R1736 4.7K_0402_5%@R1736 4.7K_0402_5%@

1 2

+3VS

R1685 4.7K_0402_5%@R1685 4.7K_0402_5%@

1 2

R1737 4.7K_0402_5%@R1737 4.7K_0402_5%@

1 2

+3VS

R1687 4.7K_0402_5%@R1687 4.7K_0402_5%@

1 2

R1689 3.6K_0402_1%

APU_HDMI_HPD5

+3VS

R1692 4.7K_0402_5%@R1692 4.7K_0402_5%@

R1689 3.6K_0402_1%

APU_HDMI_DATA

APU_HDMI_CLK

1 2

R1694 4.7K_0402_5%

HDMI_R_CLK HDMI_R_CLK#

HDMI_R_TX2 HDMI_R_TX2#

HDMI_R_TX1 HDMI_R_TX1#

HDMI_R_TX0 HDMI_R_TX0#

Trace AS Short PASS

HDMI_R_TX2#

HDMI_R_CLK#

HDMI_R_CLK

+3VS

APU_HDMI_HPD

5V PULL UP IN CONNECTER SIDE

U89

2

VCC3V

11

VCC3V

15

VCC3V

21

VCC3V

26

VCC3V

33

VCC3V

40

VCC3V

46

VCC3V

3

FUNCTION1

4

FUCNTION2

6

ANALOG1(REXT)

7

HPD_SOURCE

8

SDA_SOURCE

9

SCL_SOURCE

10

ANALOG2

13

OUT_D4+

14

OUT_D4-

16

OUT_D3+

17

OUT_D3-

19

OUT_D2+

20

OUT_D2-

22

OUT_D1+

23

OUT_D1-

1

GND

5

GND

12

GND

18

GND

24

GND

27

GND

31

GND

36

GND

37

GND

43

GND

ASM1442 QFN 48P

+3VS +3VS

1

C1594

@

2

0.1U_0402_16V4Z

HDMI_TX1_L

HDMI_TX1#_L

1

C1595

C1596

@

2

0.1U_0402_16V4Z

L15ESDL5V0NA-4 SLP2510P 8

2

0.1U_0402_16V4Z

C1602 0.1U_0402_16V7KC1602 0.1U_0402_16V7K

1 2

C1603 0.1U_0402_16V7KC1603 0.1U_0402_16V7K

1 2

C1604 0.1U_0402_16V7KC1604 0.1U_0402_16V7K

1 2

C1605 0.1U_0402_16V7KC1605 0.1U_0402_16V7K

1 2

C1606 0.1U_0402_16V7KC1606 0.1U_0402_16V7K

1 2

C1607 0.1U_0402_16V7KC1607 0.1U_0402_16V7K

1 2

C1608 0.1U_0402_16V7KC1608 0.1U_0402_16V7K

1 2

C1609 0.1U_0402_16V7KC1609 0.1U_0402_16V7K

1 2

R208 0_0402_5%

1 2

R210 0_0402_5%

1 2

R211 0_0402_5%

1 2

R213 0_0402_5%

1 2

R214 0_0402_5%

1 2

R220 0_0402_5%

1 2

R223 0_0402_5%

1 2

R226 0_0402_5%

D11

1





2



4

5

3



8

1

C1597

C1598

LS@

2

0.1U_0402_16V4Z

10U_0805_10V4Z~D

HDMI_CLK HDMI_CLK#

HDMI_TX0 HDMI_TX0#

HDMI_TX1 HDMI_TX1#

HDMI_TX2 HDMI_TX2#

HDMI_R_CLK#HDMI_CLK#_L

HDMI_R_CLK

Swap signal for layout route.

HDMI_R_TX0

HDMI_R_TX0#

HDMI_R_TX1

HDMI_R_TX1#

HDMI_R_TX2

HDMI_R_TX2#

HDMI_R_TX1

9



HDMI_R_TX1# HDMI_R_TX2



8

HDMI_R_TX0



7

HDMI_R_TX0#

6



1

C1593

D D

@

2

0.1U_0402_16V4Z

APU_HDMI_CLKP5

APU_HDMI_CLKN5

APU_HDMI_TX0P5 APU_HDMI_TX0N5

APU_HDMI_TX1P5 APU_HDMI_TX1N5

APU_HDMI_TX2P5 APU_HDMI_TX2N5

C C

B B

A A

HDMI_CLK_L

HDMI_TX0_L

HDMI_TX0#_L

HDMI_TX2_L

HDMI_TX2#_L

HDMI_R_TX1

HDMI_R_TX1# HDMI_R_TX2

HDMI_R_TX0

HDMI_R_TX0#

1

C1600

C1599

LS@

2

0.1U_0402_16V4Z

APU_HDMI_DATA5

APU_HDMI_CLK5

D13

HDMI_R_TX2#

HDMI_R_CLK#

HDMI_R_CLK

D13

1





2



4

5

3



8

L15ESDL5V0NA-4 SLP2510P 8

For ESD request.

5

4

SCLK

SDATA

+HDMI_5V_OUT

R200

R201

12

2.2K_0402_5%

R200, R201 place near JHDMI connect

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY CO MPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

1

+5VS +HDMI_5V_OUT

HDMI_HPD_R

FUNCTION3 FUNCTION4

THERMAL_GND

VIN

@

+3VS

HDMI_HPD_R#

2

G

25

OE*

28

SCL_SINK

29

SDA_SINK

30

HPD_SINK

32

DDC_EN

34 35

48

IN_D4+

47

IN_D4-

45

IN_D3+

44

IN_D3-

42

IN_D2+

41

IN_D2-

39

IN_D1+

38

IN_D1-

49

+HDMI_5V_OUT

2010/06/30 2012/06/30

3

VOUT

GND

2

AP2230_SOT23-3

R1678

12

R1701

R1701 10K_0402_5%

10K_0402_5%

13

D

Q84

S

SSM3K7002FU_SC70-3

HDMI_HPD_R#

1 2

R204 2.2K_0402_5%

HDMI_HPD_R SDATA

+5VS

SUSP34,41

HDMI_HPD_R

R1684 4.7K_0402_5%LS@R1684 4.7K_0402_5%LS@

1 2

R1703 4.7K_0402_5%@R1703 4.7K_0402_5%@

1 2

R1686 4.7K_0402_5%@R1686 4.7K_0402_5%@

1 2

R1688 4.7K_0402_5%@R1688 4.7K_0402_5%@

1 2

R1707 4.7K_0402_5%@R1707 4.7K_0402_5%@

1 2

HDMI_CLK HDMI_CLK#

HDMI_TX2 HDMI_TX2#

HDMI_TX1 HDMI_TX1#

HDMI_TX0 HDMI_TX0#

Compal Secret Data

Deciphered Date

D16

6

I/O4

5

VDD

4

I/O3

AZC099-04S.R7G_SOT23-6

2

G

SCLK

SDATA

+3VS +3VS

I/O2

GND

I/O1

For ESD request.

Q95

D

S

6

1U_0603_10V6K

EN_HDMI

12

@

R1679

HDMI_HPD_R

R1704

R1704 100K_0402_5%

100K_0402_5%

4 5

+HDMI_5V

2 1

W=40mils

G

3

SI3456BDV-T1-E3 1N TS OP6

12

C1601

1.5M_0402_5%

+HDMI_5V_OUT

SDATA SCLK

HDMI_CLK#_L

HDMI_CLK_L HDMI_TX0#_L

HDMI_TX0_L HDMI_TX1#_L

HDMI_TX1_L HDMI_TX2#_L

HDMI_TX2_L

Compal Electronics, Inc.

Title

Size Doc ument Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

F2

2 1

0.5A_15V_SMD1812P050TF

1

2

0.1U_0402_16V7K

JHDMI1

19

HP_DET

18

+5V

17

DDC/CEC_GND

16

SDA

15

SCL

14

Reserved

13

CEC

12

CK-

11

CK_shield

10

CK+

9

D0-

8

D0_shield

7

D0+

6

D1-

5

D1_shield

4

D1+

3

D2-

2

D2_shield

1

D2+

SUYIN_100042MR019S153ZL

P11-HDMI CONN

LA-7322P

1

+HDMI_5V_OUT

C1592

GND GND GND GND

1

2

1U_0603_10V4Z

20 21 22 23

1.0

of

11 47Thursday, February 17, 2011

A

B

C

D

E

For PCIE device reset on FS1 (GFX,GLAN,WLAN,LVDS Travis)

U31E

PCIE_RST#

A_RST#30

UMI_RX0P6

UMI_RX0N6

UMI_RX1P6

+PCIE_VDDAN

PCIE_FTX_C_DRX_P025 PCIE_FTX_C_DRX_N025 PCIE_FTX_C_DRX_P128 PCIE_FTX_C_DRX_N128

PCIE_FRX_DTX_P025 PCIE_FRX_DTX_N025 PCIE_FRX_DTX_P128 PCIE_FRX_DTX_N128

UMI_RX1N6

UMI_RX2P6

UMI_RX2N6

UMI_RX3P6

UMI_RX3N6

UMI_TX0P6 UMI_TX0N6 UMI_TX1P6 UMI_TX1N6 UMI_TX2P6 UMI_TX2N6 UMI_TX3P6 UMI_TX3N6

1 1

LAN WLAN

2 2

C53 0.1U_0402_16V7KC53 0.1U_0402_16V7K

1 2

C54 0.1U_0402_16V7KC54 0.1U_0402_16V7K

1 2

C55 0.1U_0402_16V7KC55 0.1U_0402_16V7K

1 2

C56 0.1U_0402_16V7KC56 0.1U_0402_16V7K

1 2

C57 0.1U_0402_16V7KC57 0.1U_0402_16V7K

1 2

C58 0.1U_0402_16V7KC58 0.1U_0402_16V7K

1 2

C59 0.1U_0402_16V7KC59 0.1U_0402_16V7K

1 2

C60 0.1U_0402_16V7KC60 0.1U_0402_16V7K

1 2

R560 590_0402_1%R560 590_0402_1% R561 2K_0402_1%R561 2K_0402_1%

12 12

C61 0.1U_0402_16V7KC61 0.1U_0402_16V7K

1 2

C62 0.1U_0402_16V7KC62 0.1U_0402_16V7K

1 2

C717 0.1U_0402_16V 7KC717 0.1U_0402_16V7K

1 2

C63 0.1U_0402_16V7KC63 0.1U_0402_16V7K

1 2

A_RST#

UMI_RX0P_C UMI_RX0N_C UMI_RX1P_C UMI_RX1N_C UMI_RX2P_C UMI_RX2N_C UMI_RX3P_C UMI_RX3N_C

PCIE_FTX_DRX_P0 PCIE_FTX_DRX_N0 PCIE_FTX_DRX_P1 PCIE_FTX_DRX_N1

close to FCH within 1"

R564 0_0402_5%R564 0_0402_5%

APU_DISP_CLKP5 APU_DISP_CLKN5

APU_CLKP5

APU_CLKN5

CLK_PCIE_VGA17 CLK_PCIE_VGA#17

CLK_PCIE_LAN25

LAN WLAN

3 3

4 4

C64

1 2

10P_0402_50V8J

R563

20M_0603_5%

C65

1 2

10P_0402_50V8J

CLK_PCIE_LAN#25

CLK_PCIE_ MINI128 CLK_PCIE_ MINI1#28

Close to FCH

Y4

12

Y4

4

1

32.768KHZ_7PF_Q13MC1461000100

A

OSC

NC

1 2

R565 0_0402_5%R565 0_0402_5%

1 2

R162 0_0402_5%R162 0_0402_5%

1 2

R163 0_0402_5%R163 0_0402_5%

1 2

R569 0_0402_5%R569 0_0402_5%

1 2

R570 0_0402_5%R570 0_0402_5%

1 2

R571 0_0402_5%R571 0_0402_5%

1 2

R572 0_0402_5%R572 0_0402_5%

1 2

R573 0_0402_5%R573 0_0402_5%

1 2

R574 0_0402_5%R574 0_0402_5%

1 2

C66

CLK_SD_48M27

1 2

3

2

12

10P_0402_50V8J

C67

25MHZ_12PF_X5H025000FC1H-H

12P_0402_50V8J

RTC_32KHI

RTC_32KHO

Y3

APU_DISP_CLKP_R APU_DISP_CLKN_R

APU_CLKP_R APU_CLKN_R

CLK_PCIE_VGA_R CLK_PCIE_VGA#_R

CLK_PCIE_LAN_R CLK_PCIE_LAN#_R

CLK_PCIE_ MINI1_R CLK_PCIE_MINI1#_R

EMI

1 2

CLK_SD_48M_R

25M_CLK_X1

25M_CLK_X2

R655 22_0402_5%R655 22_0402_5%

1M_0603_5%

1M_0603_5% R576

R576

FCH : SA000046H60 (S IC 218-0792001 A12 HUDSON-M1 FCBGA 605P)

FCH : SA000046H70 (S IC 218-0792006 A13 HUDSON-M1 FCBGA 605P)

B

U31E

P1

PCIE_RST_L

L1

A_RST_L

AD26

UMI_TX0P

AD27

UMI_TX0N

AC28

UMI_TX1P

AC29

UMI_TX1N

AB29

UMI_TX2P

AB28

UMI_TX2N

AB26

UMI_TX3P

AB27

UMI_TX3N

AE24

UMI_RX0P

AE23

UMI_RX0N

AD25

UMI_RX1P

AD24

UMI_RX1N

AC24

UMI_RX2P

AC25

UMI_RX2N

AB25

UMI_RX3P

AB24

UMI_RX3N

AD29

PCIE_CALRP

AD28

PCIE_CALRN

AA28

GPP_TX0P

AA29

GPP_TX0N

Y29

GPP_TX1P

Y28

GPP_TX1N

Y26

GPP_TX2P

Y27

GPP_TX2N

W28

GPP_TX3P

W29

GPP_TX3N

AA22

GPP_RX0P

Y21

GPP_RX0N

AA25

GPP_RX1P

AA24

GPP_RX1N

W23

GPP_RX2P

V24

GPP_RX2N

W24

GPP_RX3P

W25

GPP_RX3N

M23

PCIE_RCLKP/NB_LNK_CLKP

P23

PCIE_RCLKN/NB_LNK_CLKN

U29

NB_DISP_CLKP

U28

NB_DISP_CLKN

T26

NB_HT_CLKP

T27

NB_HT_CLKN

V21

CPU_HT_CLKP

T21

CPU_HT_CLKN

V23

SLT_GFX_CLKP

T23

SLT_GFX_CLKN

L29

GPP_CLK0P

L28

GPP_CLK0N

N29

GPP_CLK1P

N28

GPP_CLK1N

M29

GPP_CLK2P

M28

GPP_CLK2N

T25

GPP_CLK3P

V25

GPP_CLK3N

L24

GPP_CLK4P

L23

GPP_CLK4N

P25

GPP_CLK5P

M25

GPP_CLK5N

P29

GPP_CLK6P

P28

GPP_CLK6N

N26

GPP_CLK7P

N27

GPP_CLK7N

T29

GPP_CLK8P

T28

GPP_CLK8N

L25

14M_25M_48M_OSC

L26

25M_X1

L27

25M_X2

21807-A11-HUDSON-M1_FCBGA605

PCI CLKS

PCI EXPRESS I/F

CLOCK GENERATOR

CPU

ALLOW_LDTSTP/DMA_ACTIVE_L

RTC

Security Classification

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONIC S, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

PCICLK1/GPO3 6 PCICLK2/GPO3 7 PCICLK3/GPO3 8

PCICLK4/14M_OSC/GPO39

AD10/GPIO10 AD11/GPIO11 AD12/GPIO12 AD13/GPIO13 AD14/GPIO14 AD15/GPIO15 AD16/GPIO16 AD17/GPIO17 AD18/GPIO18 AD19/GPIO19 AD20/GPIO20 AD21/GPIO21 AD22/GPIO22

LPC

INTRUDER_ALERT_L

C

AD23/GPIO23 AD24/GPIO24 AD25/GPIO25 AD26/GPIO26 AD27/GPIO27 AD28/GPIO28 AD29/GPIO29 AD30/GPIO30 AD31/GPIO31

REQ1_L/GPIO40

GNT1_L/GPO44 GNT2_L/GPO45

INTE_L/GPIO32 INTF_L/GPIO33 INTG_L/GPIO34 INTH_L/GPIO35

SERIRQ/GPIO48

VDDBT_RTC_G

PCI I/F

REQ2_L/CLK_REQ8_L/GPIO41 REQ3_L/CLK_REQ5_L/GPIO42

GNT3_L/CLK_REQ7_L/GPIO46

LDRQ1_L/CLK_REQ6_L/GPIO49

W2

PCICLK0

W1 W3 W4 Y1

V2

PCIRST_L

AA1

AD0/GPIO0

AA4

AD1/GPIO1

AA3

AD2/GPIO2

AB1

AD3/GPIO3

AA5

AD4/GPIO4

AB2

AD5/GPIO5

AB6

AD6/GPIO6

AB5

AD7/GPIO7

AA6

AD8/GPIO8

AC2

AD9/GPIO9

AC3 AC4 AC1 AD1 AD2 AC6 AE2 AE1 AF8 AE3 AF1 AG1 AF2 AE9 AD9 AC11 AF6 AF4 AF3 AH2 AG2 AH3 AA8

CBE0_L

AD5

CBE1_L

AD8

CBE2_L

AA10

CBE3_L

AE8

FRAME_L

AB9

DEVSEL_L

AJ3

IRDY_L

AE7

TRDY_L

AC5

PAR

AF5

STOP_L

AE6

PERR_L

AE4

SERR_L

AE11

REQ0_L

AH5 AH4 AC12 AD12

GNT0_L

AJ5 AH6 AB12 AB11

CLKRUN_L

AD7

LOCK_L

AJ6 AG6 AG4 AJ4

H24

LPCCLK0

H25

LPCCLK1

J27

LAD0

J26

LAD1

H29

LAD2

H28

LAD3

G28

LFRAME_L

J25

LDRQ0_L

AA18 AB19

G21 H21

PROCHOT_L

K19

LDT_PG

G22

LDT_STP_L

J24

LDT_RST_L

C1

32K_X1

C2

32K_X2

D2

RTCCLK

B2 B1

2010/06/30 2012/06/30

T96PADT96PAD

T92PADT92PAD

1 2

R585 0_0402_5%R585 0_0402_5%

VGA_PWRGD_R

T95PADT95PAD

R595 0_0402_5%@R595 0_0402_5%@

1 2

PE_GPIO1

T97PADT97PAD

1 2

R99 10K_0402_5%R99 10K_0402_5%

R854 0_0402_5%R854 0_0402_5%

1 2

R853 0_0402_5%R853 0_0402_5%

1 2

LPCCLK0

R575 22_0402_5%R575 22_0402_5%

1 2

LPCCLK1

R577 22_0402_5%R577 22_0402_5%

1 2

RTC_32KHI

RTC_32KHO

RTC_CLK

C1271

C1272

C1271

1

2

0.1U_0402_16V4Z

Compal Secret Data

Deciphered Date

PCI_CLK1 16 PCI_CLK2 16 PCI_CLK3 16 PCI_CLK4 16

A_RST#

PE_GPIO0

LPC_AD0 28,30 LPC_AD1 28,30 LPC_AD2 28,30 LPC_AD3 28,30 LPC_FRAME# 28,30

SERIRQ 30

ALLOW_STOP# 5 FCH_PROCHOT# 5 APU_PWRGD 5

APU_RST# 5

RTC_CLK 16,30

R864 510_0402_5%R864 510_0402_5%

for Clear CMOS

1U_0402_6.3V4Z

PE_GPIO0 1 7

PCI_AD23 16 PCI_AD24 16 PCI_AD25 16 PCI_AD26 16 PCI_AD27 16

VGA_PWRGD23,41,42,44

PE_GPIO1 2 3,30

1 2

W=20mils

R175 33_0402_5%R175 33_0402_5%

1 2

150P_0402_50V8J

LPC_CLK1 16 LPC_CLK0 16 LPC_CLK0_EC 30 CLK_PCI_DB 28

@

D

1

C1233

2

VGA_PWRGD VGA_PWRGD_R

12

CLRP1

SHORT PADS

+3VALW

C1234

1 2

0.1U_0402_16V4Z

5

2

P

B

4

Y

1

A

R174

8.2K_0402_5%@

1 2

NC7SZ08P5X_NL_SC70-5

G

3

U28

U28 NC7SZ08P5X_NL_SC70-5

NC7SZ08P5X_NL_SC70-5

Need to check material?

APU_PWRGD

+3VALW

U33

2

1

@

PE_GPIO1

+1.8VS +3V S

10K_0402_5%

G

2

13

D

S

D

S

FDV301N_NL_SOT23-3

Q90

C1199

1 2

0.1U_0402_16V4Z

5

P

B

A

G

3

R839 0_0402_5%R839 0_0402_5%

1 2

R109 10K_0402_5%

4

Y

1 2

R830 0_0402_5%

1 2

R838 100K_0402_5%

RTC BATT Conn.

+RTCVCC

1

C1270

2

0.1U_0402_16V4Z

Title

Size Document Number Rev

Custom

Date: Sheet

D23

1

DAN202UT106_SC70-3

Compal Electronics, Inc.

P12-FCH PCIE/PCI/ACPI/LPC/RTC

LA-7322P

PLT_RST# 17,25,28

PCIE_RST#

@

1 2

R582 0_0402_5%

12

R164

@

For GPIO45 leakage

+RTCBATT

1

JRTC1

+

SUYIN_060003HA002G202ZL

-

2

+RTCBATT

12

R179

R179 1K_0402_5%

1K_0402_5%

2

3

E

H_PWRGD_L 43

+CHGRTC

12 47Thursday, February 17, 2011

of

1.0

+3VALW

1 2

R871 10K_0402_5%R871 10K_0402_5%

1 2

R872 10K_0402_5%R872 10K_0402_5%

1 2

R603 10K_0402_5%R603 10K_0402_5%

1 2

R604 10K_0402_5%R604 10K_0402_5%

1 2

R605 10K_0402_5%

1 1

2 2

3 3

R605 10K_0402_5%

1 2

R817 10K_0402_5%R817 10K_0402_5%

+3VS

1 2

R818 10K_0402_5%R818 10K_0402_5%

1 2

R597 4.7K_0402_5%R597 4.7K_0402_5%

1 2

R598 2.2K_0402_5%R598 2.2K_0402_5%

1 2

R599 2.2K_0402_5%R599 2.2K_0402_5%

FCH_PWROK43

0.1U_0402_16V7K

@

1 2

+3VS

R626 2.2K_0402_5%

@

1 2

R404 100K _0402_5%

@

1 2

R173 10K_0402_5%

1 2

R587 10K_0402_5%R587 10K_0402_5%

1 2

R588 10K_0402_5%R588 10K_0402_5%

1 2

R606 150_0402_1%R606 150_0402_1%

@

1 2

R607 10K_0402_5%

@

1 2

R608 10K_0402_5%

1 2

R609 10K _0402_5%R609 10K _0402_5%

Pull-down for enable high performance mode 20100527 (required for M1)

12

VGA@

R911

10K_0402_5%

12

UMA@

R914

10K_0402_5%

VGA@

R910

10K_0402_5%

12

UMA@

R913

10K_0402_5%

UMA@

R912

10K_0402_5%

VGA@

R915

10K_0402_5%

A

USB_OC1#

USB_OC0#

FCH_SIC

FCH_SID

FCH_PCIE_WAKE_R#

LAN_CLKREQ#

MINI1_CLKREQ#

NB_PWRGD

FCH_SMCLK0

FCH_SMDAT0

R580 0_0402_5%@R580 0_0402_5%@

R581 0_0402_5%R581 0_0402_5%

4

2

@

C112

1

VRAM_SEL

VGA_CLKREQ#_R

+3VALW+3VALW+3VALW

12

GPIO189 GPIO190 GPIO191

12

+3VS

@

C111 0.1U_0402_16V7K

1 2

5

2

P

B

Y

1

A

G

NC7SZ08P5X_NL_SC70-5

3

U30

VRAM_Freq : 1->900Hz 0-> 800Hz*

FCH_SMCLK1

FCH_SMDAT1

EC_RSMRST#

HDA_BITCLK

HDA_SDIN0

HDA_SDOUT

12

@

1 2

R930 10K_0402_5%

1 2

R932 10K_0402_5%R932 10K_0402_5%

HDA_BITCLK_AUDIO26 HDA_SDOUT_AUDIO26

HDA_SDIN026

+3VALW

EC_PWROK 30

VGATE 30,43

HDA_SYNC_AUDIO26

HDA_RST_AUDIO#26

EC_LID_OUT#

PCI_PME#

R579 10K_0402_5%@R579 10K_0402_5%@

1 2

FCH_PCIE_WAKE#25,28,30

B

SLP_S3#30 SLP_S5#30

PBTN_OUT#30

EC_GA2030

EC_KBRST#30

EC_SCI#30 EC_SMI#30

R627

R627 0_0402_5%

0_0402_5%

H_THERMTRIP#5

EC_RSMRST#30

LAN_CLKREQ#25

FCH_SMCLK08,9,28 FCH_SMDAT08,9,28

MINI1_CLKREQ#28

EC_LID_OUT#30

USB_OC1#32 USB_OC0#32

R583 33_0402_5%R583 33_0402_5%

1 2

R165 33_0402_5%R165 33_0402_5%

1 2

R589 33_0402_5%R589 33_0402_5%

1 2

R590 33_0402_5%R590 33_0402_5%

1 2

R591 10K_0402_5%R591 10K_0402_5%

1 2

R592 10K_0402_5%R592 10K_0402_5%

1 2

R593 10K_0402_5%R593 10K_0402_5%

+3VALW

1 2

R596 10K_0402_5%R596 10K_0402_5%

1 2

R600 10K_0402_5%R600 10K_0402_5%

1 2

T82 PADT82 PAD T83 PADT83 PAD T84 PADT84 PAD

FCH_PCIE_WAKE_R#

12

VRAM_SEL

VGA_CLKREQ#_R

T85 PADT85 PAD T86 PADT86 PAD

PCI_PME#

FCH_PWROK

NB_PWRGD

FCH_SMCLK1 FCH_SMDAT1

USB_OC1#

HDA_BITCLK HDA_SDOUT HDA_SDIN0

HDA_SYNC HDA_RST#

GPIO189 GPIO190 GPIO191

GPIO187 GPIO188

C

U31A

J2

PCI_PME_L/GEVENT4_L

K1

RI_L/GEVENT22_L

D3

SPI_CS3_L/GBE_STAT1/GEVENT21_L

F1

SLP_S3_L

H1

SLP_S5_L

F2

PWR_BTN_L

H5

PWR_GOOD

G6

SUS_STAT_L

B3

TEST0

C4

TEST1/TMS

F6

TEST2

AD21

GA20IN/GEVENT0_L

AE21

KBRST_L/GEVENT1_L

K2

LPC_PME_L/GEVENT3_L

J29

LPC_SMI_L/GEVENT23_L

H2

GEVENT5_L

J1

SYS_RESET_L/GEVENT19_L

H6

WAKE_L/GEVENT8_L

F3

IR_RX1/GEVENT20_L

J6

THRMTRIP_L/SMBALERT_L/GEVENT2_L

AC19

NB_PWRGD

G1

RSMRST_L

AD19

CLK_REQ4_L/SATA_IS0_L/GPIO64

AA16

CLK_REQ3_L/SATA_IS1_L/GPIO63

AB21

SMARTVOLT 1/SATA_IS2_L/GPIO50

AC18

CLK_REQ0_L/SATA_IS3_L/GPIO60

AF20

SATA_IS4_L/FANOUT3/GPIO55

AE19

SATA_IS5_L/FANIN3/GPIO59

AF19

SPKR_GPIO66

AD22

SCL0_GPIO43

AE22

SDA0_GPIO47

F5

SCL1_GPIO227

F4

SDA1_GPIO228

AH21

CLK_REQ2_L/FANIN4_GPIO62

AB18

CLK_REQ1_L/FANOUT4_GPIO61

E1

IR_LED_L/LLB_L/GPIO184

AJ21

SMARTVOLT2/SHUTDOWN_L/GPIO51

H4

DDR3_RST_L/GEVENT7_L

D5

GBE_LED0/GP IO183

D7

GBE_LED1/GEVENT9_L

G5

GBE_LED2/GEVENT10_L

K3

GBE_STAT0/GEVENT11_L

AA20

CLK_REQG_L/GPIO65_OSCIN

H3

BLINK/USB_OC7_L/GEVENT18_L

D1

USB_OC6_L/IR_TX1/GEVENT6_L

E4

USB_OC5_L/IR_TX0/GEVENT17_L

D4

USB_OC4_L/IR_RX0/GEVENT16_L

E8

USB_OC3_L/AC_PRES/TDO/GEVENT15_L

F7

USB_OC2_L/TCK/GEVENT14_L

E7

USB_OC1_L/TDI/GEVENT13_L

F8

USB_OC0_L/TRST_L/GEVENT12_L

M3

AZ_BITCLK

N1

AZ_SDOUT

L2

AZ_SDIN0/GP IO167

M2

AZ_SDIN1/GP IO168

M1

AZ_SDIN2/GP IO169

M4

AZ_SDIN3/GP IO170

N2

AZ_SYNC

P2

AZ_RST_L

T1

GBE_COL

T4

GBE_CRS

L6

GBE_MDCK

L5

GBE_MDIO

T9

GBE_RXCLK

U1

GBE_RXD3

U3

GBE_RXD2

T2

GBE_RXD1

U2

GBE_RXD0

T5

GBE_RXCTL/RXDV

V5

GBE_RXERR

P5

GBE_TXCLK

M5

GBE_TXD3

P9

GBE_TXD2

T7

GBE_TXD1

P7

GBE_TXD0

M7

GBE_TXCTL/TXEN

P4

GBE_PHY_PD

M9

GBE_PHY_RST_L

V7

GBE_PHY_INTR

E23

PS2_DAT/S DA4/GPIO187

E24

PS2_CLK/SCL4/GPIO188

F21

SPI_CS2_L/GBE_STAT2/GPIO166

G29

FC_RST_L/GPO160

D27

PS2KB_DAT/GPIO189

F28

PS2KB_CLK/GPIO190

F29

PS2M_DAT/GPIO191

E27

PS2M_CLK/GPIO192

21807-A11-HUDSON-M1_FCBGA605

ACPI/WAKE UP EVENTS

GPIO

USB OC

HD AUDIO

GBE LAN

USB MISC

USBCLK/14M_25M_48M_OSC

EC_PWM0/EC_TIMER0/GPIO197 EC_PWM1/EC_TIMER1/GPIO198 EC_PWM2/EC_TIMER2/GPIO199 EC_PWM3/EC_TIMER3/GPIO200

USB_RCOMP

USB 1.1

USB_FSD1P/GPIO186

USB_FSD1N

USB_FSD0P/GPIO185

USB_FSD0N

USB_HSD13P

USB_HSD13N

USB_HSD12P

USB_HSD12N

USB_HSD11P

USB_HSD11N

USB_HSD10P

USB_HSD10N

USB_HSD9P USB_HSD9N

USB_HSD8P USB_HSD8N

USB 2.0

USB_HSD7P USB_HSD7N

USB_HSD6P USB_HSD6N

USB_HSD5P USB_HSD5N

USB_HSD4P USB_HSD4N

USB_HSD3P USB_HSD3N

USB_HSD2P USB_HSD2N

USB_HSD1P USB_HSD1N

USB_HSD0P USB_HSD0N

SCL2/GPIO193

SDA2/GPIO194 SCL3_LV/GPIO195 SDA3_LV/GPIO196

KSI_0/GPIO201 KSI_1/GPIO202

EMBEDDED CTRL

KSI_2/GPIO203 KSI_3/GPIO204 KSI_4/GPIO205 KSI_5/GPIO206 KSI_6/GPIO207 KSI_7/GPIO208

KSO_0/GPIO209 KSO_1/GPIO210 KSO_2/GPIO211 KSO_3/GPIO212 KSO_4/GPIO213 KSO_5/GPIO214 KSO_6/GPIO215 KSO_7/GPIO216 KSO_8/GPIO217

KSO_9/GPIO218 KSO_10/GPIO219 KSO_11/GPIO220 KSO_12/GPIO221 KSO_13/GPIO222 KSO_14/GPIO223 KSO_15/GPIO224 KSO_16/GPIO225 KSO_17/GPIO226

D

A10

G19

USB_RCOMP

R578

1 2

11.8K_0402_1%

10mils and <1"

J10 H11

H9

USB_HSD[13:0]P/N:

J8

USB P/N pairs with trace lengths up to 10" and have a decoupling 5.6-pF capacitor

B12

footprint placed near the USB connector or device.

A12

F11 E11

E14 E12

J12 J14

A13 B13

D13 C13

G12 G14

G16 G18

D16 C16

B14 A14

E18 E16

J16 J18

B17 A17

A16 B16

GPIO193

D25

GPIO194

F23 B26 E26 F25 E22

EC_PWM2

F22

EC_PWM3

E21

G24 G25 E28 E29 D29 D28 C29 C28

B28 A27 B27 D26 A26 C26 A24 B25 A25 D24 B24 C24 B23 A23 D22 C22 A22 B22

USB20_P5 26 USB20_N5 26

USB20_P4 27 USB20_N4 27

USB20_P3 28 USB20_N3 28

USB20_P2 10 USB20_N2 10

USB20_P1 32 USB20_N1 32

USB20_P0 32 USB20_N0 32

R584 10K_0402_5%R584 10K_0402_5% R586 10K_0402_5%R586 10K_0402_5%

12 12

FCH_SIC 5 FCH_SID 5

EC_PWM2 16 EC_PWM3 16

USB3

CardReder

WLAN(BT)

CMOS

USB2

USB1

E

Root

EHCI CTL DEV 19, Fn 2

Root

EHCI CTL DEV 18, Fn 2

SKU_ID

4 4

(GPIO189)

PX_FN (GPIO190)

PX_SEL (GPIO191)

SKU_ID : 1->VGA* 0->UMA

PX_Function : 1->PX Ena ble* 0->PX Disable

PX_SEL : 1->PX 3.0* 0->PX 4.0

A

GPIO 189 190 191

UMA DISO PX3.0 PX4.0

0 1

0

1 1

1

1 1 0

B

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

D

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

Compal Electronics, Inc.

P13-FCH HDA/USB/ACPI

LA-7322P

E

13 47Thursday, February 17, 2011

of

1.0

A

1 1

C656 0.01U_0402_16V7KC656 0.01U_0402_16V7K

SATA_ITX_DRX_P029

HDD

ODD

2 2

SATA_ITX_DRX_N029

SATA_DTX_C_IRX_N029 SATA_DTX_C_IRX_P029

SATA_ITX_DRX_P129 SATA_ITX_DRX_N129

SATA_DTX_C_IRX_N129 SATA_DTX_C_IRX_P129

1 2

C658 0.01U_0402_16V7KC658 0.01U_0402_16V7K

1 2

C648 0.01U_0402_16V7KC648 0.01U_0402_16V7K

1 2

C649 0.01U_0402_16V7KC649 0.01U_0402_16V7K

1 2

10 mils and < 1"

R610 1K_0402_1%R610 1K_0402_1%

1 2

R611 931_0402_1%R611 931_0402_1%

+AVDD_SATA

SATA_LED#28

+3VS

3 3

1 2

R616 10K_0402_5%

1 2

@

C107

@

1 2

22P_0402_50V8J

C106

@

1 2

22P_0402_50V8J

12

Y7

@

25MHZ_20PF_7A25000012

FCH_SI_SPI_SO FCH_SO_SPI_SI

FCH_SPICS#/FSEL#

R510

@

1M_0603_5%

1M_0603_5% R861

R861

@R510

@

1 2

EMI

@

+3V_SPI

R507 4.7K_0402_5%@R507 4.7K_0402_5%@

1 2

R491 4.7K_0402_5%@R491 4.7K_0402_5%@

+3V_SPI

4 4

1 2

R504 0_0603_5%

FCH_SPICS#/FSEL#_R

FCH_SPI_WP#

FCH_SPI_HOLD#

@

C784 0.1U_0402_16V 4Z

1 2

FCH_+SPI_VCC

U32

@

1

CS#

3

WP#

7 4

SCLK HOLD# GND

MX25L1606EM2I-12G_SO8

SA000041N00

B

SATA_ITX_C_DRX_P0 SATA_ITX_C_DRX_N0

SATA_ITX_C_DRX_P1 SATA_ITX_C_DRX_N1

SATA_CALRP SATA_CALRN

25M_SATA_X1

25M_SATA_X2

FCH_SPICLK_RRFCH_SPICLK

0_0402_5%

T78PADT78PAD

8

VCC

FCH_SPICLK_R

6

FCH_SO_SPI_SI_R

5

SI

FCH_SI_SPI_SO_R

2

SO

U31B

AH9

SATA_TX0P

AJ9

SATA_TX0N

AJ8

SATA_RX0N

AH8

SATA_RX0P

AH10

SATA_TX1P

AJ10

SATA_TX1N

AG10

SATA_RX1N

AF10

SATA_RX1P

AG12

SATA_TX2P

AF12

SATA_TX2N

AJ12

SATA_RX2N

AH12

SATA_RX2P

AH14

SATA_TX3P

AJ14

SATA_TX3N

AG14

SATA_RX3N

AF14

SATA_RX3P

AG17

SATA_TX4P

AF17

SATA_TX4N

AJ17

SATA_RX4N

AH17

SATA_RX4P

AJ18

SATA_TX5P

AH18

SATA_TX5N

AH19

SATA_RX5N

AJ19

SATA_RX5P

AB14

SATA_CALRP

AA14

SATA_CALRN

AD11

SATA_ACT_L/GPIO67

AD16

SATA_X1

AC16

SATA_X2

J5

SPI_DI/GPIO164

E2

SPI_DO/GPIO163

K4

SPI_CLK/GPIO162

K9

SPI_CS1_L/GPIO165

G2

ROM_RST_L/GPIO161

21807-A11-HUDSON-M1_FCBGA605

@

R511

1 2

0_0402_5%

SERIAL ATA

SPI ROM

@

C785

1 2

0.1U_0402_16V4Z

FC_CLK

FC_FBCLKOUT

FC_FBCLKIN

FC_OE_L/GPIOD145

FC_AVD_L/GPIOD146

FC_WE_L/GPIOD148 FC_CE1_L/GPIOD149 FC_CE2_L/GPIOD150

FC_INT1/GPIOD144

GPIOD

FC_INT2/GPIOD147

FC_ADQ0/GPIOD128

FC_ADQ1/GPIOD129

FC_ADQ2/GPIOD130

FC_ADQ3/GPIOD131

FC_ADQ4/GPIOD132

FC_ADQ5/GPIOD133

FC_ADQ6/GPIOD134

FC_ADQ7/GPIOD135

FC_ADQ8/GPIOD136

FC_ADQ9/GPIOD137

FC_ADQ10/GPIOD138 FC_ADQ11/GPIOD139 FC_ADQ12/GPIOD140 FC_ADQ13/GPIOD141 FC_ADQ14/GPIOD142 FC_ADQ15/GPIOD143

HW MONITOR

FANOUT0/GPIO5 2 FANOUT1/GPIO5 3 FANOUT2/GPIO5 4

FANIN0/GPIO56 FANIN1/GPIO57 FANIN2/GPIO58

TEMPIN0/GPIO1 71 TEMPIN1/GPIO1 72 TEMPIN2/GPIO1 73

TEMPIN3/TALERT_L/GPIO174

TEMP_COMM

VIN0/GPIO175 VIN1/GPIO176 VIN2/GPIO177 VIN3/GPIO178 VIN4/GPIO179 VIN5/GPIO180

VIN6/GBE_STAT3/GPIO181

VIN7/GBE_LED3/GPIO182

EMI

NC1 NC2

C

AH28 AG28 AF26

AF28 AG29 AG26 AF27 AE29 AF29 AH27

AJ27 AJ26 AH25 AH24 AG23 AH23 AJ22 AG21 AF21 AH22 AJ23 AF23 AJ24 AJ25 AG25 AH26

W5 W6 Y9

W7 V9 W8

TEMPIN0

B6

TEMPIN1

A6

TEMPIN2

A5 B5 C7

GPIO175

A3

GPIO176

B4

GPIO177

A4

GPIO178

C5

GPIO179

A7

GPIO180

B7

GPIO181

B8

GPIO182

A8

G27 Y2

BT_ON 28

WL_OFF# 28

R612 10K_0402_5%R612 10K_0402_5% R613 10K_0402_5%R613 10K_0402_5% R614 10K_0402_5%R614 10K_0402_5% R615 10K_0402_5%R615 10K_0402_5%

R617 10K_0402_5%R617 10K_0402_5% R618 10K_0402_5%R618 10K_0402_5% R619 10K_0402_5%R619 10K_0402_5% R620 10K_0402_5%R620 10K_0402_5% R621 10K_0402_5%R621 10K_0402_5% R622 10K_0402_5%R622 10K_0402_5% R623 10K_0402_5%@R623 10K_0402_5%@ R624 10K_0402_5%R624 10K_0402_5%

12 12 12 12

12 12 12 12 12 12 12 12

KSI430,31 KSI530,31 KSI630,31 KSI730,31

+3VALW

KSI4 KSI5 KSI6 KSI7

FCH_SPICS#/FSEL# FCH_SPICLK FCH_SO_SPI_SI FCH_SI_SPI_SO

D

VIN6/GBE_STAT3/GPIO181 Enable integrated pull-down/up and leave unconnected

+3VALW

U11

1

VDD

4

VDD

9

VDD

19

VDD

24

A0

22

B0

18

C0

17

D0

14

E0

23

A1

21

B1

16

C1

15

D1

13

E1

PI3V512QE_QSOP24

@

SEL

GND GND GND GND

YA YB YC

YD YE

EC_ON

12

2

FCH_SPICS#/FSEL#_R

5 6

FCH_SO_SPI_SI_R

8

FCH_SI_SPI_SO_R

11

3 7 10 20

FCH_SPICLK_R

E

+3V_SPI

EC_ON 30,33

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2010/06/30 2012/06/30

Compal Secret Data

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

P14-FCH-SATA/SPI

LA-7322P

E

1.0

14 47Thursday, February 17, 2011

1.0

of

A

+3VS

2

C113

C121

1

10U_0603_6.3V6M

1 1

FBMA-L11-201209-221LMA30T_0805

2 2

+3VALW

+1.1VALW

3 3

R632

+1.8VS

1 2

0_0603_5%

+1.1VS

L45

L46

FBMA-L11-201209-221LMA30T_0805

L48

FBMA-L11-160808-221LMT_2P

GPIO I/F implemented: tied to +1.8V_S0 GPIO I/F not implemented: tied to

+1.8V_S0 or 0 ohm to ground

12

R633

@

+3VS

12

C105

12

C85

12

2

C115

C114

1

0.1U_0402_16V7K

10U_0603_6.3V6M

2

C69

C744

1

0_0402_5%

4.7U_0603_6.3V6K

L44

FBMA-L11-160808-221LMT_2P

1

2

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

12

1

C78

C77

2

10U_0603_6.3V6M

1

C86

C87

2

10U_0603_6.3V6M

2

C116

1

0.1U_0402_16V7K

+VDDIO_18_FC

2

C746

1

0.1U_0402_16V7K

+VDDPL33_PCIE

1

C76

2

2.2U_0603_6.3V6K

2

C80

C79

1

0.1U_0402_16V7K

1U_0402_6.3V6K

+PCIE_VDDAN

0.1U_0402_16V7K

+VDDPL_33_SATA

+AVDD_SATA

1115.6mA

1345.2mA

+AVDD_USB

1

C88

2

1U_0402_6.3V6K

1

C93

2

534.5mA

1

C89

2

1U_0402_6.3V6K

0.1U_0402_16V7K

+VDDAN_11_USB

2

88.6mA

C94

1

0.1U_0402_16V7K

2.2U_0603_6.3V6K

42mA

0.16mA

22.5mA

15.5mA

B

U31C

AH1

VDDIO_33_PCIGP_1

V6

VDDIO_33_PCIGP_2

Y19

VDDIO_33_PCIGP_3

AE5

VDDIO_33_PCIGP_4

AC21

VDDIO_33_PCIGP_5

AA2

VDDIO_33_PCIGP_6

AB4

VDDIO_33_PCIGP_7

AC8

VDDIO_33_PCIGP_8

AA7

VDDIO_33_PCIGP_9

AA9

VDDIO_33_PCIGP_10

AF7

VDDIO_33_PCIGP_11

AA19

VDDIO_33_PCIGP_12

AF22

VDDIO_18_FC_1

AE25

VDDIO_18_FC_2

AF24

VDDIO_18_FC_3

AC22

VDDIO_18_FC_4

AE28

VDDPL_33_PCIE

U26

VDDAN_11_PCIE_1

V22

VDDAN_11_PCIE_2

V26

VDDAN_11_PCIE_3

V27

VDDAN_11_PCIE_4

V28

VDDAN_11_PCIE_5

V29

VDDAN_11_PCIE_6

W22

VDDAN_11_PCIE_7

W26

VDDAN_11_PCIE_8

AD14

VDDPL_33_SATA

AJ20

VDDAN_11_SATA_1

AF18

VDDAN_11_SATA_4

AH20

VDDAN_11_SATA_2

AG19

VDDAN_11_SATA_3

AE18

VDDAN_11_SATA_5

AD18

VDDAN_11_SATA_6

AE16

VDDAN_11_SATA_7

A18

VDDAN_33_USB_S_1

A19

VDDAN_33_USB_S_2

A20

VDDAN_33_USB_S_3

B18

VDDAN_33_USB_S_4

B19

VDDAN_33_USB_S_5

B20

VDDAN_33_USB_S_6

C18

VDDAN_33_USB_S_7

C20

VDDAN_33_USB_S_8

D18

VDDAN_33_USB_S_9

D19

VDDAN_33_USB_S_10

D20

VDDAN_33_USB_S_11

E19

VDDAN_33_USB_S_12

C11

VDDAN_11_USB_S_1

D11

VDDAN_11_USB_S_2

21807-A11-HUDSON-M1_FCBGA605

POWER

PCI/GPIO I/O

FLASH I/O

PCI EXPRESS

SERIAL ATA

USB I/O

VDDCR_11_1 VDDCR_11_2 VDDCR_11_3 VDDCR_11_4 VDDCR_11_5 VDDCR_11_6 VDDCR_11_7 VDDCR_11_8 VDDCR_11_9

VDDAN_11_CLK_1 VDDAN_11_CLK_2 VDDAN_11_CLK_3 VDDAN_11_CLK_4 VDDAN_11_CLK_5 VDDAN_11_CLK_6 VDDAN_11_CLK_7 VDDAN_11_CLK_8

VDDRF_GBE_S

VDDIO_33_GBE_S

GBE LAN

VDDCR_11_GBE_S_1 VDDCR_11_GBE_S_2

VDDIO_GBE_S_1 VDDIO_GBE_S_2

VDDIO_33_S_1 VDDIO_33_S_2 VDDIO_33_S_3 VDDIO_33_S_4 VDDIO_33_S_5 VDDIO_33_S_6 VDDIO_33_S_7 VDDIO_33_S_8

CORE S5CORE S0 CLKGEN I/O 3.3V_S5 I/O

VDDCR_11_S_1 VDDCR_11_S_2

VDDIO_AZ_S

VDDCR_11_USB_S_1 VDDCR_11_USB_S_2

VDDPL_33_SYS

PLL

VDDPL_11_SYS_S

VDDPL_33_USB_S

VDDAN_33_HWM_S

VDDXL_33_S

C

N13 R15 N17 U13 U17 V12 V18 W12 W18

+VDDAN_11_CLK

K28 K29 J28 K26 J21 J20 K21 J22

V1

M10

L7 L9

M6 P8

49.5mA

A21 D21 B21 K10 L10 J9 T6 T8

F26 G26

15.3mA

M8

58mA

A11 B11

46.5mA

M21

65.3mA

L22

16.1mA

F19

11.4mA

D6

+VDDXL_33_S

L20

5mA

979.4mA

165.2mA

+VDDCR_11_USB

1

C738

2

0.1U_0402_16V7K

382.9mA

1

C72

2

0.1U_0402_16V7K

+VDDIO_AZ

+VDDPL33

+VDDPL11

+AVDD_USB

+VDDAN33_HWM

1

C95

2

2.2U_0603_6.3V6K

1

C70

C73

C81

C83

1

C117

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C74

2

1U_0402_6.3V6K

0.1U_0402_16V7K

1

C82

2

1

2

FBMA-L11-160808-221LMT_2P

2.2U_0603_6.3V6K

1

C84

2

1U_0402_6.3V6K

L49

12

D

1

C71

C118

2

1U_0402_6.3V6K

10U_0603_6.3V6M

1

C75

C743

2

1U_0402_6.3V6K

10U_0603_6.3V6M

+3VALW

+1.1VALW

1

C90

C91

2

0.1U_0402_16V7K

+3VS

+1.1VS

1

FBMA-L11-201209-221LMA30T_0805

C109

2

10U_0603_6.3V6M

1

C92

2

0.1U_0402_16V7K

L43

12

+VDDCR_11_USB

FBMA-L11-160808-221LMT 0603

L107

@

Reserve

L47

FBMA-L11-201209-221LMA30T_0805

10U_0603_6.3V6M

12

+1.1VS

12

5

VOUT

4

FB

APL5317

+1.1VALW

+1.1VS

C119

GND

1

+

2

VIN

EN

E

330U_D2_2.5VY_R9M

@

U85

1

2

3

1U_0402_6.3V6K

1 2

C989

@

C68

+3VALW

1

2

10U_0603_6.3V6M

+AVDD_SATA

1

C776

2

0.1U_0402_16V7K

Security Classification

Issued Date

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEER ING DRAWING IS THE PROPRIETAR Y PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRI OR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

12

A

+VDDPL_33_SATA

+VDDPL11

+VDDPL33

+1.1VS

+3VALW

L51

+3VS

+1.1VALW

4 4

+3VS

L51

FBMA-L11-160808-221LMT_2P

C777 2.2U_0603_6.3V6KC777 2.2U_0603_6.3V6K

1 2

L52

FBMA-L11-160808-221LMT_2P

C99 2.2U_0603_6.3V6KC99 2.2U_0603_6.3V6K

1 2

L55

FBMA-L11-160808-221LMT_2P

C120 2.2U_0603_6.3V6KC120 2.2U_0603_6.3V6K

1 2

L50

FBMA-L11-201209-221LMA30T_0805

FBMA-L11-160808-221LMT_2P

12

L53

12

1

C96

C108

2

10U_0603_6.3V6M

1

2

C100

C782

2

1

2.2U_0603_6.3V6K

B

1

C97

C778

2

1U_0402_6.3V6K

+VDDAN33_HWM

0.1U_0402_16V7K

1

C775

2

1U_0402_6.3V6K

1

+VDDIO_AZ +3VALW

1 2

R634 0_0603_5%

1 2

R635 0_0603_5%R635 0_0603_5%

1

C98

2.2U_0603_6.3V6K

2

2010/06/30 2012/06/30

C

@

For 3V AZ device

Compal Secret Data

+3VS

Deciphered Date

Compal Electronics, Inc.

Title

Size Document Number Rev

Custom

Date: Sheet

D

Date: Sheet

Compal Electronics, Inc.

P15-FCH PWR

LA-7322P

E

1.0

15 47Thursday, February 17, 2011

1.0

of

Compal LA-7322P PBL60, K53U Schematic