LA-6582P
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
148Friday, July 02, 2010
2009/5/12 2010/04/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
148Friday, July 02, 2010
2009/5/12 2010/04/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
148Friday, July 02, 2010
2009/5/12 2010/04/15
Compal Electronics, Inc.
Intel Arrandale Processor with DDRIII + Ibex Peak-M
PEW71_81_91 UMA <LA-6582P> M/B Schematics Document
REV:0.2
Compal Confidential
2010-06-18
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
248Friday, July 02, 2010
2009/5/12 2010/04/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
248Friday, July 02, 2010
2009/5/12 2010/04/15
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
248Friday, July 02, 2010
2009/5/12 2010/04/15
Compal Electronics, Inc.
USB port 8USB port 11
6.4G/8.5G/10.6G
100M/133M/166M(CFD)
100MHz
33MHz
100MHz
100MHz
1GB/s x4
DMI x4
FDI x8
page 34
port 2,4 port 1
LVDS Conn.
page 22
CRT Conn.
page 23
HDMI(UMA)
page 13
SPI
Model Name PEW71_81 UMA
3.3V 24MHz
GIGA LAN
BCM57780
page 27
MINI Card x1
WLAN
CMOS
Camera
PCI-Express x 8 (ABD PCIE1 2.5GT/S CKD PCIE1/2 2.5/5GT/S)
Dual Channel
2.7GT/s
File Name : LA-6582P
Touch Pad
LPC BUS
page 33
Processor
Compal Confidential
page 34
Int.KBD
page 31
BANK 0, 1, 2, 3
USB conn x3
(UMA)
Arrandale (UMA)
3.3V 48MHz
page 30
Fan Control
204pin DDRIII-SO-DIMM X2
Intel
BIOS ROM
1.5V DDRIII 800/1066/1333
page 31
HDA Codec
ALC272X
Memory BUS(DDRIII)
PCH
HD Audio
page 26
page 4,5,6,7,8,9
Ibex Peak-M
page 10,11
page 31
ENE KB926
Audio AMP
TPA6017
page 26
USB port 0 (Left Low)
USB Port 1 (Left High)
USB port 2 (sub board)
page 29page 29 page 22
rPGA988A
Intel
page 24
Bluetooth
Conn
port 1
SATA ODD
Conn.
page 25
SPI ROM
CRT(UMA)
LVDS(UMA)
USBx14
page 13,14,15,16,17
18,19,20,21
port 0
page 25
Int. Speaker
100MHz
SATA x 6 (GEN1 1.5GT/S ,GEN2 3GT/S)
SATA HDD
Conn.
HDMI Conn.
USB port 9
Card
Reader
page 29
Level Shift
page 24
USB port 12
Mini card
page 26
Power ON/Off CKT.
DC/DC Interface CKT.
Power Circuit DC/DC CKT.
RTC CKT. LS-6581P USB/B
LS-6582P PWR/B
LS-6583P ODD/B
133/120/100/96/14.318MHZ to PCH
48MHZ to CardReader
Clock Generator
IDT: 9LRS3199AKLFT
SILEGO: SLG8SP587
page 12
RJ45 Conn.
page 28
ZZZ1
M/B PCB
DA60000IQ00
ZZZ1
M/B PCB
DA60000IQ00
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
348Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
348Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
348Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator
+1.5VS
+1.8VS 1.8V switched power rail
+3VALW 3.3V always on power rail
EC SM Bus1 address
Device
OFF
+1.05VS_VTT 1.05V switched power rail (1.05 for AUB CPU) ON OFF OFF
1.5V switched power rail
+CPU_CORE
Ibex SM Bus address
Device Address
Address Address
Voltage Rails
VIN
B+
+1.05VS
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
1.05V switched power rail for PCH
External PCI Devices
Device IDSEL# REQ#/GNT# Interrupts
ON
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
ON OFF
ON ON*
ON OFF OFF
S1 S3 S5
ON
ON OFF
N/A N/A N/A
N/AN/AN/A
Power Plane Description
EC SM Bus2 address
Device
Smart Battery
OFF
OFF
+1.5V 1.5V power rail for DDRIII ON ON OFF
0001 011X b
ON
1101 0010b
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
Clock Generator
(9LRS3199AKLFT, SLG8SP587)
+3VS
+5VALW
+5VS
3.3V switched power rail
5V always on power rail
5V switched power rail OFF
ON
OFF
OFFON
ON OFF
ON*ON
+3V_LAN 3.3V power rail for LAN ON ON ON*
+RTCVCC RTC power
+VSB VSB always on power rail ONON
ON ON
ON*
ON
Ext3 Right USB Ext3 Right USB
Ext1 Left Low USB
Ext2 Left High USB
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3#
SLP_S4# SLP_S5# +VALW +V +VS Clock
USB 2.0 USB 1.1 Port
4 External
USB Port
3 External
USB Port
Ext1 Left Low USB
Ext2 Left High USB
Camera
1st Min-Card
Card Reader
Camera
1st Min-Card
Card Reader
ON
Blue Tooth Blue Tooth
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
0
1
2
3
OFF
OFF
LOW
LOW LOW
4
5
6
7
8
LOW LOW
LOWLOWLOW
LOW
9
10
11
12
13
LOW
LOW
HIGH HIGH HIGH
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
HIGH
HIGHHIGHHIGH
HIGH
UHCI5
UHCI6
EHCI1
EHCI2
USB Port Table
HIGH
HIGH
BTO Option Table
BTO Item BOM Structure
HDMI
HDMI@
Project IDBoard ID
Project ID / Board ID Table for EC-AD channel
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc
Rb / Rd V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID
V typ
AD_BID
V
AD_BID
max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
0.1
0.2
0.3
1.0
Original NEW70/80/90/50/71/91
PEW71/81/91 Audio Mono/Crystal
PEW71/81/91 Audio Mono/SUSCLK
NEW71/91 Optumis
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PEG_IRCOMP
EXP_RBIAS
DMI_PTX_HRX_N0
H_FDI_TXP0
H_FDI_TXP1
H_FDI_TXP2
H_FDI_TXP3
H_FDI_TXP4
H_FDI_TXP5
H_FDI_TXP6
H_FDI_TXP7
H_FDI_TXN0
H_FDI_TXN1
H_FDI_TXN2
H_FDI_TXN3
H_FDI_TXN4
H_FDI_TXN5
H_FDI_TXN6
H_FDI_TXN7
DMI_PTX_HRX_N1
DMI_PTX_HRX_N2
DMI_PTX_HRX_N3
DMI_PTX_HRX_P0
DMI_PTX_HRX_P1
DMI_PTX_HRX_P3
DMI_PTX_HRX_P2
DMI_HTX_PRX_N0
DMI_HTX_PRX_N1
DMI_HTX_PRX_N3
DMI_HTX_PRX_N2
DMI_HTX_PRX_P0
DMI_HTX_PRX_P1
DMI_HTX_PRX_P3
DMI_HTX_PRX_P2
CFG3
CFG4
CFG7
H_RSVD17_R
H_RSVD18_R
CFG0
RSVD65_R
RSVD64_R
H_FDI_FSYNC0<15>
H_FDI_FSYNC1<15>
H_FDI_INT<15>
H_FDI_LSYNC0<15>
H_FDI_LSYNC1<15>
DMI_HTX_PRX_N[0..3] <15>
DMI_HTX_PRX_P[0..3] <15>
DMI_PTX_HRX_N[0..3] <15>
DMI_PTX_HRX_P[0..3] <15>
H_FDI_TXN[0..7] <15>
H_FDI_TXP[0..7] <15>
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
448Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
448Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
448Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
WW41 Recommend not pull down
PCIE2.0 Jitter is over on ES1
*1:Disabled; No Physical Display Port
attached to Embedded Display Port
0:Enabled; An external Display Port
device is connected to the Embedded
Display Port
*:Default
CFG4 - Display Port Presence
*1 :Normal Operation
0 :Lane Numbers Reversed
15 -> 0, 14 -> 1, ...
CFG0 - PCI-Express Configuration Select
CFG3 - PCI-Express Static Lane Reversal
*1:Single PEG
0:Bifurcation enabled
eDP Signals Mapping
PEG_HTX_C_GRX_N1
PEG_GTX_C_HRX_N2
PEG_HTX_C_GRX_P2
PEG_HTX_C_GRX_P0
PEG_HTX_C_GRX_N2
PEG_HTX_C_GRX_P3
PEG_GTX_C_HRX_P3
PEG_HTX_C_GRX_N0
PEG_HTX_C_GRX_N3
PEG_HTX_C_GRX_P1
PEG_GTX_C_HRX_P2
eDP_TX2
PEG_HTX_C_GRX_N14
PEG Singals
PEG_GTX_C_HRX_N13
eDP_HPD#
eDP_TX3
PEG_HTX_C_GRX_P13
Lane Reversal
PEG_GTX_C_HRX_P12
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_P15
eDP_TX#1
PEG_HTX_C_GRX_P12
eDP Singal
eDP_TX0
eDP_TX#0 PEG_HTX_C_GRX_N15
eDP_TX#2
PEG_HTX_C_GRX_N12
eDP_AUX
eDP_TX1 PEG_HTX_C_GRX_P14
eDP_TX#3
PEG_GTX_C_HRX_P13
eDP_AUX#
(CFD Only)
(CFD Only)
R9
0_0402_5%
@
R9
0_0402_5%
@
12
R8
3.01K_0402_1%
@R8
3.01K_0402_1%
@
1 2
R7
3.01K_0402_1%
@R7
3.01K_0402_1%
@
1 2
R3 750_0402_1%R3 750_0402_1%
1 2
R6
3.01K_0402_1% @
R6
3.01K_0402_1% @
1 2
R11
0_0402_5%
@
R11
0_0402_5%
@
1 2
RESERVED
JCPU1E
IC,AUB_CFD_rPGA,R1P0
CONN@
RESERVED
JCPU1E
IC,AUB_CFD_rPGA,R1P0
CONN@
CFG[0]
AM30
CFG[1]
AM28
CFG[2]
AP31
CFG[3]
AL32
CFG[4]
AL30
CFG[5]
AM31
CFG[6]
AN29
CFG[7]
AM32
CFG[8]
AK32
CFG[9]
AK31
CFG[10]
AK28
CFG[11]
AJ28
CFG[12]
AN30
CFG[13]
AN32
CFG[14]
AJ32
CFG[15]
AJ29
CFG[16]
AJ30
CFG[17]
AK30
RSVD34
AH25
RSVD35
AK26
RSVD38
AJ26
RSVD_NCTF_42
AT3
RSVD39
AJ27
RSVD_NCTF_40
AP1
RSVD_NCTF_41
AT2
RSVD_NCTF_43
AR1
RSVD_TP_86
H16
RSVD45
AL28
RSVD46
AL29
RSVD47
AP30
RSVD48
AP32
RSVD49
AL27
RSVD50
AT31
RSVD51
AT32
RSVD52
AP33
RSVD53
AR33
RSVD_NCTF_54
AT33
RSVD_NCTF_55
AT34
RSVD_NCTF_56
AP35
RSVD_NCTF_57
AR35
RSVD58
AR32
RSVD_NCTF_30
C35
RSVD_NCTF_31
B35
RSVD_NCTF_28
A34
RSVD_NCTF_29
A33
RSVD27
J28
RSVD26
J29
RSVD16
A19
RSVD15
B19
RSVD17
A20
RSVD18
B20
RSVD20
T9
RSVD19
U9
RSVD22
AB9
RSVD21
AC9
RSVD_NCTF_23
C1
RSVD_NCTF_24
A3
RSVD_TP_66
AA5
RSVD_TP_67
AA4
RSVD_TP_68
R8
RSVD_TP_71
AA2
RSVD_TP_72
AA1
RSVD_TP_73
R9
RSVD_TP_69
AD3
RSVD_TP_74
AG7
RSVD_TP_70
AD2
RSVD_TP_75
AE3
RSVD_TP_76
V4
RSVD_TP_77
V5
RSVD_TP_78
N2
RSVD_TP_81
W3
RSVD_TP_82
W2
RSVD_TP_83
N3
RSVD_TP_79
AD5
RSVD_TP_84
AE5
RSVD_TP_80
AD7
RSVD_TP_85
AD9
RSVD36
AL26
RSVD_NCTF_37
AR2
RSVD1
AP25
RSVD2
AL25
RSVD3
AL24
RSVD4
AL22
RSVD5
AJ33
RSVD6
AG9
RSVD7
M27
RSVD8
L28
SA_DIMM_VREF
J17
SB_DIMM_VREF
H17
RSVD11
G25
RSVD12
G17
RSVD13
E31
RSVD14
E30
RSVD32
AJ13
RSVD33
AJ12
RSVD_TP_59
E15
RSVD_TP_60
F15
KEY
A2
RSVD62
D15
RSVD63
C15
RSVD64
AJ15
RSVD65
AH15
VSS
AP34
R10
0_0402_5%
@
R10
0_0402_5%
@
12
R1 49.9_0402_1%R1 49.9_0402_1%
1 2
R5
3.01K_0402_1% @
R5
3.01K_0402_1% @
1 2
R12
0_0402_5%
@
R12
0_0402_5%
@
1 2
PCI EXPRESS -- GRAPHICS
DMI Intel(R) FDI
JCPU1A
IC,AUB_CFD_rPGA,R1P0
CONN@
PCI EXPRESS -- GRAPHICS
DMI Intel(R) FDI
JCPU1A
IC,AUB_CFD_rPGA,R1P0
CONN@
DMI_RX#[0]
A24
DMI_RX#[1]
C23
DMI_RX#[2]
B22
DMI_RX#[3]
A21
DMI_RX[0]
B24
DMI_RX[1]
D23
DMI_RX[2]
B23
DMI_RX[3]
A22
DMI_TX#[0]
D24
DMI_TX#[1]
G24
DMI_TX#[2]
F23
DMI_TX#[3]
H23
DMI_TX[0]
D25
DMI_TX[1]
F24
DMI_TX[3]
G23
DMI_TX[2]
E23
FDI_TX#[0]
E22
FDI_TX#[1]
D21
FDI_TX#[2]
D19
FDI_TX#[3]
D18
FDI_TX#[4]
G21
FDI_TX#[5]
E19
FDI_TX#[6]
F21
FDI_TX#[7]
G18
FDI_TX[0]
D22
FDI_TX[1]
C21
FDI_TX[2]
D20
FDI_TX[3]
C18
FDI_TX[4]
G22
FDI_TX[5]
E20
FDI_TX[6]
F20
FDI_TX[7]
G19
FDI_FSYNC[0]
F17
FDI_FSYNC[1]
E17
FDI_INT
C17
FDI_LSYNC[0]
F18
FDI_LSYNC[1]
D17
PEG_ICOMPI
B26
PEG_ICOMPO
A26
PEG_RBIAS
A25
PEG_RCOMPO
B27
PEG_RX#[0]
K35
PEG_RX#[1]
J34
PEG_RX#[2]
J33
PEG_RX#[3]
G35
PEG_RX#[4]
G32
PEG_RX#[5]
F34
PEG_RX#[6]
F31
PEG_RX#[7]
D35
PEG_RX#[8]
E33
PEG_RX#[9]
C33
PEG_RX#[10]
D32
PEG_RX#[11]
B32
PEG_RX#[12]
C31
PEG_RX#[13]
B28
PEG_RX#[14]
B30
PEG_RX#[15]
A31
PEG_RX[0]
J35
PEG_RX[1]
H34
PEG_RX[2]
H33
PEG_RX[3]
F35
PEG_RX[4]
G33
PEG_RX[5]
E34
PEG_RX[6]
F32
PEG_RX[7]
D34
PEG_RX[8]
F33
PEG_RX[9]
B33
PEG_RX[10]
D31
PEG_RX[11]
A32
PEG_RX[12]
C30
PEG_RX[13]
A28
PEG_RX[14]
B29
PEG_RX[15]
A30
PEG_TX#[0]
L33
PEG_TX#[1]
M35
PEG_TX#[2]
M33
PEG_TX#[3]
M30
PEG_TX#[4]
L31
PEG_TX#[5]
K32
PEG_TX#[6]
M29
PEG_TX#[7]
J31
PEG_TX#[8]
K29
PEG_TX#[9]
H30
PEG_TX#[10]
H29
PEG_TX#[11]
F29
PEG_TX#[12]
E28
PEG_TX#[13]
D29
PEG_TX#[14]
D27
PEG_TX#[15]
C26
PEG_TX[0]
L34
PEG_TX[1]
M34
PEG_TX[2]
M32
PEG_TX[3]
L30
PEG_TX[4]
M31
PEG_TX[5]
K31
PEG_TX[6]
M28
PEG_TX[7]
H31
PEG_TX[8]
K28
PEG_TX[9]
G30
PEG_TX[10]
G29
PEG_TX[11]
F28
PEG_TX[12]
E27
PEG_TX[13]
D28
PEG_TX[14]
C27
PEG_TX[15]
C25
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SM_RCOMP_2
H_VTTPWRGD
H_COMP3
H_COMP1
H_COMP0
H_COMP2
SKTOCC#_R
XDP_DBRESET#
PLT_RST#_R
H_CATERR#
H_PECI_R
PM_EXTTS#1_R
H_PROCHOT#
H_THERMTRIP#_R
H_CPURST#
H_PM_SYNC_R
XDP_TRST#
PM_DRAM_PWRGD_R
XDP_TDO_M
XDP_TDI_M
XDP_DBR#_R
H_CPUPWRGD_1
H_CPUPWRGD_0
H_VTTPWRGD
PM_DRAM_PWRGD_R
H_VTTPWRGD_R
H_VTTPWRGD
H_CATERR#
H_PROCHOT#
H_CPURST#
H_VTTPWRGD_R
PM_EXTTS#0
SM_RCOMP_0
SM_RCOMP_1
XDP_TDO
XDP_DBRESET#
XDP_TDO_M
XDP_TDI_M
XDP_TDO
XDP_TRST#
SM_RCOMP_1
SM_RCOMP_2
SM_RCOMP_0
H_TCK
H_TMS
H_TDI
PLT_RST#<17,27,30>
H_PECI<18>
H_THERMTRIP#<18>
PM_EXTTS#0_1 <10,11>
H_PM_SYNC<15>
H_CPUPWRGD<18>
SM_DRAMRST# <10>
PM_DRAM_PWRGD<15>
XDP_DBRESET# <15>
H_PROCHOT#<45>
CLK_CPU_DMI# <14>
CLK_CPU_DMI <14>
CLK_CPU_BCLK# <18>
CLK_CPU_BCLK <18>
H_VTTPWRGD<43>
CLK_CPU_DP <14>
CLK_CPU_DP# <14>
+1.05VS_VTT
+3VALW
+1.5V_1
+3VALW
+1.05VS_VTT
+3VS
+1.05VS_VTT
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
548Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
548Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
548Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
2009/2/4
#414044 DG
Update Rev1.11
2009/08/14 #425302
CP_S3PowerReduction
WhitePaper_Rev0.9
#425302
CP_S3PowerReduction
WhitePaper_Rev0.7
2009/04/23
Intel CRB 1.55 Update
Change R68 to 1.1K_1%, R71 to 3.01K_1%
Need to check Voltage Level
2009/8/14
change back to 2K
del net for XDP remove
del R27 / R29 / R30 / R31 / R33 for XDP remove
del net for XDP remove
del R41 / R43 / R48 / R49
XDP remove
del net for XDP remove
U1 / U2
change to SA00000OH00
20100610 Add
R59 68_0402_5% R59 68_0402_5%
12
R69
1.5K_0402_1%
R69
1.5K_0402_1%
12
R50
0_0402_5%
R50
0_0402_5%
1 2
R18 20_0402_1%R18 20_0402_1%
12
R57
750_0402_1%
R57
750_0402_1%
12
R71
3.01K_0402_1%
@
R71
3.01K_0402_1%
@
12
R56
1.5K_0402_1%
R56
1.5K_0402_1%
1 2
R62
1K_0402_1%
R62
1K_0402_1%
12
R28 100K_0402_5%R28 100K_0402_5%
1 2
R70 51_0402_5%R70 51_0402_5%
1 2
R26
0_0402_5%
R26
0_0402_5%
1 2
R38 100_0402_1%R38 100_0402_1%
1 2
R39 24.9_0402_1%R39 24.9_0402_1%
1 2
U1
MC74VHC1G08DFT2G_SC70-5
U1
MC74VHC1G08DFT2G_SC70-5
B
2
A
1
Y
4
P
5
G
3
R19 20_0402_1%R19 20_0402_1%
12
R32 10K_0402_5%R32 10K_0402_5%
1 2
T26
PAD
@
T26
PAD
@
R47
0_0402_5%
R47
0_0402_5%
1 2
R42
0_0402_5%
R42
0_0402_5%
1 2
R60 68_0402_5%@R60 68_0402_5%@
12
R61
2K_0402_1%
R61
2K_0402_1%
1 2
U2
MC74VHC1G08DFT2G_SC70-5
U2
MC74VHC1G08DFT2G_SC70-5
B
2
A
1
Y
4
P
5
G
3
R36
0_0402_5%
R36
0_0402_5%
1 2
R72
750_0402_1%
R72
750_0402_1%
12
R35 0_0402_5%R35 0_0402_5%
1 2
R20 49.9_0402_1%R20 49.9_0402_1%
12
T27
PAD
@
T27
PAD
@
T24
PAD
@
T24
PAD
@
R37 51_0402_5%R37 51_0402_5%
1 2
R68
1.1K_0402_1%
@
R68
1.1K_0402_1%
@
12
CLOCKS
MISC THERMAL
PWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
IC,AUB_CFD_rPGA,R1P0
CONN@
CLOCKS
MISC THERMAL
PWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
IC,AUB_CFD_rPGA,R1P0
CONN@
SM_RCOMP[1]
AM1
SM_RCOMP[2]
AN1
SM_DRAMRST#
F6
SM_RCOMP[0]
AL1
BCLK#
B16
BCLK
A16
BCLK_ITP#
AT30
BCLK_ITP
AR30
PEG_CLK#
D16
PEG_CLK
E16
DPLL_REF_SSCLK#
A17
DPLL_REF_SSCLK
A18
CATERR#
AK14
COMP3
AT23
PECI
AT15
PROCHOT#
AN26
THERMTRIP#
AK15
RESET_OBS#
AP26
VCCPWRGOOD_1
AN14
VCCPWRGOOD_0
AN27
SM_DRAMPWROK
AK13
VTTPWRGOOD
AM15
RSTIN#
AL14
PM_EXT_TS#[0]
AN15
PM_EXT_TS#[1]
AP15
PRDY#
AT28
PREQ#
AP27
TCK
AN28
TMS
AP28
TRST#
AT27
TDI
AT29
TDO
AR27
TDI_M
AR29
TDO_M
AP29
DBR#
AN25
BPM#[0]
AJ22
BPM#[1]
AK22
BPM#[2]
AK24
BPM#[3]
AJ24
BPM#[4]
AJ25
BPM#[5]
AH22
BPM#[6]
AK23
BPM#[7]
AH23
COMP2
AT24
PM_SYNC
AL15
TAPPWRGOOD
AM26
COMP1
G16
COMP0
AT26
SKTOCC#
AH24
R34 10K_0402_5%R34 10K_0402_5%
1 2
R45
0_0402_5%
R45
0_0402_5%
12
R44
0_0402_5%
R44
0_0402_5%
1 2
R46 0_0402_5%R46 0_0402_5%
1 2
R40 130_0402_1%R40 130_0402_1%
1 2
R21 49.9_0402_1%R21 49.9_0402_1%
12
R52 0_0402_5%
@
R52 0_0402_5%
@
1 2
T25
PAD
@
T25
PAD
@
R67 1K_0402_5%R67 1K_0402_5%
1 2
R58 49.9_0402_1% R58 49.9_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D63
DDR_A_D62
DDR_A_D8
DDR_A_D5
DDR_A_D4
DDR_A_D3
DDR_A_D7
DDR_A_D6
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D47
DDR_A_D46
DDR_A_D43
DDR_A_D42
DDR_A_D41
DDR_A_D40
DDR_A_D45
DDR_A_D44
DDR_A_D39
DDR_A_D38
DDR_A_D35
DDR_A_D34
DDR_A_D33
DDR_A_D32
DDR_A_D37
DDR_A_D36
DDR_A_D61
DDR_A_D60
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_D55
DDR_A_D54
DDR_A_D51
DDR_A_D50
DDR_A_D49
DDR_A_D48
DDR_A_D53
DDR_A_D52
DDR_A_D31
DDR_A_D30
DDR_A_D27
DDR_A_D26
DDR_A_D25
DDR_A_D24
DDR_A_D15
DDR_A_D14
DDR_A_D11
DDR_A_D10
DDR_A_D9
DDR_A_D13
DDR_A_D12
DDR_A_D29
DDR_A_D28
DDR_A_D23
DDR_A_D22
DDR_A_D19
DDR_A_D18
DDR_A_D17
DDR_A_D16
DDR_A_D21
DDR_A_D20
DDR_A_BS2
DDR_A_BS1
DDR_A_BS0
DDR_A_WE#
DDR_A_RAS#
DDR_A_CAS#
DDR_A_MA14
DDR_A_MA0
DDR_A_MA1
DDR_A_MA4
DDR_A_MA2
DDR_A_MA3
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA12
DDR_A_MA13
DDR_A_MA11
DDR_A_MA10
DDR_A_MA15
DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#3
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS1
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DM7
DDR_A_DM5
DDR_A_DM2
DDR_A_DM1
DDR_A_DM6
DDR_A_DM4
DDR_A_DM0
DDR_A_DM3
DDR_B_D32
DDR_B_D33
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D48
DDR_B_D49
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D50
DDR_B_D51
DDR_B_D56
DDR_B_D57
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63
DDR_B_D58
DDR_B_D59
DDR_B_D34
DDR_B_D35
DDR_B_D40
DDR_B_D41
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D42
DDR_B_D43
DDR_B_D0
DDR_B_D1
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D16
DDR_B_D17
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D26
DDR_B_D27
DDR_B_D2
DDR_B_D3
DDR_B_D8
DDR_B_D9
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D10
DDR_B_D11
DDR_B_MA2
DDR_B_MA3
DDR_B_MA10
DDR_B_MA11
DDR_B_MA8
DDR_B_MA9
DDR_B_MA0
DDR_B_MA6
DDR_B_MA7
DDR_B_MA1
DDR_B_MA4
DDR_B_MA5
DDR_B_MA14
DDR_B_MA12
DDR_B_MA13
DDR_B_MA15
DDR_B_DQS#5
DDR_B_DQS#7
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#1
DDR_B_DQS#0
DDR_B_DQS#6
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS0
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS6
DDR_B_DQS2
DDR_B_DQS1
DDR_B_DM3
DDR_B_DM0
DDR_B_DM1
DDR_B_DM5
DDR_B_DM6
DDR_B_DM7
DDR_B_DM2
DDR_B_DM4
DDR_B_BS2
DDR_B_BS1
DDR_B_BS0
DDR_B_CAS#
DDR_B_WE#
DDR_B_RAS#
DDR_A_BS0<10>
DDR_A_BS1<10>
DDR_A_BS2<10>
DDR_A_CAS#<10>
DDR_A_RAS#<10>
DDR_A_WE#<10>
DDR_B_BS0<11>
DDR_B_BS1<11>
DDR_B_BS2<11>
DDR_B_CAS#<11>
DDR_B_RAS#<11>
DDR_B_WE#<11>
DDR_A_CLK0 <10>
DDR_A_CLK1 <10>
DDR_B_CLK0 <11>
DDR_B_CLK1 <11>
DDR_A_CLK0# <10>
DDR_A_CLK1# <10>
DDR_B_CLK0# <11>
DDR_B_CLK1# <11>
DDR_A_CKE0 <10>
DDR_A_CKE1 <10>
DDR_B_CKE0 <11>
DDR_B_CKE1 <11>
DDR_A_CS0# <10>
DDR_A_CS1# <10>
DDR_B_CS0# <11>
DDR_B_CS1# <11>
DDR_A_ODT0 <10>
DDR_A_ODT1 <10>
DDR_B_ODT0 <11>
DDR_B_ODT1 <11>
DDR_B_MA[0..15]<11>
DDR_B_DQS[0..7]<11>
DDR_B_DQS#[0..7]<11>
DDR_B_DM[0..7]<11>
DDR_B_D[0..63]<11>
DDR_A_D[0..63]<10>
DDR_A_DM[0..7]<10>
DDR_A_DQS#[0..7]<10>
DDR_A_DQS[0..7]<10>
DDR_A_MA[0..15]<10>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
648Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
648Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
B
648Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
DDR SYSTEM MEMORY - B
JCPU1D
IC,AUB_CFD_rPGA,R1P0
CONN@
DDR SYSTEM MEMORY - B
JCPU1D
IC,AUB_CFD_rPGA,R1P0
CONN@
SB_BS[0]
AB1
SB_BS[1]
W5
SB_BS[2]
R7
SB_CAS#
AC5
SB_RAS#
Y7
SB_WE#
AC6
SB_CK[0]
W8
SB_CK[1]
V7
SB_CK#[0]
W9
SB_CK#[1]
V6
SB_CKE[0]
M3
SB_CKE[1]
M2
SB_CS#[0]
AB8
SB_CS#[1]
AD6
SB_ODT[0]
AC7
SB_ODT[1]
AD1
SB_DM[0]
D4
SB_DM[1]
E1
SB_DM[2]
H3
SB_DM[3]
K1
SB_DM[4]
AH1
SB_DM[5]
AL2
SB_DM[6]
AR4
SB_DM[7]
AT8
SB_DQS[4]
AG2
SB_DQS#[4]
AH2
SB_DQS[5]
AL5
SB_DQS#[5]
AL4
SB_DQS[6]
AP5
SB_DQS#[6]
AR5
SB_DQS[7]
AR7
SB_DQS#[7]
AR8
SB_DQS[0]
C5
SB_DQS#[0]
D5
SB_DQS[1]
E3
SB_DQS#[1]
F4
SB_DQS[2]
H4
SB_DQS#[2]
J4
SB_DQS[3]
M5
SB_DQS#[3]
L4
SB_MA[0]
U5
SB_MA[1]
V2
SB_MA[2]
T5
SB_MA[3]
V3
SB_MA[4]
R1
SB_MA[5]
T8
SB_MA[6]
R2
SB_MA[7]
R6
SB_MA[8]
R4
SB_MA[9]
R5
SB_MA[10]
AB5
SB_MA[11]
P3
SB_MA[12]
R3
SB_MA[13]
AF7
SB_MA[14]
P5
SB_MA[15]
N1
SB_DQ[0]
B5
SB_DQ[1]
A5
SB_DQ[2]
C3
SB_DQ[3]
B3
SB_DQ[4]
E4
SB_DQ[5]
A6
SB_DQ[6]
A4
SB_DQ[7]
C4
SB_DQ[8]
D1
SB_DQ[9]
D2
SB_DQ[10]
F2
SB_DQ[11]
F1
SB_DQ[12]
C2
SB_DQ[13]
F5
SB_DQ[14]
F3
SB_DQ[15]
G4
SB_DQ[16]
H6
SB_DQ[17]
G2
SB_DQ[18]
J6
SB_DQ[19]
J3
SB_DQ[20]
G1
SB_DQ[21]
G5
SB_DQ[22]
J2
SB_DQ[23]
J1
SB_DQ[24]
J5
SB_DQ[25]
K2
SB_DQ[26]
L3
SB_DQ[27]
M1
SB_DQ[28]
K5
SB_DQ[29]
K4
SB_DQ[30]
M4
SB_DQ[31]
N5
SB_DQ[32]
AF3
SB_DQ[33]
AG1
SB_DQ[34]
AJ3
SB_DQ[35]
AK1
SB_DQ[36]
AG4
SB_DQ[37]
AG3
SB_DQ[38]
AJ4
SB_DQ[39]
AH4
SB_DQ[40]
AK3
SB_DQ[41]
AK4
SB_DQ[42]
AM6
SB_DQ[43]
AN2
SB_DQ[44]
AK5
SB_DQ[45]
AK2
SB_DQ[46]
AM4
SB_DQ[47]
AM3
SB_DQ[48]
AP3
SB_DQ[49]
AN5
SB_DQ[50]
AT4
SB_DQ[51]
AN6
SB_DQ[52]
AN4
SB_DQ[53]
AN3
SB_DQ[54]
AT5
SB_DQ[55]
AT6
SB_DQ[56]
AN7
SB_DQ[57]
AP6
SB_DQ[58]
AP8
SB_DQ[59]
AT9
SB_DQ[60]
AT7
SB_DQ[61]
AP9
SB_DQ[62]
AR10
SB_DQ[63]
AT10
DDR SYSTEM MEMORY A
JCPU1C
IC,AUB_CFD_rPGA,R1P0
CONN@
DDR SYSTEM MEMORY A
JCPU1C
IC,AUB_CFD_rPGA,R1P0
CONN@
SA_BS[0]
AC3
SA_BS[1]
AB2
SA_BS[2]
U7
SA_CAS#
AE1
SA_RAS#
AB3
SA_WE#
AE9
SA_CK[0]
AA6
SA_CK[1]
Y6
SA_CK#[0]
AA7
SA_CK#[1]
Y5
SA_CKE[0]
P7
SA_CKE[1]
P6
SA_CS#[0]
AE2
SA_CS#[1]
AE8
SA_ODT[0]
AD8
SA_ODT[1]
AF9
SA_DM[0]
B9
SA_DM[1]
D7
SA_DM[2]
H7
SA_DM[3]
M7
SA_DM[4]
AG6
SA_DM[5]
AM7
SA_DM[6]
AN10
SA_DM[7]
AN13
SA_DQS[0]
C8
SA_DQS#[0]
C9
SA_DQS[1]
F9
SA_DQS#[1]
F8
SA_DQS[2]
H9
SA_DQS#[2]
J9
SA_DQS[3]
M9
SA_DQS#[3]
N9
SA_DQS[4]
AH8
SA_DQS#[4]
AH7
SA_DQS[5]
AK10
SA_DQS#[5]
AK9
SA_DQS[6]
AN11
SA_DQS#[6]
AP11
SA_DQS[7]
AR13
SA_DQS#[7]
AT13
SA_MA[0]
Y3
SA_MA[1]
W1
SA_MA[2]
AA8
SA_MA[3]
AA3
SA_MA[4]
V1
SA_MA[5]
AA9
SA_MA[6]
V8
SA_MA[7]
T1
SA_MA[8]
Y9
SA_MA[9]
U6
SA_MA[10]
AD4
SA_MA[11]
T2
SA_MA[12]
U3
SA_MA[13]
AG8
SA_MA[14]
T3
SA_MA[15]
V9
SA_DQ[0]
A10
SA_DQ[1]
C10
SA_DQ[2]
C7
SA_DQ[3]
A7
SA_DQ[4]
B10
SA_DQ[5]
D10
SA_DQ[6]
E10
SA_DQ[7]
A8
SA_DQ[8]
D8
SA_DQ[9]
F10
SA_DQ[10]
E6
SA_DQ[11]
F7
SA_DQ[12]
E9
SA_DQ[13]
B7
SA_DQ[14]
E7
SA_DQ[15]
C6
SA_DQ[16]
H10
SA_DQ[17]
G8
SA_DQ[18]
K7
SA_DQ[19]
J8
SA_DQ[20]
G7
SA_DQ[21]
G10
SA_DQ[22]
J7
SA_DQ[23]
J10
SA_DQ[24]
L7
SA_DQ[25]
M6
SA_DQ[26]
M8
SA_DQ[27]
L9
SA_DQ[28]
L6
SA_DQ[29]
K8
SA_DQ[30]
N8
SA_DQ[31]
P9
SA_DQ[32]
AH5
SA_DQ[33]
AF5
SA_DQ[34]
AK6
SA_DQ[35]
AK7
SA_DQ[36]
AF6
SA_DQ[37]
AG5
SA_DQ[38]
AJ7
SA_DQ[39]
AJ6
SA_DQ[40]
AJ10
SA_DQ[41]
AJ9
SA_DQ[42]
AL10
SA_DQ[43]
AK12
SA_DQ[44]
AK8
SA_DQ[45]
AL7
SA_DQ[46]
AK11
SA_DQ[47]
AL8
SA_DQ[48]
AN8
SA_DQ[49]
AM10
SA_DQ[50]
AR11
SA_DQ[51]
AL11
SA_DQ[52]
AM9
SA_DQ[53]
AN9
SA_DQ[54]
AT11
SA_DQ[55]
AP12
SA_DQ[56]
AM12
SA_DQ[57]
AN12
SA_DQ[58]
AM13
SA_DQ[59]
AT14
SA_DQ[60]
AT12
SA_DQ[61]
AL13
SA_DQ[62]
AR14
SA_DQ[63]
AP14
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_VTTVID1
VCCSENSE
VSSSENSE
VSS_SENSE_VTT
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID6
H_DPRSLPVR
CPU_VID4
CPU_VID5
H_PSI#
H_PSI# <45>
CPU_VID0 <45>
CPU_VID1 <45>
CPU_VID2 <45>
CPU_VID3 <45>
CPU_VID4 <45>
CPU_VID5 <45>
CPU_VID6 <45>
H_DPRSLPVR <45>
VCCSENSE <45>
VSSSENSE <45>
VTT_SENSE <43>
IMVP_IMON <45>
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+1.05VS_VTT
+1.05VS_VTT
+CPU_CORE
+1.05VS_VTT
+1.05VS_VTT
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
748Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
748Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
748Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
(Place these capacitors between inductor and socket on Bottom)
(Place these capacitors on CPU cavity, Bottom Layer)
TOP side (under inductor)
4 x 470uF(4.5mohm@100kHz; 4.0mohm@SRF)
(Place these capacitors on CPU cavity, Bottom Layer)
16X10uF 3m ohm/16
4X470uF 4m ohm/4
3m ohm/12
C,uF
MLCC 0805 X5R
+CPU-CORE
Decoupling
16X22uF
ESR, mohm
SPCAP,Polymer
Stuffing Option
2X470uF
H_VTTVID1 = low, 1.1V
H_VTTVID1 = high, 1.05V
48A Continuous 18A
(Place these capacitors under CPU socket, top layer)
CSC (Current Sense Configuration)
8/25
VTT Rail
Auburndale +1.1VS_VTT=1.05V
Clarksfield +1.1VS_VTT=1.1V
Peak 21A
WW15 MOW
20090915 Modify
Change to OS-CON
20100414
Del C106
C97
22U_0805_6.3V6M
C97
22U_0805_6.3V6M
1
2
+
C272
330U_D2E_2.5VM_R6M
+
C272
330U_D2E_2.5VM_R6M
1
2
+
C82
330U_2.5V_M_R15
+
C82
330U_2.5V_M_R15
12
C69
10U_0805_6.3V6M
C69
10U_0805_6.3V6M
1
2
C81
10U_0805_6.3V6M
C81
10U_0805_6.3V6M
1
2
R87 1K_0402_1%R87 1K_0402_1%
1 2
R74 1K_0402_1%@R74 1K_0402_1%@
1 2
R95 0_0402_5% R95 0_0402_5%
1 2
C78
10U_0805_6.3V6M
C78
10U_0805_6.3V6M
1
2
R89 1K_0402_1%@R89 1K_0402_1%@
1 2
C94
22U_0805_6.3V6M
C94
22U_0805_6.3V6M
1
2
C102
22U_0805_6.3V6M
C102
22U_0805_6.3V6M
1
2
C74
10U_0805_6.3V6M
C74
10U_0805_6.3V6M
1
2
C77
10U_0805_6.3V6M
C77
10U_0805_6.3V6M
1
2
R91 100_0402_1%
R91 100_0402_1%
1 2
R78 1K_0402_1%@R78 1K_0402_1%@
1 2
C103
22U_0805_6.3V6M
C103
22U_0805_6.3V6M
1
2
C91
22U_0805_6.3V6M
C91
22U_0805_6.3V6M
1
2
C85
10U_0805_6.3V6M
C85
10U_0805_6.3V6M
1
2
R86 1K_0402_1%R86 1K_0402_1%
1 2
C86
10U_0805_6.3V6M
C86
10U_0805_6.3V6M
1
2
C71
10U_0805_6.3V6M
C71
10U_0805_6.3V6M
1
2
R88 1K_0402_1%@R88 1K_0402_1%@
1 2
+
C105
330U_D2E_2.5VM_R6M
+
C105
330U_D2E_2.5VM_R6M
1
2
C96
22U_0805_6.3V6M
C96
22U_0805_6.3V6M
1
2
C104
22U_0805_6.3V6M
C104
22U_0805_6.3V6M
1
2
POWER
CPU CORE SUPPLY
1.1V RAIL POWER
SENSE LINES
CPU VIDS
JCPU1F
IC,AUB_CFD_rPGA,R1P0
CONN@
POWER
CPU CORE SUPPLY
1.1V RAIL POWER
SENSE LINES
CPU VIDS
JCPU1F
IC,AUB_CFD_rPGA,R1P0
CONN@
ISENSE
AN35
VTT_SENSE
B15
PSI#
AN33
VID[0]
AK35
VID[1]
AK33
VID[2]
AK34
VID[3]
AL35
VID[4]
AL33
VID[5]
AM33
VID[6]
AM35
PROC_DPRSLPVR
AM34
VTT_SELECT
G15
VCC_SENSE
AJ34
VSS_SENSE_VTT
A15
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VTT0_33
AF10
VTT0_34
AE10
VTT0_35
AC10
VTT0_36
AB10
VTT0_37
Y10
VTT0_38
W10
VTT0_39
U10
VTT0_40
T10
VTT0_41
J12
VTT0_42
J11
VTT0_1
AH14
VTT0_2
AH12
VTT0_3
AH11
VTT0_4
AH10
VTT0_5
J14
VTT0_6
J13
VTT0_7
H14
VTT0_8
H12
VTT0_9
G14
VTT0_10
G13
VTT0_11
G12
VTT0_12
G11
VTT0_13
F14
VTT0_14
F13
VTT0_15
F12
VTT0_16
F11
VTT0_17
E14
VTT0_18
E12
VTT0_19
D14
VTT0_20
D13
VTT0_21
D12
VTT0_22
D11
VTT0_23
C14
VTT0_24
C13
VTT0_25
C12
VTT0_26
C11
VTT0_27
B14
VTT0_28
B12
VTT0_29
A14
VTT0_30
A13
VTT0_31
A12
VTT0_32
A11
VSS_SENSE
AJ35
VTT0_43
J16
VTT0_44
J15
+
C273
330U_D2E_2.5VM_R6M
+
C273
330U_D2E_2.5VM_R6M
1
2
C67
10U_0805_6.3V6M
C67
10U_0805_6.3V6M
1
2
C73
10U_0805_6.3V6M
C73
10U_0805_6.3V6M
1
2
T14
PAD
@
T14
PAD
@
C95
22U_0805_6.3V6M
C95
22U_0805_6.3V6M
1
2
R77 1K_0402_1%R77 1K_0402_1%
1 2
R85 1K_0402_1%@R85 1K_0402_1%@
1 2
C100
22U_0805_6.3V6M
C100
22U_0805_6.3V6M
1
2
C88
10U_0805_6.3V6M
C88
10U_0805_6.3V6M
1
2
R79 1K_0402_1%@R79 1K_0402_1%@
1 2
R76 1K_0402_1%@R76 1K_0402_1%@
1 2
C101
22U_0805_6.3V6M
C101
22U_0805_6.3V6M
1
2
R83 1K_0402_1%R83 1K_0402_1%
1 2
C80
10U_0805_6.3V6M
C80
10U_0805_6.3V6M
1
2
R75 1K_0402_1%R75 1K_0402_1%
1 2
C76
10U_0805_6.3V6M
C76
10U_0805_6.3V6M
1
2
C66
10U_0805_6.3V6M
C66
10U_0805_6.3V6M
1
2
R84 1K_0402_1%@R84 1K_0402_1%@
1 2
C87
10U_0805_6.3V6M
C87
10U_0805_6.3V6M
1
2
+
C275
330U_D2E_2.5VM_R6M
+
C275
330U_D2E_2.5VM_R6M
1
2
C84
10U_0805_6.3V6M
C84
10U_0805_6.3V6M
1
2
R94 100_0402_1%
R94 100_0402_1%
1 2
C72
10U_0805_6.3V6M
C72
10U_0805_6.3V6M
1
2
R90 1K_0402_1%R90 1K_0402_1%
1 2
C70
10U_0805_6.3V6M
C70
10U_0805_6.3V6M
1
2
R80 1K_0402_1%R80 1K_0402_1%
1 2
R81 1K_0402_1%@R81 1K_0402_1%@
1 2
C79
10U_0805_6.3V6M
C79
10U_0805_6.3V6M
1
2
C92
22U_0805_6.3V6M
C92
22U_0805_6.3V6M
1
2
+
C83
330U_2.5V_M_R15
+
C83
330U_2.5V_M_R15
12
R82 1K_0402_1%R82 1K_0402_1%
1 2
C75
10U_0805_6.3V6M
C75
10U_0805_6.3V6M
1
2
C89
10U_0805_6.3V6M
C89
10U_0805_6.3V6M
1
2
C99
22U_0805_6.3V6M
C99
22U_0805_6.3V6M
1
2
C98
22U_0805_6.3V6M
C98
22U_0805_6.3V6M
1
2
R73 1K_0402_1%R73 1K_0402_1%
1 2
C68
10U_0805_6.3V6M
C68
10U_0805_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GFXVR_EN
GFXVR_DPRSLPVR_R
+1.8VS_VCCSFR
GFXVR_EN
VCC_AXG_SENSE <44>
VSS_AXG_SENSE <44>
GFXVR_VID_0 <44>
GFXVR_VID_1 <44>
GFXVR_VID_2 <44>
GFXVR_VID_3 <44>
GFXVR_VID_4 <44>
GFXVR_VID_5 <44>
GFXVR_VID_6 <44>
GFXVR_EN <44>
GFXVR_DPRSLPVR <44>
GFXVR_IMON <44>
+VGFX_CORE
+1.05VS_VTT
+1.8VS
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+1.5V+1.5V_1
+1.5VS
+1.5V+1.5V_1
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
848Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
848Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
848Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
15A
3A
0.6A
Reserved for +1.5VS to +1.5V_1
Reserved for +1.5V to +1.5V_1
PD 470ohm 20091105
11/03 add four 0.1u 0402
Intel suggest
C131
4.7U_0805_10V4Z
C131
4.7U_0805_10V4Z
1
2
C122
22U_0805_6.3V6M
C122
22U_0805_6.3V6M
1
2
+
C107
330U_D2E_2.5VM_R6M
+
C107
330U_D2E_2.5VM_R6M
1
2
C117
1U_0402_6.3V6K
C117
1U_0402_6.3V6K
1
2
C130
2.2U_0603_6.3V6K
C130
2.2U_0603_6.3V6K
1
2
C113
10U_0805_6.3V6M
C113
10U_0805_6.3V6M
1
2
C119
22U_0805_6.3V6M
C119
22U_0805_6.3V6M
1
2
+
C121
330U_D2E_2.5VM_R6M
+
C121
330U_D2E_2.5VM_R6M
1
2
C124
10U_0805_6.3V6M
C124
10U_0805_6.3V6M
1
2
C125
22U_0805_6.3V6M
C125
22U_0805_6.3V6M
1
2
C672 0.1U_0402_16V4ZC672 0.1U_0402_16V4Z
1 2
J1
JUMP_43X118@
J1
JUMP_43X118@
1
1
2
2
J3
JUMP_43X118@
J3
JUMP_43X118@
1
1
2
2
C118
1U_0402_6.3V6K
C118
1U_0402_6.3V6K
1
2
R97 0_0402_5%R97 0_0402_5%
1 2
C128
1U_0402_6.3V6K
C128
1U_0402_6.3V6K
1
2
C111
22U_0805_6.3V6M
C111
22U_0805_6.3V6M
1
2
C129
1U_0402_6.3V6K
C129
1U_0402_6.3V6K
1
2
C123
22U_0805_6.3V6M
C123
22U_0805_6.3V6M
1
2
C114
1U_0402_6.3V6K
C114
1U_0402_6.3V6K
1
2
C120
22U_0805_6.3V6M
C120
22U_0805_6.3V6M
1
2
C673 0.1U_0402_16V4ZC673 0.1U_0402_16V4Z
1 2
C116
1U_0402_6.3V6K
C116
1U_0402_6.3V6K
1
2
C110
22U_0805_6.3V6M
C110
22U_0805_6.3V6M
1
2
C671 0.1U_0402_16V4ZC671 0.1U_0402_16V4Z
1 2
R167 470_0402_5%
R167 470_0402_5%
1 2
C132
22U_0805_6.3V6M
C132
22U_0805_6.3V6M
1
2
C670 0.1U_0402_16V4ZC670 0.1U_0402_16V4Z
1 2
C126
22U_0805_6.3V6M
C126
22U_0805_6.3V6M
1
2
C115
1U_0402_6.3V6K
C115
1U_0402_6.3V6K
1
2
C112
10U_0805_6.3V6M
C112
10U_0805_6.3V6M
1
2
POWER
GRAPHICS VIDs
GRAPHICS
DDR3 - 1.5V RAILS
FDI PEG & DMI
SENSE
LINES
1.1V1.8V
JCPU1G
IC,AUB_CFD_rPGA,R1P0
CONN@
POWER
GRAPHICS VIDs
GRAPHICS
DDR3 - 1.5V RAILS
FDI PEG & DMI
SENSE
LINES
1.1V1.8V
JCPU1G
IC,AUB_CFD_rPGA,R1P0
CONN@
GFX_VID[0]
AM22
GFX_VID[1]
AP22
GFX_VID[2]
AN22
GFX_VID[3]
AP23
GFX_VID[4]
AM23
GFX_VID[5]
AP24
GFX_VID[6]
AN24
GFX_VR_EN
AR25
GFX_DPRSLPVR
AT25
GFX_IMON
AM24
VAXG_SENSE
AR22
VSSAXG_SENSE
AT22
VAXG1
AT21
VAXG2
AT19
VAXG3
AT18
VAXG4
AT16
VAXG5
AR21
VAXG6
AR19
VAXG7
AR18
VAXG8
AR16
VAXG9
AP21
VAXG10
AP19
VAXG11
AP18
VAXG12
AP16
VAXG13
AN21
VAXG14
AN19
VAXG15
AN18
VAXG16
AN16
VAXG17
AM21
VAXG18
AM19
VAXG19
AM18
VAXG20
AM16
VAXG21
AL21
VAXG22
AL19
VAXG23
AL18
VAXG24
AL16
VAXG25
AK21
VAXG26
AK19
VAXG27
AK18
VAXG28
AK16
VAXG29
AJ21
VAXG30
AJ19
VAXG31
AJ18
VAXG32
AJ16
VAXG33
AH21
VAXG34
AH19
VAXG35
AH18
VAXG36
AH16
VTT1_45
J24
VTT1_46
J23
VTT1_47
H25
VTT1_48
K26
VTT1_49
J27
VTT1_50
J26
VTT1_51
J25
VTT1_52
H27
VTT1_53
G28
VTT1_54
G27
VTT1_55
G26
VTT1_56
F26
VTT1_57
E26
VTT1_58
E25
VDDQ1
AJ1
VDDQ2
AF1
VDDQ3
AE7
VDDQ4
AE4
VDDQ5
AC1
VDDQ6
AB7
VDDQ7
AB4
VDDQ8
Y1
VDDQ9
W7
VDDQ10
W4
VDDQ11
U1
VDDQ12
T7
VDDQ13
T4
VDDQ14
P1
VDDQ15
N7
VDDQ16
N4
VDDQ17
L1
VDDQ18
H1
VTT0_59
P10
VTT0_60
N10
VTT0_61
L10
VTT0_62
K10
VCCPLL1
L26
VCCPLL2
L27
VCCPLL3
M26
VTT1_63
J22
VTT1_64
J20
VTT1_65
J18
VTT1_66
H21
VTT1_67
H20
VTT1_68
H19
R99
0_0805_5%
R99
0_0805_5%
1 2
C127
22U_0805_6.3V6M
C127
22U_0805_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
H_NCTF1
H_NCTF2
H_NCTF6
H_NCTF7
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
948Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
948Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
948Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
VSS
NCTF
JCPU1I
IC,AUB_CFD_rPGA,R1P0
CONN@
VSS
NCTF
JCPU1I
IC,AUB_CFD_rPGA,R1P0
CONN@
VSS161
K27
VSS162
K9
VSS163
K6
VSS164
K3
VSS165
J32
VSS166
J30
VSS167
J21
VSS168
J19
VSS169
H35
VSS170
H32
VSS171
H28
VSS172
H26
VSS173
H24
VSS174
H22
VSS175
H18
VSS176
H15
VSS177
H13
VSS178
H11
VSS179
H8
VSS180
H5
VSS181
H2
VSS182
G34
VSS183
G31
VSS184
G20
VSS185
G9
VSS186
G6
VSS187
G3
VSS188
F30
VSS189
F27
VSS190
F25
VSS191
F22
VSS192
F19
VSS193
F16
VSS194
E35
VSS195
E32
VSS196
E29
VSS197
E24
VSS198
E21
VSS199
E18
VSS200
E13
VSS201
E11
VSS202
E8
VSS203
E5
VSS204
E2
VSS205
D33
VSS206
D30
VSS207
D26
VSS208
D9
VSS209
D6
VSS210
D3
VSS211
C34
VSS212
C32
VSS213
C29
VSS214
C28
VSS215
C24
VSS216
C22
VSS217
C20
VSS218
C19
VSS219
C16
VSS220
B31
VSS221
B25
VSS222
B21
VSS223
B18
VSS224
B17
VSS225
B13
VSS226
B11
VSS227
B8
VSS228
B6
VSS229
B4
VSS230
A29
VSS_NCTF1
AT35
VSS_NCTF2
AT1
VSS_NCTF3
AR34
VSS_NCTF4
B34
VSS_NCTF5
B2
VSS_NCTF6
B1
VSS_NCTF7
A35
VSS231
A27
VSS232
A23
VSS233
A9
T5
PAD
@
T5
PAD
@
VSS
JCPU1H
IC,AUB_CFD_rPGA,R1P0
CONN@
VSS
JCPU1H
IC,AUB_CFD_rPGA,R1P0
CONN@
VSS1
AT20
VSS2
AT17
VSS3
AR31
VSS4
AR28
VSS5
AR26
VSS6
AR24
VSS7
AR23
VSS8
AR20
VSS9
AR17
VSS10
AR15
VSS11
AR12
VSS12
AR9
VSS13
AR6
VSS14
AR3
VSS15
AP20
VSS16
AP17
VSS17
AP13
VSS18
AP10
VSS19
AP7
VSS20
AP4
VSS21
AP2
VSS22
AN34
VSS23
AN31
VSS24
AN23
VSS25
AN20
VSS26
AN17
VSS27
AM29
VSS28
AM27
VSS29
AM25
VSS30
AM20
VSS31
AM17
VSS32
AM14
VSS33
AM11
VSS34
AM8
VSS35
AM5
VSS36
AM2
VSS37
AL34
VSS38
AL31
VSS39
AL23
VSS40
AL20
VSS41
AL17
VSS42
AL12
VSS43
AL9
VSS44
AL6
VSS45
AL3
VSS46
AK29
VSS47
AK27
VSS48
AK25
VSS49
AK20
VSS50
AK17
VSS51
AJ31
VSS52
AJ23
VSS53
AJ20
VSS54
AJ17
VSS55
AJ14
VSS56
AJ11
VSS57
AJ8
VSS58
AJ5
VSS59
AJ2
VSS60
AH35
VSS61
AH34
VSS62
AH33
VSS63
AH32
VSS64
AH31
VSS65
AH30
VSS66
AH29
VSS67
AH28
VSS68
AH27
VSS69
AH26
VSS70
AH20
VSS71
AH17
VSS72
AH13
VSS73
AH9
VSS74
AH6
VSS75
AH3
VSS76
AG10
VSS77
AF8
VSS78
AF4
VSS79
AF2
VSS80
AE35
VSS81
AE34
VSS82
AE33
VSS83
AE32
VSS84
AE31
VSS85
AE30
VSS86
AE29
VSS87
AE28
VSS88
AE27
VSS89
AE26
VSS90
AE6
VSS91
AD10
VSS92
AC8
VSS93
AC4
VSS94
AC2
VSS95
AB35
VSS96
AB34
VSS97
AB33
VSS98
AB32
VSS99
AB31
VSS100
AB30
VSS101
AB29
VSS102
AB28
VSS103
AB27
VSS104
AB26
VSS105
AB6
VSS106
AA10
VSS107
Y8
VSS108
Y4
VSS109
Y2
VSS110
W35
VSS111
W34
VSS112
W33
VSS113
W32
VSS114
W31
VSS115
W30
VSS116
W29
VSS117
W28
VSS118
W27
VSS119
W26
VSS120
W6
VSS121
V10
VSS122
U8
VSS123
U4
VSS124
U2
VSS125
T35
VSS126
T34
VSS127
T33
VSS128
T32
VSS129
T31
VSS130
T30
VSS131
T29
VSS132
T28
VSS133
T27
VSS134
T26
VSS135
T6
VSS136
R10
VSS137
P8
VSS138
P4
VSS139
P2
VSS140
N35
VSS141
N34
VSS142
N33
VSS143
N32
VSS144
N31
VSS145
N30
VSS146
N29
VSS147
N28
VSS148
N27
VSS149
N26
VSS150
N6
VSS151
M10
VSS152
L35
VSS153
L32
VSS154
L29
VSS155
L8
VSS156
L5
VSS157
L2
VSS158
K34
VSS159
K33
VSS160
K30
T3
PAD
@
T3
PAD
@
T2
PAD
@
T2
PAD
@
T4
PAD
@
T4
PAD
@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_CKE0
DDR_A_D59
DDR_A_MA3
D_CK_SCLK
DDR_A_CS1#
DDR_A_D39
DDR_A_BS1
DDR_A_WE#
DDR_A_MA7
DDR_A_MA0
DDR_A_DQS7
DDR_A_D57
DDR_A_D46
DDR_A_DQS#5
DDR_A_D51
DDR_A_DM4
DDR_A_D44DDR_A_D44
DDR_A_RAS#
DDR_A_D33
DDR_A_D58
DDR_A_DM5
DDR_A_MA8
DDR_A_CS0#
DDR_A_MA6
DDR_A_MA10
DDR_A_DQS#7
DDR_A_DQS#6
DDR_A_D40
DDR_A_MA9
DDR_A_DQS#4
DDR_A_D52
DDR_A_DQS5
DDR_A_D54
DDR_A_D49
DDR_A_BS2
DDR_A_D45
DDR_A_DM7
DDR_A_MA1
DDR_A_D60
DDR_A_BS0
DDR_A_CAS# DDR_A_ODT0
DDR_A_D37
DDR_A_MA5
DDR_A_MA14
DDR_A_D55
DDR_A_MA4
DDR_A_D62
DDR_A_D56
DDR_A_D53
DDR_A_D47
DDR_A_ODT1
DDR_A_D43
DDR_A_D34
DDR_A_CLK1
DDR_A_CLK1#
DDR_A_D48
D_CK_SDATA
DDR_A_D38
DDR_A_CLK0
DDR_A_CLK0#
DDR_A_D32
DDR_A_MA13
DDR_A_MA11
DDR_A_D50
DDR_A_D61
DDR_A_MA2
DDR_A_D41
DDR_A_D36
DDR_A_D63
DDR_A_DQS6
DDR_A_D35
DDR_A_MA12
DDR_A_DQS4
DDR_A_DM6
DDR_A_D42
DDR_A_CKE1
PM_EXTTS#0_1
DDR_A_MA15
DIMM_DRAMRST#
RST_GATE
DDR_VREF_CA_DIMMA
DDR_A_D5
DDR_A_D22
DDR_A_D14
DDR_A_DQS#0
DDR_A_D31
DDR_A_D12
DDR_A_D6
DDR_A_DQS0
DDR_A_DM2
DDR_A_DM1
DDR_A_D28
DDR_A_D4
DDR_A_D30
DDR_A_DQS3
DIMM_DRAMRST#
DDR_A_D29
DDR_A_D7
DDR_A_D13
DDR_A_D20
DDR_A_D21
DDR_A_D15
DDR_A_D23
DDR_A_DQS#3
+DIMM_VREFDQA
DDR_A_D26
DDR_A_D2
DDR_A_D25
DDR_A_D27
DDR_A_D0
DDR_A_DM0
DDR_A_D19
DDR_A_DQS2
DDR_A_D10
DDR_A_D3
DDR_A_D1
DDR_A_D16
DDR_A_DM3
DDR_A_D9
DDR_A_DQS#1
DDR_A_D24
DDR_A_D18
DDR_A_DQS#2
DDR_A_D11
DDR_A_D8
DDR_A_DQS1
DDR_A_D17
DDR_A_CKE0<6>
DDR_A_CS1#<6>
DDR_A_BS1 <6>
DDR_A_WE#<6>
DDR_A_RAS# <6>
DDR_A_CS0# <6>
DDR_A_BS2<6>
DDR_A_BS0<6>
DDR_A_CAS#<6> DDR_A_ODT0 <6>
DDR_A_ODT1 <6>
DDR_A_CLK1# <6>
DDR_A_CLK1 <6>
DDR_A_CLK0<6>
DDR_A_CLK0#<6>
DDR_A_CKE1 <6>
PM_EXTTS#0_1 <5,11>
D_CK_SDATA <11,12>
D_CK_SCLK <11,12>
DDR_A_DQS#[0..7]<6>
DDR_A_DQS[0..7]<6>
DDR_A_D[0..63]<6>
DDR_A_DM[0..7]<6>
DDR_A_MA[0..15]<6>
SM_DRAMRST#<5>
RST_GATE<18>
DIMM_DRAMRST# <11>
+0.75VS
+1.5V +1.5V
+DIMM_VREFCA
+3VS
+1.5V
+0.75VS
+DIMM_VREFDQA
+1.5V
+DIMM_VREFCA
+1.5V
+1.5V
+DIMM_VREFDQA
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
10 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
10 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
10 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Change to Reverse Type
DDR3 SO-DIMM A
Layout Note: Place these 4 Caps near Command
and Control signals of DIMMA
Layout Note:
Place near JDIMM1.203 & JDIMM1.204
Layout Note:
Place near JDIMM1
DIMMA VREFDQ M1 Circuit
DIMMA & DIMMB VREFCA circuit
#425302
CP_S3PowerReduction
WhitePaper_Rev1.0
M1 Circuit
8mm High
C154
10U_0805_6.3V6M
C154
10U_0805_6.3V6M
1
2
C153
1U_0402_6.3V6K
C153
1U_0402_6.3V6K
1
2
R104
1K_0402_1%
R104
1K_0402_1%
12
C134
0.1U_0402_16V4Z
C134
0.1U_0402_16V4Z
1
2
C143
0.1U_0402_16V4Z
C143
0.1U_0402_16V4Z
1
2
C137
10U_0805_6.3V6M
C137
10U_0805_6.3V6M
1
2
C136
0.1U_0402_16V4Z
C136
0.1U_0402_16V4Z
1
2
C140
10U_0805_6.3V6M
C140
10U_0805_6.3V6M
1
2
C150
1U_0402_6.3V6K
C150
1U_0402_6.3V6K
1
2
G
D
S
Q2
BSS138LT1G_SOT23-3
G
D
S
Q2
BSS138LT1G_SOT23-3
2
13
R106
1K_0402_1%
R106
1K_0402_1%
12
C145
0.1U_0402_16V4Z
C145
0.1U_0402_16V4Z
1
2
R110
10K_0402_5%
R110
10K_0402_5%
12
C146
0.1U_0402_16V4Z
C146
0.1U_0402_16V4Z
1
2
C149
0.1U_0402_16V4Z
C149
0.1U_0402_16V4Z
1
2
R101
1K_0402_1%
R101
1K_0402_1%
12
R109 10K_0402_5% R109 10K_0402_5%
1 2
+
C147
330U_2.5V_M_R15
@
+
C147
330U_2.5V_M_R15
@
12
C138
10U_0805_6.3V6M
C138
10U_0805_6.3V6M
1
2
C139
10U_0805_6.3V6M
C139
10U_0805_6.3V6M
1
2
C133
2.2U_0603_6.3V6K
C133
2.2U_0603_6.3V6K
1
2
C617
0.047U_0402_16V7K
C617
0.047U_0402_16V7K
1 2
C151
1U_0402_6.3V6K
C151
1U_0402_6.3V6K
1
2
R103
1K_0402_1%
R103
1K_0402_1%
12
R107
1K_0402_1%
R107
1K_0402_1%
12
C141
10U_0805_6.3V6M
C141
10U_0805_6.3V6M
1
2
C144
0.1U_0402_16V4Z
C144
0.1U_0402_16V4Z
1
2
R102
0_0402_5%
@
R102
0_0402_5%
@
1 2
C148
2.2U_0603_6.3V6K
C148
2.2U_0603_6.3V6K
1
2
C142
10U_0805_6.3V6M
C142
10U_0805_6.3V6M
1
2
JDIMM1
FOX_AS0A626-U8RN-7F
JDIMM1
FOX_AS0A626-U8RN-7F
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C152
1U_0402_6.3V6K
C152
1U_0402_6.3V6K
1
2
R108 0_0402_5% R108 0_0402_5%
1 2
C135
2.2U_0603_6.3V6K
C135
2.2U_0603_6.3V6K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_D26
DDR_B_D2
DDR_B_D5
DDR_B_D22
DDR_B_D25
DDR_B_D14
DDR_B_DQS#0
DDR_B_D31
DDR_B_D12
DDR_B_D6
DDR_B_DQS0
DDR_B_DM2
DDR_B_DM1
+DIMM_VREFDQB
DDR_B_D0
DDR_B_D28
DDR_B_DM0
DDR_B_D19
DDR_B_D4
DDR_B_D30
DDR_B_DQS2
DDR_B_DQS3
DDR_B_D10
DDR_B_D27
DDR_B_D3
DIMM_DRAMRST#
DDR_B_D1
DDR_B_D16
DDR_B_D29
DDR_B_DM3
DDR_B_D9
DDR_B_D7
DDR_B_D13
DDR_B_D20
DDR_B_DQS#1
DDR_B_D21
DDR_B_D24
DDR_B_D15
DDR_B_D23DDR_B_D18
DDR_B_DQS#2
DDR_B_D11
DDR_B_DQS#3
DDR_B_D8
DDR_B_DQS1
DDR_B_D17
DDR_B_MA12
DDR_B_CKE0
DDR_B_MA3
DDR_B_CS1#
DDR_B_WE#
DDR_B_MA8
DDR_B_MA10
DDR_B_MA9
DDR_B_BS2
DDR_B_MA1
DDR_B_BS0
DDR_B_CAS#
DDR_B_MA5
DDR_B_CLK0
DDR_B_CLK0#
DDR_B_MA13
DDR_B_DQS6
DDR_B_D35
DDR_B_DQS4
DDR_B_D42
DDR_B_D59
DDR_B_D57
DDR_B_D51
DDR_B_D33
DDR_B_D58
DDR_B_DM5
DDR_B_DQS#6
DDR_B_D40
DDR_B_DQS#4
DDR_B_D49
DDR_B_DM7
DDR_B_D56
DDR_B_D43
DDR_B_D34
DDR_B_D48
DDR_B_D32
DDR_B_D50
DDR_B_D41
DDR_B_CKE1
DDR_B_BS1
DDR_B_MA7
DDR_B_MA0
DDR_B_RAS#
DDR_B_CS0#
DDR_B_MA6
DDR_B_ODT0
DDR_B_MA14
DDR_B_MA4
DDR_B_ODT1
DDR_B_CLK1
DDR_B_CLK1#
DDR_B_MA11
DDR_B_MA2
DDR_B_MA15
DDR_B_D62
DDR_B_D36
DDR_B_DM6
DDR_B_D39
DDR_B_DQS7
DDR_B_D46
DDR_B_DQS#5
DDR_B_DM4
DDR_B_D44
DDR_B_DQS#7
DDR_B_D52
DDR_B_DQS5
DDR_B_D54
DDR_B_D45
DDR_B_D60
DDR_B_D37
DDR_B_D55
DDR_B_D63
DDR_B_D53
DDR_B_D47
DDR_B_D38
DDR_B_D61
D_CK_SCLK
D_CK_SDATA
PM_EXTTS#0_1
DDR_VREF_CA_DIMMB
DDR_B_DQS#[0..7]<6>
DDR_B_DQS[0..7]<6>
DDR_B_D[0..63]<6>
DDR_B_MA[0..15]<6>
DDR_B_DM[0..7]<6>
DIMM_DRAMRST# <10>
DDR_B_CKE0<6>
DDR_B_CS1#<6>
DDR_B_WE#<6>
DDR_B_BS2<6>
DDR_B_BS0<6>
DDR_B_CAS#<6>
DDR_B_CLK0<6>
DDR_B_CLK0#<6>
DDR_B_CKE1 <6>
DDR_B_BS1 <6>
DDR_B_RAS# <6>
DDR_B_CS0# <6>
DDR_B_ODT0 <6>
DDR_B_ODT1 <6>
DDR_B_CLK1# <6>
DDR_B_CLK1 <6>
PM_EXTTS#0_1 <5,10>
D_CK_SDATA <10,12>
D_CK_SCLK <10,12>
+1.5V
+1.5V
+1.5V
+0.75VS
+DIMM_VREFDQB
+1.5V
+DIMM_VREFDQB
+0.75VS
+3VS
+DIMM_VREFCA
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
11 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
11 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
11 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
DDR3 SO-DIMM B
Reverse Type
2008/9/8 #400755
Calpella Clarksfield
DDR3 SO-DIMM
VREFDQ Platform
Design Guide Change Details
Layout Note:
Place near JDIMM2
Layout Note:
Place near JDIMM2.203 & JDIMM2.204
Layout Note: Place these 4 Caps near Command
and Control signals of DIMMB
DIMMB VREFDQ M1 Circuit
M1 Circuit
4mm High
C163
10U_0805_6.3V6M
C163
10U_0805_6.3V6M
1
2
+
C169
330U_2.5V_M_R15
+
C169
330U_2.5V_M_R15
12
R115 0_0402_5%R115 0_0402_5%
1 2
C170
1U_0402_6.3V6K
C170
1U_0402_6.3V6K
1
2
C155
2.2U_0603_6.3V6K
C155
2.2U_0603_6.3V6K
1
2
C164
10U_0805_6.3V6M
C164
10U_0805_6.3V6M
1
2
JDIMM2
FOX_AS0A626-U4RN-7F
CONN@
JDIMM2
FOX_AS0A626-U4RN-7F
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C160
10U_0805_6.3V6M
C160
10U_0805_6.3V6M
1
2
C175
2.2U_0603_6.3V6K
C175
2.2U_0603_6.3V6K
1
2
C159
10U_0805_6.3V6M
C159
10U_0805_6.3V6M
1
2
C165
0.1U_0402_16V4Z
C165
0.1U_0402_16V4Z
1
2
R113
1K_0402_1%
R113
1K_0402_1%
12
R116 10K_0402_5%R116 10K_0402_5%
1 2
C176
0.1U_0402_16V4Z
C176
0.1U_0402_16V4Z
1
2
C166
0.1U_0402_16V4Z
C166
0.1U_0402_16V4Z
1
2
C158
0.1U_0402_16V4Z
C158
0.1U_0402_16V4Z
1
2
C172
1U_0402_6.3V6K
C172
1U_0402_6.3V6K
1
2
C168
0.1U_0402_16V4Z
C168
0.1U_0402_16V4Z
1
2
C167
0.1U_0402_16V4Z
C167
0.1U_0402_16V4Z
1
2
C161
10U_0805_6.3V6M
C161
10U_0805_6.3V6M
1
2
C173
1U_0402_6.3V6K
C173
1U_0402_6.3V6K
1
2
C162
10U_0805_6.3V6M
C162
10U_0805_6.3V6M
1
2
C174
10U_0805_6.3V6M
C174
10U_0805_6.3V6M
1
2
C171
1U_0402_6.3V6K
C171
1U_0402_6.3V6K
1
2
R117 10K_0402_5%R117 10K_0402_5%
1 2
C157
2.2U_0603_6.3V6K
C157
2.2U_0603_6.3V6K
1
2
C156
0.1U_0402_16V4Z
C156
0.1U_0402_16V4Z
1
2
R114
1K_0402_1%
R114
1K_0402_1%
12
A
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
1 1
2 2
3 3
4 4
CLK_XTAL_OUT
CLK_XTAL_IN
CK505_PWRGD
D_CK_SCLK
D_CK_SDATA
H_STP_CPU#
REF_0/CPU_SEL
D_CK_SCLK
D_CK_SDATA
CLK_XTAL_OUT
CLK_XTAL_IN
CK505_PWRGD
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
CLK_BUF_CPU_BCLK
CLK_BUF_CPU_BCLK#
CLK_SD_48M_R
H_STP_CPU#
REF_0/CPU_SEL
D_CK_SCLK <10,11>
D_CK_SDATA <10,11>
CLK_ENABLE# <45>
VGATE <15,45>
CLK_BUF_ICH_14M <14>CLK_BUF_DREF_96M<14>
CLK_BUF_DREF_96M#<14>
CLK_BUF_PCIE_SATA#<14>
CLK_BUF_PCIE_SATA<14>
CLK_BUF_CPU_DMI<14>
CLK_BUF_CPU_DMI#<14>
CLK_BUF_CPU_BCLK <14>
CLK_BUF_CPU_BCLK# <14>
CLK_SD_48M<29>
PCH_SMBDATA<14,26>
PCH_SMBCLK<14,26>
+CLK_1.05VS
+3VS
+3VS
+3VS
+3VS
+CLK_1.05VS
+CLK_3VS
+3VS
+CLK_3VS
+3VS
+CLK_1.5VS
+1.5VS
+CLK_1.5VS
+CLK_3VS
+CLK_1.5VS
+CLK_1.05VS
+3VS
+1.05VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
12 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
12 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
12 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Clock Generator
IDT: 9LRS3199AKLFT, SA000030P00
SILEGO: SLG8SP587V(WF), SA00002XY10
IDT SA00003HR00
Change to 5x3.2
IDT: 9LVS3199AKLFT, SA00003HR00
Realtek: RTM890N-631-GRT, SA00003HQ00
Low Power:
Y1 Change to SJ100009R00
20091117
For Cardreader
Silego Have Internal Pull-Up
IDT Have Internal Pull-Down
1
CPU_1PIN 30 CPU_0
0 133MHz
(Default)
133MHz
100MHz 100MHz
Change to 2N7002DW
20100416
Del 3G solution Del 3G solution
Del 3G solution
Del L3
change to +1.05VS
20100429
L2
FBMA-L11-201209-221LMA30T_0805
L2
FBMA-L11-201209-221LMA30T_0805
12
C182
10U_0805_10V4Z
C182
10U_0805_10V4Z
1
2
C178
10U_0805_10V4Z
C178
10U_0805_10V4Z
1
2
Y1
14.31818MHZ 20PF 7A14300003
Y1
14.31818MHZ 20PF 7A14300003
12
R119 33_0402_5%
R119 33_0402_5%
1 2
C183
0.1U_0402_16V4Z
C183
0.1U_0402_16V4Z
1
2
R120
10K_0402_5%
R120
10K_0402_5%
1 2
C190
33P_0402_50V8J
C190
33P_0402_50V8J
12
L1
FBMA-L11-201209-221LMA30T_0805
L1
FBMA-L11-201209-221LMA30T_0805
12
Q4B
2N7002DW-T/R7_SOT363-6
Q4B
2N7002DW-T/R7_SOT363-6
3
5
4
U3
SLG8SP587VTR_QFN32_5X5
U3
SLG8SP587VTR_QFN32_5X5
CPU_1#
19
SATA
10
CKPWRGD/PD#
25
DOT_96#
4
CPU_0#
22
XTAL_OUT
27
VSS_REF
26
VDD_CPU
24
CPU_0
23
27MHZ_SS
7
XTAL_IN
28
27MHZ
6
USB_48
8
CPU_1
20
VSS_CPU
21
VDD_CPU_IO
18
VDD_USB_48
1
VSS_48M
2
REF_0/CPU_SEL
30
SDA
31
SCL
32
VDD_27
5
VSS_27M
9
SATA#
11
VSS_SRC
12
SRC_1
13
SRC_1#
14
VDD_SRC_IO
15
VDD_SRC
17
VDD_REF
29
DOT_96
3
CPU_STOP#
16
TGND
33
C185
10U_0805_10V4Z
C185
10U_0805_10V4Z
1
2
C179
0.1U_0402_16V4Z
C179
0.1U_0402_16V4Z
1
2
C186
10U_0805_10V4Z
C186
10U_0805_10V4Z
1
2
G
D
S
Q5
2N7002_SOT23
G
D
S
Q5
2N7002_SOT23
2
13
R121 10K_0402_5% R121 10K_0402_5%
1 2
C181
10U_0805_10V4Z
C181
10U_0805_10V4Z
1
2
R125
4.7K_0402_5%
R125
4.7K_0402_5%
1 2
C191
33P_0402_50V8J
C191
33P_0402_50V8J
12
R118 33_0402_5% R118 33_0402_5%
1 2
C180
0.1U_0402_16V4Z
C180
0.1U_0402_16V4Z
1
2
R123
4.7K_0402_5%
R123
4.7K_0402_5%
1 2
C184
0.1U_0402_16V4Z
C184
0.1U_0402_16V4Z
1
2
Q4A
2N7002DW-T/R7_SOT363-6
Q4A
2N7002DW-T/R7_SOT363-6
6 1
2
C189
0.1U_0402_16V4Z
C189
0.1U_0402_16V4Z
1
2
R122
0_0402_5%
@
R122
0_0402_5%
@
1 2
C187
0.1U_0402_16V4Z
C187
0.1U_0402_16V4Z
1
2
C177
10U_0805_10V4Z
C177
10U_0805_10V4Z
1
2
L4
FBMA-L11-201209-221LMA30T_0805
L4
FBMA-L11-201209-221LMA30T_0805
12
C188
0.1U_0402_16V4Z
C188
0.1U_0402_16V4Z
1
2
R124 10K_0402_5% R124 10K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
PCH_INTVRMEN
SM_INTRUDER#
PCH_RTCRST#
PCH_SRTCRST#
HDA_BITCLK_PCH
HDA_SYNC_PCH
HDA_RST_PCH#
HDA_SDOUT_PCH
PCH_JTAG_TCK
LPC_AD0
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
SERIRQ
SATA_PTX_DRX_N0
SATA_DTX_C_PRX_P0
SATA_DTX_C_PRX_N0
SATA_PTX_DRX_P0
SATA_PTX_DRX_N1
SATA_PTX_DRX_P1
SATA_DTX_C_PRX_P1
SATA_DTX_C_PRX_N1
SATA_COMP
PCH_GPIO19
PCH_SPI_CS0#_R
PCH_SPKR
PCH_SPKR
SERIRQ
PCH_GPIO21
PCH_SPI_CS1#
PCH_SPI_CS0#
PCH_SPI_MISO_1 PCH_SPI_MISO
PCH_SPI_CLK_1
PCH_SPI_MOSIPCH_SPI_MOSI_1
PCH_SPI_CLKPCH_SPI_CLK
SATA_LED#
PCH_GPIO33#
SPI_WP1#
PCH_SPI_MISO_1
PCH_SPI_CS0#
SPI_HOLD1#
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_GPIO33#
PCH_SPI_CLK_1
PCH_JTAG_TCK
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_RST#
PCH_SPI_MOSI
HDA_SDIN0<33>
PCH_JTAG_RST#
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMS
LPC_FRAME# <30>
LPC_AD0 <30>
LPC_AD1 <30>
LPC_AD2 <30>
LPC_AD3 <30>
SERIRQ <30>
SATA_DTX_C_PRX_N0 <25>
SATA_DTX_C_PRX_P0 <25>
SATA_DTX_C_PRX_N1 <25>
SATA_DTX_C_PRX_P1 <25>
PCH_SPKR<33>
SATA_PTX_DRX_P0 <25>
SATA_PTX_DRX_N0 <25>
SATA_PTX_DRX_P1 <25>
SATA_PTX_DRX_N1 <25>
PCH_JTAG_TCK
SATA_LED# <32>
ME_OVERRIDE<30>
HDA_BITCLK_AUDIO<33>
HDA_SYNC_AUDIO<33>
HDA_RST_AUDIO#<33>
HDA_SDOUT_AUDIO<33>
+RTCVCC
+RTCVCC
+RTCVCC
+3VS
+3VS
+3VS
+1.05VS
+3VS
+3VS
+1.05VS
+3VALW
+3VS
+RTCBATT+RTCVCC
+CHGRTC
+RTCBATT
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
13 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
13 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
13 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
INTVRMEN - Integrated SUS
1.1V VRM Enable High - Enable Internal VRs
close to RAM door
close to RAM door
SATA for ODD
SATA for HDD1
HDA for AUDIO
GPIO33 can not pull down
(manufacturing environments)
RC Delay 18~25mS
RC Delay 18~25mS
Have internal PD
SPI ROM Footprint 200mil
2/10 SATA2, SATA3 not support on HM55
If GPIO33 pull down, ME will not working.
For factory update ME, pull down resistor pull
under door.
modify to 330K
X1 Change to mini type
20091102
GPIO33 has a weak internal pull-up
NOTE: Asserting the GPIO33 low on the
rising edge of PWROK will also halt Intel
Management Engine after chipset bringup
and disable runtime Intel Management
Engine features. This is a debug mode and
must not be asserted after manfacturing/
debug.
For 3G team
Close to U5 20090915
CRB 1.0 Change to 4.7K
enable iTPM: SPI_MOSI High
20100421 Modify
20100416 add
GPIO19 GPIO37
00
1
1
X
0
SG
dGPU
iGPU
VGA_PRSNT_L#PCH_GPIO19
GPIO21 Project
0
1
NEW50/70/80/90
NEW71/91
R133 1M_0402_5% R133 1M_0402_5%
1 2
R151 51_0402_5%@R151 51_0402_5%@
1 2
R136 33_0402_5%
R136 33_0402_5%
1 2
JBATT1
SUYIN_060003HA002G202ZL
@
JBATT1
SUYIN_060003HA002G202ZL
@
+
1
-
2
C192
18P_0402_50V8J
C192
18P_0402_50V8J
12
R128
10M_0402_5%
R128
10M_0402_5%
12
R149
10K_0402_5%
R149
10K_0402_5%
12
R478 200_0402_1%R478 200_0402_1%
1 2
C557 10P_0402_50V8J
@
C557 10P_0402_50V8J
@
1 2
R138
10K_0402_5%
R138
10K_0402_5%
1 2
R129 1K_0402_5%R129 1K_0402_5%
1 2
R483 100_0402_5% R483 100_0402_5%
1 2
C195
18P_0402_50V8J
C195
18P_0402_50V8J
12
R132
20K_0402_1%
R132
20K_0402_1%
1 2
R484 20K_0402_5% R484 20K_0402_5%
1 2
R148 10K_0402_5%@R148 10K_0402_5%@
1 2
C193
1U_0402_6.3V6K
C193
1U_0402_6.3V6K
1 2
U18
MX25L1605DM2I-12G SOP 8P
SA000021A00
U18
MX25L1605DM2I-12G SOP 8P
SA000021A00
CS#
1
SO
2
WP#
3
GND
4
SI
5
SCLK
6
HOLD#
7
VCC
8
R144 10K_0402_5% R144 10K_0402_5%
1 2
R479 100_0402_5%R479 100_0402_5%
1 2
G
D
S
Q7
2N7002_SOT23
G
D
S
Q7
2N7002_SOT23
2
13
R134 330K_0402_1% R134 330K_0402_1%
1 2
R157 1K_0402_5%@R157 1K_0402_5%@
1 2
R156 3.3K_0402_5% R156 3.3K_0402_5%
1 2
R141 37.4_0402_1% R141 37.4_0402_1%
1 2
R135 33_0402_5%
R135 33_0402_5%
1 2
R154 51_0402_5%@R154 51_0402_5%@
1 2
R126
20K_0402_1%
R126
20K_0402_1%
1 2
R152 51_0402_5%@R152 51_0402_5%@
1 2
R127
10K_0603_5%
@R127
10K_0603_5%
@
1 2
R139 33_0402_5%
R139 33_0402_5%
1 2
R482 200_0402_1%R482 200_0402_1%
1 2
RTCIHDA
SATA
LPC
SPI JTAG
REV1.0
U4A
IBEXPEAK-M_FCBGA107
RTCIHDA
SATA
LPC
SPI JTAG
REV1.0
U4A
IBEXPEAK-M_FCBGA107
RTCX1
B13
RTCX2
D13
INTVRMEN
A14
INTRUDER#
A16
HDA_BCLK
A30
HDA_SYNC
D29
HDA_RST#
C30
HDA_SDIN0
G30
HDA_SDIN1
F30
HDA_SDIN2
E32
HDA_SDO
B29
SATALED#
T3
FWH0 / LAD0
D33
FWH1 / LAD1
B33
FWH2 / LAD2
C32
FWH3 / LAD3
A32
LDRQ1# / GPIO23
F34
FWH4 / LFRAME#
C34
LDRQ0#
A34
RTCRST#
C14
HDA_SDIN3
F32
HDA_DOCK_EN# / GPIO33
H32
HDA_DOCK_RST# / GPIO13
J30
SRTCRST#
D17
SATA0RXN
AK7
SATA0RXP
AK6
SATA0TXN
AK11
SATA0TXP
AK9
SATA1RXN
AH6
SATA1RXP
AH5
SATA1TXN
AH9
SATA1TXP
AH8
SATA2RXN
AF11
SATA2RXP
AF9
SATA2TXN
AF7
SATA2TXP
AF6
SATA3RXN
AH3
SATA3RXP
AH1
SATA3TXN
AF3
SATA3TXP
AF1
SATA4RXN
AD9
SATA4RXP
AD8
SATA4TXN
AD6
SATA4TXP
AD5
SATA5RXN
AD3
SATA5RXP
AD1
SATA5TXN
AB3
SATA5TXP
AB1
SATAICOMPI
AF15
SPI_CLK
BA2
SPI_CS0#
AV3
SPI_CS1#
AY3
SPI_MOSI
AY1
SPI_MISO
AV1
SATA0GP / GPIO21
Y9
SATA1GP / GPIO19
V1
JTAG_TCK
M3
JTAG_TMS
K3
JTAG_TDI
K1
JTAG_TDO
J2
TRST#
J4
SERIRQ
AB9
SPKR
P1
SATAICOMPO
AF16
R137
1K_0402_5%
@
R137
1K_0402_5%
@
1 2
R130
10K_0603_5%
@R130
10K_0603_5%
@
1 2
R340 10_0402_5%
@
R340 10_0402_5%
@
1 2
R145 15_0402_5% R145 15_0402_5%
1 2
R485 10K_0402_5% R485 10K_0402_5%
1 2
R150
10K_0402_5%
R150
10K_0402_5%
12
R155 3.3K_0402_5% R155 3.3K_0402_5%
1 2
D1
DAN202UT106_SC70-3
D1
DAN202UT106_SC70-3
2
3
1
R147 33_0402_5% R147 33_0402_5%
1 2
T6
PAD
@
T6
PAD
@
R146 10K_0402_5%@R146 10K_0402_5%@
1 2
R143 15_0402_5% R143 15_0402_5%
1 2
R481 100_0402_5%R481 100_0402_5%
1 2
R480 200_0402_1%R480 200_0402_1%
1 2
R131 33_0402_5%
R131 33_0402_5%
1 2
X1
32.768KHZ_12.5PF_Q13MC14610002
X1
32.768KHZ_12.5PF_Q13MC14610002
OSC
4
OSC
1
NC
3
NC
2
R158 4.7K_0402_5% R158 4.7K_0402_5%
1 2
R142 0_0402_5% R142 0_0402_5%
1 2
R140
100K_0402_5%
R140
100K_0402_5%
12
C194
1U_0402_6.3V6K
C194
1U_0402_6.3V6K
1 2
R153 51_0402_5%@R153 51_0402_5%@
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCIE_DTX_C_PRX_P1
PCIE_PTX_DRX_N1
PCIE_DTX_C_PRX_N1
PCIE_PTX_DRX_P1
PCIE_PTX_DRX_P2
PCIE_DTX_C_PRX_N2
PCIE_DTX_C_PRX_P2
PCIE_PTX_DRX_N2
PCH_SMBDATA
PCH_SMBCLK
EC_LID_OUT#
PCH_GPIO60
PCH_GPIO74
XTAL25_IN
XTAL25_OUT
XCLK_RCOMP
EC_LID_OUT#
PCH_SMBCLK
PCH_SMBDATA
PCH_GPIO60
PCH_GPIO74
PCH_GPIO25
PCH_GPIO44
PCH_GPIO56
PCH_GPIO44
PCH_GPIO56
PCH_GPIO20
PCH_GPIO18
PCH_GPIO73
PCH_GPIO73
PCH_GPIO25
PCH_GPIO20
MINI1_CLKREQ#
PCH_GPIO26
PROJECT_ID0
PROJECT_ID1
PCH_SML1DAT
PCH_SML1CLK
PCH_SML1CLK
PCH_SML1DAT
PCH_SML1CLK EC_SMB_CK2
PCH_SML1DAT EC_SMB_DA2
PEG_CLKREQ#
PCH_GPIO26
PCIE_DTX_C_PRX_N1<27>
PCIE_PTX_C_DRX_N1<27>
PCIE_PTX_C_DRX_P1<27>
PCIE_DTX_C_PRX_P1<27>
PCIE_DTX_C_PRX_N2<26>
PCIE_PTX_C_DRX_N2<26>
PCIE_PTX_C_DRX_P2<26>
PCIE_DTX_C_PRX_P2<26>
PCH_SMBDATA <12,26>
PCH_SMBCLK <12,26>
CLK_CPU_DMI <5>
CLK_BUF_DREF_96M# <12>
CLK_BUF_DREF_96M <12>
CLK_BUF_CPU_BCLK# <12>
CLK_BUF_CPU_BCLK <12>
CLK_BUF_CPU_DMI# <12>
CLK_BUF_CPU_DMI <12>
CLK_BUF_PCIE_SATA# <12>
CLK_BUF_PCIE_SATA <12>
CLK_BUF_ICH_14M <12>
CLK_PCI_FB <17>
CLK_CPU_DMI# <5>
EC_LID_OUT# <30>
LAN_CLKREQ#<27>
MINI1_CLKREQ#<26>
CLK_PCIE_LAN#<27>
CLK_PCIE_LAN<27>
CLK_PCIE_MINI1<26>
CLK_PCIE_MINI1#<26>
EC_SMB_DA2 <30>
EC_SMB_CK2 <30>
CLK_CPU_DP <5>
CLK_CPU_DP# <5>
+3VALW
+3VS
+3VALW
+1.05VS
+3VS
+3VS
+3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
14 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
14 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
14 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
For Wireless LAN
For PCIE LAN
For Wireless LAN
For PCIE LAN
2. Level Shift1, Pull-Up to +3VS
CLOCK GEN, DIMM1, DIMM2
3. Level Shift2, Pull-Up to +3VS
LAN
4. Level Shift3, Pull-Up to +3VS
CPU & PCH XDP
1. Connect Directly
EXPRESS CARD, MINI1, MINI2
6/9 MOW23 Request add 25MHz crystal
supporting Integrated Graphics
Project Port ID
2/10 PCIE7, PCIE8 not support on HM55
Change to 5x3.2
Pull high +3VS at KB926 side
2009/08/13: Change back to +3VALW
20090915 Add
2009/09/23:Change to +3VALW
GPIO66 6L/8L
SATA register separe
1
0
8L
6L
GPIO66
*
0602 GPIO65 no use
PULL HIGH:PVT
PULL DOWN:DVT
C200 0.1U_0402_16V7KC200 0.1U_0402_16V7K
12
C199 0.1U_0402_16V7KC199 0.1U_0402_16V7K
12
Q9B
2N7002DW-T/R7_SOT363-6
Q9B
2N7002DW-T/R7_SOT363-6
3
5
4
R187 10K_0402_5%R187 10K_0402_5%
1 2
R177 10K_0402_5%R177 10K_0402_5%
1 2
10K_0402_5%R172@ 10K_0402_5%R172@
1 2
R184 2.2K_0402_5%R184 2.2K_0402_5%
1 2
R182 10K_0402_5%R182 10K_0402_5%
1 2
R338 10_0402_5%R338 10_0402_5%
1 2
C204
27P_0402_50V8J
C204
27P_0402_50V8J
1 2
R189 10K_0402_5% R189 10K_0402_5%
1 2
R174 10K_0402_5%@R174 10K_0402_5%@
1 2
R166 10K_0402_5%R166 10K_0402_5%
1 2
R188 10K_0402_5% R188 10K_0402_5%
1 2
R181 2.2K_0402_5%R181 2.2K_0402_5%
1 2
R183 2.2K_0402_5%R183 2.2K_0402_5%
1 2
R165 0_0402_5% R165 0_0402_5%
1 2
R164 0_0402_5% R164 0_0402_5%
1 2
R169 90.9_0402_1% R169 90.9_0402_1%
1 2
R186 10K_0402_5%R186 10K_0402_5%
1 2
R180 2.2K_0402_5%R180 2.2K_0402_5%
1 2
R179 10K_0402_5%R179 10K_0402_5%
1 2
C555 10P_0402_50V8JC555 10P_0402_50V8J
1 2
R170
1M_0402_5%
R170
1M_0402_5%
12
C197 0.1U_0402_16V7KC197 0.1U_0402_16V7K
12
PCI-E*
SMBus
Controller
From CLK BUFFER
PEG
Clock Flex
Link
REV1.0
U4B
IBEXPEAK-M_FCBGA107
PCI-E*
SMBus
Controller
From CLK BUFFER
PEG
Clock Flex
Link
REV1.0
U4B
IBEXPEAK-M_FCBGA107
PERN1
BG30
PERP1
BJ30
PERN2
AW30
PERP2
BA30
PERN3
AU30
PERP3
AT30
PERN4
BA32
PERP4
BB32
PERN5
BF33
PERP5
BH33
PERN6
BA34
PERP6
AW34
PERN7
AT34
PERP7
AU34
PERN8
BG34
PERP8
BJ34
PETN1
BF29
PETP1
BH29
PETN2
BC30
PETP2
BD30
PETN3
AU32
PETP3
AV32
PETN4
BD32
PETP4
BE32
PETN5
BG32
PETP5
BJ32
PETN6
BC34
PETP6
BD34
PETN7
AU36
PETP7
AV36
PETN8
BG36
PETP8
BJ36
SMBALERT# / GPIO11
B9
SMBCLK
H14
SMBDATA
C8
SML0CLK
C6
SML0DATA
G8
CLKOUT_PCIE0N
AK48
CLKOUT_PCIE0P
AK47
CLKOUT_PCIE1N
AM43
CLKOUT_PCIE1P
AM45
CLKOUT_PCIE2N
AM47
CLKOUT_PCIE2P
AM48
CLKOUT_PCIE3N
AH42
CLKOUT_PCIE3P
AH41
CLKOUT_PCIE4N
AM51
CLKOUT_PCIE4P
AM53
CLKOUT_PCIE5N
AJ50
CLKOUT_PCIE5P
AJ52
SML0ALERT# / GPIO60
J14
CL_CLK1
T13
CL_DATA1
T11
CL_RST1#
T9
CLKIN_BCLK_N
AP3
CLKIN_BCLK_P
AP1
CLKIN_DMI_N
AW24
CLKIN_DMI_P
BA24
CLKIN_DOT_96N
F18
CLKIN_DOT_96P
E18
CLKIN_SATA_N / CKSSCD_N
AH13
CLKIN_SATA_P / CKSSCD_P
AH12
XTAL25_IN
AH51
XTAL25_OUT
AH53
REFCLK14IN
P41
CLKIN_PCILOOPBACK
J42
CLKOUT_PEG_A_N
AD43
CLKOUT_PEG_A_P
AD45
PEG_A_CLKRQ# / GPIO47
H1
PCIECLKRQ0# / GPIO73
P9
PCIECLKRQ1# / GPIO18
U4
PCIECLKRQ2# / GPIO20
N4
PCIECLKRQ3# / GPIO25
A8
PCIECLKRQ4# / GPIO26
M9
PCIECLKRQ5# / GPIO44
H6
CLKOUTFLEX0 / GPIO64
T45
CLKOUTFLEX1 / GPIO65
P43
CLKOUTFLEX2 / GPIO66
T42
CLKOUTFLEX3 / GPIO67
N50
CLKOUT_DMI_N
AN4
CLKOUT_DMI_P
AN2
PEG_B_CLKRQ# / GPIO56
P13
CLKOUT_PEG_B_P
AK51
CLKOUT_PEG_B_N
AK53
SML1ALERT# / GPIO74
M14
SML1CLK / GPIO58
E10
SML1DATA / GPIO75
G12
XCLK_RCOMP
AF38
CLKOUT_DP_P / CLKOUT_BCLK1_P
AT3
CLKOUT_DP_N / CLKOUT_BCLK1_N
AT1
R185 10K_0402_5%R185 10K_0402_5%
1 2
Q9A
2N7002DW-T/R7_SOT363-6
Q9A
2N7002DW-T/R7_SOT363-6
6 1
2
R178 10K_0402_5%R178 10K_0402_5%
1 2
R159
10K_0402_5%
R159
10K_0402_5%
1 2
R175 10K_0402_5%R175 10K_0402_5%
1 2
Y2
25MHZ_20PF_7A25000012
Y2
25MHZ_20PF_7A25000012
12
C203
27P_0402_50V8J
C203
27P_0402_50V8J
1 2
C198 0.1U_0402_16V7KC198 0.1U_0402_16V7K
12
R171 10K_0402_5%R171 10K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_COMP
DMI_HTX_PRX_N0
DMI_HTX_PRX_N1
DMI_HTX_PRX_N3
DMI_HTX_PRX_N2
DMI_HTX_PRX_P0
DMI_HTX_PRX_P1
DMI_HTX_PRX_P3
DMI_HTX_PRX_P2
DMI_PTX_HRX_N0
DMI_PTX_HRX_N1
DMI_PTX_HRX_N2
DMI_PTX_HRX_N3
DMI_PTX_HRX_P0
DMI_PTX_HRX_P1
DMI_PTX_HRX_P3
DMI_PTX_HRX_P2
XDP_DBRESET#
SYS_PWROK_R
PCH_RSMRST#
LAN_RST#
SUS_PWR_ACK
PBTN_OUT#
PCH_GPIO72
EC_SWI#
PM_SLP_DSW#
PM_SLP_LAN#
PCH_PCIE_WAKE#
PM_CLKRUN#
EC_PWROK
SYS_PWROK
VGATE
LAN_RST#
SYS_PWROK
PCH_RSMRST#
SYS_PWROK
EC_PWROK
PCH_ACIN
PCH_GPIO61
PM_SLP_M#
H_FDI_TXP0
H_FDI_TXP1
H_FDI_TXP2
H_FDI_TXP3
H_FDI_TXP4
H_FDI_TXP5
H_FDI_TXP6
H_FDI_TXP7
H_FDI_TXN0
H_FDI_TXN1
H_FDI_TXN2
H_FDI_TXN3
H_FDI_TXN4
H_FDI_TXN5
H_FDI_TXN6
H_FDI_TXN7
EC_SWI#
PCH_GPIO72
SUS_PWR_ACK
PM_SLP_LAN#
PCH_PCIE_WAKE#
VGATE
SYS_PWROK
H_FDI_TXP[0..7]
H_FDI_TXN[0..7]
PM_CLKRUN#
DMI_PTX_HRX_N[0..3]
DMI_PTX_HRX_P[0..3]
DMI_HTX_PRX_N[0..3]
DMI_HTX_PRX_P[0..3]
PM_DRAM_PWRGD<5>
PBTN_OUT#<30>
PM_SLP_S5# <30>
PM_SLP_S4# <30>
PM_SLP_S3# <30>
PCH_PCIE_WAKE# <26,27>
PM_CLKRUN# <30>
H_PM_SYNC <5>
XDP_DBRESET#<5>
EC_RSMRST# <30>
EC_ACIN<30>
EC_SWI#<30>
VGATE <12,45>
H_FDI_FSYNC1 <4>
H_FDI_INT <4>
H_FDI_LSYNC0 <4>
H_FDI_LSYNC1 <4>
H_FDI_FSYNC0 <4>
SUS_PWR_ACK<30>
EC_PWROK <30>
PCH_SUSCLK <30>
H_FDI_TXP[0..7] <4>
H_FDI_TXN[0..7] <4>
DMI_HTX_PRX_N[0..3]<4>
DMI_HTX_PRX_P[0..3]<4>
DMI_PTX_HRX_N[0..3]<4>
DMI_PTX_HRX_P[0..3]<4>
+3VS
+3VALW
+3VALW
+3VALW
+1.05VS
+3VS
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
15 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
15 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
401939
A
SCHEMATIC,MB A6582
Custom
15 48Friday, July 02, 2010
2009/08/01 2010/08/01
Compal Electronics, Inc.
No used Integrated LAN,
connecting LAN_RST# to GND
10/2
R199 Intel suggestion change to 10K
R195 Change to 10K for WW37
20090916
U6 change to SA00000OH00
32.768KHZ ouput for remove EC crystal
20091103
R194 10K_0402_5%R194 10K_0402_5%
1 2
T10
PAD
@
T10
PAD
@
R190 8.2K_0402_5%R190 8.2K_0402_5%
1 2
R204
2.2K_0402_5%
R204
2.2K_0402_5%
12
R206 10K_0402_5%R206 10K_0402_5%
1 2
R191 10K_0402_5%R191 10K_0402_5%
1 2
R192
49.9_0402_1%
R192
49.9_0402_1%
1 2
R196 10K_0402_5%
@
R196 10K_0402_5%
@
1 2
D3B
BAV99DW-7_SOT363
D3B
BAV99DW-7_SOT363
4
5
3
D3A
BAV99DW-7_SOT363
D3A
BAV99DW-7_SOT363
1
2
6
DMI
FDI
System Power Management
REV1.0
U4C
IBEXPEAK-M_FCBGA107
DMI
FDI
System Power Management
REV1.0
U4C
IBEXPEAK-M_FCBGA107
DMI0RXN
BC24
DMI1RXN
BJ22
DMI2RXN
AW20
DMI3RXN
BJ20
DMI0RXP
BD24
DMI1RXP
BG22
DMI2RXP
BA20
DMI3RXP
BG20
DMI0TXN
BE22
DMI1TXN
BF21
DMI2TXN
BD20
DMI3TXN
BE18
DMI0TXP
BD22
DMI1TXP
BH21
DMI2TXP
BC20
DMI3TXP
BD18
DMI_ZCOMP
BH25
DMI_IRCOMP
BF25
FDI_RXN0
BA18
FDI_RXN1
BH17
FDI_RXN2
BD16
FDI_RXN3
BJ16
FDI_RXN4
BA16
FDI_RXN5
BE14
FDI_RXN6
BA14
FDI_RXN7
BC12
FDI_RXP0
BB18
FDI_RXP1
BF17
FDI_RXP2
BC16
FDI_RXP3
BG16
FDI_RXP4
AW16
FDI_RXP5
BD14
FDI_RXP6
BB14
FDI_RXP7
BD12
FDI_FSYNC0
BF13
FDI_FSYNC1
BH13
FDI_LSYNC0
BJ12
FDI_LSYNC1
BG14
FDI_INT
BJ14
PMSYNCH
BJ10
TP23
N2
SLP_M#
K8
SLP_S3#
P12
SLP_S4#
H7
SLP_S5# / GPIO63
E4
SYS_RESET#
T6
SYS_PWROK
M6
PWRBTN#
P5
RI#
F14
WAKE#
J12
SUS_STAT# / GPIO61
P8
SUSCLK / GPIO62
F3
ACPRESENT / GPIO31
P7
LAN_RST#
A10
MEPWROK
K5
BATLOW# / GPIO72
A6
PWROK
B17
CLKRUN# / GPIO32
Y1
SUS_PWR_DN_ACK / GPIO30
M1
RSMRST#
C16
DRAMPWROK
D9
SLP_LAN# / GPIO29
F6
R200 0_0402_5%
@
R200 0_0402_5%
@
12
R202 4.7K_0402_5%R202 4.7K_0402_5%
1 2
R193 8.2K_0402_5%R193 8.2K_0402_5%
1 2
T9
PAD
@
T9
PAD
@
R197 0_0402_5% R197 0_0402_5%
12
C
B
E
Q11
MMBT3906_SOT23-3
C
B
E
Q11
MMBT3906_SOT23-3
1
2
3
R207 10K_0402_5%R207 10K_0402_5%
1 2
R201
10K_0402_5%
R201
10K_0402_5%
12
D2
CH751H-40PT_SOD323-2
D2
CH751H-40PT_SOD323-2
21
T7
PAD
@
T7
PAD
@
R198 0_0402_5%@R198 0_0402_5%@
12
R203 0_0402_5%@R203 0_0402_5%@
12
R195 10K_0402_5%R195 10K_0402_5%
1 2
R199 10K_0402_5%
R199 10K_0402_5%
1 2
R205 10K_0402_5%R205 10K_0402_5%
1 2
U6
MC74VHC1G08DFT2G_SC70-5
U6
MC74VHC1G08DFT2G_SC70-5
B
2
A
1
Y
4
P
5
G
3
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