LA-6752P G470 UMA
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Cover Page
Custom
1 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Cover Page
Custom
1 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Cover Page
Custom
1 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
Intel Sandy Bridge Processor with DDRIII + Cougar Point PCH
G470/G570 UMA M/B Schematics Document
REV:0.2
Compal Confidential
2010-10-22
LA-6752P / LA-6754P
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Block Diagram
Custom
2 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Block Diagram
Custom
2 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Block Diagram
Custom
2 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
File Name : G470/G570
Compal confidential
37.5mm*37.5mm
25mm*25mm
FDI *8
100MHz
2.7GT/s
Intel
LPC BUS
BANK 0, 1, 2, 3
Sandy Bridge
Socket-rPGA988B
DMI *4
FCBGA 989
Thermal Sensor
PCI-E(WLAN)
USB(WiMAX)
Intel
Cougar Point
EC
Touch Pad Int. KBD
SPI ROM
DDR3 SO-DIMM *2
Dual Channel
DDR3 1066MHz(1.5V)
DDR3 1333MHz(1.5V)
Up to 8GB
HDMI
Connector
CRT
Connector
LVDS
Connector
PCI Express
Mini Card Slot *1
Athros
AR8151-B(GLAN)
AR8152-B(10/100)
RJ-45
Connector
PCI-E x1 *6
WiMAX
WLAN
SPIROM
BIOS
USB2.0 *14
SATA *6
SATA ODD
SATA3 HDD
eSATA+USB(Left)
(Port 0/Port 1 support SATA3)
Audio Codec
CX20671
LAN
Conexant
Card Reader
RTS5139
Reltek
SDXC/MMC/MS/xD
Camera Conn.
BlueTooth Conn.
Mini Card Slot *1
USB2.0 *1(Right)
USB2.0 *2(Left)
AZALIA
2 channel speaker
Int. MIC
Audio Jacks
For 14"(Page 4x)
LS6753P PWR/B
LS6751P CardReader/B
For 15"(Page 4x+1)
LS6753P PWR/B
LS6754P LED/B
LS6751P CardReader/B
LS6755P ODD/B
ENE KB930
ENE KB9012
Page5-11
Page12-13
Page14-22
Page31
Page32
Page33
Page34
Page35
Page36
Page37
EMC1403
Page38
Page38
Page39
Page41 Page42
Page42
Page34
Page40
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Notes List
B
3 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Notes List
B
3 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
Notes List
B
3 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
EC SM Bus1 address
Device
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
PCH SM Bus address
Device Address
Address
Address
Voltage Rails
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
EC SM Bus2 address
Device
Smart Battery
0001 011X b
X
V
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VS
XX
V
V
X
XX
PCH
Thermal
Sensor
X
X
X
SML0CLK
SML0DATA
PCH
SMB_EC_CK2
SOURCE
KB930
VGA BATT KE930 SODIMM
SMBUS Control Table
SMBCLK
SMBDATA
PCH
WLAN
WWAN
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
X V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
KB930
SML1CLK
SML1DATA
PCH
XX X
X
X
V
+3VS
+3VS
+3VS
+3VS
V
+3VS
O
X
S3
+3VS
X
X
+3VALW
+5VS
O
+CPU_CORE
OO
X
X X
+VCCP
power
plane
O
O
O
O
X
S5 S4/ Battery only
X X X
+B
State
+1.5VS
+1.5V
S5 S4/AC & Battery
don't exist
S5 S4/AC
+5VALW
S0
O
O
+GFX_CORE
+1.8VS
+0.75VS
+1.05VS
+VGA_CORE
USB 2.0 USB 1.1 Port
3 External
USB Port
USB Port (Left Side)
Camera
Blue Tooth
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
EHCI1
EHCI2
USB Port Table
USB/B (Right Side)
Card Reader
Mini Card(WLAN)
USB Port (Left Side)
USB Port (Left Side)
COMMON HDMI HDMI@
Unpop
BTO Item BOM Structure
Blue Tooth BT@
Connector ME@
@
eSATA ESATA@
BOM Structure Table
BOARD ID Table
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
EVT
DVT
PVT
MP
Board ID / SKU ID Table for AD channel
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID
V typ
AD_BID
V
AD_BID
max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7 NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
CMOS@CAMERA DEVICE
45 LEVEL 45@
10/100 LAN 8152@
GIGA@GIGA LAN
1001_101xb
Thermal Sensor EMC1403-2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
CLOCK GENERATOR
4 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
CLOCK GENERATOR
4 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
CLOCK GENERATOR
4 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
Note: Do not drive any IOs before VDDR3 is ramped up.
VDD_CT(1.8V)
VDDR3(3.3VGS)
VDDC/VDDCI(1.12V)
PERSTb
Straps Reset
Straps Valid
REFCLK
VDDR1(1.5VGS)
Power-Up/Down Sequence
All the ASIC supplies must fully reach their respective nominal voltages within 20 ms of the start of the ramp-up
sequence, though a shorter ramp-up duration is preferred.
VDDR3 should ramp-up before or simultaneously with VDDC.
For LVDS, DPx_VDD10 should ramp-up before DPx_VDD18 and the PCIe Reference clock should begin before
DPx_VDD18. For power-down, DPx_VDD18 should ramp-down before DPx_VDD10.
The external pull-ups on the DDC/AUX signals (if applicable) should ramp-up before or after both VDDC and
VDD_CT have ramped up.
VDDC and VDD_CT should not ramp-up simultaneously. (e.g., VDDC should reach 90% before VDD_CT starts to
ramp-up (or vice versa).)
PCIE_VDDC(1.0V)
Global ASIC Reset
T4+16clock
1.12V
dGPU Power Pins
Max current
1679mA
575mA
SI4800
2A
190mA
70mA
2.8A
12.9A
Power Sequence
PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,
DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and
SPV10
PCIE_VDDC
VDDR3 , and A2VDD
BIF_VDDC (current consumption = 55mA@1.0V, in
BACO mode)
VDDR1
VDDC/VDDCI
Voltage
1.8V
1.0V
1.0V
3.3V
VDDC
Same as
EN
1.5V
1.12V
SI4800
EN
SI4800
PX 3.0
OFF
MOS
OFF
OFF
OFF
OFF
OFF
OFF
BACO Mode
ON
ON
ON
ON
ON
Same as
PCIE_VDDC
OFF
OFF
+1.0VGS
+3.3VGS
+1.5VGS
+VGA_CORE
+1.8VGS
Regulator
iGPU
+1.0V
dGPU
+3.3VALW
PE_GPIO1
+1.5V
+B
+1.8V
PE_GPIO0
PE_EN
BACO Switch
BACO(jmp)
BIF_VDDC
EN
BACO(jmp)
BACO(jmp)
PX_mode
PWRGOOD
Regulators
VDDC/VDDCI
VDDR1
PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
Without BACO option :
BACO option :
PE_GPIO0 : High ->Normal operation (dGPU is not reseton BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
P25
P24
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
FDI_FSYNC0
FDI_LSYNC0
FDI_LSYNC1
FDI_FSYNC1
FDI_INT
EDP_COMP
PEG_COMP
eDP_HPD
DMI_CTX_PRX_P0<16>
DMI_CRX_PTX_P0<16>
DMI_CTX_PRX_N1<16>
DMI_CRX_PTX_N1<16>
DMI_CTX_PRX_P3<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_N0<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P1<16>
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_P1<16>
DMI_CTX_PRX_N2<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
+1.05VS
+1.05VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(1/7) DMI,FDI,PEG
Custom
5 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(1/7) DMI,FDI,PEG
Custom
5 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(1/7) DMI,FDI,PEG
Custom
5 50Friday, November 26, 2010
2010/07/12 2012/07/11
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
- typical impedance = 14.5 mohms
eDP_COMPIO and ICOMPO signals
should be shorted near balls
and routed with typical
impedance <25 mohms
Compal Electronics, Inc.
R7
24.9_0402_1%
R7
24.9_0402_1%
12
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
Sandy Bridge_rPGA_Rev1p0
ME@
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
Sandy Bridge_rPGA_Rev1p0
ME@
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21
DMI_TX[2]
F20
FDI0_TX#[0]
A21
FDI0_TX#[1]
H19
FDI0_TX#[2]
E19
FDI0_TX#[3]
F18
FDI1_TX#[0]
B21
FDI1_TX#[1]
C20
FDI1_TX#[2]
D18
FDI1_TX#[3]
E17
FDI0_TX[0]
A22
FDI0_TX[1]
G19
FDI0_TX[2]
E20
FDI0_TX[3]
G18
FDI1_TX[0]
B20
FDI1_TX[1]
C19
FDI1_TX[2]
D19
FDI1_TX[3]
F17
FDI0_FSYNC
J18
FDI1_FSYNC
J17
FDI_INT
H20
FDI0_LSYNC
J19
FDI1_LSYNC
H17
PEG_ICOMPI
J22
PEG_ICOMPO
J21
PEG_RCOMPO
H22
PEG_RX#[0]
K33
PEG_RX#[1]
M35
PEG_RX#[2]
L34
PEG_RX#[3]
J35
PEG_RX#[4]
J32
PEG_RX#[5]
H34
PEG_RX#[6]
H31
PEG_RX#[7]
G33
PEG_RX#[8]
G30
PEG_RX#[9]
F35
PEG_RX#[10]
E34
PEG_RX#[11]
E32
PEG_RX#[12]
D33
PEG_RX#[13]
D31
PEG_RX#[14]
B33
PEG_RX#[15]
C32
PEG_RX[0]
J33
PEG_RX[1]
L35
PEG_RX[2]
K34
PEG_RX[3]
H35
PEG_RX[4]
H32
PEG_RX[5]
G34
PEG_RX[6]
G31
PEG_RX[7]
F33
PEG_RX[8]
F30
PEG_RX[9]
E35
PEG_RX[10]
E33
PEG_RX[11]
F32
PEG_RX[12]
D34
PEG_RX[13]
E31
PEG_RX[14]
C33
PEG_RX[15]
B32
PEG_TX#[0]
M29
PEG_TX#[1]
M32
PEG_TX#[2]
M31
PEG_TX#[3]
L32
PEG_TX#[4]
L29
PEG_TX#[5]
K31
PEG_TX#[6]
K28
PEG_TX#[7]
J30
PEG_TX#[8]
J28
PEG_TX#[9]
H29
PEG_TX#[10]
G27
PEG_TX#[11]
E29
PEG_TX#[12]
F27
PEG_TX#[13]
D28
PEG_TX#[14]
F26
PEG_TX#[15]
E25
PEG_TX[0]
M28
PEG_TX[1]
M33
PEG_TX[2]
M30
PEG_TX[3]
L31
PEG_TX[4]
L28
PEG_TX[5]
K30
PEG_TX[6]
K27
PEG_TX[7]
J29
PEG_TX[8]
J27
PEG_TX[9]
H28
PEG_TX[10]
G28
PEG_TX[11]
E28
PEG_TX[12]
F28
PEG_TX[13]
D27
PEG_TX[14]
E26
PEG_TX[15]
D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_COMPIO
A18
eDP_HPD
B16
eDP_ICOMPO
A17
R1
24.9_0402_1%
R1
24.9_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XDP_TCK
XDP_TRST#
XDP_TMS
XDP_TDI
XDP_TDO
SUSP
H_CATERR#
XDP_BPM#4
XDP_TRST#
XDP_PREQ#
SM_RCOMP0
H_PECI
XDP_BPM#7
PM_DRAM_PWR GD_R
H_THRMTRIP#
XDP_TDO
SM_RCOMP2
XDP_BPM#1
XDP_BPM#6
CLK_CPU_DMI_R
CLK_CPU_DMII#_R
XDP_BPM#3
H_CPUPWRGD_R
XDP_TDI
XDP_BPM#0
BUF_CPU_RST#
XDP_DBRESET#
H_PROCHOT#_R
XDP_TCK
H_DRAMRST#
XDP_BPM#2
H_PM_SYNC_R
XDP_PRDY#
SM_RCOMP1
XDP_BPM#5
PLT_RST#
BUFO_CPU_RST#
H_PROCHOT#
PM_SYS_PWRGD_BUF
BUF_CPU_RST#
XDP_TMS
PM_DRAM_PWR GD<16>
SUSP<10,37,51>
H_DRAMRST# <7>
H_PM_SYNC<16>
CLK_CPU_DMI# <15>
H_THRMTRIP#<19>
CLK_CPU_DMI <15>
H_CPUPWRGD<19>
H_SNB_IVB#<18>
H_PECI<19,32>
H_PROCHOT#<32>
PLT_RST# <18>
SYS_PWROK<16>
PCH_POK< 16,32>
+1.05VS
+1.5V_CPU_VDDQ
+3VALW
+1.05VS
+3VS
+1.05VS
+1.05VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(2/7) PM,XDP,CLK
Custom
6 50Friday, November 26, 2010
2009/12/01 2010/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(2/7) PM,XDP,CLK
Custom
6 50Friday, November 26, 2010
2009/12/01 2010/12/31
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(2/7) PM,XDP,CLK
Custom
6 50Friday, November 26, 2010
2009/12/01 2010/12/31
PU/PD for JTAG signa ls
DDR3 Compe nsation Si gnals
Compal Electronics, Inc.
Buffered reset to CPU
DG1.0
closs to EC 250~750mils
DG1.0
3V
Change footprint
20100814
10/12 reserve R880 / R882
R13 1K_0402_5%R13 1K_0402_5%
12
R23 51_0402_5%@R23 51_0402_5%@
12
R8820_0402_5%
@
R8820_0402_5%
@
1 2
U2
SN74LVC1G07DCKR_SC70-5
U2
SN74LVC1G07DCKR_SC70-5
NC
1
A
2
G
3
Y
4
P
5
R32
75_0402_5%
R32
75_0402_5%
12
R34
43_0402_1%
R34
43_0402_1%
1 2
R30
200_0402_5%
R30
200_0402_5%
12
R21 51_0402_5%R21 51_0402_5%
12
R22
0_0402_5%
R22
0_0402_5%
1 2
R27
10K_0402_5%
R27
10K_0402_5%
1 2
R24 51_0402_5%R24 51_0402_5%
12
R20 51_0402_5%R20 51_0402_5%
12
R10 0_0402_5%R10 0_0402_5%
1 2
R33
39_0402_5%
@
R33
39_0402_5%
@
12
R35
0_0402_5%
@R35
0_0402_5%
@
12
R15
56_0402_5%
R15
56_0402_5%
1 2
R161 100K _0402_5%R161 100K _0402_5%
1 2
C33
0.1U_0402_16V4Z
C33
0.1U_0402_16V4Z
1
2
R18 200_0402_1%R18 200_0402_1%
12
R26
0_0402_5%
R26
0_0402_5%
1 2
R8800_0402_5%
@
R8800_0402_5%
@
1 2
R11
0_0402_5%
R11
0_0402_5%
1 2
R17 25.5_0402_1%R17 25.5_0402_1%
12
G
D
S
Q1
2N7002H_SOT23-3
@
G
D
S
Q1
2N7002H_SOT23-3
@
2
13
R16 140_0402_1%R16 140_0402_1%
12
U1
74AHC1G09GW_TSSOP5
U1
74AHC1G09GW_TSSOP5
B
1
A
2
G
3
O
4
P
5
R12 1K_0402_5%R12 1K_0402_5%
12
R29
130_0402_5%
R29
130_0402_5%
1 2
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
Sandy Bridge_rPGA_Rev1p0
ME@
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
Sandy Bridge_rPGA_Rev1p0
ME@
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_REF_CLK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPWR OK
V8
RESET#
AR33
PRDY#
AP29
PREQ#
AP27
TCK
AR26
TMS
AR27
TRST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
R28 1K_0402_5%R28 1K_0402_5%
12
C34
0.1U_0402_16V4Z
C34
0.1U_0402_16V4Z
1
2
R25 51_0402_5%R25 51_0402_5%
12
R9
62_0402_5%
R9
62_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D63
DDR_A_D62
DDR_A_D8
DDR_A_D3
DDR_A_D4
DDR_A_D7
DDR_A_D5
DDR_A_D6
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D47
DDR_A_D46
DDR_A_D42
DDR_A_D43
DDR_A_D34
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_D38
DDR_A_D36
DDR_A_D37
DDR_A_D32
DDR_A_D33
DDR_A_D61
DDR_A_D60
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_D55
DDR_A_D54
DDR_A_D51
DDR_A_D48
DDR_A_D50
DDR_A_D49
DDR_A_D52
DDR_A_D53
DDR_A_D31
DDR_A_D14
DDR_A_D15
DDR_A_D25
DDR_A_D24
DDR_A_D26
DDR_A_D27
DDR_A_D30
DDR_A_D9
DDR_A_D13
DDR_A_D12
DDR_A_D10
DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_D19
DDR_A_D20
DDR_A_D16
DDR_A_D21
DDR_A_D17
DDR_A_D22
DDR_A_D18
DDR_A_D23
DDR_A_MA15
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS1
DDR_A_DQS6
DDR_A_DQS5
DDR_A_DQS4
DDR_A_DQS3
DDR_A_DQS7
DDR_A_DQS#7
DDR_A_DQS#0
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#3
DDR_A_DQS#1
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_MA0
DDR_A_MA14
DDR_A_MA5
DDR_A_MA4
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA9
DDR_A_MA7
DDR_A_MA6
DDR_A_MA12
DDR_A_MA13
DDR_A_MA8
DDR_A_MA11
DDR_A_MA10
DDR_B_D33
DDR_B_D14
DDR_B_D42
DDR_B_D59
DDR_B_D63
DDR_B_D43
DDR_B_D55
DDR_B_D53
DDR_B_D29
DDR_B_D24
DDR_B_D34
DDR_B_D4
DDR_B_D26
DDR_B_D13
DDR_B_D10
DDR_B_D21
DDR_B_D11
DDR_B_D57
DDR_B_D44
DDR_B_D0
DDR_B_D7
DDR_B_D46
DDR_B_D3
DDR_B_D15
DDR_B_D27
DDR_B_D30
DDR_B_D35
DDR_B_D40
DDR_B_D49
DDR_B_D23
DDR_B_D25
DDR_B_D19
DDR_B_D37
DDR_B_D48
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D47
DDR_B_D9
DDR_B_D60
DDR_B_D50
DDR_B_D62
DDR_B_D52
DDR_B_D2
DDR_B_D51
DDR_B_D56
DDR_B_D39
DDR_B_D22
DDR_B_D28
DDR_B_D6
DDR_B_D45
DDR_B_D17
DDR_B_D58
DDR_B_D61
DDR_B_D31
DDR_B_D54
DDR_B_D1
DDR_B_D41
DDR_B_D5
DDR_B_D12
DDR_B_D20
DDR_B_D38
DDR_B_D32
DDR_B_D16
DDR_B_MA15
DDR_B_DQS#1
DDR_B_DQS#7
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS#0
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS6
DDR_B_MA0
DDR_B_MA9
DDR_B_MA7
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_B_MA11
DDR_B_MA3
DDR_B_MA5
DDR_B_MA6
DDR_B_MA10
DDR_B_MA8
DDR_B_MA1
DDR_B_MA12
DDR_B_MA14
DDR3_DRAMRST#_RH_DRAMRST#
DRAMRST_CNTRL
DDR_A_D[0..63]<12>
DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>
DDR_A_WE#<12>
DDR_A_RAS#<12>
DDR_A_CAS#<12>
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
M_CLK_DDR1 <12>
M_CLK_DDR#1 <12>
DDR_CKE1_DIMMA <12>
DDR_CS0_DIMMA# <12>
DDR_CS1_DIMMA# <12>
M_ODT0 <12>
M_ODT1 <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_D[0..63]<13>
DDR_B_WE#<13>
DDR_B_RAS#<13>
DDR_B_CAS#<13>
DDR_CS3_DIMMB# <13>
DDR_B_DQS[0..7] <13>
DDR_B_DQS#[0..7] <13>
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
DDR_CS2_DIMMB# <13>
M_ODT3 <13>
M_ODT2 <13>
DDR_CKE3_DIMMB <13>
M_CLK_DDR#3 <13>
DDR3_DRAMRST# <12,13>
H_DRAMRST#<6>
DRAMRST_CNTRL_PC H<15>
DDR_A_MA[0..15] <12> DDR_B_MA[0..15] <13>
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(3/7) DDRIII
Custom
7 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(3/7) DDRIII
Custom
7 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(3/7) DDRIII
Custom
7 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
Eiffel used 0.01u
Module design used 0.047u
R36
0_0402_5%
@R36
0_0402_5%
@
1 2
DDR SYSTEM MEMORY B
JCPU1D
Sandy Bridge_rPGA_Rev1p0
ME@
DDR SYSTEM MEMORY B
JCPU1D
Sandy Bridge_rPGA_Rev1p0
ME@
SB_BS[0]
AA9
SB_BS[1]
AA7
SB_BS[2]
R6
SB_CAS#
AA10
SB_RAS#
AB8
SB_WE#
AB9
SB_CLK[0]
AE2
SB_CLK[1]
AE1
SB_CLK#[0]
AD2
SB_CLK#[1]
AD1
SB_CKE[0]
R9
SB_CKE[1]
R10
SB_ODT[0]
AE4
SB_ODT[1]
AD4
SB_DQS[4]
AN6
SB_DQS#[4]
AN5
SB_DQS[5]
AP8
SB_DQS#[5]
AP9
SB_DQS[6]
AK11
SB_DQS#[6]
AK12
SB_DQS[7]
AP14
SB_DQS#[7]
AP15
SB_DQS[0]
C7
SB_DQS#[0]
D7
SB_DQS[1]
G3
SB_DQS#[1]
F3
SB_DQS[2]
J6
SB_DQS#[2]
K6
SB_DQS[3]
M3
SB_DQS#[3]
N3
SB_MA[0]
AA8
SB_MA[1]
T7
SB_MA[2]
R7
SB_MA[3]
T6
SB_MA[4]
T2
SB_MA[5]
T4
SB_MA[6]
T3
SB_MA[7]
R2
SB_MA[8]
T5
SB_MA[9]
R3
SB_MA[10]
AB7
SB_MA[11]
R1
SB_MA[12]
T1
SB_MA[13]
AB10
SB_MA[14]
R5
SB_MA[15]
R4
SB_DQ[0]
C9
SB_DQ[1]
A7
SB_DQ[2]
D10
SB_DQ[3]
C8
SB_DQ[4]
A9
SB_DQ[5]
A8
SB_DQ[6]
D9
SB_DQ[7]
D8
SB_DQ[8]
G4
SB_DQ[9]
F4
SB_DQ[10]
F1
SB_DQ[11]
G1
SB_DQ[12]
G5
SB_DQ[13]
F5
SB_DQ[14]
F2
SB_DQ[15]
G2
SB_DQ[16]
J7
SB_DQ[17]
J8
SB_DQ[18]
K10
SB_DQ[19]
K9
SB_DQ[20]
J9
SB_DQ[21]
J10
SB_DQ[22]
K8
SB_DQ[23]
K7
SB_DQ[24]
M5
SB_DQ[25]
N4
SB_DQ[26]
N2
SB_DQ[27]
N1
SB_DQ[28]
M4
SB_DQ[29]
N5
SB_DQ[30]
M2
SB_DQ[31]
M1
SB_DQ[32]
AM5
SB_DQ[33]
AM6
SB_DQ[34]
AR3
SB_DQ[35]
AP3
SB_DQ[36]
AN3
SB_DQ[37]
AN2
SB_DQ[38]
AN1
SB_DQ[39]
AP2
SB_DQ[40]
AP5
SB_DQ[41]
AN9
SB_DQ[42]
AT5
SB_DQ[43]
AT6
SB_DQ[44]
AP6
SB_DQ[45]
AN8
SB_DQ[46]
AR6
SB_DQ[47]
AR5
SB_DQ[48]
AR9
SB_DQ[49]
AJ11
SB_DQ[50]
AT8
SB_DQ[51]
AT9
SB_DQ[52]
AH11
SB_DQ[53]
AR8
SB_DQ[54]
AJ12
SB_DQ[55]
AH12
SB_DQ[56]
AT11
SB_DQ[57]
AN14
SB_DQ[58]
AR14
SB_DQ[59]
AT14
SB_DQ[60]
AT12
SB_DQ[61]
AN15
SB_DQ[62]
AR15
SB_DQ[63]
AT15
RSVD_TP[11]
AB2
RSVD_TP[12]
AA2
RSVD_TP[13]
T9
RSVD_TP[14]
AA1
RSVD_TP[15]
AB1
RSVD_TP[16]
T10
SB_CS#[0]
AD3
SB_CS#[1]
AE3
RSVD_TP[17]
AD6
RSVD_TP[18]
AE6
RSVD_TP[19]
AD5
RSVD_TP[20]
AE5
R40
0_0402_5%
R40
0_0402_5%
1 2
R38
1K_0402_5%
R38
1K_0402_5%
1 2
DDR SYSTEM MEMORY A
JCPU1C
Sandy Bridge_rPGA_Rev1p0
ME@
DDR SYSTEM MEMORY A
JCPU1C
Sandy Bridge_rPGA_Rev1p0
ME@
SA_BS[0]
AE10
SA_BS[1]
AF10
SA_BS[2]
V6
SA_CAS#
AE8
SA_RAS#
AD9
SA_WE#
AF9
SA_CLK[0]
AB6
SA_CLK[1]
AA5
SA_CLK#[0]
AA6
SA_CLK#[1]
AB5
SA_CKE[0]
V9
SA_CKE[1]
V10
SA_CS#[0]
AK3
SA_CS#[1]
AL3
SA_ODT[0]
AH3
SA_ODT[1]
AG3
SA_DQS[0]
D4
SA_DQS#[0]
C4
SA_DQS[1]
F6
SA_DQS#[1]
G6
SA_DQS[2]
K3
SA_DQS#[2]
J3
SA_DQS[3]
N6
SA_DQS#[3]
M6
SA_DQS[4]
AL5
SA_DQS#[4]
AL6
SA_DQS[5]
AM9
SA_DQS#[5]
AM8
SA_DQS[6]
AR11
SA_DQS#[6]
AR12
SA_DQS[7]
AM14
SA_DQS#[7]
AM15
SA_MA[0]
AD10
SA_MA[1]
W1
SA_MA[2]
W2
SA_MA[3]
W7
SA_MA[4]
V3
SA_MA[5]
V2
SA_MA[6]
W3
SA_MA[7]
W6
SA_MA[8]
V1
SA_MA[9]
W5
SA_MA[10]
AD8
SA_MA[11]
V4
SA_MA[12]
W4
SA_MA[13]
AF8
SA_MA[14]
V5
SA_MA[15]
V7
SA_DQ[0]
C5
SA_DQ[1]
D5
SA_DQ[2]
D3
SA_DQ[3]
D2
SA_DQ[4]
D6
SA_DQ[5]
C6
SA_DQ[6]
C2
SA_DQ[7]
C3
SA_DQ[8]
F10
SA_DQ[9]
F8
SA_DQ[10]
G10
SA_DQ[11]
G9
SA_DQ[12]
F9
SA_DQ[13]
F7
SA_DQ[14]
G8
SA_DQ[15]
G7
SA_DQ[16]
K4
SA_DQ[17]
K5
SA_DQ[18]
K1
SA_DQ[19]
J1
SA_DQ[20]
J5
SA_DQ[21]
J4
SA_DQ[22]
J2
SA_DQ[23]
K2
SA_DQ[24]
M8
SA_DQ[25]
N10
SA_DQ[26]
N8
SA_DQ[27]
N7
SA_DQ[28]
M10
SA_DQ[29]
M9
SA_DQ[30]
N9
SA_DQ[31]
M7
SA_DQ[32]
AG6
SA_DQ[33]
AG5
SA_DQ[34]
AK6
SA_DQ[35]
AK5
SA_DQ[36]
AH5
SA_DQ[37]
AH6
SA_DQ[38]
AJ5
SA_DQ[39]
AJ6
SA_DQ[40]
AJ8
SA_DQ[41]
AK8
SA_DQ[42]
AJ9
SA_DQ[43]
AK9
SA_DQ[44]
AH8
SA_DQ[45]
AH9
SA_DQ[46]
AL9
SA_DQ[47]
AL8
SA_DQ[48]
AP11
SA_DQ[49]
AN11
SA_DQ[50]
AL12
SA_DQ[51]
AM12
SA_DQ[52]
AM11
SA_DQ[53]
AL11
SA_DQ[54]
AP12
SA_DQ[55]
AN12
SA_DQ[56]
AJ14
SA_DQ[57]
AH14
SA_DQ[58]
AL15
SA_DQ[59]
AK15
SA_DQ[60]
AL14
SA_DQ[61]
AK14
SA_DQ[62]
AJ15
SA_DQ[63]
AH15
RSVD_TP[1]
AB4
RSVD_TP[2]
AA4
RSVD_TP[4]
AB3
RSVD_TP[5]
AA3
RSVD_TP[3]
W9
RSVD_TP[6]
W10
RSVD_TP[7]
AG1
RSVD_TP[8]
AH1
RSVD_TP[9]
AG2
RSVD_TP[10]
AH2
R39
4.99K_0402_1%
R39
4.99K_0402_1%
1 2
R37
1K_0402_5%
R37
1K_0402_5%
12
G
D
S
Q2
BSS138_NL_SOT23-3
G
D
S
Q2
BSS138_NL_SOT23-3
2
13
C35
0.047U_0402_16V4Z
C35
0.047U_0402_16V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG4
CFG6
CFG2
CFG7
CFG2
CFG4
CFG6
CFG7
CFG5
CFG5
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(4/7) RSVD,CFG
Custom
8 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(4/7) RSVD,CFG
Custom
8 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(4/7) RSVD,CFG
Custom
8 50Friday, November 26, 2010
2010/07/12 2012/07/11
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
PCIE Port Bifurcation Straps
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
1: (Default) PEG Train immediately following xxRESETB
de assertion
CFG4
Display Port Presence Strap
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG Straps for Processor
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
Compal Electronics, Inc.
*
*
*
R353
1K_0402_1%
R353
1K_0402_1%
12
R43
1K_0402_1%
@R43
1K_0402_1%
@
12
T12 PADT12 PAD
R44
1K_0402_1%
@R44
1K_0402_1%
@
12
T11 PADT11 PAD
T9 PADT9 P AD
T10 PADT10 PAD
T13PAD T13PAD
RESERVED
JCPU1E
Sandy Bridge_rPGA_Rev1p0
ME@
RESERVED
JCPU1E
Sandy Bridge_rPGA_Rev1p0
ME@
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34
AM33
RSVD35
AJ27
RSVD38
J16
RSVD42
AT34
RSVD39
H16
RSVD40
G16
RSVD41
AR35
RSVD43
AT33
RSVD45
AR34
RSVD56
AT2
RSVD57
AT1
RSVD58
AR1
RSVD46
B34
RSVD47
A33
RSVD48
A34
RSVD49
B35
RSVD50
C35
RSVD51
AJ32
RSVD52
AK32
RSVD30
AE7
RSVD31
AK2
RSVD28
L7
RSVD29
AG7
RSVD27
J15
RSVD16
C30
RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30
RSVD19
B29
RSVD22
A30
RSVD21
B31
RSVD23
C29
RSVD24
J20
RSVD37
T8
RSVD6
B4
RSVD7
D1
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G25
RSVD13
G24
RSVD14
E23
RSVD32
W8
RSVD33
AT26
RSVD25
B18
RSVD44
AP35
RSVD10
F23
RSVD5
AJ26
VAXG_VAL_SENSE
AJ31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ33
VSS_VAL_SENSE
AH33
KEY
B1
VCC_DIE_SENSE
AH27
VCCIO_SEL
A19
RSVD54
AN35
RSVD55
AM35
R45
1K_0402_1%
@R45
1K_0402_1%
@
12
R42
1K_0402_1%
@ R42
1K_0402_1%
@
12
R41
1K_0402_1%
R41
1K_0402_1%
12
R64
1K_0402_1%
R64
1K_0402_1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+1.05VS
VSSSENSE_R
VCCSENSE_R
H_CPU_SVIDCLK
H_CPU_SVIDDAT
H_CPU_SVIDALRT#
VSSIO_SENSE
VCCIO_SENSE <51>
VCCSENSE <53>
VSSSENSE <53>
VR_SVID_ALRT# <53>
VR_SVID_CLK <53>
VR_SVID_DAT <53>
+CPU_CORE
+CPU_CORE
+CPU_CORE
+CPU_CORE
+1.05VS
+1.05VS
+1.05VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(5/7) PWR,BYPASS
Custom
9 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(5/7) PWR,BYPASS
Custom
9 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(5/7) PWR,BYPASS
Custom
9 50Friday, November 26, 2010
2010/07/12 2012/07/11
18A
DC=53A
Compal Electronics, Inc.
VR_SVID_CL K
Cap quantity follow HR_PDDG_Rev07
QC=94A
(6/16 change 10uF_0603_6.3V)*5
(22uF_0805_6.3V)*16
(330uF)*4
(22uF_0805_6.3V)*13
series-res istors clo se to VR
VCC_SENCE 100ohm +-1% pull-up to VCC near processor
VSS_SENCE 100ohm +-1% pull-down to GND near processor
22uF*7 NO-STUFF
(220uF_6.3V_4.2L_ESR17m)*2=(SF000002Y00)
OSCAN
OSCAN
8/12 Modif y, need fo llow diffe ntial rout ing
R74 close CPU,R75 cl ose PWR
8/23 modif y
C76
22U_0805_6.3V6M
C76
22U_0805_6.3V6M
1
2
C67
22U_0805_6.3V6M
C67
22U_0805_6.3V6M
1
2
C58
22U_0805_6.3V6M
C58
22U_0805_6.3V6M
1
2
C74
22U_0805_6.3V6M
C74
22U_0805_6.3V6M
1
2
+
C399
330U_X_2VM_R6M
@
+
C399
330U_X_2VM_R6M
@
1
2
C59
22U_0805_6.3V6M
@
C59
22U_0805_6.3V6M
@
1
2
C56
22U_0805_6.3V6M
C56
22U_0805_6.3V6M
1
2
C54
22U_0805_6.3V6M
C54
22U_0805_6.3V6M
1
2
C55
22U_0805_6.3V6M
C55
22U_0805_6.3V6M
1
2
C87
22U_0805_6.3V6M
C87
22U_0805_6.3V6M
1
2
R53 0_0402_5%R53 0_0402_5%
1 2
C68
22U_0805_6.3V6M
C68
22U_0805_6.3V6M
1
2
C60
22U_0805_6.3V6M
@
C60
22U_0805_6.3V6M
@
1
2
R49 0_0402_5% R49 0_0402_5%
1 2
C84
22U_0805_6.3V6M
C84
22U_0805_6.3V6M
1
2
+
C89
330U_X_2VM_R6M
+
C89
330U_X_2VM_R6M
1
2
+
C91
330U_X_2VM_R6M
+
C91
330U_X_2VM_R6M
1
2
C38
10U_0805_6.3V6M
C38
10U_0805_6.3V6M
1
2
C61
22U_0805_6.3V6M
@
C61
22U_0805_6.3V6M
@
1
2
C40
10U_0805_6.3V6M
C40
10U_0805_6.3V6M
1
2
C66
22U_0805_6.3V6M
@
C66
22U_0805_6.3V6M
@
1
2
C82
22U_0805_6.3V6M
@
C82
22U_0805_6.3V6M
@
1
2
+
C69
220U_6.3V_M
+
C69
220U_6.3V_M
1
2
C62
22U_0805_6.3V6M
@
C62
22U_0805_6.3V6M
@
1
2
C77
22U_0805_6.3V6M
C77
22U_0805_6.3V6M
1
2
R46
75_0402_5%
R46
75_0402_5%
12
C50
10U_0603_6.3V6M
C50
10U_0603_6.3V6M
1
2
C52
10U_0603_6.3V6M
C52
10U_0603_6.3V6M
1
2
C86
22U_0805_6.3V6M
C86
22U_0805_6.3V6M
1
2
+
C88
330U_X_2VM_R6M
+
C88
330U_X_2VM_R6M
1
2
R52 0_0402_5%R52 0_0402_5%
1 2
C63
22U_0805_6.3V6M
@
C63
22U_0805_6.3V6M
@
1
2
R48 0_0402_5% R48 0_0402_5%
1 2
C78
22U_0805_6.3V6M
C78
22U_0805_6.3V6M
1
2
C81
22U_0805_6.3V6M
@
C81
22U_0805_6.3V6M
@
1
2
+
C73
330U_D2_2.5VY_R9M
@
+
C73
330U_D2_2.5VY_R9M
@
1
2
R47 43_0402_5%R47 43_0402_ 5%
1 2
C46
22U_0805_6.3V6M
C46
22U_0805_6.3V6M
1
2
C79
22U_0805_6.3V6M
C79
22U_0805_6.3V6M
1
2
C36
10U_0805_6.3V6M
C36
10U_0805_6.3V6M
1
2
C44
22U_0805_6.3V6M
C44
22U_0805_6.3V6M
1
2
R54
100_0402_1%
R54
100_0402_1%
12
C71
22U_0805_6.3V6M
C71
22U_0805_6.3V6M
1
2
C70
22U_0805_6.3V6M
C70
22U_0805_6.3V6M
1
2
C64
22U_0805_6.3V6M
@
C64
22U_0805_6.3V6M
@
1
2
+
C394
330U_X_2VM_R6M
@
+
C394
330U_X_2VM_R6M
@
1
2
R51
100_0402_1%
R51
100_0402_1%
12
+
C90
330U_X_2VM_R6M
+
C90
330U_X_2VM_R6M
1
2
C41
22U_0805_6.3V6M
C41
22U_0805_6.3V6M
1
2
R74
0_0402_5%
@
R74
0_0402_5%
@
1 2
C45
22U_0805_6.3V6M
C45
22U_0805_6.3V6M
1
2
C37
10U_0805_6.3V6M
C37
10U_0805_6.3V6M
1
2
C39
10U_0805_6.3V6M
C39
10U_0805_6.3V6M
1
2
C47
22U_0805_6.3V6M
C47
22U_0805_6.3V6M
1
2
C65
22U_0805_6.3V6M
@
C65
22U_0805_6.3V6M
@
1
2
+
C72
220U_6.3V_M
+
C72
220U_6.3V_M
1
2
C80
22U_0805_6.3V6M
C80
22U_0805_6.3V6M
1
2
C75
22U_0805_6.3V6M
C75
22U_0805_6.3V6M
1
2
R75
0_0402_5%
@
R75
0_0402_5%
@
1 2
R50 130_0402_5%R50 130_04 02_5%
12
C49
10U_0603_6.3V6M
C49
10U_0603_6.3V6M
1
2
C83
22U_0805_6.3V6M
C83
22U_0805_6.3V6M
1
2
POWER
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
JCPU1F
Sandy Bridge_rPGA_Rev1p0
ME@
POWER
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
JCPU1F
Sandy Bridge_rPGA_Rev1p0
ME@
VCC_SENSE
AJ35
VSS_SENSE
AJ34
VIDALERT#
AJ29
VIDSCLK
AJ30
VIDSOUT
AJ28
VSSIO_SENSE
A10
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VCCIO1
AH13
VCCIO12
J11
VCCIO18
G12
VCCIO19
F14
VCCIO20
F13
VCCIO21
F12
VCCIO22
F11
VCCIO23
E14
VCCIO24
E12
VCCIO2
AH10
VCCIO3
AG10
VCCIO4
AC10
VCCIO5
Y10
VCCIO6
U10
VCCIO7
P10
VCCIO8
L10
VCCIO9
J14
VCCIO10
J13
VCCIO11
J12
VCCIO13
H14
VCCIO14
H12
VCCIO15
H11
VCCIO16
G14
VCCIO17
G13
VCCIO25
E11
VCCIO32
C12
VCCIO33
C11
VCCIO34
B14
VCCIO35
B12
VCCIO36
A14
VCCIO37
A13
VCCIO38
A12
VCCIO39
A11
VCCIO26
D14
VCCIO27
D13
VCCIO28
D12
VCCIO29
D11
VCCIO30
C14
VCCIO31
C13
VCCIO_SENSE
B10
VCCIO40
J23
C51
10U_0603_6.3V6M
@
C51
10U_0603_6.3V6M
@
1
2
C53
10U_0603_6.3V6M
C53
10U_0603_6.3V6M
1
2
C57
22U_0805_6.3V6M
C57
22U_0805_6.3V6M
1
2
C43
22U_0805_6.3V6M
C43
22U_0805_6.3V6M
1
2
C85
22U_0805_6.3V6M
C85
22U_0805_6.3V6M
1
2
C42
22U_0805_6.3V6M
C42
22U_0805_6.3V6M
1
2
C48
10U_0603_6.3V6M
C48
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+V_SM_VREF_CNT +V_SM_VREF
+VCCSA
H_FC_C22
+1.8VS_VCCPLL VCCSA_SENSE
VCCSA_SENSE
RUN_ON_CPU1.5VS3# RUN_ON_CPU1.5VS3
RUN_ON_CPU1.5VS3
RUN_ON_CPU1.5VS3#
VCCSA_SEL <50>
VCC_AXG_SENSE < 53>
VSS_AXG_SENSE <53>
VSSSA_SENSE <50>
VCCSA_SENSE <50>
SUSP#<32,37,49,51>
CPU1.5V_S3_GATE<32>
SUSP<6,37,51>
+VCCSA
+1.5V_CPU_VDDQ
+1.8VS
+VGFX_CORE
+1.5V_CPU_VDDQ
+1.5V
+1.5V_CPU_VDDQ
+1.5V +1.5V_CPU_VDDQ
+VSB
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(6/7) PWR
Custom
10 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(6/7) PWR
Custom
10 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(6/7) PWR
Custom
10 50Friday, November 26, 2010
2010/07/12 2012/07/11
6/9 change 330U to 22U X2
8/27 change to stuff
Change footprint
20100814
Change footprint
20100814
Change footprint
20100814
10/21 Change
8/27 change to @
8/27 change to @
6.3 X4.2
10/5 change to 1K
11/18 add for sequence
C132
1U_0402_6.3V6K
C132
1U_0402_6.3V6K
1
2
R62
1K_0402_1%
R62
1K_0402_1%
12
R55
220_0402_5%
R55
220_0402_5%
12
C127
10U_0805_6.3V6M
@
C127
10U_0805_6.3V6M
@
1
2
POWER
GRAPHICS
DDR3 -1.5V RAILS
SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
JCPU1G
Sandy Bridge_rPGA_Rev1p0
ME@
POWER
GRAPHICS
DDR3 -1.5V RAILS
SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
JCPU1G
Sandy Bridge_rPGA_Rev1p0
ME@
SM_VREF
AL1
VSSAXG_SENSE
AK34
VAXG_SENSE
AK35
VAXG1
AT24
VAXG2
AT23
VAXG3
AT21
VAXG4
AT20
VAXG5
AT18
VAXG6
AT17
VAXG7
AR24
VAXG8
AR23
VAXG9
AR21
VAXG10
AR20
VAXG11
AR18
VAXG12
AR17
VAXG13
AP24
VAXG14
AP23
VAXG15
AP21
VAXG16
AP20
VAXG17
AP18
VAXG18
AP17
VAXG19
AN24
VAXG20
AN23
VAXG21
AN21
VAXG22
AN20
VAXG23
AN18
VAXG24
AN17
VAXG25
AM24
VAXG26
AM23
VAXG27
AM21
VAXG28
AM20
VAXG29
AM18
VAXG30
AM17
VAXG31
AL24
VAXG32
AL23
VAXG33
AL21
VAXG34
AL20
VAXG35
AL18
VAXG36
AL17
VAXG37
AK24
VAXG38
AK23
VAXG39
AK21
VAXG40
AK20
VAXG41
AK18
VAXG42
AK17
VAXG43
AJ24
VAXG44
AJ23
VAXG45
AJ21
VAXG46
AJ20
VAXG47
AJ18
VAXG48
AJ17
VAXG49
AH24
VAXG50
AH23
VAXG51
AH21
VAXG52
AH20
VAXG53
AH18
VAXG54
AH17
VDDQ11
U4
VDDQ12
U1
VDDQ13
P7
VDDQ14
P4
VDDQ15
P1
VDDQ1
AF7
VDDQ2
AF4
VDDQ3
AF1
VDDQ4
AC7
VDDQ5
AC4
VDDQ6
AC1
VDDQ7
Y7
VDDQ8
Y4
VDDQ9
Y1
VDDQ10
U7
VCCPLL1
B6
VCCPLL2
A6
VCCSA1
M27
VCCSA2
M26
VCCSA3
L26
VCCSA4
J26
VCCSA5
J25
VCCSA6
J24
VCCSA7
H26
VCCSA8
H25
VCCSA_SENSE
H23
VCCSA_VID1
C24
VCCPLL3
A2
FC_C22
C22
C107
22U_0805_6.3V6M
C107
22U_0805_6.3V6M
1
2
C113
22U_0805_6.3V6M
C113
22U_0805_6.3V6M
1
2
J1
PAD-OPEN 4x4m
@J1
PAD-OPEN 4x4m
@
1 2
R63
1K_0402_1%
R63
1K_0402_1%
12
R580_0402_5%
@
R580_0402_5%
@
1 2
R69 10K_0402_5%
R69 10K_0402_5%
1 2
R60
0_0402_5%
@
R60
0_0402_5%
@
12
C125
10U_0805_6.3V6M
C125
10U_0805_6.3V6M
1
2
C99
22U_0805_6.3V6M
C99
22U_0805_6.3V6M
1
2
R590_0402_5%
@
R590_0402_5%
@
1 2
+
C115
330U_D2_2.5VY_R9M
+
C115
330U_D2_2.5VY_R9M
1
2
C126
10U_0805_6.3V6M
C126
10U_0805_6.3V6M
1
2
R56
15K_0402_1%
R56
15K_0402_1%
12
C108
22U_0805_6.3V6M
C108
22U_0805_6.3V6M
1
2
C104
22U_0805_6.3V6M
C104
22U_0805_6.3V6M
1
2
C129
0.1U_0402_10V6K
@
C129
0.1U_0402_10V6K
@
1
2
C114
0.1U_0402_16V4Z
C114
0.1U_0402_16V4Z
1
2
C97
0.1U_0603_25V7K
C97
0.1U_0603_25V7K
1
2
C122
10U_0603_6.3V6M
C122
10U_0603_6.3V6M
1
2
C106
22U_0805_6.3V6M
C106
22U_0805_6.3V6M
1
2
C154
22U_0805_6.3V6M
@
C154
22U_0805_6.3V6M
@
1
2
R61
0_0402_5%
R61
0_0402_5%
12
R666
100K_0402_5%
@
R666
100K_0402_5%
@
1 2
C121
10U_0603_6.3V6M
C121
10U_0603_6.3V6M
1
2
C105
22U_0805_6.3V6M
C105
22U_0805_6.3V6M
1
2
R667
100K_0402_5% @
R667
100K_0402_5% @
12
C98
22U_0805_6.3V6M
C98
22U_0805_6.3V6M
1
2
G
D
S
Q4
2N7002H_SOT23-3
G
D
S
Q4
2N7002H_SOT23-3
2
13
C124
10U_0805_6.3V6M
C124
10U_0805_6.3V6M
1
2
C109
22U_0805_6.3V6M
C109
22U_0805_6.3V6M
1
2
C396
0.1U_0402_10V6K
@
C396
0.1U_0402_10V6K
@
1
2
C111
22U_0805_6.3V6M
@
C111
22U_0805_6.3V6M
@
1
2
Q5
AP2302GN-HF_SOT23-3
@Q5
AP2302GN-HF_SOT23-3
@
1
2
3
C100
22U_0805_6.3V6M
C100
22U_0805_6.3V6M
1
2
C345
22U_0805_6.3V6M
@
C345
22U_0805_6.3V6M
@
1
2
C120
10U_0603_6.3V6M
C120
10U_0603_6.3V6M
1
2
C117
10U_0603_6.3V6M
C117
10U_0603_6.3V6M
1
2
C130
10U_0805_6.3V6M
C130
10U_0805_6.3V6M
1
2
G
D
S
Q7
2N7002H_SOT23-3
@
G
D
S
Q7
2N7002H_SOT23-3
@
2
13
C92
0.1U_0402_10V6K
@ C92
0.1U_0402_10V6K
@
1
2
G
D
S
Q3
2N7002H_SOT23-3
G
D
S
Q3
2N7002H_SOT23-3
2
13
C95
0.1U_0402_10V6K
C95
0.1U_0402_10V6K
1
2
C119
10U_0603_6.3V6M
C119
10U_0603_6.3V6M
1
2
+
C116
330U_D2_2.5VY_R9M
@
+
C116
330U_D2_2.5VY_R9M
@
1
2
C112
22U_0805_6.3V6M
C112
22U_0805_6.3V6M
1
2
C102
22U_0805_6.3V6M
C102
22U_0805_6.3V6M
1
2
R57
330K_0402_5%
@
R57
330K_0402_5%
@
12
C118
10U_0603_6.3V6M
C118
10U_0603_6.3V6M
1
2
R885
0_0402_5%
R885
0_0402_5%
1 2
+
C123
330U_2.5V_M
+
C123
330U_2.5V_M
1
2
R66 0_0402_5%R66 0_0402_5%
1 2
U3
DMN3030LSS-13_SOP8L-8
U3
DMN3030LSS-13_SOP8L-8
36
5
7
8
2
4
1
C131
1U_0402_6.3V6K
C131
1U_0402_6.3V6K
1
2
R68 0_0402_5%
@
R68 0_0402_5%
@
1 2
R65 0_0402_5%R65 0_0402_5%
1 2
C96
0.1U_0402_10V6K
C96
0.1U_0402_10V6K
1
2
C103
22U_0805_6.3V6M
C103
22U_0805_6.3V6M
1
2
C101
22U_0805_6.3V6M
C101
22U_0805_6.3V6M
1
2
R6680_0402_5% R6680_0402_5%
1 2
+
C128
330U_2.5V_M
@
+
C128
330U_2.5V_M
@
1
2
R67
0_0805_5%
R67
0_0805_5%
1 2
C110
22U_0805_6.3V6M
@
C110
22U_0805_6.3V6M
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(7/7) VSS
Custom
11 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(7/7) VSS
Custom
11 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PROCESSOR(7/7) VSS
Custom
11 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
VSS
JCPU1H
Sandy Bridge_rPGA_Rev1p0
ME@
VSS
JCPU1H
Sandy Bridge_rPGA_Rev1p0
ME@
VSS1
AT35
VSS2
AT32
VSS3
AT29
VSS4
AT27
VSS5
AT25
VSS6
AT22
VSS7
AT19
VSS8
AT16
VSS9
AT13
VSS10
AT10
VSS11
AT7
VSS12
AT4
VSS13
AT3
VSS14
AR25
VSS15
AR22
VSS16
AR19
VSS17
AR16
VSS18
AR13
VSS19
AR10
VSS20
AR7
VSS21
AR4
VSS22
AR2
VSS23
AP34
VSS24
AP31
VSS25
AP28
VSS26
AP25
VSS27
AP22
VSS28
AP19
VSS29
AP16
VSS30
AP13
VSS31
AP10
VSS32
AP7
VSS33
AP4
VSS34
AP1
VSS35
AN30
VSS36
AN27
VSS37
AN25
VSS38
AN22
VSS39
AN19
VSS40
AN16
VSS41
AN13
VSS42
AN10
VSS43
AN7
VSS44
AN4
VSS45
AM29
VSS46
AM25
VSS47
AM22
VSS48
AM19
VSS49
AM16
VSS50
AM13
VSS51
AM10
VSS52
AM7
VSS53
AM4
VSS54
AM3
VSS55
AM2
VSS56
AM1
VSS57
AL34
VSS58
AL31
VSS59
AL28
VSS60
AL25
VSS61
AL22
VSS62
AL19
VSS63
AL16
VSS64
AL13
VSS65
AL10
VSS66
AL7
VSS67
AL4
VSS68
AL2
VSS69
AK33
VSS70
AK30
VSS71
AK27
VSS72
AK25
VSS73
AK22
VSS74
AK19
VSS75
AK16
VSS76
AK13
VSS77
AK10
VSS78
AK7
VSS79
AK4
VSS80
AJ25
VSS81
AJ22
VSS82
AJ19
VSS83
AJ16
VSS84
AJ13
VSS85
AJ10
VSS86
AJ7
VSS87
AJ4
VSS88
AJ3
VSS89
AJ2
VSS90
AJ1
VSS91
AH35
VSS92
AH34
VSS93
AH32
VSS94
AH30
VSS95
AH29
VSS96
AH28
VSS97
AH26
VSS98
AH25
VSS99
AH22
VSS100
AH19
VSS101
AH16
VSS102
AH7
VSS103
AH4
VSS104
AG9
VSS105
AG8
VSS106
AG4
VSS107
AF6
VSS108
AF5
VSS109
AF3
VSS110
AF2
VSS111
AE35
VSS112
AE34
VSS113
AE33
VSS114
AE32
VSS115
AE31
VSS116
AE30
VSS117
AE29
VSS118
AE28
VSS119
AE27
VSS120
AE26
VSS121
AE9
VSS122
AD7
VSS123
AC9
VSS124
AC8
VSS125
AC6
VSS126
AC5
VSS127
AC3
VSS128
AC2
VSS129
AB35
VSS130
AB34
VSS131
AB33
VSS132
AB32
VSS133
AB31
VSS134
AB30
VSS135
AB29
VSS136
AB28
VSS137
AB27
VSS138
AB26
VSS139
Y9
VSS140
Y8
VSS141
Y6
VSS142
Y5
VSS143
Y3
VSS144
Y2
VSS145
W35
VSS146
W34
VSS147
W33
VSS148
W32
VSS149
W31
VSS150
W30
VSS151
W29
VSS152
W28
VSS153
W27
VSS154
W26
VSS155
U9
VSS156
U8
VSS157
U6
VSS158
U5
VSS159
U3
VSS160
U2
VSS
JCPU1I
Sandy Bridge_rPGA_Rev1p0
ME@
VSS
JCPU1I
Sandy Bridge_rPGA_Rev1p0
ME@
VSS161
T35
VSS162
T34
VSS163
T33
VSS164
T32
VSS165
T31
VSS166
T30
VSS167
T29
VSS168
T28
VSS169
T27
VSS170
T26
VSS171
P9
VSS172
P8
VSS173
P6
VSS174
P5
VSS175
P3
VSS176
P2
VSS177
N35
VSS178
N34
VSS179
N33
VSS180
N32
VSS181
N31
VSS182
N30
VSS183
N29
VSS184
N28
VSS185
N27
VSS186
N26
VSS187
M34
VSS188
L33
VSS189
L30
VSS190
L27
VSS191
L9
VSS192
L8
VSS193
L6
VSS194
L5
VSS195
L4
VSS196
L3
VSS197
L2
VSS198
L1
VSS199
K35
VSS200
K32
VSS201
K29
VSS202
K26
VSS203
J34
VSS204
J31
VSS205
H33
VSS206
H30
VSS207
H27
VSS208
H24
VSS209
H21
VSS210
H18
VSS211
H15
VSS212
H13
VSS213
H10
VSS214
H9
VSS215
H8
VSS216
H7
VSS217
H6
VSS218
H5
VSS219
H4
VSS220
H3
VSS221
H2
VSS222
H1
VSS223
G35
VSS224
G32
VSS225
G29
VSS226
G26
VSS227
G23
VSS228
G20
VSS229
G17
VSS230
G11
VSS231
F34
VSS232
F31
VSS233
F29
VSS234
F22
VSS235
F19
VSS236
E30
VSS237
E27
VSS238
E24
VSS239
E21
VSS240
E18
VSS241
E15
VSS242
E13
VSS243
E10
VSS244
E9
VSS245
E8
VSS246
E7
VSS247
E6
VSS248
E5
VSS249
E4
VSS250
E3
VSS251
E2
VSS252
E1
VSS253
D35
VSS254
D32
VSS255
D29
VSS256
D26
VSS257
D20
VSS258
D17
VSS259
C34
VSS260
C31
VSS261
C28
VSS262
C27
VSS263
C25
VSS264
C23
VSS265
C10
VSS266
C1
VSS267
B22
VSS268
B19
VSS269
B17
VSS270
B15
VSS271
B13
VSS272
B11
VSS273
B9
VSS274
B8
VSS275
B7
VSS276
B5
VSS277
B3
VSS278
B2
VSS279
A35
VSS280
A32
VSS281
A29
VSS282
A26
VSS283
A23
VSS284
A20
VSS285
A3
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D31
DDR_A_D12
DDR_CKE0_DIMMA
DDR_A_D59
DDR_A_D6
DDR_A_MA3
DDR_CS1_DIMMA#
DDR_A_D39
DDR_A_BS1
DDR_A_DQS0
DDR_A_WE#
DDR_A_MA7
DDR_A_MA0
DDR_A_DM2
DDR_A_DM1
DDR_A_DQS7
DDR_A_D0
DDR_A_D57
DDR_A_D46
DDR_A_D28
DDR_A_DM0
DDR_A_D19
DDR_A_DQS#5
DDR_A_D51
DDR_A_D4
DDR_A_DM4
DDR_A_D30
DDR_A_DQS2
DDR_A_D44
DDR_A_RAS#
DDR_A_D33
DDR_A_D58
DDR_A_DM5
DDR_A_DQS3
DDR_A_MA8
DDR_CS0_DIMMA#
DDR_A_D10
DDR_A_MA6
DDR_A_D27
DDR_A_D3
DDR3_DRAMRST#
DDR_A_MA10
DDR_A_DQS#7
DDR_A_D1
DDR_A_DQS#6
DDR_A_D40
DDR_A_MA9
DDR_A_D16
DDR_A_D29
DDR_A_DQS#4
DDR_A_D52
DDR_A_DM3
DDR_A_DQS5
DDR_A_D54
DDR_A_D49
DDR_A_BS2
DDR_A_D45
DDR_A_D9
DDR_A_DM7
DDR_A_D7
DDR_A_MA1
DDR_A_D13
DDR_A_D20
DDR_A_D60
DDR_A_BS0
DDR_A_CAS# M_ODT0
DDR_A_D37
DDR_A_MA5
DDR_A_DQS#1
DDR_A_MA14
DDR_A_D55
DDR_A_MA4
DDR_A_D21
DDR_A_D62
DDR_A_D24
DDR_A_D15
DDR_A_D23
DDR_A_D56
DDR_A_D53
DDR_A_D47
DDR_A_D18
M_ODT1
DDR_A_D43
DDR_A_D34
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_D48
DDR_A_DQS#2
DDR_A_D11
DDR_A_D38
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_DQS#3
DDR_A_D32
DDR_A_D8
DDR_A_DQS1
DDR_A_MA13
DDR_A_MA11
DDR_A_D50
DDR_A_D61
DDR_A_MA2
DDR_A_D41
DDR_A_D17
DDR_A_D36
DDR_A_D26
DDR_A_D63
DDR_A_D2
DDR_A_D5
DDR_A_D22
DDR_A_D25
DDR_A_DQS6
DDR_A_D35
DDR_A_D14
DDR_A_MA12
DDR_A_DQS#0
DDR_A_DQS4
DDR_A_DM6
DDR_A_D42
DDR_CKE1_DIMMA
+VREF_CA
+VREF_DQ_DIMMA
DDR_A_MA15
DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3
DDR_A_DM4
DDR_A_DM5
DDR_A_DM6
DDR_A_DM7
SMB_CLK_S3
SMB_DATA_S3
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..15]<7>
DDR_CKE0_DIMMA<7>
DDR_A_BS2<7>
M_CLK_DDR0<7>
M_CLK_DDR#0<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1_DIMMA#<7>
DDR_CKE1_DIMMA <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
M_ODT0 <7>
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
M_ODT1 <7>
DDR3_DRAMRST# <7,13>
SMB_CLK_S3 <13,15,26>
SMB_DATA_S3 <13,15,26>
+0.75VS
+3VS
+1.5V +1.5V
+VREF_DQ_DIMMA +1.5V
+VREF_DQ_DIMMA
+1.5V
+0.75VS
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
DDRIII-SODIMM SLOT1
Custom
12 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
DDRIII-SODIMM SLOT1
Custom
12 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
DDRIII-SODIMM SLOT1
Custom
12 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
DDR3 SO-DIMM A
Layout Note:
Place near DIMM
3A@1.5V
3A@1.5V3A@1.5V
3A@1.5V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
0.65A@0.75V
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
VDDQ(1.5V) =
3*0805 10uf
VTT(0.75V) =
4*0402 1uf
1*0402 0.1uf
VREF =
1*0402 2.2uf
VDDSPD (3.3V)=
1*0402 0.1uf 1*0402 2.2uf
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
(220uF_6.3V_4.2L_ESR17m)*1=(SF000002Y00)OSCAN
7/28 Update connect GND directly
C136
2.2U_0603_6.3V4Z
C136
2.2U_0603_6.3V4Z
1
2
C139
10U_0603_6.3V6M
C139
10U_0603_6.3V6M
1
2
C134
2.2U_0603_6.3V4Z
C134
2.2U_0603_6.3V4Z
1
2
C155
2.2U_0603_6.3V4Z
C155
2.2U_0603_6.3V4Z
1
2
C143
10U_0603_6.3V6M
C143
10U_0603_6.3V6M
1
2
C141
10U_0603_6.3V6M
C141
10U_0603_6.3V6M
1
2
R73
1K_0402_1%
R73
1K_0402_1%
12
C137
10U_0603_6.3V6M
@
C137
10U_0603_6.3V6M
@
1
2
C138
10U_0603_6.3V6M
@
C138
10U_0603_6.3V6M
@
1
2
C156
0.1U_0402_10V6K
C156
0.1U_0402_10V6K
1
2
C142
10U_0603_6.3V6M
C142
10U_0603_6.3V6M
1
2
C145
0.1U_0402_10V6K
C145
0.1U_0402_10V6K
1
2
R81
10K_0402_5%
R81
10K_0402_5%
1 2
C146
0.1U_0402_10V6K
C146
0.1U_0402_10V6K
1
2
C144
10U_0603_6.3V6M
C144
10U_0603_6.3V6M
1
2
C133
0.1U_0402_10V6K
C133
0.1U_0402_10V6K
1
2
JDIMM1
FOX_AS0A626-U4SN-7F
ME@
JDIMM1
FOX_AS0A626-U4SN-7F
ME@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C148
0.1U_0402_10V6K
C148
0.1U_0402_10V6K
1
2
C140
10U_0603_6.3V6M
C140
10U_0603_6.3V6M
1
2
C147
0.1U_0402_10V6K
C147
0.1U_0402_10V6K
1
2
C135
0.1U_0402_10V6K
C135
0.1U_0402_10V6K
1
2
C151
1U_0402_6.3V6K
C151
1U_0402_6.3V6K
1
2
R83
10K_0402_5%
R83
10K_0402_5%
12
R72
1K_0402_1%
R72
1K_0402_1%
12
C150
1U_0402_6.3V6K
@
C150
1U_0402_6.3V6K
@
1
2
C152
1U_0402_6.3V6K
C152
1U_0402_6.3V6K
1
2
R71
1K_0402_1%
R71
1K_0402_1%
12
R70
1K_0402_1%
R70
1K_0402_1%
12
C153
1U_0402_6.3V6K
@
C153
1U_0402_6.3V6K
@
1
2
+
C149
220U_6.3V_M
@
+
C149
220U_6.3V_M
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_D36
DDR_B_D63
DDR_B_MA15
DDR_B_DM6
DDR_B_D39
DDR_B_BS1
DDR_B_MA7
DDR_B_MA0
DDR_B_DQS7
DDR_B_D46
DDR_B_DQS#5
DDR_B_DM4
DDR_B_D44
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_MA6
DDR_B_DQS#7
DDR_B_D52
DDR_B_DQS5
DDR_B_D54
DDR_B_D45
DDR_B_D60
M_ODT2
DDR_B_D37
DDR_B_MA14
DDR_B_D55
DDR_B_MA4
DDR_B_D62
DDR_B_D53
DDR_B_D47
M_ODT3
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D38
DDR_B_MA11
DDR_B_D61
DDR_B_MA2
SMB_CLK_S3
SMB_DATA_S3
DDR_B_DQS6
DDR_B_D35
DDR_B_MA12
DDR_B_DQS4
DDR_B_D42
DDR_CKE2_DIMMB
DDR_B_D59
DDR_B_MA3
DDR_CS3_DIMMB#
DDR_B_WE#
DDR_B_D57
DDR_B_D51
DDR_B_D33
DDR_B_D58
DDR_B_DM5
DDR_B_MA8
DDR_B_MA10
DDR_B_DQS#6
DDR_B_D40
DDR_B_MA9
DDR_B_DQS#4
DDR_B_D49
DDR_B_BS2
DDR_B_DM7
DDR_B_MA1
DDR_B_BS0
DDR_B_CAS#
DDR_B_MA5
DDR_B_D56
DDR_B_D43
DDR_B_D34
DDR_B_D48
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_D32
DDR_B_MA13
DDR_B_D50
DDR_B_D41
DDR_B_DM6
DDR_B_DM7
DDR_B_DM0
DDR_B_DM1
DDR_B_DM2
DDR_B_DM3
DDR_B_DM4
DDR_B_DM5
+VREF_CB
DDR_B_D5
DDR_B_D22
DDR_B_D14
DDR_B_DQS#0
DDR_B_D31
DDR_B_D12
DDR_B_D6
DDR_B_DQS0
DDR_B_DM2
DDR_B_DM1
DDR_B_D28
DDR_B_D4
DDR_B_D30
DDR_B_DQS3
DDR3_DRAMRST#
DDR_B_D29
DDR_B_D7
DDR_B_D13
DDR_B_D20
DDR_B_D21
DDR_B_D15
DDR_B_D23
DDR_B_DQS#3
DDR_CKE3_DIMMB
DDR_B_D26
DDR_B_D2
DDR_B_D25
+VREF_DQ_DIMMB
DDR_B_D0
DDR_B_DM0
DDR_B_D19
DDR_B_DQS2
DDR_B_D10
DDR_B_D27
DDR_B_D3
DDR_B_D1
DDR_B_D16
DDR_B_DM3
DDR_B_D9
DDR_B_DQS#1
DDR_B_D24
DDR_B_D18
DDR_B_DQS#2
DDR_B_D11
DDR_B_D8
DDR_B_DQS1
DDR_B_D17
DDR3_DRAMRST# <7,12>
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..15]<7>
DDR_CKE3_DIMMB <7>
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <7>
M_ODT2 <7>
M_ODT3 <7>
SMB_DATA_S3 <12,15,26>
SMB_CLK_S3 <12,15,26>
DDR_B_BS2<7>
DDR_CKE2_DIMMB<7>
M_CLK_DDR2<7>
M_CLK_DDR#2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<7>
+0.75VS
+3VS
+1.5V
+VREF_DQ_DIMMB
+1.5V
+0.75VS
+1.5V
+VREF_DQ_DIMMB
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
DDRIII-SODIMM SLOT2
13 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
DDRIII-SODIMM SLOT2
13 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
DDRIII-SODIMM SLOT2
13 50Friday, November 26, 2010
2010/07/12 2012/07/11
Compal Electronics, Inc.
LA-6752P
Layout Note:
Place near DIMM
3A@1.5V
3A@1.5V3A@1.5V
3A@1.5V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
0.65A@0.75V
1*0402 0.1uf 1*0402 2.2uf
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
3*0805 10uf
VTT(0.75V) =
4*0402 1uf
1*0402 0.1uf
VDDQ(1.5V) =
1*0402 2.2uf
VDDSPD (3.3V)=
For Arranale only +VREF_DQ_DIMMB
supply from a external 1.5V voltage divide
circuit.
07/17/2009
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
(10uF_0603_6.3V)*8
(0.1uF_402_10V)*4
7/28 Update connect GND directly
C165
10U_0603_6.3V6M
C165
10U_0603_6.3V6M
1
2
R86
1K_0402_1%
R86
1K_0402_1%
12
R95
10K_0402_5%
R95
10K_0402_5%
1 2
C170
0.1U_0402_10V6K
C170
0.1U_0402_10V6K
1
2
C158
2.2U_0603_6.3V4Z
C158
2.2U_0603_6.3V4Z
1
2
C161
10U_0603_6.3V6M
@
C161
10U_0603_6.3V6M
@
1
2
C162
10U_0603_6.3V6M
@
C162
10U_0603_6.3V6M
@
1
2
C168
10U_0603_6.3V6M
C168
10U_0603_6.3V6M
1
2
R84
1K_0402_1%
R84
1K_0402_1%
12
C163
10U_0603_6.3V6M
C163
10U_0603_6.3V6M
1
2
C166
10U_0603_6.3V6M
C166
10U_0603_6.3V6M
1
2
R87
1K_0402_1%
R87
1K_0402_1%
12
JDIMM2
FOX_AS0A626-U8SN-7F
ME@
JDIMM2
FOX_AS0A626-U8SN-7F
ME@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C173
1U_0402_6.3V6K
C173
1U_0402_6.3V6K
1
2
C174
1U_0402_6.3V6K
@
C174
1U_0402_6.3V6K
@
1
2
R97 10K_0402_5%R97 10K_0402_5%
1 2
C175
1U_0402_6.3V6K
C175
1U_0402_6.3V6K
1
2
C169
0.1U_0402_10V6K
C169
0.1U_0402_10V6K
1
2
C176
1U_0402_6.3V6K
@
C176
1U_0402_6.3V6K
@
1
2
C167
10U_0603_6.3V6M
C167
10U_0603_6.3V6M
1
2
C159
0.1U_0402_10V6K
C159
0.1U_0402_10V6K
1
2
C172
0.1U_0402_10V6K
C172
0.1U_0402_10V6K
1
2
C178
0.1U_0402_10V6K
C178
0.1U_0402_10V6K
1
2
C160
2.2U_0603_6.3V4Z
C160
2.2U_0603_6.3V4Z
1
2
C177
2.2U_0603_6.3V4Z
C177
2.2U_0603_6.3V4Z
1
2
R85
1K_0402_1%
R85
1K_0402_1%
12
C157
0.1U_0402_10V6K
C157
0.1U_0402_10V6K
1
2
C171
0.1U_0402_10V6K
C171
0.1U_0402_10V6K
1
2
C164
10U_0603_6.3V6M
C164
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_RTCX1
PCH_RTCX2
PCH_RTCX1
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
SM_INTRUDER#
HDA_SPKR
SPI_CLK_PCH_R
SPI_SI
SPI_SO_R
SPI_SB_CS0#
PCH_JTAG_TCK
HDD_LED#
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
HDA_SYNC
HDA_RST#
HDA_SDIN0
HDA_SDOUT
PCH_GPIO21
PCH_RTCX2
HDA_BIT_CLK
PCH_JTAG_TDO PCH_JTAG_TDIPCH_JTAG_TMS
LPC_AD2
LPC_FRAME#
LPC_AD0
LPC_AD3
LPC_AD1
SERIRQ
SATA_COMP
RBIAS_SATA3
SATA3_COMP
HDA_BIT_CLK
HDA_RST#
HDA_SDOUT
PCH_INTVRMEN
HDA_SPKR
HDA_SDOUT
HDA_SYNC
SPI_WP#
SPI_HOLD#
SPI_WP#
SPI_HOLD#SPI_SO_R SPI_SO_L
SPI_SI_R
SPI_CLK_PCH
SPI_CLK_PCH
SPI_CLK_PCH_R
SPI_SB_CS0#
PCH_GPIO33
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
SPI_SI
SERIRQ
SATA_ITX_DRX_N2_CONN
SATA_DTX_C_IRX_N2
SATA_ITX_DRX_P2_CONN
SATA_DTX_C_IRX_P2
SATA_ITX_C_DRX_N2
SATA_ITX_C_DRX_P2
ME_FLASH
HDA_SYNC
Kill_SW#
PCH_GPIO19
SATA_ITX_DRX_P4
SATA_ITX_DRX_N4
SATA_DTX_C_IRX_N4
SATA_DTX_C_IRX_P4
SATA_ITX_C_DRX_N4
SATA_ITX_C_DRX_P4
HDA_SYNC_R
HDA_SPKR<31 >
HDA_SDIN0<31>
SERIRQ <32>
LPC_AD0 <26,32>
LPC_AD1 <26,32>
LPC_AD2 <26,32>
LPC_AD3 <26,32>
LPC_FRAME# <26,32>
HDA_SYNC_AUDIO<31>
HDA_SDOUT_AUDIO<31>
HDA_RST_AUDIO#<31>
HDA_BITCLK_AUDIO<31>
HDD_LED# <56,57>
SATA_DTX_C_IRX_N0 <30>
SATA_DTX_C_IRX_P0 <30>
SATA_ITX_DRX_N0 <30>
SATA_ITX_DRX_P0 <30>
SATA_DTX_C_IRX_P2 <56,57>
SATA_ITX_DRX_N2_CONN < 56,57>
SATA_DTX_C_IRX_N2 <56,57>
SATA_ITX_DRX_P2_CONN <56,57>
ME_FLASH<32>
Kill_SW#<56,57>
PCH_RTCX1_OUT <3 2>
PCH_RTCX2_OUT <3 2>
SATA_ITX_DRX_N4 <35>
SATA_ITX_DRX_P4 <35>
SATA_DTX_C_IRX_N4 <35>
SATA_DTX_C_IRX_P4 <35>
+RTCVCC
+RTCVCC
+3VALW +3VALW+3VALW
+1.05VS_VCC_SATA
+1.05VS_SATA3
+3VS
+3VALW
+3VALW
+3VS
+3VS
+RTCBATT+RTCVC C
+3VS
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6751P
0.2
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Custom
14 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6751P
0.2
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Custom
14 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6751P
0.2
PCH (1/8) SATA,HDA,SPI, LPC, XDP
Custom
14 50Friday, November 26, 2010
2010/07/12 2012/07/11
CMOS
HDD
Compal Electronics, Inc.
H
：
：：
：
Integrated VRM enable
L
：
：：
：
Integrated VRM disable
INTVRMEN
*
LOW= Disable (Default)
HIGH= Enable ( No Reboot )
*
*
Low = Disabled (Default)
High = Enabled [Flash Descriptor Security Overide]
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
1.5V when smapled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
*
(INTVRMEN should always be pull high.)
4MB SPI ROM FOR ME
& Non-share ROM.
W=20milsW=20mils
DPDG1.1
EC and Mini card debug port
ODD
6/24 Update R663,R670 must be close Y1
6/30 updat e R121, R1 22, R123
ESATA
7/28 chang e from por t 5 to por t 4
8/16 reser ved for MO W
9/27 reserve R878 for DG1.5
R119
10K_0402_5%
R119
10K_0402_5%
12
R107 1K_0402_1%@R107 1K_0402_1%@
1 2
R187 10K_0402_5%
@
R187 10K_0402_5%
@
12
R122
200_0402_5%
R122
200_0402_5%
12
C1850.01U_0402_16V7K C1850.01U_0402_16V7K
12
R108 1K_0402_5% R108 1K_0402_5%
12
R109
0_0402_5%
R109
0_0402_5%
1 2
R128
100_0402_1%
R128
100_0402_1%
12
R129
3.3K_0402_5%
R129
3.3K_0402_5%
1 2
R104 10K_0402_5%R104 10K_040 2_5%
12
R116
33_0402_5%
R116
33_0402_5%
1 2
R110
51_0402_5%
R110
51_0402_5%
12
CLRP2
SHORT PADS
CLRP2
SHORT PADS
12
C1840.01U_0402_16V7K C1840.01U_0402_16V7K
12
R124
33_0402_5%
@
R124
33_0402_5%
@
12
C1870.01U_0402_16V7K C1870.01U_0402_16V7K
12
R133
33_0402_5%
R133
33_0402_5%
1 2
R100 20K_0402_5%R100 20K _0402_5%
1 2
C180
15P_0402_50V8J
C180
15P_0402_50V8J
1
2
CLRP3
SHORT PADS
CLRP3
SHORT PADS
12
R127
3.3K_0402_5%
R127
3.3K_0402_5%
1 2
R325
0_0402_5%
@R325
0_0402_5%
@
1 2
G
D
S
Q10
BSS138_NL_SOT23-3
G
D
S
Q10
BSS138_NL_SOT23-3
2
13
R1320_0402_5% R1320_0402_5%
1 2
C181
15P_0402_50V8J
C181
15P_0402_50V8J
1
2
C191
0.1U_0402_16V4Z
C191
0.1U_0402_16V4Z
1 2
C190
22P_0402_50V8J
@
C190
22P_0402_50V8J
@
U5
S IC FL 32M W25Q32BVSSIG SOIC 8P
U5
S IC FL 32M W25Q32BVSSIG SOIC 8P
CS#
1
SO
2
WP#
3
GND
4
VCC
8
HOLD#
7
SCLK
6
SI
5
R99
1K_0402_5%
R99
1K_0402_5%
1 2
R130
0_0402_5%
R130
0_0402_5%
1 2
R878
1M_0402_5%
R878
1M_0402_5%
1 2
R131
33_0402_5%
R131
33_0402_5%
1 2
R101 1M_0402_5%R101 1M_0402_5%
1 2
C1890.01U_0402_16V7K
ESATA@
C1890.01U_0402_16V7K
ESATA@
12
R670 0_040 2_5%@ R670 0_0402_ 5%@
1 2
R105 1K_0402_5%@R105 1K_0402_5%@
1 2
R117 10K_0402_5%R117 10K_040 2_5%
12
R126
100_0402_1%
R126
100_0402_1%
12
C1880.01U_0402_16V7K
ESATA@
C1880.01U_0402_16V7K
ESATA@
12
R123
200_0402_5%
R123
200_0402_5%
12
R663 0_040 2_5%@ R663 0_0402_ 5%@
1 2
CLRP1
SHORT PADS
CLRP1
SHORT PADS
12
R121
200_0402_5%
@
R121
200_0402_5%
@
12
R111
37.4_0402_1%
R111
37.4_0402_1%
1 2
RTCIHDA
SATA
LPC
SPI
JTAG
SATA 6G
U4A
COUGARPOINT_FCBGA989
RTCIHDA
SATA
LPC
SPI
JTAG
SATA 6G
U4A
COUGARPOINT_FCBGA989
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED#
P3
FWH0 / LAD0
C38
FWH1 / LAD1
A38
FWH2 / LAD2
B37
FWH3 / LAD3
C37
LDRQ1# / GPIO23
K36
FWH4 / LFRAME#
D36
LDRQ0#
E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_EN# / GPIO33
C36
HDA_DOCK_RST# / GPIO13
N32
SRTCRST#
G22
SATA0RXN
AM3
SATA0RXP
AM1
SATA0TXN
AP7
SATA0TXP
AP5
SATA1RXN
AM10
SATA1RXP
AM8
SATA1TXN
AP11
SATA1TXP
AP10
SATA2RXN
AD7
SATA2RXP
AD5
SATA2TXN
AH5
SATA2TXP
AH4
SATA3RXN
AB8
SATA3RXP
AB10
SATA3TXN
AF3
SATA3TXP
AF1
SATA4RXN
Y7
SATA4RXP
Y5
SATA4TXN
AD3
SATA4TXP
AD1
SATA5RXN
Y3
SATA5RXP
Y1
SATA5TXN
AB3
SATA5TXP
AB1
SATAICOMPI
Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP / GPIO21
V14
SATA1GP / GPIO19
P1
JTAG_TCK
J3
JTAG_TMS
H7
JTAG_TDI
K5
JTAG_TDO
H1
SERIRQ
V5
SPKR
T10
SATAICOMPO
Y11
SATA3COMPI
AB13
SATA3RCOMPO
AB12
SATA3RBIAS
AH1
C1860.01U_0402_16V7K C1860.01U_0402_16V7K
12
R118
33_0402_5%
R118
33_0402_5%
1 2
R102 330K_0402_5%R102 330K_0402_5%
1 2
Y1
32.768KHZ_12.5PF_9H03200413
Y1
32.768KHZ_12.5PF_9H03200413
OSC
4
OSC
1
NC
3
NC
2
R125
100_0402_1%
@
R125
100_0402_1%
@
12
R106 1K_0402_5%@R106 1K_0402_5%@
12
R115 750_0402_1%R115 750_0402_1%
1 2
R114
33_0402_5%
R114
33_0402_5%
1 2
R112
33_0402_5%
R112
33_0402_5%
1 2
R98 10M_0402_5%R98 10M_0402_5%
1 2
C179
1U_0603_10V4Z
C179
1U_0603_10V4Z
1
2
R103 20K_0402_5%R103 20K _0402_5%
1 2
C182
1U_0603_10V4Z
C182
1U_0603_10V4Z
1
2
R113
49.9_0402_1%
R113
49.9_0402_1%
1 2
C183
1U_0603_10V4Z
C183
1U_0603_10V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XTAL25_IN
XTAL25_OUT
PCH_SML1DATA
XCLK_RCOMP
CLK_PCI_LPBACK
CLK_CPU_DMI#
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2
PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N1
PCIE_PRX_DTX_P1
PCIE_PRX_DTX_N1
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
CLK_BUF_CPU_DMI
CLK_BUF_CPU_DMI#
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
PCH_GPIO26
PCH_GPIO44
XTAL25_OUT
XTAL25_IN
EC_SMB_CK2
EC_SMB_DA2
CLKIN_DMI2#
CLKIN_DMI2
PCH_GPIO56
PCH_GPIO73
PCH_GPIO74
EC_LID_OUT#
PEG_CLKREQ#_R
CLK_CPU_DMI
CLK_PCI_DB_R
CLK_BUF_ICH_14M
PCH_SMBCLK
PCH_SMBDATA
DRAMRST_CNTRL_PC H
PCH_SML1CLK
PCH_GPIO46
SMB_CLK_S3
SMB_DATA_S3
CLK_CPU_DMI
CLK_CPU_DMI#
PCH_GPIO25
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
WLAN_CLKREQ1#_R
CLK_PCIE_WLAN1_R
CLK_PCIE_WLAN1#_R
PCH_GPIO45
PCIE_CLK_8N
PCIE_CLK_8P
PCH_SML0CLK
PCH_SML0DATA
PCH_SML0DATA
PCH_SML0CLK
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
PCIE_PRX_DTX_N1<27>
PCIE_PTX_C_DRX_N1<27>
PCIE_PRX_DTX_P1<27>
PCIE_PTX_C_DRX_P1<27>
PCIE_PRX_DTX_N2<26>
PCIE_PRX_DTX_P2<26>
PCIE_PTX_C_DRX_N2<26>
PCIE_PTX_C_DRX_P2<26>
CLK_PCI_LPBACK <18>
DRAMRST_CNTRL_PC H <7>
EC_SMB_CK2 <29,32>
EC_SMB_DA2 <29,32>
EC_LID_OUT# <32>
CLK_PCI_DB <26>
SMB_DATA_S3 <12,13,26>
SMB_CLK_S3 <12,13,26>
CLK_PCIE_LAN<27>
CLK_PCIE_LAN#<27>
CLKREQ_LAN#<27>
CLK_PCIE_WLAN1<26>
CLK_PCIE_WLAN1#<26>
WLAN_CLKREQ1#<26>
+1.05VS_VCCDIFFCLKN
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW +3VS
+3VS
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VS
+3VS
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PCH (2/8) PCIE, SMBUS, CLK
Custom
15 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PCH (2/8) PCIE, SMBUS, CLK
Custom
15 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PCH (2/8) PCIE, SMBUS, CLK
Custom
15 50Friday, November 26, 2010
2010/07/12 2012/07/11
WLAN
LAN
Compal Electronics, Inc.
Reserve for EMI please close t o PCH
Reserve for EMI please close t o PCH
Desktop Only
DIMM1
DIMM2
MINI CARD
EC
thermal sensor
VGA
LAN
WLAN
6/30 Update to @
7/5 change to 1K
7/28 reserved
7/28 reserved
8/14 change P/N to
DMN66D0LDW-7_SOT363-6
(SB00000DH00)
R169 1M_0402_5%R169 1M_040 2_5%
1 2
Y2
25MHZ_20PF_7A25000012
Y2
25MHZ_20PF_7A25000012
12
Q61B
2N7002DW-T/R7_SOT363-6
Q61B
2N7002DW-T/R7_SOT363-6
3
5
4
C199
22P_0402_50V8J
@C199
22P_0402_50V8J
@
1 2
R149 0_0402_5%R149 0_0402_5%
1 2
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
U4B
COUGARPOINT_FCBGA989
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
U4B
COUGARPOINT_FCBGA989
PERN1
BG34
PERP1
BJ34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ38
PERP6
BG38
PERN7
BG40
PERP7
BJ40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_DMI2_N
BJ30
CLKIN_DMI2_P
BG30
CLKIN_DMI_N
BF18
CLKIN_DMI_P
BE18
CLKIN_DOT_96N
G24
CLKIN_DOT_96P
E24
CLKIN_SATA_N / CKSSCD_N
AK7
CLKIN_SATA_P / CKSSCD_P
AK5
XTAL25_IN
V47
XTAL25_OUT
V49
REFCLK14IN
K45
CLKIN_PCILOOPBACK
H45
CLKOUT_PEG_A_N
AB37
CLKOUT_PEG_A_P
AB38
PEG_A_CLKRQ# / GPIO47
M10
PCIECLKRQ0# / GPIO73
J2
PCIECLKRQ1# / GPIO18
M1
PCIECLKRQ2# / GPIO20
V10
PCIECLKRQ3# / GPIO25
A8
PCIECLKRQ4# / GPIO26
L12
PCIECLKRQ5# / GPIO44
L14
CLKOUTFLEX0 / GPIO64
K43
CLKOUTFLEX1 / GPIO65
F47
CLKOUTFLEX2 / GPIO66
H47
CLKOUTFLEX3 / GPIO67
K49
CLKOUT_DMI_N
AV22
CLKOUT_DMI_P
AU22
PEG_B_CLKRQ# / GPIO56
E6
CLKOUT_PEG_B_P
AB40
CLKOUT_PEG_B_N
AB42
XCLK_RCOMP
Y47
CLKOUT_DP_P / CLKOUT_BCLK1_P
AM13
CLKOUT_DP_N / CLKOUT_BCLK1_N
AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
PCIECLKRQ7# / GPIO46
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK14
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AK13
SMBALERT# / GPIO11
E12
SMBCLK
H14
SMBDATA
C9
SML0ALERT# / GPIO60
A12
SML0CLK
C8
SML0DATA
G12
SML1ALERT# / PCHHOT# / GPIO74
C13
SML1CLK / GPIO58
E14
SML1DATA / GPIO75
M16
CL_CLK1
M7
CL_DATA1
T11
CL_RST1#
P10
PCIECLKRQ6# / GPIO45
T13
R168 10K_0402_5%R168 10K_040 2_5%
12
R171
90.9_0402_1%
R171
90.9_0402_1%
1 2
R165 10K_0402_5%R165 10K_040 2_5%
12
R150 0_0402_5%R150 0_0402_5%
1 2
C192 0.1U_0402_10V7KC192 0.1U_0402_10V7K
1 2
R162 10K_0402_5%R162 10K_040 2_5%
1 2
R138
2.2K_0402_5%
R138
2.2K_0402_5%
1 2
R136
2.2K_0402_5%
R136
2.2K_0402_5%
1 2
R157 10K_0402_5%R157 10K_040 2_5%
1 2
R167 10K_0402_5%R167 10K_040 2_5%
1 2
R141
2.2K_0402_5%
R141
2.2K_0402_5%
1 2
R160 10K_0402_5%R160 10K_040 2_5%
1 2
R152 10K_0402_5%R152 10K_040 2_5%
12
R163 10K_0402_5%R163 10K_040 2_5%
1 2
R147 10K_0402_5%R147 10K_040 2_5%
12
R137
2.2K_0402_5%
R137
2.2K_0402_5%
1 2
R139
1K_0402_5%
R139
1K_0402_5%
12
R155 10K_0402_5%R155 10K_040 2_5%
1 2
C195 0.1U_0402_10V7KC195 0.1U_0402_10V7K
1 2
R142
2.2K_0402_5%
R142
2.2K_0402_5%
1 2
R159 10K_0402_5%R159 10K_040 2_5%
1 2
Q60A
2N7002DW-T/R7_SOT363-6
Q60A
2N7002DW-T/R7_SOT363-6
6 1
2
R158 10K_0402_5%R158 10K_040 2_5%
12
C196
27P_0402_50V8J
C196
27P_0402_50V8J
1
2
R156 0_0402_5%R156 0_0402_5%
1 2
R347 10K_0402_5%
@
R347 10K_0402_5%
@
1 2
R170 10K_0402_5%R170 10K_040 2_5%
12
C198
22P_0402_50V8J
@C198
22P_0402_50V8J
@
1 2
R301 10K_0402_5%R301 10K_040 2_5%
12
R175
33_0402_5%
@R175
33_0402_5%
@
12
R135
2.2K_0402_5%
R135
2.2K_0402_5%
1 2
C197
27P_0402_50V8J
C197
27P_0402_50V8J
1
2
R153 0_0402_5%R153 0_0402_5%
1 2
R174 10K_0402_5%R174 10K_040 2_5%
12
R349 10K_0402_5%
@
R349 10K_0402_5%
@
1 2
R164 10K_0402_5%R164 10K_040 2_5%
1 2
R172 10K_0402_5%R172 10K_040 2_5%
12
R154 0_0402_5%R154 0_0402_5%
1 2
Q61A
2N7002DW-T/R7_SOT363-6
Q61A
2N7002DW-T/R7_SOT363-6
6 1
2
Q60B
2N7002DW-T/R7_SOT363-6
Q60B
2N7002DW-T/R7_SOT363-6
3
5
4
R166 10K_0402_5%R166 10K_040 2_5%
1 2
R140
10K_0402_5%
R140
10K_0402_5%
12
R151 0_0402_5%R151 0_0402_5%
1 2
R134
10K_0402_5%
R134
10K_0402_5%
12
R173
22_0402_5%
@
R173
22_0402_5%
@
1 2
R544
2.2K_0402_5%
R544
2.2K_0402_5%
1 2
C194 0.1U_0402_10V7KC194 0.1U_0402_10V7K
1 2
R143
10K_0402_5%
R143
10K_0402_5%
1 2
R176
33_0402_5%
@R176
33_0402_5%
@
12
C193 0.1U_0402_10V7KC193 0.1U_0402_10V7K
1 2
R545
2.2K_0402_5%
R545
2.2K_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_IRCOMP
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CRX_PTX_N2
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_P2
DMI_CTX_PRX_N1
DMI_CRX_PTX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CRX_PTX_N3
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC1
FDI_LSYNC0
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P5
PCH_GPIO72
RI#
SUSACK#
RBIAS_CPY
APWROK
PM_DRAM_PWR GD
PCH_RSMRST#_R
PBTN_OUT#_R
ACIN_R
DSWODVREN
WAKE#
PCH_RSMRST#_R
PCH_DPWROK_R
SLP_S5#
SLP_S4#
PM_SLP_SUS#
SUS_STAT#
H_PM_SYNC
SUSCLK
PCH_POK_R
SYS_RST#
SUSWARN#
PCH_RSMRST#_R
ACIN_R
SYS_PWROK
PM_DRAM_PWR GD
SYS_PWROK
SYS_PWROK
VGATE
PCH_POK
SUSWARN#_R SLP_S3#
PM_CLKRUN#
PCH_POK_R APWROK
SYS_PWROKPCH_POK_R
PM_DRAM_PWR GD
DMI_CTX_PRX_N0<5>
DMI_CRX_PTX_N2<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P3<5>
DMI_CTX_PRX_P2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P0<5>
FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>
FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>
FDI_FSYNC1 <5>
FDI_LSYNC0 <5>
FDI_FSYNC0 <5>
FDI_INT <5>
FDI_LSYNC1 <5>
PM_DRAM_PWR GD<6>
PBTN_OUT#<32>
PCH_DPWROK <32>
PCIE_WAKE# <26,27>
H_PM_SYNC <6>
SLP_S3# <32>
SLP_S4# <32>
SLP_S5# <32>
EC_RSMRST#<32>
SUSWARN#<32>
SUSCLK <32>
PCH_APWROK<32>
ACIN<32,47>
VGATE<53>
PCH_POK<6,32>
SYS_PWROK_EC<32>
SYS_PWROK <6>
+1.05VS_PCH
+3VALW
+3VS
+3VS
+3VALW
+3VALW
+3VS
+RTCVCC
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PCH (3/8) DMI,FDI,PM,
Custom
16 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PCH (3/8) DMI,FDI,PM,
Custom
16 50Friday, November 26, 2010
2010/07/12 2012/07/11
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COM PAL ELECTRONICS, INC. AND CONTAIN S CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFER ED FROM THE CUSTOD Y OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCE PT AS AUTHORIZED BY COMPAL ELECTR ONICS, INC. NEITHER THIS SHEET NOR T HE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-6752P
0.2
PCH (3/8) DMI,FDI,PM,
Custom
16 50Friday, November 26, 2010
2010/07/12 2012/07/11
4mil width and place
within 500mil of the PCH
Can be left NC
when IAMT is no t
support on the
platfrom
Compal Electronics, Inc.
AEPWROK can be connect to
PWROK if iAMT d isable
SUSACK# is only used on platfo rm
that support th e Deep Sx state .
Can be left NC if no use
integrated LAN.
*
DSWODVREN - On Die DSW VR Enab le
H
：
Enable
L
：
Disable
7/22 modify
7/22 modify
7/28 modify
7/28 Updat e
*
7/28 Deful t use AND Gate
7/28 Modify follow CRB & ORB
R193 0_0402_5%R193 0_0402_5%
1 2
R184 10K_0402_5%R184 10K_0402_5%
12
R742
0_0402_5%
@
R742
0_0402_5%
@
1 2
R189
8.2K_0402_5%
R189
8.2K_0402_5%
1 2
R302 0_0402_5%R302 0_0402_5%
1 2
U6
MC74VHC1G08DFT2G SC70 5P
U6
MC74VHC1G08DFT2G SC70 5P
B
2
A
1
Y
4
P
5
G
3
R1820_0402_5% R1820_0402_5%
1 2
R201
10K_0402_5%
R201
10K_0402_5%
12
R185
0_0402_5%
R185
0_0402_5%
1 2
R191
0_0402_5% @
R191
0_0402_5% @
1 2
R194 10K_0402_5%R194 10K_0402_5%
12
R546 200_0402_5%R546 200_0402_5%
12
T72 PADT72 PAD
R188 0_0402_5%@R188 0_0402_5%@
1 2
R180 100K_0402_1%R180 100K_0402_1%
12
R197 10K_0402_5%R197 10K_0402_5%
12
R192 200_0402_5%
@
R192 200_0402_5%
@
12
R743
0_0402_5%
@
R743
0_0402_5%
@
1 2
D29
CH751H-40PT_SOD323-2
D29
CH751H-40PT_SOD323-2
21
R196 0_0402_5%R196 0_0402_5%
1 2
R190 0_0402_5%R190 0_0402_5%
1 2
R1810_0402_5% @R1810_0402_5% @
1 2
R195
200K_0402_1%
R195
200K_0402_1%
12
R179
330K_0402_5%
R179
330K_0402_5%
12
R186
10K_0402_5%
R186
10K_0402_5%
1 2
R199 0_0402_5%@R199 0_0402_5%@
1 2
DMI
FDI
System Power Management
U4C
COUGARPOINT_FCBGA989
DMI
FDI
System Power Management
U4C
COUGARPOINT_FCBGA989
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ18
DMI3RXP
BJ20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ24
DMI_IRCOMP
BG25
FDI_RXN0
BJ14
FDI_RXN1
AY14
FDI_RXN2
BE14
FDI_RXN3
BH13
FDI_RXN4
BC12
FDI_RXN5
BJ12
FDI_RXN6
BG10
FDI_RXN7
BG9
FDI_RXP0
BG14
FDI_RXP1
BB14
FDI_RXP2
BF14
FDI_RXP3
BG13
FDI_RXP4
BE12
FDI_RXP5
BG12
FDI_RXP6
BJ10
FDI_RXP7
BH9
FDI_FSYNC0
AV12
FDI_FSYNC1
BC10
FDI_LSYNC0
AV14
FDI_LSYNC1
BB10
FDI_INT
AW16
PMSYNCH
AP14
SLP_SUS#
G16
SLP_S3#
F4
SLP_S4#
H4
SLP_S5# / GPIO63
D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE#
B9
SUS_STAT# / GPIO61
G8
SUSCLK / GPIO62
N14
ACPRESENT / GPIO31
H20
BATLOW# / GPIO72
E10
PWROK
L22
CLKRUN# / GPIO32
N3
SUSWARN# / SUS_PW R_DN_ACK / GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN# / GPIO29
K14
APWROK
L10
DPWROK
E22
DMI2RBIAS
BH21
SLP_A#
G10
DSWVRMEN
A18
SUSACK#
C12
R177 49.9_0402_1%R177 49.9_0402_1%
1 2
T73PAD T73PAD
R200
8.2K_0402_5%
R200
8.2K_0402_5%
1 2
R183
330K_0402_5%
@
R183
330K_0402_5%
@
12
R178 750_0402_1%R178 750_0402_1%
1 2
R198 0_0402_5%R198 0_0402_5%
1 2
T66 PAD@T66 PAD@
T71PAD T71PAD
Loading...