LA-8971P VITU5
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A
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B
C
C
D
D
E
E
1 1
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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
Cover Page
Custom
1 58Thursday, February 16, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
Cover Page
Custom
1 58Thursday, February 16, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
Cover Page
Custom
1 58Thursday, February 16, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Intel Ivy Bridge ULV Processor + Panther Point PCH(HM77)
VITU5 M/B Schematics Document
REV:0.1
Compal Confidential
2012-02-16
Nvidia chip:N13M-GS(23x23)
Model Name : VITU5
File Name : LA-8971P
Compal Confidential
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
MB Block Diagram
Custom
2 58Wednesday, February 15, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
LA-8971P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
MB Block Diagram
Custom
2 58Wednesday, February 15, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
LA-8971P
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.2
MB Block Diagram
Custom
2 58Wednesday, February 15, 2012
2011/07/21 2012/12/31
Compal Electronics, Inc.
LA-8971P
File Name :LA-8971P
Compal confidential
SPI ROM
BIOS
Std HDMI
USB PORT 3.0 x1 (Left)
25mm*25mm
SATA3.0 HDD CONN
6*PCI-E x1
PCI Express (Half)
Mini card Slot 1
FDI *8
100MHz
2.7GT/s
Intel
6*SATA
Single Digital MIC
PCI-E X16
LED BOARD
BlueTooth CONN
CMOS Camera
RealTek
ALC259-VC2-CG
Audio Codec
2Channel Speaker
LPC BUS
HD Audio
Int.KBD
ENE KB9012
Touch Pad
DDR3-1333/1600
14*USB2.0
LVDS
Connector
EC
IVY Bridge ULV
(Sandy Bridge)
BGA1023
DMI2 *4
FCBGA 989 Balls
Intel
Panther Point
Connector
NV N13M-GS
VRAM 128*16
DDR3*4
Audio Combo Jack
(APPLE type)
HeadPhone Output
Microphone Input
(port0,1 Support SATA3)
LAN(10/100/Giga)
RJ45 CONN
Thermal Sensor
WLAN/WiMAX
PCI-E(WLAN)
100MHz
5GT/s
Gen 2
Processor
Sub-borad
IO Board
Chief River
4*USB3.0
USB PORT 2.0 x2 (Right)
Card Reader RTS 5178 (2in1)
Realtek
8105E-VD (10/100)
8111F-CGT (Giga)
POWER BOARD
4MB*1
2MB*1
23mm *23mm
IO Board
IO Board
HM77
USB2.0*2,card reader
Mini VGA
Connector
PCI Express (Full)
Mini card Slot 2
SSD(SATA3.0)
ODD (SATA2.0)
DDR3-SO-DIMM X2
Dual Channel
ODD Board
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-7981P
0.2
Notes List
B
3 58Wednesday, February 15, 2012
2011/06/15 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-7981P
0.2
Notes List
B
3 58Wednesday, February 15, 2012
2011/06/15 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-7981P
0.2
Notes List
B
3 58Wednesday, February 15, 2012
2011/06/15 2012/07/11
Compal Electronics, Inc.
USB 2.0 Port
3 External
USB Port
USB 3.0 Port (Left Side)
Camera
Blue Tooth
0
1
2
3
4
5
6
7
8
9
10
11
12
13
UHCI0
UHCI1
UHCI2
UHCI3
UHCI4
UHCI5
UHCI6
EHCI1
EHCI2
USB Port Table
Board ID / SKU ID Table for AD channelBOARD ID Table
EC SM Bus1 address
Device
DDR DIMM0
1001 000Xb
DDR DIMM2
1001 010Xb
STATE
SIGNAL
Full ON
S1(Power On Suspend)
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF)
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID
V typ
AD_BID
V
AD_BID
max
18K +/- 5%
33K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V
0 V
4
5
6
7 NC
1.036 V
1.453 V
1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID
0
1
2
3
4
5
6
7
PCB Revision
0.1
PCH SM Bus address
Device Address
Address
Address
Voltage Rails
Unpop
BTO Item BOM Structure
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW LOW LOW LOW
LOWLOWLOW
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
EC SM Bus2 address
Device
Smart Battery
0001 011X b
Blue Tooth BT@
Connector ME@
@
USB/B (Right Side USB-BD)
Mini Card(WLAN)
X
V
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VS
XX
V
V
X
XX
PCH
Thermal
Sensor
X
X
X
SML0CLK
SML0DATA
PCH
SMB_EC_CK2
SOURCE
KB9012
VGA BATT KB9012 SODIMM
SMBUS Control Table
SMBCLK
SMBDATA
PCH
WLAN
WWAN
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
X V
V
X
X
X
X
X
X
X
X
X
X
X
X
X
KB9012
SML1CLK
SML1DATA
PCH
XX X
X
X
USB Port (Right Side CR-BD)
V
+3VS
+3VS
+3VS
+3VS
V
+3VS
Interna-Intel-USB3.0 IU3@
O
X
S3
+3VS
X
X
+3VALW
+5VS
O
+VCC_CORE
OO
X
X X
+V1.05S_VCCP
power
plane
O
O
O
O
X
S5 S4/ Battery only
X X X
+B
State
+1.5VS
+1.5V
S5 S4/AC & Battery
don't exist
S5 S4/AC
+5VALW
S0
O
O
+VCC_GFXCORE_AXG
+1.8VS
+0.75VS
+1.05VS
+VGA_CORE
HDMI HDMI@
BOM Structure Table
EVT
DVT
PVT
MP
45 LEVEL 45@
10/100 LAN 8105E@
GIGA LAN 8111F@
Thermal Sensor F75303M
1001_101xb
XTX@ GPU:Seymour XTX
MP
EVT
DVT
PVT
Porject Phase
G-series
G-series
G-series
G-series
Y-series
Y-series
Y-series
Y-series
AMD-GPU SM Bus address
Device Address
Internal thermal sensor
1001 111Xb (0x9E)
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
X (USB PORT disabled on HM70 )
Interna-Intel-USB2.0 IU2@
HDD2 (HM70 SATA 2.0) HDD2@
HDD1 (HM77 SATA 3.0) HDD1@
INTEL UMA only UMA@
USB 3.0
xHCI1
xHCI2
xHCI3
xHCI4
HM70 Disable xHCI3,xHCI4
HM70 Disable P1,P3
HM77
SATA Port Table
SATA P0
SSD
SATA P1
SATA P2
SATA P3
SATA P5
SATA P4
HM70
GEN3/2/1
DisableGEN3/2/1
GEN3/2/1
GEN2/1
GEN2/1
GEN2/1
GEN2/1
GEN2/1
GEN2/1
GEN2/1
Disable
HDD (HM77)
HDD (HM70)
HM77
PCIe Port Table
LAN
PCIe P1
PCIe P2
PCIe P3
PCIe P5
PCIe P4
HM70
Enable
HM70 Disable P5,P6,P7,P8
PCIe P6
PCIe P7
PCIe P8
Enable
Enable
Enable
Enable
Enable
Enable
Enable
Disable
Enable
Enable
Enable
Enable
Disable
Disable
Disable
WLAN
USB/B (Right Side USB-BD)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-7981P
0.2
VGA Notes List
Custom
4 58Wednesday, February 15, 2012
2011/06/15 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-7981P
0.2
VGA Notes List
Custom
4 58Wednesday, February 15, 2012
2011/06/15 2012/07/11
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-7981P
0.2
VGA Notes List
Custom
4 58Wednesday, February 15, 2012
2011/06/15 2012/07/11
Compal Electronics, Inc.
32Mx32 PD 15K
PD 15K PD 35KPU 20KPD 10K PD 20K PU 45K
PD 15K PD 35KPU 20KPD 10K PD 20K PU 45K64Mx32
64Mx32
K4G20325FG-HC04
H5GQ2H24MFR-T2CHynix
2500MHz
Samsung
2500MHz
1.all GPU power rails should be turned off within 10ms
OUT GPU VID4-
Tpower-off <10ms
GPU VID0-OUT
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
+3VS_VGA
FB[1]
3GIO_PAD_CFG_ADR[0]
USER[2] USER[1] USER[0]USER[3]
3GIO_PAD_CFG_ADR[2] 3GIO_PAD_CFG_ADR[1]3GIO_PAD_CFG_ADR[3]
PCI_DEVID[3] PCI_DEVID[2] PCI_DEVID[1] PCI_DEVID[0]
STRAP3
STRAP4
+3VS_VGA
+3VS_VGA
SOR3_EXPOSED
RESERVED PCIE_SPEED_
CHANGE_GEN3
PCIE_MAX_SPEED DP_PLL_VDD33V
SOR2_EXPOSED SOR1_EXPOSED
Power Rail
+3VS_VGA
ROM_SCLK
SOR0_EXPOSED
Logical
Strapping Bit3
Logical
Strapping Bit2
SLOT_CLK_CFG
Logical
Strapping Bit0
SUB_VENDOR
PEX_PLL_EN_TERM
RAM_CFG[0]
STRAP0
STRAP1
STRAP2
ROM_SI
RAM_CFG[1]RAM_CFG[3] RAM_CFG[2]
VGA_DEVICESMB_ALT_ADDR
PCI_DEVID[4]
ROM_SO FB[0]
Logical
Strapping Bit1
Physical
Strapping pin
N13P-GL
(28nm)
???
Device ID
N13M-GE
(28nm)
???
TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
+1.5VS_VGA
1. all power rail ramp up time should be larger than 40us
2. Optimus system VDD33 avoids drop down earlier than NVDD and FBVDDQ
+3VS_VGA
+1.05VS_VGA
+VGA_CORE
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
OUT
OUT
OUT
OUT
OUT
OUT
I/O
OUT
OUT
IN
OUT
OUT
Panel Back-Light brightness(PWM capable)
Panel Power Enable
Panel Back-Light On/Off (PWM)
GPU VID1
GPU VID2
-
H
H
H
GPIO I/O ACTIVE Function Description
-
-
IN
OUT
IN
IN
IN
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
VGA and GDDR3 Voltage Rails (N13x GPIO)
N/A
(10K pull low)
N/A
N/A
Thermal Catastrophic Over Temperature
Thermal Alert
Memory VREF Control
AC Power Detect Input
N/A
Hot Plug Detect for IFPE
N/A
-
-
-
Products
GPU Mem NVCLK
/MCLK NVVDD
FBVDD
FBVDDQ PCI Express I/O and
PLLVDD
I/O and
PLLVDD
Other
(3.3V)(1.05V)(1.8V)
(1.05V)
(1.35V)(1.35V)
(GPU+Mem)
(4) (1,5) (6)
(V) (A) (W) (A) (W)
Performance Mode P0 TDP at Tj = 102 C* (GDDR3)
(A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
N13P-GL
64bit
1GB
GDDR3
(W) (W) (MHz)
TBD TBD
Hot plug detect for IFP link C
GPU VID3OUT
Hot plug detect for IFP link C
GPU VID5-
tFBVDDQ >0
tNVVDD >0
tPEX_VDD >0
X76
H5GQ1H24BFR-T2C
K4G10325FG-HC04
N13P-GL
N13M-GE
PD 35K
PD 10K
PU 20K
ROM_SO
PD 15K
PD 15K
ROM_SCLK ROM_SI
PD 35K
Samsung
2500MHz
GPU STRAP2 STRAP1 STRAP0
PD 20KPD 10K PU 45K
FB Memory (GDDR3)
PU 45K
PU 20K
Hynix
2500MHz
32Mx32
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
FDI_CTX_PRX_N1
FDI_CTX_PRX_N4
FDI_CTX_PRX_N6
FDI_CTX_PRX_P1
FDI_CTX_PRX_P6
FDI_FSYNC0
DMI_CTX_PRX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CTX_PRX_N2
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N0
FDI_CTX_PRX_N0
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N5
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P7
FDI_LSYNC0
FDI_LSYNC1
FDI_FSYNC1
FDI_INT
DMI_CTX_PRX_N3
PEG_COMP
EDP_COMP
PEG_GTX_HRX_N8
PEG_GTX_HRX_N12
PEG_GTX_HRX_N10
PEG_GTX_HRX_N11
PEG_GTX_HRX_N9
PEG_GTX_HRX_N13
PEG_GTX_HRX_N14
PEG_GTX_HRX_N15PEG_GTX_C_HRX_N15
PEG_GTX_C_HRX_N14
PEG_GTX_C_HRX_N13
PEG_GTX_C_HRX_N12
PEG_GTX_C_HRX_N11
PEG_GTX_C_HRX_N10
PEG_GTX_C_HRX_N9
PEG_GTX_C_HRX_N8
PEG_GTX_HRX_P8
PEG_GTX_HRX_P9
PEG_GTX_HRX_P10
PEG_GTX_HRX_P11
PEG_GTX_HRX_P12
PEG_GTX_HRX_P13
PEG_GTX_HRX_P14
PEG_GTX_HRX_P15PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_P8
PEG_HTX_C_GRX_N8
PEG_HTX_C_GRX_N9
PEG_HTX_C_GRX_N10
PEG_HTX_C_GRX_N11
PEG_HTX_C_GRX_N12
PEG_HTX_C_GRX_N13
PEG_HTX_C_GRX_N14
PEG_HTX_C_GRX_N15PEG_HTX_GRX_N15
PEG_HTX_GRX_N14
PEG_HTX_GRX_N13
PEG_HTX_GRX_N12
PEG_HTX_GRX_N11
PEG_HTX_GRX_N10
PEG_HTX_GRX_N9
PEG_HTX_GRX_N8
PEG_HTX_C_GRX_P8
PEG_HTX_C_GRX_P9
PEG_HTX_C_GRX_P10
PEG_HTX_C_GRX_P11
PEG_HTX_C_GRX_P12
PEG_HTX_C_GRX_P13
PEG_HTX_C_GRX_P14
PEG_HTX_C_GRX_P15PEG_HTX_GRX_P15
PEG_HTX_GRX_P14
PEG_HTX_GRX_P13
PEG_HTX_GRX_P12
PEG_HTX_GRX_P11
PEG_HTX_GRX_P10
PEG_HTX_GRX_P9
PEG_HTX_GRX_P8
DMI_CTX_PRX_P0<16>
DMI_CRX_PTX_P0<16>
DMI_CTX_PRX_N1<16>
DMI_CRX_PTX_N1<16>
DMI_CTX_PRX_P3<16>
DMI_CRX_PTX_P3<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_N0<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P1<16>
DMI_CRX_PTX_N0<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_P1<16>
DMI_CTX_PRX_N2<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P3<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P6<16>
FDI_CTX_PRX_P7<16>
FDI_FSYNC0<16>
FDI_FSYNC1<16>
FDI_INT<16>
FDI_LSYNC0<16>
FDI_LSYNC1<16>
PEG_GTX_HRX_N[8..15] <23>
PEG_HTX_C_GRX_P[8..15] <23>
PEG_HTX_C_GRX_N[8..15] <23>
PEG_GTX_HRX_P[8..15] <23>
+1.05VS_VTT
+1.05VS_VTT
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(1/7) DMI,FDI,PEG
Custom
5 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(1/7) DMI,FDI,PEG
Custom
5 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(1/7) DMI,FDI,PEG
Custom
5 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
PEG_ICOMPI and RCOMPO signals should be
shorted and routed
with - max length = 500 mils - typical
impedance = 43 mohms
PEG_ICOMPO signals should be routed with -
max length = 500 mils
- typical impedance = 14.5 mohms
Typ- suggest 220nF. The change in AC capacitor
value from 100nF to 220nF is to enable
compatibility with future platforms having PCIE
Gen3 (8GT/s)
eDP_COMPIO and ICOMPO signals
should be shorted near balls and
routed with typical impedance
<25 mohms
can't be left floating
,even if disable eDP function...
W=12mil L=500mil S=15mil
W=12mil L=500mil S=15mil
PCI EXPRESS -- GRAPHICS
DMI Intel(R) FDI
eDP
UCPU1A
IVY-BRIDGE_BGA1023
PCI EXPRESS -- GRAPHICS
DMI Intel(R) FDI
eDP
UCPU1A
IVY-BRIDGE_BGA1023
DMI_RX#[0]
M2
DMI_RX#[1]
P6
DMI_RX#[2]
P1
DMI_RX#[3]
P10
DMI_RX[0]
N3
DMI_RX[1]
P7
DMI_RX[2]
P3
DMI_RX[3]
P11
DMI_TX#[0]
K1
DMI_TX#[1]
M8
DMI_TX#[2]
N4
DMI_TX#[3]
R2
DMI_TX[0]
K3
DMI_TX[1]
M7
DMI_TX[3]
T3
DMI_TX[2]
P4
FDI0_TX#[0]
U7
FDI0_TX#[1]
W11
FDI0_TX#[2]
W1
FDI0_TX#[3]
AA6
FDI1_TX#[0]
W6
FDI1_TX#[1]
V4
FDI1_TX#[2]
Y2
FDI1_TX#[3]
AC9
FDI0_TX[0]
U6
FDI0_TX[1]
W10
FDI0_TX[2]
W3
FDI0_TX[3]
AA7
FDI1_TX[0]
W7
FDI1_TX[1]
T4
FDI1_TX[2]
AA3
FDI1_TX[3]
AC8
FDI0_FSYNC
AA11
FDI1_FSYNC
AC12
FDI_INT
U11
FDI0_LSYNC
AA10
FDI1_LSYNC
AG8
PEG_ICOMPI
G3
PEG_ICOMPO
G1
PEG_RCOMPO
G4
PEG_RX#[0]
H22
PEG_RX#[1]
J21
PEG_RX#[2]
B22
PEG_RX#[3]
D21
PEG_RX#[4]
A19
PEG_RX#[5]
D17
PEG_RX#[6]
B14
PEG_RX#[7]
D13
PEG_RX#[8]
A11
PEG_RX#[9]
B10
PEG_RX#[10]
G8
PEG_RX#[11]
A8
PEG_RX#[12]
B6
PEG_RX#[13]
H8
PEG_RX#[14]
E5
PEG_RX#[15]
K7
PEG_RX[0]
K22
PEG_RX[1]
K19
PEG_RX[2]
C21
PEG_RX[3]
D19
PEG_RX[4]
C19
PEG_RX[5]
D16
PEG_RX[6]
C13
PEG_RX[7]
D12
PEG_RX[8]
C11
PEG_RX[9]
C9
PEG_RX[10]
F8
PEG_RX[11]
C8
PEG_RX[12]
C5
PEG_RX[13]
H6
PEG_RX[14]
F6
PEG_RX[15]
K6
PEG_TX#[0]
G22
PEG_TX#[1]
C23
PEG_TX#[2]
D23
PEG_TX#[3]
F21
PEG_TX#[4]
H19
PEG_TX#[5]
C17
PEG_TX#[6]
K15
PEG_TX#[7]
F17
PEG_TX#[8]
F14
PEG_TX#[9]
A15
PEG_TX#[10]
J14
PEG_TX#[11]
H13
PEG_TX#[12]
M10
PEG_TX#[13]
F10
PEG_TX#[14]
D9
PEG_TX#[15]
J4
PEG_TX[0]
F22
PEG_TX[1]
A23
PEG_TX[2]
D24
PEG_TX[3]
E21
PEG_TX[4]
G19
PEG_TX[5]
B18
PEG_TX[6]
K17
PEG_TX[7]
G17
PEG_TX[8]
E14
PEG_TX[9]
C15
PEG_TX[10]
K13
PEG_TX[11]
G13
PEG_TX[12]
K10
PEG_TX[13]
G10
PEG_TX[14]
D8
PEG_TX[15]
K4
eDP_AUX
AF4
eDP_AUX#
AG4
eDP_TX[0]
AC1
eDP_TX[1]
AA4
eDP_TX[2]
AE10
eDP_TX[3]
AE6
eDP_COMPIO
AF3
eDP_HPD#
AG11
eDP_ICOMPO
AD2
eDP_TX#[0]
AC3
eDP_TX#[1]
AC4
eDP_TX#[2]
AE11
eDP_TX#[3]
AE7
C582 0.22U_0402_6.3V6KOPT@C582 0.22U_0402_6.3V6KOPT@
1 2
C587 0.22U_0402_6.3V6KOPT@C587 0.22U_0402_6.3V6KOPT@
1 2
C272 0.22U_0402_6.3V6KOPT@C272 0.22U_0402_6.3V6KOPT@
1 2
C568 0.22U_0402_6.3V6KOPT@C568 0.22U_0402_6.3V6KOPT@
1 2
C256 0.22U_0402_6.3V6KOPT@C256 0.22U_0402_6.3V6KOPT@
1 2
C567 0.22U_0402_6.3V6KOPT@C567 0.22U_0402_6.3V6KOPT@
1 2
C564 0.22U_0402_6.3V6KOPT@C564 0.22U_0402_6.3V6KOPT@
1 2
C253 0.22U_0402_6.3V6KOPT@C253 0.22U_0402_6.3V6KOPT@
1 2
C585 0.22U_0402_6.3V6KOPT@C585 0.22U_0402_6.3V6KOPT@
1 2
C566 0.22U_0402_6.3V6KOPT@C566 0.22U_0402_6.3V6KOPT@
1 2
R247
24.9_0402_1%
R247
24.9_0402_1%
12
C259 0.22U_0402_6.3V6KOPT@C259 0.22U_0402_6.3V6KOPT@
1 2
C258 0.22U_0402_6.3V6KOPT@C258 0.22U_0402_6.3V6KOPT@
1 2
C274 0.22U_0402_6.3V6KOPT@C274 0.22U_0402_6.3V6KOPT@
1 2
C563 0.22U_0402_6.3V6KOPT@C563 0.22U_0402_6.3V6KOPT@
1 2
C586 0.22U_0402_6.3V6KOPT@C586 0.22U_0402_6.3V6KOPT@
1 2
C276 0.22U_0402_6.3V6KOPT@C276 0.22U_0402_6.3V6KOPT@
1 2
C562 0.22U_0402_6.3V6KOPT@C562 0.22U_0402_6.3V6KOPT@
1 2
C273 0.22U_0402_6.3V6KOPT@C273 0.22U_0402_6.3V6KOPT@
1 2
C255 0.22U_0402_6.3V6KOPT@C255 0.22U_0402_6.3V6KOPT@
1 2
C583 0.22U_0402_6.3V6KOPT@C583 0.22U_0402_6.3V6KOPT@
1 2
C561 0.22U_0402_6.3V6KOPT@C561 0.22U_0402_6.3V6KOPT@
1 2
C252 0.22U_0402_6.3V6KOPT@C252 0.22U_0402_6.3V6KOPT@
1 2
C254 0.22U_0402_6.3V6KOPT@C254 0.22U_0402_6.3V6KOPT@
1 2
C589 0.22U_0402_6.3V6KOPT@C589 0.22U_0402_6.3V6KOPT@
1 2
C275 0.22U_0402_6.3V6KOPT@C275 0.22U_0402_6.3V6KOPT@
1 2
C565 0.22U_0402_6.3V6KOPT@C565 0.22U_0402_6.3V6KOPT@
1 2
C271 0.22U_0402_6.3V6KOPT@C271 0.22U_0402_6.3V6KOPT@
1 2
C270 0.22U_0402_6.3V6KOPT@C270 0.22U_0402_6.3V6KOPT@
1 2
C257 0.22U_0402_6.3V6KOPT@C257 0.22U_0402_6.3V6KOPT@
1 2
R249
24.9_0402_1%
R249
24.9_0402_1%
12
C277 0.22U_0402_6.3V6KOPT@C277 0.22U_0402_6.3V6KOPT@
1 2
C588 0.22U_0402_6.3V6KOPT@C588 0.22U_0402_6.3V6KOPT@
1 2
C584 0.22U_0402_6.3V6KOPT@C584 0.22U_0402_6.3V6KOPT@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
XDP_TDI
XDP_TDO
H_CATERR#
CLK_CPU_DPLL#
CLK_CPU_DPLL
H_CPUPWRGD_RH_CPUPWRGD
H_THERMTRIP#
XDP_TCK
XDP_TMS
XDP_TRST#
XDP_DBRESET#
SM_RCOMP1
SM_RCOMP2
SM_RCOMP0
H_CPUPWRGD_R
H_PROCHOT#_RH_PROCHOT#
CLK_CPU_DMI#
CLK_CPU_DMI
H_PM_SYNC
H_PECI
XDP_DBRESET#
BUF_CPU_RST#
BUF_CPU_RST#
PM_DRAM_PWRGD
RUN_ON_CPU1.5VS3#
VDDPWRGOOD_R
H_DRAMRST#
XDP_TCK
XDP_TDI
XDP_TDO
XDP_TMS
XDP_TRST#
PCH_PLTRST#
BUFO_CPU_RST#
PM_SYS_PWRGD_BUF
SYS_PWROK
H_THERMTRIP#<19>
H_SNB_IVB#<18>
H_PROCHOT#<42,49>
CLK_CPU_DMI# <15>
CLK_CPU_DMI <15>
H_PM_SYNC<16>
H_CPUPWRGD<19>
H_PECI<19,42>
PM_DRAM_PWRGD<16>
RUN_ON_CPU1.5VS3#<10>
PCH_PLTRST# <18>
H_DRAMRST# <7>
SUSP<10,47,52>
SYS_PWROK<16>
+1.05VS_VTT
+1.05VS_VTT
+3VS
+1.5V_CPU_VDDQ
+3VALW
+1.05VS_VTT
+3VS
+3VS
+1.05VS_VTT
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(2/7) DDRIII
Custom
6 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(2/7) DDRIII
Custom
6 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(2/7) DDRIII
Custom
6 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
reserve
XBOX
PROC_SELECT#
PH VCPLL and connect to PCH DF_TVS
PCH->CPU
UNCOREPWRGOOD:
CORE
OK
SM_DRAMPWROK:DRAM power ok
RESET#:
ok
CPU
reset
DDR3 Compensation Signals
UNCOREPWRGOOD:
CORE
OK
Follow DG 1.5& Tacoma_Fall2 1.0
SM_RCOMP0,SM_RCOMP1
W=20mil L=500mil S=13mil
SM_RCOMP2
W=15mil L=500mil S=13mil
Tacoma_Fall2 1.0 PH 1K +3VS
Check list 1.5 PH 1K +3VS
Debug port DG1.1-1.3 50~5K ohm
Buffered reset to CPU
ESD
C Reserve
PU/PD for JTAG signals
R40 51_0402_5%R40 51_0402_5%
12
R292
10K_0402_5%
R292
10K_0402_5%
12
C617
0.1U_0402_16V4Z
C617
0.1U_0402_16V4Z
12
R14
0_0402_5%
@R14
0_0402_5%
@
1 2
R534
62_0402_5%
R534
62_0402_5%
1 2
R28 51_0402_5%R28 51_0402_5%
12
R39 51_0402_5%R39 51_0402_5%
12
R305
0_0402_5%
R305
0_0402_5%
1 2
R237
130_0402_1%
R237
130_0402_1%
1 2
R312 1K_0402_5%@R312 1K_0402_5%@
12
R267 200_0402_1%R267 200_0402_1%
1 2
CLOCKS
MISC THERMAL PWR MANAGEMENT
DDR3
MISC
JTAG & BPM
UCPU1B
IVY-BRIDGE_BGA1023
CLOCKS
MISC THERMAL PWR MANAGEMENT
DDR3
MISC
JTAG & BPM
UCPU1B
IVY-BRIDGE_BGA1023
SM_RCOMP[1]
BE43
SM_RCOMP[2]
BG43
SM_DRAMRST#
AT30
SM_RCOMP[0]
BF44
BCLK#
H2
BCLK
J3
DPLL_REF_CLK#
AG1
DPLL_REF_CLK
AG3
CATERR#
C49
PECI
A48
PROCHOT#
C45
THERMTRIP#
D45
SM_DRAMPWROK
BE45
RESET#
D44
PRDY#
N53
PREQ#
N55
TCK
L56
TMS
L55
TRST#
J58
TDI
M60
TDO
L59
DBR#
K58
BPM#[0]
G58
BPM#[1]
E55
BPM#[2]
E59
BPM#[3]
G55
BPM#[4]
G59
BPM#[5]
H60
BPM#[6]
J59
BPM#[7]
J61
PM_SYNC
C48
PROC_DETECT#
C57
PROC_SELECT#
F49
UNCOREPWRGOOD
B46
C43
@
0.1U_0402_16V4Z
C43
@
0.1U_0402_16V4Z
12
C228
0.1U_0402_16V4Z
C228
0.1U_0402_16V4Z
12
R37 51_0402_5%R37 51_0402_5%
12
R31 10K_0402_5%R31 10K_0402_5%
1 2
R20 51_0402_5%R20 51_0402_5%
12
R516 1K_0402_5%R516 1K_0402_5%
1 2
U22
74AHC1G09GW_TSSOP5
U22
74AHC1G09GW_TSSOP5
B
1
A
2
G
3
O
4
P
5
C82
100P_0402_50V8J
@
C82
100P_0402_50V8J
@
1
2
R35
10K_0402_5%
@R35
10K_0402_5%
@
12
R60 10K_0402_5%@R60 10K_0402_5%@
1 2
R517 1K_0402_5%R517 1K_0402_5%
12
U45
SN74LVC1G07DCKR_SC70-5
U45
SN74LVC1G07DCKR_SC70-5
NC
1
A
2
G
3
Y
4
P
5
R38
@
39_0402_5%
R38
@
39_0402_5%
12
G
D
S
Q4
2N7002K_SOT23-3
@
G
D
S
Q4
2N7002K_SOT23-3
@
2
13
R546
75_0402_5%
R546
75_0402_5%
12
R13
0_0402_5%
@R13
0_0402_5%
@
1 2
T33
PAD
@
T33
PAD
@
R273 25.5_0402_1%R273 25.5_0402_1%
1 2
R9
0_0402_5%
@R9
0_0402_5%
@
12
C614 0.1U_0402_16V4Z
@
C614 0.1U_0402_16V4Z
@
12
R272 140_0402_1%R272 140_0402_1%
1 2
R544
43_0402_5%
R544
43_0402_5%
1 2
R238
200_0402_5%
R238
200_0402_5%
12
R533
56_0402_5%
R533
56_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_A_D63
DDR_A_D62
DDR_A_D8
DDR_A_D3
DDR_A_D4
DDR_A_D7
DDR_A_D5
DDR_A_D6
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D47
DDR_A_D46
DDR_A_D42
DDR_A_D43
DDR_A_D34
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_D38
DDR_A_D36
DDR_A_D37
DDR_A_D32
DDR_A_D33
DDR_A_D61
DDR_A_D60
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_D55
DDR_A_D54
DDR_A_D51
DDR_A_D48
DDR_A_D50
DDR_A_D49
DDR_A_D52
DDR_A_D53
DDR_A_D31
DDR_A_D14
DDR_A_D15
DDR_A_D25
DDR_A_D24
DDR_A_D26
DDR_A_D27
DDR_A_D30
DDR_A_D9
DDR_A_D13
DDR_A_D12
DDR_A_D10
DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_D19
DDR_A_D20
DDR_A_D16
DDR_A_D21
DDR_A_D17
DDR_A_D22
DDR_A_D18
DDR_A_D23
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE# DDR_A_MA15
DDR_A_MA0
DDR_A_MA14
DDR_A_MA5
DDR_A_MA4
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA9
DDR_A_MA7
DDR_A_MA6
DDR_A_MA12
DDR_A_MA13
DDR_A_MA8
DDR_A_MA11
DDR_A_MA10
SM_DRAMRST#_R
DDR_A_DQS#7
DDR_A_DQS#0
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#3
DDR_A_DQS#1
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS1
DDR_A_DQS6
DDR_A_DQS5
DDR_A_DQS4
DDR_A_DQS3
DDR_A_DQS7
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE1_DIMMA
DDR_CS0_DIMMA#
DDR_CS1_DIMMA#
M_ODT0
M_ODT1
M_CLK_DDR0
DDR_CKE0_DIMMA
M_CLK_DDR#0
DRAMRST_CNTRL_PCH
M_CLK_DDR2
DDR_CKE2_DIMMB
M_CLK_DDR#2
M_CLK_DDR3
M_CLK_DDR#3
DDR_CKE3_DIMMB
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
M_ODT2
M_ODT3
DDR_B_DQS#1
DDR_B_DQS#7
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS#0
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS6
DDR_B_MA15
DDR_B_MA0
DDR_B_MA9
DDR_B_MA7
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_B_MA11
DDR_B_MA3
DDR_B_MA5
DDR_B_MA6
DDR_B_MA10
DDR_B_MA8
DDR_B_MA1
DDR_B_MA12
DDR_B_MA14
DDR_B_BS0
DDR_B_BS1
DDR_B_BS2
DDR_B_CAS#
DDR_B_RAS#
DDR_B_WE#
DDR_B_D33
DDR_B_D14
DDR_B_D42
DDR_B_D59
DDR_B_D63
DDR_B_D43
DDR_B_D55
DDR_B_D53
DDR_B_D29
DDR_B_D24
DDR_B_D34
DDR_B_D4
DDR_B_D26
DDR_B_D13
DDR_B_D10
DDR_B_D21
DDR_B_D11
DDR_B_D57
DDR_B_D44
DDR_B_D0
DDR_B_D7
DDR_B_D46
DDR_B_D3
DDR_B_D15
DDR_B_D27
DDR_B_D30
DDR_B_D35
DDR_B_D40
DDR_B_D49
DDR_B_D23
DDR_B_D25
DDR_B_D19
DDR_B_D37
DDR_B_D48
DDR_B_D36
DDR_B_D18
DDR_B_D8
DDR_B_D47
DDR_B_D9
DDR_B_D60
DDR_B_D50
DDR_B_D62
DDR_B_D52
DDR_B_D2
DDR_B_D51
DDR_B_D56
DDR_B_D39
DDR_B_D22
DDR_B_D28
DDR_B_D6
DDR_B_D45
DDR_B_D17
DDR_B_D58
DDR_B_D61
DDR_B_D31
DDR_B_D54
DDR_B_D1
DDR_B_D41
DDR_B_D5
DDR_B_D12
DDR_B_D20
DDR_B_D38
DDR_B_D32
DDR_B_D16
H_DRAMRST#
DDR_A_D[0..63]<12>
DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>
DDR_A_WE#<12>
DDR_A_RAS#<12>
DDR_A_CAS#<12>
SM_DRAMRST# <12,13>
H_DRAMRST#<6>
DRAMRST_CNTRL_PCH<10,15>
DDR_A_MA[0..15] <12>
DDR_A_DQS#[0..7] <12>
DDR_A_DQS[0..7] <12>
M_CLK_DDR1 <12>
DDR_CKE1_DIMMA <12>
M_CLK_DDR#1 <12>
DDR_CS1_DIMMA# <12>
DDR_CS0_DIMMA# <12>
M_ODT1 <12>
M_ODT0 <12>
M_CLK_DDR0 <12>
M_CLK_DDR#0 <12>
DDR_CKE0_DIMMA <12>
M_CLK_DDR2 <13>
M_CLK_DDR#2 <13>
DDR_CKE2_DIMMB <13>
M_CLK_DDR3 <13>
DDR_CKE3_DIMMB <13>
M_CLK_DDR#3 <13>
DDR_CS3_DIMMB# <13>
DDR_CS2_DIMMB# <13>
M_ODT3 <13>
M_ODT2 <13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
DDR_B_MA[0..15] <13>
DDR_B_BS0<13>
DDR_B_BS1<13>
DDR_B_BS2<13>
DDR_B_WE#<13>
DDR_B_RAS#<13>
DDR_B_CAS#<13>
DDR_B_D[0..63]<13>
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(3/7) DDRIII
Custom
7 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(3/7) DDRIII
Custom
7 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(3/7) DDRIII
Custom
7 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
CPU
DIMM
reset
S0
DRAMRST_CNTRL_PCH hgih ,MOS ON
SM_DRAMRST# HIGH,DDR3 DRAMRST# HIGH
Dimm not reset
S3
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# HIGH
Dimm not reset
S4,5
DRAMRST_CNTRL_PCH Low ,MOS OFF
SM_DRAMRST# lo,DDR3 DRAMRST# low
Dimm reset
R216
0_0402_5%
@R216
0_0402_5%
@
1 2
R217
4.99K_0402_1%
R217
4.99K_0402_1%
12
DDR SYSTEM MEMORY B
UCPU1D
IVY-BRIDGE_BGA1023
DDR SYSTEM MEMORY B
UCPU1D
IVY-BRIDGE_BGA1023
SB_CK[0]
BA34
SB_CK[1]
BA36
SB_CK#[0]
AY34
SB_CK#[1]
BB36
SB_CKE[0]
AR22
SB_CKE[1]
BF27
SB_ODT[0]
AT43
SB_ODT[1]
BG47
SB_DQS[4]
BE51
SB_DQS#[4]
BG51
SB_DQS[5]
BA61
SB_DQS#[5]
BA59
SB_DQS[6]
AR59
SB_DQS#[6]
AT60
SB_DQS[7]
AK61
SB_DQS#[7]
AK59
SB_DQS[0]
AM2
SB_DQS#[0]
AL3
SB_DQS[1]
AV1
SB_DQS#[1]
AV3
SB_DQS[2]
BE11
SB_DQS#[2]
BG11
SB_DQS[3]
BD18
SB_DQS#[3]
BD17
SB_MA[0]
BF32
SB_MA[1]
BE33
SB_MA[2]
BD33
SB_MA[3]
AU30
SB_MA[4]
BD30
SB_MA[5]
AV30
SB_MA[6]
BG30
SB_MA[7]
BD29
SB_MA[8]
BE30
SB_MA[9]
BE28
SB_MA[10]
BD43
SB_MA[11]
AT28
SB_MA[12]
AV28
SB_MA[13]
BD46
SB_MA[14]
AT26
SB_MA[15]
AU22
SB_DQ[0]
AL4
SB_DQ[1]
AL1
SB_DQ[2]
AN3
SB_DQ[3]
AR4
SB_DQ[4]
AK4
SB_DQ[5]
AK3
SB_DQ[6]
AN4
SB_DQ[7]
AR1
SB_DQ[8]
AU4
SB_DQ[9]
AT2
SB_DQ[10]
AV4
SB_DQ[11]
BA4
SB_DQ[12]
AU3
SB_DQ[13]
AR3
SB_DQ[14]
AY2
SB_DQ[15]
BA3
SB_DQ[16]
BE9
SB_DQ[17]
BD9
SB_DQ[18]
BD13
SB_DQ[19]
BF12
SB_DQ[20]
BF8
SB_DQ[21]
BD10
SB_DQ[22]
BD14
SB_DQ[23]
BE13
SB_DQ[24]
BF16
SB_DQ[25]
BE17
SB_DQ[26]
BE18
SB_DQ[27]
BE21
SB_DQ[28]
BE14
SB_DQ[29]
BG14
SB_DQ[30]
BG18
SB_DQ[31]
BF19
SB_DQ[32]
BD50
SB_DQ[33]
BF48
SB_DQ[34]
BD53
SB_DQ[35]
BF52
SB_DQ[36]
BD49
SB_DQ[37]
BE49
SB_DQ[38]
BD54
SB_DQ[39]
BE53
SB_DQ[40]
BF56
SB_DQ[41]
BE57
SB_DQ[42]
BC59
SB_DQ[43]
AY60
SB_DQ[44]
BE54
SB_DQ[45]
BG54
SB_DQ[46]
BA58
SB_DQ[47]
AW59
SB_DQ[48]
AW58
SB_DQ[49]
AU58
SB_DQ[50]
AN61
SB_DQ[51]
AN59
SB_DQ[52]
AU59
SB_DQ[53]
AU61
SB_DQ[54]
AN58
SB_DQ[55]
AR58
SB_DQ[56]
AK58
SB_DQ[57]
AL58
SB_DQ[58]
AG58
SB_DQ[59]
AG59
SB_DQ[60]
AM60
SB_DQ[61]
AL59
SB_DQ[62]
AF61
SB_DQ[63]
AH60
SB_CS#[0]
BE41
SB_CS#[1]
BE47
SB_CAS#
AV43
SB_RAS#
BF40
SB_WE#
BD45
SB_BS[0]
BG39
SB_BS[1]
BD42
SB_BS[2]
AT22
R219
1K_0402_5%
R219
1K_0402_5%
1 2
C190
0.047U_0402_16V7K
C190
0.047U_0402_16V7K
1
2
DDR SYSTEM MEMORY A
UCPU1C
IVY-BRIDGE_BGA1023
DDR SYSTEM MEMORY A
UCPU1C
IVY-BRIDGE_BGA1023
SA_CK[0]
AU36
SA_CK[1]
AT40
SA_CK#[0]
AV36
SA_CK#[1]
AU40
SA_CKE[0]
AY26
SA_CKE[1]
BB26
SA_CS#[0]
BB40
SA_CS#[1]
BC41
SA_ODT[0]
AY40
SA_ODT[1]
BA41
SA_DQS[0]
AJ11
SA_DQS#[0]
AL11
SA_DQS[1]
AR10
SA_DQS#[1]
AR8
SA_DQS[2]
AY11
SA_DQS#[2]
AV11
SA_DQS[3]
AU17
SA_DQS[4]
AW45
SA_DQS#[4]
AV45
SA_DQS[5]
AV51
SA_DQS#[5]
AY51
SA_DQS[6]
AT56
SA_DQS#[6]
AT55
SA_DQS[7]
AK54
SA_DQS#[7]
AK55
SA_MA[0]
BG35
SA_MA[1]
BB34
SA_MA[2]
BE35
SA_MA[3]
BD35
SA_MA[4]
AT34
SA_MA[5]
AU34
SA_MA[6]
BB32
SA_MA[7]
AT32
SA_MA[8]
AY32
SA_MA[9]
AV32
SA_MA[10]
BE37
SA_MA[11]
BA30
SA_MA[12]
BC30
SA_MA[13]
AW41
SA_MA[14]
AY28
SA_MA[15]
AU26
SA_DQ[0]
AG6
SA_DQ[1]
AJ6
SA_DQ[2]
AP11
SA_DQ[3]
AL6
SA_DQ[4]
AJ10
SA_DQ[5]
AJ8
SA_DQ[6]
AL8
SA_DQ[7]
AL7
SA_DQ[8]
AR11
SA_DQ[9]
AP6
SA_DQ[10]
AU6
SA_DQ[11]
AV9
SA_DQ[12]
AR6
SA_DQ[13]
AP8
SA_DQ[14]
AT13
SA_DQ[15]
AU13
SA_DQ[16]
BC7
SA_DQ[17]
BB7
SA_DQ[18]
BA13
SA_DQ[19]
BB11
SA_DQ[20]
BA7
SA_DQ[21]
BA9
SA_DQ[22]
BB9
SA_DQ[23]
AY13
SA_DQ[24]
AV14
SA_DQ[25]
AR14
SA_DQ[26]
AY17
SA_DQ[27]
AR19
SA_DQ[28]
BA14
SA_DQ[29]
AU14
SA_DQ[30]
BB14
SA_DQ[31]
BB17
SA_DQ[32]
BA45
SA_DQ[33]
AR43
SA_DQ[34]
AW48
SA_DQ[35]
BC48
SA_DQ[36]
BC45
SA_DQ[37]
AR45
SA_DQ[38]
AT48
SA_DQ[39]
AY48
SA_DQ[40]
BA49
SA_DQ[41]
AV49
SA_DQ[42]
BB51
SA_DQ[43]
AY53
SA_DQ[44]
BB49
SA_DQ[45]
AU49
SA_DQ[46]
BA53
SA_DQ[47]
BB55
SA_DQ[48]
BA55
SA_DQ[49]
AV56
SA_DQ[50]
AP50
SA_DQ[51]
AP53
SA_DQ[52]
AV54
SA_DQ[53]
AT54
SA_DQ[54]
AP56
SA_DQ[55]
AP52
SA_DQ[56]
AN57
SA_DQ[57]
AN53
SA_DQ[58]
AG56
SA_DQ[59]
AG53
SA_DQ[60]
AN55
SA_DQ[61]
AN52
SA_DQ[62]
AG55
SA_DQ[63]
AK56
SA_CAS#
BE39
SA_RAS#
BD39
SA_WE#
AT41
SA_BS[0]
BD37
SA_BS[1]
BF36
SA_BS[2]
BA28
SA_DQS#[3]
AT17
G
D
S
Q16
BSS138_NL_SOT23-3
G
D
S
Q16
BSS138_NL_SOT23-3
2
13
R212
1K_0402_5%
R212
1K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
VAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
CFG2
CFG4
CFG5
CFG6
CFG7
VSSAXG_VAL_SENSE
VCC_VAL_SENSE
VSS_VAL_SENSE
CFG4
CFG5
CFG2
CFG7
CFG0
CFG6
+VGFX_CORE
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(4/7) RSVD,CFG
Custom
8 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(4/7) RSVD,CFG
Custom
8 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(4/7) RSVD,CFG
Custom
8 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
These pins are for solder joint
reliability and non-critical to
function. For BGA only.
10: 2x8 PCI Express
PCIE Port Bifurcation Straps
CFG[6:5]
11: (Default) 1x16 PCI Express
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
1: (Default) PEG Train immediately following
xxRESETB de assertion
CFG4
eDP enable
0:Enable
1:Disable
CFG Straps for Processor
01: Reserved
00: 1x8,2x4 PCI Express
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1: Normal Operation; Lane # definition matches
socket pin map definition
*
*
*
UMA,Optimus eDP
DISO eDP
Tacoma_Fall2 1.0 P.12
R302
49.9_0402_1%
R302
49.9_0402_1%
12
R296
1K_0402_1%
R296
1K_0402_1%
12
T32
PAD
@
T32
PAD
@
R541
1K_0402_1%
R541
1K_0402_1%
12
R306
49.9_0402_1%
R306
49.9_0402_1%
12
R91
100_0402_1%
@
R91
100_0402_1%
@
12
R543
1K_0402_1%
@
R543
1K_0402_1%
@
12
R311
49.9_0402_1%
R311
49.9_0402_1%
12
R95
100_0402_1%
@
R95
100_0402_1%
@
12
RESERVED
UCPU1E
IVY-BRIDGE_BGA1023
RESERVED
UCPU1E
IVY-BRIDGE_BGA1023
CFG[0]
B50
CFG[1]
C51
CFG[2]
B54
CFG[3]
D53
CFG[4]
A51
CFG[5]
C53
CFG[6]
C55
CFG[7]
H49
CFG[8]
A55
CFG[9]
H51
CFG[10]
K49
CFG[11]
K53
CFG[12]
F53
CFG[13]
G53
CFG[14]
L51
CFG[15]
F51
CFG[16]
D52
CFG[17]
L53
DC_TEST_A4
A4
DC_TEST_A58
A58
DC_TEST_A59
A59
DC_TEST_A61
A61
DC_TEST_BD1
BD1
DC_TEST_BD61
BD61
DC_TEST_BE1
BE1
DC_TEST_BE3
BE3
DC_TEST_BE59
BE59
DC_TEST_BE61
BE61
DC_TEST_BG1
BG1
DC_TEST_BG3
BG3
DC_TEST_BG4
BG4
DC_TEST_BG58
BG58
DC_TEST_BG59
BG59
DC_TEST_BG61
BG61
DC_TEST_C4
C4
DC_TEST_C59
C59
DC_TEST_C61
C61
DC_TEST_D1
D1
DC_TEST_D3
D3
DC_TEST_D61
D61
VCC_VAL_SENSE
H43
VSS_VAL_SENSE
K43
VAXG_VAL_SENSE
H45
VSSAXG_VAL_SENSE
K45
VCC_DIE_SENSE
F48
RSVD41
AH2
RSVD42
AG13
RSVD43
AM14
RSVD44
AM15
RSVD8
BA19
RSVD9
AV19
RSVD10
AT21
RSVD11
BB21
RSVD12
BB19
RSVD13
AY21
RSVD14
BA22
RSVD15
AY22
RSVD16
AU19
RSVD17
AU21
RSVD18
BD21
RSVD19
BD22
RSVD20
BD25
RSVD21
BD26
RSVD22
BG22
RSVD23
BE22
RSVD24
BG26
RSVD25
BE26
RSVD26
BF23
RSVD27
BE24
RSVD45
N50
RSVD30
N42
RSVD31
L42
RSVD32
L45
RSVD33
L47
RSVD34
M13
RSVD35
M14
RSVD36
U14
RSVD37
W14
RSVD38
P13
RSVD39
AT49
RSVD40
K24
RSVD6
H48
RSVD7
K48
BCLK_ITP
N59
BCLK_ITP#
N58
T18
PAD
@
T18
PAD
@
R297
1K_0402_1%
@
R297
1K_0402_1%
@
12
R293
1K_0402_1%
@
R293
1K_0402_1%
@
12
R310
49.9_0402_1%
R310
49.9_0402_1%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VCCIO_SENSE
VSSIO_SENSE_L
VSSSENSE_R
VCCSENSE_R
H_CPU_SVIDALRT#
H_CPU_SVIDCLK
H_CPU_SVIDDAT
VCCIO_SEL
VCCIO_SEL
VCCIO_SENSE <54>
VCCSENSE <56>
VSSSENSE <56>
VR_SVID_ALRT# <56>
VR_SVID_CLK <56>
VR_SVID_DAT <56>
VSSIO_SENSE_L <54>
+CPU_CORE
+1.05VS_VTT+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+1.05VS_VTT
+CPU_CORE
+3VS
+1.05VS_VTT
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(5/7) PWR,BYPASS
Custom
9 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(5/7) PWR,BYPASS
Custom
9 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(5/7) PWR,BYPASS
Custom
9 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
8.5A
Should change to connect form
power cirucit & layout differential
with VCCIO_SENSE.
ULV type
DC 33A
Place the PU
resistors close to CPU
Place the PU
resistors close to VR
*
BC22
VCCIO_SEL after Ivy bridge ES2 Voltage support
0: +1.0VS_VTT
1/NC : (Default) +1.05VS_VTT
INTEL Recommend VCC
4*470UF,12*22uF(0805) and 35*2.2uF(0402)
PD0.8
CAP at Power side
INTEL Recommend VCCIO
2*330UF,10*10uF(0603) and 26*1uF(0402)
PD0.8
CAP at Power side
Check list 1.5
For DDR
For PEG
R281
100_0402_1%
R281
100_0402_1%
12
R527 0_0402_5%
R527 0_0402_5%
1 2
R529
75_0402_5%
R529
75_0402_5%
12
R521
10K_0402_5%
R521
10K_0402_5%
12
R79
100_0402_1%
@R79
100_0402_1%
@
1 2
POWER
CORE SUPPLY
PEG IO AND DDR IO
SENSE LINES SVID QUIET
RAILS
UCPU1F
IVY-BRIDGE_BGA1023
POWER
CORE SUPPLY
PEG IO AND DDR IO
SENSE LINES SVID QUIET
RAILS
UCPU1F
IVY-BRIDGE_BGA1023
VCC_SENSE
F43
VSS_SENSE
G43
VIDALERT#
A44
VIDSCLK
B43
VIDSOUT
C44
VSS_SENSE_VCCIO
AN17
VCC[1]
A26
VCC[2]
A29
VCC[3]
A31
VCC[4]
A34
VCC[5]
A35
VCC[6]
A38
VCC[7]
A39
VCC[8]
A42
VCC[9]
C26
VCC[10]
C27
VCC[11]
C32
VCC[12]
C34
VCC[13]
C37
VCC[14]
C39
VCC[15]
C42
VCC[16]
D27
VCC[17]
D32
VCC[18]
D34
VCC[19]
D37
VCC[20]
D39
VCC[21]
D42
VCC[22]
E26
VCC[23]
E28
VCC[24]
E32
VCC[25]
E34
VCC[26]
E37
VCC[27]
E38
VCC[28]
F25
VCC[29]
F26
VCC[30]
F28
VCC[31]
F32
VCC[32]
F34
VCC[33]
F37
VCC[34]
F38
VCC[35]
F42
VCC[36]
G42
VCC[37]
H25
VCC[38]
H26
VCC[39]
H28
VCC[40]
H29
VCC[41]
H32
VCC[42]
H34
VCC[43]
H35
VCC[44]
H37
VCC[45]
H38
VCC[46]
H40
VCC[47]
J25
VCC[48]
J26
VCC[49]
J28
VCC[50]
J29
VCC[51]
J32
VCC[52]
J34
VCC[53]
J35
VCC[54]
J37
VCC[55]
J38
VCC[56]
J40
VCC[57]
J42
VCC[58]
K26
VCC[59]
K27
VCC[60]
K29
VCC[61]
K32
VCC[62]
K34
VCC[63]
K35
VCC[64]
K37
VCC[66]
K39
VCC[67]
K42
VCC[68]
L25
VCC[69]
L28
VCC[70]
L33
VCC[71]
L36
VCC[72]
L40
VCC[73]
N26
VCC[74]
N30
VCC[75]
N34
VCC[76]
N38
VCCIO[1]
AF46
VCCIO[3]
AG48
VCCIO[4]
AG50
VCCIO[5]
AG51
VCCIO[6]
AJ17
VCCIO[7]
AJ21
VCCIO[8]
AJ25
VCCIO[9]
AJ43
VCCIO[10]
AJ47
VCCIO[11]
AK50
VCCIO[12]
AK51
VCCIO[13]
AL14
VCCIO[14]
AL15
VCCIO[15]
AL16
VCCIO[16]
AL20
VCCIO[17]
AL22
VCCIO[18]
AL26
VCCIO[19]
AL45
VCCIO[20]
AL48
VCCIO[21]
AM16
VCCIO[22]
AM17
VCCIO[23]
AM21
VCCIO[24]
AM43
VCCIO[25]
AM47
VCCIO[26]
AN20
VCCIO[27]
AN42
VCCIO[28]
AN45
VCCIO[29]
AN48
VCCIO[30]
AA14
VCCIO[31]
AA15
VCCIO[32]
AB17
VCCIO[33]
AB20
VCCIO[34]
AC13
VCCIO[35]
AD16
VCCIO[36]
AD18
VCCIO[37]
AD21
VCCIO[38]
AE14
VCCIO[39]
AE15
VCCIO[40]
AF16
VCCIO[41]
AF18
VCCIO[42]
AF20
VCCIO[43]
AG15
VCCIO[44]
AG16
VCCIO[45]
AG17
VCCIO[46]
AG20
VCCIO[47]
AG21
VCCIO[48]
AJ14
VCCIO[49]
AJ15
VCCIO50
W16
VCCIO51
W17
VCCPQE[1]
AM25
VCCPQE[2]
AN22
VCCIO_SENSE
AN16
VCCIO_SEL
BC22
R282 0_0402_5%R282 0_0402_5%
1 2
R528 43_0402_1%
R528 43_0402_1%
1 2
R512
10_0402_5%
R512
10_0402_5%
12
R288
100_0402_1%
R288
100_0402_1%
12
R531
130_0402_5%
R531
130_0402_5%
12
R530 0_0402_5%
R530 0_0402_5%
1 2
R522
10K_0402_5%
@
R522
10K_0402_5%
@
12
R289 0_0402_5%R289 0_0402_5%
1 2
C553
1U_0402_6.3V6K
C553
1U_0402_6.3V6K
12
R513 10_0402_5%R513 10_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
H_VCCSA_VID0
H_VCCSA_VID1
+VCCSA
SA_DIMM_VREFDQ
SA_DIMM_VREFDQ
DRAMRST_CNTRL_PCH
RUN_ON_CPU1.5VS3
RUN_ON_CPU1.5VS3#
RUN_ON_CPU1.5VS3#
SB_DIMM_VREFDQ
RUN_ON_CPU1.5VS3
+V_SM_VREF_CNT +V_SM_VREF
SB_DIMM_VREFDQ
DRAMRST_CNTRL_PCH
VCCSA_SENSE <53>
VCC_AXG_SENSE<56>
VSS_AXG_SENSE<56>
H_VCCSA_VID1 <53>
H_VCCSA_VID0 <53>
CPU1.5V_S3_GATE<42,47>
SUSP#<42,47,52,54>
RUN_ON_CPU1.5VS3# <6>
SUSP<6,47,52>
DRAMRST_CNTRL_PCH <7,15>
+VGFX_CORE
+VCCSA
+1.8VS
+VGFX_CORE
+1.5V_CPU_VDDQ
+1.5V_CPU_VDDQ
+V_DDR_REFA
+1.5V
+VSB
+3VALW
+1.5V_CPU_VDDQ
+1.5V_CPU_VDDQ +1.5V
+1.5V_CPU_VDDQ +1.5V
+V_DDR_REFB
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(6/7) PWR
Custom
10 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(6/7) PWR
Custom
10 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(6/7) PWR
Custom
10 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
DC 29A
INTEL Recommend VCCPLL
1*330uF,2*1uF(0402)
PD0.8
5A
6A
CPU EDS1.3 P.93
VCCSA_VID0 Must PD
1.2A
Place BOT OUT Conn
1
HR CR
0
0
0 X1
1 1
V
V V
V
V
VX
Vout
0.9V
0.85V
0.725V
VCCSA
VID0
0.675V
VID1
0
SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9
INTEL Recommend VAXG
2*470uF,6*22uF(0805) and 6*10uF(0603)
11*1U(0402)
PD0.8
INTEL Recommend VDDQ
1*330uF,8*10uF(0603) ,10*1uF(0402)
PD0.8
INTEL Recommend VCCSA
1*330uF,5*10uF(0603) ,5*1uF(0402)
PD0.8
+V_SM_VREF_CNT should
have 20 mil trace width
Place BOT OUT BGA
SGA20331E10 S POLY C 330U
2V Y D2 LESR9M EEFSX H1.9
SA_DIMM_VREFDQ
SB_DIMM_VREFDQ
Check list1.5 P18 M1 default M3 no stuff
CR CheckList Rev1.5
Place TOP IN BGA
Place BOT OUT BGA
Place TOP IN BGA
M3 Support
B phase Cost down proposal
C348
1U_0402_6.3V6K
C348
1U_0402_6.3V6K
12
G
D
S
Q8
2N7002K_SOT23-3
G
D
S
Q8
2N7002K_SOT23-3
2
13
C560
10U_0603_6.3V6M
C560
10U_0603_6.3V6M
12
+
C286
330U_2.5V_M
SF000002Z00
+
C286
330U_2.5V_M
SF000002Z00
1
2
C151 0.1U_0402_10V7KC151 0.1U_0402_10V7K
12
R87
100_0402_5%
@
R87
100_0402_5%
@
1 2
C338
10U_0603_6.3V6M
C338
10U_0603_6.3V6M
12
C302
1U_0402_6.3V6K
C302
1U_0402_6.3V6K
12
R65 0_0402_5%R65 0_0402_5%
1 2
C320
1U_0402_6.3V6K
C320
1U_0402_6.3V6K
12
C633
22U_0805_6.3V6M
C633
22U_0805_6.3V6M
12
C301
1U_0402_6.3V6K
C301
1U_0402_6.3V6K
12
C577
10U_0603_6.3V6M
C577
10U_0603_6.3V6M
12
C153
10U_0603_6.3V6M
C153
10U_0603_6.3V6M
12
R85
82K_0402_5%
R85
82K_0402_5%
12
C296
10U_0603_6.3V6M
C296
10U_0603_6.3V6M
12
C300
1U_0402_6.3V6K
C300
1U_0402_6.3V6K
12
C555
10U_0603_6.3V6M
C555
10U_0603_6.3V6M
12
POWER
GRAPHICS
DDR3 - 1.5V RAILS
1.8V RAIL
SENSE
LINES
SA RAIL
SENSE LINES
QUIET RAILS
VREF
VCCSA VID
lines
UCPU1G
IVY-BRIDGE_BGA1023
POWER
GRAPHICS
DDR3 - 1.5V RAILS
1.8V RAIL
SENSE
LINES
SA RAIL
SENSE LINES
QUIET RAILS
VREF
VCCSA VID
lines
UCPU1G
IVY-BRIDGE_BGA1023
SM_VREF
AY43
VAXG[1]
AA46
VAXG[2]
AB47
VAXG[3]
AB50
VAXG[4]
AB51
VAXG[5]
AB52
VAXG[6]
AB53
VAXG[7]
AB55
VAXG[8]
AB56
VAXG[9]
AB58
VAXG[10]
AB59
VAXG[11]
AC61
VAXG[12]
AD47
VAXG[13]
AD48
VAXG[14]
AD50
VAXG[15]
AD51
VAXG[16]
AD52
VAXG[17]
AD53
VAXG[18]
AD55
VAXG[19]
AD56
VAXG[20]
AD58
VAXG[21]
AD59
VAXG[22]
AE46
VAXG[23]
N45
VAXG[24]
P47
VAXG[25]
P48
VAXG[26]
P50
VAXG[27]
P51
VAXG[28]
P52
VAXG[29]
P53
VAXG[30]
P55
VAXG[31]
P56
VAXG[32]
P61
VAXG[33]
T48
VAXG[34]
T58
VAXG[35]
T59
VAXG[36]
T61
VAXG[37]
U46
VAXG[38]
V47
VAXG[39]
V48
VAXG[40]
V50
VAXG[41]
V51
VAXG[42]
V52
VAXG[43]
V53
VAXG[44]
V55
VAXG[45]
V56
VAXG[46]
V58
VAXG[47]
V59
VAXG[48]
W50
VAXG[49]
W51
VAXG[50]
W52
VAXG[51]
W53
VAXG[52]
W55
VAXG[53]
W56
VAXG[54]
W61
VDDQ[11]
AM40
VDDQ[12]
AN30
VDDQ[13]
AN34
VDDQ[14]
AN38
VDDQ[15]
AR26
VDDQ[1]
AJ28
VDDQ[2]
AJ33
VDDQ[3]
AJ36
VDDQ[4]
AJ40
VDDQ[5]
AL30
VDDQ[6]
AL34
VDDQ[7]
AL38
VDDQ[8]
AL42
VDDQ[9]
AM33
VDDQ[10]
AM36
VCCPLL[1]
BB3
VCCPLL[2]
BC1
VCCSA_SENSE
U10
VCCSA_VID[1]
D49
VAXG[55]
Y48
VAXG[56]
Y61
VCCPLL[3]
BC4
VAXG_SENSE
F45
VSSAXG_SENSE
G45
VCCSA[1]
L17
VCCSA[10]
R21
VCCSA[12]
V16
VCCSA[13]
V17
VCCSA[14]
V18
VCCSA[4]
N20
VCCSA[5]
N22
VCCSA[6]
P17
VCCSA[9]
R18
VDDQ[16]
AR28
VDDQ[17]
AR30
VDDQ[18]
AR32
VDDQ[19]
AR34
VDDQ[20]
AR36
VDDQ[21]
AR40
VDDQ[22]
AV41
VDDQ[23]
AW26
VDDQ[24]
BA40
VDDQ[25]
BB28
VDDQ[26]
BG33
VCCSA[11]
U15
VCCSA[15]
V21
VCCSA[16]
W20
VCCSA[2]
L21
VCCSA[3]
N16
VCCDQ[1]
AM28
VCCDQ[2]
AN26
VCCSA[7]
P20
VCCSA[8]
R16
VDDQ_SENSE
BC43
VSS_SENSE_VDDQ
BA43
VCCSA_VID[0]
D48
SA_DIMM_VREFDQ
BE7
SB_DIMM_VREFDQ
BG7
R81 0_0402_5%@R81 0_0402_5%@
1 2
R175
15K_0402_1%
R175
15K_0402_1%
1 2
R78
100K_0402_5%
@
R78
100K_0402_5%
@
12
C340
10U_0603_6.3V6M
C340
10U_0603_6.3V6M
12
C318
1U_0402_6.3V6K
C318
1U_0402_6.3V6K
12
C280
1U_0402_6.3V6K
C280
1U_0402_6.3V6K
1
2
R519
1K_0402_1%
@
R519
1K_0402_1%
@
12
C328
1U_0402_6.3V6K
C328
1U_0402_6.3V6K
12
G
D
S
Q9
BSS138_NL_SOT23-3
G
D
S
Q9
BSS138_NL_SOT23-3
2
13
C299
10U_0603_6.3V6M
C299
10U_0603_6.3V6M
12
R113
1K_0402_1%~D
R113
1K_0402_1%~D
12
R124
1K_0402_1%~D
R124
1K_0402_1%~D
12
C312
1U_0402_6.3V6K
C312
1U_0402_6.3V6K
12
C157 0.1U_0402_10V7KC157 0.1U_0402_10V7K
12
C281
1U_0402_6.3V6K
C281
1U_0402_6.3V6K
1
2
+
C242
330U_D2_2V_Y
+
C242
330U_D2_2V_Y
1
2
C321
1U_0402_6.3V6K
C321
1U_0402_6.3V6K
12
R518
1K_0402_1%
@
R518
1K_0402_1%
@
12
C579
10U_0603_6.3V6M
C579
10U_0603_6.3V6M
12
U11
AO4430L_SO8
U11
AO4430L_SO8
6
2
4
1
3
5
7
8
R117 0_0402_5%@R117 0_0402_5%@
12
C309
1U_0402_6.3V6K
C309
1U_0402_6.3V6K
12
C298
10U_0603_6.3V6M
C298
10U_0603_6.3V6M
12
C349
1U_0402_6.3V6K
C349
1U_0402_6.3V6K
12
G
D
S
Q6
2N7002K_SOT23-3
@
G
D
S
Q6
2N7002K_SOT23-3
@
2
13
R248
0_0402_5%
@R248
0_0402_5%
@
1 2
C316
1U_0402_6.3V6K
C316
1U_0402_6.3V6K
12
C308
1U_0402_6.3V6K
C308
1U_0402_6.3V6K
12
R77
@
330K_0402_5%
R77
@
330K_0402_5%
12
R308
100_0402_5%
R308
100_0402_5%
12
C329
1U_0402_6.3V6K
C329
1U_0402_6.3V6K
12
R82 @ 0_0402_5%R82 @ 0_0402_5%
1 2
C351
1U_0402_6.3V6K
C351
1U_0402_6.3V6K
12
G
D
S
Q11
AO3414_SOT23-3
@
G
D
S
Q11
AO3414_SOT23-3
@
1
2
3
C337
10U_0603_6.3V6M
C337
10U_0603_6.3V6M
12
J1 @
PAD-OPEN 4x4m
J1 @
PAD-OPEN 4x4m
1 2
R309
100_0402_5%
R309
100_0402_5%
12
R76
@
1K_0402_1%~D
R76
@
1K_0402_1%~D
12
C116
@
0.1U_0402_10V6K
C116
@
0.1U_0402_10V6K
12
C115
0.047U_0603_25V7K
C115
0.047U_0603_25V7K
12
R116
@
1K_0402_1%~D
R116
@
1K_0402_1%~D
12
R80
220_0402_5%
R80
220_0402_5%
12
G
D
S
Q10
BSS138_NL_SOT23-3
G
D
S
Q10
BSS138_NL_SOT23-3
2
13
+
C287
330U_2.5V_M
SF000002Z00
@
+
C287
330U_2.5V_M
SF000002Z00
@
1
2
C339
10U_0603_6.3V6M
C339
10U_0603_6.3V6M
12
C150 0.1U_0402_10V7KC150 0.1U_0402_10V7K
12
C559
10U_0603_6.3V6M
C559
10U_0603_6.3V6M
12
C317
1U_0402_6.3V6K
C317
1U_0402_6.3V6K
12
C117
0.1U_0402_16V4Z
C117
0.1U_0402_16V4Z
12
C295
10U_0603_6.3V6M
C295
10U_0603_6.3V6M
12
R148
0_0402_5%
@R148
0_0402_5%
@
1 2
R86
0_0402_5%
@R86
0_0402_5%
@
1 2
G
D
S
Q7
2N7002K_SOT23-3
G
D
S
Q7
2N7002K_SOT23-3
2
13
C152 0.1U_0402_10V7KC152 0.1U_0402_10V7K
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(7/7) VSS
Custom
11 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(7/7) VSS
Custom
11 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PROCESSOR(7/7) VSS
Custom
11 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
VSS
NCTF
UCPU1I
IVY-BRIDGE_BGA1023
VSS
NCTF
UCPU1I
IVY-BRIDGE_BGA1023
VSS[181]
BG17
VSS[182]
BG21
VSS[183]
BG24
VSS[184]
BG28
VSS[185]
BG37
VSS[186]
BG41
VSS[187]
BG45
VSS[188]
BG49
VSS[189]
BG53
VSS[190]
BG9
VSS[191]
C29
VSS[192]
C35
VSS[193]
C40
VSS[194]
D10
VSS[195]
D14
VSS[196]
D18
VSS[197]
D22
VSS[198]
D26
VSS[199]
D29
VSS[200]
D35
VSS[201]
D4
VSS[202]
D40
VSS[203]
D43
VSS[204]
D46
VSS[205]
D50
VSS[206]
D54
VSS[207]
D58
VSS[208]
D6
VSS[209]
E25
VSS[210]
E29
VSS[211]
E3
VSS[212]
E35
VSS[213]
E40
VSS[214]
F13
VSS[215]
F15
VSS[216]
F19
VSS[217]
F29
VSS[218]
F35
VSS[219]
F40
VSS[220]
F55
VSS[221]
G51
VSS[222]
G6
VSS[223]
G61
VSS[224]
H10
VSS[225]
H14
VSS[226]
H17
VSS[227]
H21
VSS[228]
H4
VSS[229]
H53
VSS[230]
H58
VSS[231]
J1
VSS[232]
J49
VSS[233]
J55
VSS[234]
K11
VSS[235]
K21
VSS[236]
K51
VSS[237]
K8
VSS[238]
L16
VSS[239]
L20
VSS[240]
L22
VSS[241]
L26
VSS[242]
L30
VSS[243]
L34
VSS[244]
L38
VSS[245]
L43
VSS[246]
L48
VSS[268]
P14
VSS[269]
P16
VSS[270]
P18
VSS[271]
P21
VSS[272]
P58
VSS[273]
P59
VSS[274]
P9
VSS[275]
R17
VSS[276]
R20
VSS[277]
R4
VSS[278]
R46
VSS[279]
T1
VSS[280]
T47
VSS[281]
T50
VSS[282]
T51
VSS[283]
T52
VSS[284]
T53
VSS[285]
T55
VSS[286]
T56
VSS[287]
U13
VSS[288]
U8
VSS[289]
V20
VSS[290]
V61
VSS_NCTF_1
A5
VSS_NCTF_2
A57
VSS_NCTF_3
BC61
VSS_NCTF_4
BD3
VSS_NCTF_5
BD59
VSS_NCTF_6
BE4
VSS_NCTF_7
BE58
VSS_NCTF_8
BG5
VSS_NCTF_9
BG57
VSS_NCTF_10
C3
VSS_NCTF_11
C58
VSS_NCTF_12
D59
VSS_NCTF_13
E1
VSS_NCTF_14
E61
VSS[250]
M4
VSS[251]
M58
VSS[252]
M6
VSS[253]
N1
VSS[254]
N17
VSS[255]
N21
VSS[256]
N25
VSS[257]
N28
VSS[258]
N33
VSS[259]
N36
VSS[260]
N40
VSS[261]
N43
VSS[262]
N47
VSS[263]
N48
VSS[264]
N51
VSS[265]
N52
VSS[266]
N56
VSS[267]
N61
VSS[247]
L61
VSS[248]
M11
VSS[291]
W13
VSS[292]
W15
VSS[293]
W18
VSS[294]
W21
VSS[295]
W46
VSS[296]
W8
VSS[297]
Y4
VSS[298]
Y47
VSS[299]
Y58
VSS[300]
Y59
VSS[249]
M15
VSS[301]
G48
VSS
UCPU1H
IVY-BRIDGE_BGA1023
VSS
UCPU1H
IVY-BRIDGE_BGA1023
VSS[1]
A13
VSS[2]
A17
VSS[3]
A21
VSS[4]
A25
VSS[5]
A28
VSS[6]
A33
VSS[7]
A37
VSS[8]
A40
VSS[9]
A45
VSS[10]
A49
VSS[11]
A53
VSS[12]
A9
VSS[13]
AA1
VSS[14]
AA13
VSS[15]
AA50
VSS[16]
AA51
VSS[17]
AA52
VSS[18]
AA53
VSS[19]
AA55
VSS[20]
AA56
VSS[21]
AA8
VSS[22]
AB16
VSS[23]
AB18
VSS[24]
AB21
VSS[25]
AB48
VSS[26]
AB61
VSS[27]
AC10
VSS[28]
AC14
VSS[29]
AC46
VSS[30]
AC6
VSS[31]
AD17
VSS[32]
AD20
VSS[33]
AD4
VSS[34]
AD61
VSS[35]
AE13
VSS[36]
AE8
VSS[37]
AF1
VSS[38]
AF17
VSS[39]
AF21
VSS[40]
AF47
VSS[41]
AF48
VSS[42]
AF50
VSS[43]
AF51
VSS[44]
AF52
VSS[45]
AF53
VSS[46]
AF55
VSS[47]
AF56
VSS[48]
AF58
VSS[49]
AF59
VSS[50]
AG10
VSS[51]
AG14
VSS[52]
AG18
VSS[53]
AG47
VSS[54]
AG52
VSS[55]
AG61
VSS[56]
AG7
VSS[57]
AH4
VSS[58]
AH58
VSS[59]
AJ13
VSS[60]
AJ16
VSS[61]
AJ20
VSS[62]
AJ22
VSS[63]
AJ26
VSS[64]
AJ30
VSS[65]
AJ34
VSS[66]
AJ38
VSS[67]
AJ42
VSS[68]
AJ45
VSS[69]
AJ48
VSS[70]
AJ7
VSS[71]
AK1
VSS[72]
AK52
VSS[73]
AL10
VSS[74]
AL13
VSS[75]
AL17
VSS[76]
AL21
VSS[77]
AL25
VSS[78]
AL28
VSS[79]
AL33
VSS[80]
AL36
VSS[81]
AL40
VSS[82]
AL43
VSS[83]
AL47
VSS[84]
AL61
VSS[85]
AM13
VSS[86]
AM20
VSS[87]
AM22
VSS[88]
AM26
VSS[89]
AM30
VSS[90]
AM34
VSS[91]
AM38
VSS[92]
AM4
VSS[93]
AM42
VSS[94]
AM45
VSS[95]
AM48
VSS[96]
AM58
VSS[97]
AN1
VSS[98]
AN21
VSS[99]
AN25
VSS[100]
AN28
VSS[101]
AN33
VSS[102]
AN36
VSS[103]
AN40
VSS[104]
AN43
VSS[105]
AN47
VSS[106]
AN50
VSS[107]
AN54
VSS[108]
AP10
VSS[109]
AP51
VSS[110]
AP55
VSS[111]
AP7
VSS[112]
AR13
VSS[113]
AR17
VSS[114]
AR21
VSS[115]
AR41
VSS[116]
AR48
VSS[117]
AR61
VSS[118]
AR7
VSS[119]
AT14
VSS[120]
AT19
VSS[121]
AT36
VSS[122]
AT4
VSS[123]
AT45
VSS[124]
AT52
VSS[125]
AT58
VSS[126]
AU1
VSS[127]
AU11
VSS[128]
AU28
VSS[129]
AU32
VSS[130]
AU51
VSS[131]
AU7
VSS[132]
AV17
VSS[133]
AV21
VSS[134]
AV22
VSS[135]
AV34
VSS[136]
AV40
VSS[137]
AV48
VSS[138]
AV55
VSS[139]
AW13
VSS[140]
AW43
VSS[141]
AW61
VSS[142]
AW7
VSS[143]
AY14
VSS[144]
AY19
VSS[145]
AY30
VSS[146]
AY36
VSS[147]
AY4
VSS[148]
AY41
VSS[149]
AY45
VSS[150]
AY49
VSS[151]
AY55
VSS[152]
AY58
VSS[153]
AY9
VSS[154]
BA1
VSS[155]
BA11
VSS[156]
BA17
VSS[157]
BA21
VSS[158]
BA26
VSS[159]
BA32
VSS[160]
BA48
VSS[161]
BA51
VSS[162]
BB53
VSS[163]
BC13
VSS[164]
BC5
VSS[165]
BC57
VSS[166]
BD12
VSS[167]
BD16
VSS[168]
BD19
VSS[169]
BD23
VSS[170]
BD27
VSS[171]
BD32
VSS[172]
BD36
VSS[173]
BD40
VSS[174]
BD44
VSS[175]
BD48
VSS[176]
BD52
VSS[177]
BD56
VSS[178]
BD8
VSS[179]
BE5
VSS[180]
BG13
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDR_A_DM0
SM_DRAMRST#
DDR_A_MA15
DDR_A_D31
DDR_CKE0_DIMMA
DDR_A_D12
DDR_A_D59
DDR_A_MA3
DDR_A_D6
DDR_CS1_DIMMA#
PCH_SMBCLK
DDR_A_BS1
DDR_A_D39
DDR_A_WE#
DDR_A_DQS0
DDR_A_MA7
DDR_A_MA0
DDR_A_DM2
DDR_A_D0
DDR_A_DQS7
DDR_A_DM1
DDR_A_D28
DDR_A_D46
DDR_A_D57
DDR_A_D19
DDR_A_DQS#5
DDR_A_D4
DDR_A_D51
DDR_A_DM4
DDR_A_DQS2
DDR_A_D30
DDR_A_D44
DDR_A_D33
DDR_A_RAS#
DDR_A_DM5
DDR_A_D58
DDR_A_DQS3
DDR_A_MA8
DDR_CS0_DIMMA#
DDR_A_D27
DDR_A_MA6
DDR_A_D10
DDR_A_MA10
DDR_A_D3
DDR_A_DQS#7
DDR_A_DQS#6
DDR_A_D1
DDR_A_MA9
DDR_A_D40
DDR_A_D29
DDR_A_D16
DDR_A_D52
DDR_A_DQS#4
DDR_A_DM3
DDR_A_D54
DDR_A_DQS5
DDR_A_BS2
DDR_A_D49
DDR_A_D9
DDR_A_D45
DDR_A_MA1
DDR_A_D7
DDR_A_DM7
DDR_A_D20
DDR_A_D13
DDR_A_BS0
DDR_A_D60
M_ODT0DDR_A_CAS#
DDR_A_DQS#1
DDR_A_MA5
DDR_A_D37
DDR_A_MA14
DDR_A_D55
DDR_A_D21
DDR_A_MA4
DDR_A_D62
DDR_A_D23
DDR_A_D15
DDR_A_D24
DDR_A_D53
DDR_A_D56
DDR_A_D18
DDR_A_D47DDR_A_D43
M_ODT1
M_CLK_DDR1
DDR_A_D34
DDR_A_D48
M_CLK_DDR#1
DDR_A_D11
DDR_A_DQS#2
PCH_SMBDATA
DDR_A_D38
M_CLK_DDR#0
M_CLK_DDR0
DDR_A_D8
DDR_A_D32
DDR_A_DQS#3
DDR_A_MA11
DDR_A_MA13
DDR_A_DQS1
DDR_A_D61
DDR_A_D50
DDR_A_D41
DDR_A_MA2
DDR_A_D17
DDR_A_D36
DDR_A_D26
DDR_A_D2
DDR_A_D63
DDR_A_D25
DDR_A_D22
DDR_A_D5
DDR_A_D35
DDR_A_DQS6
DDR_A_MA12
DDR_A_D14
DDR_A_DQS4
DDR_A_DQS#0
DDR_A_D42
DDR_A_DM6
DDR_CKE1_DIMMA
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..15]<7>
DDR_A_BS2<7>
DDR_CKE0_DIMMA<7>
M_CLK_DDR#0<7>
M_CLK_DDR0<7>
DDR_A_CAS#<7>
DDR_A_WE#<7>
DDR_A_BS0<7>
DDR_A_BS1 <7>
DDR_CKE1_DIMMA <7>
DDR_CS1_DIMMA#<7>
DDR_CS0_DIMMA# <7>
DDR_A_RAS# <7>
M_CLK_DDR#1 <7>
M_CLK_DDR1 <7>
M_ODT0 <7>
SM_DRAMRST# <7,13>
M_ODT1 <7>
PCH_SMBCLK <13,15,40,43>
PCH_SMBDATA <13,15,40,43>
+1.5V
+VREF_CA
+1.5V
+0.75VS
+3VS
+1.5V+1.5V
+V_DDR_REFA
+1.5V
+1.5V
+0.75VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
DDRIII DIMMB
Custom
12 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
DDRIII DIMMB
Custom
12 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
DDRIII DIMMB
Custom
12 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
DDR3 SO-DIMM A
Layout Note:
Place near JDIMM1
Layout Note: Place these 4 Caps near
Command and Control signals of JDIMM1
Layout Note:
Place near JDDRL.203,204
CD13
10U_0603_6.3V6M
@
CD13
10U_0603_6.3V6M
@
1
2
CD15
1U_0402_6.3V6K
CD15
1U_0402_6.3V6K
1
2
CD24
0.1U_0402_10V6K
CD24
0.1U_0402_10V6K
1
2
CD22
0.1U_0402_10V6K
CD22
0.1U_0402_10V6K
RD8
10K_0402_5%
RD8
10K_0402_5%
12
CD8
10U_0603_6.3V6M
CD8
10U_0603_6.3V6M
1
2
CD9
10U_0603_6.3V6M
CD9
10U_0603_6.3V6M
1
2
RD1
1K_0402_1%
RD1
1K_0402_1%
12
CD23
2.2U_0603_6.3V4Z
CD23
2.2U_0603_6.3V4Z
1
2
+
CD4
330U_B2_2.5VM_R15M
+
CD4
330U_B2_2.5VM_R15M
1
2
CD17
1U_0402_6.3V6K
CD17
1U_0402_6.3V6K
1
2
CD2
0.1U_0402_10V6K
CD2
0.1U_0402_10V6K
1
2
CD7
10U_0603_6.3V6M
CD7
10U_0603_6.3V6M
1
2
RD2
1K_0402_1%
RD2
1K_0402_1%
12
CD5
0.1U_0402_10V6K
CD5
0.1U_0402_10V6K
1
2
CD11
10U_0603_6.3V6M
CD11
10U_0603_6.3V6M
1
2
CD6
2.2U_0603_6.3V4Z
CD6
2.2U_0603_6.3V4Z
1
2
CD21
0.1U_0402_10V6K
CD21
0.1U_0402_10V6K
CD14
10U_0603_6.3V6M
@
CD14
10U_0603_6.3V6M
@
1
2
RD5
1K_0402_1%
RD5
1K_0402_1%
12
CD10
10U_0603_6.3V6M
CD10
10U_0603_6.3V6M
1
2
CD20
0.1U_0402_10V6K
CD20
0.1U_0402_10V6K
RD6
1K_0402_1%
RD6
1K_0402_1%
12
RD7
10K_0402_5%
RD7
10K_0402_5%
12
CD12
10U_0603_6.3V6M
CD12
10U_0603_6.3V6M
1
2
CD1
0.1U_0402_10V6K
CD1
0.1U_0402_10V6K
1
2
CD18
1U_0402_6.3V6K
CD18
1U_0402_6.3V6K
1
2
JDIMM1
TYCO_2-2013022-1
CONN@
JDIMM1
TYCO_2-2013022-1
CONN@
VREF_DQ
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DM0
11
VSS
13
DQ2
15
DQ3
17
VSS
19
DQ8
21
DQ9
23
VSS
25
DQS1#
27
DQS1
29
VSS
31
DQ10
33
DQ11
35
VSS
37
DQ16
39
VSS
2
DQ4
4
DQ5
6
VSS
8
DQS0#
10
DQS0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
RESET#
30
VSS
32
DQ14
34
DQ15
36
VSS
38
DQ20
40
DQ17
41
VSS
43
DQS2#
45
DQS2
47
VSS
49
DQ18
51
DQ19
53
VSS
55
DQ24
57
DQ25
59
VSS
61
DM3
63
VSS
65
DQ26
67
DQ27
69
VSS
71
CKE0
73
VDD
75
NC
77
BA2
79
VDD
81
A12/BC#
83
A9
85
VDD
87
A8
89
A5
91
VDD
93
A3
95
A1
97
VDD
99
CK0
101
CK0#
103
VDD
105
A10/AP
107
BA0
109
VDD
111
WE#
113
CAS#
115
VDD
117
A13
119
S1#
121
VDD
123
TEST
125
VSS
127
DQ32
129
DQ33
131
VSS
133
DQS4#
135
DQS4
137
VSS
139
DQ34
141
DQ35
143
VSS
145
DQ40
147
DQ41
149
VSS
151
DM5
153
VSS
155
DQ42
157
DQ43
159
VSS
161
DQ48
163
DQ49
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SA0
197
VDDSPD
199
DQ21
42
VSS
44
DM2
46
VSS
48
DQ22
50
DQ23
52
VSS
54
DQ28
56
DQ29
58
VSS
60
DQS3#
62
DQS3
64
VSS
66
DQ30
68
DQ31
70
VSS
72
CKE1
74
VDD
76
A15
78
A14
80
VDD
82
A11
84
A7
86
VDD
88
A6
90
A4
92
VDD
94
A2
96
A0
98
VDD
100
CK1
102
CK1#
104
VDD
106
BA1
108
RAS#
110
VDD
112
S0#
114
ODT0
116
VDD
118
ODT1
120
NC
122
VDD
124
VREF_CA
126
VSS
128
DQ36
130
DQ37
132
VSS
134
DM4
136
VSS
138
DQ38
140
DQ39
142
VSS
144
DQ44
146
DQ45
148
VSS
150
DQS5#
152
DQS5
154
VSS
156
DQ46
158
DQ47
160
VSS
162
DQ52
164
DQ53
166
VSS
168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60
180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
EVENT#
198
SDA
200
SA1
201
VTT
203
GND1
205
SCL
202
VTT
204
GND2
206
BOSS1
207
BOSS2
208
CD19
0.1U_0402_10V6K
CD19
0.1U_0402_10V6K
CD16
1U_0402_6.3V6K
CD16
1U_0402_6.3V6K
1
2
CD3
2.2U_0603_6.3V4Z
CD3
2.2U_0603_6.3V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SM_DRAMRST#
PCH_SMBCLK
PCH_SMBDATA
DDR_B_D36
DDR_B_D26
DDR_B_D63
DDR_B_D2
DDR_B_MA15
DDR_B_D5
DDR_B_D22
DDR_B_D25
DDR_B_DQS6
DDR_B_D35
DDR_B_D14
DDR_B_MA12
DDR_B_DQS#0
DDR_B_DQS4
DDR_B_DM6
DDR_B_D42
DDR_CKE3_DIMMB
DDR_B_D31
DDR_B_D12
DDR_CKE2_DIMMB
DDR_B_D59
DDR_B_D6
DDR_B_MA3
DDR_CS3_DIMMB#
DDR_B_D39
DDR_B_BS1
DDR_B_DQS0
DDR_B_WE#
DDR_B_MA7
DDR_B_MA0
DDR_B_DM2
DDR_B_DM1
DDR_B_DQS7
DDR_B_D0
DDR_B_D57
DDR_B_D46
DDR_B_D28
DDR_B_DM0
DDR_B_D19
DDR_B_DQS#5
DDR_B_D51
DDR_B_D4
DDR_B_DM4
DDR_B_D30
DDR_B_DQS2
DDR_B_D44
DDR_B_RAS#
DDR_B_D33
DDR_B_D58
DDR_B_DM5
DDR_B_DQS3
DDR_B_MA8
DDR_CS2_DIMMB#
DDR_B_D10
DDR_B_MA6
DDR_B_D27
DDR_B_D3
DDR_B_MA10
DDR_B_DQS#7
DDR_B_D1
DDR_B_DQS#6
DDR_B_D40
DDR_B_MA9
DDR_B_D16
DDR_B_D29
DDR_B_DQS#4
DDR_B_D52
DDR_B_DM3
DDR_B_DQS5
DDR_B_D54
DDR_B_D49
DDR_B_BS2
DDR_B_D45
DDR_B_D9
DDR_B_DM7
DDR_B_D7
DDR_B_MA1
DDR_B_D13
DDR_B_D20
DDR_B_D60
DDR_B_BS0
DDR_B_CAS# M_ODT2
DDR_B_D37
DDR_B_MA5
DDR_B_DQS#1
DDR_B_MA14
DDR_B_D55
DDR_B_MA4
DDR_B_D21
DDR_B_D62
DDR_B_D24
DDR_B_D15
DDR_B_D23
DDR_B_D56
DDR_B_D53
DDR_B_D47
DDR_B_D18
M_ODT3
DDR_B_D43
DDR_B_D34
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D48
DDR_B_DQS#2
DDR_B_D11
DDR_B_D38
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_DQS#3
DDR_B_D32
DDR_B_D8
DDR_B_DQS1
DDR_B_MA13
DDR_B_MA11
DDR_B_D50
DDR_B_D61
DDR_B_MA2
DDR_B_D41
DDR_B_D17
+VREF_CB
SM_DRAMRST# <7,12>
DDR_CKE3_DIMMB <7>
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <7>
M_ODT2 <7>
M_ODT3 <7>
DDR_B_BS2<7>
DDR_CKE2_DIMMB<7>
M_CLK_DDR2<7>
M_CLK_DDR#2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<7>
PCH_SMBDATA <12,15,40,43>
PCH_SMBCLK <12,15,40,43>
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..15]<7>
+VREF_CB
+0.75VS
+3VS
+1.5V +1.5V
+1.5V
+1.5V
+V_DDR_REFB
+1.5V
+0.75VS
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
DDRIII DIMMB
Custom
13 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
DDRIII DIMMB
Custom
13 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
DDRIII DIMMB
Custom
13 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Layout Note:
Place near JDIMM2.203 and 204
Layout Note:
Place near JDIMM2
Layout Note: Place these 4 Caps near
Command and Control signals of JDIMM2
RD11
1K_0402_1%
RD11
1K_0402_1%
12
CD32
10U_0603_6.3V6M
CD32
10U_0603_6.3V6M
1
2
CD42
1U_0402_6.3V6K
CD42
1U_0402_6.3V6K
1
2
CD30
10U_0603_6.3V6M
CD30
10U_0603_6.3V6M
1
2
CD37
0.1U_0402_10V6K
CD37
0.1U_0402_10V6K
CD43
1U_0402_6.3V6K
CD43
1U_0402_6.3V6K
1
2
CD34
10U_0603_6.3V6M
CD34
10U_0603_6.3V6M
1
2
RD12
1K_0402_1%
RD12
1K_0402_1%
12
CD44
1U_0402_6.3V6K
CD44
1U_0402_6.3V6K
1
2
JDIMM2
TYCO_2-2013287-1
CONN@
JDIMM2
TYCO_2-2013287-1
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
CD45
0.1U_0402_10V6K
CD45
0.1U_0402_10V6K
1
2
CD40
0.1U_0402_10V6K
CD40
0.1U_0402_10V6K
CD46
2.2U_0603_6.3V4Z
CD46
2.2U_0603_6.3V4Z
1
2
CD33
10U_0603_6.3V6M
CD33
10U_0603_6.3V6M
1
2
CD48
0.1U_0402_10V6K
CD48
0.1U_0402_10V6K
1
2
CD27
0.1U_0402_10V6K
CD27
0.1U_0402_10V6K
1
2
+
CD28
330U_B2_2.5VM_R15M
@
+
CD28
330U_B2_2.5VM_R15M
@
1
2
RD13
10K_0402_5%
RD13
10K_0402_5%
1 2
CD26
10U_0603_6.3V6M
CD26
10U_0603_6.3V6M
1
2
RD9
1K_0402_1%
RD9
1K_0402_1%
12
RD14
10K_0402_5%
RD14
10K_0402_5%
1 2
CD39
0.1U_0402_10V6K
CD39
0.1U_0402_10V6K
CD25
10U_0603_6.3V6M
@
CD25
10U_0603_6.3V6M
@
1
2
RD10
1K_0402_1%
RD10
1K_0402_1%
12
CD41
1U_0402_6.3V6K
CD41
1U_0402_6.3V6K
1
2
CD36
2.2U_0603_6.3V4Z
CD36
2.2U_0603_6.3V4Z
1
2
CD47
2.2U_0603_6.3V4Z
CD47
2.2U_0603_6.3V4Z
1
2
CD38
0.1U_0402_10V6K
CD38
0.1U_0402_10V6K
CD31
10U_0603_6.3V6M
CD31
10U_0603_6.3V6M
1
2
CD35
0.1U_0402_10V6K
CD35
0.1U_0402_10V6K
1
2
CD29
10U_0603_6.3V6M
@
CD29
10U_0603_6.3V6M
@
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCH_RTCX1
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
SM_INTRUDER# PCH_SPKR
PCH_SPI_CLK
PCH_SPI_MISO
PCH_SPI_CS0#
PCH_JTAG_TCK
PCH_SATALED#
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
HDA_RST_PCH#
HDA_SDIN0
HDA_SDOUT_PCH
PCH_GPIO21
PCH_RTCX2
HDA_BITCLK_PCH
LPC_AD2
LPC_FRAME#
LPC_AD0
LPC_AD3
LPC_AD1
SERIRQ
BBS_BIT0_R
SATA_COMP
RBIAS_SATA3
SATA3_COMP
HDA_BITCLK_PCH
HDA_RST_PCH#
HDA_SDOUT_PCH
PCH_INTVRMEN
PCH_SPKR
HDA_SDOUT_PCH
HDA_SYNC_PCH
HDA_SYNC_PCH_R
PCH_SPI_CLK_1
PCH_SPI_CS0#_1
PCH_SPI_MOSI_1
PCH_SPI_MISO_1
PCH_RTCX1
PCH_RTCX2
PCH_SRTCRST#
PCH_RTCRST#
SPI_WP1#
PCH_SPI_MISO_1
PCH_SPI_CS0#_1
SPI_HOLD1#
PCH_SPI_CLK_1
PCH_SPI_MOSI_1
PCH_SPI_CS1#_2 PCH_SPI_CS1#
PCH_SPI_MOSI
PCH_SPI_MOSI_2
PCH_SPI_MISO_2
PCH_SPI_CLK_2
PCH_SPI_MISO_2
PCH_SPI_CLK_2
PCH_SPI_MOSI_2
PCH_SPI_CS1#_2
SPI_WP2#
SPI_HOLD2#
PCH_SPI_CLK
PCH_JTAG_TDIPCH_JTAG_TDO PCH_JTAG_TMS
HDA_SYNC_PCHHDA_SYNC_PCH_R
SATA_PTX_DRX_N2
SATA_PTX_DRX_P2
SATA_PRX_C_DTX_P2
SATA_PRX_C_DTX_N2
SERIRQ
SATA_PTX_DRX_N4
SATA_PTX_DRX_P4
SATA_PRX_C_DTX_P4
SATA_PRX_C_DTX_N4
SATA_PTX_DRX_N0SATA_PTX_C_DRX_N0
SATA_PTX_DRX_P0SATA_PTX_C_DRX_P0
SATA_PRX_DTX_N0
SATA_PRX_DTX_P0
SATA_PTX_DRX_N1_R
SATA_PTX_DRX_P1_R
SATA_PRX_C_DTX_P1_R
SATA_PRX_C_DTX_N1_R
PCH_SPKR<31>
HDA_SDIN0<31>
SERIRQ <42>
LPC_AD0 <40,42>
LPC_AD1 <40,42>
LPC_AD2 <40,42>
LPC_AD3 <40,42>
LPC_FRAME# <40,42>
HDA_SYNC_AUDIO<31>
HDA_SDOUT_AUDIO<31>
HDA_RST_AUDIO#<31>
HDA_BITCLK_AUDIO<31>
ME_FLASH<42>
SATA_PTX_DRX_N4 <39>
SATA_PRX_C_DTX_N4 <39>
SATA_PTX_DRX_P4 <39>
SATA_PRX_C_DTX_P4 <39>
SATA_PTX_DRX_N0 <40>
SATA_PRX_DTX_N0 <40>
SATA_PTX_DRX_P0 <40>
SATA_PRX_DTX_P0 <40>
SATA_PTX_DRX_P1_R <38>
SATA_PTX_DRX_N1_R <38>
SATA_PRX_C_DTX_P1_R <38>
SATA_PRX_C_DTX_N1_R <38>
SATA_PTX_DRX_P2 <38>
SATA_PTX_DRX_N2 <38>
SATA_PRX_C_DTX_P2 <38>
SATA_PRX_C_DTX_N2 <38>
+RTCVCC
+1.05VS_VTT
+1.05VS_VTT
+3VS
+3V_PCH
+3V_PCH
+3VS
+RTCVCC
+3VS
+3VS
+3VS
+3VS
+3VS
+3V_PCH+3V_PCH +3V_PCH
+5VS
+RTCBATT+RTCVCC
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Custom
14 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Custom
14 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (1/9) SATA,HDA,SPI, LPC, XDP
Custom
14 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
H
Integrated VRM enable
L
Integrated VRM disable
INTVRMEN
*
LOW= Disable (Default internal PD)
HIGH= Enable ( No Reboot)Disable TCO timer system reboot feature
*
*
Low = Disabled (Default)
This signal has a weak internal pull-down
On Die PLL VR Select is supplied by
*
(INTVRMEN should always be pull high.)
ME debug mode,this signal has a weak internal PD
HDA_SDO
Boot BIOS
GPIO19
0
1
GPIO51
Boot BIOS Strap
0 0
1
0
SPI
-
Reserved
LPC
1 1
CLRP1/2 close RAM door JDIMM1/2
High = Enabled [Flash Descriptor Security Overide]
1.5V when sampled high
1.8V when sampled low
Needs to be pulled High for Huron River platfrom
*
SPI ROM FOR ME (4MB)
Footprint 200mil
SPI ROM FOR ME (2MB)
Footprint 200mil
Reserve for EMI
L=500mil S=15mil
L=500mil S=15mil
HDD for HM77
mSATA
HDD for HM70
Disable w/ HM70
Prevent back drive issue.
ODD
W=20mils W=20mils
R47 1K_0402_5%
R47 1K_0402_5%
12
R89 3.3K_0402_5%
R89 3.3K_0402_5%
1 2
R134
200_0402_5%
R134
200_0402_5%
12
CLRP1
SHORT PADS
CLRP1
SHORT PADS
1 2
R429 10K_0402_5%R429 10K_0402_5%
12
R440
750_0402_1%
R440
750_0402_1%
1 2
R75
33_0402_5%
R75
33_0402_5%
1 2
C441
1U_0603_10V4Z
C441
1U_0603_10V4Z
1
2
R142
100_0402_1%
R142
100_0402_1%
12
R88 3.3K_0402_5%WIN8@R88 3.3K_0402_5%WIN8@
1 2
U46
MX25L1606EM2I-12G_SO8
SA000041N00
WIN8@U46
MX25L1606EM2I-12G_SO8
SA000041N00
WIN8@
CS#
1
SO
2
WP#
3
GND
4
SI
5
SCLK
6
HOLD#
7
VCC
8
R29
1M_0402_5%
R29
1M_0402_5%
12
R356
20K_0402_5%
R356
20K_0402_5%
1 2
R48
0_0402_5%
@R48
0_0402_5%
@
1 2
R121
37.4_0402_1%
R121
37.4_0402_1%
1 2
R30
33_0402_5%
R30
33_0402_5%
1 2
R72
33_0402_5%
R72
33_0402_5%
1 2
R406
10M_0402_5%
R406
10M_0402_5%
1 2
R446 33_0402_5%WIN8@R446 33_0402_5%WIN8@
12
R123 33_0402_5%WIN8@R123 33_0402_5%WIN8@
12
R73
0_0402_5%
R73
0_0402_5%
1 2
R363 330K_0402_5%
R363 330K_0402_5%
1 2
R100
51_0402_5%
R100
51_0402_5%
12
R21 3.3K_0402_5%WIN8@R21 3.3K_0402_5%WIN8@
1 2
RTCIHDA
SATA
LPC
SPI
JTAG
SATA 6G
U13A
COUGARPOINT_FCBGA989
RTCIHDA
SATA
LPC
SPI
JTAG
SATA 6G
U13A
COUGARPOINT_FCBGA989
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED#
P3
FWH0 / LAD0
C38
FWH1 / LAD1
A38
FWH2 / LAD2
B37
FWH3 / LAD3
C37
LDRQ1# / GPIO23
K36
FWH4 / LFRAME#
D36
LDRQ0#
E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_EN# / GPIO33
C36
HDA_DOCK_RST# / GPIO13
N32
SRTCRST#
G22
SATA0RXN
AM3
SATA0RXP
AM1
SATA0TXN
AP7
SATA0TXP
AP5
SATA1RXN
AM10
SATA1RXP
AM8
SATA1TXN
AP11
SATA1TXP
AP10
SATA2RXN
AD7
SATA2RXP
AD5
SATA2TXN
AH5
SATA2TXP
AH4
SATA3RXN
AB8
SATA3RXP
AB10
SATA3TXN
AF3
SATA3TXP
AF1
SATA4RXN
Y7
SATA4RXP
Y5
SATA4TXN
AD3
SATA4TXP
AD1
SATA5RXN
Y3
SATA5RXP
Y1
SATA5TXN
AB3
SATA5TXP
AB1
SATAICOMPI
Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP / GPIO21
V14
SATA1GP / GPIO19
P1
JTAG_TCK
J3
JTAG_TMS
H7
JTAG_TDI
K5
JTAG_TDO
H1
SERIRQ
V5
SPKR
T10
SATAICOMPO
Y11
SATA3COMPI
AB13
SATA3RCOMPO
AB12
SATA3RBIAS
AH1
R136 10K_0402_5%R136 10K_0402_5%
12
R437 33_0402_5%
R437 33_0402_5%
12
C452
18P_0402_50V8J
C452
18P_0402_50V8J
1
2
U44
MX25L3206EM2I-12G_SO8
SA000041P00
U44
MX25L3206EM2I-12G_SO8
SA000041P00
CS#
1
SO
2
WP#
3
GND
4
SI
5
SCLK
6
HOLD#
7
VCC
8
R122 33_0402_5%
R122 33_0402_5%
12
C440
1U_0603_10V6K
C440
1U_0603_10V6K
1
2
R127 33_0402_5%
R127 33_0402_5%
12
Y2
32.768KHZ_12.5PF_9H03200019
Y2
32.768KHZ_12.5PF_9H03200019
1 2
R46
1K_0402_5%
@
R46
1K_0402_5%
@
1 2
R358 1M_0402_5%
R358 1M_0402_5%
1 2
G
D
S
Q3
BSS138_NL_SOT23-3
G
D
S
Q3
BSS138_NL_SOT23-3
2
13
R466 10K_0402_5%R466 10K_0402_5%
12
C127 0.01U_0402_16V7KC127 0.01U_0402_16V7K
12
R109 1K_0402_5%@
R109 1K_0402_5%@
1 2
R432 33_0402_5%
R432 33_0402_5%
12
R438 33_0402_5%WIN8@R438 33_0402_5%WIN8@
12
R143
200_0402_5%
R143
200_0402_5%
12
R137
200_0402_5%
R137
200_0402_5%
12
R434 33_0402_5%
@
R434 33_0402_5%
@
12
C131 0.01U_0402_16V7KC131 0.01U_0402_16V7K
12
C439
1U_0603_10V6K
C439
1U_0603_10V6K
1
2
R140
100_0402_1%
R140
100_0402_1%
12
R141
100_0402_1%
R141
100_0402_1%
12
C451
18P_0402_50V8J
C451
18P_0402_50V8J
1
2
C459
10P_0402_50V8J
@
C459
10P_0402_50V8J
@
1 2
R357
20K_0402_5%
R357
20K_0402_5%
1 2
R74
33_0402_5%
R74
33_0402_5%
1 2
R126
49.9_0402_1%
R126
49.9_0402_1%
1 2
R22 3.3K_0402_5%
R22 3.3K_0402_5%
1 2
CLRP2
SHORT PADS
CLRP2
SHORT PADS
12
R118
10K_0402_5%
R118
10K_0402_5%
12
R433 33_0402_5%WIN8@R433 33_0402_5%WIN8@
12
R59
1K_0402_5%
R59
1K_0402_5%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
PCH_SMBDATA_R
XTAL25_IN
XTAL25_OUT
PCH_SML1CLK
PCH_SML1DATA
XCLK_RCOMP
CLK_CPU_DMI
CLK_CPU_DMI#
PCIE_PTX_DRX_N2
PCIE_PTX_DRX_P1
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2
PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N1
PCIE_DTX_C_PRX_P1
PCIE_DTX_C_PRX_N1
CLK_PCIE_WLAN1_R
CLK_PCIE_WLAN1#_R
XTAL25_OUT
XTAL25_IN
DRAMRST_CNTRL_PCH
PCH_SML1CLK
PCH_SML1DATA
EC_SMB_CK2
EC_SMB_DA2
CLKIN_GND1#
CLKIN_GND1CLK_PCIE_LAN
CLK_PCIE_LAN#
PCH_GPIO11
PCH_SMBDATA_R
PCH_SML1CLK
PCH_SML1DATA
PCH_HOT#
PCH_HOT#
PCH_SMBDATA_R
CLK_BUF_CPU_DMI#
CLK_BUF_CPU_DMI
CLK_BUF_DREF_96M
CLK_BUF_DREF_96M#
CLK_BUF_PCIE_SATA
CLK_BUF_PCIE_SATA#
CLK_BUF_ICH_14M
CLK_PCI_LPBACK
DRAMRST_CNTRL_PCH
DGPU_PRSNT#
PCH_GPIO20
DGPU_PRSNT#
CLK_FLEX2
PEG_CLKREQ#_R
CLK_PCIE_VGA#
CLK_PCIE_VGA
PCH_SMBCLK_R
PCH_SMBCLK_R
PCH_SMBCLK_R
PCH_GPIO73
PCH_GPIO45
PCH_GPIO46
PCH_GPIO44
PCH_GPIO26
PCH_GPIO56
LAN_CLKREQ#
WLAN_CLKREQ#
PCH_SML0DATA
PCH_SML0CLK
PEG_CLKREQ#_R
CLK_CPU_DMI# <6>
CLK_CPU_DMI <6>
PCIE_DTX_C_PRX_N1<33>
PCIE_PTX_C_DRX_N1<33>
PCIE_DTX_C_PRX_P1<33>
PCIE_PTX_C_DRX_P1<33>
PCIE_PRX_DTX_N2<40>
PCIE_PRX_DTX_P2<40>
PCIE_PTX_C_DRX_N2<40>
PCIE_PTX_C_DRX_P2<40>
CLK_PCIE_WLAN1#<40>
CLK_PCIE_WLAN1<40>
WLAN_CLKREQ#<40>
CLK_PCI_LPBACK <18>
DRAMRST_CNTRL_PCH <7,10>
EC_SMB_CK2 <23,42,44>
EC_SMB_DA2 <23,42,44>
CLK_PCIE_LAN#<33>
CLK_PCIE_LAN<33>
LAN_CLKREQ#<33>
PCH_SMBDATA <12,13,40,43>
PCH_SMBCLK <12,13,40,43>
CLK_PCIE_VGA# <23>
CLK_PCIE_VGA <23>
PCH_HOT# <42>
PEG_CLKREQ# <23>
DGPU_PWR_EN <18,30,55>
+1.05VS_VTT
+3VS
+3V_PCH
+3VS
+3VS
+3VS
+3VS
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3V_PCH
+3VS
+3V_PCH
+3V_PCH
+3V_PCH
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (2/9) PCIE, SMBUS, CLK
Custom
15 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (2/9) PCIE, SMBUS, CLK
Custom
15 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (2/9) PCIE, SMBUS, CLK
Custom
15 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
PCIE LAN
WLAN
Reserve for EMI please close to PCH
WLAN
PCIE LAN
Pull up at EC side.
For VGA,EC,Thermal sensor
For DDR
GPIO67
0
1
DIS,Optimus
UMA
DGPU_PRSNT#
W=12mil S=15mil
HM70 not support
PCIE port 4-7
Pull high @ VGA side
Y6
25MHZ_10PF_7V25000014
Y6
25MHZ_10PF_7V25000014
GND
2
3
3
1
1
GND
4
R404
4.7K_0402_5%
R404
4.7K_0402_5%
12
C468
10P_0402_50V8J
C468
10P_0402_50V8J
1
2
R138 10K_0402_5%
R138 10K_0402_5%
1 2
R405 2.2K_0402_5%R405 2.2K_0402_5%
1 2
R420
10K_0402_5%
OPT@
R420
10K_0402_5%
OPT@
12
R110
10K_0402_5%
R110
10K_0402_5%
1 2
R443
1M_0402_5%
R443
1M_0402_5%
1 2
Q34B
DMN66D0LDW-7_SOT363-6
Q34B
DMN66D0LDW-7_SOT363-6
3 4
5
R421
10K_0402_5%
UMA@
R421
10K_0402_5%
UMA@
12
R392 10K_0402_5%R392 10K_0402_5%
1 2
R214
10K_0402_5%
R214
10K_0402_5%
1 2
C29
22P_0402_50V8J
@
C29
22P_0402_50V8J
@
1 2
R147 10K_0402_5%
R147 10K_0402_5%
1 2
R53
10K_0402_5%
R53
10K_0402_5%
1 2
R371
4.7K_0402_5%
R371
4.7K_0402_5%
12
Q34A
DMN66D0LDW-7_SOT363-6
Q34A
DMN66D0LDW-7_SOT363-6
6 1
2
C482 0.1U_0402_16V7KC482 0.1U_0402_16V7K
1 2
R403 2.2K_0402_5%R403 2.2K_0402_5%
1 2
R391 1K_0402_5%R391 1K_0402_5%
1 2
R51
10K_0402_5%
R51
10K_0402_5%
1 2
R369 2.2K_0402_5%R369 2.2K_0402_5%
1 2
T26 PAD@ T26 PAD@
R152 10K_0402_5%
R152 10K_0402_5%
1 2
R213
10K_0402_5%
R213
10K_0402_5%
1 2
C123
0.1U_0402_16V4Z
OPT@C123
0.1U_0402_16V4Z
OPT@
1 2
R101 10K_0402_5%
R101 10K_0402_5%
1 2
R33 10K_0402_5%R33 10K_0402_5%
12
R8
10K_0402_5%
OPT@ R8
10K_0402_5%
OPT@
12
R93 10K_0402_5%
R93 10K_0402_5%
1 2
R99 10K_0402_5%
R99 10K_0402_5%
1 2
R32
10K_0402_5%
R32
10K_0402_5%
1 2
Q33A
DMN66D0LDW-7_SOT363-6
Q33A
DMN66D0LDW-7_SOT363-6
6 1
2
R4082.2K_0402_5% R4082.2K_0402_5%
12
C478 0.1U_0402_16V7KC478 0.1U_0402_16V7K
1 2
R453 10K_0402_5%
R453 10K_0402_5%
1 2
R291 0_0402_5%R291 0_0402_5%
1 2
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
U13B
COUGARPOINT_FCBGA989
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
U13B
COUGARPOINT_FCBGA989
PERN1
BG34
PERP1
BJ34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ38
PERP6
BG38
PERN7
BG40
PERP7
BJ40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_DMI2_N
BJ30
CLKIN_DMI2_P
BG30
CLKIN_DMI_N
BF18
CLKIN_DMI_P
BE18
CLKIN_DOT_96N
G24
CLKIN_DOT_96P
E24
CLKIN_SATA_N / CKSSCD_N
AK7
CLKIN_SATA_P / CKSSCD_P
AK5
XTAL25_IN
V47
XTAL25_OUT
V49
REFCLK14IN
K45
CLKIN_PCILOOPBACK
H45
CLKOUT_PEG_A_N
AB37
CLKOUT_PEG_A_P
AB38
PEG_A_CLKRQ# / GPIO47
M10
PCIECLKRQ0# / GPIO73
J2
PCIECLKRQ1# / GPIO18
M1
PCIECLKRQ2# / GPIO20
V10
PCIECLKRQ3# / GPIO25
A8
PCIECLKRQ4# / GPIO26
L12
PCIECLKRQ5# / GPIO44
L14
CLKOUTFLEX0 / GPIO64
K43
CLKOUTFLEX1 / GPIO65
F47
CLKOUTFLEX2 / GPIO66
H47
CLKOUTFLEX3 / GPIO67
K49
CLKOUT_DMI_N
AV22
CLKOUT_DMI_P
AU22
PEG_B_CLKRQ# / GPIO56
E6
CLKOUT_PEG_B_P
AB40
CLKOUT_PEG_B_N
AB42
XCLK_RCOMP
Y47
CLKOUT_DP_P / CLKOUT_BCLK1_P
AM13
CLKOUT_DP_N / CLKOUT_BCLK1_N
AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
PCIECLKRQ7# / GPIO46
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AK14
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AK13
SMBALERT# / GPIO11
E12
SMBCLK
H14
SMBDATA
C9
SML0ALERT# / GPIO60
A12
SML0CLK
C8
SML0DATA
G12
SML1ALERT# / PCHHOT# / GPIO74
C13
SML1CLK / GPIO58
E14
SML1DATA / GPIO75
M16
CL_CLK1
M7
CL_DATA1
T11
CL_RST1#
P10
PCIECLKRQ6# / GPIO45
T13
R23
2.2K_0402_5%
@
R23
2.2K_0402_5%
@
12
Q33B
DMN66D0LDW-7_SOT363-6
Q33B
DMN66D0LDW-7_SOT363-6
3 4
5
R54
10K_0402_5%
R54
10K_0402_5%
1 2
R3732.2K_0402_5% R3732.2K_0402_5%
12
C480 0.1U_0402_16V7KC480 0.1U_0402_16V7K
1 2
R287 0_0402_5%R287 0_0402_5%
1 2
C481 0.1U_0402_16V7KC481 0.1U_0402_16V7K
1 2
R215 10K_0402_5%R215 10K_0402_5%
1 2
C457
10P_0402_50V8J
C457
10P_0402_50V8J
1
2
G
D
S
Q2
2N7002K_SOT23-3
OPT@
G
D
S
Q2
2N7002K_SOT23-3
OPT@
2
1 3
R50
10K_0402_5%
R50
10K_0402_5%
1 2
R139 10K_0402_5%
R139 10K_0402_5%
1 2
R27
10K_0402_5%
R27
10K_0402_5%
12
R96
33_0402_5%
@ R96
33_0402_5%
@
1 2
R370 2.2K_0402_5%R370 2.2K_0402_5%
1 2
R120
90.9_0402_1%
R120
90.9_0402_1%
12
R452 10K_0402_5%
R452 10K_0402_5%
1 2
R12
2.2K_0402_5%
@
R12
2.2K_0402_5%
@
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DMI_IRCOMP
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CRX_PTX_N2
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_P2
DMI_CTX_PRX_N1
DMI_CRX_PTX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CRX_PTX_N3
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC1
FDI_LSYNC0
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_CTX_PRX_P5
PCH_GPIO72
RI#
SUSACK#_R
DMI2RBIAS
SUSWARN#_R
PM_DRAM_PWRGD
PCH_RSMRST#
PBTN_OUT#_R
PCH_ACIN
DSWODVREN
PCH_PCIE_WAKE#
PM_SLP_S5#
PM_SLP_S4#
PM_SLP_S3#
SUS_STAT#
H_PM_SYNC
SUSCLK
ACIN
PCH_GPIO29
SYS_RST#
DSWODVREN
CLKRUN#SYS_PWROK
PCH_PWROK
VGATE
PCH_PWROK
PCH_PWROK_R
PM_DRAM_PWRGD
PCH_RSMRST#
PCH_GPIO72
SUSWARN#_R
RI#
SLP_A#
SYS_PWROK
SLP_SUS#
EC_RSMRST#
PBTN_OUT#
PCH_RSMRST#
PCH_GPIO29
PCH_PCIE_WAKE#
PCH_DPWROKSUSACK#
SUSWARN#
PCH_ACIN
DMI_CTX_PRX_N0<5>
DMI_CRX_PTX_N2<5>
DMI_CTX_PRX_N1<5>
DMI_CTX_PRX_N3<5>
DMI_CTX_PRX_N2<5>
DMI_CTX_PRX_P0<5>
DMI_CTX_PRX_P1<5>
DMI_CTX_PRX_P3<5>
DMI_CTX_PRX_P2<5>
DMI_CRX_PTX_N3<5>
DMI_CRX_PTX_N1<5>
DMI_CRX_PTX_N0<5>
DMI_CRX_PTX_P2<5>
DMI_CRX_PTX_P3<5>
DMI_CRX_PTX_P1<5>
DMI_CRX_PTX_P0<5>
FDI_CTX_PRX_N0 <5>
FDI_CTX_PRX_N1 <5>
FDI_CTX_PRX_N2 <5>
FDI_CTX_PRX_N3 <5>
FDI_CTX_PRX_N4 <5>
FDI_CTX_PRX_N5 <5>
FDI_CTX_PRX_N6 <5>
FDI_CTX_PRX_N7 <5>
FDI_CTX_PRX_P0 <5>
FDI_CTX_PRX_P1 <5>
FDI_CTX_PRX_P2 <5>
FDI_CTX_PRX_P3 <5>
FDI_CTX_PRX_P4 <5>
FDI_CTX_PRX_P5 <5>
FDI_CTX_PRX_P6 <5>
FDI_CTX_PRX_P7 <5>
FDI_FSYNC1 <5>
FDI_LSYNC0 <5>
FDI_FSYNC0 <5>
FDI_INT <5>
FDI_LSYNC1 <5>
PM_DRAM_PWRGD<6>
ACIN<23,42,50>
PCH_PCIE_WAKE# <33,40>
H_PM_SYNC <6>
PM_SLP_S3# <42>
PM_SLP_S4# <42>
PM_SLP_S5# <42>
SUSCLK <42>
PCH_PWROK<42>
VGATE<56>
SYS_PWROK <6>
EC_RSMRST#<42>
PBTN_OUT#<42>
SUSACK#<42>
SUSWARN#<42>
AC_PRESENT<42>
SLP_SUS# <42>
+1.05VS_VTT
+RTCVCC
+3VS
+3V_PCH
+3VS
+3V_PCH
+3VS
+3V_PCH
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (3/9) DMI,FDI,PM
Custom
16 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (3/9) DMI,FDI,PM
Custom
16 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (3/9) DMI,FDI,PM
Custom
16 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
4mil width and place
within 500mil of the PCH
Can be left NC when IAMT is not
support on the platfrom
*
not support AMT APWROK can mux
with PWROK (check list1.5 P.47)
L
Disable
Must always PH at +RTCVCC
DSWODVREN - On Die DSW VR Enable
H
Enable internal DSW +1.05VS
ALL power OK
tell PCH all power ok
but cpu core
No use ,PH 10K +3VALW
No use ,PH 10K +3VALW
Ring Indicator CRB1.0 PH 10K +3VALW
Follow G
L=500mil S=15mil
C52
0.047U_0402_16V7K
@
C52
0.047U_0402_16V7K
@
1
2
R129
0_0402_5%
R129
0_0402_5%
1 2
D3 RB751V-40_SOD323-2D3 RB751V-40_SOD323-2
1 2
R104
10K_0402_5%
R104
10K_0402_5%
12
U36
MC74VHC1G08DFT2G_SC70-5
U36
MC74VHC1G08DFT2G_SC70-5
B
2
A
1
Y
4
P
5
G
3
R26
200K_0402_5%
R26
200K_0402_5%
1 2
R270 0_0402_5%
DSP3@
R270 0_0402_5%
DSP3@
1 2
R368 330K_0402_5%@R368 330K_0402_5%@
1 2
R49 10K_0402_5%R49 10K_0402_5%
1 2
R390 10K_0402_5%
R390 10K_0402_5%
1 2
R374
10K_0402_5%
R374
10K_0402_5%
12
DMI
FDI
System Power Management
U13C
COUGARPOINT_FCBGA989
DMI
FDI
System Power Management
U13C
COUGARPOINT_FCBGA989
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ18
DMI3RXP
BJ20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ24
DMI_IRCOMP
BG25
FDI_RXN0
BJ14
FDI_RXN1
AY14
FDI_RXN2
BE14
FDI_RXN3
BH13
FDI_RXN4
BC12
FDI_RXN5
BJ12
FDI_RXN6
BG10
FDI_RXN7
BG9
FDI_RXP0
BG14
FDI_RXP1
BB14
FDI_RXP2
BF14
FDI_RXP3
BG13
FDI_RXP4
BE12
FDI_RXP5
BG12
FDI_RXP6
BJ10
FDI_RXP7
BH9
FDI_FSYNC0
AV12
FDI_FSYNC1
BC10
FDI_LSYNC0
AV14
FDI_LSYNC1
BB10
FDI_INT
AW16
PMSYNCH
AP14
SLP_SUS#
G16
SLP_S3#
F4
SLP_S4#
H4
SLP_S5# / GPIO63
D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE#
B9
SUS_STAT# / GPIO61
G8
SUSCLK / GPIO62
N14
ACPRESENT / GPIO31
H20
BATLOW# / GPIO72
E10
PWROK
L22
CLKRUN# / GPIO32
N3
SUSWARN# / SUS_PWR_DN_ACK / GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN# / GPIO29
K14
APWROK
L10
DPWROK
E22
DMI2RBIAS
BH21
SLP_A#
G10
DSWVRMEN
A18
SUSACK#
C12
T4
PAD
@
T4
PAD
@
R125
0_0402_5%
R125
0_0402_5%
1 2
R359 330K_0402_5%
R359 330K_0402_5%
12
R36
10K_0402_5%
@ R36
10K_0402_5%
@
12
R423
8.2K_0402_5%
R423
8.2K_0402_5%
12
R393 300_0402_5%R393 300_0402_5%
1 2
R107
0_0402_5%
R107
0_0402_5%
1 2
T1
PAD
@
T1
PAD
@
R15649.9_0402_1%
R15649.9_0402_1%
1 2
R271 0_0402_5%
DSP3@
R271 0_0402_5%
DSP3@
1 2
R155750_0402_1%
R155750_0402_1%
1 2
R263
0_0402_5%
@R263
0_0402_5%
@
1 2
R133
0_0402_5%
R133
0_0402_5%
1 2
R34 10K_0402_5%R34 10K_0402_5%
1 2
R119
100K_0402_5%
R119
100K_0402_5%
12
R394 10K_0402_5%R394 10K_0402_5%
12
R415
10K_0402_5%
R415
10K_0402_5%
1 2
R153 100K_0402_5%
@
R153 100K_0402_5%
@
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
CTRL_CLK
CTRL_DATA
LVDS_IBG
TMDS_B_HPD#
LVDS_A1#
LVDS_A2#
LVDS_A0
LVDS_A2
LVDS_A0#
LVDS_A1
LVDS_ACLK#
LVDS_ACLK
CRT_IREF
PCH_ENVDD
PCH_PWM
EDID_CLK
EDID_DATA
EDID_CLK
EDID_DATA
CTRL_CLK
CTRL_DATA PCH_HDMIDAT
PCH_HDMICLK
TMDS_B_CLK#_PCH
TMDS_B_CLK_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA0_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
PCH_CRT_DATA
PCH_CRT_CLK
PCH_CRT_HSYNC
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_CRT_VSYNC
LVDS_B1#
LVDS_B2#
LVDS_B0
LVDS_B2
LVDS_B0#
LVDS_B1
LVDS_BCLK#
LVDS_BCLK
PCH_ENBKL
PCH_CRT_CLK
PCH_CRT_DATA
PCH_CRT_B
PCH_CRT_G
PCH_CRT_R
PCH_HDMICLK <37>
PCH_HDMIDAT <37>
TMDS_B_HPD# <37>
LVDS_ACLK#<35>
LVDS_ACLK<35>
LVDS_A0#<35>
LVDS_A1#<35>
LVDS_A2#<35>
LVDS_A0<35>
LVDS_A1<35>
LVDS_A2<35>
PCH_ENVDD<35>
PCH_PWM<35>
EDID_CLK<35>
PCH_ENBKL<35>
EDID_DATA<35>
HDMI_CLK+_CK <37>
HDMI_CLK-_CK <37>
HDMI_TX0+_CK <37>
HDMI_TX0-_CK <37>
HDMI_TX1+_CK <37>
HDMI_TX1-_CK <37>
HDMI_TX2+_CK <37>
HDMI_TX2-_CK <37>
PCH_CRT_CLK<36>
PCH_CRT_DATA<36>
PCH_CRT_R<36>
PCH_CRT_G<36>
PCH_CRT_B<36>
PCH_CRT_HSYNC<36>
PCH_CRT_VSYNC<36>
LVDS_BCLK#<35>
LVDS_BCLK<35>
LVDS_B0#<35>
LVDS_B1#<35>
LVDS_B2#<35>
LVDS_B0<35>
LVDS_B1<35>
LVDS_B2<35>
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (4/9) LVDS,CRT,DP,HDMI
Custom
17 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (4/9) LVDS,CRT,DP,HDMI
Custom
17 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (4/9) LVDS,CRT,DP,HDMI
Custom
17 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
HDMI D2
HDMI D1
HDMI D0
HDMI CLK
HDMI
Place close to Connector side(0210)
C536 0.1U_0402_10V6KHDMI@ C536 0.1U_0402_10V6KHDMI@
1 2
R193
150_0402_1%
R193
150_0402_1%
12
R192
150_0402_1%
R192
150_0402_1%
12
R194
150_0402_1%
R194
150_0402_1%
12
R144
2.2K_0402_5%
HDMI@
R144
2.2K_0402_5%
HDMI@
12
R196 2.2K_0402_5%R196 2.2K_0402_5%
1 2
R191 2.2K_0402_5%R191 2.2K_0402_5%
1 2
R108 2.2K_0402_5%R108 2.2K_0402_5%
1 2
C406 0.1U_0402_10V6KHDMI@ C406 0.1U_0402_10V6KHDMI@
1 2
C534 0.1U_0402_10V6KHDMI@ C534 0.1U_0402_10V6KHDMI@
1 2
C537 0.1U_0402_10V6KHDMI@ C537 0.1U_0402_10V6KHDMI@
1 2
R105 2.2K_0402_5%R105 2.2K_0402_5%
1 2
C535 0.1U_0402_10V6KHDMI@ C535 0.1U_0402_10V6KHDMI@
1 2
LVDS
Digital Display Interface
CRT
U13D
COUGARPOINT_FCBGA989
LVDS
Digital Display Interface
CRT
U13D
COUGARPOINT_FCBGA989
L_BKLTCTL
P45
L_BKLTEN
J47
L_CTRL_CLK
T45
L_CTRL_DATA
P39
L_DDC_CLK
T40
L_DDC_DATA
K47
L_VDD_EN
M45
LVDSA_CLK#
AK39
LVDSA_CLK
AK40
LVDSA_DATA#0
AN48
LVDSA_DATA#1
AM47
LVDSA_DATA#2
AK47
LVDSA_DATA#3
AJ48
LVDSA_DATA0
AN47
LVDSA_DATA1
AM49
LVDSA_DATA2
AK49
LVDSA_DATA3
AJ47
LVDSB_CLK#
AF40
LVDSB_CLK
AF39
LVDSB_DATA#0
AH45
LVDSB_DATA#1
AH47
LVDSB_DATA#2
AF49
LVDSB_DATA#3
AF45
LVDSB_DATA0
AH43
DDPB_0N
AV42
DDPB_1N
AV45
LVD_VREFH
AE48
LVD_VREFL
AE47
DDPD_2N
BF42
DDPD_3N
BJ42
DDPB_2N
AU48
DDPB_3N
AV47
DDPC_0N
AY47
DDPC_1N
AY43
DDPC_2N
BA47
DDPC_3N
BB47
DDPD_0N
BB43
DDPD_1N
BF44
DDPB_0P
AV40
DDPB_1P
AV46
DDPD_2P
BE42
DDPD_3P
BG42
DDPB_2P
AU47
DDPB_3P
AV49
LVDSB_DATA1
AH49
LVDSB_DATA2
AF47
LVDSB_DATA3
AF43
LVD_IBG
AF37
LVD_VBG
AF36
DDPC_1P
AY45
DDPC_0P
AY49
DDPC_2P
BA48
DDPC_3P
BB49
DDPD_0P
BB45
DDPD_1P
BE44
CRT_BLUE
N48
CRT_DDC_CLK
T39
CRT_DDC_DATA
M40
CRT_GREEN
P49
CRT_HSYNC
M47
CRT_IRTN
T42
CRT_RED
T49
CRT_VSYNC
M49
DAC_IREF
T43
SDVO_CTRLCLK
P38
SDVO_CTRLDATA
M39
DDPC_CTRLCLK
P46
DDPC_CTRLDATA
P42
DDPD_CTRLCLK
M43
DDPD_CTRLDATA
M36
DDPB_AUXN
AT49
DDPC_AUXN
AP47
DDPD_AUXN
AT45
DDPB_AUXP
AT47
DDPC_AUXP
AP49
DDPD_AUXP
AT43
DDPB_HPD
AT40
DDPC_HPD
AT38
DDPD_HPD
BH41
SDVO_TVCLKINP
AP45
SDVO_TVCLKINN
AP43
SDVO_STALLP
AM40
SDVO_STALLN
AM42
SDVO_INTP
AP40
SDVO_INTN
AP39
R114
1K_0402_0.5%
R114
1K_0402_0.5%
12
C539 0.1U_0402_10V6KHDMI@ C539 0.1U_0402_10V6KHDMI@
1 2
R131
2.2K_0402_5%
HDMI@
R131
2.2K_0402_5%
HDMI@
12
R132
2.37K_0402_1%
R132
2.37K_0402_1%
12
C538 0.1U_0402_10V6KHDMI@ C538 0.1U_0402_10V6KHDMI@
1 2
R195 2.2K_0402_5%R195 2.2K_0402_5%
1 2
C352 0.1U_0402_10V6KHDMI@ C352 0.1U_0402_10V6KHDMI@
1 2
R190 2.2K_0402_5%R190 2.2K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USBRBIAS
PCH_PLTRST#
PCI_PME#
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQC#
PCI_PIRQB#
PCH_ODD_DA#
PCH_GPIO4
CLK_PCI0
CLK_PCI1
USB20_P0
USB20_N0
USB_OC7#
USB_OC4#
USB_OC5#
USB_OC6#
USB_OC3#
USB_OC1#
USB_OC0#
USB_OC2#
DF_TVS
PCH_GPIO53
DF_TVS
CLK_PCI_LPBACK
CLK_PCI_EC
PCH_GPIO2
USB_OC4#
USB_OC3#
USB_OC1#
USB_OC2#
USB20_N8
USB20_P8
USB20_N10
USB20_P10
PCH_PLTRST#
DGPU_HOLD_RST#
DGPU_HOLD_RST#
PCH_GPIO53
PCH_GPIO5
DGPU_PWR_EN2
PCH_GPIO5
USB_OC7#
USB_OC5#
PCI_PIRQC#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQD#
PCH_GPIO2
PCH_ODD_DA#
USB_OC0#
PCH_GPIO51
PCH_WL_OFF#
PCH_WL_OFF#
PCH_GPIO51
USB3_TX1_P
USB3_RX1_P
USB3_TX1_N
USB3_RX1_N
USB_OC6#
USB20_N9
USB20_P9
CLK_PCI2
DGPU_HOLD_RST#
DGPU_PWR_EN1
DGPU_PWR_EN2
USB20_N3
USB20_P3
USB20_P11
USB20_N11
USB20_N1
USB20_P1
PCH_WL_OFF#
DGPU_PWR_EN2NVDD_PWR_EN
DGPU_PWR_EN1
PCH_GPIO4
CLK_PCI_DB
USB20_N0 <45>
USB20_P0 <45>
H_SNB_IVB# <6>
DGPU_RST# <23>
CLK_PCI_LPBACK<15>
CLK_PCI_EC<42>
USB20_N8 <35>
USB20_P8 <35>
USB20_N10 <40>
USB20_P10 <40>
PCH_PLTRST#<6>
PLT_RST# <33,40,42>
USB3_TX1_P<45>
USB_OC0# <45,46>
USB3_RX1_P<45>
USB3_TX1_N<45>
USB3_RX1_N<45>
USB_OC1# <46>
USB20_N9 <43>
USB20_P9 <43>
CLK_PCI_DB<40>
DGPU_PWR_EN<15,30,55>
NVDD_PWR_EN<55>
PCH_WL_OFF#<40>
PCI_PME#<42>
USB20_N3 <46>
USB20_P3 <46>
USB20_N11 <46>
USB20_P11 <46>
USB20_N1 <46>
USB20_P1 <46>
PCH_ODD_DA#<39>
+3VS
+3VS
+1.8VS
+3V_PCH
+3VS
+3V_PCH
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (5/9) PCI, USB, NVRAM
Custom
18 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (5/9) PCI, USB, NVRAM
Custom
18 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-8971P
0.1
PCH (5/9) PCI, USB, NVRAM
Custom
18 58Wednesday, February 15, 2012
2011/06/24 2012/07/12
Compal Electronics, Inc.
Set to Vcc when HIGH
DMI,FDI Termination Voltage
DF_TVS
Set to Vss when LOW
USB3 (Left side)
CLOSE TO THE BRANCHING POINT
CMOS Camera (LVDS)
Mini Card (WLAN)
Bit11
GNT1#/
GPIO51
Internal
PH
Boot BIOS Strap
Bit10
0 1
Boot BIOS
Destination
Reserved
PCI
SPI
LPC
HM70 not support USB port 4,5,6,7,12,13
CR Check list P.89 PH 2.2K series 1K
EHCI 1
EHCI 2
PCI Interrupt Requests
GPIO51GPIO19
*
1
1 1
0
00
USB3.0
L=500mil S=15mil
Card Reader
Bluetooth
CR CPU PD
HR CPU NC
USB2 (Right side)
USB2 (Right side)
RP3
10K_1206_8P4R_5%
RP3
10K_1206_8P4R_5%
1 8
2 7
3 6
4 5
U25
MC74VHC1G08DFT2G_SC70-5
@U25
MC74VHC1G08DFT2G_SC70-5
@
B
2
A
1
Y
4
P
5
G
3
R417 22_0402_5%
R417 22_0402_5%
1 2
R41
8.2K_0402_5%
@ R41
8.2K_0402_5%
@
12
R11
100K_0402_5%
R11
100K_0402_5%
12
R56 0_0402_5%OPT@R56 0_0402_5%OPT@
12
C149
0.1U_0402_16V4Z
@
C149
0.1U_0402_16V4Z
@
1
2
R399
22.6_0402_1%
R399
22.6_0402_1%
1 2
RSVD
NVRAM
PCI
USB
U13E
COUGARPOINT_FCBGA989
RSVD
NVRAM
PCI
USB
U13E
COUGARPOINT_FCBGA989
NV_ALE
AV5
NV_CE#0
AY7
NV_CE#1
AV7
NV_CE#2
AU3
NV_CE#3
BG4
NV_CLE
AY1
NV_DQS0
AT10
NV_DQS1
BC8
NV_DQ0 / NV_IO0
AU2
NV_DQ1 / NV_IO1
AT4
NV_DQ10 / NV_IO10
BB5
NV_DQ11 / NV_IO11
BB3
NV_DQ12 / NV_IO12
BB7
NV_DQ13 / NV_IO13
BE8
NV_DQ14 / NV_IO14
BD4
NV_DQ15 / NV_IO15
BF6
NV_DQ2 / NV_IO2
AT3
NV_DQ3 / NV_IO3
AT1
NV_DQ4 / NV_IO4
AY3
NV_DQ5 / NV_IO5
AT5
NV_DQ6 / NV_IO6
AV3
NV_DQ7 / NV_IO7
AV1
NV_DQ8 / NV_IO8
BB1
NV_DQ9 / NV_IO9
BA3
NV_RB#
AT8
NV_RCOMP
AV10
NV_RE#_WRB0
AY5
NV_RE#_WRB1
BA2
NV_WE#_CK0
AT12
NV_WE#_CK1
BF3
PIRQA#
K40
PIRQB#
K38
PIRQC#
H38
PIRQD#
G38
REQ1# / GPIO50
C46
REQ2# / GPIO52
C44
REQ3# / GPIO54
E40
GNT1# / GPIO51
D47
GNT2# / GPIO53
E42
GNT3# / GPIO55
F46
PIRQE# / GPIO2
G42
PIRQF# / GPIO3
G40
PIRQG# / GPIO4
C42
PIRQH# / GPIO5
D44
USBP0N
C24
USBP0P
A24
USBP1N
C25
USBP1P
B25
USBP2N
C26
USBP2P
A26
USBP3N
K28
USBP3P
H28
USBP4N
E28
USBP4P
D28
USBP5N
C28
USBP5P
A28
USBP6N
C29
USBP6P
B29
USBP7N
N28
USBP7P
M28
USBP8N
L30
USBP8P
K30
USBP9N
G30
USBP9P
E30
USBP10N
C30
USBP10P
A30
USBP11N
L32
USBP11P
K32
USBP12N
G32
USBP12P
E32
USBP13N
C32
USBP13P
A32
PME#
K10
CLKOUT_PCI0
H49
CLKOUT_PCI1
H43
CLKOUT_PCI2
J48
USBRBIAS#
C33
USBRBIAS
B33
OC0# / GPIO59
A14
OC1# / GPIO40
K20
OC2# / GPIO41
B17
OC3# / GPIO42
C16
OC4# / GPIO43
L16
OC5# / GPIO9
A16
OC6# / GPIO10
D14
OC7# / GPIO14
C14
CLKOUT_PCI4
H40
CLKOUT_PCI3
K42
PLTRST#
C6
TP1
BG26
TP2
BJ26
TP3
BH25
TP6
AH38
TP7
AH37
TP8
AK43
TP9
AK45
TP16
Y13
TP17
K24
TP18
L24
TP19
AB46
TP20
AB45
TP21
B21
TP22
M20
TP23
AY16
TP25
BE28
TP26
BC30
TP27
BE32
TP28
BJ32
TP29
BC28
TP30
BE30
TP31
BF32
TP32
BG32
TP33
AV26
TP34
BB26
TP35
AU28
TP36
AY30
TP37
AU26
TP38
AY26
TP39
AV28
TP40
AW30
TP4
BJ16
TP5
BG16
TP15
AM5
TP14
AM4
TP13
AH12
TP12
H3
TP11
N30
TP10
C18
TP24
BG46
R57 0_0402_5%OPT@R57 0_0402_5%OPT@
12
R25
1K_0402_5%
@
R25
1K_0402_5%
@
12
R162 22_0402_5%@R162 22_0402_5%@
1 2
R395
8.2K_1206_8P4R_5%
R395
8.2K_1206_8P4R_5%
18
27
36
45
R90
8.2K_1206_8P4R_5%
R90
8.2K_1206_8P4R_5%
18
27
36
45
R377
10K_0402_5%
R377
10K_0402_5%
12
R367
10K_0402_5%
R367
10K_0402_5%
12
R218
0_0402_5%
@
R218
0_0402_5%
@
12
R409
8.2K_1206_8P4R_5%
R409
8.2K_1206_8P4R_5%
18
27
36
45
R307
10K_0402_5%
@
R307
10K_0402_5%
@
12
R145
2.2K_0402_5%
R145
2.2K_0402_5%
12
R401
8.2K_0402_5%
R401
8.2K_0402_5%
1 2
R84 22_0402_5%
R84 22_0402_5%
1 2
R24
10K_0402_5%
R24
10K_0402_5%
12
R6
100_0402_5%
OPT@R6
100_0402_5%
OPT@
1 2
R3
100K_0402_5%
OPT@
R3
100K_0402_5%
OPT@
12
R66
8.2K_0402_5%
R66
8.2K_0402_5%
1 2
R146
1K_0402_5%
R146
1K_0402_5%
12
R10
0_0402_5%
R10
0_0402_5%
12
R410
8.2K_0402_5%
R410
8.2K_0402_5%
1 2
R378
10K_0402_5%
R378
10K_0402_5%
12
U29
MC74VHC1G08DFT2G_SC70-5
OPT@
U29
MC74VHC1G08DFT2G_SC70-5
OPT@
B
2
A
1
Y
4
P
5
G
3
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