LA-7902P QXW10 Korbel 15 UMA
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Cover Sheet
1 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Cover Sheet
1 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Cover Sheet
1 61Wednesday, March 07, 2012
Compal Electronics, Inc.
BOM P/N :
PCB NO :
COMPAL CONFIDENTIAL
MODEL NAME :
Korbel 15 UMA
REV : 1.0 (A00)
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
@ : Nopop Component
2012-03-07
1@
MB Type
TPM(R1)
BOM P/N
TPM DIS(R1) 2@
3@
3@
CONN@ : Connector Component
Ivy/Sandy Bridge + Panther POINT(HM77 w/o Vpro,/QM77 w/Vpro)
LA-7902P (DA60000PV00 )
4319F831L01
GPIO MAP: E4_VC_GPIO_map_rev_1.1
4319F831L01
QXW10
HM77 w/o Vpro
QM77 w/ Vpro
PXDP@PCH XDP
46@HDMI LOGO
*
*
5@
TPM DIS(R3)
TPM(R3) 5@1@
2@
3@
3@
4319F831L02
4319F831L03
4319F831L04
Part Number Description
DA60000PV00
PCB 0LH LA-7902P REV0 M/B UMA
MB PCB
Part Number Description
DA60000PV00
PCB 0LH LA-7902P REV0 M/B UMA
MB PCB
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
UMA Block Diagram
2 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
UMA Block Diagram
2 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
UMA Block Diagram
2 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
USB 3.0 Port
Block Diagram
USB2.0 [3,7]
SATA5
DOCK LAN
DAI
DOCKING PORT
VGA
VGA
LVDS
PI3V713-AZLEX
Video Switch
CRT CONN
1333/1600 MHz
USB5USB4
100MHz
W25Q32BVSSIG
64M 4K sector
100MHz
PCI Express BUS
on IO/Audio board
on Audio board
On IO board
LVDS CONN
PCI Express BUS
PCIE 6
MDC
HD Audio I/F
WWAN
Combo Jack RJ45
S-ATA 0/1 6GB/s, S-ATA 2/3/4/5 3GB/s
1/2 Mini Card
WiFi ON/OFF
PCH XDP Port
CPU XDP Port
DC/DC Interface
Memory BUS (DDR3)
LED
BANK 0, 1, 2, 3, 4 ,5 ,6 ,7
DDRIII-DIMM X2
KB CONN
1/2 Mini Card
TP CONN
Lane x 8
FDI
32M 4K sector
HDD
ODD
Dig.
MIC
Through LVDS Cable
INT.Speaker
PCIE1PCIE3
Lane x 4
USB6
PCIE5
92HD93
HDA Codec
USB10
Through LVDS Cable
Camera
USB
RJ11
LAN SWITCH
PI3L720
BCM5761
BROADCOM
PCIE2
E-SATA
Smart
/Express
Card
BT 4.0
SDXC/MMC
OZ600FJ0
Card Reader
SPI
To Docking side
rPGA CPU
INTEL
DMI2
Ivy/Sandy Bridge
BGA
Panther POINT-M
DAI
DOCK LAN
Full Mini Card
WLAN/WiFi
HDMI CONN
DPC
DPD
DPB
For MB/DOCK
VGA
USB3.0 [4]
W25Q64CVSSIGPP
FFS LNG3DM
pg6~11
pg12~13
pg23
pg38
pg24
pg33
pg33
pg14~21
pg34pg34pg34pg35
pg7
pg14
pg42
pg43
pg41 pg41
pg28
pg14
pg14 pg27
pg27
pg29
pg36
USB 2.0 Port
USB 3.0 Port
USB3.0[2]
USB2.0[0,9]
USB2.0[11]
USB2.0[12]
SATA[4]
USB2.0
pg41
pg24
pg36
pg30,31
pg29
pg30
pg37
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
pg25
USB2.0[2]
USB2.0[1]
USB 2.0 Port
USB3.0[3]
pg37
USB2.0[13]
pg41
Fingerprint CONN
pg22
pg39
pg40
pg22
EMC4021
ECE5048
PWM FAN
SMSC SIO
BC BUS
SMSC KBC
MEC5055
pg32
Discrete TPM
AT97SC3204
33MHz
LPC BUS
on IO board
Through Cable
on IO board
pg37
pg37
pg37
pg37
HM77/QM77
PCIE7
pg32
33MHz
LPC BUS
China TCM1.2
SSX44B
Option
Sigle.
MIC
on PWR board
DMIC0
DMIC1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Index and Config.
3 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Index and Config.
3 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Index and Config.
3 61Wednesday, March 07, 2012
Compal Electronics, Inc.
PM TABLE
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
MINI CARD-2 WLAN
PCI EXPRESS
Lane 1
DESTINATION
Lane 2
Lane 3
Lane 4
MINI CARD-1 WWAN
POWER STATES
Lane 5
Lane 6
Express card
MMI
+3.3V_M +3.3V_M
(M-OFF)
ON
ON
ON
ON
OFF
OFF
OFFOFF
+3.3V_SUS
+5V_ALW
+5V_RUN
+3.3V_ALW_PCH
+1.5V_MEM
S0
S3
S5 S4/AC don't exist
ON
power
plane
S5 S4/AC
State
OFFON
ON
ON
ON ON
OFF
OFF
OFF
OFFOFF
+15V_ALW
+3.3V_RTC_LDO
+1.05V_M
Lane 7
Lane 8 None
10/100/1G LOM
+1.05V_M
+1.8V_RUN
+1.05V_RUN_VTT
+3.3V_RUN
+0.75V_DDR_VTT
+1.5V_RUN
+VCC_CORE
+1.05V_RUN
1/2vMINI CARD-3 PCIE
need to update Power Status and PM
Table
OFF
OFF
OFF
LOW
LOW
OFF
OFF
S0 (Full ON) / M0
SLP
S3#
SLP
S5#
HIGH
Signal
State
SLP
S4#
HIGH HIGH
ALWAYS
PLANE
ON
M
PLANE
ON
SUS
PLANE
RUN
PLANE
CLOCKS
ON ON ON
S3 (Suspend to RAM) / M3 LOW HIGH HIGH ON ON ON OFF
S4 (Suspend to DISK) / M3 ON ON OFF
SLP
A#
HIGH
HIGH
LOW HIGH HIGH
S5 (SOFT OFF) / M3 ON ON OFFLOW HIGHLOW
S3 (Suspend to RAM) / M-OFF
S5 (SOFT OFF) / M-OFF
LOW HIGH HIGH LOW ON ONOFF OFF OFF
LOW LOW LOW ON OFF OFF OFF OFF
LOW LOW LOW LOW ON OFF OFF OFF OFF
S4 (Suspend to DISK) / M-OFF HIGH
DOCKING
JESA1 (Left side ESATA)
WLAN
JMINI3(Flash)-for w/ Vpro
WWAN
DOCKING
8
9
NA
10 Express card
11
2
3
1
4
USB PORT#
0
DESTINATION
6
5
7
JUSB (Right side-Audio/B)
Camera
JUSB1 (Left side)
12
13 BIO
Bluetooth
PCH
None
JUSB (Right side-IO/B)
4
NA
JUSB1 (Left side)
USB 3.0 PORT#
1
Connetion
2
3 JESA1 (Left side)
MLK DOCK
HDD
NA
ODD/ E3 Module Bay
SATA
SATA 0
DESTINATION
NA
SATA 1
SATA 2
SATA 3
SATA 4
SATA 5
ESATA
Dock
Dock DP port 2
UMA DP/HDMI Port
Port C
Connetion
Port D
Port B
Dock DP port 1
MB HDMI Conn
*1
*1
*1: HM76 don't support port 6,7
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Power Rail
4 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Power Rail
4 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Power Rail
4 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
BATTERY
+PWR_SRC
ADAPTER
FDC654P
+BL_PWR_SRC
EN_INVPWR
SI3456BDVSI3456BDV
SIO_SLP_S3#
+5V_MOD
MODC_EN
CHARGER
+3.3V_ALW
RT8205
+5V_ALW
ALWON
SI3456
+3.3V_LAN+3.3V_SUS
DMN3030LSS
SIO_SLP_S3#
+3.3V_RUN
+5V_HDD
(Q21)
(Q30)(Q27)
(PU100)
(Q34) (Q61)
+VCC_CORE
ISL95836
(PU700)
+1.05V_RUN_VTT +1.05V_M
SIO_SLP_A#
SIO_SLP_S4#
S13456
(Q54)
SI3456
+3.3V_M
(Q58)
SIO_SLP_A#
+3.3V_ALW_PCH
PCH_ALW_ON
SI3456
(Q49)
SIO_SLP_LAN#
+3.3V_WLAN
SI3456
(Q38)
AUX_EN_WOWL
SI4164
(Q63)
+1.05V_RUN
(PU500)
SIO_SLP_S3#(PT)
+3.3V_M
Pop option
CPU_VTT_ON
TPS51212
(PU400)
TPS51212
+1.5V_MEM
DDR_ON
0.75V_DDR_VTT_ON
RT8207
(PU200)
(Q59)
AO4304LAO4304L
(QC3)
SIO_SLP_S3#
+0.75V_DDR_VTT+1.5V_RUN+1.5V_CPU_VDDQ
+VCC_SA
1.05V_VTTPWRGD
+1.8V_RUN
(PU300)
SYN470
(PU7)
TPS51461
+5V_RUN
SIO_SLP_S3#
+3.3V_PCIE_WWAN
SI3456
(Q40)
MCARD_WWAN_PWREN
SI3456
(Q42)
+3.3V_PCIE_FLASH
MCARD_MISC_PWREN
+VCC_GFXCORE
1.05V_0.8V_PWROK
ISL95836
(PU700)
1.05V_0.8V_PWROK
+5V_RUN
Pop option
+3.3V_SUS
SIO_SLP_S3#
PJP8(SSI)
R206
AUX_ON
SIO_SLP_S3#
RUN_ON
SIO_SLP_S3#
SIO_SLP_S4#
SUS_ON
SIO_SLP_S5#
CPU1.5V_S3_GATE
PJP7
DASH(SSI)DASH(PT)
DASH(SSI)
TM/TL(PT)
vPro DASH
PJP3 PJP4
R563
(Q55)
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
SMBUS TOPOLOGY
5 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
SMBUS TOPOLOGY
5 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
SMBUS TOPOLOGY
5 61Wednesday, March 07, 2012
Compal Electronics, Inc.
MEC 5055
MEM_SMBDATA
MEM_SMBCLK
KBC
C9
H14
+3.3V_ALW_PCH
2.2K
2.2K
200
DIMM1
SMBUS Address [A4]
202
DIMM2
SMBUS Address [A0]
200
202
C8
G12
A4
B5
2.2K
2.2K
LCD_SMBCLK
LCD_SMDATA
1B
1B
1C
1C
B59
A56
+3.3V_ALW
2.2K
2.2K
100 ohm
100 ohm
BATTERY
CONN
7
6
SMBUS Address [0x16]
PBAT_SMBCLK
PBAT_SMBDAT
3A
1E
1E
2B
2B
B50
1G
1G
A47
B7
A7
+3.3V_ALW
2.2K
2.2K
2D
2D
BAY_SMBDAT
BAY_SMBCLK
A49
B52
CARD_SMBCLK
CARD_SMBDAT
+3.3V_SUS
2.2K
2.2K
CHARGER_SMBCLK
CHARGER_SMBDAT
Charger
SMBUS Address [0x12]
SML1_SMBDATA
PCH
SML1_SMBCLK
E14M16
A50
B53
3A
B6A5
+3.3V_ALW_PCH
2.2K
2.2K
+3.3V_ALW
2.2K
2.2K
53
51
SMBUS Address [TBD]
XDP1
SMBUS Address [TBD]
XDP2
53
51
10
9
G Sensor
SMBUS Address [3B]
DMN66D0L
DMN66D0L
+3.3V_RUN
10K
10K
4
6
Express card
7
8
SMBUS Address [TBD]
SMBUS Address [0x9a]
+3.3V_ALW
WWAN
SMBUS Address [TBD]
32
30
L10
L09
+3.3V_ALW
2.2K
2.2K
SIO_LAN_SMBCLK
SIO_LAN_SMBDAT
DMN66D0L
DMN66D0L
SMBUS Address [C8]
BCM LOM
LAN_APE_SMB_DATA0
LAN_APE_SMB_CLK0
+3.3V_LAN
2.2K
2.2K
MCTP Endpoint ID 0x09
PLDM Sensor Aggregator 0xDA
DMN66D0L
DMN66D0L
+3.3V_ALW
129
127
SMBUS Address
2.2K
DOCK_SMB_CLK
DOCK_SMB_DAT
DOCKING
2.2K
B4
A3
1A
1A
APR_EC: 0x48
SPR_EC: 0x70
MSLICE_EC: 0x72
USB: 0x59
AUDIO: 0x34
SLICE_BATTERY: 0x17
SLICE_CHARGER: 0x13
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CTX_PRX_N0
DMI_CRX_PTX_N2
DMI_CTX_PRX_P2
DMI_CTX_PRX_P1
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CRX_PTX_N3
DMI_CTX_PRX_N3
DMI_CRX_PTX_P3
DMI_CTX_PRX_P3
DMI_CTX_PRX_P0
DMI_CTX_PRX_N1
DMI_CRX_PTX_N1
DMI_CTX_PRX_N2
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N6
FDI_CTX_PRX_N5
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P5
FDI_CTX_PRX_P4
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC0
FDI_INT
FDI_LSYNC1
FDI_CTX_PRX_N0
PEG_COMP
EDP_COMP
EDP_COMP
+1.05V_RUN_VTT
+1.05V_RUN_VTT
DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_N3<16>
DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_N1<16>
DMI_CRX_PTX_P3<16>
DMI_CRX_PTX_N2<16>
DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_N0<16>
DMI_CTX_PRX_N0<16>
DMI_CTX_PRX_N1<16>
DMI_CTX_PRX_N2<16>
DMI_CTX_PRX_N3<16>
DMI_CTX_PRX_P0<16>
DMI_CTX_PRX_P1<16>
DMI_CTX_PRX_P2<16>
DMI_CTX_PRX_P3<16>
FDI_CTX_PRX_N1<16>
FDI_CTX_PRX_N0<16>
FDI_CTX_PRX_N4<16>
FDI_CTX_PRX_N3<16>
FDI_CTX_PRX_N2<16>
FDI_CTX_PRX_N7<16>
FDI_CTX_PRX_N6<16>
FDI_CTX_PRX_N5<16>
FDI_CTX_PRX_P2<16>
FDI_CTX_PRX_P1<16>
FDI_CTX_PRX_P0<16>
FDI_CTX_PRX_P5<16>
FDI_CTX_PRX_P4<16>
FDI_CTX_PRX_P3<16>
FDI_FSYNC0<16>
FDI_LSYNC0<16>
FDI_CTX_PRX_P7<16>
FDI_CTX_PRX_P6<16>
FDI_LSYNC1<16>
FDI_FSYNC1<16>
FDI_INT<16>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandt Bridge (1/6)
6 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandt Bridge (1/6)
6 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandt Bridge (1/6)
6 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
PEG Compensation
PEG_ICOMPI and RCOMPO signals should be shor ted and routed
with - max leng th = 500 mils - typical imped ance = 43 mohm s
PEG_ICOMPO sign als should be routed with - m ax length = 50 0 mils
- typical imped ance = 14.5 mo hms
(1)PEG_RCOMPO (H22) use 4mil connect to PEG_ICOMPI, then use 4mil connect to RC2.
(2)PEG_ICOMPO use 12mil connect to RC2
eDP_COMPIO and ICOMPO signals should be shor ted near
balls and route d with typical impedance <25 mohms
DP Compensation
(1) EDP_COMPIO use 4mil trace to RC1
(2) EDP_ICOMPO use 12mil to RC1
VSS
JCPU1I
TYCO_2013620-3_IVYBRIDGE
CONN@
VSS
JCPU1I
TYCO_2013620-3_IVYBRIDGE
CONN@
VSS161
T35
VSS162
T34
VSS163
T33
VSS164
T32
VSS165
T31
VSS166
T30
VSS167
T29
VSS168
T28
VSS169
T27
VSS170
T26
VSS171
P9
VSS172
P8
VSS173
P6
VSS174
P5
VSS175
P3
VSS176
P2
VSS177
N35
VSS178
N34
VSS179
N33
VSS180
N32
VSS181
N31
VSS182
N30
VSS183
N29
VSS184
N28
VSS185
N27
VSS186
N26
VSS187
M34
VSS188
L33
VSS189
L30
VSS190
L27
VSS191
L9
VSS192
L8
VSS193
L6
VSS194
L5
VSS195
L4
VSS196
L3
VSS197
L2
VSS198
L1
VSS199
K35
VSS200
K32
VSS201
K29
VSS202
K26
VSS203
J34
VSS204
J31
VSS205
H33
VSS206
H30
VSS207
H27
VSS208
H24
VSS209
H21
VSS210
H18
VSS211
H15
VSS212
H13
VSS213
H10
VSS214
H9
VSS215
H8
VSS216
H7
VSS217
H6
VSS218
H5
VSS219
H4
VSS220
H3
VSS221
H2
VSS222
H1
VSS223
G35
VSS224
G32
VSS225
G29
VSS226
G26
VSS227
G23
VSS228
G20
VSS229
G17
VSS230
G11
VSS231
F34
VSS232
F31
VSS233
F29
VSS234
F22
VSS235
F19
VSS236
E30
VSS237
E27
VSS238
E24
VSS239
E21
VSS240
E18
VSS241
E15
VSS242
E13
VSS243
E10
VSS244
E9
VSS245
E8
VSS246
E7
VSS247
E6
VSS248
E5
VSS249
E4
VSS250
E3
VSS251
E2
VSS252
E1
VSS253
D35
VSS254
D32
VSS255
D29
VSS256
D26
VSS257
D20
VSS258
D17
VSS259
C34
VSS260
C31
VSS261
C28
VSS262
C27
VSS263
C25
VSS264
C23
VSS265
C10
VSS266
C1
VSS267
B22
VSS268
B19
VSS269
B17
VSS270
B15
VSS271
B13
VSS272
B11
VSS273
B9
VSS274
B8
VSS275
B7
VSS276
B5
VSS277
B3
VSS278
B2
VSS279
A35
VSS280
A32
VSS281
A29
VSS282
A26
VSS283
A23
VSS284
A20
VSS285
A3
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
TYCO_2013620-3_IVYBRIDGE
CONN@
PCI EXPRESS* - GRAPHICS
DMI
Intel(R) FDI
eDP
JCPU1A
TYCO_2013620-3_IVYBRIDGE
CONN@
DMI_RX#[0]
B27
DMI_RX#[1]
B25
DMI_RX#[2]
A25
DMI_RX#[3]
B24
DMI_RX[0]
B28
DMI_RX[1]
B26
DMI_RX[2]
A24
DMI_RX[3]
B23
DMI_TX#[0]
G21
DMI_TX#[1]
E22
DMI_TX#[2]
F21
DMI_TX#[3]
D21
DMI_TX[0]
G22
DMI_TX[1]
D22
DMI_TX[3]
C21
DMI_TX[2]
F20
FDI0_TX#[0]
A21
FDI0_TX#[1]
H19
FDI0_TX#[2]
E19
FDI0_TX#[3]
F18
FDI1_TX#[0]
B21
FDI1_TX#[1]
C20
FDI1_TX#[2]
D18
FDI1_TX#[3]
E17
FDI0_TX[0]
A22
FDI0_TX[1]
G19
FDI0_TX[2]
E20
FDI0_TX[3]
G18
FDI1_TX[0]
B20
FDI1_TX[1]
C19
FDI1_TX[2]
D19
FDI1_TX[3]
F17
FDI0_FSYNC
J18
FDI1_FSYNC
J17
FDI_INT
H20
FDI0_LSYNC
J19
FDI1_LSYNC
H17
PEG_ICOMPI
J22
PEG_ICOMPO
J21
PEG_RCOMPO
H22
PEG_RX#[0]
K33
PEG_RX#[1]
M35
PEG_RX#[2]
L34
PEG_RX#[3]
J35
PEG_RX#[4]
J32
PEG_RX#[5]
H34
PEG_RX#[6]
H31
PEG_RX#[7]
G33
PEG_RX#[8]
G30
PEG_RX#[9]
F35
PEG_RX#[10]
E34
PEG_RX#[11]
E32
PEG_RX#[12]
D33
PEG_RX#[13]
D31
PEG_RX#[14]
B33
PEG_RX#[15]
C32
PEG_RX[0]
J33
PEG_RX[1]
L35
PEG_RX[2]
K34
PEG_RX[3]
H35
PEG_RX[4]
H32
PEG_RX[5]
G34
PEG_RX[6]
G31
PEG_RX[7]
F33
PEG_RX[8]
F30
PEG_RX[9]
E35
PEG_RX[10]
E33
PEG_RX[11]
F32
PEG_RX[12]
D34
PEG_RX[13]
E31
PEG_RX[14]
C33
PEG_RX[15]
B32
PEG_TX#[0]
M29
PEG_TX#[1]
M32
PEG_TX#[2]
M31
PEG_TX#[3]
L32
PEG_TX#[4]
L29
PEG_TX#[5]
K31
PEG_TX#[6]
K28
PEG_TX#[7]
J30
PEG_TX#[8]
J28
PEG_TX#[9]
H29
PEG_TX#[10]
G27
PEG_TX#[11]
E29
PEG_TX#[12]
F27
PEG_TX#[13]
D28
PEG_TX#[14]
F26
PEG_TX#[15]
E25
PEG_TX[0]
M28
PEG_TX[1]
M33
PEG_TX[2]
M30
PEG_TX[3]
L31
PEG_TX[4]
L28
PEG_TX[5]
K30
PEG_TX[6]
K27
PEG_TX[7]
J29
PEG_TX[8]
J27
PEG_TX[9]
H28
PEG_TX[10]
G28
PEG_TX[11]
E28
PEG_TX[12]
F28
PEG_TX[13]
D27
PEG_TX[14]
E26
PEG_TX[15]
D25
eDP_AUX
C15
eDP_AUX#
D15
eDP_TX[0]
C17
eDP_TX[1]
F16
eDP_TX[2]
C16
eDP_TX[3]
G15
eDP_TX#[0]
C18
eDP_TX#[1]
E16
eDP_TX#[2]
D16
eDP_TX#[3]
F15
eDP_COMPIO
A18
eDP_HPD#
B16
eDP_ICOMPO
A17
RC1
24.9_0402_1%~D
RC1
24.9_0402_1%~D
12
RC2
24.9_0402_1%~D
RC2
24.9_0402_1%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XDP_TMS
XDP_TDO_R
SM_RCOMP0
XDP_TRST#
XDP_TDI_R
XDP_TCLK
XDP_PRDY#
SM_RCOMP2
XDP_PREQ#
SM_RCOMP1
CLK_XDP
CLK_XDP#
XDP_OBS4
XDP_OBS5
XDP_OBS6
XDP_OBS7
CFG1
CFG2
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
XDP_TMS
XDP_PREQ#
XDP_PRDY#
XDP_DBRESET#
XDP_TDO
XDP_TRST#
XDP_TDI
XDP_TCLK
XDP_OBS0
XDP_OBS1
XDP_OBS2
XDP_OBS3
XDP_RST#_R
DDR_HVREF_RST
VCCPWRGOOD_0_R
H_PM_SYNC
H_CATERR#
H_PROCHOT#_R
PM_DRAM_PWR GD_CPU
H_CATERR#
H_PROCHOT#
H_THERMTRIP#
CPU_DPLL
CPU_DPLL#
DDR3_DRAMRST#_CP U
XDP_DBRESET#
XDP_TCLK
XDP_TMS
XDP_TRST#
XDP_TDO
XDP_TDI
XDP_PREQ#
SYS_PWROK_XDP
SM_RCOMP0
SM_RCOMP2
SM_RCOMP1
PCH_PLTRST#_R
PCH_PLTRST#_BUF
CFG11
CFG10
CFG9
CFG8
CFG16
CFG17
XDP_RST#_R
RUNPWROK_AND PM_DRAM_PWR GD_CPU
XDP_DBRESET#
VCCPWRGOOD_0_R
PCH_PLTRST#_R
CFD_PWRBTN#_X DP
H_CPUPWRGD
CFG0
H_CPUPWRGD_XDP
XDP_HOOK2
DDR_XDP_SMBDAT_R 1
DDR_XDP_SMBCLK_R 1
SYS_PWROK_XDP
CPU_DMI
CPU_DMI#
XDP_DBRESET#
XDP_OBS2
XDP_OBS3X DP_OBS3_R
XDP_OBS5_R
XDP_OBS2_R
XDP_OBS1_R
XDP_OBS0_R
XDP_OBS4_R XDP_OBS4
XDP_OBS7
XDP_OBS5
XDP_OBS6_R
XDP_OBS7_R
XDP_OBS6
XDP_OBS0
XDP_OBS1
XDP_DBRESET#_R
XDP_TDIXDP_TDI_R
XDP_TDO_R XDP_TDO
CLK_XDP
CLK_XDP#
H_THERMTRIP#_RH_THERMTRIP#_R
+1.05V_RUN_VTT
+1.05V_RUN_VTT +1.05V_RUN_VTT
+1.05V_RUN_VTT
+1.05V_RUN_VTT
+1.05V_RUN_VTT
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_ALW_PCH
+1.5V_CPU_VDDQ
+3.3V_ALW_PCH
+1.05V_RUN_VTT
CFG0 <9>
CFG1 <9>
CFG2 <9>
CFG3 <9>
CFG4 <9>
CFG5 <9>
CFG6 <9>
CFG7 <9>
DDR3_DRAMRST# <12>
H_CPUPWRGD<18>
H_PM_SYNC<16>
CPU_DETECT#<39>
H_PROCHOT#<40,51,52>
PECI_EC<40>
CLK_CPU_ITP <15>
CLK_CPU_ITP# <15>
CLK_XDP_ITP<9>
CLK_XDP_ITP#<9>
PCH_PLTRST#<14,17>
CFG11<9>
CFG10<9>
CFG9 <9>
CFG8 <9>
CFG16 <9>
CFG17 <9>
DDR_HVREF_RST_GATE<40>
PLTRST_XDP# <17>
RUN_ON_CPU1.5VS3#<11,42>
RUNPWROK<39,40>
PM_DRAM_PWR GD<16>
H_SNB_IVB#<18>
DDR_HVREF_RST <12>
SIO_PWRBTN#_R<14,16>
SYS_PWROK<16,39>
DDR_XDP_WAN_ SMBCLK<12,13,14,15,27,34>
DDR_XDP_WAN_ SMBDAT<12,13,14,15,27,34>
CLK_CPU_DMI <15>
CLK_CPU_DMI# <15>
XDP_DBRESET# <14,16>
DDR_HVREF_RST_PCH<15>
H_THERMTRIP#<22>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (2/6)
7 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (2/6)
7 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (2/6)
7 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Place near JXDP1
For ESD concern, please put near CPU
Avoid stub in t he PWRGD path
while placing r esistors RC25 & RC130
place RC129 near CPU
PU/PD for JTAG signals
The resistor fo r HOOK2 should beplaced
such that the s tub is very sm all on CFG0 net
Buffered reset to CPU
Close to JCPU1
Max 500mils
Follow DG Rev0.71 SM_DRAMPWROK topology
Open drain buffer
SM_RCOMP2 --> 15mil
SM_RCOMP1/0 --> 20mil
VR1 TOPOLOGY
Follow check list 0.5
M3 control
INTEL suggest RC64 and QC1 NO stuff by default
Remove DPLL Ref clock (for eDP only)
Reserve fo r ESD in 6 /22
Place clos ed JCPU1
RC28 130_0402_1%~DRC28 130_0402_1%~D
1 2
RC35 51_0402_1%~DRC35 51_0402_1%~D
12
RC5 1K_0402_1%~DRC5 1K_0402_1%~D
1 2
RC10 43_0402_5%~DRC10 43_0402_5%~D
1 2
RC44 62_0402_5%~DRC44 62_0402_5%~D
1 2
UC2
74AHC1G09GW_TSSOP5~D
UC2
74AHC1G09GW_TSSOP5~D
B
1
A
2
G
3
O
4
P
5
RC39 0_0402_5%~DRC39 0_0402_5%~D
1 2
RC126 56_0402_5%~D@RC126 56_0402_5%~D@
1 2
CC141
100P_0402_50V8J~D
CC141
100P_0402_50V8J~D
1
2
RC9 0_0402_5%~D@ RC9 0_0402_5%~D@
1 2
RC36 0_0402_5%~DRC36 0_0402_5%~D
1 2
RC45
200_0402_1%~D
RC45
200_0402_1%~D
12
CC177
0.047U_0402_16V4Z~D
CC177
0.047U_0402_16V4Z~D
1
2
RC6 0_0402_5%~DRC6 0_0402_5%~D
1 2
RC50
4.99K_0402_1%~D
RC50
4.99K_0402_1%~D
12
RC31 0_0402_5%~DRC31 0_0402_5%~D
1 2
RC125 0_0402 _5%~DRC125 0_0402_5%~D
1 2
RC19 1K_0402_1%~DRC19 1K_0402_1%~D
12
RC37 0_0402_5%~DRC37 0_0402_5%~D
1 2
RC124
1K_0402_1%~D
@RC124
1K_0402_1%~D
@
12
JXDP1
SAMTE_BSH-030-01-L-D-A
CONN@
JXDP1
SAMTE_BSH-030-01-L-D-A
CONN@
GND0
1
OBSFN_A0
3
OBSFN_A1
5
GND2
7
OBSDATA_A0
9
OBSDATA_A1
11
GND4
13
OBSDATA_A2
15
OBSDATA_A3
17
GND6
19
OBSFN_B0
21
OBSFN_B1
23
GND8
25
OBSDATA_B0
27
OBSDATA_B1
29
GND10
31
OBSDATA_B2
33
OBSDATA_B3
35
GND12
37
PWRGOOD/HOOK0
39
HOOK1
41
VCC_OBS_AB
43
HOOK2
45
HOOK3
47
GND14
49
SDA
51
SCL
53
TCK1
55
TCK0
57
GND16
59
GND1
2
OBSFN_C0
4
OBSFN_C1
6
GND3
8
OBSDATA_C0
10
OBSDATA_C1
12
GND5
14
OBSDATA_C2
16
OBSDATA_C3
18
GND7
20
OBSFN_D0
22
OBSFN_D1
24
GND9
26
OBSDATA_D0
28
OBSDATA_D1
30
GND11
32
OBSDATA_D2
34
OBSDATA_D3
36
GND13
38
ITPCLK/HOOK4
40
ITPCLK#/HOOK5
42
VCC_OBS_CD
44
RESET#/HOOK6
46
DBR#/HOOK7
48
GND15
50
TD0
52
TRST#
54
TDI
56
TMS
58
GND17
60
RC127 0_0402 _5%~DRC127 0_0402_5%~D
1 2
RC27 51_0402_1%~DRC27 51_0402_1%~D
12
RH109 0_0402 _5%~D@RH109 0_0402_5 %~D@
1 2
RC33 0_0402_5%~DRC33 0_0402_5%~D
1 2
UC1
SN74LVC1G07DCKR_SC70-5~D
UC1
SN74LVC1G07DCKR_SC70-5~D
NC
1
A
2
GND
3
Y
4
VCC
5
CC66
0.1U_0402_25V6K~D
CC66
0.1U_0402_25V6K~D
1
2
RC13 0_0402_5%~D@RC13 0_0402_5%~D@
1 2
RC7 1K_0402_1%~DRC7 1K_0402_1%~D
1 2
RC46 0_0402_5%~D@RC46 0_0402_5%~D@
1 2
RC40
51_0402_1%~D
RC40
51_0402_1%~D
12
RC15 0_0402_5%~D@RC15 0_0402_5%~D@
1 2
RC12
200_0402_1%~D
RC12
200_0402_1%~D
12
RC43
25.5_0402_1%~D
RC43
25.5_0402_1%~D
12
RC57 56_0402_5%~DRC57 56_0402_5%~D
1 2
RC23 0_0402_5%~DRC23 0_0402_5%~D
1 2
RC41
51_0402_1%~D
RC41
51_0402_1%~D
12
CC65
0.1U_0402_25V6K~D
CC65
0.1U_0402_25V6K~D
1
2
RC47 0_0402_5%~D@ RC47 0_0402_5%~D@
1 2
RC24 0_0402_5%~DRC24 0_0402_5%~D
1 2
RH107 0_0402 _5%~DRH107 0_0402_5%~D
1 2
RC18 200_0402_1%~DRC18 200_0402_1%~D
1 2
RC4
75_0402_1%~D
RC4
75_0402_1%~D
12
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
TYCO_2013620-3_IVYBRIDGE
CONN@
CLOCKS
MISCTHERMALPWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
TYCO_2013620-3_IVYBRIDGE
CONN@
SM_RCOMP[1]
A5
SM_RCOMP[2]
A4
SM_DRAMRST#
R8
SM_RCOMP[0]
AK1
BCLK#
A27
BCLK
A28
DPLL_REF_CLK#
A15
DPLL_REF_CLK
A16
CATERR#
AL33
PECI
AN33
PROCHOT#
AL32
THERMTRIP#
AN32
SM_DRAMPWR OK
V8
RESET#
AR33
PRDY#
AP29
PREQ#
AP27
TCK
AR26
TMS
AR27
TRST#
AP30
TDI
AR28
TDO
AP26
DBR#
AL35
BPM#[0]
AT28
BPM#[1]
AR29
BPM#[2]
AR30
BPM#[3]
AT30
BPM#[4]
AP32
BPM#[5]
AR31
BPM#[6]
AT31
BPM#[7]
AR32
PM_SYNC
AM34
SKTOCC#
AN34
PROC_SELECT#
C26
UNCOREPWRGOOD
AP33
RC130
10K_0402_5%~D
RC130
10K_0402_5%~D
12
RC64
39_0402_5%~D
@RC64
39_0402_5%~D
@
1 2
RH106 0_0402 _5%~DRH106 0_0402_5%~D
1 2
CC140
0.1U_0402_25V6K~D
CC140
0.1U_0402_25V6K~D
1
2
RH108 0_0402 _5%~D@RH108 0_0402_5 %~D@
1 2
RC17 1K_0402_1%~DRC17 1K_0402_1%~D
1 2
RC38 0_0402_5%~DRC38 0_0402_5%~D
1 2
RC16 1K_0402_1%~DRC16 1K_0402_1%~D
1 2
RC25 1K_0402_5%~DRC25 1K_0402_5%~D
1 2
RC128 49.9_0402_1%~D@RC128 49.9_0402_1%~D@
1 2
G
D
S
QC1
SSM3K7002FU_SC70-3~D
@
G
D
S
QC1
SSM3K7002FU_SC70-3~D
@
2
13
RC26 0_0402_5%~DRC26 0_0402_5%~D
12
RC48 0_0402_5%~D@ RC48 0_0402_5%~D@
1 2
RC32 51_0402_1%~D@RC32 51_0402_1%~D@
12
CE13
0.047U_0402_16V4Z~D
@
CE13
0.047U_0402_16V4Z~D
@
1
2
CC142
100P_0402_50V8J~D
CC142
100P_0402_50V8J~D
1
2
CC156 0.1U_0402_25V6K~DCC156 0.1U_0402_25V6K~D
1 2
RC29 51_0402_1%~DRC29 51_0402_1%~D
12
RC129 0_0402 _5%~DRC129 0_0402_5%~D
1 2
RC8 1K_0402_1%~DRC8 1K_0402_1%~D
12
RC34 0_0402_5%~DRC34 0_0402_5%~D
1 2
G
D
S
QC2
BSS138W-7-F_SOT323-3~D
G
D
S
QC2
BSS138W-7-F_SOT323-3~D
2
13
RC30 0_0402_5%~DRC30 0_0402_5%~D
1 2
RC42
140_0402_1%~D
RC42
140_0402_1%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D59
DDR_A_D31
DDR_A_D9
DDR_A_BS1
DDR_A_D50
DDR_A_D42
DDR_A_D29
DDR_A_D51
DDR_A_D46
DDR_A_D36
DDR_A_D18
DDR_A_D4
DDR_A_D58
DDR_A_D55
DDR_A_D14
DDR_A_D24
DDR_A_D8
DDR_A_D63
DDR_A_D49
DDR_A_D41
DDR_A_D34
DDR_A_D28
DDR_A_D25
DDR_A_D35
DDR_A_D17
DDR_A_D13
DDR_A_D3
DDR_A_RAS#
DDR_A_D57
DDR_A_D54
DDR_A_D22
DDR_A_D21
DDR_A_D6
DDR_A_D23
DDR_A_D7
DDR_A_BS2
DDR_A_D62
DDR_A_D48
DDR_A_D40
DDR_A_D33
DDR_A_D27
DDR_A_WE#
DDR_A_D44
DDR_A_D16
DDR_A_D12
DDR_A_D2
DDR_A_CAS#
DDR_A_D56
DDR_A_D53
DDR_A_D45
DDR_A_D38
DDR_A_D20
DDR_A_D60
DDR_A_D5
DDR_A_D61
DDR_A_D47
DDR_A_D39
DDR_A_D32
DDR_A_D26
DDR_A_D10
DDR_A_D0
DDR_A_BS0
DDR_A_D43
DDR_A_D15
DDR_A_D11
DDR_A_D1
DDR_A_D52
DDR_A_D37
DDR_A_D30
DDR_A_D19
DDR_B_D29
DDR_B_RAS#
DDR_B_D59
DDR_B_D50
DDR_B_D49
DDR_B_D13
DDR_B_D11
DDR_B_D19
DDR_B_D14
DDR_B_D3
DDR_B_D55
DDR_B_D47
DDR_B_WE#
DDR_B_BS2
DDR_B_D52
DDR_B_D44
DDR_B_D41
DDR_B_D8
DDR_B_D5
DDR_B_CAS#
DDR_B_D56
DDR_B_D48
DDR_B_D38
DDR_B_D35
DDR_B_D26
DDR_B_D25
DDR_B_D4
DDR_B_D63
DDR_B_D34
DDR_B_D32
DDR_B_D10
DDR_B_BS1
DDR_B_D17
DDR_B_D51
DDR_B_D40
DDR_B_D36
DDR_B_D31
DDR_B_D21
DDR_B_D20
DDR_B_D15
DDR_B_D7
DDR_B_D62
DDR_B_D46
DDR_B_D42
DDR_B_D18
DDR_B_D12
DDR_B_D1
DDR_B_D53
DDR_B_D37
DDR_B_D22
DDR_B_D57
DDR_B_D27
DDR_B_D54
DDR_B_D45
DDR_B_D39
DDR_B_D30
DDR_B_D9
DDR_B_D60
DDR_B_D58
DDR_B_D33
DDR_B_D0
DDR_B_D61
DDR_B_D43
DDR_B_D28
DDR_B_D23
DDR_B_D24
DDR_B_D16
DDR_B_D6
DDR_B_D2
DDR_B_BS0
M_CLK_DDR#0
M_CLK_DDR#1
DDR_CKE0_DIMMA
DDR_A_DQS7
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS5
DDR_A_DQS#5
DDR_A_DQS3
DDR_A_DQS4
DDR_A_DQS#7
DDR_A_DQS0
DDR_A_DQS6
DDR_A_DQS#2
DDR_A_DQS#1
DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_MA0
DDR_A_MA1
DDR_A_MA3
DDR_A_MA7
DDR_A_MA8
DDR_A_MA13
DDR_A_MA2
DDR_A_MA14
DDR_A_MA5
DDR_A_MA10
DDR_A_MA4
DDR_A_MA11
DDR_A_MA9
DDR_A_MA6
DDR_A_MA12
M_CLK_DDR1
M_CLK_DDR0
DDR_A_MA15
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
DDR_CKE1_DIMMA
M_ODT1
M_ODT0
M_CLK_DDR3
M_CLK_DDR#2
M_CLK_DDR#3
DDR_B_MA10
DDR_B_MA9
DDR_B_MA14
DDR_B_MA5
DDR_B_MA13
DDR_B_MA11
DDR_B_MA7
DDR_B_MA2
DDR_B_MA0
DDR_B_MA6
DDR_B_MA1
DDR_B_MA12
DDR_B_MA4
DDR_B_MA8
DDR_B_MA3
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS7
DDR_B_DQS4
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS0
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#1
M_CLK_DDR2
DDR_B_DQS#2
DDR_B_DQS#0
DDR_B_DQS#5
DDR_B_DQS#7
DDR_B_DQS#4
M_ODT2
DDR_CKE2_DIMMB
DDR_B_MA15
DDR_CKE3_DIMMB
M_ODT3
DDR_CS2_DIMMB#
DDR_CS3_DIMMB#
DDR_A_D[0..63]<12>
DDR_A_BS0<12>
DDR_A_BS1<12>
DDR_A_BS2<12>
DDR_A_WE#<12>
DDR_A_CAS#<12>
DDR_A_RAS#<12>
DDR_B_D[0..63]<13>
DDR_B_BS2<13>
DDR_B_BS1<13>
DDR_B_WE#<13>
DDR_B_CAS#<13>
DDR_B_RAS#<13>
DDR_B_BS0<13>
DDR_A_DQS[0..7] <12>
DDR_A_DQS#[0..7] <12>
DDR_A_MA[0..15] <12>
DDR_CKE1_DIMMA <12>
DDR_CKE0_DIMMA <12>
DDR_CS0_DIMMA# <12>
M_ODT0 <12>
DDR_CS1_DIMMA# <12>
M_ODT1 <12>
M_CLK_DDR1 <12>
M_CLK_DDR0 <12>
M_CLK_DDR#1 <12>
M_CLK_DDR#0 <12>
DDR_B_MA[0..15] <13>
DDR_B_DQS#[0..7] <13>
DDR_B_DQS[0..7] <13>
DDR_CS3_DIMMB# <13>
DDR_CS2_DIMMB# <13>
M_ODT3 <13>
DDR_CKE3_DIMMB <13>
DDR_CKE2_DIMMB <13>
M_ODT2 <13>
M_CLK_DDR#2 <13>
M_CLK_DDR2 <13>
M_CLK_DDR#3 <13>
M_CLK_DDR3 <13>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (3/6)
8 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (3/6)
8 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (3/6)
8 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DDR SYSTEM MEMORY B
JCPU1D
TYCO_2013620-3_IVYBRIDGE
CONN@
DDR SYSTEM MEMORY B
JCPU1D
TYCO_2013620-3_IVYBRIDGE
CONN@
SB_BS[0]
AA9
SB_BS[1]
AA7
SB_BS[2]
R6
SB_CAS#
AA10
SB_RAS#
AB8
SB_WE#
AB9
SB_CK[0]
AE2
SB_CK[1]
AE1
SB_CLK#[0]
AD2
SB_CLK#[1]
AD1
SB_CKE[0]
R9
SB_CKE[1]
R10
SB_ODT[0]
AE4
SB_ODT[1]
AD4
SB_DQS[4]
AN6
SB_DQS#[4]
AN5
SB_DQS[5]
AP8
SB_DQS#[5]
AP9
SB_DQS[6]
AK11
SB_DQS#[6]
AK12
SB_DQS[7]
AP14
SB_DQS#[7]
AP15
SB_DQS[0]
C7
SB_DQS#[0]
D7
SB_DQS[1]
G3
SB_DQS#[1]
F3
SB_DQS[2]
J6
SB_DQS#[2]
K6
SB_DQS[3]
M3
SB_DQS#[3]
N3
SB_MA[0]
AA8
SB_MA[1]
T7
SB_MA[2]
R7
SB_MA[3]
T6
SB_MA[4]
T2
SB_MA[5]
T4
SB_MA[6]
T3
SB_MA[7]
R2
SB_MA[8]
T5
SB_MA[9]
R3
SB_MA[10]
AB7
SB_MA[11]
R1
SB_MA[12]
T1
SB_MA[13]
AB10
SB_MA[14]
R5
SB_MA[15]
R4
SB_DQ[0]
C9
SB_DQ[1]
A7
SB_DQ[2]
D10
SB_DQ[3]
C8
SB_DQ[4]
A9
SB_DQ[5]
A8
SB_DQ[6]
D9
SB_DQ[7]
D8
SB_DQ[8]
G4
SB_DQ[9]
F4
SB_DQ[10]
F1
SB_DQ[11]
G1
SB_DQ[12]
G5
SB_DQ[13]
F5
SB_DQ[14]
F2
SB_DQ[15]
G2
SB_DQ[16]
J7
SB_DQ[17]
J8
SB_DQ[18]
K10
SB_DQ[19]
K9
SB_DQ[20]
J9
SB_DQ[21]
J10
SB_DQ[22]
K8
SB_DQ[23]
K7
SB_DQ[24]
M5
SB_DQ[25]
N4
SB_DQ[26]
N2
SB_DQ[27]
N1
SB_DQ[28]
M4
SB_DQ[29]
N5
SB_DQ[30]
M2
SB_DQ[31]
M1
SB_DQ[32]
AM5
SB_DQ[33]
AM6
SB_DQ[34]
AR3
SB_DQ[35]
AP3
SB_DQ[36]
AN3
SB_DQ[37]
AN2
SB_DQ[38]
AN1
SB_DQ[39]
AP2
SB_DQ[40]
AP5
SB_DQ[41]
AN9
SB_DQ[42]
AT5
SB_DQ[43]
AT6
SB_DQ[44]
AP6
SB_DQ[45]
AN8
SB_DQ[46]
AR6
SB_DQ[47]
AR5
SB_DQ[48]
AR9
SB_DQ[49]
AJ11
SB_DQ[50]
AT8
SB_DQ[51]
AT9
SB_DQ[52]
AH11
SB_DQ[53]
AR8
SB_DQ[54]
AJ12
SB_DQ[55]
AH12
SB_DQ[56]
AT11
SB_DQ[57]
AN14
SB_DQ[58]
AR14
SB_DQ[59]
AT14
SB_DQ[60]
AT12
SB_DQ[61]
AN15
SB_DQ[62]
AR15
SB_DQ[63]
AT15
SB_CK[2]
AB2
SB_CLK#[2]
AA2
SB_CKE[2]
T9
SB_CK[3]
AA1
SB_CLK#[3]
AB1
SB_CKE[3]
T10
SB_CS#[0]
AD3
SB_CS#[1]
AE3
SB_CS#[2]
AD6
SB_CS#[3]
AE6
SB_ODT[2]
AD5
SB_ODT[3]
AE5
DDR SYSTEM MEMORY A
JCPU1C
TYCO_2013620-3_IVYBRIDGE
CONN@
DDR SYSTEM MEMORY A
JCPU1C
TYCO_2013620-3_IVYBRIDGE
CONN@
SA_BS[0]
AE10
SA_BS[1]
AF10
SA_BS[2]
V6
SA_CAS#
AE8
SA_RAS#
AD9
SA_WE#
AF9
SA_CK[0]
AB6
SA_CK[1]
AA5
SA_CLK#[0]
AA6
SA_CLK#[1]
AB5
SA_CKE[0]
V9
SA_CKE[1]
V10
SA_CS#[0]
AK3
SA_CS#[1]
AL3
SA_ODT[0]
AH3
SA_ODT[1]
AG3
SA_DQS[0]
D4
SA_DQS#[0]
C4
SA_DQS[1]
F6
SA_DQS#[1]
G6
SA_DQS[2]
K3
SA_DQS#[2]
J3
SA_DQS[3]
N6
SA_DQS#[3]
M6
SA_DQS[4]
AL5
SA_DQS#[4]
AL6
SA_DQS[5]
AM9
SA_DQS#[5]
AM8
SA_DQS[6]
AR11
SA_DQS#[6]
AR12
SA_DQS[7]
AM14
SA_DQS#[7]
AM15
SA_MA[0]
AD10
SA_MA[1]
W1
SA_MA[2]
W2
SA_MA[3]
W7
SA_MA[4]
V3
SA_MA[5]
V2
SA_MA[6]
W3
SA_MA[7]
W6
SA_MA[8]
V1
SA_MA[9]
W5
SA_MA[10]
AD8
SA_MA[11]
V4
SA_MA[12]
W4
SA_MA[13]
AF8
SA_MA[14]
V5
SA_MA[15]
V7
SA_DQ[0]
C5
SA_DQ[1]
D5
SA_DQ[2]
D3
SA_DQ[3]
D2
SA_DQ[4]
D6
SA_DQ[5]
C6
SA_DQ[6]
C2
SA_DQ[7]
C3
SA_DQ[8]
F10
SA_DQ[9]
F8
SA_DQ[10]
G10
SA_DQ[11]
G9
SA_DQ[12]
F9
SA_DQ[13]
F7
SA_DQ[14]
G8
SA_DQ[15]
G7
SA_DQ[16]
K4
SA_DQ[17]
K5
SA_DQ[18]
K1
SA_DQ[19]
J1
SA_DQ[20]
J5
SA_DQ[21]
J4
SA_DQ[22]
J2
SA_DQ[23]
K2
SA_DQ[24]
M8
SA_DQ[25]
N10
SA_DQ[26]
N8
SA_DQ[27]
N7
SA_DQ[28]
M10
SA_DQ[29]
M9
SA_DQ[30]
N9
SA_DQ[31]
M7
SA_DQ[32]
AG6
SA_DQ[33]
AG5
SA_DQ[34]
AK6
SA_DQ[35]
AK5
SA_DQ[36]
AH5
SA_DQ[37]
AH6
SA_DQ[38]
AJ5
SA_DQ[39]
AJ6
SA_DQ[40]
AJ8
SA_DQ[41]
AK8
SA_DQ[42]
AJ9
SA_DQ[43]
AK9
SA_DQ[44]
AH8
SA_DQ[45]
AH9
SA_DQ[46]
AL9
SA_DQ[47]
AL8
SA_DQ[48]
AP11
SA_DQ[49]
AN11
SA_DQ[50]
AL12
SA_DQ[51]
AM12
SA_DQ[52]
AM11
SA_DQ[53]
AL11
SA_DQ[54]
AP12
SA_DQ[55]
AN12
SA_DQ[56]
AJ14
SA_DQ[57]
AH14
SA_DQ[58]
AL15
SA_DQ[59]
AK15
SA_DQ[60]
AL14
SA_DQ[61]
AK14
SA_DQ[62]
AJ15
SA_DQ[63]
AH15
SA_CK[2]
AB4
SA_CLK#[2]
AA4
SA_CK[3]
AB3
SA_CLK#[3]
AA3
SA_CKE[2]
W9
SA_CKE[3]
W10
SA_CS#[2]
AG1
SA_CS#[3]
AH1
SA_ODT[2]
AG2
SA_ODT[3]
AH2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG10
CFG11
CFG16
CFG17
CFG1
CFG2
CFG0
CFG3
CFG4
CFG5
CFG6
CFG7
CFG8
CFG9
VCC_VAL_SNESE
VSS_VAL_SNESE
VAXG_VAL_SENSE
VSSAXG_VAL_SENSE
CFG4
CFG6
CFG5
CFG2
CFG7
VSSAXG_VAL_SENSE
VAXG_VAL_SENSE
VCC_VAL_SNESE
CFG14
CFG15
CFG12
CFG13
VSS_VAL_SNESE
+VCC_CORE
+VCC_GFXCORE
CFG0<7>
CFG1<7>
CFG2<7>
CFG3<7>
CFG4<7>
CFG5<7>
CFG6<7>
CFG7<7>
CFG8<7>
CFG9<7>
CFG10<7>
CFG11<7>
CFG17<7>
CFG16<7>
CLK_XDP_ITP <7>
CLK_XDP_ITP# <7>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (4/6)
9 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (4/6)
9 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (4/6)
9 61Wednesday, March 07, 2012
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
DELL CONFIDENTIAL/PROPRIETARY
10: x8, x8 - Device 1 function 1 enabled ; function 2
disabled
PCIE Port Bifurcation Straps
CFG[6:5]
11: (Default) x16 - Device 1 functions 1 and 2 disabled
CFG7
PEG DEFER TRAINING
0: PEG Wait for BIOS for training
1: (Default) PEG Train immediately
following xxRESETB de assertion
CFG4
Display Port Presence Strap
0 : Enabled; An external Display Port device is
connected to the Embedded Display Port
1 : Disabled; No Physical Display Port
attached to Embedded Display Port
CFG Straps for Processor
01: Reserved - (Device 1 function 1 disabled ; function
2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
PEG Static Lane Reversal - CFG2 is for the 16x
CFG2
0:Lane Reversed
1:(Default) Normal Operation; Lane #
definition matches socket pin map definition
T15 PAD~D@T15 PAD~D@
T45PAD~D @T45PAD~D @
T49 PAD~D@T49 PAD~D@
RC52
1K_0402_1%~D
@ RC52
1K_0402_1%~D
@
12
T16 PAD~D@T16 PAD~D@
T39 PAD~D@T39 PAD~D@
T36PAD~D @T36PAD~D @
RC71
100_0402_1%~D
@ RC71
100_0402_1%~D
@
12
T31PAD~D @T31PAD~D @
RC120 49.9_0402_1%~D@RC120 49.9_0402_1%~D@
1 2
RC56
1K_0402_1%~D
@ RC56
1K_0402_1%~D
@
12
T29PAD~D @T29PAD~D @
T50 PAD~D@T50 PAD~D@
RC54
1K_0402_1%~D
@ RC54
1K_0402_1%~D
@
12
RC53
1K_0402_1%~D
@ RC53
1K_0402_1%~D
@
12
T37PAD~D @T37PAD~D @
T20 PAD~D@T20 PAD~D@
T35PAD~D @T35PAD~D @
T11 PAD~D@T11 PAD~D@
T33PAD~D @T33PAD~D @
T1 PAD~D@T1 PAD~D@
RESERVED
CFG
JCPU1E
TYCO_2013620-3_IVYBRIDGE
CONN@
RESERVED
CFG
JCPU1E
TYCO_2013620-3_IVYBRIDGE
CONN@
CFG[0]
AK28
CFG[1]
AK29
CFG[2]
AL26
CFG[3]
AL27
CFG[4]
AK26
CFG[5]
AL29
CFG[6]
AL30
CFG[7]
AM31
CFG[8]
AM32
CFG[9]
AM30
CFG[10]
AM28
CFG[11]
AM26
CFG[12]
AN28
CFG[13]
AN31
CFG[14]
AN26
CFG[15]
AM27
CFG[16]
AK31
CFG[17]
AN29
RSVD34
AM33
RSVD35
AJ27
RSVD38
J16
RSVD_NCTF2
AT34
RSVD39
H16
RSVD40
G16
RSVD_NCTF1
AR35
RSVD_NCTF3
AT33
RSVD_NCTF5
AR34
RSVD_NCTF11
AT2
RSVD_NCTF12
AT1
RSVD_NCTF13
AR1
RSVD_NCTF6
B34
RSVD_NCTF7
A33
RSVD_NCTF8
A34
RSVD_NCTF9
B35
RSVD_NCTF10
C35
RSVD51
AJ32
RSVD52
AK32
RSVD27
J15
RSVD16
C30
RSVD15
D23
RSVD17
A31
RSVD18
B30
RSVD20
D30
RSVD19
B29
RSVD22
A30
RSVD21
B31
RSVD23
C29
RSVD37
T8
RSVD8
F25
RSVD9
F24
RSVD11
D24
RSVD12
G25
RSVD13
G24
RSVD14
E23
RSVD32
W8
RSVD33
AT26
RSVD_NCTF4
AP35
RSVD10
F23
RSVD5
AJ26
VAXG_VAL_SENSE
AJ31
VSSAXG_VAL_SENSE
AH31
VCC_VAL_SENSE
AJ33
VSS_VAL_SENSE
AH33
KEY
B1
VCC_DIE_SENSE
AH27
BCLK_ITP
AN35
BCLK_ITP#
AM35
VSS_DIE_SENSE
AH26
RSVD31
AK2
RSVD30
AE7
RSVD29
AG7
RSVD28
L7
RSVD24
J20
RSVD25
B18
RC121 49.9_0402_1%~D@RC121 49.9_0402_1%~D@
1 2
T24 PAD~D@T24 PAD~D@
T7 PAD~D@T7 PAD~D@
T6 PAD~D@T6 PAD~D@
RC123 49.9_0402_1%~D@RC123 49.9_0402_1%~D@
1 2
T5 PAD~D@T5 PAD~D@
T22PAD~D @T22PAD~D @
T44PAD~D @T44PAD~D @
RC51
1K_0402_1%~D
@ RC51
1K_0402_1%~D
@
12
T47PAD~D @T47PAD~D @
T53 PAD~D@T53 PAD~D@
T18 PAD~D@T18 PAD~D@
T42PAD~D @T42PAD~D @
T3 PAD~D@T3 PAD~D@
T4 PAD~D@T4 PAD~D@
T17 PAD~D@T17 PAD~D@
RC122 49.9_0402_1%~D@RC122 49.9_0402_1%~D@
1 2
T21 PAD~D@T21 PAD~D@
T25 PAD~D@T25 PAD~D@
T2 PAD~D@T2 PAD~D@
T43PAD~D @T43PAD~D @
T51 PAD~D@T51 PAD~D@
T52PAD~D @T52PAD~D @
T41PAD~D @T41PAD~D @
T8 PAD~D@T8 PAD~D@
T46PAD~D @T46PAD~D @
T19 PAD~D@T19 PAD~D@
T23 PAD~D@T23 PAD~D@
T48PAD~D @T48PAD~D @
T28PAD~D @T28PAD~D @
T30PAD~D @T30PAD~D @
T40PAD~D @T40PAD~D @
T13 PAD~D@T13 PAD~D@
T34 PAD~D@T34 PAD~D@
T38PAD~D @T38PAD~D @
T26 PAD~D@T26 PAD~D@
RC69
100_0402_1%~D
@ RC69
100_0402_1%~D
@
12
T32 PAD~D@T32 PAD~D@
T27 PAD~D@T27 PAD~D@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCSENSE_R
VSSSENSE_R
H_CPU_SVIDALRT#
VIDSOUT
H_CPU_SVIDALRT#
VIDSCLK
VTT_SENSE
VSSIO_SENSE_R
+VCC_CORE
+VCC_CORE
+1.05V_RUN_VTT
+1.05V_RUN_VTT
+1.05V_RUN_VTT
+1.05V_RUN_VTT
VSSSENSE <51>
VCCSENSE <51>
VTT_SENSE <49>
VIDALERT_N <51>
VIDSCLK <51>
VIDSOUT < 51>
VSSIO_SENSE_R <49>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (5/6)
10 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (5/6)
10 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (5/6)
10 61Wednesday, March 07, 2012
Compal Electronics, Inc.
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
8.5A
CPU Power Rail Table
1.5
0.65-0.9
VCC
VCCIO
VAXG
VCCPLL
VDDQ
VCCSA
Voltage Rail
0.65-1.3
1.05
1.8
53
8.5
26
3
12-16
6
0.0-1.1
Voltage
S0 Iccmax
Current (A)
5A to Mem contr oller(+1.5V_CP U_VDDQ)
5-6A to 2 DIMMs /channel
2-5A to +1.5V_R UN & +0.75V_DD R_VTT
*
*
Description
5
+1.5V_MEM 1.5
Iccmax current changed for PD DG Rev0.7
Note: Place the PU resistors close to CPU
RC61 close to C PU 300 - 1500m ils
CAD Note: Place the PU
resistors close to CPU
RC63 close to C PU 300 - 1500m ils
DELL CONFIDENTIAL/PROPRIETARY
Place RC66, RC70near CPU
53A
H_CPU_SVIDALRT# must be routed between the
VIDSOUT and VIDSCLK lines to reduce cross
talk. 18 mils spacing to others.
RC75
100_0402_1%~D
@RC75
100_0402_1%~D
@
1 2
RC61 43_0402_5%~DRC61 43_0402_5%~D
1 2
RC70
100_0402_1%~D
RC70
100_0402_1%~D
12
RC60
75_0402_1%~D
RC60
75_0402_1%~D
12
POWER
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
JCPU1F
TYCO_2013620-3_IVYBRIDGE
CONN@
POWER
CORE SUPPLY
PEG AND DDR
SENSE LINES SVID
JCPU1F
TYCO_2013620-3_IVYBRIDGE
CONN@
VCC_SENSE
AJ35
VSS_SENSE
AJ34
VIDALERT#
AJ29
VIDSCLK
AJ30
VIDSOUT
AJ28
VSS_SENSE_VCCIO
A10
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VCCIO1
AH13
VCCIO12
J11
VCCIO18
G12
VCCIO19
F14
VCCIO20
F13
VCCIO21
F12
VCCIO22
F11
VCCIO23
E14
VCCIO24
E12
VCCIO2
AH10
VCCIO3
AG10
VCCIO4
AC10
VCCIO5
Y10
VCCIO6
U10
VCCIO7
P10
VCCIO8
L10
VCCIO9
J14
VCCIO10
J13
VCCIO11
J12
VCCIO13
H14
VCCIO14
H12
VCCIO15
H11
VCCIO16
G14
VCCIO17
G13
VCCIO25
E11
VCCIO32
C12
VCCIO33
C11
VCCIO34
B14
VCCIO35
B12
VCCIO36
A14
VCCIO37
A13
VCCIO38
A12
VCCIO39
A11
VCCIO26
D14
VCCIO27
D13
VCCIO28
D12
VCCIO29
D11
VCCIO30
C14
VCCIO31
C13
VCCIO_SENSE
B10
VCCIO40
J23
RC66
100_0402_1%~D
RC66
100_0402_1%~D
12
RC67 0_0402_5%~D@ RC67 0_0402_5%~D@
1 2
RC68 0_0402_5%~D@ RC68 0_0402_5%~D@
1 2
RC133
10_0402_1%~D
RC133
10_0402_1%~D
12
RC63
130_0402_1%~D
RC63
130_0402_1%~D
12
RC98 10_0402_1%~DRC98 10_0402_1%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
+DIMM0_1_CA_CPU
+DIMM0_1_VREF_CPU
RUN_ON_CPU1.5VS3#
RUN_ON_CPU1.5VS3
RUN_ON_CPU1.5VS3
+1.5V_MEM +1 .5V_CPU_VDDQ
+3.3V_ALW2
+VCC_GFXCORE
+1.8V_RUN
+V_SM_VREF_CNT
+VCC_SA
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
+V_DDR_SMREF
+V_SM_VREF_CNT
+1.5V_MEM
+PWR_SRC_S
+1.5V_CPU_VDDQ
+VCC_GFXCORE
+V_DDR_REF
+1.5V_MEM
+1.5V_CPU_VDDQ
CPU1.5V_S3_GATE<40>
RUN_ON_CPU1.5VS3# <7,42>
VCCSA_SENSE <50>
VCCSA_VID_1 <50>
VCCSA_VID_0 <50>
VCCP_PWRCTR L <49>
SIO_SLP_S3#<16,27,35,39,42,47,48,49>
VCC_AXG_SENSE <51>
VSS_AXG_SENSE <51>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (6/6)
11 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (6/6)
11 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
Ivy/Sandy Bridge (6/6)
11 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+1.5V_CPU_VDDQ Source
33A
5A
1.2A
6A
+V_SM_VREF should
have 10 mil trace width
added VCCSA_VID_0 to Power page
6A
Intel is recommended to provide stitching capacitors for
Vccd power planes +1.5V_MEM and +1.5V_CPU_VDDQ
(Follow Intel CRB) _0721
Depop RC140 for ES2 CPU
RC99
100_0402_1%~D
RC99
100_0402_1%~D
12
CC170
10U_0603_6.3V6M~D
CC170
10U_0603_6.3V6M~D
1
2
RC135 0_0402 _5%~D@RC135 0_0402_5 %~D@
1 2
CC166
10U_0603_6.3V6M~D
CC166
10U_0603_6.3V6M~D
1
2
RC97 1K_0402_1%~D@RC97 1K_0402_1%~D@
1 2
RC80
1K_0402_1%~D
@
RC80
1K_0402_1%~D
@
12
RC81
1K_0402_1%~D
@
RC81
1K_0402_1%~D
@
12
CC178 0.1U_0402_10V7K~DCC178 0.1U_0402_10V7K~D
12
RC78
1K_0402_1%~D
RC78
1K_0402_1%~D
12
RC73
20K_0402_5%~D
@
RC73
20K_0402_5%~D
@
12
CC173
10U_0603_6.3V6M~D
CC173
10U_0603_6.3V6M~D
1
2
CC149 0.1U_0402_10V7K~DCC149 0.1U_0402_10V7K~D
12
QC3
AO4304L_SO8
QC3
AO4304L_SO8
6
2
4
1
3
5
7
8
RC84
1K_0402_1%~D
RC84
1K_0402_1%~D
12
RC72
330K_0402_5%~D
RC72
330K_0402_5%~D
12
CC150 0.1U_0402_10V7K~DCC150 0.1U_0402_10V7K~D
12
+
CC172
330U_D2_2VM_R6M~D
+
CC172
330U_D2_2VM_R6M~D
1
2
RC96 1K_0402_1%~D@RC96 1K_0402_1%~D@
1 2
QC4B
DMN66D0LDW-7_SOT363-6~D
QC4B
DMN66D0LDW-7_SOT363-6~D
3
5
4
QC4A
DMN66D0LDW-7_SOT363-6~D
QC4A
DMN66D0LDW-7_SOT363-6~D
61
2
+
CC167
330U_D2_2VM_R6M~D
+
CC167
330U_D2_2VM_R6M~D
1
2
CC179 0.1U_0402_10V7K~DCC179 0.1U_0402_10V7K~D
12
CC174
1U_0402_6.3V6K~D
CC174
1U_0402_6.3V6K~D
1
2
CC135
10U_0603_6.3V6M~D
CC135
10U_0603_6.3V6M~D
1
2
CC169
10U_0603_6.3V6M~D
CC169
10U_0603_6.3V6M~D
1
2
CC161
10U_0603_6.3V6M~D
CC161
10U_0603_6.3V6M~D
1
2
RC76
100_0402_1%~D
@RC76
100_0402_1%~D
@
1 2
RC143
1M_0402_5%~D
RC143
1M_0402_5%~D
12
VSS
JCPU1H
TYCO_2013620-3_IVYBRIDGE
CONN@
VSS
JCPU1H
TYCO_2013620-3_IVYBRIDGE
CONN@
VSS1
AT35
VSS2
AT32
VSS3
AT29
VSS4
AT27
VSS5
AT25
VSS6
AT22
VSS7
AT19
VSS8
AT16
VSS9
AT13
VSS10
AT10
VSS11
AT7
VSS12
AT4
VSS13
AT3
VSS14
AR25
VSS15
AR22
VSS16
AR19
VSS17
AR16
VSS18
AR13
VSS19
AR10
VSS20
AR7
VSS21
AR4
VSS22
AR2
VSS23
AP34
VSS24
AP31
VSS25
AP28
VSS26
AP25
VSS27
AP22
VSS28
AP19
VSS29
AP16
VSS30
AP13
VSS31
AP10
VSS32
AP7
VSS33
AP4
VSS34
AP1
VSS35
AN30
VSS36
AN27
VSS37
AN25
VSS38
AN22
VSS39
AN19
VSS40
AN16
VSS41
AN13
VSS42
AN10
VSS43
AN7
VSS44
AN4
VSS45
AM29
VSS46
AM25
VSS47
AM22
VSS48
AM19
VSS49
AM16
VSS50
AM13
VSS51
AM10
VSS52
AM7
VSS53
AM4
VSS54
AM3
VSS55
AM2
VSS56
AM1
VSS57
AL34
VSS58
AL31
VSS59
AL28
VSS60
AL25
VSS61
AL22
VSS62
AL19
VSS63
AL16
VSS64
AL13
VSS65
AL10
VSS66
AL7
VSS67
AL4
VSS68
AL2
VSS69
AK33
VSS70
AK30
VSS71
AK27
VSS72
AK25
VSS73
AK22
VSS74
AK19
VSS75
AK16
VSS76
AK13
VSS77
AK10
VSS78
AK7
VSS79
AK4
VSS80
AJ25
VSS81
AJ22
VSS82
AJ19
VSS83
AJ16
VSS84
AJ13
VSS85
AJ10
VSS86
AJ7
VSS87
AJ4
VSS88
AJ3
VSS89
AJ2
VSS90
AJ1
VSS91
AH35
VSS92
AH34
VSS93
AH32
VSS94
AH30
VSS95
AH29
VSS96
AH28
VSS98
AH25
VSS99
AH22
VSS100
AH19
VSS101
AH16
VSS102
AH7
VSS103
AH4
VSS104
AG9
VSS105
AG8
VSS106
AG4
VSS107
AF6
VSS108
AF5
VSS109
AF3
VSS110
AF2
VSS111
AE35
VSS112
AE34
VSS113
AE33
VSS114
AE32
VSS115
AE31
VSS116
AE30
VSS117
AE29
VSS118
AE28
VSS119
AE27
VSS120
AE26
VSS121
AE9
VSS122
AD7
VSS123
AC9
VSS124
AC8
VSS125
AC6
VSS126
AC5
VSS127
AC3
VSS128
AC2
VSS129
AB35
VSS130
AB34
VSS131
AB33
VSS132
AB32
VSS133
AB31
VSS134
AB30
VSS135
AB29
VSS136
AB28
VSS137
AB27
VSS138
AB26
VSS139
Y9
VSS140
Y8
VSS141
Y6
VSS142
Y5
VSS143
Y3
VSS144
Y2
VSS145
W35
VSS146
W34
VSS147
W33
VSS148
W32
VSS149
W31
VSS150
W30
VSS151
W29
VSS152
W28
VSS153
W27
VSS154
W26
VSS155
U9
VSS156
U8
VSS157
U6
VSS158
U5
VSS159
U3
VSS160
U2
RC82 0_0402_5%~D
@
RC82 0_0402_5%~D
@
1 2
CC162
10U_0603_6.3V6M~D
CC162
10U_0603_6.3V6M~D
1
2
CC168
10U_0603_6.3V6M~D
@
CC168
10U_0603_6.3V6M~D
@
1
2
RC134 0_0402 _5%~D@RC134 0_0402_5 %~D@
1 2
RC100
100_0402_1%~D
RC100
100_0402_1%~D
12
CC171
10U_0603_6.3V6M~D
CC171
10U_0603_6.3V6M~D
1
2
CC163
10U_0603_6.3V6M~D
CC163
10U_0603_6.3V6M~D
1
2
RC140 0_0402_5%~D@RC140 0_0402_5%~D@
1 2
CC175
1U_0402_6.3V6K~D
CC175
1U_0402_6.3V6K~D
1
2
CC164
10U_0603_6.3V6M~D
CC164
10U_0603_6.3V6M~D
1
2
RC79 0_0402_5%~D@RC79 0_0402_5%~D@
1 2
RC74
100K_0402_5%~D
RC74
100K_0402_5%~D
12
QC5
NTR4503NT1G_SOT23-3~D
@QC5
NTR4503NT1G_SOT23-3~D
@
1
2
3
CC136
0.022U_0402_25V7K~D
CC136
0.022U_0402_25V7K~D
1
2
CC165
10U_0603_6.3V6M~D
CC165
10U_0603_6.3V6M~D
1
2
+
CC176
330U_D2_2.5VM_R6M~D
+
CC176
330U_D2_2.5VM_R6M~D
1
2
POWER
GRAPHICS
DDR3 -1.5V RAILS
SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
JCPU1G
TYCO_2013620-3_IVYBRIDGE
CONN@
POWER
GRAPHICS
DDR3 -1.5V RAILS
SENSE
LINES
1.8V RAIL
SA RAIL
VREFMISC
JCPU1G
TYCO_2013620-3_IVYBRIDGE
CONN@
SM_VREF
AL1
VSSAXG_SENSE
AK34
VAXG_SENSE
AK35
VAXG1
AT24
VAXG2
AT23
VAXG3
AT21
VAXG4
AT20
VAXG5
AT18
VAXG6
AT17
VAXG7
AR24
VAXG8
AR23
VAXG9
AR21
VAXG10
AR20
VAXG11
AR18
VAXG12
AR17
VAXG13
AP24
VAXG14
AP23
VAXG15
AP21
VAXG16
AP20
VAXG17
AP18
VAXG18
AP17
VAXG19
AN24
VAXG20
AN23
VAXG21
AN21
VAXG22
AN20
VAXG23
AN18
VAXG24
AN17
VAXG25
AM24
VAXG26
AM23
VAXG27
AM21
VAXG28
AM20
VAXG29
AM18
VAXG30
AM17
VAXG31
AL24
VAXG32
AL23
VAXG33
AL21
VAXG34
AL20
VAXG35
AL18
VAXG36
AL17
VAXG37
AK24
VAXG38
AK23
VAXG39
AK21
VAXG40
AK20
VAXG41
AK18
VAXG42
AK17
VAXG43
AJ24
VAXG44
AJ23
VAXG45
AJ21
VAXG46
AJ20
VAXG47
AJ18
VAXG48
AJ17
VAXG49
AH24
VAXG50
AH23
VAXG51
AH21
VAXG52
AH20
VAXG53
AH18
VAXG54
AH17
VDDQ11
U4
VDDQ12
U1
VDDQ13
P7
VDDQ14
P4
VDDQ15
P1
VDDQ1
AF7
VDDQ2
AF4
VDDQ3
AF1
VDDQ4
AC7
VDDQ5
AC4
VDDQ6
AC1
VDDQ7
Y7
VDDQ8
Y4
VDDQ9
Y1
VDDQ10
U7
VCCPLL1
B6
VCCPLL2
A6
VCCSA1
M27
VCCSA2
M26
VCCSA3
L26
VCCSA4
J26
VCCSA5
J25
VCCSA6
J24
VCCSA7
H26
VCCSA8
H25
VCCSA_SENSE
H23
VCCSA_VID[1]
C24
VCCPLL3
A2
VCCSA_VID[0]
C22
SA_DIMM_VREFDQ
B4
SB_DIMM_VREFDQ
D1
VCCIO_SEL
A19
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D32
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D45
DDR_A_D46
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_MA2
DDR_A_MA0DDR_A_MA1
DDR_A_MA3
DDR_A_MA4DDR_A_MA5
DDR_A_MA6DDR_A_MA8
DDR_A_MA7DDR_A_MA9
DDR_A_MA10
DDR_A_MA11DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7
DDR_A_BS0
DDR_A_BS1
DDR_A_BS2
DDR_CS1_DIMMA#
DDR_CS0_DIMMA#
M_CLK_DDR0
M_CLK_DDR#0
M_CLK_DDR1
M_CLK_DDR#1
DDR_CKE0_DIMMA DDR_CKE1_DIMMA
DDR_A_CAS#
DDR_A_RAS#
DDR_A_WE#
M_ODT0
M_ODT1
DDR_A_D63
DDR_A_MA15
DDR_A_D39
DDR_A_D54
DDR_A_D33
DDR_A_D38
DDR_A_D47
DDR_A_D44
DDR_A_D48
DDR3_DRAMRST#_R
DDR_HVREF_RST
DDR_HVREF_RST
DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D8
DDR_A_D10
DDR_A_D11
DDR_A_D18
DDR_A_D19
DDR_A_D26
DDR_A_D27
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_D17
DDR_A_D9
DDR_A_D16
DDR_A_D25
DDR_A_D24
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D21
DDR_A_D28
DDR_A_D29
DDR_A_DQS0
DDR_A_DQS3
DDR_A_DQS#0
DDR_A_DQS#3
DDR_A_D23
DDR_A_D31
DDR_A_D13
DDR_A_D20
DDR_A_D30
DDR_A_D14
DDR_A_D15
DDR_A_D12
DDR_A_D22
DDR3_DRAMRST#_R
+0.75V_DDR_VTT
+1.5V_MEM
+3.3V_RUN
+0.75V_DDR_VTT
+0.75V_DDR_VTT
+DIMM1_VREF_CA
+1.5V_MEM
+V_DDR_REF
+1.5V_MEM
+DIMM0_1_VREF_CPU
+DIMM0_1_CA_CPU
+V_DDR_REFA_M3
+V_DDR_REFB_M3
+V_DDR_REFA_M3
+V_DDR_REF
+1.5V_MEM
+DIMM1_VREF_DQ
+1.5V_MEM
DDR_A_D[0..63]<8>
DDR_A_DQS[0..7]<8>
DDR_A_MA[0..15]<8>
DDR_A_DQS#[0..7]<8>
DDR_CKE0_DIMMA<8>
DDR_A_BS2<8>
DDR_CS1_DIMMA#<8>
DDR_A_WE#<8>
DDR_A_CAS#<8>
DDR_A_BS0<8>
DDR_A_BS1 <8>
M_ODT0 <8>
DDR_A_RAS# <8>
M_CLK_DDR1 <8>
M_CLK_DDR#1 <8>M_CLK_DDR#0<8>
M_CLK_DDR0<8>
DDR_CKE1_DIMMA <8>
DDR_CS0_DIMMA# <8>
M_ODT1 <8>
DDR3_DRAMRST# <7>DDR3_DRAMRST#_R<13>
DDR_XDP_WAN_ SMBCLK <7,13,14,15,27,34>
DDR_XDP_WAN_ SMBDAT <7,13,14,15,27,34>
DDR_HVREF_RST<7>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
DDRIII-SODIMM SLOT1
12 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
DDRIII-SODIMM SLOT1
12 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
DDRIII-SODIMM SLOT1
12 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Layout Note:
Place near JDIMM1
Layout Note:
Place near JDIMM1.203,204
Populate RD1, De-Populate RD7 for Intel DDR3
VREFDQ multiple methods M1
Populate RD7, De-Populate RD1 for Intel DDR3
VREFDQ multiple methods M3
JDIMM1 H=8
All VREF traces should
have 10 mil trace width
M3 Circuit (Processor Generated SO-DIMM VREF_DQ)
Reverse Type
2-3A to 1 DIMMs/channel
Follow CON N List_060 9A
RD3 10K_0402_5%~DRD3 10K_0402_5%~D
1 2
RD29 0_0402_5%~D@RD29 0_0402_5%~D@
1 2
CD19
1U_0402_6.3V6K~D
CD19
1U_0402_6.3V6K~D
1
2
CD15
2.2U_0603_6.3V6K~D
CD15
2.2U_0603_6.3V6K~D
1
2
RD2 10K_0402_5%~DRD2 10K_0402_5%~D
1 2
CD16
0.1U_0402_25V6K~D
CD16
0.1U_0402_25V6K~D
1
2
RD30 0_0402_5%~D@RD30 0_0402_5%~D@
1 2
G
D
S
QD1
BSS138_NL_SOT23-3
G
D
S
QD1
BSS138_NL_SOT23-3
2
13
CD2
0.1U_0402_25V6K~D
CD2
0.1U_0402_25V6K~D
1
2
CD8
10U_0603_6.3V6M~D
CD8
10U_0603_6.3V6M~D
1
2
CD18
1U_0402_6.3V6K~D
CD18
1U_0402_6.3V6K~D
1
2
+
CD14
330U_SX_2VY~D
+
CD14
330U_SX_2VY~D
1
2
RD7 0_0402_5%~D@ RD7 0_0402_5%~D@
1 2
G
D
S
QD2
BSS138_NL_SOT23-3
G
D
S
QD2
BSS138_NL_SOT23-3
2
13
CD4
1U_0402_6.3V6K~D
CD4
1U_0402_6.3V6K~D
1
2
RD11 0_0402_5%~D@RD11 0_0402_5%~D@
12
RD1 0_0402_5%~D@ RD1 0_0402_5%~D@
1 2
JDIMM1
TYCO_2-2013298-1~D
CONN@
JDIMM1
TYCO_2-2013298-1~D
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
CD7
10U_0603_6.3V6M~D
CD7
10U_0603_6.3V6M~D
1
2
CD3
1U_0402_6.3V6K~D
CD3
1U_0402_6.3V6K~D
1
2
CD5
1U_0402_6.3V6K~D
CD5
1U_0402_6.3V6K~D
1
2
CD22
2.2U_0603_6.3V6K~D
CD22
2.2U_0603_6.3V6K~D
1
2
CD17
1U_0402_6.3V6K~D
CD17
1U_0402_6.3V6K~D
1
2
CD13
10U_0603_6.3V6M~D
@CD13
10U_0603_6.3V6M~D
@
1
2
RD28 1K_0402_1%~DRD28 1K_0402_1%~D
1 2
CD6
1U_0402_6.3V6K~D
CD6
1U_0402_6.3V6K~D
1
2
CD9
10U_0603_6.3V6M~D
CD9
10U_0603_6.3V6M~D
1
2
CD1
2.2U_0603_6.3V6K~D
CD1
2.2U_0603_6.3V6K~D
1
2
CD21
0.1U_0402_25V6K~D
CD21
0.1U_0402_25V6K~D
1
2
CD10
10U_0603_6.3V6M~D
CD10
10U_0603_6.3V6M~D
1
2
RD27
1K_0402_1%~D
RD27
1K_0402_1%~D
12
CD11
10U_0603_6.3V6M~D
CD11
10U_0603_6.3V6M~D
1
2
CD20
1U_0402_6.3V6K~D
CD20
1U_0402_6.3V6K~D
1
2
CD51
10U_0603_6.3V6M~D
CD51
10U_0603_6.3V6M~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_MA7
DDR_B_D62
DDR_B_D59
DDR_CS3_DIMMB#
DDR_B_BS0
DDR_B_D52
M_ODT2
DDR_B_MA14
DDR_B_D57
DDR_B_DQS6
DDR_B_D43
DDR_B_DQS4
DDR_B_BS2
DDR_B_D37
DDR_B_D36
DDR_B_MA6
DDR_B_D41
DDR_B_MA3
DDR_B_D63
DDR_B_D44
DDR_B_D40
DDR_CKE2_DIMMB
DDR_B_D54
DDR_B_D53
DDR_B_D46
DDR_CKE3_DIMMB
DDR_B_D50
DDR_B_D48
DDR_B_D61
DDR_B_MA4
DDR_B_MA1
DDR_B_D45
DDR_B_D38
DDR_B_BS1
DDR_B_WE#
DDR_B_D55
DDR_B_D47
M_ODT3
DDR_B_D49
DDR_B_MA12
M_CLK_DDR3
DDR_B_RAS#
DDR_B_D34
DDR_B_D32
DDR_B_CAS#
DDR_B_DQS#6
DDR_B_MA8
DDR_B_DQS7
DDR_B_DQS#7
M_CLK_DDR#3
DDR_B_MA2
DDR_B_MA15
DDR_B_DQS#5
DDR_B_MA11
DDR_B_D51
DDR_B_D35
DDR_B_D33
M_CLK_DDR2
DDR_B_D60
DDR_B_MA5
DDR_B_D39
DDR_B_MA0
DDR_B_D58
DDR_B_MA10
DDR_B_DQS5
DDR_CS2_DIMMB#
DDR_B_D56
DDR_B_D42
DDR_B_DQS#4
DDR_B_MA13
M_CLK_DDR#2
DDR_B_MA9
DDR_B_D22
DDR_B_D20
DDR3_DRAMRST#_R
DDR_B_D23
DDR_B_D21
DDR_B_DQS#3
DDR_B_D14
DDR_B_DQS3
DDR_B_D7
DDR_B_D6
DDR_B_D15
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D12
DDR_B_D31
DDR_B_D13
DDR_B_D4
DDR_B_D5
DDR_B_DQS#0
DDR_B_DQS0
DDR_B_D27
DDR_B_D8
DDR_B_DQS1
DDR_B_D9
DDR_B_DQS#1
DDR_B_D2
DDR_B_D0
DDR_B_D1
DDR_B_D3
DDR_B_D10
DDR_B_D11
DDR_B_D16
DDR_B_D17
DDR_B_DQS#2
DDR_B_DQS2
DDR_B_D18
DDR_B_D19
DDR_B_D24
DDR_B_D25
DDR_B_D26
+1.5V_MEM
+0.75V_DDR_VTT
+3.3V_RUN
+3.3V_RUN
+0.75V_DDR_VTT
+DIMM2_VREF_CA
+1.5V_MEM
+0.75V_DDR_VTT
+V_DDR_REF
+1.5V_MEM+1.5V_MEM+DIMM2_VREF_DQ
+V_DDR_REFB_M3
+V_DDR_REF
DDR_B_D[0..63]<8>
DDR_B_DQS[0..7]<8>
DDR_B_MA[0..15]<8>
DDR_B_DQS#[0..7]<8>
DDR_B_CAS#<8>
DDR_CKE3_DIMMB <8>
DDR_B_WE#<8>
DDR_CKE2_DIMMB<8>
DDR_B_BS0<8>
DDR_B_RAS# <8>
DDR_B_BS1 <8>
DDR_B_BS2<8>
M_ODT2 <8>
DDR_CS3_DIMMB#<8>
DDR_CS2_DIMMB# <8>
M_CLK_DDR3 <8>
M_CLK_DDR#3 <8>
M_ODT3 <8>
M_CLK_DDR2<8>
M_CLK_DDR#2<8>
DDR_XDP_WAN_ SMBCLK <7,12,14,15,27,34>
DDR_XDP_WAN_ SMBDAT <7,12,14,15,27,34>
DDR3_DRAMRST#_R <12>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
DDRIII-SODIMM SLOT2
13 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
DDRIII-SODIMM SLOT2
13 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
DDRIII-SODIMM SLOT2
13 61W ednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Layout Note:
Place near JDIMM2
Layout Note:
Place near JDIMM2.203,204
All VREF traces should
have 10 mil trace width
Populate RD4, De-Populate RD8 for Intel DDR3
VREFDQ multiple methods M1
Populate RD8, De-Populate RD4 for Intel DDR3
VREFDQ multiple methods M3
Reverse Type
2-3A to 1 DIMMs/channel
JDIMM2 H=4
Check connection and symbol
JDIMM2
FOX_AS0A626-U4RN-7F
CONN@
JDIMM2
FOX_AS0A626-U4RN-7F
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
+
CD36
330U_SX_2VY~D
+
CD36
330U_SX_2VY~D
1
2
CD34
10U_0603_6.3V6M~D
CD34
10U_0603_6.3V6M~D
1
2
CD37
2.2U_0603_6.3V6K~D
CD37
2.2U_0603_6.3V6K~D
1
2
RD6
10K_0402_5%~D
RD6
10K_0402_5%~D
12
CD38
0.1U_0402_25V6K~D
CD38
0.1U_0402_25V6K~D
1
2
CD35
10U_0603_6.3V6M~D
@CD35
10U_0603_6.3V6M~D
@
1
2
RD4 0_0402_5%~D@ RD4 0_0402_5%~D@
1 2
CD26
1U_0402_6.3V6K~D
CD26
1U_0402_6.3V6K~D
1
2
CD31
10U_0603_6.3V6M~D
CD31
10U_0603_6.3V6M~D
1
2
RD8 0_0402_5%~D@ RD8 0_0402_5%~D@
1 2
CD44
2.2U_0603_6.3V6K~D
CD44
2.2U_0603_6.3V6K~D
1
2
CD27
1U_0402_6.3V6K~D
CD27
1U_0402_6.3V6K~D
1
2
CD33
10U_0603_6.3V6M~D
CD33
10U_0603_6.3V6M~D
1
2
RD15 0_0402_5%~D@RD15 0_0402_5%~D@
12
CD30
10U_0603_6.3V6M~D
CD30
10U_0603_6.3V6M~D
1
2
CD25
1U_0402_6.3V6K~D
CD25
1U_0402_6.3V6K~D
1
2
CD39
1U_0402_6.3V6K~D
CD39
1U_0402_6.3V6K~D
1
2
CD23
2.2U_0603_6.3V6K~D
CD23
2.2U_0603_6.3V6K~D
1
2
CD28
1U_0402_6.3V6K~D
CD28
1U_0402_6.3V6K~D
1
2
CD29
10U_0603_6.3V6M~D
CD29
10U_0603_6.3V6M~D
1
2
CD24
0.1U_0402_25V6K~D
CD24
0.1U_0402_25V6K~D
1
2
CD32
10U_0603_6.3V6M~D
CD32
10U_0603_6.3V6M~D
1
2
CD42
1U_0402_6.3V6K~D
CD42
1U_0402_6.3V6K~D
1
2
RD5 10K_04 02_5%~DRD 5 10K_0402_5%~D
12
CD40
1U_0402_6.3V6K~D
CD40
1U_0402_6.3V6K~D
1
2
CD43
0.1U_0402_25V6K~D
CD43
0.1U_0402_25V6K~D
1
2
CD41
1U_0402_6.3V6K~D
CD41
1U_0402_6.3V6K~D
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_AZ_SDOUT
LPC_LDRQ1#
PCH_JTAG_TCK
PCH_AZ_RST#
SATA_COMP
PCH_AZ_BITCLK
SRTCRST#
SATA_ACT#
PCH_RTCX1
PCH_RTCRST#
LPC_LAD0
PCH_RTCX2_R
PCH_INTVRMEN
PCH_JTAG_TDI
LPC_LAD3
INTRUDER#
PCH_AZ_SYNC_Q
IRQ_SERIRQ
PCH_JTAG_TMS
PCH_JTAG_TDO
PCH_INTVRMEN
PCH_RTCX2
+3.3V_ALW_PCH_JTAG
LPC_LAD2
LPC_LAD1
PCH_AZ_MDC_SDIN1
LPC_LFRAME#
PCH_AZ_RST#
PCH_AZ_CODEC_SDIN0
PCH_AZ_SDOUT
PCH_AZ_BITCLK
HDD_DET#_R
BBS_BIT0_R
PCH_AZ_SYNC
XDP_FN15
PCH_PWRBTN#_XDP
DDR_XDP_WAN_SMBDAT_R2
DDR_XDP_WAN_SMBCLK_R2
XDP_DBRESET#
PCH_JTAG_TDO
PCH_JTAG_TDI
PCH_JTAG_TMSPCH_JTAG_TCK
RSMRST#_XDP
XDP_FN0
XDP_FN1
XDP_FN2
XDP_FN3
XDP_FN4
XDP_FN5
XDP_FN6
XDP_FN7
XDP_FN16
XDP_FN17
XDP_FN8
XDP_FN9
XDP_FN10
XDP_FN11
XDP_FN12
XDP_FN13
XDP_FN14
USB_OC4#_R
USB_OC2#
USB_OC5#
USB_OC3#
SIO_EXT_SMI#
USB_OC6#
USB_OC0#_R
USB_OC1#_R
XDP_FN8
XDP_FN9
XDP_FN11
XDP_FN10
XDP_FN12
XDP_FN13
XDP_FN14
SLP_ME_CSW_DEV#
XDP_FN15
XDP_FN16
XDP_FN17
USB_MCARD1_DET#
HDD_DET#_R
BBS_BIT0_R
PCH_GPIO37
PCH_GPIO16
TEMP_ALERT#
SIO_EXT_SCI#_R
PCH_GPIO15
XDP_FN2
XDP_FN1
XDP_FN4
XDP_FN6
XDP_FN5
XDP_FN3
XDP_FN0
XDP_FN7
RBIAS_SATA3
SATA3_COMP
SPKR
IRQ_SERIRQ
PCH_SPI_CLK
PCH_SPI_CS1#
PCH_SPI_DIN
PCH_SPI_DO
PCH_GPIO33
1.05V_0.8V_PWROK_R
PCH_SPI_CS0#
PCH_SPI_DIN
PCH_SPI_CLK
PCH_SPI_DO
PCH_SPI_CS1#
PCH_SPI_CS0#
SPI_PCH_CS1#
SPI_PCH_CLK
SPI_PCH_DIN
SPI_PCH_DO
SPI_PCH_CS0#
RSMRST#_XDP
PCH_GPIO36
PCH_AZ_SYNCPCH_AZ_SYNC_Q
PCH_AZ_SYNC
PCH_GPIO33
BBS_BIT0_R
PCH_AZ_SYNC_Q
SPI_PCH_DO
SPI_PCH_CLKSPI_CLK32
SPI_HOLD#
SPI_DO32SPI_WP#_SEL_R
SPI_PCH_DIN SPI_DIN32
SPI_PCH_CS1#
SPI_CLK32SPI_CLK64
SPI_PCH_CS1#_R
PCH_GPIO13
PCH_GPIO13
SPI_CLK64
SPI_DO64
SPI_WP#_SEL SPI_WP#_SEL_R
SPI_PCH_DIN SPI_DIN64
SPI_PCH_DO
SPI_PCH_CLK
SPI_HOLD#
SPI_PCH_CS0# SPI_PCH_CS0#_R
+3.3V_ALW_PCH
+RTC_CELL
+3.3V_RUN
+1.05V_RUN
+RTC_CELL
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+1.05V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_M_RUN
+3.3V_SPI
+3.3V_RUN
+3.3V_ALW_PCH
+5V_RUN
+3.3V_SPI
+3.3V_ALW_PCH
+3.3V_M_RUN
+3.3V_M
+3.3V_RUN
+3.3V_SPI
PCH_AZ_MDC_SDIN1<37>
PCH_AZ_MDC_RST#<37>
PCH_AZ_CODEC_SDIN0<29>
PCH_AZ_CODEC_SYNC<29>
PCH_AZ_CODEC_SDOUT<29>
IRQ_SERIRQ <32,39,40>
PCH_AZ_MDC_BITCLK<37>
PCH_AZ_CODEC_RST#<29>
SATA_ACT# <43>
SPKR<29>
HDD_DET# <27>
PCH_AZ_MDC_SYNC<37>
PCH_AZ_MDC_SDOUT<37>
PCH_AZ_CODEC_BITCLK< 29>
XDP_DBRESET# <7,16>
SIO_PWRBTN#_R<7,16>
SLP_ME_CSW_DEV#<18,39>
USB_MCARD1_DET#<18,34>
PCH_GPIO15<18>
TEMP_ALERT#<18,39>
PCH_GPIO16<18>
PCH_GPIO37<18>
USB_OC3#<17>
USB_OC2#<17>
SIO_EXT_SCI#_R<18>
USB_OC6#<17>
USB_OC5#<17>
USB_OC4#_R<17>
SIO_EXT_SMI#<17,40>
USB_OC1#_R<17>
USB_OC0#_R<17>
PSATA_PRX_DTX_N0_C <27>
PSATA_PTX_DRX_P0_C <27>
PSATA_PTX_DRX_N0_C <27>
PSATA_PRX_DTX_P0_C <27>
SATA_PRX_DKTX_P5_C <38>
SATA_PRX_DKTX_N5_C <38>
SATA_PTX_DKRX_P5_C <38>
SATA_PTX_DKRX_N5_C <38>
ESATA_PTX_DRX_P4_C <36>
ESATA_PRX_DTX_P4_C <36>
ESATA_PRX_DTX_N4_C <36>
ESATA_PTX_DRX_N4_C <36>
SATA_ODD_PRX_DTX_P1_C <28>
SATA_ODD_PTX_DRX_N1_C <28>
SATA_ODD_PTX_DRX_P1_C <28>
SATA_ODD_PRX_DTX_N1_C <28>
PCH_SATA_MOD_EN# <40>
ME_FWP<39>
1.05V_0.8V_PWROK<40,51>
LPC_LAD0 <32,34,39,40>
LPC_LAD1 <32,34,39,40>
LPC_LAD2 <32,34,39,40>
LPC_LAD3 <32,34,39,40>
LPC_LFRAME# <32,34, 39,40>
LPC_LDRQ1# <39>
PCH_PLTRST#<7,17>
PCH_RSMRST#_Q<16,41>
PCH_GPIO36<18>
DDR_XDP_WAN_SMBCLK<7,12,13,15,27,34>
DDR_XDP_WAN_SMBDAT<7,12,13,15,27,34>
SPI_WP#_SEL<39>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (1/8)
14 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (1/8)
14 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (1/8)
14 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
INTVRMEN- Integrated SUS
1.1V VRM Enable
High - Enable Internal VRs
Low - Enable External VRs
On Die PLL VR is supplied by
1.5V when sampled high, 1.8 V
when sampled low
CMOS place near DIMM
HDD
E-SATA
DOCK
Low = Default
High = No Reboot
SPKR
No Reboot Strap
ODD/ E Module Bay
BBS_BIT0 - BIOS BOOT STRAP BIT 0
CMOS settingCMOS_CLR1
Open
Clear CMOSShunt
ME_CLR1
Keep CMOS
TPM setting
Shunt
Keep ME RTC Registers
Clear ME RTC Registers
Open
PCH_AZ_SYNC is sampled
at the rising edge of RSMRST# pin.
So signal should be PU to the ALWAYS rail.
*
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Follow INTEL CRB 0.7
INTEL feedback 0302
32Mb Flash ROM
200 MIL SO8
RF review in 0629
INTEL HDA_SYNC
isolation circuit
200 MIL SO8
64Mb Flash ROM
ME1 SHORT PADS~D
@
ME1 SHORT PADS~D
@
1
1
2
2
RH12 33_0402_5%~DPXDP@ RH12 33_0402_5%~DPXDP@
1 2
RH5 33_0402_5%~DPXDP@ RH5 33_0402_5%~DPXDP@
1 2
CMOS1 SHORT PADS~D
@
CMOS1 SHORT PADS~D
@
1
1
2
2
RH59 51_0402_1%~DRH59 51_0402_1%~D
12
CH4
1U_0402_6.3V6K~D
CH4
1U_0402_6.3V6K~D
1 2
JXDP2
SAMTE_BSH-030-01-L-D-A
CONN@
JXDP2
SAMTE_BSH-030-01-L-D-A
CONN@
GND0
1
OBSFN_A0
3
OBSFN_A1
5
GND2
7
OBSDATA_A 0
9
OBSDATA_A 1
11
GND4
13
OBSDATA_A 2
15
OBSDATA_A 3
17
GND6
19
OBSFN_B0
21
OBSFN_B1
23
GND8
25
OBSDATA_B 0
27
OBSDATA_B 1
29
GND10
31
OBSDATA_B 2
33
OBSDATA_B 3
35
GND12
37
PWRGOO D/HOOK0
39
HOOK1
41
VCC_OBS_ AB
43
HOOK2
45
HOOK3
47
GND14
49
SDA
51
SCL
53
TCK1
55
TCK0
57
GND16
59
GND1
2
OBSFN_C0
4
OBSFN_C1
6
GND3
8
OBSDATA_C0
10
OBSDATA_C1
12
GND5
14
OBSDATA_C2
16
OBSDATA_C3
18
GND7
20
OBSFN_D0
22
OBSFN_D1
24
GND9
26
OBSDATA_D0
28
OBSDATA_D1
30
GND11
32
OBSDATA_D2
34
OBSDATA_D3
36
GND13
38
ITPCLK/HOOK 4
40
ITPCLK#/HOO K5
42
VCC_OBS_ CD
44
RESET#/HOO K6
46
DBR#/HOOK 7
48
GND15
50
TD0
52
TRST#
54
TDI
56
TMS
58
GND17
60
C746
0.1U_0402_25V6K~D
C746
0.1U_0402_25V6K~D
1 2
CE2
27P_0402_50V8J~D
@
CE2
27P_0402_50V8J~D
@
1
2
RH346 0_0402_5%~DRH346 0_0402_5%~D
1 2
RH14 33_0402_5%~DPXDP@ RH14 33_0402_5%~DPXDP@
1 2
RH8 33_0402_5%~DPXDP@ RH8 33_0402_5%~DPXDP@
1 2
RH286 0_0402_5%~D@ RH286 0_0402_5%~D@
1 2
CH3
18P_0402_50V8J~D
CH3
18P_0402_50V8J~D
12
RH22 20K_0402_5%~DRH22 20K_0402_5%~D
1 2
RH350 0_0603_5%~DRH350 0_0603_5%~D
1 2
R898 0_0402_5%~D@R898 0_0402_5%~D@
1 2
RH35 10K_0402_5%~D@ RH35 10K_0402_5%~D@
12
U53
W25Q32BVSSIG_SO8
U53
W25Q32BVSSIG_SO8
CS#
1
DO
2
WP#
3
GND
4
VCC
8
HOLD#
7
CLK
6
DI
5
RH9 33_0402_5%~DPXDP@ RH9 33_0402_5%~DPXDP@
1 2
R891
3.3K_0402_5%~D
R891
3.3K_0402_5%~D
12
RH288
0_0603_5%~D
@
RH288
0_0603_5%~D
@
12
R900 33_0402_5%~DR900 33_0402_5%~D
1 2
RH20 33_0402_5%~DPXDP@ RH20 33_0402_5%~DPXDP@
1 2
RH15 33_0402_5%~DPXDP@ RH15 33_0402_5%~DPXDP@
1 2
RH40 37.4_0402_1%~DRH40 37.4_0402_1%~D
1 2
CE1
27P_0402_50V8J~D
@
CE1
27P_0402_50V8J~D
@
1
2
CH2
18P_0402_50V8J~D
CH2
18P_0402_50V8J~D
12
RH46 750_0402_1%~DRH46 750_0402_1%~D
1 2
U52
W25Q64CVSSIG_SO8~D
U52
W25Q64CVSSIG_SO8~D
CLK
6
GND
4
DIO
5
DO
2
/WP
3
VCC
8
/HOLD
7
/CS
1
RH2
10M_0402_5%~D
RH2
10M_0402_5%~D
12
RH359 0_0603_5%~D@RH359 0_0603_5%~D@
1 2
RH48
100_0402_1%~D
@
RH48
100_0402_1%~D
@
12
RH25 33_0402_5%~DRH25 33_0402_5%~D
1 2
RH290 0_0402_5%~D@ RH290 0_0402_5%~D@
1 2
RH10 33_0402_5%~DPXDP@ RH10 33_0402_5%~DPXDP@
1 2
R895 33_0402_5%~DR895 33_0402_5%~D
1 2
R936 47_0402_5%~DR936 47_0402_5%~D
1 2
RH49
100_0402_1%~D
@
RH49
100_0402_1%~D
@
12
R901 33_0402_5%~DR901 33_0402_5%~D
1 2
RH29 33_0402_5%~DRH29 33_0402_5%~D
1 2
RH66
1K_0402_1%~D
RH66
1K_0402_1%~D
12
RH3 33_0402_5%~DPXDP@ RH3 33_0402_5%~DPXDP@
1 2
RH347 0_0402_5%~DRH347 0_0402_5%~D
1 2
R712 100K_0402_5%~DR712 100K_0402_5%~D
12
RE2
33_0402_5%~D
@
RE2
33_0402_5%~D
@
12
RH285 0_0402_5%~DPXDP@ RH285 0_0402_5%~DPXDP@
1 2
RH23 20K_0402_5%~DRH23 20K_0402_5%~D
1 2
RH32 33_0402_5%~DRH32 33_0402_5%~D
1 2
RH52 4.7K_0402_5%~DRH52 4.7K_0402_5%~D
12
R890
3.3K_0402_5%~D
R890
3.3K_0402_5%~D
12
RH50 1K_0402_1%~DRH50 1K_0402_1%~D
1 2
RH42 49.9_0402_1%~DRH42 49.9_0402_1%~D
1 2
RE1
33_0402_5%~D
@
RE1
33_0402_5%~D
@
12
RH16 33_0402_5%~DPXDP@ RH16 33_0402_5%~DPXDP@
1 2
RH31 1M_0402_5%~DRH31 1M_0402_5%~D
1 2
RH21 0_0402_5%~DPXDP@ RH21 0_0402_5%~DPXDP@
1 2
R897 33_0402_5%~DR897 33_0402_5%~D
1 2
RH6 33_0402_5%~DPXDP@ RH6 33_0402_5%~DPXDP@
1 2
RH34 33_0402_5%~DRH34 33_0402_5%~D
1 2
R899 33_0402_5%~DR899 33_0402_5%~D
1 2
RH43 200_0402_1%~DRH43 200_0402_1%~D
12
RH45 200_0402_1%~DRH45 200_0402_1%~D
12
RH283 1K_0402_1%~DPXDP@ RH283 1K_0402_1%~DPXDP@
1 2
RH47
100_0402_1%~D
@
RH47
100_0402_1%~D
@
12
RH4 33_0402_5%~DPXDP@ RH4 33_0402_5%~DPXDP@
1 2
RH11 1M_0402_5%~DRH11 1M_0402_5%~D
1 2
RH27 33_0402_5%~DRH27 33_0402_5%~D
1 2
R894 33_0402_5%~DR894 33_0402_5%~D
1 2
RH36 33_0402_5%~DRH36 33_0402_5%~D
1 2
CE15
10P_0402_50V8J~D
@
CE15
10P_0402_50V8J~D
@
1
2
RH1 33_0402_5%~DPXDP@ RH1 33_0402_5%~DPXDP@
1 2
RH355 100K_0402_5%~DRH355 100K_0402_5%~D
12
RH345 0_0402_5%~DRH345 0_0402_5%~D
1 2
RH13 33_0402_5%~DPXDP@ RH13 33_0402_5%~DPXDP@
1 2
RH28 8.2K_0402_5%~DRH28 8.2K_0402_5%~D
12
RH284 0_0402_5%~DPXDP@ RH284 0_0402_5%~DPXDP@
1 2
R935 47_0402_5%~DR935 47_0402_5%~D
1 2
RH349 0_0402_5%~DRH349 0_0402_5%~D
1 2
RH44 200_0402_1%~DRH44 200_0402_1%~D
12
RH39
330K_0402_1%~D
@RH39
330K_0402_1%~D
@
12
RH348 0_0402_5%~DRH348 0_0402_5%~D
1 2
RH19 33_0402_5%~DPXDP@ RH19 33_0402_5%~DPXDP@
1 2
C745
0.1U_0402_25V6K~D
C745
0.1U_0402_25V6K~D
1 2
YH1
32.768KHZ_12.5PF_Q13FC1350000~D
YH1
32.768KHZ_12.5PF_Q13FC1350000~D
12
RH7 33_0402_5%~DPXDP@ RH7 33_0402_5%~DPXDP@
1 2
RH287 1K_0402_1%~D@RH287 1K_0402_1%~D@
1 2
RH33 33_0402_5%~DRH33 33_0402_5%~D
1 2
RH18 33_0402_5%~DPXDP@ RH18 33_0402_5%~DPXDP@
1 2
RH38
330K_0402_1%~D
RH38
330K_0402_1%~D
12
CH100
27P_0402_50V8J~D
@CH100
27P_0402_50V8J~D
@
12
JSPI1
HRS_FH12-16S-0P5SH(55)~D
CONN@
JSPI1
HRS_FH12-16S-0P5SH(55)~D
CONN@
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
G1
17
G2
18
RH30
10K_0402_5%~D
RH30
10K_0402_5%~D
12
CH5 1U_0402_6.3V6K~DCH5 1U_0402_6.3V6K~D
1 2
RH282
100K_0402_5%~D
@RH282
100K_0402_5%~D
@
12
RH17 33_0402_5%~DPXDP@ RH17 33_0402_5%~DPXDP@
1 2
G
D
S
QH7
SSM3K7002FU_SC70-3~D
G
D
S
QH7
SSM3K7002FU_SC70-3~D
2
13
RH360 0_0603_5%~DRH360 0_0603_5%~D
1 2
CH101
27P_0402_50V8J~D
@CH101
27P_0402_50V8J~D
@
1
2
RH24 1K_0402_1%~DPXDP@ RH24 1K_0402_1%~DPXDP@
1 2
RH26 33_0402_5%~DRH26 33_0402_5%~D
1 2
G
D
S
QH1 BSS138W-7-F_SOT323-3~D
G
D
S
QH1 BSS138W-7-F_SOT323-3~D
2
1 3
CH1
0.1U_0402_25V6K~D
PXDP@
CH1
0.1U_0402_25V6K~D
PXDP@
1
2
RTCIHDA
SATA
LPC
SPI
JTAG
SATA 6G
UH4A
BD82HM77 SLJ8C C1_BGA989~D
RTCIHDA
SATA
LPC
SPI
JTAG
SATA 6G
UH4A
BD82HM77 SLJ8C C1_BGA989~D
RTCX1
A20
RTCX2
C20
INTVRMEN
C17
INTRUDER#
K22
HDA_BCLK
N34
HDA_SYNC
L34
HDA_RST#
K34
HDA_SDIN0
E34
HDA_SDIN1
G34
HDA_SDIN2
C34
HDA_SDO
A36
SATALED#
P3
FWH0 / L AD0
C38
FWH1 / L AD1
A38
FWH2 / L AD2
B37
FWH3 / L AD3
C37
LDRQ1# / GPIO23
K36
FWH4 / L FRAME#
D36
LDRQ0#
E36
RTCRST#
D20
HDA_SDIN3
A34
HDA_DOCK_ EN# / GPIO3 3
C36
HDA_DOCK_ RST# / GPIO13
N32
SRTCRST#
G22
SATA0RXN
AM3
SATA0RXP
AM1
SATA0TXN
AP7
SATA0TXP
AP5
SATA1RXN
AM10
SATA1RXP
AM8
SATA1TXN
AP11
SATA1TXP
AP10
SATA2RXN
AD7
SATA2RXP
AD5
SATA2TXN
AH5
SATA2TXP
AH4
SATA3RXN
AB8
SATA3RXP
AB10
SATA3TXN
AF3
SATA3TXP
AF1
SATA4RXN
Y7
SATA4RXP
Y5
SATA4TXN
AD3
SATA4TXP
AD1
SATA5RXN
Y3
SATA5RXP
Y1
SATA5TXN
AB3
SATA5TXP
AB1
SATAICOMPI
Y10
SPI_CLK
T3
SPI_CS0#
Y14
SPI_CS1#
T1
SPI_MOSI
V4
SPI_MISO
U3
SATA0GP / GPIO21
V14
SATA1GP / GPIO19
P1
JTAG_TCK
J3
JTAG_TMS
H7
JTAG_TDI
K5
JTAG_TDO
H1
SERIRQ
V5
SPKR
T10
SATAICOMPO
Y11
SATA3COMPI
AB13
SATA3RCOMP O
AB12
SATA3RBIA S
AH1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SML1_SMBCLK
SML1_SMBDATA
PCH_SMB_ALERT#
MEM_SMBDATA
SML0CLK
SML0DATA
PCH_CL_RST1#
SML1_SMBCLK
PCH_CL_CLK1
SML1_SMBDATA
PCH_CL_DATA1
MEM_SMBCLK
MEM_SMBDATA
MEM_SMBCLK
PCIE_PRX_EXPTX_N3
PCIE_PTX_EXPRX_P3
PCIE_PTX_EXPRX_N3
PCIE_PRX_EXPTX_P3
PCIE_MINI3#
PCIE_MINI3
PCIE_PTX_WLANRX_ N2
PCIE_PRX_WLANTX_ P2
PCIE_PRX_WLANTX_ N2
PCIE_PTX_WLANRX_ P2
PCIE_PTX_WANRX_N 1
PCIE_PTX_WANRX_P 1
PCIE_PRX_WANTX_P 1
PCIE_PRX_WANTX_N 1
MINI3CLK_REQ#
MINI2CLK_REQ#
PCIE_MINI2
PCIE_MINI2#
PCIE_LAN
PCIE_LAN#
LANCLK_REQ#
PCIE_PTX_WPANRX _N5
PCIE_PRX_WPANTX _P5
PCIE_PRX_WPANTX _N5
PCIE_PTX_WPANRX _P5
PCIE_EXP
PCIE_EXP#
EXPCLK_REQ#
MEM_SMBCLK
MEM_SMBDATA
SML0CLK
SML0DATA
PCH_SMB_ALERT#
DDR_HVREF_RST_PCH
XCLK_RCOMP
CLK_CPU_DMI
CLK_CPU_DMI#
PCH_GPIO74
CLK_PCI_LOOPBACK
CLK_BUF_DOT96
CLK_BUF_DOT96#
CLK_BUF_CKSSCD
CLK_BUF_CKSSCD#
CLK_BUF_DMI#
CLK_BUF_BCLK
CLK_BUF_DMI
CLK_BUF_BCLK
CLK_PCH_14M
DDR_HVREF_RST_PCH
PCH_GPIO74
CLK_BUF_CKSSCD
CLK_BUF_DOT96#
CLK_BUF_DOT96
CLK_BUF_CKSSCD#
CLK_BUF_DMI#
CLK_PCH_14M
CLK_BUF_BCLK
CLK_BUF_DMI
PEG_B_CLKRQ#
MINI1CLK_REQ#
PCIE_MINI1#
PCIE_MINI1
PCIE_PRX_GLANTX_P7
PCIE_PRX_GLANTX_N7
PCIE_PTX_GLANRX_N7
PCIE_PTX_GLANRX_P7
PCIE_PRX_MMITX_P6
PCIE_PRX_MMITX_N6
PCIE_PTX_MMIRX_N6
PCIE_PTX_MMIRX_P6
CLK_BCLK_ITP
CLK_BCLK_ITP#
PCIECLKRQ7#
MMICLK_REQ#
PCIE_MMI#
PCIE_MMI
PEG_A_CLKRQ#
PEG_A_CLKRQ#
XTAL25_OUT
XTAL25_IN
CLK_48M
SIO_14M
JETWAY_14M
PCI_TPM_TCM
PCH_CL_CLK1
CLK_PCI_LOOPBACK
PCIECLKRQ6#
MEM_SMBCLK
MEM_SMBDATA
CLK_SMART_48M
SIO_14M
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_RUN
+3.3V_ALW_PCH
+1.05V_RUN
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
+3.3V_ALW_PCH
PCH_CL_DATA1 <34>
PCH_CL_CLK1 <34>
PCH_CL_RST1# <34>
SML1_SMBDATA <30,40>
DDR_XDP_WAN_ SMBDAT <7,12,13,14,27,34>
DDR_XDP_WAN_ SMBCLK <7,12,13,14,27,34>
PCIE_PRX_WLANTX_ P2<34>
PCIE_PRX_WLANTX_ N2<34>
PCIE_PRX_WANTX_P 1<34>
PCIE_PRX_WANTX_N 1<34>
PCIE_PTX_WLANRX_ N2<34>
PCIE_PTX_WLANRX_ P2<34>
PCIE_PTX_WANRX_P 1<34>
PCIE_PTX_WANRX_N 1<34>
CLK_PCIE_EXP#< 35>
CLK_PCIE_EXP<35>
PCIE_PRX_EXPTX_P3<35>
PCIE_PRX_EXPTX_N3<35>
EXPCLK_REQ#<35>
PCIE_PTX_EXPRX_P3<35>
PCIE_PTX_EXPRX_N3<35>
CLK_PCIE_MINI2<34>
PCIE_PRX_WPANTX _N5<34>
MINI2CLK_REQ#<34>
CLK_PCIE_MINI2#<34>
CLK_PCIE_MINI3#<34>
PCIE_PTX_WPANRX _P5<34>
PCIE_PTX_WPANRX _N5<34>
PCIE_PRX_WPANTX _P5<34>
MINI3CLK_REQ#<34>
CLK_PCIE_MINI3<34>
CLK_PCIE_LAN#<30>
LANCLK_REQ#<30>
CLK_PCIE_LAN<30>
CLK_CPU_DMI# <7>
CLK_CPU_DMI <7>
CLK_PCI_LOOPBACK <17>
CLK_PCIE_MINI1#<34>
CLK_PCIE_MINI1<34>
MINI1CLK_REQ#<34>
PCIE_PTX_GLANRX_N7<30>
PCIE_PRX_GLANTX_P7<30>
PCIE_PTX_GLANRX_P7<30>
PCIE_PRX_GLANTX_N7<30>
DDR_HVREF_RST_PCH <7>
PCIE_PTX_MMIRX_N6<33>
PCIE_PRX_MMITX_P6<33>
PCIE_PTX_MMIRX_P6<33>
PCIE_PRX_MMITX_N6<33>
CLK_CPU_ITP#<7>
CLK_CPU_ITP<7>
CLK_PCIE_MMI#<33>
CLK_PCIE_MMI<33>
SML1_SMBCLK <30,40>
MMICLK_REQ#<33>
CLK_SMART_48M <35>
CLK_SIO_14M <39>
CLK_PCI_TPM_TCM <32>
PCLK_80H < 34>
JETWAY_CLK14M <32>
SIO_LAN_SMBCLK<30,40>
SIO_LAN_SMBDATA<30,40>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (2/8)
15 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (2/8)
15 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (2/8)
15 61W ednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
EXPRESS Card--->
Express card--->
WLAN (Mini Card 2)--->
WWAN (Mini Card 1)--->
WLAN (Mini Card 2)--->
10/100/1G LAN --->
1/2 MINI CARD-3 PCIE
(Mini Card 3)--->
PP (Mini Card 3)--->
WWAN (Mini Card 1)--->
10/100/1G LAN --->
CLOCK TERMINATION for FCIM and need close to PCH
MMI --->
PCIE REQ power rail:
suspend: 0 3 4 5 6 7
core: 1 2
MMI--->
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
RF review in 0629
RF review in 0913
RF review in 1130
RH301 10K_0402_5%~DRH301 10K_0402_ 5%~D
12
QH5A
DMN66D0LDW-7_SOT363-6~D
QH5A
DMN66D0LDW-7_SOT363-6~D
6 1
2
QH8A
DMN66D0LDW-7_SOT363-6~D
QH8A
DMN66D0LDW-7_SOT363-6~D
6 1
2
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
UH4B
BD82HM77 SLJ8C C1_BGA989~D
PCI-E*
CLOCKS
FLEX CLOCKS
SMBUSController
Link
UH4B
BD82HM77 SLJ8C C1_BGA989~D
PERN1
BG34
PERP1
BJ34
PERN2
BE34
PERP2
BF34
PERN3
BG36
PERP3
BJ36
PERN4
BF36
PERP4
BE36
PERN5
BG37
PERP5
BH37
PERN6
BJ38
PERP6
BG38
PERN7
BG40
PERP7
BJ40
PERN8
BE38
PERP8
BC38
PETN1
AV32
PETP1
AU32
PETN2
BB32
PETP2
AY32
PETN3
AV34
PETP3
AU34
PETN4
AY34
PETP4
BB34
PETN5
AY36
PETP5
BB36
PETN6
AU36
PETP6
AV36
PETN7
AY40
PETP7
BB40
PETN8
AW38
PETP8
AY38
CLKOUT_PCIE0N
Y40
CLKOUT_PCIE0P
Y39
CLKOUT_PCIE1N
AB49
CLKOUT_PCIE1P
AB47
CLKOUT_PCIE2N
AA48
CLKOUT_PCIE2P
AA47
CLKOUT_PCIE3N
Y37
CLKOUT_PCIE3P
Y36
CLKOUT_PCIE4N
Y43
CLKOUT_PCIE4P
Y45
CLKOUT_PCIE5N
V45
CLKOUT_PCIE5P
V46
CLKIN_GND1_N
BJ30
CLKIN_GND1_P
BG30
CLKIN_DMI_N
BF18
CLKIN_DMI_P
BE18
CLKIN_DOT_96N
G24
CLKIN_DOT_96P
E24
CLKIN_SATA_N
AK7
CLKIN_SATA_P
AK5
XTAL25_IN
V47
XTAL25_OUT
V49
REFCLK14IN
K45
CLKIN_PCILOOPBACK
H45
CLKOUT_PEG_A_N
AB37
CLKOUT_PEG_A_P
AB38
PEG_A_CLKRQ# / GPIO47
M10
PCIECLKRQ0# / GPIO73
J2
PCIECLKRQ1# / GPIO18
M1
PCIECLKRQ2# / GPIO20
V10
PCIECLKRQ3# / GPIO25
A8
PCIECLKRQ4# / GPIO26
L12
PCIECLKRQ5# / GPIO44
L14
CLKOUTFLEX0 / GPIO64
K43
CLKOUTFLEX1 / GPIO65
F47
CLKOUTFLEX2 / GPIO66
H47
CLKOUTFLEX3 / GPIO67
K49
CLKOUT_DMI_N
AV22
CLKOUT_DMI_P
AU22
PEG_B_CLKRQ# / GPIO56
E6
CLKOUT_PEG_B_P
AB40
CLKOUT_PEG_B_N
AB42
XCLK_RCOMP
Y47
CLKOUT_DP_P
AM13
CLKOUT_DP_N
AM12
CLKOUT_PCIE6N
V40
CLKOUT_PCIE6P
V42
PCIECLKRQ7# / GPIO46
K12
CLKOUT_PCIE7N
V38
CLKOUT_PCIE7P
V37
CLKOUT_ITPXDP_N
AK14
CLKOUT_ITPXDP_P
AK13
SMBALERT# / GPIO11
E12
SMBCLK
H14
SMBDATA
C9
SML0ALERT# / GPIO60
A12
SML0CLK
C8
SML0DATA
G12
SML1ALERT# / PCHHOT# / GPIO74
C13
SML1CLK / GPIO58
E14
SML1DATA / GPIO75
M16
CL_CLK1
M7
CL_DATA1
T11
CL_RST1#
P10
PCIECLKRQ6# / GPIO45
T13
RH82 0_0402_5%~D@ RH82 0_0402_5%~D@
12
RH313 22_0402_5%~DRH313 22_0402_5%~D
12
RH74 10K_0402_5%~DRH74 10K_0402_5%~D
1 2
RH303 2.2K_0402_5%~DRH303 2.2K_0402_5%~D
12
RH81 10K_0402_5%~DRH81 10K_0402_5%~D
12
RH83 0_0402_5%~D@ RH83 0_0402_5%~D@
12
RH299 2.2K_0402_5%~DRH299 2.2K_0402_5%~D
1 2
CE16
10P_0402_50V8J~D
@
CE16
10P_0402_50V8J~D
@
1
2
RH80 10K_0402_5%~DRH80 10K_0402_5%~D
12
RH302 2.2K_0402_5%~DRH302 2.2K_0402_5%~D
12
RH100 90.9_0402_1%~DRH100 90.9_0402_1%~D
1 2
RH92 0_0402_5%~D@ RH92 0_0402_5%~D@
12
CE17
10P_0402_50V8J~D
@
CE17
10P_0402_50V8J~D
@
1
2
RH280 0_0402_5%~D@ RH280 0_0402_5%~D@
12
RH78 10K_0402_5%~DRH78 10K_0402_5%~D
1 2
RH99
1M_0402_5%~D
RH99
1M_0402_5%~D
12
RH93 0_0402_5%~D@ RH93 0_0402_5%~D@
12
RH75 10K_0402_5%~DRH75 10K_0402_5%~D
1 2
RH281 0_0402_5%~D@ RH281 0_0402_5%~D@
12
RH314 10_0402_1%~DRH314 10_0402_1%~D
12
RH152 10K_0402_5%~DRH 152 10 K_0402_5%~D
12
RH86 0_0402_5%~D@ RH86 0_0402_5%~D@
12
RH79 10K_0402_5%~DRH79 10K_0402_5%~D
1 2
RH97 10K_0402_5%~DRH97 10K_0402_5%~D
12
RH306 2.2K_0402_5%~DRH306 2.2K_0402_5%~D
12
RH304 10K_0402_5%~DRH304 10K_0402_ 5%~D
12
RH85 0_0402_5%~D@ RH85 0_0402_5%~D@
12
RH183 10K_0402_5%~DRH 183 10K_0402_5%~D
1 2
RH76 10K_0402_5%~DRH76 10K_0402_5%~D
1 2
CH18
10P_0402_50V8J~D
CH18
10P_0402_50V8J~D
1
2
RH95 0_0402_5%~D@ RH95 0_0402_5%~D@
12
RH300 1K_0402_1%~DRH300 1K_0402_1%~D
12
RH98 10K_0402_5%~DRH98 10K_0402_5%~D
1 2
RH96 0_0402_5%~D@ RH96 0_0402_5%~D@
12
RH87 10K_0402_5%~DRH87 10K_0402_5%~D
1 2
RH309 0_0402_5%~D@ RH309 0_0402_5%~D@
12
RH322 22_0402_5%~DRH322 22_0402_5%~D
12
QH5B
DMN66D0LDW-7_SOT363-6~D
QH5B
DMN66D0LDW-7_SOT363-6~D
3
5
4
RH315 22_0402_5%~D@ RH315 22_0402_5%~D@
12
RH104 10K_0402_5%~DRH 104 10 K_0402_5%~D
12
RH110 10K_0402_5%~DRH 110 10 K_0402_5%~D
12
RH307 0_0402 _5%~D@RH307 0_0402_5%~D@
12
RH91 10K_0402_5%~DRH91 10K_0402_5%~D
1 2
RH298 2.2K_0402_5%~DRH298 2.2K_0402_5%~D
1 2
RH305 2.2K_0402_5%~DRH305 2.2K_0402_5%~D
12
RH308 0_0402 _5%~D@RH308 0_0402_5%~D@
12
RH311 10_0402_1%~D5@ RH311 10_0402_1%~D5@
12
CH19
10P_0402_50V8J~D
CH19
10P_0402_50V8J~D
1
2
RH77 10K_0402_5%~DRH77 10K_0402_5%~D
1 2
RH94 10K_0402_5%~DRH94 10K_0402_5%~D
12
CE19
10P_0402_50V8J~D
CE19
10P_0402_50V8J~D
1
2
RH88 0_0402_5%~D@ RH88 0_0402_5%~D@
12
QH8B
DMN66D0LDW-7_SOT363-6~D
QH8B
DMN66D0LDW-7_SOT363-6~D
3
5
4
CE18
10P_0402_50V8J~D
@
CE18
10P_0402_50V8J~D
@
1
2
YH2
25MHZ_10PF_Q22FA2380049900~D
YH2
25MHZ_10PF_Q22FA2380049900~D
IN
1
GND
2
OUT
3
GND
4
RH90 0_0402_5%~D@ RH90 0_0402_5%~D@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_PCIE_WAKE#
CLKRUN#
SIO_SLP_LAN#
ME_SUS_PWR_ACK
PCH_RI#
CRT_IREF
PCH_CRT_DDC_DAT
PCH_CRT_DDC_CLK
HSYNC
VSYNC
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH
BIA_PWM_PCH
FDI_INT
FDI_FSYNC0
FDI_FSYNC1
FDI_LSYNC1
FDI_LSYNC0
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
PANEL_BKEN_PCH
SIO_PWRBTN#_R
PCH_BATLOW#
DMI_COMP_R
PCH_RI#
DMI_CRX_PTX_N1
DMI_CRX_PTX_P0
DMI_CRX_PTX_P3
DMI_CTX_PRX_P0
DMI_CRX_PTX_N2
DMI_CRX_PTX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_N2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_P2
DMI_CTX_PRX_N1
DMI_CRX_PTX_N0
DMI_CTX_PRX_N0
DMI_CTX_PRX_P1
DMI_CRX_PTX_N3
PCH_PWROK
AC_PRESENT
SUSACK#_R
RBIAS_CPY
SIO_SLP_S5#
SIO_SLP_S4#
SIO_SLP_S3#
SIO_SLP_A#
SUSCLK
PCH_DPWROK
PCH_PCIE_WAKE#
CLKRUN#
SIO_SLP_SUS#
SUS_STAT#/LPCPD#
SIO_SLP_LAN#
H_PM_SYNC
PCH_RSMRST#_R
ME_SUS_PWR_ACK_R
PCH_CRT_DDC_CLK
PCH_CRT_DDC_DAT
SUS_STAT#/LPCPD#
PM_DRAM_PWRGD_R
LCD_ACLK+_PCH
LCD_ACLK-_PCH
LCD_BCLK+_PCH
LCD_BCLK-_PCH
LCD_A2-_PCH
LCD_A0-_PCH
LCD_A1-_PCH
LCD_A0+_PCH
LCD_A2+_PCH
LCD_A1+_PCH
LCD_B2-_PCH
LCD_B0-_PCH
LCD_B1-_PCH
LCD_B0+_PCH
LCD_B2+_PCH
LCD_B1+_PCH
LVD_IBG
LDDC_CLK_PCH
LDDC_DATA_PCH
PCH_DPWROK PCH_RSMRST#_R
ME_SUS_PWR_ACK_R SUSACK#_R
DSWODVREN
PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA
PCH_SDVO_CTRLCLK
PCH_SDVO_CTRLDATA
PCH_CRT_BLU
PCH_CRT_GRN
PCH_CRT_RED
ENVDD_PCH
SYS_RESET#
ME_RESET#
ME_RESET#
SYS_RESET#
SYS_PWROK_R
PM_APWROK_R
PM_APWROK
PM_APWROK_R
SIO_SLP_A#
+3.3V_ALW_PCH
+3.3V_RUN
+1.05V_RUN
+3.3V_ALW_PCH
+RTC_CELL
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_ALW2
PCH_CRT_BLU<23>
PCH_CRT_GRN<23>
PCH_CRT_RED<23>
BIA_PWM_PCH<2 4>
ENVDD_PCH<24,39 >
FDI_INT <6>
FDI_FSYNC0 <6>
FDI_FSYNC1 <6>
FDI_LSYNC1 <6>
FDI_LSYNC0 <6>
FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_N7 <6>
FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P6 <6>
FDI_CTX_PRX_P7 <6>
PANEL_BKEN_PCH<24>
RESET_OUT#<40>
SIO_PWRBTN#<40>
DMI_CTX_PRX_P0< 6>
DMI_CTX_PRX_P3< 6>
DMI_CRX_PTX_N0<6>
DMI_CTX_PRX_P1< 6>
DMI_CTX_PRX_P2< 6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N1<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N0<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P0< 6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_N2<6>
DMI_CRX_PTX_P3< 6>
DMI_CRX_PTX_P2< 6>
DMI_CRX_PTX_P1< 6>
SIO_PWRBTN#_R<7,14>
AC_PRESENT<40>
SUSACK#<39> PCH_DPWROK < 39>
PCH_PCIE_WAKE# <40>
SIO_SLP_S4# <39,42,46>
SIO_SLP_S3# <11,27,35,39,42,47,48,4 9>
SIO_SLP_S5# <40,42>
H_PM_SYNC <7>
SIO_SLP_A# <39,42,48>
SIO_SLP_LAN# <30,39>
CLKRUN# <32,39,40>
SIO_SLP_SUS# <39>
PCH_RSMRST#_Q<1 4,41>
ME_SUS_PWR_ACK<40>
PCH_CRT_DDC_DAT <2 3>
SYS_PWROK<7 ,39>
PM_DRAM_PWRGD<7>
PCH_CRT_HSYNC<23>
PCH_CRT_VSYNC<23>
PCH_CRT_DDC_CLK <23>
LCD_ACLK-_PCH<24>
LCD_ACLK+_PCH<24>
LCD_BCLK-_PCH<24>
LCD_BCLK+_PCH<24>
LCD_A0-_PCH< 24>
LCD_A1-_PCH< 24>
LCD_A2-_PCH< 24>
LCD_A2+_PCH< 24>
LCD_A0+_PCH< 24>
LCD_A1+_PCH< 24>
LCD_B0-_PCH< 24>
LCD_B1-_PCH< 24>
LCD_B2-_PCH< 24>
LCD_B2+_PCH< 24>
LCD_B0+_PCH< 24>
LCD_B1+_PCH< 24>
LDDC_DATA_PCH<24>
LDDC_CLK_PCH<24>
DPC_PCH_LANE_N0 <3 8>
DPC_PCH_LANE_N1 <3 8>
DPC_PCH_LANE_N2 <3 8>
DPC_PCH_LANE_N3 <3 8>
DPC_PCH_LANE_P0 <38>
DPC_PCH_LANE_P1 <38>
DPC_PCH_LANE_P2 <38>
DPC_PCH_LANE_P3 <38>
DPC_PCH_DOCK_AUX <26 >
DPC_PCH_DOCK_HPD <38>
DPC_PCH_DOCK_AUX# <2 6>
PCH_DDPC_CTRLDATA <26>
PCH_DDPC_CTRLCLK <26>
DPD_PCH_LANE_P0 <38>
DPD_PCH_LANE_P1 <38>
DPD_PCH_LANE_P2 <38>
DPD_PCH_LANE_P3 <38>
PCH_DDPD_CTRLDATA <26>
PCH_DDPD_CTRLCLK <26>
DPD_PCH_DOCK_AUX <26 >
DPD_PCH_DOCK_HPD <38>
DPD_PCH_LANE_N0 <3 8>
DPD_PCH_LANE_N1 <3 8>
DPD_PCH_LANE_N2 <3 8>
DPD_PCH_LANE_N3 <3 8>
DPD_PCH_DOCK_AUX# <2 6>
TMDSB_PCH_CLK# <25>
TMDSB_PCH_N0 <25>
TMDSB_PCH_N1 <25>
TMDSB_PCH_N2 <25>
TMDSB_PCH_P1 <25>
TMDSB_PCH_P2 <25>
TMDSB_PCH_CLK <25>
TMDSB_PCH_P0 <25>
HDMIB_PCH_HPD <25>
PCH_SDVO_CTRLDATA <25>
PCH_SDVO_CTRLCLK <25 >
XDP_DBRESET#<7,14>
PM_APWROK<40>
Title
Size Document Number Rev
Date: Sh eet of
LA-7902P
1.0
PCH (3/8)
16 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sh eet of
LA-7902P
1.0
PCH (3/8)
16 61Wednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sh eet of
LA-7902P
1.0
PCH (3/8)
16 61Wednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
Intel request DDPB can not support eDP
DSWODVREN - On Die DSW VR Enable
HIGH: RH127 STUFFED,
RH129 UNSTUFFED
Enabled (DEFAULT)
Disabled
LOW: RH129 STUFFED,
RH127 UNSTUFFED
Minimum speacing of 20mils for LVD_IBG
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
Follow E4
T63 PAD~D @T63 PAD~D @
RH116 0_0402 _5%~D@ RH116 0_0402_5%~D@
1 2
LVDS
Digital Display Interface
CRT
UH4D
BD82HM77 SLJ8C C1_BGA989~ D
LVDS
Digital Display Interface
CRT
UH4D
BD82HM77 SLJ8C C1_BGA989~ D
L_BKLTCTL
P45
L_BKLTEN
J47
L_CTRL_CLK
T45
L_CTRL_DATA
P39
L_DDC_CLK
T40
L_DDC_DATA
K47
L_VDD_EN
M45
LVDSA_CLK#
AK39
LVDSA_CLK
AK40
LVDSA_DATA#0
AN48
LVDSA_DATA#1
AM47
LVDSA_DATA#2
AK47
LVDSA_DATA#3
AJ48
LVDSA_DATA0
AN47
LVDSA_DATA1
AM49
LVDSA_DATA2
AK49
LVDSA_DATA3
AJ47
LVDSB_CLK#
AF40
LVDSB_CLK
AF39
LVDSB_DATA#0
AH45
LVDSB_DATA#1
AH47
LVDSB_DATA#2
AF49
LVDSB_DATA#3
AF45
LVDSB_DATA0
AH43
DDPB_0N
AV42
DDPB_1N
AV45
LVD_VREFH
AE48
LVD_VREFL
AE47
DDPD_2N
BF42
DDPD_3N
BJ42
DDPB_2N
AU48
DDPB_3N
AV47
DDPC_0N
AY47
DDPC_1N
AY43
DDPC_2N
BA47
DDPC_3N
BB47
DDPD_0N
BB43
DDPD_1N
BF44
DDPB_0P
AV40
DDPB_1P
AV46
DDPD_2P
BE42
DDPD_3P
BG42
DDPB_2P
AU47
DDPB_3P
AV49
LVDSB_DATA1
AH49
LVDSB_DATA2
AF47
LVDSB_DATA3
AF43
LVD_IBG
AF37
LVD_VBG
AF36
DDPC_1P
AY45
DDPC_0P
AY49
DDPC_2P
BA48
DDPC_3P
BB49
DDPD_0P
BB45
DDPD_1P
BE44
CRT_BLUE
N48
CRT_DDC_CLK
T39
CRT_DDC_DATA
M40
CRT_GREEN
P49
CRT_HSYNC
M47
CRT_IRTN
T42
CRT_RED
T49
CRT_VSYNC
M49
DAC_IREF
T43
SDVO_CTRLCLK
P38
SDVO_CTRLDATA
M39
DDPC_CTRLCLK
P46
DDPC_CTRLDATA
P42
DDPD_CTRLCLK
M43
DDPD_CTRLDATA
M36
DDPB_AUXN
AT49
DDPC_AUXN
AP47
DDPD_AUXN
AT45
DDPB_AUXP
AT47
DDPC_AUXP
AP49
DDPD_AUXP
AT43
DDPB_HPD
AT40
DDPC_HPD
AT38
DDPD_HPD
BH41
SDVO_TVCLKINP
AP45
SDVO_TVCLKINN
AP43
SDVO_STALLP
AM40
SDVO_STALLN
AM42
SDVO_INTP
AP40
SDVO_INTN
AP39
RH112 750_0402_1%~DRH112 75 0_0402_1%~D
1 2
RH113 0_0402_5%~D@ RH113 0_0402_5%~D@
1 2
RH319 10K_0402_5%~D@ RH319 10K_0402_5%~D@
1 2
CH99
0.1U_0402_25V6K~D
@CH99
0.1U_0402_25V6K~D
@
1 2
RH323 0_0402_5%~D@ RH323 0_0402_5%~D@
1 2
RH344 2.3 7K_0402_1%~DRH344 2.3 7K_0402_1%~D
1 2
RH316
2.2K_0402_5%~D
RH316
2.2K_0402_5%~D
12
RH119 0_0402 _5%~D@RH119 0_0402 _5%~D@
1 2
CH108 0.1U_0402_25V6K~DCH1 08 0.1U_0402_25V6K~D
1 2
RH140 10K_0402_5%~DRH140 10K_0402_5%~D
1 2
RH123 20_0402_1%~DRH123 20 _0402_1%~D
1 2
RH118 0_0402_5%~D@ RH118 0_0402_5%~D@
1 2
T62 PAD~D @T62 PAD~D @
RH351 2.2K_0402_5%~DRH351 2.2K_0402_5%~D
12
RH318 10K_0402_5%~D@ RH318 10K_0402_5%~D@
1 2
RH320 0_0402_5%~D@ RH320 0_0402_5%~D@
1 2
T56 PAD~D @T56 PAD~D @
T59 PAD~D @T59 PAD~D @
RH357 0 _0402_5%~DRH357 0_0402_5%~D
1 2
T57 PAD~D @T57 PAD~D @
RH138 8 .2K_0402_5%~D@ RH138 8.2K_0402 _5%~D@
1 2
RH321 0_0402 _5%~D@RH321 0_0402 _5%~D@
1 2
RH120 0_0402_5%~D@ RH120 0_0402_5%~D@
1 2
RH144 10K_0402_5%~DRH144 10K_0402_5%~D
1 2
RH121 0_0402_5%~D@ RH121 0_0402_5%~D@
1 2
RH111 49.9_0402_1%~ DRH111 49.9_0402_1%~D
1 2
RH124 20_0402_1%~DRH124 20 _0402_1%~D
1 2
RH317
2.2K_0402_5%~D
RH317
2.2K_0402_5%~D
12
RH139 8.2K_0402_5%~DRH139 8.2K_0402_5%~D
1 2
RH352 2.2K_0402_5%~DRH352 2.2K_0402_5%~D
12
DMI
FDI
System Power Management
UH4C
BD82HM77 SLJ8C C1_BGA989~ D
DMI
FDI
System Power Management
UH4C
BD82HM77 SLJ8C C1_BGA989~ D
DMI0RXN
BC24
DMI1RXN
BE20
DMI2RXN
BG18
DMI3RXN
BG20
DMI0RXP
BE24
DMI1RXP
BC20
DMI2RXP
BJ18
DMI3RXP
BJ20
DMI0TXN
AW24
DMI1TXN
AW20
DMI2TXN
BB18
DMI3TXN
AV18
DMI0TXP
AY24
DMI1TXP
AY20
DMI2TXP
AY18
DMI3TXP
AU18
DMI_ZCOMP
BJ24
DMI_IRCOMP
BG25
FDI_RXN0
BJ14
FDI_RXN1
AY14
FDI_RXN2
BE14
FDI_RXN3
BH13
FDI_RXN4
BC12
FDI_RXN5
BJ12
FDI_RXN6
BG10
FDI_RXN7
BG9
FDI_RXP0
BG14
FDI_RXP1
BB14
FDI_RXP2
BF14
FDI_RXP3
BG13
FDI_RXP4
BE12
FDI_RXP5
BG12
FDI_RXP6
BJ10
FDI_RXP7
BH9
FDI_FSYNC0
AV12
FDI_FSYNC1
BC10
FDI_LSYNC0
AV14
FDI_LSYNC1
BB10
FDI_INT
AW16
PMSYNCH
AP14
SLP_SUS#
G16
SLP_S3#
F4
SLP_S4#
H4
SLP_S5# / GPIO63
D10
SYS_RESET#
K3
SYS_PWROK
P12
PWRBTN#
E20
RI#
A10
WAKE#
B9
SUS_STAT# / GPIO61
G8
SUSCLK / GPIO62
N14
ACPRESENT / GPIO31
H20
BATLOW# / GPIO72
E10
PWROK
L22
CLKRUN# / GPIO32
N3
SUSWARN#/SUSPWRDNACK/GPIO30
K16
RSMRST#
C21
DRAMPWROK
B13
SLP_LAN# / GPIO29
K14
APWROK
L10
DPWROK
E22
DMI2RBIAS
BH21
SLP_A#
G10
DSWVRMEN
A18
SUSACK#
C12
UH5
TC7SH08FU_SSOP5~D
UH5
TC7SH08FU_SSOP5~D
B
1
A
2
G
3
O
4
P
5
RH127 330K_0402_1%~DRH127 330K_0402_1%~D
1 2
RH129 330K_0402_1%~D@RH12 9 330K_0 402_1%~D@
1 2
RH132 150 _0402_1%~DRH132 150_0402_ 1%~D
1 2
RH142 10K_0402_5%~DRH142 10K_0402_5%~D
1 2
RH137 8 .2K_0402_5%~DRH137 8.2K_0402 _5%~D
1 2
RH131 150 _0402_1%~DRH131 150_0402_ 1%~D
1 2
RH122 0_0402_5%~D@ RH122 0_0402_5%~D@
1 2
UC3
74AHC1G09GW_TSSOP5~D
@UC3
74AHC1G09GW_TSSOP5~D
@
B
1
A
2
G
3
O
4
P
5
RH126
1K_0402_0.5%~D
RH126
1K_0402_0.5%~D
12
RH114 0_0402_5%~D@ RH114 0_0402_5%~D@
1 2
RH133 150 _0402_1%~DRH133 150_0402_ 1%~D
1 2
T58 PAD~D @T58 PAD~D @
RH134 100 K_0402_5%~DRH134 100 K_0402_5%~D
1 2
RH117 0_0402 _5%~D@ RH117 0_0402_5%~D@
1 2
RH141 8 .2K_0402_5%~D@ RH141 8.2K_0402 _5%~D@
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CAM_MIC_CBL_DET#
PCH_PLTRST#
PCH_PLTRST#_EC
USBP10+
USBP10-
USBP11+
USBP11-
USBP9+
USBP0-
USBP0+
USBP3+
USBP5+
USBP7+
USBP3-
USBP1-
USBP9-
USBP8-
USBP8+
USBP5-
USBP7-
USBP4-
USBP2+
USBP4+
USBP2-
USBP1+
USBRBIAS
USB_OC4#_R
USB_OC1#_R
USB_OC5#
PCI_GNT3#
BBS_BIT1
BT_DET#
USBP6+
USBP6-
USB_OC0#_R
USB_OC2#
USB_OC3#
USB_OC5#
USB_OC6#
USB_OC1#_R
USBP13+
USBP13-
PCI_REQ1#
PCH_PLTRST#
LCD_CBL_DET#
BT_DET#
PCI_GNT3#
FFS_PCH_INT
PCI_LOOPBACKOUT
PCI_MEC
PCI_5048
PCI_DOCK
BBS_BIT1
PCI_PIRQA#
PCI_PIRQC#
PCI_PIRQD#
PCI_PIRQB#
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
PCI_REQ1#
LCD_CBL_DET#
USBP12+
USBP12-
SIO_EXT_SMI#
SIO_EXT_SMI#
PCH_GPIO3
PCH_GPIO3
USB_OC4#_R
CAM_MIC_CBL_DET#
PCH_PLTRST#
USB_OC3#
USB_OC6#
USB_OC2#
USB_OC0#_R
PCIE_MCARD2_DET#
+3.3V_RUN
+3.3V_RUN
+3.3V_ALW_PCH
PCH_PLTRST#_EC <32,34,35,39,40>
USBP10+ <35>
USBP10- <35>
USBP11+ <41>
USBP11- <41>
USBP4+ <34>
USBP5- <34>
USBP3+ <38>
USBP5+ <34>
USBP4- <34>
USBP3- <38>
USBP2+ <36>
USBP2- <36>
USBP1+ <36>
USBP1- <36>
USBP0- <37>
USBP0+ <37>
USBP9+ <37>
USBP9- <37>
USB_OC0# <36,37>
USB_OC1# <36>
USB_OC0#_R <14>
USB_OC1#_R <14>
USB_OC2# <14>
USB_OC3# <14>
USB_OC4# <37>
USB_OC5# <14>
USB_OC6# <14>
LCD_CBL_DET#<24>
PCIE_MCARD2_DET#<34>
BT_DET#< 41>
HDD_FALL_INT<27>
CLK_PCI_MEC<40>
CLK_PCI_5048<39>
CLK_PCI_LOOPBACK<15>
CLK_PCI_DOCK<38>
PLTRST_LAN#<30>
PLTRST_MMI#<33>
PLTRST_XDP#<7>
USBP12- <24>
USBP12+ <24>
PCH_PLTRST#<7,14>
SIO_EXT_SMI# <14,40>
USB3RN2<36>
USB3RN4<38>
USB3RP4<3 8>
USB3TN4<38>
USB3TP4<38>
USB_OC4#_R <14>
CAM_MIC_CBL_DET#<24>
USB3RN3<36>
USB3RP3<3 6>
USB3RP2<3 6>
USB3TN3<36>
USB3TN2<36>
USB3TP3<36>
USB3TP2<36>
USBP13- <32>
USBP13+ <32>
USBP6- <34>
USBP6+ <34>
USBP7+ <38>
USBP7- <38>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (4/8)
17 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (4/8)
17 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (4/8)
17 61W ednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
A16 swap overri de Strap/Top-B lock
PCI_GNT#3
Swap Override jumper
Low = A16 swap
High = Default
Boot BIOS Strap
SATA_SLPD
(BBS_BIT0)
BBS_BIT1 Boot BIOS Location
0 0
Reserved (NAND)
PCI
SPI
LPC
0 1
1 0
1 1
*
----->Camera
----->Left side JESA1
----->MLK DOCK
----->Non used
----->Blue Tooth
----->Express Card
----->Flash
----->WLAN/WIMAX
----->Left Side
----->Back Right--JIO1
----->WWAN/UWB
----->DOCK
----->Right side--JAUD1
Route single-end 50-ohms and max 500-mils length.
Minimum spacing to other signals: 15 mils
----->BIO
Reserve fo r ESD in 6 /22
RSVD
PCI
USB
USB30
UH4E
BD82HM77 SLJ8C C1_BGA989~D
RSVD
PCI
USB
USB30
UH4E
BD82HM77 SLJ8C C1_BGA989~D
RSVD23
AV5
RSVD1
AY7
RSVD2
AV7
RSVD3
AU3
RSVD4
BG4
RSVD5
AT10
RSVD6
BC8
RSVD7
AU2
RSVD8
AT4
RSVD17
BB5
RSVD18
BB3
RSVD19
BB7
RSVD20
BE8
RSVD21
BD4
RSVD22
BF6
RSVD9
AT3
RSVD10
AT1
RSVD11
AY3
RSVD12
AT5
RSVD13
AV3
RSVD14
AV1
RSVD15
BB1
RSVD16
BA3
RSVD25
AT8
RSVD24
AV10
RSVD26
AY5
RSVD27
BA2
RSVD28
AT12
RSVD29
BF3
PIRQA#
K40
PIRQB#
K38
PIRQC#
H38
PIRQD#
G38
REQ1# / GPIO50
C46
REQ2# / GPIO52
C44
REQ3# / GPIO54
E40
GNT1# / GPIO51
D47
GNT2# / GPIO53
E42
GNT3# / GPIO55
F46
PIRQE# / GPIO2
G42
PIRQF# / GPIO3
G40
PIRQG# / GPIO4
C42
PIRQH# / GPIO5
D44
USBP0N
C24
USBP0P
A24
USBP1N
C25
USBP1P
B25
USBP2N
C26
USBP2P
A26
USBP3N
K28
USBP3P
H28
USBP4N
E28
USBP4P
D28
USBP5N
C28
USBP5P
A28
USBP6N
C29
USBP6P
B29
USBP7N
N28
USBP7P
M28
USBP8N
L30
USBP8P
K30
USBP9N
G30
USBP9P
E30
USBP10N
C30
USBP10P
A30
USBP11N
L32
USBP11P
K32
USBP12N
G32
USBP12P
E32
USBP13N
C32
USBP13P
A32
PME#
K10
CLKOUT_PCI0
H49
CLKOUT_PCI1
H43
CLKOUT_PCI2
J48
USBRBIAS#
C33
USBRBIAS
B33
OC0# / GPIO59
A14
OC1# / GPIO40
K20
OC2# / GPIO41
B17
OC3# / GPIO42
C16
OC4# / GPIO43
L16
OC5# / GPIO9
A16
OC6# / GPIO10
D14
OC7# / GPIO14
C14
CLKOUT_PCI4
H40
CLKOUT_PCI3
K42
PLTRST#
C6
TP1
BG26
TP2
BJ26
TP3
BH25
TP6
AH38
TP7
AH37
TP8
AK43
TP9
AK45
TP16
Y13
TP17
K24
TP18
L24
TP19
AB46
TP20
AB45
TP21
B21
TP22
M20
TP23
AY16
USB3Rn1
BE28
USB3Rn2
BC30
USB3Rn3
BE32
USB3Rn4
BJ32
USB3Rp1
BC28
USB3Rp2
BE30
USB3Rp3
BF32
USB3Rp4
BG32
USB3Tn1
AV26
USB3Tn2
BB26
USB3Tn3
AU28
USB3Tn4
AY30
USB3TP1
AU26
USB3Tp2
AY26
USB3Tp3
AV28
USB3Tp4
AW30
TP4
BJ16
TP5
BG16
TP15
AM5
TP14
AM4
TP13
AH12
TP12
H3
TP11
N30
TP10
C18
TP24
BG46
RH326 8.2K_0402_5%~DRH326 8.2K_0402_5%~D
1 2
T76PAD~D @T76PAD~D @
T71PAD~D @T71PAD~D @
RH160 22_0402_5%~DRH160 22_0402_5%~D
12
RH336 0_0402_5%~D@RH336 0_0402_5%~D@
1 2
RH334 0_0402_5%~D@ RH334 0_0402_5%~D@
1 2
UH3
TC7SH08FU_SSOP5~D
UH3
TC7SH08FU_SSOP5~D
B
1
A
2
G
3
O
4
P
5
T67PAD~D @T67PAD~D @
T73PAD~D @T73PAD~D @
T77PAD~D @T77PAD~D @
RH342
1K_0402_1%~D
@RH342
1K_0402_1%~D
@
12
T80PAD~D @T80PAD~D @
T66PAD~D @T66PAD~D @
RH102 22_0402_5%~DRH102 22_0402_5%~D
12
RH151
22.6_0402_1%~D
RH151
22.6_0402_1%~D
1 2
RPH1
10K_1206_8P4R_5%~D
RPH1
10K_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
RH103 22_0402_5%~DRH103 22_0402_5%~D
12
T104PAD~D @T104PAD~D @
CE10
0.1U_0402_25V6K~D
@
CE10
0.1U_0402_25V6K~D
@
1
2
T65PAD~D @T65PAD~D @
T81PAD~D @T81PAD~D @
RH339 0_0402_5%~D@RH339 0_0402_5%~D@
1 2
T70PAD~D @T70PAD~D @
T86PAD~D @T86PAD~D @
RH341 0_0402_5%~D@RH341 0_0402_5%~D@
1 2
RH331 10K_0402_5%~DRH331 10K_0402_5%~D
1 2
T68PAD~D @T68PAD~D @
RH361 10K_0402_5%~DRH361 10K_0402_5%~D
1 2
RH356 0_0402_5%~D@RH356 0_0402_5%~D@
1 2
RH329 8.2K_0402_5%~DRH329 8.2K_0402_5%~D
1 2
T82PAD~D @T82PAD~D @
T69PAD~D @T69PAD~D @
RH333
1K_0402_1%~D
@RH333
1K_0402_1%~D
@
12
T78PAD~D @T78PAD~D @
RPH2
10K_1206_8P4R_5%~D
RPH2
10K_1206_8P4R_5%~D
1 8
2 7
3 6
4 5
T84PAD~D @T84PAD~D @
T83PAD~D @T83PAD~D @
RH327 10K_0402_5%~DRH327 10K_0402_5%~D
1 2
RH105 22_0402_5%~DRH105 22_0402_5%~D
12
T79PAD~D @T79PAD~D @
T74PAD~D @T74PAD~D @
RH330 10K_0402_5%~DRH330 10K_0402_5%~D
1 2
T85PAD~D @T85PAD~D @
RH337 0_0402_5%~DRH337 0_0402_5%~D
1 2
T72PAD~D @T72PAD~D @
T87PAD~D @T87PAD~D @
RH328 10K_0402_5%~DRH328 10K_0402_5%~D
1 2
RH325 8.2K_0402_5%~DRH325 8.2K_0402_5%~D
1 2
T64PAD~D @T64PAD~D @
RH332 10K_0402_5%~DRH332 10K_0402_5%~D
1 2
T75PAD~D @T75PAD~D @
RH338 0_0402_5%~D@RH338 0_0402_5%~D@
1 2
CH102
0.1U_0402_25V6K~D
CH102
0.1U_0402_25V6K~D
1 2
RH324 8.2K_0402_5%~DRH324 8.2K_0402_5%~D
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SIO_A20GATE
SIO_RCIN#
PM_LANPHY_ENABLE
MEDIA_DET#
TPM_ID0
PCH_GPIO17
SIO_EXT_SCI#
TPM_ID0
PCH_GPIO37
PCH_GPIO36
PCH_GPIO37
TEMP_ALERT#
TPM_ID1
PCH_GPIO17
TEMP_ALERT#
TPM_ID1
USB_MCARD1_DET#
FFS_INT2
IO_LOOP#
IO_LOOP#
LED_B_DET#
VSS_NCTF_32
VSS_NCTF_17
VSS_NCTF_29
VSS_NCTF_26
VSS_NCTF_25
VSS_NCTF_23
VSS_NCTF_15
VSS_NCTF_20
VSS_NCTF_16
VSS_NCTF_18
VSS_NCTF_30
VSS_NCTF_19
VSS_NCTF_21
VSS_NCTF_31
VSS_NCTF_28
VSS_NCTF_24
VSS_NCTF_27
VSS_NCTF_22
H_CPUPWRGD
SIO_RCIN#
PCH_GPIO69
INIT3_3V#
SIO_A20GATE
VSS_NCTF_4
VSS_NCTF_11
VSS_NCTF_5
VSS_NCTF_14
VSS_NCTF_2
VSS_NCTF_8
VSS_NCTF_13
VSS_NCTF_7
VSS_NCTF_9
VSS_NCTF_3
VSS_NCTF_10
VSS_NCTF_12
VSS_NCTF_6
VSS_NCTF_1
PCH_GPIO69
PCH_THRMTRIP#_R
SIO_EXT_WAKE# PCH_GPIO1
CONTACTLESS_DET#
DF_TVS
NC_1
SIO_EXT_SCI#
KB_DET#
MEDIA_DET#
DF_TVSDF_TVS_R
CONTACTLESS_DET#
PCH_GPIO36
PCIE_MCARD3_DET#
KB_DET#
PCH_GPIO15
PCH_GPIO15
SLP_ME_CSW_DE V#
SLP_ME_CSW_DE V#
PCH_GPIO17
PCH_GPIO16
PCH_GPIO37
PCH_GPIO36
PCH_GPIO1
LED_B_DET#
PCH_GPIO16
PCH_GPIO16
PM_LANPHY_ENABLE
PCH_GPIO27
PCH_GPIO27
PCH_GPIO34
PCH_GPIO34
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+1.05V_RUN_VTT
+3.3V_ALW_PCH
+VCCDFTERM
+3.3V_ALW_PCH
+3.3V_ALW_PCH
SIO_EXT_SCI#<40>
PCIE_MCARD1_DET#<34>
TEMP_ALERT#<14,39>
USB_MCARD1_DET#<14,34>
PCH_GPIO37<14>
SIO_EXT_SCI#_R<14>
FFS_INT2<27>
SIO_A20GATE <40>
H_CPUPWRGD <7>
SIO_RCIN# <40>
PCH_GPIO16<14>
MEDIA_DET#<37 >
KB_DET#<41>
PCIE_MCARD3_DET# <34>
SIO_EXT_WAKE#<39>
USB_MCARD2_DET# <34>
PCH_GPIO36<14>
SLP_ME_CSW_DE V#<14,39>
PCH_GPIO15<14>
H_SNB_IVB#<7>
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (5/8)
18 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (5/8)
18 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (5/8)
18 61W ednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
Layout note:
Trace wide 10mil & length 30mil
All NCTF pins should have thick
traces at 45°from the pad.
DMI & FDI Termination Voltage
DF_TVS
Set to Vss when LOW
Set to Vcc when HIGH
PLACE RH150 CLO SE TO THE BRAN CHING POINT
( TO CPU and NV RAM CONNECTOR)
RH149 need to close to CPU
SLP_ME_CSW_DEV# PLL ON DIE VR ENABLE
ENABLED - HIGH DEFAULT
DISABLED - LOW
Note: PCH has internal pull up 20k ohm on
E3_PAID_TS_DET# (GPIO27)
TPM_ID1TPM_ID0
0
1
0
0
1 1
China TPM
TPM
No TPM, No China TPM
TBD
vPro only- --
Intel revi ew feedbac k in 0701
RH173 1K_0402_1%~D@RH173 1K_0402_1%~D@
12
RH259 0_0402_5%~D@ RH259 0_040 2_5%~D@
1 2
RH263 10K_0402_5%~DRH263 10K_0402_5%~D
1 2
RH273 1K_0402_1%~D@RH273 1K_0402 _1%~D@
12
RH181 10K_0402_5%~DRH181 10K_0402_5%~D
12
RH271
2.2K_0402_5%~D
4@ RH271
2.2K_0402_5%~D
4@
12
RH272 10K_0402_5%~DRH272 10K_0402_5%~D
1 2
T106PAD~D
@
T106PAD~D
@
RH171 10K_0402_5%~D@ RH171 10K_0402_5%~D@
12
CPU/MISC
NCTF
GPIO
UH4F
BD82HM77 SLJ8C C1_BGA989~D
CPU/MISC
NCTF
GPIO
UH4F
BD82HM77 SLJ8C C1_BGA989~D
GPIO27
E16
GPIO28
P8
GPIO24
E8
GPIO57
D6
LAN_PHY_PWR_CTRL / GPIO12
C4
VSS_NCTF_1
A4
VSS_NCTF_2
A44
VSS_NCTF_3
A45
VSS_NCTF_4
A46
VSS_NCTF_5
A5
VSS_NCTF_6
A6
VSS_NCTF_7
B3
VSS_NCTF_8
B47
VSS_NCTF_9
BD1
VSS_NCTF_10
BD49
VSS_NCTF_11
BE1
VSS_NCTF_12
BE49
TACH2 / GPIO6
H36
TACH0 / GPIO17
D40
TACH3 / GPIO7
E38
SATA3GP / GPIO37
M5
SATA5GP / GPIO49 / TEMP_ALERT#
V3
SCLOCK / GPIO22
T5
SLOAD / GPIO38
N2
SDATAOUT0 / GPIO39
M3
SDATAOUT1 / GPIO48
V13
PROCPWRGD
AY11
RCIN#
P5
PECI
AU16
THRMTRIP#
AY10
GPIO8
C10
BMBUSY# / GPIO0
T7
GPIO15
G2
TACH1 / GPIO1
A42
SATA2GP / GPIO36
V8
INIT3_3V#
T14
STP_PCI# / GPIO34
K1
GPIO35
K4
SATA4GP / GPIO16
U2
VSS_NCTF_32
F49
A20GATE
P4
TACH4 / GPIO68
C40
TACH6 / GPIO70
C41
TACH7 / GPIO71
A40
TACH5 / GPIO69
B41
VSS_NCTF_17
BH3
VSS_NCTF_18
BH47
VSS_NCTF_19
BJ4
VSS_NCTF_20
BJ44
VSS_NCTF_21
BJ45
VSS_NCTF_22
BJ46
VSS_NCTF_23
BJ5
VSS_NCTF_24
BJ6
VSS_NCTF_25
C2
VSS_NCTF_26
C48
VSS_NCTF_27
D1
VSS_NCTF_28
D49
VSS_NCTF_29
E1
VSS_NCTF_30
E49
VSS_NCTF_31
F1
TS_VSS4
AK10
TS_VSS3
AH10
TS_VSS2
AK11
TS_VSS1
AH8
NC_1
P37
VSS_NCTF_13
BF1
VSS_NCTF_14
BF49
VSS_NCTF_15
BG2
VSS_NCTF_16
BG48
DF_TVS
AY1
RH203 10K_0402_5%~DRH203 10K_0402_5%~D
12
T108PAD~D @T108PAD~D @
RH268
20K_0402_5%~D
3@ RH268
20K_0402_5%~D
3@
12
RH150 0_0402_5%~D@ RH150 0_0402_5%~D@
1 2
RH358 1K_0402_1%~DRH358 1K _0402_1%~D
1 2
RH164 100K_0402_5%~DRH164 100K_0402_5%~D
1 2
RH170 10K_0402_5%~DRH170 10K_0402_5%~D
12
RH178 10K_0402_5%~DRH178 10K_0402_5%~D
12
RH256 10K _0402_5%~DRH256 10K_0402_5%~D
12
RH267
10K_0402_5%~D
1@ RH267
10K_0402_5%~D
1@
1 2
RH354 1K_0402_1%~DRH354 1K_0402_1%~D
1 2
CH97
0.1U_0402_25V6K~D
CH97
0.1U_0402_25V6K~D
1
2
RH180 10K_0402_5%~DRH180 10K_0402_5%~D
12
RH149
2.2K_0402_5%~D
RH149
2.2K_0402_5%~D
12
RH182 10K_0402_5%~DRH182 10K_0402_5%~D
12
RH174 10K_0402_5%~DRH174 10K_0402_5%~D
12
RH266 10K_0402_5%~DRH266 10K_0402_5%~D
12
RH158 10K_0402_5%~DRH158 10K_0402_5%~D
12
RH270
10K_0402_5%~D
2@ RH270
10K_0402_5%~D
2@
1 2
RH53
4.7K_0402_5%~D
RH53
4.7K_0402_5%~D
1 2
RH262 56_0402_5%~DRH262 56_0402_5%~D
12
RH265 10K_0402_5%~D@ RH265 10K_0402_5%~D@
12
RH269 8.2K_0402_5%~DRH269 8.2K_0402_5%~D
1 2
RH179 10K_0402_5%~DRH179 10K_0402_5%~D
12
RH163 10K_0402_5%~DRH163 10K_0402_5%~D
1 2
RH172 10K_0402_5%~DRH172 10K_0402_5%~D
12
RH260 1.5K_0402 _1%~DRH260 1.5K_0402_1%~D
1 2
RH353
1K_0402_1%~D
@
RH353
1K_0402_1%~D
@
12
RH177 10K_0402_5%~DRH177 10K_0402_5%~D
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
+VCCAPLLEXP
+1.05V_RUN_VCCCLKDMI
+VCCADAC
+1.8V_RUN_LVDS
+VCCAPLL_FDI
+VCCAPLL_FDI
+VCCSPI
+1.5V_RUN +1.05V_+1.5V_1.8V_RUN
+1.8V_RUN
+3.3V_RUN
+VCCDFTERM
+1.05V_RUN
+1.05V_RUN
+1.05V_RUN
+1.05V_RUN
+1.05V_RUN
+3.3V_RUN
+1.05V_RUN
+3.3V_RUN
+3.3V_RUN
+1.8V_RUN
+3.3V_RUN
+1.05V_RUN_VTT
+1.05V_+1.5V_1.8V_RUN
+1.05V_+1.5V_1.8V_RUN
+1.05V_RUN_VTT
+1.05V_RUN
+3.3V_M
+3.3V_RUN
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (6/8)
19 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (6/8)
19 61W ednesday, March 07, 2012
Compal Electronics, Inc.
Title
Size Document Number Rev
Date: Sheet of
LA-7902P
1.0
PCH (6/8)
19 61W ednesday, March 07, 2012
Compal Electronics, Inc.
DELL CONFIDENTIAL/PROPRIETARY
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
0.1uH inductor, 200mA
CPN: SHI0110BJ0L
INTEL feedback 0302
INTEL feedback 0307
3.3
1.05
1.05
1.05
1.05
V_PROC_IO
V5REF
V5REF_Sus
Vcc3_3
VccASW
VccADAC3
VccADPLLA
VccADPLLB
VccSPI
Voltage Rail
VccCore
VccDMI
1.05
5
3.3
1.05
0.001
0.001
0.001
0.288
0.903
0.063
0.08
0.08
0.047
1.7
0.01
5
Voltage
S0 Iccmax
Current (A)
1.05
VccDSW3_3 0.001
3.3
3.3
VccDIFFCLKN 0.055
1.05VccIO 3.711
1.8 0.002VCCDFTERM
3.3VccRTC 6uA
1.05VccClkDMI 0.07
3.3VccSus 3_3
3.3VccSus HDA
0.126
0.01
VccVRM 1.8 / 1.5 0.167
1.05VccSSC
VccALVDS 3.3
1.8VccTX_ LVDS 0.04
0.001
0.095
PCH Power Rail Table
short
RH205 0_0603_5%~D@ RH205 0_0603_5%~D@
12
CH33
1U_0402_6.3V6K~D
CH33
1U_0402_6.3V6K~D
1
2
CH44
10U_0603_6.3V6M~D
CH44
10U_0603_6.3V6M~D
1
2
CH30
10U_0603_6.3V6M~D
CH30
10U_0603_6.3V6M~D
1
2
LH8
100NH_HK1608R10J-T_5%_0603~D
LH8
100NH_HK1608R10J-T_5%_0603~D
12
CH31
1U_0402_6.3V6K~D
CH31
1U_0402_6.3V6K~D
1
2
CH35
0.1U_0402_10V7K~D
CH35
0.1U_0402_10V7K~D
1
2
CH46
1U_0402_6.3V6K~D
CH46
1U_0402_6.3V6K~D
1
2
CH48
1U_0402_6.3V6K~D
CH48
1U_0402_6.3V6K~D
1
2
CH49
1U_0402_6.3V6K~D
CH49
1U_0402_6.3V6K~D
1 2
CH104
0.01U_0402_16V7K~D
CH104
0.01U_0402_16V7K~D
1
2
CH47
1U_0402_6.3V6K~D
CH47
1U_0402_6.3V6K~D
1
2
CH36
10U_0603_6.3V6M~D
CH36
10U_0603_6.3V6M~D
1
2
CH43
0.1U_0402_10V7K~D
CH43
0.1U_0402_10V7K~D
1
2
CH103
0.01U_0402_16V7K~D
CH103
0.01U_0402_16V7K~D
1
2
CH54
1U_0402_6.3V6K~D
CH54
1U_0402_6.3V6K~D
1
2
RH195 0.022_0805_1%@RH 195 0.022_0805_1%@
1 2
CH40
10U_0603_6.3V6M~D
@
CH40
10U_0603_6.3V6M~D
@
1
2
RH276 0_0805_5%~D@ RH276 0_0805_5%~D@
12
RH197 0_0603_5%~D@ RH197 0_060 3_5%~D@
12
LH1
1UH_GLFR1608T1R0M-LR_20%~D
LH1
1UH_GLFR1608T1R0M-LR_20%~D
12
CH52
0.1U_0402_10V7K~D
CH52
0.1U_0402_10V7K~D
1
2
CH34
0.01U_0402_16V7K~D
CH34
0.01U_0402_16V7K~D
1
2
CH106
10U_0603_6.3V6M~D
@
CH106
10U_0603_6.3V6M~D
@
1
2
RH204 0_0603_5%~D@ RH204 0_0603_5%~D@
12
CH45
1U_0402_6.3V6K~D
CH45
1U_0402_6.3V6K~D
1
2
CH51
0.1U_0402_10V7K~D
CH51
0.1U_0402_10V7K~D
1
2
POWER
VCC CORE
DMI
VCCIO
CRTLVDS
FDI
DFT / SPI HVCMOS
UH4G
BD82HM77 SLJ8C C1_BGA989~D
POWER
VCC CORE
DMI
VCCIO
CRTLVDS
FDI
DFT / SPI HVCMOS
UH4G
BD82HM77 SLJ8C C1_BGA989~D
VCCCORE[1]
AA23
VCCCORE[2]
AC23
VCCCORE[3]
AD21
VCCCORE[4]
AD23
VCCCORE[5]
AF21
VCCCORE[6]
AF23
VCCCORE[7]
AG21
VCCCORE[8]
AG23
VCCCORE[9]
AG24
VCCCORE[10]
AG26
VCCCORE[11]
AG27
VCCCORE[12]
AG29
VCCCORE[13]
AJ23
VCCCORE[14]
AJ26
VCCCORE[15]
AJ27
VCCDFTERM[4]
AJ17
VCCDFTERM[3]
AJ16
VCCIO[17]
AN21
VCCIO[18]
AN26
VCCIO[19]
AN27
VCCIO[20]
AP21
VCCIO[23]
AP26
VCCIO[24]
AT24
VCCIO[15]
AN16
VCCIO[16]
AN17
VCCIO[21]
AP23
VCCIO[22]
AP24
VCCADAC
U48
VCCTX_LVDS[1]
AM37
VCCTX_LVDS[2]
AM38
VCCALVDS
AK36
VCCVRM[3]
AT16
VCCVRM[2]
AP16
VCCAPLLEXP
BJ22
VccAFDIPLL
BG6
VCCIO[28]
AN19
VCCTX_LVDS[4]
AP37
VCCTX_LVDS[3]
AP36
VSSADAC
U47
VSSALVDS
AK37
VCCIO[27]
AP17
VCC3_3[6]
V33
VCC3_3[7]
V34
VCC3_3[3]
BH29
VCCDFTERM[2]
AG17
VCCDFTERM[1]
AG16
VCCDMI[1]
AT20
VCCIO[25]
AN33
VCCIO[26]
AN34
VCCCORE[16]
AJ29
VCCCORE[17]
AJ31
VCCSPI
V1
VCCCLKDMI
AB36
VCCDMI[2]
AU20
RH202 0_0603_5%~D@ RH202 0_060 3_5%~D@
12
CH50
1U_0402_6.3V6K~D
CH50
1U_0402_6.3V6K~D
1
2
CH32
1U_0402_6.3V6K~D
CH32
1U_0402_6.3V6K~D
1
2
PJP66
PAD-OPEN1x1m
@PJP66
PAD-OPEN1x1m
@
1 2
CH105
22U_0805_6.3V6M~D
CH105
22U_0805_6.3V6M~D
1
2
RH247
1UH_LB2012T1R0M_20%~D
@ RH247
1UH_LB2012T1R0M_20%~D
@
1 2
Loading...