LA-8124P QALEA
A
1 1
B
C
D
E
Compal Confidential
2 2
QALEA/QALEB Schematics Document
AMD APU Trinity FS1r2 + FCH Hudson-M3 + GPU Seymour XTX/Thames XT
2012-01-16
3 3
4 4
A
B
REV:0.4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Cover Page
Cover Page
Cover Page
LA-8124P
LA-8124P
LA-8124P
1 50Monday, January 16, 2 012
1 50Monday, January 16, 2 012
1 50Monday, January 16, 2 012
E
0.4
0.4
0.4
A
Compal confidential
File Name : QALEA/QALEB
Themes XT M2/Seymour XTX M2
B
C
D
E
1 1
VRAM
64M16/128M16/256M16
DDR3 x 8
Page 17
～～～～
24
LVDS
translator
RTD2132S
Page 25
HDMI Conn.
Page 27
4 * x1 PCI-E 2.0
LVDS Conn.
Page 26
GPP1GPP3
CardReader
2 2
4 in 1 Conn.
PCI Express
Mini card Slot 1
WLAN
Page 33
IC
RTS5229
USB(BT)
PCI-E(WLAN)
CRT CONN
Page 28
GPP0
LAN
RTL 8111F
FCH CRT (VGA DAC)
SPI ROM
4MB
3 3
Sub board
Power Board
LAN
Page 35
15" only
ODD board
G Sensor
ST LIS34ALTR
Audio Jack+
USB2.0
Gen2PCIE x 16
DP Port0
DP Port2
DP Port1
Page 13
Page 30
Track Point
AMD FS1r2 APU
Trinity
uPGA 722 pin
35mm x 35mm
x4 UMI Gen. 1
2.5GT/s per lane
Hudson M3
uFCBGA-656
24.5mm x 24.5mm
EC
ENE KB9012
Page 33
Click Pad
Page 33
Page 5
～～～～
Page 12
LPC BUS
Page 31
Memory BUS(DDRIII)
Dual Channel
1.5V DDRIII 1600 (1866)
9
AZALIA
14*USB2.0/
4*USB3.0,10*USB2.0
6*SATA serial
～～～～
16
Int.KBD
Page 33
SATA0
SATA1
204pin DDRIII-SO-DIMM X2
Page 10
～～～～
BANK 0, 1, 2
11
2Channel Speaker
Audio Codec
CX20671-21Z
Page 29
CMOS Camera
BlueTooth CONN
USB PORT 3.0 x3
Internal MIC
Audio Jacks
Combo jack
Page 26
Page 32
Page 34
USB PORT 2.0 x1 +Charger
WLAN
Page 33
Finger Printer
UPEK TCS5DA6C0
SATA3.0 HDD CONN
SATA ODD CONN
Page 30
Page 30
4 4
FingerPrint
Card reader
A
B
Thermal Sensor
Fintek 5303
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
Page 32
Compal Secret Data
Compal Secret Data
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
Block Diagrams
Block Diagrams
Block Diagrams
LA-8124P
LA-8124P
LA-8124P
2 50Monday, January 16, 2 012
2 50Monday, January 16, 2 012
2 50Monday, January 16, 2 012
E
0.4
0.4
0.4
A
Voltage Rails
Power Plane Description
VIN
B+
+APU_CORE
+APU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU
1 1
+1.5V ON
+0.75VS OFFON OFF0.75V switched power rail for DDR termi nator
+1.2VS ON OFF OFF
+2.5VS
+1.1VALW 1.1V switched power rail for FCH ON ON*ON
+1.1VS
+1.5VS OFF1.5V switched power rail ON OFF
+VGA_CORE OFFOFFON0.95-1.2V switched power rai l
+1.5VGS
+1.8VGS OFFON OFF1.8V switched power rail
+1.0VGS ON OFF OFF1.0V switched power rail for VGA
+3VALW
+3VS_WLAN ON OFF
+3VS
+5VALW
+5VS
2 2
+VSB ON ON*
+RTCVCC
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
EC SM Bus1 address
Device Address Address
Smart Battery
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for APU
1.5V power rail for APU VDDIO and DDR
1.2V (VDDR, VDDP) switched power rail for APU
2.5V for APU VDDA
1.5V switched power rail
3.3V always on power rail
3.3V power rail for WLAN
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
RTC power
EC SM Bus2 address
0001-011xb
HEX
15H
Device
F75303 (DDR,VRAM,CPUCORE)1001-101xb
SB-TSI
Seymour XTX
LVDS translator
B
S0 S3 S5
N/A N/A N/A
ON OFF
ON
ON OFF OFF1.1V switched power rail for FCH
ON OFF
ON
ON
ON
ON
ON
1001-100xb
1000-0010b
N/AN/AN/A
OFF
OFF
ON
OFF
OFF
OFF
ON ON*
OFF
OFF
OFF
ON
ON*
OFF
OFFON
ONON
HEX
9AH
98H
82H
FCH Hudson-M2/3
SATA Port List
SATA0
SATA1
SATA2
SATA3
SATA4
SATA5
HDD
ODD
NC
NC
NC
NC
BOM Structure
UMA@ : UMA only
DIS@ : DIS muxluss
PX40@ : PX4.0 Support
PX50@ : PX5.0 Support
CMOS@ : USB camera
C
Comal
PCIE Port List
LAN
WLAN
NC
Card Reader
NC
NC
NC
NC
APUFCH
PCIE0
PCIE1
PCIE2
PCIE3
PCIE0
PCIE1
PCIE2
PCIE3
D
FCH Hudson-M2/3
USB Port List
USB1.1
Port0
Port1
USB2.0
Port0
Port1
Port2
Port3
Port4
Port5
Port6
Port7
Port8
Port9
Port10
Port11
Port12
Port13
NC
NC
USB2.0 Port
NC
NC
NC
NC
WLAN
CMOS
FP
BT
NC
USB 3.0
USB 3.0
USB 3.0
NC
E
CONN@ : ME components
X76@, H2G@, S2G@ : VRAM
3 3
Tha@: Thames VGA
Sey@: Seymour VGA
BOM option and stencil
SDV:
FCH SMB0
Device Address
DDR DIMM1 (FCH_SMB0)
DDR DIMM2 (FCH_SMB0)
WLAN (FCH_SMB 0)
Security ROM
1001-000xb
1001-001xb
(FCH_SMB0)
HEX
90
92
CMOS@/DIS@/PX40@/SEY@ + X76@
PJ201,PJ401,PJ502,PJ503,PJ504,PJ601,PJ603,PJ604,
PJ701,PJ702,PJ703,PJ704,J1,J2301,J2401,J2402,J2403
PJ402,PJ403,PJ501,PJ602,PJ801,PJ802,PJ803,PJ804,PJ805
Stencil Memo
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
Notes List
Notes List
Notes List
LA-8124P
LA-8124P
LA-8124P
3 50Monday, January 16, 2 012
3 50Monday, January 16, 2 012
3 50Monday, January 16, 2 012
E
0.4
0.4
0.4
5
4
3
2
1
Without BACO option :
Power-Up/Down Sequence
All the ASIC supplies, except for VDDR3, must fully reach their respective
‧
nominal voltages within 20 ms of the start of the ramp-up sequence, though a
shorter ramp-up duration is preferred. There is no timing requirement on the
ramp up of VDDR3 relative to other power rails.
D D
The external pull-up resistors on the DDC/AUX signals (if applicable) should
‧
ramp up before or after both VDDC and VDD_CT have ramped up.
VDDC and VDD_CT should not ramp up simultaneously. For example, VDDC
‧
should reach 90% before VDD_CT starts to ramp up (or vice versa).
For power down, reversing the ramp-up sequence is recommended.
‧
VDDR3(3.3VGS)
PCIE_VDDC(1.0V)
C C
VDDR1(1.5VGS)
PE_GPIO0 : Low -> Reset dGPU ; High ->Normal operation
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON
BACO option :
PE_GPIO0 : High ->Normal operation (dGPU is not reset on BACO mode)
PE_GPIO1 : Low -> dGPU Power OFF ; High -> dGPU Power ON (always High)
dGPU Power Pins Max current
PCIE_PVDD, PCIE_VDDR, TSVDD, VDDR4, VDD_CT,
DPE_PVDD, DP[F:E]_VDD18, DP[D:A]_PVDD,
DP[D:A]_VDD18, AVDD, VDD1DI, A2VDDQ, VDD2DI,
DPLL_PVDD, MPV18, and SPV18
DP[F:E]_VDD10, DP[D:A]_VDD10, DPLL_VDDC, and
SPV10
PCIE_VDDC
VDDR3
BIF_VDDC (current consumption = 55mA@1.0V, in
BACO mode)
VDDR1
VDDC/VDDCI
Voltage
1.8V
1.0V
1.0V
3.3V
Same as
VDDC
1.5V
TBD
PX 3.0
OFF
OFF
OFF
OFF
OFF
OFF
OFF
BACO Mode
ON
ON
ON
ON
ON
Same as
PCIE_VDDC
OFF
OFF
1679mA
775mA
1.1A
60mA
70mA
1.2A
28
VDDC/VDDCI(1.12V)
VDD_CT(1.8V)
iGPU
PERSTb
REFCLK
B B
Straps Reset
Straps Valid
Global ASIC Reset
T4+16clock
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
PE_GPIO0(PXS_RST#) PE_EN
dGPU
BIF_VDDC
PE_GPIO1(PXS_PWREN )
+3.3VALW
+1.5V
+5VLAW
MOS
LDO
Regulator
2
+3.3VGS
1
+1.0VGS
2
+1.8VGS
5
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
BACO Switch
PX_mode
+1.5V
SI4800
+B
Regulator
dGPU Block Diagram
dGPU Block Diagram
dGPU Block Diagram
LA-8124P
LA-8124P
LA-8124P
3
4
1
+1.5VGS
+VGA_CORE
PWRGOOD
4 50Monday, January 16, 2012
4 50Monday, January 16, 2012
4 50Monday, January 16, 2012
0.4
0.4
0.4
A
B
C
D
E
PCIE_CRX_GTX_P[0..15]17
JCPU1A
JCPU1A
PCI EXPRESS
PCI EXPRESS
P_GFX_RXP0
P_GFX_RXN0
P_GFX_RXP1
P_GFX_RXN1
P_GFX_RXP2
P_GFX_RXN2
P_GFX_RXP3
P_GFX_RXN3
P_GFX_RXP4
P_GFX_RXN4
P_GFX_RXP5
P_GFX_RXN5
P_GFX_RXP6
P_GFX_RXN6
P_GFX_RXP7
P_GFX_RXN7
P_GFX_RXP8
P_GFX_RXN8
P_GFX_RXP9
P_GFX_RXN9
P_GFX_RXP10
P_GFX_RXN10
P_GFX_RXP11
P_GFX_RXN11
P_GFX_RXP12
P_GFX_RXN12
P_GFX_RXP13
P_GFX_RXN13
P_GFX_RXP14
P_GFX_RXN14
P_GFX_RXP15
P_GFX_RXN15
P_GPP_RXP0
P_GPP_RXN0
P_GPP_RXP1
P_GPP_RXN1
P_GPP_RXP2
P_GPP_RXN2
P_GPP_RXP3
P_GPP_RXN3
P_UMI_RXP0
P_UMI_RXN0
P_UMI_RXP1
P_UMI_RXN1
P_UMI_RXP2
P_UMI_RXN2
P_UMI_RXP3
P_UMI_RXN3
P_ZVDDP
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
GPP GRAPHICS
GPP GRAPHICS
UMI
UMI
P_GFX_TXP0
P_GFX_TXN0
P_GFX_TXP1
P_GFX_TXN1
P_GFX_TXP2
P_GFX_TXN2
P_GFX_TXP3
P_GFX_TXN3
P_GFX_TXP4
P_GFX_TXN4
P_GFX_TXP5
P_GFX_TXN5
P_GFX_TXP6
P_GFX_TXN6
P_GFX_TXP7
P_GFX_TXN7
P_GFX_TXP8
P_GFX_TXN8
P_GFX_TXP9
P_GFX_TXN9
P_GFX_TXP10
P_GFX_TXN10
P_GFX_TXP11
P_GFX_TXN11
P_GFX_TXP12
P_GFX_TXN12
P_GFX_TXP13
P_GFX_TXN13
P_GFX_TXP14
P_GFX_TXN14
P_GFX_TXP15
P_GFX_TXN15
P_GPP_TXP0
P_GPP_TXN0
P_GPP_TXP1
P_GPP_TXN1
P_GPP_TXP2
P_GPP_TXN2
P_GPP_TXP3
P_GPP_TXN3
P_UMI_TXP0
P_UMI_TXN0
P_UMI_TXP1
P_UMI_TXN1
P_UMI_TXP2
P_UMI_TXN2
P_UMI_TXP3
P_UMI_TXN3
P_ZVSS
AB2
PCIE_CTX_C_GRX_P0
AB1
PCIE_CTX_C_GRX_N0
AA3
PCIE_CTX_C_GRX_P1
AA2
PCIE_CTX_C_GRX_N1
Y5
PCIE_CTX_C_GRX_P2
Y4
PCIE_CTX_C_GRX_N2
Y2
PCIE_CTX_C_GRX_P3
Y1
PCIE_CTX_C_GRX_N3
W3
PCIE_CTX_C_GRX_P4
W2
PCIE_CTX_C_GRX_N4
V5
PCIE_CTX_C_GRX_P5
V4
PCIE_CTX_C_GRX_N5
V2
PCIE_CTX_C_GRX_P6
V1
PCIE_CTX_C_GRX_N6
U3
PCIE_CTX_C_GRX_P7
U2
PCIE_CTX_C_GRX_N7
T5
PCIE_CTX_C_GRX_P8
T4
PCIE_CTX_C_GRX_N8
T2
PCIE_CTX_C_GRX_P9
T1
PCIE_CTX_C_GRX_N9
R3
PCIE_CTX_C_GRX_P10
R2
PCIE_CTX_C_GRX_N10
P5
PCIE_CTX_C_GRX_P11
P4
PCIE_CTX_C_GRX_N11
P2
PCIE_CTX_C_GRX_P12
P1
PCIE_CTX_C_GRX_N12
N3
PCIE_CTX_C_GRX_P13
N2
PCIE_CTX_C_GRX_N13
M5
PCIE_CTX_C_GRX_P14
M4
PCIE_CTX_C_GRX_N14
M2
PCIE_CTX_C_GRX_P15
M1
PCIE_CTX_C_GRX_N15
AD5
PCIE_CTX_C_DRX_P0
AD4
PCIE_CTX_C_DRX_N0
AD2
PCIE_CTX_C_DRX_P1
AD1
PCIE_CTX_C_DRX_N1
AC3
AC2
AB5
PCIE_CTX_C_DRX_P3
AB4
PCIE_CTX_C_DRX_N3
AG2
UMI_TXP0_C
AG3
UMI_TXN0_C
AF4
UMI_TXP1_C
AF5
UMI_TXN1_C
AF1
UMI_TXP2_C
AF2
UMI_TXN2_C
AE2
UMI_TXP3_C
AE3
UMI_TXN3_C
AH11
P_ZVSS
1 2
R2 196_0402_1%R2 196_0402_1%
P_ZVDDP
AG11
AB8
AB7
AA9
AA8
AA5
AA6
Y8
Y7
W9
W8
W5
W6
V8
V7
U9
U8
U5
U6
T8
T7
R9
R8
R5
R6
P8
P7
N9
N8
N5
N6
M8
M7
AE5
AE6
AD8
AD7
AC9
AC8
AC5
AC6
AG8
AG9
AG6
AG5
AF7
AF8
AE8
AE9
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_N1
1 1
PCIE_CRX_DTX_P035
PCIE_CRX_DTX_N035
LAN
PCIE_CRX_DTX_P133
PCIE_CRX_DTX_N133
2 2
WLAN
Card Reader
PCIE_CRX_DTX_P335
PCIE_CRX_DTX_N335
UMI_RXP012
UMI_RXN012
UMI_RXP112
UMI_RXN112
UMI_RXP212
UMI_RXN212
UMI_RXP312
UMI_RXN312
+1.2VS
PCIE_CRX_GTX_P2
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_N15
1 2
R1 196_0402_1%R1 196_0402_1%
1 2
C1 .1U_0402_16V7KDIS@C1 .1U_0402_16V7KDIS@
1 2
C2 .1U_0402_16V7KDIS@C2 .1U_0402_16V7KDIS@
1 2
C3 .1U_0402_16V7KDIS@C3 .1U_0402_16V7KDIS@
1 2
C4 .1U_0402_16V7KDIS@C4 .1U_0402_16V7KDIS@
1 2
C5 .1U_0402_16V7KDIS@C5 .1U_0402_16V7KDIS@
1 2
C6 .1U_0402_16V7KDIS@C6 .1U_0402_16V7KDIS@
1 2
C7 .1U_0402_16V7KDIS@C7 .1U_0402_16V7KDIS@
1 2
C8 .1U_0402_16V7KDIS@C8 .1U_0402_16V7KDIS@
1 2
C9 .1U_0402_16V7KDIS@C9 .1U_0402_16V7KDIS@
1 2
C10 .1U_0402_16V7KDIS@C10 .1U_0402_16V7KDIS@
1 2
C11 .1U_0402_16V7KDIS@C11 .1U_0402_16V7KDIS@
1 2
C12 .1U_0402_16V7KDIS@C12 .1U_0402_16V7KDIS@
1 2
C13 .1U_0402_16V7KDIS@C13 .1U_0402_16V7KDIS@
1 2
C14 .1U_0402_16V7KDIS@C14 .1U_0402_16V7KDIS@
1 2
C15 .1U_0402_16V7KDIS@C15 .1U_0402_16V7KDIS@
1 2
C16 .1U_0402_16V7KDIS@C16 .1U_0402_16V7KDIS@
1 2
C17 .1U_0402_16V7KDIS@C17 .1U_0402_16V7KDIS@
1 2
C18 .1U_0402_16V7KDIS@C18 .1U_0402_16V7KDIS@
1 2
C19 .1U_0402_16V7KDIS@C19 .1U_0402_16V7KDIS@
1 2
C20 .1U_0402_16V7KDIS@C20 .1U_0402_16V7KDIS@
1 2
C21 .1U_0402_16V7KDIS@C21 .1U_0402_16V7KDIS@
1 2
C22 .1U_0402_16V7KDIS@C22 .1U_0402_16V7KDIS@
1 2
C23 .1U_0402_16V7KDIS@C23 .1U_0402_16V7KDIS@
1 2
C24 .1U_0402_16V7KDIS@C24 .1U_0402_16V7KDIS@
1 2
C25 .1U_0402_16V7KDIS@C25 .1U_0402_16V7KDIS@
1 2
C26 .1U_0402_16V7KDIS@C26 .1U_0402_16V7KDIS@
1 2
C27 .1U_0402_16V7KDIS@C27 .1U_0402_16V7KDIS@
1 2
C28 .1U_0402_16V7KDIS@C28 .1U_0402_16V7KDIS@
1 2
C29 .1U_0402_16V7KDIS@C29 .1U_0402_16V7KDIS@
1 2
C30 .1U_0402_16V7KDIS@C30 .1U_0402_16V7KDIS@
1 2
C31 .1U_0402_16V7KDIS@C31 .1U_0402_16V7KDIS@
1 2
C32 .1U_0402_16V7KDIS@C32 .1U_0402_16V7KDIS@
1 2
C33 . 1U_0402_16V7KC33 .1U_0402_16 V7K
1 2
C34 . 1U_0402_16V7KC34 .1U_0402_16 V7K
1 2
C123 .1U_0402_16V7KC123 .1U_0402_16V7K
1 2
C124 .1U_0402_16V7KC124 .1U_0402_16V7K
1 2
C35 . 1U_0402_16V7KC35 .1U_0402_16 V7K
1 2
C36 . 1U_0402_16V7KC36 .1U_0402_16 V7K
1 2
C37 . 1U_0402_16V7KC37 .1U_0402_16 V7K
1 2
C38 . 1U_0402_16V7KC38 .1U_0402_16 V7K
1 2
C39 . 1U_0402_16V7KC39 .1U_0402_16 V7K
1 2
C40 . 1U_0402_16V7KC40 .1U_0402_16 V7K
1 2
C41 . 1U_0402_16V7KC41 .1U_0402_16 V7K
1 2
C42 .1U_0402_16V7KC42 .1U_0402_16V7K
1 2
C43 . 1U_0402_16V7KC43 .1U_0402_16 V7K
1 2
C44 . 1U_0402_16V7KC44 .1U_0402_16 V7K
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_P12
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_P[0..15] 17
PCIE_CTX_GRX_N[0..15] 17PCIE_CRX_GTX_N[0..15]17
PCIE_CTX_DRX_P0 35
PCIE_CTX_DRX_N0 35
PCIE_CTX_DRX_P1 33
PCIE_CTX_DRX_N1 33
PCIE_CTX_DRX_P3 35
PCIE_CTX_DRX_N3 35
UMI_TXP0 12
UMI_TXN0 12
UMI_TXP1 12
UMI_TXN1 12
UMI_TXP2 12
UMI_TXN2 12
UMI_TXP3 12
UMI_TXN3 12
3 3
Power Sequence of APU
+1.5V
+2.5VS
+1.5VS
+APU_CORE
4 4
+APU_CORE_NB
+1.2VS
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
B
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
D
Date: Sheet of
Compal Electronics, Inc.
FS1r2 PCIE/UMI
FS1r2 PCIE/UMI
FS1r2 PCIE/UMI
LA-8121P
LA-8121P
LA-8121P
E
5 50Monday, January 16, 2 012
5 50Monday, January 16, 2 012
5 50Monday, January 16, 2 012
Group A
Group B
0.4
0.4
0.4
A
1 1
JCPU1B
JCPU1B
MEMORY CHANNEL A
DDRA_SMA[15..0]10
DDRA_SBS0#10
DDRA_SBS1#10
DDRA_SBS2#10
DDRA_SDM[7..0]10
2 2
DDRA_SDQS010
DDRA_SDQS0#10
DDRA_SDQS110
DDRA_SDQS1#10
DDRA_SDQS210
DDRA_SDQS2#10
DDRA_SDQS310
DDRA_SDQS3#10
DDRA_SDQS410
DDRA_SDQS4#10
DDRA_SDQS510
DDRA_SDQS5#10
DDRA_SDQS610
DDRA_SDQS6#10
DDRA_SDQS710
DDRA_SDQS7#10
DDRA_CLK010
DDRA_CLK0#10
DDRA_CLK110
DDRA_CLK1#10
DDRA_CKE010
DDRA_CKE110
DDRA_ODT010
DDRA_ODT110
3 3
DDRA_SCS0#10
DDRA_SCS1#10
DDRA_SRAS#10
DDRA_SCAS#10
DDRA_SWE#10
MEM_MA_RST#10
MEM_MA_EVENT#10
+MEM_VREF
+1.5V
15mil
Place them close to APU within 1"
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRA_SMA15
DDRA_SBS0#
DDRA_SBS1#
DDRA_SBS2#
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7
DDRA_SDQS7#
DDRA_CLK0
DDRA_CLK0#
DDRA_CLK1
DDRA_CLK1#
DDRA_CKE0
DDRA_CKE1
DDRA_ODT0
DDRA_ODT1
DDRA_SCS0#
DDRA_SCS1#
DDRA_SRAS#
DDRA_SCAS#
DDRA_SWE#
MEM_MA_RST#
MEM_MA_EVENT#
1 2
R3 39.2_0402_1%R3 39.2_0402_1%
M_ZVDDIO
AA25
AD27
AC23
AD19
AC15
AE26
AD26
AB22
AA22
AB18
AA18
AA14
AA15
AA27
AA26
W24
W23
W20
W21
U20
R20
R21
P22
P21
N24
N23
N20
N21
M21
U23
M22
L24
L21
L20
U24
U21
L23
E14
J17
E21
F25
G14
H14
G18
H18
J21
H21
E27
E26
T21
T22
R23
R24
H28
H27
Y25
V22
V21
H25
T24
MEMORY CHANNEL A
MA_ADD0
MA_ADD1
MA_ADD2
MA_ADD3
MA_ADD4
MA_ADD5
MA_ADD6
MA_ADD7
MA_ADD8
MA_ADD9
MA_ADD10
MA_ADD11
MA_ADD12
MA_ADD13
MA_ADD14
MA_ADD15
MA_BANK0
MA_BANK1
MA_BANK2
MA_DM0
MA_DM1
MA_DM2
MA_DM3
MA_DM4
MA_DM5
MA_DM6
MA_DM7
MA_DQS_H0
MA_DQS_L0
MA_DQS_H1
MA_DQS_L1
MA_DQS_H2
MA_DQS_L2
MA_DQS_H3
MA_DQS_L3
MA_DQS_H4
MA_DQS_L4
MA_DQS_H5
MA_DQS_L5
MA_DQS_H6
MA_DQS_L6
MA_DQS_H7
MA_DQS_L7
MA_CLK_H0
MA_CLK_L0
MA_CLK_H1
MA_CLK_L1
MA_CKE0
MA_CKE1
MA_ODT0
MA_ODT1
MA_CS_L0
MA_CS_L1
MA_RAS_L
MA_CAS_L
MA_WE_L
MA_RESET_L
MA_EVENT_L
M_VREF
M_ZVDDIO
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
B
MA_DATA0
MA_DATA1
MA_DATA2
MA_DATA3
MA_DATA4
MA_DATA5
MA_DATA6
MA_DATA7
MA_DATA8
MA_DATA9
MA_DATA10
MA_DATA11
MA_DATA12
MA_DATA13
MA_DATA14
MA_DATA15
MA_DATA16
MA_DATA17
MA_DATA18
MA_DATA19
MA_DATA20
MA_DATA21
MA_DATA22
MA_DATA23
MA_DATA24
MA_DATA25
MA_DATA26
MA_DATA27
MA_DATA28
MA_DATA29
MA_DATA30
MA_DATA31
MA_DATA32
MA_DATA33
MA_DATA34
MA_DATA35
MA_DATA36
MA_DATA37
MA_DATA38
MA_DATA39
MA_DATA40
MA_DATA41
MA_DATA42
MA_DATA43
MA_DATA44
MA_DATA45
MA_DATA46
MA_DATA47
MA_DATA48
MA_DATA49
MA_DATA50
MA_DATA51
MA_DATA52
MA_DATA53
MA_DATA54
MA_DATA55
MA_DATA56
MA_DATA57
MA_DATA58
MA_DATA59
MA_DATA60
MA_DATA61
MA_DATA62
MA_DATA63
E13
J13
H15
J15
H13
F13
F15
E15
H17
F17
E19
J19
G16
H16
H19
F19
H20
F21
J23
H23
G20
E20
G22
H22
G24
E25
G27
G26
F23
H24
E28
F27
AB28
AC27
AD25
AA24
AE28
AD28
AB26
AC25
Y23
AA23
Y21
AA20
AB24
AD24
AA21
AC21
AA19
AC19
AC17
AA17
AB20
Y19
AD18
AD17
AA16
Y15
AA13
AC13
Y17
AB16
AB14
Y13
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
DDRA_SDQ[63..0] 10
C
DDRB_SMA[15..0]11
DDRB_SBS0#11
DDRB_SBS1#11
DDRB_SBS2#11
DDRB_SDM[7..0]11
DDRB_SDQS011
DDRB_SDQS0#1 1
DDRB_SDQS111
DDRB_SDQS1#1 1
DDRB_SDQS211
DDRB_SDQS2#1 1
DDRB_SDQS311
DDRB_SDQS3#1 1
DDRB_SDQS411
DDRB_SDQS4#1 1
DDRB_SDQS511
DDRB_SDQS5#1 1
DDRB_SDQS611
DDRB_SDQS6#1 1
DDRB_SDQS711
DDRB_SDQS7#1 1
DDRB_CLK011
DDRB_CLK0#11
DDRB_CLK111
DDRB_CLK1#11
DDRB_CKE011
DDRB_CKE111
DDRB_ODT011
DDRB_ODT111
DDRB_SCS0#11
DDRB_SCS1#11
DDRB_SRAS#11
DDRB_SCAS#11
DDRB_SWE#11
MEM_MB_RST#11
MEM_MB_EVENT#11
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
DDRB_SMA15
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_CLK0
DDRB_CLK0#
DDRB_CLK1
DDRB_CLK1#
DDRB_CKE0
DDRB_CKE1
DDRB_ODT0
DDRB_ODT1
DDRB_SCS0#
DDRB_SCS1#
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
MEM_MB_RST#
MEM_MB_EVENT#
D
JCPU1C
JCPU1C
MEMORY CHANNEL B
MEMORY CHANNEL B
MB_ADD0
MB_ADD1
MB_ADD2
MB_ADD3
MB_ADD4
MB_ADD5
MB_ADD6
MB_ADD7
MB_ADD8
MB_ADD9
MB_ADD10
MB_ADD11
MB_ADD12
MB_ADD13
MB_ADD14
MB_ADD15
MB_BANK0
MB_BANK1
MB_BANK2
MB_DM0
MB_DM1
MB_DM2
MB_DM3
MB_DM4
MB_DM5
MB_DM6
MB_DM7
MB_DQS_H0
MB_DQS_L0
MB_DQS_H1
MB_DQS_L1
MB_DQS_H2
MB_DQS_L2
MB_DQS_H3
MB_DQS_L3
MB_DQS_H4
MB_DQS_L4
MB_DQS_H5
MB_DQS_L5
MB_DQS_H6
MB_DQS_L6
MB_DQS_H7
MB_DQS_L7
MB_CLK_H0
MB_CLK_L0
MB_CLK_H1
MB_CLK_L1
MB_CKE0
MB_CKE1
MB_ODT0
MB_ODT1
MB_CS_L0
MB_CS_L1
MB_RAS_L
MB_CAS_L
MB_WE_L
MB_RESET_L
MB_EVENT_L
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
W26
AF25
AG22
AH18
AD14
AG24
AG25
AG21
AF21
AG17
AG18
AH14
AG14
W27
T27
P24
P25
N27
N26
M28
M27
M24
M25
L26
U26
L27
K27
K25
K24
U27
T28
K28
D14
A18
A22
C25
C15
B15
E18
D18
E22
D22
B26
A26
R26
R27
P27
P28
J26
J27
Y28
V25
Y27
V24
V27
V28
J25
T25
MB_DATA0
MB_DATA1
MB_DATA2
MB_DATA3
MB_DATA4
MB_DATA5
MB_DATA6
MB_DATA7
MB_DATA8
MB_DATA9
MB_DATA10
MB_DATA11
MB_DATA12
MB_DATA13
MB_DATA14
MB_DATA15
MB_DATA16
MB_DATA17
MB_DATA18
MB_DATA19
MB_DATA20
MB_DATA21
MB_DATA22
MB_DATA23
MB_DATA24
MB_DATA25
MB_DATA26
MB_DATA27
MB_DATA28
MB_DATA29
MB_DATA30
MB_DATA31
MB_DATA32
MB_DATA33
MB_DATA34
MB_DATA35
MB_DATA36
MB_DATA37
MB_DATA38
MB_DATA39
MB_DATA40
MB_DATA41
MB_DATA42
MB_DATA43
MB_DATA44
MB_DATA45
MB_DATA46
MB_DATA47
MB_DATA48
MB_DATA49
MB_DATA50
MB_DATA51
MB_DATA52
MB_DATA53
MB_DATA54
MB_DATA55
MB_DATA56
MB_DATA57
MB_DATA58
MB_DATA59
MB_DATA60
MB_DATA61
MB_DATA62
MB_DATA63
A14
B14
D16
E16
B13
C13
B16
A16
C17
B18
B20
A20
E17
B17
B19
C19
C21
B22
C23
A24
D20
B21
E23
B23
E24
B25
B27
D28
B24
D24
D26
C27
AG26
AH26
AF23
AG23
AG27
AF27
AH24
AE24
AE22
AH22
AE20
AH20
AD23
AD22
AD21
AD20
AF19
AE18
AE16
AH16
AG20
AG19
AF17
AD16
AG15
AD15
AG13
AD13
AG16
AF15
AE14
AF13
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
E
DDRB_SDQ[63..0] 1 1
EVENT# pull high 0.75V reference voltage
+1.5V
4 4
1 2
R5 1K_0402_5%R5 1K_0402_5%
1 2
R6 1K_0402_5%R6 1K_0402_5%
MEM_MA_EVENT#
MEM_MB_EVENT# +MEM_VREF
A
R4
R4
1K_0402_1%
1K_0402_1%
R7
R7
1K_0402_1%
1K_0402_1%
+1.5V
1 2
1
C45
C45
1000P_0402_50V7K
1000P_0402_50V7K
2
1 2
B
15mil
2
C46
C46
.1U_0402_16V7K
.1U_0402_16V7K
1
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FS1r2 DDRIII Memory I/F
FS1r2 DDRIII Memory I/F
FS1r2 DDRIII Memory I/F
LA-8121P
LA-8121P
LA-8121P
6 50Monday, January 16, 2 012
6 50Monday, January 16, 2 012
6 50Monday, January 16, 2 012
E
0.4
0.4
0.4
A
Place near APU
1 2
DP0_TXP0_C25
DP0_TXN0_C25
1 1
2 2
+1.5V
3 3
4 4
1 2
R49 1K_0402_5%R49 1K_0402_5%
1 2
R52 1K_0402_5%R52 1K_0402_5%
1 2
R32 1K_0402_5%R32 1K_0402_5%
1 2
R37 1K_0402_5%R37 1K_0402_5%
1 2
R39 1K_0402_5%R39 1K_0402_5%
R36 1K_0402_5%R36 1K_0402_5%
1 2
R33 1K_0402_5%@R33 1K_0402_5%@
1 2
R38 1K_0402_5%@R38 1K_0402_5%@
1 2
R40 1K_0402_5%@R40 1K_0402_5%@
1 2
R41 1K_0402_5%R41 1K_0402_5%
1 2
R43 1K_0402_5%R43 1K_0402_5%
1 2
R46 1K_0402_5%R46 1K_0402_5%
+1.5VS
1 2
R54 300_0402_5%R54 300_0402_5%
1 2
R57 300_0402_5%R57 300_0402_5%
+3VS
1 2
R60 10K_0402_5%R60 10K_0402_5%
1 2
R61 10K_0402_5%R61 10K_0402_5%
Aux signal are re-configured as I2C signals for DDC. APU AUX pin are 3.3V tolerant
Default follow PAWGX setting for pull-high resistor value
ML_VGA_TXP013
ML_VGA_TXN01 3
ML_VGA_TXP113
ML_VGA_TXN11 3
ML_VGA_TXP213
ML_VGA_TXN21 3
ML_VGA_TXP313
ML_VGA_TXN31 3
HDMI_TX2P27
HDMI_TX2N27
HDMI_TX1P27
HDMI_TX1N27
HDMI_TX0P27
HDMI_TX0N27
HDMI_CLKP27
HDMI_CLKN27
Route as differential
with VSS_SENSE
ALLOW_STOP
APU_DBREQ#
12
APU_TRST#
APU_RST#
APU_PWRGD
A
APU_TCK
APU_TMS
APU_TDI
APU_SVT
APU_SVC
APU_SVD
APU_SIC
APU_SID
ALERT_L
HDMI_CLK
HDMI_DATA
C52 .1U_0402_16V7KC52 .1U_0402_16V7K
1 2
C47 .1U_0402_16V7KC47 .1U_0402_16V7K
1 2
C61 .1U_0402_16V7KC61 .1U_0402_16V7K
1 2
C62 .1U_0402_16V7KC62 .1U_0402_16V7K
1 2
C63 .1U_0402_16V7KC63 .1U_0402_16V7K
1 2
C64 .1U_0402_16V7KC64 .1U_0402_16V7K
1 2
C65 .1U_0402_16V7KC65 .1U_0402_16V7K
1 2
C66 .1U_0402_16V7KC66 .1U_0402_16V7K
1 2
C67 .1U_0402_16V7KC67 .1U_0402_16V7K
1 2
C68 .1U_0402_16V7KC68 .1U_0402_16V7K
1 2
C50 .1U_0402_16V7KC50 .1U_0402_16V7K
1 2
C51 .1U_0402_16V7KC51 .1U_0402_16V7K
1 2
C55 .1U_0402_16V7KC55 .1U_0402_16V7K
1 2
C56 .1U_0402_16V7KC56 .1U_0402_16V7K
1 2
C57 .1U_0402_16V7KC57 .1U_0402_16V7K
1 2
C58 .1U_0402_16V7KC58 .1U_0402_16V7K
1 2
C59 .1U_0402_16V7KC59 .1U_0402_16V7K
1 2
C60 .1U_0402_16V7KC60 .1U_0402_16V7K
APU_CLK12
APU_CLK#12
APU_DISP_CLK12
APU_DISP_CLK#12
APU_SVC45
APU_SVD45
APU_SVT45
T32T32
APU_RST#1 2
APU_PWRGD12,45
APU_PROCHOT#1 2
APU_VDD_SEN_L4 5
APU_VDDNB_SEN45
APU_VDD_SEN_H45
T33T33
T23T23
T24T24
T25T25
T26T26
T27T27
T28T28
T29T29
APU_RST#
APU_PWRGD
APU_PROCHOT#
APU_THERMTRIP#
ALERT_L
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
APU_VDD_SEN_L
APU_VDDNB_SEN
APU_VDD_SEN_H
FVT, NO.37
APU_CLK
APU_CLK#
APU_DISP_CLK
APU_DISP_CLK#
APU_SIC
APU_SID
T20T20
T21T21
DP0_TXP0
DP0_TXN0
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
DP2_TXP0
DP2_TXN0
DP2_TXP1
DP2_TXN1
DP2_TXP2
DP2_TXN2
DP2_TXP3
DP2_TXN3
B
ANALOG/DISPLAY/MISC
ANALOG/DISPLAY/MISC
DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_TXP2
DP0_TXN2
DP0_TXP3
DP0_TXN3
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
To FCH
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
DP2_TXP0
DP2_TXN0
DP2_TXP1
HDMI
DP2_TXN1
DP2_TXP2
DP2_TXN2
DP2_TXP3
DP2_TXN3
CLKIN_H
CLKIN_L
DISP_CLKIN_H
DISP_CLKIN_L
SVC
SVD
SVT
SIC
SID
RESET_L
PWROK
PROCHOT_L
THERMTRIP_L
ALERT_L
TDI
TDO
TCK
TMS
TRST_L
DBRDY
DBREQ_L
VSS_SENSE
VDDP_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDD_SENSE
VDDR_SENSE
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
+3VS
AE11
AD11
AB11
AA11
AG12
AH12
AF10
AB12
AC10
AE12
AF12
L3
L2
K5
K4
K2
K1
J3
J2
H5
H4
H2
H1
G3
G2
F2
F1
L9
L8
L5
L6
K8
K7
J6
J5
B3
A3
C3
H10
J10
F10
G10
F9
G9
H9
B4
C5
A4
A5
C4
B5
SIT, NO.3
APU_SIC
B
LVDS
JCPU1D
JCPU1D
DISPLAY PORT 0
DISPLAY PORT 0
DISPLAY PORT MISC.
DISPLAY PORT MISC.
DISPLAY PORT 2 DISPLAY PORT 1
DISPLAY PORT 2 DISPLAY PORT 1
TEST
TEST
CTRL SER. CLK
CTRL SER. CLK
JTAG
JTAG
SENSE
SENSE
1 2
R34
R34
31.6K_0402_1%
31.6K_0402_1%
D1
DP0_AUXP
D2
DP0_AUXN
E1
DP1_AUXP
E2
DP1_AUXN
D5
DP2_AUXP
D6
DP2_AUXN
E5
DP3_AUXP
E6
DP3_AUXN
F5
DP4_AUXP
F6
DP4_AUXN
G5
DP5_AUXP
G6
DP5_AUXN
D3
DP0_HPD
E3
DP1_HPD
D7
DP2_HPD
E7
DP3_HPD
F7
DP4_HPD
G7
DP5_HPD
C6
DP_BLON
B6
DP_DIGON
DP_VARY_BL
DP_AUX_ZVSS
DMAACTIVE_L
RSVD
RSVD
A6
C1
AD12
TEST6
M18
TEST9
N18
TEST10
F11
TEST14
G11
TEST15
H11
TEST16
J11
TEST17
F12
TEST18
G12
TEST19
J12
TEST20
H12
TEST24
AE10
TEST25_H
AD10
TEST25_L
L10
TEST28_H
M10
TEST28_L
P19
TEST30_H
R19
TEST30_L
K22
TEST31
T19
TEST32_H
N19
TEST32_L
AA12
TEST35
W10
FS1R2
AC12
P18
TEST4
R18
TEST5
Y10
RSVD1
AA10
RSVD2
Y12
RSVD3
K21
RSVD4
@
@
1 2
C69 0.1U_0402_16V4Z
C69 0.1U_0402_16V4Z
1 2
R35
R35
30K_0402_1%
30K_0402_1%
2
3 1
SGD
SGD
BSH111_SOT23-3
BSH111_SOT23-3
2
3 1
SGD
SGD
BSH111_SOT23-3
BSH111_SOT23-3
DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN
HDMI_CLK
HDMI_DATA
LVDS_HPD
ML_VGA_HPD
HDMI_DET
DP_INT_PWM
DP_AUX_ZVSS
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST24
TEST25_H
TEST25_L
TEST28_H
TEST28_L
TEST30_H
TEST30_L
APU_TEST31
APU_TEST35
FS1R2
ALLOW_STOP
C
1 2
C53 . 1U_0402_16V7KC53 .1U_0402_16 V7K
1 2
C48 . 1U_0402_16V7KC48 .1U_0402_16 V7K
1 2
C54 . 1U_0402_16V7KC54 .1U_0402_16 V7K
1 2
C49 . 1U_0402_16V7KC49 .1U_0402_16 V7K
SIT, NO.4
LVDS_HPD 25
ML_VGA_HPD 13
HDMI_DET 27
DP_INT_PWM 9
1 2
R13 150_0402_1%R13 150_0402_1%
T1T1
T2T2
T3T3
T4T4
T5T5
T6T6
T14T14
T15T15
T7T7
T8T8
T9T9
T10T10
T30T30
T31T31
1 2
R14 1K_0402_5%R14 1K_0402_5%
1 2
R15 1K_0402_5%R15 1K_0402_5%
1 2
R16 1K_0402_5%R16 1K_0402_5%
1 2
R17 1K_0402_5%R17 1K_0402_5%
1 2
R20 510_0402_1%R20 510_0402_1%
1 2
R23 510_0402_1%R23 510_0402_1%
1 2
R25 39.2_0402_1%R25 39.2_0402_1%
1 2
R26 300_0402_5%R26 300_0402_5%
1 2
R27 300_0402_5%@R27 300_0402_5%@
1 2
R28 10K_0402_5%R28 10K_0402_5%
ALLOW_STOP 12
DP0_AUXP_C 25
DP0_AUXN_C 25
ML_VGA_AUXP_C 13
ML_VGA_AUXN_C 13
HDMI_CLK 27
HDMI_DATA 27
+1.2VS
+1.5V
+3VALW
To LVDS
Translater
To FCH
MainLink
To HDMI
Asserted as an input to force the
processor into the HTC-active state
D
SDV2, NO.45
R12
R12
1K_0402_5%
1K_0402_5%
APU_PROCHOT#
THERMTRIP shutdown
Temperature: 125 degree
ALERT_L
To FCH
+1.5V
1 2
R78 0_0402_5%@R78 0_0402_5%@
APU_THERMTRIP#
3 1
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
CPU TSI interface level shift
BSH111, the Vgs is:
min = 0.4V
Max = 1.3V
Q4
Q4
EC_SMB_DAAPU_SID
1 2
R50
@ R50
@
0_0402_5%
0_0402_5%
Q5
Q5
EC_SMB_CK
1 2
R59
@ R59
@
0_0402_5%
0_0402_5%
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
@ R47
@
@ R58
@
R44
R44
R47
R55
R55
R58
1 2
0_0402_5%
0_0402_5%
1 2
0_0402_5%
0_0402_5%
1 2
0_0402_5%
0_0402_5%
1 2
0_0402_5%
0_0402_5%
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
EC_SMB_DA2 18,25,31,32,33
FCH_SID 14
EC_SMB_CK2 18,25,31,32,33
FCH_SIC 14
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
To EC
To FCH
To EC
To FCH
D
E
If not used, pins are left unconnected (DG ref.)
20101111
ML_VGA_AUXP
R9 1.8K_0402_5%R9 1.8K_0402_5%
ML_VGA_AUXN
R8 1.8K_0402_5%R8 1.8K_0402_5%
DP0_AUXP
R79 1.8K_0402_5%R79 1.8K_0402_5%
DP0_AUXN
R81 1.8K_0402_5%R81 1.8K_0402_5%
H_PROCHOT#_EC: default low/a ctive high
APU_PROCHOT# : default high/ active low
H_PROCHOT#: default high/ ac tive low
Q7
Q7
13
2N7002K_SOT23-3
2N7002K_SOT23-3
D
D
2
G
G
S
S
1 2
+1.5V
R21
R21
1K_0402_5%
1K_0402_5%
1 2
E
E
3 1
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
+1.5V
12
R29
R29
10K_0402_5%@
10K_0402_5%@
B
B
2
Q3
@
Q3
@
E
E
C
C
R30 0_0402_5%@R30 0_0402_5%@
R31 0_0402_5%@R31 0_0402_5%@
Title
Title
Title
FS1r2 Display/MISC/HDT
FS1r2 Display/MISC/HDT
FS1r2 Display/MISC/HDT
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
SIT, NO.16
Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the
FCH to transition the system to S5 immediately
12
R18
R18
10K_0402_5%
10K_0402_5%
B
B
2
Q2
Q2
C
C
1 2
1 2
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
LA-8121P
LA-8121P
LA-8121P
12
12
12
12
H_THERMTRIP# 14
E
H_PROCHOT#_EC 31,38
H_PROCHOT# 38,45
APU_ALERT#_FCH 13
APU_ALERT#_EC 3 1
0.4
0.4
7 50Monday, January 16, 2 012
7 50Monday, January 16, 2 012
7 50Monday, January 16, 2 012
0.4
A
Power Name
VDD
+APU_CORE
VDDNB
+APU_CORE_NB
VDDIO
+1.5V
VDDP / VDDR
+1.2VS
VDDA
1 1
+2.5VS 0.5A
2 2
3 3
Consumption
5A / 3.5A
VDDR decoupling
180P_0402_50V8J
180P_0402_50V8J
C104
C104
C103
C103
1
1
2
2
60A
44A
3.2A
180P_0402_50V8J
180P_0402_50V8J
+APU_CORE
F8
VDD_1
H6
VDD_2
J1
VDD_3
J14
VDD_4
P6
VDD_5
P10
VDD_6
J16
VDD_7
J18
VDD_8
J9
VDD_9
K19
VDD_10
K3
VDD_11
K17
VDD_12
M3
VDD_13
K6
VDD_14
V10
VDD_15
V18
VDD_16
V3
VDD_17
F3
VDD_18
L18
VDD_19
V6
VDD_20
W1
VDD_21
T18
VDD_22
Y14
VDD_23
AA1
VDD_24
AB6
VDD_25
AC1
VDD_26
R1
VDD_27
P3
VDD_28
K10
VDD_29
H3
VDD_30
M19
VDD_31
+APU_CORE_NB
+1.5V
+1.2VS
C106
0.22U_0402_6.3V6K
C106
0.22U_0402_6.3V6K
C105
0.22U_0402_6.3V6K
C105
0.22U_0402_6.3V6K
1
1
2
2
C8
VDDNB_1
D10
VDDNB_2
B8
VDDNB_3
B12
VDDNB_4
C9
VDDNB_5
A9
VDDNB_6
A10
VDDNB_7
A8
VDDNB_8
A11
VDDNB_9
E10
VDDNB_10
E11
VDDNB_11
C10
VDDNB_12
H26
VDDIO_1
K20
VDDIO_2
J28
VDDIO_3
K23
VDDIO_4
K26
VDDIO_5
L22
VDDIO_6
L25
VDDIO_7
L28
VDDIO_8
M20
VDDIO_9
M23
VDDIO_10
M26
VDDIO_11
N22
VDDIO_12
N25
VDDIO_13
N28
VDDIO_14
P20
VDDIO_15
P23
VDDIO_16
P26
VDDIO_17
AA28
VDDIO_18
AH6
VDDP_1
AH5
VDDP_2
AH4
VDDP_3
AH3
VDDP_4
AH7
VDDP_5
AB10
VDDA
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
JCPU1E
JCPU1E
VDDNB_13
VDDNB_14
VDDNB_15
VDDNB_16
VDDNB_17
VDDNB_18
VDDNB_19
VDDNB_20
VDDNB_21
VDDNB_22
VDDNB_23
VDDNB_CAP_1
VDDNB_CAP_2
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDR_1
VDDR_2
VDDR_3
VDDR_4
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
VDD_44
VDD_45
VDD_46
VDD_47
VDD_48
VDD_49
VDD_50
VDD_51
VDD_52
VDD_53
VDD_54
VDD_55
VDD_56
VDD_57
VDD_58
VDD_59
VDD_60
VDD_61
VDD_62
B
+APU_CORE
R11
T10
H8
G1
U11
W11
W13
W15
W17
W19
AB3
AD3
AD6
AE1
L1
Y6
M6
N11
N1
T3
T6
U19
U1
Y16
Y18
Y3
D4
F4
AF6
AF3
L11
C11
C12
D9
D8
D12
D11
B11
A12
B10
E12
B9
K13
K12
T23
T26
U22
U25
U28
Y26
T20
R28
R25
R22
V20
V23
V26
W22
W25
W28
Y24
G28
AG10
AH8
AH9
AH10
+APU_CORE_NB
+APU_CORE_NB_CAP
+1.5V
C107
180P_0402_50V8J
C107
180P_0402_50V8J
1
2
C108
180P_0402_50V8J
C108
180P_0402_50V8J
1
2
+APU_CORE
C73
0.22U_0402_6.3V6K
C73
0.22U_0402_6.3V6K
1
2
+APU_CORE_NB
C77
0.22U_0402_6.3V6K
C77
0.22U_0402_6.3V6K
1
2
+1.5V
C82
22U_0603_6.3V6M@C82
22U_0603_6.3V6M
1
@
2
+1.5V
C99
0.22U_0402_6.3V6K
C99
0.22U_0402_6.3V6K
1
2
C110
C109
1000P_0402_50V7K
C109
1000P_0402_50V7K
1
2
@
C70
0.01U_0402_16V7K
C70
0.01U_0402_16V7K
C74
0.22U_0402_6.3V6K
C74
0.22U_0402_6.3V6K
1
1
2
2
C78
0.22U_0402_6.3V6K
C78
0.22U_0402_6.3V6K
C79
180P_0402_50V8J
C79
180P_0402_50V8J
1
1
2
2
C84
22U_0603_6.3V6M
C84
22U_0603_6.3V6M
C83
22U_0603_6.3V6M
C83
22U_0603_6.3V6M
1
1
2
2
Across VDDIO and VSS
split
C100
0.22U_0402_6.3V6K
C100
0.22U_0402_6.3V6K
C101
180P_0402_50V8J
C101
180P_0402_50V8J
1
1
2
2
1000P_0402_50V7K@C110
1000P_0402_50V7K
C112
C111
1000P_0402_50V7K@C111
1000P_0402_50V7K
1
1
2
2
@
@
C
C71
0.01U_0402_16V7K
C71
0.01U_0402_16V7K
C75
C75
1
1
2
2
C80
180P_0402_50V8J
C80
180P_0402_50V8J
C81
C81
1
1
2
2
C85
22U_0603_6.3V6M
C85
22U_0603_6.3V6M
C86
C86
1
1
2
2
C102
180P_0402_50V8J
C102
180P_0402_50V8J
1
2
VDDR decoupling
C113
0.22U_0402_6.3V6K
C113
0.22U_0402_6.3V6K
1000P_0402_50V7K@C112
1000P_0402_50V7K
1
1
2
2
D
C72
180P_0402_50V8J
C72
180P_0402_50V8J
0.01U_0402_16V7K
0.01U_0402_16V7K
C76
180P_0402_50V8J
C76
180P_0402_50V8J
1
1
2
2
180P_0402_50V8J
180P_0402_50V8J
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
C114
C114
1
2
4.7U_0603_6.3V6K
C87
C87
C88
C88
1
1
2
2
+1.2VS
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
C91
C91
C90
C90
C89
C89
1
1
2
1
2
2
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
C92
0.22U_0402_6.3V6K
C92
0.22U_0402_6.3V6K
1
2
+APU_CORE_NB_CAP
C216
1
@
2
C93
0.22U_0402_6.3V6K
C93
0.22U_0402_6.3V6K
C94
C94
1
1
2
2
22U_0603_6.3V6M@C216
22U_0603_6.3V6M
C215
C215
C214
22U_0603_6.3V6M
C214
22U_0603_6.3V6M
1
2
C96
0.22U_0402_6.3V6K
C96
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
22U_0603_6.3V6M
22U_0603_6.3V6M
1
2
0.22U_0402_6.3V6K
C97
180P_0402_50V8J
C97
C95
0.22U_0402_6.3V6K
C95
0.22U_0402_6.3V6K
1
2
C217
180P_0402_50V8J
C217
180P_0402_50V8J
1
2
180P_0402_50V8J
C136
180P_0402_50V8J
C136
180P_0402_50V8J
C98
330U_D2_2.5VY_R9M+C98
330U_D2_2.5VY_R9M
1
1
2
2
1
1
+
2
2
Demo Board Capacitor
APU_CORE
22uF x 10
0.22uF x 2
0.01uF x 3
180pF x 2
CORE_NB
22uF x 2
10uF x 1
0.22uF x 2
180pF x 3
CORE_NB_CAP
22uF x 2
180pF x 1
E
JCPU1F
JCPU1F
J20
VSS_1
L4
VSS_2
R7
VSS_3
W18
VSS_4
A15
VSS_5
AB17
VSS_6
AC22
VSS_7
AE21
VSS_8
AF24
VSS_9
AH23
VSS_10
AH25
VSS_11
B7
VSS_12
C14
VSS_13
C16
VSS_14
C2
VSS_15
C20
VSS_16
C22
VSS_17
C24
VSS_18
C26
VSS_19
C28
VSS_20
D13
VSS_21
D15
VSS_22
D17
VSS_23
D19
VSS_24
D23
VSS_25
D25
VSS_26
D27
VSS_27
E4
VSS_28
E9
VSS_29
F14
VSS_30
F16
VSS_31
F18
VSS_32
F20
VSS_33
F22
VSS_34
F26
VSS_35
F28
VSS_36
G13
VSS_37
G15
VSS_38
G17
VSS_39
G19
VSS_40
G21
VSS_41
G23
VSS_42
G25
VSS_43
G4
VSS_44
J22
VSS_45
J24
VSS_46
J4
VSS_47
J7
VSS_48
K11
VSS_49
K14
VSS_50
K9
VSS_51
AC11
VSS_52
L19
VSS_53
L7
VSS_54
M11
VSS_55
AF11
VSS_56
V19
VSS_57
V9
VSS_58
W16
VSS_59
W4
VSS_60
W7
VSS_61
Y11
VSS_62
Y20
VSS_63
Y22
VSS_64
Y9
VSS_65
A17
VSS_66
A13
VSS_67
K16
VSS_68
F24
VSS_69
G8
VSS_70
H7
VSS_71
J8
VSS_72
LOTES_ACA-ZIF-109-P12-A_FS1R2
LOTES_ACA-ZIF-109-P12-A_FS1R2
CONN@
CONN@
VDDIO_SUS
(CPU side)
22uF x 4
4.7uF x 4
0.22uF x 6 +2(split)
180pF x 1 + 2(split)
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
A19
A21
A23
A25
A7
AA4
AA7
AB13
AB15
AB19
AB21
AB23
AB25
AB27
AB9
AC14
AC16
AC18
AC20
AC24
AC26
AC28
AC4
AC7
AD9
AE13
AE15
AE17
M9
N10
N4
N7
R10
R4
T11
T9
U10
U18
U4
U7
V11
AE19
AE23
AE25
AE27
AE4
AE7
AF14
AF16
AF18
AF20
AF22
AF26
AF28
AF9
AG4
AG7
AH13
AH15
AH17
AH19
AH21
P9
C18
D21
W14
P11
C7
E8
K18
W12
4 4
+2.5VS
L1
L1
FBMA-L11-201209-221LMA30T_0 805
FBMA-L11-201209-221LMA30T_0 805
12
C116
C116
C115
3300P_0402_50V7-K
C115
3300P_0402_50V7-K
1
1
2
2
A
40mil
0.22U_0402_6.3V6K
0.22U_0402_6.3V6K
+VDDA
C117
4.7U_0402_6.3V6M
C117
4.7U_0402_6.3V6M
1
2
B
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
VDDP
0.22uF x 2
180pF x 2
D
VDDR
0.22uF x 2
1nF x 4
180pF x 2
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
VDDA
4.7uF x 1
0.22uF x 1
3.3nF x 1
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
FS1r2 PWR/GND
FS1r2 PWR/GND
FS1r2 PWR/GND
VDDIO_SUS
(DIMM x2)
100uF x 2
0.1uF x 12
LA-8121P
LA-8121P
LA-8121P
E
8 50Monday, January 16, 2 012
8 50Monday, January 16, 2 012
8 50Monday, January 16, 2 012
0.4
0.4
0.4
5
4
3
2
1
Panel PWM
D D
C C
SIT, NO.4
HPD
DP_INT_PWM7
1 2
R66 2.2K_0402_5%R66 2.2K_0402_5%
12
R67
R67
4.7K_0402_5%
4.7K_0402_5%
+3VS
R62
R62
47K_0402_5%
47K_0402_5%
2
MMBT3904_NL_SOT23-3
MMBT3904_NL_SOT23-3
G
G
12
R63
R63
4.7K_0402_5%
4.7K_0402_5%
13
D
D
Q6
Q6
2N7002K_SOT23-3
2N7002K_SOT23-3
S
S
APU_INVT_PWM 25
12
C
C
Q8
Q8
2
B
B
E
E
3 1
B B
A A
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5
4
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Docum ent Number Rev
Size Docum ent Number Rev
Size Docum ent Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
FS1r2 Signal Level Shifter
FS1r2 Signal Level Shifter
FS1r2 Signal Level Shifter
LA-8121P
LA-8121P
LA-8121P
9 50Monday, January 16, 2012
9 50Monday, January 16, 2012
9 50Monday, January 16, 2012
1
0.4
0.4
0.4
A
B
C
D
E
+VREF_DQ
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDM0
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ8
C2011
C2011
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
DDRA_SBS2#
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_CLK0
DDRA_CLK0#
DDRA_SMA10
DDRA_SBS0#
DDRA_SWE#
DDRA_SCAS#
DDRA_SMA13
DDRA_SCS1#
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQS6#
DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
R2005 10K_0402_5%
R2005 10K_0402_5%
1 2
12
R2000
R2000
10K_0402_5%
10K_0402_5%
1 1
2 2
3 3
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
+3VS
C2010
C2010
DDRA_SDQS1#6
DDRA_SDQS16
DDRA_SDQS2#6
DDRA_SDQS26
DDRA_SBS2#6
DDRA_CLK06
DDRA_CLK0#6
DDRA_SBS0#6
DDRA_SWE#6
DDRA_SCAS#6
DDRA_SCS1#6
DDRA_SDQS4#6
DDRA_SDQS46
DDRA_SDQS6#6
DDRA_SDQS66
1
1
2
2
JDIMM2
JDIMM2
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
VSS1849DQ22
51
DQ18
DQ1953VSS19
VSS2055DQ28
57
DQ24
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A626-U2RN-7F
FOX_AS0A626-U2RN-7F
CONN@
CONN@
VREF_CA
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ23
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
+1.5V+1.5V
2
4
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
A7
A6
A4
A2
A0
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
G2
DDRA_SDQ4
6
DDRA_SDQ5
8
10
DDRA_SDQS0#
12
DDRA_SDQS0
14
16
DDRA_SDQ6
18
DDRA_SDQ7
20
22
DDRA_SDQ12
24
DDRA_SDQ13
26
28
DDRA_SDM1
30
MEM_MA_RST#
32
34
DDRA_SDQ14
36
DDRA_SDQ15
38
40
DDRA_SDQ20
42
DDRA_SDQ21
44
46
DDRA_SDM2
48
50
DDRA_SDQ22
52
DDRA_SDQ23
54
56
DDRA_SDQ28
58
DDRA_SDQ29
60
62
DDRA_SDQS3#
64
DDRA_SDQS3
66
68
DDRA_SDQ30
70
DDRA_SDQ31
72
74
DDRA_CKE1
76
78
DDRA_SMA15
80
DDRA_SMA14
82
84
DDRA_SMA11
86
DDRA_SMA7
88
90
DDRA_SMA6
92
DDRA_SMA4
94
96
DDRA_SMA2
98
DDRA_SMA0
100
102
DDRA_CLK1
104
DDRA_CLK1#
106
108
DDRA_SBS1#
110
DDRA_SRAS#
112
114
DDRA_SCS0#
116
DDRA_ODT0
118
120
DDRA_ODT1
122
124
126
128
130
DDRA_SDQ36
132
DDRA_SDQ37
134
136
DDRA_SDM4
138
140
DDRA_SDQ38
142
DDRA_SDQ39
144
146
DDRA_SDQ44
148
DDRA_SDQ45
150
152
DDRA_SDQS5#
154
DDRA_SDQS5
156
158
DDRA_SDQ46
160
DDRA_SDQ47
162
164
DDRA_SDQ52
166
DDRA_SDQ53
168
170
DDRA_SDM6
172
174
DDRA_SDQ54
176
DDRA_SDQ55
178
180
DDRA_SDQ60
182
DDRA_SDQ61
184
186
DDRA_SDQS7#
188
DDRA_SDQS7
190
192
DDRA_SDQ62
194
DDRA_SDQ63
196
198
MEM_MA_EVENT#
200
202
204
206
+0.75VS
DDRA_SDQS0# 6
DDRA_SDQS0 6
MEM_MA_RST# 6
DDRA_SDQS3# 6
DDRA_SDQS3 6
DDRA_CKE1 6DDRA_CKE06
DDRA_CLK1 6
DDRA_CLK1# 6
DDRA_SBS1# 6
DDRA_SRAS# 6
DDRA_SCS0# 6
DDRA_ODT0 6
DDRA_ODT1 6
+VREF_CA
DDRA_SDQS5# 6
DDRA_SDQS5 6
DDRA_SDQS7# 6
DDRA_SDQS7 6
MEM_MA_EVENT# 6
FCH_SDATA0 11,14,31,33
FCH_SCLK0 11,14,31,33
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
+1.5V
2
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VREF_DQ
15mil
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C2001
C2001
1
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRA_SDQ[0..63] 6
DDRA_SDM[0..7] 6
DDRA_SMA[0..15] 6
2
C2002
C2002
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VREF_DQ
1
C2007
C2007
2
1000P_0402_50V7K
1000P_0402_50V7K
2
1
C2008
C2008
C2003
C2003
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2004
C2004
1
+1.5V
R2001
R2001
1K_0402_1%
1K_0402_1%
1 2
R2003
R2003
1K_0402_1%
1K_0402_1%
1 2
Place near DIMM1
2
C2005
C2005
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+1.5V
1
+
+
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2006
C2006
1
+VREF_CA
C2025
C2025
330U_D2_2V_Y
330U_D2_2V_Y
15mil
+1.5V
R2002
R2002
1K_0402_1%
1K_0402_1%
+VREF_CA
1
C2000
C2000
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1 2
1
C2009
C2009
R2004
R2004
1K_0402_1%
1K_0402_1%
2
1 2
1000P_0402_50V7K
1000P_0402_50V7K
Reverse H:5.2mm
4 4
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
A
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDRIII SO-DIMM 1
DDRIII SO-DIMM 1
DDRIII SO-DIMM 1
LA-8121P
LA-8121P
LA-8121P
E
10 50Monday, January 16, 2012
10 50Monday, January 16, 2012
10 50Monday, January 16, 2012
0.4
0.4
0.4
A
B
C
D
E
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
VSS3
DQS0
VSS6
VSS8
DQ12
DQ13
DQ14
DQ15
DQ20
DQ21
DQ23
DQ29
DQS3
DQ30
DQ31
CKE1
VDD2
VDD4
VDD6
VDD8
CK1#
VDD12
RAS#
VDD14
ODT0
VDD16
ODT1
VDD18
VSS28
DQ36
DQ37
VSS30
VSS31
DQ38
DQ39
VSS33
DQ44
DQ45
VSS35
DQS#5
DQS5
VSS38
DQ46
DQ47
VSS40
DQ52
DQ53
VSS42
VSS43
DQ54
DQ55
VSS45
DQ60
DQ61
VSS47
DQS#7
DQS7
VSS50
DQ62
DQ63
VSS52
EVENT#
VTT2
+1.5V+1.5V
2
4
DQ4
DQ5
DQ6
DQ7
DM1
DM2
A15
A14
CK1
BA1
S0#
NC2
DM4
DM6
SDA
SCL
DDRB_SDQ4
6
DDRB_SDQ5
8
10
DDRB_SDQS0#
12
DDRB_SDQS0
14
16
DDRB_SDQ6
18
DDRB_SDQ7
20
22
DDRB_SDQ12
24
DDRB_SDQ13
26
28
DDRB_SDM1
30
MEM_MB_RST#
32
34
DDRB_SDQ14
36
DDRB_SDQ15
38
40
DDRB_SDQ20
42
DDRB_SDQ21
44
46
DDRB_SDM2
48
50
DDRB_SDQ22
52
DDRB_SDQ23
54
56
DDRB_SDQ28
58
DDRB_SDQ29
60
62
DDRB_SDQS3#
64
DDRB_SDQS3
66
68
DDRB_SDQ30
70
DDRB_SDQ31
72
74
DDRB_CKE1
76
78
DDRB_SMA15
80
DDRB_SMA14
82
84
DDRB_SMA11
86
A7
A6
A4
A2
A0
G2
DDRB_SMA7
88
90
DDRB_SMA6
92
DDRB_SMA4
94
96
DDRB_SMA2
98
DDRB_SMA0
100
102
DDRB_CLK1
104
DDRB_CLK1#
106
108
DDRB_SBS1#
110
DDRB_SRAS#
112
114
DDRB_SCS0#
116
DDRB_ODT0
118
120
DDRB_ODT1
122
124
126
128
130
DDRB_SDQ36
132
DDRB_SDQ37
134
136
DDRB_SDM4
138
140
DDRB_SDQ38
142
DDRB_SDQ39
144
146
DDRB_SDQ44
148
DDRB_SDQ45
150
152
DDRB_SDQS5#
154
DDRB_SDQS5
156
158
DDRB_SDQ46
160
DDRB_SDQ47
162
164
DDRB_SDQ52
166
DDRB_SDQ53
168
170
DDRB_SDM6
172
174
DDRB_SDQ54
176
DDRB_SDQ55
178
180
DDRB_SDQ60
182
DDRB_SDQ61
184
186
DDRB_SDQS7#
188
DDRB_SDQS7
190
192
DDRB_SDQ62
194
DDRB_SDQ63
196
198
MEM_MB_EVENT#
200
202
204
206
+0.75VS
DDRB_SDQS0# 6
DDRB_SDQS0 6
DDRB_SDQS3# 6
DDRB_SDQS3 6
DDRB_CKE1 6
DDRB_CLK1 6
DDRB_CLK1# 6
DDRB_SBS1# 6
DDRB_SRAS# 6
DDRB_SCS0# 6
DDRB_ODT0 6
DDRB_ODT1 6
+VREF_CA
DDRB_SDQS5# 6
DDRB_SDQS5 6
DDRB_SDQS7# 6
DDRB_SDQS7 6
MEM_MB_EVENT# 6
FCH_SDATA0 10,14,31,33
FCH_SCLK0 10,14,31,33
+VREF_DQ
DDRB_SDQ0
+3VS
DDRB_SDQ1
DDRB_SDM0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
DDRB_SDQ26
DDRB_SDQ27
DDRB_CKE0
DDRB_SBS2#
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
DDRB_CLK0
DDRB_CLK0#
DDRB_SMA10
DDRB_SBS0#
DDRB_SWE#
DDRB_SCAS#
DDRB_SMA13
DDRB_SCS1#
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
R2006 10K_0402_5%
R2006 10K_0402_5%
1 2
12
<BOM Structure>
<BOM Structure>
R2007
<BOM Structure>R2007
<BOM Structure>
10K_0402_5%
10K_0402_5%
1 1
DDRB_SDQS1#6
DDRB_SDQS16 MEM_MB_RST# 6
DDRB_SDQS2#6
DDRB_SDQS26
2 2
3 3
DDRB_CKE06
DDRB_SBS2#6
DDRB_CLK06
DDRB_CLK0#6
DDRB_SBS0#6
DDRB_SWE#6
DDRB_SCAS#6
DDRB_SCS1#6
DDRB_SDQS4#6
DDRB_SDQS46
DDRB_SDQS6#6
DDRB_SDQS66
JDIMM1
JDIMM1
VREF_DQ1VSS1
3
VSS2
5
DQ0
7
DQ1
VSS49DQS#0
11
DM0
13
VSS5
15
DQ2
17
DQ3
19
VSS7
21
DQ8
23
DQ9
VSS925VSS10
27
DQS#1
DQS129RESET#
VSS1131VSS12
33
DQ10
35
DQ11
VSS1337VSS14
39
DQ16
41
DQ17
VSS1543VSS16
45
DQS#2
DQS247VSS17
VSS1849DQ22
51
DQ18
DQ1953VSS19
VSS2055DQ28
57
DQ24
DQ2559VSS21
VSS2261DQS#3
63
DM3
VSS2365VSS24
67
DQ26
69
DQ27
VSS2571VSS26
73
CKE0
75
VDD1
77
NC1
79
BA2
81
VDD3
A12/BC#83A11
85
A9
87
VDD5
89
A8
91
A5
93
VDD7
95
A3
97
A1
VDD999VDD10
101
CK0
103
CK0#
105
VDD11
107
A10/AP
109
BA0
111
VDD13
113
WE#
115
CAS#
117
VDD15
119
A13
121
S1#
123
VDD17
125
NCTEST
127
VSS27
129
DQ32
131
DQ33
133
VSS29
135
DQS#4
137
DQS4
139
VSS32
141
DQ34
143
DQ35
145
VSS34
147
DQ40
149
DQ41
151
VSS36
153
DM5
155
VSS37
157
DQ42
159
DQ43
161
VSS39
163
DQ48
165
DQ49
167
VSS41
169
DQS#6
171
DQS6
173
VSS44
175
DQ50
177
DQ51
179
VSS46
181
DQ56
183
DQ57
185
VSS48
187
DM7
189
VSS49
191
DQ58
193
DQ59
195
VSS51
197
SA0
199
VDDSPD
201
SA1
203
VTT1
205
G1
FOX_AS0A626-UARN-7F
FOX_AS0A626-UARN-7F
CONN@
CONN@
VREF_CA
DDRB_SDQ[0..63] 6
DDRB_SDM[0..7] 6
DDRB_SMA[0..15] 6
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VREF_DQ
15mil
+VREF_DQ +VREF_CA
1000P_0402_50V7K
1000P_0402_50V7K
0.1U_0402_16V4Z
0.1U_0402_16V4Z
C2012
C2012
C2013
C2013
1
1
2
2
+1.5V
0.1U_0402_16V4Z
C2022
C2022
2
1
C2016
C2016
+0.75VS
2
1
0.1U_0402_16V4Z
2
1
C2017
C2017
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
C2023
C2023
4.7U_0603_6.3V6K
4.7U_0603_6.3V6K
2
2
C2018
C2018
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+VREF_CA
2
C2019
C2019
1
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
15mil
1000P_0402_50V7K
1000P_0402_50V7K
C2014
C2014
1
1
C2015
C2015
2
2
Place near DIMM2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
C2020
C2020
1
+1.5V
1
+
+
2
8/25
2
C2021
C2021
1
C2024
C2024
330U_D2_2V_Y
330U_D2_2V_Y
@
@
4 4
A
Reverse H:9.2mm
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
B
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
C
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
D
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
C
C
C
Date: Sheet of
Date: Sheet of
Date: Sheet of
DDRIII SO-DIMM 2
DDRIII SO-DIMM 2
DDRIII SO-DIMM 2
LA-8121P
LA-8121P
LA-8121P
E
11 50Monday, January 16, 2012
11 50Monday, January 16, 2012
11 50Monday, January 16, 2012
0.4
0.4
0.4
A
150P_0402_50V8J
R90/ C146 close to FCH
1 1
150P_0402_50V8J
SDV2, NO.42
1 2
C129
C129
22P_0402_50V8J
22P_0402_50V8J
20M_0402_5%
20M_0402_5%
C130
C130
27P_0402_50V8J
27P_0402_50V8J
8/26 G3 mode RTC time issue - need to check
2 2
8/26 follow CRB
R75
R75
1 2
33P_0402_50V8J
33P_0402_50V8J
1 2
C131
C131
1M_0402_5%
1M_0402_5%
C134
C134
1 2
33P_0402_50V8J
33P_0402_50V8J
12
Close to HUDSON-M2/3
X1
X1
25MHZ_20PF_7V25000016
25MHZ_20PF_7V25000016
1
R88
R88
1
GND
FVT, NO.22
32K_X1
12
Y1
Y1
32.768KHZ_12.5PF_CM31532768DZFT
32.768KHZ_12.5PF_CM31532768DZFT
32K_X2
25M_X1
3
3
GND
2
4
25M_X2
WLAN
3 3
LAN
Card Reader
For PCIE device reset on FS1
(GFX,GLAN,WLAN,LVDS Travis)
APU_PCIE_RST #: Reset PCIE device on APU
MC74VHC1G08DFT2G_SC70-5
4 4
APU_PCIE_RST#_C
R89/ C135 close to FCH
MC74VHC1G08DFT2G_SC70-5
R89
R89
1 2
33_0402_5%
33_0402_5%
C135
C135
A
1
R90
R90
@
@
2
1 2
150P_0402_50V8J
150P_0402_50V8J
+3V_FCH
5
2
B
1
A
3
8.2K_0402_5%
8.2K_0402_5%
R92
@R92
@
1 2
0_0402_5%
0_0402_5%
CLK_PCIE_VGA17
CLK_PCIE_VGA#17
CLK_PCIE_WLAN#33
CLK_PCIE_LAN35
CLK_PCIE_LAN#35
SDV2, NO.54
CLK_PCIE_CARD35
CLK_PCIE_CARD#35
SDV2, NO.64
CLK_LAN_25M35
C133
C133
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
P
4
Y
G
U3
U3
C125
C125
8/25
1 2
UMI_RXP05
UMI_RXN05
UMI_RXP15
UMI_RXN15
UMI_RXP25
UMI_RXN25
UMI_RXP35
UMI_RXN35
UMI_TXP05
UMI_TXN05
UMI_TXP15
UMI_TXN15
UMI_TXP25
UMI_TXN25
UMI_TXP35
UMI_TXN35
+VDDAN_11_PCIE
12
B
PLT_RST#
1 2
C126 .1U_0402_16V7KC126 .1U_0402_16V7K
1 2
C118 .1U_0402_16V7KC118 .1U_0402_16V7K
1 2
C119 .1U_0402_16V7KC119 .1U_0402_16V7K
1 2
C120 .1U_0402_16V7KC120 .1U_0402_16V7K
1 2
C127 .1U_0402_16V7KC127 .1U_0402_16V7K
1 2
C121 .1U_0402_16V7KC121 .1U_0402_16V7K
1 2
C128 .1U_0402_16V7KC128 .1U_0402_16V7K
1 2
C122 .1U_0402_16V7KC122 .1U_0402_16V7K
R71 590_0402_1%R71 590_0402_1%
R73 2K_0402_1%R73 2K_0402_1%
+1.1VS_CKVDD
1 2
R76 0_0402_5%R76 0_0402_5%
1 2
R77 0_0402_5%R77 0_0402_5%
1 2
R150 0_0402_5%R150 0_0402_5%
1 2
R142 0_0402_5%R142 0_0402_5%
1 2
R80 33_0402_5%R80 33_0402_5%
1 2
R82 33_0402_5%R82 33_0402_5%
1 2
R83 33_0402_5%R83 33_0402_5%
1 2
R84 33_0402_5%R84 33_0402_5%
1 2
R86 22_0402_5%@R86 22_0402_5%@
APU_PCIE_RST# 17,33,35
R91
R91
0_0402_5%
0_0402_5%
@
@
PLT_RST# 31,35
B
1 2
R72 3 3_0402_5%R72 3 3_0402_5%
1 2
1 2
R74
R74
1 2
APU_DISP_CLK7
APU_DISP_CLK#7
APU_CLK7
APU_CLK#7
8/26
APU_PCIE_RST#_C
A_RST#
UMI_RXP0_C
UMI_RXN0_C
UMI_RXP1_C
UMI_RXN1_C
UMI_RXP2_C
UMI_RXN2_C
UMI_RXP3_C
UMI_RXN3_C
PCIE_CALRP
PCIE_CALRN
CLK_CALRN
2K_0402_1%
2K_0402_1%
CLK_PCIE_VGA_R
CLK_PCIE_VGA#_R
CLK_PCIE_WLAN_R
CLK_PCIE_WLAN#_R
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLK_PCIE_CARD_R
CLK_PCIE_CARD#_R
CLK_LAN_25M_R
C
U2A
U2A
HUDSON-2
AE2
PCIE_RST#
AD5
A_RST#
AE30
UMI_TX0P
AE32
UMI_TX0N
AD33
UMI_TX1P
AD31
UMI_TX1N
AD28
UMI_TX2P
AD29
UMI_TX2N
AC30
UMI_TX3P
AC32
UMI_TX3N
AB33
UMI_RX0P
AB31
UMI_RX0N
AB28
UMI_RX1P
AB29
UMI_RX1N
Y33
UMI_RX2P
Y31
UMI_RX2N
Y28
UMI_RX3P
Y29
UMI_RX3N
AF29
PCIE_CALRP
AF31
PCIE_CALRN
V33
GPP_TX0P
V31
GPP_TX0N
W30
GPP_TX1P
W32
GPP_TX1N
AB26
GPP_TX2P
AB27
GPP_TX2N
AA24
GPP_TX3P
AA23
GPP_TX3N
AA27
GPP_RX0P
AA26
GPP_RX0N
W27
GPP_RX1P
V27
GPP_RX1N
V26
GPP_RX2P
W26
GPP_RX2N
W24
GPP_RX3P
W23
GPP_RX3N
F27
CLK_CALRN
G30
PCIE_RCLKP
G28
PCIE_RCLKN
R26
DISP_CLKP
T26
DISP_CLKN
H33
DISP2_CLKP
H31
DISP2_CLKN
T24
APU_CLKP
T23
APU_CLKN
J30
SLT_GFX_CLKP
K29
SLT_GFX_CLKN
H27
GPP_CLK0P
H28
GPP_CLK0N
J27
GPP_CLK1P
K26
GPP_CLK1N
F33
GPP_CLK2P
F31
GPP_CLK2N
E33
GPP_CLK3P
E31
GPP_CLK3N
M23
GPP_CLK4P
M24
GPP_CLK4N
M27
GPP_CLK5P
M26
GPP_CLK5N
N25
GPP_CLK6P
N26
GPP_CLK6N
R23
GPP_CLK7P
R24
GPP_CLK7N
N27
GPP_CLK8P
R27
GPP_CLK8N
J26
14M_25M_48M_OSC
C31
25M_X1
25M_X2
25M_X1
C33
25M_X2
21807-A13-HUDSON-M3_FCBGA656
21807-A13-HUDSON-M3_FCBGA656
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
C
HUDSON-2
PCICLK1/GPO36
PCICLK2/GPO37
PCI CLKS
PCI CLKS
PCI EXPRESS INTERFACES
PCI EXPRESS INTERFACES
PCI INTERFACE
PCI INTERFACE
CLOCK GENERATOR
CLOCK GENERATOR
LPCAPUS5 PLUS
LPCAPUS5 PLUS
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
PCICLK3/GPO38
PCICLK4/14M_OSC/G PO39
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
REQ1#/GPIO40
REQ2#/CLK_REQ8#/G PIO41
REQ3#/CLK_REQ5#/G PIO42
GNT1#/GPO44
GNT2#/SD_LED/GPO 45
GNT3#/CLK_REQ7#/G PIO46
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
LDRQ1#/CLK_REQ6#/ GPIO49
SERIRQ/GPIO48
DMA_ACTIVE#
S5_CORE_EN
INTRUDER_ALERT#
VDDBT_RTC_G
Compal Secret Data
Compal Secret Data
Compal Secret Data
PCICLK0
PCIRST#
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
GNT0#
CLKRUN#
LOCK#
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
PROCHOT#
APU_PG
LDT_STP#
APU_RST#
RTCCLK
32K_X1
32K_X2
Deciphered Date
Deciphered Date
Deciphered Date
AF3
AF1
AF5
AG2
AF6
AB5
AJ3
AL5
AG4
AL6
AH3
AJ5
AL1
AN5
AN6
AJ1
AL8
AL3
AM7
AJ6
AK7
AN8
AG9
AM11
AJ10
AL12
AK11
AN12
AG12
AE12
AC12
AE13
AF13
AH13
AH14
AD15
AC15
AE16
AN3
AJ8
AN10
AD12
AG10
AK9
AL10
AF10
AE10
AH1
AM9
AH8
AG15
AG13
AF15
AM17
AD16
AD13
AD21
AK17
AD19
AH9
AF18
AE18
AC16
AD18
B25
D25
D27
C28
A26
A29
A31
B27
AE27
AE19
G25
E28
E26
G26
F26
H7
F1
F3
E6
G2
G4
D
1 2
R209 0_0402_5%@R209 0_0402_5%@
1 2
R208 0_0402_5%@R208 0_0402_5%@
LPCCLK0
APU_PROCHOT#_R
32K_X1
32K_X2
D
PCI_CLK1 16
PCI_CLK3 16
PCI_CLK4 16
PCI_AD23 16
PCI_AD24 16
PCI_AD25 16
PCI_AD26 16
PCI_AD27 16
T11T11
T22T22
1 2
R110 0_0402_5%@R110 0_0402_5%@
1 2
R215 33_0402_5%R215 33_0402_5%
LPC_CLK1 16
LPC_AD0 31,33,35
LPC_AD1 31,33,35
LPC_AD2 31,33,35
LPC_AD3 31,33,35
LPC_FRAME# 31,33,35
SERIRQ 31
R85 0_0402_5%@R85 0_0402_5%@
APU_PWRGD 45,7
APU_RST# 7
RTC_CLK 16,31
1 2
E
PXS_RST# 14,17
PXS_PWREN 14,19,43,44
CLK_PCI_DB 33,35CLK_PCIE_WLAN33
CLK_PCI_EC 16,31
ALLOW_STOP 7
APU_PROCHOT# 7
+RTCBATT
12
JCMOS1
@JC MOS1
@
SHORT PADS
SHORT PADS
1U_0402_6.3V6K
1U_0402_6.3V6K
W=20mils
1
C132
C132
2
1 2
R87 510_0402_5%R87 510_04 02_5%
for Clear CMOS
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size D ocument Number Rev
Size D ocument Number Rev
Size D ocument Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FCH PCIE/CLK/PCI/LPC/RTC
FCH PCIE/CLK/PCI/LPC/RTC
FCH PCIE/CLK/PCI/LPC/RTC
LA-8121P
LA-8121P
LA-8121P
12 50Monday, January 16, 2012
12 50Monday, January 16, 2012
12 50Monday, January 16, 2012
E
0.4
0.4
0.4
A
B
C
D
E
4MB SPI ROM
SPI_CLK_FCH_R
R99
R99
0_0402_5%
0_0402_5%
SPI_CLK_FCH
R93
R93
33_0402_5%
33_0402_5%
@
@
22P_0402_50V8J
22P_0402_50V8J
@
@
+3V_FCH
13 50Mon day, January 16, 2012
13 50Mon day, January 16, 2012
13 50Mon day, January 16, 2012
C138
C138
12
0.4
0.4
0.4
& Non-share ROM.
8/26 use +3VALW
U2B
1 1
HDD
ODD
2 2
3 3
4 4
SATA_FTX_DRX_P030
SATA_FTX_DRX_N030
SATA_FRX_C_DTX_N030
SATA_FRX_C_DTX_P030
SATA_FTX_DRX_P130
SATA_FTX_DRX_N130
SATA_FRX_C_DTX_N130
SATA_FRX_C_DTX_P130
+AVDD_SATA
A
1 2
C139 0.01U_0402_16V7KC139 0.01U_04 02_16V7K
1 2
C140 0.01U_0402_16V7KC140 0.01U_04 02_16V7K
1 2
C143 0.01U_0402_16V7KC143 0.01U_04 02_16V7K
1 2
C142 0.01U_0402_16V7KC142 0.01U_04 02_16V7K
+3VS
8/26
BT_ON#32
WLBT_OFF#33
WL_OFF#33
8/25
ODD_EN30
APU_ALERT#_FCH7
SATA_FTX_C_DRX_P0
SATA_FTX_C_DRX_N0
SATA_FTX_C_DRX_P1
SATA_FTX_C_DRX_N1
12
SATA_CALRP
R1071K_0402_1 % R1071K_0 402_1%
12
SATA_CALRN
R108931_0402 _1% R108931_0402_1%
12
R21410K_0402_ 5% R21410K_0402_ 5%
BT_ON#
WLBT_OFF#
WL_OFF#
ODD_EN
1 2
R119 10K_0402_5%R119 10K_0402_5%
1 2
R122 10K_0402_5%R122 10K_0402_5%
1 2
R123 10K_0402_5%R123 10K_0402_5%
B
U2B
AK19
SATA_TX0P
AM19
SATA_TX0N
AL20
SATA_RX0N
AN20
SATA_RX0P
AN22
SATA_TX1P
AL22
SATA_TX1N
AH20
SATA_RX1N
AJ20
SATA_RX1P
AJ22
SATA_TX2P
AH22
SATA_TX2N
AM23
SATA_RX2N
AK23
SATA_RX2P
AH24
SATA_TX3P
AJ24
SATA_TX3N
AN24
SATA_RX3N
AL24
SATA_RX3P
AL26
SATA_TX4P
AN26
SATA_TX4N
AJ26
SATA_RX4N
AH26
SATA_RX4P
AN29
SATA_TX5P
AL28
SATA_TX5N
AK27
SATA_RX5N
AM27
SATA_RX5P
AL29
NC6
AN31
NC7
AL31
NC8
AL33
NC9
AH33
NC10
AH31
NC11
AJ33
NC12
AJ31
NC13
AF28
SATA_CALRP
AF27
SATA_CALRN
AD22
SATA_ACT#/GPIO67
AF21
SATA_X1
AG21
SATA_X2
AH16
FANOUT0/GPIO52
AM15
FANOUT1/GPIO53
AJ16
FANOUT2/GPIO54
AK15
FANIN0/GPIO56
AN16
FANIN1/GPIO57
AL16
FANIN2/GPIO58
K6
TEMPIN0/GPIO171
K5
TEMPIN1/GPIO172
K3
TEMPIN2/GPIO173
M6
TEMPIN3/TALERT#/GPIO174
21807-A13-HUDSON-M3_FCBGA656
21807-A13-HUDSON-M3_FCBGA656
HUDSON-2
HUDSON-2
SERIAL ATA
SERIAL ATA
HW MONITOR
HW MONITOR
SD_CLK/SCLK_2/GPIO73
SD_CMD/SLOAD_2/GPIO74
SD_CD/GPIO75
SD_WP/GPIO76
SD_DATA0/SDATI_2/GPIO77
SD_DATA1/SDATO_2/GPIO78
SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK
SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK
SD_DATA2/GPIO79
SD_DATA3/GPIO80
GBE_RXCTL/RXDV
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/SPI_WP#/GPIO161
VGA_HSYNC/GPO68
VGA_VSYNC/GPO69
VGA_DDC_SDA/GPO70
VGA_DDC_SCL/GPO71
VGA_DAC_RSET
AUX_VGA_CH_P
AUX_VGA_CH_N
ML_VGA_L0N
ML_VGA_L1P
ML_VGA_L1N
ML_VGA_L2P
ML_VGA_L2N
ML_VGA_L3P
ML_VGA_L3N
ML_VGA_HPD/GPIO229
VIN0/GPIO175
VIN1/GPIO176
VIN2/SDATI_1/GPIO177
VIN3/SDATO_1/GPIO178
VIN4/SLOAD_1/GPIO179
VIN5/SCLK_1/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
VGA_RED
VGA_GREEN
VGA_BLUE
AUXCAL
ML_VGA_L0P
NC1
NC2
NC3
NC4
NC5
C
AL14
AN14
AJ12
AH12
AK13
AM13
AH15
AJ14
AC4
AD3
AD9
W10
FCH SCLv1.20 19:
AB8
GBE_COL/GBE_CRS/GBE_RXERR NC
AH7
AF7
AE7
AD7
AG8
AD1
AB7
AF9
AG6
AE8
AD8
AB9
AC2
AA7
W9
GBE_PHY_INTR
V6
SPI_SO
V5
SPI_SI
V3
SPI_CLK_FCH_R
T6
SPI_SB_CS0#
V1
SPI_WP#
L30
L32
M29
M28
N30
M33
N32
K31
V28
V29
U28
T31
T33
T29
T28
R32
R30
P29
P28
C29
N2
M3
L2
N4
P1
P3
M1
M5
AG16
AH10
A28
G27
L4
1 2
R104 150 _0402_1%R1 04 150_0402_1%
1 2
R105 150 _0402_1%R1 05 150_0402_1%
1 2
R106 150 _0402_1%R1 06 150_0402_1%
1 2
R109 715 _0402_1%R1 09 715_0402_1%
AUXCAL
1 2
R111 100 _0402_1%R1 11 100_0402_1%
1 2
R113 10K_0402_5%R113 10K_0402_5%
1 2
R114 10K_0402_5%R114 10K_0402_5%
1 2
R115 10K_0402_5%R115 10K_0402_5%
1 2
R116 10K_0402_5%R116 10K_0402_5%
1 2
R117 10K_0402_5%R117 10K_0402_5%
1 2
R118 10K_0402_5%R118 10K_0402_5%
1 2
R120 10K_0402_5%R120 10K_0402_5%
1 2
R121 10K_0402_5%R121 10K_0402_5%
Follow Comal ORB Rework Memo
Compal Secret Data
Compal Secret Data
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Compal Secret Data
+3VALW
CRT_HSYNC 28
CRT_VSYNC 28
CRT_DDC_DATA 28
CRT_DDC_CLK 28
ML_VGA_AUXP_C 7
ML_VGA_AUXN_C 7
ML_VGA_TXP0 7
ML_VGA_TXN0 7
ML_VGA_TXP1 7
ML_VGA_TXN1 7
ML_VGA_TXP2 7
ML_VGA_TXN2 7
ML_VGA_TXP3 7
ML_VGA_TXN3 7
ML_VGA_HPD 7
Deciphered Date
Deciphered Date
Deciphered Date
R94 10K_040 2_5%R94 10K_0402_5%
SIT, NO.4
+3VALW
1 2
R95
R95
R101
R101
10K_0402_5%
10K_0402_5%
1 2
SPI_SB_CS0#
SPI_SO
1 2
SPI_WP#
DAC_RED 28
DAC_GRN 28
DAC_BLU 28
+VDDAN_11_ML
+FCH_VDDAN_33_DAC
12
R11210K_0402_5% R11210K_ 0402_5%
Used as GPIO181 or configure as one of the following:
-> 10-KΩ 5% pull-down resistor.
-> 10-KΩ 5% pull-up resistor to +3.3V_S5.
-> Enabled integrated pull-down/up and left unconnected.
D
SPI_HOLD#
10K_0402_5%
10K_0402_5%
FVT, No.45
U4
U4
1
CS#
2
DO
HOLD#
3
WP#
4
GND
W25Q32BVSSIG_SO8
W25Q32BVSSIG_SO8
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
+3VALW
C141
C141
1 2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
8
VCC
7
SPI_HOLD#
6
SPI_CLK_FCH
CLK
5
SPI_SI
DI
GBE_PHY_INTR
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
FCH SATA/SPI/VGA/HWM/SD
FCH SATA/SPI/VGA/HWM/SD
FCH SATA/SPI/VGA/HWM/SD
LA-8121P
LA-8121P
LA-8121P
1 2
1 2
R100 10K_ 0402_5%R100 10K_0402_5%
E
A
+3VS
@
@
C144 .1U_0402_16V7K
C144 .1U_0402_16V7K
1 2
5
2
P
B
Y
1
A
G
MC74VHC1G08DFT2G_SC70-5
MC74VHC1G08DFT2G_SC70-5
3
U5
U5
S
S
Q43
Q43
2N7002K_SOT23-3
2N7002K_SOT23-3
TEST0
TEST1
TEST2
USB_OC3#
USB_OC1#
USB_OC0#
ODD_DETECT#
H_THERMTRIP#
EC_LID_OUT#
FCH_PCIE_WAKE#
ODD_DA#_FCH_R
WLAN_CLKREQ#
CARD_CLKREQ#
FCH_SCLK0
FCH_SDATA0
WD_PWRGD
LAN_CLKREQ#
FCH_SCLK1
FCH_SDATA1
EC_RSMRST#
HDA_BITCLK
HDA_SDIN0
PEG_CLKREQ#_R
12
12
FCH_POK 31
VGATE 31,45
@
@
+3V_FCH
2
G
G
13
ODD_DA#_FCH_R
D
D
PEG_CLKREQ#18
HDA_BITCLK_AUDIO29
HDA_SDOUT_AUDIO29
HDA_SDIN029
HDA_SYNC_AUDIO29
HDA_RST_AUDIO#29
PXS_RST#12,17
PXS_PWREN12,19,43,44
SDV2, NO.51
+3V_FCH
1 2
R211 10K_ 0402_5%DIS@R211 10K_0402_5%DIS@
EC_PXCONTROL3 1
SCL1/SDA1: ASF-Capable LAN Devices Not Implemented: Used as
GPIO227 or configured for one of the following options: 10-KΩ 5% pull-up
resistor to +3.3V_S5; 10-KΩ 5% pull-down resistor.
+3V_FCH
12
UMA@
UMA@
12
DIS@
DIS@
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
8/26
12
12
@
@
UMA@
UMA@
R157
R157
R164
R164
R206
R206
R158
R158
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
GPIO188
GPIO189
GPIO190
12
12
DIS@
DIS@
R165
R165
R210
R210
10K_0402_5%
10K_0402_5%
10K_0402_5%
10K_0402_5%
R124 0_040 2_5%@R124 0_ 0402_5%@
R125 0_040 2_5%R125 0_0402_5%
FCH_PWRGD45
1 1
For ODD Power Leakage issue
ODD_DA#_FCH3 0
2 2
+3V_FCH
For FCH internal debug use
1 2
R128 2.2 K_0402_5%@R128 2.2K_0402_5%@
1 2
R129 2.2 K_0402_5%@R129 2.2K_0402_5%@
1 2
R130 2.2 K_0402_5%@R130 2.2K_0402_5%@
+3V_FCH
1 2
R154 10K_0402_ 5%R154 10K_0402_5%
1 2
R137 10K_0402_ 5%R137 10K_0402_5%
1 2
R139 10K_0402_ 5%R139 10K_0402_5%
1 2
R205 10K_0402_ 5%@R205 10K_0402_5%@
1 2
R143 10K_0402_ 5%@R143 10K_0402_5%@
1 2
R145 100K_0402 _5%@R145 100K_04 02_5%@
1 2
R149 10K_0402_ 5%R149 10K_0402_5%
3 3
4 4
1 2
R155 10K_0402_ 5%@R155 10K_0402_5%@
+3VS
1 2
R174 10K_ 0402_5%R174 10K_0402_5%
1 2
R156 10K_ 0402_5%R156 10K_0402_5%
1 2
R151 2.2 K_0402_5%R151 2.2 K_0402_5%
1 2
R152 2.2 K_0402_5%R152 2.2 K_0402_5%
1 2
R153 10K_ 0402_5%R153 10K_0402_5%
1 2
R159 8.2 K_0402_5%R159 8.2 K_0402_5%
1 2
R160 10K_ 0402_5%R160 10K_0402_5%
1 2
R161 10K_ 0402_5%R161 10K_0402_5%
1 2
R162 2.2 K_0402_5%R162 2.2 K_0402_5%
1 2
R163 10K_ 0402_5%@R163 10K_0402_5%@
1 2
R166 10K_ 0402_5%@R166 10K_0402_5%@
1 2
R167 10K_ 0402_5%@R167 10K_0402_5%@
CLKREQG Not Implemented:
Used as GPIO65, IDLEEXIT#, or left unconnected.
4
2
@
@
C145
C145
.1U_0402_16V7K
.1U_0402_16V7K
1
+3VS +3VS
R213
R213
10K_0402_5%
10K_0402_5%
1 2
THERMTRIP
8/16 AMD confirmed: The FCH already have internal PU resistor
and don't need external PU resistor.
Note: need BIOS check: Ensure FCH internal pull-up resistor to
+3.3V S5 is disabled to prevent leakage when APU is powered down.
8/25
A
B
PCIE_RST2 : Reset PCIE device on Hudson2/3
EC_LID_OUT#31
PM_SLP_S3#31
PM_SLP_S5#31
PBTN_OUT#31
GATEA2031
KB_RST#31
EC_SCI#31
EC_SMI#31
1 2
R126 10K_ 0402_5%@R126 10K_0402_5%@
FCH_PCIE_WAKE#35
H_THERMTRIP#7
EC_RSMRST#31
LAN_CLKREQ#35
CARD_CLKREQ#35
FCH_SPKR29
FCH_SCLK010,11,31,33
FCH_SDATA010,11,31,33
WLAN_CLKREQ#33
VGA_PWRGD19,44
R131 0_0 402_5%@R131 0_0402_5%@
ODD_DETECT#3 0
R134 33_ 0402_5%R134 33_0402 _5%
R135 33_ 0402_5%R135 33_0402 _5%
R138 33_ 0402_5%R138 33_0402 _5%
R140 33_ 0402_5%R140 33_0402 _5%
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
EC_PXCONTROL
0
12
USB_OC3#35
USB_OC1#34
USB_OC0#34
1 2
1 2
1 2
1 2
12
R1460_0402_5% DIS@ R1460_0402_5% DIS@
12
R1480_0402_5% DIS@ R1480_0402_5% DIS@
DIS@
DIS@
Q44A
Q44A
61
DIS@
DIS@
Q44B
Q44B
DMN66D0LDW-7_SOT363-6
DMN66D0LDW-7_SOT363-6
2
3 4
5
0 0
0
0
0
1 1
B
FCH_PWRGD
TEST0
TEST1
TEST2
SYS_RESET#
WD_PWRGD
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
PEG_CLKREQ#_R
ODD_DA#_FCH_R
ODD_DETECT#
USB_OC3#
USB_OC1#
USB_OC0#
10
01
T13T13
T19T19
HDA_BITCLK
HDA_SDOUT
HDA_SDIN0
HDA_SYNC
HDA_RST#
GPIO188
GPIO189
GPIO190
T34T34
T35T35
T36T36
T37T37
T38T38
T39T39
T43T43
T44T44
T45T45
T40T40
T41T41
T42T42
T49T49
T50T50
T51T51
T46T46
T47T47
T48T48
FunctionGPIO188 GPIO189 GPIO190
PX
Reserved
DISCRET
UMA
C
U2D
U2D
HUDSON-2
AB6
PCIE_RST2#/PCI_PME#/GEVENT4#
R2
RI#/GEVENT22#
W7
SPI_CS3#/GBE_STAT1/GEVENT21#
T3
SLP_S3#
W2
SLP_S5#
J4
PWR_BTN#
N7
PWR_GOOD
T9
TEST0
T10
TEST1/TMS
V9
TEST2
AE22
GA20IN/GEVENT0#
AG19
KBRST#/GEVENT1#
R9
LPC_PME#/GEVENT3#
C26
LPC_SMI#/GEVENT23#
T5
LPC_PD#/GEVENT5#
U4
SYS_RESET#/GEVENT19#
K1
WAKE#/GEVENT8#
V7
IR_RX1/GEVENT20#
R10
THRMTRIP#/SMBALERT#/GEVENT2#
AF19
WD_PWRGD
U2
RSMRST#
AG24
CLK_REQ4#/SATA_IS0#/GPIO64
AE24
CLK_REQ3#/SATA_IS1#/GPIO63
AE26
SMARTVOLT1/SATA_IS2#/GPIO50
AF22
CLK_REQ0#/SATA_IS3#/GPIO60
AH17
SATA_IS4#/FANOUT3/GPIO55
AG18
SATA_IS5#/FANIN3/GPIO59
AF24
SPKR/GPIO66
AD26
SCL0/GPIO43
AD25
SDA0/GPIO47
T7
SCL1/GPIO227
R7
SDA1/GPIO228
AG25
CLK_REQ2#/FANIN4/GPIO62
AG22
CLK_REQ1#/FANOUT4/GPIO61
J2
IR_LED#/LLB#/GPIO184
AG26
SMARTVOLT2/SHUTDOWN#/GPIO51
V8
DDR3_RST#/GEVENT7#/VGA_PD
W8
GBE_LED0/GPIO183
Y6
SPI_HOLD#/GBE_LED1/GEVENT9#
V10
GBE_LED2/GEVENT10#
AA8
GBE_STAT0/GEVENT11#
AF25
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
M7
BLINK/USB_OC7#/GEVENT18#
R8
USB_OC6#/IR_TX1/GEVENT6#
T1
USB_OC5#/IR_TX0/GEVENT17#
P6
USB_OC4#/IR_RX0/GEVENT16#
F5
USB_OC3#/AC_PRES/TDO/GEVENT15#
P5
USB_OC2#/TCK/GEVENT14#
J7
USB_OC1#/TDI/GEVENT13#
T8
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12#
AB3
AZ_BITCLK
AB1
AZ_SDOUT
AA2
AZ_SDIN0/GPIO167
Y5
AZ_SDIN1/GPIO168
Y3
AZ_SDIN2/GPIO169
Y1
AZ_SDIN3/GPIO170
AD6
AZ_SYNC
AE4
AZ_RST#
K19
PS2_DAT/SDA4/GPIO187
J19
PS2_CLK/CEC/SCL4/GPIO188
J21
SPI_CS2#/GBE_STAT2/GPIO166
D21
PS2KB_DAT/GPIO189
C20
PS2KB_CLK/GPIO190
D23
PS2M_DAT/GPIO191
C22
PS2M_CLK/GPIO192
F21
KSO_0/GPIO209
E20
KSO_1/GPIO210
F20
KSO_2/GPIO211
A22
KSO_3/GPIO212
E18
KSO_4/GPIO213
A20
KSO_5/GPIO214
J18
KSO_6/GPIO215
H18
KSO_7/GPIO216
G18
KSO_8/GPIO217
B21
KSO_9/GPIO218
K18
KSO_10/GPIO219
D19
KSO_11/GPIO220
A18
KSO_12/GPIO221
C18
KSO_13/GPIO222
B19
KSO_14/GPIO223
B17
KSO_15/GPIO224
A24
KSO_16/GPIO225
D17
KSO_17/GPIO226
21807-A13-HUDSON-M3_FCBGA656
21807-A13-HUDSON-M3_FCBGA656
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
C
HUDSON-2
EMBEDDED CTRL
EMBEDDED CTRL
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
USBCLK/14M_25M_48M_OSC
USB MISCUSB 1.1USB 2.0USB 3.0
USB MISCUSB 1.1USB 2.0USB 3.0
USB_FSD1P/GPIO186
USB_FSD0P/GPIO185
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/WOL_EN/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
USB_RCOMP
USB_FSD1N
USB_FSD0N
USB_HSD13P
USB_HSD13N
USB_HSD12P
USB_HSD12N
USB_HSD11P
USB_HSD11N
USB_HSD10P
USB_HSD10N
USB_HSD9P
USB_HSD9N
USB_HSD8P
USB_HSD8N
USB_HSD7P
USB_HSD7N
USB_HSD6P
USB_HSD6N
USB_HSD5P
USB_HSD5N
USB_HSD4P
USB_HSD4N
USB_HSD3P
USB_HSD3N
USB_HSD2P
USB_HSD2N
USB_HSD1P
USB_HSD1N
USB_HSD0P
USB_HSD0N
USBSS_CALRP
USBSS_CALRN
USB_SS_TX3P
USB_SS_TX3N
USB_SS_RX3P
USB_SS_RX3N
USB_SS_TX2P
USB_SS_TX2N
USB_SS_RX2P
USB_SS_RX2N
USB_SS_TX1P
USB_SS_TX1N
USB_SS_RX1P
USB_SS_RX1N
USB_SS_TX0P
USB_SS_TX0N
USB_SS_RX0P
USB_SS_RX0N
SCL2/GPIO193
SDA2/GPIO194
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
D
G8
B9
USB_RCOMP
H1
H3
H6
H5
H10
G10
K10
J12
G12
F12
K12
K13
B11
D11
E10
F10
C10
A10
H9
G9
A8
C8
F8
E8
FVT, NO.28 Near Device
C6
A6
C5
A5
C1
C3
E1
E3
C16
USBSS_CALRP
A16
USBSS_CALRN
A14
C14
C12
A12
D15
USB30_FTX_DRX_P2_C
B15
USB30_FTX_DRX_N2_C
E14
USB30_FRX_DTX_P2
F14
USB30_FRX_DTX_N2
F15
USB30_FTX_DRX_P1_C
G15
USB30_FTX_DRX_N1_C
H13
USB30_FRX_DTX_P1
G13
USB30_FRX_DTX_N1
J16
USB30_FTX_DRX_P0_C
H16
USB30_FTX_DRX_N0_C
J15
USB30_FRX_DTX_P0
K15
USB30_FRX_DTX_N0
1 2
H19
R144 10K_ 0402_5%R144 10K_0402_5%
1 2
G19
R147 10K_ 0402_5%R147 10K_0402_5%
G22
FCH_SIC
G21
FCH_SID
E22
H22
J22
EC_PWM2
H21
K21
K22
F22
F24
E24
B23
C24
F18
D
1 2
R127 11.8K_0 402_1%R127 11.8K_0 402_1%
USB30_P12 34
USB30_N12 34
USB30_P11 34
USB30_N11 34
USB30_P10 34
USB30_N10 34
USB20_P8 32
USB20_N8 32
USB20_P7 35
USB20_N7 35
USB20_P6 26
USB20_N6 26
USB20_P5 33
USB20_N5 33
USB30_N12
USB30_N11
USB30_N10
USB20_N6
USB20_N0
R230 300 _0402_5%@R230 300_0402_5 %@
R231 300 _0402_5%@R231 300_0402_5 %@
R232 300 _0402_5%@R232 300_0402_5 %@
R233 300 _0402_5%@R233 300_0402_5 %@
R234 300 _0402_5%@R234 300_0402_5 %@
1 2
R132 1K_0 402_1%R132 1K_0402_1%
1 2
R133 1K_0 402_1%R133 1K_0402_1%
C212 .1U_0402_16V7KC212 .1U_0402_16V7K
C213 .1U_0402_16V7KC213 .1U_0402_16V7K
C218 .1U_0402_16V7KC218 .1U_0402_16V7K
C219 .1U_0402_16V7KC219 .1U_0402_16V7K
C220 .1U_0402_16V7KC220 .1U_0402_16V7K
C221 .1U_0402_16V7KC221 .1U_0402_16V7K
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
E
LP3
LP2
LP1
BT
FP
CMOS
WLAN
1 2
1 2
1 2
1 2
1 2
USB20_P0 35
USB20_N0 35
1 2
1 2
1 2
1 2
1 2
1 2
RP1
FCH_SIC 7
FCH_SID 7
EC_PWM2 1 6
Compal Electronics, Inc.
Compal Electronics, Inc.
Compal Electronics, Inc.
FCH SATA/SPI/VGA/HWM/SD
FCH SATA/SPI/VGA/HWM/SD
FCH SATA/SPI/VGA/HWM/SD
1 2
C222 10P_0402_50V8J@C222 10P_0 402_50V8J@
1 2
C223 10P_0402_50V8J@C223 10P_0 402_50V8J@
1 2
C224 10P_0402_50V8J@C224 10P_0 402_50V8J@
1 2
C225 10P_0402_50V8J@C225 10P_0 402_50V8J@
1 2
C226 10P_0402_50V8J@C226 10P_0 402_50V8J@
+FCH_VDD_11_SSUSB_S
USB30_FTX_DRX_P2 34
USB30_FTX_DRX_N2 34
USB30_FRX_DTX_P2 34
USB30_FRX_DTX_N2 34
USB30_FTX_DRX_P1 34
USB30_FTX_DRX_N1 34
USB30_FRX_DTX_P1 34
USB30_FRX_DTX_N1 34
USB30_FTX_DRX_P0 34
USB30_FTX_DRX_N0 34
USB30_FRX_DTX_P0 34
USB30_FRX_DTX_N0 34
strap pin
LA-8121P
LA-8121P
LA-8121P
E
LP3
LP2
LP1
0.4
0.4
14 50Mon day, January 16, 2012
14 50Mon day, January 16, 2012
14 50Mon day, January 16, 2012
0.4
A
B
C
D
E
+3VS
+FCH_VDDAN_33_DAC
1 1
+3VS
+3VS +FCH_VDDAN_33_DAC
FBMA-L11-201209-221LMA30T_0 805
FBMA-L11-201209-221LMA30T_0 805
2 2
SIT, NO.52
+3V
SIT, NO.53
+3V
3 3
+3VS
+3VS
4 4
L2
L2
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm
1 2
R168 0_0402_5%R168 0_0402_5%
L3
L3
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
@
@
L5
L5
1 2
30mil
220 ohm
L7
L7
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm
L11
L11
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm
L14
L14
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm
L15
L15
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm
A
+VDDPL_33_SYS
C154
2.2U_0402_6.3V6M
C154
2.2U_0402_6.3V6M
1
2
+VDDPL_33_MLDAC
.1U_0402_16V7K
.1U_0402_16V7K
C153
C153
1
2
C175
2.2U_0603_6.3V6K
C175
2.2U_0603_6.3V6K
C176
C176
1
2
+VDDPL_33_SSUSB_S
C185
2.2U_0402_6.3V6M
C185
2.2U_0402_6.3V6M
1
2
+VDDPL_33_USB_S
C193
2.2U_0402_6.3V6M
C193
2.2U_0402_6.3V6M
1
2
+VDDPL_33_PCIE
+VDDPL_33_SATA
C147
.1U_0402_16V7K
C147
.1U_0402_16V7K
1
2
.1U_0402_16V7K
.1U_0402_16V7K
C158
C158
1
2
LDO_CAP: Internally generated 1.8V
supply for the RGB outputs
+1.1VS
0.1U_0402_16V4Z
0.1U_0402_16V4Z
1
2
+3VS
+VDDPL_33_MLDAC
L4
L4
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm/2A
R171 0_0603_5%R171 0_0603_5%
SIT, NO.51
C186
.1U_0402_16V7K
C186
.1U_0402_16V7K
1
2
C194
.1U_0402_16V7K
C194
.1U_0402_16V7K
1
2
C200
2.2U_0402_6.3V6M
C200
2.2U_0402_6.3V6M
1
2
C207
2.2U_0402_6.3V6M
C207
2.2U_0402_6.3V6M
1
2
SIT, NO.49
+1.1V
+3V
FBMA-L11-201209-221LMA30T_0 805
FBMA-L11-201209-221LMA30T_0 805
SIT, NO.47
+1.1V
SIT, NO.48
+1.1V
FBMA-L11-201209-221LMA30T_0 805
FBMA-L11-201209-221LMA30T_0 805
1 2
220 ohm/2A
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
+FCH_VDD_11_SSUSB_S
40mils
L16
L16
42 ohm/4A
L6
L6
L10
L10
220 ohm
L12
L12
220 ohm
12
1 2
+VDDPL_33_SYS
1 2
R173 0_0402_5%R173 0_0402_5%
1 2
R169 0_0402_5%R169 0_0402_5%
+VDDPL_33_SSUSB_S
+VDDPL_33_USB_S
+VDDPL_33_PCIE
+VDDPL_33_SATA
1 2
R176 0_0 402_5%R176 0_0402_5%
1 2
R177 0_0 603_5%R177 0_0603_5%
C180
C180
1
2
C188
C188
1
2
C195
C195
1
2
1 2
R183 0_0603_5%R183 0_0603_5%
1 2
R185 0_0603_5%R185 0_0603_5%
B
22U_0603_6.3V6M
22U_0603_6.3V6M
C151
C151
C146
C146
1
1
2
2
C168
C168
1
2
R180 0_0402_5%R180 0_0402_5%
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
10U_0603_6.3V6M
C181
C181
1
2
C189
.1U_0402_16V7K
C189
.1U_0402_16V7K
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1
2
C196
.1U_0402_16V7K
C196
.1U_0402_16V7K
10U_0603_6.3V6M
10U_0603_6.3V6M
1
2
C201
C201
1
2
C208
C208
1
2
+VDDIO_33_PCIGP
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
C152
C152
C157
C157
1
1
2
2
+VDDPL_33_DAC
+VDDPL_33_ML
+FCH_VDDAN_33_DAC
@
@
1 2
C164 2.2U_0603 _6.3V6K
C164 2.2U_0603 _6.3V6K
+VDDPL_11_DAC
+VDDAN_11_ML
4.7U_0402_6.3V6M
4.7U_0402_6.3V6M
C170
.1U_0402_16V7K
C170
.1U_0402_16V7K
C169
.1U_0402_16V7K
C169
.1U_0402_16V7K
1
1
2
2
1 2
+VDDAN_33_USB
C182
C182
1
2
+VDDAN_11_USB_S
C190
1
@
2
+VDDCR_11V_USB
C197
C197
1
2
+VDDAN_11_SSUSB
1U_0402_6.3V6K
1U_0402_6.3V6K
+VDDCR_11_SSUSB
10U_0603_6.3V6M
10U_0603_6.3V6M
C184
C184
C183
1U_0402_6.3V6K
C183
1U_0402_6.3V6K
1U_0402_6.3V6K
1U_0402_6.3V6K
.1U_0402_16V7K@C190
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1
1
2
2
C203
.1U_0402_16V7K
C203
.1U_0402_16V7K
C202
.1U_0402_16V7K
C202
.1U_0402_16V7K
1
1
2
2
C210
C210
C209
1U_0402_6.3V6K
C209
1U_0402_6.3V6K
1
1
2
2
U2C
U2C
HUDSON-2
102mA
AB17
VDDIO_33_PCIGP_1
AB18
VDDIO_33_PCIGP_2
AE9
VDDIO_33_PCIGP_3
AD10
VDDIO_33_PCIGP_4
AG7
VDDIO_33_PCIGP_5
AC13
VDDIO_33_PCIGP_6
AB12
VDDIO_33_PCIGP_7
AB13
VDDIO_33_PCIGP_8
AB14
VDDIO_33_PCIGP_9
AB16
VDDIO_33_PCIGP_10
47mA
H24
VDDPL_33_SYS
20mA
V22
VDDPL_33_DAC
12mA
U22
VDDPL_33_ML
30mA
T22
VDDAN_33_DAC
11mA
L18
VDDPL_33_SSUSB_S
14mA
D7
VDDPL_33_USB_S
11mA
AH29
VDDPL_33_PCIE
12mA
AG28
VDDPL_33_SATA
M31
LDO_CAP
7mA
V21
VDDPL_11_DAC
226mA
Y22
VDDAN_11_ML_1
V23
VDDAN_11_ML_2
V24
VDDAN_11_ML_3
V25
VDDAN_11_ML_4
AB10
VDDIO_33_GBE_S
AB11
VDDCR_11_GBE_S_1
AA11
VDDCR_11_GBE_S_2
AA9
VDDIO_GBE_S_1
AA10
VDDIO_GBE_S_2
470mA
G7
VDDAN_33_USB_S_1
H8
.1U_0402_16V7K
.1U_0402_16V7K
VDDAN_33_USB_S_2
J8
VDDAN_33_USB_S_3
K8
VDDAN_33_USB_S_4
K9
VDDAN_33_USB_S_5
M9
VDDAN_33_USB_S_6
M10
VDDAN_33_USB_S_7
N9
VDDAN_33_USB_S_8
N10
VDDAN_33_USB_S_9
M12
VDDAN_33_USB_S_10
N12
VDDAN_33_USB_S_11
M11
VDDAN_33_USB_S_12
140mA
U12
VDDAN_11_USB_S_1
U13
VDDAN_11_USB_S_2
42mA
T12
VDDCR_11_USB_S_1
T13
VDDCR_11_USB_S_2
282mA
P16
VDDAN_11_SSUSB_S_1
M14
VDDAN_11_SSUSB_S_2
N14
VDDAN_11_SSUSB_S_3
P13
VDDAN_11_SSUSB_S_4
P14
VDDAN_11_SSUSB_S_5
424mA
N16
VDDCR_11_SSUSB_S_1
N17
VDDCR_11_SSUSB_S_2
P17
VDDCR_11_SSUSB_S_3
M17
VDDCR_11_SSUSB_S_4
21807-A13-HUDSON-M3_FCBGA656
21807-A13-HUDSON-M3_FCBGA656
C211
.1U_0402_16V7K
C211
.1U_0402_16V7K
.1U_0402_16V7K
.1U_0402_16V7K
1
2
Security Classification
Security Classification
Security Classification
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
HUDSON-2
PCI/GPIO I/O
PCI/GPIO I/O
USB SS USB MAIN LINKGBE LAN
USB SS USB MAIN LINKGBE LAN
POWER
POWER
C
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
CORE S0
CORE S0
VDDCR_11_9
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O
CLKGEN I/OPCI EXPRESSSERIAL ATA3.3V_S5 I/O
VDDAN_11_CLK_7
VDDAN_11_CLK_8
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
VDDAN_11_SATA_8
VDDAN_11_SATA_9
VDDAN_11_SATA_10
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
VDDXL_33_S
VDDCR_11_S_1
VDDCR_11_S_2
VDDPL_11_SYS_S
VDDAN_33_HWM_S
VDDIO_AZ_S
2011/04/18 2015/07/08
2011/04/18 2015/07/08
2011/04/18 2015/07/08
1007mA
C155
.1U_0402_16V7K
C155
T14
T17
T20
U16
U18
V14
V17
V20
Y17
340mA
H26
J25
K24
L22
M22
N21
N22
P22
1088mA
AB24
Y21
AE25
AD24
AB23
AA22
AF26
AG27
1337mA
AA21
Y20
AB21
AB22
AC22
AC21
AA20
AA18
AB20
AC19
59mA
N18
L19
M18
V12
V13
Y12
Y13
W11
5mA
G24
187mA
N20
M20
70mA
J24
12mA
M8
26mA
AA4
Compal Secret Data
Compal Secret Data
Compal Secret Data
.1U_0402_16V7K
1
2
C159
.1U_0402_16V7K
C159
.1U_0402_16V7K
1
2
C165
.1U_0402_16V7K
C165
.1U_0402_16V7K
1
2
C171
.1U_0402_16V7K
C171
.1U_0402_16V7K
1
2
C177
1U_0402_6.3V6K
C177
1U_0402_6.3V6K
1
2
C187
2.2U_0402_6.3V6M
C187
2.2U_0402_6.3V6M
1
2
C191
1U_0402_6.3V6K
C191
1U_0402_6.3V6K
1
2
C198
2.2U_0402_6.3V6M
C198
2.2U_0402_6.3V6M
1
2
C204
2.2U_0402_6.3V6M
C204
2.2U_0402_6.3V6M
1
2
Deciphered Date
Deciphered Date
Deciphered Date
+VCC_VDDCR_11
C149
C149
C148
.1U_0402_16V7K
C148
.1U_0402_16V7K
1
1
2
2
+1.1VS_CKVDD
C160
.1U_0402_16V7K
C160
.1U_0402_16V7K
C161
C161
1
1
2
2
+VDDAN_11_PCIE
C166
1U_0402_6.3V6K
C166
1U_0402_6.3V6K
C167
C167
1
1
2
2
C172
1U_0402_6.3V6K
C172
1U_0402_6.3V6K
C173
C173
1
1
2
2
+VDDIO_33_S
C178
1U_0402_6.3V6K
C178
1U_0402_6.3V6K
C179
C179
1
1
2
2
+VDDXL_3.3V
+VDDCR_1.1V
C192
1U_0402_6.3V6K
C192
1U_0402_6.3V6K
1
2
+VDDPL_11_SYS_S
.1U_0402_16V7K
.1U_0402_16V7K
C199
C199
1
2
+VDDAN_33_HWM
C205
.1U_0402_16V7K
C205
.1U_0402_16V7K
1
2
+VDDIO_AZ
C206 2.2U_0402_6.3V6MC206 2.2U_0402_6.3V6M
D
C150
C150
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
C162
C162
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
+VDDAN_11_PCIE
22U_0603_6.3V6M
22U_0603_6.3V6M
C174
C174
1U_0402_6.3V6K
1U_0402_6.3V6K
1
2
2.2U_0402_6.3V6M
2.2U_0402_6.3V6M
1 2
1U_0402_6.3V6K
1U_0402_6.3V6K
C156
10U_0603_6.3V6M
C156
10U_0603_6.3V6M
1
2
+1.1VS_CKVDD
1U_0402_6.3V6K
1U_0402_6.3V6K
C163
22U_0603_6.3V6M
C163
22U_0603_6.3V6M
1
2
+AVDD_SATA
22U_0603_6.3V6M
22U_0603_6.3V6M
1 2
R179 0_0402_5%R179 0_0402_5%
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm
1 2
R181 0_0603_5%R181 0_0603_5%
1 2
MBK1608221YZF_2P
MBK1608221YZF_2P
220 ohm
1 2
R182 0_0402_5%R182 0_0402_5%
1 2
R184 0_0402_5%R184 0_0402_5%
1 2
R170 0_0805_5%R170 0_0805_5%
42ohm @ 100MHz
1 2
R172 0_0603_5%R172 0_0603_5%
42ohm @ 100MHz
R175 0_0805_5%R175 0_0805_5%
42ohm @ 100MHz
R178 0_0805_5%R178 0_0805_5%
L8
L8
L13
L13
+1.1VS
+1.1VS
1 2
1 2
+1.1VS
+1.1VS
SIT, NO.54
+3V_FCH
SIT, NO.56
+3V
+VDDXL_3.3V
Tie to +3.3V_S5 rail if USB3 Wake
is supported; otherwise, tie to
+3.3V_S0 rail.
Hudson-2 designs: Tie to +3.3V_S0
rail.
+1.1VALW
SIT, NO.50
VDDPL_11_SYS_S should be
+1.1V
tied to +1.1V_S5 rail if USB 3.0 Wake is
supported; otherwise, it can be tied to
+1.1V_S0 rail.
SIT, NO.55
+3V_FCH
AMD reply:
VDDAN_33_HWM_S: Please connect
it to +3.3V_S5 directly if HWM is not used.
VDDIO_AZ_S
+3VS
Wake on Ring supported: Tie to +3.3/
1.5V_S5 rail, and treat like a 3.3/1.1V_S5 rail.
Wake on Ring not supported: Tie to +3.3/
1.5V_S0 rail, and treat like a 3.3/1.1V S0 rail.
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
Date: Sheet of
Date: Sheet of
Date: Sheet of
Compal Electronics, Inc.
FCH PWR
FCH PWR
FCH PWR
LA-8121P
LA-8121P
LA-8121P
15 50Mon day, January 16, 2012
15 50Mon day, January 16, 2012
15 50Mon day, January 16, 2012
E
0.4
0.4
0.4
5
4
3
2
1
U2E
U2E
HUDSON-2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSAN_HWM
VSSXL
VSSPL_SYS
HUDSON-2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
GROUND
GROUND
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSPL_DAC
VSSAN_DAC
VSSANQ_DAC
VSSIO_DAC
EFUSE
T25
T27
U6
U14
U17
U20
U21
U30
U32
V11
V16
V18
W4
W6
W25
W28
Y14
Y16
Y18
AA6
AA12
AA13
AA14
AA16
AA17
AA25
AA28
AA30
AA32
AB25
AC6
AC18
AC28
AD27
AE6
AE15
AE21
AE28
AF8
AF12
AF16
AF33
AG30
AG32
AH5
AH11
AH18
AH19
AH21
AH23
AH25
AH27
AJ18
AJ28
AJ29
AK21
AK25
AL18
AM21
AM25
AN1
AN18
AN28
AN33
T21
L28
K33
N28
R6
A3
A33
B7
B13
D D
C C
B B
D13
E12
E16
E29
F11
F13
F16
F17
F19
F23
F25
F29
G16
G32
H12
H15
H29
K16
K27
K28
M13
M16
M21
M25
N11
N13
N23
N24
P12
P18
P20
P21
P31
P33
R11
R25
R28
K25
H25
J10
J13
J28
J32
L12
L13
L15
L16
L21
T11
T16
T18
D9
E5
F7
F9
G6
J6
J9
K7
L6
N6
R4
N8
STRAP PINS
PCI_CLK1
ALLOW
PULL
PCIE GEN2
HIGH
DEFAULT
FORCE
PULL
PCIE GEN1
LOW
PCI_CLK112
PCI_CLK312
PCI_CLK412
CLK_PCI_EC12,31
LPC_CLK112
EC_PWM214
RTC_CLK12,31
PCI_CLK3
USE
DEBUG
STRAPS
IGNORE
DEBUG
STRAP
DEFAULT
12
12
@
PCI_CLK4 CLK_PCI_EC
NON_FUSION
CLOCK MODE
FUSION
CLOCK
MODE
DEFAULT
R187 10K_0402_5%@R187 10K_0402_5%
R186 10K_0402_5%R186 10K_0402_5%
12
@
R198 10K_0402_5%@R198 10K_0402_5%
12
R188 10K_0402_5%@R188 10K_0402_5%
12
@
R200 10K_0402_5%R200 10K_0402_5%
R199 10K_0402_5%R199 10K_0402_5%
12
EC
ENABLED
EC
DISABLED
DEFAULT
R189 10K_0402_5%@R189 10K_0402_5%
12
@
R201 10K_0402_5%R201 10K_0402_5%
12
12
12
@
CLKGEN
ENABLED
DEFAULT
CLKGEN
DISABLE
R190 10K_0402_5%R190 10K_0402_5%
@
R202 10K_0402_5%@R202 10K_0402_5%
EC_PWM2
LPC ROM
SPI ROM
DEFAULT
+3V_FCH+3V_FCH+3V_FCH+3V_FCH+3VS+3VS+3VS
R192 10K_0402_5%R192 10K_0402_5%
R191 10K_0402_5%@R191 10K_0402_5%
12
12
R204 2.2K_0402_5%@R204 2.2K_0402_5%
R203 2.2K_0402_5%R203 2.2K_0402_5%
12
12
@
RTC_CLKLPC_CLK1
S5 PLUS
MODE
DISABLED
DEFAULT
S5 PLUS
MODE
ENABLED
DEBUG STRAPS
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PCI_AD27 PCI_AD26
PULL
HIGH
PULL
LOW
PCI_AD2712
PCI_AD2612
PCI_AD2512
PCI_AD2412
PCI_AD2312
USE PCI
PLL
DEFAULT
BYPASS
PCI PLL
DISABLE
ILA
AUTORUN
DEFAULT
ENABLE
ILA
AUTORUN
R193 2.2K_0402_5%@R193 2.2K_0402_5%
12
@
PCI_AD25 PCI_AD24
USE FC
PLL
BYPASS
FC PLL
R194 2.2K_0402_5%@R194 2.2K_0402_5%
12
@
@
R195 2.2K_0402_5%@R195 2.2K_0402_5%
12
USE DEFAULT
PCIE STRAPS
DEFAULT
USE EEPROM
PCIE STRAPS
12
@
R196 2.2K_0402_5%@R196 2.2K_0402_5%
PCI_AD23
DISABLE PCI
MEM BOOT
DEFAULTDEFAULT
ENABLE PCI
MEM BOOT
12
@
R197 2.2K_0402_5%@R197 2.2K_0402_5%
21807-A13-HUDSON-M3_FCBGA656
A A
21807-A13-HUDSON-M3_FCBGA656
5
Security Classification
Security Classification
Security Classification
2011/04/18 2015/07/08
2011/04/18 2015/07/08
Issued Date
Issued Date
Issued Date
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
THIS SHEET OF ENGINEERI NG DRAWING IS THE PROPRIETARY PROPERTY OF COMP AL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
AND TRADE SECRET INFORMAT ION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISI ON OF R&D
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S
DEPARTMENT EXCEPT AS A UTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION IT CONTAIN S
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
4
MAY BE USED BY OR DISCLOSED T O ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONS ENT OF COMPAL ELECTRONICS, INC.
2011/04/18 2015/07/08
3
Compal Secret Data
Compal Secret Data
Compal Secret Data
Deciphered Date
Deciphered Date
Deciphered Date
Compal Electronics, Inc.
Compal Electronics, Inc.
Title
Title
Title
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
B
B
B
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
Compal Electronics, Inc.
FCH-VSS/Strap
FCH-VSS/Strap
FCH-VSS/Strap
LA-8121P
LA-8121P
LA-8121P
16 50Monday, January 16, 2012
16 50Monday, January 16, 2012
16 50Monday, January 16, 2012
1
0.4
0.4
0.4
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