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LA-7553P QBL70 K73TA
Schematic
53 pgs1.36 Mb0

Compal LA-7553P QBL70 K73TA, K73T, K73TA, K73TK Schematic

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Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
Cover Page
B
1 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
APU Llano / Hudson M3 / Whistler
K73TA Schematics Document
LA-7553P REV: 0.2
Compal Confidential
2011-03-08
AMD Sabine
DIS only
ZZZ
PCB
Part Number = DAZ0K400100
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A
B
B
C
C
D
D
E
E
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2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
Block Diagrams
B
2 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
LPC BUS
Compal Confidential
USB2
3.3V 48MHz
HD Audio
FCH
Page 13~17
3.3V 24.576MHz/48Mhz
Model Name : QBL70
S-ATA
page 29
port 0
CMOS
Camera
Port 1
USB
ODD
Conn.
page 29
port 1
page 30 page 27
uFCBGA-656
Sabine
Gen2
AMD FS1 APU
uPGA-722 Package
Page 6~10
Llano
Hudson-M2/M3
Dual Channel
BANK 0, 1, 2, 3
204pin DDRIII-SO-DIMM X2
1.5V DDRIII 800~1333MHz
Memory BUS(DDR3)
Page 11,12
page 28
Gen2GFX x 8
VRAM 512M/1G/2G
64M16/128M16 x 8
DDR3
page 23, 24
ATI
uFCBGA-962
Vancuver Whistler
page 19
Thermal Sensor
ADM1032
GFX x 4
APU HDMI
(UMA / Muxless)
HDMI Conn.
page 27
LVDS Conn.
Reserve eDP
DP x1 (DP0 TXP/N0)
LVDS
Travis LVDS
Translator
page 26
DP x 4
(DP1 TXP/N 0~4)
UMI
FCH CRT (VGA DAC)
page 31
MINI Card 1
WLAN
page 35
GPP0
GPP0
RJ45
page 31
LAN(GbE)
RTL8111E
SATA HDD1
Conn.
page 35
Mini Card
(with BT)
P_GPP x 2
GEN1
CRT Conn.
page 27
Page 18~22
Touch Pad Int.KBD
page 32
page 37
page 37
ENE KB930
Port2 Port 3
page 33
USB2 x 2
(LS-7323P)
page 33
HDA Codec
ALC269
page 30
USB2
Port 0 Port 5
page 35
LED
RTC CKT.
page 13
DC/DC
Interface CKT.
page 38
Power Circuit
page 39~48
LS-7323P
Audio BD
page 36
LS-7325P
Power/B
page 33 page 32
EC BIOS (128K)
page 15
SYS BIOS (2M)
BIOS ROM
Card Reader
RTS5137
Port 4
page 34
SATA HDD2
port 2
page 29
page 36
LS-7324P
HDD/B
External board
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A A
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECT RONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSE NT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
CLOCK / DISPLAY DISTRIBUTION
Custom
3 51Friday, April 29, 2011
2010/08/04 2010/08/04
A_SODIMM
CPU FS1 SOCKET
FCH
Hudson-M2/M3
Internal CLK GEN
B_SODIMM
MEM_MA_CLK7_P/N
1066~1600MHz
1
066~1600MHz
MEM_MA_CLK1_P/N
M
EM_MB_CLK1_P/N
MEM_MB_CLK7_P/N
AMD
AMD
CLK_PEG_VGAP/N
100MHz
100MHz
32.768KHz 25MHz
APU_DISP_CLKP/N
100MHz
APU_CLKP/N
100MHz
ATI VGA
Whistler
AMD
LVDS CONN
APU
DP0
DP0_TXP/N[0:1]
DP0_AUXP/N
C
RTD2132
DP_IN
LVDS_OUT
APU_TXOUT[0:2]+/-
APU_TXOUT_CLK+/-
APU_TZOUT[0:2]+/-
APU_TZOUT_CLK+/-
APU_LVDS_CLK/DATA
R
TXOUT[0:2]+/-
TXCLK+/-
TZOUT[0:2]+/-
TZCLK+/-
I2CC_SCL/DA
VGA
CLOCK DISTRIBUTION
DISPLAY DISTRIBUTION
: LVDS PATH
HDMI CONNCRT CONN
PCIE_GFX[0:7]
PCIE_GFX[12:15]
C
C
PCIE_GFX[0:7]
LS
DP1
FCH
R
: APU HDMI PATH
GbE LAN
25MHz
WLAN
Mini PCI Socket
GPP_CLK
GPP0GPP1
DP0_AUX
LVDS Transtator
A
A
B
B
C
C
D
D
E
E
1 1
2 2
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4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
Notes List
B
4 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
BOM Config
FCH
SM Bus 1 address
DDR DIMM1
1101 000X b
DDR DIMM2
1101 001X b
FCH
SM Bus 0 address
Device Address Device Address
HEX
D0
D2
HEX
Device Address HEX
EC SM Bus1 address EC SM Bus2 address
Smart Battery
0001 011X b
16H
Device IDSEL# REQ#/GNT# Interrupts
External PCI Devices
+CPU_CORE_NB ON OFF OFFVoltage for On-die VGA of APU
+CPU_CORE
Voltage Rails
VIN
B+
+CPU_CORE_1 ON OFF OFF
S1 S3 S5
ON OFF
N/A N/A N/A
N/AN/AN/A
Power Plane Description
OFF
Adapter power supply (19V)
AC or battery power rail for power circuit.
Core voltage for CPU
Core voltage for CPU (0.7-1.2V)
+VGA_CORE OFFOFFON0.95-1.2V switched power rail
+0.75VS ONON OFF0.75V switched power rail for DDR terminator
+1.0VSG ON OFF OFF1.0V switched power rail for VGA
STATE
LOW
LOW
LOW
SIGNAL
Full ON
S1(Power On Suspend)
LOW
LOW LOW
LOW
S3 (Suspend to RAM)
S4 (Suspend to Disk)
S5 (Soft OFF) LOW
SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock
Vcc 3.3V +/- 5%
100K +/- 5%Ra/Rc/Re
Board ID
Rb / Rd / Rf V min
0
1
2
3
0
8.2K +/- 5%
0 V
0.216 V 0.250 V 0.289 V
0.436 V
0.712 V
0.503 V
0.819 V
0.538 V
0.875 V
AD_BID
V typ
AD_BID
V
AD_BID
max
18K +/- 5%
3
3K +/- 5%
56K +/- 5%
100K +/- 5%
200K +/- 5%
3.300 V
0 V 0 V
4
5
6
7 NC
1.036 V
1.453 V 1.650 V 1.759 V
1.935 V
2.500 V
2.200 V
3.300 V
2.341 V
1.185 V 1.264 V
Board ID / SKU ID Table for AD channel
ON
ON
ON
ON
ON
ON
ON ON
ON
ON
ON
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
LOW
LOW
LOW
HIGH HIGH HIGH HIGH
HIGHHIGHHIGH
HIGH
HIGH
HIGH
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
+RTCVCC
+2.5VS
+5VS
+3VS
+5VALW
+3VALW
+VSB ON ON*
ONON
ON
ON
ON ON*
+3V_LAN ON ON ON
ON
OFF
OFF
OFF
ON
OFFON
ON
ON
OFF
ON*
OFF
ON
RTC power
2.5V for CPU_VDDA
3.3V always on power rail
3.3V switched power rail
5V always on power rail
5V switched power rail
VSB always on power rail
3.3V power rail for LAN
+1.8VSG OFFON OFF1.8V switched power rail
+1.5VS
+1.5V ON
OFF
OFF
ON OFF
ON
1.5V switched power rail
1.5V power rail for CPU VDDIO and DDR
+1.1VS
+1.2VS ON OFF OFF
ON OFF OFF1.1V switched power rail for FCH
1.2V switched power rail for APU
+1.1ALW 1.1V switched power rail for FCH ON ON*ON
2
3
4
5
6
7
PCB Revision
BOARD ID Table
Board ID
0
1
Device Address HEX
ADI ADM1032 (VGA)
1001 101X b
9AH
x = 1 is read cmd, x= 0 is writee cmd.
NA
NA
NA
P5WS5
P7YE5
P5WH5
P7YS5
NA
TranslatorTL@
VGA@ Use VGA (Mux)
128@ Use VRAM channel A&B
VRAM ID TableX76@
M2@ Use Hudson-M2
M3@ Use Hudson-M3
USB30@ USB30 on M/B
USB20@ USB20 on M/B
BTO Option Table
BTO ItemBOM Structure
U25
FCH M3
Part Number = SA000043ID0
M3@
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAW ING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTR ONICS, INC. AND CONTAINS CONF IDENTIAL
AND TRADE SECRET INFORMATI ON. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT D IVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY C OMPAL ELECTRONICS, INC. NEITHER T HIS SHEET NOR THE INFORMATION I T CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THI RD PARTY WITHOUT PRIOR WRIT TEN CONSENT OF COMPAL ELECTRONICS, INC .
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
POWER DELIVERY CHART
Custom
5 51Friday, April 29, 2011
2010/08/04 2010/08/04
EC
ENE KB930
+1.5V
+0.75VS
+1.5VS 500mA
+3.3VS 1A+3.3VS 300mA
+3.3VALW 330mA
+3.3VS 3mA
+3.3VALW 30mA
SATA
HDD*2
ODD*1
+5V 45mA
+3.3VS 25mA
+3.3VALW 201mA
+5V 3A
+3.3V
BATTERY
12.6V
PU3
CHARGER
ISL6251AHAZ-T
AC ADAPTOR
19V 90W
LAN
Atheros AR8151
RAM DDRIII SODIMMX2
VDD_MEM 4A
FAN Control
APL5607
+5VS 500mA
Audio Codec
ALC271X
RTC
Bettary
VTT_MEM 0.5A
Realtek
RTS5138
Mini Card*2
BATT+
VIN
VDD CORE 54A
VDDNB 27.5A
VDDIO 4.6A
VDDR 6.7A
VDDA 500mA
AMD APU FS1
0.7~1.475V
+2.5VS
+1.5V
+1.2VS
FCH AMD Hudson M2/M3
VDDIO_33_PCIGP: 131 mA
VDDPL_33_SYS: 47 mA
VDDPL_33_DAC: 20 mA
VDDPL_33_ML: 20 mA
VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
VDDPL_33_SATA: 93 mA
VDDIO_AZ_S: 26 mA
VDDPL_33_SSUSB_S: 20 mA
VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
VDDAN_33_HWM_S: 12 mA
VDDIO_33_GBE_S
VDDCR_11_GBE_S
VDDIO_GBE_S
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
VDDCR_11: 1007 mA
VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA
VDDAN_11_USB_S: 140 mA
VDDCR_11_USB_S: 197 mA
VDDAN_11_SSUSB_S: 282 mA
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
VDDPL_11_SYS: 70 mA
+1.1VALW
+1.1VS
+3VALW
+3VS
GND
VDDBT_RTC_GRTC BAT
VGA ATI
W
histler/Seymour/Granville
PLL_PVDD: 75 mA
TSVDD: 20 mA
AVDD: 70 mA
VDD1DI: 100 mA
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
VDD_CT: 110 mA
VDDR4: 170 mA
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
VDDCI 4.6A
DPLL_VDDC: 125 mA
SPV10: 120 mA
PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
VDDC 47A
A2VDD: 130 mA
VDDR3: 60 mA
+1.0VSG
+3VSG
0.85~1.1V
+1.5VSG
+1.8VSG
B+
+CPU_CORE
+CPU_CORE_NB
+5VALW
+3VALW
+USB_VCCA
+USB_VCCB
U22/U23
TPA2301DRG4
+CPU_CORE
+CPU_CORE_NB
0.9~1.0V
VDDR1: 3400 mA
VRAM 512/1GB/2GB
64M / 128Mx16 * 4 / 8
+1.5VSG 2.4 A
0.7~1.475V
+1.8VSG
+1.0VSG
PU13
ISL6267HRZ-T
+1.5V
PU6
G5603RU1U
PU10
G5603RU1U
+1.2VS
+1.2VS
+1.5V
PU11
TPS51218DSCR
+VGA_CORE
+VGA_CORE
PU12
G5603RU1U
+VDDCI
+VDDCI
+1.0VSG
PU8
G9731G11U
PU7
SY8033BDBC
+1.8VSG
PU9
APL5508
+2.5VS
+2.5VS
PU4
RT8205EGQW
+1.1VALW
PU5
G5603RU1U
U34
AO4430L
+1.5VSG
+1.5VSG
PU2
UP7711U8
+0.75VS
+0.75VS
U34
AO4430L
+1.1VS
+1.1VS
+1.1VALW
U33
SI4800
+3VALW
+3VS
Q61
SI2301
+3VSG
+3VSG
+3.3 350mA
B+ 300mA
LCD panel
15.6"
+INVPWR_B+
U33
SI4800
+5V
Dual+1
2.5A
USB X3
Q57
SI2301
+1.5VS
+3VALW
+3VS
+5VS
+5VALW
+3VS
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
P_ZVDDP
UMI_FTX_MRX_P0
UMI_FTX_MRX_N0
UMI_FTX_MRX_P1
UMI_FTX_MRX_N1
UMI_FTX_MRX_P2
UMI_FTX_MRX_N2
UMI_FTX_MRX_P3
UMI_FTX_MRX_N3
PCIE_FTX_DRX_P0
PCIE_FTX_DRX_N0
PCIE_FTX_GRX_P0
PCIE_FTX_GRX_N0
PCIE_FTX_GRX_P1
PCIE_FTX_GRX_N1
PCIE_FTX_GRX_P2
PCIE_FTX_GRX_N2
PCIE_FTX_GRX_P3
PCIE_FTX_GRX_N3
PCIE_FTX_C_GRX_P0
PCIE_FTX_C_GRX_N0
PCIE_FTX_C_GRX_P1
PCIE_FTX_C_GRX_N1
PCIE_FTX_C_GRX_P2
PCIE_FTX_C_GRX_N2
PCIE_FTX_C_GRX_P3
PCIE_FTX_C_GRX_N3
PCIE_FTX_GRX_P4
PCIE_FTX_GRX_N4
PCIE_FTX_GRX_P5
PCIE_FTX_GRX_N5
PCIE_FTX_GRX_P6
PCIE_FTX_GRX_N6
PCIE_FTX_GRX_P7
PCIE_FTX_GRX_N7
PCIE_FTX_C_GRX_P4
PCIE_FTX_C_GRX_N4
PCIE_FTX_C_GRX_P5
PCIE_FTX_C_GRX_N5
PCIE_FTX_C_GRX_P6
PCIE_FTX_C_GRX_N6
PCIE_FTX_C_GRX_P7
PCIE_FTX_C_GRX_N7
PCIE_FTX_GRX_P12
PCIE_FTX_GRX_N12
PCIE_FTX_GRX_P13
PCIE_FTX_GRX_N13
PCIE_FTX_GRX_P14
PCIE_FTX_GRX_N14
PCIE_FTX_GRX_P15
PCIE_FTX_GRX_N15
PCIE_GTX_C_FRX_P0
PCIE_GTX_C_FRX_N0
PCIE_GTX_C_FRX_P1
PCIE_GTX_C_FRX_N1
PCIE_GTX_C_FRX_P2
PCIE_GTX_C_FRX_N2
PCIE_GTX_C_FRX_P3
PCIE_GTX_C_FRX_N3
PCIE_GTX_C_FRX_P4
PCIE_GTX_C_FRX_N4
PCIE_GTX_C_FRX_P5
PCIE_GTX_C_FRX_N5
PCIE_GTX_C_FRX_P6
PCIE_GTX_C_FRX_N6
PCIE_GTX_C_FRX_P7
PCIE_GTX_C_FRX_N7
APU_SID
APU_SIC
EC_SMB_DA
EC_SMB_CK
P_ZVSS
UMI_MTX_C_FRX_P013
UMI_MTX_C_FRX_N013
UMI_MTX_C_FRX_P113
UMI_MTX_C_FRX_N113
UMI_MTX_C_FRX_P213
UMI_MTX_C_FRX_N213
UMI_MTX_C_FRX_P313
UMI_MTX_C_FRX_N313
PCIE_FTX_C_DRX_P0 31
PCIE_FTX_C_DRX_N0 31
UMI_FTX_C_MRX_P0 13
UMI_FTX_C_MRX_N0 13
UMI_FTX_C_MRX_P1 13
UMI_FTX_C_MRX_N1 13
UMI_FTX_C_MRX_P2 13
UMI_FTX_C_MRX_N2 13
UMI_FTX_C_MRX_P3 13
UMI_FTX_C_MRX_N3 13
PCIE_FTX_C_GRX_P[0..7] 18
PCIE_FTX_C_GRX_N[0..7] 18PCIE_GTX_C_FRX_N[0..7]18
PCIE_GTX_C_FRX_P[0..7]18
PCIE_FTX_GRX_P[12..15] 28
PCIE_FTX_GRX_N[12..15] 28
EC_SMB_DA2 19,32
EC_SMB_CK2 19,32
APU_SID8,14
APU_SIC8,14
PCIE_DTX_C_FRX_P031
PCIE_DTX_C_FRX_N031
+1.2VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
AMD FS1 PCIE / UMI / TSI
Custom
6 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
GLAN
Power Sequence of APU
+1.5V
+2.5VS
+1.5VS
+CPU_CORE
+CPU_CORE_NB
+1.2VS
Group A
Group B
APU To HDMI
CPU TSI interface level shift
BSH111, the Vgs is:
min = 0.4V
Max = 1.3V
To EC
For UMA Mux.
To HDMI
2
1
0
CK
R1802 196_0402_1%
1 2
C920 0.1U_ 0402_16V7K
1 2
C921 0.1U_ 0402_16V7K
1 2
C950 0.1U_0402_16V7K
1 2
C923 0.1U_ 0402_16V7K
1 2
R1801 0_0402_5%
1 2
C956 0.1U_0402_16V7K
1 2
C958 0.1U_0402_16V7K
1 2
C961 0.1U_0402_16V7K
1 2
C962 0.1U_0402_16V7K
1 2
C932 0.1U_ 0402_16V7K
1 2
C926 0.1U_ 0402_16V7K
1 2
C918 0.1U_ 0402_16V7K
1 2
C930 0.1U_ 0402_16V7K
1 2
C922 0.1U_ 0402_16V7K
1 2
C963 0.1U_0402_16V7K
1 2
C925 0.1U_ 0402_16V7K
1 2
C928 0.1U_ 0402_16V7K
1 2
C960 0.1U_0402_16V7K
1 2
R1798
31.6K_0402_1%
1 2
G
D
S
Q9
BSH111 1N_SOT23-3
2
13
C957 0.1U_0402_16V7K
1 2
C959 0.1U_0402_16V7K
1 2
C919 0.1U_ 0402_16V7K
1 2
C935 0.1U_0402_16V4Z
1 2
C951 0.1U_0402_16V7K
1 2
R1799
30K_0402_1%
1 2
R1803 196_0402_1%
1 2
G
D
S
Q10
BSH111 1N_SOT23-3
2
13
C917 0.1U_ 0402_16V7K
1 2
R1800 0_0402_5%
1 2
C931 0.1U_ 0402_16V7K
1 2
C929 0.1U_ 0402_16V7K
1 2
GPPUMI-LINK GRAPHICS
PCI EXPRESS
JCPU1A
AMD_TOPEDO_FS-1
CONN@
P_GFX_RXP0
AA8
P_GFX_RXP1
Y7
P_GFX_RXP2
W5
P_GFX_RXP3
W8
P_GFX_RXP4
V7
P_GFX_RXP5
U5
P_GFX_RXP6
U8
P_GFX_RXP7
T7
P_GFX_RXP8
R5
P_GFX_RXP9
R8
P_GFX_RXP10
P7
P_GFX_RXP11
N5
P_GFX_RXP12
N8
P_GFX_RXP13
M7
P_GFX_RXP14
L5
P_GFX_RXP15
L8
P_GFX_RXN0
AA9
P_GFX_RXN1
Y8
P_GFX_RXN2
W6
P_GFX_RXN3
W9
P_GFX_RXN4
V8
P_GFX_RXN5
U6
P_GFX_RXN6
U9
P_GFX_RXN7
T8
P_GFX_RXN8
R6
P_GFX_RXN9
R9
P_GFX_RXN10
P8
P_GFX_RXN11
N6
P_GFX_RXN12
N9
P_GFX_RXN13
M8
P_GFX_RXN14
L6
P_GFX_RXN15
L9
P_GPP_RXP0
AC5
P_GPP_RXP1
AC8
P_GPP_RXP2
AB7
P_GPP_RXP3
AA5
P_GPP_RXN0
AC6
P_GPP_RXN1
AC9
P_GPP_RXN2
AB8
P_GPP_RXN3
AA6
P_UMI_RXP0
AF8
P_UMI_RXP1
AE6
P_UMI_RXP2
AE9
P_UMI_RXP3
AD8
P_UMI_RXN0
AF7
P_UMI_RXN1
AE5
P_UMI_RXN2
AE8
P_UMI_RXN3
AD7
P_ZVDDP
K5
P_GFX_TXP0
AA2
P_GFX_TXP1
Y2
P_GFX_TXP2
Y4
P_GFX_TXP3
W2
P_GFX_TXP4
V2
P_GFX_TXP5
V4
P_GFX_TXP6
U2
P_GFX_TXP7
T2
P_GFX_TXP8
T4
P_GFX_TXP9
R2
P_GFX_TXP10
P2
P_GFX_TXP11
P4
P_GFX_TXP12
N2
P_GFX_TXP13
M2
P_GFX_TXP14
M4
P_GFX_TXP15
L2
P_GFX_TXN0
AA3
P_GFX_TXN1
Y1
P_GFX_TXN2
Y5
P_GFX_TXN3
W3
P_GFX_TXN4
V1
P_GFX_TXN5
V5
P_GFX_TXN6
U3
P_GFX_TXN7
T1
P_GFX_TXN8
T5
P_GFX_TXN9
R3
P_GFX_TXN10
P1
P_GFX_TXN11
P5
P_GFX_TXN12
N3
P_GFX_TXN13
M1
P_GFX_TXN14
M5
P_GFX_TXN15
L3
P_GPP_TXP0
AD4
P_GPP_TXP1
AC2
P_GPP_TXP2
AB2
P_GPP_TXP3
AB4
P_GPP_TXN0
AD5
P_GPP_TXN1
AC3
P_GPP_TXN2
AB1
P_GPP_TXN3
AB5
P_UMI_TXP0
AF1
P_UMI_TXP1
AF5
P_UMI_TXP2
AE3
P_UMI_TXP3
AD1
P_UMI_TXN0
AF2
P_UMI_TXN1
AF4
P_UMI_TXN2
AE2
P_UMI_TXN3
AD2
P_ZVSS
K4
C924 0.1U_ 0402_16V7K
1 2
C927 0.1U_ 0402_16V7K
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ3
DDRA_SDQ13
DDRA_SDQ40
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ61
DDRA_SDQ15
DDRA_SDQ34
DDRA_SDQ36
DDRA_SDQ4
DDRA_SDQ0
DDRA_SDQ53
DDRA_SDQ47
DDRA_SDQ43
DDRA_SDQ39
DDRA_SDQ46
DDRA_SDQ33
DDRA_SDQ24
DDRA_SDQ54
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ8
DDRA_SDQ51
DDRA_SDQ9
DDRA_SDQ50
DDRA_SDQ12
DDRA_SDQ31
DDRA_SDQ7
DDRA_SDQ63
DDRA_SDQ62
DDRA_SDQ42
DDRA_SDQ26
DDRA_SDQ58
DDRA_SDQ25
DDRA_SDQ32
DDRA_SDQ1
DDRA_SDQ44
DDRA_SDQ48
DDRA_SDQ11
DDRA_SDQ55
DDRA_SDQ2
DDRA_SDQ38
DDRA_SDQ27
DDRA_SDQ41
DDRA_SDQ10
DDRA_SDQ14
DDRA_SDQ49
DDRA_SDQ30
DDRA_SDQ35
DDRA_SDQ37
DDRA_SDQ52
DDRA_SDQ45
DDRA_SDQ57
DDRA_SDQ56
DDRB_SDQ48
DDRB_SDQ39
DDRB_SDQ1
DDRB_SDQ42
DDRB_SDQ36
DDRB_SDQ2
DDRB_SDQ58
DDRB_SDQ33
DDRB_SDQ31
DDRB_SDQ21
DDRB_SDQ54
DDRB_SDQ62
DDRB_SDQ24
DDRB_SDQ15
DDRB_SDQ12
DDRB_SDQ49
DDRB_SDQ60
DDRB_SDQ43
DDRB_SDQ18
DDRB_SDQ34
DDRB_SDQ4
DDRB_SDQ61
DDRB_SDQ6
DDRB_SDQ25
DDRB_SDQ23
DDRB_SDQ57
DDRB_SDQ13
DDRB_SDQ0
DDRB_SDQ28
DDRB_SDQ16
DDRB_SDQ22
DDRB_SDQ19
DDRB_SDQ9
DDRB_SDQ50
DDRB_SDQ35
DDRB_SDQ46
DDRB_SDQ5
DDRB_SDQ37
DDRB_SDQ26
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ29
DDRB_SDQ14
DDRB_SDQ7
DDRB_SDQ51
DDRB_SDQ10
DDRB_SDQ59
DDRB_SDQ17
DDRB_SDQ44
DDRB_SDQ41
DDRB_SDQ38
DDRB_SDQ47
DDRB_SDQ32
DDRB_SDQ20
DDRB_SDQ52
DDRB_SDQ30
DDRB_SDQ63
DDRB_SDQ53
DDRB_SDQ40
DDRB_SDQ27
DDRB_SDQ45
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ11
DDRA_SWE#
DDRA_SCAS#
DDRA_SRAS#
DDRA_SBS2#
DDRA_SBS1#
DDRA_SBS0#
DDRA_SMA15
DDRA_SMA12
DDRA_SMA14
DDRA_SMA13
DDRA_SMA11
DDRA_SMA10
DDRA_SMA6
DDRA_SMA1
DDRA_SMA7
DDRA_SMA2
DDRA_SMA3
DDRA_SMA8
DDRA_SMA5
DDRA_SMA4
DDRA_SMA9
DDRA_SMA0
DDRA_SDM6
DDRA_SDM3
DDRA_SDM5
DDRA_SDM4
DDRA_SDM2
DDRA_SDM1
DDRA_SDM7
DDRA_SDM0
DDRA_SDQS0
DDRA_SDQS0#
DDRA_SDQS3
DDRA_SDQS3#
DDRA_SDQS2
DDRA_SDQS2#
DDRA_SDQS1
DDRA_SDQS1#
DDRA_SDQS4
DDRA_SDQS4#
DDRA_SDQS5
DDRA_SDQS5#
DDRA_SDQS6
DDRA_SDQS6#
DDRA_SDQS7#
DDRA_SDQS7
DDRA_CLK0#
DDRA_CLK0
DDRA_SCS1#
DDRA_SCS0#
DDRA_ODT0
DDRA_ODT1
DDRA_CKE0
DDRA_CKE1
MEM_MA_EVENT#
M_ZVDDIO
MEM_MA_RST#
DDRA_CLK1#
DDRA_CLK1
DDRA_SDQ20
DDRA_SDQ22
DDRA_SDQ21
DDRA_SDQ23
DDRA_SDQ17
DDRA_SDQ16
DDRA_SDQ18
DDRB_SMA14
DDRB_SMA10
DDRB_SMA7
DDRB_SMA1
DDRB_SMA12
DDRB_SMA6
DDRB_SMA11
DDRB_SMA0
DDRB_SMA9
DDRB_SMA15
DDRB_SMA3
DDRB_SMA5
DDRB_SMA8
DDRB_SMA13
DDRB_SMA2
DDRB_SMA4
DDRB_SRAS#
DDRB_SCAS#
DDRB_SWE#
DDRB_ODT0
DDRB_ODT1
DDRB_CKE1
DDRB_CKE0
DDRB_CLK0#
DDRB_CLK0
DDRB_SCS1#
DDRB_SCS0#
DDRB_CLK1#
MEM_MB_RST#
MEM_MB_EVENT#
DDRB_CLK1
DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS5
DDRB_SDQS5#
DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS7
DDRB_SDQS7#
DDRB_SDQS3
DDRB_SDQS3#
DDRB_SDM6
DDRB_SDM4
DDRB_SDM2
DDRB_SDM0
DDRB_SDM5
DDRB_SDM3
DDRB_SDM1
DDRB_SDM7
DDRB_SBS0#
DDRB_SBS1#
DDRB_SBS2#
DDRA_SDQ19
MEM_MA_EVENT#
MEM_MB_EVENT# +MEM_VREF
DDRB_SDQ[63..0] 12
DDRA_SBS0#11
DDRA_SBS1#11
DDRA_SBS2#11
DDRA_SDQS011
DDRA_SDQS0#11
DDRA_SDQS111
DDRA_SDQS1#11
DDRA_SDQS211
DDRA_SDQS2#11
DDRA_SDQS311
DDRA_SDQS3#11
DDRA_SDQS411
DDRA_SDQS4#11
DDRA_SDQS511
DDRA_SDQS5#11
DDRA_SDQS611
DDRA_SDQS6#11
DDRA_SDQS711
DDRA_SDQS7#11
DDRA_CLK011
DDRA_CLK0#11
DDRA_CKE011
DDRA_CKE111
DDRA_ODT011
DDRA_ODT111
DDRA_SCS0#11
DDRA_SCS1#11
DDRA_SRAS#11
DDRA_SCAS#11
DDRA_SWE#11
MEM_MA_RST#11
MEM_MA_EVENT#11
DDRA_CLK111
DDRA_CLK1#11
DDRA_SMA[15..0]11
DDRA_SDM[7..0]11
DDRA_SDQ[63..0] 11
DDRB_SBS0#12
DDRB_SBS1#12
DDRB_SBS2#12
DDRB_SMA[15..0]12
DDRB_SRAS#12
DDRB_SCAS#12
DDRB_SWE#12
DDRB_CLK012
DDRB_CLK0#12
DDRB_CKE012
DDRB_CKE112
DDRB_ODT012
DDRB_ODT112
DDRB_SCS0#12
DDRB_SCS1#12
MEM_MB_RST#12
MEM_MB_EVENT#12
DDRB_CLK112
DDRB_CLK1#12
DDRB_SDQS712
DDRB_SDQS7#12
DDRB_SDQS612
DDRB_SDQS512
DDRB_SDQS412
DDRB_SDQS312
DDRB_SDQS212
DDRB_SDQS112
DDRB_SDQS012
DDRB_SDQS6#12
DDRB_SDQS5#12
DDRB_SDQS4#12
DDRB_SDQS3#12
DDRB_SDQS2#12
DDRB_SDQS1#12
DDRB_SDQS0#12
DDRB_SDM[7..0]12
+1.5V
+MEM_VREF
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
AMD FS1 DDRIII I/F
Custom
7 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
Place them close to APU within 1"
Place them close to APU within 1"Place them close to APU within 1"
Place them close to APU within 1"
EVENT# pull high 0.75V reference voltage
15mil
15mil
R1804 39.2_0402_1%
1 2
R1807 1K_0402_5%
1 2
C964
1000P_0402_50V7K
1
2
C965
0.1U_0402_16V7K
1
2
R1806 1K_0402_5%
1 2
R1805
1K_0402_1%
1 2
R1808
1K_0402_1%
1 2
MEMORY CHANNEL A
JCPU1B
AMD_TOPEDO_FS-1
CONN@
MA_DATA0
E13
MA_DATA1
J13
MA_DATA2
H15
MA_DATA3
J15
MA_DATA4
H13
MA_DATA5
F13
MA_DATA6
F15
MA_DATA7
E15
MA_DATA8
H17
MA_DATA9
F17
MA_DATA10
E19
MA_DATA11
J19
MA_DATA12
G16
MA_DATA13
H16
MA_DATA14
H19
MA_DATA15
F19
MA_DATA16
H20
MA_DATA17
F21
MA_DATA18
J23
MA_DATA19
H23
MA_DATA20
G20
MA_DATA21
E20
MA_DATA22
G22
MA_DATA23
H22
MA_DATA24
G24
MA_DATA25
E25
MA_DATA26
G27
MA_DATA27
G26
MA_DATA28
F23
MA_DATA29
H24
MA_DATA30
E28
MA_DATA31
F27
MA_DATA32
AB28
MA_DATA33
AC27
MA_DATA34
AD25
MA_DATA35
AA24
MA_DATA36
AE28
MA_DATA37
AD28
MA_DATA38
AB26
MA_DATA39
AC25
MA_DATA40
Y23
MA_DATA41
AA23
MA_DATA42
Y21
MA_DATA43
AA20
MA_DATA44
AB24
MA_DATA45
AD24
MA_DATA46
AA21
MA_DATA47
AC21
MA_DATA48
AA19
MA_DATA49
AC19
MA_DATA50
AC17
MA_DATA51
AA17
MA_DATA52
AB20
MA_DATA53
Y19
MA_DATA54
AD18
MA_DATA55
AD17
MA_DATA56
AA16
MA_DATA57
Y15
MA_DATA58
AA13
MA_DATA59
AC13
MA_DATA60
Y17
MA_DATA61
AB16
MA_DATA62
AB14
MA_DATA63
Y13
MA_ADD0
U20
MA_ADD1
R20
MA_ADD2
R21
MA_ADD3
P22
MA_ADD4
P21
MA_ADD5
N24
MA_ADD6
N23
MA_ADD7
N20
MA_ADD8
N21
MA_ADD9
M21
MA_ADD10
U23
MA_ADD11
M22
MA_ADD12
L24
MA_ADD13
AA25
MA_ADD14
L21
MA_ADD15
L20
MA_BANK0
U24
MA_BANK1
U21
MA_BANK2
L23
MA_DM0
E14
MA_DM1
J17
MA_DM2
E21
MA_DM3
F25
MA_DM4
AD27
MA_DM5
AC23
MA_DM6
AD19
MA_DM7
AC15
MA_DQS_L7
AA15
MA_DQS_H7
AA14
MA_DQS_L6
AA18
MA_DQS_H6
AB18
MA_DQS_L5
AA22
MA_DQS_H5
AB22
MA_DQS_L4
AD26
MA_DQS_H4
AE26
MA_DQS_L3
E26
MA_DQS_H3
E27
MA_DQS_L2
H21
MA_DQS_H2
J21
MA_DQS_L1
H18
MA_DQS_H1
G18
MA_DQS_L0
H14
MA_DQS_H0
G14
MA_CLK_H0
T21
MA_CLK_L0
T22
MA_CLK_H1
R23
MA_CLK_L1
R24
MA_CKE0
H28
MA_CKE1
H27
MA_ODT0
Y25
MA_ODT1
AA27
MA_CS_L0
V22
MA_CS_L1
AA26
MA_RAS_L
V21
MA_CAS_L
W24
MA_WE_L
W23
MA_RESET_L
H25
MA_EVENT_L
T24
M_VREF
W20
M_ZVDDIO
W21
MEMORY CHANNEL B
JCPU1C
AMD_TOPEDO_FS-1
CONN@
MB_ADD0
T27
MB_ADD1
P24
MB_ADD2
P25
MB_ADD3
N27
MB_ADD4
N26
MB_ADD5
M28
MB_ADD6
M27
MB_ADD7
M24
MB_ADD8
M25
MB_ADD9
L26
MB_ADD10
U26
MB_ADD11
L27
MB_ADD12
K27
MB_ADD13
W26
MB_ADD14
K25
MB_ADD15
K24
MB_BANK0
U27
MB_BANK1
T28
MB_BANK2
K28
MB_DM0
D14
MB_DM1
A18
MB_DM2
A22
MB_DM3
C25
MB_DM4
AF25
MB_DM5
AG22
MB_DM6
AH18
MB_DM7
AD14
MB_DQS_H0
C15
MB_DQS_L0
B15
MB_DQS_H1
E18
MB_DQS_L1
D18
MB_DQS_H2
E22
MB_DQS_L2
D22
MB_DQS_H3
B26
MB_DQS_L3
A26
MB_DQS_H4
AG24
MB_DQS_L4
AG25
MB_DQS_H5
AG21
MB_DQS_L5
AF21
MB_DQS_H6
AG17
MB_DQS_L6
AG18
MB_DQS_H7
AH14
MB_DQS_L7
AG14
MB_CLK_H0
R26
MB_CLK_L0
R27
MB_CLK_H1
P27
MB_CLK_L1
P28
MB_CKE0
J26
MB_CKE1
J27
MB_ODT0
W27
MB_ODT1
Y28
MB_CS_L0
V25
MB_CS_L1
Y27
MB_RAS_L
V24
MB_CAS_L
V27
MB_WE_L
V28
MB_RESET_L
J25
MB_EVENT_L
T25
MB_DATA0
A14
MB_DATA1
B14
MB_DATA2
D16
MB_DATA3
E16
MB_DATA4
B13
MB_DATA5
C13
MB_DATA6
B16
MB_DATA7
A16
MB_DATA8
C17
MB_DATA9
B18
MB_DATA10
B20
MB_DATA11
A20
MB_DATA12
E17
MB_DATA13
B17
MB_DATA14
B19
MB_DATA15
C19
MB_DATA16
C21
MB_DATA17
B22
MB_DATA18
C23
MB_DATA19
A24
MB_DATA20
D20
MB_DATA21
B21
MB_DATA22
E23
MB_DATA23
B23
MB_DATA24
E24
MB_DATA25
B25
MB_DATA26
B27
MB_DATA27
D28
MB_DATA28
B24
MB_DATA29
D24
MB_DATA30
D26
MB_DATA31
C27
MB_DATA32
AG26
MB_DATA33
AH26
MB_DATA34
AF23
MB_DATA35
AG23
MB_DATA36
AG27
MB_DATA37
AF27
MB_DATA38
AH24
MB_DATA39
AE24
MB_DATA40
AE22
MB_DATA41
AH22
MB_DATA42
AE20
MB_DATA43
AH20
MB_DATA44
AD23
MB_DATA45
AD22
MB_DATA46
AD21
MB_DATA47
AD20
MB_DATA48
AF19
MB_DATA49
AE18
MB_DATA50
AE16
MB_DATA51
AH16
MB_DATA52
AG20
MB_DATA53
AG19
MB_DATA54
AF17
MB_DATA55
AD16
MB_DATA56
AG15
MB_DATA57
AD15
MB_DATA58
AG13
MB_DATA59
AD13
MB_DATA60
AG16
MB_DATA61
AF15
MB_DATA62
AE14
MB_DATA63
AF13
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
APU_TEST18
APU_TEST19
APU_TEST20
APU_TEST21
APU_TEST22
APU_DISP_CLKP
APU_DISP_CLKN
APU_THERMTRIP#
APU_PROCHOT#
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_TRST#
APU_DBRDY
APU_DBREQ#
APU_PWRGD
APU_RST#
APU_CLKP
APU_CLKN
M_TEST
DP_AUX_ZVSS
APU_TEST24
TEST35
TEST25_H
TEST25_L
DP0_TXP0
DP0_TXN0
DP0_TXP1
DP0_TXN1
DP0_AUXP
DP0_AUXN
APU_SID
APU_SIC
APU_TRST#
APU_DBRDY
APU_DBREQ#
APU_TEST18
APU_TEST19
FS1R1
DP0_HPD
DP1_HPD
DP1_TXP0
DP1_TXN0
DP1_TXP1
DP1_TXN1
ML_VGA_AUXP
ML_VGA_AUXN
APU_TDI
APU_TDO
APU_TCK
APU_TMS
APU_RST#
APU_PWRGD
DP1_TXP2
DP1_TXN2
DP1_TXP3
DP1_TXN3
APU_TDI
APU_TCK
APU_TMS
APU_TRST#
APU_DBREQ#
ALERT_L
APU_SVC
APU_SVD
APU_SIC
APU_SID
ALERT_L
APU_SVC
APU_SVD
APU_VDD_SEN
APU_VDDNB_SEN
DP_INT_PWM
DP_ENVDD
DP_ENBKL
DP0_AUXP
DP0_AUXN
ML_VGA_AUXP
ML_VGA_AUXN
M_TEST
APU_PWRGD
APU_RST#
FS1R1
TEST25_H
TEST25_L
TEST35
APU_PROCHOT#
APU_THERMTRIP#
APU_HDMI_DATA
APU_HDMI_CLK
DP5_HPD
DP0_TXP2
DP0_TXN2
DP0_TXN3
DP0_TXP3
ALLOW_STOP
ALLOW_STOP
APU_CLKP13
APU_CLKN13
APU_DISP_CLKP13
APU_DISP_CLKN13
APU_RST#13
APU_PWRGD13
DP0_TXP0_C26
DP0_TXN0_C26
DP0_AUXP_C 26
DP0_AUXN_C 26
APU_VDDNB_RUN_FB_ L47
APU_VDD_RUN_FB_L47
DP0_HPD 10
DP1_HPD 10
ML_VGA_TXP015
ML_VGA_TXN015
ML_VGA_TXP115
ML_VGA_TXN115
ML_VGA_AUXP_C 15
ML_VGA_AUXN_C 15
APU_SID6,14
APU_SIC6,14
ML_VGA_TXP215
ML_VGA_TXN215
ML_VGA_TXP315
ML_VGA_TXN315
ALLOW_STOP 13
APU_SVC47
APU_SVD47
APU_VDD_SEN47
APU_VDDNB_SEN47
DP_INT_PWM 10
DP_ENBKL 10
DP_ENVDD 10
EC_THERM# 13,32,47
H_THERMTRIP# 14
APU_HDMI_CLK 28
APU_HDMI_DATA 28
DP5_HPD 10
DP0_TXP1_C26
DP0_TXN1_C26
+1.5V
+1.5V
+1.5V
+1.5V
+1.5V
+1.5VS
+3VALW
+1.2VS
+1.5V
+3VS+1.5V
+1.5V
+1.5V
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
AMD FS1 Display / MISC / HDT
Custom
8 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
System DP
100MHz
100MHz_NSS
TSI
Cut on CPU side, Debug mount
To FCH VGA ML
HDT Debug conn
Llano do not support this thermal die
AUX 2~5 are for GFX interface
use, they could be selected to I2C
or AUX logic
VDDIO level
Need Level shift
LVDS
VDDIO level
Need Level shift
Place near APU
Place near APU
Place near APU
To LVDS
Translator
CRT
HDMI
To LVDS
Translator
To FCH
Close to Header
Chang to PU +1.5VS (DG ref.)
20101111
Serial VID
Route as differential
with VSS_SENSE
Chang to unpop (DG ref.)
20101111
VDDIO level
Need Level shift
If not used, pins are left unconnected (DG ref.)
20101111
FS1R1 : Control S5 Dual PWR plane
In laptop, seems no use
TEST35 PD 300ohm (DG ref.)
20101111
MISC
THERMTRIP shutdown
temperature: 125 degree
Asserted as an input to force the
processor into the HTC-active state
Indicates to the FCH that a thermal trip
has occurred. Its assertion will cause the FCH to
transition the system to S5 immediately
C981 0.1U_0402_16V7K
1 2
R587
10K_0402_5%
12
R548 510_0402_1%
1 2
R564 39.2_0402_1%@
1 2
R583 1K_0402_5%
1 2
C639 0.1U_0402_16V4Z
@
1 2
R602 0_0402_5%@
1 2
R791 1K_0402_5%
1 2
R609
10K_0402_5%
12
R595 1K_0402_5%
1 2
T8
R599 0_0402_5%@
1 2
R593 1K_0402_5%
1 2
T35
T22
C970 0.1U_0402_16V7K
1 2
R567 39.2_0402_1%
1 2
C979 0.1U_0402_16V7K
1 2
R556 1.8K_0 402_5%
12
C978 0.1U_0402_16V7K
1 2
R601 10K_0402_5%
1 2
E
B
C
Q12
MMBT3904_NL_SOT23-3
2
3 1
T15
R596 300_0402_5%
1 2
R591 0_0402_5%
1 2
T21
R606 0_0402_5%
1 2
C1016 0.1U_0402_16V7K
1 2
R600 0_0402_5%
1 2
T6
T11
JHDT1
SAMTE_ASP-136446-07-B
CONN@
1
1
3
3
5
5
7
7
9
9
11
11
13
13
15
15
17
17
19
19
2
2
4
4
6
6
8
8
10
10
12
12
14
14
16
16
18
18
20
20
R576 1K_0402_5%
1 2
R605 10K_0402_5%
1 2
C973 0.1U_0402_16V7K
1 2
R555 1.8K_0 402_5%
12
R584 1K_0402_5%
1 2
R1809 1.8K_0402_5%
12
C968 0.1U_0402_16V7K
1 2
T16
R1812 1K_0402_5%
1 2
C971 0.1U_0402_16V7K
1 2
C977 0.1U_0402_16V7K
1 2
R611 0_0402_5%
1 2
DISPLAY PORT 0DISPLAY PORT 1CLKSER.CTRLJTAG RSVDSENSE
TEST DISPLAY PORT MISC.
JCPU1D
AMD_TOPEDO_FS-1
CONN@
DP0_TXP0
F2
DP0_TXP1
E3
DP0_TXP2
D2
DP0_TXP3
C2
DP0_TXN0
F1
DP0_TXN1
E2
DP0_TXN2
D1
DP0_TXN3
C3
DP1_TXP0
K2
DP1_TXP1
J3
DP1_TXP2
H2
DP1_TXP3
G2
DP1_TXN0
K1
DP1_TXN1
J2
DP1_TXN2
H1
DP1_TXN3
G3
CLKIN_L
AH6
CLKIN_H
AH7
DISP_CLKIN_L
AH3
DISP_CLKIN_H
AH4
SVC
B8
SVD
A8
SIC
AH11
SID
AG11
RESET_L
AF10
PWROK
AE10
PROCHOT_L
AD10
THERMTRIP_L
AG12
ALERT_L
AH12
TDI
C12
TDO
A12
TCK
A11
TMS
D12
TRST_L
B12
DBRDY
B11
DBREQ_L
C11
RSVD_1
E8
RSVD_2
K21
RSVD_3
AC11
VSS_SENSE
B9
VDDP_SENSE
C8
VDDNB_SENSE
A9
VDDIO_SENSE
B10
VDD_SENSE
C9
VDDR_SENSE
A10
DP0_AUXP
D4
DP1_AUXP
E5
DP2_AUXP
J5
DP3_AUXP
H4
DP4_AUXP
G5
DP5_AUXP
F4
DP0_AUXN
D5
DP1_AUXN
E6
DP2_AUXN
J6
DP3_AUXN
H5
DP4_AUXN
G6
DP5_AUXN
F5
DP0_HPD
D7
DP1_HPD
E7
DP2_HPD
J7
DP3_HPD
H7
DP4_HPD
G7
DP5_HPD
F7
DP_DIGON
C5
DP_BLON
C6
DP_VARY_BL
C7
DP_AUX_ZVSS
D8
TEST6
AA10
TEST9
G10
TEST10
H10
TEST12
H12
TEST14
D9
TEST15
E9
TEST16
G9
TEST17
H9
TEST18
H11
TEST19
G11
TEST20
F12
TEST21
E11
TEST22
D11
TEST23
F10
TEST24
G12
TEST25_H
AH10
TEST25_L
AH9
TEST28_H
K7
TEST28_L
K8
TEST30_H
AA12
TEST30_L
AB12
TEST31
K22
TEST32_H
AB11
TEST32_L
AA11
TEST35
D10
FS1R1
Y11
DMAACTIVE_L
AB10
THERMDA
AE12
THERMDC
AD12
R608 0_0402_5%
1 2
R573 0_0402_5%@
1 2
R571 10K_0402_5%
1 2
E
B
C
Q11
MMBT3904_NL_SOT23-3
2
31
T20
R558 300_0402_5%
1 2
C1017 0.1U_0402_16V7K
1 2
T7
T13
T12
C976 0.1U_0402_16V7K
1 2
R603 10K_0402_5%
1 2
R574 1K_0402_5%
1 2
C975 0.1U_0402_16V7K
1 2
R579 1K_0402_5%
1 2
R581 1K_0402_5%
1 2
R610
1K_0402_5%
1 2
R590 1K_0402_5%
1 2
R582 1K_0402_5%
1 2
R559 300_0402_5%
@
1 2
T14
R586
1K_0402_5%
1 2
C972 0.1U_0402_16V7K
1 2
C969 0.1U_0402_16V7K
1 2
R578 300_0402_5%
1 2
R575 1K_0402_5%
1 2
R580 300_0402_5%
1 2
R585 1K_0402_5%
1 2
T9
R592 1K_0402_5%
1 2
R588
10K_0402_5%
12
C980 0.1U_0402_16V7K
1 2
C974 0.1U_0402_16V7K
1 2
R597 0_0402_5%
1 2
R554 1.8K_0 402_5%
12
R577 1K_0402_5%
@
1 2
R569 150_0402_1%
1 2
R594 1K_0402_5%
1 2
T10
R557 510_0402_1%
1 2
R589 1K_0402_5%
1 2
R598 0_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VDDA
+CPU_CORE
+CPU_CORE_NB
+1.5V
+1.2VS
+1.2VS
+CPU_CORE
+CPU_CORE_NB
+1.5V
+1.2VS
+1.5V
+1.5V
+CPU_CORE
+CPU_CORE_NB
+1.2VS
+1.2VS
+2.5VS
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
AMD FS1 PWR / GND
Custom
9 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
Keep trace from resistor to AP U
within 0.6"
Keep trace from Caps to APU
within 1.2"
Decoupling betw een CPU and DIM Ms
across VDDIO an d VSS split
CPU BOTTOM SIDE DECOUPLING
CPU_CORE
330uF X 4
22uF X 11
CORE_NB
330uF X 2
22uF X 4
VDDP decoupling
VDDR decoupling
40mil
120mil120mil
160mil160mil
160mil160mil
900mil900mil
2000mil2000mil
C1038 change to SF000002Y00
20101228
4A
VDD
+CPU_CORE
VDDA
+2.5VS
0.75A
VDDNB
+CPU_CORE_NB
VDDIO
+1.5V
Consumption
50A
VDDP / VDDR
+1.2VS
Power Name
3A / 3.5A
22.5A
VDDP/R_PWM
470uF x 2
10uF x 1
VDDP
10uF x 3
0.22uF x 2
180pF x 2
VDDIO_SUS
(CPU side)
680uF x 1
330uF x 1
22uF x 3
4.7uF x 4
0.22uF x 6
180pF x 4
VDDR
4.7uF x 4
0.22uF x 4
1nF x 4
180pF x 4
Demo Board Capacitor (include PWM side)
CPU_CORE
470uF x 6
22uF x 9
0.22uF x 2
180pF x 2
10nF x 3
CORE_NB
470uF x 4
22uF x 6
0.22uF x 2
180uF x 3
VDDIO_SUS
(DIMM x2)
100uF x 4
0.1uF
Del C1039
201012061900
C998
0.01U_0402_16V7K
1
2
C1036
0.22U_0603_16V4Z
1
2
C1008
180P_0402_50V8J
1
2
C982
22U_0805_6.3V6M
1
2
C11
4.7U_0603_6.3V6K
1
2
L1
FBMA-L11-201209-221LMA30T_0805
12
C1027
0.22U_0603_16V4Z
1
2
C1044
180P_0402_50V8J
1
2
C1052
0.22U_0603_16V4Z
1
2
+
C994
390U_2.5V_10M
1
2
C1019
0.22U_0603_16V4Z
1
2
+
C993
390U_2.5V_10M
1
2
C988
0.22U_0603_16V4Z
1
2
C1022
0.22U_0603_16V4Z
1
2
C997
22U_0805_6.3V6M
1
2
C8
10U_0603_6.3V6M
1
2
C1045
180P_0402_50V8J
1
2
+
C5
330U_D2_2V_Y
1
2
C1055
0.22U_0603_16V4Z
1
2
C1043
180P_0402_50V8J
@
1
2
C983
22U_0805_6.3V6M
1
2
C1030
180P_0402_50V8J
1
2
C1012
22U_0805_6.3V6M
1
2
C1021
0.22U_0603_16V4Z
1
2
C7
10U_0603_6.3V6M
1
2
C989
0.01U_0402_16V7K
1
2
C1051
1000P_0402_50V7K
1
2
C984
22U_0805_6.3V6M
1
2
C15
4.7U_0603_6.3V6K
1
2
C13
4.7U_0603_6.3V6K
1
2
C986
22U_0805_6.3V6M
1
2
+
C1015
390U_2.5V_10M
1
2
+
C999
390U_2.5V_10M
1
2
C1001
22U_0805_6.3V6M
1
2
C18
4.7U_0805_10V4Z
1
2
+
C1014
390U_2.5V_10M
1
2
+
C1011
390U_2.5V_10M
1
2
C12
4.7U_0603_6.3V6K
1
2
C10
4.7U_0603_6.3V6K
1
2
C1046
180P_0402_50V8J
1
2
C991
180P_0402_50V8J
1
2
C996
22U_0805_6.3V6M
1
2
C16
4.7U_0603_6.3V6K
1
2
C1020
0.22U_0603_16V4Z
1
2
C1000
22U_0805_6.3V6M
1
2
C1023
0.22U_0603_16V4Z
1
2
C17
4.7U_0603_6.3V6K
1
2
C1050
1000P_0402_50V7K
1
2
C1013
22U_0805_6.3V6M
1
2
+
C1010
390U_2.5V_10M
1
2
C990
0.01U_0402_16V7K
1
2
C1048
1000P_0402_50V7K
1
2
C1018
0.22U_0603_16V4Z
1
2
C1024
180P_0402_50V8J
1
2
C1025
180P_0402_50V8J
1
2
+
C1009
390U_2.5V_10M
1
2
JCPU1F
AMD_TOPEDO_FS-1
CONN@
VSS
A7
VSS
A13
VSS
A15
VSS
A17
VSS
A19
VSS
A21
VSS
A23
VSS
A25
VSS
B7
VSS
C4
VSS
C10
VSS
C14
VSS
C16
VSS
C18
VSS
C20
VSS
C22
VSS
C24
VSS
C26
VSS
C28
VSS
D13
VSS
D15
VSS
D17
VSS
D19
VSS
D21
VSS
D23
VSS
D25
VSS
D27
VSS
E4
VSS
E10
VSS
E12
VSS
F9
VSS
F11
VSS
F14
VSS
F16
VSS
F18
VSS
F20
VSS
F22
VSS
F24
VSS
F26
VSS
F28
VSS
G4
VSS
G8
VSS
G13
VSS
G15
VSS
G17
VSS
G19
VSS
G21
VSS
G23
VSS
G25
VSS
J4
VSS
J8
VSS
J18
VSS
J20
VSS
J22
VSS
J24
VSS
K19
VSS
L4
VSS
L7
VSS
L10
VSS
M9
VSS
M11
VSS
M19
VSS
N4
VSS
N7
VSS
N10
VSS
N18
VSS
P9
VSS
P11
VSS
P19
VSS
R4
VSS
R7
VSS
R10
VSS
R18
VSS
T9
VSS
T11
VSS
T19
VSS
U4
VSS
U7
VSS
U10
VSS
U18
VSS
V9
VSS
V11
VSS
V19
VSS
W4
VSS
W7
VSS
W10
VSS
W12
VSS
W14
VSS
W16
VSS
W18
VSS
Y9
VSS
Y22
VSS
AA4
VSS
AA7
VSS
AB9
VSS
AB13
VSS
AB15
VSS
AB17
VSS
AB19
VSS
AB21
VSS
AB23
VSS
AB25
VSS
AB27
VSS
AC4
VSS
AC7
VSS
AC10
VSS
AC12
VSS
AC14
VSS
AC16
VSS
AC18
VSS
AC20
VSS
AC22
VSS
AC24
VSS
AC26
VSS
AC28
VSS
AD9
VSS
AD11
VSS
AE4
VSS
AE7
VSS
AE13
VSS
AE15
VSS
AE17
VSS
AE19
VSS
AE21
VSS
AE23
VSS
AE25
VSS
AE27
VSS
AF3
VSS
AF6
VSS
AF9
VSS
AF12
VSS
AF14
VSS
AF16
VSS
AF18
VSS
AF20
VSS
AF22
VSS
AF24
VSS
AF26
VSS
AF28
VSS
AG10
VSS
AH5
VSS
AH8
VSS
AH13
VSS
AH15
VSS
AH17
VSS
AH19
VSS
AH21
VSS
AH23
VSS
AH25
C1053
0.22U_0603_16V4Z
1
2
C1041
0.22U_0603_16V4Z
1
2
C1040
3300P_0402_50V7K
12
C992
180P_0402_50V8J
1
2
+
C1038
220U_6.3V_M
1
2
C1002
22U_0805_6.3V6M
1
2
C1004
0.22U_0603_16V4Z
1
2
C1054
0.22U_0603_16V4Z
1
2
C1007
180P_0402_50V8J
1
2
C1029
180P_0402_50V8J
1
2
C14
4.7U_0603_6.3V6K
1
2
C1005
0.22U_0603_16V4Z
1
2
+
C995
330U_D2_2V_Y
@
1
2
C1028
0.22U_0603_16V4Z
1
2
C1047
180P_0402_50V8J
1
2
C6
10U_0603_6.3V6M
1
2
C1035
180P_0402_50V8J
1
2
C1037
0.22U_0603_16V4Z
1
2
C987
0.22U_0603_16V4Z
1
2
C1034
180P_0402_50V8J
1
2
C1003
22U_0805_6.3V6M
1
2
C985
22U_0805_6.3V6M
1
2
JCPU1E
AMD_TOPEDO_FS-1
CONN@
VDD
C1
VDD
D3
VDD
D6
VDD
E1
VDD
F3
VDD
F6
VDD
F8
VDD
G1
VDD
H3
VDD
H6
VDD
H8
VDD
J1
VDD
K3
VDD
K6
VDD
L1
VDD
L11
VDD
L19
VDD
M3
VDD
M6
VDD
M10
VDD
M18
VDD
N1
VDD
N11
VDD
N19
VDD
P3
VDD
P6
VDD
P10
VDD
P18
VDD
R1
VDD
R11
VDD
R19
VDD
T3
VDDNB
K9
VDDNB
J9
VDDNB
J10
VDDNB
J11
VDDNB
J12
VDDNB
J14
VDDNB
J16
VDDNB
K10
VDD
T6
VDD
T10
VDD
T18
VDD
U1
VDD
U11
VDD
U19
VDD
V3
VDD
V6
VDD
V10
VDD
V18
VDD
W1
VDD
W11
VDD
W13
VDD
W15
VDD
W17
VDD
W19
VDD
Y3
VDD
Y6
VDD
Y10
VDD
Y12
VDD
Y14
VDD
Y16
VDD
Y18
VDD
Y20
VDD
AA1
VDD
AB3
VDD
AB6
VDD
AC1
VDD
AD3
VDD
AD6
VDD
AE1
VDDNB
L18
VDDNB
K11
VDDNB
K12
VDDNB
K13
VDDNB
K14
VDDNB
K16
VDDNB
K17
VDDNB
K18
VDDIO
G28
VDDIO
H26
VDDIO
J28
VDDIO
K20
VDDIO
K23
VDDIO
K26
VDDIO
L22
VDDIO
L25
VDDIO
L28
VDDIO
M20
VDDIO
M23
VDDIO
M26
VDDIO
N22
VDDIO
N25
VDDIO
N28
VDDIO
P20
VDDIO
P23
VDDIO
P26
VDDIO
R22
VDDIO
R25
VDDIO
R28
VDDIO
T20
VDDIO
T23
VDDIO
T26
VDDIO
U22
VDDIO
U25
VDDIO
U28
VDDIO
V20
VDDIO
V23
VDDIO
V26
VDDIO
W22
VDDIO
W28
VDDIO
W25
VDDIO
Y24
VDDIO
Y26
VDDIO
AA28
VDDP_A_1
AG2
VDDP_A_2
AG3
VDDP_A_3
AG4
VDDP_A_4
AG5
VDDP_B_1
A3
VDDP_B_2
A4
VDDP_B_3
B3
VDDP_B_4
B4
VDDR
AG6
VDDR
AG7
VDDR
AG8
VDDR
AG9
VDDR
A5
VDDR
A6
VDDR
B5
VDDR
B6
VDDA
AE11
VDDA
AF11
C1006
180P_0402_50V8J
1
2
C1049
1000P_0402_50V7K
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
LVDS_HPD
FCH_CRT_HPD
APU_HDMI_HPD
DP_ENBKL ENBKL
DP_ENBKL
ENBKL
ENBKL 32
LVDS_HPD26 DP0_HPD 8
FCH_CRT_HPD15 DP1_HPD 8
APU_HDMI_HPD28 DP5_HPD 8
DP_ENBKL8
DP_ENVDD8
APU_ENVDD 27
DP_INT_PWM8
APU_INVT_PWM 26,27
+1.5VS
+3VS
+1.5VS
+3VS
+1.5VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
AMD FS1 Singal Level Shifter
Custom
10 51Friday, April 29, 2011
2010/08/04 2010/08/04
Translator HPD
CRT HPD
HDMI HPD
HPD
HPDHPD
HPD Panel ENBKL
Panel ENBKLPanel ENBKL
Panel ENBKL
From Translator
From FCH
From HDMI Conn
Panel ENVDD
Panel ENVDDPanel ENVDD
Panel ENVDD
Panel PWM
Panel PWMPanel PWM
Panel PWM
Q15 / Q19 / Q21 change to SB000006A00
20101228
R632
4.7K_0402_5%
@
12
R630
4.7K_0402_5%
@
12
R615
1K_0402_5%
@
1 2
R620
100K_0402_5%
@
1 2
R634
100K_0402_5%
@
1 2
R635
47K_0402_5%
12
G
D
S
Q18
2N7002_SOT23
@
2
13
G
D
S
Q14
2N7002_SOT23
@
2
13
E
B
C
Q19
MMBT3904_NL_SOT23-3
@
2
3 1
R659 100K_0402_5%
@
12
G
D
S
Q16
2N7002_SOT23
2
1 3
R618 100K_0402_5%
@
12
R627 100K_0402_5%
@
12
R638
4.7K_0402_5%
12
R677 0_0402_5%
1 2
R623
1K_0402_5%
12
R1810
100K_0402_5%
@
1 2
R613
10K_0402_5%
12
R616
1K_0402_5%
1 2
R622
1K_0402_5%
@
1 2
R621
10K_0402_5%
12
E
B
C
Q15
MMBT3904_NL_SOT23-3
@
2
3 1
G
D
S
Q20
2N7002_SOT23
2
13
G
D
S
Q13
2N7002_SOT23
2
1 3
R617
100K_0402_5%
@
1 2
R624 0_0402_5%
1 2
R633 2.2K_0402_5%
@
1 2
R619 2.2K_0402_5%
@
1 2
R637 2.2K_0402_5%
1 2
R636
4.7K_0402_5%
12
E
B
C
Q21
MMBT3904_NL_SOT23-3
2
3 1
R614
4.7K_0402_5%
@
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRA_SDQ36
DDRA_SDQ63
DDRA_SDQ26
DDRA_SDQS6
DDRA_SDQ2
DDRA_SDQ5
DDRA_SDQ22
DDRA_SDQ25
DDRA_SDQ35
DDRA_SMA12
DDRA_SDQ14
DDRA_SDQS0#
DDRA_SDQS4
DDRA_SDM6
DDRA_SDQ42
DDRA_CKE1
DDRA_SDQ27
DDRA_SMA15
DDRA_SDQ31
DDRA_CKE0
DDRA_SDQ12
DDRA_SDQ59
DDRA_SMA3
DDRA_SDQ6
DDRA_SCS1#
DDRA_SDQ39
DDRA_SBS1#
DDRA_SWE#
DDRA_SMA7
DDRA_SDQS0
DDRA_SMA0
DDRA_SDM2
DDRA_SDQS7
DDRA_SDM1
DDRA_SDQ57
DDRA_SDQ46
DDRA_SDQ0
DDRA_SDQ28
DDRA_SDM0
DDRA_SDQS5#
DDRA_SDQ51
DDRA_SDQ19
DDRA_SDM4
DDRA_SDQ4
DDRA_SDQ30
DDRA_SDQS2
DDRA_SDQ44
DDRA_SRAS#
DDRA_SDQ33
DDRA_SDQ58
DDRA_SDM5
DDRA_SDQS3
DDRA_SMA8
DDRA_SCS0#
DDRA_SDQ10
DDRA_SMA6
DDRA_SMA10
DDRA_SDQ3
MEM_MA_RST#
DDRA_SDQS7#
DDRA_SDQS6#
DDRA_SDQ1
DDRA_SDQ40
DDRA_SMA9
DDRA_SDQ16
DDRA_SDQ29
DDRA_SDQS4#
DDRA_SDQ52
DDRA_SDM3
DDRA_SDQS5
DDRA_SDQ54
DDRA_SDQ49
DDRA_SBS2#
DDRA_SDQ45
DDRA_SDQ9
DDRA_SDM7
DDRA_SMA1
DDRA_SDQ7
DDRA_SDQ13
DDRA_SDQ20
DDRA_SDQ60
DDRA_SBS0#
DDRA_SCAS# DDRA_ODT0
DDRA_SDQ37
DDRA_SMA5
DDRA_SDQS1#
DDRA_SMA14
DDRA_SDQ55
DDRA_SMA4
DDRA_SDQ21
DDRA_SDQ62
DDRA_SDQ24
DDRA_SDQ15
DDRA_SDQ56
DDRA_SDQ23
DDRA_SDQ53
DDRA_SDQ47
DDRA_ODT1
DDRA_SDQ18
DDRA_SDQ43
DDRA_SDQ34
DDRA_CLK1
DDRA_CLK1#
DDRA_SDQ48
DDRA_SDQS2#
DDRA_SDQ11
DDRA_SDQ38
DDRA_CLK0
DDRA_CLK0#
DDRA_SDQ32
DDRA_SDQS3#
DDRA_SMA13
DDRA_SMA11
DDRA_SDQ50
DDRA_SDQ8
DDRA_SDQS1
DDRA_SDQ61
DDRA_SMA2
DDRA_SDQ41
DDRA_SDQ17
DDRA_SDQ[0..63]
DDRA_SDM[0..7]
DDRA_SMA[0..15]
+VREF_DQ
+VREF_CA
MEM_MA_EVENT#
DDRA_CKE07
DDRA_SCS1#7
DDRA_SBS1# 7
DDRA_SWE#7
DDRA_SRAS# 7
DDRA_SCS0# 7
MEM_MA_RST# 7
DDRA_SBS2#7
DDRA_SBS0#7
DDRA_SCAS#7 DDRA_ODT0 7
DDRA_ODT1 7
DDRA_CLK1# 7
DDRA_CLK1 7
DDRA_CLK07
DDRA_CLK0#7
DDRA_CKE1 7
FCH_SDATA0 12,14,35
FCH_SCLK0 12,14,35
DDRA_SDQS3 7
DDRA_SDQS0 7
DDRA_SDQS3# 7
DDRA_SDQS0# 7
DDRA_SDQS5 7
DDRA_SDQS5# 7
DDRA_SDQS7 7
DDRA_SDQS7# 7
DDRA_SDQS1#7
DDRA_SDQS17
DDRA_SDQS2#7
DDRA_SDQS27
DDRA_SDQS4#7
DDRA_SDQS47
DDRA_SDQS6#7
DDRA_SDQS67
DDRA_SDQ[0..63] 7
DDRA_SDM[0..7] 7
DDRA_SMA[0..15] 7
MEM_MA_EVENT# 7
+0.75VS
+3VS
+1.5V +1.5V+VREF_DQ
+VREF_CA
+3VS
+1.5V+VREF_DQ
+1.5V+VREF_CA
+1.5V
+1.5V+0.75VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
DDRIII SO-DIMM 2
Custom
11 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
DIMM_A STD H:9.2mm
<Address: 00>
15mil
15mil
15mil
15mil
Add C1106
20101101
Place near DIMM1
C1066
1000P_0402_50V7K
1
2
C1074
0.1U_0402_16V4Z
1
2
C1081
0.1U_0402_16V4Z
1
2
R641
1K_0402_1%
1 2
C1064
0.1U_0402_16V4Z
1
2
C1073
0.1U_0402_16V4Z
1
2
C1072
0.1U_0402_16V4Z
1
2
C1079
4.7U_0603_6.3V6K
1
2
C1077
0.1U_0402_16V4Z
1
2
JDIMM2
TYCO_2-2013310-1
CONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C1061
0.1U_0402_16V4Z
1
2
C1078
0.1U_0402_16V4Z
1
2
C1062
1000P_0402_50V7K
1
2
R640
1K_0402_1%
1 2
C1080
2.2U_0603_6.3V4Z
1
2
R642
1K_0402_1%
1 2
R645
10K_0402_5%
12
C1063
4.7U_0603_6.3V6K
@
1
2
C1070
0.1U_0402_16V4Z
1
2
C1106 0.1U_0402_16V4Z
@
1 2
C1075
0.1U_0402_16V4Z
1
2
C1069
0.1U_0402_16V4Z
1
2
R643 10K_0402_5%
1 2
C1071
0.1U_0402_16V4Z
1
2
C1067
0.1U_0402_16V4Z
1
2
C1076
0.1U_0402_16V4Z
1
2
C1065
1000P_0402_50V7K
1
2
R639
1K_0402_1%
1 2
C1068
0.1U_0402_16V4Z
1
2
C1060
4.7U_0603_6.3V6K
@
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
DDRB_SDQS6
DDRB_SDQ26
DDRB_SDQ63
DDRB_SDQ36
DDRB_SDQ35
DDRB_SDQ25
DDRB_SDQ22
DDRB_SDQ5
DDRB_SDQ2
DDRB_SDQS0#
DDRB_SDQ14
DDRB_SMA12
DDRB_CKE1
DDRB_SDQ42
DDRB_SDM6
DDRB_SDQS4
DDRB_SMA15
DDRB_SDQ27
DDRB_SDQ12
DDRB_CKE0
DDRB_SDQ31
DDRB_SMA3
DDRB_SDQ59
DDRB_SBS1#
DDRB_SDQ39
DDRB_SCS1#
DDRB_SDQ6
DDRB_SDQS0
DDRB_SMA7
DDRB_SWE#
DDRB_SMA0
DDRB_SDM2
DDRB_SDQ0
DDRB_SDQ46
DDRB_SDQ57
DDRB_SDM1
DDRB_SDQS7
DDRB_SDM0
DDRB_SDQ28
DDRB_SDM4
DDRB_SDQ19
DDRB_SDQ51
DDRB_SDQS5#
DDRB_SDQS2
DDRB_SDQ30
DDRB_SDQ4
DDRB_SDQ33
DDRB_SRAS#
DDRB_SDQ44
DDRB_SDQS3
DDRB_SDM5
DDRB_SDQ58
DDRB_SMA8
DDRB_SCS0#
DDRB_SMA10
DDRB_SMA6
DDRB_SDQ10
DDRB_SDQS6#
DDRB_SDQS7#
MEM_MB_RST#
DDRB_SDQ3
DDRB_SDQ16
DDRB_SMA9
DDRB_SDQ1
DDRB_SDQS4#
DDRB_SDQ29
DDRB_SDQ49
DDRB_SDQ54
DDRB_SDQS5
DDRB_SDM3
DDRB_SDQ9
DDRB_SDQ45
DDRB_SBS2#
DDRB_SDQ20
DDRB_SDQ13
DDRB_SDQ7
DDRB_SMA1
DDRB_SDM7
DDRB_SBS0#
DDRB_SDQ60
DDRB_SDQ37
DDRB_ODT0DDRB_SCAS#
DDRB_SDQ55
DDRB_SMA14
DDRB_SDQS1#
DDRB_SMA5
DDRB_SDQ21
DDRB_SMA4
DDRB_SDQ62
DDRB_SDQ15
DDRB_SDQ24
DDRB_SDQ47
DDRB_SDQ53
DDRB_SDQ23
DDRB_SDQ56
DDRB_SDQ43
DDRB_SDQ18
DDRB_ODT1
DDRB_CLK1#
DDRB_CLK1
DDRB_SDQ34
DDRB_SDQS2#
DDRB_SDQ48
DDRB_CLK0#
DDRB_CLK0
DDRB_SDQ11
DDRB_SDQ50
DDRB_SMA11
DDRB_SMA13
DDRB_SDQS3#
DDRB_SDQ32
DDRB_SMA2
DDRB_SDQ61
DDRB_SDQS1
DDRB_SDQ8
DDRB_SDQ17
DDRB_SDQ41
DDRB_SDQ40
DDRB_SDQ38
DDRB_SDQ52
+VREF_DQ +VREF_CA
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..15]
MEM_MB_EVENT#
DDRB_SCS1#7
DDRB_CKE07
DDRB_SCS0# 7
DDRB_SRAS# 7
DDRB_SWE#7
DDRB_SBS1# 7
DDRB_SCAS#7
DDRB_SBS0#7
DDRB_SBS2#7
MEM_MB_RST# 7
DDRB_CLK1 7
DDRB_CLK1# 7
DDRB_ODT1 7
DDRB_ODT0 7
DDRB_CKE1 7
DDRB_CLK0#7
DDRB_CLK07
DDRB_SDQS27
DDRB_SDQS2#7
DDRB_SDQS47
DDRB_SDQS4#7
DDRB_SDQS67
DDRB_SDQS6#7
DDRB_SDQS0# 7
DDRB_SDQS0 7
DDRB_SDQS3# 7
DDRB_SDQS3 7
DDRB_SDQS5 7
DDRB_SDQS5# 7
DDRB_SDQS7 7
DDRB_SDQS7# 7
FCH_SDATA0 11,14,35
FCH_SCLK0 11,14,35
DDRB_SDQS1#7
DDRB_SDQS17
DDRB_SDQ[0..63] 7
DDRB_SDM[0..7] 7
DDRB_SMA[0..15] 7
MEM_MB_EVENT# 7
+0.75VS
+1.5V+1.5V
+3VS
+VREF_DQ
+VREF_CA
+VREF_DQ +VREF_CA
+1.5V+1.5V
+1.5V
+0.75VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
DDRIII SO-DIMM 1
Custom
12 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
DIMM_B STD H:5.2mm
<Address: 01>
15mil
15mil
15mil 15mil
C1102 change to OSCON
20101101
Place near DIMM2
Add C1107
20101101
C1094
0.1U_0402_16V4Z
1
2
C1082
4.7U_0603_6.3V6K
@
1
2
C1091
0.1U_0402_16V4Z
1
2
C1088
1000P_0402_50V7K
1
2
C1098
0.1U_0402_16V4Z
1
2
C1097
0.1U_0402_16V4Z
1
2
C1093
0.1U_0402_16V4Z
1
2
C1089
0.1U_0402_16V4Z
1
2
C1099
0.1U_0402_16V4Z
1
2
R646 10K_0402_5%
<BOM Structure>
1 2
C1090
0.1U_0402_16V4Z
1
2
C1107 0.1U_0402_16V4Z
@
1 2
C1095
0.1U_0402_16V4Z
1
2
+
C1668
330U_2.5V_M_R15
@
12
C1101
4.7U_0603_6.3V6K
1
2
C1100
0.1U_0402_16V4Z
1
2
JDIMM1
TYCO_2-2013289-1
C
ONN@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C1087
1000P_0402_50V7K
1
2
C1084
1000P_0402_50V7K
1
2
R648
10K_0402_5%
<BOM Structure>
12
C1092
0.1U_0402_16V4Z
1
2
C1083
0.1U_0402_16V4Z
1
2
C1086
0.1U_0402_16V4Z
1
2
C1085
4.7U_0603_6.3V6K
@
1
2
C1096
0.1U_0402_16V4Z
1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
UMI_MTX_FRX_P0
UMI_MTX_FRX_N0
UMI_MTX_FRX_P1
UMI_MTX_FRX_N1
UMI_MTX_FRX_P2
UMI_MTX_FRX_N2
UMI_MTX_FRX_P3
UMI_MTX_FRX_N3
A_RST#_R
PCIE_CALRP
PCIE_CALRN
APU_PWRGD
CLK_CALRN
UMI_FTX_C_MRX_P0
UMI_FTX_C_MRX_N0
UMI_FTX_C_MRX_P1
UMI_FTX_C_MRX_N1
UMI_FTX_C_MRX_P2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
UMI_FTX_C_MRX_N3
25M_X2
32K_X1
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
25M_X1
32K_X2
32K_X1
32K_X2
VGA_PWRGD VGA_PWRGD_R
VGA_PWRGD_R
RTCVCC_R
APU_PWRGD
APU_PCIE_RST#_C
CLK_SD_48M_R
PE_GPIO1
APU_CLKP
APU_CLKN
CLK_PEG_VGA
CLK_PEG_VGA#
APU_DISP_CLKP
APU_DISP_CLKN APU_DISP_C LKN_R
APU_DISP_CLKP_R
CLK_PCIE_MINI1
CLK_PCIE_MINI1#
CLK_PCIE_MINI1_R
CLK_PCIE_MINI1#_R
CLK_PCIE_LAN
CLK_PCIE_LAN#
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
LPC_CLK1_R
APU_PCIE_RST#_C
LPC_CLK0_ECLPC_CLK0_EC _R
PCIE_W_FTX_DRX_P0
PCIE_W_FTX_DRX_N 0
PCIE_W_DTX_C_FRX _P0
PCIE_W_DTX_C_FRX _N0
TRAVIS_CLKP
APU_CLKP_R
APU_CLKN_R
TRAVIS_CLKN TRAVIS_CLKN_R
CLK_PEG_VGA#_R
CLK_PEG_VGA_R
TRAVIS_CLKP_R
ALLOW_STOP 8
PCI_CLK4 16
APU_RST# 8
EC_THERM# 8,32,47
UMI_FTX_C_MRX_P06
UMI_FTX_C_MRX_N06
UMI_FTX_C_MRX_P16
UMI_FTX_C_MRX_N16
UMI_FTX_C_MRX_P26
UMI_FTX_C_MRX_N26
UMI_FTX_C_MRX_P36
UMI_FTX_C_MRX_N36
UMI_MTX_C_FRX_P06
UMI_MTX_C_FRX_N06
UMI_MTX_C_FRX_P16
UMI_MTX_C_FRX_N16
UMI_MTX_C_FRX_P26
UMI_MTX_C_FRX_N26
UMI_MTX_C_FRX_P36
UMI_MTX_C_FRX_N36
APU_PWRGD 8
LPC_CLK1 16
RTC_CLK 16,32
LPC_AD0 32,35
LPC_AD1 32,35
LPC_AD2 32,35
LPC_AD3 32,35
SERIRQ 32
LPC_FRAME# 32,35
PCI_AD27 16
PCI_CLK3 16
PCI_AD26 16
PCI_AD25 16
PCI_AD24 16
PCI_AD23 16
PCI_CLK1 16
VGA_PWRGD25,48
PE_GPIO0 18
PE_GPIO1 25,32
APU_PWRGD_L 47
LPC_CLK0_EC 16,32
CLK_SD_48M34
CLK_PEG_VGA18
CLK_PEG_VGA#18
APU_CLKP8
APU_CLKN8
APU_DISP_CLKP8
APU_DISP_CLKN8
CLK_PCIE_MINI135
CLK_PCIE_MINI1#35
CLK_PCIE_LAN31
CLK_PCIE_LAN#31
CLK_PCI_DB 35
PLT_RST# 18,26,31,35
A_RST#32
PCIE_W_FTX_DRX_P035
PCIE_W_FTX_DRX_N 035
PCIE_W_DTX_C_FRX _P035
PCIE_W_DTX_C_FRX _N035
TRAVIS_CLKP26
TRAVIS_CLKN26
+1.1VS_CKVDD
+PCIE_VDDR_FCH
+3VALW
+RTCVCC
+CHGRTC
+RTCBATT
+RTCBATT
+3VS
+3VALW
+1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
Hudson-M2/M3-UMI/PCI/CLOCK/LPC/RTC
Custom
13 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
WLAN
For PCIE device reset on FS1
(
GFX,GLAN,WLAN,LVDS Travis)
Close to HUDSON-M2
PCI Host Bus Reset (To EC)
PROCHOT# : IN, 0.8V threshold
V
GA
APU
APU DISP
APU_PG/APU_RST#/LDT_STP# : OD pin
LDT_STP : No use, NC
DMA_ACTIVE# : IN/OD, 0.8V threshold
W=20mils
for Clear CMOS
DMA active. The FCH drives the DMA_ACTIVE# to
APU to notify DMA activity. This will cause the APU
to reestablish the UMI link quicker.
NSS
SS
SS
Level shift to ISL6267
RTC BATT Conn.
GPP Port0 For USB30 on SUS/B
GPP Port0 For USB30 on SUS/BGPP Port0 For USB30 on SUS/B
GPP Port0 For USB30 on SUS/B
GPP Port1 For USB30 on M/B 20101103
GPP Port1 For USB30 on M/B 20101103GPP Port1 For USB30 on M/B 20101103
GPP Port1 For USB30 on M/B 20101103
Q38 change to SB000006A00
20101228
GLAN
EMI
For "EXT" CLK mode, input to PCIE,
WLAN
Translator
R163 0_0402_5%
1 2
R844
0_0402_5%
1 2
JRTC1
SUYIN_060003HA002G202ZL
CONN@
+
1
-
2
R612 0_0402_5%
1 2
R833 2K_0402_1%
1 2
C1195 150P_0402_50V8J
12
R830 0_0402_5%@
1 2
C1192 0.1U_0402_16V7K
1 2
X1
25MHZ_20PF_7A25000012
12
R853 0_0402_5%@
1 2
U27
NC7SZ08P5X_NL_SC70-5
@
B
2
A
1
Y
4
P
5
G
3
R836
4.7K_0402_5%
1 2
R565 0_0402_5%
1 2
R829 33_ 0402_5%
1 2
C1201
10P_0402_50V8J
1 2
R832 0_0402_5%
1 2
C1196 0.1U_0402_16V7K
1 2
R826
8.2K_0402_5%@
1 2
E
B
C
Q38
MMBT3904_NL_SOT23-3
2
3 1
T23
D23
DAN202UT106_SC70-3
2
3
1
T24
R835 0_0402_5%
1 2
R566 0_0402_5%
1 2
R1811 10K_0402_5%
@
1 2
C1202
0.1U_0402_16V4Z
1
2
C1197 0.1U_0402_16V7K
1 2
C1190 0.1U_0402_16V7K
1 2
C1204
0.1U_0402_16V4Z
1
2
R843 22_0402_5%
1 2
C1205
10P_0402_50V8J
1 2
R861
20M_0402_5%
12
C1191 0.1U_0402_16V7K
1 2
C1194 0.1U_0402_16V7K
1 2
R855 22_0402_5%
1 2
R568 0_0402_5%
1 2
C1203
1U_0402_6.3V4Z
1
2
R856 0_0402_5%
1 2
C1198 0.1U_0402_16V7K
1 2
R857
1K_0402_5%
12
Y4
32.768KHZ 7PF Q13MC1461000100
OSC
4
OSC
1
NC
3
NC
2
R842 0_0402_5%
1 2
U26
NC7SZ08P5X_NL_SC70-5
@
B
2
A
1
Y
4
P
5
G
3
R827 590_0402_1%
1 2
C1188
150P_0402_50V8J
1
2
R834
10K_0402_5%
12
R671 0_0 402_5%
1 2
R162 0_0402_5%
1 2
R572 0_0402_5%
1 2
R657 22_0402_5%
1 2
R570 0_0402_5%
1 2
R604 0_0402_5%
1 2
R859 510_0402_5%
1 2
C1206
8P_0402_50V
1 2
C1193
0.1U_0402_16V4Z
@
1 2
R644 0_0402_5%
1 2
C1199
0.1U_0402_16V4Z
@
1 2
R828 2K_0402_1%
1 2
R831 100K_0402_5%@
1 2
HUDSON-2
PCI CLKS
PCI EXPRESS INTERFACES
PCI INTERFACE
CLOCK GENERATOR
LPCAPUS5 PLUS
U25A
HUDSON-M2_FCBGA656
M2@
PCIE_RST#
AE2
A_RST#
AD5
UMI_TX0P
AE30
UMI_TX0N
AE32
UMI_TX1P
AD33
UMI_TX1N
AD31
UMI_TX2P
AD28
UMI_TX2N
AD29
UMI_TX3P
AC30
UMI_TX3N
AC32
UMI_RX0P
AB33
UMI_RX0N
AB31
UMI_RX1P
AB28
UMI_RX1N
AB29
UMI_RX2P
Y33
UMI_RX2N
Y31
UMI_RX3P
Y28
UMI_RX3N
Y29
PCIE_CALRP
AF29
PCIE_CALRN
AF31
GPP_TX0P
V33
GPP_TX0N
V31
GPP_TX1P
W30
GPP_TX1N
W32
GPP_TX2P
AB26
GPP_TX2N
AB27
GPP_TX3P
AA24
GPP_TX3N
AA23
GPP_RX0P
AA27
GPP_RX0N
AA26
GPP_RX1P
W27
GPP_RX1N
V27
GPP_RX2P
V26
GPP_RX2N
W26
GPP_RX3P
W24
GPP_RX3N
W23
CLK_CALRN
F27
PCIE_RCLKP
G30
PCIE_RCLKN
G28
DISP_CLKP
R26
DISP_CLKN
T26
DISP2_CLKP
H33
DISP2_CLKN
H31
APU_CLKP
T24
APU_CLKN
T23
SLT_GFX_CLKP
J30
SLT_GFX_CLKN
K29
GPP_CLK0P
H27
GPP_CLK0N
H28
GPP_CLK1P
J27
GPP_CLK1N
K26
GPP_CLK2P
F33
GPP_CLK2N
F31
GPP_CLK3P
E33
GPP_CLK3N
E31
GPP_CLK4P
M23
GPP_CLK4N
M24
GPP_CLK5P
M27
GPP_CLK5N
M26
GPP_CLK6P
N25
GPP_CLK6N
N26
GPP_CLK7P
R23
GPP_CLK7N
R24
GPP_CLK8P
N27
GPP_CLK8N
R27
14M_25M_48M_OSC
J26
25M_X1
C31
25M_X2
C33
PCICLK0
AF3
PCICLK1/GPO36
AF1
PCICLK2/GPO37
AF5
PCICLK3/GPO38
AG2
PCICLK4/14M_OSC/GPO39
AF6
PCIRST#
AB5
AD0/GPIO0
AJ3
AD1/GPIO1
AL5
AD2/GPIO2
AG4
AD3/GPIO3
AL6
AD4/GPIO4
AH3
AD5/GPIO5
AJ5
AD6/GPIO6
AL1
AD7/GPIO7
AN5
AD8/GPIO8
AN6
AD9/GPIO9
AJ1
AD10/GPIO10
AL8
AD11/GPIO11
AL3
AD12/GPIO12
AM7
AD13/GPIO13
AJ6
AD14/GPIO14
AK7
AD15/GPIO15
AN8
AD16/GPIO16
AG9
AD17/GPIO17
AM11
AD18/GPIO18
AJ10
AD19/GPIO19
AL12
AD20/GPIO20
AK11
AD21/GPIO21
AN12
AD22/GPIO22
AG12
AD23/GPIO23
AE12
AD24/GPIO24
AC12
AD25/GPIO25
AE13
AD26/GPIO26
AF13
AD27/GPIO27
AH13
AD28/GPIO28
AH14
AD29/GPIO29
AD15
AD30/GPIO30
AC15
AD31/GPIO31
AE16
CBE0#
AN3
CBE1#
AJ8
CBE2#
AN10
CBE3#
AD12
FRAME#
AG10
DEVSEL#
AK9
IRDY#
AL10
TRDY#
AF10
PAR
AE10
STOP#
AH1
PERR#
AM9
SERR#
AH8
REQ0#
AG15
REQ1#/GPIO40
AG13
REQ2#/CLK_REQ8#/GPIO41
AF15
REQ3#/CLK_REQ5#/GPIO42
AM17
GNT0#
AD16
GNT1#/GPO44
AD13
GNT2#/SD_LED/GPO45
AD21
GNT3#/CLK_REQ7#/GPIO46
AK17
CLKRUN#
AD19
LOCK#
AH9
INTE#/GPIO32
AF18
INTF#/GPIO33
AE18
INTG#/GPIO34
AC16
INTH#/GPIO35
AD18
LPCCLK0
B25
LPCCLK1
D25
LAD0
D27
LAD1
C28
LAD2
A26
LAD3
A29
LFRAME#
A31
LDRQ0#
B27
LDRQ1#/CLK_REQ6#/GPIO49
AE27
SERIRQ/GPIO48
AE19
DMA_ACTIVE#
G25
PROCHOT#
E28
APU_PG
E26
LDT_STP#
G26
APU_RST#
F26
S5_CORE_EN
H7
RTCCLK
F1
INTRUDER_ALERT#
F3
VDDBT_RTC_G
E6
32K_X1
G2
32K_X2
G4
R607 0_0402_5%
1 2
C1189 0.1U_0402_16V7K
1 2
CLRP1
SHORT PADS
@
12
R858
1M_0402_5%
R825 33_0402_5%
1 2
R625 0_0402_5%
1 2
C1200
12P_0402_50V8J
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
USB_RCOMP
USBSS_CALRP
USBSS_CALRN
FCH_SCLK0
FCH_SDATA0
FCH_SCLK1
FCH_SDATA1
VGA_PD
USB_OC0#
HDA_BITCLK
HDA_SYNC
HDA_SDIN0
HDA_SDIN1
HDA_SDOUT
HDA_RST#
EC_PWM2
TEST0
TEST1
TEST2
FCH_PCIE_WAKE#
EC_LID_OUT#
SYS_RESET#
APU_SID
APU_SIC
HDA_BITCLK
HDA_SDIN0
HDA_SDIN1
EC_RSMRST#
MINI1_CLKREQ#
FCH_SCLK0
FCH_SDATA0
LAN_CLKREQ#_1
EC_LID_OUT#
FCH_PCIE_WAKE#
H_THERMTRIP#
FCH_SCLK1
FCH_SDATA1
FCH_GPIO190
FCH_GPIO191
FCH_GPIO189
TEST0
TEST1
TEST2
USB30_MRX_DTX_P0
USB30_MRX_DTX_N0
USB30_MTX_DRX_P0
USB30_MTX_DRX_N0
USB_OC1#
USB20_P0
USB20_N0
USB_OC1#
USB20_P1
USB20_N1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
USB20_N4
USB20_P4
USB20_N10
USB20_P10
LAN_CLKREQ#_1
MINI1_CLKREQ#
USB_OC0#
FCH_GPIO190
FCH_GPIO191
FCH_GPIO189
USB20_N11
USB20_P11
USB_OC2#
USB_OC2#
EC_GA2032
EC_RSMRST#32
H_THERMTRIP#8
SLP_S3#32
SLP_S5#32
FCH_PWRGD32
PBTN_OUT#32
FCH_SCLK011,12,35
FCH_SDATA011,12,35
EC_SMI#32
EC_SCI#32
HDA_SYNC_AUDIO33
HDA_RST_AUDIO#33
HDA_SDIN033
HDA_SDOUT_AUDIO33
HDA_BITCLK_AUDIO33
USB_OC0#30
EC_PWM2 16
EC_KBRST#32
VGA_PD16
FCH_PCIE_WAKE#31,32,35
EC_LID_OUT#32
APU_SID 6,8
APU_SIC 6,8
USB30_MRX_DTX_N0 30
USB30_MRX_DTX_P0 30
USB30_MTX_C_DRX_N0 30
USB30_MTX_C_DRX_P0 30
USB_OC1#33
USB20_P0 30
USB20_N0 30
USB20_P1 33
USB20_N1 33
USB20_N2 27
USB20_P2 27
USB20_N3 35
USB20_P3 35
USB20_N4 34
USB20_P4 34
USB20_N10 30
USB20_P10 30
LAN_CLKREQ#31
MINI1_CLKREQ#35
USB20_P11 33
USB20_N11 33
USB_OC2#30
+FCH_VDD_11_SSUSB_S
+3VS
+3VALW
+3VS
+3VALW
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
Hudson-M2/M3-ACPI/USB/EC
Custom
14 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
PCIE_RST2 : Reset PCIE device on Hudson2
VGA_PD: Support MLDAC power
save if connect
0: MLDAC power on
1: MLDAC power off
EHCI CTL
DEV 22, Fn 2
EHCI CTL
DEV 19, Fn 2
EHCI CTL
DEV 18, Fn 2
SM bus 0-->S0 PWR domain
S
M bus 1-->S5 PWR domain
THERMTRIP:
Need level shift from +3VALW to +1.5V
<Disable CTL of M2>
x
HCI CTL
DEV 16, Fn 1
Hudson-M2 Hudson-M3
xHCI CTL
DEV 16, Fn 0
Hudson-M2/M3
Hudson-M2/M3
Modify 20101111
For PCIE device reset on FS1
(GFX,GLAN,WLAN,LVDS Travis)
For FCH internal debug use
On board
USB Conn
xHCI CTL
DEV 16, Fn 0
xHCI CTL
DEV 16, Fn 1
Hudson-M3
USB1
USB2
CMOS
WLAN(BT)
CardReder
USB3
Add Project ID Table
201011301600
GPIO189 (use VGA) L(NO)
R44
H(YES)
R43
Project SKU ID
GPIO191
GPIO190 (use PX)
L(15")
R48
H(17")
R47
L(NO)
R46
H(YES)
R45
USB4
For USB 3.0
T29
R863 11.8K_0402_1%
1 2
R865 1K_0402_1%
M3@
1 2
R869 33_0402_5%
1 2
R889 2.2K_0402_5%
@
1 2
R874 2.2K_0402_5%
1 2
R56 100K_0402_5%
1 2
R871 10K_0402_5%
1 2
USB OC GPIO ACPI / WAKE UP EVENTSHD AUDIO
USB MISCUSB 1.1USB 2.0USB 3.0
EMBEDDED CTRL
HUDSON-2
U25D
HUDSON-M2_FCBGA656
M2@
SCL2/GPIO193
H19
SDA2/GPIO194
G19
SCL3_LV/GPIO195
G22
SDA3_LV/GPIO196
G21
EC_PWM0/EC_TIMER 0/GPIO197
E22
EC_PWM1/EC_TIMER 1/GPIO198
H22
EC_PWM2/EC_TIMER 2/WOL_EN/GPIO199
J22
EC_PWM3/EC_TIMER 3/GPIO200
H21
KSI_0/GPIO201
K21
KSI_1/GPIO202
K22
KSI_2/GPIO203
F22
KSI_3/GPIO204
F24
KSI_4/GPIO205
E24
KSI_5/GPIO206
B23
KSI_6/GPIO207
C24
KSI_7/GPIO208
F18
PS2_DAT/SDA4/GPIO187
K19
PS2_CLK/CEC/SCL4/GPIO188
J19
SPI_CS2#/GBE_STAT2/GPIO166
J21
PS2KB_DAT/GPIO189
D21
PS2KB_CLK/GPIO190
C20
PS2M_DAT/GPIO191
D23
PS2M_CLK/GPIO192
C22
KSO_0/GPIO209
F21
KSO_1/GPIO210
E20
KSO_2/GPIO211
F20
KSO_3/GPIO212
A22
KSO_4/GPIO213
E18
KSO_5/GPIO214
A20
KSO_6/GPIO215
J18
KSO_7/GPIO216
H18
KSO_8/GPIO217
G18
KSO_9/GPIO218
B21
KSO_10/GPIO219
K18
KSO_11/GPIO220
D19
KSO_12/GPIO221
A18
KSO_13/GPIO222
C18
KSO_14/GPIO223
B19
KSO_15/GPIO224
B17
KSO_16/GPIO225
A24
KSO_17/GPIO226
D17
AZ_BITCLK
AB3
AZ_SDOUT
AB1
AZ_SDIN0/GPIO167
AA2
AZ_SDIN1/GPIO168
Y5
AZ_SDIN2/GPIO169
Y3
AZ_SDIN3/GPIO170
Y1
AZ_SYNC
AD6
AZ_RST#
AE4
BLINK/USB_OC7#/GEVENT18#
M7
USB_OC6#/IR_TX1/GEVENT6#
R8
USB_OC5#/IR_TX0/GEVENT17#
T1
USB_OC4#/IR_RX0/GEVENT16#
P6
USB_OC3#/AC_PRES/TDO/GEVENT15#
F5
USB_OC2#/TCK/GEVENT14#
P5
USB_OC1#/TDI/GEVENT13#
J7
USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12 #
T8
CLK_REQ4#/SATA_IS0#/GPIO64
AG24
CLK_REQ3#/SATA_IS1#/GPIO63
AE24
SMARTVOLT1/SATA_IS2#/GPIO50
AE26
CLK_REQ0#/SATA_IS3#/GPIO60
AF22
SATA_IS4#/FANOUT3/GPIO55
AH17
SATA_IS5#/FANIN3/GPIO59
AG18
SPKR/GPIO66
AF24
SCL0/GPIO43
AD26
SDA0/GPIO47
AD25
SCL1/GPIO227
T7
SDA1/GPIO228
R7
CLK_REQ2#/FANIN4/GPIO62
AG25
CLK_REQ1#/FANOUT4/GPIO61
AG22
IR_LED#/LLB#/GPIO184
J2
SMARTVOLT2/SHUTDOWN #/GPIO51
AG26
DDR3_RST#/GEVENT7#/VGA_PD
V8
GBE_LED0/GPIO183
W8
SPI_HOLD#/GBE_LED1/GEVENT9#
Y6
GBE_LED2/GEVENT10#
V10
GBE_STAT0/GEVENT11#
AA8
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT#
AF25
RSMRST#
U2
TEST0
T9
TEST1/TMS
T10
TEST2
V9
GA20IN/GEVENT0#
AE22
KBRST#/GEVENT1#
AG19
LPC_PME#/GEVENT3#
R9
LPC_SMI#/GEVENT23#
C26
LPC_PD#/GEVENT5#
T5
SYS_RESET#/GEVENT19#
U4
WAKE#/GEVENT8#
K1
IR_RX1/GEVENT20#
V7
THRMTRIP#/SMBALERT#/GEVEN T2#
R10
WD_PWRGD
AF19
PCIE_RST2#/PCI_PME#/GEVENT4#
AB6
RI#/GEVENT22#
R2
SPI_CS3#/GBE_STAT1/GEVENT21#
W7
SLP_S3#
T3
SLP_S5#
W2
PWR_BTN#
J4
PWR_GOOD
N7
USBCLK/14M_25M_48M_OSC
G8
USB_RCOMP
B9
USB_FSD1P/GPIO186
H1
USB_FSD1N
H3
USB_FSD0P/GPIO185
H6
USB_FSD0N
H5
USB_HSD13P
H10
USB_HSD13N
G10
USB_HSD12P
K10
USB_HSD12N
J12
USB_HSD11P
G12
USB_HSD11N
F12
USB_HSD10P
K12
USB_HSD10N
K13
USB_HSD9P
B11
USB_HSD9N
D11
USB_HSD8P
E10
USB_HSD8N
F10
USB_HSD7P
C10
USB_HSD7N
A10
USB_HSD6P
H9
USB_HSD6N
G9
USB_HSD5P
A8
USB_HSD5N
C8
USB_HSD4P
F8
USB_HSD4N
E8
USB_HSD3P
C6
USB_HSD3N
A6
USB_HSD2P
C5
USB_HSD2N
A5
USB_HSD1P
C1
USB_HSD1N
C3
USB_HSD0P
E1
USB_HSD0N
E3
USBSS_CALRP
C16
USBSS_CALRN
A16
USB_SS_TX3P
A14
USB_SS_TX3N
C14
USB_SS_RX3P
C12
USB_SS_RX3N
A12
USB_SS_TX2P
D15
USB_SS_TX2N
B15
USB_SS_RX2P
E14
USB_SS_RX2N
F14
USB_SS_TX1P
F15
USB_SS_TX1N
G15
USB_SS_RX1P
H13
USB_SS_RX1N
G13
USB_SS_TX0P
J16
USB_SS_TX0N
H16
USB_SS_RX0P
J15
USB_SS_RX0N
K15
R877 10K_0402_5%
1 2
R45
8.2K_0402_5%
@
12
R884 2.2K_0402_5%
1 2
R888 10K_0402_5%
@
1 2
R43
8.2K_0402_5%
@
12
R54 100K_0402_5%
1 2
R880 2.2K_0402_5%
1 2
R872 10K_0402_5%
1 2
R55 100K_0402_5%
1 2
R886 10K_0402_5%
@
1 2
R867 33_0402_5%
1 2
R18 10K_0402_5%
@
1 2
R81 0_0402_5%
1 2
T37
R870 10K_0402_5%
1 2
R1813 10K_0402_5%
1 2
R885 10K_0402_5%
@
1 2
R882 8.2K_0402_5%
@
1 2
R881 2.2K_0402_5%
1 2
R44
8.2K_0402_5%
@
12
C39 0.1U_0402_16V7K
M3@
1 2
R866 33_0402_5%
1 2
R47
8.2K_0402_5%
@
12
R48
8.2K_0402_5%
@
12
C37 0.1U_0402_16V7K
M3@
1 2
R876 2.2K_0402_5%
1 2
R878 10K_0402_5%@
1 2
R868 33_0402_5%
1 2
R862 10K_0402 _5%
1 2
R890 2.2K_0402_5%
@
1 2
R46
8.2K_0402_5%
@
12
R887 2.2K_0402_5%
@
1 2
T36
R940 8.2K_0402_5%
1 2
R864 1K_0402_1%M3@
1 2
T27
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
GBE_MDIO
FCH_SPI_MISO
AUXCAL
GBE_PHY_INTR
FCH_SPI_MOSI
GBE_COL
GBE_CRS
GBE_RXERR
SATA_CALRP
SATA_CALRN
FCH_CRT_HPD
BT_ON
SATA_LED#
FCH_SPI_CS1#
FCH_SPI_WP#
WL_OFF#
FCH_SPI_CLK_R
FCH_SPI_WP#
FCH_SPI_MISO
FCH_SPI_CS1#
FCH_SPI_HOLD#
FCH_SPI_CLK
FCH_SPI_MOSI
FCH_CRT_HPD
FCH_SPI_CLK
GBE_COL
GBE_CRS
GBE_RXERR
GBE_MDIO
GBE_PHY_INTR
FCH_SPI_CLK
FCH_CRT_HPD 10
ML_VGA_AUXP_C 8
ML_VGA_AUXN_C 8
SATA_STX_DRX_P029
SATA_STX_DRX_N029
SATA_LED#35
FCH_CRT_R 27
FCH_CRT_G 27
FCH_CRT_B 27
FCH_CRT_HSYNC 27
FCH_CRT_VSYNC 27
FCH_CRT_DDC_SDA 27
FCH_CRT_DDC_SCL 27
ML_VGA_TXP2 8
ML_VGA_TXN2 8
ML_VGA_TXP3 8
ML_VGA_TXN3 8
SATA_DTX_C_SRX_P029
SATA_DTX_C_SRX_N029
BT_ON35
ML_VGA_TXP0 8
ML_VGA_TXN0 8
ML_VGA_TXP1 8
ML_VGA_TXN1 8
WL_OFF#35
SATA_DTX_C_SRX_P129
SATA_STX_DRX_P129
SATA_DTX_C_SRX_N129
SATA_STX_DRX_N129
SATA_STX_DRX_P229
SATA_STX_DRX_N229
SATA_DTX_C_SRX_P229
SATA_DTX_C_SRX_N229
+VDDAN_11_ML
+AVDD_SATA
+3VS
+FCH_VDDAN_33_DAC_R
+3VALW
+3VALW
+3VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
Hudson-M2/M3-SATA/GBE/HWM
Custom
15 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
HDD1
ODD
SYS BIOS ROM
Add SYS BIOS ROM
20101111
Change to PD 20101112
Add for EMI 201011291330
HDD2
C4660.1U_0402_16V4Z
@
12
R7 10K_0402_5%
1 2
U28
MX25L1606EM2I-12G SOP 8P
SA000041N00
@
CS#
1
SO
2
WP#
3
GND
4
SI
5
SCLK
6
HOLD#
7
VCC
8
R626 1K_0402_5%
@
1 2
R895 10K_0402_5%
1 2
R14 10K_0402_5%
1 2
R896 150_0402_1%
1 2
R897 150_0402_1%
1 2
R934 10K_0402_5%
@
1 2
R10 10K_0402_5%
1 2
C23
10P_0402_50V8J
@
1 2
R894 10K_0402_5%
1 2
R12 10K_0402_5%
1 2
R13 10K_0402_5%
1 2
R891 10K_0402_5%
1 2
R892 10K_0402_5%
1 2
R16 10K_0402_5%
1 2
R36
10_0402_5%
@
1 2
R893 10K_0402_5%
1 2
R6 10K_0402_5%
1 2
R5 10K_0402_5%
1 2
R90410K_0402_5%
12
R35 0_0402_5%@
1 2
R898 150_0402_1%
1 2
HUDSON-2
SERIAL ATA
SD CARDGBE LANSPI ROMVGA DACVGA MAINLINK
HW MONITOR
U25B
HUDSON-M2_FCBGA656
M2@
SATA_TX0P
AK19
SATA_TX0N
AM19
SATA_RX0N
AL20
SATA_RX0P
AN20
SATA_TX1P
AN22
SATA_TX1N
AL22
SATA_RX1N
AH20
SATA_RX1P
AJ20
SATA_TX2P
AJ22
SATA_TX2N
AH22
SATA_RX2N
AM23
SATA_RX2P
AK23
SATA_TX3P
AH24
SATA_TX3N
AJ24
SATA_RX3N
AN24
SATA_RX3P
AL24
SATA_TX4P
AL26
SATA_TX4N
AN26
SATA_RX4N
AJ26
SATA_RX4P
AH26
SATA_TX5P
AN29
SATA_TX5N
AL28
SATA_RX5N
AK27
SATA_RX5P
AM27
NC6
AL29
NC7
AN31
NC8
AL31
NC9
AL33
NC10
AH33
NC11
AH31
NC12
AJ33
NC13
AJ31
SATA_X2
AG21
SATA_X1
AF21
SATA_CALRP
AF28
SATA_CALRN
AF27
FANOUT0/GPIO52
AH16
FANOUT1/GPIO53
AM15
FANOUT2/GPIO54
AJ16
FANIN0/GPIO56
AK15
FANIN1/GPIO57
AN16
FANIN2/GPIO58
AL16
TEMPIN0/GPIO171
K6
TEMPIN1/GPIO172
K5
TEMPIN2/GPIO173
K3
TEMPIN3/TALERT#/GPIO174
M6
NC1
AG16
NC2
AH10
NC3
A28
NC4
G27
NC5
L4
VIN0/GPIO175
N2
VIN1/GPIO176
M3
VIN2/SDATI_1/GPIO177
L2
VIN3/SDATO_1/GPIO178
N4
VIN4/SLOAD_1/GPIO179
P1
VIN5/SCLK_1/GPIO180
P3
VIN6/GBE_STAT3/GPIO181
M1
VIN7/GBE_LED3/GPIO182
M5
SD_CLK/SCLK_2/GPIO73
AL14
SD_CMD/SLOAD_2/GPIO74
AN14
SD_CD/GPIO75
AJ12
SD_WP/GPIO76
AH12
SD_DATA0/SDATI_2/GPIO77
AK13
SD_DATA1/SDATO_2/GPIO78
AM13
SD_DATA2/GPIO79
AH15
SD_DATA3/GPIO80
AJ14
GBE_COL
AC4
GBE_CRS
AD3
GBE_MDCK
AD9
GBE_MDIO
W10
GBE_RXCLK
AB8
GBE_RXD3
AH7
GBE_RXD2
AF7
GBE_RXD1
AE7
GBE_RXD0
AD7
GBE_RXCTL/RXDV
AG8
GBE_RXERR
AD1
GBE_TXCLK
AB7
GBE_TXD3
AF9
GBE_TXD2
AG6
GBE_TXD1
AE8
GBE_TXD0
AD8
GBE_TXCTL/TXEN
AB9
GBE_PHY_PD
AC2
GBE_PHY_RST#
AA7
GBE_PHY_INTR
W9
SPI_DI/GPIO164
V6
SPI_DO/GPIO163
V5
SPI_CLK/GPIO162
V3
SPI_CS1#/GPIO165
T6
ROM_RST#/SPI_WP#/GPIO161
V1
VGA_RED
L30
VGA_GREEN
L32
VGA_BLUE
M29
VGA_DAC_RSET
K31
VGA_HSYNC/GPO68
M28
VGA_VSYNC/GPO69
N30
VGA_DDC_SDA/GPO70
M33
VGA_DDC_SCL/GPO71
N32
ML_VGA_HPD/GPIO229
C29
ML_VGA_L0P
T31
ML_VGA_L0N
T33
ML_VGA_L1P
T29
ML_VGA_L1N
T28
ML_VGA_L2P
R32
ML_VGA_L2N
R30
ML_VGA_L3P
P29
ML_VGA_L3N
P28
AUXCAL
U28
AUX_VGA_CH_P
V28
AUX_VGA_CH_N
V29
SATA_ACT#/GPIO67
AD22
R901 715_0402_1%
1 2
R903 100_0402_1%
1 2
R935 10K_0402_5%
@
1 2
R9 10K_0402_5%
1 2
T28
R9001K_0402_1%
12
R8991K_0402_1%
12
R902 10K_0402_5%
1 2
R11 10K_0402_5%@
1 2
R15 10K_0402_5%
1 2
R8 10K_0402_5%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
VGA_PD#
VGA_PD#
VGA_PD#
PCI_CLK113
PCI_CLK313
PCI_CLK413
LPC_CLK0_EC13,32
LPC_CLK113
EC_PWM214
RTC_CLK13,32
PCI_AD2713
PCI_AD2613
PCI_AD2513
PCI_AD2413
PCI_AD2313
VGA_PD14
+3VALW+3VALW+3 VALW+3VALW+3VS+3VS+3VS
+3VS +FCH_VDDAN_33_DAC_R
+1.1VS +FCH_VDDAN_11_MLDAC
+3VS
+FCH_VDDAN_33_DAC
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANS FERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSEN T OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
QBL70 LA-7553P
0.22
Hudson-M2/M3-STRAP
Custom
16 51Friday, April 29, 2011
2010/08/04 2010/08/04
Compal Electronics, Inc.
CLKGEN
ENABLED
S5 PLUS
MODE
ENABLED
DEFAULT
CLKGEN
DISABLE
PULL
LOW
PULL
HIGH
DEFAULT
RTC_CLKLPC_CLK1
LPC ROM
SPI ROM
EC_PWM2
EC
ENABLED
EC
DISABLED
DEFAULT
PCI_CLK1
ALLOW
PCIE GEN2
PCI_CLK3
NON_FUSION
CLOCK MODE
DEFAULT
IGNORE
DEBUG
STRAP
USE
DEBUG
STRAPS
PCI_CLK4 LPC_CLK0
DEFAULT
FORCE
PCIE GEN1
FUSION
CLOCK
MODE
DEFAULT DEFAULT
S5 PLUS
MODE
DISABLED
STRAP PINS
PCI_AD25 PCI_AD24
USE EEPROM
PCIE STRAPS
USE DEFAULT
PCIE STRAPS
DEFAULTD EFAULT
USE FC
PLL
DISABLE
ILA
AUTORUN
USE PCI
PLL
DEFAULT
BYPASS
FC PLL
PULL
HIGH
DEFAULT
BYPASS
PCI PLL
PCI_AD27PCI_AD26
PULL
LOW
DEFAULT
FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PCI_AD23
DEBUG STRAPS
ENABLE
ILA
AUTORUN
DISABLE PCI
MEM BOOT
ENABLE PCI
MEM BOOT
If support ML DAC power down when no VGA plug
Check VGA_PD states
AO3413 Vgs(max)=1V
VGA_PD: Support MLDAC power
save if not connect
0: MLDAC power on
1: MLDAC power off
220 ohm
2
20 ohm
30mil
30mil
R927 2.2K_0402_5%
@
12
R917 1 0K_0402_5%
12
R929 2.2K_0402_5%
@
12
R916
100K_0402_5%
12
Q40
AP2301GN-HF_SOT23-3
@
2
3 1
R914
100K_0402_5%
12
R918 1 0K_0402_5%
12
R906 10K_0402 _5%
@
12
R925
2.2K_0402_5%
1 2
C1212
1U_0402_6.3V4Z
1
2
R919 1 0K_0402_5%
12
R921 2 .2K_0402_5%
@
12
R913 0_0402_5%
@
1 2
R915 1 0K_0402_5%
@
12
R905 10K_0402_5%
12
R912 0_0402_5%
1 2
Q41A
DMN66D0LDW-7_SOT363-6
61
2
R924
0_0402_5%
@
1 2
R909 10K_0402 _5%
12
L47
FBMA-L11-201209-221LMA30T_0805
1 2
C1211
1U_0402_6.3V4Z
@
1
2
R922 2 .2K_0402_5%
@
12
R920 1 0K_0402_5%
@
12
Q39
AP2301GN-HF_SOT23-3
@
2
3 1
R907 10K_0402 _5%
@
12
R928 2.2K_0402_5%
@
12
R930 2.2K_0402_5%
@
12
R910 10K_0402 _5%
12
R923
1K_0402_5%
@
1 2
C1210
0.1U_0402_16V4Z
1
2
R926 2.2K_0402_5%
@
12
R911 10K_0402 _5%
12
L48
FBMA-L11-201209-221LMA30T_0805
@
1 2
Q41B
DMN66D0LDW-7_SOT363-6
34
5
C1209
2.2U_0603_6.3V4Z
1
2
R908 10K_0402 _5%
@
12
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