LA-5751P
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5751
0.3
Cover Sheet
Custom
1 51Thursday, October 29, 2009
2008/03/25 2008/04/
Compal Electronics,Ltd.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5751
0.3
Cover Sheet
Custom
1 51Thursday, October 29, 2009
2008/03/25 2008/04/
Compal Electronics,Ltd.
Title
Size Document Number Rev
Date: Sheet
of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
LA-5751
0.3
Cover Sheet
Custom
1 51Thursday, October 29, 2009
2008/03/25 2008/04/
Compal Electronics,Ltd.
REV:0.3
Schematics Document
Arrandale
Compal Confidential
with Intel IBEX PEAK-M core logic
NIWE1
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
MB Block Diagram
Custom
2 51Thursday, October 29, 2009
2008/03/24 2008/04/
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
MB Block Diagram
Custom
2 51Thursday, October 29, 2009
2008/03/24 2008/04/
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
MB Block Diagram
Custom
2 51Thursday, October 29, 2009
2008/03/24 2008/04/
Compal Electronics, Inc.
LA-5751
File Name :
Compal confidential
BlueTooth CONN
CMOS Camera
CONEXTAN
CX20671
Audio Codec
2Channel Speaker
LPC BUS
CRT Connector
AZALIA
RJ45 CONN
Int.KBD
ENE KB926D
Touch Pad
BANK 0, 1, 2, 3
DDR3-SO-DIMM X2
DDR3-800(1.5V)
Dual Channel
14*USB2.0
LVDS
Connector
EC
page26
page27
page29
page30
page34
page35
page36
page35
page37
page27
page33
page33
page 10,11
Clock Generator
page12
page5~9
page 13~18
Arrandale
Socket-rPGA989
DMI *4
FCBGA 951
Intel Ibex Peak M
page32
6*PCI-E BUS
page28
PCI Express
Mini card Slot 1
NVidia N11M-GE1
PCI-E X16
6*SATA serial
PCI Express
Mini card Slot 2
HDMI
DDR3-1066(1.5V)
RTL8103EL/8111DL
RTM890N
VRAM 64*16
page23
page19~23
CONN
page24
DDR3*4
10/100/1G LAN
USB CONN X1(Right)
page37
ENE UB6250/52
MS/MS
pro/SD/SD
pro/mmc/XD
Analog MIC_Int
page33
HP X 1+
MIC_Ext X1
New Card X1
page28
WWAN
page28
SIM Card
POWER BD:
POWER BTN
NOVO BTN
POWER MANAGE BTN
UP TO 8G
page38
ESATA HDD AND USB CONN
37.5mm*37.5mm
25mm*25mm
SPI ROM
SPI ROM
BIOS
page13
FDI *8
100MHz
2.7GT/s
Intel
(UMA/DIS)
level shift IC
page25
ASM1442
page28
page28
page32
page37
USB PORT X1(Left)
page37
USB(WWAN)
SATA HDD CONN
SATA ODD CONN
Card Reader/Audio Jack SB
CONN
CAP SENSOR BD:
VOLUME UP
VOLUME DOWN
MUTE
AUDIO ENHANCE
BUTTON & LED
CARD READER BD:
ENE UB6250/52
HP JACK
MIC JACK
EC
EMC1403
Thermal Sensor
page31
ZZZ1
14W_PCB_LA5751P
ZZZ1
14W_PCB_LA5751P
ZZZ
X76_H512
HYN@
ZZZ
X76_H512
HYN@
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
MB Notes List
B
3 51Thursday, October 29, 2009
2008/03/24 2008/04/
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
MB Notes List
B
3 51Thursday, October 29, 2009
2008/03/24 2008/04/
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
MB Notes List
B
3 51Thursday, October 29, 2009
2008/03/24 2008/04/
Compal Electronics, Inc.
LA-5751
O
X
S3
+3VS
X
X
+3VALW
+5VS
O
+CPU_CORE
OO
X
X X
+VCCP
power
plane
O
O
O
O
X
S5 S4/ Battery only
X X X
+B
State
+1.5VS
+1.5V
S5 S4/AC & Battery
don't exist
S5 S4/AC
+5VALW
S0
O
O
+VGA_CORE
+1.8VS
DDR3 Voltage Rails
+0.75VS
Cap sensor
board
X
X
XX
NEW
CARD
PCH
X X
X
X
N10x
Thermal
Sensor
X
X
X
SML0CLK
SML0DATA
PCH
X
+3VS
X X
SMB_EC_CK2
SOURCE
KB926
RAM M2 BATT KE926 SODIMM CLK CHIP
SMBUS Control Table
SMBCLK
SMBDATA
PCH
WLAN
WWAN
SMB_EC_DA2
SMB_EC_CK1
SMB_EC_DA1
N10x
X V
V V
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
KB926
SML1CLK
SML1DATA
PCH
XXX X X X X X
1 0 1 0 0 1 0 0A4
I2C / SMBUS ADDRESSING
1 0 1 0 0 0 0 0
D2
A0
CLOCK GENERATOR (EXT.)
HEX
DDR SO-DIMM 1
ADDRESS
DDR SO-DIMM 0
1 1 0 1 0 0 1 0
DEVICE
5
BT
3G
6
4
CMOS
RIGHT SIDE
RIGHT SIDE0
DEVICEPORT
3
2
11
NEW CARD
USB PORT LIST
WIRELESS8
10
1WLAN
NEW CARD
CARD READER
3G
9
7
LAN
LEFT SIDE
6
4
DEVICEPORT
5
3
2
PCIE PORT LIST
1
12
13
7
8
+1.05VS
X
V
X
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
+3VALW
V
+3VALW
X X
+3VALW
V
+3VS
+3VS
V
+3VS
V
V
+3VS
LEFT SIDE
UMA@
DIS@
UMA only (Arrandale)
SKU
Arrandale(dGPU)
Arrandale(iGPU)
DIS@
UMA@
DIS only
UMA only
DIS only (Arrandale)
@ FUNCTION
45@
X76@ X76 BOM
45 BOM
NON-USE
BT@
3G@
CAP@
CMOS@
HDMI@
Blue Tooth function
3G function (WWAN)
CAP Sensor function
CMOS CAMERA function
HDMI function (UMA or DIS)
DescriptionStructure
100@
GIGA@
10/100 LAN function
GIGA LAN function
UMA_HDMI@ HDMI function (UMA only)
ESATA@ E-SATA function
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
VGA Notes List
B
4 51Thursday, October 29, 2009
2009/03/16 2010/03/15
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
VGA Notes List
B
4 51Thursday, October 29, 2009
2009/03/16 2010/03/15
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
VGA Notes List
B
4 51Thursday, October 29, 2009
2009/03/16 2010/03/15
Compal Electronics, Inc.
LA-5751
(+3VS)
FBVDDQ
(+VGA_CORE)
(1.05VS)
tNVVDD
PEX_VDD can ramp up any time
VDD33
NVVDD
The ramp time for any rail must be more than 40us
(1.5VS)
Performance Mode P0 TDP at Tj = 102 C* (DDR3)VGA and DDR3 Voltage Rails (N11x GPIO)
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7
GPIO8
GPIO9
GPIO10
GPIO11
GPIO12
GPIO13
GPIO14
IN
OUT
OUT
OUT
OUT
OUT
OUT
I/O
OUT
OUT
I/O
IN
OUT
OUT
Panel Back-Light brightness(PWM capable)
Panel Power Enable
Panel Back-Light On/Off (PWM)
GPU VID0
GPU VID1
N/A
-
H
H
H
Hot plug detect for IFP link C
GPIO I/O ACTIVE Function Description
N/A
-
-
-
IN
OUT
IN
IN
IN
GPIO15
GPIO16
GPIO17
GPIO18
GPIO19
-
Products
GPU Mem NVCLK
/MCLK NVVDD
FBVDD
FBVDDQ PCI Express I/O and
PLLVDD
I/O and
PLLVDD
Other
(3.3V)(1.05V)(1.8V)
(1.05V)
(1.5V)(1.5V)
(GPU+Mem)
(4) (1,5) (6)
(V) (A) (W) (A) (W) (A) (W) (W)(mA) (W) (W) (W)(mA) (mA) (mA)
N11M-GE1
64bit
512MB
DDR3
14.02
(W) (W)
2.16
(MHz)
TBD TBD 12.9 12.26 0.66 0.99 1.3 1.95 530 84 0.15 38 0.130.56 140 0.15
PEX_VDD
(1.8VS)IFPAB_IOVDD
tNV-IFPAB_IOVDD
tNV-FBVDDQ
Power Sequence
Deep P12
P-State
P0
P8
GPIO6GPIO5
0.8V
GPU_VID1
0
GPU_VID0 VGA_CORE
1.03V
0.85V
1
0
N11M-GE1/LP1
(40nm)
0x0A7D
Device ID
1
0
1
N/A
N/A
N/A
N/A
-
N/A
N/A
Reserve 10K pull low.
Reserve 10K pull low.
N/A
N/A
PAD
N/A
N/A
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XDP_TRST#
XDP_TDO
COMP3
COMP2
COMP1
COMP0
TP_SKTOCC#
H_PECI_ISO
H_THERMTRIP#
H_PM_SYNC_R
VCCPWRGOOD_0
VDDPWRGOOD_R
PLT_RST#_R
SM_RCOMP0
SM_RCOMP1
SM_RCOMP2
PM_EXTTS#0
PM_EXTTS#1
PM_EXTTS#0
SM_RCOMP0
SM_RCOMP1
H_CPURST#_R
SM_RCOMP2
PM_EXTTS#1
CLK_CPU_BCLK#
CLK_EXP#
CLK_EXP
CLK_CPU_BCLK
XDP_PREQ#
XDP_TDI
XDP_TMS
XDP_TCK
H_CATERR#
VCCPWRGOOD_1
XDP_BPM#3
XDP_BPM#4
XDP_BPM#0
XDP_BPM#2
XDP_BPM#5
XDP_BPM#1
XDP_BPM#6
XDP_BPM#7
H_PROCHOT#
XDP_DBRESET#
XDP_PREQ#
XDP_TMS
XDP_TDO
XDP_TDI
XDP_DBRESET#
XDP_TCK
XDP_TRST#
VDDPWRGOOD_RDRAM_PWRGD
DRAMRST_CNTRL_R
DRAMRST# SM_DRAMRST#
SM_DRAMRST#
VTT_POK
CLK_CPU_ITP#
CLK_CPU_ITP
XDP_PRDY#
VCCP_POK
S3_0.75V_EN
CLK_CPU_BCLK# <16>
CLK_CPU_BCLK <16>
CLK_EXP# <14>
CLK_EXP <14>
H_PECI<16>
H_PROCHOT#<34,48>
H_PM_SYNC<15>
H_THERMTRIP#<16>
PM_DRAM_PWRGD<15>
BUF_PLT_RST#<16,19,28,29>
H_CPUPWRGD<16>
PM_EXTTS#1_R <10,11>
VCCP_POK<46>
DRAMRST_CNTRL_EC<34>
DRAMRST#<10,11>
DRAMRST_CNTRL_PCH<16>
VCCP_POK<46>
S3_0.75V_EN <44>
+VCCP
+VCCP
+VCCP
+VCCP
+3VS
+3VALW
+1.5V
+1.5V
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(1/5)-Thermal/XDP
Custom
5 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(1/5)-Thermal/XDP
Custom
5 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(1/5)-Thermal/XDP
Custom
5 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Layout Note:Please these
resistors near Processor
DDR3 Compensation Signals
Layout rule
：
10mil width trace
length < 0.5", spacing 20mil
pins unused by
Clarksfield on the
rPGA989 Package
CHECK INTEL DOCUMENT #385422
Debug Port Design Guide Rev1.3
5
EC GPIO CONTROL
6
PCH GPIO CONTROL
DDR3 CONNECTER
3
3
For Intel S3 Power Reduction. For Intel S3 Power Reduction.
FROM POWER VTT
POWER GOOD SIGNAL
R137
1K_0402_5%@
R137
1K_0402_5%@
1 2
R187
0_0402_5%
R187
0_0402_5%
1 2
R569 68_0402_5%R569 68_0402_5%
12
T19 PADT19 PAD
R138 51_0402_1%@R138 51_0402_1%@
1 2
G
D
S
Q42
2N7002_SOT23
G
D
S
Q42
2N7002_SOT23
2
13
R566 24.9_0402_1%R566 24.9_0402_1%
1 2
R281 0_0402_5%R281 0_0402_5%
1 2
R301
1K_0402_1%
R301
1K_0402_1%
1 2
R193
1.1K_0402_1%
@
R193
1.1K_0402_1%
@
12
R55749.9_0402_1% R55749.9_0402_1%
1 2
T17 PADT17 PAD
C338
0.01U_0402_16V7K
C338
0.01U_0402_16V7K
1
2
R190
0_0402_5%
R190
0_0402_5%
1 2
G
D
S
Q27
2N7002_SOT23
G
D
S
Q27
2N7002_SOT23
2
1 3
R54849.9_0402_1% R54849.9_0402_1%
1 2
R195
1.5K_0402_1%
R195
1.5K_0402_1%
1 2
R191
0_0402_5%
R191
0_0402_5%
1 2
T18 PADT18 PAD
R186
750_0402_1%
R186
750_0402_1%
12
R567 100_0402_1%R567 100_0402_1%
1 2
R282 0_0402_5%@R282 0_0402_5%@
1 2
R565 130_0402_1%R565 130_0402_1%
1 2
R564 0_0402_5%R564 0_0402_5%
1 2
R184
1K_0402_1%
R184
1K_0402_1%
12
R56020_0402_1% R56020_0402_1%
1 2
R57 51_0402_1%@R57 51_0402_1%@
1 2
R556 51_0402_1%@R556 51_0402_1%@
1 2
R192
3K_0402_1%
@
R192
3K_0402_1%
@
12
R283 100K_0402_5%R283 100K_0402_5%
12
R13568_0402_5% R13568_0402_5%
12
U8
MC74VHC1G08DFT2G SC70 5P
U8
MC74VHC1G08DFT2G SC70 5P
B
2
A
1
Y
4
P
5
G
3
R555 0_0402_5%R555 0_0402_5%
12
R185
1.5K_0402_5%
R185
1.5K_0402_5%
1 2
R561 10K_0402_5%R561 10K_0402_5%
1 2
R16349.9_0402_1% R16349.9_0402_1%
12
R3000_0402_5%
@
R3000_0402_5%
@
1 2
R55820_0402_1% R55820_0402_1%
1 2
R610
10K_0402_5%
R610
10K_0402_5%
12
R134 51_0402_5%R134 51_0402_5%
1 2
R562 10K_0402_5%R562 10K_0402_5%
1 2
R136 51_0402_1%@R136 51_0402_1%@
1 2
CLOCKS
MISC THERMAL
PWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
IC,AUB_CFD_rPGA,R1P0
ME@
CLOCKS
MISC THERMAL
PWR MANAGEMENT
DDR3
MISC
JTAG & BPM
JCPU1B
IC,AUB_CFD_rPGA,R1P0
ME@
SM_RCOMP[1]
AM1
SM_RCOMP[2]
AN1
SM_DRAMRST#
F6
SM_RCOMP[0]
AL1
BCLK#
B16
BCLK
A16
BCLK_ITP#
AT30
BCLK_ITP
AR30
PEG_CLK#
D16
PEG_CLK
E16
DPLL_REF_SSCLK#
A17
DPLL_REF_SSCLK
A18
CATERR#
AK14
COMP3
AT23
PECI
AT15
PROCHOT#
AN26
THERMTRIP#
AK15
RESET_OBS#
AP26
VCCPWRGOOD_1
AN14
VCCPWRGOOD_0
AN27
SM_DRAMPWROK
AK13
VTTPWRGOOD
AM15
RSTIN#
AL14
PM_EXT_TS#[0]
AN15
PM_EXT_TS#[1]
AP15
PRDY#
AT28
PREQ#
AP27
TCK
AN28
TMS
AP28
TRST#
AT27
TDI
AT29
TDO
AR27
TDI_M
AR29
TDO_M
AP29
DBR#
AN25
BPM#[0]
AJ22
BPM#[1]
AK22
BPM#[2]
AK24
BPM#[3]
AJ24
BPM#[4]
AJ25
BPM#[5]
AH22
BPM#[6]
AK23
BPM#[7]
AH23
COMP2
AT24
PM_SYNC
AL15
TAPPWRGOOD
AM26
COMP1
G16
COMP0
AT26
SKTOCC#
AH24
R183
560_0402_5%
R183
560_0402_5%
1 2
R194
750_0402_1%
R194
750_0402_1%
12
R563 0_0402_5%R563 0_0402_5%
1 2
R133 51_0402_5%R133 51_0402_5%
1 2
R139
0_0402_5%
R139
0_0402_5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CFG0
CFG7
CFG4
CFG3
CFG0
CFG3
EXP_ICOMPI
EXP_RBIAS
CFG4
H_RSVD17_R
H_RSVD18_R
RSVD64_R
RSVD65_R
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N5
FDI_CTX_PRX_N6
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P1
FDI_CTX_PRX_P2
FDI_CTX_PRX_P3
FDI_CTX_PRX_P4
FDI_CTX_PRX_P5
FDI_CTX_PRX_P6
FDI_CTX_PRX_P7
FDI_LSYNC0
FDI_FSYNC0
FDI_LSYNC1
FDI_FSYNC1
FDI_INT
FDI_FSYNC0
FDI_LSYNC1
FDI_FSYNC1
FDI_INT
FDI_LSYNC0
PCIE_CRX_GTX_N15
PCIE_CRX_GTX_N10
PCIE_CRX_GTX_N14
PCIE_CRX_GTX_N0
PCIE_CRX_GTX_N8
PCIE_CRX_GTX_N6
PCIE_CRX_GTX_N7
PCIE_CRX_GTX_N4
PCIE_CRX_GTX_N3
PCIE_CRX_GTX_N9
PCIE_CRX_GTX_N12
PCIE_CRX_GTX_N13
PCIE_CRX_GTX_N5
PCIE_CRX_GTX_N2
PCIE_CRX_GTX_N1
PCIE_CRX_GTX_N11
PCIE_CRX_GTX_P15
PCIE_CRX_GTX_P14
PCIE_CRX_GTX_P8
PCIE_CRX_GTX_P4
PCIE_CRX_GTX_P0
PCIE_CRX_GTX_P10
PCIE_CRX_GTX_P7
PCIE_CRX_GTX_P9
PCIE_CRX_GTX_P13
PCIE_CRX_GTX_P6
PCIE_CRX_GTX_P3
PCIE_CRX_GTX_P12
PCIE_CRX_GTX_P5
PCIE_CRX_GTX_P11
PCIE_CRX_GTX_P1
PCIE_CRX_GTX_P2
PCIE_CTX_GRX_C_P0
PCIE_CTX_GRX_C_P10
PCIE_CTX_GRX_C_P15
PCIE_CTX_GRX_C_P14
PCIE_CTX_GRX_C_P8
PCIE_CTX_GRX_C_P6
PCIE_CTX_GRX_C_P4
PCIE_CTX_GRX_C_P13
PCIE_CTX_GRX_C_P7
PCIE_CTX_GRX_C_P1
PCIE_CTX_GRX_C_P9
PCIE_CTX_GRX_C_P12
PCIE_CTX_GRX_C_P3
PCIE_CTX_GRX_C_P5
PCIE_CTX_GRX_C_P2
PCIE_CTX_GRX_C_P11
PCIE_CTX_GRX_C_N14
PCIE_CTX_GRX_C_N15
PCIE_CTX_GRX_C_N0
PCIE_CTX_GRX_C_N10
PCIE_CTX_GRX_C_N6
PCIE_CTX_GRX_C_N8
PCIE_CTX_GRX_C_N13
PCIE_CTX_GRX_C_N4
PCIE_CTX_GRX_C_N9
PCIE_CTX_GRX_C_N5
PCIE_CTX_GRX_C_N2
PCIE_CTX_GRX_C_N12
PCIE_CTX_GRX_C_N7
PCIE_CTX_GRX_C_N1
PCIE_CTX_GRX_C_N11
PCIE_CTX_GRX_C_N3
PCIE_CTX_GRX_N15
PCIE_CTX_GRX_N0
PCIE_CTX_GRX_N14
PCIE_CTX_GRX_N10
PCIE_CTX_GRX_N6
PCIE_CTX_GRX_N8
PCIE_CTX_GRX_N13
PCIE_CTX_GRX_N4
PCIE_CTX_GRX_N9
PCIE_CTX_GRX_N5
PCIE_CTX_GRX_N2
PCIE_CTX_GRX_N12
PCIE_CTX_GRX_N7
PCIE_CTX_GRX_N1
PCIE_CTX_GRX_N11
PCIE_CTX_GRX_N3
PCIE_CTX_GRX_P7
PCIE_CTX_GRX_P0
PCIE_CTX_GRX_P10
PCIE_CTX_GRX_P15
PCIE_CTX_GRX_P14
PCIE_CTX_GRX_P3
PCIE_CTX_GRX_P5
PCIE_CTX_GRX_P8
PCIE_CTX_GRX_P6
PCIE_CTX_GRX_P4
PCIE_CTX_GRX_P13
PCIE_CTX_GRX_P2
PCIE_CTX_GRX_P11
PCIE_CTX_GRX_P1
PCIE_CTX_GRX_P9
PCIE_CTX_GRX_P12
DMI_CTX_PRX_P0<15>
DMI_CRX_PTX_P0<15>
DMI_CTX_PRX_N1<15>
DMI_CRX_PTX_N1<15>
DMI_CTX_PRX_P3<15>
DMI_CRX_PTX_P3<15>
DMI_CTX_PRX_P2<15>
DMI_CTX_PRX_N0<15>
DMI_CRX_PTX_N3<15>
DMI_CRX_PTX_P2<15>
DMI_CTX_PRX_N3<15>
DMI_CTX_PRX_P1<15>
DMI_CRX_PTX_N0<15>
DMI_CRX_PTX_N2<15>
DMI_CRX_PTX_P1<15>
DMI_CTX_PRX_N2<15>
PCIE_CTX_GRX_P[0..15] <19>
PCIE_CTX_GRX_N[0..15] <19>
PCIE_CRX_GTX_N[0..15] <19>
PCIE_CRX_GTX_P[0..15] <19>
FDI_CTX_PRX_N0<15>
FDI_CTX_PRX_N1<15>
FDI_CTX_PRX_N2<15>
FDI_CTX_PRX_N3<15>
FDI_CTX_PRX_N4<15>
FDI_CTX_PRX_N5<15>
FDI_CTX_PRX_N6<15>
FDI_CTX_PRX_N7<15>
FDI_CTX_PRX_P0<15>
FDI_CTX_PRX_P1<15>
FDI_CTX_PRX_P2<15>
FDI_CTX_PRX_P3<15>
FDI_CTX_PRX_P4<15>
FDI_CTX_PRX_P5<15>
FDI_CTX_PRX_P6<15>
FDI_CTX_PRX_P7<15>
FDI_FSYNC0<15>
FDI_FSYNC1<15>
FDI_INT<15>
FDI_LSYNC0<15>
FDI_LSYNC1<15>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(2/5)-DMI/PEG/FDI
Custom
6 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(2/5)-DMI/PEG/FDI
Custom
6 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(2/5)-DMI/PEG/FDI
Custom
6 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
CFG Straps for PROCESSOR
0: Bifurcation enabled
Not applicable for Clarksfield Processor
1: Single PEG
CFG0
PCI-Express Configuration Select
0: Lane Numbers Reversed
1: Normal Operation
CFG3
CFG3-PCI Express Static Lane Reversal
15 -> 0, 14 ->1, .....
Layout rule
：
trace
length < 0.5"
CFG[1:0] 11=1*16 PEG
10=2*8 PEG
FOR ES1 SAMPLE ONLY
0: Enabled; An external Display Port
1: Disabled; No Physical Display Port
CFG4
CFG4-Display Port Presence
attached to Embedded Display Port
device is connected to the Embedded
Display Port
DIS@
PCIE Lane Numbers Reversed
CFG3-PCI Express Static Lane Reversal
C561 0.1U_0402_10V6KC561 0.1U_0402_10V6K
1 2
C565 0.1U_0402_10V6KC565 0.1U_0402_10V6K
1 2
RESERVED
JCPU1E
IC,AUB_CFD_rPGA,R1P0
ME@
RESERVED
JCPU1E
IC,AUB_CFD_rPGA,R1P0
ME@
CFG[0]
AM30
CFG[1]
AM28
CFG[2]
AP31
CFG[3]
AL32
CFG[4]
AL30
CFG[5]
AM31
CFG[6]
AN29
CFG[7]
AM32
CFG[8]
AK32
CFG[9]
AK31
CFG[10]
AK28
CFG[11]
AJ28
CFG[12]
AN30
CFG[13]
AN32
CFG[14]
AJ32
CFG[15]
AJ29
CFG[16]
AJ30
CFG[17]
AK30
RSVD34
AH25
RSVD35
AK26
RSVD38
AJ26
RSVD_NCTF_42
AT3
RSVD39
AJ27
RSVD_NCTF_40
AP1
RSVD_NCTF_41
AT2
RSVD_NCTF_43
AR1
RSVD_TP_86
H16
RSVD45
AL28
RSVD46
AL29
RSVD47
AP30
RSVD48
AP32
RSVD49
AL27
RSVD50
AT31
RSVD51
AT32
RSVD52
AP33
RSVD53
AR33
RSVD_NCTF_54
AT33
RSVD_NCTF_55
AT34
RSVD_NCTF_56
AP35
RSVD_NCTF_57
AR35
RSVD58
AR32
RSVD_NCTF_30
C35
RSVD_NCTF_31
B35
RSVD_NCTF_28
A34
RSVD_NCTF_29
A33
RSVD27
J28
RSVD26
J29
RSVD16
A19
RSVD15
B19
RSVD17
A20
RSVD18
B20
RSVD20
T9
RSVD19
U9
RSVD22
AB9
RSVD21
AC9
RSVD_NCTF_23
C1
RSVD_NCTF_24
A3
RSVD_TP_66
AA5
RSVD_TP_67
AA4
RSVD_TP_68
R8
RSVD_TP_71
AA2
RSVD_TP_72
AA1
RSVD_TP_73
R9
RSVD_TP_69
AD3
RSVD_TP_74
AG7
RSVD_TP_70
AD2
RSVD_TP_75
AE3
RSVD_TP_76
V4
RSVD_TP_77
V5
RSVD_TP_78
N2
RSVD_TP_81
W3
RSVD_TP_82
W2
RSVD_TP_83
N3
RSVD_TP_79
AD5
RSVD_TP_84
AE5
RSVD_TP_80
AD7
RSVD_TP_85
AD9
RSVD36
AL26
RSVD_NCTF_37
AR2
RSVD1
AP25
RSVD2
AL25
RSVD3
AL24
RSVD4
AL22
RSVD5
AJ33
RSVD6
AG9
RSVD7
M27
RSVD8
L28
SA_DIMM_VREF
J17
SB_DIMM_VREF
H17
RSVD11
G25
RSVD12
G17
RSVD13
E31
RSVD14
E30
RSVD32
AJ13
RSVD33
AJ12
RSVD_TP_59
E15
RSVD_TP_60
F15
KEY
A2
RSVD62
D15
RSVD63
C15
RSVD64
AJ15
RSVD65
AH15
VSS
AP34
R61 3.01K_0402_1%R61 3.01K_0402_1%
1 2
C557 0.1U_0402_10V6KC557 0.1U_0402_10V6K
1 2
R545 750_0402_1%R545 750_0402_1%
1 2
R532 1K_0402_5%DIS@R532 1K_0402_5%DIS@
1 2
C527 0.1U_0402_10V6KC527 0.1U_0402_10V6K
1 2
C547 0.1U_0402_10V6KC547 0.1U_0402_10V6K
1 2
R547
0_0402_5%
@
R547
0_0402_5%
@
1 2
C562 0.1U_0402_10V6KC562 0.1U_0402_10V6K
1 2
R536 1K_0402_5%DIS@R536 1K_0402_5%DIS@
1 2
R58 3.01K_0402_1%
@
R58 3.01K_0402_1%
@
1 2
R533 1K_0402_5%DIS@R533 1K_0402_5%DIS@
1 2
C541 0.1U_0402_10V6KC541 0.1U_0402_10V6K
1 2
C536 0.1U_0402_10V6KC536 0.1U_0402_10V6K
1 2
C535 0.1U_0402_10V6KC535 0.1U_0402_10V6K
1 2
C560 0.1U_0402_10V6KC560 0.1U_0402_10V6K
1 2
C559 0.1U_0402_10V6KC559 0.1U_0402_10V6K
1 2
C533 0.1U_0402_10V6KC533 0.1U_0402_10V6K
1 2
R535 1K_0402_5%DIS@R535 1K_0402_5%DIS@
1 2
R188
0_0402_5%
@
R188
0_0402_5%
@
12
R546
0_0402_5%
@
R546
0_0402_5%
@
1 2
C543 0.1U_0402_10V6KC543 0.1U_0402_10V6K
1 2
R544 49.9_0402_1%R544 49.9_0402_1%
1 2
C532 0.1U_0402_10V6KC532 0.1U_0402_10V6K
1 2
C542 0.1U_0402_10V6KC542 0.1U_0402_10V6K
1 2
R189
0_0402_5%
@
R189
0_0402_5%
@
12
C534 0.1U_0402_10V6KC534 0.1U_0402_10V6K
1 2
C540 0.1U_0402_10V6KC540 0.1U_0402_10V6K
1 2
C558 0.1U_0402_10V6KC558 0.1U_0402_10V6K
1 2
C546 0.1U_0402_10V6KC546 0.1U_0402_10V6K
1 2
C556 0.1U_0402_10V6KC556 0.1U_0402_10V6K
1 2
C530 0.1U_0402_10V6KC530 0.1U_0402_10V6K
1 2
C548 0.1U_0402_10V6KC548 0.1U_0402_10V6K
1 2
C555 0.1U_0402_10V6KC555 0.1U_0402_10V6K
1 2
R534 1K_0402_5%DIS@R534 1K_0402_5%DIS@
1 2
C544 0.1U_0402_10V6KC544 0.1U_0402_10V6K
1 2
C549 0.1U_0402_10V6KC549 0.1U_0402_10V6K
1 2
PCI EXPRESS -- GRAPHICS
DMI Intel(R) FDI
JCPU1A
IC,AUB_CFD_rPGA,R1P0
ME@
PCI EXPRESS -- GRAPHICS
DMI Intel(R) FDI
JCPU1A
IC,AUB_CFD_rPGA,R1P0
ME@
DMI_RX#[0]
A24
DMI_RX#[1]
C23
DMI_RX#[2]
B22
DMI_RX#[3]
A21
DMI_RX[0]
B24
DMI_RX[1]
D23
DMI_RX[2]
B23
DMI_RX[3]
A22
DMI_TX#[0]
D24
DMI_TX#[1]
G24
DMI_TX#[2]
F23
DMI_TX#[3]
H23
DMI_TX[0]
D25
DMI_TX[1]
F24
DMI_TX[3]
G23
DMI_TX[2]
E23
FDI_TX#[0]
E22
FDI_TX#[1]
D21
FDI_TX#[2]
D19
FDI_TX#[3]
D18
FDI_TX#[4]
G21
FDI_TX#[5]
E19
FDI_TX#[6]
F21
FDI_TX#[7]
G18
FDI_TX[0]
D22
FDI_TX[1]
C21
FDI_TX[2]
D20
FDI_TX[3]
C18
FDI_TX[4]
G22
FDI_TX[5]
E20
FDI_TX[6]
F20
FDI_TX[7]
G19
FDI_FSYNC[0]
F17
FDI_FSYNC[1]
E17
FDI_INT
C17
FDI_LSYNC[0]
F18
FDI_LSYNC[1]
D17
PEG_ICOMPI
B26
PEG_ICOMPO
A26
PEG_RBIAS
A25
PEG_RCOMPO
B27
PEG_RX#[0]
K35
PEG_RX#[1]
J34
PEG_RX#[2]
J33
PEG_RX#[3]
G35
PEG_RX#[4]
G32
PEG_RX#[5]
F34
PEG_RX#[6]
F31
PEG_RX#[7]
D35
PEG_RX#[8]
E33
PEG_RX#[9]
C33
PEG_RX#[10]
D32
PEG_RX#[11]
B32
PEG_RX#[12]
C31
PEG_RX#[13]
B28
PEG_RX#[14]
B30
PEG_RX#[15]
A31
PEG_RX[0]
J35
PEG_RX[1]
H34
PEG_RX[2]
H33
PEG_RX[3]
F35
PEG_RX[4]
G33
PEG_RX[5]
E34
PEG_RX[6]
F32
PEG_RX[7]
D34
PEG_RX[8]
F33
PEG_RX[9]
B33
PEG_RX[10]
D31
PEG_RX[11]
A32
PEG_RX[12]
C30
PEG_RX[13]
A28
PEG_RX[14]
B29
PEG_RX[15]
A30
PEG_TX#[0]
L33
PEG_TX#[1]
M35
PEG_TX#[2]
M33
PEG_TX#[3]
M30
PEG_TX#[4]
L31
PEG_TX#[5]
K32
PEG_TX#[6]
M29
PEG_TX#[7]
J31
PEG_TX#[8]
K29
PEG_TX#[9]
H30
PEG_TX#[10]
H29
PEG_TX#[11]
F29
PEG_TX#[12]
E28
PEG_TX#[13]
D29
PEG_TX#[14]
D27
PEG_TX#[15]
C26
PEG_TX[0]
L34
PEG_TX[1]
M34
PEG_TX[2]
M32
PEG_TX[3]
L30
PEG_TX[4]
M31
PEG_TX[5]
K31
PEG_TX[6]
M28
PEG_TX[7]
H31
PEG_TX[8]
K28
PEG_TX[9]
G30
PEG_TX[10]
G29
PEG_TX[11]
F28
PEG_TX[12]
E27
PEG_TX[13]
D28
PEG_TX[14]
C27
PEG_TX[15]
C25
C550 0.1U_0402_10V6KC550 0.1U_0402_10V6K
1 2
C563 0.1U_0402_10V6KC563 0.1U_0402_10V6K
1 2
C545 0.1U_0402_10V6KC545 0.1U_0402_10V6K
1 2
C564 0.1U_0402_10V6KC564 0.1U_0402_10V6K
1 2
R59
3.01K_0402_1%
@R59
3.01K_0402_1%
@
1 2
R60 3.01K_0402_1%
@
R60 3.01K_0402_1%
@
1 2
C528 0.1U_0402_10V6KC528 0.1U_0402_10V6K
1 2
C529 0.1U_0402_10V6KC529 0.1U_0402_10V6K
1 2
C531 0.1U_0402_10V6KC531 0.1U_0402_10V6K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D63
DDR_A_D62
DDR_A_D8
DDR_A_D3
DDR_A_D4
DDR_A_D7
DDR_A_D5
DDR_A_D6
DDR_A_D59
DDR_A_D58
DDR_A_D57
DDR_A_D56
DDR_A_D47
DDR_A_D46
DDR_A_D42
DDR_A_D43
DDR_A_D34
DDR_A_D39
DDR_A_D44
DDR_A_D45
DDR_A_D35
DDR_A_D41
DDR_A_D40
DDR_A_D38
DDR_A_D36
DDR_A_D37
DDR_A_D32
DDR_A_D33
DDR_A_D61
DDR_A_D60
DDR_A_D2
DDR_A_D1
DDR_A_D0
DDR_A_D55
DDR_A_D54
DDR_A_D51
DDR_A_D48
DDR_A_D50
DDR_A_D49
DDR_A_D52
DDR_A_D53
DDR_A_D31
DDR_A_D14
DDR_A_D15
DDR_A_D25
DDR_A_D24
DDR_A_D26
DDR_A_D27
DDR_A_D30
DDR_A_D9
DDR_A_D13
DDR_A_D12
DDR_A_D10
DDR_A_D11
DDR_A_D29
DDR_A_D28
DDR_A_D19
DDR_A_D20
DDR_A_D16
DDR_A_D21
DDR_A_D17
DDR_A_D22
DDR_A_D18
DDR_A_D23
DDR_A_DQS#7
DDR_A_DQS#0
DDR_A_DQS#2
DDR_A_DQS#5
DDR_A_DQS#3
DDR_A_DQS#1
DDR_A_DQS#4
DDR_A_DQS#6
DDR_A_DM7
DDR_A_DM2
DDR_A_DM5
DDR_A_DM4
DDR_A_DM1
DDR_A_DM6
DDR_A_DM3
DDR_A_DM0
DDR_A_MA5
DDR_A_MA0
DDR_A_MA9
DDR_A_MA14
DDR_A_MA11
DDR_A_MA4
DDR_A_MA7
DDR_A_MA6
DDR_A_MA10
DDR_A_MA1
DDR_A_MA12
DDR_A_MA2
DDR_A_MA13
DDR_A_MA3
DDR_A_MA8
DDR_B_D3
DDR_B_D51
DDR_B_D56
DDR_B_D9
DDR_B_D31
DDR_B_D39
DDR_B_D49
DDR_B_D54
DDR_B_D57
DDR_B_D24
DDR_B_D10
DDR_B_D1
DDR_B_D6
DDR_B_D44
DDR_B_D43
DDR_B_D20
DDR_B_D42
DDR_B_D55
DDR_B_D15
DDR_B_D34
DDR_B_D23
DDR_B_D60
DDR_B_D33
DDR_B_D11
DDR_B_D41
DDR_B_D45
DDR_B_D0
DDR_B_D48
DDR_B_D50
DDR_B_D38
DDR_B_D21
DDR_B_D32
DDR_B_D22
DDR_B_D4
DDR_B_D14
DDR_B_D27
DDR_B_D25
DDR_B_D62
DDR_B_D59
DDR_B_D19
DDR_B_D52
DDR_B_D7
DDR_B_D5
DDR_B_D17
DDR_B_D58
DDR_B_D30
DDR_B_D26
DDR_B_D36
DDR_B_D13
DDR_B_D53
DDR_B_D18
DDR_B_D8
DDR_B_D35
DDR_B_D46
DDR_B_D12
DDR_B_D47
DDR_B_D28
DDR_B_D2
DDR_B_D37
DDR_B_D63
DDR_B_D40
DDR_B_D29
DDR_B_D61
DDR_B_D16
DDR_A_MA15
DDR_A_DQS0
DDR_A_DQS2
DDR_A_DQS1
DDR_A_DQS6
DDR_A_DQS5
DDR_A_DQS4
DDR_A_DQS3
DDR_A_DQS7
DDR_B_MA0
DDR_B_MA9
DDR_B_MA7
DDR_B_MA13
DDR_B_MA2
DDR_B_MA4
DDR_B_MA11
DDR_B_MA3
DDR_B_MA5
DDR_B_MA6
DDR_B_MA10
DDR_B_MA8
DDR_B_MA1
DDR_B_MA12
DDR_B_MA14
DDR_B_MA15
DDR_B_DQS#1
DDR_B_DQS#7
DDR_B_DQS#5
DDR_B_DQS#4
DDR_B_DQS#0
DDR_B_DQS#3
DDR_B_DQS#6
DDR_B_DQS#2
DDR_B_DQS7
DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS5
DDR_B_DQS4
DDR_B_DQS3
DDR_B_DQS2
DDR_B_DQS6
DDR_B_DM3
DDR_B_DM1
DDR_B_DM5
DDR_B_DM0
DDR_B_DM6
DDR_B_DM7
DDR_B_DM4
DDR_B_DM2
DDR_A_MA[0..15] <10>
DDR_A_DM[0..7] <10>
DDR_A_D[0..63]<10>
DDR_A_BS0<10>
DDR_A_BS1<10>
DDR_A_BS2<10>
DDR_A_WE#<10>
DDR_A_RAS#<10>
DDR_A_CAS#<10>
DDR_B_MA[0..15] <11>
DDR_B_DM[0..7] <11>
DDR_B_BS0<11>
DDR_B_BS1<11>
DDR_B_BS2<11>
DDR_B_WE#<11>
DDR_B_RAS#<11>
DDR_B_CAS#<11>
DDR_B_D[0..63]<11>
M_CLK_DDR0 <10>
M_CLK_DDR#0 <10>
DDR_CKE0_DIMMA <10>
M_CLK_DDR1 <10>
M_CLK_DDR#1 <10>
DDR_CKE1_DIMMA <10>
DDR_CS0_DIMMA# <10>
DDR_CS1_DIMMA# <10>
M_ODT0 <10>
M_ODT1 <10>
M_ODT2 <11>
M_ODT3 <11>
DDR_CS2_DIMMB# <11>
DDR_CS3_DIMMB# <11>
DDR_B_DQS[0..7] <11>
DDR_A_DQS#[0..7] <10>
DDR_A_DQS[0..7] <10>
DDR_B_DQS#[0..7] <11>
M_CLK_DDR2 <11>
M_CLK_DDR#2 <11>
DDR_CKE2_DIMMB <11>
M_CLK_DDR3 <11>
M_CLK_DDR#3 <11>
DDR_CKE3_DIMMB <11>
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(3/5)-DDR III
Custom
7 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(3/5)-DDR III
Custom
7 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(3/5)-DDR III
Custom
7 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
DDR SYSTEM MEMORY A
JCPU1C
IC,AUB_CFD_rPGA,R1P0
ME@
DDR SYSTEM MEMORY A
JCPU1C
IC,AUB_CFD_rPGA,R1P0
ME@
SA_BS[0]
AC3
SA_BS[1]
AB2
SA_BS[2]
U7
SA_CAS#
AE1
SA_RAS#
AB3
SA_WE#
AE9
SA_CK[0]
AA6
SA_CK[1]
Y6
SA_CK#[0]
AA7
SA_CK#[1]
Y5
SA_CKE[0]
P7
SA_CKE[1]
P6
SA_CS#[0]
AE2
SA_CS#[1]
AE8
SA_ODT[0]
AD8
SA_ODT[1]
AF9
SA_DM[0]
B9
SA_DM[1]
D7
SA_DM[2]
H7
SA_DM[3]
M7
SA_DM[4]
AG6
SA_DM[5]
AM7
SA_DM[6]
AN10
SA_DM[7]
AN13
SA_DQS[0]
C8
SA_DQS#[0]
C9
SA_DQS[1]
F9
SA_DQS#[1]
F8
SA_DQS[2]
H9
SA_DQS#[2]
J9
SA_DQS[3]
M9
SA_DQS#[3]
N9
SA_DQS[4]
AH8
SA_DQS#[4]
AH7
SA_DQS[5]
AK10
SA_DQS#[5]
AK9
SA_DQS[6]
AN11
SA_DQS#[6]
AP11
SA_DQS[7]
AR13
SA_DQS#[7]
AT13
SA_MA[0]
Y3
SA_MA[1]
W1
SA_MA[2]
AA8
SA_MA[3]
AA3
SA_MA[4]
V1
SA_MA[5]
AA9
SA_MA[6]
V8
SA_MA[7]
T1
SA_MA[8]
Y9
SA_MA[9]
U6
SA_MA[10]
AD4
SA_MA[11]
T2
SA_MA[12]
U3
SA_MA[13]
AG8
SA_MA[14]
T3
SA_MA[15]
V9
SA_DQ[0]
A10
SA_DQ[1]
C10
SA_DQ[2]
C7
SA_DQ[3]
A7
SA_DQ[4]
B10
SA_DQ[5]
D10
SA_DQ[6]
E10
SA_DQ[7]
A8
SA_DQ[8]
D8
SA_DQ[9]
F10
SA_DQ[10]
E6
SA_DQ[11]
F7
SA_DQ[12]
E9
SA_DQ[13]
B7
SA_DQ[14]
E7
SA_DQ[15]
C6
SA_DQ[16]
H10
SA_DQ[17]
G8
SA_DQ[18]
K7
SA_DQ[19]
J8
SA_DQ[20]
G7
SA_DQ[21]
G10
SA_DQ[22]
J7
SA_DQ[23]
J10
SA_DQ[24]
L7
SA_DQ[25]
M6
SA_DQ[26]
M8
SA_DQ[27]
L9
SA_DQ[28]
L6
SA_DQ[29]
K8
SA_DQ[30]
N8
SA_DQ[31]
P9
SA_DQ[32]
AH5
SA_DQ[33]
AF5
SA_DQ[34]
AK6
SA_DQ[35]
AK7
SA_DQ[36]
AF6
SA_DQ[37]
AG5
SA_DQ[38]
AJ7
SA_DQ[39]
AJ6
SA_DQ[40]
AJ10
SA_DQ[41]
AJ9
SA_DQ[42]
AL10
SA_DQ[43]
AK12
SA_DQ[44]
AK8
SA_DQ[45]
AL7
SA_DQ[46]
AK11
SA_DQ[47]
AL8
SA_DQ[48]
AN8
SA_DQ[49]
AM10
SA_DQ[50]
AR11
SA_DQ[51]
AL11
SA_DQ[52]
AM9
SA_DQ[53]
AN9
SA_DQ[54]
AT11
SA_DQ[55]
AP12
SA_DQ[56]
AM12
SA_DQ[57]
AN12
SA_DQ[58]
AM13
SA_DQ[59]
AT14
SA_DQ[60]
AT12
SA_DQ[61]
AL13
SA_DQ[62]
AR14
SA_DQ[63]
AP14
DDR SYSTEM MEMORY - B
JCPU1D
IC,AUB_CFD_rPGA,R1P0
ME@
DDR SYSTEM MEMORY - B
JCPU1D
IC,AUB_CFD_rPGA,R1P0
ME@
SB_BS[0]
AB1
SB_BS[1]
W5
SB_BS[2]
R7
SB_CAS#
AC5
SB_RAS#
Y7
SB_WE#
AC6
SB_CK[0]
W8
SB_CK[1]
V7
SB_CK#[0]
W9
SB_CK#[1]
V6
SB_CKE[0]
M3
SB_CKE[1]
M2
SB_CS#[0]
AB8
SB_CS#[1]
AD6
SB_ODT[0]
AC7
SB_ODT[1]
AD1
SB_DM[0]
D4
SB_DM[1]
E1
SB_DM[2]
H3
SB_DM[3]
K1
SB_DM[4]
AH1
SB_DM[5]
AL2
SB_DM[6]
AR4
SB_DM[7]
AT8
SB_DQS[4]
AG2
SB_DQS#[4]
AH2
SB_DQS[5]
AL5
SB_DQS#[5]
AL4
SB_DQS[6]
AP5
SB_DQS#[6]
AR5
SB_DQS[7]
AR7
SB_DQS#[7]
AR8
SB_DQS[0]
C5
SB_DQS#[0]
D5
SB_DQS[1]
E3
SB_DQS#[1]
F4
SB_DQS[2]
H4
SB_DQS#[2]
J4
SB_DQS[3]
M5
SB_DQS#[3]
L4
SB_MA[0]
U5
SB_MA[1]
V2
SB_MA[2]
T5
SB_MA[3]
V3
SB_MA[4]
R1
SB_MA[5]
T8
SB_MA[6]
R2
SB_MA[7]
R6
SB_MA[8]
R4
SB_MA[9]
R5
SB_MA[10]
AB5
SB_MA[11]
P3
SB_MA[12]
R3
SB_MA[13]
AF7
SB_MA[14]
P5
SB_MA[15]
N1
SB_DQ[0]
B5
SB_DQ[1]
A5
SB_DQ[2]
C3
SB_DQ[3]
B3
SB_DQ[4]
E4
SB_DQ[5]
A6
SB_DQ[6]
A4
SB_DQ[7]
C4
SB_DQ[8]
D1
SB_DQ[9]
D2
SB_DQ[10]
F2
SB_DQ[11]
F1
SB_DQ[12]
C2
SB_DQ[13]
F5
SB_DQ[14]
F3
SB_DQ[15]
G4
SB_DQ[16]
H6
SB_DQ[17]
G2
SB_DQ[18]
J6
SB_DQ[19]
J3
SB_DQ[20]
G1
SB_DQ[21]
G5
SB_DQ[22]
J2
SB_DQ[23]
J1
SB_DQ[24]
J5
SB_DQ[25]
K2
SB_DQ[26]
L3
SB_DQ[27]
M1
SB_DQ[28]
K5
SB_DQ[29]
K4
SB_DQ[30]
M4
SB_DQ[31]
N5
SB_DQ[32]
AF3
SB_DQ[33]
AG1
SB_DQ[34]
AJ3
SB_DQ[35]
AK1
SB_DQ[36]
AG4
SB_DQ[37]
AG3
SB_DQ[38]
AJ4
SB_DQ[39]
AH4
SB_DQ[40]
AK3
SB_DQ[41]
AK4
SB_DQ[42]
AM6
SB_DQ[43]
AN2
SB_DQ[44]
AK5
SB_DQ[45]
AK2
SB_DQ[46]
AM4
SB_DQ[47]
AM3
SB_DQ[48]
AP3
SB_DQ[49]
AN5
SB_DQ[50]
AT4
SB_DQ[51]
AN6
SB_DQ[52]
AN4
SB_DQ[53]
AN3
SB_DQ[54]
AT5
SB_DQ[55]
AT6
SB_DQ[56]
AN7
SB_DQ[57]
AP6
SB_DQ[58]
AP8
SB_DQ[59]
AT9
SB_DQ[60]
AT7
SB_DQ[61]
AP9
SB_DQ[62]
AR10
SB_DQ[63]
AT10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCCSENSE
VSSSENSE
VCCSENSE
VSSSENSE
H_VID1
H_VID4
H_VID3
H_VID5
VCC_SENSE
H_VID2
PM_DPRSLPVR_R
H_VID0
VSS_SENSE
H_VID6
VTT_SELECT
GFX_IMON
GFX_IMON
GFX_VR_EN
GFX_VR_EN
SUSP
1.5V_DDR3_GATE
PSI# <48>
H_VID[0..6] <48>
PROC_DPRSLPVR <48>
IMVP_IMON <48>
VTT_SENSE <46>
VCCSENSE <48>
VSSSENSE <48>
VTT_SELECT <46>
GFXVR_IMON <47>
GFXVR_DPRSLPVR <47>
GFXVR_EN <47>
GFXVR_VID_0 <47>
GFXVR_VID_1 <47>
GFXVR_VID_3 <47>
GFXVR_VID_2 <47>
GFXVR_VID_4 <47>
GFXVR_VID_5 <47>
GFXVR_VID_6 <47>
VSS_AXG_SENSE <47>
VCC_AXG_SENSE <47>
SUSP<39,44,45>
+CPU_CORE
+CPU_CORE
+VCCP
+VCCP
+VCCP
+1.5V_DDR3
+VCCP
+1.8VS
+VCCP
+VCCP
+VCCP
+GFX_CORE
+1.5V
+1.5V_DDR3
+1.5V +1.5V_DDR3
+1.5V_DDR3
+5VALW
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(4/5)-PWR
Custom
8 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(4/5)-PWR
Custom
8 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(4/5)-PWR
Custom
8 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
CPU
H_VTTVID1 = Low, 1.1V FOR Clarksfiel
H_VTTVID1 = High, 1.05V FOR Auburndale
48A 15A18A
3A
0.6A
Close to CPU
BUT A SMALL AMOUNT OF POWER
(~15MW) MAYBE WASTED
DESIGN GUIDE REV1.1
AS NO CONNECT
2
1
1
For Intel S3 Power Reduction.
For Intel S3 Power Reduction.
Modify for cost revew.
09/16/2009
C210
10U_0805_6.3V6M
C210
10U_0805_6.3V6M
1
2
POWER
GRAPHICS VIDs
GRAPHICS
DDR3 - 1.5V RAILS
FDI PEG & DMI
SENSE
LINES
1.1V1.8V
JCPU1G
IC,AUB_CFD_rPGA,R1P0
ME@
POWER
GRAPHICS VIDs
GRAPHICS
DDR3 - 1.5V RAILS
FDI PEG & DMI
SENSE
LINES
1.1V1.8V
JCPU1G
IC,AUB_CFD_rPGA,R1P0
ME@
GFX_VID[0]
AM22
GFX_VID[1]
AP22
GFX_VID[2]
AN22
GFX_VID[3]
AP23
GFX_VID[4]
AM23
GFX_VID[5]
AP24
GFX_VID[6]
AN24
GFX_VR_EN
AR25
GFX_DPRSLPVR
AT25
GFX_IMON
AM24
VAXG_SENSE
AR22
VSSAXG_SENSE
AT22
VAXG1
AT21
VAXG2
AT19
VAXG3
AT18
VAXG4
AT16
VAXG5
AR21
VAXG6
AR19
VAXG7
AR18
VAXG8
AR16
VAXG9
AP21
VAXG10
AP19
VAXG11
AP18
VAXG12
AP16
VAXG13
AN21
VAXG14
AN19
VAXG15
AN18
VAXG16
AN16
VAXG17
AM21
VAXG18
AM19
VAXG19
AM18
VAXG20
AM16
VAXG21
AL21
VAXG22
AL19
VAXG23
AL18
VAXG24
AL16
VAXG25
AK21
VAXG26
AK19
VAXG27
AK18
VAXG28
AK16
VAXG29
AJ21
VAXG30
AJ19
VAXG31
AJ18
VAXG32
AJ16
VAXG33
AH21
VAXG34
AH19
VAXG35
AH18
VAXG36
AH16
VTT1_45
J24
VTT1_46
J23
VTT1_47
H25
VTT1_48
K26
VTT1_49
J27
VTT1_50
J26
VTT1_51
J25
VTT1_52
H27
VTT1_53
G28
VTT1_54
G27
VTT1_55
G26
VTT1_56
F26
VTT1_57
E26
VTT1_58
E25
VDDQ1
AJ1
VDDQ2
AF1
VDDQ3
AE7
VDDQ4
AE4
VDDQ5
AC1
VDDQ6
AB7
VDDQ7
AB4
VDDQ8
Y1
VDDQ9
W7
VDDQ10
W4
VDDQ11
U1
VDDQ12
T7
VDDQ13
T4
VDDQ14
P1
VDDQ15
N7
VDDQ16
N4
VDDQ17
L1
VDDQ18
H1
VTT0_59
P10
VTT0_60
N10
VTT0_61
L10
VTT0_62
K10
VCCPLL1
L26
VCCPLL2
L27
VCCPLL3
M26
VTT1_63
J22
VTT1_64
J20
VTT1_65
J18
VTT1_66
H21
VTT1_67
H20
VTT1_68
H19
R56 0_0402_5%R56 0_0402_5%
1 2
C207
10U_0805_6.3V6M
C207
10U_0805_6.3V6M
1
2
G
D
S
Q23
2N7002_SOT23
G
D
S
Q23
2N7002_SOT23
2
13
C160
22U_0805_6.3V6M
@
C160
22U_0805_6.3V6M
@
1
2
C216
10U_0805_6.3V6M
@
C216
10U_0805_6.3V6M
@
1
2
G
D
S
Q19
BSS138_NL_SOT23-3
G
D
S
Q19
BSS138_NL_SOT23-3
2
13
C199
10U_0805_6.3V6M
C199
10U_0805_6.3V6M
1
2
C213
10U_0805_6.3V6M
C213
10U_0805_6.3V6M
1
2
C240
10U_0805_6.3V6M
C240
10U_0805_6.3V6M
1
2
C252
22U_0805_6.3V6M
C252
22U_0805_6.3V6M
1
2
C289
0.1U_0402_10V6K
C289
0.1U_0402_10V6K
1
2
C273
10U_0805_6.3V6M
C273
10U_0805_6.3V6M
1
2
+
C268
220U_B2_2.5VM_R35
@
+
C268
220U_B2_2.5VM_R35
@
1
2
C257
1U_0603_10V4Z
C257
1U_0603_10V4Z
1
2
T15PAD
@
T15PAD
@
R267
0_0402_5%
@
R267
0_0402_5%
@
1 2
R268
20K_0402_5%
R268
20K_0402_5%
C167
1U_0603_10V4Z
C167
1U_0603_10V4Z
1
2
C189
22U_0805_6.3V6M
UMA@
C189
22U_0805_6.3V6M
UMA@
1
2
C191
22U_0805_6.3V6M
@
C191
22U_0805_6.3V6M
@
1
2
C168
2.2U_0603_6.3V4Z
C168
2.2U_0603_6.3V4Z
1
2
C218
10U_0805_6.3V6M
C218
10U_0805_6.3V6M
1
2
R559
0_0402_5%
DIS@
R559
0_0402_5%
DIS@
12
C211
10U_0805_6.3V6M
C211
10U_0805_6.3V6M
1
2
C208
10U_0805_6.3V6M
C208
10U_0805_6.3V6M
1
2
R141 0_0402_5%
UMA@
R141 0_0402_5%
UMA@
1 2
R551 100_0402_1%R551 100_0402_1%
1 2
C200
10U_0805_6.3V6M
C200
10U_0805_6.3V6M
1
2
C214
10U_0805_6.3V6M
C214
10U_0805_6.3V6M
1
2
C182
10U_0805_6.3V6M
C182
10U_0805_6.3V6M
1
2
U11
SI4800BDY-T1-E3_SO8
U11
SI4800BDY-T1-E3_SO8
S
1
S
2
S
3
G
4
D
8
D
7
D
6
D
5
C274
10U_0805_6.3V6M
C274
10U_0805_6.3V6M
1
2
R140
4.7K_0402_5%
UMA@
R140
4.7K_0402_5%
UMA@
1 2
C253
1U_0603_10V4Z
C253
1U_0603_10V4Z
1
2
C149
1U_0603_10V4Z
C149
1U_0603_10V4Z
1
2
C271
10U_0805_6.3V6M
C271
10U_0805_6.3V6M
1
2
C256
1U_0603_10V4Z
C256
1U_0603_10V4Z
1
2
C255
1U_0603_10V4Z
C255
1U_0603_10V4Z
1
2
C591
10U_0805_6.3V6M
UMA@
C591
10U_0805_6.3V6M
UMA@
1
2
C269
0.1U_0402_10V6K
@
C269
0.1U_0402_10V6K
@
1
2
C288
0.1U_0402_10V6K
C288
0.1U_0402_10V6K
1
2
C217
10U_0805_6.3V6M
C217
10U_0805_6.3V6M
1
2
C169
10U_0805_6.3V6M
C169
10U_0805_6.3V6M
1
2
C212
10U_0805_6.3V6M
C212
10U_0805_6.3V6M
1
2
C209
10U_0805_6.3V6M
C209
10U_0805_6.3V6M
1
2
R552 100_0402_1%R552 100_0402_1%
1 2
R553 0_0402_5%R553 0_0402_5%
1 2
C170
4.7U_0603_6.3V6K
C170
4.7U_0603_6.3V6K
1
2
C201
10U_0805_6.3V6M
C201
10U_0805_6.3V6M
1
2
+
C554
330U_D2_2.5VY_R9M
+
C554
330U_D2_2.5VY_R9M
1
2
C215
10U_0805_6.3V6M
C215
10U_0805_6.3V6M
1
2
C198
10U_0805_6.3V6M
C198
10U_0805_6.3V6M
1
2
R608 1K_0402_5%R608 1K_0402_5%
1 2
R554
0_0402_5%
R554
0_0402_5%
1 2
C254
1U_0603_10V4Z
C254
1U_0603_10V4Z
1
2
R132
1K_0402_5%
DIS@
R132
1K_0402_5%
DIS@
12
J2
JUMP_43X118
@
J2
JUMP_43X118
@
1
1
2
2
C286
0.1U_0402_10V6K
C286
0.1U_0402_10V6K
1
2
C272
10U_0805_6.3V6M
C272
10U_0805_6.3V6M
1
2
C161
22U_0805_6.3V6M
@
C161
22U_0805_6.3V6M
@
1
2
C159
22U_0805_6.3V6M
UMA@
C159
22U_0805_6.3V6M
UMA@
1
2
C219
10U_0805_6.3V6M
C219
10U_0805_6.3V6M
1
2
C190
22U_0805_6.3V6M
@
C190
22U_0805_6.3V6M
@
1
2
C258
22U_0805_6.3V6M
C258
22U_0805_6.3V6M
1
2
C181
10U_0805_6.3V6M
C181
10U_0805_6.3V6M
1
2
C287
0.1U_0402_10V6K
C287
0.1U_0402_10V6K
1
2
J3
JUMP_43X118
@
J3
JUMP_43X118
@
1
1
2
2
C270
10U_0805_6.3V6M
@
C270
10U_0805_6.3V6M
@
1
2
C592
10U_0805_6.3V6M
UMA@
C592
10U_0805_6.3V6M
UMA@
1
2
C325
0.1U_0603_25V7K
C325
0.1U_0603_25V7K
1
2
POWER
CPU CORE SUPPLY
1.1V RAIL POWER
SENSE LINES
CPU VIDS
JCPU1F
IC,AUB_CFD_rPGA,R1P0
ME@
POWER
CPU CORE SUPPLY
1.1V RAIL POWER
SENSE LINES
CPU VIDS
JCPU1F
IC,AUB_CFD_rPGA,R1P0
ME@
ISENSE
AN35
VTT_SENSE
B15
PSI#
AN33
VID[0]
AK35
VID[1]
AK33
VID[2]
AK34
VID[3]
AL35
VID[4]
AL33
VID[5]
AM33
VID[6]
AM35
PROC_DPRSLPVR
AM34
VTT_SELECT
G15
VCC_SENSE
AJ34
VSS_SENSE_VTT
A15
VCC1
AG35
VCC2
AG34
VCC3
AG33
VCC4
AG32
VCC5
AG31
VCC6
AG30
VCC7
AG29
VCC8
AG28
VCC9
AG27
VCC10
AG26
VCC11
AF35
VCC12
AF34
VCC13
AF33
VCC14
AF32
VCC15
AF31
VCC16
AF30
VCC17
AF29
VCC18
AF28
VCC19
AF27
VCC20
AF26
VCC21
AD35
VCC22
AD34
VCC23
AD33
VCC24
AD32
VCC25
AD31
VCC26
AD30
VCC27
AD29
VCC28
AD28
VCC29
AD27
VCC30
AD26
VCC31
AC35
VCC32
AC34
VCC33
AC33
VCC34
AC32
VCC35
AC31
VCC36
AC30
VCC37
AC29
VCC38
AC28
VCC39
AC27
VCC40
AC26
VCC41
AA35
VCC42
AA34
VCC43
AA33
VCC44
AA32
VCC45
AA31
VCC46
AA30
VCC47
AA29
VCC48
AA28
VCC49
AA27
VCC50
AA26
VCC51
Y35
VCC52
Y34
VCC53
Y33
VCC54
Y32
VCC55
Y31
VCC56
Y30
VCC57
Y29
VCC58
Y28
VCC59
Y27
VCC60
Y26
VCC61
V35
VCC62
V34
VCC63
V33
VCC64
V32
VCC65
V31
VCC66
V30
VCC67
V29
VCC68
V28
VCC69
V27
VCC70
V26
VCC71
U35
VCC72
U34
VCC73
U33
VCC74
U32
VCC75
U31
VCC76
U30
VCC77
U29
VCC78
U28
VCC79
U27
VCC80
U26
VCC81
R35
VCC82
R34
VCC83
R33
VCC84
R32
VCC85
R31
VCC86
R30
VCC87
R29
VCC88
R28
VCC89
R27
VCC90
R26
VCC91
P35
VCC92
P34
VCC93
P33
VCC94
P32
VCC95
P31
VCC96
P30
VCC97
P29
VCC98
P28
VCC99
P27
VCC100
P26
VTT0_33
AF10
VTT0_34
AE10
VTT0_35
AC10
VTT0_36
AB10
VTT0_37
Y10
VTT0_38
W10
VTT0_39
U10
VTT0_40
T10
VTT0_41
J12
VTT0_42
J11
VTT0_1
AH14
VTT0_2
AH12
VTT0_3
AH11
VTT0_4
AH10
VTT0_5
J14
VTT0_6
J13
VTT0_7
H14
VTT0_8
H12
VTT0_9
G14
VTT0_10
G13
VTT0_11
G12
VTT0_12
G11
VTT0_13
F14
VTT0_14
F13
VTT0_15
F12
VTT0_16
F11
VTT0_17
E14
VTT0_18
E12
VTT0_19
D14
VTT0_20
D13
VTT0_21
D12
VTT0_22
D11
VTT0_23
C14
VTT0_24
C13
VTT0_25
C12
VTT0_26
C11
VTT0_27
B14
VTT0_28
B12
VTT0_29
A14
VTT0_30
A13
VTT0_31
A12
VTT0_32
A11
VSS_SENSE
AJ35
VTT0_43
J16
VTT0_44
J15
R233
220_0402_5%
R233
220_0402_5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VSS_NCTF7_R
VSS_NCTF5_R
VSS_NCTF3_R
VSS_NCTF2_R
VSS_NCTF1_R
VSS_NCTF6_R
VSS_NCTF4_R
+CPU_CORE
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(5/5)-GND/Bypass
Custom
9 51Thursday, October 29, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(5/5)-GND/Bypass
Custom
9 51Thursday, October 29, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
Arrandale(5/5)-GND/Bypass
Custom
9 51Thursday, October 29, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
470uF 4.5mohm
Under cavity
between Inductor and socket
CPU CORE
Inside cavity
C162
10U_0805_6.3V6M
C162
10U_0805_6.3V6M
1
2
C148
10U_0805_6.3V6M
C148
10U_0805_6.3V6M
1
2
C584
22U_0805_6.3V6M
C584
22U_0805_6.3V6M
1
2
C129
22U_0805_6.3V6M
C129
22U_0805_6.3V6M
1
2
C163
10U_0805_6.3V6M
C163
10U_0805_6.3V6M
1
2
C88
10U_0805_6.3V6M
C88
10U_0805_6.3V6M
1
2
C90
22U_0805_6.3V6M
C90
22U_0805_6.3V6M
1
2
C192
10U_0805_6.3V6M
C192
10U_0805_6.3V6M
1
2
C579
22U_0805_6.3V6M
C579
22U_0805_6.3V6M
1
2
C578
22U_0805_6.3V6M
C578
22U_0805_6.3V6M
1
2
C91
22U_0805_6.3V6M
C91
22U_0805_6.3V6M
1
2
+
C92
470U_D2T_2VM
+
C92
470U_D2T_2VM
1
2 3
C194
10U_0805_6.3V6M
C194
10U_0805_6.3V6M
1
2
C193
10U_0805_6.3V6M
C193
10U_0805_6.3V6M
1
2
+
C76
470U_D2T_2VM
+
C76
470U_D2T_2VM
1
2 3
C165
10U_0805_6.3V6M
C165
10U_0805_6.3V6M
1
2
C583
22U_0805_6.3V6M
C583
22U_0805_6.3V6M
1
2
C585
22U_0805_6.3V6M
C585
22U_0805_6.3V6M
1
2
VSS
NCTF
JCPU1I
IC,AUB_CFD_rPGA,R1P0
ME@
VSS
NCTF
JCPU1I
IC,AUB_CFD_rPGA,R1P0
ME@
VSS161
K27
VSS162
K9
VSS163
K6
VSS164
K3
VSS165
J32
VSS166
J30
VSS167
J21
VSS168
J19
VSS169
H35
VSS170
H32
VSS171
H28
VSS172
H26
VSS173
H24
VSS174
H22
VSS175
H18
VSS176
H15
VSS177
H13
VSS178
H11
VSS179
H8
VSS180
H5
VSS181
H2
VSS182
G34
VSS183
G31
VSS184
G20
VSS185
G9
VSS186
G6
VSS187
G3
VSS188
F30
VSS189
F27
VSS190
F25
VSS191
F22
VSS192
F19
VSS193
F16
VSS194
E35
VSS195
E32
VSS196
E29
VSS197
E24
VSS198
E21
VSS199
E18
VSS200
E13
VSS201
E11
VSS202
E8
VSS203
E5
VSS204
E2
VSS205
D33
VSS206
D30
VSS207
D26
VSS208
D9
VSS209
D6
VSS210
D3
VSS211
C34
VSS212
C32
VSS213
C29
VSS214
C28
VSS215
C24
VSS216
C22
VSS217
C20
VSS218
C19
VSS219
C16
VSS220
B31
VSS221
B25
VSS222
B21
VSS223
B18
VSS224
B17
VSS225
B13
VSS226
B11
VSS227
B8
VSS228
B6
VSS229
B4
VSS230
A29
VSS_NCTF1
AT35
VSS_NCTF2
AT1
VSS_NCTF3
AR34
VSS_NCTF4
B34
VSS_NCTF5
B2
VSS_NCTF6
B1
VSS_NCTF7
A35
VSS231
A27
VSS232
A23
VSS233
A9
VSS
JCPU1H
IC,AUB_CFD_rPGA,R1P0
ME@
VSS
JCPU1H
IC,AUB_CFD_rPGA,R1P0
ME@
VSS1
AT20
VSS2
AT17
VSS3
AR31
VSS4
AR28
VSS5
AR26
VSS6
AR24
VSS7
AR23
VSS8
AR20
VSS9
AR17
VSS10
AR15
VSS11
AR12
VSS12
AR9
VSS13
AR6
VSS14
AR3
VSS15
AP20
VSS16
AP17
VSS17
AP13
VSS18
AP10
VSS19
AP7
VSS20
AP4
VSS21
AP2
VSS22
AN34
VSS23
AN31
VSS24
AN23
VSS25
AN20
VSS26
AN17
VSS27
AM29
VSS28
AM27
VSS29
AM25
VSS30
AM20
VSS31
AM17
VSS32
AM14
VSS33
AM11
VSS34
AM8
VSS35
AM5
VSS36
AM2
VSS37
AL34
VSS38
AL31
VSS39
AL23
VSS40
AL20
VSS41
AL17
VSS42
AL12
VSS43
AL9
VSS44
AL6
VSS45
AL3
VSS46
AK29
VSS47
AK27
VSS48
AK25
VSS49
AK20
VSS50
AK17
VSS51
AJ31
VSS52
AJ23
VSS53
AJ20
VSS54
AJ17
VSS55
AJ14
VSS56
AJ11
VSS57
AJ8
VSS58
AJ5
VSS59
AJ2
VSS60
AH35
VSS61
AH34
VSS62
AH33
VSS63
AH32
VSS64
AH31
VSS65
AH30
VSS66
AH29
VSS67
AH28
VSS68
AH27
VSS69
AH26
VSS70
AH20
VSS71
AH17
VSS72
AH13
VSS73
AH9
VSS74
AH6
VSS75
AH3
VSS76
AG10
VSS77
AF8
VSS78
AF4
VSS79
AF2
VSS80
AE35
VSS81
AE34
VSS82
AE33
VSS83
AE32
VSS84
AE31
VSS85
AE30
VSS86
AE29
VSS87
AE28
VSS88
AE27
VSS89
AE26
VSS90
AE6
VSS91
AD10
VSS92
AC8
VSS93
AC4
VSS94
AC2
VSS95
AB35
VSS96
AB34
VSS97
AB33
VSS98
AB32
VSS99
AB31
VSS100
AB30
VSS101
AB29
VSS102
AB28
VSS103
AB27
VSS104
AB26
VSS105
AB6
VSS106
AA10
VSS107
Y8
VSS108
Y4
VSS109
Y2
VSS110
W35
VSS111
W34
VSS112
W33
VSS113
W32
VSS114
W31
VSS115
W30
VSS116
W29
VSS117
W28
VSS118
W27
VSS119
W26
VSS120
W6
VSS121
V10
VSS122
U8
VSS123
U4
VSS124
U2
VSS125
T35
VSS126
T34
VSS127
T33
VSS128
T32
VSS129
T31
VSS130
T30
VSS131
T29
VSS132
T28
VSS133
T27
VSS134
T26
VSS135
T6
VSS136
R10
VSS137
P8
VSS138
P4
VSS139
P2
VSS140
N35
VSS141
N34
VSS142
N33
VSS143
N32
VSS144
N31
VSS145
N30
VSS146
N29
VSS147
N28
VSS148
N27
VSS149
N26
VSS150
N6
VSS151
M10
VSS152
L35
VSS153
L32
VSS154
L29
VSS155
L8
VSS156
L5
VSS157
L2
VSS158
K34
VSS159
K33
VSS160
K30
C580
22U_0805_6.3V6M
C580
22U_0805_6.3V6M
1
2
C89
10U_0805_6.3V6M
C89
10U_0805_6.3V6M
1
2
C166
10U_0805_6.3V6M
C166
10U_0805_6.3V6M
1
2
C196
10U_0805_6.3V6M
C196
10U_0805_6.3V6M
1
2
C577
22U_0805_6.3V6M
C577
22U_0805_6.3V6M
1
2
C574
22U_0805_6.3V6M
C574
22U_0805_6.3V6M
1
2
C197
10U_0805_6.3V6M
C197
10U_0805_6.3V6M
1
2
C571
22U_0805_6.3V6M
C571
22U_0805_6.3V6M
1
2
C568
22U_0805_6.3V6M
C568
22U_0805_6.3V6M
1
2
C147
10U_0805_6.3V6M
C147
10U_0805_6.3V6M
1
2
C573
22U_0805_6.3V6M
C573
22U_0805_6.3V6M
1
2
+
C75
470U_D2T_2VM
+
C75
470U_D2T_2VM
1
2 3
+
C164
470U_D2T_2VM
+
C164
470U_D2T_2VM
1
2 3
C195
10U_0805_6.3V6M
C195
10U_0805_6.3V6M
1
2
C87
22U_0805_6.3V6M
C87
22U_0805_6.3V6M
1
2
C180
10U_0805_6.3V6M
C180
10U_0805_6.3V6M
1
2
C179
10U_0805_6.3V6M
C179
10U_0805_6.3V6M
1
2
C572
22U_0805_6.3V6M
C572
22U_0805_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_A_D31
DDR_A_D12
DDR_CKE0_DIMMA
DDR_A_D59
DDR_A_D6
DDR_A_MA3
SMB_CLK_S3
DDR_CS1_DIMMA#
DDR_A_D39
DDR_A_BS1
DDR_A_DQS0
DDR_A_WE#
DDR_A_MA7
DDR_A_MA0
DDR_A_DM2
DDR_A_DM1
DDR_A_DQS7
DDR_A_D0
DDR_A_D57
DDR_A_D46
DDR_A_D28
DDR_A_DM0
DDR_A_D19
DDR_A_DQS#5
DDR_A_D51
DDR_A_D4
DDR_A_DM4
DDR_A_D30
DDR_A_DQS2
DDR_A_D44
DDR_A_RAS#
DDR_A_D33
DDR_A_D58
DDR_A_DM5
DDR_A_DQS3
DDR_A_MA8
DDR_CS0_DIMMA#
DDR_A_D10
DDR_A_MA6
DDR_A_D27
DDR_A_D3
DRAMRST#
DDR_A_MA10
DDR_A_DQS#7
DDR_A_D1
DDR_A_DQS#6
DDR_A_D40
DDR_A_MA9
DDR_A_D16
DDR_A_D29
DDR_A_DQS#4
DDR_A_D52
DDR_A_DM3
DDR_A_DQS5
DDR_A_D54
DDR_A_D49
DDR_A_BS2
DDR_A_D45
DDR_A_D9
DDR_A_DM7
DDR_A_D7
DDR_A_MA1
DDR_A_D13
DDR_A_D20
DDR_A_D60
DDR_A_BS0
DDR_A_CAS# M_ODT0
DDR_A_D37
DDR_A_MA5
DDR_A_DQS#1
DDR_A_MA14
DDR_A_D55
DDR_A_MA4
DDR_A_D21
DDR_A_D62
DDR_A_D24
DDR_A_D15
DDR_A_D23
DDR_A_D56
DDR_A_D53
DDR_A_D47
DDR_A_D18
M_ODT1
DDR_A_D43
DDR_A_D34
M_CLK_DDR1
M_CLK_DDR#1
DDR_A_D48
SMB_DATA_S3
DDR_A_DQS#2
DDR_A_D11
DDR_A_D38
M_CLK_DDR0
M_CLK_DDR#0
DDR_A_DQS#3
DDR_A_D32
DDR_A_D8
DDR_A_DQS1
DDR_A_MA13
DDR_A_MA11
DDR_A_D50
DDR_A_D61
DDR_A_MA2
DDR_A_D41
DDR_A_D17
DDR_A_D36
DDR_A_D26
DDR_A_D63
DDR_A_D2
DDR_A_D5
DDR_A_D22
DDR_A_D25
DDR_A_DQS6
DDR_A_D35
DDR_A_D14
DDR_A_MA12
DDR_A_DQS#0
DDR_A_DQS4
DDR_A_DM6
DDR_A_D42
DDR_CKE1_DIMMA
PM_EXTTS#1_R
+VREF_DQ_DIMMA
DDR_A_MA15
DDR_A_DQS#[0..7]<7>
DDR_A_D[0..63]<7>
DDR_A_DM[0..7]<7>
DDR_A_DQS[0..7]<7>
DDR_A_MA[0..15]<7>
DDR_CKE0_DIMMA<7>
DDR_A_BS2<7>
M_CLK_DDR0<7>
M_CLK_DDR#0<7>
DDR_A_BS0<7>
DDR_A_WE#<7>
DDR_A_CAS#<7>
DDR_CS1_DIMMA#<7>
DDR_CKE1_DIMMA <7>
DDR_A_BS1 <7>
DDR_A_RAS# <7>
DDR_CS0_DIMMA# <7>
M_ODT0 <7>
M_CLK_DDR1 <7>
M_CLK_DDR#1 <7>
M_ODT1 <7>
DRAMRST# <5,11>
PM_EXTTS#1_R <5,11>
SMB_DATA_S3 <11,12,14,28>
SMB_CLK_S3 <11,12,14,28>
+0.75VS
+3VS
+1.5V +1.5V
+VREF_DQ_DIMMA
+1.5V
+VREF_DQ_DIMMA
+1.5V
+0.75VS
+VREF_DQ_DIMMA
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
DDRIII-SODIMM SLOT1
Custom
10 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
DDRIII-SODIMM SLOT1
Custom
10 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
DDRIII-SODIMM SLOT1
Custom
10 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
DDR3 SO-DIMM A
Layout Note:
Place near DIMM
3A@1.5V
3A@1.5V3A@1.5V
3A@1.5V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
0.65A@0.75V
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
VDDQ(1.5V) =
3*0805 10uf
VTT(0.75V) =
4*0402 1uf
1*0402 0.1uf
VREF =
1*0402 2.2uf
VDDSPD (3.3V)=
1*0402 0.1uf 1*0402 2.2uf
For Arranale only +VREF_DQ_DIMMA
supply from a external 1.5V voltage divide
circuit.
07/17/2009
C608
2.2U_0603_6.3V4Z
C608
2.2U_0603_6.3V4Z
1
2
C310
10U_0603_6.3V6M
C310
10U_0603_6.3V6M
1
2
+
C569
220U_B2_2.5VM_R35
+
C569
220U_B2_2.5VM_R35
1
2
C317
0.1U_0402_10V6K
C317
0.1U_0402_10V6K
1
2
C581
10U_0603_6.3V6M
C581
10U_0603_6.3V6M
1
2
C316
0.1U_0402_10V6K
C316
0.1U_0402_10V6K
1
2
C314
0.1U_0402_10V6K
C314
0.1U_0402_10V6K
1
2
C617
0.1U_0402_10V6K
C617
0.1U_0402_10V6K
1
2
C570
10U_0603_6.3V6M
C570
10U_0603_6.3V6M
1
2
C347
2.2U_0603_6.3V4Z
C347
2.2U_0603_6.3V4Z
1
2
C309
10U_0603_6.3V6M
C309
10U_0603_6.3V6M
1
2
R297
1K_0402_1%
R297
1K_0402_1%
12
C586
10U_0603_6.3V6M
C586
10U_0603_6.3V6M
1
2
C315
0.1U_0402_10V6K
C315
0.1U_0402_10V6K
1
2
C606
1U_0603_10V4Z
C606
1U_0603_10V4Z
1
2
C588
10U_0603_6.3V6M
@
C588
10U_0603_6.3V6M
@
1
2
R305
1K_0402_1%
R305
1K_0402_1%
12
C355
2.2U_0603_6.3V4Z
C355
2.2U_0603_6.3V4Z
1
2
R571
10K_0402_5%
R571
10K_0402_5%
12
C607
1U_0603_10V4Z
C607
1U_0603_10V4Z
1
2
C301
1U_0603_10V4Z
C301
1U_0603_10V4Z
1
2
C303
0.1U_0402_10V6K
C303
0.1U_0402_10V6K
1
2
C300
1U_0603_10V4Z
C300
1U_0603_10V4Z
1
2
R570
10K_0402_5%
R570
10K_0402_5%
1 2
C605
1U_0603_10V4Z
C605
1U_0603_10V4Z
1
2
C308
10U_0603_6.3V6M
C308
10U_0603_6.3V6M
1
2
JDIMM1
FOX_AS0A626-U4SN-7F
ME@
JDIMM1
FOX_AS0A626-U4SN-7F
ME@
VREF_DQ
1
VSS1
2
VSS2
3
DQ4
4
DQ0
5
DQ5
6
DQ1
7
VSS3
8
VSS4
9
DQS#0
10
DM0
11
DQS0
12
VSS5
13
VSS6
14
DQ2
15
DQ6
16
DQ3
17
DQ7
18
VSS7
19
VSS8
20
DQ8
21
DQ12
22
DQ9
23
DQ13
24
VSS9
25
VSS10
26
DQS#1
27
DM1
28
DQS1
29
RESET#
30
VSS11
31
VSS12
32
DQ10
33
DQ14
34
DQ11
35
DQ15
36
VSS13
37
VSS14
38
DQ16
39
DQ20
40
DQ17
41
DQ21
42
VSS15
43
VSS16
44
DQS#2
45
DM2
46
DQS2
47
VSS17
48
VSS18
49
DQ22
50
DQ18
51
DQ23
52
DQ19
53
VSS19
54
VSS20
55
DQ28
56
DQ24
57
DQ29
58
DQ25
59
VSS21
60
VSS22
61
DQS#3
62
DM3
63
DQS3
64
VSS23
65
VSS24
66
DQ26
67
DQ30
68
DQ27
69
DQ31
70
VSS25
71
VSS26
72
A12/BC#
83
A11
84
A9
85
A7
86
VDD5
87
VDD6
88
A8
89
A6
90
CKE0
73
CKE1
74
VDD1
75
VDD2
76
NC1
77
A15
78
BA2
79
A14
80
VDD3
81
VDD4
82
A5
91
A4
92
VDD7
93
VDD8
94
A3
95
A2
96
A1
97
A0
98
VDD9
99
VDD10
100
CK0
101
CK1
102
CK0#
103
CK1#
104
VDD11
105
VDD12
106
A10/AP
107
BA1
108
BA0
109
RAS#
110
VDD13
111
VDD14
112
WE#
113
S0#
114
CAS#
115
ODT0
116
VDD15
117
VDD16
118
A13
119
ODT1
120
S1#
121
NC2
122
VDD17
123
VDD18
124
NCTEST
125
VREF_CA
126
VSS27
127
VSS28
128
DQ32
129
DQ36
130
DQ33
131
DQ37
132
VSS29
133
VSS30
134
DQS#4
135
DM4
136
DQS4
137
VSS31
138
VSS32
139
DQ38
140
DQ34
141
DQ39
142
DQ35
143
VSS33
144
VSS34
145
DQ44
146
DQ40
147
DQ45
148
DQ41
149
VSS35
150
VSS36
151
DQS#5
152
DM5
153
DQS5
154
VSS37
155
VSS38
156
DQ42
157
DQ46
158
DQ43
159
DQ47
160
VSS39
161
VSS40
162
DQ48
163
DQ52
164
DQ49
165
DQ53
166
VSS41
167
VSS42
168
DQS#6
169
DM6
170
DQS6
171
VSS43
172
VSS44
173
DQ54
174
DQ50
175
DQ55
176
DQ51
177
VSS45
178
VSS46
179
DQ60
180
DQ56
181
DQ61
182
DQ57
183
VSS47
184
VSS48
185
DQS#7
186
DM7
187
DQS7
188
VSS49
189
VSS50
190
DQ58
191
DQ62
192
DQ59
193
DQ63
194
VSS51
195
VSS52
196
SA0
197
EVENT#
198
VDDSPD
199
SDA
200
SA1
201
SCL
202
VTT1
203
VTT2
204
G1
205
G2
206
C346
0.1U_0402_10V6K
C346
0.1U_0402_10V6K
1
2
C589
10U_0603_6.3V6M
@
C589
10U_0603_6.3V6M
@
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DDR_B_D26
DDR_B_D2
DDR_B_D5
DDR_B_D22
DDR_B_D25
DDR_B_D14
DDR_B_DQS#0
DDR_B_D31
DDR_B_D12
DDR_B_D6
DDR_B_DQS0
DDR_B_DM2
DDR_B_DM1
+VREF_DQ_DIMMB
DDR_B_D0
DDR_B_D28
DDR_B_DM0
DDR_B_D19
DDR_B_D4
DDR_B_D30
DDR_B_DQS2
DDR_B_DQS3
DDR_B_D10
DDR_B_D27
DDR_B_D3
DRAMRST#
DDR_B_D1
DDR_B_D16
DDR_B_D29
DDR_B_DM3
DDR_B_D9
DDR_B_D7
DDR_B_D13
DDR_B_D20
DDR_B_DQS#1
DDR_B_D21
DDR_B_D24
DDR_B_D15
DDR_B_D23DDR_B_D18
DDR_B_DQS#2
DDR_B_D11
DDR_B_DQS#3
DDR_B_D8
DDR_B_DQS1
DDR_B_D17
DDR_B_D36
DDR_B_D63
DDR_B_MA15
DDR_B_DM6
DDR_CKE3_DIMMB
DDR_B_D39
DDR_B_BS1
DDR_B_MA7
DDR_B_MA0
DDR_B_DQS7
DDR_B_D46
DDR_B_DQS#5
DDR_B_DM4
DDR_B_D44
DDR_B_RAS#
DDR_CS2_DIMMB#
DDR_B_MA6
DDR_B_DQS#7
DDR_B_D52
DDR_B_DQS5
DDR_B_D54
DDR_B_D45
DDR_B_D60
M_ODT2
DDR_B_D37
DDR_B_MA14
DDR_B_D55
DDR_B_MA4
DDR_B_D62
DDR_B_D53
DDR_B_D47
M_ODT3
M_CLK_DDR3
M_CLK_DDR#3
DDR_B_D38
DDR_B_MA11
DDR_B_D61
DDR_B_MA2
SMB_CLK_S3
SMB_DATA_S3
PM_EXTTS#1_R
DDR_B_DQS6
DDR_B_D35
DDR_B_MA12
DDR_B_DQS4
DDR_B_D42
DDR_CKE2_DIMMB
DDR_B_D59
DDR_B_MA3
DDR_CS3_DIMMB#
DDR_B_WE#
DDR_B_D57
DDR_B_D51
DDR_B_D33
DDR_B_D58
DDR_B_DM5
DDR_B_MA8
DDR_B_MA10
DDR_B_DQS#6
DDR_B_D40
DDR_B_MA9
DDR_B_DQS#4
DDR_B_D49
DDR_B_BS2
DDR_B_DM7
DDR_B_MA1
DDR_B_BS0
DDR_B_CAS#
DDR_B_MA5
DDR_B_D56
DDR_B_D43
DDR_B_D34
DDR_B_D48
M_CLK_DDR2
M_CLK_DDR#2
DDR_B_D32
DDR_B_MA13
DDR_B_D50
DDR_B_D41
DRAMRST# <5,10>
DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DM[0..7]<7>
DDR_B_DQS[0..7]<7>
DDR_B_MA[0..15]<7>
DDR_CKE3_DIMMB <7>
M_CLK_DDR3 <7>
M_CLK_DDR#3 <7>
DDR_B_BS1 <7>
DDR_B_RAS# <7>
DDR_CS2_DIMMB# <7>
M_ODT2 <7>
M_ODT3 <7>
SMB_DATA_S3 <10,12,14,28>
SMB_CLK_S3 <10,12,14,28>
PM_EXTTS#1_R <5,10>
DDR_B_BS2<7>
DDR_CKE2_DIMMB<7>
M_CLK_DDR2<7>
M_CLK_DDR#2<7>
DDR_B_BS0<7>
DDR_B_WE#<7>
DDR_B_CAS#<7>
DDR_CS3_DIMMB#<7>
+0.75VS
+3VS
+1.5V +1.5V
+VREF_DQ_DIMMB
+1.5V
+0.75VS
+VREF_DQ_DIMMB
+1.5V
+VREF_DQ_DIMMB
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
DDRIII-SODIMM SLOT2
11 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
DDRIII-SODIMM SLOT2
11 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
DDRIII-SODIMM SLOT2
11 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Layout Note:
Place near DIMM
Layout Note:
Place near DIMM
3A@1.5V
3A@1.5V3A@1.5V
3A@1.5V
0.65A@0.75V
0.65A@0.75V0.65A@0.75V
0.65A@0.75V
1*0402 0.1uf 1*0402 2.2uf
3*330uf / 12m ohm (TOTAL FOR 2 SO-DIMMs)
6*0603 10uf (PER CONNECTOR)
3*0805 10uf
VTT(0.75V) =
4*0402 1uf
1*0402 0.1uf
VDDQ(1.5V) =
1*0402 2.2uf
VDDSPD (3.3V)=
For Arranale only +VREF_DQ_DIMMB
supply from a external 1.5V voltage divide
circuit.
07/17/2009
C587
10U_0603_6.3V6M
@
C587
10U_0603_6.3V6M
@
1
2
C383
2.2U_0603_6.3V4Z
C383
2.2U_0603_6.3V4Z
1
2
R341
1K_0402_1%
R341
1K_0402_1%
12
R572
10K_0402_5%
R572
10K_0402_5%
1 2
C382
2.2U_0603_6.3V4Z
C382
2.2U_0603_6.3V4Z
1
2
C595
1U_0603_10V4Z
C595
1U_0603_10V4Z
1
2
C596
10U_0603_6.3V6M
C596
10U_0603_6.3V6M
1
2
C299
1U_0603_10V4Z
C299
1U_0603_10V4Z
1
2
C304
0.1U_0402_10V6K
C304
0.1U_0402_10V6K
1
2
C384
0.1U_0402_10V6K
C384
0.1U_0402_10V6K
1
2
R340
1K_0402_1%
R340
1K_0402_1%
12
C313
10U_0603_6.3V6M
C313
10U_0603_6.3V6M
1
2
C305
0.1U_0402_10V6K
C305
0.1U_0402_10V6K
1
2
R573 10K_0402_5%R573 10K_0402_5%
1 2
JDIMM2
TYCO_2-2013297-2~D
ME@
JDIMM2
TYCO_2-2013297-2~D
ME@
VREF_DQ
1
VSS
3
DQ0
5
DQ1
7
VSS
9
DM0
11
VSS
13
DQ2
15
DQ3
17
VSS
19
DQ8
21
DQ9
23
VSS
25
DQS1#
27
DQS1
29
VSS
31
DQ10
33
DQ11
35
VSS
37
DQ16
39
VSS
2
DQ4
4
DQ5
6
VSS
8
DQS0#
10
DQS0
12
VSS
14
DQ6
16
DQ7
18
VSS
20
DQ12
22
DQ13
24
VSS
26
DM1
28
RESET#
30
VSS
32
DQ14
34
DQ15
36
VSS
38
DQ20
40
DQ17
41
VSS
43
DQS2#
45
DQS2
47
VSS
49
DQ18
51
DQ19
53
VSS
55
DQ24
57
DQ25
59
VSS
61
DM3
63
VSS
65
DQ26
67
DQ27
69
VSS
71
CKE0
73
VDD
75
NC
77
BA2
79
VDD
81
A12/BC#
83
A9
85
VDD
87
A8
89
A5
91
VDD
93
A3
95
A1
97
VDD
99
CK0
101
CK0#
103
VDD
105
A10/AP
107
BA0
109
VDD
111
WE#
113
CAS#
115
VDD
117
A13
119
S1#
121
VDD
123
TEST
125
VSS
127
DQ32
129
DQ33
131
VSS
133
DQS4#
135
DQS4
137
VSS
139
DQ34
141
DQ35
143
VSS
145
DQ40
147
DQ41
149
VSS
151
DM5
153
VSS
155
DQ42
157
DQ43
159
VSS
161
DQ48
163
DQ49
165
VSS
167
DQS6#
169
DQS6
171
VSS
173
DQ50
175
DQ51
177
VSS
179
DQ56
181
DQ57
183
VSS
185
DM7
187
VSS
189
DQ58
191
DQ59
193
VSS
195
SA0
197
VDDSPD
199
DQ21
42
VSS
44
DM2
46
VSS
48
DQ22
50
DQ23
52
VSS
54
DQ28
56
DQ29
58
VSS
60
DQS3#
62
DQS3
64
VSS
66
DQ30
68
DQ31
70
VSS
72
CKE1
74
VDD
76
A15
78
A14
80
VDD
82
A11
84
A7
86
VDD
88
A6
90
A4
92
VDD
94
A2
96
A0
98
VDD
100
CK1
102
CK1#
104
VDD
106
BA1
108
RAS#
110
VDD
112
S0#
114
ODT0
116
VDD
118
ODT1
120
NC
122
VDD
124
VREF_CA
126
VSS
128
DQ36
130
DQ37
132
VSS
134
DM4
136
VSS
138
DQ38
140
DQ39
142
VSS
144
DQ44
146
DQ45
148
VSS
150
DQS5#
152
DQS5
154
VSS
156
DQ46
158
DQ47
160
VSS
162
DQ52
164
DQ53
166
VSS
168
DM6
170
VSS
172
DQ54
174
DQ55
176
VSS
178
DQ60
180
DQ61
182
VSS
184
DQS7#
186
DQS7
188
VSS
190
DQ62
192
DQ63
194
VSS
196
EVENT#
198
SDA
200
SA1
201
VTT
203
GND1
205
SCL
202
VTT
204
GND1
206
C306
0.1U_0402_10V6K
C306
0.1U_0402_10V6K
1
2
C575
10U_0603_6.3V6M
C575
10U_0603_6.3V6M
1
2
C618
2.2U_0603_6.3V4Z
C618
2.2U_0603_6.3V4Z
1
2
C616
0.1U_0402_10V6K
C616
0.1U_0402_10V6K
1
2
C307
0.1U_0402_10V6K
C307
0.1U_0402_10V6K
1
2
C385
0.1U_0402_10V6K
C385
0.1U_0402_10V6K
1
2
C598
1U_0603_10V4Z
C598
1U_0603_10V4Z
1
2
C582
10U_0603_6.3V6M
@
C582
10U_0603_6.3V6M
@
1
2
C590
10U_0603_6.3V6M
C590
10U_0603_6.3V6M
1
2
C576
10U_0603_6.3V6M
C576
10U_0603_6.3V6M
1
2
C311
10U_0603_6.3V6M
C311
10U_0603_6.3V6M
1
2
C312
10U_0603_6.3V6M
C312
10U_0603_6.3V6M
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_XTAL_IN
CLK_XTAL_OUT
CLK_XTAL_OUT
SMB_CLK_S3
SMB_DATA_S3
CLK_XTAL_IN
CK_PWRGD
CPU_STOP#
CLK_14M_PCH
R_CLK_BUF_BCLK# CLK_BUF_BCLK#
CLK_48M_CR_R
REF_0/CPU_SEL
CLK_14M_PCH
CLK_BUF_DOT96#
CLK_BUF_DOT96
L_CLK_BUF_DOT96#
L_CLK_BUF_DOT96
CLK_DMI#
CLK_DMI
L_CLK_DMI#
L_CLK_DMI
CLK_48M_CR_R
CK_PWRGD
REF_0/CPU_SEL
REF_0/CPU_SEL
R_CLK_BUF_BCLK CLK_BUF_BCLK
VDD_3V3_1V5
VDD_3V3_1V5
VDD_3V3_1V5
VDD_3V3_1V5
CLK_BUF_CKSSCD
CLK_BUF_CKSSCD#
CLK_BUF_CKSSCD_R
CLK_BUF_CKSSCD#_R
CLK_BUF_BCLK# <14>
CLK_BUF_BCLK <14>
CLK_14M_PCH <14>
CLK_EN# <48>
CLK_DMI<14>
CLK_DMI#<14>
CLK_BUF_DOT96<14>
CLK_BUF_DOT96#<14>
SMB_DATA_S3 <10,11,14,28>
SMB_CLK_S3 <10,11,14,28>
CLK_48M_CR
CLK_BUF_CKSSCD<14>
CLK_BUF_CKSSCD#<14>
+3VS
+3VS_CK505
+1.05VS_CK505+1.05VS
+3VS_CK505 +1.05VS_CK505+3VS_CK505 +1.05VS_CK505
+1.05VS
+3VS_CK505
+3VS_CK505
VDD_3V3_1V5+3VS_CK505
+1.5VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
CLOCK GENERATOR
12 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
CLOCK GENERATOR
12 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
CLOCK GENERATOR
12 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
1 PCS CAP(0.1u) BY 1 INPUT PIN
S IC ICS9LRS3199AKLFT MLF 32P CLK GEN (SA000030P00)
1 PCS CAP(0.1u) BY 1 INPUT PIN
1
CPU_1PIN 30 CPU_0
0 133MHz
(Default)
133MHz
100MHz 100MHz
CLOSE U14
CLK GEN TO PCH
1. CLK_DMI
EMI Capacitor
2. CLK_BUF_BCLK
3. CLK_BUF_CKSSCD
4. CLK_BUF_DOT96
5. CLK_14M_PCH
PIN8 IS GND FOR ICS3197
PIN8 IS 48MHz FOR ICS3199
CLK GEN TO VGA
Unused
1. 27M_CLK
1. 27M_CLK_SS
S IC SLG8SP587VTR QFN 32P CLK GEN (SA00002XY00)
Reserve for Low Power CLK GEN.
RTM890N-631(SA00003HQ00)
SLG8LV597VTR
9VLS3199 (SA00003HR00)
1 PCS CAP(0.1u) BY 1 INPUT PIN
unstuff 09.09.08
R2780_0603_5%
@
R2780_0603_5%
@
1 2
C344
10U_0805_10V4Z
C344
10U_0805_10V4Z
1
2
C366
0.1U_0402_10V6K
C366
0.1U_0402_10V6K
1
2
C364
10P_0402_50V8J@
C364
10P_0402_50V8J@
12
C336
10U_0805_10V4Z
C336
10U_0805_10V4Z
1
2
R308
0_0402_5%
R308
0_0402_5%
1 2
Y1
14.31818MHZ_16PF_DSX840GA
Y1
14.31818MHZ_16PF_DSX840GA
12
C367
0.1U_0402_10V6K
C367
0.1U_0402_10V6K
1
2
U14
RTM890N-631-GRT QFN 32P
U14
RTM890N-631-GRT QFN 32P
CPU_1#
19
SATA
10
CKPWRGD/PD#
25
DOT_96#
4
CPU_0#
22
XTAL_OUT
27
VSS_REF
26
VDD_CPU
24
CPU_0
23
27MHZ_SS
7
XTAL_IN
28
27MHZ
6
USB_48
8
CPU_1
20
VSS_CPU
21
VDD_CPU_IO
18
VDD_USB_48
1
VSS_48M
2
REF_0/CPU_SEL
30
SDA
31
SCL
32
VDD_27
5
VSS_27M
9
SATA#
11
VSS_SRC
12
SRC_1
13
SRC_1#
14
VDD_SRC_IO
15
VDD_SRC
17
VDD_REF
29
DOT_96
3
CPU_STOP#
16
TGND
33
R2790_0603_5% R2790_0603_5%
1 2
R2770_0603_5% R2770_0603_5%
1 2
C331
10U_0805_10V4Z
C331
10U_0805_10V4Z
1
2
R276 0_0402_5%R276 0_0402_5%
1 2
R298
10K_0402_5%
R298
10K_0402_5%
1 2
C343
0.1U_0402_10V6K
C343
0.1U_0402_10V6K
1
2
G
D
S
Q25
2N7002_SOT23-3
G
D
S
Q25
2N7002_SOT23-3
2
13
R2690_0603_5% R2690_0603_5%
1 2
C342
0.1U_0402_10V6K
C342
0.1U_0402_10V6K
1
2
C330
0.1U_0402_10V6K
C330
0.1U_0402_10V6K
1
2
C332
0.1U_0402_10V6K
C332
0.1U_0402_10V6K
1
2
C334
0.1U_0402_10V6K
C334
0.1U_0402_10V6K
1
2
R306
0_0402_5%
R306
0_0402_5%
1 2
C348
22P_0402_50V8J
C348
22P_0402_50V8J
C350
0.1U_0402_10V6K
C350
0.1U_0402_10V6K
1
2
R315
33_0402_1%
R315
33_0402_1%
12
R319 0_0402_5%R319 0_0402_5%
1 2
R3230_0402_5%
@
R3230_0402_5%
@
12
C365
10P_0402_50V8J@
C365
10P_0402_50V8J@
12
R307 0_0402_5%R307 0_0402_5%
1 2
R324 0_0402_5%R324 0_0402_5%
1 2
C349
22P_0402_50V8J
C349
22P_0402_50V8J
R32233_0402_1% @ R32233_0402_1% @
1 2
R275 0_0402_5%R275 0_0402_5%
1 2
R299
10K_0402_5%
R299
10K_0402_5%
1 2
R316 10K_0402_5%R316 10K_0402_5%
1 2
R317 10K_0402_5%@R317 10K_0402_5%@
1 2
R318 0_0402_5%R318 0_0402_5%
1 2
C335
0.1U_0402_10V6K
C335
0.1U_0402_10V6K
1
2
C333
10U_0805_10V4Z
C333
10U_0805_10V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCH_RTCX1
PCH_RTCX2
PCH_RTCX1
PCH_RTCX2
PCH_RTCRST#
PCH_SRTCRST#
SM_INTRUDER#
PCH_INTVRMEN
SM_INTRUDER#
HDA_RST#
PCH_SPKR
HDA_SDIN1
SERIRQ
GPIO23
SATAICOMPPCH_JTAG_RST#
PCH_JTAG_TMS
PCH_JTAG_TDI
PCH_JTAG_TDO
BITCLK
HDA_SYNC
HDA_SDIN0
HDA_SDOUT
PCH_INTVRMEN
SATA_ITX_DRX_P0
SATA_ITX_DRX_N0
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_C_DRX_N0
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N4
SATA_ITX_C_DRX_P4
SATA_ITX_DRX_P1
SATA_ITX_DRX_N1
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_C_DRX_N1
SATA_ITX_C_DRX_P1
PCH_JTAG_TCK
SPI_WP#
SPI_HOLD#
SPI_CLK_PCH_R
SPI_SB_CS0#
SPI_SI
SPI_SO_R
PCH_JTAG_TMS PCH_JTAG_RST#PCH_JTAG_TDO PCH_JTAG_TDI
GPIO19
GPIO21
GPIO19
GPIO21
PCH_SPKR
GPIO13
SPI_WP#
SPI_HOLD#
SPI_SB_CS0#
SPI_SO_R SPI_SO_L
SPI_SI
SPI_CLK_PCH
SPI_CLK_PCH
SPI_CLK_PCH
SATA_ITX_DRX_N4_CONN
SATA_DTX_C_IRX_N4
SATA_ITX_DRX_P4_CONN
SATA_DTX_C_IRX_P4
PCH_JTAG_TCK
HDA_SDIN1<33>
LPC_AD0 <28,34>
LPC_AD1 <28,34>
LPC_AD2 <28,34>
LPC_AD3 <28,34>
LPC_FRAME# <28,34>
SERIRQ <34>
HDD_LED# <36>
HDA_BITCLK_CODEC<33>
HDA_SYNC_CODEC<33>
HDA_RST_CODEC#<33>
HDA_SDOUT_CODEC<33>
SATA_DTX_C_IRX_N0 <32>
SATA_DTX_C_IRX_P0 <32>
SATA_ITX_DRX_N0 <32>
SATA_ITX_DRX_P0 <32>
SATA_ITX_DRX_N1 <32>
SATA_ITX_DRX_P1 <32>
SATA_DTX_C_IRX_N1 <32>
SATA_DTX_C_IRX_P1 <32>
PCH_SPKR<33>
ME_FLASH<34>
SATA_DTX_C_IRX_P4 <37>
SATA_ITX_DRX_N4_CONN <37>
SATA_DTX_C_IRX_N4 <37>
SATA_ITX_DRX_P4_CONN <37>
+RTCVCC
+RTCVCC
+1.05VS
+3VS
+3VS
+3VS
+3VALW+3VALW +3VALW +3VALW +3VS
+RTCVCC
+RTCBATT
+3VS
+3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(1/6)-HDA/JTAG/SATA
Custom
13 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(1/6)-HDA/JTAG/SATA
Custom
13 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(1/6)-HDA/JTAG/SATA
Custom
13 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
H
：
Integrated VRM enable
L
：
Integrated VRM disable
*
GPIO33 = GPO , internal pull-up,should not be pulled low
GPIO19 = GPI,3.3V,CORE
GPIO21 = GPI,3.3V,CORE
GPIO23 = NATIVE,3.3V,CORE
GPIO13 = GPI,3.3V,SUS
flash ME core of strap pin pull down
*
No Install
No Install
No Install
100ohm 100ohm
100ohm 100ohm
10Kohm 10Kohm
20Kohm 20Kohm
100ohm
200ohm
200ohm
200ohm
200ohm
200ohm
51ohm
No Install
R580
No Install
No InstallPCH_JTAG_TMS
PCH JTAG
Pre-Production
PCH JTAG
Production
RefDesPCH Pin
No InstallPCH_JTAG_TDO
ES1 MPES2
PCH_JTAG_TDI
PCH_JTAG_TCK
PCH_JTAG_RST#
R584
R583
R591
R590
No InstallR587
R586
R595
R594
No Install
No Install
51ohm 51ohm
(2009,07,07)
4MB SPI ROM FOR HM55
& Non-share ROM.
HDD
ODD
E-SATA
(2009,05,04)
FOR INTEL DPDG REV1.6 (MAY 2009)
RF team request.
R453 10K_0402_5%R453 10K_0402_5%
1 2
R118
10K_0402_5%
@
R118
10K_0402_5%
@
12
R144
100_0603_1%
R144
100_0603_1%
1 2
R62
3.3K_0402_5%
R62
3.3K_0402_5%
1 2
T7 PADT7 PAD
RTCIHDA
SATA
LPC
SPI JTAG
U7A
IBEXPEAK-M_FCBGA1071
RTCIHDA
SATA
LPC
SPI JTAG
U7A
IBEXPEAK-M_FCBGA1071
RTCX1
B13
RTCX2
D13
INTVRMEN
A14
INTRUDER#
A16
HDA_BCLK
A30
HDA_SYNC
D29
HDA_RST#
C30
HDA_SDIN0
G30
HDA_SDIN1
F30
HDA_SDIN2
E32
HDA_SDO
B29
SATALED#
T3
FWH0 / LAD0
D33
FWH1 / LAD1
B33
FWH2 / LAD2
C32
FWH3 / LAD3
A32
LDRQ1# / GPIO23
F34
FWH4 / LFRAME#
C34
LDRQ0#
A34
RTCRST#
C14
HDA_SDIN3
F32
HDA_DOCK_EN# / GPIO33
H32
HDA_DOCK_RST# / GPIO13
J30
SRTCRST#
D17
SATA0RXN
AK7
SATA0RXP
AK6
SATA0TXN
AK11
SATA0TXP
AK9
SATA1RXN
AH6
SATA1RXP
AH5
SATA1TXN
AH9
SATA1TXP
AH8
SATA2RXN
AF11
SATA2RXP
AF9
SATA2TXN
AF7
SATA2TXP
AF6
SATA3RXN
AH3
SATA3RXP
AH1
SATA3TXN
AF3
SATA3TXP
AF1
SATA4RXN
AD9
SATA4RXP
AD8
SATA4TXN
AD6
SATA4TXP
AD5
SATA5RXN
AD3
SATA5RXP
AD1
SATA5TXN
AB3
SATA5TXP
AB1
SATAICOMPI
AF15
SPI_CLK
BA2
SPI_CS0#
AV3
SPI_CS1#
AY3
SPI_MOSI
AY1
SPI_MISO
AV1
SATA0GP / GPIO21
Y9
SATA1GP / GPIO19
V1
JTAG_TCK
M3
JTAG_TMS
K3
JTAG_TDI
K1
JTAG_TDO
J2
TRST#
J4
SERIRQ
AB9
SPKR
P1
SATAICOMPO
AF16
R115
100_0402_1%
@
R115
100_0402_1%
@
12
R74
200_0402_5%
@
R74
200_0402_5%
@
12
U3
S IC FL 32M W25Q32BVSSIG SOIC 8P
U3
S IC FL 32M W25Q32BVSSIG SOIC 8P
CS#
1
SO
2
WP#
3
GND
4
VCC
8
HOLD#
7
SCLK
6
SI
5
C64712P_0402_50V8J
@
C64712P_0402_50V8J
@
1 2
C460
0.1U_0402_16V4Z
C460
0.1U_0402_16V4Z
1 2
C171
15P_0402_50V8J
C171
15P_0402_50V8J
1
2
R482
10K_0402_5%
R482
10K_0402_5%
1 2
R167 33_0402_5%R167 33_0402_5%
1 2
R100
33_0402_5%
@
R100
33_0402_5%
@
12
C64812P_0402_50V8J
@
C64812P_0402_50V8J
@
1 2
R420
330K_0402_5%
R420
330K_0402_5%
1 2
R114 51_0402_5%R114 51_0402_5%
1 2
CLRP3
SHORT PADS
CLRP3
SHORT PADS
12
R447
10K_0402_5%
R447
10K_0402_5%
1 2
CLRP2
SHORT PADS
CLRP2
SHORT PADS
12
C1400.01U_0402_16V7K C1400.01U_0402_16V7K
12
R500
37.4_0402_1%
R500
37.4_0402_1%
1 2
C183
15P_0402_50V8J
C183
15P_0402_50V8J
1
2
R47910K_0402_5% R47910K_0402_5%
12
C4280.01U_0402_16V7K C4280.01U_0402_16V7K
12
R169 33_0402_5%R169 33_0402_5%
1 2
R102
3.3K_0402_5%
R102
3.3K_0402_5%
1 2
R99
0_0402_5%
R99
0_0402_5%
1 2
R409 1K_0402_5%@R409 1K_0402_5%@
1 2
C202
1U_0603_10V4Z
C202
1U_0603_10V4Z
1
2
R422 20K_0402_1%R422 20K_0402_1%
1 2
C4270.01U_0402_16V7K C4270.01U_0402_16V7K
12
R75
20K_0402_5%
@
R75
20K_0402_5%
@
1 2
R116
100_0402_1%
@
R116
100_0402_1%
@
12
R117
100_0402_1%
@
R117
100_0402_1%
@
12
R452 1K_0402_5%@R452 1K_0402_5%@
1 2
CLRP1
SHORT PADS
CLRP1
SHORT PADS
12
C1420.01U_0402_16V7K
ESATA@
C1420.01U_0402_16V7K
ESATA@
12
R168 33_0402_5%R168 33_0402_5%
1 2
R154 10M_0402_5%R154 10M_0402_5%
1 2
R73
200_0402_5%
@
R73
200_0402_5%
@
12
R166 33_0402_5%R166 33_0402_5%
1 2
R425 0_0402_5%R425 0_0402_5%
1 2
C1430.01U_0402_16V7K
ESATA@
C1430.01U_0402_16V7K
ESATA@
12
R424 10K_0402_5%
@
R424 10K_0402_5%
@
1 2
C1410.01U_0402_16V7K C1410.01U_0402_16V7K
12
R103
15_0402_5%
R103
15_0402_5%
1 2
C441
0.1U_0402_16V4Z
C441
0.1U_0402_16V4Z
1
2
R72
200_0402_5%
@
R72
200_0402_5%
@
12
R101
15_0402_5%
R101
15_0402_5%
12
X1
32.768KHZ_12.5PF_9H03200413
X1
32.768KHZ_12.5PF_9H03200413
OSC
4
OSC
1
NC
3
NC
2
C138
22P_0402_50V8J
@
C138
22P_0402_50V8J
@
R421
1M_0402_5%
R421
1M_0402_5%
1 2
R419 20K_0402_1%R419 20K_0402_1%
1 2
C184
1U_0603_10V4Z
C184
1U_0603_10V4Z
1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
CLK_PCIE_WLAN1_R
CLK_PCIE_WLAN1#_R
PCIE_PTX_DRX_P3
PCIE_PTX_DRX_N3
PCIE_PRX_DTX_P3
PCIE_PRX_DTX_N3
PCIE_PTX_DRX_P2
PCIE_PTX_DRX_N2
PCIE_PRX_DTX_P2
PCIE_PRX_DTX_N2
LID_OUT#
SMBCLK
SMBDATA
GPIO60
SML0CLK
SML0DATA
GPIO74
SMB_EC_CK2_REC_SMB_CK2
SMB_EC_DA2_REC_SMB_DA2
EC_SMB_CK2
EC_SMB_DA2
SML1CLK
SML1DATA
LID_OUT#
PEG_CLKREQ#
SMBCLK
SMBDATA
SML1CLK
SML1DATA
SML0CLK
SML0DATA
GPIO74
SMB_CLK_S3
SMB_DATA_S3
SMB_CLK_S3
SMB_DATA_S3
XTAL25_IN
CLK_14M_PCH
GPIO60
SMBCLK
SMBDATA SMB_DATA_S3
SMB_CLK_S3
SMB_EC_CK2_R
SMB_EC_DA2_R
EC_SMB_CK2
EC_SMB_DA2
PEG_CLKREQ#
CLK_PCI_FB
CLK_PCIE_LAN_R
CLK_PCIE_LAN#_R
CLKOUT_DP_N
CLKOUT_DP_P
CLK_14M_PCHCLK_PCI_FB
CLK_PCIE_VGA#
CLK_PCIE_VGA
CLK_PCIE_VGA#_R
CLK_PCIE_VGA_R
CLK_EXP#_R
CLK_EXP_R
PCIE_PTX_DRX_P4
PCIE_PRX_DTX_N4
PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
CLK_PCIE_CARD_PCH#_R
CLK_PCIE_CARD_PCH_R
CLK_PCI_DB_R
XTAL25_IN
XTAL25_OUT
XTAL25_OUT
PCIE_PTX_DRX_P5
PCIE_PTX_DRX_N5
PCIE_PRX_DTX_P5
PCIE_PRX_DTX_N5
CLK_PCIE_EXP_PCH_R
CLK_PCIE_EXP_PCH#_R
CLKREQ_EXP#
WLAN_CLKREQ1#<28>
CLK_PCIE_WLAN1<28>
CLK_PCIE_WLAN1#<28>
PCIE_PTX_C_DRX_P2<28>
PCIE_PRX_DTX_N2<28>
PCIE_PTX_C_DRX_N2<28>
PCIE_PRX_DTX_P2<28>
PCIE_PTX_C_DRX_P3<29>
PCIE_PRX_DTX_N3<29>
PCIE_PTX_C_DRX_N3<29>
PCIE_PRX_DTX_P3<29>
SMB_EC_DA2_R <19,31>
SMB_EC_CK2_R <19,31>
EC_SMB_CK2 <34>
EC_SMB_DA2 <34>
CLK_14M_PCH <12>
SMB_CLK_S3 <10,11,12,28>
SMB_DATA_S3 <10,11,12,28>
CLK_DMI# <12>
CLK_DMI <12>
CLK_BUF_BCLK <12>
CLK_BUF_BCLK# <12>
CLK_BUF_DOT96 <12>
CLK_BUF_DOT96# <12>
CLK_BUF_CKSSCD <12>
CLK_BUF_CKSSCD# <12>
SMBCLK
SMBDATA
CLK_PCI_FB <16>
EC_LID_OUT# <34>
CLKREQ_LAN#<29>
CLK_PCIE_LAN<29>
CLK_PCIE_LAN#<29>
PEG_CLKREQ# <19>
CLK_PCIE_VGA# <19>
CLK_PCIE_VGA <19>
CLK_EXP <5>
CLK_EXP# <5>
PCIE_PTX_C_DRX_P4<28>
PCIE_PTX_C_DRX_N4<28>
PCIE_PRX_DTX_N4<28>
PCIE_PRX_DTX_P4<28>
CLK_PCIE_CARD_PCH#<28>
CLK_PCIE_CARD_PCH<28>
PCIECLKREQ3#<28>
CLK_PCI_DB <28>
PCIE_PTX_C_DRX_P5<28>
PCIE_PRX_DTX_N5<28>
PCIE_PTX_C_DRX_N5<28>
PCIE_PRX_DTX_P5<28>
CLK_PCIE_EXP_PCH<28>
CLK_PCIE_EXP_PCH#<28>
CLKREQ_EXP#<28>
+3VALW
+3VALW
+3VALW
+3VALW
+3VS
+3VALW
+3VS
+3VS
+3VS
+1.05VS
+3VS +3VALW
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(2/6)-PCI-E/SMBUS/CLK
Custom
14 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(2/6)-PCI-E/SMBUS/CLK
Custom
14 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(2/6)-PCI-E/SMBUS/CLK
Custom
14 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
WLAN
WLAN
LAN
LAN
Nvidia thermal
sensor
DTS , read from EC
DDR3*2 AND CLK GEN
EC_THERMAL
NEW CARD
WLAN
MINI1
LAN
WLAN
NEW CARD
LAN
6
4
DEVICEPORT
5
3
2
PCIE PORT LIST
1
7
8
X
X
X
GPIO11 = NATIVE,3.3V,SUS
GPIO60 = NATIVE,3.3V,SUS
GPIO74 = NATIVE,3.3V,SUS
GPIO47 = 10Kohm PULL DOWN
GPIO56 = NATIVE,3.3V,SUS
GPIO44 = NATIVE,3.3V,SUS
GPIO26 = NATIVE,3.3V,SUS
GPIO25 = NATIVE,3.3V,SUS
GPIO20 = NATIVE,3.3V,CORE
GPIO18 = NATIVE,3.3V,CORE
GPIO73 = NATIVE,3.3V,SUS
EMI REQUEST 0303
3G
3G
3G
X
XTAL25_IN needs a
pull-down to GND via
a 0Ω resistor.
Calpella
schematic
checklist REV1.6
EXP
EXP
R220 0_0402_5%R220 0_0402_5%
1 2
R81 0_0402_5%
@
R81 0_0402_5%
@
1 2
R223 0_0402_5%3G@R223 0_0402_5%3G@
1 2
C222 0.1U_0402_10V6KC222 0.1U_0402_10V6K
1 2
R225 0_0402_5%R225 0_0402_5%
1 2
R413
33_0402_5%
@
R413
33_0402_5%
@
1 2
C221 0.1U_0402_10V6KC221 0.1U_0402_10V6K
1 2
R122
0_0402_5%
@
R122
0_0402_5%
@
1 2
R148 2.2K_0402_5%R148 2.2K_0402_5%
1 2
R404 2.2K_0402_5%R404 2.2K_0402_5%
1 2
R222 0_0402_5%
3G@
R222 0_0402_5%
3G@
1 2
R598 1M_0402_5%@R598 1M_0402_5%@
1 2
C231 0.1U_0402_10V6K
3G@
C231 0.1U_0402_10V6K
3G@
1 2
R224 0_0402_5%R224 0_0402_5%
1 2
R491 90.9_0402_1%R491 90.9_0402_1%
1 2
R106 0_0402_5%R106 0_0402_5%
1 2
C220 0.1U_0402_10V6KC220 0.1U_0402_10V6K
1 2
R105 0_0402_5%R105 0_0402_5%
1 2
C631
18P_0402_50V8J
@
C631
18P_0402_50V8J
@
1
2
C263
22P_0402_50V8J
@
C263
22P_0402_50V8J
@
R434 10K_0402_5%R434 10K_0402_5%
1 2
R79
0_0402_5%
R79
0_0402_5%
C232 0.1U_0402_10V6K
3G@
C232 0.1U_0402_10V6K
3G@
1 2
R525 0_0402_5%R525 0_0402_5%
1 2
C223 0.1U_0402_10V6KC223 0.1U_0402_10V6K
1 2
R407
0_0402_5%
R407
0_0402_5%
C229 0.1U_0402_10V6KC229 0.1U_0402_10V6K
1 2
C630
18P_0402_50V8J
@
C630
18P_0402_50V8J
@
1
2
R431 10K_0402_5%R431 10K_0402_5%
1 2
R457 10K_0402_5%R457 10K_0402_5%
1 2
R197 0_0402_5%R197 0_0402_5%
1 2
R78 2.2K_0402_5%R78 2.2K_0402_5%
1 2
R196 0_0402_5%R196 0_0402_5%
1 2
R524 0_0402_5%R524 0_0402_5%
1 2
R41210K_0402_5% R41210K_0402_5%
1 2
R147 2.2K_0402_5%R147 2.2K_0402_5%
1 2
R198
22_0402_5%
@
R198
22_0402_5%
@
1 2
Y4
25MHZ_20P_1BG25000CK1A
@Y4
25MHZ_20P_1BG25000CK1A
@
1 2
R406 10K_0402_5%R406 10K_0402_5%
1 2
R80
0_0402_5%
R80
0_0402_5%
R209
33_0402_5%
@
R209
33_0402_5%
@
1 2
R400 10K_0402_5%R400 10K_0402_5%
1 2
Q8B
2N7002DW-T/R7_SOT363-6
Q8B
2N7002DW-T/R7_SOT363-6
3
5
4
C631
0_0402_5%
C631
0_0402_5%
R83 0_0402_5%
@
R83 0_0402_5%
@
1 2
R435 10K_0402_5%R435 10K_0402_5%
1 2
C439
22P_0402_50V8J
@
C439
22P_0402_50V8J
@
R403 2.2K_0402_5%R403 2.2K_0402_5%
1 2
C230 0.1U_0402_10V6KC230 0.1U_0402_10V6K
1 2
R221 0_0402_5%R221 0_0402_5%
1 2
R124
2.2K_0402_5%
R124
2.2K_0402_5%
R145 10K_0402_5%R145 10K_0402_5%
1 2
R119
0_0402_5%
@
R119
0_0402_5%
@
1 2
R123 2.2K_0402_5%R123 2.2K_0402_5%
1 2
R399 10K_0402_5%R399 10K_0402_5%
1 2
R121 10K_0402_5%R121 10K_0402_5%
1 2
PCI-E*
SMBus
Controller
From CLK BUFFER
PEG
Clock Flex
Link
U7B
IBEXPEAK-M_FCBGA1071
PCI-E*
SMBus
Controller
From CLK BUFFER
PEG
Clock Flex
Link
U7B
IBEXPEAK-M_FCBGA1071
PERN1
BG30
PERP1
BJ30
PERN2
AW30
PERP2
BA30
PERN3
AU30
PERP3
AT30
PERN4
BA32
PERP4
BB32
PERN5
BF33
PERP5
BH33
PERN6
BA34
PERP6
AW34
PERN7
AT34
PERP7
AU34
PERN8
BG34
PERP8
BJ34
PETN1
BF29
PETP1
BH29
PETN2
BC30
PETP2
BD30
PETN3
AU32
PETP3
AV32
PETN4
BD32
PETP4
BE32
PETN5
BG32
PETP5
BJ32
PETN6
BC34
PETP6
BD34
PETN7
AU36
PETP7
AV36
PETN8
BG36
PETP8
BJ36
SMBALERT# / GPIO11
B9
SMBCLK
H14
SMBDATA
C8
SML0CLK
C6
SML0DATA
G8
CLKOUT_PCIE0N
AK48
CLKOUT_PCIE0P
AK47
CLKOUT_PCIE1N
AM43
CLKOUT_PCIE1P
AM45
CLKOUT_PCIE2N
AM47
CLKOUT_PCIE2P
AM48
CLKOUT_PCIE3N
AH42
CLKOUT_PCIE3P
AH41
CLKOUT_PCIE4N
AM51
CLKOUT_PCIE4P
AM53
CLKOUT_PCIE5N
AJ50
CLKOUT_PCIE5P
AJ52
SML0ALERT# / GPIO60
J14
CL_CLK1
T13
CL_DATA1
T11
CL_RST1#
T9
CLKIN_BCLK_N
AP3
CLKIN_BCLK_P
AP1
CLKIN_DMI_N
AW24
CLKIN_DMI_P
BA24
CLKIN_DOT_96N
F18
CLKIN_DOT_96P
E18
CLKIN_SATA_N / CKSSCD_N
AH13
CLKIN_SATA_P / CKSSCD_P
AH12
XTAL25_IN
AH51
XTAL25_OUT
AH53
REFCLK14IN
P41
CLKIN_PCILOOPBACK
J42
CLKOUT_PEG_A_N
AD43
CLKOUT_PEG_A_P
AD45
PEG_A_CLKRQ# / GPIO47
H1
PCIECLKRQ0# / GPIO73
P9
PCIECLKRQ1# / GPIO18
U4
PCIECLKRQ2# / GPIO20
N4
PCIECLKRQ3# / GPIO25
A8
PCIECLKRQ4# / GPIO26
M9
PCIECLKRQ5# / GPIO44
H6
CLKOUTFLEX0 / GPIO64
T45
CLKOUTFLEX1 / GPIO65
P43
CLKOUTFLEX2 / GPIO66
T42
CLKOUTFLEX3 / GPIO67
N50
CLKOUT_DMI_N
AN4
CLKOUT_DMI_P
AN2
PEG_B_CLKRQ# / GPIO56
P13
CLKOUT_PEG_B_P
AK51
CLKOUT_PEG_B_N
AK53
SML1ALERT# / GPIO74
M14
SML1CLK / GPIO58
E10
SML1DATA / GPIO75
G12
XCLK_RCOMP
AF38
CLKOUT_DP_P / CLKOUT_BCLK1_P
AT3
CLKOUT_DP_N / CLKOUT_BCLK1_N
AT1
R113 10K_0402_5%R113 10K_0402_5%
1 2
R82
2.2K_0402_5%
R82
2.2K_0402_5%
R120 10K_0402_5%R120 10K_0402_5%
1 2
Q7B
2N7002DW-T/R7_SOT363-6
Q7B
2N7002DW-T/R7_SOT363-6
3
5
4
Q8A
2N7002DW-T/R7_SOT363-6
Q8A
2N7002DW-T/R7_SOT363-6
6 1
2
R454 10K_0402_5%R454 10K_0402_5%
1 2
Q7A
2N7002DW-T/R7_SOT363-6
Q7A
2N7002DW-T/R7_SOT363-6
6 1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PM_RSMRST#
SLP_S4#
SLP_S5#
SYS_RST#
PM_DRAM_PWRGD
GPIO61
GPIO62
SYS_PWROK
SLP_S3#
GPIO72
PBTN_OUT#
DMI_CTX_PRX_N2
DMI_CRX_PTX_N0
DMI_CRX_PTX_N1
DMI_CRX_PTX_N2
DMI_CRX_PTX_N3
DMI_CRX_PTX_P0
DMI_CRX_PTX_P1
DMI_CRX_PTX_P2
DMI_CRX_PTX_P3
DMI_CTX_PRX_N1
DMI_CTX_PRX_N0
PM_RSMRST#
DMI_CTX_PRX_N3
DMI_CTX_PRX_P1
DMI_CTX_PRX_P2
DMI_CTX_PRX_P0
DMI_CTX_PRX_P3
DMI_IRCOMP
AC_PRESENT_R
CRT_IREF
FDI_CTX_PRX_N0
FDI_CTX_PRX_N1
FDI_CTX_PRX_N2
FDI_CTX_PRX_N3
FDI_CTX_PRX_N4
FDI_CTX_PRX_N6
FDI_CTX_PRX_N5
FDI_CTX_PRX_P1
FDI_CTX_PRX_N7
FDI_CTX_PRX_P0
FDI_CTX_PRX_P3
FDI_CTX_PRX_P2
FDI_CTX_PRX_P6
FDI_CTX_PRX_P5
FDI_CTX_PRX_P4
FDI_CTX_PRX_P7
FDI_INT
FDI_FSYNC1
FDI_FSYNC0
FDI_LSYNC1
FDI_LSYNC0
PCH_ENVDD
EDID_DATA
EDID_CLK
DAC_BLU
DAC_RED
DAC_GRN
HDMICLK_NB
HDMIDAT_NB
TMDS_B_DATA2#_PCH
TMDS_B_DATA2_PCH
TMDS_B_DATA1#_PCH
TMDS_B_DATA0#_PCH
TMDS_B_DATA1_PCH
TMDS_B_DATA0_PCH
TMDS_B_CLK_PCH
DAC_BLU
DAC_RED
DAC_GRN
PCH_ENBKL
EDID_CLK
EDID_DATA
SUS_PWR_DN_ACK_R
TMDS_B_CLK#_PCH
SYS_PWROK
VGATE
ICH_POK
PCIE_WAKE#
VGATE<48>
ICH_POK<34>
PBTN_OUT#<34>
PM_DRAM_PWRGD<5>
PCIE_WAKE# <28>
SLP_S5# <34>
H_PM_SYNC <5>
SLP_S4# <34>
SLP_S3# <34>
EC_RSMRST#<34>
DMI_CRX_PTX_N0<6>
DMI_CTX_PRX_N0<6>
DMI_CTX_PRX_N1<6>
DMI_CTX_PRX_N2<6>
DMI_CTX_PRX_N3<6>
DMI_CTX_PRX_P0<6>
DMI_CTX_PRX_P1<6>
DMI_CTX_PRX_P2<6>
DMI_CTX_PRX_P3<6>
DMI_CRX_PTX_N1<6>
DMI_CRX_PTX_N2<6>
DMI_CRX_PTX_N3<6>
DMI_CRX_PTX_P0<6>
DMI_CRX_PTX_P1<6>
DMI_CRX_PTX_P2<6>
DMI_CRX_PTX_P3<6>
AC_PRESENT<34>
FDI_CTX_PRX_N0 <6>
FDI_CTX_PRX_N1 <6>
FDI_CTX_PRX_N3 <6>
FDI_CTX_PRX_N2 <6>
FDI_CTX_PRX_N5 <6>
FDI_CTX_PRX_N4 <6>
FDI_CTX_PRX_N7 <6>
FDI_CTX_PRX_N6 <6>
FDI_CTX_PRX_P1 <6>
FDI_CTX_PRX_P0 <6>
FDI_CTX_PRX_P3 <6>
FDI_CTX_PRX_P2 <6>
FDI_CTX_PRX_P4 <6>
FDI_CTX_PRX_P5 <6>
FDI_CTX_PRX_P7 <6>
FDI_CTX_PRX_P6 <6>
FDI_INT <6>
FDI_FSYNC0 <6>
FDI_LSYNC0 <6>
FDI_FSYNC1 <6>
FDI_LSYNC1 <6>
LVDS_ACLK#<27>
LVDS_ACLK<27>
LVDS_A0#<27>
LVDS_A1#<27>
LVDS_A2#<27>
LVDS_A0<27>
LVDS_A1<27>
LVDS_A2<27>
EDID_DATA<27>
PCH_ENVDD<27>
PCH_PWM<27>
EDID_CLK<27>
CRT_HSYNC<26>
CRT_VSYNC<26>
CRT_DDC_CLK<26>
CRT_DDC_DATA<26>
DAC_BLU<26>
DAC_GRN<26>
DAC_RED<26>
TMDS_B_HPD# <25>
HDMIDAT_NB <25>
HDMICLK_NB <25>
PCH_ENBKL<27>
SUS_PWR_DN_ACK<34>
TMDS_B_DATA2# <25>
TMDS_B_DATA2 <25>
TMDS_B_DATA1# <25>
TMDS_B_DATA1 <25>
TMDS_B_DATA0# <25>
TMDS_B_DATA0 <25>
TMDS_B_CLK# <25>
TMDS_B_CLK <25>
+3VALW
+3VS
+3VALW
+3VALW
+3VALW
+1.05VS
+3VS
+3VALW
+3VS
+3VS
+3VS
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(3/6)-DMI/GPIO/LVDS
Custom
15 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(3/6)-DMI/GPIO/LVDS
Custom
15 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(3/6)-DMI/GPIO/LVDS
Custom
15 51Friday, October 30, 2009
2008/10/31 2009/10/31
Compal Electronics, Inc.
LA-5751
GPIO61 = NATIVE,3.3V,SUS
GPIO62 = NATIVE,3.3V,SUS
Checklist0.8
：
MEPWROK
can be connect to
PWROK if iAMT disable
If not using integrated
LAN,signal may be left as NC.
Can be left NC when IAMT is
not support on the platfrom
GPIO29 = GPO,3.3V,SUS
GPIO31 = GPI,3.3V,SUS
GPIO30 = GPI,3.3V,SUS
RSMRST circuit
4mil width and place
within 500mil of the PCH
GPIO32 = GPO,3.3V,CORE
CRT OUT
(2009,05,04)
HDMI
UMA_HDMI@
Reserved
(2009,09,08)
R418 10K_0402_5%@R418 10K_0402_5%@
1 2
R496 10K_0402_5%R496 10K_0402_5%
1 2
R146 10K_0402_5%R146 10K_0402_5%
1 2
R417 10K_0402_5%@R417 10K_0402_5%@
1 2
C639 0.1U_0402_10V6KC639 0.1U_0402_10V6K
1 2
C644 0.1U_0402_10V6KC644 0.1U_0402_10V6K
1 2
T10 PADT10 PAD
LVDS
Digital Display Interface
CRT
U7D
IBEXPEAK-M_FCBGA1071
LVDS
Digital Display Interface
CRT
U7D
IBEXPEAK-M_FCBGA1071
L_BKLTCTL
Y48
L_BKLTEN
T48
L_CTRL_CLK
AB46
L_CTRL_DATA
V48
L_DDC_CLK
AB48
L_DDC_DATA
Y45
L_VDD_EN
T47
LVDSA_CLK#
AV53
LVDSA_CLK
AV51
LVDSA_DATA#0
BB47
LVDSA_DATA#1
BA52
LVDSA_DATA#2
AY48
LVDSA_DATA#3
AV47
LVDSA_DATA0
BB48
LVDSA_DATA1
BA50
LVDSA_DATA2
AY49
LVDSA_DATA3
AV48
LVDSB_CLK#
AP48
LVDSB_CLK
AP47
LVDSB_DATA#0
AY53
LVDSB_DATA#1
AT49
LVDSB_DATA#2
AU52
LVDSB_DATA#3
AT53
LVDSB_DATA0
AY51
DDPB_0N
BD42
DDPB_1N
BJ42
LVD_VREFH
AT43
LVD_VREFL
AT42
DDPD_2N
BF37
DDPD_3N
BE36
DDPB_2N
BB40
DDPB_3N
AW38
DDPC_0N
BE40
DDPC_1N
BF41
DDPC_2N
BD38
DDPC_3N
BB36
DDPD_0N
BJ40
DDPD_1N
BJ38
DDPB_0P
BC42
DDPB_1P
BG42
DDPD_2P
BH37
DDPD_3P
BD36
DDPB_2P
BA40
DDPB_3P
BA38
LVDSB_DATA1
AT48
LVDSB_DATA2
AU50
LVDSB_DATA3
AT51
LVD_IBG
AP39
LVD_VBG
AP41
DDPC_1P
BH41
DDPC_0P
BD40
DDPC_2P
BC38
DDPC_3P
BA36
DDPD_0P
BG40
DDPD_1P
BG38
CRT_BLUE
AA52
CRT_DDC_CLK
V51
CRT_DDC_DATA
V53
CRT_GREEN
AB53
CRT_HSYNC
Y53
CRT_IRTN
AB51
CRT_RED
AD53
CRT_VSYNC
Y51
DAC_IREF
AD48
SDVO_CTRLCLK
T51
SDVO_CTRLDATA
T53
DDPC_CTRLCLK
Y49
DDPC_CTRLDATA
AB49
DDPD_CTRLCLK
U50
DDPD_CTRLDATA
U52
DDPB_AUXN
BG44
DDPC_AUXN
BE44
DDPD_AUXN
BC46
DDPB_AUXP
BJ44
DDPC_AUXP
BD44
DDPD_AUXP
BD46
DDPB_HPD
AU38
DDPC_HPD
AV40
DDPD_HPD
AT38
SDVO_TVCLKINP
BG46
SDVO_TVCLKINN
BJ46
SDVO_STALLP
BG48
SDVO_STALLN
BJ48
SDVO_INTP
BH45
SDVO_INTN
BF45
R77 8.2K_0402_1%R77 8.2K_0402_1%
1 2
R416 10K_0402_5%@R416 10K_0402_5%@
1 2
R398 0_0402_5%@R398 0_0402_5%@
1 2
R450 10K_0402_5%R450 10K_0402_5%
1 2
R108 10K_0402_5%R108 10K_0402_5%
1 2
C645 0.1U_0402_10V6KC645 0.1U_0402_10V6K
1 2
DMI
FDI
System Power Management
U7C
IBEXPEAK-M_FCBGA1071
DMI
FDI
System Power Management
U7C
IBEXPEAK-M_FCBGA1071
DMI0RXN
BC24
DMI1RXN
BJ22
DMI2RXN
AW20
DMI3RXN
BJ20
DMI0RXP
BD24
DMI1RXP
BG22
DMI2RXP
BA20
DMI3RXP
BG20
DMI0TXN
BE22
DMI1TXN
BF21
DMI2TXN
BD20
DMI3TXN
BE18
DMI0TXP
BD22
DMI1TXP
BH21
DMI2TXP
BC20
DMI3TXP
BD18
DMI_ZCOMP
BH25
DMI_IRCOMP
BF25
FDI_RXN0
BA18
FDI_RXN1
BH17
FDI_RXN2
BD16
FDI_RXN3
BJ16
FDI_RXN4
BA16
FDI_RXN5
BE14
FDI_RXN6
BA14
FDI_RXN7
BC12
FDI_RXP0
BB18
FDI_RXP1
BF17
FDI_RXP2
BC16
FDI_RXP3
BG16
FDI_RXP4
AW16
FDI_RXP5
BD14
FDI_RXP6
BB14
FDI_RXP7
BD12
FDI_FSYNC0
BF13
FDI_FSYNC1
BH13
FDI_LSYNC0
BJ12
FDI_LSYNC1
BG14
FDI_INT
BJ14
PMSYNCH
BJ10
TP23
N2
SLP_M#
K8
SLP_S3#
P12
SLP_S4#
H7
SLP_S5# / GPIO63
E4
SYS_RESET#
T6
SYS_PWROK
M6
PWRBTN#
P5
RI#
F14
WAKE#
J12
SUS_STAT# / GPIO61
P8
SUSCLK / GPIO62
F3
ACPRESENT / GPIO31
P7
LAN_RST#
A10
MEPWROK
K5
BATLOW# / GPIO72
A6
PWROK
B17
CLKRUN# / GPIO32
Y1
SUS_PWR_DN_ACK / GPIO30
M1
RSMRST#
C16
DRAMPWROK
D9
SLP_LAN# / GPIO29
F6
R520 49.9_0402_1%R520 49.9_0402_1%
1 2
C640 0.1U_0402_10V6KC640 0.1U_0402_10V6K
1 2
R165 10K_0402_5%R165 10K_0402_5%
1 2
R458 2.2K_0402_5%UMA@R458 2.2K_0402_5%UMA@
D8B
BAV99DW-7_SOT363
D8B
BAV99DW-7_SOT363
4
5
3
C
B
E
Q14
MMBT3906_SOT23-3
C
B
E
Q14
MMBT3906_SOT23-3
1
2
3
R401
10K_0402_5%
R401
10K_0402_5%
12
R504
2.2K_0402_5%
UMA@
R504
2.2K_0402_5%
UMA@
12
R437 10K_0402_5%R437 10K_0402_5%
1 2
R495 150_0402_1%UMA@R495 150_0402_1%UMA@
1 2
R503
2.2K_0402_5%
UMA@
R503
2.2K_0402_5%
UMA@
12
R448
10K_0402_5%
R448
10K_0402_5%
1 2
R176 4.7K_0402_5%R176 4.7K_0402_5%
1 2
R175
2.2K_0402_5%
R175
2.2K_0402_5%
1 2
C641 0.1U_0402_10V6KC641 0.1U_0402_10V6K
1 2
R510 10K_0402_5%R510 10K_0402_5%
12
R451 0_0402_5%R451 0_0402_5%
1 2
R502
2.37K_0402_1%
R502
2.37K_0402_1%
12
R497
10K_0402_5%
R497
10K_0402_5%
1 2
U28
MC74VHC1G08DFT2G SC70 5P
@
U28
MC74VHC1G08DFT2G SC70 5P
@
B
2
A
1
Y
4
P
5
G
3
R494 150_0402_1%UMA@R494 150_0402_1%UMA@
1 2
R599 0_0402_5%@R599 0_0402_5%@
1 2
R397 0_0402_5%R397 0_0402_5%
1 2
R493 150_0402_1%UMA@R493 150_0402_1%UMA@
1 2
C642 0.1U_0402_10V6KC642 0.1U_0402_10V6K
1 2
C638 0.1U_0402_10V6KC638 0.1U_0402_10V6K
1 2
R402
0_0402_5%
@R402
0_0402_5%
@
1 2
R455
0_0402_5%
R455
0_0402_5%
1 2
R436 10K_0402_5%R436 10K_0402_5%
1 2
R498 2.2K_0402_5%UMA@R498 2.2K_0402_5%UMA@
R492
1K_0402_5%
R492
1K_0402_5%
12
R396 100K_0402_1%R396 100K_0402_1%
12
D8A
BAV99DW-7_SOT363
D8A
BAV99DW-7_SOT363
1
2
6
C643 0.1U_0402_10V6KC643 0.1U_0402_10V6K
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
USBRBIAS
USB20_N0
USB20_P0
USB20_N5
USB20_P5
USB20_P10
USB20_N10
USB20_N8
USB20_P8
USB20_P2
USB20_N2
USB_OC#4
NV_RCOMP
EC_SMI#
H_PECI
KB_RST#
USB20_N1
USB20_P1
PLT_RST#
USB_OC#0
GPIO0
PCI_FRAME#
PCI_DEVSEL#
PCI_STOP#
PCI_LOCK#
PCI_TRDY#
PCI_IRDY#
PCI_PERR#
PCI_SERR#
PCI_PIRQA#
PCI_PIRQD#
PCI_PIRQE#
PCI_PIRQH#
PCI_PIRQB#
PCI_PIRQF#
PCI_PIRQC#
PCI_PIRQG#
PCI_REQ2#
PCI_REQ1#
PCI_REQ3#
PCI_REQ0#
PLT_RST#
PCI_GNT0#
PCI_GNT1#
PCI_GNT3#
NV_CLE
NV_ALE
PCI_GNT1#
PCI_GNT0#
USB20_N11
USB20_P11
USB20_N13
USB20_P13
USB_OC#1
USB_OC#2
USB_OC#3
USB_OC#5
USB_OC#6
USB_OC#7
USB_OC#2
USB_OC#7
USB_OC#4
USB_OC#0
USB_OC#3
USB_OC#5
USB_OC#1
USB_OC#6
GPIO1
GPIO6
GPIO15
GPIO22
GPIO28
GPIO35
GPIO37
GPIO38
GPIO39
GPIO45
GPIO48
CLK_PCI_LPC_R
CLK_PCI_FB_R
CPUSB#
GPIO34
KB_RST#
INT3_3V#
TP24
PCH_TEMP_ALERT#
EC_SMI#
EC_SCI#
PCH_TEMP_ALERT#
PCI_DEVSEL#
PCI_TRDY#
PCI_FRAME#
PCI_STOP#
PCI_LOCK#
PCI_IRDY#
PCI_PERR#
PCI_SERR#
PCI_REQ3#
PCI_REQ0#
PCI_REQ1#
PCI_REQ2#
PCI_PIRQH#
PCI_PIRQE#
PCI_PIRQD#
PCI_PIRQA#
PCI_PIRQC#PCI_PIRQB#
PCI_PIRQF#
PCI_PIRQG#
EC_SCI#
USB20_P3
USB20_N3
PCI_GNT3#
GPIO16
GPIO17
GPIO36
GPIO36
GPIO17
GPIO16
H_THERMTRIP#_L
PCI_GNT2#
NV_ALE
NV_CLE
DRAMRST_CNTRL_PCH GPIO46
DRAMRST_CNTRL_PCH
GPIO57
USB20_N0 <37>
USB20_P0 <37>
USB20_N2 <27>
USB20_P2 <27>
USB20_N5 <38>
USB20_P5 <38>
USB20_N8 <28>
USB20_P8 <28>
USB20_N10 <28>
USB20_P10 <28>
BUF_PLT_RST#<5,19,28,29>
GATEA20 <34>
H_CPUPWRGD <5>
H_PECI <5>
H_THERMTRIP# <5>
KB_RST# <34>
USB_OC#0 <37>
CLK_CPU_BCLK <5>
CLK_CPU_BCLK# <5>
PCI_PME#<34>
PCI_RST#<28,34>
USB20_N11 <37>
USB20_P11 <37>
CLK_PCI_LPC<34>
CLK_PCI_FB<14>
CPUSB#<28>
EC_SMI#<34>
EC_SCI#<34>
USB20_N1 <37>
USB20_P1 <37>
USB20_N13 <28>
USB20_P13 <28>
USB20_N3 <37>
USB20_P3 <37>
USB_OC#1 <37>
SUSP#<28,34,39,42,44,46> VGA_EN <45>
DRAMRST_CNTRL_PCH<5>
PCH_TEMP_ALERT#<34>
+3VS +3VS
+VCCP
+3VS
+3VALW
+3VS
+3VS
+1.8VS
+3VALW
+3VALW
+3VALW
+3VALW
+3VS
+3VALW
+3VS
+3VS
+3VALW
+3VS
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(4/6)-PCI/USB/RSVD
Custom
16 51Friday, October 30, 2009
2008/08/12 2009/08/12
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(4/6)-PCI/USB/RSVD
Custom
16 51Friday, October 30, 2009
2008/08/12 2009/08/12
Compal Electronics, Inc.
LA-5751
Title
Size Document Number Rev
Date: Sheet of
Security Classification
Compal Secret Data
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Issued Date
Deciphered Date
0.3
IBEX-M(4/6)-PCI/USB/RSVD
Custom
16 51Friday, October 30, 2009
2008/08/12 2009/08/12
Compal Electronics, Inc.
LA-5751
Within 500 mils minimum spacing to other
signal is 15mil
LEFT USB (COMBO)
Bluetooth
3G CARD
CARD READER
EXPRESS
WLAN
USB Camera
GPIO27 if pull down to turn off 1.8V VR
GPIO8
Weak internal PU, don't PD
*
GNT2
Default-Internal pull up
Low=Configures DMI for ESI
compatible operation(for
servers only.Not for
mobile/desktops)
*
override/Top-Block
Low=A16 swap
PCI_GNT3#
A16 swap overide Strap/Top-Block
Swap Override jumper
Swap Override enabled
High=Default
Intel Anti-Theft Techonlogy
*
Weak internal
PU,Do not pull low
Set to Vcc when HIGH
DMI Termination Voltage
NV_ALE
High=Enabled
Low=Disable(floating)
NV_CLE
Set to Vss when LOW
NV_ALE
NV_CLE
Enable Intel Anti-Theft
Technology
：
8.2K PU to +3VS
Disable Intel Anti-Theft
Technology
：
floating(internal PD)
DMI termination voltage.
weak internal PU, don't PD
11
PCI_GNT1#PCI_GNT0#
0
Boot BIOS
Location
1
LPC
Boot BIOS Strap
PCI
0
Reserved(NAND)
SPI
1
0
0
*
GPIO27
GPIO15
*
5
BT
3G
6
4
CMOS
RIGHT SIDE0
DEVICEPORT
3
2
11
NEW CARD
USB PORT LIST
WIRELESS8
10
1
CARD READER
9
7
12
13
GPIO18 = NATIVE,5V,CORE
GPIO52 = NATIVE,5V,CORE
GPIO54 = NATIVE,5V,CORE
GPIO2 = GPI,5V,CORE
GPIO3 = GPI,5V,CORE
GPIO4 = GPI,5V,CORE
GPIO5 = GPI,5V,CORE
GPIO0 = GPI,3.3V,CORE
RIGHT USB
LEFT USB
LEFT SIDE
LEFT SIDE
56 5%-->checklist 1.6
54.9 1%-->CRB 1.0
H
：
Intel ME Crypto Transport
Layer Security(TLS) chiper suite
with confidentiality
L
：
Intel ME Crypto Transport
Layer Security(TLS) chiper suite
with no confidentiality
High
：
Enables the internal VccVRM
to have a clean supply for analog
rails. no need to use on board
filter circuit.
Default
：
Do not connect(floating)
it have weak internal PU 20K
GPIO12 = GPI,3.3V,SUS
GPIO8 = GPO,3.3V,SUS
GPIO7 = GPI,3.3V,CORE
GPIO6 = GPI,3.3V,CORE
GPIO1 = GPI,3.3V,CORE
Check list Rev0.8 section1.23.2
If not implemented, the
Braidwood
interface signals can be
left as No Connect (NC).
within 500mil
6
R429 10K_0402_5%R429 10K_0402_5%
1 2
R42710K_0402_5% R42710K_0402_5%
1 2
R212 1K_0402_5%@R212 1K_0402_5%@
1 2
R199 22_0402_5%R199 22_0402_5%
1 2
R506 0_0402_5%
DIS@
R506 0_0402_5%
DIS@
1 2
R44910K_0402_5% R44910K_0402_5%
1 2
R426 10K_0402_5%
@
R426 10K_0402_5%
@
1 2
RP5
8.2K_0804_8P4R_5%
RP5
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R98 1K_0402_5%@R98 1K_0402_5%@
1 2
R45610K_0402_5% R45610K_0402_5%
12
R164 22.6_0402_1%R164 22.6_0402_1%
1 2
R200 1K_0402_5%@ R200 1K_0402_5%@
1 2
GPIO
MISC
NCTF
RSVD
CPU
U7F
IBEXPEAK-M_FCBGA1071
GPIO
MISC
NCTF
RSVD
CPU
U7F
IBEXPEAK-M_FCBGA1071
GPIO27
AB12
GPIO28
V13
GPIO24
H10
GPIO57
F8
LAN_PHY_PWR_CTRL / GPIO12
K9
VSS_NCTF_1
A4
VSS_NCTF_2
A49
VSS_NCTF_3
A5
VSS_NCTF_4
A50
VSS_NCTF_5
A52
VSS_NCTF_6
A53
VSS_NCTF_7
B2
VSS_NCTF_8
B4
VSS_NCTF_9
B52
VSS_NCTF_10
B53
VSS_NCTF_11
BE1
VSS_NCTF_12
BE53
VSS_NCTF_13
BF1
VSS_NCTF_14
BF53
VSS_NCTF_15
BH1
VSS_NCTF_16
BH2
VSS_NCTF_17
BH52
VSS_NCTF_18
BH53
VSS_NCTF_19
BJ1
VSS_NCTF_20
BJ2
VSS_NCTF_21
BJ4
VSS_NCTF_22
BJ49
VSS_NCTF_23
BJ5
VSS_NCTF_24
BJ50
VSS_NCTF_25
BJ52
VSS_NCTF_26
BJ53
VSS_NCTF_27
D1
VSS_NCTF_28
D2
VSS_NCTF_29
D53
VSS_NCTF_30
E1
VSS_NCTF_31
E53
TACH2 / GPIO6
D37
TACH0 / GPIO17
F38
TACH3 / GPIO7
J32
TP9
M18
TP10
N18
TP11
AJ24
TP12
AK41
SATA3GP / GPIO37
AB13
SATA5GP / GPIO49
AA4
SCLOCK / GPIO22
Y7
SLOAD / GPIO38
V3
SDATAOUT0 / GPIO39
P3
SDATAOUT1 / GPIO48
AB6
A20GATE
U2
PROCPWRGD
BE10
RCIN#
T1
PECI
BG10
THRMTRIP#
BD10
GPIO8
F10
CLKOUT_PCIE6N
AH45
CLKOUT_PCIE6P
AH46
PCIECLKRQ6# / GPIO45
H3
CLKOUT_PCIE7N
AF48
CLKOUT_PCIE7P
AF47
PCIECLKRQ7# / GPIO46
F1
TP5
AY46
TP4
AY45
TP6
AV43
TP7
AV45
BMBUSY# / GPIO0
Y3
TP16
M30
TP17
N30
NC_1
AB45
NC_2
AB38
NC_3
AB42
NC_4
AB41
GPIO15
T7
TACH1 / GPIO1
C38
TP13
AK42
TP3
BB22
TP1
BA22
TP2
AW22
TP14
M32
TP15
N32
SATA2GP / GPIO36
AB7
NC_5
T39
INIT3_3V#
P6
STP_PCI# / GPIO34
M11
SATACLKREQ# / GPIO35
V6
SATA4GP / GPIO16
AA2
TP24
C10
TP8
AF13
CLKOUT_BCLK0_N / CLKOUT_PCIE8N
AM3
CLKOUT_BCLK0_P / CLKOUT_PCIE8P
AM1
TP19
AA23
TP18
H12
R110
10K_0402_5%
R110
10K_0402_5%
1 2
R111
10K_0402_5%
R111
10K_0402_5%
12
PCI
NVRAM
USB
U7E
IBEXPEAK-M_FCBGA1071
PCI
NVRAM
USB
U7E
IBEXPEAK-M_FCBGA1071
AD0
H40
AD1
N34
AD2
C44
AD20
C42
AD21
K46
AD22
M51
AD23
J52
AD24
K51
AD25
L34
AD26
F42
AD27
J40
AD28
G46
AD29
F44
AD3
A38
AD30
M47
AD31
H36
AD4
C36
AD5
J34
AD6
A40
AD7
D45
AD8
E36
AD9
H48
C/BE0#
J50
C/BE1#
G42
C/BE2#
H47
C/BE3#
G34
PCIRST#
K6
PERR#
E50
PIRQA#
G38
PIRQB#
H51
PIRQC#
B37
PIRQD#
A44
PLOCK#
D49
PLTRST#
D5
PME#
M7
REQ0#
F51
REQ1# / GPIO50
A46
REQ2# / GPIO52
B45
REQ3# / GPIO54
M53
SERR#
E44
STOP#
D41
TRDY#
C48
NV_ALE
BD3
NV_CE#0
AY9
NV_CE#1
BD1
NV_CE#2
AP15
NV_CE#3
BD8
NV_CLE
AY6
NV_DQS0
AV9
NV_DQS1
BG8
NV_DQ0 / NV_IO0
AP7
NV_DQ1 / NV_IO1
AP6
NV_DQ10 / NV_IO10
BD6
NV_DQ11 / NV_IO11
BB7
NV_DQ12 / NV_IO12
BC8
NV_DQ13 / NV_IO13
BJ8
NV_DQ14 / NV_IO14
BJ6
NV_DQ15 / NV_IO15
BG6
NV_DQ2 / NV_IO2
AT6
NV_DQ3 / NV_IO3
AT9
NV_DQ4 / NV_IO4
BB1
NV_DQ5 / NV_IO5
AV6
NV_DQ6 / NV_IO6
BB3
NV_DQ7 / NV_IO7
BA4
NV_DQ8 / NV_IO8
BE4
NV_DQ9 / NV_IO9
BB6
NV_RB#
AV7
NV_RCOMP
AU2
NV_WR#0_RE#
AY8
NV_WR#1_RE#
AY5
NV_WE#_CK0
AV11
NV_WE#_CK1
BF5
USBP0N
H18
USBP0P
J18
USBP10N
A22
USBP10P
C22
USBP11N
G24
USBP11P
H24
USBP12N
L24
USBP12P
M24
USBP13N
A24
USBP13P
C24
USBP1N
A18
USBP1P
C18
USBP2N
N20
USBP2P
P20
USBP3N
J20
USBP3P
L20
USBP4N
F20
USBP4P
G20
USBP5N
A20
USBP5P
C20
USBP6N
M22
USBP7N
B21
USBP7P
D21
USBP8N
H22
USBP8P
J22
USBP9N
E22
USBP9P
F22
USBRBIAS#
B25
USBRBIAS
D25
USBP6P
N22
AD10
E40
AD11
C40
AD12
M48
AD13
M45
AD14
F53
AD15
M40
AD16
M43
AD17
J36
AD18
K48
AD19
F40
DEVSEL#
F46
FRAME#
C46
GNT0#
F48
GNT1# / GPIO51
K45
GNT2# / GPIO53
F36
GNT3# / GPIO55
H53
PIRQE# / GPIO2
B41
PIRQF# / GPIO3
K53
PIRQG# / GPIO4
A36
PIRQH# / GPIO5
A48
IRDY#
A42
PAR
H44
OC0# / GPIO59
N16
OC1# / GPIO40
J16
OC2# / GPIO41
F16
OC3# / GPIO42
L16
OC4# / GPIO43
E14
OC5# / GPIO9
G16
OC6# / GPIO10
F12
OC7# / GPIO14
T15
CLKOUT_PCI0
N52
CLKOUT_PCI1
P53
CLKOUT_PCI2
P46
CLKOUT_PCI3
P51
CLKOUT_PCI4
P48
R485 10K_0402_5%R485 10K_0402_5%
1 2
RP6
8.2K_0804_8P4R_5%
RP6
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R414 10K_0402_5%
@
R414 10K_0402_5%
@
1 2
R48310K_0402_5% R48310K_0402_5%
1 2
R211
22_0402_5%
R211
22_0402_5%
1 2
RP2
8.2K_0804_8P4R_5%
RP2
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R10910K_0402_5% R10910K_0402_5%
1 2
R107 10K_0402_5%R107 10K_0402_5%
12
R7610K_0402_5% R7610K_0402_5%
1 2
C646
0.1U_0402_16V4Z
C646
0.1U_0402_16V4Z
1
2
R48010K_0402_5% R48010K_0402_5%
1 2
R149 0_0402_5%R149 0_0402_5%
1 2
R484 10K_0402_5%R484 10K_0402_5%
1 2
RP4
8.2K_0804_8P4R_5%
RP4
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP1
8.2K_0804_8P4R_5%
RP1
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R50710K_0402_5%
@
R50710K_0402_5%
@
12
R609 10K_0402_5%@R609 10K_0402_5%@
1 2
R104
32.4_0402_1%
@
R104
32.4_0402_1%
@
1 2
R405 10K_0402_5%R405 10K_0402_5%
12
R42810K_0402_5% R42810K_0402_5%
1 2
R155
100K_0402_5%
R155
100K_0402_5%
12
RP3
8.2K_0804_8P4R_5%
RP3
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
RP7
8.2K_0804_8P4R_5%
RP7
8.2K_0804_8P4R_5%
1 8
2 7
3 6
4 5
R11210K_0402_5% R11210K_0402_5%
1 2
R415 10K_0402_5%R415 10K_0402_5%
1 2
R518
56_0402_5%
R518
56_0402_5%
1 2
U5
MC74VHC1G08DFT2G SC70 5P
@
U5
MC74VHC1G08DFT2G SC70 5P
@
B
2
A
1
Y
4
P
5
G
3
R48110K_0402_5% R48110K_0402_5%
1 2
R44610K_0402_5% R44610K_0402_5%
1 2
R408 100K_0402_1%R408 100K_0402_1%
12
R4331K_0402_5% R4331K_0402_5%
1 2
R515 1K_0402_5%@ R515 1K_0402_5%@
1 2
R210 1K_0402_5%@R210 1K_0402_5%@
1 2
R519
56_0402_5%
R519
56_0402_5%
12
R43210K_0402_5% R43210K_0402_5%
12
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