Apple A1261 Schematic

APPLE INC.

6

DESIGNER

DESCRIPTION OF CHANGE

REV.

A

D

C

B

A

D

C

B

8 7

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

TITLE

DRAWING NUMBER

SHT

OF

METRIC

DRAFTER

ENG APPD

QA APPD

RELEASE

DESIGN CK

MFG APPD

SCALE

NONE

MATERIAL/FINISH

NOTED AS

APPLICABLE

SIZE

D

THIRD ANGLE PROJECTION

DIMENSIONS ARE IN MILLIMETERS

XX

X.XX

X.XXX

DO NOT SCALE DRAWING

REV

ZONE

ECN

CK APPD

DATE

ENG APPD

DATE

1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%.

2. ALL CAPACITANCE VALUES ARE IN MICROFARADS.

3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.

ANGLES

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

DRAWING

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_TABLEOFCONTENTS_ITEM

TABLE_TABLEOFCONTENTS_HEAD

TABLE_TABLEOFCONTENTS_ITEM

SCHEM,MLB,MBP17

12/18/2007

PVT

521911

Schematic / PCB #’s

ALIASES RESOLVED

SMC

45

49

M87_MLB

08/28/2007

Left Clutch Barrel Interconnect

44

47

M87_MLB

08/28/2007

External USB Connector

43

46

MASTER

PATA Connector

42

44

MASTER

FireWire Ports

41

43

M87_MLB

08/28/2007

FireWire Port Power

40

42

M87_MLB

08/28/2007

FireWire PHY (TSB83AA22)

39

41

M87_MLB

08/28/2007

FireWire Link (TSB83AA22)

38

40

M87_MLB

08/28/2007

Ethernet Connector

37

39

M87_MLB

08/28/2007

Yukon Power Control

36

38

T9_NOME

03/19/2007

Ethernet (Yukon)

35

37

T9_NOME

01/25/2007

Left I/O Board Connector

34

(MASTER)

Memory Active Termination

33

(MASTER)

DDR2 SO-DIMM Connector B

32

M87_MLB

08/28/2007

DDR2 SO-DIMM Connector A

31

M87_MLB

08/28/2007

Clock Termination

30

M87_MLB

08/28/2007

Clock (CK505)

29

T9_NOME

01/25/2007

SB Misc

28

M87_MLB

08/28/2007

SB Decoupling

27

MASTER

SB Power & Ground

26

T9_NOME

01/25/2007

SB Pwr Mgt, GPIO, Clink

25

M87_MLB

08/28/2007

SB PCI, PCIe, DMI, USB

24

M87_MLB

08/28/2007

SB Enet, Disk, FSB, LPC

23

T9_NOME

01/25/2007

NB Graphics Decoupling

22

M87_MLB

08/28/2007

NB Standard Decoupling

21

MASTER

NB Grounds

20

T9_NOME

01/25/2007

NB Power 2

19

T9_NOME

01/25/2007

NB Power 1

18

T9_NOME

01/25/2007

NB DDR2 Interfaces

17

T9_NOME

01/25/2007

NB Misc Interfaces

16

T9_NOME

01/25/2007

NB PEG / Video Interfaces

15

T9_NOME

03/19/2007

NB CPU Interface

14

T9_NOME

01/25/2007

eXtended Debug Port (XDP)

13

T9_NOME

01/22/2007

CPU Decoupling & VID

12

M87_MLB

08/28/2007

CPU Power & Ground

11

M87_MLB

08/28/2007

CPU FSB

10

M87_MLB

08/28/2007

Signal Aliases

9

MASTER

Power Aliases

8

(MASTER)

Functional / ICT Test

7

MASTER

Revision History

6

N/A

BOM Configuration

5

N/A

Power Block Diagram

4

N/A

Power Block Diagram

3

(MASTER)

System Block Diagram

2

(MASTER)

106

01/25/2007

T9_NOME

FireWire Constraints

89

105

08/28/2007

M87_MLB

Clock & SMC Constraints

88

104

01/25/2007

T9_NOME

SB Constraints (2 of 2)

87

103

01/25/2007

T9_NOME

SB Constraints (1 of 2)

86

102

01/25/2007

T9_NOME

Memory Constraints

85

101

01/25/2007

T9_NOME

NB Constraints

84

100

01/25/2007

T9_NOME

CPU/FSB Constraints

83

98

12/06/2007

M87_LIO

LCD Backlight Support

82

96

(MASTER)

Project Specific Connectors

81

94

MASTER

DVI Display Connector

80

93

MASTER

1.8V FB Power Supply

79

92

08/28/2007

M87_MLB

GDDR3 Frame Buffer B (Bot)

78

91

08/28/2007

M87_MLB

GDDR3 Frame Buffer A (Bot)

77

90

MASTER

LVDS Display Connector

76

89

09/26/2007

M87_MLB

GPU (G84M) Core Supply

75

88

08/28/2007

M87_MLB

NV G84M Video Interfaces

74

87

08/28/2007

M87_MLB

GPU Straps

73

86

08/28/2007

M87_MLB

NV G84M GPIO/MIO/Misc

72

85

08/28/2007

M87_MLB

GDDR3 Frame Buffer B (Top)

71

84

08/28/2007

M87_MLB

GDDR3 Frame Buffer A (Top)

70

82

08/28/2007

M87_MLB

NV G84M Frame Buffer I/F

69

81

08/28/2007

M87_MLB

NV G84M Core/FB Power

68

80

08/28/2007

M87_MLB

NV G84M PCI-E

67

79

MASTER

PBus Supply & Batt. Charger

66

78

09/26/2007

M87_MLB

3.425V G3Hot Supply & Power Control

65

77

08/28/2007

M87_MLB

FW PHY Power Supplies

64

76

MASTER

1.5V Power Supply

63

75

08/28/2007

M87_MLB

1.8V DDR2 Supply

62

74

08/28/2007

M87_MLB

1.25V / 1.05V Power Supply

61

73

MASTER

5V / 3.3V Power Supply

60

71

MASTER

IMVP6 CPU VCore Regulator

59

70

08/28/2007

M87_MLB

Power FETs

58

69

(MASTER)

DC-In & Battery Connectors

57

61

01/25/2007

T9_NOME

SPI BootROM

56

59

08/28/2007

M87_MLB

Sudden Motion Sensor (SMS)

55

58

08/28/2007

M87_MLB

ALS Support

54

57

11/06/2007

M87_LIO

Current & Thermal Sensors

53

56

08/28/2007

M87_MLB

Fan Connectors

52

55

08/28/2007

M87_MLB

Thermal Sensors

51

54

MASTER

Current Sensing

50

53

08/28/2007

M87_MLB

Current & Voltage Sensing

49

52

(MASTER)

SMBus Connections

48

51

08/28/2007

M87_MLB

LPC+ Debug Connector

47

92

PCB Rule Definitions

M87_MLB

10/03/2007

109

91

Project Specific Constraints

M87_MLB

08/28/2007

108

Contents

(.csa)

Sync

Date

Page

Table of Contents

1

N/A

1

PCB

CRITICAL820-2262

PCBF,MLB,MBP17

TITLE=MLB

ABBREV=DRAWING

LAST_MODIFIED=Tue Dec 18 15:43:01 2007

Date

Page Contents Sync

(.csa)

90

GPU (G84M) Constraints

M87_MLB

10/02/2007

107

CRITICAL051-7431

SCH

1

SCHEM,MLB,MBP17

50

10/15/2007

M87_MLB

SMC Support

46

(.csa)

Sync

Date

Page Contents

92

1

0.1

? ?

Proto Release

051-7431

A.0.0

SCHEM,MLB,MBP17

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PG 66

PG 81PG 81

PG 81

J9610

CLK CHIP

DIMM’s

100 MHz

PG 81

PG 80

PG 67

PG 74

PG 69

1.26V - 1.05V

GDDR3 FRAME BUFFER A/B (BOT)

U9100,U9150,U9200,U9250

PG 77,78

GDDR3 FRAME BUFFER A/B (TOP)

PG 71,72

U8400,U8450,U8500,U8550

Core 1.05V

J4300

Conn

FireWire

TSB83AA22

LVDS DISP

DVI-INTERFACE

VIDEO INTERFACES

DVI DISPLAY CONN

NV G84M FRAME BUFFER I/F

NV G84M

Core

PCI-EBUS INTERFACE

PG 23

CAMERA

PG 44

LEFT CLUTCH BARREL INTERCONN

Supply

Power

U5570

Pg 51

U5500

Temp Sense

PG 54

ALS SENS

J6990/50

DC/Batt

U5805

CPU GPU

Conn

PG 57

PG 30

TERMSClocks

PG 29

CK 505

U2900

J3200

J3100

DIMM

PG31,32

DDR2 - Dual Channel

1.8V - 64 Bits

533/667/800? MHz

U1000

CPU

PG 13

J1300

PG 16/17

Main Memory

2.? GHz

PG 10

Core ~1.2V

PG 11,12

FSB

64-Bit

Core

1.05 - 1.25V

NB-GMCH

PG 14

TV

PCI-E

U1400

U5550 Pg 51

Right Side

LPC Conn

PG 47

J5100

PG 44

WWAN

J4731

Geyser

Trackpad/Keyboard

J9600

U5900

PG 55

PG 52

FAN CONN

POWER SENSE PG 49-50

J5650/60

SUDDEN MOTION SENSOR

Ser Prt

FanADC

Pg 46

SMC

BSBB,0 BSA

U4900

A

Bluetooth

J9660

IR

LEFT I/O J3400

U2900

SPI

PG 56

Boot ROM

USB

J4600

PG 43

EXT-A

CONN

PG 25

GPIOs

LPC

0

2 14 3

USB

5

PG 24

7 69 8

U6100

Misc

CLnk 0

PG 16

PG 16PG 16

DMI

PG 18~22

x4 DMI

2.5 GHz

DMI SPI

CLnk 0

PG 25

PG 24

SB-ICH8

U2300

SATA

PG 23

IDE

PG 23

PCI-E

PG 24

J3200

J3100

PG 25

AZALIA

PG 23

TSB83BA22

FW-Link

U4000

32-Bit

33 MHz

Pg 38

Pg 39

FW-PHY

J4310

Pg 41

PCI

PG 24PG 25

CLnk 1

PG 23

Pg 25

Core

E-NET

ETHERNET

Pg 35

(YUKON ULTRA)

J3900

U3700

E-NET

Pg 37

Conn

Pg 59

Audio Codec

U6200

PG 15

RGB LVDS

800/1066? MHz

PG 15

LIO BOARD

Mini PCI-E

AirPort

Out

x16 PCI-E

SDVO

U8000

J9400

SATA-2SATA-1 Ln1 Ln3Ln2

1.2 V / 1.5 GHz

3.3 V

PG 77

J9000/10

Conn

PATA

Pg 42

Conn

J4400

J9660

SATA

Ln4 Ln5 Ln6

3 - X1

2.5 GHz

PG 34

EXT-B

CONNS

USB

EXT-C

PG 34

EXPRESS CARD

PG 34

PG 24

SATA-0

ITP/XDP CONN

8-Bit

U4000

100 MHz

SMB

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

System Block Diagram

051-7431

2

92

A.0.0

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

M88 POWER SYSTEM ARCHITECTURE

PM_SLP_S3_DELAY_L

P3V3S3_SS

(12A MAX CURRENT)

VOUT2

CURRENT)

PP0V9_S0

(10mA MAX CURRENT)

PP1V8_S3_ISNS

(10A MAX CURRENT)

PP1V8_S0GPU

P1V25S0_SS

Q7095

PP1V25_ENET

PP1V8_S3

(5.5A MAX)

PP3V3_S5

(8A MAX CURRENT)

PP5V_S5

CHGR_EN

LIO_DCIN_ISENSE

A

U5705

INRUSH LIMITER

(PAGE 57)

Q7970

VIN

U5495

SMC_GPU_VSENSE

(PAGE 61)

U7450

U5420

NBCORE_IOUT

PWRBTN*

PLT_RST_L

CPU_PWRGD

CPUPWRGD(GPIO49)

CLPWROK

P1V8P1V5P1V05S0_PGOOD

SIGNAL DELAY TIME

99ms 200ms

STEP 06 (S5 POWER STATUS)TRUTH TABLE

L(S5 OFF)

ACIN WITH/WITHOUT BATTERY

BATTERY ONLY,PRESS PWR BUTTON

(UNUSED)

TP1V25ENET_PGOOD

(PAGE 61)

U7400

TPS51117

VIN

1V8S3_PGOOD

(PAGE 62)

U7500

1.8V

0.9V

VOUT1

RSMRST_PWRGD

GPUVCORE_IOUT

VOUT

PPVBAT_G3H_CHGR_OUT

BATTERY CHARGE

SMC_ADAPTER_EN

SMC_BC_ACOK

PP18V5_G3H_CHGR

U7859

U7858

P3V3GPU_SS

PP3V3_S0

PP1V9_ENET

V4(1.25V)

V2(3.3V)

V1(5V)

S0PGOOD_PWROK

V3(1.8V)

LTC2900

(PAGE 66)

U7870

RST*

Q7020

VIN

VOUT

TP_P1V8_S0GPU_PGOOD (UNUSED)

Q4260

FWPWR_EN_L_DIV

PPBUS_FW_FWPWRSW_F

ISL6269

U9300

(PAGE 79)

PGOOD

EN

VOUT

PGOOD

EN_PSV

PM_ENET_EN

P1V8_S3_IOUT

VOUT2

VOUT

EN

PP1V25_S0

Q7010

PP3V3_GPU

PP5V_S5

Q3810

Q7030

IN

(PAGE 36)

TPS79501

U3850

01,05-09

ALL_SYS_PWRGD

MCH

POWER ON SEQUENCE LIST

PPVIN_FW_3V3FW

1.5A FUSE

(PAGE 64)

TPS799195

(PAGE 64)

VIN

Q4261

Q3801

Q7850

Q3801

U5440

P1V8S3_EN

PM_S4_STATE_L

C=0.47UF

A

R=10K

DELAY

P3V3S3_SS

PP5V_S0

(PAGE 60)

TPS51120

EN2

PGOOD

PP3V42_G3H

SMC_PM_G2_EN

EN2

P5VS3_SS

C=68NF

R=47K

DELAY

EN1

3.3V

EN2

5V

VIN

VOUT1

PM_SLP_S3_L

PGOOD

Q7012

SLP_S3*

Q7851

U2300

S4_STATE*

ICH8M

VR_PWRGD_CLKEN_L

P5VS3_SS

P5VS0_SS

V

EN_PSV

PM_GPUVCORE_EN

A

PPBUS_G3H

ISL9504

CPUVCORE

U7100

VOUT

VIN

VR_ON

A

(PAGE 66)

FET

PBUS SUPPLY /

BATTERY CHARGER

U7900

(PAGE 66)

PGOOD

(44A MAX CURRENT)

PPVCORE_SO_CPU

V

SMC_CPU_VSENSE

CPUVCORE_IOUT

U5400

CLKEN#

(PAGE 59)

BATTERY ONLY:

ADAPTER IN :

PM_S4_STATE_L

PM_SLP_S4_L(P94)

PM_SLP_S5_L(P95)

P17(BTN_OUT)

PLT_RST*

IMVP_VR_ON(P16)

99ms DLY

RSMRST_OUT(P15)

U1400

(PAGE 63)

PPVCORE_S0_NB_R

U7880

P1V8S3_PGOOD

PP1V5_S0

TPS51117

PM_SLP_S3_DELAY_L

PGOOD

1.5V

EN_PSV

(PAGE 65)

Q6950

PPVBATT_G3H_FET_F

BATT_POS

518S0457

J6950

87438-1043

CRITICAL

PPVBATT_G3H_FET

8A FUSE

A

VR_PWRGOOD_DELAY

PM_SB_PWROK

U2840

SHDN*

VIN

PBUS_LDO_EN

Energy Star LDO

(PAGE 66)

U7950

MAX8719

VOUT

ISL6257

VOUT

VIN

ENABLES

VIN

VOUT

PP5V_S3

Q7000

IMVP_VR_ON

87438-0832

CRITICAL

PP18V5_DCIN

J6990

27.11UF

H(S5 ON)

518S0456

Q7096

C=1UF

R=100K

DELAY

P1V25S0_SS

Q7002

S3_VTT_EN

VIN

EN

SHDN*

U7700

VOUT

U7720

VOUT

PP3V3_FW

PP1V95_FW

4.2UF

(0.2A MAX CURRENT)

PLATFORM,CPU RESET

BATTERY ONLY

NO AC/BATTERY

S0 CPU POWER ON

VR_PWRGOOD_DELAY

S0PWRGD_OK

S0 SYSTEM POWER ON

S3 POWER ON

S5 POWER ON

G3H POWER ON

PWR/RST STATUS

7ms

STEP

H(S5 ON)

14-18 17,19-24 25-27

L(S5 OFF)

01-04

10-13

PM_SLP_S5_L

PM_SLP_S3_L

08-1

05

PM_SLP_S3_L(P93)

U4900

(PAGE 45)

RST*

PWR_BUTTON(P90)

U2830

VR_PWRGD_CLKEN

RSMRST_PWRGD

SMC_ONOFF_L

RSMRST_IN(P13)

PWRGD(P12)

PWROK

SMC

RESET*

HCPURST*

U1000

PWROK

VRMPWRGD

CPU

PWRGOOD

RSMRST*

PLTRST*

SMC_PBUS_VSENSE

VIN

U7600

VOUT

V

Q5315

EN_PSV

VIN

TPS51117

1.05V

VOUT

PGOOD

SHDN*

VIN

3.425V"G3HOT" LT3470

U7800

VOUT

SMC RESET "BUTTON"

(PAGE 46)

(0.2A MAX CURRENT)

RN5VD30A-F

PP3V42_G3H

PP1V05_S0

U5000

VOUT

SMC_RESET_L

(10A MAX CURRENT)

FSB_CPURST_L

IMVP_VR_ON

PM_RSMRST_L

PM_PWRBTN_L

10

28

26

27

PPDCIN_G3H

P3V3S0_SS

Q7070

(4.5A MAX CURRENT)

GPUVCORE_PGOOD

U2300

ICH8M

A

IMVP_VR_ON

U7300

(18A MAX CURRENT)

PGOOD

Q7850

SMC_ADAPTER_EN

P1V8S3_EN

PM_GPUVCORE_EN

DELAY

Q7002

P5VS0_SS

P3V3S0_SS

R=47K C=68NF

R=100K

DELAY

C=33NF

Q7012

PM_P1V8_S0GPU_EN

PM_SLP_S3_LS5V

Q7851

C=33NF

R=100K

DELAY

PP3V3_S5

PPVCORE_GPU

U7850

PP3V3_S5

PP3V3_ENET

P3V3ENET_SS

PM_P1V8_S0GPU_EN

WOL_EN

P3V3ENET_SS

PM_SLP_S3_L

S5_EN

TPS511160

(6A MAX CURRENT)

LT3470

P1V8_S0GPU_IOUT

A

PPVP_FW

P3V3GPU_SS

R=100K

DELAY

C=1UF

Q7072

PM_P3V3GPU_EN

RST*

(PAGE 65)

U7860

MAX6838

VCC

RSTIN

PP3V3_S3

A

P1V25_S0_IOUT

PP1V25_S0_ISNS

VIN

PM_SLP_S3_DELAY_L

C=33NF

R=100K

Q3800

FWPWR_EN_L_DIV

PM_ENET_EN

U5410

PP1V8_S0GPU_ISNS

U5430

(PAGE 75)

U8900

ISL6263B

LIO_BATT_ISENSE

U5715

SYNC_DATE=(MASTER)

Power Block Diagram

051-7431

A.0.0

92

3

SYNC_MASTER=(MASTER)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Power Block Diagram

051-7431

A.0.0

92

4

SYNC_MASTER=N/A

SYNC_DATE=N/A

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

BOM OPTIONS

BOM NAME

BOM NUMBER

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

TABLE_BOMGROUP_ITEM

TABLE_ALT_ITEM

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

TABLE_BOMGROUP_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Alternate Parts

BOM Variants

BOM Groups

Module Parts

Bar Code Labels / EEE #’s

SYNC_DATE=N/A

92

A.0.0

051-7431

5

BOM Configuration

SYNC_MASTER=N/A

VRAM8,VRAM_16M,VRAM_SAMSUNG,VRAM_512_SAMSUNG

FB_512_SAMSUNG

CRITICAL826-4393

1

[EEE:Z3K]

EEE_Z3K

LBL,P/N LABEL,PCB,28MM X 6 MM

EEE_ZVX

[EEE:ZVX]

826-4393

1

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

CRITICAL338S0509

1

U8000

IC,GPU,NV,G84M,BGA

338S0434

1

CRITICAL

U2300

IC,SB,ICH8M,B1,PRQ,BGA

353S1651

1

ISL9504BCRITICAL

U7100

IC,ISL9504B,2PH IMVP6 REG,PMON,QFN48

1

359S0130

U2900

CRITICAL

IC,SLG2AP101,LW PWR CLK GEN,CK505,QFN68

CRITICAL

SMC_BLANK

338S0274

1

U4900

IC,SMC,HS8/2116

CRITICAL341S2194

U4900

1

SMC_PROG

IC,SMC,DEVELOPMENT,M88

U6100

341S2192

BOOTROM_PROG

1

CRITICAL

IC,EFI ROM,DEVELOPMENT,M87

IC,SGRAM,GDDR3,16MX32,800MHZ,136 FBGA

U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250

333S0423

8

CRITICAL

VRAM_512_SAMSUNG

333S0424

U8400,U8450,U8500,U8550

4

IC,SGRAM,GDDR3,16MX32,900MHZ,136 FBGA

VRAM_256_HYNIX

CRITICAL

IC,SGRAM,GDDR3,16MX32,900MHZ,136 FBGA

333S0424

U8400,U8450,U8500,U8550,U9100,U9150,U9200,U9250

CRITICAL

8

VRAM_512_HYNIX

ALL

376S0445376S0448

Si7806ADN for FSM6296

CRITICAL

1

338S0432

U1400

IC,NB,CRESTLINE,GM,C0,PRQ,ROHS-SPECIAL,965PM

337S3559

IC,PDC,SR,PRQ,2.6G,35W,800FSB,6M,BGA

1

CRITICAL

CPU_2_6GHZ

U1000

337S3560

IC,PDC,SR,PRQ,2.5G,35W,800FSB,6M,BGA

U1000

CRITICAL

1

CPU_2_5GHZ

P1V8S3_1V8,SMS_MOT_DIS,YUKON_ULTRA,VGA_TERM_CONN

M88_COMMON2

U8400,U8450,U8500,U8550

4

333S0423

VRAM_256_SAMSUNG

IC,SGRAM,GDDR3,16MX32,800MHZ,136 FBGA

CRITICAL

U6100

335S0384 CRITICAL

BOOTROM_BLANK

1

IC,16MBIT 8-PIN SPI SERIAL FLASH,SOIC8

[EEE:ZVW]

1

826-4393 CRITICAL

EEE_ZVW

LBL,P/N LABEL,PCB,28MM X 6 MM

1

826-4393

[EEE:Z3L]

EEE_Z3L

CRITICAL

LBL,P/N LABEL,PCB,28MM X 6 MM

FB_256_SAMSUNG

VRAM4,VRAM_16M,VRAM_SAMSUNG,VRAM_256_SAMSUNG

PCBA,2.6GHZ,512VRAM-HY,M88

630-9092

M88_COMMON,CPU_2_6GHZ,FB_512_HYNIX,EEE_Z3K

PCBA,2.5GHZ,512VRAM-HY,M88

630-9225

M88_COMMON,CPU_2_5GHZ,FB_512_HYNIX,EEE_ZVW

1

338S0386

U3700

CRITICAL

IC,88E8058,GIGABIT ENET XCVR,64P QFN

VRAM8,VRAM_16M,VRAM_HYNIX,VRAM_512_HYNIX

FB_512_HYNIX

VRAM4,VRAM_16M,VRAM_HYNIX,VRAM_256_HYNIX

FB_256_HYNIX

M88_PROGPARTS

BOOTROM_PROG,SMC_PROG

SMC_DEBUG_NO,XDP,LPCPLUS

M88_DEBUG

M88_COMMON1

BKLT_5V_PWR,ISL9504B,ONEWIRE_PU,GPUVID_1P23V

M88_COMMON

COMMON,ALTERNATE,M88_COMMON1,M88_COMMON2,M88_DEBUG,M88_PROGPARTS

PCBA,2.5GHZ,512VRAM-SAM,M88

630-9228

M88_COMMON,CPU_2_5GHZ,FB_512_SAMSUNG,EEE_ZVX

PCBA,2.6GHZ,512VRAM-SAM,M88

630-9093

M88_COMMON,CPU_2_6GHZ,FB_512_SAMSUNG,EEE_Z3L

157S0030157S0011

E&E alt to TDK/BiTech magnetics

ALL

138S0602138S0603

Murata alt to Samsung 22uF acoustic caps

ALL

TI alternate to National

353S1294353S1681

ALL

376S0466

AOS alternate to Siliconix Si4413

376S0543

152S0276152S0683

ALL

Mag Layers alternate to Dale/Vishay

104S0017104S0024

ALL

Panasonic alternate to Cyntec

128S0175

alternate to Halogen free Sanyo 330uf D3 tant

ALL

128S0056

128S0147

alternate to Halogen free Sanyo 100uF tant

ALL

128S0057

128S0157

alternate to Halogen free Sanyo 220uF 15 mohm tant

128S0122

ALL

alternate to halogen free Sanyo 150uF tant

128S0150128S0115

ALL

alternate to halogen free Sanyo 220uF 35 mohm tant

128S0160128S0113

ALL

alternate to halogen free Sanyo 330uF C2 tant

ALL

128S0083 128S0165

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

11/06/07 --

Page 25: Removed NO STUFF BOM option from R2552, pull up on SB GPIO38.

12/12/07 --

18.0.0:

pg. 82 Changed C9805 to 2.2uF for LED power sequencing.

08/10/07 -- Page 65: Changed L7810 3.425V G3 Hot inductor to 152S0301. R7070 changed from 100K to 10K.

08/17/07 -- Page 48: Changed SMBus SMC "A" pull ups R5270 and R5271 to 3.3K to improve rise time on SCL..

08/03/07 -- Page 5: Removed Q4690 BOM table entry. BOM table is on CSA pg. 46

08/10/07 -- Synced to M87 MLB label 4.3.0 08/10/07 -- Page 3: Revised power block diagram.

08/10/07 -- Page 37: T3900,T3901 magnetics changed to 157S0053.

Removed R3410 and R3411.

Added GPIOs to support iPhone headset.

08/14/07 -- Synced to M87 MLB label 5.1.0

08/16/07 -- Removed Rev B Silego clock chip as alternate. 08/16/07 -- Page 51: Temp Sensors: Changed U5500 and U5570 to EMC1043-1 APN 353S1947.

Page. 9,34: Page. 9,34:

7.1.0:

08/22/07 --

5.0.0:

6.2.0:

6.0.0 & 5.1.0:

6.1.0:

7.0.0:

08/22/07 --

Changed R5413 and R5443 to 0.005 ohm resistors.

Changed L7100 and L7101 to 152S0624.

Page 50: Adding C5411,C5412,C5441,C5442 feedback caps for current sense op amps Page 66: Changed R7920 to halogen free 107S0110.

Changed R5491 and R5493 to 6.81K to allow full resolution of GPUVCORE current sense

Page 61: R7455 changed to 7.5K to change max load current margin on PP1V05.

Page 9: IPHS_SW_BIAS_EN_L now connected to SB_SLOAD (GPIO 38).

Page 91: Added diff pair properties to new current sensor pairs.

Page 59: CPU Vcore supply changes per characterization.

Page 5,75: Changed BOM option to GPUVID_1P23V

Page 51: Temp sensors: Added R5501,R5502,R5571,R5572 pull ups on U5500 and U5570.

Page 82: Changed L9891,L9893,L9894 to 155S0220

Page 50: Current Sensors: Changed U5410 and U5440 to MAX4245

Page 66: Changed U7901 to MAX4245. Changed F7902 to 740S0055.

Page 25: Added NO STUFF to R2552 (was pull up on SB GPIO38 which is now used on IPHS).

Page 90: Changed frame buffer net physical type to GDDR3_50SE.

Page 66: U7901 voltage follower changed from OPA333 to OPA705.

Page 5: Changed CPU parts to ES2, B1 for EVT

label 6.2.0

label 1.5.0

label 6.5.0

label 1.7.0

label 8.2.0

Page 82: Add BOMOPTION OMIT to RX9892.

Synced M87 LIO

Synced M87 MLB

Synced M87 LIO

Synced M87 MLB

Page 73:

Synced M87 MLB

08/22/07 -08/22/07 -08/22/07 -08/22/07 -08/22/07 --

08/24/07 --

8.1.0:

08/24/07 --

8.0.0:

08/24/07 --

08/23/07 --

08/23/07 -08/23/07 --

08/23/07 --

08/22/07 -08/22/07 --

08/23/07 --

7.2.0:

pg. 76 L9010,L9011pg. 43 L4600

pg. 44 FL4735

pg. 43 L4600

NB_CLK100M_DPLSS_P/N

Changed the orientation on these filters to match layout:

EVT Release of Schematic BOM and PCBF

152S0683 is the Mag layers alternate for Dale/Vishay inductors.

Page 5: Added alternate sources for these parts:

128S0164 is the Kemet alternate to Sanyo caps 104S0023 is the Panasonic alternate to Cyntec resistors

pg. 80 L9460,L9464,L9468,L9476,L9480,L9484

Changed the following filters to 155S0371 for supply issues:

Changed net physical and net spacing to CRT_50S on these signals

Major release label name : m87_mlb_051-7413_8.2.0

BOM Changes only

RFA 529050

Synced m87_mlb CSA pgs.

09/04/07 -09/04/07 --

08/30/07 --

8.2.0:

09/04/07 --

9.1.0:

08/30/07 --

9.0.0:

8.4.0:

08/29/07 --

8.3.0:

08/29/07 --

ICH8 GPIO 22 IPHS_SW_BIAS_EN_L routes to JJ3400.63

pg. 76 L9010,L9011

NB_CLK96M_DOT_P/N

Changed C7134 to 0.01uF 132S0042.

09/11/07 --

11.0.0:

09/11/07 --

09/06/07 --

09/04/07 --

10.0.0:

Page 50:

Page 82: LCD Backlight

630-9228: ZVX PCBA,2.5GHZ,512VRAM-SAM,M88

Changed R5425 and R5435 to 104S0023.

630-9225: ZVW PCBA,2.5GHZ,512VRAM-HY,M88

Added BOM variants and EEE codes for 2.5GHz:

HF capacitor substitution, with halogen parts as alternates.

Page 62: Removed OMIT property and BOM option table to make C7540 and C7541 only 128S0073.

Page 5: Removed alternate to 128S0164 Kemet 220uF tantalum cap at C7540 and C7541.

Page 57: Removed NO STUFF from DZ6960 (377S0044), ESD diode on BATT_POS per Chris.

pg. 5 Alternates BOM table updates.

Added OMIT properties and BOM option table to change these beads to 155S0220:

L9891,L9893,L9894

removed R8992,C8992

Page 75: GPU Vcore supply: Changed L8920 from 152S0525 to 152S0697.Dale 0.9uH 27A inductor has smaller pad size than Vishay IHLP4040.

<rdar://problem/5493576> M87/M88 MLB/LED: LED driver current mirror can not be disabled + power sequencing issue

Removed BOM tables and OMIT BOM options from HF capacitor substitution, with halogen parts as alternates.

Added R9810

label 7.0.0

label 9.0.0

label 10.3.0

label 10.2.0

Page 5: Added 376S0448 as alternate for 376S0445.

GPUVCORE: Current sense to use IMVP6 IMON + Non-inverting Opamp

<rdar://problem/5510696> TASK: M87 LIO changes to support LED board

Page 5: Removed HDCP ROM. Removed U8770, R8770,R871, C8770.

Page 50: updating GPUVcore current sense resistor values for gain of 4.83

Page 65: Changed C7860 to 0.0047uF (radar://5468257

Page 66: Swapped U7901 pins 1 and 3 signals (positive and negative inputs).

10/01/07 --

Synced M87 LIO

09/12/07 --

Synced M87 MLB

Page 50 & 75:

Synced M*& MLB

12.0.0:

13.0.0:

10/05/07 --

09/26/07 -09/26/07 --

12.0.0: 09/28/07 -09/28/07 -09/28/07 --

09/26/07 --

11.1.0:

11.2.0:

Page 93: <rdar://problem/5525486> M87/88 1V8 FB DC converter transient response improve/BOM change

C9307 change to 68pF, 0402, 10V, 10%

Page 5: Changed Module parts for new Penryn APNs.

C9308 change to 680pF, 0402, 10V, 10%

R9308 change to 40.2k, 0402, 1%;

Change 72968

Synced m87_MLB label

10/09/07 --

13.1.0:

DVT:

08/10/07 -- Page 10-12: Updated U1000 CPU part number to reflect latest Penryn pin-out.

08/14/07 -- Page 49: Changed Q5322 to SOT23 part same as M87. 08/14/07 -- Page 75: Changed GPU VID pull up/downs to 2.2K ohms.

DVT (cont):

Changed Q5030 to new LED Driver IC

Changed all GDDR3_46SE constraints back to GDDR3_50SE.

Deleted, Q5032,R5032,R5030

Changed R9809 to 200k

Added, C5030

Page 50: Named unnamed net on Q5030.

as alternate.

change C7134 to 0.022uF 132S0102 per Dayu

Page 90: Graphics constraints

10.0.0

12.2.0

12.1.0

Changed C9807 to 0.1uF

Page 57: Changed DZ6960-DZ6963 to 377S0068. These are NO STUFFs.

Page 81: Added FL9600 155S0372 to multi-touch trackpad power and GND.

Page 53: Changed U5750 TMP102 to RevE part 353S2039 with old part 353S1807

Page 69: NO STUFF battery positive terminal varistor DZ6960

Page 46: Changed to new Sleep LED circuit

Page 43: Changed L4605 ferrite bead to 155S0329 for lower DCR.

Page 59: CPU Vcore power supply

Changed R9807 to 5.1k

Synced M87_MLB label:

Synced M*&_LIO label:

10/24/07 --

14.5.0:

10/24/07 --

10/19/07 --

10/12/07 --

14.0.0:

10/12/07 -10/12/07 --

10/12/07 --

14.1.0:

10/12/07 --

11/01/07 --

17.0.0:

16.0.0:

11/01/07 --

14.0.0

ICH8 GPIO 2 IPHS_SW_INT routes to JJ3400.65

11/06/07 --

Synced M87_LIO label

Page 50: Removed ST SIL driver and returned to EVT’s BJT-driven current source

Page 5: Updated CPUs to PRQ parts, removed XDP_CONN and GPU_TMP401 bom options and changed to SMC_DEBUG_NO for PVT

Page 98: Changed R9808 to 200K, R9809 to 100K, C9802 to 0.033uF, C9807 to 0.33uF to improve Q9806 Vgs and sequencing

12/10/07 --

PVT:

12/12/07 --

Page 98: Changed C9805 to actual 2.2uF part (removed table entry)

18.1.0:

18.2.0: 12/13/07 --

Page 13: NO STUFFed R1330/R1331 since the LVDS_CTRL_DATA/CLK lines are grounded

EVT:

See earlier schematics for info about releases 0.0.1 - 4.0.0

Proto:

18.3.0: 12/16/07 --

Page 54: Added C8992/R8992 to provide differential sense option A.0.0: 12/18/07 --

Release as Rev A

6

92

A.0.0

051-7431

Revision History

SYNC_MASTER=N/A

SYNC_DATE=N/A

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Backlight Connector

6 TPs, 2 with each of above TP pairs

Left Clutch Barrel Connector

Other Func Test Points

IR & Sleep LED Connector

(HOST_DETECT_L)

Left I/O Power Connector

Request for at least 10 GND test points

NOTE: 10 additional GND test points are called out separately in these notes.

RTC Battery Connector

FUNC_TEST

Thermal Diode Connectors

LPC+ Debug Connector

FUNC_TEST

2 TPs per

FUNC_TEST

Battery Digital Connector

FUNC_TEST

Request for 3 test points

Request for 2 test points

Fan Connectors

System Validation TPs

FUNC_TEST

FUNC_TESTFUNC_TEST

Left ALS

FUNC_TEST

Functional Test Points

NO_TEST

MAKE_ BASE

NB NO_TESTs

FUNC_TEST

ICT Test Points

Current Sense Calibration

MAKE_ BASE

NO_TEST

CPU FSB NO_TESTs

I404

I405

I406

I407

I408

I409

I410

I411

I412

I413

I414

I415

I416

I417

I418

I419

I420

I421

I422

I423

I424

I426

I427

I430

I431

I432

I433

I436

I442

I443

I447

I448

I490

I491

I492

I493

I494

I495

I496

I497

I498

I506

I507

I509

I515

I516 I517

I519

I520

I521

I529

I530

I531

I533

I534

I535

I536

I539 I540

I541

I542

I544

I545

I546

I547

I548

I549

I550 I551

I552

I553

I554

I555

I556

I557

I558 I559

I561

I567

I568

I569 I570

I571

Functional / ICT Test

051-7431

A.0.0

92

7

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

TRUE

FSB_BNR_L

FSB_ADSTB_L<1..0>

TRUE

NC_CPU_RSVD5

TRUE

FSB_DBSY_L

TRUE

FSB_REQ_L<4..0>

FSB_HIT_L

TRUE

FSB_DSTB_L_N<3..0>

TRUE

FSB_DINV_L<3..0>

NC_CPU_RSVD5

TRUE TRUE

TRUE

FSB_BREQ0_L

TRUE

FSB_ADS_L

TRUE

FSB_HITM_L FSB_LOCK_L

TRUE

FSB_D_L<63..0>

FSB_DSTB_L_P<3..0>

TRUE

FSB_DRDY_L

TRUE

FSB_A_L<31..3>

TRUE

NC_NB_RSVD<24>

TRUE

NC_NB_RSVD<26..27>

TRUETRUE

TP_NB_NC<1..16>

LPC_FRAME_L

TRUE

FWH_INIT_L

SMC_TX_L

TRUE

NC_NB_NC<1..16>

TRUE

TP_NB_RSVD<26..27> TP_NB_RSVD<24>

PPVCORE_S0_CPU

TRUE

PP5V_S3

TRUE

USB_IR_N

TRUE

NB_CLK100M_PCIE_P

TRUE

NB_RESET_L

TRUE

PP5V_S3_CAMERA_F

TRUE

P1V8P1V5P1V05S0_PGOOD

TRUE

PM_ENET_EN

TRUE

PM_S4_STATE_L

TRUE

FSB_DPWR_L

TRUE

SYS_LED_ANODE

CPU_STPCLK_L

TRUE

FSB_CLK_NB_P

TRUE

PLT_RST_L

TRUE

FSB_CLK_CPU_N

TRUE

USB_IR_P

IMVP_VR_ON

TRUE

IMVP_DPRSLPVR

TRUE

IMVP6_VID<6..0>

TRUE

PPVBATT_G3_RTC

SMBUS_SMC_BSA_SCL

TRUE

SMC_BS_ALRT_L

TRUE

BKLT_PWM

TRUE

FSB_CLK_NB_N

TRUE

NB_CLK100M_PCIE_N

TRUE

PP5V_S0

TRUE

FAN_LT_PWM FAN_LT_TACH

TRUE

FAN_RT_PWM

TRUE

FAN_RT_TACH

TRUE

PP3V42_G3H

TRUE

PP5V_S0

TRUE

LPC_AD<0>

TRUE

LPC_AD<1>

PM_CLKRUN_L

TRUE TRUE

PCI_FW_GNT_L

TRUE

SMC_TMS

TRUE

DEBUG_RESET_L SMC_TRST_L

TRUE TRUE

SMC_TDO SMC_MD1

TRUE

PCI_CLK33M_LPCPLUS LPC_AD<2>

TRUE

LPC_AD<3>

TRUE

INT_SERIRQ

TRUE TRUE

PM_SUS_STAT_L

TRUE

SMC_TDI

TRUE

SMC_TCK

TRUE

SMC_RESET_L

TRUE

SMC_NMI

TRUE

SMC_RX_L LINDACARD_GPIO

TRUE

ALS_GAIN

TRUE

LTALS_OUT

HSTHMSNS_D_P

TRUE

HSTHMSNS_D_N

TRUE TRUE

RSFSTHMSNS_D_P

TRUE

RSFSTHMSNS_D_N CPUTHMSNS_D2_P

TRUE TRUE

CPUTHMSNS_D2_N

TRUE

CPU_PWRGD

TRUE

CPU_DPSLP_L

TRUE

PM_DPRSLPVR CPU_DPSLP_L

TRUE TRUE

PM_LAN_ENABLE PCI_RST_L

TRUE

PM_RSMRST_L

TRUE

PM_SB_PWROK

TRUE

SB_RTC_RST_L

TRUE

PM_STPCPU_L

TRUE

PM_STPPCI_L

TRUE

VR_PWRGD_CLKEN

TRUE TRUE

VR_PWRGOOD_DELAY FSB_CPURST_L

TRUE

FSB_CPUSLP_L

TRUE

NB_SB_SYNC_L

TRUE

PM_BMBUSY_L

TRUE

CPU_THERMTRIP_R

TRUE

NB_CLKREQ_L

TRUE

SMC_LRESET_L

TRUE

GPU_RESET_L

TRUE

FSB_CLK_CPU_P

TRUE

CPU_DPRSTP_L

TRUE

PM_SLP_S5_L

TRUE

PM_SLP_S3_L

TRUE

SMC_ONOFF_L

TRUE

PM_SYSRST_L

USB_CAMERA_F_P

TRUE

USB_CAMERA_F_N

TRUE

PPVCORE_GPU

TRUE

PP5V_S0

TRUE

ISENSE_CAL_EN

TRUE

PPBUS_G3H

TRUE

PP18V5_DCIN

TRUE

GND

TRUE

BATT_POS

TRUE

SMBUS_SMC_BSA_SDA

TRUE

BKLT_P5V_EN

TRUE

BKLT_GND

TRUE

BKLT_PWR

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

GND

TRUE

82

81

79

80

75

65

81

65

66

59

66

59

63

58

65

58

65

58

62

54

57

54

62

54

61

52

48

52

58

52

60

65

49

47

49

59

81

58

47

46

47

83

45

47

58

47

49

58

88

65

45

88

82

88

42

45

42

87

47

83

59

83

88

59

40

75

42

57

88

83

47

46

12

46

86

30

63

65

43

83

30

28

30

86

83

57

30

27

43

27

47

88

47

46

47

46

54

23

59

23

28

30

28

14

83

30

23

46

36

81

45

68

27

49

57

14

10

14

16

45

11

44

81

29

28

62

61

34

14

81

23

29

24

29

81

59

83

59

48

46

82

29

8

28

8

45

38

46

47

46

47

45

46

47

45

47

45

54

91

13

10

25

10

45

28

45

25

28

29

28

16

13

14

25

29

45

67

29

16

45

35

46

28

91

49

8

49

40

66

48

82

10

7

10

10 16

23

47

43

16

8

24

16

44

61

36

25

10

46

10

14

9

10

24

45

59

12

28

45

81

14

16

7

52

8

7

23

25

24

45

28

45

30

23

25

45

43

25

34

51

10

7

16

7

25

24

25

9

23

25

9

10

16

23

16

28

10

25

45

25

44

8

7

45

8

57

45

81

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Yukon EC will not be supported

1.8V-0.9V Rails

5V Rails

"FW" (FireWire) Rails

"ENET" Rails

3.3V-2.5V Rails

"G3Hot" (Always-Present) Rails

Chipset "VCore" Rails

MAX I = ?.??A

"GPU" Rails

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

8

92

A.0.0

051-7431

Power Aliases

PP3V3_S0GPU

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V25_S0_ISNS

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_FW

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

PPVP_FW_PORTB_UF

MAKE_BASE=TRUE

PPVP_FW_PORTA_UF

MAKE_BASE=TRUE

PP1V8_S3

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

MAKE_BASE=TRUE

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V25_S0_ISNS

PP1V05_S0

PPVCORE_S0_NB_R

PP0V9_S3_MEM_VREF

PP0V9_S0

PP3V3_ENET

PP3V3_S0

PP3V3_S0 PP3V3_S0

MIN_LINE_WIDTH=0.6 mm

PP3V3_S0

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S3 PP3V3_S3

PP3V3_S3

VOLTAGE=3.3V

PP3V3_S3

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP5V_S0 PP5V_S0

VOLTAGE=5V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S0

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PPBUS_G3H

PPBUS_G3H PPBUS_G3H

PPBUS_G3H

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25 mm

PP3V3_S0GPU_TMDS PP3V3_S0GPU_TMDS

PP3V42_G3H

VOLTAGE=3.42V

MIN_LINE_WIDTH=0.3 mm

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP3V42_G3H

PP5V_S5

PP5V_S3

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm

PP5V_S0

PP5V_S5

VOLTAGE=5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP5V_S5

PP3V42_G3H

PPDCIN_G3H

PP3V3_S3

PP3V3_S0

PP1V25_S0

PP5V_S0

PP3V3_S0

PP3V3_S3

PP3V3_S5

PP5V_S3

PP5V_S5

PP3V42_G3H

PP5V_S0

PP3V3_S0

PP3V42_G3H

PPDCIN_G3H

PP3V42_G3H

PPDCIN_G3H

PP5V_S3

PP3V3_S0

PP3V3_S5

PP3V3_S0

PP3V3_S0 PP3V3_S0

PP3V3_S0

PP5V_S5

PPVCORE_S0_CPU

PP3V3_S0GPU PP3V3_S0GPU

PP3V3_S0GPU

PP1V9_ENET

PP1V25_S0_ISNS

PP1V5_S0

PP1V5_S0 PP1V5_S0

PP1V5_S0

PP1V8_S3_ISNS

PP3V3_S5

PP3V3_S3 PP3V3_S3

PP5V_S3

PPBUS_G3H

PP1V8_S3

PP0V9_S3_MEM_VREF

PP3V3_ENET

PPVCORE_S0_NB_R

PP1V05_S0

PP1V95_FW

PP3V3_S0GPU_TMDS

PP1V05_S0

PP0V9_S3_MEM_VREF

PP1V05_S0

PP0V9_S3_MEM_VREF

PP0V9_S0

PP3V3_ENET

PP1V9_ENET

PP1V25_ENET

PP3V3_S5 PP3V3_S5

PP3V3_S5

PP5V_S0

PP3V3_S5

PPVCORE_S0_CPU

PP1V8_S3

PP1V25_ENET

PP0V9_S3_MEM_VREF

PP1V05_S0

GND

PPVP_FW

PPVP_FW_PORTB_UF

PP3V3_FW

PPBUS_FW_FWPWRSW_F

PPVP_FW

PPVP_FW_PORTA_UF

PP1V25_S0

PP3V3_FW PP3V3_FW PP3V3_FW PP3V3_FW

PP1V95_FW PP1V95_FW

PP3V3_S5

PP1V05_S0

PPVP_FW

PP3V42_G3H PP3V42_G3H

PP1V25_S0_ISNS

PPBUS_G3H

PP5V_S3

PP5V_S5

PP3V42_G3H

PP5V_S5

PP3V3_S0

PP1V25_ENET

GND

PPVCORE_GPU

PP1V8_S0GPU

PP1V05_S0

PP1V8_S0GPU_ISNS

PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS PP1V8_S0GPU_ISNS

PP1V05_S0

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.05V MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm

PP3V3_S0GPU_TMDS

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.4 mm VOLTAGE=18.5V

MIN_NECK_WIDTH=0.2 mm

PPDCIN_G3H

MAKE_BASE=TRUE

PP3V3_S5

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=3.3V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm VOLTAGE=1.5V

PP1V5_S0

PP1V8_S3_ISNS

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V MAKE_BASE=TRUE

MAKE_BASE=TRUE

VOLTAGE=0.9V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP0V9_S3_MEM_VREF

PPVCORE_S0_NB_R

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=0.9V MAKE_BASE=TRUE

VOLTAGE=1.9V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V9_ENET

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V

PPVCORE_S0_CPU

PPBUS_FW_FWPWRSW_F

MAKE_BASE=TRUE

PPVP_FW

VOLTAGE=33V

MIN_NECK_WIDTH=0.3 mm

MIN_LINE_WIDTH=0.6 mm

MAKE_BASE=TRUE

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm

MAKE_BASE=TRUE

PP3V3_ENET

MAKE_BASE=TRUE

VOLTAGE=1.95V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.4 mm

PP1V95_FW

MIN_LINE_WIDTH=0.6 mm VOLTAGE=1.25V

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP1V25_S0

VOLTAGE=0.9V

PP0V9_S0

MAKE_BASE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP1V25_ENET

VOLTAGE=1.25V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PPVCORE_GPU

VOLTAGE=1.2V MAKE_BASE=TRUE

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_S0GPU

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V8_S0GPU_ISNS

PP5V_S0

PP5V_S5

PP3V3_S0

PP1V25_S0_ISNS

PP3V3_S0GPU

PP3V3_S0GPU PP3V3_S0GPU

PP1V25_S0_ISNS

42 58 43

91

82

65

59

58

53

52

51

50

48

47

46

61

42

61

61 50

32

82

32

82

50

82

50

50 46

31

82

79

82

31

82

31

91

82

31

91

79

46

91

82

91

46

91

46

79

46

82

30

81

75

81

30

81

30

76

81

30

76

75

30

76

81

76

30

76

30

75

30

81

27

29

80

66

81

79

80

79

81

29

80

29

65

79

81

80

29

81

29

79

65

66

27

65

80

65

27

65

27

81

66

79

81

79

27

80

79

26

28

81

65

63

66

75

65

75

66

81

28

65

28

81

60

75

66

65

28

66

28

75

60

81

63

26

60

65

60

26

60

26

66

63

75

66

75

26

65

75

80

72

23

27

65

59

62

65

59

65

27

59

27

65

58

65

59

27

65

27

65

80

72

58

65

62

23

58

59

58

23

58

23

65

72

62

65

23

78

23

78

59

65

72

80

72

65

76

69

21

26

58

61

57

63

58

63

57

58

26

58

26

58

56

63

57

58

26

57

26

63

76

69

91

56

58

61

21

56

58

56

21

56

21

57

69

61

63

57

63

21

77

21

91

77

58

63

69

76

69

63

75

67

19

25

55

54

60

48

62

54

62

48

55

25

54

25

55

48

62

48

54

25

48

25

62

75

67

63

48

55

60

19

48

54

48

19

48

19

48

67

60

62

48

62

19

74

19

63

74

54

62

67

75

67

62

74

65

91

65

18

24

54

52

59

47

61

52

61

47

54

24

52

24

54

46

61

47

52

24

47

24

61

74

65

34

46

54

59

91

18

46

52

46

91

18

46

18

47

65

59

61

47

61

18

71

18

34

71

52

61

65

74

65

61

73

50

62

50

14

23

51

49

58

46

60

81

49

60

46

51

23

49

23

51

28

81

60

46

49

23

46

81

23

60

59

73

50

27

28

51

81

58

62

14

28

49

28

59

62

14

28

14

46

50

58

81

60

46

60

14

70

14

27

59

70

49

60

50

73

50

60

72

27

64

50

27

13

62

21

50

47

57

45

58

47

58

45

50

21

47

21

50

27

58

45

47

21

45

58

21

58

49

72

27

26

50

27

50

58

57

50

62

13

62

13

62

27

47

27

49

50

62

13

64

27

13

45

27

57

58

45

58

75

13

69

13

26

50

62

49

75

69

47

58

27

72

27

65

26

41

38

26

12

50

32

19

48

42

49

80

43

46

42

43

66

48

19

42

19

48

26

46

43

42

19

43

66

43

66

46

19

43

12

65

26

22

21

26

48

46

49

38

32

50

12

80

12

32

12

32

61

26

42

26

12

38

61

32

12

64

41

64

41

26

12

64

43

26

49

46

43

61

68

12

68

12

80

66

22

21

32

50

12

64

61

68

42

43

26

65

26

58

21

40

41

32

21

11

21

31

62

36

16

38

27

40

74

28

42

44

27

42

28

65

38

16

58

27

16

38

25

44

42

28

27

16

28

65

28

65

44

16

42

11

58

36

21

12

18

25

38

44

40

32

31

36

21

11

74

11

31

11

31

62

36

58

25

27

25

11

32

58

31

11

40

41

40

64

40

41

58

40

64

25

11

40

28

21

40

44

42

28

42

58

49

79

11

65

11

74

65

12

18

31

21

36

11

64

40

36

64

62

58

49

79

65

27

42

21

58

21

48

19

39

40

31

19

10

18

16

33

35

13

36

8

73

8

27

8

27

8

57

36

13

50

8

13

36

24

8

27

8

13

8

57

8

57

8

13

27

8

48

35

19

11

16

24

36

8

31

16

35

18

10

73

10

16

10

16

33

35

24

8

24

8

31

35

16

10

39

40

39

40

39

40

50

39

24

10

39

8

19

8

27

8

27

35

8

50

10

50

10

73

57

11

16

18

35

8

40

39

35

39

33

35

8

50

8

27

19

48

19

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

7

8

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

All holes are plated through holes with two exceptions:

GND_CHASSIS_BATTCONN_HOLE (to the left of DIMM cutout near board edge)

Chassis GNDs

TM Hole

RAM door (Torx) holes

Left CPU TM Hole

TM Hole

Top CPU TM "Hole"

Add 8 blind vias per side to GND

Thermal Module Holes

Digital Ground

Chassis connection to be made at the mounting hole east of the LVDS connector

Frame holes

Right CPU TM Hole

Top Right GPU

Bottom Left GPU

GND_CHASSIS_RIGHT_FAN_NOTCH (to the left of small well on lower board edge near USB)

195R106

ZT0955

1

195R106

ZT0965

1

235R126

ZT0930

235R126

ZT0935

1

SHLD-SM-LF

OG-503040

SH0925

1 2 3

195R106

ZT0900

1

195R106

ZT0901

1

195R106

ZT0985

1

195R106

ZT0975

1

195R106

ZT0970

1

195R106

ZT0980

1

9

24 86

9

24 86

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

Signal Aliases

9

051-7431

A.0.0

92

SMC_SMS_INT

MAKE_BASE=TRUE

IPHS_SW_BIAS_EN_L

IPHS_SW_INT

TP_MEM_A_A<15> TP_MEM_B_A<15>

MAKE_BASE=TRUE

TP_MEM_A_A<15>

SMC_ENRGYSTR_LDO_EN SMC_ENRGYSTR_LDO_EN

GPU_BL_PWM GPU_BKLT_EN

TP_EXTGPU_PWR_EN

MAKE_BASE=TRUE

IPHS_SW_INT

TP_EXTGPU_PWR_EN

IPHS_SW_BIAS_EN_L

MAKE_BASE=TRUE

TP_MEM_B_A<15>

MAKE_BASE=TRUE

GPU_BL_PWM

GND

VOLTAGE=0V

GND

MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

SMC_SMS_INT

PLT_RST_L

GPU_BKLT_EN

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

TP_USB_EXTDN

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

PEG_CLK100M_GPU_P

PM_SB_PWROK

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

PEG_CLK100M_GPU_NPEG_CLK100M_GPU_N

MAKE_BASE=TRUE

TP_USB_EXTDN

MAKE_BASE=TRUE

TP_USB_EXTDP

VOLTAGE=0V

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

PEG_CLK100M_GPU_P

MAKE_BASE=TRUE

VR_PWRGOOD_DELAY

MAKE_BASE=TRUE

PM_SB_PWROK

MAKE_BASE=TRUE

TP_USB_EXTDP

VR_PWRGOOD_DELAY

PLT_RST_L

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm VOLTAGE=0V

GND

82

88

88 88

88

59 59

82

66 66

82

28

82

67

28

67 67

67

28

55

34

46 46

73

34

73

55

24

73

30

25

30 30

86

30

16

25

86

16

24

45

25

24

31

32

31

45 45

72

23

24

23

25

32

72

45

9

72

29

9

29 29

24

29

9

24

9

9 9

9

7

9

7

9 9

9

7

9

7

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN IN

IN

OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

OUT OUT

OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI

BI

BI BI

BI BI BI BI BI

BI

OUT

IN

IN IN IN IN IN

IN IN

OUT

IN IN

IN

IN IN

IN

OUT

BI BI BI BI

LOCK*

INIT*

A20M*

A6*

A3* A4*

A14*

A16*

REQ0* REQ1* REQ2* REQ3* REQ4*

BCLK1

BCLK0

THERMTRIP*

THERMDA

PROCHOT*

DBR*

TRST*

TMS

TDO

TDI

TCK

PREQ*

PRDY*

BPM3*

BPM2*

BPM1*

BPM0*

HITM*

HIT*

TRDY*

RS2*

RS1*

RS0*

RESET*

IERR*

BR0*

DBSY*

DRDY*

DEFER*

BNR*

RSVD4

RSVD3

RSVD2

RSVD1

RSVD0

SMI*

LINT1

LINT0

STPCLK*

FERR*

ADSTB1*

A35*

A34*

A33*

A32*

A31*

A30*

A29*

A28*

A19*

A18*

A17*

ADSTB0*

A13*

A12*

BPRI*

A20* A21* A22* A23* A24*

A26* A27*

A9*

A8*

A7*

A11*

A25*

THERMDC

IGNNE*

ADS*

A10*

A15*

A5*

RSVD5 RSVD6 RSVD7 RSVD8

1 OF 4

CONTROL

THERMAL

XDP/ITP SIGNALS

H CLK

ADDR GROUP1

ICH

RESERVED

ADDR GROUP0

TEST7

TEST6

DSTBP1* DINV1*

D31*

D30*

D25*

D11* D12* D13* D14*

DSTBP0* DINV0*

D9*

D8*

D7*

D6*

D19*

D18*

D0*

D32* D1* D2*

D5*

D16*

D20* D21* D22* D23* D24*

D26* D27* D28* D29*

DSTBN1*

GTLREF

TEST3 TEST4 TEST5

BSEL0 BSEL1 BSEL2

D33*

D34*

D35*

D36*

D37*

D38*

D39*

D40*

D41*

D42*

D43*

D44*

D45*

D46*

D47*

DSTBN2* DSTBP2*

DINV2*

D48*

D49*

D50*

D51*

D52*

D53*

D54*

D55*

D56*

D57*

D58*

D59*

D60*

D61*

D62*

D63*

DSTBN3* DSTBP3*

DINV3*

COMP0 COMP1 COMP2 COMP3

DPRSTP*

DPSLP*

DPWR*

PWRGOOD

SLP*

PSI*

D17*

D4*

D3*

DSTBN0*

D15*

D10*

TEST2

TEST1

2 OF 4

DATA GRP 3 DATA GRP 2

MISC

DATA GRP 0DATA GRP 1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LAYOUT NOTE:

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP0,2 CONNECT WITH ZO=27.4OHM,

MAKE TRACE LENGTH SHORTER THAN 0.5".

COMP1,3 CONNECT WITH ZO=55OHM,

PM_THRMTRIP# SHOULD CONNECT TO ICH AND GMCH WITHOUT T (NO STUB)

0.1" AWAY

PLACE TESTPOINT ON FSB_IERR_L WITH A GND

0.5" MAX LENGTH FOR CPU_GTLREF

REFERENCED TO GND

PLACE C1000 CLOSE TO CPU_TEST4 PIN. MAKE SURE CPU_TEST4 IS

402

MF-LF

54.9

1/16W

1%

R1002

1

2

MF-LF 402

1/16W

5%

68

R1004

1

2

402

1K

MF-LF

1%

1/16W

R1005

1

2

402

1/16W

2.0K

MF-LF

1%

R1006

1

2

402

54.9

1/16W MF-LF

1%

R1019

402

1%

MF-LF

1/16W

27.4

R1018

402

54.9

1/16W MF-LF

1%

R1017

402

27.4

1/16W MF-LF

1%

R1016

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

16 23 59 83

7

23 83

7

14 83

7

14 83

28 59

7

13 23 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

30 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

7

14 83

13 83

10 13 83

13 28

46 59 83

51 91

16 23 46 83

23 47 83

7

13 14 83

14 83

10 13 83

51 91

7

29 30 88

7

29 30 88

23 83

7

23 83

402

NOSTUFF

5%

MF-LF

1/16W

0

R1030

402

NOSTUFF

1K

MF-LF

5% 1/16W

R1007

1

2

402

54.9

MF-LF

1%

1/16W

R1003

1

2

402

54.9

1/16W MF-LF

1%

R1020

402

1%

MF-LF

1/16W

54.9

R1021

402

1%

MF-LF

1/16W

54.9

R1022

14 83

402

1%

MF-LF

1/16W

649

R1023

402

MF-LF

NOSTUFF

1K

5%

1/16W

R1012

1

2

402

16V

10%

0.1uF

NOSTUFF

X5R

C1000

1

2

402

PLACEMENT_NOTE=Place R1024 near ITP connector (if present)

54.9

1/16W MF-LF

1%

R1024

OMIT

PENRYN

FCBGA

U1000

N3 P5 P2 L2 P4 P1 R1

Y2 U5 R3 W6

A6

U4 Y5 U1 R4 T5 T3 W2 W5 Y4

J4

U2 V4

W3 AA4 AB2 AA3

L5

L4

K5

M3

N2

J1

H1

M1

V1

A22 A21

E2

AD4 AD3 AD1 AC4

G5

F1

C20

E1

H5 F21

A5

G6 E4

D20

C4

B3

C6

B4

H4

AC2 AC1

D21

K3

H2

K2

J3

L1

C1 F3 F4 G3

M4

N5

T2

V3

B2

F6

D2 D22

D3

A3

D5

AC5 AA6 AB3

A24 B25

C7

AB5

G2

AB6

OMIT

PENRYN

FCBGA

U1000

B22 B23 C21

R26 U26 AA1 Y1

E22 F24

J24 J23 H22 F26 K22 H23

N22 K25 P26 R23

E26

L23 M24 L22 M23 P25 P23 P22 T24 R24 L25

G22

T25 N25

Y22 AB24 V24 V26 V23 T22 U25 U23

F23

Y25 W22 Y23 W24 W25 AA23 AA24 AB25

AE24 AD24

G25

AA21 AB22 AB21 AC26 AD20 AE22 AF23 AC25 AE21 AD21

E25

AC22 AD23 AF22 AC23

E23 K24 G24

H25

N24

U22

AC20

E5 B5 D24

J26

L26

Y26

AE25

H26

M26

AA26

AF24

AD26

AE6

D6 D7

C23 D25 C24

AF26

AF1 A26

C3

CPU FSB

10

A.0.0

051-7431

92

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

FSB_A_L<14>

FSB_A_L<16>

FSB_A_L<18>

FSB_A_L<25>

PP1V05_S0

TP_CPU_TEST6 TP_CPU_TEST7

CPU_TEST2

FSB_DSTB_L_P<1> FSB_DINV_L<1>

FSB_D_L<31>

FSB_D_L<30>

FSB_D_L<25>

FSB_D_L<11> FSB_D_L<12> FSB_D_L<13> FSB_D_L<14>

FSB_DSTB_L_P<0> FSB_DINV_L<0>

FSB_D_L<9>

FSB_D_L<8>

FSB_D_L<7>

FSB_D_L<6>

FSB_D_L<19>

FSB_D_L<18>

FSB_D_L<0>

FSB_D_L<32> FSB_D_L<1> FSB_D_L<2>

FSB_D_L<5>

FSB_D_L<16>

FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23> FSB_D_L<24>

FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29>

FSB_DSTB_L_N<1>

CPU_GTLREF

TP_CPU_TEST3 CPU_TEST4 TP_CPU_TEST5

CPU_BSEL<0> CPU_BSEL<1> CPU_BSEL<2>

FSB_D_L<33>

FSB_D_L<34>

FSB_D_L<35>

FSB_D_L<36>

FSB_D_L<37>

FSB_D_L<38>

FSB_D_L<39>

FSB_D_L<40>

FSB_D_L<41>

FSB_D_L<42>

FSB_D_L<43>

FSB_D_L<44>

FSB_D_L<45>

FSB_D_L<46>

FSB_D_L<47>

FSB_DSTB_L_N<2>

FSB_DSTB_L_P<2>

FSB_DINV_L<2>

FSB_D_L<48>

FSB_D_L<49>

FSB_D_L<50>

FSB_D_L<51>

FSB_D_L<52>

FSB_D_L<53>

FSB_D_L<54>

FSB_D_L<55>

FSB_D_L<56>

FSB_D_L<57>

FSB_D_L<58>

FSB_D_L<59>

FSB_D_L<60>

FSB_D_L<61>

FSB_D_L<62>

FSB_D_L<63>

FSB_DSTB_L_N<3>

FSB_DSTB_L_P<3>

FSB_DINV_L<3>

CPU_COMP<0>

CPU_COMP<1>

CPU_COMP<2>

CPU_COMP<3>

CPU_DPRSTP_L

CPU_DPSLP_L

FSB_DPWR_L

CPU_PWRGD

FSB_CPUSLP_L

CPU_PSI_L

FSB_D_L<17>

FSB_D_L<4>

FSB_D_L<3>

FSB_DSTB_L_N<0>

FSB_D_L<15>

FSB_D_L<10>

CPU_TEST1

FSB_REQ_L<1>

FSB_LOCK_L

CPU_INIT_L

CPU_A20M_L

FSB_A_L<6>

FSB_A_L<3> FSB_A_L<4>

FSB_REQ_L<0>

FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_CLK_CPU_N

FSB_CLK_CPU_P

PM_THRMTRIP_L

CPU_THERMD_P

CPU_PROCHOT_L

XDP_DBRESET_L

XDP_TRST_L

XDP_TMS

XDP_TDO

XDP_TDI

XDP_TCK

XDP_BPM_L<5>

XDP_BPM_L<4>

XDP_BPM_L<3>

XDP_BPM_L<2>

XDP_BPM_L<1>

XDP_BPM_L<0>

FSB_HITM_L

FSB_HIT_L

FSB_TRDY_L

FSB_RS_L<2>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_CPURST_L

CPU_IERR_L

FSB_BREQ0_L

FSB_DBSY_L

FSB_DRDY_L

FSB_DEFER_L

FSB_BNR_L

TP_CPU_RSVD4

TP_CPU_RSVD3

TP_CPU_RSVD2

TP_CPU_RSVD1

TP_CPU_RSVD0

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_STPCLK_L

CPU_FERR_L

FSB_ADSTB_L<1>

FSB_A_L<35>

FSB_A_L<34>

FSB_A_L<33>

FSB_A_L<32>

FSB_A_L<31>

FSB_A_L<30>

FSB_A_L<29>

FSB_A_L<28>

FSB_A_L<19>

FSB_A_L<17>

FSB_ADSTB_L<0>

FSB_A_L<13>

FSB_A_L<12>

FSB_BPRI_L

FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24>

FSB_A_L<26> FSB_A_L<27>

FSB_A_L<9>

FSB_A_L<8>

FSB_A_L<7>

FSB_A_L<11>

CPU_THERMD_N

CPU_IGNNE_L

FSB_ADS_L

FSB_A_L<10>

FSB_A_L<15>

FSB_A_L<5>

NC_CPU_RSVD5 TP_CPU_RSVD6 TP_CPU_RSVD7 TP_CPU_RSVD8

PP1V05_S0

XDP_TRST_L

XDP_TDI

XDP_TMS

XDP_TDO

XDP_TCK

61

50

46

30

27

26

23

21

19

18

14

13

12

11

83

10

13

8

83 83

83

7

8

10

OUT OUT OUT OUT OUT OUT OUT

OUT

VCC

VCCP

VCCA

VID0 VID1 VID2 VID3 VID4 VID5 VID6

VCCSENSE

VSSSENSE

VCC

3 OF 4

VSS VSS

4 OF 4

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TBD A (Enhanced Deeper Sleep)

17.0 A (Design Target)

Ultra Low Voltage:

Standard Voltage:

44.0 A (Design Target)

27.4 A (Auto-Halt/Stop-Grant HFM)

TBD A (Deep Sleep SuperLFM)

TBD A (Deep Sleep HFM) TBD A (Deep Sleep LFM)

TBD A (Deeper Sleep) TBD A (Enhanced Deeper Sleep)

TBD A (Auto-Halt/Stop-Grant HFM) TBD A (Auto-Halt/Stop-Grant SuperLFM)

TBD A (Deep Sleep HFM)

21.0 A (HFM)

TBD A (Sleep HFM)

9.4 A (Enhanced Deeper Sleep)

11.5 A (Deeper Sleep)

25.0 A (Deep Sleep HFM)

27.4 A (Sleep HFM)

25.5 A (SuperLFM)

TBD A (Sleep LFM)

TBD A (Auto-Halt/Stop-Grant LFM)

Current numbers from Merom for Santa Rosa EMTS, doc #22221.

TBD A (LFM)

TBD A (HFM)

TBD A (Auto-Halt/Stop-Grant HFM)

TBD A (Sleep HFM)

TBD A (Deeper Sleep)

TBD A (Sleep SuperLFM)

TBD A (SuperLFM)

18.7 A (LFM)

23.0 A (Design Target)

Low Voltage:

(CPU INTERNAL PLL POWER 1.5V)

(CPU IO POWER 1.05V)

130 mA

(CPU CORE POWER)

41.0 A (HFM)

16.8 A (Sleep SuperLFM)

16.0 A (Deep Sleep SuperLFM)

4500 mA (before VCC stable) 2500 mA (after VCC stable)

30.4 A (LFM)

17.0 A (Auto-Halt/Stop-Grant SuperLFM)

12 83

1/16W

1%

100

402

MF-LF

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

R1101

1

2

12 83

59 83

100

1% 1/16W

PLACEMENT_NOTE=Place within 1 inch of CPU, no stub.

402

MF-LF

R1100

1

2

FCBGA

PENRYN

OMIT

U1000

A7 A9

B9 B10 B12 B14 B15 B17 B18 B20

C9 C10

A10

C12 C13 C15 C17 C18

D9 D10 D12 D14 D15

A12

D17 D18

E7

E9 E10 E12 E13 E15 E17 E18

A13

E20

F7

F9 F10 F12 F14 F15 F17 F18 F20

A15

AA7 AA9

AA10 AA12 AA13 AA15 AA17 AA18 AA20

AB9

A17

AC10 AB10 AB12 AB14 AB15 AB17 AB18

AB20 AB7 AC7

A18

AC9 AC12 AC13 AC15 AC17 AC18 AD7 AD9 AD10 AD12

A20

AD14 AD15 AD17 AD18 AE9 AE10 AE12 AE13 AE15 AE17

B7

AE18 AE20 AF9 AF10 AF12 AF14 AF15 AF17 AF18 AF20

B26 C26

G21 V6

R21 R6 T21 T6 V21 W21

J6 K6 M6 J21 K21 M21 N21 N6

AF7

AD6 AF5 AE5 AF4 AE3 AF3 AE2

AE7

FCBGA

PENRYN

OMIT

U1000

A4 A8

B11

W1 W4 W23 W26 Y3 Y6 Y21 Y24 AA2 AA5

B13

AA8 AA11 AA14 AA16 AA19 AA22 AA25 AB1 AB4 AB8

B16

AB11 AB13 AB16 AB19 AB23 AB26 AC3 AC6 AC8 AC11

B19

AC14 AC16 AC19 AC21 AC24 AD2 AD5 AD8 AD11 AD13

B21

AD16 AD19 AD22 AD25 AE1 AE4 AE8 AE11 AE14 AE16

B24

AE19 AE23 AE26 A2 AF6 AF8 AF11 AF13 AF16 AF19

C5

AF21 A25 AF25

B1

C8 C11 C14

A11

C16 C19

C2 C22 C25

D1

D4

D8 D11 D13

A14

D16 D19 D23 D26

E3

E6

E8 E11 E14 E16

A16

E19 E21 E24

F5

F8 F11 F13 F16 F19

F2

A19

F22 F25

G4

G1 G23 G26

H3

H6 H21 H24

A23

J2

J5 J22 J25

K1

K4 K23 K26

L3

L6

AF2

L21 L24

M2

M5 M22 M25

N1

N4 N23 N26

B6

P3

P6 P21 P24 R2 R5 R22 R25 T1 T4

B8

T23 T26 U3 U6 U21 U24 V2 V5 V22 V25

9211

A.0.0

051-7431

CPU Power & Ground

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

PPVCORE_S0_CPU

CPU_VCCSENSE_N

CPU_VCCSENSE_P

CPU_VID<6>

CPU_VID<5>

CPU_VID<4>

CPU_VID<3>

CPU_VID<2>

CPU_VID<1>

CPU_VID<0>

PP1V5_S0

PP1V05_S0

PPVCORE_S0_CPU

61 50 46 30

27 26 23

91

21

63

19

59

34

18

59

49

27

14

49

12

26

13

12

11

22

12

11

8

12

10

8

7

8

7

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

WF: Consider sharing bulk cap with NB Vtt?

VCCA (CPU AVdd) DECOUPLING

1x 10uF, 1x 0.01uF

VCCP (CPU I/O) DECOUPLING

1x 470uF, 6x 0.1uF 0402

CPU VCORE HF AND BULK DECOUPLING

CPU VCORE VID CONNECTIONS

4x 330uF, 20x 22uF 0805

22UF

20%

6.3V 805

CERM-X5R

C1206

1

2

470UF

20%

D2T

TANT

2.5V

CRITICAL

C1235

1

2 3

22UF

20%

6.3V 805

CERM-X5R

C1204

1

2

22UF

CERM-X5R 805

6.3V

20%

C1216

1

2

22UF

CERM-X5R 805

6.3V

20%

C1214

1

2

22UF

20%

6.3V 805

CERM-X5R

C1208

1

2

22UF

20%

6.3V 805

CERM-X5R

C1203

1

2

22UF

20%

6.3V 805

CERM-X5R

C1207

1

2

6.3V

22UF

20% 805

CERM-X5R

C1202

1

2

22UF

20%

6.3V 805

CERM-X5R

C1201

1

2

22UF

CERM-X5R 805

6.3V

20%

C1213

1

2

22UF

CERM-X5R

20%

805

6.3V

C1212

1

2

22UF

CERM-X5R 805

6.3V

20%

C1211

1

2

22UF

CERM-X5R

20%

6.3V 805

C1219

1

2

20% 805

6.3V

22UF

CERM-X5R

C1200

1

2

22UF

CERM-X5R

20%

6.3V 805

C1210

1

2

10V 402

CERM

20%

0.1UF

C1236

1

2

22UF

20%

6.3V 805

CERM-X5R

C1205

1

2

22UF

20%

6.3V 805

CERM-X5R

C1209

1

2

22UF

CERM-X5R 805

6.3V

20%

C1215

1

2

22UF

CERM-X5R 805

6.3V

20%

C1217

1

2

10V

0.1UF

402

CERM

20%

C1237

1

2

10V

0.1UF

402

CERM

20%

C1238

1

2

10V

0.1UF

402

CERM

20%

C1239

1

2

10V

0.1UF

402

CERM

20%

C1240

1

2

10V

0.1UF

402

CERM

20%

C1241

1

2

22UF

CERM-X5R

20%

805

6.3V

C1218

1

2

0.01UF

10% 16V

402

CERM

PLACEMENT_NOTE=Place near CPU pin B26.

C1281

1

2

603

10uF

20%

6.3V X5R

C1280

1

2

CRITICAL

PLACEMENT_NOTE=Place in CPU center cavity.

D2T

TANT

330UF

2.0V

10%

C1250

1

2 3

PLACEMENT_NOTE=Place in CPU center cavity.

D2T

TANT

CRITICAL

330UF

2.0V

10%

C1251

1

2 3

PLACEMENT_NOTE=Place in CPU center cavity.

10%

D2T

TANT

CRITICAL

330UF

2.0V

C1252

1

2 3

PLACEMENT_NOTE=Place in CPU center cavity.

CRITICAL

D2T

TANT

10%

330UF

2.0V

C1253

1

2 3

051-7431

SYNC_DATE=08/28/2007

A.0.0

12 92

SYNC_MASTER=M87_MLB

CPU Decoupling & VID

PPVCORE_S0_CPU

CPU_VID<0..6>

MAKE_BASE=TRUE

IMVP6_VID<0..6>

PP1V5_S0

PP1V05_S0

61 50 46 30 27

26 23

91

21

63

19

34

18

59

27

14

49

26

13

11

83

22

11

8

83

59

11

10

7

11

7

8

IN

BI

OUT

OUT IN

BI

IN

IN IN

OUT

IN

OUT OUT

OUT

IN

BI

IN

BI

IN

IN IN

IN

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

998-1571

OBSDATA_B0

(OBSDATA_A1)

(OBSDATA_A0)

OBSDATA_C1

SB OC[3]#

OBSFN_C0

NOTE: XDP_DBRESET_L must be pulled-up to 3.3V.

Use with 920-0451 adapter board to support CPU, NB & SB debugging.

Mini-XDP Connector

(VCC_OBS_CD)

OBSDATA_D3

SB GPIO[8]

NB CFG[8]

NB CFG[3]

NB CFG[7]

NB CFG[6]

NB CFG[5]

NB CFG[4]

NB CFG[1]

NB CFG[0] NB CFG[2]

SB OC[4]#

(OBSDATA_A2)

TCK0

(OBSDATA_A3)

NC

OBSFN_C1

OBSDATA_C0

OBSDATA_C2

TDO

TDI

ITPCLK#/HOOK5

RESET#/HOOK6 DBR#/HOOK7

SB OC[0]#

OBSDATA_C3

SB OC[1]#

SB OC[2]#

SB OC[5]#

SB OC[7]#

TCK1

SCL

SDA

OBSDATA_B1

OBSDATA_A1

OBSFN_A1

TRSTn

HOOK3

HOOK2

VCC_OBS_AB

HOOK1

TMS

OBSDATA_D1

OBSDATA_D0

OBSDATA_A3

OBSDATA_B3

OBSDATA_B2

OBSFN_A0

OBSDATA_A0

XDP_PRESENT#

OBSDATA_D2

ITPCLK/HOOK4

on even-numbered side of J1300

Please avoid any obstructions

Direction of XDP module

PWRGD/HOOK0

OBSDATA_A2

NOTE: This is not the standard XDP pinout.

SB OC[6]#

7

10 23 83

402

MF-LF

1/16W

5%

1K

XDP

R1399

1 2

XDP

1/16W

402

MF-LF

1%

54.9

R1315

1

2

402

16V

10%

0.1uF

X5R

XDP

C1300

1

2

MF-LF

10K

5% 1/16W

402

XDP_IG

R1331

1

2

402

MF-LF

10K

5%

1/16W

XDP_IG

R1330

1

2

402

16V

10%

0.1uF

X5R

XDP

C1301

1

2

10 28

10 83

7

10 14 83

10 83

29 30 83 88

24 34

24

24 36

24

24 43

1/16W

402

MF-LF

5%

1K

XDP

R1303

1 2

LTH-030-01-G-D-NOPEGS

CRITICAL

F-ST-SM

XDP_CONN

J1300

1

10

1112 1314 1516 1718 19

2

20

2122 2324 2526 2728 29

3

30

3132 3334 3536 3738 39

4

40

4142 4344 4546 4748 49

5

50

5152 5354 5556 5758 59

6

60

78 9

16 30 83

16

25 45

16

16 30 83

16

eXtended Debug Port (XDP)

SYNC_DATE=01/22/2007

SYNC_MASTER=T9_NOME

13

A.0.0

92

051-7431

PP3V3_S0

SMC_WAKE_SCI_L

NB_CFG<8>

XDP_TMS

XDP_CPURST_L

PM_LATRIGGER_L

FSB_CPURST_L

XDP_TDO XDP_TRST_L

XDP_TCK

XDP_BPM_L<3>

TP_XDP_HOOK3

USB_EXTA_OC_L

SB_GPIO30

XDP_CLK_P

USB_EXTB_OC_L

TP_XDP_HOOK2

WOW_EN

XDP_OBS20

XDP_BPM_L<2>

XDP_BPM_L<0>

NB_BSEL<0> NB_BSEL<1>

NB_CFG<7>

XDP_PWRGDCPU_PWRGD

NB_BSEL<2> NB_CFG<3>

PP1V05_S0

XDP_CLK_N

XDP_TDI

XDP_DBRESET_L

EXTGPU_LVDS_EN

USB_EXTD_OC_L

SB_GPIO40

XDP_BPM_L<5> XDP_BPM_L<4>

GND

XDP_BPM_L<1>

GND

NB_CFG<4> NB_CFG<5>

NB_CFG<6>

91 82 65 59 58 53 52

51 50 48 47 46 42

61

32

50

31

46

30

29

27

28

26

27

23

26

21

25

19

24

18

23

14

21

12

19

11

16

10

8

83

8

BI

BI BI

OUT

BI

BI BI

BI

BI BI BI BI

BI BI

BI

BI BI

BI BI BI BI

BI BI

OUT

BI

OUT

BI BI BI BI BI

BI BI

H_D0*

H_D3*

H_D2*

H_D33* H_D34* H_D35*

H_D1*

H_D4*

H_D10*

H_A4* H_A5* H_A6* H_A7* H_A8*

H_A9* H_A10* H_A11* H_A12* H_A13* H_A14* H_A15* H_A16* H_A17* H_A18* H_A19* H_A20* H_A21* H_A22* H_A23* H_A24* H_A25* H_A26* H_A27* H_A28* H_A29* H_A30* H_A31* H_A32* H_A33* H_A34* H_A35*

H_ADS*

H_ADSTB0* H_ADSTB1*

H_A3*

H_D7* H_D8* H_D9*

H_D11* H_D12* H_D13* H_D14* H_D15* H_D16* H_D17* H_D18* H_D19* H_D20* H_D21* H_D22* H_D23*

H_D25* H_D26* H_D27* H_D28* H_D29* H_D30*

H_D32*

H_D36* H_D37* H_BNR* H_D38*

H_BPRI* H_D39* H_D40*

H_DEFER*

H_D41*

H_DBSY* H_D42* H_D43* H_D44*

H_DPWR* H_D45*

H_DRDY* H_D46* H_HIT* H_D47*

H_HITM* H_D48*

H_LOCK*

H_TRDY*

H_D51* H_D52* H_D53*

H_DINV0*

H_D54*

H_DINV1*

H_D55*

H_DINV2*

H_D56*

H_DINV3*

H_D57* H_D58*

H_DSTBN0*

H_D59*

H_DSTBN1*

H_D60*

H_DSTBN2*

H_D61*

H_DSTBN3*

H_D62* H_D63*

H_DSTBP0* H_DSTBP1*

H_DSTBP2* H_SWING H_RCOMP

H_REQ0* H_SCOMP H_REQ1* H_SCOMP*

H_REQ2*

H_REQ3* H_CPURST*

H_REQ4* H_CPUSLP*

H_RS0* H_RS1*

H_AVREF

H_RS2*

H_DVREF

H_D5* H_D6*

H_D31*

H_BREQ*

H_D24*

H_D49* H_D50*

H_DSTBP3*

HPLL_CLK

HPLL_CLK*

HOST

(1 OF 10)

BI BI BI BI

BI

IN

OUT OUT

BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI

BI BI BI BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

X5R

0.1uF

10% 16V

402

C1425

1

2

2.0K

MF-LF

1%

1/16W

402

R1426

1

2

1K

MF-LF

1%

1/16W

402

R1425

1

2

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

54.9

MF-LF

1% 1/16W

402

R1420

1

2

24.9

MF-LF

1%

1/16W

402

R1415

1

2

221

MF-LF

1%

1/16W

402

R1410

1

2

100

MF-LF

1%

1/16W

402

R1411

1

2

X5R

0.1uF

10% 16V

402

C1410

1

2

7

10 83

OMIT

CRESTLINE

FCBGA

U1400

G17 C14 K16 B13 L16 J17 B14 K19 P15 R17 B16 H20 L19 D17 M17 N16 J19 B18 E19 B17

J13

B15 E17 C18 A19 B19 N19

B11 C11 M11 C15 F16 L13

G12 H17 G20

B9

C8 E8 F12

B6 E5

E2 G2

M10 N12

N9 H5

P13

K9 M2

W10

Y8 V4

G7

M3 J1 N5 N3 W6 W9 N2 Y7 Y9 P4

M6

W3 N1

AD12

AE3 AD9 AC9

AC7 AC14 AD11 AC11

H7

AB2

AD7

AB1

Y3 AC6 AE2 AC5 AG3 AJ9 AH8

H3

AJ14

AE9

AE11 AH12

AJ5 AH5 AJ6 AE7 AJ7 AJ2

G4

AE5 AJ3 AH2

AH13

F3

N8

H2

C10

D6

K5 L2 AD13 AE13

H8 K7

M7 K3 AD2 AH11

L7 K2 AC2 AJ10

A9

E4 C6 G10

C2

M14 E13 A11 H13 B12

E12 D7 D8

W1

W2

B3

B7

AM5 AM7

10 83

7

10 83

54.9

MF-LF

1%

1/16W

402

R1421

1

2

7

10 83

7

29 30 88

7

29 30 88

7

10 13 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

7

10 83

SYNC_DATE=01/25/2007

NB CPU Interface

051-7431

A.0.0

9214

SYNC_MASTER=T9_NOME

PP1V05_S0

FSB_D_L<47>

FSB_D_L<3>

FSB_D_L<2>

FSB_D_L<33> FSB_D_L<34> FSB_D_L<35>

FSB_D_L<1>

FSB_D_L<10>

FSB_D_L<7> FSB_D_L<8> FSB_D_L<9>

FSB_D_L<11>

FSB_D_L<13> FSB_D_L<14> FSB_D_L<15> FSB_D_L<16> FSB_D_L<17> FSB_D_L<18> FSB_D_L<19> FSB_D_L<20> FSB_D_L<21> FSB_D_L<22> FSB_D_L<23>

FSB_D_L<25> FSB_D_L<26> FSB_D_L<27> FSB_D_L<28> FSB_D_L<29> FSB_D_L<30>

FSB_D_L<32>

FSB_D_L<36> FSB_D_L<37>

FSB_D_L<39> FSB_D_L<40>

FSB_D_L<42>

FSB_D_L<44> FSB_D_L<45> FSB_D_L<46>

FSB_D_L<48>

FSB_D_L<51> FSB_D_L<52> FSB_D_L<53> FSB_D_L<54> FSB_D_L<55> FSB_D_L<56> FSB_D_L<57> FSB_D_L<58>

FSB_D_L<60> FSB_D_L<61> FSB_D_L<62> FSB_D_L<63>

NB_FSB_SCOMP NB_FSB_SCOMP_L

FSB_CPURST_L FSB_CPUSLP_L

FSB_D_L<6>

FSB_D_L<31>

FSB_D_L<24>

FSB_D_L<49> FSB_D_L<50>

FSB_D_L<12>

FSB_D_L<43>

FSB_D_L<5>

FSB_D_L<4>

FSB_D_L<0>

FSB_D_L<38>

FSB_D_L<41>

FSB_D_L<59>

NB_FSB_SWING NB_FSB_RCOMP

NB_FSB_VREF

FSB_A_L<3>

FSB_A_L<6>

FSB_A_L<4> FSB_A_L<5>

FSB_A_L<7> FSB_A_L<8> FSB_A_L<9>

FSB_A_L<11>

FSB_A_L<10>

FSB_A_L<12> FSB_A_L<13> FSB_A_L<14> FSB_A_L<15> FSB_A_L<16> FSB_A_L<17> FSB_A_L<18> FSB_A_L<19> FSB_A_L<20> FSB_A_L<21> FSB_A_L<22> FSB_A_L<23> FSB_A_L<24> FSB_A_L<25> FSB_A_L<26> FSB_A_L<27> FSB_A_L<28> FSB_A_L<29>

FSB_A_L<32>

FSB_A_L<30> FSB_A_L<31>

FSB_A_L<33> FSB_A_L<34> FSB_A_L<35>

FSB_ADS_L FSB_ADSTB_L<0> FSB_ADSTB_L<1>

FSB_BPRI_L

FSB_BNR_L

FSB_BREQ0_L FSB_DEFER_L FSB_DBSY_L

FSB_DPWR_L

FSB_CLK_NB_P FSB_CLK_NB_N

FSB_DRDY_L FSB_HIT_L FSB_HITM_L

FSB_TRDY_L

FSB_LOCK_L

FSB_DINV_L<0> FSB_DINV_L<1> FSB_DINV_L<2> FSB_DINV_L<3>

FSB_DSTB_L_N<0> FSB_DSTB_L_N<1> FSB_DSTB_L_N<2> FSB_DSTB_L_N<3>

FSB_DSTB_L_P<0> FSB_DSTB_L_P<1> FSB_DSTB_L_P<2> FSB_DSTB_L_P<3>

FSB_REQ_L<0> FSB_REQ_L<1> FSB_REQ_L<2> FSB_REQ_L<3> FSB_REQ_L<4>

FSB_RS_L<1>

FSB_RS_L<0>

FSB_RS_L<2>

61 50 46 30 27

26 23 21 19 18 13 12 11 10

8

IN

OUT

IN

OUT OUT OUT

OUT

IN

OUT

BI

L_BKLT_CTRL

L_VDD_EN

PEG_TX15*

PEG_TX14*

PEG_TX13*

PEG_TX12*

PEG_TX11*

PEG_TX10*

PEG_TX9*

PEG_TX8*

PEG_TX7*

PEG_TX6*

PEG_TX5*

PEG_TX4*

PEG_TX3*

PEG_TX2*

PEG_TX1*

PEG_TX0*

PEG_TX15

PEG_TX14

PEG_TX13

PEG_TX12

PEG_TX11

PEG_TX10

PEG_TX9

PEG_TX8

PEG_TX7

PEG_TX6

PEG_TX5

PEG_TX4

PEG_TX3

PEG_TX2

PEG_TX1

PEG_TX0

PEG_RX14

PEG_RX15*

PEG_RX14*

PEG_RX13*

PEG_RX12*

PEG_RX11*

PEG_RX15

PEG_RX13

PEG_RX12

PEG_RX11

PEG_RX10

PEG_RX9

PEG_RX8

PEG_RX7

PEG_RX6

PEG_RX5

PEG_RX4

PEG_RX3

PEG_RX2

PEG_RX1

PEG_RX0

PEG_RX10*

PEG_RX9*

PEG_RX8*

PEG_RX7*

PEG_RX6*

PEG_RX5*

PEG_RX4*

PEG_RX3*

PEG_RX2*

PEG_RX1*

PEG_RX0*

PEG_COMPI PEG_COMPO

CRT_DDC_DATA

L_CTRL_DATA

LVDSB_DATA1 LVDSB_DATA2

LVDSB_DATA0

LVDSB_DATA2*

LVDSB_DATA1*

LVDSB_DATA0*

LVDSA_DATA2

LVDSA_DATA0 LVDSA_DATA1

LVDSB_CLK*

LVDS_VREFL

LVDS_IBG

TVC_RTN

TVA_RTN TVB_RTN

TVC_DAC

TVB_DAC

TVA_DAC

CRT_RED*

CRT_RED

CRT_GREEN*

CRT_GREEN

CRT_BLUE*

CRT_BLUE

CRT_VSYNC

CRT_TVO_IREF

CRT_HSYNC

CRT_DDC_CLK

L_BKLT_EN

L_DDC_CLK

TV_DCONSEL0 TV_DCONSEL1

LVDSA_DATA2*

L_DDC_DATA

LVDSA_DATA1*

LVDSA_DATA0*

LVDSB_CLK

LVDSA_CLK

LVDSA_CLK*

LVDS_VREFH

L_CTRL_CLK

LVDS_VBG

VGA

TV

LVDS

(3 OF 10)

PCI-EXPRESS GRAPHICS

BI

OUT

IN

IN IN

IN

IN IN IN IN IN

IN

OUT

IN

OUT

IN

OUT

IN

OUT

OUT OUT

IN

BI BI

OUT OUT OUT OUT

OUT OUT

IN

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT OUT

OUT

BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

recommendation is to float both signals, see Radar #5067636.

a glitch during wake-up on LVDS DATA/CLK pairs. New

Note: SR DG says to tie LVDS_VREFH/L to GND. This causes

If SDVO is used, VCCD_LVDS must remain powered with proper

should connect to GND through 75-ohm resistors.

omit filtering components. Unused DAC outputs

Unused DAC outputs must remain powered, but can

Can leave all signals NC if LVDS is not implemented.

decoupling. Otherwise, tie VCCD_LVDS to GND also.

Tie VCC_TX_LVDS and VCCA_LVDS to GND.

SDVO_FLDSTALL#

SDVO Alternate Function

SDVO_TVCLKIN# SDVO_INT#

SDVO_TVCLKIN SDVO_INT SDVO_FLDSTALL

SDVOB_GREEN

SDVOB_RED

SDVOC_CLKN

SDVOC_BLUE#

SDVOC_GREEN#

SDVOC_RED#

SDVOB_CLKN

SDVOB_BLUE#

SDVOB_GREEN#

SDVOB_RED#

SDVOB_CLKP

SDVOB_BLUE

SDVOC_CLKP

SDVOC_BLUE

SDVOC_GREEN

SDVOC_RED

LVDS Disable

TVDAC rails. VCCA_TVx_DAC and VCCA_DAC_BG can

Component: DACA, DACB & DACC

Composite: DACA only

TV-Out Signal Usage:

Can tie the following rails to GND:

VSYNC and CRT_TVO_IREF to GND.

CRT Disable / TV-Out Enable

TV-Out Disable / CRT Enable Tie TVx_DAC and TVx_RTN to GND. Must power all

Leave GFX_VID<3..0> and GFX_VR_EN as NC.

Tie VCC_AXG and VCC_AXG_NCTF to GND.

Tie VCCA_DPLLA and VCCA_DPLLB to VCC (VCore).

Tie DPLL_REF_CLK and DPLL_REF_SSCLK to GND.

Can also tie CRT_DDC_*, L_CTRL_*, L_DDC_*, SDVO_CTRL_* and TV_DCONSELx to GND.

Follow instructions for LVDS and CRT & TV-Out Disable above.

Internal Graphics Disable

and filtered at all times!

NOTE: Must keep VDDC_TVDAC powered

VCCD_CRT, VCCD_QDAC and VCC_SYNC.

VCCA_CRT_DAC, VCCA_DAC_BG, VCCA_TVx_DAC,

All CRT/TVDAC rails must be powered. All

CRT & TV-Out Disable Tie TVx_DAC, TVx_RTN, R/R#/G/G#/B/B#, HSYNC,

Tie R/R#/G/G#/B/B#, HSYNC and VSYNC to GND.

share filtering with VCCA_CRT_DAC.

S-Video: DACB & DACC only

Tie DPLL_REF_CLK* and DPLL_REF_SSCLK* to VCC (VCore).

rails must be filtered except for VCCA_CRT.

67 84

402

MF-LF

1/16W

1%

24.9

R1510

1

2

22

67 84

22 84

OMIT

CRESTLINE

FCBGA

U1400

H32 G32

K33 G35

K29 J29

F33

F29 E29

C32 E33

J40 H39 E39 E40 C37 D35 K40

L41 L43 N41 N40

C45

D46

G50

G51

E50

E51

F48

F49

E42

D44

E44

G44

A47

B47

A45

B45

N43 M43

J50

J51

L50

L51

AC45

AD44

AC41

AD40

AH47

AG46

AG49

AH49

AH45

AG45

AG42

AG41

M47

N47

U44

T45

T49

T50

T41

U40

W45

Y44

W41

Y40

AB50

AB51

Y48

W49

M45

N45

T38

U39

AD47

AC46

AC50

AC49

AD43

AC42

AG39

AH39

AE50

AE49

AH43

AH44

T46

U47

N50

N51

R51

R50

U43

T42

W42

Y43

Y47

W46

Y39

W38

AC38

AD39

M35 P33

E27

F27

G27

J27

K27

L27

67 84

22

67 84

22 84

22

22 84

67 84

22 84

22

22 84

22

22 84

22

22 84

67 84

SYNC_DATE=03/19/2007

15 92

A.0.0

051-7431

NB PEG / Video Interfaces

SYNC_MASTER=T9_NOME

GND

LVDS_B_DATA_N<2>

LVDS_B_DATA_N<1>

GND

NC_LVDS_VBG

PEG_D2R_P<9>

PEG_D2R_P<11>

PEG_D2R_P<10>

PP1V05_S0_NB_VCCPEG

PEG_D2R_N<1>

PEG_D2R_N<6>

NC_LVDS_VREFH

NC_LVDS_A_CLKN NC_LVDS_A_CLKP

NC_LVDS_B_CLKP

NC_LVDS_A_DATAN<0> LVDS_A_DATA_N<1>

GND

LVDS_A_DATA_N<2>

GND

NC_LVDS_BKLT_EN

GND

GND GND GND

GND GND GND GND GND GND

GND

NC_LVDS_IBG

NC_LVDS_VREFL

NC_LVDS_B_CLKN

LVDS_A_DATA_P<1>

NC_LVDS_A_DATAP<0>

LVDS_A_DATA_P<2>

NC_LVDS_B_DATAN<0>

NC_LVDS_B_DATAP<0>

LVDS_B_DATA_P<2>

LVDS_B_DATA_P<1>

GND

PEG_COMP

PEG_D2R_N<0>

PEG_D2R_N<2> PEG_D2R_N<3> PEG_D2R_N<4> PEG_D2R_N<5>

PEG_D2R_N<7> PEG_D2R_N<8> PEG_D2R_N<9> PEG_D2R_N<10>

PEG_D2R_P<0> PEG_D2R_P<1> PEG_D2R_P<2> PEG_D2R_P<3> PEG_D2R_P<4> PEG_D2R_P<5> PEG_D2R_P<6> PEG_D2R_P<7> PEG_D2R_P<8>

PEG_D2R_P<12> PEG_D2R_P<13>

PEG_D2R_P<15>

PEG_D2R_N<11> PEG_D2R_N<12> PEG_D2R_N<13> PEG_D2R_N<14> PEG_D2R_N<15>

PEG_D2R_P<14>

PEG_R2D_C_P<0> PEG_R2D_C_P<1> PEG_R2D_C_P<2> PEG_R2D_C_P<3> PEG_R2D_C_P<4> PEG_R2D_C_P<5> PEG_R2D_C_P<6> PEG_R2D_C_P<7> PEG_R2D_C_P<8> PEG_R2D_C_P<9> PEG_R2D_C_P<10> PEG_R2D_C_P<11> PEG_R2D_C_P<12> PEG_R2D_C_P<13> PEG_R2D_C_P<14> PEG_R2D_C_P<15>

PEG_R2D_C_N<0> PEG_R2D_C_N<1> PEG_R2D_C_N<2> PEG_R2D_C_N<3> PEG_R2D_C_N<4> PEG_R2D_C_N<5> PEG_R2D_C_N<6> PEG_R2D_C_N<7> PEG_R2D_C_N<8> PEG_R2D_C_N<9> PEG_R2D_C_N<10> PEG_R2D_C_N<11> PEG_R2D_C_N<12> PEG_R2D_C_N<13> PEG_R2D_C_N<14> PEG_R2D_C_N<15>

NC_LVDS_VDD_EN

NC_LVDS_BKLT_CTL

21

22

19

22

IN

CLKREQ*

NC1

NC8

CL_CLK

CL_PWROK

CL_RST*

RSVD6

THERMTRIP*

PM_BM_BUSY*

RSVD4

RSVD3

RSVD7

SM_CKE1

SM_CK0*

SM_CKE0

SM_ODT0

SM_ODT2

SM_RCOMP

SM_RCOMP*

SM_VREF0 SM_VREF1

SM_RCOMP_VOL

SM_CS1*

SM_CS0*

RSVD14

RSVD11

RSVD10

RSVD9

RSVD5

RSVD8

RSVD2

DPLL_REF_CLK*

DPLL_REF_SSCLK

PEG_CLK

DMI_RXN1

DMI_RXN0

DMI_RXN3

DMI_RXN2

DMI_RXP0 DMI_RXP1 DMI_RXP2

DMI_TXN0

DMI_RXP3

DMI_TXN2

DMI_TXN1

DMI_TXP0

DMI_TXN3

DMI_TXP1 DMI_TXP2 DMI_TXP3

PEG_CLK*

RSVD12

CL_DATA

CL_VREF

SDVO_CTRL_CLK

SDVO_CTRL_DATA

ICH_SYNC*

TEST1 TEST2

GFX_VID0 GFX_VID1 GFX_VID2

GFX_VR_EN

GFX_VID3

RSVD20 RSVD21

RSVD24 RSVD25

RSVD27

RSVD34 RSVD35 RSVD36 RSVD37 RSVD38 RSVD39

RSVD41 RSVD42

RSVD40

RSVD43 RSVD44 RSVD45

CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13

CFG16

CFG15

CFG14

CFG17 CFG18 CFG19 CFG20

PM_DPRSTP* PM_EXT_TS0*

PWROK

PM_EXT_TS1*

RSTIN*

DPRSLPVR

NC2

NC4

NC3

NC5

NC7

NC6

NC10

NC9

NC12

NC11

NC13 NC14 NC15 NC16

DPLL_REF_CLK

SM_RCOMP_VOH

SM_ODT3

SM_ODT1

RSVD13

SM_CS2* SM_CS3*

SM_CK3 SM_CK4

SM_CK4*

SM_CKE3

RSVD1

SM_CKE4

DPLL_REF_SSCLK*

SM_CK3*

SM_CK1*

SM_CK1

SM_CK0

SA_MA14

RSVD22 RSVD23

RSVD26

SB_MA14

SM_CK2 SM_CK2* SM_CK5 SM_CK5*

(2 OF 10)

RSVD

DDR MUXING

CLK

CFG

DMI

PM

GRAPHICS VID

ME

MISC

NC

OUT OUT OUT OUT OUT

BI BI

IN

OUT

BI

BI OUT OUT

IN

OUT

OUT OUT

IN IN IN OUT

OUT OUT OUT

BI

OUT

BI

OUT

IN

OUT

OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT

IN

IN IN

IN

IN IN IN IN

IN IN

IN

OUT

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NB CFG<8:0> used for debug access

IPU IPU

NB_CFG<4> NB_CFG<5>

DMI x2 Select

NOTE: GMCH CL_PWROK input must be PWRGD signal for PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

If ME/AMT is not used, short CL_PWROK to PWROK.

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

NB_CFG<18>

NB_CFG<15>

FSB Dynamic ODT

NB_CFG<17>

NB_CFG<14>

NB_CFG<16>

NB_CFG<11> NB_CFG<12> NB_CFG<13>

DMI Lane Reversal

SDVO/PCIe x1

Concurrent

NB_CFG<20>

NB_CFG<19>

00 = RESERVED

or PCIe x16

11 = Normal Operation

High = Reversed

Low = Only SDVO

NB_CFG<13:12>

High = Both active

Low = Normal

01 = XOR Mode Enabled 10 = All-Z Mode Enabled

High = Enabled Low = Disabled

See Below See Below

RESERVED

Lane Reversal

PCIe Graphics

NB_CFG<9>

NB_CFG<10>

Low = Reversed

High = Normal

RESERVED

NB_CFG<7>

High = DMIx4

NB_CFG<6>

RESERVED

IPU

Clk used for PEG and DMI

IPD IPD

IPD

IPU

NB_CFG<8>

NB_CFG<3>

Low = DMIx2

RESERVED

IPU

NB CFG<13:12> require ICT access

7

28

8

16 31 32 62

402

CERM

20%

0.1uF

10V

C1616

1

2

402

CERM

20%

0.1uF

10V

C1615

1

2

CRESTLINE

FCBGA

OMIT

U1400

P27 N27

R24 L23 J23 E23 E20 K23 M20 M24 L32 N33

N24

L35

C21 C23 F23 N23 G23 J20 C20

AM49 AK50 AT43 AN49 AM50

G39

AN47 AJ38 AN42 AN46

AM47 AJ39 AN41 AN45

AJ46 AJ41 AM40 AM44

AJ47 AJ42 AM39 AM43

B42 C42 H48 H47

G36

E35 A39 C38 B39 E36

G40

BJ51

E1

A5 C51 B50 A50 A49 BK2

BK51 BK50 BL50 BL49

BL3 BL2 BK1 BJ1

K44 K45

G41 L39 L36 J36

AW49 AV20

P36

AR37 AM36 AL36 AM37

D20

P37

H10 B51

BJ20 BK22 BF19 BH20 BK18 BJ18

R35

BH39 AW20 BK20

C48 D47 B44

N35

C44 A35 B37 B36 B34 C34

AR12 AR13 AM12 AN13

J12

BJ29 BE24

H35 K36

AV29

AW30

BB23

BA23

BF23 BG23

BA25

AW25

AV23

AW23

BC23 BD24

BE29 AY32 BD39 BG37

BG20 BK16 BG16 BE13

BH18 BJ15 BJ14 BE16

BL15 BK14

BK31 BL31

AR49 AW4

A37 R32

N20

22

25 87

7 9

16 28 59

25 87

7

29

7

25

402

20K

MF-LF

1/16W

5%

R1691

1

2

402

0

MF-LF

1/16W

5%

R1690

1

2

7

25 59 83

32 45

402

10K

MF-LF

5% 1/16W

R1631

1

2

0.01UF

10% 16V

CERM

402

C1625

1

2

603

2.2UF

6.3V CERM1

20%

C1624

1

2

1K

MF-LF

1% 1/16W

402

R1624

1

2

402

1% 1/16W MF-LF

3.01K

R1622

1

2

603

6.3V CERM1

2.2UF

20%

C1622

1

2

0.01UF

10% 16V

CERM

402

C1623

1

2

1K

402

1/16W

1% MF-LF

R1620

1

2

402

392

MF-LF

1/16W

1%

R1641

1

2

402

MF-LF

1/16W

1K

1%

R1640

1

2

402

20% 10V

CERM

0.1uF

C1640

1

2

402

5%

3.9K

MF-LF

1/16W

NBCFG_DMI_X2

R1655

1

2

402

5% 1/16W MF-LF

3.9K

NBCFG_PEG_REVERSE

R1659

1

2

402

NBCFG_DYN_ODT_DISABLE

3.9K

1/16W

5% MF-LF

R1666

1

2

402

3.9K

MF-LF

1/16W

5%

NBCFG_DMI_REVERSE

R1669

1

2

402

5% 1/16W MF-LF

3.9K

NBCFG_SDVO_AND_PCIE

R1670

1

2

31 33 85

32 33 85

13 30 83

13

13 16

7

25

13

10 23 46 83

31 45

7

10 23 59 83

7 9

16 28 59

31 85

32 85

31 85

32 85

31 85

31 33 85

32 33 85

31 33 85

32 33 85

31 33 85

32 33 85

31 33 85

32 33 85

MF-LF

1/16W

1%

20

402

R1610

1

2

1/16W

1%

MF-LF

20

402

R1611

1

2

8

16 31 32 62

7

29 30 88

7

29 30 88

24 84

402

MF-LF

1/16W

5%

10K

R1630

1

2

051-7431

A.0.0

9216

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

NB Misc Interfaces

TP_LVDS_A_DATAP3

TP_NB_RSVD<34>

MEM_B_A<14>

NC_NB_RSVD<27>

NC_NB_RSVD<26>

TP_NB_RSVD<25>

GND GND

NB_BSEL<0>

NB_CFG<5>

MEM_CKE<4>

TP_NB_RSVD<1>

MEM_CLK_P<0>

MEM_CLK_N<4>

MEM_CLK_N<3>

MEM_CLK_P<4>

MEM_CLK_P<3>

TP_NB_RSVD<13>

TP_NB_NC<16>

TP_NB_NC<15>

TP_NB_NC<14>

TP_NB_NC<13>

TP_NB_NC<11> TP_NB_NC<12>

TP_NB_NC<9> TP_NB_NC<10>

TP_NB_NC<6> TP_NB_NC<7>

TP_NB_NC<5>

TP_NB_NC<3>

TP_NB_NC<2>

PM_EXTTS_L<0>

NB_CFG<20>

NB_CFG<19>

TP_NB_CFG<18>

TP_NB_CFG<14> TP_NB_CFG<15> NB_CFG<16>

TP_NB_CFG<12>

TP_NB_CFG<10>

TP_NB_RSVD<41>

TP_NB_RSVD<23>

TP_NB_RSVD<22>

TP_NB_RSVD<21>

TP_NB_RSVD<20>

NB_TEST2

NB_TEST1

TP_NB_RSVD<2>

TP_NB_RSVD<8> TP_NB_RSVD<9> TP_NB_RSVD<10> TP_NB_RSVD<11>

MEM_CS_L<0> MEM_CS_L<1>

MEM_CKE<0>

MEM_CLK_N<1>

MEM_CLK_P<1>

MEM_CLK_N<0>

TP_NB_RSVD<7>

TP_NB_RSVD<3> TP_NB_RSVD<4>

TP_NB_NC<8>

TP_NB_NC<1>

GND

NB_CLK100M_PCIE_P NB_CLK100M_PCIE_N

DMI_S2N_P<0> DMI_S2N_P<1> DMI_S2N_P<2>

DMI_N2S_N<0> DMI_N2S_N<1>

DMI_N2S_N<3>

DMI_N2S_N<2>

DMI_N2S_P<0> DMI_N2S_P<1> DMI_N2S_P<2> DMI_N2S_P<3>

GFX_VID<2>

CLINK_NB_DATA VR_PWRGOOD_DELAY CLINK_NB_RESET_L

GND GND NB_CLKREQ_L NB_SB_SYNC_L

TP_MEM_CLKN2 TP_MEM_CLKP5 TP_MEM_CLKN5

PM_BMBUSY_L CPU_DPRSTP_L

VR_PWRGOOD_DELAY

PM_THRMTRIP_L

MEM_CS_L<2>

MEM_ODT<2> MEM_ODT<3>

GND

MEM_CS_L<3> MEM_ODT<0>

MEM_ODT<1>

TP_NB_RSVD<6>

TP_NB_RSVD<12>

TP_NB_NC<4>

GFX_VID<4>

DMI_S2N_P<3>

DMI_S2N_N<2>

PP0V9_S3_MEM_VREF

TP_NB_RSVD<5>

TP_NB_RSVD<24>

TP_MEM_CLKP2

TP_LVDS_A_DATAN3

TP_LVDS_B_DATAP3

MEM_A_A<14>

DMI_S2N_N<0>

TP_NB_RSVD<35> TP_NB_RSVD<36>

TP_LVDS_B_DATAN3

TP_NB_RSVD<45>

TP_NB_RSVD<42>

DMI_S2N_N<3>

DMI_S2N_N<1>

TP_NB_RSVD<14>

PM_DPRSLPVR

NB_RESET_L

PM_EXTTS_L<1>

NB_CFG<9>

NB_CFG<16>

PP3V3_S0

NB_CFG<19>

NB_CFG<20>

PP3V3_S0

TP_NB_CFG<11>

TP_NB_CFG<13>

GFX_VID<3>

TP_GFX_VR_EN

PP3V3_S0

TP_NB_CFG<17>

TP_GFX_VID<1>

CLINK_NB_CLK

PP1V25_S0M_NB_VCCAXD

NB_CLINK_VREF

NB_BSEL<2>

NB_BSEL<1>

NB_CFG<3>

NB_CFG<6> NB_CFG<7> NB_CFG<8> NB_CFG<9>

NB_CFG<5>

MEM_RCOMP_L

TP_NB_RSVD<43> TP_NB_RSVD<44>

NB_CFG<4>

MEM_CKE<1> MEM_CKE<3>

PP0V9_S3_MEM_VREF

MEM_RCOMP_VOL

MEM_RCOMP

PP1V8_S3_ISNS

MEM_RCOMP_VOH

GND

91

82

65

59

58

53

52

51

50

48

47

46

42

32

31

30

29

28

27

26

25

24

23

21

19

50

16

21

16

13

21

18

7

13

7

16

7

16

8

16

8

19

87

16

8

BI

BI BI BI BI BI

OUT

BI

OUT

BI BI BI

BI

BI BI BI BI

BI BI

BI BI BI BI BI

BI BI BI

BI

BI BI BI

BI

BI BI BI BI

BI

BI BI BI BI BI

BI BI

BI

OUT

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

BI

OUT

BI

BI BI BI

BI

BI BI BI

BI BI

BI

BI BI

OUT

BI

OUT OUT

OUT

BI

OUT

SA_DQ0 SA_DQ1 SA_DQ2

SA_DQ4

SA_DQ6

SA_DQ14

SA_CAS*

SA_BS2

SA_DQ63

SA_DQ62

SA_DQ61

SA_DQ60

SA_DQ59

SA_DQ58

SA_DQ57

SA_DQ56

SA_DQ55

SA_DQ54

SA_DQ53

SA_DQ52

SA_DQ51

SA_DQ50

SA_DQ49

SA_DQ48

SA_DQ47

SA_DQ46

SA_DQ44

SA_DQ43

SA_DQ42

SA_DQ41

SA_DQ40

SA_DQ39

SA_DQ38

SA_DQ37

SA_DQ36

SA_DQ34 SA_DQ35

SA_DQ33

SA_DQ32

SA_DQ31

SA_DQ30

SA_DQ28 SA_DQ29

SA_DQ27

SA_DQ26

SA_DQ25

SA_DQ24

SA_DQ23

SA_DQ22

SA_DQ21

SA_DQ20

SA_DQ19

SA_DQ18

SA_DQ17

SA_DQ16

SA_DQ15

SA_DQ13

SA_DQ11 SA_DQ12

SA_DQ10

SA_DQ9

SA_DQ8

SA_DQ7

SA_DQ5

SA_DQ3

SA_BS1

SA_BS0

SA_DQ45

SA_DM0 SA_DM1

SA_DM3

SA_DM2

SA_DM5

SA_DM4

SA_DM7

SA_DM6

SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7

SA_DQS1*

SA_DQS0*

SA_DQS2*

SA_DQS4*

SA_DQS3*

SA_DQS5* SA_DQS6* SA_DQS7*

SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7

SA_MA9

SA_MA8

SA_MA10 SA_MA11 SA_MA12 SA_MA13

SA_RAS*

SA_RCVEN*

SA_WE*

DDR SYSTEM MEMORY A

(4 OF 10)

SB_DQ2

SB_DQ1

SB_DQ5

SB_DM0

SB_DQ0

SB_DQ4

SB_DQ6 SB_DQ7

SB_CAS*

SB_BS2

SB_BS0 SB_BS1

SB_DQ63

SB_DQ62

SB_DQ59

SB_DQ58

SB_DQ56

SB_DQ55

SB_DQ54

SB_DQ53

SB_DQ52

SB_DQ51

SB_DQ50

SB_DQ49

SB_DQ48

SB_DQ47

SB_DQ45 SB_DQ46

SB_DQ44

SB_DQ43

SB_DQ42

SB_DQ41

SB_DQ40

SB_DQ39

SB_DQ38

SB_DQ37

SB_DQ36

SB_DQ34 SB_DQ35

SB_DQ33

SB_DQ32

SB_DQ31

SB_DQ30

SB_DQ28 SB_DQ29

SB_DQ27

SB_DQ26

SB_DQ25

SB_DQ24

SB_DQ23

SB_DQ22

SB_DQ21

SB_DQ20

SB_DQ19

SB_DQ18

SB_DQ17

SB_DQ16

SB_DQ15

SB_DQ14

SB_DQ13

SB_DQ11 SB_DQ12

SB_DQ10

SB_DQ9

SB_DQ8

SB_DQ3

SB_DQ57

SB_DQ61

SB_DQ60

SB_WE*

SB_RCVEN*

SB_RAS*

SB_MA13

SB_MA12

SB_MA11

SB_MA10

SB_MA8 SB_MA9

SB_MA7

SB_MA6

SB_MA5

SB_MA4

SB_MA3

SB_MA2

SB_MA1

SB_MA0

SB_DQS7*

SB_DQS6*

SB_DQS5*

SB_DQS3* SB_DQS4*

SB_DQS2*

SB_DQS0* SB_DQS1*

SB_DQS7

SB_DQS6

SB_DQS5

SB_DQS4

SB_DQS3

SB_DQS2

SB_DQS1

SB_DQS0

SB_DM6 SB_DM7

SB_DM4 SB_DM5

SB_DM2 SB_DM3

SB_DM1

(5 OF 10)

DDR SYSTEM MEMORY B

BI

OUT OUT OUT

BI

OUT

BI

OUT

BI

BI BI BI BI BI BI BI BI BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

31 85

32 85

31 85 32 85

32 85

31 85

32 85

31 85

32 85

31 85

32 85

31 85

32 85

31 85

32 85

32 33 85

31 85

32 33 85

31 85

32 33 85

32 85

31 85

32 85

31 85

32 85

32 33 85

31 85

32 33 85

FCBGA

CRESTLINE

OMIT

U1400

BB19 BK19 BF29

BL17

AT45 BD44 BD42 AW38 AW13 BG8 AY5 AN6

AR43 AW44

BG47 BJ45 BB47 BG50 BH49 BE45 AW43 BE44 BG42 BE40

BA45

BF44 BH45 BG40 BF40 AR40 AW40 AT39 AW36 AW41 AY41

AY46

AV38 AT38 AV13 AT13 AW11 AV11 AU15 AT11 BA13 BA11

AR41

BE10 BD10

BD8 AY9

BG10

AW9 BD7 BB9 BB5 AY7

AR45

AT5 AT7 AY6 BB7 AR5 AR8 AR9 AN3 AM8

AN10

AT42

AT9 AN9 AM9

AN11

AW47 BB45 BF48

AT46

AT47

BE48

BD47

BB43

BC41

BC37

BA37

BB16

BA16

BH6

BH7

BB2

BC1

AP3

AP2

BJ19 BD20

BC19 BE28 BG30 BJ16

BK27 BH28 BL24 BK28 BJ27 BJ25 BL28 BA28

BE18 AY20

BA19

FCBGA

CRESTLINE

OMIT

U1400

AY17 BG18 BG36

BE17

AR50 BD49 BK45 BL39 BH12 BJ7 BF3 AW2

AP49 AR51

BA49 BE50 BA51 AY49 BF50 BF49 BJ50 BJ44 BJ43 BL43

AW50

BK47 BK49 BK43 BK42 BJ41 BL41 BJ37 BJ36 BK41 BJ40

AW51

BL35 BK37 BK13 BE11 BK11 BC11 BC13 BE12 BC12 BG12

AN51

BJ10

BL9 BK5 BL5 BK9

BK10

BJ8 BJ6 BF4 BH5

AN50

BG1 BC2 BK3 BE4 BD3 BJ2 BA3 BB3 AR1 AT3

AV50

AY2 AY3 AU2 AT2

AV49 BA50 BB50

AT50

AU50

BD50

BC50

BK46

BL45

BK39

BK38

BJ12

BK12

BL7

BK7

BE2

BF2

AV2

AV3

BC18 BG28

BG17 BE37 BA39 BG13

BG25 AW17 BF25 BE25 BA29 BC28 AY28 BD37

AV16 AY18

BC17

31 85

31 33 85

31 85

31 33 85

31 85

31 33 85

31 85

31 33 85

31 85

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

NB DDR2 Interfaces

051-7431

A.0.0

9217

MEM_A_DQ<35>

TP_MEM_A_RCVEN_L TP_MEM_B_RCVEN_L

MEM_B_DQ<39>

MEM_B_BS<0> MEM_B_BS<1> MEM_B_BS<2>

MEM_B_DM<0>

MEM_B_CAS_L

MEM_B_DM<1> MEM_B_DM<2>

MEM_B_DQ<0> MEM_B_DQ<1> MEM_B_DQ<2> MEM_B_DQ<3> MEM_B_DQ<4> MEM_B_DQ<5> MEM_B_DQ<6> MEM_B_DQ<7> MEM_B_DQ<8>

MEM_B_DM<3> MEM_B_DM<4> MEM_B_DM<5> MEM_B_DM<6> MEM_B_DM<7>

MEM_B_DQS_P<1>

MEM_B_DQS_P<0>

MEM_B_DQS_P<4>

MEM_B_DQS_P<3>

MEM_B_DQS_P<2>

MEM_B_DQS_P<6>

MEM_B_DQS_P<5>

MEM_B_DQS_N<1>

MEM_B_DQS_P<7> MEM_B_DQS_N<0>

MEM_B_DQS_N<3>

MEM_B_DQS_N<2>

MEM_B_DQS_N<4>

MEM_B_DQS_N<6>

MEM_B_DQS_N<5>

MEM_B_DQS_N<7>

MEM_B_A<0> MEM_B_A<1> MEM_B_A<2> MEM_B_A<3> MEM_B_A<4> MEM_B_A<5> MEM_B_A<6> MEM_B_A<7> MEM_B_A<8> MEM_B_A<9> MEM_B_A<10> MEM_B_A<11> MEM_B_A<12>

MEM_B_RAS_L

MEM_B_A<13>

MEM_B_WE_L

MEM_B_DQ<9> MEM_B_DQ<10> MEM_B_DQ<11> MEM_B_DQ<12> MEM_B_DQ<13> MEM_B_DQ<14> MEM_B_DQ<15> MEM_B_DQ<16> MEM_B_DQ<17> MEM_B_DQ<18> MEM_B_DQ<19> MEM_B_DQ<20> MEM_B_DQ<21> MEM_B_DQ<22> MEM_B_DQ<23> MEM_B_DQ<24> MEM_B_DQ<25> MEM_B_DQ<26> MEM_B_DQ<27> MEM_B_DQ<28> MEM_B_DQ<29> MEM_B_DQ<30> MEM_B_DQ<31> MEM_B_DQ<32> MEM_B_DQ<33> MEM_B_DQ<34> MEM_B_DQ<35> MEM_B_DQ<36> MEM_B_DQ<37> MEM_B_DQ<38>

MEM_B_DQ<40> MEM_B_DQ<41> MEM_B_DQ<42> MEM_B_DQ<43> MEM_B_DQ<44> MEM_B_DQ<45> MEM_B_DQ<46> MEM_B_DQ<47> MEM_B_DQ<48> MEM_B_DQ<49> MEM_B_DQ<50> MEM_B_DQ<51> MEM_B_DQ<52> MEM_B_DQ<53> MEM_B_DQ<54> MEM_B_DQ<55> MEM_B_DQ<56> MEM_B_DQ<57> MEM_B_DQ<58> MEM_B_DQ<59> MEM_B_DQ<60> MEM_B_DQ<61> MEM_B_DQ<62> MEM_B_DQ<63>

MEM_A_DQ<0> MEM_A_DQ<1> MEM_A_DQ<2>

MEM_A_DQ<4>

MEM_A_DQ<6>

MEM_A_CAS_L

MEM_A_BS<2>

MEM_A_DQ<8>

MEM_A_DQ<7>

MEM_A_DQ<5>

MEM_A_DQ<3>

MEM_A_BS<1>

MEM_A_BS<0>

MEM_A_DM<0> MEM_A_DM<1>

MEM_A_DM<3>

MEM_A_DM<2>

MEM_A_DM<5>

MEM_A_DM<4>

MEM_A_DM<7>

MEM_A_DM<6>

MEM_A_DQS_P<0> MEM_A_DQS_P<1> MEM_A_DQS_P<2> MEM_A_DQS_P<3> MEM_A_DQS_P<4> MEM_A_DQS_P<5> MEM_A_DQS_P<6> MEM_A_DQS_P<7>

MEM_A_DQS_N<1>

MEM_A_DQS_N<0>

MEM_A_DQS_N<2>

MEM_A_DQS_N<4>

MEM_A_DQS_N<3>

MEM_A_DQS_N<5> MEM_A_DQS_N<6> MEM_A_DQS_N<7>

MEM_A_A<0> MEM_A_A<1> MEM_A_A<2> MEM_A_A<3> MEM_A_A<4> MEM_A_A<5> MEM_A_A<6> MEM_A_A<7>

MEM_A_A<9>

MEM_A_A<8>

MEM_A_A<10> MEM_A_A<11> MEM_A_A<12> MEM_A_A<13>

MEM_A_RAS_L

MEM_A_WE_L

MEM_A_DQ<9> MEM_A_DQ<10> MEM_A_DQ<11> MEM_A_DQ<12> MEM_A_DQ<13> MEM_A_DQ<14> MEM_A_DQ<15> MEM_A_DQ<16> MEM_A_DQ<17> MEM_A_DQ<18> MEM_A_DQ<19> MEM_A_DQ<20> MEM_A_DQ<21> MEM_A_DQ<22> MEM_A_DQ<23> MEM_A_DQ<24> MEM_A_DQ<25> MEM_A_DQ<26> MEM_A_DQ<27> MEM_A_DQ<28> MEM_A_DQ<29> MEM_A_DQ<30> MEM_A_DQ<31> MEM_A_DQ<32> MEM_A_DQ<33> MEM_A_DQ<34>

MEM_A_DQ<36> MEM_A_DQ<37> MEM_A_DQ<38> MEM_A_DQ<39> MEM_A_DQ<40> MEM_A_DQ<41> MEM_A_DQ<42> MEM_A_DQ<43> MEM_A_DQ<44> MEM_A_DQ<45> MEM_A_DQ<46> MEM_A_DQ<47> MEM_A_DQ<48> MEM_A_DQ<49> MEM_A_DQ<50> MEM_A_DQ<51> MEM_A_DQ<52> MEM_A_DQ<53> MEM_A_DQ<54> MEM_A_DQ<55> MEM_A_DQ<56> MEM_A_DQ<57> MEM_A_DQ<58> MEM_A_DQ<59> MEM_A_DQ<60> MEM_A_DQ<61> MEM_A_DQ<62> MEM_A_DQ<63>

VCC_SM20

VCC_AXG_NCTF42

VCC_SM9 VCC_SM10

VCC_SM17

VCC_SM16

VCC3

VCC_SM5

VCC_SM8

VCC_AXG_NCTF1 VCC_AXG_NCTF2 VCC_AXG_NCTF3 VCC_AXG_NCTF4 VCC_AXG_NCTF5 VCC_AXG_NCTF6

VCC_AXG_NCTF8

VCC_AXG_NCTF7

VCC_AXG_NCTF10

VCC_AXG_NCTF9

VCC_AXG_NCTF11 VCC_AXG_NCTF12 VCC_AXG_NCTF13 VCC_AXG_NCTF14 VCC_AXG_NCTF15 VCC_AXG_NCTF16

VCC_AXG_NCTF18

VCC_AXG_NCTF17

VCC_AXG_NCTF20

VCC_AXG_NCTF19

VCC_AXG_NCTF21 VCC_AXG_NCTF22

VCC_AXG_NCTF25 VCC_AXG_NCTF26

VCC_AXG_NCTF28

VCC_AXG_NCTF27

VCC_AXG_NCTF29 VCC_AXG_NCTF20 VCC_AXG_NCTF31 VCC_AXG_NCTF32 VCC_AXG_NCTF33 VCC_AXG_NCTF34 VCC_AXG_NCTF35 VCC_AXG_NCTF36

VCC_AXG_NCTF38

VCC_AXG_NCTF37

VCC_AXG_NCTF40

VCC_AXG_NCTF39

VCC_AXG_NCTF41

VCC_AXG_NCTF43 VCC_AXG_NCTF44 VCC_AXG_NCTF45 VCC_AXG_NCTF46

VCC_AXG_NCTF48

VCC_AXG_NCTF47

VCC_AXG_NCTF49 VCC_AXG_NCTF50 VCC_AXG_NCTF51

VCC_AXG_NCTF55

VCC_AXG_NCTF58

VCC_AXG_NCTF57

VCC_AXG_NCTF59

VCC_AXG_NCTF61

VCC_AXG_NCTF60

VCC_AXG_NCTF62 VCC_AXG_NCTF63 VCC_AXG_NCTF64

VCC_AXG_NCTF66

VCC_AXG_NCTF65

VCC_AXG_NCTF67 VCC_AXG_NCTF68 VCC_AXG_NCTF69

VCC_AXG_NCTF71

VCC_AXG_NCTF70

VCC_AXG_NCTF72 VCC_AXG_NCTF73 VCC_AXG_NCTF74

VCC_AXG_NCTF76

VCC_AXG_NCTF75

VCC_AXG_NCTF77 VCC_AXG_NCTF78 VCC_AXG_NCTF79

VCC_AXG_NCTF81

VCC_AXG_NCTF80

VCC_AXG_NCTF82 VCC_AXG_NCTF83

VCC_SM_LF1 VCC_SM_LF2 VCC_SM_LF3 VCC_SM_LF4 VCC_SM_LF5 VCC_SM_LF6 VCC_SM_LF7

VCC_AXG_NCTF56

VCC_AXG_NCTF54

VCC_AXG_NCTF53

VCC_AXG_NCTF52

VCC_AXG1 VCC_AXG2 VCC_AXG3 VCC_AXG4 VCC_AXG5 VCC_AXG6 VCC_AXG7 VCC_AXG8 VCC_AXG9 VCC_AXG10 VCC_AXG11 VCC_AXG12 VCC_AXG13 VCC_AXG14 VCC_AXG15 VCC_AXG16 VCC_AXG17 VCC_AXG18 VCC_AXG19 VCC_AXG20 VCC_AXG21 VCC_AXG22 VCC_AXG23 VCC_AXG24 VCC_AXG25 VCC_AXG26 VCC_AXG27 VCC_AXG28 VCC_AXG29 VCC_AXG30 VCC_AXG31 VCC_AXG32 VCC_AXG33 VCC_AXG34

VCC_SM1 VCC_SM2 VCC_SM3 VCC_SM4

VCC_SM6 VCC_SM7

VCC_SM11 VCC_SM12 VCC_SM13 VCC_SM14 VCC_SM15

VCC_SM18 VCC_SM19

VCC_SM21 VCC_SM22 VCC_SM23

VCC_SM26 VCC_SM27 VCC_SM28 VCC_SM29 VCC_SM30 VCC_SM31 VCC_SM32 VCC_SM33 VCC_SM34 VCC_SM35 VCC_SM36

VCC_SM25

VCC_SM24

VCC1 VCC2

VCC7 VCC8 VCC9 VCC10 VCC11 VCC12

VCC13

VCC_AXG_NCTF24

VCC_AXG_NCTF23

VCC6

VCC5 VCC4

VCC GFX

VCC SM

VCC SM LF

(6 OF 10)

VCC CORE

POWER

VCC GFX NCTF

VCC_NCTF49

VCC_NCTF15

VCC_NCTF2

VCC_NCTF10

VCC_AXM7

VCC_AXM5

VCC_AXM4

VCC_AXM3

VCC_AXM2

VCC_AXM1

VSS_SCB6

VSS_SCB5

VSS_SCB4

VSS_SCB3

VSS_SCB2

VSS_SCB1

VCC_NCTF11 VCC_NCTF12 VCC_NCTF13 VCC_NCTF14

VSS_NCTF21

VSS_NCTF20

VSS_NCTF19

VSS_NCTF18

VSS_NCTF17

VSS_NCTF16

VSS_NCTF15

VSS_NCTF14

VSS_NCTF12

VSS_NCTF11

VSS_NCTF13

VSS_NCTF10

VSS_NCTF9

VSS_NCTF8

VSS_NCTF7

VSS_NCTF6

VSS_NCTF5

VSS_NCTF4

VSS_NCTF3

VSS_NCTF2

VSS_NCTF1

VCC_NCTF22

VCC_NCTF27

VCC_NCTF50

VCC_NCTF47 VCC_NCTF48

VCC_NCTF44

VCC_NCTF43

VCC_NCTF39 VCC_NCTF40

VCC_NCTF38

VCC_NCTF37

VCC_NCTF34 VCC_NCTF35

VCC_NCTF33

VCC_NCTF32

VCC_NCTF31

VCC_NCTF29

VCC_NCTF28

VCC_NCTF26

VCC_NCTF24 VCC_NCTF25

VCC_NCTF23

VCC_NCTF21

VCC_NCTF18 VCC_NCTF19

VCC_NCTF16 VCC_NCTF17

VCC_NCTF3 VCC_NCTF4

VCC_NCTF41 VCC_NCTF42

VCC_NCTF45 VCC_NCTF46

VCC_AXM6

VCC_AXM_NCTF1 VCC_AXM_NCTF2 VCC_AXM_NCTF3 VCC_AXM_NCTF4 VCC_AXM_NCTF5 VCC_AXM_NCTF6 VCC_AXM_NCTF7 VCC_AXM_NCTF8 VCC_AXM_NCTF9 VCC_AXM_NCTF10 VCC_AXM_NCTF11 VCC_AXM_NCTF12 VCC_AXM_NCTF13 VCC_AXM_NCTF14 VCC_AXM_NCTF15 VCC_AXM_NCTF16 VCC_AXM_NCTF17 VCC_AXM_NCTF18 VCC_AXM_NCTF19

VCC_NCTF8

VCC_NCTF20

VCC_NCTF1

VCC_NCTF5 VCC_NCTF6 VCC_NCTF7

VCC_NCTF36

VCC_NCTF30

VCC_NCTF9

VCC AXM NCTF

VCC NCTF

VSS SCBVCC AXM

VSS NCTF

(7 OF 10)

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1395 mA (1 ch, 533MHz)

1700 mA (1 ch, 667MHz)

2700 mA (2 ch, 533MHz)

3300 mA (2 ch, 667MHz)

540 mA

1573 mA (Int Graphics)

1310 mA (Ext Graphics)

7700 mA (Int Graphics)

5 mA (standby)

impacting part performance.

These connections can break without

NCTF balls are Not Critical To Function

Current numbers from Crestline EDS, doc #21749.

FCBGA

CRESTLINE

OMIT

U1400

AT35

AH31 AH29 AF32

R30

AT34 AH28

AC31

AC32

AK32 AJ31 AJ28 AH32

R20

AB21 AB24 AB29 AC20 AC21 AC23 AC24 AC26 AC28 AC29

T14

AD20 AD23 AD24 AD28 AF21 AF26 AA31 AH20 AH21 AH23

W13

AH24 AH26 AD31 AJ20 AN14

W14

Y12 AA20 AA23 AA26 AA28

T17

U17 U19 U20 U21 U23 U26 V16 V17 V19 V20

T18

V21 V23 V24 Y15 Y16 Y17 Y19 Y20 Y21 Y23

T19

Y24 Y26 Y28 Y29 AA16 AA17 AB16 AB19 AC16 AC17

T21

AC19 AD15 AD16 AD17 AF16 AF19 AH15 AH16 AH17 AH19

T22

AJ16 AJ17 AJ19 AK16 AK19 AL16 AL17 AL19 AL20 AL21

T23

AL23 AM15 AM16 AM19 AM20 AM21 AM23 AP15 AP16 AP17

T25

AP19 AP20 AP21 AP23 AP24 AR20 AR21 AR23 AR24 AR26

U15

V26 V28 V29 Y31

U16

AU32

BA35 BB33 BC32 BC33 BC35 BD32 BD35 BE32 BE33 BE35

AU33

BF33 BF34 BG32 BG33 BG35 BH32 BH34 BH35 BJ32 BJ33

AU35

BJ34 BK32 BK33 BK34 BK35 BL33 AU30

AV33 AW33 AW35 AY35 BA32 BA33

AW45 BC39 BE39 BD17 BD4 AW8 AT6

FCBGA

CRESTLINE

OMIT

U1400

AT33 AT31 AK29 AK24 AK23 AJ26 AJ23

AL24

AP29 AP31 AP32 AP33 AL29 AL31 AL32 AR31 AR32 AR33

AL26 AL28 AM26 AM28 AM29 AM31 AM32 AM33

AB33

AF36 AH33 AH35 AH36 AH37 AJ33 AJ35 AK33 AK35 AK36

AB36

AK37 AD33 AJ36 AM35 AL33 AL35 AA33 AA35 AA36 AP35

AB37

AP36 AR35 AR36

Y32 Y33 Y35 Y36 Y37 T30 T34

AC33

T35 U29 U31 U32 U33 U35 U36 V32 V33 V36

AC35

V37

AC36 AD35 AD36 AF33

T27

AD19 AD37 AF17 AF35 AK17 AM17 AM24 AP26 AP28 AR15

T37

AR19 AR28

U24 U28 V31 V35 AA19 AB17 AB35

A3 B2 C1 BL1 BL51 A51

20%

CERM

10V

0.1uF

402

C1806

1

2

20%

CERM

10V

0.1uF

402

C1807

1

2

20%

6.3V

0.22UF

X5R 402

C1804

1

2

20%

6.3V

0.22UF

X5R 402

C1805

1

2

6.3V

1uF

CERM

10%

402

C1802

1

2

CERM-X5R

6.3V

0.47UF

10%

402

C1803

1

2

6.3V

1uF

CERM

10%

402

C1801

1

2

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

NB Power 1

051-7431

A.0.0

9218

PP1V05_S0

NB_VCCSM_LF5

NB_VCCSM_LF7

PPVCORE_S0_NB_R

PP1V05_S0

NB_VCCSM_LF1 NB_VCCSM_LF2 NB_VCCSM_LF3 NB_VCCSM_LF4

NB_VCCSM_LF6

GND

PPVCORE_S0_NB_R

GND

PP1V8_S3_ISNS

61

50

46

30

27

26

23

21

19

18

14

13

12

50

12

50

11

21

11

21

10

18

10

18

16

8

VCCA_CRT_DAC1

VTT7 VTT8

VCC_AXD_NCTF

VCCD_CRT

VCC_RXR_DMI1 VCC_RXR_DMI2

VTT1

VCCA_SM_CK2 VCC_TX_LVDS

VCC_HV2

VCC_PEG1 VCC_PEG2 VCC_PEG3

VCC_AXF2

VCC_AXD1 VCC_AXD2

VSSA_LVDS

VCCA_SM5

VCCA_PEG_PLL

VCCA_MPLL

VCCA_HPLL VTT16

VTT17

VTT15

VCCD_LVDS2

VCCD_LVDS1

VCCD_PEG_PLL

VCCD_HPLL

VCCD_QDAC

VCCD_TVDAC

VCCA_TVC_DAC1 VCCA_TVC_DAC2

VCCA_TVB_DAC2

VCCA_TVB_DAC1

VCCA_TVA_DAC2

VCCA_TVA_DAC1

VCCA_SM_CK1

VCCA_SM2

VCCA_SM1

VCCA_SM_NCTF2

VCCA_SM_NCTF1

VCCA_SM11

VCCA_SM10

VCCA_SM9

VCCA_SM8

VCCA_SM7

VCCA_SM4

VCCA_SM3

VSSA_PEG_BG

VCCA_PEG_BG

VCCA_LVDS

VCCA_DPLLB

VCCA_DPLLA

VSSA_DAC_BG

VCCA_DAC_BG

VCC_AXF3

VCC_HV1

VCC_PEG5

VTTLF1

VTTLF3

VTTLF2

VCC_PEG4

VCC_SM_CK3

VCC_SM_CK2

VCC_SM_CK1

VCC_SM_CK4

VCC_DMI

VCC_AXF1

VTT22

VCC_AXD6

VCC_AXD5

VCC_AXD4

VCC_AXD3

VTT19

VTT2

VTT6

VTT5

VTT11

VTT10

VTT9

VTT13

VTT12

VTT14

VTT18

VTT21

VTT20

VTT3 VTT4

VCCA_CRT_DAC2

VCC_SYNC

CRT

AXD

PEG

HV

AXF

VTTLF

VTT

SM CK

DMI

TV/CRT

D

LVDS

A SMA CK

CRT A LVDS

A PEG

PLL

(8 OF 10)

POWER

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

550 mA (533MHz DDR)

640 mA (667MHz DDR)

Current numbers from Crestline EDS, doc #21749.

515 mA

495 mA

850 mA @ 800MHz FSB (1.05V)

35 mA

100 mA

60 mA

30 mA

80 mA

0.4 mA

260 mA

1260 mA

770 mA @ 667MHz FSB (1.05V)

150 mA

TBD mA @ 1067MHz FSB (1.25V)

S0 or S3M is acceptable

5 mA

150 mA

250 mA

60 mA

40 mA

10 mA

100 mA

50 mA

5 mA

200 mA

100 mA

6.3V 402

CERM-X5R

10%

0.47UF

C1911

1

2

402

CERM-X5R

6.3V

10%

0.47UF

C1913

1

2

402

CERM-X5R

6.3V

10%

0.47UF

C1912

1

2

CRESTLINE

FCBGA

OMIT

U1400

AT23 AU28 AU24 AT29 AT25 AT30

AR29

B23 B21 A21

AJ50

C40 B40

AD51 W50 W51 V49 V50

AH50 AH51

BK24 BK23 BJ24 BJ23

J32

A43

A33 B33

A30

B49

H49

AL2

A41

AM2

K50

U51

AW18

AT18 AT17

AV19 AU19 AU18 AU17

AT22 AT21 AT19

BC29 BB29

AR17 AR16

C25 B25 C27 B27 B28 A28

M32

AN2

J41 H42

U48

N28

L29

B32

B41

K49

U13

U1 T13 T11 T10 T9 T7 T6 T5 T3 T2

U12

R3 R2 R1

U11 U9 U8 U7 U5 U3 U2

A7 F2 AH1

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

NB Power 2

19 92

A.0.0

051-7431

NB_VTTLF_CAP2

GND

PP1V25_S0M_NB_VCCA_HPLL

GND

GND PP1V5_S0_NB_VCCD_TVDAC

GND

PP1V25_S0_ISNS

GND

PP1V25_S0M_NB_VCCA_MPLL

NB_VTTLF_CAP1

NB_VTTLF_CAP3

PP1V25_S0_ISNS

GND

PP1V05_S0_NB_VCCPEG

PP3V3_S0

PP1V05_S0_NB_VCCPEG

PP1V25_S0_NB_VCCAXF

PP1V25_S0M_NB_VCCAXD

GND

PP1V05_S0

GND

PP1V25_S0M_NB_VCCA_SM_CK

PP1V25_S0_NB_PEGPLL

PP1V8_S3M_NB_VCCSMCK

PP1V25_S0M_NB_VCCA_SM

PP3V3_S0

91

82

65

59

58

53

52

51

50

48

47

46

42

32

61

32

31

50

31

30

46

30

29

30

29

28

27

28

72

27

26

27

69

26

23

26

67

25

21

25

65

24

18

24

50

23

14

23

27

21

13

21

26

19

12

19

21

16

21

11

16

19

13

19

21

10

13

21

22

8

21

8

15

8

15

21

16

8

21

8

VSS198VSS99

VSS197VSS98

VSS196VSS97

VSS195VSS96

VSS194VSS95

VSS193VSS94

VSS192VSS93

VSS191VSS92

VSS190VSS91

VSS189VSS90

VSS188VSS89

VSS187VSS88

VSS186VSS87

VSS185VSS86

VSS184VSS85

VSS183VSS84

VSS182VSS83

VSS181VSS82

VSS180VSS81

VSS179VSS80

VSS178VSS79

VSS177VSS78

VSS176VSS77

VSS175VSS76

VSS174VSS75

VSS173VSS74

VSS172VSS73

VSS171VSS72

VSS170VSS71

VSS169VSS70

VSS168VSS69

VSS167VSS68

VSS166VSS67

VSS165VSS66

VSS164VSS65

VSS163VSS64

VSS162VSS63

VSS161VSS62

VSS160VSS61

VSS159VSS60

VSS158VSS59

VSS157VSS58

VSS156VSS57

VSS155VSS56

VSS154VSS55

VSS153VSS54

VSS152VSS53

VSS151VSS52

VSS150VSS51

VSS149VSS50

VSS148VSS49

VSS147VSS48

VSS146VSS47

VSS145VSS46

VSS144VSS45

VSS143VSS44

VSS142VSS43

VSS141VSS42

VSS140VSS41

VSS139VSS40

VSS138VSS39

VSS137VSS38

VSS136VSS37

VSS135VSS36

VSS134VSS35

VSS133VSS34

VSS132VSS33

VSS131VSS32

VSS130VSS31

VSS129VSS30

VSS128VSS29

VSS127VSS28

VSS126VSS27

VSS125VSS26

VSS124VSS25

VSS123VSS24

VSS122VSS23

VSS121VSS22

VSS120VSS21

VSS119VSS20

VSS118VSS19

VSS117

VSS116VSS17

VSS115VSS16

VSS114VSS15

VSS113VSS14

VSS112VSS13

VSS111VSS12

VSS110VSS11

VSS109VSS10

VSS108

VSS9

VSS107VSS8

VSS106VSS7

VSS105VSS6

VSS104VSS5

VSS103VSS4

VSS102

VSS101

VSS100

VSS1

VSS18

VSS2 VSS3

VSS

(9 OF 10)

VSS202

VSS289 VSS290 VSS291 VSS292

VSS295

VSS199 VSS287 VSS200 VSS288 VSS201

VSS203 VSS204

VSS293 VSS294

VSS208 VSS296 VSS209 VSS297 VSS210 VSS298 VSS211 VSS299 VSS212 VSS300 VSS213 VSS301 VSS214 VSS215 VSS216 VSS302 VSS217 VSS218 VSS219 VSS303 VSS220 VSS221 VSS222 VSS304 VSS223 VSS224 VSS225 VSS305 VSS226 VSS227 VSS228 VSS229 VSS306 VSS230 VSS307 VSS231 VSS308 VSS232 VSS309 VSS233 VSS310 VSS234 VSS311 VSS235 VSS312 VSS236 VSS313 VSS237 VSS238 VSS239 VSS240 VSS241 VSS242 VSS243

VSS245 VSS246 VSS247 VSS248 VSS249 VSS250 VSS251 VSS252 VSS253 VSS254 VSS255 VSS256 VSS257 VSS258 VSS259 VSS260 VSS261 VSS262 VSS263 VSS264 VSS265 VSS266 VSS267 VSS268 VSS269 VSS270 VSS271 VSS272 VSS273 VSS274 VSS275 VSS276 VSS277 VSS278 VSS279 VSS280 VSS281 VSS282 VSS283 VSS284 VSS285 VSS286

VSS207

VSS206

VSS205

(10 OF 10)

VSS

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NOTE: TDE = _P

Crestline Thermal Diode Pins

TDB_SENSE

NOTE: TDB = _N

Mainly for investigation. If not used, alias these nets directly to GND.

TDB_FORCE

TDE_FORCE

TDE_SENSE

CRESTLINE

OMIT

FCBGA

U1400

A13

AB26

AW24 AW29 AW32 AW5 AW7 AY10 AY24 AY37 AY42 AY43

AB28 AY45

AY47 AY50 B10 B20 B24 B29 B30 B35 B38

AB31

B43 B46 B5 B8 BA1 BA17 BA18 BA2 BA24 BB12

AC10

BB25 BB40 BB44 BB49 BB8 BC16 BC24 BC25 BC36 BC40

AC13

BC51 BD13 BD2 BD28 BD45 BD48 BD5 BE1 BE19 BE23

AC3

BE30 BE42 BE51 BE8 BF12 BF16 BF36 BG19 BG2 BG24

AC39

BG29 BG39 BG48 BG5 BG51 BH17 BH30 BH44 BH46 BH8

AC43

BJ11 BJ13 BJ38 BJ4 BJ42 BJ46 BK15 BK17 BK25 BK29

AC47

BK36 BK40 BK44 BK6 BK8 BL11 BL13 BL19 BL22 BL37

AD1

BL47 C12 C16 C19 C28 C29 C33 C36 C41

A15

AD21 AD26 AD29

AD3 AD41 AD45 AD49

AD5 AD50

AD8

A17

AE10 AE14

AE6 AF20 AF23 AF24 AF31

AG2 AG38 AG43

A24

AG47 AG50

AH3 AH40 AH41

AH7

AH9 AJ11 AJ13 AJ21

AA21

AJ24 AJ29 AJ32 AJ43 AJ45 AJ49 AK20 AK21 AK26 AK28

AA24

AK31 AK51

AL1 AM11 AM13

AM3

AM4 AM41 AM45

AN1

AA29

AN38 AN39 AN43

AN5

AN7

AP4 AP48 AP50 AR11

AR2

AB20

AR39 AR44 AR47

AR7 AT10 AT14 AT41 AT49

AU1 AU23

AB23

AU29

AU3 AU36 AU49 AU51 AV39 AV48

AW1 AW12 AW16

CRESTLINE

OMIT

FCBGA

U1400

C46 C50

C7 D13 D24

D3 D32 D39 D45 D49 E10 E16 E24 E28 E32 E47 F19 F36

F4 F40 F50

G1 G13 G16 G19 G24 G28 G29 G33 G42 G45 G48

G8 H24 H28

H4 H45 J11 J16

J2 J24 J28 J33 J35 J39

K12 K47

K8

L1 L17 L20 L24 L28

L3 L33 L49 M28 M42 M46 M49

M5 M50

M9 N11 N14 N17 N29 N32 N36 N39 N44 N49

N7 P19

P2 P23

P3 P50 R49 T39 T43 T47 U41 U45 U50

V2

V3

W11 W39 W43 W47 W5 W7 Y13 Y2 Y41 Y45 Y49 Y5 Y50 Y11 P29

T29

T31

T33

R28

AA32 AB32 AD32 AF28 AF29 AT27 AV25 H50

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

NB Grounds

20 92

A.0.0

051-7431

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Layout Note:

NOTE: This follower is redundant if VCORE is always 1.05V.

Layout Note: Place L and C close to MCH

on opposite side.

be close to MCH

10uF caps should

Layout Note:

495 mA

1573mA (Int Graphics) 1310mA (Ext Graphics)

GMCH ME Core Power

0.4 mA

675 mA (667MHz DDR2)

and DDR2 taps." (C2135)

550 mA (533MHz DDR2)

WF: "Place where LVDS

Placeholder for 2.2nH, 1.4A, 17mOhm

100 mA

Placeholder for 5.6nH, 0.9A, 45mOhm max

Current numbers from Crestline EDS, doc #21749.

260 mA

1260 mA

495 mA

640 mA (667MHz DDR2)

35 mA

515 mA515 mA

585 mA (533MHz DDR2)

100 mA

200 mA 200 mA

be close to MCH

450 mA

150 mA

50 mA

250 mA

10uF caps should

100 mA

540 mA

WF: Matanzas has 2-pin 270uF bulk cap

GMCH Core Power

770 mA (667MHz FSB)

850 mA (800MHz FSB)

GMCH FSB I/O Rail

1700 mA (1ch 667MHz)

5 mA (standby)

1395 mA (1ch 533MHz)

2700 mA (2ch 533MHz)

3300 mA (2ch 667MHz)

1520 mA

100 mA

GMCH Memory I/O Rail

Placeholder for 3.9nH, 1A, 32mOhm

Layout Note: Route to caps, then GND

0.47UF

CERM-X5R 402

10%

6.3V

PLACEMENT_NOTE=Place close to U1400

C2124

1

2

6.3V

20%

PLACEMENT_NOTE=Place close to U1400

2.2uF

603

CERM1

C2123

1

2

603

PLACEMENT_NOTE=Place close to U1400

CERM

20%

6.3V

4.7uF

C2121

1

2

10V

0.1uF

402

20% CERM

C2161

1

2

10V

0.1uF

402

CERM

20%

C2165

1

2

CRITICAL

D2T

20%

TANT

2.5V

470UF

C2100

1

2 3

10V

0.1uF

402

CERM

20%

PLACEMENT_NOTE=Place in GMCH cavity

C2113

1

2

0.22uF

402

20%

6.3V X5R

C2112

1

2

402

X5R

20%

6.3V

0.22uF

C2111

1

2

6.3V

CERM-X5R

20%

805-3

22UF

C2110

1

2

CERM

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

402

20%

C2114

1

2

PLACEMENT_NOTE=Place in GMCH cavity

10V CERM

20%

402

0.1uF

C2115

1

2

603

PLACEMENT_NOTE=Place close to U1400

6.3V CERM

20%

4.7uF

C2122

1

2

22UF

805-3

6.3V

20% CERM-X5R

PLACEMENT_NOTE=Place close to U1400

C2131

1

2

22UF

805-3

6.3V

20% CERM-X5R

PLACEMENT_NOTE=Place close to U1400

C2132

1

2

CERM 402

20% 10V

0.1uF

C2135

1

2

0.51

MF-LF

1/16W

1%

402

R2183

1

2

10V

0.1uF

402

CERM

20%

C2191

1

2

402

1.1

1% 1/16W MF-LF

R2190

1

2

FERR-220-OHM

0805

CRITICAL

L2190

1 2

10uF

20%

6.3V X5R 603

C2190

1

2

CERM

0.1uF

10V 402

20%

C2192

1

2

PLACEMENT_NOTE=Place C2180 by U1400.AN2

10V

0.1uF

402

CERM

20%

C2180

1

2

CASE-B2-SM-HF

CRITICAL

POLY

20%

220UF

2.5V

C2120

1

2

603

X5R

20%

6.3V

10uF

C2174

1

2

CRITICAL

CASE-B2-HF

POLY

20%

2.5V

220UF

C2173

1

2

1210

91NH

L2173

1 2

10V 402

CERM

20%

0.1uF

C2197

1

2

402

MF-LF

1%

1/16W

1.1

R2195

1

2

0805

1.0UH-220MA-0.12-OHM

L2195

1 2

603

10uF

20%

6.3V X5R

C2195

1

2

22UF

805-3

6.3V

20%

CERM-X5R

C2196

1

2

10V

0.1uF

402

CERM

20%

C2160

1

2

X5R

10V

10%

402

1uF

C2171

1

2

603

X5R

6.3V

20%

10uF

C2170

1

2

603

5%

MF-LF

1/10W

0

R2170

1 2

X5R

10V

10%

1uF

402

C2151

1

2

5% 1/10W MF-LF

0

603

R2150

1 2

NO STUFF

0603

FERR-120-OHM-0.2A

L2150

1 2

CERM-X5R

805-3

22UF

6.3V

20%

C2142

1

2

22UF

CERM-X5R

20%

6.3V

805-3

NO STUFF

C2141

1

2

4.7UF

6.3V

20% CERM

603

C2143

1

2

CASE-B2-SM-HF

CRITICAL

POLY

20%

220UF

2.5V

C2140

1

2

X5R

1uF

402

10% 10V

C2144

1

2

1/10W

MF-LF

603

5%

0

R2141

1 2

22UF

CERM-X5R

20%

6.3V

805-3

C2145

1

2

0

MF-LF

603

1/10W

5%

R2145

1 2

CERM

20%

402

0.1uF

10V

C2148

1

2

1/16W MF-LF

402

1%

10

R2186

1 2

BAT54E3

SOT23

D2186

1 3

10

MF-LF

1%

1/16W

402

R2185

1 2

BAT54E3

SOT23

D2185

1 3

22UF

NO STUFF

6.3V

805-3

20%

CERM-X5R

C2150

1

2

6.3V

20%

2.2uF

603

CERM1

NO STUFF

C2146

1

2

CASE-C2S-HF

CRITICAL

POLY

2.5V

20%

330UF

C2130

1

2

FERR-120-OHM-0.2A

0603

L2181

1 2

PLACEMENT_NOTE=Place in GMCH cavity

10V

0.1uF

402

CERM

20%

C2104

1

2

603

10uF

20%

6.3V X5R

C2177

1

2

PLACEMENT_NOTE=Place in GMCH cavity

402

20%

6.3V X5R

0.22uF

C2103

1

2

0.22uF

PLACEMENT_NOTE=Place in GMCH cavity

402

20%

6.3V X5R

C2102

1

2

10V

PLACEMENT_NOTE=Place C2184 by U1400.AM2

0.1uF

402

CERM

20%

C2184

1

2

PLACEMENT_NOTE=Place C2182 by U1400.AL2

10V

0.1uF

402

CERM

20%

C2182

1

2

22UF

20%

6.3V

CERM-X5R

805-3

C2181

1

2

0603

FERR-120-OHM-0.2A

L2183

1 2

CERM-X5R

20%

22UF

6.3V

805-3

C2183

1

2

805-3

6.3V

20%

PLACEMENT_NOTE=Place in GMCH cavity

22UF

CERM-X5R

C2101

1

2

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

NB Standard Decoupling

92

051-7431

A.0.0

21

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP1V25_S0_NB_PEGPLL

VOLTAGE=1.25V

PP1V25_S0_ISNS

PP1V05_S0

PPVCORE_S0_NB_R

PP1V8_S3_ISNS

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_NBCORE_FOLLOW_R

PP3V3_S0

PP1V25_S0_ISNS

PP1V05_S0_NB_VCCPEG

MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.05V

MIN_LINE_WIDTH=0.5 MM

PP1V8_S3M_NB_VCCSMCK

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.8V

PP1V8_S3_ISNS

PP1V25_S0_ISNS

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_PEGPLL_RC

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V

PP1V25_S0_ISNS

PP1V25_S0M_NB_VCCAXD

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_NB_VCCAXF

MIN_LINE_WIDTH=0.4 MM MIN_NECK_WIDTH=0.2 MM VOLTAGE=1.25V

PP1V25_S0_ISNS

PP1V05_S0

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

PP1V8_S3M_NB_VCCSMCK_RC

VOLTAGE=1.8V

PP3V3_S0

PP1V05_S0

PP3V3_S0_NB1V05_FOLLOW_R

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM VOLTAGE=3.3V

PP1V25_S0_ISNS

VOLTAGE=1.25V

MIN_LINE_WIDTH=0.3 MM

PP1V25_S0M_NB_MPLL_RC

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0_ISNS

MIN_LINE_WIDTH=0.3 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_VCCA_MPLL

PP3V3_S0

GND

MIN_LINE_WIDTH=0.25 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

PP1V25_S0M_NB_VCCA_HPLL

PP1V25_S0M_NB_VCCA_SM_CK

MIN_LINE_WIDTH=0.4 MM VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

VOLTAGE=1.25V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.4 MM

PP1V25_S0M_NB_VCCA_SM

PP1V05_S0 PP1V05_S0

PP1V05_S0_NB_VCCPEG

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.5 MM VOLTAGE=1.05V

MAKE_BASE=TRUE

91

82

65

59

58

53

52

51

50

48

47

46

61

42 61

42

61

42

61 61

50

32 50

32

50

32

50 50

46

31 46

31

46

31

46 46

30

30 30

30

30 30

27

29 27

29

27

29

27 27

26

28

26

28

26

28

26 26

72

23

27

72

23

27

23

72

27

23 23

69

21

26

69

21

26

21

69

26

21 21

67

19

25

67

19

25

19

67

25

19 19

65

18

24

65

18

24

18

65

24

18 18

50

14

23

50

14

23

14

50

23

14 14

27

13

50

21

27

50

27

13

21

13

27

21

13 13

26

12

21

19

26

21

26

12

19

12

26

19

12 12

21

11

50

18

16

21

18

21

11

16

11

21

16

11 11 21

19

10

18

16

13

19

16

19

10

13

10

19

13

10 10 19

19

8

15

19

8

16

8

19

8

19

8 8

15

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

These 2 caps should be

Current numbers from Crestline EDS Addendum, doc #20127.

65 mA

Crestline LVDS Strapping

60 mA

VCCD_TVDAC also powers internal thermal sensors.

NOTE: This filter is required even if using only external graphics.

Layout Note:

within 6.35 mm of NB edge

22000pF-1000mA

CRITICAL

NFM18

16V

C2201

2

1 3

402

10V

0.1uF

CERM

20%

C2200

1

2

SYNC_DATE=08/28/2007

NB Graphics Decoupling

051-7431

A.0.0

9222

SYNC_MASTER=M87_MLB

TP_GFX_VID<4>

MAKE_BASE=TRUE

TP_GFX_VR_EN

MAKE_BASE=TRUE

GFX_VID<4> TP_GFX_VR_EN

PP1V5_S0

GND GND

GND

NC_LVDS_B_CLKP

NC_LVDS_BKLT_CTL NC_LVDS_BKLT_EN NC_LVDS_VDD_EN

NC_LVDS_VBG NC_LVDS_A_CLKN

GND

MAKE_BASE=TRUE

NC_LVDS_BKLT_CTL

NO_TEST=TRUE

GND

GND GND

GND

GND GND

GND

GND GND GND

GND

MAKE_BASE=TRUE

NC_LVDS_VDD_EN

NO_TEST=TRUE

NC_LVDS_BKLT_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_CLKN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_CLKP

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_CLKP

NC_LVDS_B_CLKN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_CLKN

NC_LVDS_A_DATAN<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_DATAN<0>

NC_LVDS_B_CLKP

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_A_DATAN<2>

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_A_DATA_N<2>

NC_LVDS_A_DATAN<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_A_DATA_N<1>

NC_LVDS_A_DATAP<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_A_DATAP<0>

NC_LVDS_A_DATAP<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_A_DATA_P<1>

NC_LVDS_A_DATAP<2>

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_A_DATA_P<2>

NC_LVDS_B_DATAN<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

LVDS_B_DATA_N<1>

NC_LVDS_B_DATAN<0>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_B_DATAN<0>

LVDS_B_DATA_N<2>

LVDS_B_DATA_P<1>

NC_LVDS_B_DATAP<0>

NC_LVDS_VREFH

LVDS_B_DATA_P<2>

GND

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_VREFH

NC_LVDS_VREFL

MAKE_BASE=TRUE NO_TEST=TRUE

NC_LVDS_B_DATAN<2>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_B_DATAP<1>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_B_DATAP<0>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_B_DATAP<2>

NO_TEST=TRUE

MAKE_BASE=TRUE

GFX_VID<2>

TP_GFX_VID<1>

GFX_VID<3>

GND

GND GND GND

GND

NC_LVDS_IBG

MAKE_BASE=TRUE

NC_LVDS_IBG

NO_TEST=TRUE

NC_LVDS_VBG

MAKE_BASE=TRUE

VOLTAGE=1.5V

MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.3 MM

PP1V5_S0_NB_VCCD_TVDAC

NC_LVDS_VREFL

MAKE_BASE=TRUE

TP_GFX_VID<3>

MAKE_BASE=TRUE

TP_GFX_VID<2>

MAKE_BASE=TRUE

TP_GFX_VID<1>

91 63 34 27

26 12

84

84 84

84

84 84

22 22

11

22

22 22

22

84

22 22

84

22 22

84

22

84

22

22 22

22

16

8

15

15 15

15

15 15

15

15 15

15

16

15 15

15

19

15

16

SATA0RXP

SATA0RXN

SATALED*

RTCRST*

HDA_BIT_CLK

DDREQ

RTCX1 RTCX2

DCS1* DCS3*

IDEIRQ

DDACK*

IORDY

DIOR* DIOW*

DD11 DD12

DD4

DD2

DD14

DD0

DD15

DD1

DD13

DD5

DD10

DD8

DD3

DD9

LDRQ0*

FWH2/LAD2 FWH3/LAD3

FWH1/LAD1

LDRQ1*/GPIO23

FWH0/LAD0

FWH4/LFRAME*

HDA_SDIN0

HDA_SYNC

SATA1TXN SATA1TXP

HDA_SDIN1 HDA_SDIN2

RCIN*

SATA0TXP

SATA0TXN

CPUPWRGD/GPIO49

SMI*

A20M*

SATA1RXP

SATA1RXN

SATARBIAS

SATARBIAS*

IGNNE*

DPRSTP*

INTVRMEN

A20GATE

SATA2RXN SATA2RXP

THRMTRIP*

DPSLP*

INIT*

HDA_RST*

HDA_SDOUT

HDA_DOCK_EN*/GPIO33

SATA2TXN SATA2TXP

FERR*

NMI

HDA_SDIN3

INTR

SATA_CLKP

SATA_CLKN

DA2

DD6

STPCLK*

TP8

DA0 DA1

HDA_DOCK_RST*/GPIO34

INTRUDER*

LAN_TXD0

LAN100_SLP

LAN_RSTSYNC

LAN_RXD0 LAN_RXD1 LAN_RXD2

DD7

LAN_TXD2

LAN_TXD1

GLAN_DOCK*/GPIO13

GLAN_COMPI GLAN_COMPO

GLAN_CLK

LAN/GLANIHDA

CPU

RTC

LPC

(1 OF 6)

SATA

IDE

OUT

IN

BI

BI BI

BI

OUT

IN

OUT

IN

IN OUT OUT

IN

OUT

IN

OUT OUT

IN

OUT

OUT OUT OUT

IN IN IN

BI

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

IN

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

INT PU

INT PD

HDA

24.000MHZ CLOCK W/INTERNAL WEAK PD

HDA_BIT_CLK HDA_RST# HDA_SDIN[0-2] HDA_SDOUT ACZ_SYNC

INTEGRATED PDs INTEGRATED PD INTEGRATED PD

INT PDINT PU

INT PD

INT PU

NOTE: ALL IDE PINS HAVE INTERNAL 33-OHM SERIES R’S

ICH8M

BGA

OMIT

U2300

AF13 AG26

AG29

AA4 AA1 AB3

Y6 Y5

V1 U2

T4 V6 V5 U1 V2 U6

V3 T1 V4 T5 AB2 T6 T3 R2

Y2

W5

W4 W3

AF26 AE26

AD24

E5 F5 G8 F6

C4

B24

D25 C25

AH21

AJ16

AE10 AG14

AE14

AJ17 AH17 AH15 AD13

AE13

AJ15

Y3

AF27

AE24 AC20

AD22

AF25

Y1

AD21

D22

C21 B21 C22

D21 E20 C20

G9 E6

AD23

AH14

AF23

AG25 AF24

AF6 AF5 AH5 AH6

AG3 AG4 AJ4 AJ3

AF2 AF1 AE4 AE3

AB7 AC6

AF10

AG2

AG1

AG28

AA24

AE27

AA23

28

7

28

7

45 47

7

45 47

7

45 47

7

45 47

9

7

45 47

10 83

NO STUFF

2.2K

5% 1/16W MF-LF

402

R2304

1

2

1/16W MF-LF

24.9

1%

402

R2302

1

2

1/16W 402

MF-LF

332K

1%

R2301

1

2

81 86

42 86

29 30 88

23 42 86

7

10 16 59 83

7

10 83

7

10 13 83

42 86

7

10 83

10 47 83

10 83

1/16W

5%

402

MF-LF

10K

R2306

1

2

10 16 46 83

402

24.9

1/16W MF-LF

1%

PLACEMENT_NOTE=Place R2308 within 50mm of U2300

R2308

1 2

34 86

MF-LF

402

332K

1%

1/16W

R2300

1

2

402

MF-LF

1/16W

5%

8.2K

R2303

1

2

34 86

8.2K

5% 1/16W MF-LF

402

R2310

1

2

54.9

402

MF-LF

1/16W

1%

R2305

1

2

PLACEMENT_NOTE=Place R2309 within 50mm of R2308 (NO STUB)

54.9

402

MF-LF

1/16W

1%

R2309

1

2

5%

1/16W MF-LF33402

R2313

1 2

402

33

MF-LF1/16W

5%

R2314

1 2

4025%

MF-LF

33

1/16W

R2315

1 2

33

402

MF-LF1/16W

5%

R2316

1 2

5%

10K

MF-LF 402

1/16W

R2311

1

2

42 86

SB Enet, Disk, FSB, LPC

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

051-7431

9223

A.0.0

TP_HDA_SDIN2 TP_HDA_SDIN3

HDA_SDIN0

TP_LAN_D2R<1>

TP_ENET_GLAN_CLK

TP_HDA_SDIN1

SATA_A_D2R_N

HDA_SDOUT

HDA_RST_L

HDA_BIT_CLK HDA_SYNC

HDA_SDOUT_R

HDA_RST_L_R

HDA_SYNC_R

HDA_BIT_CLK_R

SATA_RBIAS SATA_RBIAS

SB_CLK100M_SATA_N SB_CLK100M_SATA_P

TP_SATA_C_R2DP

TP_SATA_C_R2DN

TP_SATA_C_D2RN TP_SATA_C_D2RP

TP_SATA_B_R2DP

TP_SATA_B_R2DN

TP_LAN_R2D<1>

TP_LAN_D2R<0>

TP_LAN_RSTSYNC

TP_LAN_R2D<0>

TP_HDA_DOCK_RST_L

TP_SATA_B_D2RN TP_SATA_B_D2RP

SATA_A_R2D_C_N SATA_A_R2D_C_P

TP_SB_SATALED_L

SATA_A_D2R_P

TP_LAN_D2R<2>

TP_SB_TP8

SB_RCIN_L

TP_LPC_DRQ0_L

SB_A20GATE

CPU_FERR_L

PP3V3_S0

PP1V05_S0

IDE_PDDREQ

IDE_PDIORDY

IDE_IRQ14

IDE_PDDACK_L

IDE_PDIOR_L IDE_PDIOW_L

IDE_PDCS1_L IDE_PDCS3_L

IDE_PDA<2>

IDE_PDA<1>

IDE_PDA<0>

IDE_PDD<14> IDE_PDD<15>

IDE_PDD<13>

IDE_PDD<11> IDE_PDD<12>

IDE_PDD<9> IDE_PDD<10>

IDE_PDD<8>

IDE_PDD<6> IDE_PDD<7>

IDE_PDD<5>

IDE_PDD<4>

IDE_PDD<3>

IDE_PDD<1> IDE_PDD<2>

IDE_PDD<0>

CPU_STPCLK_L

CPU_SMI_L

CPU_NMI

CPU_INTR

CPU_INIT_L

CPU_IGNNE_L

CPU_PWRGD

CPU_DPRSTP_L CPU_DPSLP_L

CPU_A20M_L

CPU_THERMTRIP_R

PM_THRMTRIP_L

TP_EXTGPU_PWR_EN

LPC_FRAME_L

LPC_AD<3>

LPC_AD<1>

LPC_AD<0>

LPC_AD<2>

TP_LAN_R2D<2>

SB_RTC_X1 SB_RTC_X2

SB_RTC_RST_L SB_SM_INTRUDER_L

SB_LAN100_SLP

SB_INTVRMEN

HDA_DOCK_EN_L

PP3V3_G3_SB_RTC

GLAN_COMP

PP1V5_S0_SB_VCC1_5_B

PP3V3_S0

LAN_ENERGY_DET

91

82

65

59

58

53

52

51

50

48

47

46

42

32

61

32

31

50

31

30

46

30

29

30

29

28

27

28

27

26

27

26

21

26

25

19

25

24

18

24

23

14

23

21

13

21

19

12

19

16

11

28

27

16

13

10

27

26

13

86

8

7

26

87

24

8

SPI_CS1*

PETN1

PERP1

OC4*/GPIO43 OC5*/GPIO29 OC6*/GPIO30 OC7*/GPIO31 OC8* OC9*

SPI_MOSI

OC0* OC1*/GPIO40 OC2*/GPIO41 OC3*/GPIO42

PERN5

DMI1RXN DMI1RXP DMI1TXN DMI1TXP

DMI0RXN DMI0RXP DMI0TXN DMI0TXP

DMI_CLKN DMI_CLKP

PETP1

USBP9N USBP9P

PERN2

USBP7N USBP7P USBP8N USBP8P

PETN2

USBP6N USBP6P

PERP3

USBP4N USBP4P USBP5N USBP5P

PETN3 PETP3

USBP3N USBP3P

PERN4 PERP4

USBP1N USBP1P USBP2N USBP2P

PETN4 PETP4

USBP0N USBP0P

PERP5

SPI_MISO

USBRBIAS

USBRBIAS*

PETP5

PERN6/GLAN_RXN PERP6/GLAN_RXP PETN6/GLAN_TXN PETP6/GLAN_TXP

SPI_CLK SPI_CS0*

DMI3RXN DMI3RXP DMI3TXN DMI3TXP

DMI2RXN DMI2RXP DMI2TXN DMI2TXP

DMI_IRCOMP

DMI_ZCOMP

PERN1

PERP2

PETP2

PERN3

PETN5

PCI_EXPRESS

DIRECT MEDIA INTERFACE

SPI

USB

(2 OF 6)

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

IN OUT OUT

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

IN IN OUT OUT

BI BI

BI

AD4 AD5

AD9

PIRQF*/GPIO3

PIRQE*/GPIO2

AD13

PME*

PCIRST*

GNT2*/GPIO53

C/BE2*

PIRQG*/GPIO4

SERR*

PIRQA*

AD1

REQ1*/GPIO50

C/BE3*

AD11

C/BE1*

AD25 AD26

AD0

AD2

DEVSEL*

AD18

AD21

PAR

GNT0*

AD7

GNT1*/GPIO51

C/BE0*

STOP*

AD20

AD16

GNT3*/GPIO55

TRDY*

IRDY*

AD22

PIRQC*

REQ2*/GPIO52

AD19

PCICLK

PLOCK*

AD15

PIRQB*

PIRQH*/GPIO5

PLTRST*

AD3

AD6

AD8

FRAME*

AD14

AD12

AD10

REQ3*/GPIO54

PIRQD*

AD17

PERR*

REQ0*

AD31

AD27 AD28

AD30

AD29

AD24

AD23

(3 OF 6)

INTERRUPT I/F

PCI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

BI BI BI

BI

IN

BI

BI BI

OUT

BI BI BI

BI

OUT

IN

BI BI

IN

IN IN IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(x2-capable, pull HDA_SYNC high for x2)

enabled only when PCIRST# = 0 and PWROK = 1

selects SPI ROM by default.

SPI_CS1# HAS INT PU (NOMINAL=20K, SIMULATION=15K-35K)

GNT0# HAS INT PU; ENABLED ONLY WHEN PCIRST#=0 AND PWROK=H

INT PD

(AirPort)

PCIe Mini Card

FireWire INT*

NOTE: GNT[0-3]# have internal 20K pull-ups

If used, ensure GNT2# is not low when PWROK rises, or PCIe ports 5 & 6 will be disabled.

INT PU

R2415 pull-down on GNT0#

SB BOOT BIOS SELECT

I/F LPC

Nineveh-GLCI

Yukon-PCIE

SPI

NOTE:

0

GNT0#

1

Ethernet

FireWire

ExpressCard

Spares

INT PD

INT PD INT PD

EHCI1

INT PU INT PU

INT PU

INT PD

INT PD INT PD

INT PD

EHCI0

INT PD

INT PD INT PD INT PD INT PD

INT PD

External C

Camera

AirPort (PCIe Mini-Card)

ExpressCard

External B

Geyser Trackpad/Keyboard

External A

External D / WWAN

Bluetooth

IR

NOTE: USBP[0-9]P/N have internal 15K pull-downs.

1/16W

402

10K

5%

MF-LF

R2408

1

2

5%

10K

402

MF-LF

1/16W

R2407

1

2

MF-LF

1/16W

5%

402

10K

R2400

1

2

5% MF-LF

402

1/16W

10K

R2409

1

2

1/16W

10K

5%

402

MF-LF

R2401

1

2

1/16W

5%

402

MF-LF

10K

R2402

1

2

5%

MF-LF

10K

1/16W

402

R2404

1

2

5% 1/16W

402

MF-LF

10K

R2403

1

2

OMIT

ICH8M

BGA

U2300

V27 V26 U29 U28

Y27 Y26 W29 W28

AB26 AB25 AA29 AA28

AD27 AD26 AC29 AC28

T26 T25

Y24

Y23

AJ19 AG16 AG15 AE15 AF15 AG17 AD12 AJ18 AD14 AH18

P27

M27

K27

H27

F27

D27

P26

M26

K26

H26

F26

D26

N29

L29

J29

G29

E29

C29

N28

L28

J28

G28

E28

C28

C23 B23 E22

F21

D23

G3 G2 H5 H4 H2 H1 J3 J2 K5 K4 K2 K1 L3 L2 M5 M4 M2 M1 N3 N2

F3

F2

16 84

29 30 88

24.9

1/16W MF-LF

4021%

R2413

1 2

43 86

34 86

9

86

9

86

44 86

7

81 86

7

81 86

34 86

1/16W

1%

402

MF-LF

22.6

R2414

1 2

34 87

35 87

56 86

OMIT

BGA

ICH8M

U2300

D20 E19

A12 E16 A14 G16 A15

B6

C11

A9 D11 B12

D19

C12 D10

C7 F13 E11 E13 E12

D8

A6

E8

A20

D6

A3

D17 A21 A19 C19 A18 B16 C17

E15 F16 E17

D16

A17

D7

C18

F18

C10

C8 D9

B10

G6

A7

F9

B5

C5 A10

F8 G11 F12 B3

B7

AG24

G7

A4

E18

B19

A11

F10 C16 C9

38 87

24 87

24 38 87

24 87

24 38 87

24 87

38 87

24 38 87

38 87

7

28

24 38 87

24 87

24 38 87

7 9

28 82

30 88

9

24 34

10K

1/16W MF-LF 402

5%

R2405

1

2

10K

MF-LF

5%

1/16W

402

R2406

2

1

1K

MF-LF

1/16W

5%

402

R2415

1

2

8.2K

R2423

1 2

8.2K

R2424

1 2

8.2K

R2425

1 2

8.2K

R2426

1 2

8.2K

R2427

1 2

8.2K

R2428

1 2

8.2K

R2430

1 2

8.2K

R2429

1 2

8.2K

R2432

1 2

8.2K

R2431

1 2

8.2K

R2433

1 2

8.2K

R2437

1 2

8.2K

R2439

1 2

8.2K

R2438

1 2

8.2K

R2436

1 2

100K

R2440

1 2

24 87

8.2K

R2441

1 2

13 43

13

13 34

34 46

34

24 42

7

24 38 47 87

42 86

13

7

24 38 47 87

13

8.2K

R2442

1 2

13

13 36

13

80

SB PCI, PCIe, DMI, USB

SYNC_MASTER=M87_MLB

A.0.0

24 92

051-7431

SYNC_DATE=08/28/2007

DMI_N2S_N<0> DMI_N2S_P<0> DMI_S2N_N<0> DMI_S2N_P<0>

DMI_N2S_N<1> DMI_N2S_P<1> DMI_S2N_N<1> DMI_S2N_P<1>

DMI_N2S_N<2> DMI_N2S_P<2> DMI_S2N_N<2> DMI_S2N_P<2>

DMI_N2S_N<3> DMI_N2S_P<3> DMI_S2N_N<3> DMI_S2N_P<3>

SB_CLK100M_DMI_N SB_CLK100M_DMI_P

USB_EXTA_N USB_EXTA_P USB_MINI_N USB_MINI_P TP_USB_EXTDN TP_USB_EXTDP

USB_CAMERA_P

USB_CAMERA_N

USB_IR_N USB_IR_P USB_TPAD_N

USB_BT_N

USB_TPAD_P

USB_BT_P USB_EXTB_N USB_EXTB_P USB_EXCARD_N

USB_EXTC_N

USB_EXCARD_P

USB_EXTC_P

PCIE_MINI_R2D_C_N

PCIE_EXCARD_D2R_N

TP_PCIE_B_R2D_C_P

TP_PCIE_B_D2R_P

TP_PCIE_A_D2R_N

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_P

PCIE_ENET_D2R_N

PCIE_MINI_R2D_C_P

SPI_SO

PCIE_MINI_D2R_P

TP_PCIE_FW_R2D_C_P

TP_PCIE_FW_D2R_P

TP_PCIE_FW_D2R_N

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D_C_N

PCIE_EXCARD_D2R_P

TP_PCIE_B_R2D_C_N

TP_PCIE_B_D2R_N

PCIE_MINI_D2R_N

USB_EXTD_OC_L

SPI_SI_R

EXCARD_OC_L

USB_EXTB_OC_L

PM_LATRIGGER_L

TP_PCIE_A_D2R_P TP_PCIE_A_R2D_C_N

TP_SPI_CE_R_L<1>

DMI_IRCOMP_R

PP1V5_S0_SB_VCC1_5_B

PCI_PERR_L

PCI_DEVSEL_L

PCI_SERR_L

INT_PIRQC_L

PCI_FRAME_L

PCI_STOP_L

INT_PIRQD_L

PCI_TRDY_L

TP_PCIE_A_R2D_C_P

SB_GPIO30

PP3V3_S5

PCI_FW_GNT_L

TP_SB_GPIO53

PCI_REQ1_L TP_SB_GPIO51

TP_SB_GPIO55

PCI_FW_REQ_L

ODD_RST_5VTOL_L

PCI_C_BE_L<2>

PCI_C_BE_L<0> PCI_C_BE_L<1>

PCI_IRDY_L PCI_PAR

PCI_PERR_L

PCI_DEVSEL_L

PCI_LOCK_L PCI_SERR_L PCI_STOP_L

PCI_FRAME_L

PCI_TRDY_L

PCI_CLK33M_SB

PLT_RST_L

PCI_AD<0>

PCI_AD<2>

PCI_AD<1>

PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6>

PCI_AD<8>

PCI_AD<7>

PCI_AD<9> PCI_AD<10> PCI_AD<11>

PCI_AD<13>

PCI_AD<12>

PCI_AD<14> PCI_AD<15> PCI_AD<16>

PCI_AD<18>

PCI_AD<17>

PCI_AD<19> PCI_AD<20> PCI_AD<21>

PCI_AD<24>

PCI_AD<23>

PCI_AD<25> PCI_AD<26>

PCI_AD<28> PCI_AD<29> PCI_AD<30> PCI_AD<31>

INT_PIRQB_L

INT_PIRQA_L

INT_PIRQC_L INT_PIRQD_L

PCI_AD<27>

PCI_AD<22>

WOW_EN

PCIE_ENET_R2D_C_N

SPI_CE_R_L<0>

SB_GPIO40

USB_RBIAS

PCI_IRDY_L

INT_PIRQF_L

PP3V3_S0

ODD_PWR_EN_L

IPHS_SW_INT

INT_PIRQA_L

MAKE_BASE=TRUE

PCI_FW_GNT_L

PCI_C_BE_L<3>

PCI_RST_L

PCI_REQ2_L

USB_EXTC_OC_L

ODD_PWR_EN_L

IPHS_SW_INT INT_PIRQF_L

TP_PCI_PME_L

DVI_HOTPLUG_DET

SPI_SCLK_R

TP_PCIE_FW_R2D_C_N

USB_EXTA_OC_L

EXTGPU_LVDS_EN

PCI_LOCK_L PCI_FW_REQ_L

PCI_REQ1_L PCI_REQ2_L

INT_PIRQB_L

91 82 65 59 58 53 52

51 50 48 47 46 42 32

91

31

76

30

65

29

60

28

58

27

56

26

48

25

46

23

28

21

27

19

27

87

26

87

16

34

87

26

38

87

38

25

38

87

13

42

24

87

38

87

34

23

24

8

86

24

8

24

9

24

OUT OUT

BI

IN

BI

IN IN

SMBALERT*/GPIO11

STP_PCI*/GPIO15

BMBUSY*/GPIO0

SYS_RESET*

SUS_STAT*/LPCPD*

QRT_STATE0/GPIO27

THRM*

SMLINK0

GPIO12

SPKR

SDATAOUT1/GPIO48

QRT_STATE1/GPIO28

SLP_S5*

GPIO20

GPIO8

WAKE*

CL_CLK1

BATLOW*

PWROK

SLOAD/GPIO38

SATA2GP/GPIO36

SERIRQ

RI*

CL_DATA1

SLP_S4*

EC_ME_ALERT/GPIO14

TACH0/GPIO17

CLK14

SCLOCK/GPIO22

SATA3GP/GPIO37

SATACLKREQ*/GPIO35

STP_CPU*/GPIO25

WOL_EN/GPIO9

LINKALERT*

SLP_S3*

RSMRST*

TACH3/GPIO7

CLKRUN*/GPIO32

GPIO18

LAN_RST*

CL_VREF1

S4_STATE*/GPIO26

TACH1/GPIO1 TACH2/GPIO6

SATA1GP/GPIO19

SDATAOUT0/GPIO39

SATA0GP/GPIO21

MCH_SYNC*

DPRSLPVR/GPIO16

VRMPWRGD

TP3

TP7

CL_RST*

ME_EC_ALERT/GPIO10

SLP_M*

MEM_LED/GPIO24

PWRBTN*

SUSCLK

CL_VREF0

CK_PWRGD

CLPWROK

CL_DATA0

CL_CLK0

CLK48

SMBCLK SMBDATA

SMLINK1

MISC

SYS GPIO

SMB

CLOCKS

POWER MGT

CONTROLLER LINK

GPIO

SATA

GPIO

(4 OF 6)

IN IN

OUT

IN

BI BI

OUT

IN

OUT

IN

BI

OUT

BI

IN

OUT OUT

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

See note below

PP1V05_S0M, PP0V9_S3M and PP0V9_S0M.

for XOR chain testing.

INT PU

NOTE: DPRSLPVR HAS INT 20K PD ENABLED AT BOOT/RESET FOR STRAPPING FUNCTION

Test access required

INT PU

INT PD

NOTE: ICH CLPWROK input must be PWRGD signal for

INT PU

until VccCL3_3, VccLAN3_3 and VccLAN1_05

PM_LAN_ENABLE must remain deasseted

have been up for at least 1ms.

PP3V3_S0M, PP3V3_S0MWOL, PP1V8_S3M, PP1V25_S0M,

If ME/AMT is not used, short CLPWROK to PWROK.

7

29 30

7

29 30

7

45 47

34 35

7

45 47

45

13 45

5% 1/16W MF-LF 402

10K

R2515

1

2

402

0

5% 1/16W MF-LF

ARB_ONLY

R2516

1

2

MF-LF

1/16W

5%

10K

402

R2511

1

2

MF-LF

1/16W

5%

0

402

NOSTUFF

R2512

1

2

5%

10K

MF-LF

402

1/16W

R2502

1

2

10K

402

5% MF-LF

1/16W

R2504

1

2

MF-LF

1K

5% 1/16W

402

R2500

1

2

402

8.2K

5% 1/16W MF-LF

R2507

1

2

10K

5% 1/16W MF-LF 402

R2506

1

2

402

1/16W

8.2K

5%

MF-LF

R2505

1

2

OMIT

BGA

ICH8M

U2300

AE21

AG12

E1

F23 AE18

F22 AF19

AJ23

D24 AH23

AG9 G5

AH11

E3

AJ14

AF22

AC19

AH12 AE11

AE16

AH20

AG21

AJ13 AJ24

AJ27

C2

AE23

AH25 AD16

AF17

AG27

AH27

AJ12 AJ10 AF11 AG11

AG13

AG10

AJ11 AD10

AF12

AF9

AJ25

AG23 AF21 AD18

AG22

AJ26 AD19

AC17 AE19

AD9

AG18

AE20

F4 D3

AD15

AG8

AJ8 AJ9 AH9

AC13

AJ21

AJ22

AJ20

AE17

AG19

30 88

45 46

7

35 36 40 45 49 58 62 65

402

1/16W

5%

1K

NO_REBOOT_MODE

MF-LF

R2510

1

2

7

45 46

7

16 59 83

7 9

25 28

25 45

7

45

29 31 32 34 48 86

7

45 46 47

7

28 45

7

16

7

28

25 38

7

16

7

34 43 45 58 65

29

7 9

25 28

16 87

402

3.24K

1% 1/16W MF-LF

R2526

1

2

402

453

1% 1/16W MF-LF

R2527

1

2

402

16V

10%

0.1uF

X5R

C2500

1

2

402

1/16W

1% MF-LF

4.53K

R2529

1

2

1% 1/16W MF-LF 402

32.4K

R2528

1

2

402

16V

10% X5R

0.1uF

C2501

1

2

16 87

25

100K

1/16W

402

MF-LF

5%

R2523

1

2

48 86

25

1/16W

10K

MF-LF

1%

402

R2536

1 2

5%

MF-LF

1/16W

8.2K

402

R2544

1 2

MF-LF

10K

1/16W

1%

402

R2545

1 2

10K

MF-LF

1/16W

5%

402

R2525

1

2

7

25 47

25

25 28

29

MF-LF

1/16W

5%

10K

402

R2534

2

1

1/16W

10K

5%

402

MF-LF

R2552

1

2

MF-LF

402

1/16W

5%

10K

R2550

1

2

402

MF-LF

5%

8.2K

1/16W

R2553

1

2

5% MF-LF

402

1/16W

8.2K

R2551

1

2

7

45

1%

MF-LF

1/16W

10K

402

R2598

1 2

1%

MF-LF

1/16W

10K

402

R2546

1 2

10K

MF-LF

402

5%

1/16W

R2532

2

1

402

1/16W

5%

MF-LF

10K

R2533

2

1

1/16W MF-LF

10K

402

5%

R2535

2

1

1/16W

402

10K

5%

MF-LF

R2547

2

1

100K

402

5% 1/16W MF-LF

R2524

1

2

10K

1/16W MF-LF

1%

402

R2530

1 2

10K

1/16W MF-LF

1%

402

R2531

1 2

MF-LF

1/16W

5%

100K

402

R2514

2

1

MF-LF

10K

1/16W

1%

402

R2596

1 2

10K

1/16W MF-LF

1%

402

R2597

1 2

A.0.0

25 92

051-7431

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

SB Pwr Mgt, GPIO, Clink

SB_SCLOCK

PM_STPPCI_L

PCIE_WAKE_L INT_SERIRQ

PM_CLKRUN_L

PM_STPCPU_L

PP3V3_S0 PP3V3_S5

EXTGPU_RST_L

PP3V3_S0

SB_GPIO6

ARB_DETECT_L FWH_MFG_MODE

LINDACARD_GPIO

PP3V3_S5

SB_CLINK_VREF0

SB_GPIO36 SB_CRT_TVOUT_MUX_L

PM_SB_PWROK

PM_RI_L

CLINK_NB_RESET_L

PP3V3_S5

SB_CLK48M_USBCTLR SUS_CLK_SB

TP_CLINK_WLAN_RESET_L

PM_PWRBTN_L

SMBUS_SB_ME_SCL

SMBUS_SB_SCL

PM_DPRSLPVR

PM_RI_L

PM_BATLOW_L

SB_GPIO10_CL1

LAN_PHYPC

SB_GPIO14_CL2

PP3V3_S0

SMBUS_SB_SDA

SMBUS_SB_ME_SDA

PM_SYSRST_L

TP_PM_SLP_S4_L PM_SLP_S5_L

PM_SB_PWROK

PM_S4_STATE_L

PM_BATLOW_L

TP_CLINK_WLAN_CLK

CLINK_NB_DATA

PM_BMBUSY_L LINDACARD_GPIO

NB_SB_SYNC_L

PM_SUS_STAT_L

VR_PWRGD_CLKEN

SB_CLK14P3M_TIMER

PM_SLP_S3_L

WOL_EN

SB_GPIO10_CL1

TP_CLINK_WLAN_DATA

SATA_B_DET_L

PCI_PME_FW_L

TP_SB_TP7

SB_GPIO6

LAN_PHYPC EXTGPU_RST_L

TP_SB_GPIO20

SATA_B_PWR_EN_L FWH_MFG_MODE SB_SATA_CLKREQ_L

TP_SB_TP3

SATA_B_PWR_EN_L

PP3V3_S5

PCI_PME_FW_L

CLK_PWRGD

PM_RSMRST_L

PM_LAN_ENABLE

SB_CLINK_VREF1

SB_GPIO14_CL2

CLINK_NB_CLK

TP_PM_SLP_M_L

ARB_DETECT_L

RSVD_EXTGPU_LVDS_EN

PM_THRM_L

SB_SDATAOUT<1>

SB_SDATAOUT<0>

IPHS_SW_BIAS_EN_L

SB_SPKR

SMC_WAKE_SCI_L

SMC_RUNTIME_SCI_L

SB_GPIO18

91

82

65

59

58

53

52

51

50

48

47

46

42

32

31

91

31

91

31

91

30

76

30

76

30

76

29

65

29

65

29

65

28

60

28

60

28

60

27

58

27

58

27

58

26

56

26

56

26

56

25

48

25

48

25

48

24

46

24

46

24

46

23

28

23

28

23

28

21

27

21

27

21

27

19

26

19

26

19

26

16

25

16

47

25

16

25

13

24

28

13

25

24

45

13

24

38

34

8

25

8

25

7

8

87

8

25

8

36

25

8

25

87

25

9

VSS

VSS_NCTF

VSS

(5 OF 6)

VCC1_5_B

V5REF_SUS

VCCDMIPLL

VCC_DMI

VCC3_3

VCC1_05

V5REF

VCCCL1_5

VCCGLANPLL

VCC3_3

VCC1_5_A

VCC3_3

VCCHDA

VCCSUS1_5

VCCSUS3_3

V_CPU_IO

VCC3_3

VCCSUSHDA

VCC1_5_A

VCC3_3

VCCSATAPLL

VCCGLAN3_3

VCCSUS3_3

VCCLAN3_3

VCCCL1_05

VCCSUS1_05

VCCSUS1_5

VCCSUS3_3

VCCA3GP

VCCGLAN1_5

VCCCL3_3

VCCLAN1_05

VCC1_5_A24

VCC1_5_A

VCCRTC

VCC1_5_A

VCCUSBPLL

VCC1_5_A

GLAN POWER

USB CORE

ATX ARX

(6 OF 6)

VCCPSUS

IDE

COREVCCP CORE

PCI

VCCPUSB

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

19 mA S0, 51 mA M1 & WOL

1 mA

80 mA

23 mA

10 mA

19 mA S0, 63 mA M1 & WOL

(VCC1_5_A total)

47 mA

1080 mA

32 mA

(VCCSUS3_3 total)

1 mA S3-S5

44 mA S3-S5

11 mA S0,

117 mA S0,

442 mA

(VCC3_3 total)

1 mA

50 mA

23 mA

1130 mA

NOTE: VccHDA and VccSusHDA can be 1.5V or 3.3V depending on VIO of HD Audio interface.

Current figures provided assume 1.5V.

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

657 mA

1 mA S0-S5

1 mA

6 uA S0-G3

1uF

6.3V CERM

10%

402

C2600

1

2

402

CERM

10V

20%

0.1uF

C2601

1

2

ICH8M

BGA

OMIT

U2300

A23

A5

AC26

L13 L15 L26 L27 L4 L5 M12 M13 M14 M15

AC27

M16 M17 M23 M28 M29 M3 N1 N11 N12 N13

AD17

N14 N15 N16 N17 N18 N26 N27 N4 N5 N6

AD20

P12 P13 P14 P15 P16 P17 P23 P28 P29 R11

AD28

R12 R13 R14 R15 R16 R17 R18 R28 R4 T12

AD29

T13 T14 T15 T16 T17 T2 U12 U13 U14 U15

AD3

U16 U17 U23 U26 U27 U3 U5 V13 V15 V28

AD4

V29 W2 W26 W27 Y28 Y29 Y4 AB4 AB23 AB5

AD6

AB6 AD5 U4 W24

AE1

AA2

AE12

AE2

AE22

AD1

AE25

AE5 AE6

AE9 AF14 AF16

AA7

AF18

AF3

AF4

AG5

AG6 AH10 AH13 AH16 AH19

AH2

A25

AF28 AH22 AH24 AH26

AH3

AH4

AH8

AJ5

B11

B14

AB1

B17

B2 B20 B22

B8 C24 C26 C27

C6 D12

AB24

D15 D18

D2

D4 E21 E24

E4

E9 F15 E23

AC11

F28 F29

F7

G1

E2 G10 G13 G19 G23 G25

AC14

G26 G27 H25 H28 H29

H3

H6

J1 J25 J26

AC25

J27

J4

J5 K23 K28 K29

K3

K6

K7 L1

A1 A2

B1 B29

A28 A29 AH1 AH29 AJ1 AJ2 AJ28 AJ29

BGA

ICH8M

OMIT

U2300

A16

T7

G4

AC23 AC24

A13 B13

L14 L16 L17 L18 M11 M18 P11 P18 T11 T18

C13

U18 V17 V14 V11 U11 V18 V16 V12

C14 D14 E14 F14 G14 L11 L12

AE7 AF7

AC10

AC9

AA5 AA6

G12 G17

H7

AC7 AD7

F1

AG7

L6 L7 M6 M7

W23

AH7 AJ7

AC1 AC2 AC3 AC4 AC5

AA25 AA26

E27 F24 F25 G24 H23 H24 J23 J24 K24 K25

AA27

L23 L24 L25 M24 M25 N23 N24 N25 P24 P25

AB27

R24 R25 R26 R27 T23 T24 T27 T28 T29 U24

AB28

W25 V24 U25 Y25 V25 V23

AB29

D28 D29 E25 E26

AF29

AD2

W6 W7 Y7

A8 B15 B18 B4 B9 C15 D13

AC8

D5 E10 E7 F11

AD8 AE8 AF8

AA3 U7 V7 W1

AE28 AE29

G22

A22

F20 G21

R29

B27 A27 B28 B26 A26

B25

A24

AC12

F17 G18

F19 G20

AD25

AJ6

J6 AF20

AC16

J7

C3

AC18

P1 P2 P3 P4 P5 R1 R3 R5 R6

AC21 AC22 AG20 AH28

P6 P7 C1 N7

AD11

D1

SYNC_MASTER=T9_NOME

051-7431

9226

A.0.0

SYNC_DATE=01/25/2007

SB Power & Ground

PP1V05_S0

PP3V3_S0

PP1V5_S0_SB_VCC1_5_B

PP5V_S0_SB_V5REF

VCCCL1_5V

PP1V05_S0

PP1V25_S0_ISNS

PP1V5_S0

PP3V3_S5

PP3V3_S0

PP1V5_S0

PP3V3_S0

PP1V5_S0_SB_VCC1_5_B

PP5V_S5_SB_V5REF_SUS

PP1V5_S0_SB_VCCDMIPLL

PP1V5_S0

PP3V3_S0

TP_VCCSUS1_5_INTERNAL_REG1

PP3V3_S0

PP3V3_S5

PP3V3_S0

PP1V5_S0_SB_VCCSATAPLL

PP3V3_S0

TP_VCCCL1_05_INTERNAL_REG

TP_VCCSUS1_05_INTERNAL_REG1

TP_VCCSUS1_5_INTERNAL_REG2

TP_VCCSUS1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG2

TP_VCCLAN1_05_INTERNAL_REG1

PP3V3_G3_SB_RTC

PP1V5_S0

PP3V3_S0

91

82

65

59

58

53

52

51

50

48

47

46

61

42

61

42

50

32

50

32

46

31

46

91

31

91

31

30

76

30

76

30

27

29

27

65

29

65

29

26

28

26

60

28

60

28

23

27

23

58

27

58

27

21

26

21

72

91

56

26

91

26

91

26

56

26

91

26

19

25

19

69

63

48

25

63

25

63

25

48

25

63

25

18

24

18

67

34

46

24

34

24

34

24

46

24

34

24

14

23

14

65

27

28

23

27

23

27

23

28

23

27

23

13

21

13

50

26

27

21

26

21

26

21

27

21

26

21

12

19

27

12

27

22

26

19

22

19

27

22

19

26

19

22

19

11

16

26

11

21

12

25

16

12

16

26

12

16

25

16

28

12

16

10

13

24

10

19

11

24

13

11

13

24

11

13

24

13

27

11

13

8

23

27

8

23

27

8

27

8

23

8

NCNC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

PLACE C2736 NEAR PIN B27..A26

PLACE CAPS NEAR PINS AC18..AH28

ICH USB/VCCSUS3_3 BYPASS

(ICH IO,LOGIC 1.5V PWR)

PLACEMENT NOTE:

OR 3.56MM ON PRIMARY NEAR PIN AJ6

NEAR PINS A8 ... F11

(ICH SUSPEND USB 3.3V PWR)

ICH VCCSUS3_3 BYPASS

PLACEMENT NOTE:

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2704 < 2.54MM OF PIN G4 OF SB

3.56MM ON PRIMARY NEAR PIN AC1..AC5

PLACEMENT NOTE:

ICH V5REF_SUS Filter & Follower

PLACEMENT NOTE:

ICH VCCGLANPLL Filter

PLACEMENT NOTE:

(ICH GLAN PLL PWR)

ICH VCC1_5_A/ARX BYPASS (ICH LOGIC&IO[ARX] 1.5V PWR)

(ICH LOGIC&IO[ATX] 1.5V PWR)

ICH VCC1_5_A/ATX BYPASS

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS AE7..AJ7

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

PLACEMENT NOTE:

(ICH USB CORE 1.5V PWR)

PLACE < 2.54MM OF SB ON SECONDARY OR

ICH USB CORE/VCC1_5_A BYPASS

3.56MM ON PRIMARY NEAR PINS F1..M7

PLACE C2715 NEAR PIN D1 OF SB

ICH VCCUSBPLL BYPASS (ICH USB PLL 1.5V PWR)

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AE29

PLACE NEAR PINS AC23,AC24 OF SB

PLACEMENT NOTE:

10 mA

(ICH CORE 1.05V PWR)

ICH CORE/VCC1_05 BYPASS

1130 mA

1 mA

50 mA

(ICH CPU I/O 1.05V PWR)

ICH V_CPU_IO BYPASS

PLACE CAPS AT EDGE OF SB

PLACEMENT NOTE:

F19 AND G20

PLACE CAP UNDER SB NEAR PINS

ICH VCC_PAUX/VCCLAN3_3 BYPASS (ICH LAN I/F BUFFER 3.3V PWR)

ICH IDE/VCC3_3 BYPASS (ICH IDE I/O 3.3V PWR)

(ICH PCI I/O 3.3V PWR)

ICH PCI/VCC3_3 BYPASS

(ICH INTEL HDA CORE 3.3V/1.5V PWR)

ICH VCCHDA BYPASS

PLACEMENT NOTE:

PLACE CAP < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN AF29

DISTRIBUTE IN PCI SECTION OF SB

PLACEMENT NOTE:

OR 3.56MM ON PRIMARY NEAR PIN AC12

PLACE < 2.54MM OF SB ON SECONDARY

OR 3.56MM ON PRIMARY NEAR PIN AD11

PLACE < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

OR 3.56MM ON PRIMARY NEAR PIN AD2

PLACE < 2.54MM OF SB ON SECONDARY

PLACEMENT NOTE:

PLACE < 2.54MM OF SB ON SECONDARY OR

3.56MM ON PRIMARY NEAR PINS AA3...Y7

(VCC3_3 Total)

1 mA S0-S5

1 mA

PLACEMENT NOTE:

837 mA

PLACE CAPS < 2.54MM OF SB ON SECONDARY OR 3.56MM ON PRIMARY NEAR PIN A24

SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE CAPS < 2.54MM OF SB ON

PLACEMENT NOTE:

23 mA

47 mA

33 mA

ICH VCCDMIPLL Filter (ICH DMI PLL PWR)

23 mA

ICH VCCSATAPLL Filter (ICH SATA PLL PWR)

33 mA

47 mA

ICH VCC1_5_B BYPASS

657 mA

(VCC1_5_A Total)

1080 mA

(ICH RTC 3.3V PWR)

ICH VCCRTC BYPASS

PLACEMENT NOTE: PLACE CAP NEAR PINS

(ICH SUSPEND 3.3V PWR)

PLACE CAPS NEAR PIN AD25 OF SB

P6..R6

(VCCSUS3_3 Total)

442 mA

44 mA S3-S5

117 mA S0 /

Current numbers from ICH8M Max Power Estimates Rev 2.0, doc #610194.

0.6 uA G3

(@ 1.5V)

32 mA

11 mA S0 / 1 mA S3-S5

ICH VCCSUSHDA BYPASS (ICH INTEL HDA SUSPEND 3.3V/1.5V PWR)

114 mA M1 & WOL

38 mA S0 /

PLACE CAPS < 2.54MM OF SB ON SECONDARY

(ICH Reference for 5V Tolerance on Resume Well Inputs)

PLACEMENT NOTE:

1 mA S0-S5

1 mA

PLACE C2700 & C2705-07 < 2.54MM OF SB ON SECONDARY SIDE OR 3.56MM ON PRIMARY DISTRIBUTED BETWEEN AA25..V23

ON SECONDARY SIDE OR 3.56MM ON PRIMARY

PLACE C2703 < 2.54MM OF PIN A16..T7 OF SB

(ICH Reference for 5V Tolerance on Core Well Inputs)

ICH V5REF Filter & Follower

80 mA

CASE-B2-HF

2.5V POLY

20%

CRITICAL

220UF

C2700

1

2

0.1UF

10% 16V

402

X5R

C2712

1

2

603

5%

MF-LF

1/10W

1

R2700

1 2

603

CERM

20%

6.3V

4.7UF

C2724

1

2

X5R 402

16V

10%

0.1UF

C2722

1

2

BAT54DW

SOT-363

D2702

1

6

5

BAT54DW

SOT-363

D2702

4

3

2

1.0UH-0.5A

1210

L2703

1 2

603

10UF

20%

6.3V X5R

C2735

1

2

X5R 402

10%

1UF

10V

C2703

1

2

6.3V CERM 402

10%

1UF

C2711

1

2

6.3V

20% CERM1

603

2.2uF

C2732

1

2

4.7uF

603

CERM

20%

6.3V

C2736

1

2

6.3V

20%

603

CERM

4.7uF

C2733

1

2

0.1UF

10% 16V

402

X5R

C2741

1

2

X5R 402

16V

10%

0.1UF

C2738

1

2

0805

10UH-100MA

L2702

1 2

X5R 402

16V

10%

0.1UF

C2737

1

2

CERM-X5R

20%

805-3

22UF

6.3V

C2739

1

2

0.1UF

10% 16V

402

X5R

C2702

1

2

402

0

1/16W MF-LF

5%

R2735

1 2

402

5% 1/16W MF-LF

100

R2702

2

1

402

5% 1/16W MF-LF

10

R2701

2

1

10% 402

X5R

16V

0.1UF

C2704

1

2

0805-1

FERR-330-OHM-1.5A

L2700

1 2

805-3

CERM-X5R

22UF

20%

6.3V

C2705

805-3

CERM-X5R

6.3V

22UF

20%

C2706

20%

6.3V 603

2.2UF

CERM1

C2707

10%

0.01UF

16V CERM 402

C2701

1

2

X5R

6.3V

20%

10UF

603

C2708

1

2

10%

1UF

402

CERM

6.3V

C2717

1UF

10% 402

CERM

6.3V

C2714

1

2

0.1UF

10% 16V

402

X5R

C2715

1

2

0.1UF

10% 16V

402

X5R

C2718

1

2

X5R 402

16V

10%

0.1UF

C2719

1

2

0.1UF

10% 16V

402

X5R

C2721

1

2

X5R 402

16V

10%

0.1UF

C2723

1

2

0.1UF

10% 16V

402

X5R

C2725

1

2

0.1UF

10% 16V

402

X5R

C2726

1

2

0.1UF

10% 16V

402

X5R

C2727

1

2

0.1UF

10% 16V

402

X5R

C2728

1

2

X5R 402

16V

10%

0.1UF

C2729

1

2

X5R 402

16V

10%

0.1UF

C2730

1

2

X5R 402

16V

10%

0.1UF

C2734

1

2

0.1UF

16V

10% 402

X5R

C2731

1

2

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

SB Decoupling

051-7431

A.0.0

9227

PP5V_S0

PP3V3_S5

PP3V3_S0

PP3V3_S5

PP3V3_G3_SB_RTC

PP3V3_S5

PP1V5_S0_SB_VCCSATAPLL

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM VOLTAGE=1.5V

PP1V5_S0_SB_VCCDMIPLL

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP1V5_S0_SB_VCCSATAPLL_F

PP1V5_S0_SB_VCCDMIPLL_F

VOLTAGE=1.5V

MIN_LINE_WIDTH=0.5MM MIN_NECK_WIDTH=0.25MM

PP5V_S0_SB_V5REF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.25MM VOLTAGE=5V

VOLTAGE=5V

MIN_NECK_WIDTH=0.25MM

PP5V_S5_SB_V5REF_SUS

MIN_LINE_WIDTH=0.3MM

PP3V3_S0

PP3V3_S5

PP3V3_S0

PP1V05_S0

PP1V25_S0_ISNS

PP1V5_S0

PP5V_S5

PP1V5_S0_SB_VCC1_5_B

VOLTAGE=1.5V MAKE_BASE=TRUE

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.2 mm

PP1V5_S0_SB_VCC1_5_B

91

82

65

59

58

53

52

51

50

48

47

46

42

61

32

50

91

31

91

31

91

31

46

82

76

30

76

30

76

30

81

65

29

65

29

65

29

27

80

60

28

60

28

60

28

26

79

65

58

27

58

27

58

27

23

75

59

56

26

56

26

56

26

21

72

91

65

58

48

25

48

25

48

25

19

69

63

54

46

24

46

24

46

24

18

67

34

62

52

28

23

28

23

28

23

14

65

27

61

49

27

21

27

21

27

21

13

50

26

60

47

26

19

26

19

26

19

12

26

22

58

27

42

25

16

25

28

25

16

25

16

11

21

12

43

26

8

24

13

24

26

24

13

24

13

10

19

11

42

24

7

8

23

8

26

8

23

OUT

IN

OUT

IN

NCNC

IN

OUT

IN

OUT

IN

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

SB RTC Crystal

NOTE: R2800 and D2805 form the double-

CPU VCore ForcePSI

NC

518S0487

fault protection for RTC battery.

RTC Power Sources

NC

Unbuffered

NC

Platform Reset Connections

NC

VRMPWRGD Inverter

PWROK Circuit

Coin-Cell Connector

System Reset "Button"

PCI Reset Connections

to solder a reset button.

This part is never stuffed, it provides a set of pads on the board to short or

402

20K

MF-LF

5%

1/16W

R2806

1 2

23

402

0.1UF

10V

20% CERM

C2830

1

2

402

10%

1UF

CERM

6.3V

C2806

1

2

10 13

5%

402

1M

1/16W MF-LF

R2805

1

2

7

25 45

1/16W 402

5% MF-LF

10K

R2825

1

2

1/16W

402

MF-LF

1K

5%

R2800

2 1

12pF

402

50V

5%

CERM

C2810

1 2

CERM

402

12pF

50V

5%

C2811

1 2

CRITICAL

SM-2

32.768K

Y2810

2 4

1 3

402

1/16W

5%

MF-LF

0

R2810

1 2

402

5%

10M

MF-LF

1/16W

R2811

1

2

7 9

24 82

ITP&XDP

402

MF-LF

1/16W

1K

5%

R2826

1 2

BAT54DW

SOT-363

D2805

1

4

6

3

5

2

5%

100

MF-LF

1/16W

402

R2862

1 2

402

MF-LF

0

5%

1/16W

R2863

1 2

100

1/16W

5%

402

MF-LF

R2864

1 2

402

1/16W

5%

MF-LF

100

R2860

1 2

402

0.1UF

CERM

20% 10V

C2840

1

2

7 9

16 59

45 46 65

7 9

25

0.1UF

20% 10V

CERM

402

C2880

1

2

402

MF-LF

5%

1/16W

0

R2881

1 2

7

16

7

47

7

45

34

7

67

SC70

MC74VHC1G08

U2880

3

2

1

4

5

MC74VHC1G08

SC70

U2840

3

2

1

4

5

MC74VHC1G00

SC70-5

U2830

3

2

1

4

5

SILK_PART=SYS RST

603

1/10W

0

5%

OMIT

MF-LF

R2820

1

2

38

MF-LF

1/16W

5%

0

402

R2861

1 2

38

100

MF-LF

5%

1/16W

402

R2890

1 2

7

24

10 28 59 10 28 59

59

7

25

10K

MF-LF

5% 1/16W

402

R2840

1

2

MF-LF

1/16W

402

5%

10K

R2841

1

2

M-RT-SM

CRITICAL

BM02B-ACHKS-GAN-TF-LF-SN-M

J2800

3

4

1 2

1/16W

0

MF-LF

402

5%

R2865

1 2

35

25

7

23

CERM

402

6.3V

1UF

10%

C2805

1

2

SB Misc

SYNC_MASTER=M87_MLB

92

A.0.0

051-7431

28

SYNC_DATE=08/28/2007

PP3V3_S0

GPU_RESET_R_L

EXTGPU_RST_L

PP3V42_G3H

PP3V3_S0

PCI_RST_L

ENET_RESET_L

DEBUG_RESET_L

PP3V3_S5

PCI_FW_RST_L

GPU_RESET_L

PP3V3_S0

SB_RTC_X2

VR_PWRGOOD_DELAY

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PPVBATT_G3_RTC

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PPVBATT_G3_RTC_R

MIN_LINE_WIDTH=0.3 mm

PM_SYSRST_L

XDP_DBRESET_L

SB_RTC_X1

LIO_PLT_RST_L

NB_RESET_L

FW_PLT_RST_L

PP3V3_G3_SB_RTC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.3 mm MIN_NECK_WIDTH=0.2 mm

SB_RTC_RST_L

SB_SM_INTRUDER_L

SMC_LRESET_L

VR_PWRGD_CLKEN_L

ALL_SYS_PWRGD

VR_PWRGD_CLKEN

SB_RTC_X1_R

CPU_PSI_LCPU_PSI_L

MAKE_BASE=TRUE

PM_SB_PWROK

PLT_RST_L

MAKE_BASE=TRUE

91

91 91

82

82 82

65

65 65

59

59 59

58

58 58

53

53 53

52

52 52

51

51 51

50

50 50

48

48 48

47

47 47

46

46 46

42

42 42

32

32 32

31

31 31

30

91

30

29

76

29

28

81

28

65

28

27

66

27

60

27

26

65

26

58

26

25

57

25

56

25

24

48

24

48

24

23

47

23

46

23

21

46

21

27

21

19

45

19

26

19

16

43

16

25

16

27

13

8

13

24

13

26

8

7

8

23

7

23

IN IN

OUT OUT

OUT

IN

OUT

OUT OUT OUT OUT

IN

BI

OUT

IN

BI

OUT

IN

OUT

IN

OUT

OUT OUT

IN

OUT

VSS_PCI

CLKREQ_7*

CLKREQ_8*

GPU_STOP*

REF_0/FS_C/TEST_SEL

48M/FS_A

DOT_96/27M

DOT_96*/27M_SS

SRC_8*

SRC_8

PCI_5/FCT_SEL

PCIF_0/ITP_EN

VDD_PCI

VDD_48

THRM_PAD

SRC_4*

CLKREQ_3*

SRC_3

SRC_0/LCD_CLK

SRC_0*/LCD_CLK*

CPU_1_MCH*

CPU_1_MCH

CPU_ITP*/SRC_10*

CPU_ITP/SRC_10

VSS_SRC

VSS_REF

VSS_CPU

VSS_48

SDA

PCIF_1

PCI_4

PCI_3

PCI_2

PCI_1

VSS_A

XTAL_OUT

CLKREQ_6*

CLKREQ_5*

CLKREQ_4*

CLKREQ_1*

SCL

CPU_0

SRC_1

SRC_2*

SRC_2

SRC_4

SRC_5*

SRC_5

SRC_7*

SRC_7

SRC_6*

SRC_6

VDD_REF

CPU_0*

SRC_3*

CPU_STOP*

PCI_STOP*

XTAL_IN

VDD_A

FS_B/TEST_MODE

VDD_CPU

SRC_1*

CKPWRGD/PD*

VDD_SRC

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FW PCI 33MHz

(INT PD*)

(INT PU*)

0 1

FCT_SEL

27M

DOT_96+

PIN 6

27M w/SS

DOT_96-

PIN 7

PIN 10

LCD_CLK+

SRC_0+ SRC_0-

PIN 11

LCD_CLK-

(For Internal Graphics) (For External Graphics)

TP or GPU PGOOD

(INT PU*)

GMCH Display PLL A 96MHz (Int GFX)

NOTE: Pin 40 was PGMODE on SLG8LP537. Do not pull low

ICH PCI 33MHz

(INT PU*)

Spare 100MHz

From ICH

ICH SIO/LPC/REF 14.318MHz

ICH USB/Audio 48MHz

(Or 27MHz Spread & Non-Spread for Ext GFX)

PCIe Mini Card (AirPort) 100MHz

GMCH DMI/PCIe 100MHz

Spare 33MHz

Linda/LPC+ 33MHz

ExpressCard / Spare 100MHz

SMC LPC 33MHz

GMCH Display PLL B 100MHz (Int GFX)

From ICH

ICH DMI/PCIe 100MHz

ICH SATA 100MHz

GPU PCIe 100MHz (Ext GFX)

ITP/XDP Host Clock (FSB/4)

GMCH Host Clock (FSB/4)

One 0.1uF per power pin (place at pin).

CPU Host Clock (FSB/4)

CPU MHz

133.3

1

0

200.0

0

0 1

RSVD

(400.0)

100.0

(333.3)

166.6

1

0

1

0 0

00

0 1

0

1

0

1

One 10uF cap per rail.

FS_C FS_B FS_A

(266.6)

NEED TO CHECK CAP VALUE

on SLG8LP537 or device is set to CK410M mode.

Yukon PCIe 100MHz

(*) CLKREQ# internal pull-ups/downs only on SLG2AP101, not SLG8LP537.

NOTE: Pin 53 was REF_1 on SLG8LP537.

6.3V

20% 603

X5R

10UF

C2910

1

2

0402

FERR-120-OHM-1.5A

L2902

1 2

16V

10%

402

X5R

0.1UF

C2912

1

2

16V

10%

402

X5R

0.1UF

C2913

1

2

16V

10%

402

X5R

0.1UF

C2915

1

2

16V

10% 402

X5R

0.1UF

C2909

1

2

7

25 30

7

25 30

7

10 30 88

7

10 30 88

7

14 30 88

7

14 30 88

13 30 83 88

30 88

9

30 67 88

9

30 67 88

23 30 88

7

16 30 88

23 30 88

30 34 88

7

16 30 88

30 34 88

30 88

25

30 88

402

CERM

50V

5%

18pF

C2990

1

2

50V

5%

CERM

18pF

402

C2989

1

2

30 88

25 31 32 34 48 86

6.3V

20%

603

X5R

10UF

C2907

1

2

16V

10%

402

X5R

0.1UF

C2908

1

2

30 88

30

30 88

16V

10%

402

X5R

0.1UF

C2906

1

2

16V

10%

402

X5R

0.1UF

C2905

1

2

16V

10%

402

X5R

0.1UF

C2904

1

2

16V

10%

402

X5R

0.1UF

C2903

1

2

6.3V

10% 402

CERM

1UF

C2911

1

2

6.3V

20%

603

X5R

10UF

C2901

1

2

16V

10%

402

X5R

0.1UF

C2902

1

2

0402

FERR-120-OHM-1.5A

L2901

1 2

6.3V

10%

402

CERM

1UF

C2900

1

2

1/16W

5%

402

MF-LF

2.2

R2901

1 2

1/16W

5%

402

MF-LF

1

R2902

1 2

6.3V

20%

603

X5R

10UF

C2914

1

2

402

MF-LF

2.2

1/16W

5%

R2900

1 2

30 35 88

30

30 34

30 35

1/16W

5%

402

MF-LF

10K

XDP

R2903

1

2

30 88

25

30 88

30 34 88

24 30 88

7

16

5X3.2-SM

14.31818

CRITICAL

Y2901

1 2

6.3V

20%

603

X5R

10UF

C2916

1

2

0402

FERR-120-OHM-1.5A

L2903

1 2

30 65

OMIT

SLG2AP101

QFN

U2900

4

2

9

59

20

60

25

40

34

45

44

42

41

37

36

55

6

7

8

53

57 58 63 64 65

56

68

1

54

47 48

10

11

13

14

15

16

18

19

21

22

23

24

26

27

29

30

33

32

69

33843616749121728

35

5

39

46

62 66

52

31

51 50

30

051-7431

29 92

A.0.0

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

Clock (CK505)

ENET_CLKREQ_L

PCIE_CLK100M_MINI_N

PP3V3_S0

CK505_PCIF0_CLK_ITPEN

CK505_PCI5_CLK_FCTSEL

TP_PCIE_CLK100M_SRC7P TP_CK505_CLKREQ7_L

CK505_XTAL_OUT

NB_CLK100M_PCIE_N

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDDA_R

PP3V3_S0

S0PGOOD_PWROK

CK505_REF0_FSC

CK505_48M_FSA

CLK_PWRGD

CK505_CLK27M

CK505_CLK27M_SS

PCIE_CLK100M_ENET_N PCIE_CLK100M_ENET_P

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDD48

SB_CLK100M_SATA_N

EXCARD_CLKREQ_L

PCIE_CLK100M_EXCARD_P

TP_NB_CLK100M_DPLLSS_P

TP_NB_CLK100M_DPLLSS_N

FSB_CLK_NB_N FSB_CLK_NB_P

XDP_CLK_N XDP_CLK_P

SMBUS_SB_SDA

CK505_PCIF1_CLK

TP_CK505_PCI4_CLK

CK505_PCI3_CLK

TP_CK505_PCI2_CLK

CK505_PCI1_CLK

NB_CLKREQ_L

SB_SATA_CLKREQ_L

TP_CK505_CLKREQ1_L

FSB_CLK_CPU_P

PEG_CLK100M_GPU_P

PEG_CLK100M_GPU_N

SB_CLK100M_DMI_N SB_CLK100M_DMI_P

SB_CLK100M_SATA_P

TP_PCIE_CLK100M_SRC7N

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDD_CPU_SRC

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDD_REF

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.5mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDD_PCI

FSB_CLK_CPU_N

PCIE_CLK100M_EXCARD_N

PM_STPCPU_L

PM_STPPCI_L

CK505_FSB_TEST_MODE

CK505_XTAL_IN

MIN_NECK_WIDTH=0.2mm VOLTAGE=3.3V

PP3V3_S0M_CK505_VDDA

MIN_LINE_WIDTH=0.5mm

SMBUS_SB_SCL

NB_CLK100M_PCIE_P

PCIE_CLK100M_MINI_P MINI_CLKREQ_L

91

82

65

59

58

53

52

51

50

48

47

46

42

32

31

30

29

28

27

26

25

24

23

21

19

16

13

8

IN

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

OUT

BI

OUT

IN

OUT

BI

OUT

IN

OUT

IN

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(Note: HOST/SRC/GFX clock termination removed. Silego SL8GLP536 or equiv. support only)

(ITP HOST 167/200MHZ)

(ExpressCard 100MHz)

(ICH8M DMI 100MHZ)

(Int Gfx LVDS 100MHz)

FS_A, FS_B, FS_C (Host clock freq select)

FCT_SEL (GFX clock select)

CK505 Configuration Straps

NO STUFF R3082, R3086 & R3090 for manual CPU clk frequency.

(Only 100-200MHz supported by

(FW 100MHz)

(LINDA/LPC+ LPC 33MHZ)

CLK Termination

(Spare 33MHZ)

(Reserved for TPM PCI 33MHZ)

(GMCH PEG/DMI 100MHZ)

CLKREQ Controls

(SMC PCI 33MHZ)

(FIREWIRE PCI 33MHZ)

(ICH8M PCI 33MHZ)

(Ext GFX Spread 27MHz)

(Ext GFX 27MHz)

(ENET 100MHZ)

(GPU PCIe 100MHz)

(GMCH HOST 167/200MHZ)

(CPU HOST 167/200MHZ)

(TO ICH8M USB 48MHZ)

SLG8LP536 and CY28545-5)

CPU MHz

200.0

166.6

100.0

133.3

(266.6)

(333.3)

(400.0)

FS_AFS_BFS_C

1 RSVD

1

0

1

0

0 1

0

00

0

10

1

0 1

1 1

11

(TO/FROM CK505)

(TO MCH FS_C)

(TO CK505)

(TO MCH FS_B)

(TO/FROM CK505)

(TO ICH8M 14.318MHZ)

(FROM CPU FS_C)

(FROM CPU FS_A)

(FROM CPU FS_B)

0

(ICH8M SATA 100MHZ)

(TO MCH FS_A)

Unused Clocks

(WIRELESS PCIe MINI 100MHZ)

are not shown here).

NB and SATA CLKREQs are not remappable (and thus

CLKREQ# pins. Support for SL8GLP537 or equiv. only.

Silego SLG2AP101 has internal pull-ups on all

GPU Clock Gating

7

10 29 30 88

7

10 29 30 88

7

14 29 30 88

7

14 29 30 88

29 30 88

7

16 29 30 88

7

16 29 30 88

7

16 29 30 88

7

16 29 30 88

29 30 35 88

29 30 35 88 29 30 35 88

29 30 35 88

24 29 30 88

29 88

38 88

45 88

24 88

29 30 34 88

29 30 34 88 29 30 34 88

29 30 34 88

7

47 88 29 88

24 29 30 88

402

10K

MF-LF

1/16W

5%

R3067

1

2

1/16W

5%

402

MF-LF

1K

R3083

1

2

1K

MF-LF

402

5%

1/16W

R3084

1

2

29

29 88

23 29 30 88

MF-LF

1K

402

5%

1/16W

NO STUFF

R3080

1

2

1/16W

5%

MF-LF

0

402

R3082

1 2

10 83

1/16W

5%

402

MF-LF

0

R3086

1 2

MF-LF

1K

402

NO STUFF

1/16W

5%

R3087

1

2

29 30 34 88

7

14 29 30 88

29 30 34 88

9

29 30 67 88

9

29 30 67 88

9

29 30 67 88

9

29 30 67 88

7

14 29 30 88

29 30 88

7

10 29 30 88

25 88

33

1/16W

5%

402

MF-LF

R3032

1 2

29 88

7

10 29 30 88

MF-LF

1/16W

5%

402

1K

R3081

1 2

13 16 83

1K

5%

1/16W

402

MF-LF

R3085

1 2

13 16 83

10 83

1/16W

5%

402

MF-LF

0

R3090

1 2

MF-LF

402

5%

1/16W

1K

NO STUFF

R3088

1

2

1/16W

5%

402

MF-LF

1K

R3091

1

2

13 29 30 83 88

1K

1/16W

5%

402

MF-LF

R3089

1 2

13 16 83

25 88

33

402

1/16W

5%

MF-LF

R3034

1 2

29 88

13 29 30 83 88

33

MF-LF

5%

1/16W

402

R3024

1 2

MF-LF

402

5%

1/16W

33

R3025

1 2

29 30 88

33

402

1/16W

5%

MF-LF

R3026

1 2

402

MF-LF

1/16W

5%

33

R3027

1 2

33

402

1/16W

5%

MF-LF

R3028

1 2

33

5% 1/16W MF-LF

402

R3030

1 2

10K

MF-LF

1/16W

5%

402

R3035

2

1

MF-LF

402

2.2K

5%

1/16W

R3033

2

1

402

5%

MF-LF

1/16W

10K

NO STUFF

R3046

1 2

NO STUFF

402

5%

MF-LF

1/16W

10K

R3047

1 2

29 30 34

7

25 29

7

25 29

29 30 88

29 30 34

29 30 35

29 30

29 30 35

29 30

72 73 90

29 30 65

13 29 30 83 88

SYNC_MASTER=M87_MLB

051-7431

30 92

A.0.0

SYNC_DATE=08/28/2007

Clock Termination

PP3V3_S0

TP_CK505_CLKREQ1_L

MAKE_BASE=TRUE

TP_CK505_CLKREQ7_L

MAKE_BASE=TRUE

TP_CK505_CLKREQ1_L

ENET_CLKREQ_L

EXCARD_CLKREQ_L

MAKE_BASE=TRUE

MINI_CLKREQ_L

MAKE_BASE=TRUE

MINI_CLKREQ_L

TP_CK505_CLKREQ7_L

GPU_CLK27M_SS

GPU_CLK27M

NB_CLK100M_PCIE_N

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_N

TP_CK505_PCI2_CLK

MAKE_BASE=TRUE

PCIE_CLK100M_EXCARD_N

CK505_FSA

CK505_PCI5_CLK_FCTSEL

PP3V3_S0

PEG_CLK100M_GPU_N

PCIE_CLK100M_EXCARD_P

MAKE_BASE=TRUE

CK505_PCIF1_CLK

CK505_CLK27M

MAKE_BASE=TRUE

PP1V05_S0

CK505_FSB_TEST_MODE

CK505_FSC

SB_CLK48M_USBCTLR

CPU_BSEL<0>

CPU_BSEL<1>

CPU_BSEL<2>

CK505_REF0_FSC

SB_CLK14P3M_TIMER

NB_BSEL<0>

CK505_48M_FSA

NB_BSEL<1>

NB_BSEL<2>

CK505_PCI1_CLK

CK505_PCIF0_CLK_ITPEN

CK505_PCI3_CLK

PCI_CLK33M_FW

PCI_CLK33M_SB

PCI_CLK33M_SMC

MAKE_BASE=TRUE

FSB_CLK_CPU_N

FSB_CLK_CPU_P

FSB_CLK_NB_N

FSB_CLK_NB_P

MAKE_BASE=TRUE

FSB_CLK_NB_P

MAKE_BASE=TRUE

FSB_CLK_NB_N

MAKE_BASE=TRUE

XDP_CLK_P

SB_CLK100M_DMI_N

MAKE_BASE=TRUE

SB_CLK100M_DMI_N

PCIE_CLK100M_EXCARD_N

SB_CLK100M_SATA_P

MAKE_BASE=TRUE

SB_CLK100M_SATA_N

SB_CLK100M_SATA_P

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_N

PCIE_CLK100M_MINI_P

TP_PCIE_CLK100M_SRC7N

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_N

MAKE_BASE=TRUE

PCIE_CLK100M_ENET_P

MAKE_BASE=TRUE

XDP_CLK_N

PP1V05_S0

SB_CLK100M_SATA_N

MAKE_BASE=TRUE

TP_PCIE_CLK100M_SRC7P

CK505_CLK27M_SS

MAKE_BASE=TRUE

PM_STPPCI_L

PM_STPCPU_L

MAKE_BASE=TRUE

TP_CK505_PCI4_CLK

TP_CK505_PCI2_CLK

TP_CK505_PCI4_CLK

MAKE_BASE=TRUE

NB_CLK100M_PCIE_P

PP1V05_S0

MAKE_BASE=TRUE

FSB_CLK_CPU_P

MAKE_BASE=TRUE

NB_CLK100M_PCIE_N

MAKE_BASE=TRUE

PCIE_CLK100M_MINI_P

PCIE_CLK100M_EXCARD_P

PEG_CLK100M_GPU_P

PCI_CLK33M_LPCPLUS

CK505_CLK27M_SS

CK505_CLK27M

ENET_CLKREQ_L

EXCARD_CLKREQ_L

ENET_CLKREQ_L

MAKE_BASE=TRUE

PEG_CLK100M_GPU_P

MAKE_BASE=TRUE

SB_CLK100M_DMI_PSB_CLK100M_DMI_P

TP_NB_CLK100M_DPLLSS_N

S0PGOOD_PWROK

MAKE_BASE=TRUE

S0PGOOD_PWROK

NB_CLK100M_PCIE_P

PCIE_CLK100M_ENET_N

PCIE_CLK100M_ENET_P

TP_PCIE_CLK100M_SRC7N

TP_PCIE_CLK100M_SRC7P

MAKE_BASE=TRUE

PEG_CLK100M_GPU_N

TP_NB_CLK100M_DPLLSS_P

MAKE_BASE=TRUE

TP_NB_CLK100M_DPLLSS_N

MAKE_BASE=TRUE

TP_NB_CLK100M_DPLLSS_P

XDP_CLK_N

MAKE_BASE=TRUE

FSB_CLK_CPU_N

XDP_CLK_P

91

82

65

59

58

53

52

51

50

48

47

46

42

61

32

50

31

46

30

29

27

28

26

27

23

26

21

25

19

24

18

23

14

21

13

19

12

35

16

88

16

88

11

88

11

88

11

30

65

88

13

30

13

30

10

30

10

30

10

29

30

8

29

88

8

29

8

88

29

8

29

8

29

VSS7

VSS12

VSS9

KEY

DQ57

DQ51

DQS6

DQ43

DQ42

DQ40

DQ34

DQ1

DQ0

VSS1

DQS0* DQS0 VSS6 DQ2 DQ3

DQ8 DQ9 VSS10 DQS1* DQS1

DQ10 DQ11 VSS14

VSS16 DQ16 DQ17 VSS18 DQS2* DQS2 VSS21 DQ18 DQ19 VSS23 DQ24 DQ25 VSS25 DM3 NC1 VSS27 DQ26 DQ27 VSS29 CKE0 VDD0 NC2 BA2 VDD2 A12 A9 A8 VDD4 A5 A3 A1 VDD6 A10/AP BA0 WE* VDD8 CAS* NC/S1* VDD10 NC/ODT1 VSS31 DQ32 DQ33 VSS33 DQS4* DQS4 VSS36

DQ35 VSS38

DQ41 VSS40 DM5 VSS41

VSS43 DQ48 DQ49 VSS45 NC_TEST VSS47 DQS6*

VSS49 DQ50

VSS51 DQ56

VSS53 DM7 VSS55 DQ58 DQ59 VSS57 SDA SCL VDDSPD

DM6

DQ55

DQ61

DQ46 DQ47

DQ12

DM1

DM0

DQ7

DQ13

VSS11

CK0

CK0*

VSS13

DQ14 DQ15

VSS15

VSS17

DQ20 DQ21

VSS19

NC0 DM2

VSS22

DQ22 DQ23

VSS24

DQ28

DQ29 VSS26 DQS3*

DQS3 VSS28

DQ30

DQ31 VSS30

NC/CKE1

VDD1

NC/A15 NC/A14

VDD3

A11

A7 A6

VDD5

A4 A2 A0

VDD7

BA1

RAS*

S0* VDD9 ODT0

NC/A13

VDD11

NC3

VSS32

DQ36 DQ37

VSS34

DM4

VSS35

DQ38 DQ39

VSS37

DQ44 DQ45

VSS39 DQS5*

DQS5

VSS42

VSS44

DQ52 DQ53

VSS46

CK1 CK1*

VSS48

VSS50

DQ54

VSS52

DQ60

VSS54 DQS7*

DQS7

VSS56

DQ62 DQ63

VSS58

SA0

SA1

DQ5 VSS2

VREF

VSS4

VSS8

VSS0

DQ4

VSS5

DQ6

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

- =PP0V9_S3M_MEM_DIMMVREFA

- =PP1V8_S3M_MEM_A

- =I2C_SODIMMA_SCL

(NONE)

BOM options provided by this page:

- =I2C_SODIMMA_SDA

- =PPSPD_S0M_MEM_A (2.5V - 3.3V)

NC

ADDR=0xA0(WR)/0xA1(RD)

(For return current)

NC

516-0140

NC

DDR2 Bypass Caps

"Factory" (thru-hole) slot

NC

Signal aliases required by this page:

402

6.3V CERM

1UF

10%

C3113

1

2

402

6.3V CERM

1UF

10%

C3112

1

2

10UF

X5R 603

20%

6.3V

C3109

1

2

402

6.3V CERM

1UF

10%

C3111

1

2

10UF

X5R 603

20%

6.3V

C3108

1

2

402

6.3V CERM

1UF

10%

C3110

1

2

402

10%

6.3V CERM

1UF

C3119

1

2

402

10%

6.3V CERM

1UF

C3118

1

2

402

6.3V CERM

1UF

10%

C3117

1

2

402

6.3V CERM

1UF

10%

C3116

1

2

402

10%

6.3V CERM

1UF

C3121

1

2

402

10%

6.3V CERM

1UF

C3120

1

2

402

6.3V CERM

1UF

10%

C3115

1

2

402

6.3V CERM

1UF

10%

C3114

1

2

0.1uF

CERM 402

20% 10V

C3100

1

2

2.2uF

20%

603

CERM1

6.3V

C3101

1

2

F-RT-TH1

DDR2-SODIMM-DUAL

CRITICAL

J3100

102B

105B

90B89B

101B

100B

99B

98B97B

94B

92B

93B

91B

107B

106B

85B

113B

30B 32B

164B 166B

79B

10B

26B

52B

67B

130B

147B

170B

185B

5B

35B 37B

20B 22B

36B 38B

43B 45B

55B 57B

7B

44B 46B

56B 58B

61B 63B

73B 75B

62B 64B

17B

74B 76B

123B 125B

135B 137B

124B 126B

134B 136B

19B

141B 143B

151B 153B

140B 142B

152B 154B

157B 159B

4B

173B 175B

158B 160B

174B 176B

179B 181B

189B 191B

6B

180B 182B

192B 194B

14B 16B

23B 25B

13B

11B

31B

29B

51B

49B

70B

68B

131B

129B

148B

146B

169B

167B

188B

186B

201

202

116B

86B

84B

80B

119B

115B

50B

69B

83B

120B

163B

114B

108B 110B

198B 200B

197B

195B

81B

117B 118B

82B

87B 88B

95B 96B

103B 104B

111B 112B

199B

1B 2B

27B 28B

33B 34B

39B 40B

41B 42B

47B 48B

3B

53B 54B

59B 60B

65B 66B

71B 72B

77B

8B

78B

121B 122B

127B 128B

132B

133B

138B

139B

144B

145B

149B 150B

155B 156B

161B 162B

165B

168B

171B

9B

172B

177B 178B

183B 184B

187B

190B

193B

196B

12B

15B

18B

21B

24B

109B

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

DDR2 SO-DIMM Connector A

051-7431

A.0.0

9231

MEM_A_DM<7>

MEM_A_DQS_N<6>

MEM_A_DQ<22> MEM_A_DQ<19>

PP1V8_S3

MEM_A_A<14>

TP_MEM_A_A<15>

MEM_CKE<1>

MEM_A_DM<3>

MEM_A_A<6>

SMBUS_SB_SCL

MEM_A_DQS_N<4>

MEM_A_A<0>

MEM_A_BS<1>

MEM_A_DQ<14>

MEM_A_DM<1>

MEM_A_DQ<2>

MEM_A_DQ<13>

MEM_A_DQS_N<1> MEM_A_DQS_P<1>

MEM_A_DQ<10> MEM_A_DQ<11>

MEM_A_DQ<7> MEM_A_DQ<0>

MEM_A_DQS_N<0> MEM_A_DQS_P<0>

MEM_A_DQ<4>

MEM_A_DQ<17> MEM_A_DQ<21>

MEM_A_DQS_N<2> MEM_A_DQS_P<2>

MEM_A_DQ<23> MEM_A_DQ<16>

MEM_A_DQ<31> MEM_A_DQ<27>

MEM_A_DQ<30> MEM_A_DQ<28>

MEM_CKE<0>

PP1V8_S3

MEM_A_BS<2>

MEM_A_A<12> MEM_A_A<9> MEM_A_A<8>

MEM_A_A<5> MEM_A_A<3> MEM_A_A<1>

MEM_A_A<10> MEM_A_BS<0> MEM_A_WE_L

MEM_A_CAS_L MEM_CS_L<1>

MEM_ODT<1>

MEM_A_DQ<36> MEM_A_DQ<38>

MEM_A_DQS_P<4>

MEM_A_DQ<37> MEM_A_DQ<34>

MEM_A_DQ<56> MEM_A_DQ<59>

MEM_A_DQ<54>

MEM_A_DQS_P<6>

MEM_A_DQ<48> MEM_A_DQ<53>

MEM_A_DQ<43> MEM_A_DQ<42>

MEM_A_DM<5>

MEM_A_DQ<46> MEM_A_DQ<41>

SMBUS_SB_SDA

PP3V3_S0

MEM_A_RAS_L MEM_CS_L<0>

MEM_ODT<0> MEM_A_A<13>

MEM_A_DQ<39>

MEM_A_DM<4>

MEM_A_DQ<33> MEM_A_DQ<32>

MEM_A_DQ<63> MEM_A_DQ<62>

MEM_A_DQS_N<7> MEM_A_DQS_P<7>

MEM_A_DQ<57> MEM_A_DQ<61>

MEM_A_DQ<55> MEM_A_DQ<50>

MEM_CLK_P<1> MEM_CLK_N<1>

MEM_A_DM<6>

MEM_A_DQ<49> MEM_A_DQ<52>

MEM_A_DQ<45> MEM_A_DQ<40>

MEM_A_DQS_N<5> MEM_A_DQS_P<5>

MEM_A_DQ<44> MEM_A_DQ<47>

MEM_A_DQ<35>

MEM_A_DQ<8> MEM_A_DQ<12>

MEM_A_DQ<3>

MEM_A_DM<0>

MEM_CLK_P<0> MEM_CLK_N<0>

MEM_A_DQ<1> MEM_A_DQ<5>

MEM_A_DQ<18> MEM_A_DQ<20>

PM_EXTTS_L<0> MEM_A_DM<2>

MEM_A_DQ<26> MEM_A_DQ<24>

MEM_A_DQS_N<3> MEM_A_DQS_P<3>

MEM_A_DQ<25> MEM_A_DQ<29>

MEM_A_A<11> MEM_A_A<7>

MEM_A_A<4> MEM_A_A<2>

MEM_A_DQ<9> MEM_A_DQ<15>

MEM_A_DQ<6>

PP0V9_S3_MEM_VREF

PP1V8_S3

MEM_A_DQ<51>

MEM_A_DQ<60>

MEM_A_DQ<58>

91 82 65 59 58 53 52

51 50 48 47 46 42 32 30 29 28

27 26 25

91 91

24

91

62

86

62

86

23

62

50

48

50

48

21

50

38

34

38

34

19

62

38

32

85

32

85

32

85

32

16

85

32

85

31

33

85

33

29

85

33

85

33

31

33

85

29

13

33

85

45

85

33

85

16

31

85

17

8

16

9

16

17

25

17

16

8

17

16

17

25

8

17

16

17

16

17

16

17

16

17

8

17

VSS2

DQS0*

DQ5

VSS0

DQ4

VSS5

DQ6

VSS29

DM0

VSS7

DM1

DQ7

VDD1

DQ30

DQ23

VSS22

NC/ODT1

RAS*

SA1

SA0

VSS58

DQ63

DQ62

VSS56

DQS7

DQS7*

VSS54

DQ60

VSS52

DQ54

VSS50

VSS48

CK1*

CK1

VSS46

DQ53

DQ52

VSS44

VSS42

DQS5

DQS5*

VSS39

DQ45

DQ44

VSS37

DQ39

DQ38

VSS35

DM4

VSS34

DQ37

DQ36

VSS32

NC3

VDD11

NC/A13

ODT0

VDD9

S0*

BA1

VDD7

A0

A2

A4

VDD5

A6

A7

A11

VDD3

NC/A14

NC/A15

NC/CKE1

VSS30

DQ31

DQS3

DQ29

DQ28

VSS24

DQ22

DM2

NC0

VSS19

DQ21

DQ20

VSS17

VSS15

DQ15

DQ14

VSS13

CK0*

CK0

VSS11

DQ13

DQ12

DQ47

DQ46

DQ61

DQ55

DM6

VDDSPD

SCL

SDA

VSS57

DQ59

DQ58

VSS55

DM7

VSS53

DQ56

VSS51

DQ50

VSS49

DQS6*

VSS47

NC_TEST

VSS45

DQ49

DQ48

VSS43

VSS41

DM5

VSS40

DQ41

VSS38

DQ35

VSS36

DQS4

DQS4*

VSS33

DQ33

DQ32

VSS31

VDD10

NC/S1*

CAS*

VDD8

WE*

BA0

A10/AP

VDD6

A1

A3

A5

VDD4

A8

A9

A12

VDD2

BA2

NC2

VDD0

CKE0

DQ27

DQ26

VSS27

NC1

DM3

DQ25

DQ24

VSS23

DQ19

DQ18

VSS21

DQS2

DQS2*

VSS18

DQ17

DQ16

VSS16

VSS14

DQ11

DQ10

VSS12

DQS1

DQS1*

DQ9

DQ8

VSS8

DQ3

DQ2

VSS6

DQS0

VREF

DQ34

DQ40

DQ42 DQ43

DQS6

DQ51

DQ57

KEY

VSS9

DQ1 VSS4

DQ0

VSS1

DQS3*

VSS26

VSS28

VSS25

VSS10

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =PP1V8_S3M_MEM_B

- =PPSPD_S0M_MEM_B (2.5V - 3.3V)

- =PP0V9_S3M_MEM_DIMMVREFB

- =I2C_SODIMMB_SDA

- =I2C_SODIMMB_SCL

(NONE)

BOM options provided by this page:

NC

(For return current)

DDR2 Bypass Caps

516S0471

"Expansion" (surface-mount) slot

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

ADDR=0xA4(WR)/0xA5(RD)

Resistor prevents pwr-gnd short

402

CERM

1UF

10%

6.3V

C3213

1

2

402

CERM

1UF

10%

6.3V

C3212

1

2

6.3V

20% 603

X5R

10UF

C3209

1

2

10V

0.1uF

CERM 402

20%

C3211

1

2

603

20%

6.3V

X5R

10UF

C3208

1

2

402

CERM

1UF

10%

6.3V

C3210

1

2

10V

0.1uF

CERM 402

20%

C3219

1

2

10V

0.1uF

CERM 402

20%

C3218

1

2

0.1uF

CERM 402

20%

10V

C3217

1

2

402

CERM

1UF

10%

6.3V

C3216

1

2

10V

0.1uF

CERM 402

20%

C3221

1

2

0.1uF

10V

CERM 402

20%

C3220

1

2

402

CERM

1UF

10%

6.3V

C3215

1

2

402

CERM

1UF

10%

6.3V

C3214

1

2

1/16W 402

MF-LF

5%

10K

R3200

1

2

0.1uF

CERM 402

20% 10V

C3200

1

2

2.2uF

20%

603

CERM1

6.3V

C3201

1

2

DDR2-SODIMM-DUAL

CRITICAL

F-RT-SM-M9

J3200

102A

105A

90A89A

101A

100A

99A

98A97A

94A

92A

93A

91A

107A

106A

85A

113A

30A 32A

164A 166A

79A

10A

26A

52A

67A

130A

147A

170A

185A

5A

35A 37A

20A 22A

36A 38A

43A 45A

55A 57A

7A

44A 46A

56A 58A

61A 63A

73A 75A

62A 64A

17A

74A 76A

123A 125A

135A 137A

124A 126A

134A 136A

19A

141A 143A

151A 153A

140A 142A

152A 154A

157A 159A

4A

173A 175A

158A 160A

174A 176A

179A 181A

189A 191A

6A

180A 182A

192A 194A

14A 16A

23A 25A

13A

11A

31A

29A

51A

49A

70A

68A

131A

129A

148A

146A

169A

167A

188A

186A

201

202

203

204

116A

86A

84A

80A

119A

115A

50A

69A

83A

120A

163A

114A

108A 110A

198A 200A

197A

195A

81A

117A 118A

82A

87A 88A

95A 96A

103A 104A

111A 112A

199A

1A 2A

27A 28A

33A 34A

39A 40A

41A 42A

47A 48A

3A

53A 54A

59A 60A

65A 66A

71A 72A

77A

8A

78A

121A 122A

127A 128A

132A

133A

138A

139A

144A

145A

149A 150A

155A 156A

161A 162A

165A

168A

171A

9A

172A

177A 178A

183A 184A

187A

190A

193A

196A

12A

15A

18A

21A

24A

109A

9232

051-7431

A.0.0

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

DDR2 SO-DIMM Connector B

MEM_B_CAS_L

MEM_B_DQ<33>

MEM_B_DQS_N<4>

MEM_B_DM<6>

MEM_B_DQ<49>

MEM_B_DQ<44>

MEM_B_A<10>

MEM_CS_L<3>

MEM_ODT<3>

MEM_B_DQ<34>

MEM_B_DQ<36>

MEM_CLK_P<3> MEM_CLK_N<3>

MEM_B_DQ<52>

MEM_B_DQ<46>

SODIMM_B_SA1

PP3V3_S0

MEM_B_DQ<43>

PP3V3_S0

MEM_B_A<7>

MEM_B_A<4>

MEM_B_DQS_P<1>

MEM_B_DQ<12>

MEM_B_DQ<6>

MEM_B_DQS_N<1>

MEM_B_DQ<29>

MEM_B_DQ<31>

MEM_B_DQS_P<3>

MEM_B_DQ<58>

PM_EXTTS_L<1>

MEM_B_DQ<41>

MEM_B_DQS_P<5>

MEM_B_DQS_N<5>

MEM_B_DQ<53>

MEM_B_DQ<54>

MEM_B_DQ<63>

MEM_B_DQS_P<7>

MEM_B_DQS_N<7>

MEM_B_DQ<59>

MEM_B_DQ<56>

MEM_B_DQ<39>

MEM_B_DQ<38>

MEM_B_DM<4>

MEM_B_DQ<37>

MEM_B_DQ<32>

MEM_B_A<13>

PP1V8_S3

MEM_CS_L<2>

MEM_B_A<2>

MEM_B_A<6>

MEM_B_A<14>

TP_MEM_B_A<15>

MEM_B_DQ<17>

MEM_B_DQ<5>

MEM_CLK_N<4>

MEM_CLK_P<4>

MEM_B_DM<0>

MEM_B_DM<1>

MEM_B_DQ<9>

SMBUS_SB_SCL

SMBUS_SB_SDA

MEM_B_DQ<45>

MEM_B_DQ<42>

MEM_B_DM<5>

MEM_B_DQ<47>

MEM_B_DQ<40>

MEM_B_DQ<55>

MEM_B_DQ<50>

MEM_B_DQS_P<6>

MEM_B_DQS_N<6>

MEM_B_DQ<51>

MEM_B_DQ<48>

MEM_B_DQ<62>

MEM_B_DQ<61>

MEM_B_DM<7>

MEM_B_DQ<60>

MEM_B_DQ<57>

MEM_B_DQ<35>

MEM_B_DQS_P<4>

MEM_B_DQ<4>

MEM_B_WE_L

MEM_B_BS<0>

MEM_B_A<1>

MEM_B_A<3>

MEM_B_A<5>

MEM_B_A<8>

MEM_B_A<9>

MEM_B_A<12>

MEM_B_BS<2>

MEM_CKE<3>

MEM_B_DQ<25>

MEM_B_DQ<27>

MEM_B_DM<3>

MEM_B_DQ<24>

MEM_B_DQ<20>

MEM_B_DQS_P<2>

MEM_B_DQS_N<2>

MEM_B_DQ<19>

MEM_B_DQ<21>

MEM_B_DQ<1>

MEM_B_DQS_P<0>

MEM_B_DQS_N<0>

MEM_B_DQ<2>

MEM_B_DQ<7>

MEM_B_DQ<13>

MEM_B_DQ<10>

MEM_B_DQ<15>

MEM_CKE<4>

MEM_B_BS<1>

MEM_B_DQ<0>

MEM_B_DQ<18>

MEM_B_DM<2>

MEM_B_DQ<16>

MEM_B_DQ<26> MEM_B_DQ<28>

MEM_B_DQ<30>

MEM_B_A<11>

MEM_B_A<0>

MEM_B_RAS_L

MEM_ODT<2>

MEM_B_DQ<22>

MEM_B_DQS_N<3>

MEM_B_DQ<11>

MEM_B_DQ<14>

MEM_B_DQ<3>

MEM_B_DQ<8>

PP1V8_S3

MEM_B_DQ<23>

PP0V9_S3_MEM_VREF

PP1V8_S3

91

82

65

59

58

53

52

51

50

48

47

46

42

32

31

30

29

28

27

26

25

24

91 91

91

23

62

86

62

21

50

48

50

19

38

34

38

62

38

85

16

85

32

85

31

85

85 85

85

32

31

32

33

85

33

85

13

85

13

33

85 85

85

45

85

33

31

33

85

29

85

33

85

33

85

33

85

31

85

16

31

17

16

17

16

17

8

17

8

17

17 17

17

16

17

8

16

17

16

9

17

16

17

25

17

16

17

16

17

16

17

8

17

8

IN

IN IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

One cap for each side of every RPAK, one cap for every two discrete resistors

Ensure CS_L and ODT resistors are close to SO-DIMM connector

CERM

20% 10V

0.1uF

402

C3352

1

2

CERM

20% 10V

0.1uF

402

C3356

1

2

CERM

20% 10V

0.1uF

402

C3354

1

2

CERM

20% 10V

0.1uF

402

C3350

1

2

CERM

20% 10V

0.1uF

402

C3360

1

2

CERM

20% 10V

0.1uF

402

C3364

1

2

CERM

20% 10V

0.1uF

402

C3368

1

2

CERM

20% 10V

0.1uF

402

C3366

1

2

20% 10V CERM

0.1uF

402

C3362

1

2

CERM

20% 10V

0.1uF

402

C3358

1

2

17 32 85

16 32 85

SM-LF1/16W

5%

56

RP3358

2 7

SM-LF

5%

1/16W

56

RP3300

3 6

17 31 85

17 32 85

17 31 85

16 32 85

16 31 85

16 32 85

16 31 85

17 32 85

17 31 85

16 31 85

17 31 85

17 32 85

17 31 85

17 32 85

16 32 85

17 32 85

56

5%

MF-LF

402

1/16W

R3370

1 2

16 31 85

SM-LF1/16W

5%

56

RP3346

4 5

56

5%

1/16W SM-LF

RP3330

1 8

SM-LF1/16W

5%

56

RP3342

2 7

SM-LF1/16W

56

5%

RP3330

3 6

1/16W56SM-LF

5%

RP3330

4 5

SM-LF1/16W

5%

56

RP3330

2 7

1/16W

5%

56

SM-LF

RP3342

4 5

56

5%

1/16W SM-LF

RP3342

3 6

1/16W

5%

56

SM-LF

RP3342

1 8

SM-LF1/16W

5%

56

RP3358

4 5

SM-LF

56

5%

1/16W

RP3346

3 6

SM-LF1/16W

5%

56

RP3358

3 6

SM-LF

56

5%

1/16W

RP3346

1 8

SM-LF1/16W

5%

56

RP3346

2 7

SM-LF1/16W

5%

56

RP3358

1 8

SM-LF1/16W

5%

56

RP3366

4 5

1/16W5%SM-LF

56

RP3366

1 8

56

5%

1/16W SM-LF

RP3366

2 7

SM-LF1/16W

5%

56

RP3350

1 8

SM-LF1/16W

5%

56

RP3334

4 5

56

5%

1/16W SM-LF

RP3338

2 7

SM-LF1/16W

5%

56

RP3354

3 6

56

5%

1/16W SM-LF

RP3354

4 5

SM-LF

56

5%

1/16W

RP3310

1 8

56

5%

1/16W SM-LF

RP3310

4 5

56

5%

1/16W SM-LF

RP3310

2 7

SM-LF1/16W

5%

56

RP3362

3 6

SM-LF

56

5%

1/16W

RP3350

4 5

SM-LF1/16W

5%

56

RP3350

2 7

1/16W

5%

56

SM-LF

RP3354

2 7

5%

1/16W SM-LF

56

RP3350

3 6

SM-LF

56

5%

1/16W

RP3354

1 8

56

5%

1/16W SM-LF

RP3338

4 5

SM-LF

56

5%

1/16W

RP3338

3 6

56

5%

1/16W SM-LF

RP3338

1 8

1/16W

5%

56

SM-LF

RP3334

2 7

56

5%

1/16W SM-LF

RP3334

1 8

SM-LF

56

5%

1/16W

RP3334

3 6

SM-LF1/16W

5%

56

RP3300

4 5

1/16W5%SM-LF

56

RP3305

2 7

SM-LF1/16W

5%

56

RP3366

3 6

1/16W56SM-LF

5%

RP3300

2 7

5%

1/16W SM-LF

56

RP3310

3 6

1/16W5%SM-LF

56

RP3362

2 7

56

5%

1/16W SM-LF

RP3305

4 5

1/16W5%SM-LF

56

RP3305

1 8

5%

1/16W SM-LF

56

RP3305

3 6

1/16W

5%

56

SM-LF

RP3300

1 8

SM-LF1/16W

5%

56

RP3362

1 8

SM-LF

56

5%

1/16W

RP3362

4 5

MF-LF1/16W

5%

56

402

R3371

1 2

16 32 85

10V

20% CERM

0.1uF

402

C3370

1

2

17 31 85

16 31 85

17 31 85

16 32 85

CERM

20% 10V

0.1uF

402

C3348

1

2

CERM

20% 10V

0.1uF

402

C3346

1

2

CERM

20% 10V

0.1uF

402

C3336

1

2

CERM

20% 10V

0.1uF

402

C3334

1

2

20%

0.1uF

10V 402

CERM

C3332

1

2

20% 10V

402

CERM

0.1uF

C3330

1

2

402

20% 10V

0.1uF

CERM

C3312

1

2

10V

20% CERM

0.1uF

402

C3310

1

2

CERM

20% 10V

0.1uF

402

C3307

1

2

CERM

20% 10V

0.1uF

402

C3305

1

2

CERM

20% 10V

0.1uF

402

C3302

1

2

CERM

20% 10V

0.1uF

402

C3300

1

2

CERM

20% 10V

0.1uF

402

C3344

1

2

CERM

20% 10V

0.1uF

402

C3342

1

2

CERM

20% 10V

0.1uF

402

C3340

1

2

CERM

20% 10V

0.1uF

402

C3338

1

2

051-7431

9233

A.0.0

Memory Active Termination

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

MEM_B_A<10>

MEM_A_A<3>

MEM_B_A<3>

MEM_B_WE_L

MEM_B_CAS_L

MEM_A_A<9>

MEM_B_A<6>

MEM_B_A<0>

MEM_B_BS<0>

MEM_CS_L<1>

MEM_B_RAS_L

MEM_CS_L<3>

MEM_CS_L<0>

MEM_B_A<5>

MEM_B_A<2>

MEM_B_A<12>

MEM_B_A<1>

MEM_A_A<4>

MEM_A_A<12>

MEM_ODT<2>

MEM_A_A<2>

MEM_A_A<1>

MEM_A_A<0>

MEM_ODT<3>

MEM_A_A<5>

MEM_A_A<14>

MEM_A_BS<0>

MEM_A_RAS_L MEM_A_CAS_L

MEM_A_BS<1>

MEM_A_A<10>

MEM_A_A<13>

MEM_A_A<7> MEM_A_A<8>

MEM_A_A<6>

MEM_ODT<1>

MEM_ODT<0>

MEM_CKE<4>

MEM_CKE<3>

MEM_CKE<0> MEM_CKE<1>

MEM_CS_L<2>

MEM_B_BS<1>

MEM_A_WE_L

MEM_B_A<4>

MEM_B_A<14>

MEM_B_A<13>

MEM_B_A<9>

MEM_B_A<8>

MEM_B_A<7>

MEM_B_BS<2>

MEM_B_A<11>

MEM_A_BS<2>

PP0V9_S0

MEM_A_A<11>

62

8

IN

OUT

BI

IN

IN IN IN

OUT OUT OUT

OUT

OUT OUT OUT OUT

OUT

IN

OUT

IN

BI

BI BI

IN IN

OUT OUT

IN

IN BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Pull-up on LIO, FETs to GND on MLB

516S0348

Output to LIO

NC

Left I/O Board Connector

Place caps close to SB

24 86

24 34 87

24 87

36

9

25

9

24

7

45 54

M-ST-SM

QT500806-L121-9F

CRITICAL

J3400

1

10 11 12 13 14 15 16 17 18 19220 21 22 23 24 25 26 27 28 29330 31 32 33 34 35 36 37 38 39440 41 42 43 44 45 46 47 48 49550 51 52 53 54 55 56 57 58 59660 61 62 63 64 65 66 67 68 69770 71 72 73 74 75 76 77 78 79880

81

82 83

84

9

65

45

7

25 43 45 58 65

45 46 57 66

24

13 24

7

54

29 30

24 46

45 46

25 35

23 86

28

45 46

24 86

29 30 88

24 87

24 34 87

45 48 51 81 88

25 29 31 32 48 86

45 48 51 81 88

10% X5R

0.1uF

16V 402

C3421

12

10% 16V

0.1uF

402

X5R

C3420

12

402

16V

0.1uF

X5R

10%

C3411

12

16V

10%

402

X5R

0.1uF

C3410

12

24 86

SYNC_DATE=(MASTER)

SYNC_MASTER=(MASTER)

Left I/O Board Connector

051-7431

A.0.0

9234

IPHS_SW_INT

SMBUS_SMC_A_S3_SDA

IPHS_SW_BIAS_EN_L

SMBUS_SMC_A_S3_SCL

PP1V5_S0

PCIE_EXCARD_R2D_P

USB_MINI_N USB_MINI_P

PCIE_MINI_R2D_P

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_P

HDA_SYNC

MAKE_BASE=TRUE

PCIE_EXCARD_D2R_N

PCIE_EXCARD_R2D_N

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D_C_N

PCIE_CLK100M_MINI_N PCIE_CLK100M_MINI_P

PCIE_EXCARD_R2D_C_P

USB_EXTC_P

PM_WLAN_EN_L

ALS_GAIN

HDA_SDIN0

USB_EXTC_N

HDA_RST_L

HDA_BIT_CLK

HDA_SDOUT

SMBUS_SB_SDA

SMBUS_SB_SCL

SMC_EXCARD_CP

EXCARD_OC_L

MINI_CLKREQ_L

EXCARD_CLKREQ_L

LIO_PLT_RST_L

USB_EXTC_OC_L

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_D2R_N PCIE_EXCARD_D2R_P

PCIE_EXCARD_R2D_C_N

PCIE_MINI_D2R_P

PCIE_MINI_D2R_N

SMC_BC_ACOK

USB_EXTB_OC_L

PCIE_CLK100M_EXCARD_P

PCIE_CLK100M_EXCARD_N

PCIE_WAKE_L

PM_S4_STATE_L

SMC_EXCARD_PWR_EN

PM_SLP_S3_LS5V

USB_EXCARD_P

USB_EXCARD_N

USB_EXTB_P

SYS_ONEWIRE

LTALS_OUT

USB_EXTB_N

PCIE_MINI_R2D_N

MAKE_BASE=TRUE

PCIE_EXCARD_R2D_C_N

91 63 27 26 22 12

87

11

34

8

91

24

91

24

91

24

BI BI

OUT

IN

OUT

IN IN

THRML_PAD

VDDO_TTL1

VMAIN_AVLBL

SWITCH_VAUX

VAUX_AVLBL

LED_DUPLEX*

RSVD_43

RSVD_29

RSVD_25

RSVD_24

NC_64

CTRL12

NC_57

NC_52

NC_51

NC_32

RSET

SWITCH_VCC

AVDDH

AVDD0

AVDD3

VDDO_TTL3

LOM_DISABLE*

VDD0

VDD1

VDD3

VDD4

TX_P

CTRL18

TESTMODE

VDD2

VDD5

VDD7

CLKREQ*

WAKE*

PERST*

MDIP0

MDIP1 MDIN1

MDIP2 MDIN2

MDIP3

XTALI

MDIN3

XTALO

REFCLKP REFCLKN

RX_N

RX_P

SPI_DO

SPI_CLK

SPI_CS

VPD_DATA

VPD_CLK

TX_N

MDIN0

AVDD1

LED_LINK1000*

VDD6

VDDO_TTL2

VDDO_TTL0

LED_ACT*

LED_LINK10/100*

AVDD2

SPI_DI

ANALOG

PCI EXPRESS

SPI

LED

TWSI

MEDIA

MAIN CLK

TEST/RSVD

IN

OUT OUT

E2

WC*

NC0

NC1

VSS

SCL

SDA

VCC

IN

OUT

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

No link: 60 mA 10 Mbps: 70 mA

- Alias =YUKON_EC_PP2V5_ENET to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF and 1x 0.001uF caps

- Connect =ENET_CLKREQ_L to clock generator via 0-ohm resistor (BOMOPTION: YUKON_ULTRA)

- Use YUKON_EC and YUKON_ULTRA BOMOPTIONs to select stuffed part

- Use 0-ohm resistors or variable supply to provide 1.8V or 2.5V to =PP1V8R2V5_ENET_PHY

Yukon EC: Pin 42 should be NC (or TP) net.

Page Notes

Power aliases required by this page:

- =PP3V3_ENET_PHY

- =PP1V2_ENET_PHY

(EC / Ultra) (2.5V / 1.8V) (2.5V / GND)

NC

NC NC NC

(IPD)

(IPU) (IPU) (IPU) (IPU)

(IPU)

NC

NC NC

NC

EC:AVDD 2.5V

EC:NO CONNECT

100 Mbps: 70 mA

Yukon Ultra

10 Mbps: 179 mA

No link: 4 mA

1000 Mbps: 4 mA

NC

VPD ROM

Yukon EC

100 Mbps: 150 mA

Yukon EC No link: 171 mA

100 Mbps: 203 mA 1000 Mbps: 426 mA

Yukon Ultra

- =YUKON_EC_PP2V5_ENET

Must be high in S0 state (can use PP3V3_S0 as input)

1000 Mbps: 80 mA

100 Mbps: 4 mA

10 Mbps: 4 mA

Yukon Ultra (1.8V)

10 Mbps: 30 mA

No link: 0 mA

100 Mbps: 40 mA 1000 Mbps: 150 mA

Yukon EC (2.5V)

10 Mbps: 108 mA 100 Mbps: 126 mA 1000 Mbps: 218 mA

No link: 82 mA

Yukon EC: Alias to PP1V8R2V5_ENET_PHY_AVDD, add 1x 0.1uF & 1x 0.001uF caps Yukon Ultra: Alias to GND

(EC:2.5V)

YUKON_ULTRA - Selects Yukon Ultra RSET.

BOM options provided by this page:

- =ENET_CLKREQ_L (NC/TP for Yukon EC)

Signal aliases required by this page:

- =PP1V8R2V5_ENET_PHY

To support Yukon EC and Ultra on the same board:

YUKON_EC - Selects Yukon EC RSET value.

instructions for dual Yukon EC / Yukon Ultra schematic support.

NOTE: See bottom of page for

- =ENET_VMAIN_AVLBL (See note by pin)

and magnetics. Can also use BCP69T1 connected to CTRL18 pin 4 for internal VR.

(IPU)

1000 Mbps: 290 mA

10 Mbps: 130 mA

No link: 130 mA

NC

EC:CTRL25

SIGNAL_MODEL=EMPTY

402

1/16W

1% MF-LF

49.9

R3740

1

2

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

49.9

1/16W

R3741

1

2

37 87

24 87

10% CERM

50V

0.001UF

402

C3740

1

2

10% CERM

50V

0.001UF

402

C3742

1

2

10% CERM

50V

0.001UF

402

C3744

1

2

10% CERM

50V

0.001UF

402

C3746

1

2

1/16W

SIGNAL_MODEL=EMPTY

402

1% MF-LF

49.9

R3742

1

2

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

49.9

1/16W

R3743

1

2

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

49.9

1/16W

R3747

1

2

SIGNAL_MODEL=EMPTY

402

1% MF-LF

49.9

1/16W

R3746

1

2

SIGNAL_MODEL=EMPTY

402

1%

MF-LF

49.9

1/16W

R3745

1

2

SIGNAL_MODEL=EMPTY

402

1/16W

1% MF-LF

49.9

R3744

1

2

0.1uF

10% X5R 40216V

C3735

1 2

0.1uF

10% 16V X5R 402

C3736

1 2

PLACEMENT_NOTE=Place C3730 close to southbridge.

16V10%

0.1uF

X5R 402

C3730

1 2

PLACEMENT_NOTE=Place C3731 close to southbridge.

402X5R16V10%

0.1uF

C3731

1 2

24 87

28

25 34

29 30

29 30 88

BOMOPTION=OMIT

CRITICAL

88E8058

QFN

U3700

192223

28

8

42

3

4

59

63

62

60

10

18

21

27

31

17

20

26

30

3251525764

5

56

55

16

24 25 29 43

53

54

37 36

35

34

9

11

46

65

50

49

12

271333394448

58

14045

61

47

38 41

6

15 14

7

25 36 40 45 49 58 62 65

YUKON_ULTRA

4.99K

402

MF-LF

1/16W

1%

R3765

1

2

CERM

6.3V

20%

4.7UF

603

C3720

1

2

50V CERM

0.001UF

402

10%

C3724

1

2

0.1UF

402

16V

10% X5R

C3723

1

2

402

0.1UF

16V

10% X5R

C3722

1

2

X5R

10% 16V

402

0.1UF

C3721

1

2

402

10%

0.001UF

50V CERM

C3714

1

2

0.1UF

402

16V

10% X5R

C3713

1

2

0.1UF

402

16V

10% X5R

C3712

1

2

X5R

10% 16V

402

0.1UF

C3711

1

2

6.3V

20%

603

4.7UF

CERM

C3710

1

2

CERM

50V

0.001UF

402

10%

C3715

1

2

0.1UF

X5R

10% 16V

402

C3705

1

2

0.1UF

X5R

10% 16V

402

C3704

1

2

X5R

10% 16V

402

0.1UF

C3703

1

2

X5R

10% 16V

402

0.1UF

C3702

1

2

0.1UF

402

16V

10% X5R

C3701

1

2

603

4.7UF

20%

6.3V CERM

C3700

1

2

10%

402

0.001UF

50V

CERM

C3708

1

2

10%

402

0.001UF

50V CERM

C3707

1

2

10%

402

0.001UF

50V CERM

C3706

1

2

SO8

M24C08

OMIT

CRITICAL

U3780

3

1

2

6

5

8

4

7

X5R

10% 16V

402

0.1UF

C3780

1

2

4.7K

5%

402

MF-LF

1/16W

R3780

1

2

4.7K

5%

402

MF-LF

1/16W

R3781

1

2

5%

4.7K

402

MF-LF

1/16W

R3760

1

2

FERR-120-OHM-1.5A

0402

L3720

1 2

36

051-7431

A.0.0

92

Ethernet (Yukon)

35

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

YUKON_EC1 U3700338S0270

IC,88E8053,GIGABIT ENET XCVR,64P QFN

CRITICAL

1338S0386 U3700 CRITICAL

YUKON_ULTRA

IC,88E8058,GIGABIT ENET XCVR,64P QFN

CRITICAL1 U3780

YUKON_ULTRA

341S2060

IC,FLASH,88E8058 ETHERNET VPD,IIC,SO8

CRITICAL1 YUKON_EC341S1797

IC,EEPROM,SERIAL IIC,8KBIT,SO8

U3780

114S0285 1 YUKON_EC

RES,4.87K,1%,1/16W,0402,LF

R3760

PP3V3_ENET

GND

PP1V9_ENET

PP1V8R2V5_ENET_PHY_AVDD

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

PP1V25_ENET

PCIE_ENET_R2D_P

YUKON_VPD_DATA

PCIE_ENET_R2D_C_N

PCIE_ENET_R2D_C_P

PCIE_ENET_D2R_N

PCIE_ENET_D2R_P

PCIE_ENET_R2D_N

PCIE_ENET_D2R_C_N

TP_YUKON_CTRL18 TP_YUKON_CTRL12

PM_SLP_S3_L

YUKON_RSET

ENET_LOM_DIS_L

ENET_MDI0 ENET_MDI1 ENET_MDI2 ENET_MDI3

YUKON_VPD_CLK

PCIE_ENET_D2R_C_P

ENET_MDI_P<2> ENET_MDI_N<2>

ENET_MDI_P<1>

PCIE_CLK100M_ENET_P

ENET_MDI_N<1>

ENET_MDI_N<0>

ENET_CLKREQ_L

PCIE_CLK100M_ENET_N

PCIE_WAKE_L

ENET_MDI_P<0>

ENET_RESET_L

ENET_CLK25M_XTALI ENET_CLK25M_XTALO

ENET_MDI_N<3>

ENET_MDI_P<3>

61

36

58

8

37

8

87

OUT

THRM_PAD

NC

IN1

EN

IN2

OUT1 OUT2

NR/FB

GND

IN

OUT

G

D

S

IN

G

D

S

G

D

S

IN

OUT

G

DS

G

D

S

G

D

S

G

D

S

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

DESCRIPTION

REFERENCE DES

BOM OPTION

QTY

PART NUMBER

CRITICAL

ENET Enable Generation

NOTE: S3 term is guaranteed by source of R3800 & Q3810, MUST BE S3 RAIL.

"ENET" = "S0" || ("S3" && "AC" && "WOL_EN")

EC: Vout = 2.510V

Yukon Ultra requires 1.9V on its magnetics to pass compliance tests

Yukon AVDDL LDO

WLAN Enable Generation

"WLAN" = "S0" || ("S3" && "AC" && "WOW_EN")

NOTE: S3 term is guaranteed by FET & pull-up source, MUST BE S3 RAIL.

Ultra: Vout = 1.912V

(PM_SLP_S3_L)

3.3V ENET FET

NC

500 mA max output (U3850 limit)

Vout = 1.2246V * (1 + Ra / Rb)

NC

1.9V for Yukon Ultra, 2.5V for Yukon EC

(AC_EN_L)

Yukon Crystal

NC

7

61 65

CRITICAL

SON

LREG_TPS79501DRB

U3850

8

6

1 2

7

5

3 4

9

10%

402

CERM

6.3V

1UF

C3850

1

2

1UF

6.3V CERM 402

10%

C3851

1

2

16.9K

1% 1/16W MF-LF 402

YUKON_ULTRA

R3855

1

2

MF-LF

30.1K

1% 1/16W

402

R3856

1

2

5%

50V

CERM

402

33PF

C3855

1

2

SM-3.2X2.5MM

25.0000M

CRITICAL

Y3860

24

13

CERM 402

50V

5%

18PF

C3861

1

2

CERM

5%

50V 402

18PF

C3860

1

2

35

2N7002DW-X-F

SOT-363

Q3800

6

2

1

40 45 46 57

402

10%

CERM

0.22UF

10V

C3800

1

2

SOT-363

2N7002DW-X-F

Q3805

3

5

4

2N7002DW-X-F

SOT-363

Q3805

6

2

1

13 24

34

1/16W

5%

MF-LF

100K

402

R3810

1 2

10K

MF-LF

5%

1/16W

402

R3811

1

2

10% 16V

402

0.01UF

CERM

C3810

12

CRITICAL

SOT-23

NTR4101P

Q3810

3

1

2

10% 16V

402

X5R

0.033UF

C3811

1

2

5%

1/16W

10K

402

MF-LF

R3800

1

2

SOT-363

2N7002DW-X-F

Q3801

3

5

4

SOT-363

2N7002DW-X-F

Q3800

3

5

4

2N7002DW-X-F

SOT-363

Q3801

6

2

1

7

25 35 40 45 49 58 62 65

25

1 R3855 YUKON_EC

RES,31.6K,1%,1/16W,402,LF

114S0363

SYNC_DATE=03/19/2007

SYNC_MASTER=T9_NOME

36 92

A.0.0

051-7431

Yukon Power Control

PM_ENET_EN_L

WOL_EN

PM_SLP_S3_L

AC_EN_L

PP3V3_ENET

ENET_CLK25M_XTALI ENET_CLK25M_XTALO

PM_ENET_EN

SMC_ADAPTER_EN

WOW_EN

ENETAVDDL_FB

PP1V9_ENET

P3V3ENET_SS

PP3V3_ENET

PM_WLAN_EN_L

PP3V3_S3

81 65 58 55 54 51 50

36

36 48

35 35

35 38

8 8

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

SYM_VER2

NC2

NC3

NC4

LINE

SIDE

CHIP

SIDE

NC1

BI

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BOM options provided by this page:

Power aliases required by this page:

Signal aliases required by this page:

Place one cap at each pin of transformer

- =GND_CHASSIS_ENET

New Series Rs required for European Telecom Compliance

Place close to connector

(NONE)

Page Notes

mirrored on opposite sides of the board

Transformers should be

Short shielded RJ-45

514-0277

10%

6.3V

1uF

CERM 402

C3903

1

2

1uF

10% CERM

402

6.3V

C3902

1

2

MF-LF 402

1/16W

5%

75

R3903

1

2

75

MF-LF 402

5% 1/16W

R3902

1

2

1/16W

5%

402

MF-LF

75

R3901

1

2

1/16W MF-LF

5%

402

75

R3900

1

2

6.3V 402

1uF

10% CERM

C3901

1

2

1uF

CERM

6.3V

10% 402

C3900

1

2

1000BT-824-00275

CRITICAL

XFR-SM

OMIT

T3900

1

10

11

14

15

16

2

3

6

7

8 9

4 5 12

13

OMIT

CRITICAL

XFR-SM

1000BT-824-00275

T3901

1

10

11

14

15

16

2

3

6

7

8 9

4 5 12

13

35 87

JM36113-P2054-7F

F-RT-TH-RJ45

CRITICAL

J3900

9

10

11

12

1 2 3 4 5 6 7 8

CRITICAL

10% 2KV

CERM

1000PF

1206

C3904

1 2

Ethernet Connector

92

051-7431

37

A.0.0

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

157S0053

2

CRITICAL

T3900,T3901

XFMR,ISO,HALF-PORT,1000T,16P,SMD,2MM

ENETCONN_N<1>

ENETCONN_P<2>

ENETCONN_P<3>

ENETCONN_N<3>

ENET_CTAP0

ENET_CTAP1

ENET_CTAP2

PP1V8R2V5_ENET_PHY_AVDD

ENET_MDI_N<3>

ENET_MDI_P<1>

ENET_MDI_P<0>

ENET_CTAP3

ENETCONN_P<1>

ENETCONN_N<0>

ENETCONN_P<0>

ENETCONN_N<2>

ENET_CTAP_COMMON

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

ENET_MDI_N<0>

ENET_MDI_N<2>

ENET_MDI_P<2>

ENET_MDI_N<1>

ENET_MDI_P<3>

91

35

91

BI

BI BI BI BI

BI

BI BI

BI BI BI

OUT OUT

IN

OUT

BI

OUT

IN IN

BI

OUT

SDA

SCL

PCI_AD19

PCI_AD18

PCI_AD17

PCI_AD16

PCI_AD15

PCI_AD14

PCI_AD13

PCI_AD12

PCI_AD11

PCI_AD10

PCI_AD31

PCI_AD30

PCI_AD28 PCI_AD29

PCI_AD27

PCI_AD25 PCI_AD26

PCI_AD24

PCI_AD23

PCI_AD21

PCI_AD20

PCI_AD9

PCI_AD8

PCI_AD7

PCI_AD6

PCI_AD5

PCI_AD4

PCI_AD3

PCI_AD2

PCI_PAR

PCI_CLK PCI_IDSEL

GND

PCI_AD1

PCI_AD0

VCC

MFUNC

G_RST_L

REG18_1

REG18_0

REG_EN_L

PHY_PINT

PHY_PCLK

PHY_LREQ

PHY_LPS

PHY_LINKON

PHY_LCLK

PHY_D7

PHY_D6

PHY_D5

PHY_D4

PHY_D3

PHY_D1-D1

PHY_D2

PHY_D0-D0

PHY_CTL1-CTL1

PHY_CTL0-CTL0

PCI_ACK64_L

PCI_TRDY_L

PCI_STOP_L

PCI_SERR_L

PCI_RST_L

PCI_REQ64_L

PCI_REQ_L

PCI_PME_L

PCI_PERR_L

PCI_IRDY_L

PCI_INTA_L

PCI_GNT_L

PCI_FRAME_L

PCI_DEVSEL_L

VCCP

PCI_AD22

PCI_C_BE2_L

PCI_C_BE0_L

PCI_C_BE3_L

PCI_C_BE1_L

G

D

S

IN

G

D

S

IN

BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI BI

BI BI BI BI BI BI BI BI BI BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

when there’s no power on VCCP

G_RST* is clamped to VCCP

aliased to the same rail)

It must not be taken high

(OK if VCCP and VCC are

G_RST* assertion min 2ms

MFUNC as a GPIO

Might use

(FW_G_RST_L)

24 87

25

24 87

30 88

7

24 47 87

28

1uF

10V X5R 402

10%

C4008

1

2

10V 402

X5R

1uF

10%

C4009

1

2

10V 402

X5R

1uF

10%

C4004

1

2

10V 402

X5R

10%

1uF

C4003

1

2

10V

1uF

10% X5R

402

C4002

1

2

10%

1uF

10V X5R 402

C4001

1

2

10% X5R

10V 402

1uF

C4000

1

2

402

MF-LF

1/16W

5%

4.7K

R4002

1

2

1/16W MF-LF

402

5%

4.7K

R4001

1

2

24 87

39

220

402

MF-LF

1/16W

5%

R4090

1

2

1K

402

MF-LF

1/16W

5%

R4080

1

2

220

5% 1/16W MF-LF 402

R4091

1

2

39 89

10K

5% 1/16W MF-LF

402

R4010

1

2

TSB83AA22CZAJ

CRITICAL

(2 OF 2)

BGA

U4000

E4

C7

C8

F7F8F9

F10

G6G7G8

G9

G10

H6D6H7H8H9

H10

J8

J9

J10

K10

D7E6E7E8E9

E10

F6

A1

N12

L12 N11

N6 M6 M7 K9 K8 M5 K3 N1 L4 M2

M11

M1 L1 J4 H3 H4 J3 H2 G3 H1 F1

N10

F2 G4

M10 K12

M9 N9 L8 M8

N8 M3 K5 K2

D3

N2 L3 E3

L2

B3 K4

N3

L6 F4

J13

F3

D1 L7 L5 J5

F13 F12

E13 E12

C13 B9 B10 C11 B12 A11 B7 B4 A2 D4 B6 A3

G11 G12

C2

C3 C4

D5D8D9E5F5

H11J6J7

J11

E11

F11

SOT-363

2N7002DW-X-F

Q4070

3

5

4

39

2N7002DW-X-F

SOT-363

Q4070

6

2

1

100K

402

MF-LF

1/16W

5%

R4070

1

2

10K

5% 1/16W MF-LF 402

R4071

1

2

45

28

402

MF-LF

1/16W

5%

22

R4000

1

2

16V

10%

402

X5R

0.1uF

C4010

1

2

402

X5R

16V

10%

0.1uF

C4011

1

2

24 87

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

38 92

A.0.0

051-7431

FireWire Link (TSB83AA22)

PP3V3_S3 PP3V3_S3

INT_PIRQD_L

PCI_FW_GNT_L

PCI_FRAME_L

PCI_ACK64_L

PCI_TRDY_L

PLT_GATED_RST

SMC_RSTGATE_L

FW_G_RST_L

PP3V3_S3

FW_PLT_RST_L

PP1V8_S3

FW_DATA<4>

PCI_PAR

PCI_C_BE_L<1> PCI_C_BE_L<2>

PCI_AD<22>

PCI_C_BE_L<3>

PCI_C_BE_L<0>

PCI_PME_FW_L

PCI_FW_RST_L PCI_SERR_L PCI_STOP_L

TP_FW_CTL<0> TP_FW_CTL<1>

TP_FW_DATA<0>

FW_DATA<2>

TP_FW_DATA<1>

FW_DATA<3>

FW_DATA<5> FW_DATA<6> FW_DATA<7> CLKFW_PHY_LCLK FW_LINKON FW_LPS FW_LREQ

FW_PINT

PCI_AD<0> PCI_AD<1>

PCI_CLK33M_FW

PCI_AD<2> PCI_AD<3> PCI_AD<4> PCI_AD<5> PCI_AD<6> PCI_AD<7> PCI_AD<8> PCI_AD<9>

PCI_AD<20> PCI_AD<21>

PCI_AD<23> PCI_AD<24>

PCI_AD<26>

PCI_AD<25>

PCI_AD<27>

PCI_AD<29>

PCI_AD<28>

PCI_AD<30> PCI_AD<31>

PCI_AD<10> PCI_AD<11> PCI_AD<12> PCI_AD<13> PCI_AD<14> PCI_AD<15> PCI_AD<16> PCI_AD<17> PCI_AD<18>

FW_PCI_IDSEL

PCI_AD<19>

FW_MFUNC

FW_SDA

FW_SCL

PCI_FW_REQ_L

PCI_DEVSEL_L

PCI_PERR_L

PCI_IRDY_L

PCI_REQ64_L

FW_LLC_PP1V8LDO_EN_L

CLKFW_LINK_PCLK

81

65

58

55

54

51

91

50

62

48

50

38

32

36

31

8

SE

SM

RESET

D7

D5 D6

D4

D3

D2

CPS

PD

BMODE

PC2

PC0 PC1

LREQ

LPS

DS1 LCLK

DS0

XI

R1

R0

TESTM TESTW

TPBIAS0 TPBIAS1

TPB1N

TPB1P

TPB0N

TPB0P

TPA1N

TPA1P

TPA0P TPA0N

PINT

PCLK

AVDD_3P3

DVDD_3P3

DVDD_CORE

PLLVDD_3P3

PLLVDD_CORE

PLLGND

LKON_DS2

CNA

BI BI

OUT

OUT OUT

OUT

TRI-ST/NC

VCC

GND

IN

OUT

BI BI BI BI BI BI

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

1MA (MAX) BUS HOLDERS

NC

(IPU)

NC

pull-up provides

C4150 with internal

PHY power-up reset.

Lo: Beta Mode enable (1394b).

Hi: Data-Strobe only (1394a).

DSx Straps:

Multi-port Portable systems are Power Class 4 (’100’). Implement 1K pull-up or pull-down on port page.

Strap via alias on port page.

Single-port / Desktop systems are Power Class 0 (’000’).

Power Class:

as 3rd FireWire port is not pinned out.

No need for DS2 pull-down on TSB83AA22A,

R4160 provides isolation between R4161 and unpowered LLC.

0.22uF

X5R 402

20%

6.3V

C4150

1

2

402

MF-LF

1/16W

5%

390K

R4155

1

2

CRITICAL

(1 OF 2)

BGA

TSB83AA22CZAJ

U4000

D10

D11G5H5

L9

M12

A5

D13

C9 C10 C12 B13 B11

A6

B8

D12

H12

J12K7K6C5C6

G13

L13

N13

K13

N4

M4

N5

H13

K11

M13

A10

A7

A8

A12 A13

L10

A4

B5

L11 N7

E2

E1

J1

J2

B1

C1

G1

G2

D2 K1

A9

402

CERM

0.01uF

16V

20%

C4110

1

2

10V

10%

402

X5R

1uF

C4102

1

2

1uF

X5R 402

10% 10V

C4121

1

2

41 89

38 89

41

10V

10%

402

X5R

1uF

C4101

1

2

1uF

10V

10%

402

X5R

C4103

1

2

10V

10%

402

X5R

1uF

C4104

1

2

10V

10%

402

X5R

1uF

C4111

1

2

10% 10V

402

X5R

1uF

C4112

1

2

1uF

10V

10%

402

X5R

C4113

1

2

1uF

10V

10%

402

X5R

C4114

1

2

SM

98P3040MHZ

CRITICAL

G4180

2

3 1

4

38 89

38

5%

1/16W

402

MF-LF

1K

R4145

12

402

5%

MF-LF

1/16W

1K

R4142

12

10V

10% 402

X5R

1uF

C4131

1

2

10V

10% 402

X5R

1uF

C4130

1

2

6.3V

10% 603

CERM1

2.2uF

C4135

1

2

8

39 40 41 64

402

MF-LF

1/16W

5%

10K

R4156

1

2

402

MF-LF

1/16W

5%

4.7

R4186

1

2

1/16W

5%

402

MF-LF

1

R4100

1 2

1/16W

5%

402

MF-LF

1

R4135

1 2

1

MF-LF

402

5%

1/16W

R4120

1 2

1/16W

5%

402

MF-LF

470

R4161

1

2

1/16W

1% MF-LF

6.34K

402

R4162

1

2

5% 1/16W MF-LF

402

1K

R4160

1 2

38

22

MF-LF

402

5%

1/16W

R4180

1 2

6.3V

20% 402

X5R

0.22uF

C4180

1

2

1/16W

5%

402

MF-LF

1K

R4191

1

2

1K

MF-LF 402

5% 1/16W

R4140

1

2

1/16W

5%

402

MF-LF

1K

R4190

1

2

FireWire PHY (TSB83AA22)

SYNC_DATE=08/28/2007

051-7431

A.0.0

9239

SYNC_MASTER=M87_MLB

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.38 mm

PP3V3_FW_PHY_PLLVDD

VOLTAGE=3.3V

PP3V3_FW_PHY_AVDD

MIN_NECK_WIDTH=0.22 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=3.3V

PP1V95_FW

PP1V95_FW_PHY_PLLVDD

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.22 mm VOLTAGE=1.95V

FW_PORT1_TPA_P

FW_PORT0_TPB_P

FW_LREQ

GND

FWPHY_RESET_L

FW_LPS

FWPHY_CLK98P304M_R

PP1V8_FW_PHYOSC_R

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.25 mm VOLTAGE=1.8V

PP1V95_FW

FWPHY_CLK98P304

FW_PORT0_TPB_N

PP3V3_FW

FW_LINKON_R

PP3V3_FW

FW_DATA<3> FW_DATA<4> FW_DATA<5> FW_DATA<6> FW_DATA<7>

FW_DATA<2>

CLKFW_PHY_LCLK

FW_PORT0_TPA_N

FWPHY_BMODE

FWPHY_CPS

FW_LINKON

FWPHY_TESTW

FWPHY_DS1

FWPHY_DS0

PPVP_FW

FWPHY_R1

FW_PORT1_TPB_P FW_PORT1_TPB_N

FW_PORT1_TPA_N

FW_PORT0_TPA_P

FW_PINT

FWPHY_TESTM

CLKFW_LINK_PCLK

FW_1_TPBIAS

VOLTAGE=1.86V

FW_0_TPBIAS

VOLTAGE=1.86V

FWPHY_R0

PP3V3_FW

64

41

64

40

64

40

39

40

39

8

V-

V+

S

G

D

S

G

D

GND

SENSEB

OUTA

FAULTB_L

FAULTA_L

ONB

INB

ONA

ONQ1

INA

GATE1A

GATE2A

SENSEA

GATE1B

GATE2B

OUTB

G

D

S

G

D

S

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

is running or on AC.

Page Notes

- =PPVP_FW_SUMNODE (power passthru summation node) Signal aliases required by this page:

BOM options provided by this page:

Late-VG Event Detection

Current Limit/Active Late-VG Protection

- FW_PORT_FAULT_PU

(NONE)

spikes. Current limit has been set higher to compensate.

tends to trip easily on devices that produce periodic current

and -1/128 if under the limit. As a result, the device

reaches 16. A new sample (taken every 125 us) is weighted

MAX5944 current limiter trips if integrator (counter)

as +1 if over the limit (at any point during the period)

0.025 ohm => 2A

0.030 ohm => 1.66A (Ideal)

0.033 ohm => 1.5A

2.81V on late Vg event and port power is off

2.95V when port power is on

FWLATEVG_3V_REF Hysteresis:

Enables port power when machine

Current Limits

0.020 ohm => 2.4A

NC

FireWire Port Power Switch

Power aliases required by this page:

- =PPBUS_S5_FWPWRSW (system supply for bus power)

- =PP3V3_FW_LATEVG_ACTIVE

2.0M

1/16W

5%

402

MF-LF

R4219

1

2

10V

10%

603

CERM-X5R

0.33UF

C4219

1

2

0.1UF

CERM 402

20% 10V

C4210

1

2

200K

MF-LF

402

1%

1/16W

R4210

1 2

SM-LF1

LMC7211

U4210

4

3

1

5

2

1/16W

5%

402

MF-LF

10K

R4211

1

2

402

100pF

CERM

5%

50V

C4211

1

2

MF-LF

1/16W

1%

402

10K

R4212

1

2

80.6K

MF-LF 402

1% 1/16W

R4213

1

2

MBR0540XXG

SOD-123

D4219

12

SOT23-3

SI2318DS

CRITICAL

Q4220

3

1

2

SI2318DS

SOT23-3

CRITICAL

Q4225

3

1

2

35V

1uF

10%

805

X7R

CRITICAL

C4225

1

2

CRITICAL

1uF

X7R 805

10% 35V

C4220

1

2

CRITICAL

805

MF

1%

0.25W

0.020

R4220

1 2

CRITICAL

MAX5944

SOIC

U4220

3

11

15

7

14

6

12

1

9

2

10

4

13

5

16

8

MF

1%

0.020

805

0.25W

CRITICAL

R4225

1 2

100K

402

5% 1/16W MF-LF

FW_PORT_FAULT_PU

R4229

1

2

SOI-LF

CRITICAL

NDS9407

Q4260

5

6

7

8

4

1

2

3

16V

20%

402

CERM

0.01uF

C4260

1

2

402

470K

1/16W

5% MF-LF

R4260

1

2

2N7002DW-X-F

SOT-363

Q4261

6

2

1

402

1/16W MF-LF

330K

5%

R4261

1

2

2N7002DW-X-F

SOT-363

Q4261

3

5

4

36 45 46 57

7

25 35 36 45 49 58 62 65

MINISMDC

CRITICAL

1.5A-24V

F4260

1 2

CRITICAL

PWRDI5

PDS540XF

D4260

1

2

3

A.0.0

051-7431

40 92

FireWire Port Power

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

MIN_LINE_WIDTH=0.5 mm

PPBUS_FW_FWPWRSW_D

PPVP_FW

PPVP_FW_PORTB_UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

FW_PORTB_PWRCTRL

FWLATEGV_3V_REF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

PPVP_FW_PORTA_UF

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

PPVP_FW_PORTB_ISENSE

FW_PORTA_PWRCTRL

PPVP_FW

FW_PORT_FAULT_L

PM_SLP_S3_L

SMC_ADAPTER_EN

FWPWR_EN_L

LATEVG_EVENT_L

PP2V4_FW_LATEVG

FWPWR_EN_L_DIV

PPBUS_G3H

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

PPBUS_FW_FWPWRSW_F

VOLTAGE=33V

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PPVP_FW_PORTA_ISENSE

FW_PORTPWR_DISABLE_L

PP3V3_FW

P2V4_FWLATEVG_RC

82 79 75 66

63 62 61 60 59 58

64

57

64

40

49

41

39

41

39

8

64

39

8

41

7

8

TPO#

TPI

TPO

TPI#

VGND

VP

SYM_VER-2

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

BREF should be hard-connected to logic

between them (to avoid ground offset issue)

beta-only device, there is no DC path

When a bilingual device is connected to a

local grounds per 1394b spec

(GND_FW_PORT1_VG)

(FW_PORT1_BREF)

AREF needs to be isolated from all

PORT 0

1394A

(TPA+)

(TPB+) (TPB-)

514-0255

(GND_FW_PORT0_VG)

Cable Power

"Snapback" & "Late VG" Protection

FW spec calls out 0.33uF

Place close to FireWire PHY

Termination

(Common to all ports)

FireWire TPA/TPB pairs to their

(NONE)

- =GND_CHASSIS_FW_PORT0L

Power aliases required by this page:

514S0133

PORT 1

OUTPUT

(TPA-)

Note: Trace PPVP_FW_PORT0 must handle up to 5A

BILINGUAL

NC

NC VG

TPB+

TPA+

TPA<R>

TPA-

TPB<R>

TPB-

Cable Power

the necessary aliases to map the

NOTE: This page is expected to contain

Signal aliases required by this page:

properly terminate unused signals.

- =GND_CHASSIS_FW_PORT1

- =GND_CHASSIS_FW_PORT0U

- =PP3V3_FW_LATEVG

- =PPVP_FW_PORT1

Page Notes

Late-VG Protection Power

PP2V4_FWLATEVG needs to be biased

- Port "1" Bilingual (1394B)

Configures PHY for:

- Port "0" Data-Strobe only (1394A)

appropriate connectors and/or to

- =PPVP_FW_PORT0

- =GND_CHASSIS_FW_EMI_R

(NONE)

R4390 should be 390 Ohms max for a 3.3V rail

to at least 2.1V for FW signal integrity and should be biased to 2.4V for margin

for snap-back diodes

ESD and late-VG rail

TI PHYs require 1uF even though

1394b implementation based on Apple FireWire Design Guide (FWDG 0.6, 5/14/03)

INPUT

VP

Note: Trace PPVP_FW_PORT1 must handle up to 5A

"Snapback" & "Late VG" Protection

to apply to entire TPA/TPB XNets.

provide the appropriate constraints

assumed that FireWire PHY page will

constrained on this page. It is

NOTE: FireWire TPA/TPB pairs are NOT

BOM options provided by this page:

- 2-port Portable Power Class (4)

detection currents per 1394b V1.33

ground for speed signaling and connection

FireWire PHY Config Straps

1uF

CERM 402

10%

6.3V

C4350

1

2

1/16W

1%

402

MF-LF

56.2

R4351

1

2

1/16W

1%

402

MF-LF

56.2

R4350

1

2

1/16W

1%

402

MF-LF

56.2

SIGNAL_MODEL=EMPTY

R4353

1

2

1/16W

1%

402

MF-LF

56.2

SIGNAL_MODEL=EMPTY

R4352

1

2

4.99K

MF-LF

402

1%

1/16W

R4354

1

2

220pF

CERM 402

5% 25V

C4354

1

2

CRITICAL

FERR-250-OHM

SM

L4300

1 2

50V 402

10% X7R

0.01UF

C4304

1

2

SOT-363

BAV99DW-X-F

DP4300

4

5

3

CRITICAL

1394A

F-RT-TH-LF

J4300

7 8 9 10

4

3

6

5

2

1

SOT-363

BAV99DW-X-F

DP4301

4

5

3

10% X7R

402

0.01uF

50V

C4301

1

2

BAV99DW-X-F

SOT-363

DP4300

1

2

6

X7R

0.01uF

50V

10%

402

C4300

1

2

50V

10%

402

X7R

0.01uF

C4303

1

2

BAV99DW-X-F

SOT-363

DP4301

1

2

6

0.01uF

X7R 402

10% 50V

C4302

1

2

1/16W

1%

402

MF-LF

56.2

R4363

1

2

4.99K

MF-LF

402

1%

1/16W

R4364

1

2

1/16W

1%

402

MF-LF

56.2

R4362

1

2

220pF

CERM 402

5% 25V

C4364

1

2

1/16W

1%

402

MF-LF

56.2

R4361

1

2

1uF

CERM 402

10%

6.3V

C4360

1

2

1/16W

1% MF-LF

402

56.2

R4360

1

2

PLACEMENT_NOTE=Place C4319 close to connector pin 5.

0.1uF

X7R

603-1

10% 50V

C4319

1

2

5%

1M

1/16W 402

MF-LF

R4319

1

2

402

0.01UF

10% X7R

50V

C4314

1

2

FERR-250-OHM

CRITICAL

SM

L4310

1 2

X7R 402

10% 50V

0.01uF

C4310

1

2

SOT-363

BAV99DW-X-F

DP4310

1

2

6

X7R 402

0.01uF

50V

10%

C4311

1

2

SOT-363

BAV99DW-X-F

DP4310

4

5

3

SOT-363

BAV99DW-X-F

DP4311

1

2

6

SOT-363

BAV99DW-X-F

DP4311

4

5

3

X7R 402

10% 50V

0.01uF

C4313

1

2

0.01uF

402

X7R

10% 50V

C4312

1

2

332

MF-LF

402

1%

1/16W

R4390

1 2

CRITICAL

MMBZ5227B

SOT23

D4390

1

3

1394B-UG31903

F-RT-SM1

CRITICAL

J4310

1

10

11

2

3

4

5

6

7

8

9

1210-4SM1

90-OHM-100MA

CRITICAL

FL4300

1

2 3

4

90-OHM-100MA

CRITICAL

1210-4SM1

FL4301

1

2 3

4

0402

CRITICAL

18NH-250MA

L4360

1 2

0402

18NH-250MA

CRITICAL

L4361

1 2

0402

CRITICAL

18NH-250MA

SIGNAL_MODEL=EMPTY

L4362

1 2

0402

SIGNAL_MODEL=EMPTY

18NH-250MA

CRITICAL

L4363

1 2

SYNC_DATE=08/28/2007

FireWire Ports

SYNC_MASTER=M87_MLB

9241

A.0.0

051-7431

PP2V4_FW_LATEVG

FW_PORT0_TPA_P

FW_PORT0_TPA_N

FW_PORT0_TPB_P

FW_PORT0_TPB_N

FW_PORT0_TPB_FL_N

FW_PORT0_TPB_FL_P

FW_PORT0_TPA_FL_P FW_PORT0_TPA_FL_N

FW_B_TPA_L_P

FW_PORT1_TPB_N

MIN_NECK_WIDTH=0.25 mm

PPVP_FW_PORT1

MIN_LINE_WIDTH=0.5 mm VOLTAGE=33V

FW_B_TPB_L_N

FW_PORT1_TPA_P

FW_PORT1_TPB_P FW_PORT1_TPB_N

FW_PORT1_TPB_C

FW_PORT0_TPB_N

FW_PORT0_TPB_C

FW_PORT0_TPA_P

MAKE_BASE=TRUE

FW_PORT0_TPA_N

MAKE_BASE=TRUE

FW_PORT0_TPB_N

MAKE_BASE=TRUE

FW_PORT0_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_P

MAKE_BASE=TRUE

FW_PORT1_TPB_P

MAKE_BASE=TRUE

FW_PORT1_TPA_N

FW_PORT1_TPB_N

MAKE_BASE=TRUE

PP3V3_FW

FW_B_TPA_L_N

PP3V3_FW

FW_0_TPBIAS

FW_PORT1_TPA_N

FW_PORT0_TPA_N

FW_PORT0_TPA_P

FW_1_TPBIAS

PP2V4_FW_LATEVG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm VOLTAGE=2.4V

PPVP_FW_PORTB_UF

PPVP_FW_PORTA_UF

FW_B_TPB_L_P

GND

FW_PORT0_TPB_P

PP2V4_FW_LATEVG

PPVP_FW_PORT0

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=33V

FW_PORT1_TPA_P

FW_PORT1_TPB_P

FW_PORT1_TPA_N

FW_PORT1_AREF

64

41

89

40

89

41

39

41

40

41

40

39

91

39

8

39

40

8

39

40

39

BI BI

IN

OUT

G

D

S

G

D

S

IN

Y

B

A

SGD

IN

BI

IN

BI

IN IN

IN

OUT

BI BI BI BI

IN

OUT

IN

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

10K pull-up to 5V)

(UATA_DSTROBE)

(UATA_CS0*)

Placement note

Place within 12.7mm from ball of SB

Unused SATA Ports

IDE (ODD) Connector

(UATA_CS1*)

(UATA_STOP)

516S0335

NC

(UATA_HSTROBE)

(SB has internal 5.7k-23.5k pull-down)

Indicates disk presence

(ODD has internal

23 42 86

SOT-363

2N7002DW-X-F

Q4421

3

5

4

2N7002DW-X-F

SOT-363

Q4421

6

2

1

1/16W

5%

402

MF-LF

100K

R4422

1

2

24

CRITICAL

M-ST-SM1-LF

J4400

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26

27

28

29

3

30

31

32

33

34

35

36

37

38

39

4

40

41

42

43

44

45

46

47

48

49

5

50

6 7 8 9

23 86

CERM

10%

0.068UF

10V 402

C4422

1

2

24 86

MC74VHC1G09

SC70

U4430

3

2

1

4

5

100K

MF-LF

402

5%

1/16W

R4430

1

2

CRITICAL

SOT-6

FDC606P

Q4420

1 2 5 6

3

4

23 86

42

402

MF-LF

1/16W

24.9

1%

R4460

1

2

23 86

23 86 23 86

23 86

402

4.7K

MF-LF

5%

1/16W

R4402

1

2

6.2K

MF-LF 402

5% 1/16W

R4403

1

2

45

402

MF-LF

1/16W

5%

33K

R4410

1

2

10K

1/16W MF-LF

402

5%

R4420

1

2

23 86

23 86 23 86

23 86

16V

0.01UF

10%

CERM

402

C4421

1 2

47K

1/16W MF-LF

5%

402

R4421

1 2

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

PATA Connector

051-7431

A.0.0

42 92

PP5V_S5

MIN_NECK_WIDTH=0.4 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_ODD

VOLTAGE=5V

P5VODD_SS

PP3V3_S0

ODD_PWR_EN_L

IDE_PDDREQ

IDE_PDIORDY

IDE_IRQ14

SMC_ODD_DETECT

IDE_PDA<0>

IDE_PDD<6> IDE_PDD<5>

IDE_PDD<1>

IDE_PDIOR_L

IDE_PDA<2>

IDE_PDD<8> IDE_PDD<9> IDE_PDD<10> IDE_PDD<11>

IDE_PDD<12> IDE_PDD<13> IDE_PDD<14> IDE_PDD<15>

IDE_PDIOW_L IDE_PDDACK_L

IDE_PDA<1>

IDE_PDCS3_L

IDE_PDD<4>

IDE_PDD<3>

IDE_PDD<0>

TP_SATA_C_D2RN

TP_SATA_C_D2RP

TP_SATA_B_D2RN

TP_SATA_B_D2RP

TP_SATA_C_R2DN

TP_SATA_C_R2DP

TP_SATA_B_R2DN

TP_SATA_B_R2DP

SATA_RBIAS

MAKE_BASE=TRUE

TP_SATA_B_R2DP

MAKE_BASE=TRUE

TP_SATA_C_R2DP TP_SATA_C_R2DN

MAKE_BASE=TRUE

TP_SATA_C_D2RP

MAKE_BASE=TRUE

TP_SATA_B_R2DN

MAKE_BASE=TRUE

TP_SATA_B_D2RN

MAKE_BASE=TRUE

TP_SATA_B_D2RP

MAKE_BASE=TRUE

TP_SATA_C_D2RN

MAKE_BASE=TRUE

SATA_RBIAS

ODD_RST_BUF_L

IDE_PDD<7>

IDE_PDD<2>

P5VODD_EN_L

ODD_RST_5VTOL_L

PP5V_S0

ODD_RST_BUF_L

IDE_PDCS1_L

PP5V_S0

ODD_PWR_EN

91 82 65 59 58 53 52

51 50 48 47 46 32 31

82

30

81

29

80

79

28

65

75

27

59

65

26

58

63

25

54

62

24

52

61

23

49

60

21

47

58

19

42

43

16

86

27

13

42

8

23

7

42

7

OUT

VBUS

D-

D+

GND

VDD

THRM_PAD

GND

0I0 Y0

SEL

1I1

1I0

0I1

Y1

BI

IN

OUT

IN

IN1

OUT1

OUT2

OUT3

TPAD

GND

IN2

OC*

EN

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

If power source is S3, can tie EN to IN.

514S0115

USB/SMC Debug Mux

SEL=1 Choose USB

SEL=0 Choose SMC

Place L4600 and L4605 at connector pin

Right USB Port

Port Power Switch

FERR-220-OHM-2.5A

0603

CRITICAL

L4605

1 2

CRITICAL

20% POLY

6.3V B2-HF

100UF

C4696

1

2

603

X5R

6.3V

20%

10UF

C4695

1

2

10UF

603

6.3V

20% X5R

C4690

1

2

20% 10V CERM 402

0.1UF

C4691

1

2

13 24

F-RT-SM-USB-RGT1

CRITICAL

UAR2X

J4600

1 2 3 4

5 6

7 8

RCLAMP0502B

CRITICAL

SC-75

D4600

3

12

SIGNAL_MODEL=USB_MUX

PI3USB10

TDFN

CRITICAL

SMC_DEBUG_YES

U4650

12

10

11

9

157

6

13

2

8

3 4

24 86

CERM

402

20% 10V

0.1UF

SMC_DEBUG_YES

C4650

1

2

10K

MF-LF 402

5% 1/16W

R4650

1

2

7

45 46 47

7

45 46 47

45

7

25 34 45 58 65

SMC_DEBUG_NO

1/16W MF-LF

0

5%

402

R4651

1 2

MF-LF

1/16W

5%

402

0

SMC_DEBUG_NO

R4652

1 2

0.01uF

16V

CERM

402

20%

C4605

1

2

MSOP

CRITICAL

TPS2069DGNXG4

Q4690

4

1

2 3

5

6

7

8

9

90-OHM-100MA

DLP11S

L4600

1 2

34

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

External USB Connector

43 92

A.0.0

051-7431

USB2_RT_N

USB2_RT_P

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_ILIM

USB2_EXTA_MUXED_P

USB2_EXTA_MUXED_N

MIN_NECK_WIDTH=0.5 mm

MIN_LINE_WIDTH=0.5 mm VOLTAGE=5V

PP5V_S3_RTUSB_F

PP5V_S5

PM_S4_STATE_L

USB_DEBUGPRT_EN_L

USB_EXTA_N USB_EXTA_P

SMC_RX_L

SMC_TX_L

PP3V42_G3H

USB_EXTA_OC_L

79

81

75

66

65

63

57

62

48

61

47

60

46

58

45

42

28

27

8

91

91 91

91

8

7

BI

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Left Clutch Barrel Interconnect

Camera LDO_EN Camera RST_L Camera Power Camera Power Camera Ground

Camera Clk TwinAx Shield

Camera Clk+

Camera Clk-

Camera D TwinAx Shield

Camera Ground

Camera TwinAx Shield

Connector shield

Camera DCamera D+

514S0171

MIC

NC

Camera Ground

Mic Data

I2C Clk

I2C Data

Mic Clk

Camera Power

Camera Ground

Camera LED Ctrl

(Rsv’d)

Camera USB D-

USB I/F

(Wave 2)

Camera USB D+

CCP2 I/F

Camera Power

0.01UF

10% X7R

402

50V

C4730

1

2

0603

FERR-220-OHM-2A

CRITICAL

L4730

1 2

CRITICAL

F-RT-SM

20347-125E-12

J4731

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25

26 27 28 29

3

30

31

32

4 5 6 7 8 9

24 86

CRITICAL

DLP11S

90-OHM-100MA

FL4735

1 2

34

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

Left Clutch Barrel Interconnect

051-7431

A.0.0

9244

GND GND GND

GND

PP5V_S3

GND

PP5V_S3_CAMERA_F

MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm

TP_I2S_MIC_SDA

TP_I2S_MIC_SCL

GND

USB_CAMERA_P

USB_CAMERA_F_P

USB_CAMERA_N

USB_CAMERA_F_N

81 58 46

8

91

7

IN

OUT

IN

OUT

IN IN IN IN IN IN IN IN

IN

OUT IN

OUT

P20

P22 P23 P24 P25 P26 P27

P11

P17

P15

P14

P13

P12

P10

P16

P21

P51

P50

P45

P60/KIN0* P61/KIN1* P62/KIN2* P63/KIN3* P64/KIN4* P65/KIN5*

P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6 P77/AN7

P30/LAD0 P80/PME* P31/LAD1 P81/GA20 P32/LAD2

P82/CLKRUN* P33/LAD3 P83/LPCPD* P34/LFRAME* P35/LRESET* P36/LCLK P37/SERIRQ

P90/IRQ2* P40/TMIO P91/IRQ1* P41/TMO0 P92/IRQ0* P42/SDA1 P93/IRQ12*

P94/IRQ13*

P44/TMO1 P95/IRQ14*

P96/EXCL

P52/SCL0

P43/TMI1/EXSCK1

P46/PWX0/PWM0 P47/PWX1/PWM1

P66/IRQ6*/KIN6* P67/IRQ7*/KIN7*

P84/IRQ3*/TXD1 P85/IRQ4*/RXD1

P86/IRQ5*/SCK1/SCL1

P97/IRQ15*/SDA0

(1 OF 4)

PB7

PB6

PB2 PB3 PB4 PB5

PH5

PH4

PE0

PA0/KIN8*/PA2DC PA1/KIN9*/PA2DD

PE1*/ETCK PA2/KIN10*/PS2AC PE2*/ETDI PA3/KIN11*/PS2AD PE3*/ETDO PA4/KIN12*/PS2BC PE4*/ETMS PA5/KIN13*/PS2BD

PF0/IRQ8*/PWM2

PA6/KIN14*/PS2CC

PF1/IRQ9*/PWM3

PA7/KIN15*/PS2CD

PF2/IRQ10*/TMOY PB0/LSMI* PF3/IRQ11*/TMOX PB1/LSCI PF4/PWM4

PF5/PWM5 PF6/PWM6 PF7/PWM7

PG0/EXIRQ8*/TMIX PG1/EXIRQ9*/TMIY

PG2/EXIRQ10*/SDA2 PC0/TIOCA0/WUE8* PG3/EXIRQ11*/SCL2 PC1/TIOCB0/WUE9* PG4/EXIRQ12*/EXSDAA PC2/TIOCC0/TCLKA/WUE10* PG5/EXIRQ13*/EXSCLA PC3/TIOCD0/TCLKB/WUE11* PG6/EXIRQ14*/EXSDAB PC4/TIOCA1/WUE12* PG7/EXIRQ15*/EXSCLB PC5/TIOCB1/TCLKC/WUE13*

PH0/EXIRQ6*

PC6/TIOCA2/WUE14*

PH1/EXIRQ7*

PC7/TIOCB2/TCLKD/WUE15*

PH2/FWE

PD0/AN8

PH3/EXEXCL PD1/AN9 PD2/AN10 PD3/AN11 PD4/AN12 PD5/AN13 PD6/AN14 PD7/AN15

(2 OF 4)

VCL

AVREF

VCC

AVCC

XTAL EXTAL

AVCC

VCC

MD1 MD2

NMI

RES*

ETRST*

AVREF

AVSS

VSS

(3 OF 4)

NC22

NC21

NC20

NC19

NC18

NC17

NC16

NC15

NC14

NC13

NC12

NC9

NC6

NC11

NC10

NC8

NC7

NC5

NC4

NC3

NC2

NC1

NC0

(4 OF 4)

OUT OUT

BI

IN

OUT

BI

OUT

IN

IN OUT

OUT

IN

OUT OUT OUT OUT

IN

IN IN

IN

IN IN

IN

OUT

IN

OUT OUT OUT OUT

BI BI BI BI BI BI

OUT OUT

OUT

IN

OUT

IN

OUT OUT

BI

OUT

IN

OUT

IN

BI BI BI BI

IN IN IN

OUT

BI

IN IN IN IN

BI

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(OC)

(DEBUG_SW_1) (DEBUG_SW_2)

(OC)

(OC) (OC)

(OC)

pins designed as outputs can be left floating,

NOTE: Unused pins have "SMC_Pxx" names. Unused

those designated as inputs require pull-ups.

(DEBUG_SW_3)

NC

NC NC

NC

NC NCNC

NC

NC NC NC

NC

NC NC NC NC NC

NOTE: SMS Interrupt can be active high or low, rename net accordingly. If SMS interrupt is not used, pull up to SMC rail.

CERM-X5R

22UF

20%

6.3V

805-3

C4902

1

2

7

25 46 47

7

46 47

7

46 81

CERM-X5R

0.47UF

PLACEMENT_NOTE=Place C4907 close to U4900 pin F1

10% 402

6.3V

C4907

1

2

CERM

10V

0.1UF

402

20%

C4903

1

2

PLACEMENT_NOTE=Place C4920 close to U4900 pins N14,N15

CERM

10V

0.1UF

402

20%

C4920

1

2

MF-LF

5%

1/16W

4.7

402

PLACEMENT_NOTE=Place R4999 close to U4900 pins N14,N15

R4999

1 2

CERM

10V

0.1UF

402

20%

C4904

1

2

SM

XW4900

1

2

25

7

59

CERM

10V

0.1UF

402

20%

C4905

1

2

7

25

46 60

28 46 65

38

CERM

10V

0.1UF

402

20%

C4906

1

2

49

7

46 57

34 46 57 66

7

43 45 46 47

7

43 45 46 47

36 40 46 57

60 65

OMIT

SMC_H8S2116

BGA

U4900

B12 C13 A15 B14 B15 C14 D12 C15

D13 D14 D15 E12 E14 E15 E13 F14

D9 C9 A9 B9 D8 C8 A8 D7

A5 B5 D5 C3 B1 C2 D3 C1

G1 G4 F2

L13 L14 L15 K12 K13 K14 J12 J13

N12 R13 P13 R14 P14 R15 N13 P15

C7 A7 B7 D6 C6 A6 B6

K4 J2 J1 J3 J4 H2 H1 G2

BGA

OMIT

SMC_H8S2116

U4900

R3 P3 R2 N3 R1 N2 M4 N1

B10 A10 D10 A11 B11 C11 A12 D11

G14 G15 G13 G12 H14 H15 H13 H12

M11 P11 R11 N11 P10 R10 N10 M10

M3 M2 M1 L4 L2

M7 P6 R6 N6 M6 R5 P5 N5

P9 R9 N9 P8 R8 M8 P7 R7

E1 F3 K2 C4 D4 B3

OMIT

SMC_H8S2116

BGA

U4900

N14

N15

M14

M15

P12 R12

L1

B2

E2 K1

F4

E3

P2P1J15A1F1

D1P4R4

F12

F13

B13

A13

A4B4D2

A2

OMIT

SMC_H8S2116

BGA

U4900

G3 H3

K15 J14

F15 A14 C12 C10 C5 A3 B8 E4

K3

H4 M9 N8

L3 N4 M5

N7 M12 M13 L12

46 66

48 55 88

1/16W

5%

MF-LF

10K

402

R4909

1

2

7

47

7

47

1/16W

5%

10K

402

MF-LF

R4901

1

2

10K

MF-LF

5% 1/16W

402

R4902

1

2

1/16W

5% MF-LF

0

NO STUFF

402

R4903

1

2

1/16W

5% MF-LF

10K

402

R4998

1

2

43

34 46

16 32

25

7

49

42

34 46

34

25

46

52

46

52

55

49

55

54

49

7

46 47

46

7

46 47

7

46 47

7

46 47

46 81

66

46

66

46

7

48 57 88

7

48 57 88

34 48 51 81 88

48 51 53 88

46

7

34 54

55

49

7

43 45 46 47

7

43 45 46 47

46

9

55

46

7

25 47

16 31

7

25 28

7

47

13 25

7

25 47

7

25

46

7

23 47

7

23 47

7

23 47

7

23 47

7

23 47

7

28

30 88

54

48 51 74 88

7

25 35 36 40 49 58 62 65

7

25 34 43 58 65

7

25 46

48 51 74 88

48 55 88

46

051-7431

A.0.0

9245

SMC

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

TP_SMC_P64

TP_SMC_P63

TP_SMC_P62

SMC_ADAPTER_EN

SMC_GPU_ISENSE

TP_SMC_P14

SMC_P67

PM_LAN_PWRGD

TP_SMC_GFX_THROTTLE_L

SMC_ENRGYSTR_LDO_EN

TP_SMC_P43

SMC_SYS_LED

SMBUS_SMC_MGMT_SCL

SMC_WAKE_SCI_L TP_SMC_P81

SMC_TX_L

SMC_DCIN_ISENSE SMC_PBUS_VSENSE SMC_BATT_ISENSE SMC_NB_1V25_ISENSE

PM_SLP_S5_L

SMC_PG0

SMC_ONOFF_L

SMC_RX_L

PM_SUS_STAT_L

PM_CLKRUN_L

SMC_GPU_VSENSE

PP3V3_S5_AVREF_SMC

SMC_TCK

TP_SMC_PF0 TP_SMC_PF1 SMC_LID

SMBUS_SMC_BSA_SCL

SMC_TMS

SMC_TDO

TP_SMC_BATT_VSET SMC_SYS_ISET

PM_SLP_S3_L

PM_PWRBTN_L

SMC_PROCHOT_3_3_L

SMC_SMS_INT

SMBUS_SMC_A_S3_SCL

TP_SMC_FAN_2_TACH

SMS_Y_AXIS SMS_Z_AXIS SMC_P1V8S0GPU_ISENSE

SMC_FAN_1_CTL

IMVP_VR_ON

TP_SMC_P20 TP_SMC_P21

PM_RSMRST_L

ALS_RIGHT

ALS_LEFT

SMC_NB_1V8_ISENSE

SMC_NB_CORE_ISENSE

SMS_X_AXIS

TP_SMC_FAN_3_TACH

SMC_FAN_0_CTL

PM_EXTTS_L<1>

USB_DEBUGPRT_EN_L

TP_SMC_P46

TP_SMC_P44

INT_SERIRQ

SMBUS_SMC_0_S0_SCL

SMC_RX_L

SMC_TX_L

SMC_SYS_KBDLED

SMBUS_SMC_MGMT_SDA

PCI_CLK33M_SMC

SMC_LRESET_L

LPC_FRAME_L

LPC_AD<3>

LPC_AD<2>

LPC_AD<1>

LPC_AD<0>

SMC_BATT_CHG_EN

SMC_BATT_TRICKLE_EN_L

ALL_SYS_PWRGD

SMC_RSTGATE_L

RSMRST_PWRGD

TP_SMC_P27

TP_SMC_P26

TP_SMC_P23

SMC_KBC_MDE

SMC_TRST_L

SMC_NMI

SMC_VCL

PM_EXTTS_L<0>

SMC_PA0 SMC_PA1

PP3V42_G3H

SMC_MD1

PP3V3_S5_SMC_AVCC

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

GND_SMC_AVSS

SMC_RESET_L SMC_XTAL

SMC_EXTAL

PM_G2_EN

SMC_CPU_ISENSE SMC_CPU_VSENSE

SMC_BC_ACOK SMC_BS_ALRT_L

PM_S4_STATE_L

SUS_CLK_SB SMBUS_SMC_0_S0_SDA

SMC_CASE_OPEN

SMC_TDI

SMBUS_SMC_BSA_SDA

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_B_S0_SDA

SMC_PROCHOT

SMBUS_SMC_B_S0_SCL

SMC_THRMTRIP

ALS_GAIN

SMC_FWE

SMS_ONOFF_L

PM_BATLOW_L

SYS_ONEWIRE

SMC_PB0

SMC_EXCARD_PWR_EN

SMC_EXCARD_CP

SMC_RUNTIME_SCI_L SMC_ODD_DETECT ISENSE_CAL_EN

SMC_EXCARD_OC_L TP_SMC_GFX_OVERTEMP_L

TP_SMC_FAN_2_CTL TP_SMC_FAN_3_CTL SMC_FAN_0_TACH SMC_FAN_1_TACH

TP_SMC_SYS_VSET

SMC_BATT_ISET

PM_SYSRST_L

SMC_PF3

SMC_PH4

TP_SMC_P22

PM_LAN_ENABLE

81

66 65 57 48 47 46 43

66

28

54

46

8

49

46

9

46

7

46

46 46

46

G

D

S

NC

CD

GND

OUT

VDD

OUT

IN

OUT

IN

OUT

IN

BI

OUT

IN

G

D

S

OUT

IN

OUT

GND

OUT

IN

G

S

D

OUT

TABLE_ALT_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC

S5 Rail PWRGD Circuit

LAN PWRGD Circuit

SMC FSB to 3.3V Level Shifting

TO CPU

TO SMC

TPS51120 PGOOD threshold 87-93% (4.35 - 4.65V)

TPS51120 PGOOD threshold 87-93% (2.87 - 3.07V)

Reports when 5V S5 and 3.3V S5 are in regulation

SMC Crystal Circuit

System (Sleep) LED Circuit

Debug Power "Button"

SMC Reset "Button" / Brownout Detect

SMC AVREF Supply

CERM

20%

0.1uF

10V 402

C5000

1

2

2N7002DW-X-F

SOT-363

Q5059

6

2

1

0.47UF

6.3V

10% CERM-X5R

402

C5020

1

2

0.01UF

10% 16V

402

CERM

C5026

1

2

603

X5R

20%

6.3V

10uF

C5025

1

2

5%

0

1/16W

402

MF-LF

R5095

1 2

402

MF-LF

5%

1/16W

10K

R5070

1 2

402

1/16W5%MF-LF

100K

R5071

1 2

402

1/16W MF-LF

5%

10K

R5072

1 2

MF-LF

5%

1/16W

10K

402

R5073

1 2

100K

5%

MF-LF1/16W

402

R5074

1 2

2.0K

MF-LF

5%

1/16W

402

ONEWIRE_PU

R5075

1 2

MF-LF

5%

1/16W

100K

402

R5076

1 2

MF-LF

5%

1/16W

10K

402

R5077

1 2

10K

1/16W5%MF-LF

402

R5078

1 2

10K

5%

1/16W MF-LF

402

R5079

1 2

10K

1/16W5%MF-LF

402

R5080

1 2

10K

1/16W5%MF-LF

402

R5083

1 2

10K

1/16W5%MF-LF

402

R5084

1 2

1/16W MF-LF

5% 402

10K

R5085

1 2

1/16W5%MF-LF

402

10K

R5086

1 2

5%

470K

402

MF-LF1/16W

R5087

1 2

10K

1/16W

5% 402

MF-LF

R5088

1 2

5X3.2-SM

CRITICAL

20.00MHZ

Y5010

1

2

RN5VD30A-F

SOT23-5A

CRITICAL

U5000

5

3

4

1

2

100K

402

MF-LF

5%

1/16W

R5089

1 2

5%

100K

402

MF-LF1/16W

R5090

1 2

7

45 47

MF-LF

5%

1/16W

10K

402

R5082

1 2

402

MF-LF

5%

1/16W

10K

R5081

1 2

45

10 16 23 83

603

MF-LF

0

1/10W

OMIT

5%

R5001

1

2

603

5% MF-LF

0

1/10W

OMIT

R5015

1

2

MF-LF 402

5% 1/16W

100K

R5045

1

2

45 46 60 45 46 60

402

0.0022UF

10% 50V CERM

C5045

1

2

45 46 60

MMDT3904XF

SOT-363-LF

Q5060

5

3

4

MF-LF

1/16W

5%

402

3.3K

R5061

1

2

MMDT3904XF

SOT-363-LF

Q5060

2

6

1

3.3K

1/16W

5%

MF-LF

402

R5062

1 2

470

402

MF-LF

1/16W

5%

R5060

1

2

10 59 83

45

SOT-363

2N7002DW-X-F

Q5059

3

5

4

100K

1/16W5%MF-LF

402

R5091

1 2

100K

5%

MF-LF1/16W

402

R5093

1 2

100K

MF-LF

5%

1/16W

402

R5092

1 2

402

MF-LF

5%

1/16W

10K

R5096

1 2

402

MF-LF

5%

1/16W

10K

R5094

1 2

5%

402

NO STUFF

1/16W MF-LF

100K

R5097

1

2

0

402

5%

MF-LF

1/16W

R5098

1 2

45 28 45 65

9

45 46 66

SOT23-3

CRITICAL

REF3333

VR5020

3

1 2

45

2N7002

SOT23-LF

Q5032

3

1

2

MF-LF

402

1/16W

1%

9.09K

R5032

1

2

2.37K

1/16W MF-LF

402

1%

R5031

1

2

1/16W

100

MF-LF

5%

402

R5030

1

2

SOT23-LF

2N3906

Q5030

1

3

2

7

81

1/16W

5% MF-LF

1K

402

R5000

1

2

7

45 46 81

5%

CERM

15pF

402

50V

C5010

1 2

402

50V

15pF

5%

CERM

C5011

1 2

10%

0.01UF

16V

CERM

402

C5001

1

2

SYNC_DATE=10/15/2007

051-7431

A.0.0

9246

SYNC_MASTER=M87_MLB

SMC Support

ALL

353S1381

Intersil ISL60002-33

353S1278

SYS_LED_L

SYS_LED_ANODE

SYS_LED_ILIM

PP5V_S3

SYS_LED_L_VDIV

SMC_SYS_LED

MIN_LINE_WIDTH=0.4 mm

PP3V3_S5_AVREF_SMC

VOLTAGE=3.3V

MIN_NECK_WIDTH=0.2 mm

PP3V3_S0

SMC_XTAL

SMC_EXTAL

PP3V42_G3H

TP_SMC_P64

PP3V3_S5

SMC_BATT_CHG_EN

SMC_ENRGYSTR_LDO_EN

MAKE_BASE=TRUE

TP_SMC_PF1

MAKE_BASE=TRUE

TP_SMC_PF0

TP_SMC_P81

MAKE_BASE=TRUE

TP_SMC_P63 TP_SMC_P63

MAKE_BASE=TRUE

TP_SMC_P64

TP_SMC_P46

MAKE_BASE=TRUE

TP_SMC_P46

TP_SMC_P62

MAKE_BASE=TRUE

TP_SMC_P62

PM_LAN_PWRGD

SUS_CLK_SB

SMC_ONOFF_L

ALL_SYS_PWRGD

PP3V42_G3H

SMC_PROCHOT_3_3_L

PP3V3_S0

TP_SMC_P14

MAKE_BASE=TRUE

TP_SMC_P14 TP_SMC_P20

MAKE_BASE=TRUE

TP_SMC_P20

TP_SMC_SYS_VSET

MAKE_BASE=TRUE

TP_SMC_SYS_VSET

TP_SMC_BATT_VSET TP_SMC_BATT_VSET

MAKE_BASE=TRUE

SMC_PF3

SMC_TCK

SMC_TDI

SMC_TMS SMC_TDO

SMC_BS_ALRT_L

SYS_ONEWIRE

SMC_RX_L

SMC_LID SMC_FWE SMC_TX_L

SMC_ONOFF_L

SMC_PB0

SMC_PA1

SMC_PA0

SMC_CASE_OPEN

EXCARD_OC_L

RSMRST_PWRGD

MAKE_BASE=TRUE

RSMRST_PWRGD

PM_SLP_S5_L

SMC_BC_ACOK SMC_EXCARD_CP PM_SUS_STAT_L

SMC_RESET_L

MAKE_BASE=TRUE

TP_SMC_FAN_2_CTLTP_SMC_FAN_2_CTL

MAKE_BASE=TRUE

TP_SMC_FAN_2_TACHTP_SMC_FAN_2_TACH

MAKE_BASE=TRUE

TP_SMC_FAN_3_TACHTP_SMC_FAN_3_TACH

MAKE_BASE=TRUE

TP_SMC_FAN_3_CTLTP_SMC_FAN_3_CTL

MAKE_BASE=TRUE

TP_SMC_GFX_OVERTEMP_LTP_SMC_GFX_OVERTEMP_L

MAKE_BASE=TRUE

TP_SMC_GFX_THROTTLE_LTP_SMC_GFX_THROTTLE_L

MAKE_BASE=TRUE

TP_SMC_P21TP_SMC_P21 TP_SMC_P22

MAKE_BASE=TRUE

TP_SMC_P22

MAKE_BASE=TRUE

TP_SMC_P23TP_SMC_P23

MAKE_BASE=TRUE

TP_SMC_P26TP_SMC_P26

MAKE_BASE=TRUE

TP_SMC_P27TP_SMC_P27 TP_SMC_P43

MAKE_BASE=TRUE

TP_SMC_P43

MAKE_BASE=TRUE

TP_SMC_P44TP_SMC_P44

PP1V05_S0

CPU_PROCHOT_BUF

CPU_PROCHOT_L

CPU_PROCHOT_L_R

SMC_PROCHOT

PM_THRMTRIP_L

SMC_THRMTRIP

SMC_PG0

SMC_P67

SMC_MANUAL_RST_L

SMC_ADAPTER_EN

SMC_BATT_TRICKLE_EN_L

SMC_PH4

PP3V42_G3H

SMC_EXCARD_OC_L

TP_SMC_PF1

TP_SMC_PF0

TP_SMC_P81

SUS_CLK_SB

MAKE_BASE=TRUE

SMC_ENRGYSTR_LDO_EN

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

GND_SMC_AVSS

MIN_LINE_WIDTH=0.4 mm

91

82

65

59

58

53

52

51

50

48

47

46

42

32

61

31

50

30

91

30

29

81

76

81 29

27

81

28

66

65

66 28

26

66

27

65

60

65 27

23

65

26

57

58

57 26

21

57

25

48

56

48 25

19

48

24

47

48

47 24

18

47

23

46

28

46 23

14

46

81

21

45

27

45 21

13

45

58

19

43

26

43 19

47

81

66

47

12

57

43

66

44

16

28

25

46

28 16

47

57

45

46

45

57

45

11

45

28

46

54

8

13

8

46

24

66

46

46 46

46

46 46

45

8

13

46 46

45

43

81

43

45

34

25

45

25

46

46 46

46

46 46

10

40

66

8

46

45

49

7

45

8

45

7

45

8

45

45 45

45

45 45

25

7 8

45 45

45

7

34

7

45

7

45

24

7

34

7

45

45 45

8

45

36

45

7

45

25

9

45

BI

IN

OUT OUT OUT

OUT

IN

BI

OUT OUT OUT

OUT

IN

OUT

IN

OUT

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

FWH_INIT_L Generation

LPC+ Connector

516S0394

7

23 45

7

25 45

7

30 88

7

25 45 46

7

25 45

7

24 38 87

7

45 46

7

45

7

45

7

28

7

23 45

7

23 45

7

23 45

7

45 46

7

45 46

7

45

7

25

LPCPLUS

SOT-363-LF

MMDT3904XF

Q5190

5

3

4

MMDT3904XF

SOT-363-LF

PLACEMENT_NOTE=Place Q5190 close to R5190

LPCPLUS

Q5190

2

6

1

402

5% 1/16W MF-LF

LPCPLUS

330

R5192

1

2

1.3K

402

MF-LF

1/16W

5%

LPCPLUS

R5191

1

2

PLACEMENT_NOTE=Place R5190 to minimize CPU_INIT_L stub

1/16W

5%

MF-LF

402

330

LPCPLUS

R5190

1 2

10 23 83

7

43 45 46

7

43 45 46

7

45 46

7

45 46

QT500306-L021-9F

M-ST-SM

LPCPLUS

CRITICAL

J5100

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

25

26

27

28

29

3

30

31

32

33

34

4

5

6

7

8

9

7

23 45

SYNC_MASTER=M87_MLB

A.0.0

9247

051-7431

LPC+ Debug Connector

SYNC_DATE=08/28/2007

PP3V42_G3H PP5V_S0

LPC_AD<0> LPC_AD<1>

LPC_FRAME_L PM_CLKRUN_L PCI_FW_GNT_L SMC_TMS

CPU_INIT_LS3V3

FWH_INIT_L PCI_CLK33M_LPCPLUS

LPC_AD<2> LPC_AD<3>

INT_SERIRQ PM_SUS_STAT_L SMC_TDI SMC_TCK SMC_RESET_L SMC_NMI SMC_RX_L

LINDACARD_GPIO

DEBUG_RESET_L SMC_TRST_L SMC_TDO SMC_MD1 SMC_TX_L

CPU_INIT_L

PP3V3_S0

CPU_INIT_R_L

91 82 65 59 58 53 52

51 50 48 46 42 32 31

82

30

81

29

81

80

28

66

65

27

65

59

26

57

58

25

48

54

24

46

52

23

45

49

21

43

42

19

28

27

16

8

13

7

8

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(MASTER)

(Address determined by ARP)

Left I/O SMBus Connections:

SMC

(Write: 0xA0 Read: 0xA1)

(Write: 0xD2 Read: 0xD3)

ExpressCard Slot

U2300

(MASTER?)

ICH8-M

(See Table)

Left I/O

J3400

ICH8-M

U2300

(MASTER)

Battery

(MASTER)

U4900

SO-DIMM "A"

U4900

SMC

(MASTER)

J3100

J3200

CY28545-5: U2900

(Write: 0xA4 Read: 0xA5)

ICH8-M ME SMBus Connections

Clock Chip

U5900

SO-DIMM "B"

J6950

J3400

SMC "Management" SMBus Connections

SMC

(Write: 0x98 Read: 0x99)

U4900

(Write: 0x98 Read: 0x99)

Left I/O Board

J9600

Top-Case

TMP275

(Write: 0x9E Read: 0x9F)

(See Table)

G84M: U8000

GPU Temp (Int)

(MASTER)

U4900

Battery Charger

(Write: 0x92 Read: 0x93)

CPU Temp

(MASTER)

U4900

SMC

(Write: 0x16 Read: 0x17)

SMC "0" SMBus Connections

SMC "Battery A" SMBus Connections

(Write: 0x98 Read: 0x99)

(Write: 0x30 Read: 0x31)

GPU Temp (Ext)

TMP401: U5550

(Write: 0x92 Read: 0x93)

SMS

The bus formerly known as "Battery B"

M35C - TMP106

(Write: 0x9E Read: 0x9F)

ICH8-M SMBus Connections

Left I/O SMBus Connections: Left ALS - TMP102

SMC "A" SMBus Connections

(Write: 0x90 Read: 0x91)

SMC "B" SMBus Connections

TMP102:U5750

NOTE: SMC RMT bus remains powered and may be active in S3 state

Remote Temps

EMC1043-1: U5500

EMC1043-1: U5570

1/16W

5%

MF-LF

402

4.7K

R5200

1

2

5% 1/16W MF-LF 402

4.7K

R5201

1

2

4.7K

MF-LF

5%

402

1/16W

R5280

1

2

4.7K

402

MF-LF

1/16W

5%

R5281

1

2

4.7K

5% 1/16W

402

MF-LF

R5291

1

2

MF-LF

5%

402

4.7K

1/16W

R5290

1

2

3.3K

1/16W 402

MF-LF

5%

R5261

1

2

402

1/16W

5%

MF-LF

3.3K

R5260

1

2

MF-LF

1/16W 402

5%

3.3K

R5271

1

2

MF-LF

1/16W

5%

402

3.3K

R5270

1

2

402

1/16W

4.7K

5% MF-LF

R5251

1

2

4.7K

MF-LF

5%

402

1/16W

R5250

1

2

10K

5% 1/16W MF-LF 402

R5231

1

2

10K

5%

402

1/16W MF-LF

R5230

1

2

051-7431

9248

A.0.0

SYNC_MASTER=(MASTER)

SYNC_DATE=(MASTER)

SMBus Connections

SMBUS_SMC_A_S3_SDA

PP3V3_S0

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL SMBUS_SMC_B_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_A_S3_SCL

PP3V3_S3

SMBUS_SMC_A_S3_SCL SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_B_S0_SDA SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SCL

SMBUS_SMC_A_S3_SDA

SMBUS_SMC_A_S3_SCL

PP3V3_S0GPU

SMBUS_SMC_0_S0_SCL SMBUS_SMC_0_S0_SDA

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_0_S0_SCL

PP3V42_G3H

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_A_S3_SCLSMBUS_SMC_0_S0_SCL

PP3V3_S0

SMBUS_SB_SCL

SMBUS_SB_SDASMBUS_SB_SDA

SMBUS_SB_SCL

SMBUS_SMC_BSA_SCL SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SCL SMBUS_SMC_MGMT_SDA

SMBUS_SMC_BSA_SDA

SMBUS_SMC_MGMT_SDA

SMBUS_SMC_MGMT_SCL

PP3V3_S3

PP3V3_S5

MAKE_BASE=TRUE

SMBUS_SB_ME_SCL

MAKE_BASE=TRUE

SMBUS_SB_ME_SDASMBUS_SB_ME_SDA

SMBUS_SB_ME_SCL

SMBUS_SB_SDA

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SCL

MAKE_BASE=TRUE

SMBUS_SMC_BSA_SDA

SMBUS_SMC_A_S3_SDA

MAKE_BASE=TRUE

SMBUS_SMC_MGMT_SDA

SMBUS_SB_SCL

SMBUS_SB_SDA

SMBUS_SB_SCL SMBUS_SB_SDA

SMBUS_SB_SCL

MAKE_BASE=TRUE

SMBUS_SB_SDA

MAKE_BASE=TRUE

91

82

65

59

58

53

52

51

50

48

47

46

42

32

31

30

91

29

76

28

81

28

81

65

27

65

66

27

65

60

26

58 80

65

26

58

25

55 76

57

25

55

56

24

54 75

47

24

86

86 86

86

54

46

86

88

23

88

51

88

74

46

88

23

48

48 48

48

51

28

48

88

48

81

21

88

81

50

81

88

81

73

88

45

88

81

88

21

34

34 34

34

88

50

27

34

81

34

51

19

53

51

48

51

53

74

88

51

72

74

57

74

43

74

51

74

19

32

32 32

32

57

88

57

88

48

26

32

51

88

32

48

16

51

48

38

48

51

55

48

65

51

48

51

28

51

48

51

16

31

31 31

31

48

55

48

55

38

25

86

31

48

55

31

45

13

48

45

36

45

48 48

48

45

58

48

45

48

8

48

45 48

13

29

29 29

29

45

48

45

48

36

24

48

29

45

48

29

34

8

45

34

8

34

45 45

45

34

8

45

7

45

7

45

34 45

8

25

25 25

25

7

45

7

45

8

25

34

45

25

IN

OUT

N-CHN

S

D

G

P-CHN

G

D

S

D

S

G

IN

ININ

IN

OUT

IN

OUT

IN

OUT

IN IN

OUT

OUTOUT

OUT

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CPU Voltage Sense / Filter

CPU Current Sense Filter

GPU Current Sense Filter

Current Sense Calibration Circuit

Switches in fixed load on power supplies to calibrate current sense circuits

Place RC close to SMC

Enables PBUS VSense divider when high.

S0/GPU 1.25V Current Sense Filter

Place RC close to SMCPlace RC close to SMC

NB 1.8V Current Sense Filter

PBUS Voltage Sense & Filter

Place RC close to SMC

Rthevanin = 4573 ohms

Place RC close to SMC

Battery (PBUS) Current Sense Filter

Place RC close to SMC

DCIN Current Sense Filter

Place RC close to SMCPlace RC close to SMC

Place RC close to SMC

Place short near U1000 center

Place short near U8000 center

Place RC close to SMC

NB Core Current Sense Filter

1.8V FB Current Sense Filter

GPU Voltage Sense / Filter

Place RC close to SMC

7

45

100K

5% 1/16W MF-LF

402

R5327

1

2

100K

402

MF-LF

1/16W

5%

R5315

1

2

45

402

MF-LF

1/16W

1%

27.4K

R5385

1

2

20% X5R

402

0.22UF

6.3V

C5385

1

2

1% 1/16W MF-LF

402

5.49K

R5386

1

2

SC70-6

FDG6332C_NL

Q5315

6

2

1

SC70-6

FDG6332C_NL

Q5315

3

5

4

FDM6296

CRITICAL

MICROFET3X3

Q5320

5

4

1 2 3

1/16W

1%

402

4.53K

ISL9504B

MF-LF

R5331

1 2

59 65

1206

MF-LF

1/4W

1%

1.00

R5322

1

2

50 50

100K

402

MF-LF

1/16W

5%

R5316

1

2

SN74AHCT1G125DCKRE4

SC70-5

U5327

2

3 1

5

4

1/16W MF-LF

5%

402

1K

R5328

12

0.1UF

20% 10V

402

CERM

C5327

1 2

1%

MF-LF

402

4.53K

1/16W

R5365

1 2

50

6.3V 402

X5R

20%

0.22UF

C5365

1

2

45 49

CRITICAL

SOT23-3

SI2302ADSE3

Q5322

3

1

2

45

20%

6.3V X5R 402

0.22UF

C5359

1

2

1/16W

1%

MF-LF

402

4.53K

R5359

1 2

45

1/16W

4.53K

402

MF-LF

1%

R5370

1 2

20% X5R

402

0.22UF

6.3V

C5370

1

2

50 45

402

20% X5R

6.3V

0.22UF

C5375

1

2

402

1% 1/16W MF-LF

4.53K

R5375

1 2

50

45

402

6.3V

0.22UF

X5R

20%

C5380

1

2

1/16W

4.53K

402

MF-LF

1%

R5380

1 2

53 53

4.53K

402

MF-LF

1/16W

1%

R5390

1 2

6.3V

0.22UF

402

X5R

20%

C5390

1

2

45

6.3V

0.22UF

402

X5R

20%

C5340

1

2

4.53K

402

MF-LF

1%

1/16W

R5340

1 2

45

0.22UF

20%

6.3V 402

X5R

C5335

1

2

402

MF-LF

1%

1/16W

4.53K

R5335

1 2

45

0.22UF

402

20% X5R

6.3V

C5330

1

2

1/16W

1%

MF-LF

402

ISL9504A

4.53K

R5330

1 2

50

SM

XW5359

1 2

45

402

1%

4.53K

MF-LF

1/16W

R5309

1 2

402

X5R

20%

0.22UF

6.3V

C5309

1

2

SM

XW5309

1 2

1206

MF-LF

1/4W

1%

1.00

R5320

1

2

49 92

A.0.0

051-7431

Current & Voltage Sensing

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

GND_SMC_AVSS

SMC_GPU_VSENSE

SMC_GPU_ISENSE

P1V8_S0GPU_IOUT

PPVCORE_S0_CPU

SMC_P1V8S0GPU_ISENSE

PPVCORE_GPU

SMC_P1V8S0GPU_ISENSE

MAKE_BASE=TRUE

SMC_P1V8S0GPU_ISENSE

NBCORE_IOUT

GND_SMC_AVSS

SMC_NB_CORE_ISENSE

GND_SMC_AVSS

P1V8_S3_IOUT

GPUVCORE_IOUT

PPVCORE_S0_CPU

LIO_DCIN_ISENSE

SMC_NB_1V8_ISENSE

SMC_DCIN_ISENSE

GND_SMC_AVSS

GND_SMC_AVSS GND_SMC_AVSS

CPUVCORE_ISENSE_CAL

MIN_LINE_WIDTH=0.50 mm MIN_NECK_WIDTH=0.20 mm

SMC_BATT_ISENSE

GND_SMC_AVSS

LIO_BATT_ISENSE

GND_SMC_AVSS

PPVCORE_GPU

SMC_CPU_VSENSE

CPUVSENSE_IN

GPUVSENSE_IN

PPBUS_G3H

GND_SMC_AVSS

MIN_LINE_WIDTH=0.20 mm MIN_NECK_WIDTH=0.20 mm VOLTAGE=18.5V

PPBUS_G3H_VSENSE

GND_SMC_AVSS

SMC_NB_1V25_ISENSE

SMC_PBUS_VSENSE

PBUSVSENS_EN_DIV

PM_SLP_S3_L

PBUSVSENS_EN_L

CPUVCORE_IOUT

SMC_CPU_ISENSE

IMVP6_IMON

PP5V_S0

ISENSE_CAL_EN_LS5V_R

ISENSE_CAL_EN

P1V25_S0_IOUT

GPUCORE_ISENSE_CAL

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.50 mm

ISENSE_CAL_EN_LS5V

82 79

82

75

81

66

80

63

65

62

65

59

61

62

58

60

58

54

59

45

52

49

75 49

75

58

40

47

54

12

68

54

12

54

54 54 54

54

68

57

54

36

42

49

11

49

11

49

49 49 49

49

40

49

35

27

46

8

49

8

49

46

8

46

46 46 46

46

8

46

25

8

45

7

45

7

45

7

45

45 45 45

45

7

45

7

OUT

IN-

V+

V-

IN+

SHDN*

IN-

V+

V-

IN+

SHDN*

OUT

IN-

V+

V-

IN+

SHDN*

OUT

R1-

R1+

R2

V-

V+

+

OUT

IN

OUT

R1-

R1+

R2

V-

V+

+

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

GPU VCore Current Sense

Gain = 66:1

Gain = 165:1

Gain = 100:1

Gain = 66:1

Gain = 4.83:1

402

X5R

16V

10%

0.1UF

C5410

1

2

49

210K

1% 1/16W MF-LF 402

R5412

1

2

1/4W

1%

CRITICAL

1206

MF-LF

0.005

R5445

1 2 3 4

MF

1206

1/4W

0.002

1%

CRITICAL

R5425

1 2 3 4

MF

CRITICAL

1/4W

0.002

1206

1%

R5435

1 2 3 4

CRITICAL

MAX4245AXT-T

SC70-6

U5410

3

1

4

5

6

2

MF-LF

1%

402

1/16W

210K

R5411

1 2

3.16K

1/16W

1%

MF-LF

402

R5414

1 2

MF-LF

3.16K

402

1/16W

1%

R5415

1 2

0.005

1%

1206

MF-LF

1/4W

CRITICAL

R5413

1 2 3 4

CRITICAL

MAX4245AXT-T

SC70-6

U5440

3

1

4

5

6

2

210K

1/16W

402

1%

MF-LF

R5441

1 2

MF-LF

1%

210K

1/16W

402

R5442

1 2

3.16K

402

1% 1/16W MF-LF

R5443

1 2

402

3.16K

1/16W

1%

MF-LF

R5444

1 2

10% 50V

CERM

402

470PF

C5412

1

2

CERM

10% 50V

402

470PF

C5411

12

CERM

10% 50V

470PF

402

C5442

12

10% 50V

470PF

CERM

402

C5441

12

MF-LF

1/16W

1%

402

2.05K

R8993

1 2

1%

402

1/16W MF-LF

2.61K

R8991

1 2

1%

402

MF-LF

1/16W

10K

R8998

1 2

402

10%

0.1UF

16V X5R

C8995

1

2

50V 402

CERM

10%

470pF

C8998

12

49

SC70-6

MAX4245AXT-T

CRITICAL

U8995

3

1

4

5

6

2

10K

1% 1/16W MF-LF 402

NO STUFF

R8992

1

2

10% 50V

CERM

402

470PF

NO STUFF

C8992

1

2

50V

10%

402

CERM

470PF

C5400

1 2

1M

MF-LF

1%

402

1/16W

R5400

1 2

CERM

10V

20% 402

0.1UF

C5401

1

2

40.2K

1/16W

402

1%

MF-LF

R5402

1 2

NO STUFF

10V

20%

CERM

402

0.1UF

C5403

1

2

CRITICAL

SOT23-5

LMV2011MF

U5400

3

4

1

5

2

MF-LF

1%

1M

402

1/16W

R5404

1 2

CERM

10% 50V

470PF

402

C5405

12

1/16W

402

40.2K

1%

MF-LF

R5403

1 2

402

CERM

10V

20%

0.1UF

NO STUFF

C5404

1

2

49

MF-LF

1%

1/16W

10

402

R5420

1 2

0.1UF

402

X5R

16V

10%

C5420

1

2

50V 402

0.001UF

10%

CERM

C5422

1

2

MSOP

CRITICAL

INA326EA-250

U5420

3

2

6

1

8

5

4

7

MF-LF

1/16W

1%

100K

402

R5422

1

2

805-3

CERM-X5R

22UF

20%

6.3V

C5426

1

2

22UF

20%

6.3V CERM-X5R 805-3

C5425

1

2

402

1/16W

1% MF-LF

2.0K

SIGNAL_MODEL=EMPTY

R5421

1

2

49

59

402

1%

MF-LF

1/16W

10

R5430

1 2

49

50V

10%

402

CERM

0.001UF

C5432

1

2

X5R

10%

402

16V

0.1UF

C5430

1

2

1%

402

1/16W MF-LF

165K

R5432

1

2

22UF

20%

6.3V 805-3

CERM-X5R

C5436

1

2

INA326EA-250

CRITICAL

MSOP

U5430

3

2

6

1

8

5

4

7

22UF

6.3V CERM-X5R

20%

805-3

C5435

1

2

2.0K

MF-LF 402

1/16W

1%

SIGNAL_MODEL=EMPTY

R5431

1

2

49

402

0.1UF

10% 16V X5R

C5440

1

2

22UF

805-3

CERM-X5R

20%

6.3V

C5446

1

2

20%

6.3V

22UF

805-3

CERM-X5R

C5445

1

2

SYNC_MASTER=MASTER

SYNC_DATE=MASTER

Current Sensing

051-7431

A.0.0

9250

GFXIMVP6_IMON

GPUISENS_POS

PP1V8_S3

P1V8ISNS_P

P1V8ISNS_N

PP3V3_S0

P1V8GPUISNS_R_P

NBCORE_IOUT

PP1V8_S3_ISNS

P1V8ISNS_R_N

P1V8ISNS_R_P

P1V8GPUISNS_R_N

P1V8GPUISNS_N

P1V8_S0GPU_IOUT

PP1V8_S0GPU

PP1V8_S0GPU_ISNS

P1V8GPUISNS_P

PP1V25_S0_ISNS

NBCOREISNS_P

PP1V05_S0

NBCOREISNS_N

CPUCOREISNS_P

VOLTAGE=3.3V

PP3V3_S0_P1V25ISNS_VCC

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.25mm

CPUVCORE_IOUT

P1V25ISNS_N

P1V25ISNS_R1_P

P1V25ISNS_R1_N

NBCOREISNS_R2

PP3V3_S0

P1V25_S0_IOUT

P1V25ISNS_R2

IMVP6_DROOP

NBCOREISNS_R1_N

PP3V3_S0

P1V8_S3_IOUT

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.25mm VOLTAGE=3.3V

PP3V3_S0_NBCOREISNS_VCC

PP3V3_S0

PPVCORE_S0_NB_R

NBCOREISNS_R1_P

CPUCOREISNS_N

PP3V3_S3

P1V25ISNS_P

GPUVCORE_IOUT

PP1V25_S0

IMVP6_VO

PP3V3_S0

GPUISENS_NEG

91 82 65 59 58 53 52 51

50 48 47 46 42

32 31 30 29 28 27 26 25 24

21

91

23

91

16

82

19

65

59

58

53

52

51

50

48

47

46

42

32

61

32

31

46

31

30

29

27

29

28

26

28

27

23

27

81

27

26

78

72

21

26

65

26

25

77

69

19

25

58

25

24

74

67

18

24

55

24

91

23

71

65

14

23

54

23

62

21

70

27

13

21

51

21

38

19

21

69

26

12

19

48

19

32

16

18

68

21

11

16

21

38

16

31

13

16

79 65

19

10

13

18

36

13

75

8

91

8

91

8

91

8 8

91

8

91

8

91

8

91

8

BI BI BI BI

GND

VDD

SDATA

SCLK

THM*

ALERT*/

D+ D-

THM2*

BI

OUT

IN

ALERT*

SMCLK

SMDATA

GND

DN1

DP1

DN2

DP2

THERM*

VDD

ALERT*

SMCLK

SMDATA

GND

DN1

DP1

DN2

DP2

THERM*

VDD

BI

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

GPU/Heat Pipe & Bottom Case Skin Thermal Sensor

(TC0P)

Placement note:

Place on left side of fan cutout

(Reserved for CPU heatpipe sensor)

GPU Die Thermal Sensor

(Th2H)

Placement note:

(Th0H)

Placement note:

Place U5550 near GPU

(Th1H)

(TG0P)

NB Thermal Diodes Not Used

(TG0T)

518S0487

connectors as possible

Keep 2 caps as close to

Placement note:

Place near GPU

(TG0H)

Keep 2 caps as close to IC pins as possible

Placement note:

518S0487

(TC0D)

CPU T-Diode Thermal Sensor

CERM

10V

20%

0.1uF

402

C5500

1

2

1/16W

5%

MF-LF

47

402

R5500

1 2

5%

18PF

50V CERM 402

SIGNAL_MODEL=EMPTY

NO STUFF

C5510

1

2

50V 402

CERM

18PF

5%

NO STUFF

SIGNAL_MODEL=EMPTY

C5520

1

2

CRITICAL

M-RT-SM

BM02B-ACHKS-GAN-TF-LF-SN-M

J5510

3

4

1 2

BM02B-ACHKS-GAN-TF-LF-SN-M

CRITICAL

M-RT-SM

J5520

3

4

1 2

MF-LF

1/16W 402

5%

10K

GPU_TMP401

R5552

1

2

MF-LF

402

5%

10K

1/16W

GPU_TMP401

R5551

1

2

0.1UF

X5R 402

10% 16V

GPU_TMP401

C5550

1

2

50V CERM 402

10%

0.001UF

GPU_TMP401

SIGNAL_MODEL=EMPTY

C5560

1

2

402

MF-LF

1/16W

1%

499

GPU_TMP401

R5560

1 2

499

1% 1/16W MF-LF

402

GPU_TMP401

R5561

1 2

CRITICAL

TMP401

MSOP

GPU_TMP401

U5550

6

3

2

5

8 7

4

1

CRITICAL

BM02B-ACHKS-GAN-TF-LF-SN-M

M-RT-SM

J5590

3

4

1 2

34 45 48 81 88

45 48 74 88

34 45 48 81 88

72 73 91

402

CERM

50V

10%

0.0022uF

SIGNAL_MODEL=EMPTY

C5511

1

2

10% 50V

402

CERM

0.0022uF

SIGNAL_MODEL=EMPTY

C5521

1

2

EMC1403-1-AIZL

CRITICAL

TSSOP

U5570

8

3

5

2

4

6

10

9

7

1

CRITICAL

EMC1403-1-AIZL

TSSOP

U5500

8

3

5

2

4

6

10

9

7

1

5%

10K

1/16W MF-LF

402

R5501

1

2

MF-LF

10K

5% 1/16W

402

R5502

1

2

MF-LF

1/16W

5%

10K

402

R5572

1

2

1/16W

10K

MF-LF

5%

402

R5571

1

2

45 48 53 88

402

CERM

10V

20%

0.1uF

C5570

1

2

402

47

1/16W

5%

MF-LF

R5570

1 2

10% 50V

CERM

402

SIGNAL_MODEL=EMPTY

0.0022uF

C5590

1

2

470PF

10% 50V

402

SIGNAL_MODEL=EMPTY

CERM

C5580

1

2

10 91

SYNC_DATE=08/28/2007

51 92

A.0.0

051-7431

SYNC_MASTER=M87_MLB

Thermal Sensors

RSFSTHMSNS_D_N

PP3V3_S0

GPU_TDIODE_P

GPUTHMSNS_D_N

GPU_TDIODE_N

GPUTHMSNS_D_P

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

GND GND

GND

CPU_THERMD_P

CPUTHMSNS_D2_N

CPU_THERMD_N

GPUTHMSNS_THM_L

SMBUS_SMC_A_S3_SCL

SMBUS_SMC_A_S3_SDA

GPUTHMSNS_ALERT_L

HSTHMSNS_D_N

HSTHMSNS_D_P

PP3V3_S3

PP3V3_S0_CPUTHMSNS_R

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

SMBUS_SMC_B_S0_SCL

SMBUS_SMC_B_S0_SDA

CPUTHMSNS_THM_L

CPUTHMSNS_D2_P

RSFSTHMSNS_D_P

CPUTHMSNS_ALERT_L

PP3V3_S3_REMTHMSNS_R

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

REMTHMSNS_THM_L REMTHMSNS_ALERT_L

91

82

65

59

58

53

52

51

50

48

47

46

42

32

31

30

29

28

27

81

26

65

25

58

24

55

23

54

21

50

19

48

16

38

91

13

91

36

91

7

8

91

7

8

7

G

S D

G

S D

IN

OUT OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0369

Right Fan

Left Fan

518S0369

MF-LF

5%

402

47K

1/16W

R5650

1

2

47K

402

MF-LF

5%

1/16W

R5655

1 2

1/16W

5%

47K

MF-LF

402

R5660

1

2

5% 1/16W MF-LF

47K

402

R5665

1 2

100K

1/16W

5%

MF-LF

402

R5651

1

2

SOT-363

2N7002DW-X-F

Q5660

3

5

4

1/16W

402

MF-LF

5%

100K

R5661

1

2

2N7002DW-X-F

SOT-363

Q5660

6

2

1

M-RT-SM

SM04B-ACH

CRITICAL

J5650

5

6

1 2 3 4

M-RT-SM

SM04B-ACH

CRITICAL

J5660

5

6

1 2 3 4

45

45 45

45

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

52 92

051-7431

A.0.0

Fan Connectors

SMC_FAN_1_CTL

SMC_FAN_1_TACH

SMC_FAN_0_CTL

SMC_FAN_0_TACH

PP3V3_S0

FAN_RT_PWM

PP5V_S0

FAN_RT_TACH

PP3V3_S0

FAN_LT_PWM

FAN_LT_TACH

PP5V_S0

91

82

65

59 59 58 58 53 53 52 52 51 51

50 50 48 48 47 47 46 46 42 42 32 32 31

82

31

82

30

81

30

81

29

80

29

80

28

65

28

65

27

59

27

59

26

58

26

58

25

54

25

54

24

52

24

52

23

49

23

49

21

47

21

47

19

42

19

42

16

27

16

27

13

8

13

8

7

8

7

GND

OUT

VIN+ VIN-

V+

GND

OUT

VIN+ VIN-

V+

SDA

SCL

ALERT

ADD0

V+

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

TABLE_5_ITEM

PART NUMBER

ALTERNATE FOR

PART NUMBER

BOM OPTION

REF DES

COMMENTS:

TABLE_ALT_HEAD

TABLE_ALT_ITEM

Battery Charger Thermal Sensor

P/N OPPOSITE VIN+/- TO MEASURE DISCHARGE CURRENT

Placement Note:

Place sensor on bottom side

near L8300 and Q8301 and Q8302

DCIn Current Sense

Place near R8307

Placement Note:

Place near R8308

Battery Current Sense

TEMP SENSOR HAS ADDRESS 0X92

CRITICAL

INA193

SOT23-5

U5705

2

15

3 4

10%

402

CERM

6.3V

1uF

C5715

1

2

1uF

402

CERM

10%

6.3V

C5705

1

2

402

20%

0.1uF

CERM

10V

C5750

1

2

INA193

SOT23-5

CRITICAL

U5715

2

15

3 4

CRITICAL

TMP102

SOT563

OMIT

U5750

4 3

2

1

6

5

353S1807 353S2039

U5750

Alternate old version

353S2039

1

revE of TMP102

U5750

CRITICAL

A.0.0

051-7431

SYNC_DATE=11/06/2007

SYNC_MASTER=M87_LIO

9253

Current & Thermal Sensors

SMBUS_SMC_B_S0_SDA

SMBUS_SMC_B_S0_SCL

PP3V3_S0

LIO_BATT_ISENSE

PP3V3_S0

CHGR_CSI_P

LIO_DCIN_ISENSE

CHGR_CSO_R_P

CHGR_CSO_R_N

PP3V3_S0

CHGR_CSI_RN

91 91

91

82 82

82

65 65

65

59 59

59

58 58

58

53 53

53

52 52

52

51 51

51

50 50

50

48 48

48

47 47

47

46 46

46

42 42

42

32 32

32

31 31

31

30 30

30

29 29

29

28 28

28

27 27

27

26 26

26

25 25

25

24 24

24

23 23

23

21 21

21

88

19 19

19

51

16 16

16

48

13 13

13

45

8

49

8

66

49

66

8

66

V+

V-

G

S

D

IN

OUT

IN

OUT

IN

THRML

CAP

SW

LED

VIN

CTRL

PAD

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Left ALS circuit has 1K series-R

Left ALS Filter

WF: This circuit does not use return, can tie cathode to GND on topcase flex

Right ALS Circuit

RTALS_OP_IN and RTALS_OP_COMP need to be matched

Keyboard LED Driver

MAX4236EUTT

SOT23-6-LF

CRITICAL

U5805

3

4

1

5

6

2

CERM

402

20% 10V

0.1UF

C5805

1

2

162K

1% 1/16W

402

MF-LF

R5806

1

2

0.22UF

X5R 402

20%

6.3V

C5806

1

2

25.5K

1/16W

1%

402

MF-LF

R5807

1

2

1.37K

MF-LF

402

1/16W

1%

R5808

1

2

MF-LF

402

1%

1/16W

1K

R5801

1 2

TH

CRITICAL

BS520EOF

PD5800

1

2

5.1M

402

5% 1/16W MF-LF

R5800

1

2

402

CERM

20% 16V

0.01UF

C5800

1

2

2N7002

SOT23-LF

Q5808

3

1

2

7

34 45

45

4.53K

MF-LF

402

1%

1/16W

R5810

1 2

0.22UF

X5R

20%

6.3V 402

C5810

1

2

45

6.3V

20%

402

X5R

0.22UF

C5830

1

2

1/16W

1%

402

MF-LF

3.48K

R5830

1 2

7

34

CRITICAL

10UH-0.58A

DE2812C-SM

L5850

1 2

10V

1UF

20%

603

CERM

C5850

1

2

MF-LF

5%

1/16W

10K

402

R5852

1

2

45

402

1/16W

1% MF-LF

10

R5855

1

2

81

X5R

1UF

25V

10% 603

C5855

1

2

CRITICAL

LT3491

DFN

U5850

4

6

2

5

3

7

1

100KOHM-5%

0603-LF

R5805

1

2

ALS Support

54 92

051-7431

A.0.0

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

PP5V_S0

MIN_NECK_WIDTH=0.25 MM

KBDLED_CAP

MIN_LINE_WIDTH=0.25 MM

GND

KBDLED_SW

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.3 MM MIN_NECK_WIDTH=0.25 MM

KBDLED_ANODE

MIN_NECK_WIDTH=0.25 MM

MIN_LINE_WIDTH=0.25 MM

LTALS_OUT

ALS_GAIN

PP3V3_S3

ALS_RT_OUT

ALS_RIGHT

GND_SMC_AVSS

RTALS_OP_IN

RTALS_PHOTODIODE

RTALS_GAIN_L

GND_SMC_AVSS

ALS_LEFT

SMC_SYS_KBDLED

RTALS_OP_COMP

82 81 80

65

81

59

65

58

52

55

49

51

47

50

42

48

54

27

38

49

8

36

46

7

8

45

CS*

SCL/SCLK

ADDR/SDI

MOT_ENABLE

ENABLE

VDD

X Y Z

FF/MOT

SDA/SDO

GND

IN

OUT OUT OUT

OUT

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

APN:338S0354

Desired orientation when

+Z (up)

ADDR low => 0x30, 0x31 ADDR high => 0x32, 0x33

I2C addresses:

Alias SCL/SDA to GND if using analog outputs only

+X

1

+Z (dn)

Package Top

1

+X

+Y +Y

Desired orientation when placed on board top-side:

Top-through View

placed on board bottom-side:

10V

20% 402

CERM

0.1uF

C5900

1

2

0.033UF

10% 16V X5R 402

C5902

1

2

0.033UF

10% 16V X5R 402

C5903

1

2

KXPS5-2050

LGA

CRITICAL

U5900

3

2

6

11

10

12

5

4

11314

7 8 9

1/16W

5%

402

MF-LF

10K

R5900

1

2

45

SMS_MOT_EN

0

MF-LF 402

5% 1/16W

R5901

1

2

SMS_MOT_DIS

402

MF-LF

1/16W

5%

0

R5902

1

2

100K

402

MF-LF

1/16W

5%

R5903

1

2

9

45

45 48 88

X5R

10% 16V

0.033UF

402

C5901

1

2

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

Sudden Motion Sensor (SMS)

051-7431

A.0.0

9255

SMS_ONOFF_L

SMS_Z_AXIS

SMS_MOT_EN

SMC_SMS_INT

PP3V3_S3

SMBUS_SMC_MGMT_SCL

SMS_Y_AXIS

SMBUS_SMC_MGMT_SDA

SMS_X_AXIS

81 65 58 54 51 50 48 38 36

8

SO

VDD

CE*

SCK

VSS

HOLD*

SI

WP*

OUT

IN

IN IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

402

0.1UF

10V

20% CERM

C6100

1

2

MF-LF

3.3K

5% 1/16W

402

R6101

1

2

3.3K

MF-LF

5%

1/16W

402

R6100

1

2

402

1/16W

5%

MF-LF

15

PLACEMENT_NOTE=Place R6114 within 12.7mm of U6100

R6114

1 2

CRITICAL

16MBIT

SOI

SST25VF016B

OMIT

U6100

1

7

6

5

2

8

4

3

24 86

PLACEMENT_NOTE=Place R6190 within 12.7mm of U2300

402

15

1/16W

5%

MF-LF

R6190

1 2

PLACEMENT_NOTE=Place R6191 within 12.7mm of U2300

15

1/16W

5%

MF-LF

402

R6191

1 2

24 86

402

15

1/16W

5%

MF-LF

PLACEMENT_NOTE=Place R6193 within 12.7mm of U2300

R6193

1 2

24 86

SPI BootROM

56 92

A.0.0

051-7431

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

PP3V3_S5

SPI_SI_R

SPI_SO

SPI_HOLD_L

SPI_A_SI_R

SPI_WP_L

SPI_A_SO_R

SPI_SCLK

SPI_CE_L<0>

SPI_SCLK_R

SPI_CE_R_L<0>

91 76 65

60 58 48 46 28 27 26 25 24

8

86

BI

OUT

V-

V+

S3 S2

D1

D2

D3

D4

GATE

S1

G

S

D

BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Battery Connector

<R2b>

Assuming 1% variance for R6910-R6915 and 3.42V:

REQ of R6910 (on LIO), R6912, & R6913 is 36.9K.

NOTE: R6910 is on LIO.

System must provide 10K-70K impedance to A52 adapter for system load detection.

Inrush Limiter

ACIN Detection

518S0456

Worst case Vth: min:12.47V, max: 13.54V

Vref = 3.42V * (R2a / (R1a + R2a)) Vth = (Vref / (R2b / (R1b + R2b))

<R1a>

Vth = 13.0V

Vref = 1.23V

<R2a>

518S0457

<R1b>

DC-In Connector

(HOST_DETECT_L)

7

45 48 88

87438-0832-BLK

M-RT-SM

CRITICAL

J6990

1 2 3 4 5 6 7 8

1SS355

SOD-323

D6901

1 2

7

45

46

805

MF-LF

1/8W

47

5%

R6907

1 2

27V-40PF

NO STUFF

402

DZ6962

1

2

27V-40PF

NO STUFF

402

DZ6963

1

2

27V-40PF

402

NO STUFF

DZ6961

1

2

27V-40PF

402

NO STUFF

DZ6960

1

2

CRITICAL

LMC7211

SM-LF1

U6900

4

3

1

5

2

SI4413ADY-E3

SO-8

CRITICAL

Q6950

5

6

7

8

4

1

2

3

0.22uF

25V

20%

603

X5R

C6950

1

2

1/16W

5%

402

1M

MF-LF

R6916

12

1/16W

1%

402

MF-LF

102K

R6914

1

2

1/16W

1%

402

MF-LF

57.6K

R6915

1

2

102K

402

MF-LF

1/16W

1%

R6912

1

2

10.7K

1% 1/16W MF-LF

402

R6913

1

2

10V

20%

0.1uF

402

CERM

C6910

1

2

1%

402

MF-LF

1/16W

470K

R6921

1

2

402

1/16W

5%

MF-LF

330K

R6950

1

2

SOT23-LF

2N7002

Q6910

3

1

2

SC70

MC74VHC1G08

U6950

3

2

1

4

5

CRITICAL

87438-1043-BLK

M-RT-SM

J6950

1

10

2 3 4 5 6 7 8 9

7

45 48 88

051-7431

SYNC_MASTER=(MASTER)

DC-In & Battery Connectors

57 92

A.0.0

SYNC_DATE=(MASTER)

BATT_NEG SMC_BS_ALRT_L

SMBUS_SMC_BSA_SCL

BATT_POS

SMBUS_SMC_BSA_SDA

BATT_POS

SMC_BC_ACOK

PP3V42_G3H

ACIN_1V20_REF

ACIN_DIV

PP18V5_DCIN

MIN_LINE_WIDTH=0.60mm

PP18V5_DCIN

MIN_NECK_WIDTH=0.20mm

VOLTAGE=18.5V

GND

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

BATT_NEG

MAKE_BASE=TRUE

PP18V5_G3H_CHGR

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

MAKE_BASE=TRUE

VOLTAGE=18.5V

PP18V5_G3H_CHGR

PPDCIN_G3H

MIN_LINE_WIDTH=0.50mm MIN_NECK_WIDTH=0.20mm

VOLTAGE=18.5V

PPDCIN_G3H_R

SMC_ADAPTER_EN

ACOK_AND_PS_ON

ACIN_ENABLE_DIV2_L

MIN_LINE_WIDTH=0.2mm MIN_NECK_WIDTH=0.2mm

ACIN_ENABLE_DIV_L

PP18V5_G3H_CHGR

MIN_NECK_WIDTH=0.25mm

BATT_POS

MAKE_BASE=TRUE MIN_LINE_WIDTH=0.6mm

PPBUS_G3H

82 79 75

81

66

63

65

62

48

61

47

60

46

59

45

58

66

43

46

49

66

46

28

66

45

66

40

57

45

8

57

66

65

40

66

57

8

57

7

34

7

57

8

36

57

7

D

SG

D

SG

G

D

S

G

D

S

G

D

S

G

D

S

G

S

D

S

D

G

D

S

G

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.3V S0 FET

1.25V S0 FET

3.3V GPU FET

3.3V S3 FET

5V S3 FET

5V S0 FET

SOT563

SSM6N15FE

Q7096

3

5

4

SOT563

SSM6N15FE

Q7096

6

2

1

SOT-363

2N7002DW-X-F

Q7002

6

2

1

SOT-363

2N7002DW-X-F

Q7012

6

2

1

2N7002DW-X-F

SOT-363

Q7002

3

5

4

2N7002DW-X-F

SOT-363

Q7012

3

5

4

SOT23-LF

2N7002

Q7072

3

1

2

FDC697P

CRITICAL

SOT-6

Q7020

7

4

1

2

3

5

6

SM-LF

CRITICAL

FDC638P

Q7000

1

2

5

6

3

4

SM-LF

FDC638P

CRITICAL

Q7070

1

2

5

6

3

4

SM-LF

FDC638P

CRITICAL

Q7030

1

2

5

6

3

4

SM-LF

FDC638P

CRITICAL

Q7010

1

2

5

6

3

4

CRITICAL

MICROFET3X3

FDM6296

Q7095

5

4

1 2 3

0.01UF

10%

402

CERM

16V

C7070

1 2

402

X5R

10V

10%

1UF

C7071

1

2

402

MF-LF

1/16W

5%

1K

R7070

1 2

10K

402

MF-LF

1/16W

5%

R7072

1

2

65

499

402

1%

MF-LF

1/16W

R7098

1 2

0.15UF

402

10% CERM-X5R

6.3V

C7096

1

2

220K

5%

MF-LF

1/16W

402

R7097

1 2

1%

MF-LF

402

1/16W

15.0K

R7096

1 2

16V

10% X5R

0.1UF

402

C7095

1 2

69.8K

1% 1/16W MF-LF

402

R7095

1

2

7

25 35 36 40 45 49 58 62 65

402

CERM

0.068UF

10V

10%

C7001

1

2

0.01UF

10%

402

CERM

16V

C7000

1 2

1/16W

402

MF-LF

5%

10K

R7002

1

2

1/16W MF-LF

402

5%

47K

R7000

1 2

7

25 34 43 45

58 65

0.01UF

10%

402

CERM

16V

C7010

1 2

402

10%

0.033UF

X5R

16V

C7011

1

2

1/16W

100K

5%

MF-LF

402

R7010

1 2

MF-LF

402

1/16W

5%

10K

R7012

1

2

7

25 34 43 45

58 65

0.01UF

16V 402

10%

CERM

C7020

1 2

0.068UF

402

10V

10%

CERM

C7021

1

2

MF-LF

402

1/16W

5%

47K

R7020

1 2

10K

5% 1/16W MF-LF

402

R7022

1

2

7

25 35 36 40

45 49

58 62

65

16V

0.01UF

CERM

402

10%

C7030

1 2

402

X5R

10%

0.033UF

16V

C7031

1

2

402

MF-LF

1/16W

5%

100K

R7030

1 2

10K

5% 1/16W MF-LF

402

R7032

1

2

7

25 35 36 40

45 49

58 62

65

92

051-7431

58

A.0.0

Power FETs

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

PP5V_S5

PP5V_S0

PP3V3_S5

P5VS0_SS

PP5V_S5

PP3V3_S0

PM_S4_STATE_L

PP1V25_ENET

PP5V_S5

P5VS3_EN_L

P3V3S3_SS

P3V3GPU_SS

PM_SLP_S3_L

P5VS3_SS

P3V3GPU_EN_L

PM_SLP_S3_L

P3V3S0_EN_L

P5VS0_EN_L

P3V3S3_EN_L

PM_S4_STATE_L

P1V25S0_EN_L

P1V25S0_EN_L_RC

P3V3S0_SS

P1V25S0_SS

PP1V25_S0

P1V25S0_SS_RC

PP3V3_S5

PP3V3_S0GPU

PP5V_S3

PM_P3V3GPU_EN

PM_SLP_S3_L

PP3V3_S5

PP3V3_S3

PPBUS_G3H

91 82 65 59 53 52

51 50 48 47 46 42 32

91

31

91

82

76

30

76

79

81

65

79

29

79

65

75

80

60

75

28

75

60

66

65

58

65

27

65

58

81

63

59

56

63

26

63

56

80

56

65

62

54

48

62

25

62

48

76

48

55

61

52

46

61

24

61

46

75

46

54

60

49

28

60

23

60

28

74

28

51

59

58

47

27

58

21

58

27

73

81

27

50

57

43

42

26

43

19

43

26

72

46

26

48

49

42

27

25

42

16

61

42

25

65

44

25

38

40

27

8

24

27

13

35

27

50

24

48

8

24

36

8

7

8

8 7

8

7

IN

OUT IN OUT

IN

OUT OUT

IN

OUT

VID0

DPRSTP*

NC

VW

COMP

FB

FB2

RBIAS

VR_TT* NTC

VR_ON PGOOD

PSI*

RTN

VSEN

DFB

DROOP

VO

OCSET

VSUM

ISEN2

VID1

VID3 VID2

VID4

VID5

VID6

PGND2

VIN VDD

PVCC

LGATE2

PHASE2

UGATE2

ISEN1

PGND1

LGATE1

UGATE1

PHASE1

BOOT1 BOOT2

3V3

VDIFF

SOFT

DPRSLPVR

TPAD

GND

CLK_EN*

IMON

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(IMVP6_PHASE1)

(IMVP6_ISEN1)

These caps are for Q7100

(GND_IMVP6_SGND)

(GND)

(ISL9504A)

(PGD_IN)

LAYOUT NOTE:

DPRSLPVR

DPRSTP*

(IMVP6_VSUM)

44A MAX CURRENT

CCM

DCM DCM

CCM

1-Phase 1-Phase

2-Phase

1-Phase

PSI*

1 0

0

1

0 0

10

1

0

1

(IMVP6_PHASE2)

(IMVP6_VO)

(GND)

(IMVP6_COMP)

(IMVP6_VW)

These caps are for Q7102

(IMVP6_FB)

(IMVP6_ISEN2)

Place R7131 Between L7100,L7101 and CPU

(IMVP6_VO)

Place R7126 in hot

Mode

Operation

(IMVP6_NTC)

spot of reg circuit.

402

1%

MF-LF

1/16W

10K

R7100

1 2

402

CERM

10V

0.22UF

10%

C7103

1 2

SM

XW7104

12

X5R 603

25V

0.22UF

20%

C7115

1

2

7

10 16 23 83

7

16 25 83

10 28

28

59

7 9

16 28

SM

XW7102

12

1%

402

MF-LF

1/16W

10K

R7105

1 2

CERM

10% 10V

0.22UF

402

C7104

1 2

0.22UF

25V X5R 603

20%

C7127

1

2

1/16W

10

402

1%

MF-LF

R7120

1 2

1%

MF-LF

402

10

1/16W

R7112

1 2

X5R 402

10V

10%

1UF

C7126

1

2

1%

10

402

MF-LF

1/16W

R7121

1 2

10% 402

16V

0.1uF

X5R

C7130

1

2

MF-LF

1%

402

1/16W

499

R7119

1 2

0.001UF

10% 50V

CERM

ISL9504B

402

C7107

1

2

MF-LF

1/16W

6.81K

1%

402

ISL9504B

R7110

1

2

4.7uF

603

20%

6.3V CERM

C7135

1

2

10% 16V

402

CERM

0.01uF

C7110

1

2

1K

MF-LF

1/16W

1%

ISL9504B

402

R7113

1

2

MF-LF

ISL9504B

1/16W 402

1%

1K

R7109

1

2

10%

X7R-CERM

220PF

50V 402

ISL9504B

C7113

1

2

97.6K

1%

MF-LF

1/16W

402

ISL9504B

R7114

1

2

MF-LF

1

5% 1/16W

402

R7104

1

2

402

1

5% 1/16W MF-LF

R7107

1

2

0.001uF

NO STUFF

10% 50V

CERM

402

C7116

1

2

402

1/16W MF-LF

1%

3.09K

R7117

1 2

5%

402

50V CERM

180pF

C7129

1

2

1/16W MF-LF

1%

402

1K

R7118

1

2

402

MF-LF

1%

1/16W

2.61K

R7130

1

2

402

1/16W MF-LF

1%

11K

R7115

1

2

6.3V 402

10%

0.22UF

CERM-X5R

C7128

1

2

0.022UF

CERM-X5R

16V

10% 402

C7134

1

2

5%

MF-LF

1/16W

0

402

R7122

1 2

16V

10%

402

SIGNAL_MODEL=EMPTY

CERM

0.01UF

C7131

1

2

NO STUFF

10%

0.01uF

16V 402

CERM

C7132

1

2

0

MF-LF

402

1/16W

5%

R7123

1 2

10%

0.01uF

16V 402

CERM

C7133

1

2

X5R 402

20%

6.3V

0.22UF

C7121

1

2

SM

XW7100

1 2

1/10W

1%

603

MF-LF

3.65K

R7101

1

2

1% MF-LF

603

1/10W

3.65K

R7106

1

2

IHLP4040DZ-SM

CRITICAL

0.36UH-30A-1.2M-OHM

L7100

1 2

CRITICAL

IHLP4040DZ-SM

0.36UH-30A-1.2M-OHM

L7101

1 2

0.1UF

X5R 402

10% 16V

C7196

1

2

7

12 83

7

12 83

7

12 83

7

12 83

7

12 83

7

12 83

7

12 83

ISL9504B

402

0.001UF

10% 50V CERM

C7106

1

2

10% 50V

402

ISL9504B

CERM

470PF

C7114

1

2

255

1/16W

1%

MF-LF

402

ISL9504B

R7111

1

2

X7R

0.015UF

10% 16V

402

C7105

1

2

1/16W 402

MF-LF

1%

13.3K

R7116

1

2

1UF

603

X5R

10% 25V

C7109

1

2

0603-LF

10KOHM-5%

CRITICAL

R7131

1

2

1% MF-LF

402

147K

1/16W

R7108

1

2

4.02K

1% 1/16W MF-LF

402

R7127

1

2

2.0K

5%

402

MF-LF

1/16W

R7197

1

2

SM

XW7103

1 2

SM

XW7101

1 2

50 59

11 83

470K

402

CRITICAL

R7126

1

2

402

5%

MF-LF

0

1/16W

R7198

1 2

10 46 83

402

68

MF-LF

NO STUFF

1/16W

5%

R7199

1

2

QFN

OMIT

ISL9504BCRZ

U7100

48

36 26

47

10

17

45

46

16

11

12

21

3

24

23

32

30

25

6

8

33

29

1

34

28

2

31

4

15

7

49

35

27

22

13

37

38

39

40

41

42

43

20

18

44

5

14

19

9

RJK0305DPB

CRITICAL

LFPAK

Q7100

5

4

1 2 3

CRITICAL

RJK0301DPB

LFPAK

Q7103

5

4

1 2 3

CRITICAL

RJK0305DPB

LFPAK

Q7102

5

4

1 2 3

LFPAK

CRITICAL

RJK0301DPB

Q7105

5

4

1 2 3

RJK0301DPB

CRITICAL

LFPAK

Q7104

5

4

1 2 3

LFPAK

RJK0301DPB

CRITICAL

Q7101

5

4

1 2 3

22UF

25V

CRITICAL

20%

POLY

CASE-D2-LF

C7117

1

2

22UF

25V

CRITICAL

POLY

20%

CASE-D2-LF

C7153

1

2

CASE-D2-LF

25V

POLY

CRITICAL

20%

22UF

C7155

1

2

25V

10% X5R

603

1UF

C7154

1

2

49 65

I848I849

402

MF-LF

0

1/16W

5%

R7160

1 2

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

IMVP6 CPU VCore Regulator

9259

A.0.0

051-7431

IMVP6_VO

IMVP6_VSEN_N

IMVP6_VSUM

PPBUS_G3H

IMVP6_FB IMVP6_COMP

IMVP6_IMON

IMVP6_VID<4>

IMVP6_VID<5>

CPU_DPRSTP_L

CPU_PSI_L

VOLTAGE=3.3V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

PP3V3_S0_IMVP6_3V3

IMVP6_VW

IMVP6_RBIAS

CPU_PROCHOT_L

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.2 MM

PPVIN_S5_IMVP6_VIN

PP5V_S0

IMVP6_FB2

PPBUS_G3H

IMVP6_VDIFF

IMVP6_SOFT

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_COMP

MIN_NECK_WIDTH=0.20 MM MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VW

PP3V3_S0

IMVP6_VID<2> IMVP6_VID<1>

PM_DPRSLPVR

IMVP6_NTC_R

MIN_NECK_WIDTH=0.2 MM

IMVP6_PHASE2

MIN_LINE_WIDTH=1.5 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_BOOT2

MIN_LINE_WIDTH=0.25 MM

IMVP6_UGATE2

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

CPU_VCCSENSE_P

CPU_VCCSENSE_N

IMVP6_VO1

IMVP6_VSUM2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_VID<6>

MIN_LINE_WIDTH=0.25 MM

IMVP6_VO1

MIN_NECK_WIDTH=0.25 MM

IMVP6_LGATE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_BOOT1

MIN_LINE_WIDTH=0.25 MM

IMVP6_PHASE1

MIN_LINE_WIDTH=1.5 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_FB2

IMVP6_VDIFF

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_RBIAS

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_DFB

MIN_NECK_WIDTH=0.20 MMMIN_LINE_WIDTH=0.25 MM

IMVP6_VO

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_FB

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_DROOP

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_OCSET

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.20 MM

IMVP6_UGATE1

IMVP6_BOOT2

IMVP6_VSUM1

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_UGATE1

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

MIN_LINE_WIDTH=0.25 MM

IMVP6_ISEN1

MIN_NECK_WIDTH=0.2 MM

IMVP6_VSEN_P

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

VR_PWRGD_CLKEN_L

IMVP6_VR_TT_L

IMVP_VR_ON_R

IMVP6_COMP_RC

IMVP6_VDIFF_RC

IMVP_VR_ON

IMVP6_VO2

IMVP6_LGATE1

IMVP6_UGATE2

MIN_NECK_WIDTH=0.2 MM VOLTAGE=5V

MIN_LINE_WIDTH=0.25 MM

PP5V_S0_IMVP6_VDD

IMVP6_VSEN_N

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_VO2

MIN_LINE_WIDTH=0.25 MM MIN_NECK_WIDTH=0.25 MM

IMVP6_ISEN2

MIN_LINE_WIDTH=0.25 MM

MIN_NECK_WIDTH=0.2 MM

IMVP6_LGATE2

MIN_LINE_WIDTH=0.5 MM MIN_NECK_WIDTH=0.2 MM

IMVP6_BOOT1

IMVP6_ISEN1

IMVP6_VSUM1

IMVP6_VID<3>

IMVP_DPRSLPVR

IMVP6_SOFT

IMVP6_OCSET

IMVP6_ISEN2

IMVP6_LGATE2

IMVP6_NTC

VR_PWRGOOD_DELAY

MIN_LINE_WIDTH=0.50 MM VOLTAGE=0V

GND_IMVP6_SGND

MIN_NECK_WIDTH=0.20 MM

IMVP6_VID<0>

IMVP6_VO_R

IMVP6_PHASE2

PPVCORE_S0_CPU

IMVP6_VSUM2

IMVP6_PHASE1

IMVP6_VSEN_P

IMVP6_DFB

IMVP6_DROOP

91 82 65

58 53 52 51 50 48

47 46 42

82

32

79

31

75

82

75

30

66

81

66

29

63

80

63

28

62

65

62

27

61

58

61

26

60

54

60

25

59

52

59

24

58

49

58

23

57

47

57

21

49

42

49

19

12

40

27

40

16

11

83

8

13

59

83

45

83

8

83

59

7

59

7

59

7

59

8

59

50

59

50

59

7

59

7

59

7

59

GND

THRML_PAD

SKIPSEL TONSEL

V5FILT

VIN

VREG5

VREG3

VREF2

EN5 EN3

VBST2

DRVH2

LL2

CS2

DRVL2

VO2

PGND2

COMP2

VFB2

PGOOD2

EN2

DRVH1

LL1

DRVL1

CS1

VO1

PGND1

VFB1 COMP1

PGOOD1

EN1

VBST1

SYM (3 OF 3)

IN

OUT OUT

IN

S

D

G

S

D

G

Q1

Q2

SW

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(L7320 limit)

8A max output

Vout = 5.0V

NOTE: EN5 can float or tie to VIN for automatic 5V LDO enable EN3 can float or tie to VREG5 for automatic 3.3V LDO enable When both are low TPS51120 VIN current drops from 100-150uA to 10-20uA.

5.5A max output (L7360 limit)

Vout = 3.3V

3.3V Fixed

5V Fixed

(Available for system use)

TPS51120 LDO/Buffer outputs

50uA max load when EN5 & EN3 high

100mA max load when EN5 high

.

10% X5R

603

25V

1UF

C7300

1

2

4.7UH

IHLP

CRITICAL

L7360

1 2

1UF

25V

10% X5R

603

C7341

1

2

0.1UF

10%

603-1

X7R

50V

C7364

1

2

20%

6.3V

10UF

603

X5R

C7390

1

2

0.1UF

X7R 603-1

10% 50V

C7324

1

2

D3L-HF

CRITICAL

330UF

6.3V POLY

20%

C7352

1

2

805-2

10UF

10V

CERM

20%

C7350

1

2

10UF

805-2

10V

20% CERM

C7351

1

2

CASE-B2-HF

20%

150UF

6.3V

CRITICAL

POLY

C7392

1

2

CRITICAL

CASE-D2-LF

20%

22UF

POLY

25V

C7340

1

2

10% X5R

603

1UF

25V

C7381

1

2

CRITICAL

20%

POLY

22UF

25V

CASE-D2-LF

C7380

1

2

2.2UH-14A

CRITICAL

IHLP2525CZ-SM

L7320

1 2

CRITICAL

LLP

TPS51120

U7300

2 7

23 18

27

14

25 16

29 12

10

9

5

26 15

24 17

30 11

32

33

31

20

28 13

3 6

22

1 8

4

19

21

4.22K

1/16W 402

MF-LF

1%

R7325

1

2

MF-LF

402

3.57K

1/16W

1%

R7365

1

2

6.3V

20%

10UF

X5R 603

C7303

1

2

10UF

20%

6.3V X5R 603

C7305

1

2

402

MF-LF

1/16W

4.7

5%

R7306

1

2

1UF

X5R

10V

10%

402

C7306

1

2

65

45 60 65

65

45 46 60

45 60 65

402

CERM

50V

20%

0.001UF

C7302

1

2

PWRPK-1212-8

CRITICAL

SI7110DN

Q7320

5

4

123

SI7108DNS

CRITICAL

PWRPK-1212-8

Q7325

5

4

123

SM

PLACEMENT_NOTE=Place XW7360 next to C7390.

XW7360

1

2

PLACEMENT_NOTE=Place XW7320 next to C7350.

SM

XW7320

1

2

SM

XW7325

1 2

SM

XW7365

1 2

25V

NO STUFF

CERM

5%

220PF

402

C7307

1

2

NO STUFF

402

25V

220PF

5% CERM

C7308

1

2

SM

XW7300

1 2

CRITICAL

FDMS9600S

MLP

Q7360

2349

1

8

56

7

10

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

5V / 3.3V Power Supply

051-7431

A.0.0

9260

PPBUS_G3H

P5VS5_CS

RSMRST_PWRGD

PM_G2_P5VS5_EN

P5VS5_DRVL

MIN_LINE_WIDTH=0.6 mm GATE_NODE=TRUE MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_P5VS5_PGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P5VS5_LL

MIN_NECK_WIDTH=0.2 mm

P5VS5_VO

P5VS5_DRVH

GATE_NODE=TRUEMIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

PP2V0_S5_P5VP3V3_BUF

VOLTAGE=2V

MIN_NECK_WIDTH=0.20 mm

MIN_LINE_WIDTH=0.20 mm

PPBUS_G3H

MIN_NECK_WIDTH=0.20 mm

PP5V_S5_P5VP3V3_LDO

VOLTAGE=5V

MIN_LINE_WIDTH=0.25 mm

P3V3S5_CS

PPBUS_G3H

P3V3S5_DRVH

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

P3V3S5_DRVL

MIN_LINE_WIDTH=0.6 mm

P3V3S5_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

PP5V_S5_P5VP3V3_V5FILT

P5VP3V3_VREG3

MIN_NECK_WIDTH=0.2 mm

P5VS5_VBST

MIN_LINE_WIDTH=0.6 mm

PM_G2_EN

PM_G2_P3V3S5_EN

VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

GND_P5VP3V3_SGND

MIN_NECK_WIDTH=0.2 mm

GND_P3V3S5_PGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP3V3_S5

P3V3S5_LL

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

PP5V_S5

P3V3S5_VO

82

82 79

79

79 75

75

91

66

76

63

65

79

62

58 75

61

56 65

60

48 63

59

46 62

58

28 61

57

27 58

49

26 43

40

25 42

8

24 27

7

8 8

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

OUT

IN

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

S

D

G

S

D

G

Q1

Q2

SW

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 0.75V * (1 + Ra / Rb)

<Ra>

(P1V25ENET_VFB)

Vout = 1.051V 10A max output (L7460? limit)

<Rb>

(GND)

Vout = 1.2496V

(P1V05S0_VFB)

<Ra>

(P1V05S0_TON)

(P1V25ENET_TON)

<Rb>

6A max output (Q7410 limit)

Vout = 0.75V * (1 + Ra / Rb)

(GND)

6.81K

1/16W 402

MF-LF

1%

R7405

1

2

65

7

36 65

MF-LF

200

1%

1/16W

402

R7401

1 2

SM

XW7400

1

2

QFN

CRITICAL

TPS51117RGY_QFN14

U7400

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

X5R 603

10%

2.2UF

16V

C7401

1

2

1UF

402

X5R

10% 10V

C7400

1

2

603-1

0.1UF

X7R

10% 50V

C7420

1

2

CRITICAL

2.2UH-14A

IHLP2525CZ-SM

L7410

1 2

1/16W MF-LF

402

1%

200K

R7421

1

2

CRITICAL

CASE-D2-LF

POLY

22UF

25V

20%

C7440

1

2

603

X5R

25V

1UF

10%

C7445

1

2

402

MF-LF

1/16W

1%

12.1K

R7431

1

2

8.06K

1/16W

402

MF-LF

1%

R7430

1

2

5% 50V CERM

NO STUFF

402

100PF

C7430

1

2

PLACEMENT_NOTE=Place XW7430 close to C7415.

SM

XW7430

1

2

20%

10UF

6.3V 603

X5R

C7415

1

2

MF-LF

1%

402

1/16W

7.5K

R7455

1

2

7

62 63 65

63 65

200

1%

MF-LF

1/16W

402

R7451

1 2

SM

XW7450

1

2

TPS51117RGY_QFN14

QFN

CRITICAL

U7450

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

16V

2.2UF

10%

603

X5R

C7451

1

2

1UF

402

X5R

10V

10%

C7450

1

2

PWRPK-1212-8

SI7108DNS

CRITICAL

Q7461

5

4

1 2 3

603-1

0.1UF

50V

10% X7R

C7470

1

2

SI7110DN

CRITICAL

PWRPK-1212-8

Q7460

5

4

1 2 3

IHLP2525CZ-SM

CRITICAL

1.0UH-22A

L7460

1 2

1/16W 402

1% MF-LF

200K

R7471

1

2

CASE-D2-LF

22UF

25V

20%

CRITICAL

POLY

C7490

1

2

X5R 603

1UF

10% 25V

C7495

1

2

402

MF-LF

1/16W

1%

14.0K

R7481

1

2

MF-LF

402

1%

1/16W

5.62K

R7480

1

2

100PF

NO STUFF

5% 50V

402

CERM

C7480

1

2

SM

PLACEMENT_NOTE=Place XW7480 close to C7465.

XW7480

1

2

X5R

20% 603

6.3V

10UF

C7465

1

2

330UF

CRITICAL

POLY CASE-B2

20%

2.0V

C7410

10%

CRITICAL

TANT D2T

330UF

2.0V

C7460

1

23

SM

XW7401

1

2

SM

XW7451

1

2

MLP

FDMS9600S

CRITICAL

Q7410

2349

1

8

56

7

10

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

1.25V / 1.05V Power Supply

051-7431

A.0.0

61 92

PPBUS_G3H

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V25ENET_DRVH

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

P1V25ENET_LL

MIN_LINE_WIDTH=0.6 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P1V25ENET_DRVL

GATE_NODE=TRUE

PP5V_S5

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.2 mm

P1V25ENET_VBST

MIN_LINE_WIDTH=0.6 mm

GND_P1V25ENET_SGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.25 mm

PP1V25_ENET

P1V25ENET_TON

P1V25ENET_VFB

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVLP1V05S0_TRIP

PP1V05_S0

PP5V_S5_P1V25ENET_V5FILT

MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

PP5V_S5

P1V8P1V5P1V05S0_PGOOD

PM_ENET_EN TP_P1V25ENET_PGOOD

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V25ENET_PGND

MIN_NECK_WIDTH=0.2 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.6 mm

P1V05S0_PGND

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

PP5V_S5_P1V05S0_V5FILT

VOLTAGE=5V

PP1V05_S0_VDDQSNS

PM_SLP_S3_DELAY_L

PP1V25_ENET_VDDQSNS

PP1V25_ENET

PPBUS_G3H

P1V05S0_VFB

P1V25ENET_TRIP

MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE MIN_LINE_WIDTH=0.6 mm

P1V05S0_DRVH

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.25 mm

P1V05S0_VBST

VOLTAGE=0V

GND_P1V05S0_SGND

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.2 mm

SWITCH_NODE=TRUE

P1V05S0_LL

MIN_LINE_WIDTH=0.6 mm

P1V05S0_TON

61

82

50

82

79

46

79

75

30

75

66

79

27

79

66

63

75

26

75

63

62

65

23

65

62

61

63

21

63

61

60

62

19

62

60

59

61

18

61

59

58

60

14

60

58

57

58

13

58

57

49

43

61

12

43

61

49

40

42

58

11

42

58

40

8

27

35

10

27

35

8

7

8

7

MODE

VDDQSNS

COMP

NC0 NC1

VTTSNS

VTT

VTTREF

PGOOD

S3 S5

VTTGND

THRM_PAD

GND

CS_GND

PGND

CS

LL

DRVL

DRVH

VDDQSET

VBST

VLDOINV5FILT

V5IN

SYM (2 OF 2)

IN IN OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_5_ITEM

CRITICAL BOM OPTION

TABLE_5_HEAD

PART#

DESCRIPTION

QTY

REFERENCE DESIGNATOR(S)

(P1V8S3_LL)

(P1V8S3_DRVL)

<Ra>

<Rb>

Vout = VDDQSNS/2

10mA max load

NC

VTT Enable

Vout = VTTREF

VDDQ/VTTREF Enable

Place at pin 23

Vout = 1.80V or 1.825V

VDDQ PGOOD

(P1V8S3_DRVH)

(P1V8S3_CSGND)

(P1V8S3_FB)

(Q7536 limit)

12A max output

(P1V8S3_VDDQSNS)

Vout = 0.75V * (1 + Ra / Rb)

C7545

Place next to

X7R-CERM

805

10% 50V

0.1UF

C7525

1%

402

MF-LF

1/16W

21K

P1V8S3_1V8

R7520

1

2

402

15.0K

1/16W MF-LF

1%

R7521

1

2

330UF

CASE-C2

2.5V POLY

20%

CRITICAL

C7540

1

2

330UF

CRITICAL

20%

CASE-C2

POLY

2.5V

C7541

1

2

25V X5R

1UF

603

10%

C7532

1

2

NO STUFF

100PF

5%

CERM

50V 402

C7520

1

2

CRITICAL

QFN

TPS51116

U7500

6

16

17

21

19

3

20

4

7

12

18

13

10 11

25

14

15

22

9

8

23

24

1

5

2

402

1UF

10V

10% X5R

C7505

1

2

4.7

5%

402

1/16W MF-LF

R7505

1 2

CRITICAL

20%

6.3V

22UF

CERM-X5R

805-3

C7561

1

2

CRITICAL

20%

6.3V

22UF

CERM-X5R 805-3

C7560

1

2

SM

XW7560

1 2

SM

XW7535

1 2

16V X5R 402

10%

0.033UF

C7550

1

2

7

25 35 36 40 45 49 58 65

805-2

10UF

CERM

20% 10V

C7500

1

2

65

402

MF-LF

1/16W

1%

5.62K

R7510

1

2

7

61 63 65

25V

POLY

CASE-D2-LF

20%

22UF

CRITICAL

C7530

1

2

25V

CASE-D2-LF

POLY

22UF

20%

CRITICAL

C7531

1

2

RJK0305DPB

LFPAK

CRITICAL

Q7530

5

4

1 2 3

IHLP4040DZ11-SM

1.0UH-20A

CRITICAL

L7530

1 2

10UF

X5R 603

20%

6.3V

C7545

1

2

LFPAK

RJK0301DPB

CRITICAL

Q7536

5

4

1 2 3

SM

XW7545

1

2

X5R

10UF

20%

603

6.3V

C7501

1

2

SM

XW7500

1

2

RES,MTL FILM,21.5K,1%,0402,SM,LF

CRITICAL

1

R7520

P1V8S3_1V825

114S0346

SYNC_MASTER=M87_MLB

1.8V DDR2 Supply

051-7431

62 92

A.0.0

SYNC_DATE=08/28/2007

P1V8S3_VDDQSNS

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

P1V8S3_FB

VOLTAGE=0V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

GND_P1V8DDRREG_SGND

P1V8S3_DRVH

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

P1V8S3_CS

P1V8S3_CSGND

MIN_LINE_WIDTH=0.6 mm VOLTAGE=5V

MIN_NECK_WIDTH=0.2 mm

PP5V_S5_P1V8DDRREG_V5FILT

PP5V_S5

PP0V9_S3_MEM_VREF

PPBUS_G3H

PM_SLP_S3_L P1V8S3_EN P1V8P1V5P1V05S0_PGOOD

PP0V9_S0

DDRREG_VTTSNS

PP1V8_S3

P1V8S3_DRVL

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P1V8S3_LL

P1V8S3_VBST

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

PP1V8_S3

82 79 75

79

66

75

63

65

61

63

60

61

59

91

60

58

62

58

57

50

43

32

49

38

42

31

40

32

27

16

8

33

31

8

7

8

IN

OUT

THRM_PAD

VFB

TRIP

VOUT

EN_PSV

GND

PGND

V5DRV

V5FILT

DRVL

DRVH

LL

TON

VBST

PGOOD

SYM (2 OF 2)

Q1

Q2

SW

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(GND)

Vout = 1.50V

(P1V5S0_VFB)

(L7620 limit)

4.5A max output

Vout = 0.75V * (1 + Ra / Rb)

(P1V5S0_TON)

<Rb>

<Ra>

NO STUFF

CERM

100PF

50V 402

5%

C7610

1

2

0.1UF

X7R

10% 50V

603-1

C7615

1

2

CASE-D2-LF

22UF

25V

20%

POLY

CRITICAL

C7620

1

2

CASE-B2-SM-HF

220UF

20%

2.5V POLY

CRITICAL

C7632

1

2

61 65

7

61 62 65

10V

10%

1UF

X5R 402

C7600

1

2

200

1/16W MF-LF

402

1%

R7601

1 2

2.2UF

16V

10% 603

X5R

C7601

1

2

200K

MF-LF

1%

402

1/16W

R7619

1

2

CRITICAL

QFN

TPS51117RGY_QFN14

U7600

13

9

1

7

12

8

6

15

2

11

10

4

14

5

3

X5R

25V

1UF

10%

603

C7621

1

2

PLACEMENT_NOTE=Place XW7620 close to L7620.

SM

XW7620

1

2

SM

XW7600

1 2

CRITICAL

FDMS9600S

MLP

Q7620

2349

1

8

56

7

10

402

MF-LF

4.32K

1% 1/16W

R7605

1

2

10UF

603

X5R

20%

6.3V

C7630

1

2

MF-LF

10K

1%

402

1/16W

R7610

1

2

10K

1/16W MF-LF

402

1%

R7611

1

2

1.5UH-7.5A-18M-OHM

CRITICAL

IHLP2525BD-SM

L7620

1 2

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

1.5V Power Supply

A.0.0

051-7431

63 92

P1V5S0_TON

P1V5S0_VFB

MIN_NECK_WIDTH=0.25 mm

GND_P1V5S0_SGND

MIN_LINE_WIDTH=0.6 mm VOLTAGE=0V

MIN_LINE_WIDTH=0.25 mm

P1V5S0_VBST

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm

P1V5S0_DRVH

GATE_NODE=TRUE

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.6 mm

SWITCH_NODE=TRUE

P1V5S0_LL

MIN_NECK_WIDTH=0.2 mm

P1V5S0_DRVL

MIN_LINE_WIDTH=0.6 mmGATE_NODE=TRUE

PP5V_S5

PPBUS_G3H

P1V5S0_TRIP

PP1V5_S0

PP5V_S5_P1V5S0_V5FILT

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=5V

P1V8P1V5P1V05S0_PGOOD

PM_SLP_S3_DELAY_L

PP1V5_S0

PP1V5_S0_VDDQSNS

82 79 75

79

66

75

62

65

61

91

62

60

63

61

59

34

60

58

27

58

57

26

43

49

22

42

40

12

27

8

11

8

7

8

OUT

IN

NR

NC

THRML

EN

GND

PAD

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

200mA max output

1.95V FW PHY Supply

VP short to keep PHY powered.

Backup power in case of FW bus

NC

3.3V FW PHY Supply

Vout = 1.25V * (1 + Ra / Rb)

Vout = 3.316V

<Rb>

NC

<Ra>

(Switcher limit)

4V

20% 402

X5R

2.2uF

C7722

1

2

16V

10% 402

CERM

0.01uF

C7721

1

2

6.3V

10% 402

CERM

1uF

C7720

1

2

SON

TPS799195

CRITICAL

U7720

4

3

6

5

2

1

7

402

MF-LF

1/16W

1%

324K

R7710

1

2

1/16W

1%

402

MF-LF

196K

R7711

1

2

50V

5%

402

CERM

22pF

C7710

1

2

402

20% X5R

6.3V

0.22uF

C7705

1

2

50V

X7R-CERM

10%

1206

4.7UF

C7700

1

2

CRITICAL

TSOT23-8

LT3470

U7700

7

6

8

4

2

1 5

3

SMD20E40C-X-F

SC-59

D7700

1

2

3

33uH

CDPH4D19F-SM

CRITICAL

L7700

1 2

CRITICAL

6.3V

20%

22UF

CERM-X5R 805-3

C7701

1

2

SYNC_MASTER=M87_MLB

FW PHY Power Supplies

SYNC_DATE=08/28/2007

051-7431

A.0.0

9264

PP3V3_FW

P3V3FW_FB

P3V3FW_BOOST

PPBUS_FW_FWPWRSW_F

PP3V3_FW

PPVP_FW

VOLTAGE=33V

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PPVIN_FW_P3V3FW

P3V3FW_SW

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

P1V95FW_NR

PP1V95_FW

64

41

40

39

40

39

8

FB

BIAS

SW

SHDN*

NC

VIN

BOOST

GND

OUT OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

OUT

IN

OUT

IN

OUT

V1

PBR*

GND

THRM_PAD

CRT

RST*

V3

V4

V2

VPG

VREF

G

D

S

OUT

G

D

S

Y

B

A

Y

B

A

Y

B

A

OUT

RESET*

RESET-IN

GND

VCC

IN

OUT

IN

G

D

S

OUT

G

D

S

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

3.425V "G3Hot" Supply

Supply needs to guarantee 3.31V delivered to SMC VRef generator

<Rb>

Vout = 1.25V * (1 + Ra / Rb)

1.5V / 1.05V PWRGD Circuit

TPS51117 PGOOD threshold 92.5-97.5% (1.36 - 1.46V)

TPS51117 PGOOD does not

VIDs are changing

2) 3.3V

1) 1.2V

G84M GPU requires rails to come up in the following order:

3) Vcore

4) 1.8V

PP3V3GPU_EN IS A PROXY FOR 1.2V

LTC2900 typical threshold is 93.5% (4.675V, 3.086V, 1.685V,1.120V)

To CPU IMVP6

PM_SLP_S3_LPM_SLP_S4_L

SMC_PM_G2_ENABLE

Run (S0)

State

Soft-Off (S5)

Battery Off (G3Hot)

0

1

1 1

0 0

1

0

1

Vout = 3.425

NC

<Ra>

NC

Trst = 4.6ms/nF Trst = 216ms

(Switcher limit)

200mA max output

Reports when 1.5V S0 and 1.05V S0 are in regulation

(PM_S4_STATE_L)

(PM_ENET_EN)

Unused PGOOD Signals

TPS51117 PGOOD threshold 92.5-97.5% (0.98 - 1.02V)

Sleep (S3)

Other S0 Rails PWRGD Circuit

NOTE: 0.9V is not checked!

GPU core voltage.

deassert while GPU

Need to ensure that

Power Control Signals

(PM_SLP_S3_L)

MAX6838 threshold is 93.5% @ 1.120V

CRITICAL

TSOT23-8

LT3470

U7800

7

6

8

4

2

1 5

3

10UF

X5R

1206-1

10% 25V

C7800

1

2

6.3V

20%

22UF

CERM-X5R 805-3

C7815

1

2

1/16W

200K

MF-LF 402

1%

R7811

1

2

100K

402

5%

MF-LF

1/16W

R7865

1

2

7

25 35 36 40 45 49

58 62 65 7

25 35 36 40

45 49 58 62 65

61 63 65

7

25 35 36 40

45 49 58 62 65

7

25 35 36 40

45 49 58 62 65 7

25 35 36 40

45 49 58 62 65

61 63 65

34 65

65 75 79

7

25 34 43 45 58 65

7

25 34 43 45 58 65

62 65

SC70

MC74VHC1G08

U7880

3

2

1

4

5

7

25 34 43 45 58 65

7

25 34 43 45 58 65

7

25 35 36 40

45 49 58 62 65

10V

20% 402

CERM

0.1UF

C7880

1

2

7

36 61 65

49 59

7

36 61 65

45 60 65

7

61 62 63 65

45 60 65

MF-LF 402

5% 1/16W

0

ISL9504A

R7866

1

2

402

MF-LF

1%

93.1K

1/16W

R7871

1

2

9.53K

1/16W 402

1% MF-LF

R7870

1

2

CRITICAL

DFN

LTC2900

U7870

3

6

5

4

11

2

10

1

9

7

8

CERM

402

10%

0.047UF

16V

C7875

1

2

402

CERM

10V

20%

0.1UF

C7872

12

1/16W MF-LF 402

5%

10K

R7875

1

2

CERM

10V 402

20%

0.1UF

C7871

1

2

0.1uF

10V

20%

CERM

402

C7870

1

2

2N7002DW-X-F

SOT-363

Q7851

3

5

4

65 73 75

SOT-363

2N7002DW-X-F

Q7851

6

2

1

5%

MF-LF

402

100K

1/16W

R7852

1

2

5%

1/16W

10K

MF-LF

402

R7854

1

2

MC74VHC1G09

SC70

U7850

3

2

1

4

5

MF-LF

1/16W

402

5%

10K

R7859

1

2

5%

MF-LF

10K

402

1/16W

R7855

1 2

CERM-X5R

10%

402

0.47UF

6.3V

C7855

1

2

16V

10%

CERM

402

0.047UF

NO STUFF

C7859

1

2

SC70

MC74VHC1G09

U7858

3

2

1

4

5

MC74VHC1G09

SC70

U7859

3

2

1

4

5

60 65

100K

MF-LF

402

1/16W

5%

R7858

1

2

0.1UF

20% 10V

CERM

402

C7858

12

MAX6838XSD0

SC70-4

U7860

3

4

1

2

100K

402

1/16W

5%

MF-LF

R7862

1

2

100K

1%

402

MF-LF

1/16W

R7861

1

2

154K

1% 1/16W MF-LF

402

R7860

1

2

7

61 62 63 65

58 65

CERM

402

25V

10%

0.0047UF

C7860

1

2

58 65

CDPH4D19F-SM

33UH

CRITICAL

L7810

1 2

402

0.1UF

CERM

20% 10V

C7851

1

2

7

61 62 63 65

10K

402

1/16W MF-LF

5%

R7851

1

2

10K

402

MF-LF

5%

1/16W

R7850

1

2

SOT-363

2N7002DW-X-F

Q7850

6

2

1

28 45 46

402

348K

MF-LF

1% 1/16W

R7810

1

2

2N7002DW-X-F

SOT-363

Q7850

3

5

4

65 75 79

CERM

402

22pF

5%

50V

C7810

1

2

100K

402

1/16W

5%

MF-LF

R7856

1

2

7

25 35 36 40 45 49

58 62 65

MF-LF

10K

402

5%

1/16W

R7857

1

2

7

25 34 43 45 58 65

45 60 65

6.3V

0.22uF

X5R 402

20%

C7805

1

2

3.425V G3Hot Supply & Power Control

051-7431

9265

A.0.0

SYNC_MASTER=M87_MLB

SYNC_DATE=09/26/2007

S0PGOOD_1V2_DIV

PP3V3_S3

MAKE_BASE=TRUE

PM_P3V3GPU_EN

MAKE_BASE=TRUE

PM_SLP_S3_L

PM_SLP_S3_LS5V

MAKE_BASE=TRUE

PM_SLP_S3_L

PM_P3V3GPU_EN

PP3V3_S0 PP1V8_S0GPU_ISNS

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm SWITCH_NODE=TRUE

P3V42G3H_SW

PM_P3V3GPU_EN

PM_ENET_EN

PM_SLP_S3_L

PM_SLP_S3_L PM_SLP_S3_L

PP5V_S0

PP3V42_G3H

PM_SLP_S3_L

PM_G2_EN

PP3V3_S5

P1V8P1V5P1V05S0_PGOOD

MAKE_BASE=TRUE

P1V8S3_EN

PM_SLP_S3_L

MAKE_BASE=TRUE

P1V8S3_EN

PM_G2_EN

PM_G2_P3V3S5_EN

MAKE_BASE=TRUE

TP_P1V25ENET_PGOODTP_P1V25ENET_PGOOD

MAKE_BASE=TRUE

TP_P1V8_S0GPU_PGOODTP_P1V8_S0GPU_PGOOD

MAKE_BASE=TRUE

PM_S4_STATE_L

MAKE_BASE=TRUE

PM_G2_EN

PM_G2_P5VS5_EN

S0PGOOD_VPG

PM_ENET_EN

MAKE_BASE=TRUE

P1V8P1V5P1V05S0_PGOOD

PM_SLP_S3_DELAY_L

MAKE_BASE=TRUE

PM_S4_STATE_L

PM_GPUVCORE_EN

PM_P1V8_S0GPU_EN

PP3V3_S0GPU

PM_G2_P3V3S5_EN

IMVP6_IMON

S0PGOOD_CRT

ALL_SYS_PWRGD

P3V42G3H5_BOOST

PP3V3_S0

PM_SLP_S3_DELAY_L PM_SLP_S3_DELAY_L

PP3V3_S0

S0PGOOD_PWROK

PM_G2_EN

S0PGOOD_VREF

PM_G2_P5VS5_EN

MAKE_BASE=TRUE

PM_S4_STATE_L

PP1V25_S0_ISNS

PM_SLP_S3_LS5V

PVCOREGPU_EN_L

PPDCIN_G3H

MAKE_BASE=TRUE

PM_P1V8_S0GPU_EN

MAKE_BASE=TRUE

PM_GPUVCORE_EN

PM_P1V8_S0GPU_EN

PP5V_S5

P1V8P1V5P1V05S0_PGOOD

PP3V3_S5

P3V42G3H_FB

PP3V42_G3H

91

82

65

59

58

53

52

51

50

48

47

46

42

32

31

91

31

91

30

82

76

30

76

29

81

65

29

65

81

28

80

66

60

28

79

60

66

81

27

59

65

58

27

75

58

65

58

26

78

58

57

56

80

26

72

63

56

57

55

25

77

54

48

76

25

69

62

48

54

24

74

52

47

46

75

24

67

61

46

47

51

23

71

49

46

28

74

23

50

60

28

46

50

21

70

47

45

27

73

21

27

58

27

45

48

19

69

42

43

26

65

72

19

26

43

26

43

38

16

68

27

28

25

60

58

16

21

66

79

42

25

28

36

65

13

50

65

8

24

65

65 65

79

45

48

13

30

65

19

57

75

27

24

8

58

34

8

58

7

8

62

60

61 61

65

8

29

60

8

65

8

7

S3 S2

D1

D2

D3

D4

GATE

S1

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

D

SG

D

S G

D

G S

GND

VCC

PGOOD

OUT

FB

IN

SHDN*

I.C.

THRML

PAD

S3 S2

D1

D2

D3

D4

GATE

S1

ACSET

EN

CSIP

DCPRN

THRML_PAD

PGND

DCSET

LGATE

UGATE

BOOT

BGATE

DCIN

CSIN

SGATE

VREF

ACPRN

CSON

CSOP

VCOMP

ICOMP

VDDP

CELLS

VADJ

VDD

CHLIM

PHASE

FB

ACLIM

GND

IN-

V+

V-

IN+

SHDN*

S3 S2

D1

D2

D3

D4

GATE

S1

S3 S2

D1

D2

D3

D4

GATE

S1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

10A MAX, LIMITED BY L7900, Q7901

Battery Charge FETs

Energy Star LDO

As shown, Ichg = 4.5A max

Battery Charge Current Limit

PBus Supply & Battery Charger

NC

353S1510

As shown, Isys =~4.6A max

Adapter Input Current Limit

SINKING CURRENT FROM VREF.

ARE PROVIDED WITH SUFFICIENT CURRENT WITHOUT

VOLTAGE FOLLOWER GUARANTEES CURRENT LIMIT CIRCUITS

SM

XW7900

1 2

1/16W

3.01K

MF-LF

1%

402

R7902

1 2

10%

402

CERM

1uF

6.3V

C7912

1

2

6.3V

10%

402

CERM

1uF

C7911

1 2

IRLML5203-2.6A

SM

S

D

G

Q7940

3

1

2

603

CERM

0.1UF

25V

20%

C7940

1

2

MF-LF

3.01K

1/16W

1%

402

R7960

1 2

402

16V

10% CERM

0.047UF

C7961

1

2

17.8K

1/16W

1%

402

MF-LF

R7962

1 2

402

10% 16V CERM

0.01UF

C7962

1

2

1/16W

1%

402

MF-LF

20.0K

R7963

1

2

402

1% 1/16W MF-LF

11.3K

R7966

1

2

CRITICAL

3W MF

27

5%

2525-1

R7920

1 2

1/16W

1%

402

MF-LF

11.3K

R7941

1

2

402

1/16W

110K

1%

MF-LF

R7940

1

2

SO-8

SI4413ADY-E3

CRITICAL

Q7921

5

6

7

8

4

1

2

3

1206-1

8AMP-24V

CRITICAL

F7902

1 2

158K

MF-LF 402

1% 1/16W

R7967

1

2

10%

680pF

NO STUFF

50V

CERM

402

C7915

1 2

1/16W

402

5%

MF-LF

2.2

R7903

1 2

0

MF-LF

1/16W

5%

402

R7904

1 2

0.1UF

CERM 603

25V

20%

NO STUFF

C7907

1

2

CERM

0.22uF

402

10% 10V

C7925

1

2

470K

MF-LF

402

1%

1/16W

R7930

1

2

49.9

MF-LF

1/16W

603

0.5%

R7970

1 2

CERM 603

50V

0.0022uF

10%

C7970

1

2

MF-LF

100K

1/16W

1%

402

R7944

1

2

MF-LF

5%

1/8W

47

805

R7921

1 2

1%

100K

1/16W MF-LF

402

R7924

1

2

1W

0612

MF

0.5%

0.02

R7907

1 2

SM

XW7901

1

2

SM

XW7902

1

2

SOD-323

1SS355

D7921

1 2

20% 25V POLY

22UF

CRITICAL

CASE-D2-LF

C7908

1

2

10% X5R

603

16V

1UF

C7910

1

2

CRITICAL

RJK0305DPB

LFPAK

Q7901

5

4

1 2 3

RJK0305DPB

CRITICAL

LFPAK

Q7902

5

4

1 2 3

1/16W

1%

402

MF-LF

3.48K

R7968

1

2

402

MF-LF

1/16W

5%

10K

R7969

1

2

X5R

10% 16V

402

0.1uF

C7941

1

2

1/16W

5%

402

MF-LF

10K

R7979

1

2

SM

XW7904

1

2

SM

XW7903

1

2

56.2K

MF-LF

1/16W

1%

402

R7992

1

2

0.1UF

10V

20% 402

CERM

C7980

1

2

25V

20%

CASE-D2-LF

POLY

22UF

CRITICAL

C7906

1

2

25V

10% 805

X5R-CERM

2.2UF

CRITICAL

C7916

1

2

25V

10% 805

X5R-CERM

2.2UF

CRITICAL

C7917

1

2

CRITICAL

25V

20%

CASE-D2-LF

POLY

22UF

C7905

1

2

FDA1254-SM

4.7UH-10.2A

CRITICAL

L7900

1

2

3

10% 402

470PF

50V CERM

C7990

1

2

SSM6N15FE

SOT563

Q7960

6

2

1

SOT563

SSM6N15FE

Q7960

3

5

4

SSM6N15FE

SOT563

Q7961

6

2

1

SSM6N15FE

SOT563

Q7961

3

5

4

SOT-523-3

BAV99T-X-F

D7940

1

2

3

SSM6N15FE

SOT563

Q7924

3

5

4

SOT563

SSM6N15FE

Q7922

3

5

4

SSM6N15FE

SOT563

Q7922

6

2

1

SSM6N15FE

SOT563

Q7924

6

2

1

SOD-VESM

SSM3K15FV

Q7950

3

1

2

1/16W

1%

402

100K

MF-LF

R7950

1

2

1UF

X5R 603

10% 25V

C7950

1

2

1UF

25V

10%

603

X5R

C7951

1

2

402

200K

1% 1/16W MF-LF

R7952

1

2

MF-LF

19.6K

1%

402

1/16W

R7953

1

2

SOT-323

BAT54CW-X-F

D7950

1

2

3

TDFN

MAX8719

U7950

3

2

7

1

8

5

6

9

4

1/16W

5%

402

MF-LF

100K

R7954

1

2

1% 1/16W MF-LF 402

3.57K

R7964

1

2

SOT23

MMBZ5235B

CRITICAL

D7903

1 3

SI4413ADY-E3

SO-8

CRITICAL

Q7970

5

6

7

8

4

1

2

3

402

470K

5% 1/16W MF-LF

R7971

1 2

402

MF-LF

1/16W

330K

5%

R7972

1 2

10% 25V X5R

0.1UF

402

C7971

1 2

CRITICAL

ISL6257HRZ

QFN

U7900

8

23 27

17

14

2

7

20

19

22

21

25

24 28

1

5

10

3

12

11

16

18

29

15

9

4

26

13

6

SC70-6

CRITICAL

MAX4245AXT-T

U7901

3

1

4

5

6

2

0.033uF

16V

10%

402

X5R

C7900

1 2

X7R 402

1000PF

25V

10%

C7901

12

CRITICAL

SI4413ADY-E3

SO-8

Q7900

5

6

7

8

4

1

2

3

1/16W

1%

402

MF-LF

100K

NO STUFF

R7910

1

2

10V

20%

402

CERM

0.1UF

C7904

1

2

CRITICAL

SOD-123

B0530WXF

D7900

12

1/16W

5%

402

MF-LF

4.7

R7900

1 2

603

0.1UF

CERM

20% 25V

C7903

1 2

25V

0.0082uF

402

X7R

10%

C7902

1

2

1/16W MF-LF

402

5%

18

R7905

1 2

0.01

0.5% 1W

0612

MF

R7908

1 2

2.2

5%

1/16W

402

MF-LF

R7906

1 2

CRITICAL

SO-8

SI4413ADY-E3

Q7920

5

6

7

8

4

1

2

3

330K

MF-LF

402

5%

1/16W

R7931

1

2

402

39.2K

MF-LF

1% 1/16W

R7922

1

2

35.7K

MF-LF 402

1% 1/16W

R7923

1

2

0.01uF

CERM

402

10% 16V

C7920

1

2

402

10% 16V X5R

0.1uF

C7921

1

2

NO STUFF

20% 16V

CERM

402

0.01UF

C7924

1

2

16V

10%

402

CERM

NO STUFF

0.01UF

C7922

1

2

50V

10% 402

CERM

0.001UF

C7927

1

2

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

PBus Supply & Batt. Charger

051-7431

92

A.0.0

66

CHGR_VREF

CHGR_VREF_VF

PP3V42_G3H

CHGR_SGND

CHGR_ACSET

PPBUS_G3H

LDO_OUT

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.5MM

CHGR_VREF

CHGR_CHLIM

CHGR_CSO_P

CHGR_VDD

CHGR_ACPRN

BATT_POS

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

GND

TCHG_EN_DIV_L

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.2mm

TP_CHGR_VADJ

CHGR_ICM

TP_CHGR_DCPRN

CHGR_BOOT_R

CHGR_EN

TCHG_EN_DIV2_L

LDO_FDBK

SMC_SYS_ISET_L

CHGR_CHLIM_R

CHGR_VDD

NC

PP18V5_G3H_CHGR

CHGR_ACLIM

CHGR_ACLIM_R

CHGR_VREF_VF

CHGR_CSO_N

CHGR_VDD

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

PPVDCIN_G3H_PRE

SMC_BATT_ISET

SMC_SYS_ISET

PP3V42_G3H

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

PPVBAT_G3H_CHGR_OUT

CHGR_CSO_P

CHGR_CSO_R_P

CHGR_CSO_R_N

NO_TEST=TRUE

CHGR_PHASE_R

PPBUS_G3H

NC

CHGR_CHLIM

SMC_BATT_CHG_EN

SMC_BC_ACOK

CHGR_ACPRN

CHG_EN_DIV2_L

MIN_NECK_WIDTH=0.2mm

CHG_EN_DIV_L

MIN_LINE_WIDTH=0.2mm

SMC_BATT_TRICKLE_EN_L

CHGR_SGND

MIN_LINE_WIDTH=0.5mm MIN_NECK_WIDTH=0.25mm VOLTAGE=12.6V

PPVBATT_G3H_DIO

PP3V42_G3H

SMC_ENRGYSTR_LDO_EN

CHGR_SGND

CHGR_CSO_R_N

CHGR_VDDP

CHGR_SGATE

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.2mm

CHGR_DCIN

NC_CHGR_BGATE

NO_TEST=TRUE

CHGR_SGND

CHGR_EN

TP_CHGR_DCSET

CHGR_ACSET

CHGR_DCIN

CHGR_ACSET_D

CHGR_VCOMP

CHGR_ICOMP

CHGR_ACLIM

CHGR_VCOMP_C

CHGR_CSO_N

CHGR_ACPRN

MIN_NECK_WIDTH=0.2mm

MIN_LINE_WIDTH=0.6mm

CHGR_UGATE

CHGR_PHASE

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

SWITCH_NODE=TRUE

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

CHGR_BOOT

CHGR_CSI_N

CHGR_CSI_RN

NO_TEST=TRUE

CHGR_LGATE

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.2mm

CHGR_ICM_R

CHGR_SGND

CHGR_VREF_VF

PP18V5_G3H_CHGR

CHGR_SGND

SMC_BATT_ISET_L

PPVBAT_G3H_CHGR_OUT

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

PPVBATT_G3H_PRE

PPVBATT_G3H_FET_GATE

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

PPVBATT_G3H_FET_F

PPDCIN_G3H

MIN_LINE_WIDTH=0.6mm MIN_NECK_WIDTH=0.25mm

PPVBATT_G3H_FET

VOLTAGE=12.6V

MIN_NECK_WIDTH=0.25mm

MIN_LINE_WIDTH=0.6mm

PPVDCIN_G3H_R

CHGR_VDDP

CHGR_CSI_P

NO_TEST=TRUE

82

79

75

81

66

81

66

81

66

63

66

63

66

65

62

65

62

65

57

61

57

61

57

48

60

48

60

48

47

59

47

59

47

46

58

46

58

46

45

57

45

57

45

43

49

43

49

57

43

28

40

28

40

46

28

46

65

8

57

66

8

66

8

46

45

46

8

45

66

57

66

7

66

7

66

7

66

57

66

45

7

66

66 53

53

7

66

45

34

66

45

66

7

9

66

53

66

53

66

57

66

8

66

53

OUT

PEX_TX0

PEX_TX0_L

PEX_RX4

PEX_RX0

PEX_TX1PEX_RX1

PEX_RX2 PEX_TX2

PEX_RX3 PEX_TX3

PEX_TX4

PEX_TX5PEX_RX5

PEX_TX6PEX_RX6

PEX_RX7 PEX_TX7

PEX_TX8PEX_RX8

PEX_TX9PEX_RX9

PEX_TX10PEX_RX10

PEX_TX11PEX_RX11

PEX_TX12PEX_RX12

PEX_TX13PEX_RX13

PEX_TX14PEX_RX14

PEX_TX15PEX_RX15

PEX_TSTCLK_OUT

PEX_REFCLK

PEX_TX1_L

PEX_TX2_L

PEX_TX3_L

PEX_TX4_L

PEX_TX5_L

PEX_TX6_L

PEX_TX7_L

PEX_TX8_L

PEX_TX9_L

PEX_TX10_L

PEX_TX11_L

PEX_TX12_L

PEX_TX13_L

PEX_TX14_L

PEX_TX15_L

PEX_TSTCLK_OUT_L

PEX_RST_L

PEX_REFCLK_L

PEX_RX15_L

PEX_RX14_L

PEX_RX13_L

PEX_RX12_L

PEX_RX11_L

PEX_RX10_L

PEX_RX9_L

PEX_RX8_L

PEX_RX7_L

PEX_RX6_L

PEX_RX5_L

PEX_RX4_L

PEX_RX3_L

PEX_RX2_L

PEX_RX1_L

PEX_RX0_L

PCI-EXPRESS BUS INTERFACE

NC

PEX_IOVDD_1 PEX_IOVDD_2 PEX_IOVDD_3 PEX_IOVDD_4 PEX_IOVDD_5 PEX_IOVDD_6

PEX_IOVDDQ_1 PEX_IOVDDQ_2 PEX_IOVDDQ_3 PEX_IOVDDQ_4 PEX_IOVDDQ_5 PEX_IOVDDQ_6 PEX_IOVDDQ_7 PEX_IOVDDQ_8

PEX_IOVDDQ_9 PEX_IOVDDQ_10 PEX_IOVDDQ_11

PEX_PLLAVDD PEX_PLLDVDD

PEX_PLLGND

IN

IN IN

IN

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =PP1V2_GPU_PEX_PLLXVDD

- =PP1V2_GPU_PEX_IOVDD

1500mA

20mA

180mA

(NONE)

250mA

PEX 1.2V Current = 2A

BOM options provided by this page:

- =PP1V2_GPU_PEX_IOVDDQ

Signal aliases required by this page:

Page Notes

Power aliases required by this page:

15 84

10% 16V

0.1uF

402X5R

C8081

1 2

40210% 16V X5R

0.1uF

C8082

1 2

15 84

X5R10% 16V 402

0.1uF

C8079

1 2

10% 16V X5R

0.1uF

402

C8080

1 2

15 84

10% 16V X5R

0.1uF

402

C8077

1 2

0.1uF

10% 16V X5R 402

C8078

1 2

15 84

10% 16V X5R

0.1uF

402

C8075

1 2

10% 16V X5R

0.1uF

402

C8076

1 2

15 84

10% 16V X5R

0.1uF

402

C8073

1 2

10% 16V X5R

0.1uF

402

C8074

1 2

15 84

0.1uF

X5R16V10% 402

C8020

1 2

15 84

10% 16V X5R

0.1uF

402

C8071

1 2

10% 16V X5R

0.1uF

402

C8072

1 2

15 84

10% 16V X5R

0.1uF

402

C8069

1 2

10% 16V X5R

0.1uF

402

C8070

1 2

15 84

10% 16V X5R

0.1uF

402

C8067

1 2

402X5R16V

0.1uF

10%

C8021

1 2

10% 16V X5R

0.1uF

402

C8068

1 2

15 84

10% 16V X5R

0.1uF

402

C8065

1 2

10% 16V X5R

0.1uF

402

C8066

1 2

15 84

10% 16V X5R

0.1uF

402

C8063

1 2

10% 16V X5R

0.1uF

402

C8064

1 2

15 84

402

0.1uF

X5R16V10%

C8050

1 2

15 84

10% 16V X5R

0.1uF

402

C8061

1 2

10% 16V X5R 402

0.1uF

C8062

1 2

15 84

10% 16V X5R

0.1uF

402

C8059

1 2

10% 16V X5R

0.1uF

402

C8060

1 2

15 84

10% 16V X5R

0.1uF

402

C8057

1 2

0.1uF

402X5R16V10%

C8051

1 2

10% 16V X5R 402

0.1uF

C8058

1 2

402

0.1uF

X5R16V10%

C8048

1 2

402

0.1uF

X5R16V10%

C8049

1 2

402

0.1uF

10% X5R16V

C8046

1 2

OMIT

(1 OF 8)

BGA

NB8P-GS-W-A2

U8000

AH14 AJ14

AH15

AK13 AK14

AM14 AM15

AL23 AL24

AM24 AM25

AK25 AK26

AL26 AL27

AM27 AM28

AL28 AL29

AL15 AL16

AK16 AK17

AL17 AL18

AM18 AM19

AK19 AK20

AL20 AL21

AM21 AM22

AK22 AK23

AM12 AM11

AJ15 AK15

AH16 AG16

AG23 AH23

AK24 AJ24

AJ25 AH25

AH26 AG26

AK27 AJ27

AJ28 AH27

AG17 AH17

AG18 AH18

AK18 AJ18

AJ19 AH19

AG20 AH20

AG21 AH21

AK21 AJ21

AJ22 AH22

NB8P-GS-W-A2

BGA

(2 OF 8)

OMIT

U8000

A26

M5 U6 V1 V3 V4 V5 V6 W1 W3 W4

A28

W5 Y5

Y6 AC26 AD26 AE26 AG12 AH13 AH31 AH32

B32

AM8 AM9

D1

D31 D32

F1

F6

G8

AD23 AF23 AF24 AF25 AG24 AG25

AC16

AF21 AF22

AC17 AC21 AC22 AE18 AE21 AE22 AF12 AF18

AF15 AE15 AE16

4.7UF

CERM 603

20%

6.3V

C8001

1

2

CERM 402

1UF

10%

6.3V

C8003

1

2

402

CERM

20%

0.1UF

10V

C8004

1

2

0.1uF

X5R16V10% 402

C8047

1 2

20% CERM

402

0.1UF

10V

C8005

1

2

CERM

4.7UF

20%

6.3V 603

C8016

1

2

603

6.3V

20%

4.7UF

CERM

C8015

1

2

20%

805

6.3V

22UF

CERM-X5R

C8000

1

2

0.1uF

402X5R16V10%

C8044

1 2

1UF

6.3V

10%

402

CERM

C8002

1

2

22UF

6.3V 805

20% CERM-X5R

C8006

1

2

CERM

6.3V

20%

603

4.7UF

C8007

1

2

CERM

10%

6.3V

1UF

402

C8008

1

2

6.3V

10%

1UF

402

CERM

C8009

1

2

10V

0.1UF

20% CERM

402

C8010

1

2

CERM

20% 10V

0.1UF

402

C8011

1

2

0.1UF

20% 10V

402

CERM

C8017

1

2

16V 402

0.1uF

X5R10%

C8045

1 2

603

6.3V

20%

4.7UF

CERM

C8013

1

2

CERM 402

10V

20%

0.1UF

C8014

1

2

603

6.3V

20%

4.7UF

CERM

C8012

1

2

10NH-600MA

0603

L8015

1 2

10NH-600MA

0603

L8012

1 2

402

0.1uF

X5R16V10%

C8042

1 2

402

0.1uF

X5R16V10%

C8043

1 2

402

0.1uF

X5R16V10%

C8040

1 2

402

0.1uF

X5R16V10%

C8041

1 2

402

0.1uF

X5R16V10%

C8038

1 2

0.1uF

402X5R16V10%

C8039

1 2

402

0.1uF

X5R16V10%

C8036

1 2

402

0.1uF

X5R16V10%

C8037

1 2

402

0.1uF

X5R16V10%

C8034

1 2

402

0.1uF

X5R16V10%

C8035

1 2

402

0.1uF

X5R16V10%

C8032

1 2

16V 402

0.1uF

X5R10%

C8033

1 2

402

0.1uF

X5R16V10%

C8030

1 2

0.1uF

402X5R16V10%

C8031

1 2

402

0.1uF

X5R16V10%

C8028

1 2

402

0.1uF

X5R16V10%

C8029

1 2

402

0.1uF

X5R16V10%

C8026

1 2

402

0.1uF

X5R16V10%

C8027

1 2

10% 402

0.1uF

X5R16V

C8024

1 2

402

0.1uF

X5R16V10%

C8025

1 2

16V 402X5R10%

0.1uF

C8022

1 2

402

0.1uF

X5R16V10%

C8023

1 2

15 84

9

29 30 88

9

29 30 88

7

28

402

0.1uF

X5R16V10%

C8055

1 2

402

0.1uF

X5R16V10%

C8056

1 2

15 84

10% 16V X5R

0.1uF

402

C8085

1 2

0.1uF

10% 16V X5R 402

C8086

1 2

15 84

10% 16V X5R

0.1uF

402

C8083

1 2

10% 16V X5R

0.1uF

402

C8084

1 2

15 84

NV G84M PCI-E

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

67 92

A.0.0

051-7431

PP1V25_S0_ISNS

NO_TEST=TRUE

NC_GPU_DFM

PP1V25_S0_ISNS

PP1V2_GPU_PEX_PLLAVDD_F

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=1.2V

VOLTAGE=1.2V

PP1V2_GPU_PEX_PLLDVDD_F

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

PEG_R2D_N<10>

PEG_R2D_P<11> PEG_R2D_N<11>

PEG_D2R_C_P<13>

PEG_R2D_C_N<11>

PEG_R2D_N<13>

PEG_D2R_C_N<13>

PEG_R2D_C_P<12>

PEG_R2D_C_N<12>

PEG_CLK100M_GPU_N

TP_GPU_PEXTSTCLK_P

PEG_D2R_C_N<15>

PEG_D2R_C_P<15>

GPU_RESET_L

PEG_CLK100M_GPU_P

PEG_R2D_C_N<14>

PEG_R2D_C_P<15>

PEG_R2D_P<15>

PEG_R2D_C_N<13>

PEG_R2D_C_P<14>

PEG_R2D_C_P<13>

PEG_R2D_C_P<11>

PEG_R2D_C_P<10>

PEG_R2D_C_N<10>

PEG_R2D_C_P<9>

PEG_R2D_C_N<9>

PEG_R2D_C_P<8>

PEG_R2D_C_N<8>

PEG_R2D_C_N<7>

PEG_R2D_C_N<6>

PEG_R2D_C_N<5>

PEG_R2D_C_P<6>

PEG_R2D_P<14>

PEG_R2D_P<13>

PEG_R2D_P<12>

PEG_R2D_P<10>

PEG_R2D_P<9>

PEG_R2D_P<8>

PEG_R2D_P<7>

PEG_R2D_P<6>

PEG_R2D_C_N<4>

PEG_R2D_C_P<5>

PEG_R2D_C_N<3>

PEG_R2D_C_P<4>

PEG_R2D_C_P<3>

PEG_R2D_C_P<2>

PEG_R2D_C_N<2>

PEG_R2D_C_P<1>

PEG_R2D_C_N<1>

PEG_R2D_C_P<0>

PEG_R2D_C_N<0>

PEG_R2D_P<5>

PEG_R2D_P<4>

PEG_R2D_P<3>

PEG_R2D_P<2>

PEG_R2D_P<1>

PEG_R2D_P<0>

PEG_R2D_N<14>

PEG_R2D_N<15>

PEG_R2D_N<12>

PEG_R2D_N<5>

PEG_R2D_N<9>

PEG_R2D_N<8>

PEG_R2D_N<7>

PEG_R2D_N<4>

PEG_R2D_N<1>

PEG_R2D_N<2>

PEG_R2D_N<3>

PEG_R2D_N<0>

PEG_D2R_C_N<14>

PEG_D2R_C_N<12>

PEG_D2R_C_N<10>

PEG_D2R_C_N<9>

PEG_D2R_C_N<7>

PEG_D2R_C_N<6>

PEG_D2R_C_N<5>

PEG_D2R_C_N<4>

PEG_D2R_C_N<3>

PEG_D2R_C_N<2>

PEG_D2R_C_N<1>

PEG_D2R_C_P<12>

PEG_D2R_C_P<11>

PEG_D2R_C_P<10>

PEG_D2R_C_P<9>

PEG_D2R_C_P<8>

PEG_D2R_C_P<6>

PEG_D2R_C_P<5>

PEG_D2R_C_P<4>

PEG_D2R_C_P<3>

PEG_D2R_C_P<2>

PEG_D2R_C_P<1>

PEG_D2R_C_N<0>

PEG_D2R_C_P<0>

PEG_D2R_N<13>

PEG_D2R_N<15>

PEG_D2R_N<14>

PEG_D2R_P<15>

PEG_D2R_P<14>

PEG_D2R_P<12>

PEG_D2R_P<11>

PEG_D2R_N<11>

PEG_D2R_N<10>

PEG_D2R_N<9>

PEG_D2R_P<8>

PEG_D2R_N<7>

PEG_D2R_P<7>

PEG_D2R_P<6>

PEG_D2R_P<5>

PEG_D2R_P<4>

PEG_D2R_N<4>

PEG_D2R_P<3>

PEG_D2R_N<3>

PEG_D2R_P<2>

PEG_D2R_N<2>

PEG_D2R_P<1>

PEG_D2R_N<0>

PEG_D2R_P<0>

PEG_D2R_N<12>

PEG_D2R_N<1>

PEG_D2R_C_P<7>

PEG_D2R_N<6>

PEG_D2R_P<13>

PEG_D2R_P<10>

PEG_D2R_P<9>

PEG_D2R_N<8>

PEG_D2R_C_P<14>

PEG_D2R_N<5>

PEG_D2R_C_N<11>

PEG_D2R_C_N<8>

PEG_R2D_N<6>

PEG_R2D_C_P<7>

PEG_R2D_C_N<15>

PP1V25_S0_ISNS

TP_GPU_PEXTSTCLK_N

72

69

67

65

50

27

26

21

19

8

84

84 84

84

84 84

84

8

FBVTT

FBVDDQ

GND_SENSE

VDD_SENSE

VDD_LP

VDD

FBVDD

GND

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

- =PPVCORE_GPU

- =PP1V8_GPU_FBVDDQ

(NONE) BOM options provided by this page:

(NONE)

Signal aliases required by this page:

Power aliases required by this page:

Page Notes

???A @ ???MHz 1.8V GDDR3

NC

NC NC NC NC

NC

???A @ ???/???MHz Core/Mem Clk for VDD

1UF

402

10%

6.3V CERM

C8101

1

2

402

10%

1UF

6.3V CERM

C8100

1

2

NB8P-GS-W-A2

BGA

(7 OF 8)

OMIT

U8000

A12

A9 AA32 AD32 AG32 AK32 C32 F32 J32 M32 R32

A18 A21 A24 A27 A3 A30 A6

AA25

G22 H11 H12 H15 H18 H21 H22 L25 L26 M25

AA26

M26 R25 R26 V25 V26

AB25 AB26 G11 G12 G15 G18 G21

AA23

K12 K21 K22 K24 K9 L23 M23 T25 U25

AB23 H16 H17 J10 J23 J24 J9 K11

M21

K16

P16 P17 P19 R16 R17 T13 T14 T15 T18 T19

K17

U13 U14 U15 U18 U19 V16 V17 W13 W14 W16

N13

W17 W19 Y13 Y14 Y16 Y17 Y19 Y20

N14 N16 N17 N19 P13 P14

P20 T20 T23 U20 U23 W20

N20

NB8P-GS-W-A2

(8 OF 8)

BGA

OMIT

U8000

AE17

AG11

J16 J17 J2 J31 K10 K23 K29 K4 L27 L6

AB27

M12 M2 M31 N15 N18 N29 N4 P15 P18 P27

AB6

P6 R13 R14 R15 R18 R19 R2 R20 R31 T16

AC10

T17 T24 T29 T4 U16 U17 U24 U29 U8 V13

AC23

V14 V15 V18 V19 V2 V20 V31 W15 W18 W27

AC29

W6 Y15 Y18 Y29 Y4

AC4 AD16 AD17

AD2

AE27

AD31 AA12

AA2 AA21 AA31 AG13 AG14 AG15 AG19

AG2

AE6

AG22 AG31

AG8 AH24 AJ10 AJ13 AJ16 AJ17 AJ20 AJ23

AF11

AJ26 AJ29

AJ4

AJ7

AK2 AK28 AK31 AL10 AL11 AL14

AF26

AL19 AL22 AL25

AL3

AL6

AL9 AM10 AM13 AM16 AM17

AF29

AM20 AM23 AM26 AM29

B12

B15

B18

B21

B24

B27

AF4

B3

B30

B6 B9

C2 C31 D10 D13

D16 D17

AF7

D20 D23 D26 D29 D4 D7 F11 F14 F19 F2

AG10

F22 F25 F31 F8 G26 G29 G4 G7 H27 H6

402

10%

1UF

6.3V CERM

C8102

1

2

CERM 402

10V

20%

0.1UF

C8107

1

2

10V

0.1UF

402

CERM

20%

C8112

1

2

0.1UF

CERM 402

10V

20%

C8117

1

2

402

CERM

20%

0.1UF

10V

C8106

1

2

CERM 402

20% 10V

0.1UF

C8105

1

2

0.1UF

402

CERM

10V

20%

C8110

1

2

10V

0.1UF

CERM 402

20%

C8111

1

2

10V

0.1UF

402

20% CERM

C8116

1

2

0.1UF

CERM 402

10V

20%

C8115

1

2

20%

402

CERM

0.1UF

10V

C8104

1

2

0.1UF

402

CERM

10V

20%

C8109

1

2

0.1UF

CERM 402

10V

20%

C8114

1

2

402

CERM

10V

20%

0.1UF

C8113

1

2

0.1UF

CERM 402

10V

20%

C8108

1

2

402

20%

0.1UF

CERM

10V

C8103

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C8160

1

2

CERM-X5R

10%

6.3V

0.47UF

402

C8166

1

2

0.1UF

20% 10V

402

CERM

C8159

1

2

CERM

6.3V

20%

603

4.7UF

C8151

1

2

0.1UF

20% 10V

402

CERM

C8158

1

2

10V

20%

0.1UF

402

CERM

C8165

1

2

10V

20%

0.1UF

402

CERM

C8164

1

2

CERM

6.3V

20%

603

4.7UF

C8150

1

2

0.1UF

20% 10V

402

CERM

C8157

1

2

10V

20%

0.1UF

CERM

402

C8163

1

2

10V

20%

0.1UF

402

CERM

C8162

1

2

0.1UF

20% 10V

402

CERM

C8156

1

2

10V

20% CERM

402

0.1UF

C8122

1

2

10V

20%

402

0.1UF

CERM

C8121

1

2

0.1UF

10V

20% CERM

402

C8120

1

2

20%

0.1UF

10V CERM 402

C8119

1

2

0.1UF

10V

20%

402

CERM

C8118

1

2

0.47UF

6.3V

10%

CERM-X5R

402

C8161

1

2

CERM-X5R

10%

6.3V

0.47UF

402

C8167

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8169

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8168

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8171

1

2

402

0.47UF

6.3V

10%

CERM-X5R

C8170

1

2

SYNC_MASTER=M87_MLB

NV G84M Core/FB Power

68 92

051-7431

A.0.0

SYNC_DATE=08/28/2007

GPU_GND_SENSE

GPU_VDD_SENSE

PPVCORE_GPU

PP1V8_S0GPU_ISNS

78 77 74 71 70

75

69

49

65

75

8

50

73

7

8

BI

OUT

OUT OUT

OUT

OUT OUT

OUT

OUT OUT

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

BI BI

BI

OUT

FBAD20

FBAD22

FBAD1 FBAD2

FBAD18

FBAD0

FBAD3

FBAD5 FBAD6 FBAD7 FBAD8 FBAD9 FBAD10 FBAD11 FBAD12 FBAD13 FBAD14 FBAD15 FBAD16 FBAD17

FBAD19

FBAD21

FBAD23 FBAD24 FBAD25 FBAD26 FBAD27

FBAD29 FBAD30

FBAD32 FBAD33 FBAD34 FBAD35 FBAD36 FBAD37 FBAD38 FBAD39 FBAD40 FBAD41 FBAD42 FBAD43 FBAD44 FBAD45 FBAD46 FBAD47 FBAD48 FBAD49 FBAD50 FBAD51 FBAD52 FBAD53 FBAD54 FBAD55 FBAD56 FBAD57 FBAD58 FBAD59 FBAD60 FBAD61 FBAD62 FBAD63

FBA_PLLAVDD FBA_PLLGND

FBAD31

FBCAL_PD_VDDQ

FBCAL_PU_GND

FBAD28

FBAD4

FBADQS_WP0 FBADQS_WP1

FBADQS_WP3

FBADQS_WP2

FBADQS_WP6

FBADQS_WP5

FBADQS_WP4

FBADQS_WP7

FBA_DEBUG

FBADQS_RN2

FBADQS_RN1

FBADQS_RN0

FBADQS_RN4

FBADQS_RN3

FBADQS_RN5

FBADQS_RN7

FBADQS_RN6

FBA_CLK0

FBA_CLK0_L

FBA_CLK1_L

FBA_CLK1

FBADQM1

FBADQM0

FBADQM3

FBADQM2

FBADQM6

FBADQM5

FBADQM4

FBADQM7

FBA_CMD0

FBA_CMD2

FBA_CMD1

FBA_CMD5

FBA_CMD3 FBA_CMD4

FBA_CMD7

FBA_CMD6

FBA_CMD8

FBA_CMD10

FBA_CMD9

FBA_CMD13

FBA_CMD12

FBA_CMD11

FBA_CMD15

FBA_CMD14

FBA_CMD18

FBA_CMD17

FBA_CMD16

FBA_CMD20

FBA_CMD19

FBA_CMD23

FBA_CMD22

FBA_CMD21

FBA_CMD25

FBA_CMD24

FBA_CMD28

FBA_CMD26 FBA_CMD27

READ STROBE

WRITE STROBE

MEMORY INTERFACE A

OUT

OUT OUT

OUT

OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT

OUT

OUT OUT OUT

OUT OUT OUT OUT OUT OUT OUT OUT

OUT

FB_VREF

FBCAL_TERM_GND

FBC_PLLGND

FBC_PLLAVDD

FBCD63

FBCD62

FBCD61

FBCD60

FBCD59

FBCD58

FBCD57

FBCD56

FBCD55

FBCD53

FBCD51

FBCD50

FBCD49

FBCD48

FBCD47

FBCD46

FBCD45

FBCD44

FBCD43

FBCD41

FBCD40

FBCD39

FBCD38

FBCD37

FBCD36

FBCD35

FBCD34

FBCD33

FBCD32

FBCD31

FBCD30

FBCD29

FBCD28

FBCD27

FBCD26

FBCD25

FBCD24

FBCD23

FBCD22

FBCD21

FBCD20

FBCD19

FBCD18

FBCD17

FBCD16

FBCD15

FBCD11

FBCD9

FBCD8

FBCD7

FBCD6

FBCD5

FBCD4

FBCD3

FBCD2

FBCD1

FBCD10

FBCD42

FBCD0

FBCD54

FBCD52

FBCD13

FBCD12

FBCD14

FBCDQS_RN0 FBCDQS_RN1 FBCDQS_RN2 FBCDQS_RN3 FBCDQS_RN4 FBCDQS_RN5 FBCDQS_RN6 FBCDQS_RN7

FBCDQS_WP1 FBCDQS_WP2

FBCDQS_WP0

FBCDQS_WP4

FBCDQS_WP3

FBCDQS_WP6 FBCDQS_WP7

FBCDQS_WP5

FBC_DEBUG

FBCDQM7

FBC_CLK1

FBC_CLK0

FBC_CLK0_L

FBC_CLK1_L

FBCDQM0 FBCDQM1 FBCDQM2 FBCDQM3 FBCDQM4 FBCDQM5 FBCDQM6

FBC_CMD4

FBC_CMD3

FBC_CMD6

FBC_CMD5

FBC_CMD9

FBC_CMD8

FBC_CMD7

FBC_CMD11

FBC_CMD10

FBC_CMD14

FBC_CMD13

FBC_CMD12

FBC_CMD16

FBC_CMD15

FBC_CMD19

FBC_CMD18

FBC_CMD17

FBC_CMD21

FBC_CMD20

FBC_CMD22

FBC_CMD24

FBC_CMD23

FBC_CMD27

FBC_CMD26

FBC_CMD25

FBC_CMD28

FBC_CMD1

FBC_CMD0

FBC_CMD2

MEMORY INTERFACE B

WRITE STROBE

READ STROBE

OUT

BI BI BI BI BI BI BI BI

IN IN IN IN IN IN

IN

OUT

OUT OUT OUT OUT

OUT

BI

IN IN IN IN IN IN IN IN

OUT OUT OUT

OUT

OUT OUT OUT

D

SG

IN

OUT OUT

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

NC

- =PP1V2_GPU_FBPLLAVDD

(NONE)

- =PP1V8_GPU_FBIO Signal aliases required by this page:

BOM options provided by this page:

70 77 90

70 77

70 77 90

71 78 90

70 90

70 77 90

(3 OF 8)

OMIT

BGA

NB8P-GS-W-A2

U8000

P28 R28 Y27 AA27

P32 U27

T31 U32 W29 W30 T27 V28 V30 U31 R27 V29

P31

T30 W28 R29 R30 P29 U28 Y32 Y30 V32

U30 Y31 W32 W31 T32 V27 T28

AC27

G25 G24

N27 M27

N30 N32 L31 L30 J30 L32 H30 K30 H31 F30

N28

H32 E31 D30 E30 H28 H29 E29 J27 F27 E27

L29

E28

F28 AD29 AE29 AD28 AC28 AB29 AA30

Y28 AB30

K27

AM30 AF30 AJ31 AJ30 AJ32 AK29 AM31 AL30 AE32 AE30

K28

AE31 AD30 AC31 AC32 AB32 AB31 AG27 AF28 AH28 AG28

J29

AG29 AD27 AF27 AE28

J28

P30

N31

M29 M30 G30 F29 AA29 AK30 AC30 AG30

M28 K32 G31 G27 AA28 AL31 AF31 AH29

L28 K31 G32 G28 AB28 AL32 AF32 AH30

K26 H26

20%

0.1UF

10V CERM 402

C8201

1

2

70 77 90

71 78 90

71 78

71 90

71 78 90

5% 1/16W MF-LF 402

10K

R8200

1

2

71 78 90

5% 1/16W MF-LF 402

10K

R8250

1

2

40.2

402

1%

MF-LF

1/16W

R8292

12

1%

MF-LF

402

1/16W

24.9

R8291

1

2

OMIT

(4 OF 8)

BGA

NB8P-GS-W-A2

U8000

E32

E13 F13 F18 E17

C13 A16

C15 B16 F17 C19 D15 C17 A17 C16 D14 F16

A13

C14 C18 E14 B13 E15 F15 A20 C20 A15

B17 B20 A19 B19 B14 E16 A14

F12

G10

G9

J26

B7 A7

D12

D9 E12 D11

E8

D8

E7

F7

D6

D5

C7

D3

E4

C3

B4 C10 B10

C8 A10 C11 C12

A2

A11 B11 B28 C27 C26 B26 C30 B31 C29 A31

B2

D28 D27 F26 D24 E23 E26 E24 F23 B23 A23

C4

C25 C23 A22 C22 C21 B22 E22 D22 D21 E21

A5

E18 D19 D18 E19

B5

F9 F10

A4 E11 F5 C9 C28 F24 C24 E20

C6 E9 E6 A8 B29 E25 A25 F21

C5 E10 E5 B8 A29 D25 B25 F20

16V

0.1uF

10% X5R

402

C8296

1

2

1.07K

MF-LF

402

1/16W

1%

R8295

1

2

0402

FERR-220-OHM

L8200

1 2

402

1%

MF-LF

1/16W

45.3

R8290

12

4.7UF

20%

603

CERM

6.3V

C8200

1

2

402

5% 1/16W MF-LF

10K

R8201

1

2

5% 1/16W MF-LF 402

10K

R8251

1

2

70 77 90

71 78 90

SSM6N15FE

SOT563

Q8295

6

2

1

402

MF-LF

1/16W

1%

2.49K

R8296

1

2

402

MF-LF

1/16W

1%

1.02K

R8297

1

2

70 71 72 73

70 77 90 71 78 90

70

73

71

73

NV G84M Frame Buffer I/F

SYNC_DATE=08/28/2007

69 92

051-7431

A.0.0

SYNC_MASTER=M87_MLB

FB_B_DQ<59>

FB_VREF_UNTERM

FB_A_WDQS<4>

FB_B_DQ<63>

FB_B_DQ<60>

FB_B_DQ<55>

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

GPU_FB_VREF_UNTERM_L

FB_A_DRAM_RST

GPU_FB_VREF

PP1V8_S0GPU_ISNS

FB_B_WDQS<7>

FB_B_DQ<32>

FB_B_DQ<31>

NC_FBC_CMD28

FB_B_WDQS<6>

FB_B_WDQS<1> FB_B_WDQS<2>

FB_B_WDQS<4>

FB_B_WDQS<3>

FB_B_WDQS<5>

FB_B_RDQS<5> FB_B_RDQS<6> FB_B_RDQS<7>

FB_B_WDQS<0>

FB_B_RDQS<0> FB_B_RDQS<1> FB_B_RDQS<2> FB_B_RDQS<3> FB_B_RDQS<4>

FB_B_DQM_L<4>

FB_B_DQM_L<7>

FB_B_DQM_L<6>

FB_B_DQM_L<5>

FB_B_DQM_L<3>

FB_B_CLK_N<1>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_DQM_L<0>

FB_B_CLK_N<0>

FB_B_CLK_P<0>

FB_B_CLK_P<1>

TP_FBC_DEBUG

PP1V8_S0GPU_ISNS

FB_A_DQ<35>

FB_A_CLK_N<1>

FB_A_CLK_P<1>

NC_FBA_CMD28

FB_A_CLK_N<0>

FB_A_CLK_P<0>

FB_A_WDQS<7>

FB_A_WDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<3>

FB_A_WDQS<2>

FB_A_WDQS<1>

FB_A_WDQS<0>

FB_A_RDQS<7>

FB_A_RDQS<6>

FB_A_RDQS<5>

FB_A_RDQS<4>

FB_A_RDQS<3>

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_DQM_L<7>

FB_A_DQM_L<6>

FB_A_DQM_L<5>

FB_A_DQM_L<4>

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_DQM_L<1>

FB_A_DQM_L<0>

FBCAL_PU_GND

TP_FBA_DEBUG

FBCAL_PD_VDDQ

FB_A_DQ<5>

FB_A_DQ<2>

FB_A_DQ<1>

FB_A_DQ<63>

FB_A_DQ<54> FB_A_DQ<55> FB_A_DQ<56> FB_A_DQ<57> FB_A_DQ<58> FB_A_DQ<59> FB_A_DQ<60> FB_A_DQ<61> FB_A_DQ<62>

FB_A_DQ<44> FB_A_DQ<45> FB_A_DQ<46> FB_A_DQ<47> FB_A_DQ<48> FB_A_DQ<49> FB_A_DQ<50> FB_A_DQ<51> FB_A_DQ<52> FB_A_DQ<53>

FB_A_DQ<34>

FB_A_DQ<36> FB_A_DQ<37> FB_A_DQ<38> FB_A_DQ<39> FB_A_DQ<40> FB_A_DQ<41> FB_A_DQ<42> FB_A_DQ<43>

FB_A_DQ<33>

FB_A_DQ<25> FB_A_DQ<26>

FB_A_DQ<28> FB_A_DQ<29> FB_A_DQ<30> FB_A_DQ<31> FB_A_DQ<32>

FB_A_DQ<13> FB_A_DQ<14> FB_A_DQ<15> FB_A_DQ<16> FB_A_DQ<17> FB_A_DQ<18> FB_A_DQ<19> FB_A_DQ<20> FB_A_DQ<21>

FB_A_DQ<4>

FB_A_DQ<7>

FB_A_DQ<10> FB_A_DQ<11> FB_A_DQ<12>

FB_A_DQ<0>

FB_B_DQ<62>

FB_B_DQ<56>

FB_B_DQ<52>

FB_B_DQ<14>

FB_B_DQ<12> FB_B_DQ<13>

FB_B_DQ<54>

FB_B_UMA<2> FB_B_UMA<4>

FB_B_CS1_L

FB_B_DQ<0>

FB_B_BA<1>

FB_B_DQ<42>

FB_B_LMA<4>

FB_B_DQ<10>

FB_B_DQ<1> FB_B_DQ<2> FB_B_DQ<3> FB_B_DQ<4> FB_B_DQ<5> FB_B_DQ<6> FB_B_DQ<7> FB_B_DQ<8> FB_B_DQ<9>

FB_B_DQ<11>

FB_B_DQ<15> FB_B_DQ<16>

FB_B_DQ<19>

FB_B_DQ<22> FB_B_DQ<23> FB_B_DQ<24> FB_B_DQ<25> FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<28> FB_B_DQ<29> FB_B_DQ<30>

FB_B_DQ<33> FB_B_DQ<34> FB_B_DQ<35> FB_B_DQ<36> FB_B_DQ<37> FB_B_DQ<38> FB_B_DQ<39> FB_B_DQ<40> FB_B_DQ<41>

FB_B_DQ<44> FB_B_DQ<45> FB_B_DQ<46>

FB_B_DQ<49> FB_B_DQ<50>

FB_B_DQ<57> FB_B_DQ<58>

FB_B_DQ<61>

FB_B_RAS_L FB_B_LMA<5>

FB_B_MA<11> FB_B_CAS_L FB_B_WE_L

FB_B_UMA<5>

FB_B_MA<7> FB_B_MA<10>

FB_B_MA<6> FB_B_LMA<2> FB_B_MA<8> FB_B_LMA<3> FB_B_MA<1>

FB_A_MA<9>

FB_A_LMA<2>

FB_A_MA<0>

FB_A_UMA<3>

FB_A_RAS_L FB_A_LMA<5> FB_A_BA<1>

FB_B_DQ<17> FB_B_DQ<18>

FB_B_DQ<20> FB_B_DQ<21>

FB_A_UMA<4>

FB_B_BA<0>

FB_B_UMA<3>

FB_B_CS0_L

FB_A_UMA<2>

FB_B_DQ<43>

FB_B_DQ<51>

FB_A_LMA<4>

FB_A_MA<7>

FB_A_WE_L

FBCAL_TERM_GND

FB_B_DQ<53>

FB_A_LMA<3>

FB_A_MA<8>

FB_A_MA<1>

FB_A_MA<6>

FB_B_DQ<47> FB_B_DQ<48>

FB_B_MA<9>

FB_B_MA<0>

FB_B_CKE

FB_B_DRAM_RST

FB_A_DQ<22>

FB_A_DQ<24>

FB_A_DQ<27>

FB_A_DQ<23>

FB_A_DQ<9>

FB_A_DQ<6>

FB_A_DQ<3>

VOLTAGE=1.2V

PP1V2_GPU_FBA_PLL_F

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm

PP1V25_S0_ISNS

FB_A_CS1_L FB_A_CS0_L FB_A_MA<11> FB_A_CAS_L

FB_A_BA<0> FB_A_UMA<5>

FB_A_DQ<8>

FB_A_BA<2> FB_B_BA<2>

FB_A_CKE

FB_A_MA<10>

FB_A_MA<12>

NC_FBA_MA<13>

FB_B_MA<12>

NC_FBB_MA<13>

78

77

72

74

67

71

65

70

50

69

27

68

26

65

21

50

19

8

73

8

73

8

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

BI BI BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

D

SG

D

SG

D

SG

D

SG

IN

ININ

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(For 32Mx32 support)

U8400.J12 U8400.J12

U8400.J1

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

Connect to designated pin, then GND

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

(For 32Mx32 support)

U8400.J1

Connect to designated pin, then GND

1/16W

1%

402

MF-LF

2.37K

R8430

1

2

402

1/16W

1%

MF-LF

5.49K

R8431

1

2

0.1uF

X5R 402

10% 16V

C8403

1

2

0.1uF

402

X5R

10% 16V

C8402

1

2

0.1uF

X5R 402

10% 16V

C8404

1

2

402

10% 16V X5R

0.1uF

C8401

1

2

X5R

10% 402

16V

0.1uF

C8422

1

2

402

X5R

16V

10%

0.1uF

C8423

1

2

402

0.1uF

16V

10% X5R

C8424

1

2

0.1uF

X5R 402

10% 16V

C8425

1

2

0.1uF

X5R 402

10% 16V

C8426

1

2

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

U8400

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

OMIT

CRITICAL

FBGA

U8400

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

100

1/16W

5%

402

MF-LF

R8449

1

2

1/16W

1%

402

MF-LF

243

R8448

1

2

VRAM4

121

MF-LF 402

1% 1/16W

R8445

1

2

121

MF-LF

402

1%

1/16W

R8446

1

2

0.1uF

16V

10% X5R

402

C8421

1

2

0.1uF

X5R 402

10% 16V

C8415

1

2

402

0.1uF

X5R

16V

10%

C8410

1

2

1/16W

402

MF-LF

1K

5%

R8440

1

2

121

1% MF-LF

402

1/16W

R8447

1

2

VRAM4

1/16W

402

MF-LF

121

1%

R8444

1

2

VRAM4

MF-LF

1%

121

402

1/16W

R8443

1

2

VRAM4

1/16W

402

MF-LF

121

1%

R8442

1

2

69 77 90

69 70 77 90

69 70 90

69 77 90

69 70 77 90

69 77 90

69 70 77 90

69 77 90

69 70 77 90

69 70 90

69 70 77 90

69 77 90

69 70 77 90

69 77 90

69 70 77 90

69 77 90

69 70 77 90

5%

1K

1/16W

402

MF-LF

R8490

1

2

VRAM4

1/16W

402

MF-LF

121

1%

R8492

1

2

16V 402

X5R

0.1uF

10%

C8471

1

2

16V

10% 402

X5R

0.1uF

C8472

1

2

243

MF-LF

402

1%

1/16W

R8498

1

2

100

MF-LF 402

5% 1/16W

R8499

1

2

CRITICAL

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

OMIT

U8450

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

VRAM4

1%

121

MF-LF 402

1/16W

R8493

1

2

VRAM4

121

1/16W

1%

402

MF-LF

R8495

1

2

MF-LF

1/16W

VRAM4

402

121

1%

R8494

1

2

121

1/16W 402

MF-LF

1%

R8497

1

2

MF-LF

121

1/16W

1%

402

R8496

1

2

16V

10% 402

X5R

0.1uF

C8473

1

2

16V

10% 402

X5R

0.1uF

C8474

1

2

16V

10% 402

X5R

0.1uF

C8475

1

2

CRITICAL

OMIT

K4J52324QC-BC20

FBGA

16MX32-GDDR3-500MHZ

U8450

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

16V

10% 402

X5R

0.1uF

C8476

1

2

X5R

16V

10%

402

0.1uF

C8451

1

2

16V

10%

0.1uF

402

X5R

C8452

1

2

16V

10%

402

X5R

0.1uF

C8460

1

2

16V

10%

402

X5R

0.1uF

C8453

1

2

16V

10%

402

X5R

0.1uF

C8465

1

2

16V

10%

402

X5R

0.1uF

C8454

1

2

69 77 90

20% X5R

603

6.3V

10UF

C8400

1

2

6.3V

10UF

603

X5R

20%

C8420

1

2

10UF

603

X5R

6.3V

20%

C8450

1

2

10UF

603

X5R

6.3V

20%

C8470

1

2

CERM

0.01UF

402

10% 16V

C8446

1

2

402

16V

10%

0.01UF

CERM

C8496

1

2

1/16W MF-LF

402

1%

2.21K

R8432

1

2

402

CERM

16V

10%

0.01uF

C8481

1

2

1/16W

1%

MF-LF

402

2.21K

R8482

1

2

2.37K

MF-LF

402

1%

1/16W

R8480

1

2

5.49K

1%

MF-LF

1/16W

402

R8481

1

2

69 70 71 72 73

SSM6N15FE

SOT563

Q8400

6

2

1

SSM6N15FE

SOT563

Q8450

6

2

1

1/16W

2.21K

1%

MF-LF

402

R8435

1

2

1/16W

1%

402

MF-LF

2.37K

R8433

1

2

5.49K

1/16W

402

1%

MF-LF

R8434

1

2

10% 16V

0.01UF

402

CERM

C8431

1

2

SOT563

SSM6N15FE

Q8400

3

5

4

16V

0.01uF

CERM

10% 402

C8482

1

2

2.21K

1/16W

1%

MF-LF

402

R8485

1

2

2.37K

MF-LF

402

1%

1/16W

R8483

1

2

5.49K

MF-LF

1%

1/16W

402

R8484

1

2

SOT563

SSM6N15FE

Q8450

3

5

4

69 70

69 70 77 69 70 77

69 70

10%

0.01UF

402

CERM

16V

C8432

1

2

GDDR3 Frame Buffer A (Top)

A.0.0

92

051-7431

70

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

VOLTAGE=0.9V

FB_A_CLK0_TERM

FB_A0_VREF_UNTERM_L

PP1V8_S0GPU_ISNS

FB_A0_VREF

FB_VREF_UNTERM

FB_A2_VREF_UNTERM_L

FB_A_MA<9> FB_A_MA<10>

FB_A_CLK_P<1>

FB_A_CS0_L

FB_A_DQ<55>

FB_A_CLK_N<1>

FB_A_CKE

FB_A_MA<11>

FB_A_MA<8>

FB_A_MA<7>

FB_A_MA<6>

FB_A_UMA<5>

FB_A_UMA<2>

FB_A_MA<0>

FB_A_MA<12> FB_A_CS1_L

FB_A0_ZQ

FB_A0_SEN FB_A1_SEN

FB_A1_ZQ

PP1V8_S0GPU_ISNS

FB_A1_VREF_UNTERM_L

FB_A1_VREF

PP1V8_S0GPU_ISNS

FB_A3_VREFFB_A2_VREF

FB_A_DQM_L<0>

FB_A_UMA<3>

FB_A_MA<1>

FB_A_MA<7>

FB_A_MA<9>

FB_A_DRAM_RST

FB_A_DQ<32> FB_A_DQ<36>

FB_A_DQ<53>

FB_A_DQ<49>

FB_A_DQ<51>

FB_A_DQ<52>

FB_A_WDQS<0>

FB_A_WDQS<2>

PP1V8_S0GPU_ISNS

FB_A_WE_L

FB_A_DQ<42>

FB_A_DQ<45>

FB_A_DQ<46>

FB_A_DQ<47>

FB_A_DQ<40>

FB_A_DQ<60>

FB_A_DQ<63>

FB_A_DQ<57>

FB_A_DQ<58>

FB_A_DQ<56>

FB_A_RDQS<3>

FB_A_DQ<4>

FB_A_DQ<1>

FB_A_DQ<2>

FB_A_DQ<3>

FB_A_DQ<5>

FB_A_DQ<8> FB_A_DQ<9>

FB_A_DQ<11> FB_A_DQ<12>

FB_A_DQ<14>

FB_A_DQ<18> FB_A_DQ<16> FB_A_DQ<20> FB_A_DQ<21>

FB_A_DQ<25> FB_A_DQ<27>

FB_A_DQ<24>

FB_A_DQ<26>

FB_A_DQ<31>

FB_A_DQ<29> FB_A_DQ<30>

FB_A_DQM_L<3>

FB_A_DQM_L<2>

FB_A_MA<10>

FB_A_DQ<62>

FB_A_DQ<59>

FB_A_DQ<61>

FB_A_DQ<44> FB_A_DQ<41> FB_A_DQ<43> FB_A_DQ<50> FB_A_DQ<48>

FB_A_DQ<34>

FB_A_DQ<54>

FB_A_DQ<33> FB_A_DQ<35>

FB_A_DQ<37> FB_A_DQ<39> FB_A_DQ<38>

FB_A_RDQS<5>

FB_A_RDQS<7>

FB_A_DRAM_RST

FB_A_MA<1>

FB_A_WDQS<6>

FB_A_WDQS<5>

FB_A_WDQS<7>

FB_A_DQM_L<4>

FB_A_DQM_L<6>

FB_A_DQM_L<5>

FB_A_DQM_L<7>

FB_A_MA<11>

FB_A_MA<8>

FB_A_RAS_L

FB_A_CAS_L

FB_A_DQ<0>

FB_A_DQ<28>

FB_A_LMA<2>

FB_A1_MF

FB_A_UMA<4>

FB_A_RDQS<4>

FB_A_RDQS<6>

FB_A_MA<0>

FB_A0_MF

FB_A_RDQS<2>

FB_A_RDQS<1>

FB_A_RDQS<0>

FB_A_MA<6>

FB_A_LMA<5>

FB_A_LMA<3>

FB_A_DQ<6>

FB_A_DQ<23>

FB_A_DQ<22>

FB_A_DQ<19>

FB_A_DQ<17>

FB_A_DQ<15>

FB_A_DQ<10>

FB_A_DQ<7>

FB_A_DQM_L<1>

FB_A3_VREF_UNTERM_L

VOLTAGE=0.9V

FB_A_CLK1_TERM

FB_VREF_UNTERM

FB_A_BA<2>

FB_A_WDQS<3>

FB_A_WDQS<1>

FB_A_DQ<13>

FB_A_LMA<4>

FB_A_BA<2>

FB_A_BA<1>

FB_A_BA<0>

FB_A_WDQS<4>

FB_A_BA<1>

FB_A_BA<0>

FB_A_RAS_L

FB_A_CAS_L

FB_A_WE_L

FB_A_CS0_L

FB_A_CLK_N<0>

FB_A_CLK_P<0>

FB_A_CKE

78

77

74

71

70

69

68

65

50

8

77

8

77

8

77 77

8

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN

BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CS*

CK*

A9

A6 A7

A3 A4

A2

A0 A1

CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

A10

CKE

MFHIGH

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

BI BI BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

D

SG

D

SG

D

SG

D

SG

IN IN

ININ

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Connect to designated pin, then GND

U8500.J12

U8500.J1

U8500.J12

U8500.J1

Connect to designated pin, then GND

- =PP1V8_S0_FB_VDDQ

- =PP1V8_S0_FB_VDD

(NONE)

Signal aliases required by this page:

BOM options provided by this page:

Power aliases required by this page:

Page Notes

(For 32Mx32 support)(For 32Mx32 support)

16V

10% X5R

0.1uF

402

C8503

1

2

16V

10%

402

X5R

0.1uF

C8502

1

2

0.1uF

16V

10%

402

X5R

C8504

1

2

0.1uF

402

16V

10% X5R

C8501

1

2

0.1uF

16V

10% 402

X5R

C8522

1

2

16V

10% 402

X5R

0.1uF

C8523

1

2

16V

10% 402

X5R

0.1uF

C8524

1

2

16V

10% 402

X5R

0.1uF

C8525

1

2

10% X5R

0.1uF

402

16V

C8526

1

2

OMIT

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

CRITICAL

U8500

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

U8500

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

1/16W

5%

402

MF-LF

100

R8549

1

2

1/16W

1%

402

MF-LF

243

R8548

1

2

16V

10% X5R

0.1uF

402

C8521

1

2

16V

10%

402

X5R

0.1uF

C8515

1

2

16V

10%

402

X5R

0.1uF

C8510

1

2

69 78 90

69 71 78 90

69 71 90

69 78 90

69 71 78 90

69 78 90

69 71 78 90

69 78 90

69 71 78 90

69 78 90

69 71 78 90

69 71 90

69 71 78 90

69 78 90

69 71 78 90

X5R 402

10% 16V

0.1uF

C8571

1

2

X5R 402

10% 16V

0.1uF

C8572

1

2

1/16W

402

MF-LF

243

1%

R8598

1

2

1/16W 402

MF-LF

5%

100

R8599

1

2

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

OMIT

CRITICAL

FBGA

U8550

K9

H11

K11

L9

K10

M9 K4 H2 K3 L4 K2 M4

G9 G4 H3

F9

J11 J10

H9

F4

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H10

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H4

A4

10% 402

X5R

16V

0.1uF

C8573

1

2

16V

10% 402

X5R

0.1uF

C8574

1

2

X5R 402

10% 16V

0.1uF

C8575

1

2

K4J52324QC-BC20

OMIT

CRITICAL

FBGA

16MX32-GDDR3-500MHZ

U8550

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

X5R 402

10% 16V

0.1uF

C8576

1

2

0.1uF

X5R 402

10% 16V

C8551

1

2

0.1uF

X5R 402

10% 16V

C8552

1

2

16V

10%

402

X5R

0.1uF

C8560

1

2

16V

10%

402

X5R

0.1uF

C8553

1

2

16V

10%

402

X5R

0.1uF

C8565

1

2

0.1uF

X5R 402

10% 16V

C8554

1

2

69 78 90

10UF

603

X5R

6.3V

20%

C8500

1

2

10UF

603

X5R

6.3V

20%

C8520

1

2

10UF

603

X5R

6.3V

20%

C8550

1

2

10UF

603

X5R

6.3V

20%

C8570

1

2

121

1%

402

1/16W MF-LF

R8546

1

2

121

1% MF-LF

402

1/16W

R8547

1

2

121

VRAM4

1/16W

1%

MF-LF

402

R8544

1

2

VRAM4

MF-LF 402

1% 1/16W

121

R8545

1

2

VRAM4

402

MF-LF

121

1%

1/16W

R8542

1

2

402

5%

MF-LF

1/16W

1K

R8540

1

2

VRAM4

MF-LF

1%

121

402

1/16W

R8543

1

2

121

MF-LF

402

1%

1/16W

R8596

1

2

121

1% MF-LF

402

1/16W

R8597

1

2

VRAM4

MF-LF 402

121

1% 1/16W

R8595

1

2

VRAM4

1%

121

MF-LF

402

1/16W

R8594

1

2

VRAM4

1%

121

MF-LF

402

1/16W

R8592

1

2

VRAM4

1/16W 402

MF-LF

1%

121

R8593

1

2

MF-LF

402

1/16W

1K

5%

R8590

1

2

16V

10%

402

0.01UF

CERM

C8596

1

2

0.01UF

CERM

402

10% 16V

C8546

1

2

5.49K

MF-LF

1%

1/16W

402

R8531

1

2

2.21K

1/16W MF-LF

402

1%

R8532

1

2

402

10% CERM

0.01uF

16V

C8531

1

2

2.37K

MF-LF

402

1%

1/16W

R8530

1

2

402

1/16W

1%

MF-LF

5.49K

R8581

1

2

402

2.21K

MF-LF

1%

1/16W

R8582

1

2

1/16W

1%

402

MF-LF

2.37K

R8580

1

2

10% 402

CERM

0.01uF

16V

C8581

1

2

69 70 71 72 73

SSM6N15FE

SOT563

Q8500

6

2

1

SOT563

SSM6N15FE

Q8550

6

2

1

0.01uF

402

10% CERM

16V

C8532

1

2

2.21K

1/16W MF-LF

402

1%

R8535

1

2

1/16W

1%

402

2.37K

MF-LF

R8533

1

2

402

MF-LF

1/16W

1%

5.49K

R8534

1

2

SOT563

SSM6N15FE

Q8500

3

5

4

16V

0.01uF

CERM 402

10%

C8582

1

2

402

2.21K

MF-LF

1%

1/16W

R8585

1

2

2.37K

MF-LF

402

1%

1/16W

R8583

1

2

402

1/16W

1%

MF-LF

5.49K

R8584

1

2

SSM6N15FE

SOT563

Q8550

3

5

4

69 71 78 69 71 78

69 71 69 71

GDDR3 Frame Buffer B (Top)

71 92

A.0.0

051-7431

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

FB_B_MA<12> FB_B_CS1_L

FB_B0_SEN

FB_B0_ZQ

FB_B_MA<12> FB_B_CS1_L

FB_B1_SEN

FB_B1_ZQ

FB_B_WDQS<3> FB_B_WDQS<0>

PP1V8_S0GPU_ISNS

FB_B_LMA<4>

FB_B_LMA<2> FB_B_LMA<3>

FB_B1_VREF_UNTERM_L

FB_B1_VREF

PP1V8_S0GPU_ISNS

FB_B3_VREF

FB_B0_VREF_UNTERM_L

PP1V8_S0GPU_ISNS

FB_B0_VREF

FB_B2_VREF

FB_VREF_UNTERM

FB_B2_VREF_UNTERM_L

FB_VREF_UNTERM

FB_B3_VREF_UNTERM_L

VOLTAGE=0.9V

FB_B_CLK0_TERM

PP1V8_S0GPU_ISNS

FB_B1_MFFB_B0_MF

FB_B_RAS_L

FB_B_DRAM_RST FB_B_RDQS<2>

FB_B_UMA<2>

FB_B_LMA<5>

FB_B_RAS_L

FB_B_CAS_L

FB_B_WE_L

FB_B_CS0_L

FB_B_CKE

FB_B_CAS_L

FB_B_DQ<35>

FB_B_RDQS<5>

FB_B_BA<2>

FB_B_DQM_L<6>

FB_B_DQM_L<7>

FB_B_DRAM_RST FB_B_RDQS<6>

FB_B_DQ<57>

FB_B_DQ<62>

FB_B_DQ<59>

FB_B_DQ<61>

FB_B_DQ<33> FB_B_DQ<63>

FB_B_DQ<32>

FB_B_DQ<34>

FB_B_DQ<38>

FB_B_DQ<37>

FB_B_DQ<47>

FB_B_DQ<46>

FB_B_DQ<43>

FB_B_DQ<41>

FB_B_DQ<42>

FB_B_DQ<52>

FB_B_DQ<54>

FB_B_DQ<55>

FB_B_DQ<51>

FB_B_DQ<48>

FB_B_DQ<49> FB_B_DQ<50>

FB_B_MA<8>

FB_B_DQM_L<2> FB_B_DQM_L<1>

FB_B_MA<0>

FB_B_MA<6>

FB_B_DQ<3>

FB_B_DQ<7>

FB_B_DQ<0>

FB_B_DQ<6>

FB_B_DQ<1>

FB_B_DQ<26> FB_B_DQ<27> FB_B_DQ<2>

FB_B_DQ<30>

FB_B_DQ<31>

FB_B_DQ<29>

FB_B_DQ<28>

FB_B_DQ<24>

FB_B_DQ<11>

FB_B_DQ<9>

FB_B_DQ<12>

FB_B_DQ<22> FB_B_DQ<8>

FB_B_DQ<21>

FB_B_DQ<20>

FB_B_DQ<23>

FB_B_DQ<56> FB_B_DQ<60>

FB_B_MA<1>

FB_B_DQ<45>

FB_B_DQ<58>

FB_B_RDQS<1> FB_B_RDQS<3>

FB_B_DQM_L<3>

FB_B_DQ<18>

FB_B_DQ<19> FB_B_DQ<16>

FB_B_DQ<25>

FB_B_DQ<4> FB_B_DQ<5>

FB_B_RDQS<4>

FB_B_DQ<17>

FB_B_MA<11>

FB_B_WDQS<2>

FB_B_WE_L

FB_B_CS0_L

FB_B_CLK_N<0>

FB_B_CKE

FB_B_MA<10>

FB_B_MA<9>

FB_B_MA<7>

FB_B_MA<1>

FB_B_DQ<39>

FB_B_DQ<36>

FB_B_DQ<44>

FB_B_DQ<40>

FB_B_CLK_N<1>

FB_B_CLK_P<1>

FB_B_MA<6>

FB_B_UMA<3> FB_B_UMA<4> FB_B_UMA<5>

FB_B_MA<7> FB_B_MA<8> FB_B_MA<9> FB_B_MA<10> FB_B_MA<11>

FB_B_DQ<53>

FB_B_DQM_L<5> FB_B_DQM_L<4>

FB_B_MA<0>

FB_B_CLK_P<0>

VOLTAGE=0.9V

FB_B_CLK1_TERM

FB_B_DQM_L<0>

FB_B_BA<2>

FB_B_BA<1>

FB_B_BA<0>

FB_B_WDQS<1>

FB_B_RDQS<0>

FB_B_BA<1>

FB_B_BA<0>

FB_B_WDQS<7>

FB_B_WDQS<4>

FB_B_WDQS<5>

FB_B_WDQS<6>

FB_B_RDQS<7>

FB_B_DQ<15>

FB_B_DQ<14>

FB_B_DQ<13>

FB_B_DQ<10>

78

78 78

78

77

74

71

71 70

70 70

70 69

69 69

69 68

68 68

68 65

65 65

65 50

50 50

50

8

78

8

78

8

78

8

VDD33_1 VDD33_2 VDD33_3 VDD33_4 VDD33_5 VDD33_6 VDD33_7 VDD33_8 VDD33_9 VDD33_10 VDD33_11 VDD33_12 VDD33_13

ROM_SCLK ROM_SI ROM_SO

TESTMODE SWAPRDY_A

MIOA_VDDQ_1 MIOA_VDDQ_2 MIOA_VDDQ_3 MIOA_VDDQ_4 MIOA_VDDQ_5 MIOB_VDDQ_1 MIOB_VDDQ_2 MIOB_VDDQ_3 MIOB_VDDQ_4 MIOB_VDDQ_5

MIOA_VREF MIOB_VREF

MIOACAL_PD_VDDQ MIOACAL_PU_GND

MIOBCAL_PD_VDDQ MIOBCAL_PU_GND

PLLVDD PLLGND

H_PLLVDD

VID_PLLVDD

XTALIN XTALOUT

XTALOUTBUFF

XTALSSIN

GPIO0 GPIO1 GPIO2 GPIO3

GPIO9

GPIO11

SPDIF

STEREO

JTAG_TCK JTAG_TDI JTAG_TDO JTAG_TMS

MIOA_CLKOUT

MIOA_CTL3

MIOA_DE

MIOAD0 MIOAD1 MIOAD2 MIOAD3 MIOAD4 MIOAD5 MIOAD6 MIOAD7 MIOAD8

MIOAD9 MIOAD10 MIOAD11

MIOA_HSYNC MIOA_VSYNC

MIOB_CLKIN

MIOB_CLKOUT

MIOB_CTL3

MIOB_DE

MIOBD0

MIOBD1

MIOBD2

MIOBD3

MIOBD4

MIOBD5

MIOBD6

MIOBD7

MIOBD8

MIOBD9 MIOBD10 MIOBD11

MIOB_HSYNC MIOB_VSYNC

THERMDP THERMDN

GPIO4 GPIO5 GPIO6 GPIO7 GPIO8

GPIO10

GPIO12

GPIO13

GPIO14

BUFRST_L

JTAG_TRST_L

MIOA_CLKOUT_L

MIOB_CLKOUT_L

ROMCS_L

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

BOM options provided by this page:

(NONE)

Signal aliases required by this page:

40mA

(IPD)

(NONE)

- =PP1V2_GPU_VID_PLLVDD

- =PP1V2_GPU_H_PLLVDD

- =PP1V2_GPU_PLLVDD

- =PP3V3_GPI_MIO

- =PP3V3_GPU_VDD33

Power aliases required by this page:

40mA

Typically <??mA

BGA

(6 OF 8)

OMIT

NB8P-GS-W-A2

U8000

F3

K3 H1

H5 F4 E3 U3 U4

K5 G5 E2 J5 G6 K6 E1 D2

G23

AJ11 AK12 AL12 AK11 AL13

R4 P4 P3 P1

R3

M7 M8 R8 T8 U9

L2

R1

L1 L3

P2 N2

L4 L5

N1 N3 M1 M3 P5 N6 N5 M4

AE4 AD4 AD5 AD3 AD1

AF3

AA8 AB7 AB8 AC6 AC7

Y2

AE3

Y1 Y3

AC3 AC1

AB4 AA5

AC2 AB2 AB1 AA1 AB3 AA3 AC5 AB5

U10

T9

AA7

W2

AA6

AA4

J6 T3

M6

H2

J1

K1

AC11

L10

L7 L8

M10

AC12 AC24 AD24 AE11 AE12

H7 J7 K7

T10

U1 U2

T2

T1

10K

1/16W MF-LF

5%

402

R8696

1 2

100K

402

1/16W

5%

MF-LF

R8695

1

2

402

0.47UF

10%

6.3V CERM-X5R

C8601

1

2

402

0.47UF

10%

6.3V CERM-X5R

C8602

1

2

0.1uF

X5R

16V 402

10%

C8636

1

2

4.7UF

603

CERM

6.3V

20%

C8635

1

2

FERR-220-OHM

0402

L8635

1 2

0402

FERR-220-OHM

L8640

1 2

0.1uF

10% 16V X5R 402

C8617

1

2

MF-LF

5%

1/16W

402

10K

R8616

1

2

5%

MF-LF

402

1/16W

10K

R8617

1

2

49.9

1% 1/16W MF-LF

402

R8620

1

2

1/16W MF-LF

49.9

1%

402

R8622

1

2

49.9

1% 1/16W MF-LF 402

R8621

1

2

402

X5R

16V

10%

0.1uF

C8619

1

2

402

MF-LF

1/16W

5%

10K

R8618

1

2

1/16W MF-LF 402

5%

10K

R8619

1

2

6.3V

10%

1UF

CERM

402

C8611

1

2

6.3V 402

10%

1UF

CERM

C8610

1

2

49.9

402

MF-LF

1/16W

1%

R8623

1

2

10%

402

16V X5R

0.1uF

C8631

1

2

20%

6.3V CERM

603

4.7UF

C8630

1

2

FERR-220-OHM

0402

L8630

1 2

20%

6.3V CERM

603

4.7UF

C8633

1

2

0.1uF

X5R

16V 402

10%

C8641

1

2

4.7UF

603

CERM

6.3V

20%

C8640

1

2

20%

6.3V CERM

603

4.7UF

C8643

1

2

4.7UF

603

CERM

6.3V

20%

C8637

1

2

402

0.47UF

10%

6.3V CERM-X5R

C8600

1

2

SYNC_MASTER=M87_MLB

051-7431

A.0.0

9272

SYNC_DATE=08/28/2007

NV G84M GPIO/MIO/Misc

PP3V3_S0GPU

GPU_SWAPRDY_A

PP3V3_S0GPU

PP1V25_S0_ISNS

VOLTAGE=1.2V

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP1V2_GPU_VID_PLLVDD_F

PP1V25_S0_ISNS

PP1V2_GPU_PLLVDD_F

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.2V

PP3V3_S0GPU

GPU_MIOA_VREF GPU_MIOB_VREF

TP_GPU_MIOA_VSYNC

GPU_MIOA_D<6>

GPU_XTALOUTBUFF

NC_GPU_XTALOUT

GPU_CLK27M

TP_GPU_MIOA_D<7> GPU_MIOA_D<8>

GPU_MIOA_PU_GND GPU_MIOB_PU_GND

GPU_MIOB_PD_VDDQ

GPU_MIOA_PD_VDDQ

GPU_MIOB_PU_GND

GPU_MIOB_PD_VDDQ

GPU_MIOA_PU_GND

GPU_MIOA_PD_VDDQ

NC_GPU_ROM_SI

GPU_CLK27M_SS

GPU_MIOB_D<10>

TP_GPU_MIOB_CLKOUT_P TP_GPU_MIOB_CLKOUT_N TP_GPU_MIOB_CTL3 TP_GPU_MIOB_DE

TP_GPU_MIOB_D<2> GPU_MIOB_D<3> GPU_MIOB_D<4> GPU_MIOB_D<5> GPU_MIOB_D<6> GPU_MIOB_D<7> GPU_MIOB_D<8> GPU_MIOB_D<9>

GPU_MIOB_D<11>

TP_GPU_MIOB_VSYNC

TP_GPU_MIOA_HSYNC

GPU_MIOA_D<11>

GPU_MIOA_D<10>

GPU_MIOA_D<9>

GPU_MIOA_D<5>

GPU_MIOA_D<4>

GPU_MIOA_D<3>

GPU_MIOA_D<2>

GPU_MIOA_D<1>

GPU_MIOA_D<0>

TP_GPU_MIOA_DE

TP_GPU_MIOA_CTL3

TP_GPU_MIOA_CLKOUT_N

TP_GPU_MIOA_CLKOUT_P

GPU_GPIO_6 GPU_VGA_EN_L

NC_GPU_GPIO_1

GPU_VCORE_VID0

GPU_VCORE_VID3

NC_GPU_ROM_SCLK

NC_GPU_ROM_SO

GPU_TESTMODE_PD

TP_GPU_BUFRST_L

NC_GPU_STEREO

GPU_HPD

GPU_BL_PWM GPU_PANEL_EN

NC_GPU_GPIO_9

NC_GPU_SPDIF

TP_GPU_JTAG_TCK TP_GPU_JTAG_TDI TP_GPU_JTAG_TDO TP_GPU_JTAG_TMS

GPU_TDIODE_N

GPU_BKLT_EN TP_GPU_GSTATE<0>

NC_GPU_GPIO_8

FB_VREF_UNTERM

GPU_VCORE_VID1

TP_GPU_JTAG_TRST_L

GPU_MIOB_HSYNC

GPU_TDIODE_P

TP_GPU_MIOB_CLKIN

GPU_MIOB_D<0> GPU_MIOB_D<1>

GPU_VCORE_VID2

NC_GPU_ROM_CS_L

MIN_LINE_WIDTH=0.2 mm MIN_NECK_WIDTH=0.2 mm

PP1V2_GPU_H_PLLVDD_F

VOLTAGE=1.2V

PP1V25_S0_ISNS

80

72

80

72

76

69

76

69

75

67

75

67

74

65

74

65

73

50

73

50

72

27

72

27

65

26

65

73

26

58

21

58

90

82

91

82

71

91

21

48

19

48

73

75

80

73

76

73

70

75

73

75

19

8

73

30

73

72

73

30

73

9

73

51

9

73

69

73

51

73

8

IN

OUT

IN

G

D S

BI

OUT

DA

DB

DC

DD

EN_L

IN

S2D

S1D

S2C

S1C

S2B

S1B

S2A

S1A

VCC

GND

THRML

PAD

D

SG

NC

VCC

GND

NC

SCL

SDA

OUT

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

VID0

HPD1

HDCP Support

(I2CS requires pullups even if not used)

Unused I2C Buses

I2CS ties into SMBus connection page

RAMCFG0

3GIO_PADCFG0

PEX_PLL_EN_TERM

near GPU

PCI_DEVID<3..0>

3GIO_PADCFG2

USER<3..0>

PCI_IOBAR BAR2_SIZE

NC

Unused signals

Renamed signals

Place Rs

AC_DET

NC

RAMCFG1

Unused Clocks

near GPU

Place Rs

(BIOS ROM PRESENT)

RAMCFG3

SLOT_CLOCK_CFG

RAMCFG2

3GIO_PADCFG1

SUBVENDOR

PWR_CTL0 PWR_CTL1

MEM_VREF

TMDS Backdrive Protection

FAN_PWM

MEM_VID

PCI_DEVID<4>

ROMTYPE<1..0>

PCI_DEVID2 PCI_DEVID1

Straps not supported:

3GIO_PADCFG3

Supported straps:

PCI_DEVID3

PCI_DEVID0

Analog Video Mux

MIOA_D<5..2>

MIOA_HSYNC

MIOB_CTL3

MIOB_VSYNC, MIOB_D<10>

MIOB_D<7> MIOB_DE

THERM

HPD0

SLI_SYNC

LCD0_BL_PWM

VID1

Native Func

LCD0_VDD LCD0_BL_EN

Config Straps

GPIOs

72 73 80

2.2K

5% 1/16W MF-LF

402

R8728

1

2

VRAM8

10K

1/16W MF-LF

402

5%

R8726

1

2

10K

1/16W

5%

MF-LF

402

VRAM_8M

R8724

1

2

10K

5% 1/16W MF-LF

402

R8722

1

2

10K

5% 1/16W MF-LF

402

VRAM_SAMSUNG

R8720

1

2

10K

402

1/16W MF-LF

5%

VRAM4

R8727

1

2

1/16W

402

MF-LF

5%

10K

VRAM_16M

R8725

1

2

MF-LF

NO STUFF

5%

10K

402

1/16W

R8723

1

2

10K

1/16W

5%

402

VRAM_HYNIX

MF-LF

R8721

1

2

402

1/16W

NO STUFF

2.2K

MF-LF

5%

R8729

1

2

NO STUFF

2.2K

5% 1/16W MF-LF

402

R8730

1

2

402

2.2K

5%

NO STUFF

1/16W MF-LF

R8731

1

2

2.2K

402

MF-LF

5%

1/16W

NO STUFF

R8732

1

2

2.2K

402

5% 1/16W MF-LF

R8733

1

2

GPU_SS_INT

10K

MF-LF

1/16W

5%

402

R8781

1

2

MF-LF

1/16W

5%

402

10K

R8780

1

2

1%

150

402

MF-LF

1/16W

R8745

1

2

1/16W

1%

150

MF-LF

402

R8744

1

2

402

MF-LF

1/16W

1%

150

R8743

1

2

74 90

1/16W

1%

150

402

MF-LF

R8742

1

2

1%

MF-LF

1/16W

402

150

R8741

1

2

1/16W

1%

150

402

MF-LF

R8740

1

2

80 90

10V

0.1UF

20%

402

CERM

C8700

1 2

1/16W MF-LF 402

10K

5%

R8700

1

2

72 73 75

65 75

100K

1/16W

402

MF-LF

5%

R8791

1

2

CRITICAL

SOT-23

SI2305DS

Q8790

3

1

2

MF-LF 402

5% 1/16W

10K

R8790

1

2

HDCP

10V

0.1UF

20%

402

CERM

C8770

1 2

HDCP

1/16W

5%

MF-LF

402

10K

R8770

1

2

10K

402

MF-LF

5%

1/16W

HDCP

R8771

1

2

74

69 70 71 72 73

402

MF-LF

2.2K

5% 1/16W

R8737

1

2

2.2K

NO STUFF

402

1/16W

5%

MF-LF

R8734

1

2

1/16W

402

2.2K

5%

MF-LF

R8735

1

2

2.2K

MF-LF

402

1/16W

5%

R8736

1

2

CRITICAL

QFN

TS3V340

U8700

4

7

9

12

15

8

1

2

5

11

14

3

6

10

13

17

16

SSM6N15FE

SOT563

Q8791

6

2

1

CRITICAL HDCP

190-00001-0001

SOI

U8770

4

12

3

76

5

8

72 73 75

9

72 73 82

72 73 76

9

72 73 82

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

051-7431

A.0.0

9273

GPU Straps

GPU_HPD NC_GPU_GPIO_1

GPU_GPIO_6

NC_GPU_GPIO_9

GPU_BL_PWM

TP_GPU_GSTATE<0>

GPU_PANEL_EN

MAKE_BASE=TRUE

GPU_BL_PWM

MAKE_BASE=TRUE

TP_GPU_GSTATE<0>

GPU_VGA_EN_L

MAKE_BASE=TRUE

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_GPIO_9

NO_TEST=TRUE

NC_GPU_GPIO_1

MAKE_BASE=TRUE

TP_GPU_GSTATE<1>

GPU_HPD

MAKE_BASE=TRUE

GPU_PANEL_EN

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_GPIO_8

MAKE_BASE=TRUE

GPU_VCORE_VID3

MAKE_BASE=TRUE

GPU_VCORE_VID1

MAKE_BASE=TRUE

GPU_VCORE_VID0

FB_VREF_UNTERM

MAKE_BASE=TRUE

GPU_VCORE_VID2

MAKE_BASE=TRUE

FB_VREF_UNTERM GPU_VCORE_VID0 GPU_VCORE_VID1

NC_GPU_GPIO_8

GPU_VCORE_VID3

GPU_VGA_EN_L

PP3V3_S0GPU

GPU_MIOA_D<0>

GPU_MIOB_HSYNC

GPU_MIOA_D<9>

GPU_MIOA_D<8>

GPU_MIOB_D<8>

GPU_MIOA_D<6>

GPU_MIOB_D<9>

GPU_MIOA_D<1>

GPU_MIOB_D<3> GPU_MIOB_D<5> GPU_MIOB_D<4>

GPU_TV_C_VGA_R

GPU_TV_COMP

GPU_VGA_B

GPU_TV_Y

GPU_TV_C

MAKE_BASE=TRUE

GPU_VDD_SENSE

GPU_MIOB_D<1>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_I2CA_SDA

GPU_MIOB_D<0>

GPU_VCORE_VID2

PP3V3_S0GPU_TMDS

PP3V3_S0GPU

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_IFPD_CLK_N

MAKE_BASE=TRUE

TP_GPU_MIOA_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOB_DE

MAKE_BASE=TRUE

TP_GPU_MIOB_D<2> TP_GPU_MIOB_D<2>

GPU_MIOB_D<7..6> GPU_MIOB_D<10> TP_GPU_MIOB_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOA_D<11..10>

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKIN

MAKE_BASE=TRUE

TP_GPU_MIOB_CTL3

TP_GPU_MIOB_DE

MAKE_BASE=TRUE

TP_GPU_MIOA_DE

MAKE_BASE=TRUE

TP_GPU_MIOA_D<5..2>

MAKE_BASE=TRUE

TP_GPU_MIOA_D<7>

MAKE_BASE=TRUE

TP_GPU_MIOA_HSYNC

TP_GPU_MIOB_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOB_D<7..6>

TP_GPU_MIOA_VSYNC TP_GPU_MIOB_CLKIN TP_GPU_MIOB_CLKOUT_P

TP_GPU_MIOB_CTL3

GPU_CLK27M_SS GPU_XTALOUTBUFF

MAKE_BASE=TRUE

TP_GPU_MIOB_VSYNC

MAKE_BASE=TRUE

TP_GPU_MIOB_D<10>

NC_GPU_IFPD_CLK_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_IFPD_CLK_P NC_GPU_IFPD_CLK_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_CS_L NC_GPU_ROM_CS_L

NC_GPU_ROM_SCLK NC_GPU_ROM_SI

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_SO NC_GPU_ROM_SO

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_U_DATAP<3> NC_LVDS_U_DATAP<3>

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOB_CLKOUT_P

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_V2SYNC NC_GPU_V2SYNC

TP_GPU_MIOA_HSYNC

TP_GPU_MIOA_DE

TP_GPU_MIOA_CTL3

TP_GPU_MIOA_CLKOUT_N

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_H2SYNC NC_GPU_H2SYNC

NC_GPU_R2

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_B2 NC_GPU_B2

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_G2 NC_GPU_G2

GPU_MIOA_D<11..10>

GPU_MIOA_D<5..2> TP_GPU_MIOA_D<7>

TP_GPU_MIOA_CLKOUT_P

NC_LVDS_L_DATAN<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_GPU_CSYNC NC_GPU_CSYNC

NC_LVDS_L_DATAP<3>

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_U_DATAN<3> NC_LVDS_U_DATAN<3>

GPU_DVI_DDC_CLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_XTALOUT

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_STEREO

GPU_CLK27M

GPU_TDIODE_P

GPU_CLK27M_SS

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_SPDIF NC_GPU_SPDIF

NC_GPU_XTALOUT

NC_GPU_I2CA_SCL NC_GPU_I2CA_SDA

GPU_TDIODE_N

GPU_DVI_DDC_DATA

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_LVDS_L_DATAP<3>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_LVDS_L_DATAN<3>

NC_GPU_STEREO

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_SCLK

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_ROM_SI

NC_FBA_MA<13> NC_FBB_MA<13>

NC_FBC_CMD28

MAKE_BASE=TRUE

NO_TEST=TRUE

NC_FBC_CMD28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBA_CMD28

PP3V3_S0GPU

GPU_VGA_R

GPU_VGA_EN_L

GPU_TV_COMP_VGA_B

GPU_TV_Y_VGA_G

GPU_VGA_G

GPU_TMDS_PWREN_L

PM_GPUVCORE_EN

GPU_MIOB_D<11>

MAKE_BASE=TRUE

GPU_CLK27M

MAKE_BASE=TRUE

GPU_CLK27M_SS

MAKE_BASE=TRUE

GPU_TDIODE_N

MAKE_BASE=TRUE

GPU_PANEL_DDC_CLK GPU_PANEL_DDC_CLK

GPU_VDD_SENSE

MAKE_BASE=TRUE

GPU_PANEL_DDC_DATA

MAKE_BASE=TRUE

GPU_GND_SENSE GPU_GND_SENSE

GPU_PANEL_DDC_DATA

MAKE_BASE=TRUE

GPU_DVI_DDC_DATA

MAKE_BASE=TRUE

GPU_DVI_DDC_CLK

MAKE_BASE=TRUE

GPU_TDIODE_P

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBA_MA<13>

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_FBB_MA<13>

NC_FBA_CMD28

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_R2

MAKE_BASE=TRUE

TP_GPU_MIOA_CLKOUT_P

MAKE_BASE=TRUE

TP_GPU_MIOA_CLKOUT_N

MAKE_BASE=TRUE

TP_GPU_MIOA_CTL3

PP3V3_S0GPU

GPU_I2CH_SCL GPU_I2CH_SDA

NO_TEST=TRUE

MAKE_BASE=TRUE

NC_GPU_I2CA_SCL

PP3V3_S0GPU

GPU_BKLT_EN

MAKE_BASE=TRUE

GPU_BKLT_EN

80

76

75

74

73

72

82

72

65

90

91

90

91

65

90

91

65

82

80

73

76

71

75

58

75

80 58

73

90 90

90

90 90

80

73

80

90

58

73

76 76

75

76

75

76

80

73

58

73

72

73

70

73

48

73

74

73

74 48

74

73

73 73

73

72

73

74

73 73

73

73 73

74 74

73

74 74

73

74 74

74

74 74

73

74

74 74

74

74 74

74

73

72

73 73

73

74

72

74

73

73 73

73

48

73

72

74 74

73

74

73

74

72

73

74

73

48

74

48

72

9

72

69

72

8

72

68

72

73

72

8 8

73

72

72 72

72

30

72

73

72 72

72

72 72

73 73

72

73 73

72

73 73

73

73 73

72

73

73 73

73

73 73

73

72

30

51

30

72 72

72

73

51

73

72

69

69 69

69

8

72

30

51

73 73

68

73

68

73

51

69

73

72

8

73

8

9

OUT OUT OUT

OUT OUT

OUT

OUT OUT OUT

OUT

OUT OUT

OUT OUT OUT OUT OUT OUT

BI BI

OUT

IFPA_TXD0

I2CB_SDA

I2CB_SCL

I2CA_SDA

I2CA_SCL

DACC_VSYNC

DACC_HSYNC

DACC_BLUE

DACC_GREEN

DACC_RED

DACB_CSYNC

DACB_BLUE

DACB_GREEN

DACB_RED

DACA_VSYNC

DACA_HSYNC

DACA_BLUE

DACA_GREEN

DACA_RED

IFPD_TXD6

IFPD_TXD5

IFPD_TXD4

IFPD_TXC

IFPC_TXD2

IFPC_TXD1

IFPC_TXD0

IFPC_TXC

IFPB_TXD7

IFPB_TXD6

IFPB_TXD5

IFPB_TXD4

IFPB_TXC

IFPA_TXD3

IFPA_TXD2

IFPA_TXD1

IFPA_TXC

I2CS_SDA

I2CS_SCL

I2CH_SDA

I2CH_SCL

I2CC_SDA

I2CC_SCL

DACC_RSET

DACC_VREF

DACC_IDUMP

DACC_VDD

DACB_RSET

DACB_VREF

DACB_IDUMP

DACB_VDD

DACA_RSET

DACA_VREF

DACA_IDUMP

DACA_VDD

IFPCD_RSET

IFPCD_VPROBE

IFPCD_PLLGND

IFPCD_PLLVDD

IFPD_IOVDD

IFPC_IOVDD

IFPAB_RSET

IFPAB_VPROBE

IFPAB_PLLGND

IFPB_IOVDD

IFPA_IOVDD

IFPAB_PLLVDD

IFPA_TXC_L

IFPA_TXD0_L

IFPA_TXD1_L

IFPA_TXD2_L

IFPA_TXD3_L

IFPB_TXC_L

IFPB_TXD4_L

IFPB_TXD5_L

IFPB_TXD6_L

IFPB_TXD7_L

IFPC_TXC_L

IFPC_TXD0_L

IFPC_TXD1_L

IFPC_TXD2_L

IFPD_TXC_L

IFPD_TXD4_L

IFPD_TXD5_L

IFPD_TXD6_L

OUT OUT

OUT

BI BI BI BI BI BI

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

Sum of peak currents: 240mA

20mA peak per diff pair 160mA peak for all pairs

200mA peak for all pairs

20mA peak per diff pair

Place at AD6

BOM options provided by this page:

- =PP3V3_GPU_IFPCD_IOVDD

Sum of peak currents: 390mA

120mA peak

150mA peak

120mA peak

40mA peak

Place at AE7

40mA peak

Place at AF9 Place at AF8

Composite/S-Video VGA Component

Comp B Pb

Y G Y

C R Pr

(NONE)

- =PP1V8_GPU_IFPX

- =PP3V3_GPU_DAC

I2CS must be pulled up if not used I2CS addr fixed at 0x9E,0x9F

MF-LF 402

1% 1/16W

1K

NO STUFF

R8850

1

2

0402

FERR-220-OHM

L8805

1 2

20%

0.1UF

10V 402

CERM

C8806

1

2

FERR-220-OHM

0402

L8815

1 2

FERR-220-OHM

0402

L8830

1 2

FERR-220-OHM

0402

L8820

1 2

FERR-220-OHM

0402

NO STUFF

L8840

1 2

73 90

76 90

73 90

76 90

73 90

80 90

73

73 80

4.7UF

20%

CERM

6.3V 603

C8805

1

2

4.7UF

603

CERM

6.3V

20%

C8820

1

2

73

73 90

NB8P-GS-W-A2

BGA

(5 OF 8)

OMIT

U8000

AH12

AJ12

AF10

AG9

AH11

AH9

AD10

AH10

AK10

T6

U5

T5V7

R6

R7

V8

R5

AE5

AG6

AG7

AG4

AF6

AF5

AD7

AH4

AG5

K2 J3

H4 J4

G2 G1 G3 H3 C1 B1

AF9 AK9

AJ9

AH6 AJ6 AH8 AH7 AJ8 AK8 AJ5 AH5

AD9

AC9

AL5

AM4

AF8

AK4 AL4

AM6 AM5 AM7 AL7 AK6 AK5 AK7 AL8

AD6 AM2

AM3

AE2 AE1 AF1 AF2 AG1 AH1

AB10

AA10

AH3

AK3

AE7

AG3 AH2

AK1 AJ1 AL2 AL1 AJ2 AJ3

73

1/16W 402

MF-LF

124

1%

R8852

1

2

1/16W 402

MF-LF

124

1%

R8853

1

2

1/16W MF-LF 402

124

1%

R8854

1

2

73

0.1UF

CERM 402

20% 10V

C8852

1

2

0.1UF

10V

20% CERM

402

C8853

1

2

0.1UF

10V

20% CERM

402

C8854

1

2

73 76

73

45 48 51 88

20%

0.1UF

10V 402

CERM

C8821

1

2

20%

0.1UF

10V CERM 402

C8831

1

2

20%

6.3V CERM 603

4.7UF

C8830

1

2

20% 10V CERM 402

0.1UF

C8841

1

2

4.7UF

603

CERM

6.3V

20%

NO STUFF

C8840

1

2

20%

6.3V CERM

603

4.7UF

C8845

1

2

4.7UF

CERM

603

6.3V

20%

C8815

1

2

20%

0.1UF

10V 402

CERM

C8801

1

2

4.7UF

20%

CERM

6.3V 603

C8800

1

2

0402

FERR-220-OHM

L8800

1 2

402

CERM

10V

0.1UF

20%

C8803

1

2

CERM 402

0.01UF

16V

20%

NO STUFF

C8856

1

2

CERM 402

0.01UF

16V

20%

NO STUFF

C8855

1

2

402

CERM

10V

0.1UF

20%

C8813

1

2

20%

0.1UF

10V 402

CERM

C8811

1

2

20%

6.3V 603

CERM

4.7UF

C8810

1

2

0402

FERR-220-OHM

L8810

1 2

20%

0.1UF

10V 402

CERM

C8816

1

2

MF-LF 402

1% 1/16W

1K

NO STUFF

R8851

1

2

051-7431

A.0.0

9274

NV G84M Video Interfaces

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

GPU_VGA_G

NC_GPU_G2 NC_GPU_B2

GPU_PANEL_DDC_DATA

GPU_PANEL_DDC_CLK

GPU_DACC_RSET

GPU_DACC_VREF

PP1V8_S0GPU_ISNS

GPU_IFPAB_VPROBE GPU_IFPCD_VPROBE

GPU_DACB_VREF GPU_DACC_VREF

GPU_DACA_RSET GPU_DACA_VREF

GPU_IFPAB_RSET GPU_IFPCD_RSET

GPU_DACC_RSET

GPU_DACB_RSET

PP3V3_S0GPU_TMDS

MIN_LINE_WIDTH=0.4 mm

PP1V8_GPU_IFPAB_IOVDD_F

MIN_NECK_WIDTH=0.2 mm VOLTAGE=1.8V

MIN_NECK_WIDTH=0.2 mm

MIN_LINE_WIDTH=0.3 mm

PP1V8_GPU_IFPAB_PLLVDD_F

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.4 mm

PP3V3_GPU_IFPCD_IOVDD_F

MIN_NECK_WIDTH=0.2 mm VOLTAGE=3.3V

PP3V3_GPU_DACA_VDD_F

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_GPU_DACB_VDD_F

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_GPU_DACC_VDD_F

MIN_LINE_WIDTH=0.35 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=3.3V

PP3V3_S0GPU

LVDS_L_DATA_P<0>

GPU_DVI_DDC_DATA

GPU_DVI_DDC_CLK

NC_GPU_I2CA_SDA

NC_GPU_I2CA_SCL

NC_GPU_V2SYNC

NC_GPU_H2SYNC

NC_GPU_R2

NC_GPU_CSYNC

GPU_TV_COMP

GPU_TV_Y

GPU_TV_C

GPU_VGA_VSYNC

GPU_VGA_HSYNC

GPU_VGA_B

GPU_VGA_R

TMDS_DATA_P<5>

TMDS_DATA_P<4>

TMDS_DATA_P<3>

NC_GPU_IFPD_CLK_P

TMDS_DATA_P<2>

TMDS_DATA_P<1>

TMDS_DATA_P<0>

TMDS_CLK_P

NC_LVDS_U_DATAP<3>

LVDS_U_DATA_P<2>

LVDS_U_DATA_P<1>

LVDS_U_DATA_P<0>

LVDS_U_CLK_P

NC_LVDS_L_DATAP<3>

LVDS_L_DATA_P<2>

LVDS_L_DATA_P<1>

LVDS_L_CLK_P

GPU_DACB_RSET

GPU_DACB_VREF

GPU_DACA_RSET

GPU_DACA_VREF

GPU_IFPCD_RSET

GPU_IFPCD_VPROBE

GPU_IFPAB_RSET

GPU_IFPAB_VPROBE

LVDS_L_CLK_N

LVDS_L_DATA_N<0>

LVDS_L_DATA_N<1>

LVDS_L_DATA_N<2>

NC_LVDS_L_DATAN<3>

LVDS_U_CLK_N

LVDS_U_DATA_N<0>

LVDS_U_DATA_N<1>

LVDS_U_DATA_N<2>

NC_LVDS_U_DATAN<3>

TMDS_CLK_N

TMDS_DATA_N<0>

TMDS_DATA_N<1>

TMDS_DATA_N<2>

NC_GPU_IFPD_CLK_N

TMDS_DATA_N<3>

TMDS_DATA_N<4>

TMDS_DATA_N<5>

MIN_NECK_WIDTH=0.2 mm

PP1V8_GPU_IFPCD_PLLVDD_F

VOLTAGE=1.8V

MIN_LINE_WIDTH=0.3 mm

SMBUS_SMC_0_S0_SDA

SMBUS_SMC_0_S0_SCL

GPU_I2CH_SDA

GPU_I2CH_SCL

78

80

77

76

71

75

70

73

69

72

68

65

80

58

50

73

48

74

8

74

74 74

74

8

74

OCSET

VO

DFB

COMP

VSUM

DROOP

RTN

VDIFF

PGND

VSS

THRM_PAD

VSEN

FDE

AF_EN

VID4

SOFT

FB

VW

VR_ON

VID3

VID2

PGOOD VID0

LGATE

UGATE

PHASE

BOOT

RBIAS

VIN

PVCC

VID1

VDD

IMON

OUT

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_BOMGROUP_ITEM

BOM OPTIONS

BOM GROUP

TABLE_BOMGROUP_HEAD

GPU VCore Setpoints

M87,M88

1

1.23600V

0

VID1

(GFXIMVP6_VO)

(GFXIMVP6_AGND)

Vout = 1.25V - 0.96V 18A max output (L8920 limit)

M88

M87

-

Max perfBalanced

-

M88

M87

-

Max Batt

1.13300V

1.05575V

Voltage

VID0VID2

0 0 1

1 01

VID3

1

0

Other VID states may not be valid

GPU VCore Regulator

M87/M88 Default Vcore Setpoints

0

4.99K

MF-LF 402

1% 1/16W

R8951

1

2

MF-LF

374K

1/16W

1%

402

R8950

1

2

402

MF-LF

5%

1/16W

20

PLACEMENT_NOTE=Place R8920 at U8900

R8908

1 2

MF-LF

20

PLACEMENT_NOTE=Place R8908 at U8900

5%

1/16W

402

R8920

1 2

MF-LF

402

5%

1/16W

10K

R8907

1

2

5%

10K

1/16W MF-LF 402

R8910

1

2

CERM

560PF

402

10% 50V

C8951

1 2

1% 1/16W MF-LF

2.21K

402

R8953

1

2

68PF

CERM 402-1

50V

5%

C8952

1

2

5%

50V

CERM

180PF

402

C8950

12

0.001UF

402

50V CERM

10%

C8920

1

2

QFN

ISL6263B

CRITICAL

U8900

30

17

5

11

10

6

32

28

21

3

20

31

19

22

1

9

2

33

18

16

7

23 24 25 26 27

14

12

29

8

15

13

4

SM

XW8900

1 2

680pF

10%

402

CERM

50V

C8953

1

2

6.98K

1/16W MF-LF

402

1%

R8909

1

2

402

X7R

25V

10%

1000PF

C8922

1

2

0.001UF

10% 402

50V CERM

C8923

1

2

65 79

402

CERM

0.001UF

50V

10%

C8921

1

2

1/16W

10

1%

402

MF-LF

R8904

1 2

MF-LF

402

NO STUFF

20K

5%

1/16W

R8906

2 1

150K

1/16W MF-LF

402

1%

R8905

2 1

10% 16V X5R

0.033UF

402

C8904

12

1uF

10V 402

X5R

10%

C8901

1

2

1

MF-LF

402

5%

1/16W

R8911

1 2

X5R 402

10% 10V

1uF

C8909

1

2

402

10V

10% X5R

1uF

C8908

1

2

1uF

402

X5R

10% 10V

C8902

1

2

CERM 402

16V

0.01uF

10%

C8903

1

2

402

X5R

0.1uF

10% 16V

C8972

1

2

402

CERM

50V

10%

330pF

NO STUFF

C8971

1 2

5%

MF-LF

402

1/16W

0

R8902

2

1

MF-LF 402

5%

10K

1/16W

R8901

1

2

3.01K

1/16W

1%

MF-LF

402

R8900

1 2

402

CERM

0.068UF

NO STUFF

10V

10%

C8900

1

2

CRITICAL

RJK0301DPB

LFPAK

Q8951

5

4

1 2 3

603

X7R

16V

0.22UF

10%

C8956

1

2

RJK0301DPB

LFPAK

CRITICAL

Q8952

5

4

1 2 3

CRITICAL

0.9UH-27A

MPL104-SM

L8920

1 2

SM

XW8901

1

2

SM

XW8902

1

2

10UF

603

6.3V

20% X5R

C8965

1

2

20%

6.3V 603

X5R

10UF

C8966

1

2

330UF

TANT D2T

10%

CRITICAL

2.0V

C8943

1

23

1/16W

5%

402

MF-LF

1K

R8930

1

2

CRITICAL

LFPAK

RJK0305DPB

Q8950

5

4

1 2 3

POLY

25V

20%

22UF

CRITICAL

CASE-D2-LF

C8930

1

2

10%

1UF

X5R

25V 603

C8932

1

2

1UF

10% 25V X5R 603

C8933

1

2

402

MF-LF

5%

1/16W

10K

R8903

1

2

11.8K

1/16W

402

MF-LF

1%

R8977

1

2

10K

1/16W MF-LF

5%

402

R8976

1

2

10KOHM-5%

0603-LF

R8978

1

2

402

25V

10% X5R

0.1UF

C8906

1

2

TANT

10%

CRITICAL

330UF

2.0V D2T

C8942

1

2 3

10UF

20% X5R

603

6.3V

C8968

1

2

X5R

20%

6.3V

10UF

603

C8967

1

2

POLY

25V

20%

CRITICAL

22UF

CASE-D2-LF

C8931

1

2

2.2K

GPUVID3_1

MF-LF

402

5%

1/16W

R8980

402

0

MF-LF

1/16W

5%

R8994

1 2

MF-LF

402

5%

2.2K

1/16W

GPUVID3_0

R8981

5%

402

1/16W

0

MF-LF

R8995

1 2

2.2K

GPUVID2_0

MF-LF

402

5%

1/16W

R8983

2.2K

GPUVID2_1

5%

MF-LF

402

1/16W

R8982

1

2

MF-LF

402

5%

2.2K

1/16W

GPUVID0_1

R8986

GPUVID0_0

MF-LF

402

5%

2.2K

1/16W

R8987

1/16W

2.2K

MF-LF

402

5%

GPUVID1_1

R8984

MF-LF

402

5%

2.2K

1/16W

GPUVID1_0

R8985

402

MF-LF

1/16W

5%

0

R8988

1

2

72 73

5%

402

MF-LF

1/16W

0

R8989

1 2

MF-LF

0

1/16W

402

5%

R8990

1 2

72 73

65 73

GPUVID_1P23V

GPUVID3_0,GPUVID2_0,GPUVID1_1,GPUVID0_0

GPUVID_1P13V

GPUVID3_0,GPUVID2_1,GPUVID1_1,GPUVID0_0

GPUVID_1P05V

GPUVID3_1,GPUVID2_0,GPUVID1_0,GPUVID0_1

GPU (G84M) Core Supply

SYNC_MASTER=M87_MLB

SYNC_DATE=09/26/2007

75 92

051-7431

A.0.0

GFXIMVP6_VID0

SWITCH_NODE=TRUE

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_PHASE

PP5V_S5_GFXIMVP6_VDD

MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MIN_LINE_WIDTH=0.3MM

PP5V_S5_GFXIMVP6_PVCC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM VOLTAGE=5V

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_LGATE

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_DFB

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VID2

GFXIMVP6_VSUM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GND_GFXIMVP6_AGND

VOLTAGE=0V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_OCSET

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VID0

PP3V3_S0GPU

GFXIMVP6_VID3

GFXIMVP6_VID1

GFXIMVP6_RBIAS

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_AF_EN

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_VDIFF_RC

MIN_NECK_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VSEN_N

GFXIMVP6_FB

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VID4

PP5V_S5

GPU_VCORE_VID0

GFXIMVP6_VID4

GFXIMVP6_VID3

GFXIMVP6_VID2

GFXIMVP6_VID1

GPU_GND_SENSE

VOLTAGE=0V

MIN_NECK_WIDTH=0.20 mm MIN_LINE_WIDTH=0.25 mm

GPU_VDD_SENSE

MIN_NECK_WIDTH=0.20 mm VOLTAGE=1.25V

MIN_LINE_WIDTH=0.25 mm

GPU_VCORE_VID3

GPU_VCORE_VID1

GPU_VCORE_VID2

GFXIMVP6_COMP_RC

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.3MM

PP3V3_S0GPU

GFXIMVP6_FDE

GFXIMVP6_VSEN_P

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_COMP

GFXIMVP6_NTC

GFXIMVP6_DROOP

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

MIN_NECK_WIDTH=0.3MM

GFXIMVP6_PHASE_VSUM

MIN_LINE_WIDTH=0.3MM

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VW

PPBUS_G3H

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.3MM

GFXIMVP6_BOOT

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_SOFT

MIN_LINE_WIDTH=0.3MM

PM_P1V8_S0GPU_EN

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_UGATE

MIN_LINE_WIDTH=0.6MM

GFXIMVP6_IMON

GFXIMVP6_VDIFF

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

PM_GPUVCORE_EN

MIN_LINE_WIDTH=0.3MM MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VIN

PPVCORE_GPU

MIN_NECK_WIDTH=0.2MM

GFXIMVP6_VO

MIN_LINE_WIDTH=0.3MM

82 79 66

79

63

80

65

80

62

76

63

76

61

75

62

75

60

74

61

74

59

73

60

73

58

72

58

72

57

65

43

65

49

68

58

42

58

40

49

48

27

73

48

8

75

8

75

91

75

8

75

68

8

91

7

50

7

D

S

G

S

D

IN

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0289

LCD (LVDS) INTERFACE

Panel has 2K pull-ups

no-panel case (development).

100K pull-ups are for

Place close to the connector

0.001uF

50V

20%

402

CERM

C9010

1

2

20%

0.001uF

50V

CERM

402

C9001

1

2

SM

FERR-250-OHM

CRITICAL

L9000

0.0022uF

50V

10%

402

CERM

C9000

1 2

1/16W

5%

402

MF-LF

100K

R9001

1/16W

5%

402

MF-LF

100K

R9000

1

2

SI3443DV

TSOP-LF

CRITICAL

Q9000

1

2

5

63

4

2N7002

SOT23-LF

Q9001

3

1

2

1/16W

5%

402

100K

MF-LF

R9094

1

2

MF-LF

1/16W

100K

5%

402

R9011

1

2

1/16W

5%

MF-LF

100K

402

R9010

1

2

72 73

CRITICAL

F-RT-SM

MSC-RB30-5-FA

J9000

33

34

1

10 11 12 13 14 15 16 17 18 19

2

20 21 22 23 24 25 26 27 28 29

3

30

4 5 6 7 8 9

90-OHM-100MA

DLP11S

CRITICAL

L9010

1 2

34

90-OHM-100MA

DLP11S

CRITICAL

L9011

1 2

34

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

LVDS Display Connector

76 92

A.0.0

051-7431

GPU_PANEL_DDC_DATA

LVDS_L_CLK_CONN_F_N

LVDS_U_CLK_CONN_F_N LVDS_U_CLK_CONN_F_P

LVDS_L_CLK_CONN_F_P

LVDS_U_CLK_N

LVDS_U_CLK_P

LVDS_L_CLK_N

LVDS_L_CLK_P

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.5 mm

PP3V3_SW_LCD_UF

VOLTAGE=3.3V

GPU_PANEL_DDC_CLK

LVDS_L_DATA_N<0> LVDS_L_DATA_P<0>

LVDS_U_DATA_P<2>

LVDS_U_DATA_N<2>

LVDS_U_DATA_P<1>

LVDS_U_DATA_N<1>

LVDS_U_DATA_P<0>

LVDS_L_DATA_N<1> LVDS_L_DATA_P<1>

LVDS_L_DATA_N<2> LVDS_L_DATA_P<2>

LVDS_U_DATA_N<0>

LCD_PWREN_L

LCD_PWREN_L_RC

VOLTAGE=3.3V

PP3V3_SW_LCD

MIN_LINE_WIDTH=0.5 mm MIN_NECK_WIDTH=0.25 mm

PP3V3_S5

PP3V3_S0GPU

GPU_PANEL_EN

91 65 60

58 56

80

48

75

46

74

28

73

27

72

26

65

25

58

74

90

74

90

24

48

73

91

74

73

74

8

IN

BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

BI BI BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CK*

A10

A9

A6 A7

A3 A4

A2

A0 A1

CKE CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

CS*

MFLOW

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CK*

A10

A9

A6 A7

A3 A4

A2

A0 A1

CKE CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

CS*

MFLOW

(1 OF 2)

IN IN IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Connect to designated pin, then GND

U8400.J12

U8400.J1U8400.J1

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

NC

Connect to designated pin, then GND

Page Notes

Power aliases required by this page:

Signal aliases required by this page:

BOM options provided by this page:

U8400.J12

NC NC

VRAM8

16V

10%

402

X5R

0.1uF

C9103

1

2

VRAM8

0.1uF

16V

10% X5R

402

C9102

1

2

VRAM8

16V

10%

402

X5R

0.1uF

C9104

1

2

VRAM8

16V

0.1uF

402

X5R

10%

C9101

1

2

VRAM8

0.1uF

X5R

10% 16V

402

C9122

1

2

VRAM8

0.1uF

402

10% 16V X5R

C9123

1

2

VRAM8

X5R 402

10% 16V

0.1uF

C9124

1

2

VRAM8

16V

10% 402

X5R

0.1uF

C9125

1

2

VRAM8

0.1uF

16V

10% 402

X5R

C9126

1

2

VRAM8

100

1/16W

5%

402

MF-LF

R9149

1

2

VRAM8

1/16W

1%

402

MF-LF

243

R9148

1

2

VRAM8

402

X5R

10% 16V

0.1uF

C9121

1

2

VRAM8

16V

10%

0.1uF

X5R 402

C9115

1

2

VRAM8

402

16V X5R

0.1uF

10%

C9110

1

2

VRAM8

1/16W

402

MF-LF

1K

5%

R9140

1

2

69 70 90

69 70 77 90

69 70 77

69 70 90

69 70 77 90

69 70 90

69 70 77 90

69 70 90

69 70 77

90

69 70 77

90

69 70 77 90

69 70 90

69 70 77 90

69 70 90

69 70 77 90

VRAM8

MF-LF

402

1/16W

1K

5%

R9190

1

2

VRAM8

10%

0.1uF

X5R 402

16V

C9171

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9172

1

2

VRAM8

243

MF-LF

402

1%

1/16W

R9198

1

2

VRAM8

100

MF-LF 402

5% 1/16W

R9199

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9173

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9174

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9175

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9176

1

2

VRAM8

X5R

0.1uF

402

10% 16V

C9151

1

2

VRAM8

402

0.1uF

X5R

10% 16V

C9152

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9160

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9153

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9165

1

2

VRAM8

0.1uF

X5R 402

10% 16V

C9154

1

2

69 70 90

VRAM8

20%

6.3V X5R 603

10UF

C9100

1

2

VRAM8

6.3V

20% X5R

603

10UF

C9120

1

2

VRAM8

6.3V

20% X5R

603

10UF

C9150

1

2

VRAM8

6.3V

20% X5R

603

10UF

C9170

1

2

OMIT

16MX32-GDDR3-500MHZ

CRITICAL

FBGA

K4J52324QC-BC20

U9100

K4 H2

K2 L4

K3 M4

K9 H11 K10

L9 K11

M9

G4

G9 H10

F4

J11 J10

H4

F9

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H3

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H9

A4

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

U9100

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

OMIT

CRITICAL

U9150

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

CRITICAL

OMIT

K4J52324QC-BC20

FBGA

16MX32-GDDR3-500MHZ

U9150

K4 H2

K2 L4

K3 M4

K9 H11 K10

L9 K11

M9

G4

G9 H10

F4

J11 J10

H4

F9

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H3

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H9

A4

70

70 70

70

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

77

A.0.0

051-7431

92

GDDR3 Frame Buffer A (Bot)

FB_A_MA<10>

PP1V8_S0GPU_ISNS

FB_A_BA<2>

FB_A2_SEN

FB_A_WDQS<3>

FB_A_WDQS<0>

FB_A_WDQS<1>

FB_A_DRAM_RST

FB_A_CAS_L

FB_A_CS1_L

FB_A_MA<11>

FB_A_LMA<4>

FB_A_LMA<3>

PP1V8_S0GPU_ISNS

FB_A_UMA<5>

FB_A_UMA<4>

FB_A_UMA<3>

FB_A_UMA<2>

FB_A_LMA<5>

FB_A_LMA<2>

FB_A_DQ<23>

FB_A_DQ<29>

FB_A_DQ<15>

FB_A_MA<0>

FB_A_CLK_N<0>

FB_A_CLK_P<0>

FB_A_DQ<4> FB_A_DQ<2> FB_A_DQ<0> FB_A_DQ<5> FB_A_DQ<7>

FB_A_DQ<27>

FB_A_MA<6>

FB_A_DQ<13> FB_A_DQ<1>

FB_A_WDQS<5>

FB_A2_ZQ

FB_A_WE_L

FB_A_DQ<8>

FB_A_MA<8>

FB_A_DQ<9>

FB_A_DQ<12>

FB_A_DQ<3>

FB_A_WE_L

FB_A_RDQS<7>

FB_A_DQ<26>

FB_A_DQ<17>

FB_A_DQ<16>

FB_A_BA<1>

FB_A_DQ<43> FB_A_DQ<62> FB_A_DQ<56> FB_A_DQ<58> FB_A_DQ<59> FB_A_DQ<57> FB_A_DQ<63>

FB_A_DQ<61> FB_A_DQ<34>

FB_A_DQ<35> FB_A_DQ<32> FB_A_DQ<36>

FB_A_DQ<47>

FB_A_DQ<40>

FB_A_DQ<46> FB_A_DQ<45>

FB_A_DQ<44> FB_A_DQ<41>

FB_A_DQ<42>

FB_A_DQ<60>

FB_A_DQ<33>

FB_A_DQ<50> FB_A_DQ<48> FB_A_DQ<52>

FB_A_DQ<49> FB_A_DQ<54>

FB_A_RDQS<6>

FB_A_RDQS<4>

FB_A_MA<10>

FB_A_MA<9>

FB_A_WDQS<4> FB_A_WDQS<6>

FB_A_BA<0>

FB_A_BA<2>

FB_A_BA<1>

FB_A_DQM_L<6>

FB_A_DQM_L<4>

FB_A_DQM_L<7>

FB_A_DQM_L<5>

PP1V8_S0GPU_ISNS

FB_A_DQ<10> FB_A_DQ<11>

FB_A_DQ<14>

FB_A_DQ<6>

FB_A_DQ<20>

FB_A_DQ<19>

FB_A_DQ<21>

FB_A_RDQS<1>

FB_A_RAS_L

FB_A_CKE

FB_A_DQM_L<1>

FB_A_RDQS<5>

FB_A_DRAM_RST

FB_A3_SEN

FB_A3_MF

FB_A3_ZQ

FB_A_RAS_L

FB_A_CAS_L

FB_A_CLK_N<1>

FB_A_CLK_P<1>

FB_A_CKE

FB_A_MA<11>

FB_A_MA<7>

FB_A_MA<6>

FB_A_MA<1>

FB_A_DQ<55>

FB_A_DQ<51>

FB_A_DQ<39>

FB_A_DQ<37>

FB_A_DQ<38>

FB_A_DQ<53>

FB_A_DQ<22>

FB_A_DQ<18>

FB_A_DQ<30>

FB_A_DQ<31>

FB_A_DQ<24>

FB_A_DQ<25>

FB_A_CS1_L

FB_A_DQM_L<0> FB_A_DQM_L<3> FB_A_DQM_L<2>

FB_A_MA<9>

FB_A_MA<0>

FB_A_WDQS<7>

FB_A2_MF

FB_A_MA<7>

FB_A_BA<0>

FB_A_WDQS<2>

FB_A_RDQS<0> FB_A_RDQS<3> FB_A_RDQS<2>

FB_A_DQ<28>

FB_A_MA<8>

FB_A_MA<1>

FB_A0_VREF

FB_A2_VREF

PP1V8_S0GPU_ISNS

FB_A3_VREF FB_A1_VREF

78

77

74

71

70

70 70

70 69

69 69

69 68

68 68

68 65

65 65

65 50

50 50

50

8

8 8

8

IN

BI

IN

OUT OUT OUT OUT

IN

IN IN

IN

OUT

OUT OUT

OUT

IN

IN IN

IN

IN IN

IN

BI BI BI BI

BI BI BI BI BI

BI

BI BI BI BI

BI

IN IN

BI

IN IN

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CK*

A10

A9

A6 A7

A3 A4

A2

A0 A1

CKE CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

CS*

MFLOW

(1 OF 2)

DQ1

DQ0

DQ2 DQ3

DQ5 DQ6

DQ4

DQ8

DQ7

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21

DQ24

DQ23

DQ22

DQ25 DQ26 DQ27

DQ29

DQ28

DQ30 DQ31

RDQS3

RDQS2

RDQS1

RDQS0

SEN RESET

MF

ZQ

RAS*

CAS*

WE*

CK*

A10

A9

A6 A7

A3 A4

A2

A0 A1

CKE CK

WDQS2

WDQS1

WDQS0

WDQS3

BA0

BA2

BA1

RFU1 RFU2

DM3

DM2

DM1

DM0

A5

A11

A8/AP

CS*

MFLOW

(1 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

VSS0 VSS1 VSS2

VSS5

VSS3 VSS4

VSS7

VSS6

VSSA0 VSSA1

VSSQ0 VSSQ1 VSSQ2 VSSQ3

VSSQ5 VSSQ6

VSSQ4

VSSQ7 VSSQ8

VSSQ9 VSSQ10 VSSQ11 VSSQ12 VSSQ13 VSSQ14

VSSQ16

VSSQ15

VSSQ17 VSSQ18 VSSQ19VDDQ19

VDDQ20 VDDQ21

VREF1

VREF0

VDDQ10 VDDQ11 VDDQ12 VDDQ13 VDDQ14 VDDQ15

VDDQ18

VDDQ16 VDDQ17

VDDQ9

VDDA1

VDDQ0 VDDQ1 VDDQ2

VDDQ5

VDDQ3 VDDQ4

VDDQ6 VDDQ7 VDDQ8

VDD0 VDD1 VDD2

VDD5

VDD3 VDD4

VDD6 VDD7

VDDA0

(2 OF 2)

IN IN IN

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

NC NC

Page Notes

Power aliases required by this page:

BOM options provided by this page:

Signal aliases required by this page: (NONE)

(NONE)

- =PP1V8_S0_FB_VDD

- =PP1V8_S0_FB_VDDQ

NC

Connect to designated pin, then GND

U8500.J1

U8500.J12

U8500.J1

U8500.J12

Connect to designated pin, then GND

402

0.1uF

X5R

10% 16V

VRAM8

C9203

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9202

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9204

1

2

0.1uF

X5R

10% 16V

402

VRAM8

C9201

1

2

16V X5R 402

0.1uF

10%

VRAM8

C9222

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9223

1

2

402

0.1uF

10% X5R

16V

VRAM8

C9224

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9225

1

2

16V 402

0.1uF

X5R

10%

VRAM8

C9226

1

2

100

MF-LF 402

5% 1/16W

VRAM8

R9249

1

2

243

MF-LF

402

1%

1/16W

VRAM8

R9248

1

2

0.1uF

X5R

16V 402

10%

VRAM8

C9221

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9215

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9210

1

2

69 71 90

69 71

90

69 71 78 90

69 71 78

69 71 90

69 71 78 90

69 71 90

69 71 78 90

69 71 90

69 71 78 90

69 71 90

69 71 78 90

69 71 78

69 71 78 90

69 71 90

69 71 78 90

69 71 90

69 71 78 90

69 71 78

90

69 71 90

69 71 78 90

0.1uF

16V

10% 402

X5R

VRAM8

C9271

1

2

0.1uF

16V

10% 402

X5R

VRAM8

C9272

1

2

1%

243

MF-LF

402

1/16W

VRAM8

R9298

1

2

100

5% MF-LF

402

1/16W

VRAM8

R9299

1

2

0.1uF

16V X5R 402

10%

VRAM8

C9273

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9274

1

2

0.1uF

16V

10% 402

X5R

VRAM8

C9275

1

2

0.1uF

16V

10% 402

X5R

VRAM8

C9276

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9251

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9252

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9260

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9253

1

2

0.1uF

X5R 402

10% 16V

VRAM8

C9265

1

2

16V

10%

402

X5R

0.1uF

VRAM8

C9254

1

2

69 71 90

20%

6.3V X5R 603

10UF

VRAM8

C9200

1

2

20%

6.3V X5R 603

10UF

VRAM8

C9220

1

2

20%

6.3V X5R 603

10UF

VRAM8

C9250

1

2

20%

6.3V X5R 603

10UF

VRAM8

C9270

1

2

K4J52324QC-BC20

FBGA

CRITICAL

16MX32-GDDR3-500MHZ

OMIT

U9200

K4 H2

K2 L4

K3 M4

K9 H11 K10

L9 K11

M9

G4

G9 H10

F4

J11 J10

H4

F9

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H3

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H9

A4

5%

MF-LF

402

1/16W

1K

VRAM8

R9240

1

2

CRITICAL

OMIT

FBGA

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

U9250

K4 H2

K2 L4

K3 M4

K9 H11 K10

L9 K11

M9

G4

G9 H10

F4

J11 J10

H4

F9

E3 E10 N10 N3

B2 B3

C11 C10 E11 F10 F11 G10 M11 L10 N11 M10

C2

R11 R10 T11 T10 M2 L3 N2 M3 R2 R3

C3

T2 T3

E2 F3 F2 G3 B11 B10

A9

H3

D3 D10 P10

P3

V9

J2

J3

V4

D2 D11 P11

P2

H9

A4

CRITICAL

OMIT

FBGA

K4J52324QC-BC20

16MX32-GDDR3-500MHZ

U9200

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

16MX32-GDDR3-500MHZ

K4J52324QC-BC20

FBGA

OMIT

CRITICAL

U9250

A2

A11

F1

F12

M1

M12

V2

V11

K1

K12

A1

A12

J4 J9 N1 N4 N9

N12

R1 R4 R9

R12

C1

V1

V12

C4 C9

C12

E1 E4 E9

E12

H1

H12

A3 A10 G1 G12 L1 L12 V3 V10

J1 J12

B1 B4

L2 L11 P1 P4 P9 P12 T1 T4 T9 T12

B9 B12 D1 D4 D9 D12 G2 G11

MF-LF

402

1/16W

1K

5%

VRAM8

R9290

1

2

71

71 71

71

GDDR3 Frame Buffer B (Bot)

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

051-7431

A.0.0

9278

PP1V8_S0GPU_ISNS

FB_B1_VREF

FB_B3_VREFFB_B2_VREF

FB_B0_VREF

FB_B_MA<11>

FB_B_MA<10>

FB_B_MA<9>

FB_B_MA<8>

FB_B_MA<7>

FB_B_MA<6>

FB_B_LMA<5>

FB_B_LMA<4>

FB_B_MA<0>

FB_B_LMA<3>

FB_B_MA<1>

PP1V8_S0GPU_ISNS

FB_B_CLK_N<0>

FB_B3_MF

FB_B_DQ<42>

FB_B_DQ<40>

FB_B_DQ<41> FB_B_DQ<45>

FB_B_DQ<46>

FB_B_DQ<55>

FB_B_DQ<53> FB_B_DQ<63> FB_B_DQ<58> FB_B_DQ<61> FB_B_DQ<59> FB_B_DQ<62> FB_B_DQ<56>

FB_B_DQ<36>

FB_B_DQ<57>

FB_B_DQ<60>

FB_B_DQ<39> FB_B_DQ<37> FB_B_DQ<38>

FB_B_DQ<32>

FB_B_DQ<34>

FB_B_DQ<35> FB_B_DQ<33>

FB_B_RDQS<4>

FB_B_RDQS<7>

FB_B_RDQS<6>

FB_B_RDQS<5>

FB_B3_SEN

FB_B_DRAM_RST

FB_B3_ZQ

FB_B_RAS_L

FB_B_CAS_L

FB_B_WE_L

FB_B_CLK_N<1>

FB_B_MA<10>

FB_B_MA<9>

FB_B_CKE FB_B_CLK_P<1>

FB_B_WDQS<7>

FB_B_WDQS<6>

FB_B_WDQS<5>

FB_B_WDQS<4> FB_B_BA<0>

FB_B_BA<2>

FB_B_BA<1>

FB_B_DQM_L<4>

FB_B_DQM_L<7>

FB_B_DQM_L<6>

FB_B_DQM_L<5>

FB_B_MA<11>

FB_B_MA<8>

FB_B_CS1_L

PP1V8_S0GPU_ISNS

FB_B2_MF

FB_B_DQ<8>

FB_B_DQ<9> FB_B_DQ<10>

FB_B_DQ<14> FB_B_DQ<15>

FB_B_DQ<18>

FB_B_DQ<11>

FB_B_DQ<17> FB_B_DQ<19> FB_B_DQ<16> FB_B_DQ<21> FB_B_DQ<23> FB_B_DQ<20> FB_B_DQ<22> FB_B_DQ<2> FB_B_DQ<1> FB_B_DQ<6> FB_B_DQ<0> FB_B_DQ<7> FB_B_DQ<4>

FB_B_DQ<24>

FB_B_DQ<3>

FB_B_DQ<5>

FB_B_DQ<25>

FB_B_DQ<30>

FB_B_DQ<26> FB_B_DQ<27>

FB_B_RDQS<3>

FB_B_RDQS<0>

FB_B_RDQS<2>

FB_B_RDQS<1>

FB_B2_SEN

FB_B_DRAM_RST

FB_B2_ZQ

FB_B_CAS_L

FB_B_WE_L

FB_B_CKE FB_B_CLK_P<0>

FB_B_WDQS<0>

FB_B_WDQS<2>

FB_B_WDQS<1>

FB_B_WDQS<3> FB_B_BA<0>

FB_B_DQM_L<2>

FB_B_DQM_L<1>

FB_B_CS1_L

FB_B_BA<2>

FB_B_BA<1>

FB_B_DQ<31>

FB_B_DQ<29>

FB_B_DQ<28>

FB_B_MA<6> FB_B_MA<7>

FB_B_DQ<43>FB_B_DQ<13>

FB_B_DQ<12>

FB_B_DQM_L<0> FB_B_DQM_L<3>

FB_B_DQ<54>

FB_B_DQ<52>

FB_B_DQ<51>

FB_B_DQ<48>

FB_B_DQ<49> FB_B_DQ<50>

FB_B_DQ<44>

FB_B_DQ<47>

FB_B_MA<1>

FB_B_MA<0>

FB_B_RAS_L

FB_B_LMA<2> FB_B_UMA<2>

FB_B_UMA<3> FB_B_UMA<4> FB_B_UMA<5>

PP1V8_S0GPU_ISNS

78

78 77

77

74

71

71 70

70 70

70 69

69 69

69 68

68 68

68 65

65 65

65 50

50 50

50

8

8 8

8

S

D

G

S

D

G

PGND

PHASE

UG

LG

PVCC

FCCM

EN

PGOOD COMP

FSET

ISEN

FB

VO

BOOT

VIN

THRML

PAD

VCC

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

Vout = 0.6V * (1 + Ra / Rb)

<Ra>

<Rb>

10A max output

Vout = 1.8V

1.8V Frame Buffer Regulator

402

0.0047uF

NO STUFF

10% 25V CERM

C9320

1

2

NO STUFF

0

1/16W

402

5%

MF-LF

R9320

12

X7R

10%

0.22UF

16V 603

C9309

1

2

SI7110DN

PWRPK-1212-8

CRITICAL

Q9320

5

4

1 2 3

SI7108DNS

PWRPK-1212-8

CRITICAL

Q9321

5

4

1 2 3

402

1/16W

1%

5.62K

MF-LF

R9310

1 2

POLY

25V

20% CASE-D2-LF

CRITICAL

22UF

C9330

1

2

2.5V POLY

20%

CRITICAL

330UF

CASE-C2S-HF

C9342

1

2

5% 1/16W

10

MF-LF 402

R9300

1

2

10%

1UF

25V 603

X5R

C9303

1

2

CRITICAL

POLY

2.5V

20%

330UF

CASE-C2S-HF

C9343

1

2

2.2UF

10%

603

16V X5R

C9302

1

2

SM

XW9300

1 2

603

2.2UF

10% 16V X5R

C9300

1

2

10%

1UF

X5R 603

25V

C9301

1

2

CRITICAL

QFN

ISL6269BCRZ

U9300

13

5

4

6

3

7

9

11

10

16

15

12

17

14

2

1

8

5%

CERM

50V

68PF

402-1

C9307

1

2

10% 50V

CERM

680PF

402

C9308

1

2

40.2K

402

1% 1/16W MF-LF

R9308

1

2

1%

30.1K

MF-LF

1/16W 402

R9306

1

2

402

0.01UF

16V

10%

CERM

C9306

1

2

10UF

603

X5R

20%

6.3V

C9341

1

2

603

20% X5R

6.3V

10UF

C9340

1

2

1/16W MF-LF

1%

2.0K

402

R9321

1

2

402

1K

1% 1/16W MF-LF

R9322

1

2

IHLP2525CZ-SM

1.0UH-22A

CRITICAL

L9320

1 2

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

1.8V FB Power Supply

A.0.0

9279

051-7431

P1V8FB_FB_RC

P1V8FB_ISEN

P1V8FB_LG

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.25 mm

P1V8FB_BOOT

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

P1V8FB_UG

PP5V_S5_1V8GPU_VCC

MIN_LINE_WIDTH=0.6 mm MIN_NECK_WIDTH=0.25 mm

PP5V_S5

PPBUS_G3H

P1V8FB_PHASE

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.6 mm SWITCH_NODE=TRUE

P1V8FB_FSET

GND_P1V8FB_SGND

P3V3S5_COMP_R

P1V8FB_COMP

P1V8FB_FB

TP_P1V8_S0GPU_PGOOD

PM_P1V8_S0GPU_EN

PP1V8_S0GPU

82 75 66

75

63

65

62

63

61

62

60

61

59

60

58

57

43

49

42

40

27

8

75

50

8

7

65

8

G

SD

G

SD

SYM_VER-1

IN

OUT

G

SD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

(55mA requirement per DVI spec)

DVI DDC Current Limit

(PP5V_S0_DDC)

514-0278

(DACB TV Y)

(DACB TV COMP)

(DACB TV C)

(Place close to connector)

ANALOG FILTERING

PLACE CLOSE TO CONNECTOR

VGA SYNC Buffers

GPU Isolation / Level-Shift

Isolation required for DVI->ADC Adapter

(Place close to GPU)

TMDS Filtering

DVI INTERFACE

402

MF-LF

1/16W

5%

10K

R9421

1

2

10K

MF-LF 402

5% 1/16W

R9420

1

2

2N7002DW-X-F

SOT-363

Q9411

6

2

1

2N7002DW-X-F

SOT-363

Q9411

3

5

4

1/16W

5%

402

MF-LF

100K

R9422

1

2

100pF

CERM 402

5% 50V

C9413

1

2

1/16W

5%

402

MF-LF

4.7K

R9412

1

2

1/16W

5%

MF-LF

402

4.7K

R9410

1

2

100pF

CERM 402

5% 50V

C9411

1

2

400-OHM-EMI

SM-1

CRITICAL

L9410

1 2

SM-LF

0.5AMP-13.2V

CRITICAL

F9410

1 2

B0530WXF

SOD-123

D9410

1 2

100pF

CERM

402

5%

50V

C9414

1

2

1/16W

5%

402

MF-LF

100

R9411

1 2

100

MF-LF

402

5%

1/16W

R9413

1 2

100

5%

1/16W MF-LF

402

R9414

1 2

50V

0.25% 402

CERM

3.3pF

C9441

1

2

VGA_TERM_FILTER

402

MF-LF

150

1/16W

1%

R9442

1

2

VGA_TERM_FILTER

1/16W

1%

402

MF-LF

150

R9440

1

2

VGA_TERM_FILTER

MF-LF

402

1%

1/16W

150

R9441

1

2

50V

0.25%

402

CERM

3.3pF

C9442

1

2

3.3pF

CERM 402

0.25% 50V

C9440

1

2

33

MF-LF

402

5%

1/16W

R9450

1 2

1/16W

33

MF-LF

402

5%

R9451

1 2

CRITICAL

QH11121-RIG02-4F

F-RT-TH-DVI

J9400

C1

C2

C3

C4

C5AC5B

31

32

33

34

1

10

11

12

13

14

15

16

17

18

19

2

20

21

22

23

24

3

4

5

6

7

8

9

402

1/16W

5% MF-LF

20K

R9415

1

2

1/16W

1%

49.9

SIGNAL_MODEL=EMPTY

402

MF-LF

NO STUFF

R9486

1

2

MF-LF

402

1%

1/16W

NO STUFF

49.9

SIGNAL_MODEL=EMPTY

R9482

1

2

SIGNAL_MODEL=EMPTY

NO STUFF

1/16W

402

MF-LF

1%

49.9

R9478

1

2

1/16W

5%

402

MF-LF

0

R9473

1 2

5%

0

MF-LF

402

1/16W

R9472

1 2

MF-LF

NO STUFF

SIGNAL_MODEL=EMPTY

49.9

1/16W

1%

402

R9470

1

2

NO STUFF

SIGNAL_MODEL=EMPTY

49.9

1%

402

MF-LF

1/16W

R9466

1

2

SM

CRITICAL

370-OHM

PLACEMENT_NOTE=Place close to connector.

L9472

1

2 3

4

0.1uF

CERM

402

20% 10V

C9451

1

2

0.1uF

CERM

402

20% 10V

C9450

1

2

PLACEMENT_NOTE=Place close to connector.

MC74VHC1G08

SC70

U9450

3

2

1

4

5

PLACEMENT_NOTE=Place close to connector.

MC74VHC1G08

SC70

U9451

3

2

1

4

5

MF-LF

402

SIGNAL_MODEL=EMPTY

NO STUFF

49.9

1/16W

1%

R9462

1

2

90-OHM-100MA

CRITICAL

PLACEMENT_NOTE=Place close to connector.

DLP11S

L9460

1 2

34

90-OHM-100MA

CRITICAL

DLP11S

PLACEMENT_NOTE=Place close to connector.

L9464

1 2

34

90-OHM-100MA

CRITICAL

DLP11S

PLACEMENT_NOTE=Place close to connector.

L9468

1 2

34

CRITICAL

DLP11S

90-OHM-100MA

PLACEMENT_NOTE=Place close to connector.

L9480

1 2

34

90-OHM-100MA

CRITICAL

DLP11S

PLACEMENT_NOTE=Place close to connector.

L9476

1 2

34

DLP11S

90-OHM-100MA

CRITICAL

PLACEMENT_NOTE=Place close to connector.

L9484

1 2

34

74 90

73 90

73 74

72 73

16V 402

CERM

10%

0.01UF

NO STUFF

C9462

1

2

NO STUFF

0.01UF

CERM

402

10% 16V

C9466

1

2

10%

402

CERM

NO STUFF

0.01UF

16V

C9470

1

2

16V

0.01UF

10%

402

CERM

NO STUFF

C9478

1

2

16V

0.01UF

10%

402

NO STUFF

CERM

C9482

1

2

NO STUFF

CERM

402

10%

0.01UF

16V

C9486

1

2

NO STUFF

CERM

402

10%

0.01UF

16V

C9474

1

2

SIGNAL_MODEL=EMPTY

1/16W

1%

402

MF-LF

NO STUFF

49.9

R9474

1

2

CRITICAL

210MHZ

MEA2010P-SM

FL9440

27

36

45

18

NO STUFF

1/16W

49.9

1%

MF-LF

402

R9463

12

402

MF-LF1/16W

1%

49.9

NO STUFF

R9467

12

1%

402

MF-LF1/16W

49.9

NO STUFF

R9471

12

49.9

1%

1/16W MF-LF

402

NO STUFF

R9475

12

402

MF-LF1/16W

1%

49.9

NO STUFF

R9479

12

402

MF-LF1/16W

1%

49.9

NO STUFF

R9483

12

402

MF-LF

1%

49.9

NO STUFF

1/16W

R9487

12

VGA_TERM_CONN

402

MF-LF

150

1/16W

1%

R9443

1

2

VGA_TERM_CONN

1/16W MF-LF

1%

150

402

R9445

1

2

VGA_TERM_CONN

1%

1/16W

150

MF-LF

402

R9444

1

2

2N7002DW-X-F

SOT-363

Q9414

3

5

4

10K

402

5%

MF-LF

1/16W

R9416

1 2

0.01uF

CERM

603

20% 50V

C9410

1

2

SYNC_DATE=MASTER

SYNC_MASTER=MASTER

DVI Display Connector

80 92

A.0.0

051-7431

PP3V3_S0GPU_TMDS

TMDS_DATA_N<1>

TMDS_DATA_F_P<2>

TMDS_DATA_F_P<4>

TMDS_DATA_N<3>

TMDS_DATA_F_P<5>

TMDS_DATA_N<5>

TMDS_DATA_F_N<5>

TMDS_DATA_P<5>

TMDS_DATA_N<4>

TMDS_DATA_F_N<4>

TMDS_DATA_P<4>

TMDS_DATA_F_N<3>

TMDS_DATA_P<3>

TMDS_DATA_F_P<3>

TMDS_DATA_N<2>

TMDS_DATA_F_N<2>

TMDS_DATA_P<2>

TMDS_DATA_F_N<1>

TMDS_DATA_P<1>

TMDS_DATA_F_P<1>

TMDS_DATA_N<0>

TMDS_DATA_F_N<0>

TMDS_DATA_P<0>

TMDS_DATA_F_P<0>

GPU_HPD

DVI_HOTPLUG_DET

PP3V3_S0GPU

GPU_DVI_DDC_CLK

PP3V3_S0GPU_TMDS

VGA_B

VGA_G

GPU_TV_C_VGA_R

TMDS_CLK_F_N

GPU_TV_Y_VGA_G

PP5V_S0_DDC_PULLUPS

MIN_LINE_WIDTH=0.25 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

VGA_VSYNC

TMDS_CLK_F_P

TMDS_CLK_F_N

TMDS_DATA_F_N<0>

TMDS_DATA_F_P<0>

TMDS_DATA_F_N<4>TMDS_DATA_F_N<5>

TMDS_DATA_F_P<5>

VGA_VSYNC

VGA_VSYNC_R

VGA_HSYNC

VGA_HSYNC_R

TMDS_CLK_F_P

VGA_B

VGA_R

GPU_TV_COMP_VGA_B

VGA_G

PP3V3_S0GPU

GPU_VGA_HSYNC

GPU_VGA_VSYNC

PP3V3_S0GPU_TMDS

VGA_HSYNC

TMDS_DATA_F_P<3>

TMDS_CLK_R_N

TMDS_CLK_P

PP3V3_S0GPU_TMDS

TMDS_CLK_N

TMDS_CLK_R_P

PP3V3_S0GPU_TMDS

TMDS_DATA_F_P<2> TMDS_DATA_F_P<1>

TMDS_DATA_F_N<3> TMDS_DATA_F_P<4>

DVI_DDC_CLK_R

DVI_HPD_R

MIN_LINE_WIDTH=0.38 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

PP5V_S0_DDC

PP3V3_S0GPU_TMDS

TMDS_DATA_F_N<2> TMDS_DATA_F_N<1>

VGA_R

DVI_DDC_DATA

DVI_DDC_CLK

GPU_DVI_DDC_DATA

PP3V3_S0GPU

DVI_HPD

DVI_DDC_DATA_R

PP5V_S0

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.38 mm

PP5V_S0_DDC_F

VOLTAGE=5V

82 81 65

80

59

76

58

75

54

74

52

73

49

72

47

80

65

80

65

42

74

58

74

58

27

73

91

48

91

91 91

91

48

73

91

48

8

80

24

8

80

80 80

80

91

80

91

80

8

80

91

80

8

7

BI BI

IN

OUT

BI

SYM_VER-1

OUT

IN

BI BI

OUT

BI BI

IN

OUT

IN

SYM_VER-1

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

518S0369

PBUS GND

PWM

LED Backlight

+5V/EN

Classic Inverter/

NC

516S0350

Backlight Connector

Bluetooth (M13P) & SATA HDD Flex Connector

IR & Sleep LED Connector

518S0474

Top-Case Connector

NC NC

516S0350

7

24 86

CRITICAL

M-ST-SM

QT500166-L020

J9660

1

10

1112 1314 1516

2

34 56 78 9

7

24 86

23 86

PLACEMENT_NOTE=Place C9661 next to C9660

402

25V

CERM

0.0047uF

10%

C9661

2 1

10% 25V

0.0047uF

CERM

402

PLACEMENT_NOTE=Place C9660 close to southbridge

C9660

2 1

7

46

23 86

24 86

1210-4SM1

90-OHM-100MA

CRITICAL

PLACEMENT_NOTE=Place FL9665 close to southbridge

FL9665

1

2 3

4

PLACEMENT_NOTE=Place FL9660 close to J9660

1210-4SM1

90-OHM-100MA

CRITICAL

FL9660

1

2 3

4

10%

PLACEMENT_NOTE=Place C9666 close to J9660

25V

0.0047uF

402

CERM

C9666

2 1

PLACEMENT_NOTE=Place C9666 next to C9665

0.0047uF

10%

CERM

25V 402

C9665

2 1

M-RT-SM

CRITICAL

HS8806F-B

J9610

7

8

1 2 3 4 5 6

54

34 45 48 51 88

QT500166-L020

CRITICAL

M-ST-SM

J9600

1

10 11 12 13 14 15 16

2

3 4 5 6 7 8 9

45 46

7

45 46

24 86

CRITICAL

SC-75

RCLAMP0502B

D9600

3

1

2

7

82

7

82

7

82

7

82

SM04B-ACH

M-RT-SM

J9650

5

6

1 2 3 4

SM

0.01H-0.3A-80V

CRITICAL

FL9600

1

2 3

4

Project Specific Connectors

SYNC_MASTER=(MASTER)

81 92

A.0.0

051-7431

SYNC_DATE=(MASTER)

PP5V_S3

TPAD_GND MIN_LINE_WIDTH=0.6MM MIN_NECK_WIDTH=0.2MM

SMC_ONOFF_L

VOLTAGE=5V

MIN_NECK_WIDTH=0.2MM

MIN_LINE_WIDTH=0.6MM

PP5V_S3_TOPCASE_F

SMC_LID

SMBUS_SMC_A_S3_SDA SMBUS_SMC_A_S3_SCL

GND KBDLED_ANODE

USB_TPAD_N

USB_TPAD_P

PP3V3_S3 PP3V42_G3H

SYS_LED_ANODE

USB_IR_P

USB_IR_N

PP5V_S3

SATA_A_D2R_P

SATA_A_D2R_UF_N

SATA_A_D2R_UF_P

SATA_A_R2D_UF_P

SATA_A_R2D_UF_N

SATA_A_R2D_N

SATA_A_D2R_A_P

SATA_A_D2R_N

PP3V3_S3

SATA_A_D2R_A_N

PP5V_S0

USB_BT_N USB_BT_P

SATA_A_R2D_C_P

SATA_A_R2D_P

SATA_A_R2D_C_N

BKLT_PWR

BKLT_PWM

BKLT_GND BKLT_P5V_EN

82 80

81

66

81

65

59

58

57

58

55

48

55

54

47

54

52

81

51

46

81

51

49

58

50

45

58

50

47

46

48

43

46

48

42

44

38

28

44

38

27

8

36

8

36

8

7

8

7

91

86

8

7

86

IN

P-CHN

SGD

D

S

G

N-CHN

OUT

IN

D

G S

IN

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

R9807 is top end of resistor divider. Bottom end is on LED board

PLT_RST_L input ensures backlight PWM does not glitch during RESET.

not run if backlight is not powered/enabled

LCDBKLT_PWREN input ensures backlight PWM does

.

9

72 73

BKLT_5V_PWR

NTZD3155C

SOT-563

Q9805

3

5

4

BKLT_5V_PWR

NTZD3155C

SOT-563

Q9805

6

2

1

603

2AMP-32V-44MOHM

F9800

1 2

0.001uF

20% 50V CERM 402

C9892

1

2

0.001uF

50V 402

CERM

20%

C9893

1

2

0.001uF

20% 50V CERM 402

C9894

1

2

7

81

7

81

7

81

7

81

MC74VHC1G08

SC70

U9801

3

2

1

4

5

0.1uF

402

10V

20%

CERM

C9801

1

2

OMIT

603

SHORT

RX9892

1 2

200K

MF-LF

5%

402

1/16W

R9808

1

2

100K

1/16W MF-LF

5%

402

R9809

1

2

16V

0.033UF

10% X5R

402

C9802

1

2

5.1K

1/16W MF-LF

5%

402

BKLT_3V_SIG

R9807

1

2

FDMA530PZ

MICROFET

Q9806

1 2 5 6

7

3

4 8

SOD-VESM

SSM3K15FV

Q9807

3

1

2

0402

CRITICAL

FERR-120-OHM-1.5A

L9891

1 2

0402

CRITICAL

FERR-120-OHM-1.5A

L9893

1 2

0402

CRITICAL

FERR-120-OHM-1.5A

L9894

1 2

6.3V

0.33UF

CERM-X5R 402

BKLT_3V_SIG

10%

C9807

1

2

402-LF

20% CERM

2.2UF

6.3V

BKLT_5V_PWR

C9805

1

2

1%

51.1K

1/16W 402

MF-LF

BKLT_5V_PWR

R9810

1

2

MF-LF 402

1/16W

51.1K

1%

BKLT_5V_PWR

R9805

2

1

BKLT_5V_PWR

1/16W

5%

402

MF-LF

100K

R9806

1

2

9

72 73

SC70

MC74VHC1G08

U9800

3

2

1

4

5

CERM

20% 10V

402

0.1uF

C9800

1

2

7 9

24 28

051-7431

A.0.0

9282

LCD Backlight Support

SYNC_MASTER=M87_LIO

SYNC_DATE=12/06/2007

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_FUSED

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm

BKLT_PWR

VOLTAGE=12.6V

MIN_LINE_WIDTH=0.4 mm MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

BKLT_P5V_EN

PPBUS_G3H

BKLT_PWM

LCDBKLT_PWM

LCDBKLT_PWM_RSTGATED

PP3V3_S0

PLT_RST_L

GPU_BL_PWM

MIN_NECK_WIDTH=0.25 mm

MIN_LINE_WIDTH=0.4 mm

BKLT_GND

VOLTAGE=0V

MIN_LINE_WIDTH=0.4 mm

PPBUS_S0_LCDBKLT_SW

MIN_NECK_WIDTH=0.25 mm VOLTAGE=12.6V

GPU_BKLT_EN

MIN_NECK_WIDTH=0.25 mm VOLTAGE=5V

MIN_LINE_WIDTH=0.4 mm

PP5V_SW_LCDBKLT

LCDBKLT_PWREN_L

LCDBKLT_PWREN_SW_L

PP5V_S0

PPBUS_S0_LCDBKLT_EN_DIV

PPBUS_S0_LCDBKLT_EN_L

91 65 59 58 53 52 51 50 48 47 46 42 32

79

31

75

30

81

66

29

80

63

28

65

62

27

59

61

26

58

60

25

54

59

24

52

58

23

49

57

21

47

49

19

42

40

16

27

8

13

8

7

8

7

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

FSB (Front-Side Bus) Constraints

Design Guide recommends each strobe/signal group is routed on the same layer.

CPU Signal Constraints

Most CPU signals with impedance requirements are 55-ohm single-ended. Some signals require 27.4-ohm single-ended impedance.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.4 & 5.8.2.4

NOTE: Design Guide does not indicate FSB spacing to other signals, assumed 3:1.

DSTB complementary pairs are spaced 1:1 and routed as differential pairs.

Worst-case spacing is 2:1 within Addr bus, with 3:1 spacing to the ADSTBs.

(See above)

CPU / FSB Net Properties

PHYSICAL

NET_TYPE

SPACING

DG recommends at least 25 mils, >50 mils preferred

Worst-case spacing is 2:1 within Data bus, with 3:1 spacing to the DSTBs.

Design Guide recommends FSB signals be routed only on internal layers.

NOTE: Design Guide allows closer spacing if signal lengths can be shortened.

All FSB signals with impedance requirements are 55-ohm single-ended.

SOURCE: Santa Rosa Platform DG, Rev 0.9 (#20517), Sections 4.2 & 4.3

ELECTRICAL_CONSTRAINT_SET

(See above)

NOTE: 7 mil gap is for VCCSense pair, which Intel says to route with 7 mil spacing without specifying a target differential impedance.

(See above)

(FSB_CPURST_L)

=2:1_SPACING

?

CPU_2TO1

*

=3:1_SPACING

FSB_DATA

*

?

CPU_55S

=55_OHM_SE=55_OHM_SE

*

=55_OHM_SE

Y =STANDARD =STANDARD

=2:1_SPACING

?

*

CPU_ITP

FSB_DSTBFSB_DATA

*

FSB_DATA2DSTB

FSB_ADDR2ADDR

*

FSB_ADDR FSB_ADDR

FSB_DATA2DATA

FSB_DATA

*

FSB_DATA

?

=2:1_SPACING

*

FSB_COMMON

?

FSB_ADDR

=3:1_SPACING

*

FSB_ADDR2ADSTB

FSB_ADDR

FSB_ADSTB

*

=3:1_SPACING

*

FSB_DSTB

?

*

FSB_DATA2DSTB

?

=3:1_SPACING

SYNC_DATE=01/25/2007

CPU/FSB Constraints

SYNC_MASTER=T9_NOME

83 92

A.0.0

051-7431

=55_OHM_SE

FSB_55S

=STANDARD

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=STANDARD

?

=3:1_SPACING

FSB_ADSTB

*

?

=3:1_SPACING

*

FSB_ADDR2ADSTB

?

=2:1_SPACING

FSB_ADDR2ADDR

*

?

CPU_VCCSENSE

*

25 MIL

?

CPU_COMP

*

?

*

CPU_GTLREF

25 MIL

* Y

=27P4_OHM_SE =27P4_OHM_SE =27P4_OHM_SE

CPU_27P4S

7 MIL 7 MIL

*

FSB_DATA2DATA

?

=2:1_SPACING

=1:1_DIFFPAIR

FSB_DSTB_55S

=1:1_DIFFPAIR=1:1_DIFFPAIR

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

CPU_2TO1

CPU_VID<6..0>

CPU_55S

CPU_55S CPU_ITP

XDP_TDI

CPU_55S CPU_ITP

XDP_TDO

CPU_55S CPU_ITP

XDP_TMS

CPU_55S CPU_ITP

XDP_TCK

CPU_55S CPU_ITP

XDP_TRST_L

XDP_BPM_L<4..0>

XDP_BPM_L

CPU_ITPCPU_55S

IMVP6_VSEN_P

CPU_VCCSENSE

CPU_27P4S CPU_27P4S

IMVP6_VSEN_N

CPU_VCCSENSE

CPU_VCCSENSE_P

CPU_VCCSENSE

CPU_27P4S

CPU_VCCSENSE

CPU_VCCSENSE_N

CPU_VCCSENSE

CPU_27P4S

IMVP6_VID<6..0>

CPU_2TO1

CPU_55S

CPU_ITPCPU_55S

XDP_CPURST_L

XDP_CLK_P

CLK_FSB_100D

CLK_FSB CLK_FSB

CLK_FSB_100D

XDP_CLK_N

CPU_55S CPU_ITP

XDP_BPM_L5

XDP_BPM_L<5>

CPU_55S

NB_BSEL<2>

CPU_2TO1

CPU_COMP<3>

CPU_COMP

CPU_55S

CPU_COMP

NB_BSEL<0>

CPU_2TO1

CPU_55S

CPU_GTLREF

CPU_2TO1

CPU_55S

IMVP_DPRSLPVR

PM_DPRSLPVR

CPU_2TO1

PM_DPRSLPVR

CPU_55S

FSB_CPUSLP_L

CPU_55S

FSB_CPUSLP_L

PM_THRMTRIP_L

CPU_2TO1

CPU_55S

PM_THRMTRIP_L

CPU_FROM_SB

CPU_IGNNE_L

CPU_55S

CPU_IERR_L

CPU_55S

CPU_IERR_L

CPU_55S

CPU_BSEL2

CPU_2TO1

CPU_BSEL<2>

CPU_2TO1

CPU_BSEL<1>

CPU_BSEL1

CPU_55S

FSB_DATA

FSB_DATA_GROUP2

FSB_D_L<47..32>

FSB_55S

FSB_DATA_GROUP1

FSB_DATA

FSB_D_L<31..16>

FSB_55S

FSB_COMMON

FSB_TRDY_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_55S

FSB_BPRI_L

FSB_COMMON

FSB_ADS_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_55S

FSB_DBSY_L

FSB_COMMON

FSB_55S

FSB_BREQ0_L

FSB_COMMON

FSB_DATA_GROUP0

FSB_55S

FSB_DATA

FSB_DINV_L<0>

FSB_COMMON

FSB_RS_L<2..0>

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_LOCK_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DRDY_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DPWR_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_HITM_L

FSB_COMMON

FSB_55S

FSB_CPURST_L

FSB_COMMON

FSB_55S

FSB_COMMON

FSB_DEFER_L

FSB_COMMON

FSB_55S

FSB_ADDR

FSB_ADDR_GROUP0

FSB_55S

FSB_REQ_L<4..0>

FSB_DSTB_L_P<3>

FSB_DSTB

FSB_DSTB3

FSB_DSTB_55S

FSB_D_L<63..48>

FSB_DATA_GROUP3

FSB_55S

FSB_DATA

FSB_DSTB

FSB_DSTB_L_N<0>

FSB_DSTB_55S

FSB_DSTB0

FSB_DSTB

FSB_DSTB_L_P<0>

FSB_DSTB_55S

FSB_COMMON

FSB_BNR_L

FSB_COMMON

FSB_55S

FSB_DINV_L<3>

FSB_DATA_GROUP3

FSB_55S

FSB_DATA

FSB_DSTB_L_N<1>

FSB_DSTBFSB_DSTB_55S

FSB_55S

FSB_DATA_GROUP0

FSB_DATA

FSB_D_L<15..0>

FSB_DSTB1

FSB_DSTB

FSB_DSTB_L_P<1>

FSB_DSTB_55S

FSB_DATA_GROUP1

FSB_DATA

FSB_55S

FSB_DINV_L<1>

FSB_COMMON

FSB_HIT_L

FSB_55S

FSB_COMMON

FSB_DINV_L<2>

FSB_DATA_GROUP2

FSB_DATA

FSB_55S

FSB_DSTB_L_P<2>

FSB_DSTB

FSB_DSTB2

FSB_DSTB_55S

FSB_DSTB_L_N<2>

FSB_DSTB_55S FSB_DSTB

FSB_DSTB_L_N<3>

FSB_DSTBFSB_DSTB_55S

FSB_ADDR_GROUP0

FSB_55S

FSB_A_L<16..3>

FSB_ADDR

FSB_ADSTB

FSB_ADSTB1

FSB_ADSTB_L<1>

FSB_55S

FSB_A_L<35..17>

FSB_ADDR_GROUP1

FSB_55S

FSB_ADDR

FSB_55S

FSB_ADSTB

FSB_ADSTB_L<0>

FSB_ADSTB0

CPU_FERR_L

CPU_55S

CPU_PROCHOT_L

CPU_2TO1

CPU_55S

CPU_PWRGD

CPU_55S

CPU_PWRGD

CPU_55S

CPU_INTR

CPU_FROM_SB

CPU_NMI

CPU_55S

CPU_FROM_SB CPU_FROM_SB

CPU_A20M_L

CPU_55S

CPU_INIT_L

CPU_INIT_L CPU_FROM_SB

CPU_SMI_L

CPU_55S

CPU_COMP

CPU_27P4S

CPU_COMP<0>

CPU_COMP

CPU_55S

CPU_STPCLK_L

CPU_FROM_SB

CPU_BSEL0

CPU_BSEL<0>

CPU_2TO1

CPU_55S

CPU_FROM_SB

CPU_DPSLP_L

CPU_55S

CPU_COMPCPU_COMP

CPU_COMP<1>

CPU_55S

CPU_COMP<2>

CPU_COMP CPU_COMP

CPU_27P4S

CPU_DPRSTP_L

CPU_55S

CPU_2TO1

CPU_DPRSTP_L

NB_BSEL<1>

CPU_55S

CPU_2TO1

59

88

59

46

14

23

59

30

25

14

23

14

13

14

59

13

47

23

16

30

12

13

59

12

29

13

16

59

16

10

16

23

30

10

14

10

14

10

14

10

23

46

10

23

10

30

10

16

11

10

59

11

7

13

10

13

10

13

10

7

10

7

10

7

10

7

10

7

10

7

10

7

10

7

10

7

13

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

DG Says 30 mil spacing minimum

DG Says 40 mil spacing minimum

Video Signal Constraints

PCI-Express / DMI Bus Constraints

ELECTRICAL_CONSTRAINT_SET

PHYSICAL

SPACING

NET_TYPE

DG Says 40 mil spacing minimum

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 7.2, 9.2 & 10.5

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 8.1 - 8.3.

CRT & TVDAC signal single-ended impedence varies by location:

CRT_HSYNC/CRT_VSYNC signals are 55-ohm +/- 15% single-ended impedence.

- 55-ohm +/- 15% from second termination resistor to connector.

- 50-ohm +/- 15% from first to second termination resistor.

- 37.5-ohm +/- 15% from GMCH to first termination resistor.

LVDS signals are 100-ohm +/- 20% differential impedence.

TVDAC_2TVDAC

*

?

20 MIL

*

?

CRT_SYNC2SYNC

20 MIL

CRT 25 MIL

*

?

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

LVDS_100D

=100_OHM_DIFF

20 MIL

LVDS

*

?

TVDAC

25 MIL

*

?

CRT_2CRT

*

?

20 MIL

CRT_2CRT

CRTCRT

*

NB Constraints

SYNC_DATE=01/25/2007

84 92

A.0.0

051-7431

SYNC_MASTER=T9_NOME

DMI 20 MIL

?

*

?

*

25 MIL

CRT_SYNC

TVDAC_2TVDAC

TVDACTVDAC

*

CRT_SYNC CRT_SYNC

CRT_SYNC2SYNC

=100_OHM_DIFF

*

=100_OHM_DIFF

DMI_100D

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

=50_OHM_SE =50_OHM_SE=50_OHM_SE

=STANDARD* =STANDARD

=50_OHM_SE

CRT_50S

=100_OHM_DIFF

PCIE_100D

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

*

=100_OHM_DIFF

=55_OHM_SE =55_OHM_SE=55_OHM_SE

CRT_55S

=55_OHM_SE

=STANDARD* =STANDARD

20 MIL

PCIE

*

?

LVDS_B_DATA

LVDS_B_DATA_N<2..0>

LVDS

LVDS_100D

LVDS_B_DATA

LVDS_B_DATA_P<2..0>

LVDS

LVDS_B_CLK

NC_LVDS_B_CLKN

LVDS

LVDS_100D

CRT_SYNC

CRT_55S

CRT_SYNC

CRT_HSYNC_R

PCIE

PCIE_100D

PEG_D2R_C_P<15..0>

DMI_100D

DMI_N2S

DMI

DMI_N2S_P<3..0>

LVDS_B_DATA3

LVDS_B_DATA_P<3>

LVDS_100D

LVDS

LVDS_100D

LVDS_B_CLK

NC_LVDS_B_CLKP

LVDS

LVDS_A_DATA3

LVDS_A_DATA_P<3>

LVDS

LVDS_100D

LVDS_A_DATA3

LVDS_A_DATA_N<3>

LVDS

LVDS_100D

PCIE

PCIE_100D

PEG_R2D

PEG_R2D_P<15..0>

PCIE

PCIE_100D

PEG_R2D_N<15..0>

PCIE

PCIE_100D

PEG_D2R

PEG_D2R_P<15..0>

LVDS_A_CLK

NC_LVDS_A_CLKP

LVDS

LVDS_100D

LVDS_A_DATA

LVDS_A_DATA_N<2..0>

LVDS_100D

LVDS

LVDS_A_DATA

LVDS_A_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_A_CLK

NC_LVDS_A_CLKN

LVDS_100D

PCIE

PCIE_100D

PEG_R2D_C_P<15..0>

PCIE

PCIE_100D

PEG_R2D_C_N<15..0>

PCIE_100D

PEG_D2R_C_N<15..0>

PCIE

PCIE_100D

PEG_D2R_N<15..0>

LVDS_B_DATA3 LVDS

LVDS_100D

LVDS_B_DATA_N<3>

LVDS_IBG

NC_LVDS_IBG

LVDS

DMI

DMI_100D

DMI_S2N_N<3..0>

DMI

DMI_100D

DMI_S2N_P<3..0>

DMI_S2N

DMI_100D

DMI

DMI_N2S_N<3..0>

CRT

CRT_TVO_IREF

CRT_BLUE

CRT

CRT_50S

CRT_BLUE

CRT_GREEN

CRT

CRT_50S

CRT_GREEN

CRT_RED

CRT

CRT_50S

CRT_RED

CRT_50S

TV_B_DAC

TVDAC

TV_B_DAC

CRT_50S

TV_C_DAC

TVDAC

TV_C_DAC

CRT_SYNC

CRT_55S

CRT_SYNC

CRT_VSYNC_R

TVDAC

CRT_50S

TV_A_DAC

22

24

22

67

22

67

22

24

15

67

16

15

67

15

67

15

16

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

DDR2 Memory Bus Constraints

Need to support MEM_*-style wildcards!

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 6.2

SPACING

NET_TYPE

Memory Net Properties

MEM_2OTHER

MEM_CTRL

* *

MEM_2OTHER

MEM_CMD

**

MEM_2OTHER

MEM_DATA

* *

MEM_2OTHER

MEM_DQS

**

MEM_DQS

MEM_DQS2MEM

*

MEM_DATA

*

MEM_DQS2MEM

MEM_DQS MEM_CMD

MEM_DQS

MEM_DQS2MEM

*

MEM_CLK

*

MEM_CMD

MEM_CMD2MEM

MEM_CTRL

*

MEM_CLK

MEM_CLK2MEM

MEM_CMD

*

MEM_DQS2MEM

MEM_DQS MEM_DQS

MEM_DATA2DATA

MEM_DATAMEM_DATA

*

MEM_DATA2MEM

MEM_DATA

*

MEM_DQS

MEM_DATA2MEM

MEM_DATA

*

MEM_CMD

*

=4:1_SPACING

MEM_CLK2MEM

?

*

MEM_CLK2MEM

MEM_CLKMEM_CLK

MEM_CLK2MEM

MEM_CLK

*

MEM_DATA

=85_OHM_DIFF

MEM_85D

=85_OHM_DIFF

=85_OHM_DIFF*

=85_OHM_DIFF

25 MIL

MEM_2OTHER

*

?

MEM_2OTHER

MEM_CLK

**

*

MEM_CLK2MEM

MEM_CTRL

MEM_CLK

MEM_CMD2CMD

*

=1.5:1_SPACING

?

*

MEM_CLK

MEM_CLK2MEM

MEM_DQS

MEM_DQS2MEM

*

MEM_CTRL

MEM_CMD

*

MEM_CTRL2MEM

MEM_CTRL

*

MEM_DATA

MEM_DATA2MEM

MEM_CTRL

MEM_CTRL2MEM

*

=3:1_SPACING

?

MEM_DQS

MEM_CTRL

*

MEM_CTRL2MEM

MEM_DATA

MEM_CTRL2MEM

*

MEM_CTRL

MEM_CMD

*

MEM_CMD2MEM

MEM_CLK

=70_OHM_DIFF

=70_OHM_DIFF=70_OHM_DIFF =70_OHM_DIFF

* =70_OHM_DIFF =70_OHM_DIFF

MEM_70D

=55_OHM_SE =55_OHM_SE =55_OHM_SE

*

MEM_55S

=STANDARD =STANDARD

=55_OHM_SE

=45_OHM_SE =45_OHM_SE =45_OHM_SE

MEM_45S

=STANDARD

=45_OHM_SE

=STANDARD*

85 92

A.0.0

051-7431

Memory Constraints

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

*

MEM_CMD

MEM_CMD2MEM

MEM_DATA

MEM_CTRL2CTRL

MEM_CTRL

*

MEM_CTRL

*

MEM_DATA2MEM

MEM_DATA

MEM_CLK

=1.5:1_SPACING

MEM_DATA2DATA

*

?

MEM_DQS2MEM

*

=3:1_SPACING

?

MEM_CTRL

MEM_CTRL2MEM

MEM_CLK

*

MEM_CMD2MEM

MEM_CMD

*

MEM_DQS

*

MEM_CMD MEM_CMD

MEM_CMD2CMD

MEM_CMD2MEM

*

=3:1_SPACING

?

MEM_CTRL2CTRL

=2:1_SPACING

*

?

MEM_DATA2MEM =3:1_SPACING

*

?

MEM_CTRL

MEM_45S

MEM_ODT<3..2>

MEM_B_CNTL

MEM_CMDMEM_55S

MEM_B_CMD

MEM_B_BS<2..0>

MEM_CMDMEM_55S

MEM_B_RAS_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_CAS_L

MEM_B_CMD

MEM_A_DQS_N<6>

MEM_DQSMEM_85D

MEM_A_DQS7

MEM_A_DQS_P<7>

MEM_DQSMEM_85D

MEM_70D MEM_CLK

MEM_B_CLK

MEM_CLK_P<5..3>

MEM_A_DQS_N<7>

MEM_85D MEM_DQS

MEM_CLK_P<2..0>

MEM_A_CLK

MEM_70D MEM_CLK

MEM_A_DM<5>

MEM_55S

MEM_DATA

MEM_A_DM5

MEM_A_DM<7>

MEM_A_DM7

MEM_55S

MEM_DATA

MEM_A_DQ<47..40>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE5

MEM_A_DQ<39..32>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE4

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE3

MEM_A_DQ<31..24>

MEM_A_CMD

MEM_A_RAS_L

MEM_55S MEM_CMD

MEM_55S

MEM_A_CMD

MEM_A_BS<2..0>

MEM_CMD

MEM_55S

MEM_A_CMD

MEM_A_A<14..0>

MEM_CMD

MEM_A_CNTL

MEM_ODT<1..0>

MEM_CTRL

MEM_45S

MEM_A_CNTL

MEM_CS_L<1..0>

MEM_45S

MEM_CTRL

MEM_CLK_N<2..0>

MEM_CLKMEM_70D

MEM_DQSMEM_85D

MEM_B_DQS_N<7>

MEM_DQSMEM_85D

MEM_B_DQS_N<6>

MEM_DQSMEM_85D

MEM_B_DQS7

MEM_B_DQS_P<7>

MEM_DQSMEM_85D

MEM_B_DQS_N<5>

MEM_DQSMEM_85D

MEM_B_DQS6

MEM_B_DQS_P<6>

MEM_DQSMEM_85D

MEM_B_DQS5

MEM_B_DQS_P<5>

MEM_DQSMEM_85D

MEM_B_DQS4

MEM_B_DQS_P<4>

MEM_DQSMEM_85D

MEM_B_DQS_N<4>

MEM_DQSMEM_85D

MEM_B_DQS3

MEM_B_DQS_P<3>

MEM_DQSMEM_85D

MEM_B_DQS_N<3>

MEM_DQSMEM_85D

MEM_B_DQS_N<2>

MEM_DQSMEM_85D

MEM_B_DQS_N<1>

MEM_DQSMEM_85D

MEM_B_DQS2

MEM_B_DQS_P<2>

MEM_DQSMEM_85D

MEM_B_DQS_N<0>

MEM_DQSMEM_85D

MEM_B_DQS1

MEM_B_DQS_P<1>

MEM_DQSMEM_85D

MEM_B_DQS0

MEM_B_DQS_P<0>

MEM_55S

MEM_DATA

MEM_B_DM7

MEM_B_DM<7>

MEM_55S

MEM_DATA

MEM_B_DM6

MEM_B_DM<6>

MEM_55S

MEM_DATA

MEM_B_DM4

MEM_B_DM<4>

MEM_55S

MEM_DATA

MEM_B_DM5

MEM_B_DM<5>

MEM_55S

MEM_DATA

MEM_B_DM3

MEM_B_DM<3>

MEM_55S

MEM_DATA

MEM_B_DM1

MEM_B_DM<1>

MEM_55S

MEM_DATA

MEM_B_DM2

MEM_B_DM<2>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE7

MEM_B_DQ<63..56>

MEM_DATA

MEM_55S

MEM_B_DM0

MEM_B_DM<0>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE5

MEM_B_DQ<47..40>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE6

MEM_B_DQ<55..48>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE4

MEM_B_DQ<39..32>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE2

MEM_B_DQ<23..16>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE3

MEM_B_DQ<31..24>

MEM_DATA

MEM_55SMEM_B_DQ_BYTE0

MEM_B_DQ<7..0>

MEM_55S

MEM_DATA

MEM_B_DQ_BYTE1

MEM_B_DQ<15..8>

MEM_CMDMEM_55S

MEM_B_WE_L

MEM_B_CMD

MEM_CMDMEM_55S

MEM_B_A<14..0>

MEM_B_CMD

MEM_CTRL

MEM_45S

MEM_CS_L<3..2>

MEM_B_CNTL

MEM_CKE<4..3>

MEM_CTRL

MEM_45S

MEM_B_CNTL

MEM_70D MEM_CLK

MEM_CLK_N<5..3>

MEM_A_DQS6

MEM_A_DQS_P<6>

MEM_DQSMEM_85D

MEM_A_DQS5

MEM_A_DQS_P<5>

MEM_DQSMEM_85D

MEM_A_DQS_N<4>

MEM_DQSMEM_85D

MEM_A_DQS_N<5>

MEM_DQSMEM_85D

MEM_A_DQS_N<3>

MEM_DQSMEM_85D

MEM_A_DQS4

MEM_A_DQS_P<4>

MEM_DQSMEM_85D

MEM_A_DQS_N<2>

MEM_DQSMEM_85D

MEM_A_DQS2

MEM_A_DQS_P<2>

MEM_DQSMEM_85D

MEM_A_DQS3

MEM_A_DQS_P<3>

MEM_DQSMEM_85D

MEM_A_DQS_P<1>

MEM_A_DQS1

MEM_DQSMEM_85D

MEM_A_DQS_N<1>

MEM_DQSMEM_85D

MEM_A_DQS_N<0>

MEM_DQSMEM_85D

MEM_A_DQS_P<0>

MEM_A_DQS0

MEM_DQSMEM_85D

MEM_A_DM<6>

MEM_55S

MEM_DATA

MEM_A_DM6

MEM_55S

MEM_DATA

MEM_A_DM3

MEM_A_DM<3> MEM_A_DM<4>

MEM_55S

MEM_DATA

MEM_A_DM4

MEM_55S

MEM_DATA

MEM_A_DM2

MEM_A_DM<2>

MEM_DATA

MEM_55S

MEM_A_DM0

MEM_A_DM<0>

MEM_55S

MEM_A_DM1

MEM_DATA

MEM_A_DM<1>

MEM_A_DQ_BYTE7

MEM_A_DQ<63..56>

MEM_55S

MEM_DATA

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE6

MEM_A_DQ<55..48>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE1

MEM_A_DQ<15..8>

MEM_55S

MEM_DATA

MEM_A_DQ_BYTE2

MEM_A_DQ<23..16>

MEM_DATA

MEM_55SMEM_A_DQ_BYTE0

MEM_A_DQ<7..0>

MEM_CMD

MEM_A_CMD

MEM_A_WE_L

MEM_55S

MEM_A_CMD

MEM_A_CAS_L

MEM_55S MEM_CMD

MEM_A_CNTL

MEM_45S

MEM_CTRL

MEM_CKE<1..0>

33

31

33

32

33

32

31

32

31

17

31

32

17

32

31

16

17

16

17

16

17

16

17

16

17

16

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.7 & 10.9

HD Audio Interface Constraints

Disk Interface Constraints

USB 2.0 Interface Constraints

DG says minimum spacing 50 mils to clocks

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Section 10.13.2

Internal Interface Constraints

SOURCE: Napa Platform DG, Rev 0.9 (#17978), Section 10.9.1

SOURCE: Santa Platform DG, Rev 1.0 (#21112), Section 10.17

USB_2CLK

25 MIL

*

?

SATA

*

20 MIL

?

=90_OHM_DIFF =90_OHM_DIFF=90_OHM_DIFF

=90_OHM_DIFF=90_OHM_DIFF=90_OHM_DIFF

*

USB_90D

=55_OHM_SE

USB_60S

=55_OHM_SE=55_OHM_SE=55_OHM_SE

=STANDARD=STANDARD*

=3:1_SPACING

SMB

*

?

*

SPI

=1.8:1_SPACING

?

*

?

USB 20 MIL

HDA

=1.8:1_SPACING

?

*

=100_OHM_DIFF

*

=100_OHM_DIFF

SATA_100D

=100_OHM_DIFF

=1.8:1_SPACING

?

IDE

*

=55_OHM_SE

HDA_55S

=55_OHM_SE

*

=55_OHM_SE =55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE

SMB_55S

*

=55_OHM_SE=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

SATA_55S

=55_OHM_SE

=STANDARD

=55_OHM_SE =55_OHM_SE

=STANDARD*

=55_OHM_SE =55_OHM_SE=55_OHM_SE =55_OHM_SE

SPI_55S

* =STANDARD =STANDARD

=55_OHM_SE =55_OHM_SE

*

IDE_55S

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE

SB Constraints (1 of 2)

051-7431

A.0.0

9286

SYNC_DATE=01/25/2007

SYNC_MASTER=T9_NOME

SATA

SATA_C_R2D_N

SATA_100D

TP_SATA_C_D2RN

SATA_100D

SATA

SATA_100D

SATA

SATA_C_D2R_C_N

SATA_100D

SATA_B_D2R_C_P

SATA SATA

SATA_100D

SATA_B_D2R_C_N TP_SATA_C_R2DP

SATA_C_R2D

SATA

SATA_100D

SATA

SATA_C_R2D_P

SATA_100D

HDA_BIT_CLK

HDA_55S

HDA

HDA_BIT_CLK

HDA_SDOUT

HDA

HDA_55S

HDA_SDOUT_R

HDA_55S

HDA

HDA_55S

HDA

HDA_SYNC_R

HDA_SYNC

HDA_55S

HDA

HDA_SYNC

SATA

TP_SATA_B_R2DP

SATA_B_R2D

SATA_100D

IDE_PDIOW_L

IDE

IDE_55S

IDE_CNTL

IDE_PDCS1_L

IDE_55S

IDE

IDE_PDCS

IDE_PDCS3_L

IDE_55S

IDE

IDE_PDCS

IDE_PDDREQ

IDE_CNTL

IDE

IDE_55S

IDE_IRQ14

IDE_55S

IDE

SATA_A_D2R

SATA_A_D2R_P

SATA_100D

SATA

IDE_PDA<2..0>

IDE_55SIDE_PDA

IDE

SATA_A_R2D_P

SATA_100D

SATA

SATA_A_R2D_N

SATA

SATA_100D

TP_SATA_B_R2DN

SATA

SATA_100D

IDE_PDD<15..0>

IDE_55S

IDE

IDE_PDD

SATA_A_D2R_N

SATA

SATA_100D

ODD_RST_5VTOL_L

IDE_RST_L

IDE_55S

IDE

SATA

SATA_A_D2R_C_N

SATA_100D

SATA

SATA_A_D2R_C_P

SATA_100D

IDE_PDIORDY

IDE_55S

IDE

SATA_100D

TP_SATA_B_D2RN

SATA

SATA_B_R2D_P

SATA_100D

SATA_A_R2D_C_P

SATA_A_R2D

SATA_100D

SATA

SATA_A_R2D_C_N

SATA

SATA_100D

TP_SATA_B_D2RP

SATA

SATA_100D

SATA_B_D2R

SATA_B_R2D_N

SATA_100D

SATA

HDA_BIT_CLK_R

HDA_55S

HDA

IDE_55S

IDE

IDE_PDIOR_L

IDE_CNTL

IDE_55S

IDE

IDE_PDDACK_L

TP_SATA_C_R2DN

SATA

SATA_100D

SATA

TP_SATA_C_D2RP

SATA_100D

SATA_C_D2R

SATA_100D

SATA

SATA_C_D2R_C_P

SATA_RBIAS

SATA_55S

SATA_RBIAS

HDA

HDA_SDIN_CODEC

HDA_55S

HDA_SDIN0

HDA

HDA_55S

HDA_SDIN0

HDA_55S

HDA

HDA_RST_L_R

HDA_55S

HDA_RST_L

HDA

HDA_RST_L

USB_MINI_P

USB_MINI

USB_90D

USB

USB_MINI_N

USB

USB_90D

TP_USB_EXTDP

USB_90D

USB

USB_EXTD

TP_USB_EXTDN

USB_90D

USB

USB_CAMERA_P

USB_CAMERA

USB_90D

USB

USB_CAMERA_N

USB_90D

USB

USB_BT_P

USB_BT

USB_90D

USB

USB_BT_N

USB_90D

USB

USB_TPAD_P

USB_TPAD

USB_90D

USB

USB_TPAD_N

USB_90D

USB

USB_IR_P

USB_IR

USB_90D

USB

USB_IR_N

USB_90D

USB

USB_EXTB_P

USB_EXTB

USB

USB_90D

USB_EXTB_N

USB

USB_90D

USB_EXCARD_P

USB_EXCARD

USB

USB_90D

USB_EXCARD_N

USB

USB_90D

USB_EXTC_P

USB_EXTC

USB

USB_90D USB_90D

USB_EXTC_N

USB

USB_RBIAS

USB_60S

SMB_55S

SMB

SMB_SB_SCL

SMBUS_SB_SCL

SMB_SB_SDA

SMB

SMB_55S

SMBUS_SB_SDA

SMB

SMB_55S

SMBUS_SB_ME_SCL

SMB_SB_ME_SCL

SPI_SCLK

SPI_55S

SPI

SPI_SCLK_R

SMB_55S

SMB

SMBUS_SB_ME_SDA

SMB_SB_ME_SDA

SPI_55S

SPI

SPI_SCLK

SPI

SPI_55S

SPI_A_SCLK_R

SPI_55S

SPI

SPI_B_SCLK_R

SPI

SPI_55S

SPI_SI

SPI_SI_R

SPI

SPI_55S

SPI_SI

SPI_55S

SPI

SPI_A_SI_R

SPI

SPI_55S

SPI_B_SI_R

SPI

SPI_55S

SPI_SO

SPI_A_SO_R

SPI

SPI_55S

SPI_B_SO

SPI_55S

SPI

SPI_B_SO_R

SPI_55S

SPI

SPI_55S

SPI

SPI_CE_L0

SPI_CE_R_L<0>

SPI_55S

SPI

SPI_CE_L<0> SPI_CE_R_L<1>

SPI_CE_L1

SPI

SPI_55S SPI_55S

SPI

SPI_CE_L<1>

USB_90D

USB

USB_EXTA_N

USB_90D

USB

USB_EXTA_P

USB_EXTA

USB_EXTA_MUXED_N

USB

USB_90D

USB_EXTA_MUXED_P

USB

USB_90D

48

34

32

81

31

42

34

42

81

42

81

42

81

42

34

24

44

81

24

34

29

48

56

48

56

43

23

81

23

24

23

24

9

24

7

24

25

24

25

56

24

56

24

56

24

56

24

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

SPACING

PHYSICAL

SOURCE: Based on Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

Ethernet (Yukon) Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.27.1.5-7, 10.29 & 10.30

Controller Link (AMT) Constraints

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 10.18.1 & 10.19

PCI Bus Constraints

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

SB Constraints (2 of 2)

87 92

A.0.0

051-7431

=55_OHM_SE =55_OHM_SE

=STANDARD

PCI_55S

*

=55_OHM_SE

=STANDARD

=55_OHM_SE

CLINK_12MIL

300 MILS

5 MILS

12 MILS

=STANDARD* =STANDARD

=STANDARD

=100_OHM_DIFF

*

ENET_100D

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF

25 MILS

ENET_MDI

*

?

=1.8:1_SPACING

*

CLINK

?

=55_OHM_SE

CLINK_55S

=STANDARD

=55_OHM_SE

*

=55_OHM_SE=55_OHM_SE

=STANDARD

12 MILS

CLINK_VREF

*

?

*

=2:1_SPACING

PCI

?

PCI_GNT1_L

PCI

PCI_55S

PCI_GNT1_L

PCI_REQ2_L

PCI

PCI_55S

PCI_REQ2_L

PCI_GNT2_L

PCI

PCI_GNT2_L

PCI_55S

PCI

INT_PIRQB_L

PCI_55S

PCI

PCI_55S

INT_PIRQD_L

INT_PIRQF_L

PCI_55S

INT_PIRQF_L

PCI

PCIE

PCIE_100D

PCIE_A_R2D

PCIE_A_R2D_C_P

PCIE

PCIE_100D

PCIE_A_R2D_C_N

PCIE

PCIE_100D

PCIE_A_D2R

PCIE_A_D2R_P

PCIE_B_R2D

PCIE_100D

PCIE

PCIE_B_R2D_C_P

PCIE

PCIE_100D

PCIE_FW_D2R_N

PCIE_MINI_R2D_C_N

PCIE_100D

PCIE

INT_PIRQA_L

PCI

INT_PIRQA_L

PCI_55S

PCI_TRDY_L

PCI

PCI_55S

PCI_CNTL

SB_CLINK_VREF0

CLINK_12MIL

CLINK_VREF

SB_CLINK_VREF0

SB_CLINK_VREF1

CLINK_12MIL

CLINK_VREF

SB_CLINK_VREF1

PCIE_ENET_R2D_C_P

PCIE

PCIE_100D

PCIE_ENET_R2D

GLAN_COMP

CLINK_NB_RESET_L

CLINK

CLINK_55S

CLINK_NB_RESET_L

CLINK_WLAN_CLK

CLINK_55S

CLINK

CLINK_WLAN

CLINK_55S

CLINK

CLINK_WLAN

CLINK_WLAN_DATA

CLINK_VREF

CLINK_12MIL

NB_CLINK_VREF

CLINK

CLINK_WLAN_RESET_L

CLINK_55S

CLINK_NB_DATA

CLINK_55S

CLINK

CLINK_NB

CLINK_55S

CLINK_NB_CLK

CLINK

CLINK_NB

ENET_MDI

ENET_MDI_P<3>

ENET_MDI

ENET_100D

ENET_MDI_N<3>

ENET_MDI

ENET_100D

ENET_MDI

ENET_MDI_P<2>

ENET_100D

ENET_MDI

ENET_100D

ENET_MDI_N<1>

ENET_MDI

ENET_MDI_N<2>

ENET_MDI

ENET_100D

ENET_MDI

ENET_100D

ENET_MDI_N<0>

ENET_MDI ENET_MDI

ENET_MDI_P<1>

ENET_100D

PCIE

PCIE_100D

PCIE_ENET_D2R_C_N

ENET_MDI

ENET_100D

ENET_MDI

ENET_MDI_P<0>

PCIE_ENET_D2R_C_P

PCIE

PCIE_100D

PCIE_ENET_D2R_P

PCIE_ENET_D2R

PCIE

PCIE_100D

PCIE_ENET_D2R_N

PCIE

PCIE_100D

PCIE_ENET_R2D_P

PCIE

PCIE_100D

PCIE_ENET_R2D_C_N

PCIE_100D

PCIE

PCIE_ENET_R2D_N

PCIE

PCIE_100D

PCIE

PCIE_100D

PCIE_FW_D2R_P

PCIE_FW_D2R

PCIE_100D

PCIE

PCIE_MINI_R2D_C_P

PCIE_MINI_R2D

PCIE

PCIE_100D

PCIE_MINI_D2R_P

PCIE_MINI_D2R

PCIE

PCIE_100D

PCIE_MINI_D2R_N

PCIE_100D

PCIE

PCIE_FW_R2D_C_N

PCIE_B_D2R_N

PCIE

PCIE_100D

PCIE_B_D2R_P

PCIE

PCIE_100D

PCIE_B_D2R

PCIE_100D

PCIE

PCIE_B_R2D_C_N

PCI_FW_REQ_L

PCI

PCI_55S

PCI_SERR_L

PCI_55S

PCI

PCI_CNTL

PCI_PERR_L

PCI

PCI_55S

PCI_CNTL

PCI_DEVSEL_L

PCI

PCI_55S

PCI_CNTL

PCI

PCI_55S

PCI_CNTL

PCI_IRDY_L

PCI_LOCK_L

PCI

PCI_55S

PCI_LOCK_L

PCI_REQ1_L

PCI

PCI_55S

PCI_REQ1_L

PCI_FW_GNT_L

PCI

PCI_55S

PCI_C_BE_L<3..0>

PCI

PCI_55S

PCI_C_BE_L

PCI_AD<31..21>

PCI

PCI_55S

PCI_AD

PCI_PAR

PCI

PCI_55S

PCI_AD

PCI_AD<20>

PCI

PCI_55S

PCI_AD20

PCI_AD<19>

PCI

PCI_55S

PCI_AD19

PCI_AD<18..0>

PCI_55S

PCI

PCI_AD

PCI_STOP_L

PCI

PCI_55S

PCI_CNTL

PCI_FRAME_L

PCI

PCI_55S

PCI_CNTL

PCIE

PCIE_100D

PCIE_EXCARD_R2D_C_N

PCIE

PCIE_100D

PCIE_A_D2R_N

PCIE

PCIE_100D

PCIE_EXCARD_R2D_C_P

PCIE_EXCARD_R2D

PCI

INT_PIRQC_L

PCI_55S

PCIE

PCIE_100D

PCIE_EXCARD_D2R_P

PCIE_EXCARD_D2R

PCIE_100D

PCIE

PCIE_FW_R2D_C_P

PCIE_FW_R2D

PCIE

PCIE_100D

PCIE_EXCARD_D2R_N

47 38

38

34

38

35

25

37

35

34

38

24

38

34

24

25

24

23

16

35

24

35

24

35

24

7

24

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

Clock Signal Constraints

(CK505_CPU)

(CK505_NB) (CK505_ITP)

(CK505_PCI2)

(CK505_PCI1)

(CK505_DOT96) (CK505_DOT96)

(CPU_BSEL0) (CPU_BSEL2)

(CK505_PCI3)

(CK505_SRC2)

(CK505_SRC6) (CK505_SRC6)

(CK505_LVDS)

(CPU_BSEL2)

(CK505_SRC1)

(CK505_ITP) (CK505_PCIF0)

(CK505_PCIF1)

(CK505_NB)

CK505 SRC7 is project-specific

CK505 PCI4 is project-specific CK505 PCI5 is project-specific

PHYSICAL

(CPU_BSEL0) (CPU_BSEL2)

NET_TYPE

SPACING

SOURCE: Santa Rosa Platform DG, Rev 1.0 (#21112), Sections 14.1 - 14.6

ELECTRICAL_CONSTRAINT_SET

Clock Net Properties

(CPU_BSEL0)

(CK505_SRC2) (CK505_SRC3) (CK505_SRC3)

(CK505_SRC8)

(CK505_SRC5)

(CK505_SRC4)

SPACING

SMC SMBus Net Properties

NET_TYPE

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

(CK505_SRC5)

20 MIL

*

CLK_MED

?

=55_OHM_SE =55_OHM_SE

=STANDARD

=55_OHM_SE=55_OHM_SE

CLK_MED_55S

=STANDARD*

25 MIL

*

CLK_FSB

?

=100_OHM_DIFF

CLK_PCIE_100D =100_OHM_DIFF=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

*

=100_OHM_DIFF

=100_OHM_DIFF=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

*

CLK_FSB_100D

Clock & SMC Constraints

051-7431

A.0.0

9288

SYNC_MASTER=M87_MLB

SYNC_DATE=08/28/2007

20 MIL

CLK_PCIE

?

*

=55_OHM_SE

CLK_SLOW_55S

=55_OHM_SE

*

=55_OHM_SE

=STANDARD =STANDARD

=55_OHM_SE

10 MIL

*

?

CLK_SLOW

CLK_PCIE_100D

CLK_PCIE

NB_CLK100M_PCIE_N

PCIE_CLK100M_MINI_N

CLK_PCIE_100D

CLK_PCIE

SMBUS_SMC_MGMT_SDA

SMB_55S

SMB

SMBUS_SMC_BSA_SDA

SMB

SMB_55S

SMBUS_SMC_B_S0_SDA

SMB

SMB_55S

SMBUS_SMC_MGMT_SCL

SMB

SMB_55S

SMBUS_SMC_BSA_SCL

SMB_55S

SMB

SMBUS_SMC_0_S0_SDA

SMB

SMB_55S

SMBUS_SMC_0_S0_SCL

SMB_55S

SMB

SMBUS_SMC_B_S0_SCL

SMB_55S

SMB

SMBUS_SMC_A_S3_SCL

SMB

SMB_55S

SMBUS_SMC_A_S3_SDA

SMB

SMB_55S

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_SATA_P

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_SATA_N

CLK_PCIE_100D

CLK_PCIE

NB_CLK100M_PCIE_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_MINI_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_ENET_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_ENET_N

CLK_PCIE_100D

PCIE_CLK100M_EXCARD_N

CLK_PCIE

SB_CLK14P3M_TIMER

CLK_MED

CLK_MED_55S

CLK_MED

CLK_MED_55S

CK505_FSA

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_P

CK505_SRC7

CLK_PCIE

CLK_PCIE_100D

TP_PCIE_CLK100M_SRC7P

CK505_CPU

FSB_CLK_CPU_P

CLK_FSB

CLK_FSB_100D

CK505_PCIF1

CK505_PCIF1_CLK

CLK_MED_55S

CLK_MED

CK505_PCI1_CLK

CLK_MED_55S

CLK_MED

CK505_PCI1

CLK_FSB_100D

XDP_CLK_N

CLK_FSB

CLK_PCIE_100D

CLK_PCIE

CK505_SRC3

PCIE_CLK100M_EXCARD_P

CK505_SRC2

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_DMI_P

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_DMI_N

CK505_DOT96

CLK_PCIE_100D

CLK_PCIE

CK505_CLK27M

CLK_MED_55S

CLK_MED

CK505_REF0_FSC

CLK_FSB

FSB_CLK_NB_P

CLK_FSB_100DCK505_NB

CK505_CPU

CLK_FSB

FSB_CLK_CPU_N

CLK_FSB_100D

CLK_FSB

XDP_CLK_N

CK505_ITP

CLK_FSB_100D

XDP_CLK_P

CLK_FSB

CLK_FSB_100D

CK505_ITP

CK505_NB

CLK_FSB

FSB_CLK_NB_N

CLK_FSB_100D

CLK_MED_55S

CLK_MED

CK505_48M_FSA

CK505_CLK27M_SS

CLK_PCIE

CLK_PCIE_100D

CLK_PCIE

TP_NB_CLK100M_DPLLSS_N

PEG_CLK100M_GPU_N

CLK_PCIE_100D

CLK_PCIE

CLK_MED_55S

CK505_PCI5

CLK_MED

CK505_PCI5_CLK_FCTSEL

TP_CK505_PCI4_CLK

CK505_PCI4

CLK_MED_55S

CLK_MED

CK505_PCI3_CLK

CK505_PCI3

CLK_MED_55S

CLK_MED

TP_CK505_PCI2_CLK

CLK_MED_55S

CLK_MED

CK505_PCI2

CLK_MED_55SCK505_PCIF0

CLK_MED

CK505_PCIF0_CLK_ITPEN

CK505_SRC1

CLK_PCIE_100D

CLK_PCIE

PEG_CLK100M_GPU_P

CK505_LVDS

CLK_PCIE_100D

CLK_PCIE

TP_NB_CLK100M_DPLLSS_P

CLK_PCIE

CK505_SRC5

CLK_PCIE_100D

NB_CLK100M_PCIE_P

CLK_PCIE_100D

CLK_PCIE

PCIE_CLK100M_EXCARD_N

CLK_MED_55S

CLK_MED

PCI_CLK33M_SB

CLK_MED_55S

CLK_MED

PCI_CLK33M_LPCPLUS

CLK_MED_55S

CLK_MED

PCI_CLK33M_FW

CLK_MED_55S

CLK_MED

PCI_CLK33M_SMC

CLK_MED_55S

SB_CLK48M_USBCTLR

CLK_MED

CLK_PCIE_100D

CLK_PCIE

PEG_CLK100M_GPU_N

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_DMI_P

PCIE_CLK100M_EXCARD_P

CLK_PCIE_100D

CLK_PCIE

PEG_CLK100M_GPU_P

CLK_PCIE_100D

SB_CLK100M_DMI_N

CLK_PCIE

CLK_PCIE_100D

CLK_MED

CLK_MED_55S

CK505_FSC

CLK_MED_55S

CLK_MED

PCI_CLK33M_TPM

XDP_CLK_P

CLK_FSB

CLK_FSB_100D

CLK_FSB

FSB_CLK_NB_N

CLK_FSB_100D

CLK_FSB

FSB_CLK_NB_P

CLK_FSB_100D

CLK_FSB

FSB_CLK_CPU_N

CLK_PCIE_100D

CLK_PCIE

TP_PCIE_CLK100M_SRC7N

CLK_PCIE

CLK_PCIE_100D

PCIE_CLK100M_MINI_N

CLK_PCIE

NB_CLK100M_PCIE_N

CLK_PCIE_100D

CK505_SRC4

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_SATA_P

CLK_PCIE_100D

CLK_PCIE

SB_CLK100M_SATA_N

CLK_PCIE

CK505_SRC6

CLK_PCIE_100D

PCIE_CLK100M_MINI_P

CLK_PCIE

PCIE_CLK100M_ENET_N

CLK_PCIE_100D

CK505_SRC8

CLK_PCIE

PCIE_CLK100M_ENET_P

NB_CLK96M_DOT_P

GND

CRT_50S

NB_CLK96M_DOT_N

GND

CRT_50S

NB_CLK100M_DPLLSS_P

GND

CRT_50S

NB_CLK100M_DPLLSS_N

GND

CRT_50S

88

81

88

30

88

57

53

57

74

53

51

88

30

88

30

83

88

30

83

30

67

30

88

67

88

67

88

83

30

88

30

88

29

34

55

48

51

55

48

51

48

30

29

34

35

34

29

30

34

30

29

30

29

30

29

34

47

30

34

30

29

34

29

30

34

35

16

30

48

45

48

45

48

45

29

16

30

10

30

10

30

29

30

29

30

14

10

29

14

30

29

30

29

30

16

30

38

45

30

29

30

29

14

10

30

16

29

30

7

29

45

7

45

7

45

34

23

7

29

25

30

7

29

7

29

13

29

24

29

7

13

7

29

9

29

9

29

7

29

24

7

30

25

9

24

29

9

24

30

13

7

29

7

23

29

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

FireWire Interface Constraints

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

PHYSICAL

FireWire Net Properties

SPACING

Port 2 Not Used

=55_OHM_SE =55_OHM_SE

=STANDARD=STANDARD

=55_OHM_SE=55_OHM_SE

FW_55S

*

?

*FW

=2:1_SPACING

FireWire Constraints

051-7431

A.0.0

9289

SYNC_MASTER=T9_NOME

SYNC_DATE=01/25/2007

=110_OHM_DIFF

*

=110_OHM_DIFF

=110_OHM_DIFF =110_OHM_DIFF

FW_110D

=110_OHM_DIFF =110_OHM_DIFF

*

=3:1_SPACING

?

FW_TP

FW_110D

FW_PORT1_TPA_N

FW_1_TPA

FW_TP

FW_110D

FW_PORT1_TPA_P

FW_1_TPA

CLK_MED

CLK_MED_55S

CLKFW_PHY_LCLK

FW_0_TPB

FW_110D

FW_TP

FW_PORT0_TPB_P

FW_55S

FW

FW_LKON_R

FW_PINT

FW_55S

FW

FW_PINT

FW_TP

FW_110D

FW_0_TPA

FW_PORT0_TPA_P

FW_0_TPB

FW_110D

FW_PORT0_TPB_N

FW_TP

CLK_MED

CLK_MED_55S

CLK98P304M_FW_XI

FW_1_TPB

FW_TP

FW_110D

FW_PORT1_TPB_P

FW_1_TPB

FW_TP

FW_110D

FW_PORT1_TPB_N

FW_PORT0_TPA_N

FW_110D

FW_TP

FW_0_TPA

FW_55S

FW

FW_LKON

FW

FW_55S

FW_CTL<1..0>

FW_D_CTL FW_LCLK CLK_MED

CLK_MED_55S

CLKFW_LINK_LCLK

FW_PCLK CLK_MED

CLK_MED_55S

CLKFW_LINK_PCLK

CLK_MED_55S

CLK_MED

CLKFW_PHY_PCLK

FW_D_CTL

FW_55S

FW

FW_LINK<7..0>

CLK_MED_55S

CLK_MED

FWPHY_CLK98P304M_XI

CLK98P304M_FW_XI_R

FW_55S

FW

FW_LREQ

FW_LPS

FW

FW_55S

41

39

41

39

41

39

38

39

38

39

38

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

Video Signal Constraints

GDDR3 Frame Buffer Signal Constraints

GDDR3 FB A/B Net Properties

ELECTRICAL_CONSTRAINT_SET

G84M Net Properties

SPACING

PHYSICAL

(CK505_DOT96)

PHYSICAL

SPACING

NET_TYPE

SPACING

ELECTRICAL_CONSTRAINT_SET

GDDR3 FB C/D Net Properties

PHYSICAL

ELECTRICAL_CONSTRAINT_SET

NET_TYPE

I126

I127

I128

I129

?

20 MIL

*

VGA_SYNC

?

*

VGA 20 MIL

?

20 MIL

*

TMDS

VGA_55S

=55_OHM_SE=55_OHM_SE =55_OHM_SE

=STANDARD* =STANDARD

=55_OHM_SE

SYNC_DATE=10/02/2007

SYNC_MASTER=M87_MLB

GPU (G84M) Constraints

90 92

A.0.0

051-7431

=40_OHM_SE

*

GDDR3_40R55SE

=55_OHM_SE

=STANDARD=STANDARD

12.7 MM

=STANDARD

=50_OHM_SE=50_OHM_SE

* =STANDARD

VGA_50S

=50_OHM_SE=50_OHM_SE

=100_OHM_DIFF

=100_OHM_DIFF*=100_OHM_DIFF

TMDS_100D

=100_OHM_DIFF=100_OHM_DIFF

=2.5:1_SPACING

?

GDDR3_DQS

*

=2.5:1_SPACING

?

*

GDDR3_DATA

=2.5:1_SPACING

?

GDDR3_CMD

*

=2.5:1_SPACING

?

GDDR3_CLK

*

=50_OHM_SE=50_OHM_SE=50_OHM_SE

=50_OHM_SE

GDDR3_50SE

* =STANDARD =STANDARD

=80_OHM_DIFF

GDDR3_80D

=80_OHM_DIFF=80_OHM_DIFF =80_OHM_DIFF

* =80_OHM_DIFF =80_OHM_DIFF

GDDR3_50SE

FB_A_RDQS<2>

FB_A_RDQS2

GDDR3_DQS

GDDR3_50SEFB_C_RDQS2

GDDR3_DQS

FB_B_RDQS<2>

GDDR3_50SE

GDDR3_DQS

FB_C_RDQS3

FB_B_RDQS<3>

GDDR3_50SE

FB_B_DQ<7..0>

FB_C_DQ_BYTE0

GDDR3_DATA

GDDR3_50SE

FB_B_DQ<15..8>

FB_C_DQ_BYTE1

GDDR3_DATA

GDDR3_50SE

FB_B_DQ<23..16>

FB_C_DQ_BYTE2

GDDR3_DATA

GDDR3_50SE

FB_B_DQ<31..24>

FB_C_DQ_BYTE3

GDDR3_DATA

GDDR3_50SE

FB_C_DQM0

FB_B_DQM_L<0>

GDDR3_DATA

GDDR3_50SE

FB_C_DQM1

FB_B_DQM_L<1>

GDDR3_DATA

GDDR3_50SE

FB_B_DQM_L<2>

FB_C_DQM2

GDDR3_DATA

GDDR3_50SEFB_D_WDQS0

GDDR3_DQS

FB_B_WDQS<4>

GDDR3_50SEFB_D_WDQS2

GDDR3_DQS

FB_B_WDQS<6>

GDDR3_50SEFB_D_RDQS0

GDDR3_DQS

FB_B_RDQS<4>

GDDR3_50SE

FB_B_DQ_BYTE3

FB_A_DQ<63..56>

GDDR3_DATA

GDDR3_50SE

FB_A_DQ<55..48>

FB_B_DQ_BYTE2

GDDR3_DATA

GDDR3_50SE

FB_A_DQ<47..40>

FB_B_DQ_BYTE1

GDDR3_DATA

GDDR3_50SE

FB_A_DQ<39..32>

FB_B_DQ_BYTE0

GDDR3_DATA

GDDR3_50SE

FB_A_RDQS<7>

FB_B_RDQS3

GDDR3_DQS

GDDR3_50SE

FB_A_RDQS<6>

FB_B_RDQS2

GDDR3_DQS

GDDR3_50SE

GDDR3_DQS

FB_A_RDQS<0>

FB_A_RDQS0

GDDR3_50SE

FB_A_WDQS<1>

FB_A_WDQS1

GDDR3_DQS

GDDR3_50SE

FB_A_WDQS<0>

GDDR3_DQS

FB_A_WDQS0

GDDR3_50SE

GDDR3_CMD

FB_A_LMA<5..2>

FB_A_CMD

GDDR3_50SE

FB_A_WDQS<3>

GDDR3_DQS

FB_A_WDQS3

GDDR3_50SE

FB_A_WDQS<2>

FB_A_WDQS2

GDDR3_DQS

GDDR3_50SE

FB_A_UMA<5..2>

GDDR3_CMD

FB_B_CMD

FB_AB_CMD GDDR3_CMD

FB_A_MA<11..6>

GDDR3_40R55SE

FB_AB_CMD GDDR3_CMD

FB_A_BA<2..0>

GDDR3_40R55SE

FB_AB_CMD GDDR3_CMD

FB_A_RAS_L

GDDR3_40R55SE

GDDR3_CMD

FB_A_CAS_L

FB_AB_CMD

GDDR3_40R55SE

GDDR3_CMDFB_AB_CMD

FB_A_WE_L

GDDR3_40R55SE

FB_A_DRAM_RST

GDDR3_CMD

FB_AB_CMD_PD

GDDR3_40R55SE

FB_AB_CS0

FB_A_CS0_L

GDDR3_CMD

GDDR3_40R55SE

FB_AB_CMD_PD

GDDR3_CMD

FB_A_CKE

FB_AB_CMD GDDR3_CMD

FB_A_MA<1..0>

GDDR3_40R55SE

GDDR3_50SEFB_C_WDQS2

GDDR3_DQS

FB_B_WDQS<2>

FB_CD_CMD_PD

GDDR3_CMD

FB_B_CKE

GDDR3_40R55SE

GDDR3_50SEFB_B_WDQS0

GDDR3_DQS

FB_A_WDQS<4>

GDDR3_50SEFB_B_WDQS1

GDDR3_DQS

FB_A_WDQS<5>

GDDR3_50SE

GDDR3_DQS

FB_B_RDQS<6>

FB_D_RDQS2

GDDR3_50SE

FB_B_DQ<39..32>

GDDR3_DATA

FB_D_DQ_BYTE0

CLK_SLOWCLK_SLOW_55S

CK505_CLK27MSS

GPU_CLK27M_SS

LVDS_L_CLK

LVDS

LVDS_100D

LVDS_L_CLK_P

NC_LVDS_L_DATAP<3>

LVDS_100D

LVDS

LVDS_U_DATA_P<2..0>

LVDS

LVDS_100D

LVDS_U_DATA

LVDS

LVDS_U_DATA_N<2..0>

LVDS_100D

NC_LVDS_U_DATAP<3>

LVDS_100D

LVDS

NC_LVDS_U_DATAN<3>

LVDS

LVDS_100D

NC_LVDS_L_DATAN<3>

LVDS

TMDS_CLK_P

TMDS_100D

TMDSTMDS_CLK

LVDS_100D

LVDS_U_CLK

LVDS_U_CLK_P

LVDS

LVDS_100D

LVDS

LVDS_U_CLK_N

LVDS

LVDS_L_DATA_N<2..0>

LVDS_100D

LVDS_L_DATA_P<2..0>

LVDS_100D

LVDS

LVDS_L_DATA

TMDS_CLK

TMDS_100D

TMDS

TMDS_CLK_N

TMDS_DATA TMDS_100D

TMDS

TMDS_DATA_P<5..0>

TMDS_DATA TMDS_100D

TMDS_DATA_N<5..0>

TMDS

VGA_R_TV_C

VGA

GPU_TV_C_VGA_R

VGA_50S

VGA

GPU_TV_Y_VGA_G

VGA_G_TV_Y

VGA_50S

VGA

GPU_TV_COMP_VGA_B

VGA_B_TV_COMP

VGA_50S

GPU_VGA_R

VGA

VGA_50S

GPU_VGA_G

VGA

VGA_50S

GPU_VGA_B

VGA

VGA_50S

GPU_TV_C

VGA_50S

VGA VGA

GPU_TV_Y

VGA_50S

VGA

GPU_TV_COMP

VGA_50S

VGA_SYNC VGA_SYNC

VGA_55S

GPU_VGA_HSYNC

VGA_SYNC

GPU_VGA_VSYNC

VGA_55S

VGA_SYNC

GDDR3_50SE

FB_B_DQM0

FB_A_DQM_L<4>

GDDR3_DATA

GDDR3_50SEFB_B_RDQS0

GDDR3_DQS

FB_A_RDQS<4>

CLK_SLOWCLK_SLOW_55S

GPU_CLK27M

LVDS_L_CLK_N

LVDS_100D

LVDS

GDDR3_50SE

FB_A_DQM_L<6>

FB_B_DQM2

GDDR3_DATA

GDDR3_50SE

FB_B_DQM1

FB_A_DQM_L<5>

GDDR3_DATA

GDDR3_CLK

FB_A_CLK_N<1>

GDDR3_80D

GDDR3_40R55SE

FB_CD_CS0 GDDR3_CMD

FB_B_CS0_L

GDDR3_40R55SE

FB_B_DRAM_RST

FB_CD_CMD_PD

GDDR3_CMD

FB_A_CLK_P<0>

GDDR3_CLK

FB_A_CLK_P

GDDR3_80D

GDDR3_CLK

FB_A_CLK_N<0>

GDDR3_80D

FB_A_CLK_P<1>

GDDR3_CLK

FB_B_CLK_P

GDDR3_80D

GDDR3_50SE

FB_B_DQM_L<4>

FB_D_DQM0

GDDR3_DATA

GDDR3_50SE

FB_B_DQ<63..56>

FB_D_DQ_BYTE3

GDDR3_DATA

GDDR3_50SE

FB_B_DQ<47..40>

GDDR3_DATA

FB_D_DQ_BYTE1

GDDR3_50SEFB_D_WDQS1

GDDR3_DQS

FB_B_WDQS<5>

GDDR3_50SE

FB_B_DQM_L<3>

FB_C_DQM3

GDDR3_DATA

GDDR3_CMD

FB_B_CAS_L

FB_CD_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_B_WE_L

FB_CD_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_B_RAS_L

FB_CD_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_B_MA<11..6>

FB_CD_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_B_BA<2..0>

FB_CD_CMD

GDDR3_40R55SE

GDDR3_CMD

FB_B_MA<1..0>

FB_CD_CMD

GDDR3_40R55SE

GDDR3_CLK

FB_B_CLK_N<1>

GDDR3_80D

GDDR3_CLK

FB_B_CLK_P<1>

FB_D_CLK_P

GDDR3_80D

GDDR3_CLK

FB_B_CLK_P<0>

FB_C_CLK_P

GDDR3_80D

GDDR3_CLK

FB_B_CLK_N<0>

GDDR3_80D

GDDR3_50SE

GDDR3_CMD

FB_D_CMD

FB_B_UMA<5..2>

GDDR3_50SEFB_C_RDQS1

GDDR3_DQS

FB_B_RDQS<1>

GDDR3_50SEFB_C_RDQS0

GDDR3_DQS

FB_B_RDQS<0>

GDDR3_50SEFB_C_WDQS3

GDDR3_DQS

FB_B_WDQS<3>

GDDR3_50SEFB_C_WDQS1

GDDR3_DQS

FB_B_WDQS<1>

GDDR3_50SEFB_C_WDQS0

GDDR3_DQS

FB_B_WDQS<0>

GDDR3_50SE

FB_B_LMA<5..2>

FB_C_CMD

GDDR3_CMD

GDDR3_50SE

GDDR3_DQS

FB_B_RDQS<7>

FB_D_RDQS3

GDDR3_50SEFB_D_RDQS1

FB_B_RDQS<5>

GDDR3_DQS

GDDR3_50SE

FB_D_DQ_BYTE2

FB_B_DQ<55..48>

GDDR3_DATA

GDDR3_50SE

FB_B_DQM_L<7>

FB_D_DQM3

GDDR3_DATA

GDDR3_50SE

FB_D_DQM1

FB_B_DQM_L<5>

GDDR3_DATA

GDDR3_50SE

GDDR3_DQS

FB_B_WDQS2

FB_A_WDQS<6>

GDDR3_50SE

FB_A_RDQS<5>

FB_B_RDQS1

GDDR3_DQS

GDDR3_50SE

FB_A_DQM_L<7>

FB_B_DQM3

GDDR3_DATA

GDDR3_50SEFB_B_WDQS3

GDDR3_DQS

FB_A_WDQS<7>

GDDR3_50SE

FB_A_DQM_L<3>

FB_A_DQM3

GDDR3_DATA

GDDR3_50SE GDDR3_DATA

FB_A_DQM_L<2>

FB_A_DQM2

GDDR3_50SE GDDR3_DATA

FB_A_DQM_L<1>

FB_A_DQM1

GDDR3_50SE GDDR3_DATA

FB_A_DQM_L<0>

FB_A_DQM0

GDDR3_50SE GDDR3_DATA

FB_A_DQ<31..24>

FB_A_DQ_BYTE3

GDDR3_50SE

FB_A_DQ<23..16>

FB_A_DQ_BYTE2

GDDR3_DATA

GDDR3_50SE

FB_A_DQ<15..8>

FB_A_DQ_BYTE1

GDDR3_DATA

GDDR3_50SE

FB_A_RDQS<3>

FB_A_RDQS3

GDDR3_DQS

GDDR3_50SE

FB_A_DQ<7..0>

GDDR3_DATA

FB_A_DQ_BYTE0

GDDR3_50SE

FB_B_DQM_L<6>

GDDR3_DATA

FB_D_DQM2

GDDR3_50SEFB_D_WDQS3

GDDR3_DQS

FB_B_WDQS<7>

GDDR3_50SE

FB_A_RDQS<1>

GDDR3_DQS

FB_A_RDQS1

77 78

78

77

78

77

78

73

77

73

77

78

77

78

77

78

77

70 71

71

70

71

70

71

72

76

74

76

74

80

76

80

74

80

70

72

76

70

71

70

71

70

71

70

69 69

69

30

74

73

74

73

74

73

74

69

30

74

69

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_PHYSICAL_RULE_ITEM

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_RULE_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE OVERRIDE

TABLE_PHYSICAL_RULE_ITEM

TABLE_PHYSICAL_ASSIGNMENT_ITEM

PHYSICAL_RULE_SET

AREA_TYPE

NET_PHYSICAL_TYPE

TABLE_PHYSICAL_ASSIGNMENT_HEAD

M87 Specific Net Properties

ELECTRICAL_CONSTRAINT_SET

(VGA_SYNC) (VGA_SYNC)

(VGA_SYNC)

(VGA_G_TV_C) (VGA_B_TV_COMP)

(SATA_A_D2R) (USB_EXTA)

(USB_EXTA)

(USB_EXTA) (USB_EXTA)

(USB_EXTD) (USB_EXTD)

(USB_CAMERA)

(SATA_A_R2D) (SATA_A_R2D)

(SATA_A_D2R)

(PCIE_EXCARD) (PCIE_EXCARD)

(PCIE_MINI) (PCIE_MINI)

NET_TYPE

SPACING

PHYSICAL

(VGA_SYNC)

(VGA_R_TV_Y)

Memory Constraint Relaxations

Allow 0.127 mm necks for >0.127 mm lines for GMCH fanout.

Allow 0.1 mm necks for >0.1 mm lines between thru-hole SO-DIMM pins.

Alternate diffpair width/gap through BGA fanout areas (95-ohm diff)

Graphics ,SATA Constraint Relaxations

I120

I121 I122

I123

I124 I125

I126

I127

I128

I129

I130

I131

I132

I133

I134

I135

I136

TMDS_100D

100_DIFF_BGA

BGA

100_DIFF_BGA

SATA_100D

BGA

MEM_85D 2.54 MM

ISL4,ISL10

0.100 MM

*

2.54 MMMEM_45S

0.100 MM

*

PWR_P2MMENET_MDI

ENET_POWER

*

GND_P2MM

GND

ENET_MDI

GND_P2MM

*

GND

FSB_DSTB

GND_P2MM

*

GND

CPU_GTLREF

GND_P2MM

*

GND

CPU_COMP

*

GND

CLK_FSB

GND_P2MM

MEM_DATA

*

PWR_P2MM

PP1V8_MEM

MEM_DQS

*

PP1V8_MEM

PWR_P2MM

*

GND

GND_P2MM

CLINK_VREF

*

GND

GND_P2MM

CPU_VCCSENSE

GND

*

DMI

GND_P2MM

GND

*

SATA

GND_P2MM

PCIE

GND

*

GND_P2MM

CLK_PCIE

GND

*

GND_P2MM

*

PWR_P2MMSB_POWER

USB

PWR_P2MM

*

SB_POWER

SATA

CLK_MED

*

GND_P2MMFW_POWER

MEM_CTRL

PP1V8_MEM

*

PWR_P2MM

PP1V8_MEM

*

MEM_CLK

PWR_P2MM

GND_P2MMMEM_DATA

GND

*

GND

*

MEM_CLK

GND_P2MM

0.20 MM

PWR_P2MM

*

1000

?

=STANDARD

*

PP1V8_MEM

SB_POWER

DMI

*

PWR_P2MM

*

SB_POWERCLK_PCIE PWR_P2MM

GNDUSB

*

GND_P2MM

MEM_CTRL GND_P2MM

GND

*

THERM

=2:1_SPACING

*

?

ENETCONN

25 MILS

*

?

GND_P2MM

*

GND

MEM_DQS

*

MEM_CMD

PWR_P2MM

PP1V8_MEM

GND_P2MM

CLK_MED

*

GND

*

GND

GND_P2MM

MEM_CMD

100_DIFF_BGA

LVDS_100D

BGA

*

GND

LVDS

GND_P2MM

=2:1_SPACING

SENSE

*

?

=55_OHM_SE

=1:1_DIFFPAIR

SENSE_1TO1_55S

=55_OHM_SE

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

=55_OHM_SE

THERM_1TO1_55S

=55_OHM_SE =55_OHM_SE

*

=1:1_DIFFPAIR =1:1_DIFFPAIR

=1:1_DIFFPAIR

GND_P2MM

1000

0.20 MM

*

GND

=STANDARD

?

Project Specific Constraints

SYNC_DATE=08/28/2007

SYNC_MASTER=M87_MLB

91 92

A.0.0

051-7431

MEM_70D

ISL10

2.54 MM

0.100 MM

BOTTOM

0.127 MM

MEM_70D 6.35 MM

TMDS_100D

TMDS

TMDS_DATA_F_N<5..0>

GPUTHMSNS_D_P

THERM

THERM_DIFFPAIR THERM_1TO1_55S

THERM_1TO1_55S

GPU_TDIODE_P

THERM

THERM_DIFFPAIR

PP1V8_S3

PP1V8_MEM

SENSE_DIFFPAIR

GFXIMVP6_VSEN_P

SENSE_1TO1_55S

SENSE SENSE

SENSE_1TO1_55S

GFXIMVP6_VSEN_N NBCOREISNS_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

NBCOREISNS_N

SENSE

SENSE_1TO1_55S

USB_90D

USB

USB_CAMERA_F_N

USB_90D

USB_CAMERA_F_P

USB

USB_90D

USB_WWAN_F_N

USB

PCIE_100D

PCIE_EXCARD_R2D_P

PCIE

PCIE_EXCARD_R2D_N

PCIE

PCIE_100D

PCIE_MINI_R2D_N

PCIE_100D

PCIE

PCIE_MINI_R2D_P

PCIE_100D

ENET_MDI_R_P<3..0>

ENET_100D

ENET_MDI

ENETCONN_P<3..0>

ENET_100D

ENETCONN

ENET_MDI_R_N<3..0>

ENET_100D

ENET_MDI

FW_TP

FW_PORT0_TPA_FL_P

FW_110D

ENETCONN_N<3..0>

ENETCONN

ENET_100D

FW_PORT0_TPA_FL_N

FW_TP

FW_110D

FW_PORT0_TPB_FL_P

FW_TP

FW_110D

FW_PORT0_TPB_FL_N

FW_TP

FW_110D

SATA_A_R2D_UF_P

SATA_100D

SATA

SATA_A_D2R_UF_P

SATA_100D

SATA

SATA_A_D2R_UF_N

SATA_100D

SATA

USB2_EXTA_MUXED_P

USB

USB_90D

USB2_EXTA_MUXED_N

USB_90D

USB

USB2_RT_P

USB_90D

USB

USB2_RT_N

USB_90D

USB

USB_WWAN_F_P

USB

USB_90D

SATA_A_R2D_UF_N

SATA_100D

SATA

THERM_1TO1_55S

GPUTHMSNS_D_N

THERM

TMDS_CLK_R_P

TMDS

TMDS_100D

TMDS_CLK_F_P

TMDS_100D

TMDS

TMDS_CLK_R_N

TMDS_100D

TMDS

TMDS_100D

TMDS

TMDS_DATA_F_P<5..0>

TMDS_CLK_F_N

TMDS

TMDS_100D

VGA_R

VGA

VGA_50S

VGA_HSYNC_R

VGA_SYNC

VGA_55S

P1V8GPUISNS_N

SENSE

SENSE_1TO1_55S

FW_POWER

CPU_THERMD_N

THERM

THERM_1TO1_55S

CPU_THERMD_P

THERM

THERM_1TO1_55STHERM_DIFFPAIR

CPUTHMSNS_D2_N

THERM

THERM_1TO1_55S

THERM_DIFFPAIR

THERM

CPUTHMSNS_D2_P

THERM_1TO1_55S

SENSE_1TO1_55SSENSE_DIFFPAIR

SENSE

P1V8ISNS_P

SENSE_DIFFPAIR SENSE_1TO1_55S

SENSE

P1V25ISNS_P

SENSE_1TO1_55S

SENSE

P1V25ISNS_N

SENSE_1TO1_55S

SENSE

P1V8ISNS_N

LVDS_L_CLK_CONN_F_P

LVDS_100D

LVDS

HSTHMSNS_D_N

THERM_1TO1_55S

THERM

THERM_1TO1_55S

GPU_TDIODE_N

THERM

RSFSTHMSNS_D_P

THERM

THERM_1TO1_55STHERM_DIFFPAIR THERM_1TO1_55S

THERM

RSFSTHMSNS_D_N

LVDS_L_CLK_CONN_F_N

LVDS

LVDS_100D

HSTHMSNS_D_P

THERM_1TO1_55S

THERM

THERM_DIFFPAIR

P1V8GPUISNS_P

SENSE_1TO1_55S

SENSE

SENSE_DIFFPAIR

VGA_VSYNC

VGA_55S

VGA_SYNC

VGA_VSYNC_R

VGA_55S

VGA_SYNC

PP1V8_S3

PP1V8_MEM

ENET_POWER

PP3V3_S0

SB_POWER

PP1V5_S0

SB_POWER

PP3V3_S5

SB_POWER

VGA_HSYNC

VGA_55S

VGA_SYNC

VGA_B

VGA

VGA_50S

VGA_G

VGA

VGA_50S

P1V8ISNS_R_N

SENSE

SENSE_1TO1_55S

P1V8ISNS_R_P

SENSE

SENSE_DIFFPAIR SENSE_1TO1_55S

P1V8GPUISNS_R_N

SENSE

SENSE_1TO1_55S

P1V8GPUISNS_R_P

SENSE_DIFFPAIR

SENSE

SENSE_1TO1_55S

GND

82 65 59 58 53 52

51 50 48 47 46 42 32 31 30

76

29

65

28

60

27

58

26

56

25

63

48

91

24

34

46

62

23

27

28

50

21

26

27

38

19

22

26

73

32

73

32

16

12

25

72

31

44

51

72

51

31

13

11

24

80

51

8

75

50

7

34

37

41

37

41

81

43

81

51

80

50

10

7

50

76

7

51

7

76

7

50

80

8

80

50

TABLE_PHYSICAL_RULE_ITEM

AREA_TYPE

SPACING_RULE_SET

NET_SPACING_TYPE1 NET_SPACING_TYPE2

TABLE_SPACING_ASSIGNMENT_HEAD

TABLE_SPACING_ASSIGNMENT_ITEM

TABLE_SPACING_RULE_ITEM

TABLE_SPACING_ASSIGNMENT_ITEM

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_BOARD_INFO

VERSION

ALLEGRO

(MIL or MM)

BOARD UNITS

BOARD LAYERS

BOARD AREAS

LINE-TO-LINE SPACING

LAYER

SPACING_RULE_SET

WEIGHT

TABLE_SPACING_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_SPACING_RULE_ITEM

TABLE_PHYSICAL_RULE_ITEM

TABLE_SPACING_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

APPLE INC.

NONE

SCALE

REV.

A

D

C

B

A

D

C

B

8 7

6

5

4

3

2 1

8

7 6

5

4

3

2

1

THE INFORMATION CONTAINED HEREIN IS THE PROPRIETARY PROPERTY OF APPLE COMPUTER, INC. THE POSSESSOR AGREES TO THE FOLLOWING

II NOT TO REPRODUCE OR COPY IT

III NOT TO REVEAL OR PUBLISH IN WHOLE OR PART

I TO MAINTAIN THE DOCUMENT IN CONFIDENCE

NOTICE OF PROPRIETARY PROPERTY

DRAWING NUMBER

SHT

OF

SIZE

D

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

TABLE_PHYSICAL_RULE_ITEM

MINIMUM LINE WIDTH

ALLOW ROUTE ON LAYER?

LAYER

MINIMUM NECK WIDTH

MAXIMUM NECK LENGTH

DIFFPAIR PRIMARY GAP

DIFFPAIR NECK GAPPHYSICAL_RULE_SET

TABLE_PHYSICAL_RULE_HEAD

M75 Board-Specific Spacing & Physical Constraints

NOTE: 100_DIFF_BGA is 100-ohms differential impedance on outer layers and 95-ohms on inner layers.

0.100 MM0.100 MM

Y

55_OHM_SE

TOP,BOTTOM

55_OHM_SE

Y =STANDARD*

0.076 MM

=STANDARD

0.076 MM

=STANDARD

Y

0.125 MM

TOP,BOTTOM

50_OHM_SE

0.125 MM

* Y =STANDARD =STANDARD

0.090 MM 0.090 MM

50_OHM_SE =STANDARD

0.126 MM0.126 MM

TOP,BOTTOM

Y

46_OHM_SE

0.100 MM

=STANDARD

=STANDARD=STANDARDY*

0.100 MM

46_OHM_SE

45_OHM_SE

* Y

=STANDARD

0.105 MM 0.105 MM

=STANDARD =STANDARD

Y

TOP,BOTTOM

45_OHM_SE

0.150 MM 0.150 MM

0.185 MM0.185 MM

Y

40_OHM_SE

TOP,BOTTOM

0.131 MM0.131 MM

=STANDARD

=STANDARD=STANDARDY*

40_OHM_SE

92 92

A.0.0

051-7431

SYNC_MASTER=M87_MLB

SYNC_DATE=10/03/2007

PCB Rule Definitions

0.335 MM0.335 MM

27P4_OHM_SEYTOP,BOTTOM

0.240 MM0.240 MM

=STANDARD

27P4_OHM_SE

Y* =STANDARD=STANDARD

0.115 MM 0.115 MM

80_OHM_DIFF

Y

ISL9,ISL10

0.125 MM0.125 MM

0.115 MM0.115 MM

80_OHM_DIFF

YISL3,ISL4

0.125 MM 0.125 MM

0.080 MM

ISL3,ISL4

100_OHM_DIFF

0.080 MM

Y

0.200 MM0.200 MM

*

70_OHM_DIFF

=STANDARD

N

=STANDARD =STANDARD

=STANDARD=STANDARD

0.140 MM 0.140 MM

80_OHM_DIFF

ISL2,ISL11

Y

0.125 MM 0.125 MM

Y

ISL9,ISL10

0.075 MM 0.075 MM

100_DIFF_BGA

0.125 MM 0.125 MM

ISL3,ISL4 Y

0.075 MM 0.075 MM

100_DIFF_BGA

=100_OHM_DIFF

=100_OHM_DIFF =100_OHM_DIFF

*

=100_OHM_DIFF =100_OHM_DIFF

=100_OHM_DIFF

100_DIFF_BGA

=STANDARD

0.1 MM 0.1 MM

=STANDARD

Y*

1:1_DIFFPAIR

=STANDARD

0.089 MM0.089 MM

Y

110_OHM_DIFF

TOP,BOTTOM

0.330 MM0.330 MM

0.089 MM0.089 MM

ISL2,ISL11

110_OHM_DIFF

Y

0.330 MM0.330 MM

ISL9,ISL10

Y

0.077 MM 0.077 MM

110_OHM_DIFF

0.330 MM 0.330 MM

ISL3,ISL4

Y

0.077 MM 0.077 MM

110_OHM_DIFF

0.330 MM 0.330 MM

N

110_OHM_DIFF

*

=STANDARD=STANDARD

=STANDARD =STANDARD

=STANDARD

0.099 MM0.099 MM

TOP,BOTTOM

100_OHM_DIFF

Y

0.200 MM0.200 MM

0.099 MM

Y

0.099 MM

100_OHM_DIFF

ISL2,ISL11

0.200 MM0.200 MM

0.080 MM

Y

100_OHM_DIFF

0.080 MM

ISL9,ISL10

0.200 MM 0.200 MM

=STANDARD

*

100_OHM_DIFF

=STANDARD

N

=STANDARD

=STANDARD=STANDARD

90_OHM_DIFF

TOP,BOTTOM

0.130 MM0.130 MM

Y

0.220 MM0.220 MM

90_OHM_DIFF

ISL2,ISL11

Y

0.130 MM 0.130 MM

0.220 MM 0.220 MM

ISL9,ISL10

0.102 MM0.102 MM

90_OHM_DIFF

Y

0.220 MM0.220 MM

ISL3,ISL4

0.102 MM0.102 MM

90_OHM_DIFF

Y

0.220 MM0.220 MM

N

=STANDARD

*

=STANDARD

90_OHM_DIFF

=STANDARD =STANDARD

=STANDARD

TOP,BOTTOM

85_OHM_DIFF

Y

0.125 MM 0.125 MM

0.125 MM0.125 MM

ISL2,ISL11

85_OHM_DIFF

Y

0.125 MM 0.125 MM

Y

85_OHM_DIFF

0.101 MM 0.101 MM

ISL9,ISL10

0.125 MM 0.125 MM

Y

85_OHM_DIFF

ISL3,ISL4

0.101 MM 0.101 MM

0.125 MM 0.125 MM

=STANDARD

85_OHM_DIFF

*

=STANDARD

N

=STANDARD

=STANDARD =STANDARD

0.140 MM 0.140 MM

80_OHM_DIFF

TOP,BOTTOM

Y

0.125 MM 0.125 MM

80_OHM_DIFF

N*

=STANDARD =STANDARD

=STANDARD=STANDARD

=STANDARD

TOP,BOTTOM

Y

70_OHM_DIFF

0.185 MM 0.185 MM

0.125 MM 0.125 MM

Y

70_OHM_DIFF

0.185 MM 0.185 MM

ISL2,ISL11

0.125 MM 0.125 MM

Y

70_OHM_DIFF

0.149 MM

ISL9,ISL10

0.149 MM

0.125 MM0.125 MM

Y

70_OHM_DIFF

ISL3,ISL4

0.149 MM 0.149 MM

0.125 MM 0.125 MM

?

*

0.4 MM

4:1_SPACING

Y

ISL2,ISL11

0.250 MM 0.076 MM

55_OHM_SE

2:1_SPACING

?

0.2 MM

*

STANDARD

* Y

=DEFAULT =DEFAULT

12.7 MM

=DEFAULT =DEFAULT

0.1 MM

*

DEFAULT

?

=DEFAULTBGA_P2MM

?

* *

=DEFAULT

?

BGA_P3MM

=DEFAULT

?

BGA_P1MM

*

STANDARD

*

=DEFAULT

?

15.5.1

MM

NO_TYPE,BGA

TOP,ISL2,ISL3,ISL4,ISL5,ISL6,ISL7,ISL8,ISL9,ISL10,ISL11,BOTTOM

BGA

BGA_P2MM

*

CLK_SLOW

BGA

FSB_DSTB BGA_P3MMFSB_DSTB

0.18 MM

?

*

1.8:1_SPACING

?

*

0.15 MM

1.5:1_SPACING

2.5:1_SPACING

?

*

0.25 MM

?

*

3:1_SPACING

0.3 MM

BGA

CLK_PCIE

*

BGA_P2MM

BGA

BGA_P1MM

* *

BGA

*

BGA_P2MM

MEM_CLK

BGA

BGA_P2MM

*

CLK_FSB

BGA

BGA_P2MM

CLK_MED

*

Y

30 MM

*

0 MM 0 MM

=55_OHM_SE

DEFAULT

=55_OHM_SE

Apple A1261 Schematic

Specifications and Main Features

Frequently Asked Questions

User Manual