D R - 1 3 5 / 4 3 5 M k l l l
Service Manual
CONTENTS
SPECIFICATIONS |
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Mechanical Parts.............................. |
33 |
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GENERAL............................................... |
2 |
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Packing Parts................................... |
33 |
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TRANSMITTER....................................... |
2 |
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ACCESSORIES............................... |
33 |
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RECEIVER............................................. |
2 |
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ACCESSORIES (SCREW SET).......... |
33 |
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TNC (EJ41U).................................... |
, 34 |
CIRCUIT DISCRIPTION |
3,4 |
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TNC (EJ41U) Packing Parts............ . |
35 |
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1) |
Receiver System DR-135.......................... |
DR-135 ADJUSTMENT |
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2) |
Transmitter System DR-135....................... |
4 |
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3) |
PLL Synthesizer Circuit DR-135.................. |
5 |
1) |
Adjustment Spot.............................. |
36 |
4) |
Receiver System DR-435......... ................ |
5,6 |
2) |
VCO and RX Adjustment Specification.. |
37 |
5) |
Transmitter System DR-435....................... |
7 |
3) |
TXAdjustment Specification.............. |
37 |
6) |
PLL Synthesizer Circuit DR-435.................. |
7,8 |
4) |
RX Test Specification........................ |
38 |
7) |
CPU and Peripheral Circuit........................ |
8 |
5) |
TX Test Specification........................ |
39 |
8) |
Power Supply Circuit............................... |
9 |
DR-435 ADJUSTMENT |
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9) |
M38268MCA075GP (XA1130).................... |
1 0 -1 2 |
40 |
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1) |
Adjustment Spot.............................. |
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SEMICONDUCTOR DATA |
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2) |
VCO and RX Adjustment Specification.. |
41 |
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1) |
NJM7808FA (XA0102).............................. |
13 |
3) |
TX Adjustment Specification.............. |
42 |
2) |
TC4S66F (XA0115).................................. |
13 |
4) |
RX Test Specification........................ |
43 |
3) |
AN8010M (XA0119)................................. |
13 |
5) |
TX Test Specification........................ |
44 |
4) |
BU4052BCF (XA0236).............................. |
13 |
PC BOARD VIEW |
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5) |
TC4W53FU(XA0348)............................... |
14 |
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6) |
TA31136FN (XA0404)............................... |
14 |
1) |
CPU Unit Side ADR-135 (UP0536)..... |
45 |
7) |
LA4425A (XA0410).................................. |
15 |
2) |
CPU Unit Side B DR-135 (UP0536)..... |
45 |
8) |
BR24L32FJ (XA0604Z)............................. |
15 |
3) |
CPU Unit Side ADR-435 (UP0543)..... |
46 |
9) |
S-80845ALMP (XA0620)........................... |
15 |
4) |
CPU UnitSide B DR-435 (UP0543)..... |
46 |
10) L88MS05TLL (XA0675)............................. |
15 |
5) |
MAIN Unit Side ADR-135 (UP0536).... |
47 |
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11) S-816A50AMC (XA0925)........................... |
16 |
6) |
MAIN Unit Side B DR-135 (UP0536).... |
47 |
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12) LM2904PWR (XA1103)............................. |
16 |
7) |
MAIN Unit Side ADR-435 (UP0543).... |
48 |
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13) LM2902PWR (XA1106)............................. |
16 |
8) |
MAIN Unit Side B DR-435 (UP0543).... |
48 |
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14) MB15E07SR(XA1107).............................. |
17 |
9) |
TNC Unit Side A(UP0402) (option)..... |
49 |
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15) RA60H1317M1 (XA1108).......................... |
18 |
10) TNC Unit Side A(UP0402) (option)..... |
49 |
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16) S-AU82L(XA1142)................................... |
19 |
SCHEMATIC DIAGRAM |
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17) Transistor, Diode and LED Outline Drawing... |
2 0 |
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18) LCD Connection (TTR3626UPFDHN)......... |
21 |
1) |
CPU Unit DR-135............................. |
50 |
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2) |
CPU Unit DR-435............................. |
51 |
EXPLODED VIEW |
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3) |
MAIN Unit DR-135........................... |
52 |
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1) |
Top and FrontView.................................. |
2 2 |
4) |
MAIN Unit DR-435........................... |
53 |
2) |
Bottom View........................................... |
23 |
5) |
TNC Unit (option)............................. |
54 |
3) |
LCD Assembly........................................ |
24 |
BLOCK DIAGRAM |
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PARTS LIST |
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1) |
DR-135.......................................... |
55 |
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CPU Unit................................................. |
25,26 |
2) |
DR-435.......................................... |
56 |
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MAIN Unit DR-135.................................... |
26-29 |
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MAIN Unit DR-435....... ..... ...................... |
29-32 |
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A UNCO . n c
SPECIFICATIONS
■ |
General |
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Frequency coverage |
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DR-135 |
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DR-435 |
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118.000 - |
135.995MHz (AM RX ) |
350.000 - 511.995MHz ( RX ) |
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TM klll |
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136.000 ~ 173.995MHz ( RX ) |
430.000 ~ 449.995MHz ( TX ) |
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144.000 ~ 147.995MHz ( TX ) |
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EMklll |
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144.000 - 145.995MHz ( RX,TX ) |
430.000 ~ 439.995MHz ( RX.TX) |
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Operating mode |
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FM |
16K0F3E ( Wide mode) |
8K50F3E ( Narrow mode ) |
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Frequency resolution |
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5 , 8.33 , 10 , 12.5 , 15 , 20 , 25 , 30 , 50 |
kHz |
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Number of memory |
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1 0 0 |
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Channels |
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50ohm unbalanced |
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Antenna impedance |
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Power requirement |
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13.8V DC + / -15% (11.7 - 15.8 V ) |
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Ground method |
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Negative ground |
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Current drain |
Receive |
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0.6 A ( m ax.) |
0.4 A ( Squelched ) |
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Transmit |
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Approx. 12.0 A max. |
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Operating temperature |
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-10 °C |
~ |
60°C |
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Frequency stability |
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+- 2.5 ppm |
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Dimensions |
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142 ( w ) x 4 0 ( h ) x |
1 7 4 ( d ) mm |
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( 142 x 40 x 188 mm for projection included ) |
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Weight |
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Approx. 1.0 Kg |
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■ |
Transmitter |
50 W |
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35 W |
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Output power |
Hi |
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Mid |
20 W |
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20 W |
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Low |
Approx. 5 W |
Approx. 5 W |
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Modulation system |
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Variable reactance frequency modulation |
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Maximum |
Frequency |
+- 5kHz ( Wide mode ) |
+ / - 2.5kHz ( Narrow mode ) |
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deviation |
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Spurious emission |
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-6 0 dB |
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Adjacent channel power |
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- 60 dB |
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Noise and hum ratio |
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- 40 dB ( W ide mode ) |
- 34 dB ( Narrow mode ) |
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Microphone impedance |
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2 kohm |
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■ |
Receiver |
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Sensitivity |
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-1 4 dBu for 12 dB SINAD |
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Receiver circuit |
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Double conversion super-heterodyne |
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Intermediate frequency |
1st 21.7 MHz 2nd 450kHz |
1st 30.85 MHz |
2nd 455kHz |
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Squelch sensitivity |
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-1 8 dBu |
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Adjacent channel selectivity |
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- 65 dB ( Wide mode ) |
- 55 dB ( Narrow mode ) |
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Inter-modulation |
rejection |
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60 dB |
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ratio |
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Spurious and image rejection |
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70 dB |
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ratio |
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2.0 W ( 8ohm , 1 0 % T H D ) |
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Audio output power |
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! NOTE : All specifications are subject to change without notice or obligation.
2
CIRCUIT DESCRIPTION
1) Receiver System D R -135
The receiver system is a double super-heterodyne system with a 21.7MHz first IF and a 450kHz second IF.
1. Front End
The received signal at any frequency in the 136.000MHz to 173.995MHz range is passed through the low-pass filter (L116, L115, L114, L113, C204, C203, C202, C216 and C215) and tuning circuit (L105, L104 and D105, D104), and amplified by the RF amplifier (Q107). The signal from Q107 is then passed through the tuning circuit (L103, L102, and variable capacitor D103, D102) and converted into21.7MHz by the mixer (Q106). The tuning circuit, which consists of L105, L104, variable capacitor D105 and D104, L103, L102, variable capacitor D103 and D102, is controlled by the tracking voltage from the VCO. The local signal from the VCO is passed through the buffer (Q145), and supplied tothe source ofthe mixer (Q106). The radio uses the lower side ofthe super-heterodyne system.
2. IF Circuit
The mixer mixes the received signal with the local signal to obtain the sum of and difference between them. The crystal filter (XF102, XF101) selects 217 MHz frequency from the results and eliminates the signal of the unwanted frequencies. The first IF amplifier (Q105) then amplifies the signal of the selected frequency.
3. Demodulation Circuit
After the signal is amplified by the first IF amplifier (Q105), it is input to pin 16 ofthe demodulator IC (IC108). The second local signal of21.25MHz (shared with PLL IC reference oscillation), which is oscillated the external oscillator X102 (VCTCXO), is input through pin 1 of IC108. Then, these two signals are mixed by the internal mixer in IC108 and the result is converted into the second IF signal with a frequency of 450kHz. The second IF signal is output from pin 3 of IC108 to the ceramic filter (FL102 or FL101), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC108 through pin 5. The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circuit in IC 108, and output as an audio signal through pin 9.
4. Audio Circuit
The audio signal from pin 9 of IC 108 is amplified by the audio amplifier (IC120:A), and switched by the signal switch IC (IC111) and then input it to the de-emphasis circuit.
And is compensated to the audio frequency characteristics in the de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and amplified by the AF amplifier (IC120:B). The signal is then input to volume (VR1). The adjusted signal is sent to the audio power amplifier (1C117) through the pin 1 to drive the speaker.
3
5. Squelch Circuit
6.AIR Band Reception (T version only)
7. WIDE/NARROW Switching circuit
The detected output which is outputted from pin 9 of IC108 is inputted to pin 8 of IC108 after it was been amplified IC120:Aand it is outputted from pin 7 after the noise component was been,eliminated from the composed band pass filter in the built in amplifier ofthe IC, then the signal is rectified bythe internal diodein IC108 to convert into DC component. The adjusted voltage level at VR101 is delivered to the comparator of the CPU.
The voltage is led to pin 2 of CPU and compared with the setting voltage. The squelch will open ifthe input voltage is lower than the setting voltage. During open squelch, pin 30 (SQC) of the CPU becomes “L" level, AF control signal is begin controlled and sounds is outputted from speaker.
When the frequency is within 118.000 - 135.995MHz, Q113 automatically turns on, pin 5 of IC 121 becomes “H” level and the condition becomes in AM detection mode.
The receiver signal passed through the duplexer is let to the antenna switch (D107, D101). After passing through the band-pass filter, the signal is amplified by RF amplifier Q112. Secondly the signal is mixed with the signal from the first local oscillator in the first-mixer Q106, then converted into the first IF. Its unwanted signal is let to pin 16 of IC108. Then converted into the second IF.And is demodulated byAM decoder of Q118, and is output from Q108 as theAF signal.
The second IF 450kHz signal which passes through filter FL101 (wide) and FL102 (narrow) during narrow, changes its width using the width control switching D116 and D115.
2)Transmitter System D R -135
1.Modulator Circuit
The audio signal is converted to an electrical signal by the microphone, and input it to the microphone amplifier (Q6). Amplified signal which passes through mic-mute control IC109 is adjusted to an appropriate mic-volume by means of mic-gain adjust VR106.
IC114:D and C consists of two operational amplifiers; one amplifier (pin 12,13 and 14) is composed of pre-emphasis and IDC circuit and the other (pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency deviation is obtained by VR107. And input to the signal switch (IC113) (9600 bps packet signal input switch) and input to the cathode of the variable capacitor of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation.
2. Power Amplifier Circuit
The transmitted signal is oscillated by the VCO, amplified by the younger amplifier (Q115), and inputtothe final power module (IC110). The signal is then amplified by the final power module (IC110) and led to the antenna switch (D110) and low-pass filter (L113, L114, L115, L116, C215, C216, C202, C203 and C204), where unwanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna.
3. APC Circuit
Part of the transmission power from the low-pass filter is detected by D111, converted to DC. The detection voltage is passed through the APC circuit (IC114:A, 1C114:B), then it controls the APC voltage supplied to final power module IC110to fix the transmission power.
4
3) PLL Synthesizer Circuit D R -135
1.PLL
The dividing ratio is obtained by sending data from CPU (IC1) to pin 10 and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated signal from the VCO is amplified by the buffer (Q134 and Q135) and input to pin 8 of IC116. Each programmable divider in IC116 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz.
2.Reference Frequency Circuit
3.Phase Comparator Circuit
4.PLL Loop Filter Circuit
5.VCO Circuit
The reference frequency appropriate for the channel steps is obtained by dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according to the data from the CPU (IC1). When the resulting frequency is 5 kHz, channel step of 5, 10, 15, 20, 25, 30 and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz channel step is used.
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase comparator in the IC116 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained by the internal divider in IC116.
If a phase difference is found in the phase comparison between the reference frequency and the VCO output frequency, the charge pump output (pin 5) of IC116 generates a pulse signal, which is converted DC voltage by the PLL loop filter and input to the input to the variable capacitor of the VCO unit for oscillation frequency control.
A Colpitts oscillation circuit driven by Q131 directly oscillates the desired frequency. The frequency control voltage determine in the CPU (IC1) and PLL circuit is inputto the variable capacitor (D122 and D123). This change the oscillation frequency, which is amplified by the VCO buffer (Q134, Q145) and output from the VCO area.
6. VCO Shift Circuit
During transmission ortheAIR band Reception (118 ~ 136 MHz), the VCO shift circuit turns ON Q138, change control the capacitance of L123 and safely oscillates the VCO by means of Hsignal from pin 42 of IC1.
4) Receiver System DR435
The receiver system is a double super-heterodyne system with a 30.85MHz first IF and a 455kHz second IF.
1. Front End
The received signal at any frequency in the 430.000MHz to 439.995MHz range is passed through the low-pass filter ( L115, L114, L116, C204, C203, C202, C216 and C215) and amplified by the RF amplifier (Q107). The signal from Q107 is then passed through the BPF circuit (L103, L102) and converted into 30.85MHz by the mixer (Q106). The local signal from the VCO is passed through the buffer (Q134, Q145), and supplied to the source of the mixer (Q106). The radio uses the lower side of the super-heterodyne system.
5
2.IF Circuit
3.Demodulation Circuit
4. Audio Circuit
5. Squelch Circuit
6. WIDE/NARROW Switching circuit
The mixermixes the received signal with the local signal toobtain the sum of and difference between them. The crystal filter (XF101) selects 30.85 MHzfrequency from the results and eliminates the signal of the unwanted frequencies. The first IF amplifier (Q105) then amplifies the signal of the selected frequency.
After the signal is amplified by the first IF amplifier (Q105), it is input to pin16 of the demodulator IC (IC108). The second local signal of 30.395MHz (Crystal oscillator) is inputthrough pin 1 of IC108. Then, these two signals are mixed by the internal mixer in IC108 and the result is converted into the second IF signal with a frequency of 455kHz. The second IF signal is output from pin 3 of IC108 to the ceramic filter (FL101 or FL102), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC108 through pin 5.
The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circuit in IC 108, and output as an audio signal through pin 9.
The audio signal from pin 9 of IC 108 is amplified by the audio amplifier (IC120:A), and switched bythe signal switch IC (IC111) and then input it to the de-emphasis circuit.
And is compensated to the audio frequency characteristics in the de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and amplified bytheAF amplifier (IC120:B). The signal is then input to volume (VR1). The adjusted signal is sent to the audio power amplifier (IC117) through the pin 1 to drivethe speaker.
The detected output which is outputted from pin 9 of IC108 is inputted to pin 8 of IC108 after it was been amplified !C120:Aand it is outputted from pin 7 afterthe noise component was been eliminated from the composed band pass filter in the built in amplifier of the IC, then the signal is rectified bythe internal diode in IC108to convert into DC component. The adjusted voltage level at VR101 is delivered tothe comparator of the CPU.
The voltage is led to pin 2 of CPU and compared with the setting voltage. The squelch will open ifthe input voltage is lowerthan the setting voltage. During open squelch, pin 30 (SQC) of the CPU becomes “L” level, AF control signal is begin controlled and sounds is outputted from speaker.
The second IF 455kHz signal which passes through filter FL101 (wide) and FL102 (narrow) during narrow, changes its width using the width control switching D116 and D115.
6
5)Transmitter System DR435
1.Modulator Circuit
The audio signal is converted to an electrical signal by the microphone, and input it to the microphone amplifier (Q6). Amplified signal which passes through mic-mute control IC109 is adjusted to an appropriate mic-volume by means of mic-gain adjust VR106.
IC114:D and C consists of two operational amplifiers; one amplifier (pin 12,13 and 14) is composed of pre-emphasis and IDC circuit and the other (pin 8, 9 and 10) is composed of a splatter filter. The maximum frequency deviation is obtained by VR107. And input to the signal switch (IC113) (9600 bps packet signal input switch) and input to the cathode of the variable capacitor of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation.
2. Power Amplifier Circuit
The transmitted signal is oscillated by the VCO, amplified by the drive amplifier (Q138) and younger amplifier (Q115), and input to the final power module (IC110). The signal is then amplified by the final power module (IC110) and led to the antenna switch (D110) and low-pass filter (L116, L114, L115, C215, C216, C202, C203 and C204), where unwanted high harmonic waves are reduced as needed, and the resulting signal is supplied to the antenna.
3. APC Circuit
Part of the transmission power from the low-pass filter is detected by D111, converted to DC. The detection voltage is passed through the APC circuit (IC114:A, IC114:B), then it controls the APC voltage supplied to the final power module IC110 tofix the transmission power.
6)PLL Synthesizer Circuit DR435
1.PLL
The dividing ratio is obtained by sending data from CPU (IC1) to pin 10 and sending clock pulses to pin 9 of the PLL IC (IC116). The oscillated signal from the VCO is amplified by the buffer (Q134 and Q135) and input to pin 8 of IC116. Each programmable divider in IC116 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25 kHz.
2.Reference Frequency Circuit
3.Phase Comparator Circuit
4.PLL Loop Filter Circuit
The reference frequency appropriate for the channel steps is obtained by dividing the 21.25 MHz reference oscillation (X102) by 4250 or 3400, according to the data from the CPU (IC1). When the resulting frequency is 5 kHz, channel step of 5, 10, 15, 20, 25, 30 and 50 kHz are used. When it is 6.25 kHz, the 12.5 kHz channel step is used.
The PLL (IC116) uses the reference frequency, 5 or 6.25 kHz. The phase comparator in the 1C116 compares the phase of the frequency from the VCO with that of the comparison frequency, 5 or 6.25 kHz, which is obtained bythe internal divider in IC116.
If a phase difference is found in the phase comparison between the reference frequency and the VCO output frequency, the charge pump output (pin 5) of IC116 generates a pulse signal, which is converted DC voltage by the PLL loop filter and input to the input to the variable capacitor ofthe VCO unit foroscillation frequency control.
7
5. VCO Circuit
A Colpitts oscillation circuit driven by Q131 directly oscillates the desired frequency. The frequency control voltage determine in the CPU (IC1) and PLL circuit is inputto the variable capacitor (D122 and D123). This change the oscillation frequency, which is amplified by the VCO buffer (Q134, Q145) and outputfrom the VCO unit
7)CPU and Peripheral Circuits
1.LCD Display Circuit
The CPU turns ON the LCD via segment and common terminals with 1/4 the duty and 1/3 the bias, at the frame frequency is 64 Hz.
2. Dimmer Circuit
The dimmer circuit makes the output of pin 13 of CPU (JC1) into “H” level at set mode, so that Q9 and Q3 will turn ON to make the lamp control resistor R84 short and make its illumination bright. But on the other hand, ifthe dimmer circuit makes pin 13 Into “L” level, Q9 and Q3 will turn OFF, R84's illumination will become dimmer as its hang on voltage falls down in the working LED (D11, D2, D5, D3 and D6).
3. Reset and Backup
When the powerfrom the DC cable increases from Circuits 0 Vto 2.5 Vor more, “H" level reset signal is output from the reset IC (IC4) to pin 33 of the CPU (IC1), causing the CPU to reset. The reset signal , however, waits at 100, and dose not enter the CPU until the CPU clock (X1) has stabilized.
4. S (Signal) Meter Circuit
The DC potential of IF IC is inputto pin 1 ofthe CPU (IC1), converted from an analog to a digital signal, and displayed as the S-meter signal on the LCD.
5. DTMF Encoder
The CPU (IC1) is equipped with an internal DTMF encoder. The DTMF signal is output from pin 10, through R35, R34 and R261 (for level adjustment), and then through the microphone amplifier (IC114:A), and is sent to the variable capacitor ofthe VCOfor modulation. At the same time, the monitoring tone passes through the AF circuit and is output from the speaker.
6. Tone Encoder
The CPU (IC1) is equipped with an internal tone encoder. The tone signal (67.0 to 250.3 Hz) is output from pin 9 of CPU to the variable capacitor (D122 and D123) of the VCO for modulation.
7. DCS Encoder
The CPU (IC1) is equipped with an internal DCS code encoder. The code (023 to 754) is output from pin 9 of CPU to the voltage control pin of VCTCXO (X102) of the PLL reference oscillator. When DCS is ON, DCS MUTE circuit (Q126-ON, Q133-ON, Q132-OFF) works. The modulation activates in X102 side only.
8. CTCSS, DCS Decoder
The voice band of the AF output signal from pin 1 of IC120:A is cut by sharp active filter IC104:A, B and C (VCVS) and amplified, then led to pin 4 of CPU. The input signal is compared with the programmed tone frequency code in the CPU. The squelch will open when they match. During DCS, Q108 is ON, C419 is working and cut off frequency is lowered.
8
8) Power Supply Circuit
When power supply is ON, there is a "L" signal being inputted to pin 39 (PSW) of CPU which enables the CPU to work. Then, “H” signal is outputted from pin 41 (C5C) of CPU and drives ON the power supply switch control Q8 and Q7 which turns the 5VS ON. 5VS turns ON the PLL IC (1C116), main power supply switch Q127 and Q122, AF POWER IC117 and the 8V ofAVR (IC115). During reception, pin 29 (R5)of CPU outputs “H” level, Q124 is ON, and the reception circuits supplied by 8 V. While during transmission, pin 28 (T5) of CPU outputs “L” ievei which is reverse by Q11 so that the output in Q128 will be “H” level, Q123 is ON, and the transmission circuit is supplied by 8 V. Or, in the case when the condition of PLL is UNLOCK, “H” level is outputted from pin 14 of PLL IC, UNLOCK switch Q129 is ON, transmission switch Q128 is OFF which makes the transmission to stop.
1. ACC External Power Supply Terminal
When optional power supply cord EDC-37 etc. is connected to the external power supply terminal JK101, with ACC power supply ON, switch Q101 will turn ON, 5 V of AVR IC101 pin 2 (STB) becomes “L” which makes CSVto turn ON. With this, it can turn the power supply of the radio ON.
9
P67/AN7
P66/AN6
P65/AN5
P64/AN4
P63/SCLK22/AN3 P62/SCLK21/ AN2 P61/S0UT2/AN1 P60/SIN2/AN0 P57/ADT/DA2 P56/DA1 P55/CNTR1 P54/CNTR0 P53/RTP1 P52/RTP0 P51/PWM1 P50/PWM0 P47/SRDYT P46/SCLK1
P45/TXÜ
P44/RXD
P43/s¿/T0UT
P42/INT2
P41/JNT1
P40
P77
CO C/0Go
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SEG13
•SEG14
SEG15
■SEG16
•SEG17 -P30/SEG18 ■P31/SEG19 -P32/SEG20 ■P33/SEG21 ■P34/SEG22 •P35/SEG23 •P36/SEG24 -P37/SEG25 ■P00/SEG26 -PÛ1/SEG27 ■P02/SEG28 ■P03/SEG29 -P04/SEG30 -P05/SEG31 ■P06/SEG32 •P07/SEG33 -P10/SEG34 -P11/SEG35 ■P12/SEG36 -P13/SEÖ37
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3
(XA1130) M38268MCL075GP 9)
No. |
Terminal |
Signal |
I/O |
Description |
1 |
P67/AN7 |
SMT |
I |
S-meter input |
2 |
P66/AN6 |
SQL |
I |
Noise level input for squelch |
3 |
P65/AN5 |
BAT |
I |
Battery voltage input |
4 |
P64/AN4 |
TIN |
I |
CTCSS tone input / DCS code input |
5 |
P63/SCLK22/AN3 |
BP1 |
I |
Band plan 1 |
6 |
P62/SCLK21/AN2 |
BP2 |
I |
Band plan 2 |
7 |
P61/SOUT2/AN1 |
DCSW |
0 |
DCS signal mute |
8 |
P60/S1N2/AN0 |
RE2 |
I |
Rotary encoder input |
9 |
P57/ADT/DA2 |
TOUT |
0 |
CTCSS tone output / DCS tone output |
10 |
P56/DA1 |
DOUT |
0 |
DTMF output |
11 |
P55/CNTR1 |
SCL |
0 |
Serial clock for EEPROM |
12 |
P54/CNTR0 |
TBST |
0 |
Tone burst output |
13 |
P53/RTP1 |
BP4 |
I/O |
Band plan 4 / lamp dimmer HI / LOW switch |
14 |
P52/RTP0 |
MUTE |
I/O |
Microphone mute / Security alarm SW |
15 |
P51/PWM1 |
CLK |
o |
Serial clock output for PLL, scramble |
16 |
P50/PWM0 |
DATA |
I/O |
Serial data output for PLL scramble / PLL unlock signal input |
17 |
P47/SRDY1 |
TSTB |
I/O |
Trunking board detection / Strobe signal to trunking board |
18 |
P46/SCLK1 |
STB |
o |
Strobe for PLL IC |
19 |
P45/TXD |
UTX |
o |
UARTdata transmission output |
20 |
P44/RXD |
RTX |
I |
UARTdata reception output |
21 |
P43/cp/TOUT |
BEEP |
I/O |
Beep tone / Band plan 3 |
22 |
P42/INT2 |
SEC |
I |
Security voltage input |
23 |
P41/INT1 |
RE1 |
I |
Rotary encoder input |
24 |
P40 |
DSQ |
I |
Digital squelch input |
25 |
P77 |
PTT |
I |
PTT input |
26 |
P76 |
SSTB |
0 |
Strobe signal to scramble IC / Security mode |
27 |
P75 |
W/N |
0 |
Wide Narrow SW |
28 |
P74 |
T5 |
o |
TX power ON / OFF output |
29 |
P73 |
R5 |
0 |
RX power ON / OFF output |
30 |
P72 |
SQC |
0 |
SQL ON / OFF |
31 |
P71 |
C/S |
0 |
Digital scramble ON / OFF |
32 |
P70/INT0 |
BU |
I |
Backup signal detection input |
33 |
RESET |
RESET |
I |
Reset input |
34 |
XCIN |
Xcin |
- |
- |
35 |
XCOUT |
Xcout |
- |
- |
36 |
XIN |
Xin |
- |
Main clock input |
37 |
XOUT |
Xout |
- |
Main clock output |
38 |
VSS |
GND |
- |
CPU GND |
39 |
P27 |
PSW |
I |
Power switch input |
40 |
P26 |
SDA |
o |
Serial data for EEPROM |
41 |
P25 |
CSC |
0 |
C5V power ON / OFF output |
42 |
P24 |
AIR |
0 |
Air band SW / Tx middle power |
43 |
P23 |
LOW |
0 |
Tx low power |
44 |
P22 |
EXP |
0 |
Trunking / Packet data SW |
45 |
P21 |
SW6 |
I |
Key sw 6 (SQL) |
46 |
P20 |
SW5 |
I |
Key sw 5 (CALL) |
47 |
P17 |
SW4 |
I |
Key sw 4 (TSQ) |
48 |
P16 |
SW3 |
I |
Key sw 3 (MHz) |
49 |
P15/SEG39 |
SW2 |
I |
Key sw 2 (V/M) |
50 |
P14/SEG38 |
SW1 |
I |
Key sw 1 (FUNC) |
11
No. |
Terminal |
Signal |
I/O |
Description |
|
51 |
P13/SEG37 |
DOWN |
I |
Mic down input |
|
52 |
P12/SEG36 |
DUD |
I |
Digital unit detect |
|
53 |
P11/SEG35 |
SCR |
I |
Scramble IC ready signal / PTT input for 9600bps |
|
54 |
P10/SEG34 |
UP |
I |
Mic up input |
|
55 |
P07/SEG33 |
S33 |
0 |
|
|
56 |
P06/SEG32 |
S32 |
0 |
|
|
57 |
P05/SEG31 |
S31 |
0 |
|
|
58 |
P04/SEG30 |
S30 |
0 |
|
|
59 |
P03ÍSEG2Q |
S29 |
o |
|
|
60 |
P02/SEG28 |
S28 |
0 |
|
|
61 |
P01/SEG27 |
S27 |
0 |
|
|
62 |
P00/SEG26 |
S26 |
0 |
|
|
63 |
P37/SEG25 |
S25 |
0 |
|
|
64 |
P36/SEG24 |
S24 |
0 |
|
|
65 |
P35/SEG23 |
S23 |
0 |
|
|
66 |
P34/SEG22 |
S22 |
0 |
|
|
67 |
P33/SEG21 |
S21 |
0 |
|
|
68 |
P32/SEG20 |
S20 |
o |
|
|
69 |
P31/SEG19 |
S19 |
o |
|
|
70 |
P30/SEG18 |
S18 |
0 |
|
|
71 |
SEG17 |
S17 |
0 |
LCD segment signal |
|
72 |
SEG16 |
S16 |
0 |
||
|
|||||
73 |
SEG15 |
S15 |
0 |
|
|
74 |
SEG14 |
S14 |
0 |
|
|
75 |
SEG13 |
S13 |
0 |
|
|
76 |
SEG12 |
S12 |
0 |
|
|
77 |
SEG11 |
S11 |
0 |
|
|
78 |
SEG10 |
S10 |
0 |
|
|
79 |
SEG9 |
S9 |
0 |
|
|
80 |
SEG8 |
S8 |
o |
|
|
81 |
SEG7 |
S7 |
0 |
|
|
82 |
SEG6 |
S6 |
0 |
|
|
83 |
SEG5 |
S5 |
0 |
|
|
84 |
SEG4 |
S4 |
0 |
|
|
85 |
SEG3 |
S3 |
0 |
|
|
86 |
SEG2 |
S2 |
0 |
|
|
87 |
SEG1 |
S1 |
0 |
|
|
88 |
SEGO |
SO |
0 |
|
|
89 |
VCC |
VDD |
- |
CPU power terminal |
|
90 |
VREF |
Vref |
- |
AD converter power supply |
|
91 |
AVSS |
Avss |
- |
AD converter GND |
|
92 |
COM3 |
COM3 |
0 |
LCD COM3 output |
|
93 |
COM2 |
COM2 |
0 |
LCD COM2 output |
|
94 |
COM1 |
COM1 |
0 |
LCD COM1 output |
|
95 |
COMO |
COMO |
0 |
LCD COMO output |
|
96 |
VL3 |
VL3 |
- |
LCD power supply |
|
97 |
VL2 |
VL2 |
- |
LCD power supply |
|
98 |
C2 |
I |
- |
- |
|
99 |
C1 |
C1 |
- |
- |
|
100 |
VL1 |
VL1 |
I |
LCD power supply |
12
SEMICONDUCTOR DATA
1) NJM7808FA (XA0102)
8V (1A) Voltage Regulator
1. INPUT
2. COMMON
3. OUTPUT
1 2 3
2) TC4S66F (XA0115)
Bilateral Switch
5 4
B ______ a |
1. IN/OUT |
||
|
C 9 |
|
2. OUT/IN |
|
|
3. VSS |
|
|
|
|
|
b |
b |
b |
4. CONT |
5. VDD |
|||
1 |
2 |
3 |
|
3) AN8010M (XA0119)
10V (50mA) Voltage Regulator
■< |
|
* |
1. OUTPUT |
O |
|
* |
2. COMMON |
U |
u |
u |
3. INPUT |
|
|||
1 |
2 |
3 |
|
4) BU4052BF (XA0236)
Analog Multiplexer / De-multiplexer
5
a |
|
□ |
|
|
|
r p |
CONT |
Function (IN-OUT) |
|
|
|
|
||
a |
|
|
L |
Disconnect (Hi Z) |
|
|
H |
Connect (290ohm typ.) |
|
□ |
Ü b |
|
|
|
1 |
2 |
3 |
|
|
Vin
[4-1
1"i
&s
I
YO \T_ |
|
|
|
le] VDD |
|
Y2 [ T |
Y2 YO X2 |
1 X 2 |
|||
Y COMMON [ T |
Y |
|
XI |
7 ^ XI |
|
IN/OUT |
|||||
|
|
|
|||
Y3 | T |
Y3 |
X |
|
j3 ] X COMMON |
|
IN/OUT |
|||||
|
|
|
|||
INHIBIT |
A |
B COMMON |
ON SWITCH |
L |
L |
L |
XO YO |
L |
H |
L |
X1 Y1 |
Y1 [ T |
Y1 |
XO |
I 2] |
XO |
INHIBIT [ T |
INM |
X3 |
J j] |
X3 |
VEE | T |
VEE B |
A |
10] |
A |
L |
L |
H X Y |
X2Y2 |
L |
H |
. H |
X3 Y3 |
H |
* |
* |
NONE |
vss [T |
T ] B |
Don’t care
13
5) TC4W53FU (XA0348)
Multiplexer / De-multiplexer
8 7 6 5
P P P P
1 2 3 4
1. COMMON |
|
|
|
|
2. INH |
Control input |
ON channel |
||
3. VEE |
||||
INH |
A |
|||
4. VSS |
|
|||
L |
L |
ch 0 |
||
5. A |
||||
L |
H |
ch 1 |
||
6. ch 1 |
||||
H |
* |
NONE |
||
7. ch 0 |
||||
8. VDD |
Don’t’t care |
|
6) TA31136FN (XA0404)
Narrow Band FM IF IC
15 |
14 |
13 |
12 |
11 |
10 |
9 |
1.0SCIN |
9. AF OUT |
||
|
|
|
|
|
|
|
||||
|
n |
m |
|
|
h |
n |
2. OSC OUT |
10. QUAD |
||
|
|
|
3. |
MIX OUT |
11. IF OUT |
|||||
|
|
|
|
|
|
|
||||
|
|
|
|
|
|
|
4. Vcc |
12. |
RSSI |
|
|
|
|
|
|
|
|
5. |
IF IN |
13. |
N-DET |
|
|
|
|
|
|
|
6. |
DEC |
14. |
N-REC |
|
|
|
|
|
|
|
7. FILOUT |
15. |
GND |
|
|
|
|
|
|
|
|
8. |
FILIN |
16. |
MIX IN |
1 2 3 4 5 6 |
7 8 |
|
|
|
|
|||||
14
7) LA4425A (XA0410)
5W Audio Power Amplifier
|
1. |
Input |
LA4425 |
2. |
Small signal GND |
3. Large signal GND |
||
* * * |
4. |
Output |
|
5. Vcc |
|
1 2 3 4 5
8 ) BR24L32FJ (XA0604Z)
32K-Bit EEPROM
8 |
7 |
6 |
5 |
2. A1 |
|
n |
R |
R |
R |
||
3.A2 |
|||||
|
|
|
|
||
L32 |
|
|
4. Vss |
||
|
|
5. SDA |
|||
o * * * * * |
6. SCL |
||||
r |
m |
|
|
7. WP |
|
3 |
4 |
8. Vcc |
|||
1 2 |
|
||||
9) S-80845ALMP (XA0620)
4.5V Voltage Detector
5 |
|
4 |
1. |
GND |
f l . |
|
f l |
2. Vin |
|
B 6 6 * |
3. Vout |
|||
4. |
NC |
|||
b |
b |
b |
5. |
NC |
|
|
|||
1 |
2 |
3 |
|
|
Test Circuit
Name |
Function |
A0...A2 |
User Configurable Chip Select |
Vss |
Ground |
SDA |
Serial Address / Data / I/O |
SCL |
Serial Clock |
WP |
Write Protect Input |
Vcc |
+2.5 ~ 6.0V Power Supply |
10) L88MS05TLL (XA0675)
5V (500mA) Voltage Regulator with On/Off Function
1.Vin
2.STB
3.GND
4.Cn
5.Vout
GND
15
11) S-816A50AMC (XA0925)
External Transistor Type 5V Voltage Regulator with On/Off Function
5 |
|
4 |
|
|
n |
|
n |
1. |
EXT |
B A Z * |
2. |
Vss |
||
3. |
ON/OFF |
|||
|
|
|
4. |
Vin |
Ö |
d |
d |
5. |
Vout |
1 |
2 |
3 |
|
|
12) LM2904PWR (XA1103)
Dual Operational Amplifiers
8 7 6 5
|
|
1. |
OutputA |
• * |
|
2. |
Inverting InputA |
o |
3. |
Non-inverting InputA |
|
* |
4. GND |
||
|
CNJ |
5. |
Non-inverting Input B |
|
6. |
Inverting Input B |
|
o |
— I |
7. |
Output B |
w |
n |
8. Vcc |
|
|
|
||
1 2 3 |
|
|
|
13) LM2902PWR (XA1106)
Quad Operational Amplifiers
1413121110 9 |
8 |
1. |
OutputA |
|
|
|
|
||
|
|
|
2. |
Inverting InputA |
|
|
|
3. |
Non-inverting InputA |
|
|
|
4. |
Vcc |
|
|
|
5. |
Non-inverting Input B |
|
|
|
6. |
Inverting Input B |
|
|
|
7. |
Output B |
|
|
|
8. |
Output C |
|
|
|
9. |
Inverting Input C |
2 3 4 5 |
6 |
7 |
10. |
Non-inverting Input C |
11. GND |
||||
|
|
|
12. |
Non-inverting Input D |
|
|
|
13. |
Inverting Input D |
|
|
|
14. |
Output D |
16
14) MB15E07SR (XA1107)
PLL Synthesizer
16 15 14 13 12 11 10 9
1.0SCIN |
9. |
Clock |
|
2. |
N. C. |
10. |
Data |
3. |
Vp |
11. LE |
|
4. |
Vcc |
12. |
PS |
5. |
Do |
13. |
N. C. |
6. GND |
14. |
LD / fout |
|
7. |
Xfin |
15. |
N. C. |
8. fin |
16. |
N. C. |
|
1 2 3 4 5 6 7
OSC IN |
Reference |
Binary 14-bit |
Sff FC LDS CS |
|
Oscillator |
reference counter |
|
|
|
|
4-bit |
latch |
||
|
|
14-bit latch |
||
|
|
|
|
|
PS |
In te rm itte n t |
|
|
|
mods c o n tro l |
|
|
|
|
|
(power save) |
|
|
|
|
|
19-bit shift register |
||
LE |
1 - b i t |
|
|
|
co n tro l la tc h |
|
|
|
|
|
7-bit latch |
11-b it |
latch |
|
Data |
|
|||
|
|
|
|
|
|
|
Binaly 7-bit |
Binary |
11-bit |
Clock |
|
swallow |
programmable |
|
|
counter |
counter |
||
|
|
|||
|
|
|
|
fp |
Xfin |
Prescaler |
|
|
|
fin |
32/33 |
Sff |
|
|
64/65 |
|
|
||
VCC
GND
fr
Phase comparator
Lock detector
LD/fr/fp selector
Charge pump
LD/fout
Vp
Do
|
|
|
|
( Vcc = 2.7 to 5.0V, Ta = -40°C to +85oC ) |
||||
|
Parameter |
|
Symbo |
Condition |
Min. |
Typ. |
Max. |
Unit |
|
|
1 |
||||||
|
|
|
|
|
|
|
|
|
Power supply voltage |
|
Vcc |
- |
2.7 |
3.75 |
5.0 |
V |
|
Power supply current |
|
Icc |
2500MHz |
|
8.0 |
|
mA |
|
|
Vcc=A/p=3.75V |
|
|
|||||
LPF supply voltage |
|
Vp |
Vcc |
|
5.5 |
V |
||
|
- |
- |
||||||
Local oscillator input ievel |
Vfin |
100MHz to 300MHz |
-6 |
|
+2 |
dBm |
||
300MHz to 2500MHz |
-15 |
|
+2 |
|||||
Local |
oscillator |
input |
|
|
|
|||
fin |
- |
100 |
|
2500 |
MHz |
|||
frequency |
|
|
||||||
|
|
|
|
|
|
|
||
Xin input level |
|
Vxin |
- |
0.5 |
|
Vcc |
Vp-p |
|
Xin input frequency |
|
Fxin |
- |
3 |
|
F 40 |
MHz |
|
15) RA60H1317M1 (XA1108)
144 ~ 146MHz 60W RF Power Module
OUTLINE DRAWING
BLOCK DIAGRAM
© |
RF Input |
(Pin) |
^ |
|
(D |
Gate Voltage |
(VGG), |
Power Control |
|
(3) Drain Voltage |
(VDD), |
Battery |
||
(4) |
RF Output |
(Pout) |
|
|
(D |
RF Ground |
(Case) |
|
|
ABSOLUTE MAXIMUM RATING ( Tc = 25 °C, unless otherwise noted )
Symbol |
Parameter |
Conditions |
Ratings |
Unit |
VDD |
Drain Voltage |
VGG < 5V, ZG = ZL = 50ohm |
17 |
V |
VGG |
Gate Voltage |
VDD < 12.5V, Pin=50mW |
5.5 |
V |
IDD |
Drain Current |
ZG = ZL = 50ohm |
15 |
A |
Pin |
Input Power |
f = 1 35 - 175 MHz, Pin=50mW |
100 |
mW |
Pout |
Output Power |
ZG = ZL = 50ohm |
80 |
W |
Tease (OP) |
Operation Case Temperature |
|
-30 to +110 |
°C |
Tstg |
Storage Temprature |
|
-40 to +110 |
°C |
ELECTRICAL CHARACTERISTICS (Tc = 25 °C, unless otherwise noted )
Symbol |
Parameter |
f |
Frequency Range |
Pout |
Output Power |
v T |
Total Efficiency |
2fo |
2na Harmonic |
Pin |
Input VSWR |
IGG |
Gate Current |
- |
Stability |
|
|
- |
Load VSWR |
Tolerance |
Conditions
VDD = 12.5V
VGG = 5V
Pin = 50mW
VDD=10.0-15.2V, Pin=25-70mW,
Pout<70W (VGG control), Load
VSWR=3:1
VDD=15.2V, Pin=50mW, Pout=60W
(VGG control),
Load VSWR=8:1
Ratings |
|
Unit |
|
Min Typ |
Max |
||
|
|||
135 |
175 |
MHz |
|
60 |
|
W |
|
45 |
|
% |
|
|
-50 |
dBc |
|
|
3:1 |
- |
|
1 |
|
mA |
|
No parasitic |
|
|
|
oscillation |
|
- |
No degradation or destroy
18
16) S-AU82L (XA1142)
430 ~ 450MHz 60W RF Power Module
BLOCK DIAGRAM
(D RF Input (Pin)
(2) Gate Voltage (VGG), Power Control
(D Drain Voltage (VDD), Battery
(4) RF Output (Pout)
(D RF Ground (Frange)
ABSOLUTE MAXIMUM RATING ( Tc = 25°C, unless otherwise noted )
Symbol |
Parameter |
VDD |
Drain Voltage |
VGG |
Gate Voltage |
IDD |
Drain Current |
Pin |
input Power |
Pout |
Output Power |
Tease (OP) |
Operation Case Temperature |
Tstg |
Storage Temprature |
Conditions
VGG < 5V, Pi = 50mW, Po < 60W
VDD < 12.5V, Pin=50mW
VDD < 12.5V, VGG < 5V
12.5V < VDD < 16.5V, VGG = 5V, Pi = 50mW
Ratings Unit
16.5V
5.5 |
V |
15 |
A |
100 |
MW |
80 |
W |
-30 to +100 |
°C |
-40 to +100 |
°C |
ELECTRICAL CHARACTERISTICS ( Tc = 25 °C, unless otherwise noted )
Symbol |
Parameter |
f |
Frequency Range |
Pout |
Output Power |
n T |
Total Efficiency |
2fo |
2na Harmonic |
Pin |
Input VSWR |
IGG |
Gate Current |
- |
Stability |
|
|
- |
Load VSWR |
Tolerance |
Conditions |
Min |
Ratings |
Unit |
|
Typ Max |
||||
|
|
|||
|
400 |
470 |
MHz |
|
VDD = 12.5V |
60 |
|
W |
|
VGG = 5V |
40 |
|
% |
|
Pin = 50mW |
|
-30 |
dBc |
|
ZL = 50ohm |
|
3.0 |
- |
|
VDD=10.5-16.5V, VGG=0-5V, Pin=50mW, |
|
1 |
mA |
|
All sprious output |
|
|||
Pout<60W (VGG control), Load VSWR=3:1 |
than 60dB bellow |
- |
||
ALL PHASE |
desired signal |
|
||
VDD=10.5-16.5V, VGG=0-5V, Pin=50mW, |
No degradation |
|
||
Pout=60W (VGG control), Load |
|
|
|
|
VSWR=20:1 ALL PHASE |
|
|
|
|
19
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