Alinco DR-140E, DR-140TE1, DR-140TE2, DR-140T Service Manual

3) Receiver

Receiving System:	Dual Conversion Superheterodyne
IF Frequencies:	First: 30.85MHz; Second: 455kHz
Sensitivity:	12dB SINAD -15dB|i
Selectivity:	More than ± 6kHz at -6dB; Less than ± 15kHz at -60dB
Audio Output:	More than 2.5 Watts @10% distortion
Speaker Impedance:	8£2

Specifications are subject to change without notice or obligation. Performance specifications apply only to transmit bands. Names of certain products mentioned in this catalog are used for identification purposes only and may be trademarks or registered trademarks of their respective company.

7.AF and Mute Circuit (Main unit)

The AF signal from IC1 is filtered by the low-pass filter amplifier (Q2) and led to the high-pass filter amplifier (Q1), and output to the AF gain volume. Q3 and Q4 are switched ON/OFF by AFC signal from CPU, then AF signal is muted when the squelch is ON.

8.Squelch Circuit (CPU unit)

IC1 has the noise amplifier, rectifier circuit and comparator circuit. The noise signal from pin12 of IC1 is input to the noise amplifier (pin19 of IC1) and passed through buffer amplifier (Q28), rectified by D8, then it is input to comparator circuit (pin 21 of IC1). When the noise signal is decreased by the receiving signal, the compara­ tor output SD becomes low.

2) Transmitter System

1.Microphone Amplifier Circuit (CPU unit)

The voice from external microphone is amplified by the microphone amplifier (Q303), and passed through the microphone mute circuit (Q304), the signal is input to the microphone gain potentiometer (VR3) in the main unit.

2.Limiter Amplifier Circuit (Main unit)

The signal from microphone gain potentiometer (VR3) is amplified by limiter amplifier and low-pass (IC4). The resulting signal is passed through the modula­ tion adjustment potentiometer (VR4), then input to VCO unit. IC4A is limiter amplifier with pre-emphasis characteristics. IC4B is low-pass filter.

3.Modulation Circuit (VCO unit)

The adjusted AF signal in VR4 is led to the VCO unit. The frequency modulation is executed when the audio signal is supplied to the D207.

4.Drive Amplifier Circuit (Main unit)

5.RF Younger Amplifier Circuit (Main unit)

The signal from VCO unit is input to the drive amplifier (IC3). IC3 has high gain of approximately 30dB and high level of approximately 10dBm wide band amplifier.

The signal from IC3 is passed through diode switch D12, and input to younger amplifier Q13. Q13 has approximately 15dB gain and output level is 400mW. The output signal of younger amplifier is led to the PA amplifier (IC2).

6.RF Power Amplifier Circuit (Main unit)

IC2 is the power module, which obtains stable output power (50W T/E, 35W TE1/ TE2) within the band. The signal of younger amplifier is amplified by the PA amplifier (IC2), and then led to the antenna switch circuit.

7.Antenna Switch Circuit (RF unit)

When transmitting, D11 and D9 are ON in the antenna switch circuit, L14 becomes parallel components. This causes the output signal of IC2 not to go to the RX circuit. The signal is led to the antenna connector passing through the low-pass filter (L15 ~ L18, C76 ~ C80, C148).

8.APC Circuit (RF unit)

When the TX signal is passed through the low-pass filter, matching voltage and mismatching voltage are detected by the D14 and D15. When the antenna impedance is 50£2, the detected voltage of D14 and D15 are minimum. But when the antenna impedance is not 50ft, the detected voltage becomes higher. The detected voltage is passed through the power setting potentiometer (VR1), and the signal is amplified by Q17, Q16 and Q14. The transmitting power is controlled by the voltage of V1 (IC2) and collector voltage of Q13. When the temperature of the unit goes high, the powerdown circuit (R104, TH2) prevents the device from being damaged.

3) PLL Circuit

1. Summary

The PLL circuit uses PLL IC (IC201) equipped with built-in dual modulus prescaler.

The PLL IC serial data is sent from CPU.

The VCO output frequency divided by N is compared with reference frequency in the phase comparator.

2.Reference Oscillator Circuit (Main unit)

The reference frequency is obtained by X3 (12.8MHz), and its output is led to the

VCO unit.

3.Loop Filter Circuit (VCO unit)

The phase error of phase comparator is integrated to DC voltage by loop filter circuit, and supplied to D201, D202 of varicap diode jn VCO unit. The time constant of the active loop filter (consisting of Q202 and Q210) is determined by C211, C212, R228, R210. The output is passed th ro u g h th e lag filte r (R213,

C208), and input to VCO unit.

4.VCO Circuit (VCO unit)

The circuit is the Hartley oscillator circuit (Q201), and the signal is output passing through the buffer amplifier (Q204). C247 is switched by D205 to vary the capaci­ tance, and the oscillating frequency range is shifted.

No.	Name	Pin Name	I/O	D escription	H
36	P22	KEY 3	I	Key 3 CALL	OFF
37	P21	KEY 4	I	Key 4 V/M	OFF
38	P20	KEY 5	I	Key 5 FUN	OFF
39	S31	S31	0	Segment 31 output	Pulse
40	S30	S30	0	Segment 30 output	Pulse
41	S29	S29	0	Segment 29 output	Pulse
42	S28	S28	0	Segment 28 output	Pulse
43	S27	S27	0	Segment 27 output	Pulse
44	S26	S26	0	Segment 26 output	Pulse
45	S25	S25	0	Segment 25 output	Pulse
46	S24	S24	0	Segment 24 output	Pulse
47	S23	S23	0	Segment 23 output	Pulse
48	S22	S22	0	Segment 22 output	Pulse
49	S21	S21	0	Segment 21 output	Pulse
50	S20	S20	o	Segment 20 output	Pulse
51	S19	S19	o	Segment 19 output	Pulse
52	S18	S18	o	Segment 18 output	Pulse
53	S17	S17	o	Segment 17 output	Pulse
54	S16	S16	0	Segment 16 output	Pulse
55	S15	S15	o	Segment 15 output	Pulse
56	S14	S14	0	Segment 14 output	Pulse
57	S13	S13	0	Segment 13 output	Pulse
58	S12	S12	0	Segment 12 output	Pulse
59	S11	S11	0	Segment 11 output	Pulse
60	S10	S10	0	Segment 10 output	Pulse
61	S9	S9	0	Segment 9 output	Pulse
62	S8	S8	0	Segment 8 output	Pulse
63	S7	S7	o	Segment 7 output	Pulse
64	S6	S6	o	Segment 6 output	Pulse
65	S5	S5	0	Segment 5 output	Pulse
66	S4	S4	o	Segment 4 output	Pulse
67	S3	S3	o	Segment 3 output	Pulse
68	S2	S2	o	Segment 2 output	Pulse
69	S1	S1	0	Segment 1 output	Pulse
70	SO	SO	o	Segment 0 output	Pulse

L	H iZ	Pull UP
ON		o
ON		o
ON		o

No.

Name

Pin Name

I/O

Description

H

L

HiZ

Pull UP

71	vcc	VDD	I	Power supply
72	VREF	VREF	I	Reference voltage input
73	AVSS	GND	I	GND
74	COM3	COM3	O	LCD common 3 output	Pulse
75	COM2	COM2	0	LCD common 2 output	Pulse
76	COM1	COM1	0	LCD common 1 output	Pulse
77	COMO	COMO	0	LCD common 0 output	Pulse
78	VL3	VL3	I	LCD power supply input
79	VL2	VL2	I	LCD power supply input
80	VL1	VL1	I	LCD power supply input

9

SEMICONDUCTOR DATA

1) AK2341 (XA0239)

CTCSS Encoder/Decoder

	Pin	Pin	I/O	Function	RXIN	d =	1
	No.	Name
	1	RXIN	I	RX Signal Input	RXINO	n z	2
	2	RXINO	0	AMP2 Output
	3	TXINO	o	AMP1 Output	TXINO	n z	3
	4	TXIN	I	TX Audio Input
	5	RXOUT	0	RX Audio Output	TXIN	n z	4
	6	TXOUT	0	TX Audio Output
	7	VDD	-	Power Supply (1.8 ~ 5.5V)	RXOUT	n z	5
	8	XIN	I	Crystal Terminal (3.6864MHz)
	9	XOUT	o	Crystal Terminal (3.6864MHz)	TXOUT	n z	6
	10	STB	I	Strobe for Serial Data
	11	SDATA	I	Serial Data	VDD	n z	7
	12	SCLK	I	Serial Clock
	13	DCS	I	DCS Input	XIN	n z	8
	14	DETOUT	0	Tone Detection Output (Detect: Low)
	15	VSS	-	Ground	XOUT	n z	9
	16	DREF	I	Tone Detection Level Adjust Input
	17	TLINP	I	RX Tone Signal Reference Input	STB	n z	10
	18	TLINN	I	RX Tone Signal Input
	19	TLINO	o	AMP3 Output	SDATA	[Z Z	11
	20	RXTONE	o	RX Tone Signal Output
	21	TXTONE	o	TX Tone Signal Output	SCLK	n z	12
	22	AGNDIN	I	Analog Ground Input
	23	AGND	0	Analog Ground Output
	24	BIAS	I	Bias Input

Block Diagram

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7s

PO CO

24 Z U BIAS

23 = ] AGND

22 ZZ2 AGNDIN

21 = □ TXTONE

20 zzn RXTONE

19 Z D TLINO

18 Z □ TLINN

17 ZZ3 TLINP

16 = □ DREF

15 = □ VSS

14 = l DETOUT

13 =Z1 DCS

10

5) M56760FP (XA0235)

540MHz Frequency Synthesizer

Serial data input	S l t =	1
terminal
Clock input terminal	ere n z	2
Reset input terminal	RST C Z	3
			2
Reference Bias	REF tZ Z	4	CJ1
input terminal			o
	FIN n z		o>
Local Oscillator input		5	o
terminal fmax =540MHz			T I
Output p o rtl terminal	swi n z	6	"U
Output port2-terminal	SW 2 I—	7
G round terminal	G N D I----	8

Function Table

P/N input	Phase	PD output
High or Low	Locked	Hi-Z
High	Lead	High
High	Lag	Low
Low	Lead	Low
Low	Lag	High

	16	= ]v c c	Power supply
			terminal
			3 - 5 .5 V 14mA
	15	XIN	Reference oscillator
			input terminal
	14	ZZÏ XOUT	Reference oscillator
			output terminal
	13		Phase detector output
		H D LOCK	terminal
			when locked Low
	12	ZZÏPD	Phase detector output
			terminal
	11	= □ LFI	Low pass filter input
			terminal
	10	ZZ] LFO	Low pass filter
			output terminal
	9	= D P /N	Phase switch input terminal
			of phase com parator

XIN

XOUT

FIN

REF

SI

CPS

RST

LFI

LFO

6)M67746 (XA0412)

14 4 - 148MHz 60W RF Power Module

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D M67746

1

2

3

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	3 O	to	R-E
	CLO	4-*		s !
			Q. ^
	C CO	CO		il £

	~o	Ratings	Symbol	Ratings	Unit
	c	Supply voltage	Vcc	17	V
	3
	C	Total current	Icc	20	A
4		Input power	Pin (max)	600	mW
		Output power	Po(max)	70	W
		Operation case temperature	Tc(op)	-30 t o +110	°C
		Storage temperature	Tstg	-40 t o +110	° 0
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7) M68702H (XA0444)

1 5 0 - 175MHz 60W
RF Power Module	(TE2)

Ratings	Symbol	Ratings	Unit
Supply voltage	Vcc	17	V
Total current	Icc	20	A
Input power	Pin (max)	600	mW
Output power	Po(max)	75	W
Operation case temperature	Tc(op)	-30 t o +110	°C
Storage temperature	Tstg	-40 t o +110	°C

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8) M68702L (XA0445)

1 3 5 - 160MHz 60W
RF Power Module	(TE1)

Ratings	Symbol	Ratings	Unit
Supply voltage	Vcc	17	V
Total current	Icc	20	A
Input power	Pin (max)	600	mW
Output power	Po(max)	75	W
Operation case temperature	Tc(op)	-30 t o +110	°C
Storage temperature	Tstg	-40 t o +110	°C

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