TS2G~16GCFX500 |
CFast Card |
Description
Transcend CFast cards are designed to satisfy high performance requirements using a SATA 3Gb/s interface. As a removable device, it is easier to plug and remove in space-limited applications; such as thin-clients or industrial PCs. Complaint with CFast 1.0 standard, CFast is your best choice as an embedded SATA storage solution.
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Placement
Dimensions
Side |
Millimeters |
Inches |
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A |
42.8 |
1.685 |
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B |
36.4 |
1.433 |
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C |
3.3 |
0.13 |
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D |
0.6 |
0.02 |
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Features
•RoHS compliant
•CFast Specification Version 1.0 Compliant
•Power Supply: 3.3V±5%
•Operating Temperature: 0oC to 70oC
•Storage Temperature: -40oC to 85oC
•Humidity (Non condensation): 0% to 95%
•Built-in 8-bit/512Byte ECC (Error Correction Code) functionality ensures highly reliable of data transfer.
•Global wear-leveling algorithm eliminate excessive write operation and extends product life.
•Suppot StaticDataRefresh & EarlyRetirement technology to monitor error bit level and react before data is corrupted.
•Support S.M.A.R.T (Self-defined)
•Support Security Command
•Fully compatible with devices and OS that support the SATA 3Gb/s standard
•Non-volatile SLC Flash Memory for outstanding data retention
•Durability of Connector: 10,000 times
Transcend Information Inc. |
1 |
V0.5
TS2G~16GCFX500 |
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CFast Card |
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Specifications |
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Physical Specification |
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Form Factor |
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CFast |
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Storage Capacities |
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2GB~16 GB |
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Length |
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42.8 ± 0.1 |
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Dimensions (mm) |
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Width |
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36.4 ± 0.15 |
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Height |
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3.3 ± 0.1 |
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Input Voltage |
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3.3V ± 5% |
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TBD |
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Weight |
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Connector |
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CFAST connector |
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Environmental Specifications |
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Operating Temperature |
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0 to 70 |
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- 40 to 85 |
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Storage Temperature |
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0% to 95% (Non-condensing) |
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Humidity |
Operating |
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Non-Operating |
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0% to 95% (Non-condensing) |
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Regulations |
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Compliance |
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CE, FCC and BSMI |
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Performance |
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Model P/N |
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Read |
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Write |
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Random Read |
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Random Write |
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TS2GCFX500 |
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56 MB/s |
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27MB/s |
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50 MB/s |
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8 MB/s |
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TS4GCFX500 |
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56 MB/s |
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49MB/s |
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50 MB/s |
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12 MB/s |
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TS8GCFX500 |
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102 MB/s |
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88MB/s |
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83MB/s |
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17 MB/s |
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TS16GCFX500 |
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108 MB/s |
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91MB/s |
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89 MB/s |
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18 MB/s |
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Note: 25 , test on ASUS P4S800-MX, 1GB RAM, Windows® XP Version 2002 SP2, benchmark utility HDBENCH (version 3.4006), copied file 1GB.
Transcend Information Inc. |
2 |
V0.5
TS2G~16GCFX500 |
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CFast Card |
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Actual Capacity |
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Model P/N |
User Max. LBA |
Cylinder |
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Head |
Sector |
TS2GCFX500 |
3,865,680 |
3,835 |
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16 |
63 |
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TS4GCFX500 |
7,732,368/ |
7,671 |
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16 |
63 |
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TS8GCFX500 |
15,465,344 |
15,343 |
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16 |
63 |
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TS16GCFX500 |
30,932,992 |
16,383 |
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15 |
63 |
Power Requirements
Input Voltage |
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3.3V ± 5% |
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Mode |
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Max. (mA) |
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Write(peak) |
352 |
Power Consumption |
Read(peak) |
371 |
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Idle(peak) |
141 |
SHOCK & Vibration Test
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Condition |
Standard |
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Mechanical Shock Test |
1500G, 0.5ms, 3 axis |
IEC 60068-2-27 |
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Vibration Test |
20G (Peak-to-Peak) |
IEC 60068-2-6 |
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20Hz to 2000Hz (Frequency) |
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Transcend Information Inc. |
3 |
V0.5
TS2G~16GCFX500 |
CFast Card |
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Package Dimensions
Below figure illustrates the Transcend CFastTM. All dimensions are in mm.
Transcend Information Inc. |
4 |
V0.5
TS2G~16GCFX500 |
CFast Card |
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Pin Assignments |
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Pin No. |
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Pin Name |
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7-pin Signal Segment |
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S1 |
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GND |
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S2 |
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A+ |
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S3 |
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A- |
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S4 |
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GND |
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S5 |
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B- |
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S6 |
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B+ |
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S7 |
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GND |
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17-pin Power Segment |
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PC1 |
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CDI |
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PC2 |
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GND |
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PC3 |
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NC |
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PC4 |
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NC |
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PC5 |
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NC |
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PC6 |
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NC |
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PC7 |
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GND |
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PC8 |
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NC |
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PC9 |
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NC |
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PC10 |
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NC |
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PC11 |
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NC |
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PC12 |
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NC |
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PC13 |
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3.3V |
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PC14 |
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3.3V |
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PC15 |
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GND |
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PC16 |
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GND |
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PC17 |
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CDO |
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Pin Layout
Transcend Information Inc. |
5 |
V0.5
TS2G~16GCFX500 |
CFast Card |
|
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Block Diagram |
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CFASTTM Interface
SATA SSD CTL
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Flash |
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Flash |
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Flash |
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Flash |
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Transcend Information Inc. |
6 |
V0.5
TS2G~16GCFX500 |
CFast Card |
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Reliability
Wear-Leveling algorithm
The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block with the lowest erase count among the free blocks. This is known as dynamic wear leveling. When the free blocks' erase count is higher than a threshold value plus data blocks', it will activate the static wear leveling, replacing the not so frequently used user blocks with the high erase count free blocks.
ECC algorithm
Using 8bit BCH Error Correction Code with each channel, the controller can correct 8 random bits per 512 byte data sector for SLC NAND flash. The hardware executes parity generation and error detection/correction features.
StaticDataRefresh Technology
Normally, ECC engine corrections are taken place without affecting the host normal operations. As time passes by, the number of error bits accumulated in the read transaction exceeds the correcting capability of the ECC engine, resulting in corrupted data being sent to the host. To prevent this, the controller monitors the error bit levels at each read operation; when it reaches the preset threshold value, the controller automatically performs data refresh to “restore” the correct charge levels in the cell. This implementation practically restores the data to its original, error-free state, and hence, lengthening the life of the data.
EarlyRetirement Technology
The StaticDataRefresh feature functions well when the cells in a block are still healthy. As the block ages over time, it cannot reliably store charge anymore, EarlyRetirement enters the scene. EarlyRetirement works by moving the static data to another block (a health block) before the previously used block becomes completely incapable of holding charges for data. When the charge loss error level exceeds another threshold value (higher from that for StaticDataRefresh), the controller automatically moves its data to another block. In addition, the original block is then marked as a bad block, which prevents its further use, and thus the block enters the state of “EarlyRetirement.”
Note that, through this process, the incorrect data are detected and effectively corrected by the ECC engine, thus the data in the new block is stored error-free.
Transcend Information Inc. |
7 |
V0.5
TS2G~16GCFX500 |
CFast Card |
|
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CFastTM Interface
Out of bank signaling
There shall be three Out Of Band (OOB) signals used/detected by the Phy: COMRESET, COMINIT, and COMWAKE. COMINIT, COMRESET and COMWAKE OOB signaling shall be achieved by transmission of either a burst of four Gen1 ALIGNP primitives or a burst composed of four Gen1 Dwords with each Dword composed of four D24.3 characters, each burst having a duration of 160 UIOOB. Each burst is followed by idle periods (at common-mode levels), having durations as depicted in Figure 4 and Table 2.
Figure 4 : OOB signals
Table 2 : OOB signal times
Transcend Information Inc. |
8 |
V0.5