microSDHC Card series
Ver1.0 High Capacity microSD Card
Description
Transcend High Capacity microSD Card series are specifically designed to meet the High Capacity, High Definition Audio and Video requirement for the latest Digital Cameras, DV Recorders, Mobile Phones, etc. The new defined Speed Class enables the host to support AV applications to perform real time recording to the microSD memory card.
Placement |
1 2 3 4 5 6 7 8 |
Front |
Back |
Pin Definition
Features
•RoHS compliant product.
•Operating Voltage: 2.7 ~ 3.6V
•Operating Temperature: -25 ~ 85°C
•Durability: 10,000 insertion/removal cycles
•Compatible with SD Specification Ver. 2.0
•Comply with SD File System Specification Ver. 2.0
•Mechanical Write Protection Switch with microSD adapter
•Supports Speed Class Specification Class 6
•Supports Copy Protection for Recorded Media (CPRM) for SD-Audio
•Form Factor: 11mm x 15mm x 1mm
Pin No. |
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SD Mode |
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SPI Mode |
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Name |
Type |
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Description |
Name |
Type |
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Description |
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1 |
DAT2 |
I/O/PP |
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Data Line [Bit2] |
RSV |
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Reserved |
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2 |
CD/DAT3 |
I/O/PP |
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Card Detect / Data Line [Bit3] |
CS |
I |
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Chip Select |
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3 |
CMD |
PP |
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Command / Response |
DI |
I |
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Data In |
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4 |
VDD |
S |
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Supply voltage |
VDD |
S |
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Supply voltage |
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5 |
CLK |
I |
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Clock |
SCLK |
I |
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Clock |
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6 |
VSS |
S |
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Supply voltage ground |
VSS |
S |
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Supply voltage ground |
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7 |
DAT0 |
I/O/PP |
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Data Line [Bit0] |
DO |
O/PP |
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Data out |
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8 |
DAT1 |
I/O/PP |
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Data Line [Bit1] |
RSV |
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Reserved |
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S: Power Supply; I:Input; O:Output; PP:Push-Pull
Transcend Information Inc. |
1 |
microSDHC Card series
Ver1.0 High Capacity microSD Card
Architecture
Transcend Information Inc. |
2 |
microSDHC Card series
Ver1.0 High Capacity microSD Card
Bus Operating Conditions
• General
Parameter |
Symbol |
Min. |
Max. |
Unit |
Remark |
Peak voltage on all lines |
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-0.3 |
VDD+0.3 |
V |
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All Inputs |
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Input Leakage Current |
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-10 |
10 |
µA |
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All Outputs |
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Output Leakage Current |
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-10 |
10 |
µA |
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• Power Supply Voltage
Parameter |
Symbol |
Min. |
Max. |
Unit |
Remark |
Supply voltage |
VDD |
2.7 |
3.6 |
V |
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Output High Voltage |
VOH |
0.75* VDD |
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V |
IOH=-100uA@VDD Min. |
Output Low Voltage |
VOL |
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0.125* VDD |
V |
IOL=100uA@VDD Min. |
Input High Voltage |
VIH |
0.625* VDD |
VDD+0.3 |
V |
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Input Low Voltage |
VIL |
VSS-0.3 |
0.25* VDD |
V |
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Power up time |
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250 |
ms |
From 0v to VDD Min. |
• Current Consumption
The current consumption is measured by averaging over 1 second.
•Before first command: Maximum 15 mA
•During initialization: Maximum 100 mA
•Operation in Default Mode: Maximum 100 mA
•Operation in High Speed Mode: Maximum 200 mA
•Operation with other functions: Maximum 500 mA.
•Bus Signal Line Load
The total capacitance CL the CLK line of the SD Memory Card bus is the sum of the bus master capacitance CHOST, the bus capacitance CBUS itself and the capacitance CCARD of each card connected to this line:
CL = CHOST + CBUS + Ν*CCARD
Where N is the number of connected cards.
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Parameter |
Symbol |
Min. |
Max. |
Unit |
Remark |
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Pull-up resistance |
RCMD |
10 |
100 |
kΩ |
To prevent bus floating |
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RDAT |
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Bus signal line capacitance |
CL |
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40 |
pF |
1 card |
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CHOST+CBUS shall not exceed |
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30 pF |
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Transcend Information Inc. |
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3 |
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microSDHC Card series
Ver1.0 High Capacity microSD Card
Single card capacitance |
CCARD |
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10 |
pF |
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Maximum signal line inductance |
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16 |
nH |
fPP ≤ 20 MHz |
Pull-up resistance inside card (pin1) |
RDAT3 |
10 |
90 |
kΩ |
May be used for card |
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detection |
Note that the total capacitance of CMD and DAT lines will be consist of CHOST, CBUS and one CCARD only because they are connected separately to the SD Memory Card host.
Host should consider total bus capacitance for each signal as the sum of CHOST, CBUS, and CCARD, these parameters are defined by per signal. The host can determine CHOST and CBUS so that total bus capacitance is less than the card estimated capacitance load (CL=40 pF). The SD Memory Card guarantees its bus timing when total bus capacitance is less than
maximum value of CL (40 pF).
Transcend Information Inc. |
4 |
microSDHC Card series
Ver1.0 High Capacity microSD Card
• Bus Signal Levels
As the bus can be supplied with a variable supply voltage, all signal levels are related to the supply voltage.
To meet the requirements of the JEDEC specification JESD8-1A and JESD8-7, the card input and output voltages shall be within the following specified ranges for any VDD of the allowed voltage range:
Parameter |
Symbol |
Min. |
Max. |
Unit |
Remark |
Output HIGH voltage |
VOH |
0.75* VDD |
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V |
IOH = -100 µA @VDD min |
Output LOW voltage |
VOL |
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0.125* VDD |
V |
IOL = -100 µA @VDD min |
Input HIGH voltage |
VIH |
0.625* VDD |
VDD + 0.3 |
V |
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Input LOW voltage |
VIL |
VSS – 0.3 |
0.25* VDD |
V |
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Transcend Information Inc. |
5 |
microSDHC Card series
Ver1.0 High Capacity microSD Card
• Bus Timing
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Parameter |
Symbol |
Min |
Max. |
Unit |
Remark |
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Clock CLK (All values are referred to min (VIH) and max (VIL) |
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Clock frequency Data Transfer Mode |
fPP |
0 |
25 |
MHz |
CCARD ≤ 10 pF, (1 card) |
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Clock frequency Identification Mode |
fOD |
0(1)/100 |
400 |
KHz |
CCARD ≤ 10 pF, (1 card) |
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Clock low time |
tWL |
10 |
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ns |
CCARD ≤ 10 pF, (1 card) |
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Clock high time |
tWH |
10 |
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ns |
CCARD ≤ 10 pF, (1 card) |
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Clock rise time |
tTLH |
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10 |
ns |
CCARD ≤ 10 pF, (1 card) |
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Clock fall time |
tTHL |
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10 |
ns |
CCARD ≤ 10 pF, (1 card) |
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Inputs CMD, DAT (referenced to CLK) |
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Input set-up time |
tISU |
5 |
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ns |
CCARD ≤ 10 pF, (1 card) |
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Input hold time |
tIH |
5 |
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ns |
CCARD ≤ 10 pF, (1 card) |
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Outputs CMD, DAT (referenced to CLK) |
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Transcend Information Inc. |
|
6 |
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microSDHC Card series
Ver1.0 High Capacity microSD Card
Output Delay time during Data Transfer Mode |
tODLY |
0 |
14 |
ns |
CL ≤ 40 pF, (1 card) |
Output Delay time during Identification Mode |
tODLY |
0 |
50 |
ns |
CL ≤ 40 pF, (1 card) |
(1) 0 Hz means to stop the clock. The given minimum frequency range is for cases were continues clock is required
Transcend Information Inc. |
7 |
microSDHC Card series
Ver1.0 High Capacity microSD Card
• Bus Timing (High Speed Mode)
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Parameter |
Symbol |
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Min |
Max. |
Unit |
Remark |
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Clock CLK (All values are referred to min (VIH) and max (VIL) |
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Clock frequency Data Transfer Mode |
fPP |
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0 |
50 |
MHz |
CCARD ≤ 10 pF, (1 card) |
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Clock low time |
tWL |
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7 |
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ns |
CCARD ≤ 10 pF, (1 card) |
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Clock high time |
tWH |
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7 |
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ns |
CCARD ≤ 10 pF, (1 card) |
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Clock rise time |
tTLH |
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3 |
ns |
CCARD ≤ 10 pF, (1 card) |
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Clock fall time |
tTHL |
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3 |
ns |
CCARD ≤ 10 pF, (1 card) |
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Inputs CMD, DAT (referenced to CLK) |
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Input set-up time |
tISU |
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6 |
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ns |
CCARD ≤ 10 pF, (1 card) |
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Input hold time |
tIH |
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2 |
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ns |
CCARD ≤ 10 pF, (1 card) |
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Outputs CMD, DAT (referenced to CLK) |
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Transcend Information Inc. |
8 |
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