Transcend TS16GCF600, TS8GCF600, TS32GCF600 DATASHEET

TS8G~32GCF600		600X CompactFlash Card
	Description	Features

Dedicated to fulfilling the demanding requirements of performance-conscious photographers, Transcend proudly releases its Extreme Plus 600X CompactFlash cards with Turbo MLC technology. With its amazing performance, the Transcend 600x CompactFlash memory card allows the professional photographers and enthusiasts to get the most from your digital single lens reflex (DSLR) camera. Users are guaranteed to makes consecutive shooting and non-stop video recording and share their digital artwork with the world!

Placement

•CompactFlash Specification Version 4.1 Complaint

•RoHS compliant products

•Single Power Supply: 3.3V±5% or 5V±10%

•Operating Temperature: -25oC to 85oC

•Storage Temperature: -40oC to 85oC

•Operating Humidity (Non condensation): 0% to 95%

•Storage Humidity (Non condensation): 0% to 95%

•Operation Modes:

9PC Card Memory Mode

9PC Card IO Mode

9True IDE Mode

•True IDE Mode supports:

9Ultra DMA Mode 0 to Ultra DMA Mode 6 (Ultra DMA mode 5/6 must supply with 3.3V)

9MultiWord DMA Mode 0 to MultiWord DMA Mode 4

9PIO Mode 0 to PIO Mode 6

•PC Card Mode supports up to Ultra DMA Mode 6

•True IDE mode: Removable Disk (Default)

•PC Card Mode: Removable Disk (Default)

•Durability of Connector: 10,000 times

•Built-in 15 bit ECC (Error Correction Code) functionality

•Support Global Wear-Leveling to extend product life

•Compliant to CompactFlash, PC Card Mode, and ATA standards

Dimensions

Transcend Information Inc.

1

V1.5

	TS8G~32GCF600						600X CompactFlash Card
	Interface Specification
		Drivers				No Device Driver Required
						ATA/ATAPI 7
		ATA Compatibility				PIO Mode 0 - 6
						Multiword mode 0 - 4
						UDMA Mode 0 - 6
	Physical Specification
		Form Factor				Compact Flash Card
		Storage Capacities				8 GB to 32 GB
				Length		36.40 ± 0.15
		Dimensions (mm)		Width		42.80 ± 0.10
				Height		3.30 ± 0.10
	Environmental Specifications
		Operating Temperature				-25 to 85
		Storage Temperature				-40 to 85
	Humidity
	Operating Humidity (Non condensation)						0% to 95%
	Storage Humidity (Non condensation)						0% to 95%

* Note: 24-hours chamber test on ASUS Striker 2 Extreme, 1GB RAM, Windows® XP Version 2002 SP3.

Power Consumption

	Product		TS8GCF600	TS16GCF600	TS32GCF600
	Power	Standby	2.4mA	2.5mA	2.5mA
	Consumption	Read	222.8mA	232.8mA	233.5mA
	(DC 3.3V @25 )
		Write	218.1mA	211.5mA	231.7mA

Transcend Information Inc.

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V1.5

TS8G~32GCF600				600X CompactFlash Card
Actual Capacity
	Model P/N	User LBA	Cylinder	Head	Sector
	TS8GCF600	15662304	15538	16	63
	TS16GCF600	31293360	31045	16	63
	TS32GCF600	62537328	62041	16	63
* Note: FAT32 format

Transcend

Transcend Information Inc.

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V1.5

TS8G~32GCF600		600X CompactFlash Card

Block Diagram

Transcend Information Inc.

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V1.5

TS8G~32GCF600		600X CompactFlash Card

Transcend Information Inc.

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V1.5

TS8G~32GCF600

600X CompactFlash Card

Pin Assignments and Pin Type

PC Card Memory Mode

PC Card I/O Mode

True IDE Mode4

Pin

Signal

Pin

In, Out Type

Pin Num

Signal

Pin

In, Out

Pin

Signal

Pin

In, Out

Num

Name

Type

Name

Type

Type

Num

Name

Type

Type

1

GND

Ground

1

GND

Ground

1

GND

Ground

2

D03

I/O

I1Z, OZ3

2

D03

I/O

I1Z, OZ3

2

D03

I/O

I1Z, OZ3

3

D04

I/O

I1Z, OZ3

3

D04

I/O

I1Z, OZ3

3

D04

I/O

I1Z, OZ3

4

D05

I/O

I1Z, OZ3

4

D05

I/O

I1Z, OZ3

4

D05

I/O

I1Z, OZ3

5

D06

I/O

I1Z, OZ3

5

D06

I/O

I1Z, OZ3

5

D06

I/O

I1Z, OZ3

6

D07

I/O

I1Z, OZ3

6

D07

I/O

I1Z, OZ3

6

D07

I/O

I1Z, OZ3

7

-CE1

I

I3U

7

-CE1

I

I3U

7

-CS0

I

I3Z

8

A10

I

I1Z

8

A10

I

I1Z

8

A102

I

I1Z

9

-OE

I

I3U

9

-OE

I

I3U

9

-ATA SEL

I

I3U

10

A09

I

I1Z

10

A09

I

I1Z

10

A092

I

I1Z

11

A08

I

I1Z

11

A08

I

I1Z

11

A082

I

I1Z

12

A07

I

I1Z

12

A07

I

I1Z

12

A072

I

I1Z

13

VCC

Power

13

VCC

Power

13

VCC

Power

14

A06

I

I1Z

14

A06

I

I1Z

14

A062

I

I1Z

15

A05

I

I1Z

15

A05

I

I1Z

15

A052

I

I1Z

16

A04

I

I1Z

16

A04

I

I1Z

16

A042

I

I1Z

17

A03

I

I1Z

17

A03

I

I1Z

17

A032

I

I1Z

18

A02

I

I1Z

18

A02

I

I1Z

18

A02

I

I1Z

19

A01

I

I1Z

19

A01

I

I1Z

19

A01

I

I1Z

20

A00

I

I1Z

20

A00

I

I1Z

20

A00

I

I1Z

21

D00

I/O

I1Z, OZ3

21

D00

I/O

I1Z, OZ3

21

D00

I/O

I1Z, OZ3

22

D01

I/O

I1Z, OZ3

22

D01

I/O

I1Z, OZ3

22

D01

I/O

I1Z, OZ3

23

D02

I/O

I1Z, OZ3

23

D02

I/O

I1Z, OZ3

23

D02

I/O

I1Z, OZ3

24

WP

O

OT3

24

-IOIS16

O

OT3

24

-IOCS16

O

ON3

25

-CD2

O

Ground

25

-CD2

O

Ground

25

-CD2

O

Ground

26

-CD1

O

Ground

26

-CD1

O

Ground

26

-CD1

O

Ground

27

D111

I/O

I1Z, OZ3

27

D111

I/O

I1Z, OZ3

27

D111

I/O

I1Z, OZ3

28

D121

I/O

I1Z, OZ3

28

D121

I/O

I1Z, OZ3

28

D121

I/O

I1Z, OZ3

29

D131

I/O

I1Z, OZ3

29

D131

I/O

I1Z, OZ3

29

D131

I/O

I1Z, OZ3

30

D141

I/O

I1Z, OZ3

30

D141

I/O

I1Z, OZ3

30

D141

I/O

I1Z, OZ3

31

D151

I/O

I1Z, OZ3

31

D151

I/O

I1Z, OZ3

31

D151

I/O

I1Z, OZ3

32

-CE21

I

I3U

32

-CE21

I

I3U

32

-CS11

I

I3Z

33

-VS1

O

Ground

33

-VS1

O

Ground

33

-VS1

O

Ground

Transcend Information Inc.

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V1.5

TS8G~32GCF600

600X CompactFlash Card

PC Card Memory Mode

PC Card I/O Mode

True IDE Mode4

Pin

Signal Name

Pin

In, Out

Pin

Signal Name

Pin

In, Out

Pin

Signal Name

Pin

In, Out

Num

Type

Type

Num

Type

Type

Num

Type

Type

-HIOE

-HIOE

-HIOE7

34

HSTROBE10

I

I3U

34

HSTROBE10

I

I3U

34

HSTROBE8

I

I3Z

HDMARDY11

-HDMARDY11

-HDMARDY9

35

-IOWR

I

I3U

35

-IOWR

I

I3U

35

-IOWR7

I

I3Z

STOP10,11

STOP10,11

STOP8,9

36

-WE

I

I3U

36

-WE

I

I3U

36

-WE3

I

I3U

37

READY

O

OT1

37

-IREQ

O

OT1

37

INTRQ

O

OZ1

38

VCC

Power

38

VCC

Power

38

VCC

Power

39

-CSEL5

I

I2Z

39

-CSEL5

I

I2Z

39

-CSEL

I

I2U

40

-VS2

O

OPEN

40

-VS2

O

OPEN

40

-VS2

O

OPEN

41

RESET

I

I2Z

41

RESET

I

I2Z

41

-RESET

I

I2Z

-WAIT

-WAIT

IORDY7

ON1

42

-DDMARDY10

O

OT1

42

-DDMARDY10

O

OT1

42

-DDMARDY8

O

OT113

DSTROBE11

DSTROBE11

DSTROBE9

43

-INPACK

O

OT1

43

-INPACK

O

OT1

43

DMARQ

O

OZ1

-DMARQ12

-DMARQ12

44

-REG

I

I3U

44

-REG

I

I3U

44

-DMACK 6

I

I3U

-DMACK 12

DMACK 12

45

BVD2

O

OT1

45

-SPKR

O

OT1

45

-DASP

I/O

I1U, ON1

46

BVD1

O

OT1

46

-STSCHG

O

OT1

46

-PDIAG

I/O

I1U, ON1

47

D081

I/O

I1Z,

47

D081

I/O

I1Z,

47

D081

I/O

I1Z, OZ3

OZ3

OZ3

48

D091

I/O

I1Z,

48

D091

I/O

I1Z,

48

D091

I/O

I1Z, OZ3

OZ3

OZ3

49

D101

I/O

I1Z,

49

D101

I/O

I1Z,

49

D101

I/O

I1Z, OZ3

OZ3

OZ3

50

GND

Ground

50

GND

Ground

50

GND

Ground

Note: 1) These signals are required only for 16 bit accesses and not required when installed in 8 bit systems. Devices should allow for 3-state

signals not to consume current.

2)The signal should be grounded by the host.

3)The signal should be tied to VCC by the host.

4)The mode is required for CompactFlash Storage Cards.

5)The -CSEL signal is ignored by the card in PC Card modes. However, because it is not pulled upon the card in these modes, it should not be left floating by the host in PC Card modes. In these modes, the pin should be connected by the host to PC Card A25 or grounded by the host.

6)If DMA operations are not used, the signal should be held high or tied to VCC by the host. For proper operation in older hosts: while DMA operations are not active, the card shall ignore this signal,including a floating condition

7)Signal usage in True IDE Mode except when Ultra DMA mode protocol is active.

8)Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Write is active.

9)Signal usage in True IDE Mode when Ultra DMA mode protocol DMA Read is active.

10)Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Write is active.

11)Signal usage in PC Card I/O and Memory Mode when Ultra DMA mode protocol DMA Read is active.

12)Signal usage in PC Card I/O and Memory Mode when Ultra DMA protocol is active.

Transcend Information Inc.

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V1.5

TS8G~32GCF600		600X CompactFlash Card

Input Leakage Current

Note: In Table 1 below, x refers to the characteristics described in table 2. For example, I1U indicates a pull-up resistor with a type 1 input characteristic.

Table 1: Input Leakage Current

Type	Parameter	Symbol	Conditions	MIN	TYP	MAX	Units
IxZ	Input Leakage Current	IL	Vih = Vcc / Vil = Gnd	-1		1	μA
IxU	Pull-Up Resistor	RPU1	Vcc = 5.0V	50k		500k	Ohm
IxD	Pull-Down Resistor	RPD1	Vcc = 5.0V	50k		500k	Ohm

Note: The minimum pull-up resistor resistance meets the PCMCIA PC Card specification of 10k ohms but is intentionally higher in the CompactFlash Specification to reduce power use.

Input Characteristics

Table 2: Input Characteristics

Type

Parameter

Symbol

MIN

TYP

MAX

MIN

TYP

MAX

Units

VCC = 3.3 V

VCC = 5.0 V

1

Input Voltage

Vih

2.4

0.6

4.0 1

0.8

Volts

CMOS

Vil

2

Input Voltage

Vih

1.5

0.6

2.0

0.8

Volts

CMOS

Vil

Input Voltage

Vth

1.8

2.8

Volts

3

CMOS Schmitt

Vtl

1.0

2.0

Trigger

Notes: 1) The host provides a logic output high voltage for a CMOS load of .9 x VCC. For a 5 volt product, this translates to .9 x 4.5 = 4.05 volts minimum Voh.

Output Drive Type

Note: In Table 3 below, x refers to the characteristics described in Table 4. For example, OT3 refers to Totem pole output with a type 3 output drive characteristic.

Table 3: Output Drive Type

Type	Output Type	Valid Conditions
OTx	Totempole	Ioh & Iol
OZx	Tri-State N-P Channel	Ioh & Iol
OPx	P-Channel Only	Ioh Only
ONx	N-Channel Only	Iol Only

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V1.5

TS8G~32GCF600		600X CompactFlash Card

Output Drive Characteristics

Table 4: Output Drive Characteristics

Type	Parameter	Symbol	Conditions	MIN	TYP	MAX	Units
		Voh	Ioh = -4 mA	Vcc
1	Output Voltage			-0.8V			Volts
		Vol	Iol = 4 mA			Gnd
						+0.4V
		Voh	Ioh = -4 mA	Vcc
2	Output Voltage			-0.8V			Volts
		Vol	Iol = 4 mA			Gnd
						+0.4V
		Voh	Ioh = -4 mA	Vcc
3	Output Voltage			-0.8V			Volts
		Vol	Iol = 4 mA			Gnd
						+0.4V
X	Tri-State Leakage	Ioz	Vol = Gnd	-10		10	μA
	Current		Voh = Vcc

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V1.5

TS8G~32GCF600				600X CompactFlash Card
Signal Description
	Signal Name	Dir.	Pin	Description
A10 – A00		I	8,10,11,12,	These address lines along with the -REG signal are used to select the following:
(PC Card Memory Mode)			14,15,16,17,	The I/O port address registers within the CompactFlash Storage Card , the
			18,19,20	memory mapped port address registers within the CompactFlash Storage Card,
				a byte in the card's information structure and its configuration control and status
				registers.
A10 – A00				This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
A02 - A00		I	18,19,20	In True IDE Mode, only A[02:00] are used to select the one of eight registers
(True IDE Mode)				in the Task File, the remaining address lines should be grounded by the host.
BVD1		I/O	46	This signal is asserted high, as BVD1 is not supported.
(PC Card Memory Mode)
-STSCHG				This signal is asserted low to alert the host to changes in the READY and Write
(PC Card I/O Mode)				Protect states, while the I/O interface is configured. Its use is controlled by the
Status Changed				Card Config and Status Register.
-PDIAG				In the True IDE Mode, this input / output is the Pass Diagnostic signal in the
(True IDE Mode)				Master / Slave handshake protocol.
BVD2		I/O	45	This signal is asserted high, as BVD2 is not supported.
(PC Card Memory Mode)
-SPKR				This line is the Binary Audio output from the card. If the Card does not support
(PC Card I/O Mode)				the Binary Audio function, this line should be held negated.
-DASP				In the True IDE Mode, this input/output is the Disk Active/Slave Present signal in
(True IDE Mode)				the Master/Slave handshake protocol.
-CD1, -CD2		O	26,25	These Card Detect pins are connected to ground on the CompactFlash Storage
(PC Card Memory Mode)				Card. They are used by the host to determine that the CompactFlash Storage
				Card is fully inserted into its socket.
-CD1, -CD2				This signal is the same for all modes.
(PC Card I/O Mode)
-CD1, -CD2				This signal is the same for all modes.
(True IDE Mode)

Transcend Information Inc.

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V1.5

TS8G~32GCF600				600X CompactFlash Card
	Signal Name	Dir.	Pin	Description
-CE1, -CE2		I	7,32	These input signals are used both to select the card and to indicate to the card
				whether a byte or a word operation is being performed. -CE2 always accesses
(PC Card Memory Mode)				the odd byte of the word.-CE1 accesses the even byte or the Odd byte of the
Card Enable				word depending on A0 and -CE2. A multiplexing scheme based on A0,-CE1,
				-CE2 allows 8 bit hosts to access all data on D0-D7. See Table 27, Table 29,
				Table 31, Table 35, Table 36 and Table 37.
-CE1, -CE2				This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
Card Enable
-CS0, -CS1				In the True IDE Mode, -CS0 is the address range select for the task file
				registers while -CS1 is used to select the Alternate Status Register and the
(True IDE Mode)
				Device Control Register.
				While –DMACK is asserted, -CS0 and –CS1 shall be held negated and the
				width of the transfers shall be 16 bits.
-CSEL		I	39	This signal is not used for this mode, but should be connected by the host to PC
(PC Card Memory Mode)				Card A25 or grounded by the host.
-CSEL				This signal is not used for this mode, but should be connected by the host to PC
(PC Card I/O Mode)				Card A25 or grounded by the host.
-CSEL				This internally pulled up signal is used to configure this device as a Master or a
(True IDE Mode)				Slave when configured in the True IDE Mode.
				When this pin is grounded, this device is configured as a Master.
				When the pin is open, this device is configured as a Slave.
D15 - D00		I/O	31,30,29,28,	These lines carry the Data, Commands and Status information between the host
(PC Card Memory Mode)			27,49,48,47,	and the controller. D00 is the LSB of the Even Byte of the Word. D08 is the LSB
			6,5,4,3,2,	of the Odd Byte of the Word.
			23, 22, 21
D15 - D00				This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
D15 - D00				In True IDE Mode, all Task File operations occur in byte mode on the low order
(True IDE Mode)
				bus D[7:0] while all data transfers are 16 bit using D[15:0].
GND		--	1,50	Ground.
(PC Card Memory Mode)
GND				This signal is the same for all modes.
(PC Card I/O Mode)
GND				This signal is the same for all modes.
(True IDE Mode)
Transcend Information Inc.				11
				V1.5

TS8G~32GCF600				600X CompactFlash Card
	Signal Name	Dir.	Pin	Description
-INPACK		O	43	This signal is not used in this mode.
(PC Card Memory Mode except
Ultra DMA Protocol Active)
-INPACK				The Input Acknowledge signal is asserted by the CompactFlash Storage Card
				when the card is selected and responding to an I/O read cycle at the address that
(PC Card I/O Mode except Ultra				is on the address bus. This signal is used by the host to control the enable of any
DMA Protocol Active)				input data buffers between the CompactFlash Storage Card and the CPU.
Input Acknowledge
				Hosts that support a single socket per interface logic, such as for Advanced
				Timing Modes and Ultra DMA operation may ignore the –INPACK signal from the
				device and manage their input buffers based solely on Card Enable signals.
-DMARQ				This signal is a DMA Request that is used for DMA data transfers between host
(PC Card Memory Mode -Ultra				and device. It shall be asserted by the device when it is ready to transfer data to
DMA Protocol Active)				or from the host. For Multiword DMA transfers, the direction of data transfer is
-DMARQ				controlled by -HIOE and -IOWR. This signal is used in a handshake manner with
				(-)DMACK, i.e., the device shall wait until the host asserts (-)DMACK before
(PC Card I/O Mode -Ultra DMA
Protocol Active)				negating (-)DMARQ, and re-asserting (-)DMARQ if there is more data to
DMARQ				transfer.
				In PCMCIA I/O Mode, the -DMARQ shall be ignored by the host while the host is
(True IDE Mode)
				performing an I/O Read cycle to the device. The host shall not initiate an I/O
				Read cycle while -DMARQ is asserted by the device.
				In True IDE Mode, DMARQ shall not be driven when the device is not selected in
				the Drive-Head register.
				While a DMA operation is in progress, -CS0 (-CE1)and -CS1 (-CE2) shall be held
				negated and the width of the transfers shall be 16 bits.
				If there is no hardware support for True IDE DMA mode in the host, this output
				signal is not used and should not be connected at the host. In this case, the BIOS
				must report that DMA mode is not supported by the host so that device drivers
				will not attempt DMA mode operation.
				A host that does not support DMA mode and implements both PC Card and True
				IDE modes of operation need not alter the PC Card mode connections while in
				True IDE mode as long as this does not prevent proper operation in any mode.
-HIOE		I	34	This signal is not used in this mode.
(PC Card Memory Mode except
Ultra DMA Protocol Active)				This is an I/O Read strobe generated by the host. This signal gates I/O data onto
-HIOE				the bus from the CompactFlash Storage Card when the card is configured to use
(PC Card I/O Mode except Ultra				the I/O interface.
DMA Protocol Active)
-HIOE				In True IDE Mode, while Ultra DMA mode is not active, this signal has the same
				function as in PC Card I/O Mode.
(True IDE Mode – Except Ultra
DMA Protocol Active)
-HDMARDY				In all modes when Ultra DMA mode DMA Read is active, this signal is asserted
				by the host to indicate that the host is ready to receive Ultra DMA data-in bursts.
(All Modes - Ultra DMA Protocol				The host may negate – HDMARDY to pause an Ultra DMA transfer.
DMA Read)
HSTROBE				In all modes when Ultra DMA mode DMA Write is active, this signal is the data
(All Modes - Ultra DMA Protocol				out strobe generated by the host. Both the rising and falling edge of HSTROBE
DMA Write)				cause data to be latched by the device. The host may stop generating
				HSTROBE edges to pause an Ultra DMA data-out burst.
Transcend Information Inc.				12
				V1.5

TS8G~32GCF600				600X CompactFlash Card
	Signal Name	Dir.	Pin	Description
-IOWR		I	35	This signal is not used in this mode.
(PC Card Memory Mode– Except
Ultra DMA Protocol Active)
-IOWR				The I/O Write strobe pulse is used to clock I/O data on the Card Data bus into the
				CompactFlash Storage Card controller registers when the CompactFlash
(PC Card I/O Mode –Except Ultra
				Storage Card is configured to use the I/O interface.
DMA Protocol Active)
				The clocking shall occur on the negative to positive edge of the signal (trailing
				edge).
-IOWR				In True IDE Mode, while Ultra DMA mode protocol is not active, this signal has
(True IDE Mode – Except Ultra				the same function as in PC Card I/O Mode. When Ultra DMA mode protocol is
				supported, this signal must be negated before entering Ultra DMA mode
DMA Protocol Active)
				protocol.
STOP				In All Modes, while Ultra DMA mode protocol is active, the assertion of this signal
(All Modes – Ultra DMA Protocol				causes the termination of the Ultra DMA data burst.
Active)
-OE		I	9	This is an Output Enable strobe generated by the host interface. It is used to read
(PC Card Memory Mode)				data from the CompactFlash Storage Card in Memory Mode and to read the CIS
				and configuration registers.
-OE				In PC Card I/O Mode, this signal is used to read the CIS and configuration
(PC Card I/O Mode)				registers.
-ATA SEL				To enable True IDE Mode this input should be grounded by the host.
(True IDE Mode)
READY		O	37	In Memory Mode, this signal is set high when the CompactFlash Storage Card is
(PC Card Memory Mode)				ready to accept a new data transfer operation and is held low when the card is
				busy.
				At power up and at Reset, the READY signal is held low (busy) until the
				CompactFlash Storage Card has completed its power up or reset function. No
				access of any type should be made to the CompactFlash Storage Card during
				this time.
				Note, however, that when a card is powered up and used with RESET
				continuously disconnected or asserted, the Reset function of the RESET pin is
				disabled. Consequently, the continuous assertion of RESET from the application
				of power shall not cause the READY signal to remain continuously in the busy
				state.
-IREQ				I/O Operation – After the CompactFlash Storage Card Card has been configured
(PC Card I/O Mode)				for I/O operation, this signal is used as -Interrupt Request. This line is strobed
				low to generate a pulse mode interrupt or held low for a level mode interrupt.
INTRQ				In True IDE Mode signal is the active high Interrupt Request to the host.
(True IDE Mode)

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TS8G~32GCF600				600X CompactFlash Card
	Signal Name	Dir.	Pin	Description
-REG		I	44	This signal is used during Memory Cycles to distinguish between Common
				Memory and Register (Attribute) Memory accesses. High for Common Memory,
(PC Card Memory Mode– Except				Low for Attribute Memory.
Ultra DMA Protocol Active)
Attribute Memory Select				In PC Card Memory Mode, when Ultra DMA Protocol is supported by the host
				and the host has enabled Ultra DMA protocol on the card the, host shall keep the
				-REG signal negated during the execution of any DMA Command by the device.
-REG				The signal shall also be active (low) during I/O Cycles when the I/O address is on
(PC Card I/O Mode –Except Ultra				the Bus.
DMA Protocol Active)				In PC Card I/O Mode, when Ultra DMA Protocol is supported by the host and the
				host has enabled Ultra DMA protocol on the card the, host shall keep the -REG
				signal asserted during the execution of any DMA Command by the device.
-DMACK				This is a DMA Acknowledge signal that is asserted by the host in response to
(PC Card Memory Mode when				(-)DMARQ to initiate DMA transfers.
Ultra DMA Protocol Active)				In True IDE Mode, while DMA operations are not active, the card shall ignore the
DMACK
				(-)DMACK signal, including a floating condition.
(PC Card I/O Mode when Ultra				If DMA operation is not supported by a True IDE Mode only host, this signal
DMA Protocol Active)
-DMACK				should be driven high or connected to VCC by the host.
(True IDE Mode)				A host that does not support DMA mode and implements both PC Card and
				True-IDE modes of operation need not alter the PC Card mode connections
				while in True-IDE mode as long as this does not prevent proper operation all
				modes.
RESET		I	41	The CompactFlash Storage Card is Reset when the RESET pin is high with the
(PC Card Memory Mode)				following important exception:
				The host may leave the RESET pin open or keep it continually high from the
				application of power without causing a continuous Reset of the card. Under
				either of these conditions, the card shall emerge from power-up having
				completed an initial Reset.
				The CompactFlash Storage Card is also Reset when the Soft Reset bit in the
				Card Configuration Option Register is set.
RESET				This signal is the same as the PC Card Memory Mode signal.
(PC Card I/O Mode)
-RESET				In the True IDE Mode, this input pin is the active low hardware reset from the
(True IDE Mode)				host.
VCC		--	13,38	+5 V, +3.3 V power.
(PC Card Memory Mode)
VCC				This signal is the same for all modes.
(PC Card I/O Mode)
VCC				This signal is the same for all modes.
(True IDE Mode)
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				V1.5

	TS8G~32GCF600				600X CompactFlash Card
		Signal Name	Dir.	Pin	Description
	-VS1		O	33	Voltage Sense Signals. -VS1 is grounded on the Card and sensed by the Host so
	-VS2				that the CompactFlash Storage Card CIS can be read at 3.3 volts and -VS2 is
				40
	(PC Card Memory Mode)				reserved by PCMCIA for a secondary voltage and is not connected on the Card.
	-VS1				This signal is the same for all modes.
	-VS2
	(PC Card I/O Mode)
	-VS1				This signal is the same for all modes.
	-VS2
	(True IDE Mode)
	-WAIT		O	42	The -WAIT signal is driven low by the CompactFlash Storage Card to signal the
	(PC Card Memory Mode – Except				host to delay completion of a memory or I/O cycle that is in progress.
	Ultra DMA Protocol Active)
	-WAIT				This signal is the same as the PC Card Memory Mode signal.
	(PC Card I/O Mode –Except Ultra
	DMA Protocol Active)
	IORDY				In True IDE Mode, except in Ultra DMA modes, this output signal may be used as
	(True IDE Mode – Except Ultra				IORDY.
	DMA Protocol Active)
	-DDMARDY				In all modes, when Ultra DMA mode DMA Write is active, this signal is asserted
					by the device during a data burst to indicate that the device is ready to receive
	(All Modes – Ultra DMA Write
	Protocol Active)				Ultra DMA data out bursts. The device may negate -DDMARDY to pause an
					Ultra DMA transfer.
	DSTROBE				In all modes, when Ultra DMA mode DMA Read is active, this signal is the data in
	(All Modes – Ultra DMA Read				strobe generated by the device. Both the rising and falling edge of DSTROBE
	Protocol Active)				cause data to be latched by the host. The device may stop generating
					DSTROBE edges to pause an Ultra DMA data in burst.
	-WE		I	36	This is a signal driven by the host and used for strobing memory write data to the
	(PC Card Memory Mode)				registers of the CompactFlash Storage Card when the card is configured in the
					memory interface mode. It is also used for writing the configuration registers.
	-WE				In PC Card I/O Mode, this signal is used for writing the configuration registers.
	(PC Card I/O Mode)
	-WE				In True IDE Mode, this input signal is not used and should be connected to VCC
	(True IDE Mode)				by the host.
	WP		O	24	Memory Mode – The CompactFlash Storage Card does not have a write protect
	(PC Card Memory Mode)				switch. This signal is held low after the completion of the reset initialization
	Write Protect				sequence.
	-IOIS16				I/O Operation – When the CompactFlash Storage Card is configured for I/O
	(PC Card I/O Mode)				Operation Pin 24 is used for the -I/O Selected is 16 Bit Port (-IOIS16) function. A
					Low signal indicates that a 16 bit or odd byte only operation can be performed at
					the addressed port.
	-IOCS16				In True IDE Mode this output signal is asserted low when this device is expecting
	(True IDE Mode)				a word data transfer cycle.

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TS8G~32GCF600		600X CompactFlash Card

Electrical Specification

The following tables indicate all D.C. Characteristics for the CompactFlash Storage Card. Unless otherwise stated, conditions are:

Vcc = 5V ±10%

Vcc = 3.3V ± 5%

Absolute Maximum Conditions

DC Characteristics CompactFlash Interface I/O at 5.0V

Parameter	Symbol	Min.	Max.	Unit	Remark
Supply Voltage	VCC	4.5	5.5	V
High level output voltage	VOH	VCC ─ 0.8		V
Low level output voltage	VOL		0.8	V
High level input voltage	VIH	4.0		V	Non-schmitt trigger
		2.92		V	Schmitt trigger1
Low level input voltage	VIL		0.8	V	Non-schmitt trigger
			1.70	V	Schmitt trigger1
Pull up resistance2	RPU	50	73	KOhm
Pull down resistance	RPD	50	97	KOhm

CompactFlash Interface I/O at 3.3V

Parameter	Symbol	Min.	Max.	Unit	Remark
Supply Voltage	VCC	3.135	3.465	V
High level output voltage	VOH	VCC ─ 0.8		V
Low level output voltage	VOL		0.8	V
High level input voltage	VIH	2.4		V	Non-schmitt trigger
		2.05		V	Schmitt trigger1
Low level input voltage	VIL		0.6	V	Non-schmitt trigger
			1.25	V	Schmitt trigger1
Pull up resistance2	RPU	52.7	141	KOhm
Pull down resistance	RPD	47.5	172	KOhm

1.Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW pins

2.Include CE1, CE2, HREG, HOE, HIOE, HWE, HIOW, CSEL (P35), PDIAG, DASP pins

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TS8G~32GCF600		600X CompactFlash Card

Input Power

Input Characteristics for UDMA mode >4

In UDMA modes greater than 4, the following characteristics apply. Voltage output high and low values shall be met at the source connector to include the effect of series termination.

Table: Input Characteristics (UDMA Mode > 4)

	Parameter	Symbol	MIN	MAX	Units
	DC supply voltage to drivers	VDD3	3.3 –8%	3.3% + 8%	Volts
	Low to high input threshold	V+	1.5	2.0	Volts
	High to low input threshold	V-	1.0	1.5	Volts
	Difference between input thresholds:	VHYS	320		Volts
	((V+ current value) - (V-current value))
	Average of thresholds:	VTHRAVG	1.3	1.7	Volts
	((V+ current value) + (V-current value))/2

Output Drive Characteristics for UDMA mode > 4

In UDMA modes greater than 4, the characteristics specified in the following table apply. Voltage output high and low values shall be met at the source connector to include the effect of series termination.

Table: Output Drive Characteristics (UDMA Mode > 4)

	Parameter	Symbol	MIN	MAX	Units
	DC supply voltage to drivers	VDD3	3.3 –8%	3.3% + 8%	Volts
	Voltage output high at -6 mA to +3 mA (at VoH2 the output shall be	VoH2	VDD3–0.51	VDD3+0.3	Volts
	able to supply and sink current toVDD3)
	Voltage output low at 6 mA	VoL2		0.51	Volts

Notes:

1)IoLDASP shall be 12 mA minimum to meet legacy timing and signal integrity.

2)IoH value at 400 μ A is insufficient in the case of DMARQ that is pulled low by a 5.6 kΩ resistor.

3)Voltage output high and low values shall be met at the source connector to include the effect of series termination.

4)A device shall have less than 64 μ A of leakage current into a 6.2 KΩ pull-down resistor while the INTRQ signal is in the released state.

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TS8G~32GCF600		600X CompactFlash Card

Signal Interface

Electrical specifications shall be maintained to ensure data reliability. Additional requirements are necessary for Advanced Timing Modes and Ultra DMA modes operations. See next sections for additional information.

Item	Signal	Card10	Host10
	-CE1	Pull-up to VCC 500 KΩ R 50 KΩ and
	-CE2
		shall be sufficient to keep inputs inactive
Control Signal	-REG
	-HIOE	when the pins are not connected at the
	-IOWR	host.1
	-OE	Pull-up to VCC 500 KΩ R 50 KΩ .1,2
	-WE
	RESET	Pull-up to VCC 500 KΩ R 50 KΩ .1,2,9,
	READY		Pull-up to VCC R 10 KΩ .3
Status Signal	-WAIT
	WP
			In PCMCIA PC Card modes Pull-up to VCC
			R 10 KΩ .4
			In True IDE mode, if DMA operation is
			supported by the host, Pull-down to Gnd R
	-INPACK		5.6 KΩ .5
			PC Card / True IDE hosts switch the pull-up
			to pull down in True IDE mode if DMA
			operation is supported.
			The PC Card mode Pull-up may be left
			active during True IDE mode if True IDE
			DMA operation is not supported.
Address	A[10:00]
	-CSEL
Data Bus	D[15:00]		1.
Card Detect	-CD[2:1]	Connected to GND in the card
Voltage Sense	-VS1		Pull-up to Vcc 10 KΩ R 100KΩ .
	-VS2
Battery/Detect	BVD[2:1]		Pull-up R 50 KΩ .3.6

Notes: 1) Control Signals: each card shall present a load to the socket no larger than 50 pF 10 at a DC current of 700 μ A low

state and 150 μ A high state, including pull-resistor. The socket shall be able to drive at least the following load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (50 pF with DC current 700 μ A low state and 150 μ A high state per socket).

2)Resistor is optional.

3)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μ A low

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V1.5

TS8G~32GCF600		600X CompactFlash Card

state and 100 μ A high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μ A low state and 100 μ A high state.

4)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μ A low state and 100 μ A high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μ A low state and 100 μ A high state.

5)Status Signals: the socket shall present a load to the card no larger than 50 pF 10 at a DC current of 400 μ A low

state and 100 μ A high state, including pull-up resistor. The card shall be able to drive at least the following load 10 while meeting all AC timing requirements: 50 pF at a DC current of 400 μ A low state and 1100 μ A high state.

6)BVD2 was not defined in the JEIDA 3.0 release. Systems fully supporting JEIDA release 3 SRAM cards shall pull-up pin 45 (BVD2) to avoid sensing their batteries as “Low.”

7)Address Signals: each card shall present a load of no more than 100pF 10 at a DC current of 450μ A low state and

150μ A high state. The host shall be able to drive at least the following load 10 while meeting all AC timing requirements: (the number of sockets wired in parallel) multiplied by (100pF with DC current 450μ A low state and 150μ A high state per socket).

8)Data Signals: the host and each card shall present a load no larger than 50pF 10 at a DC current of 450μ A and 150μ A high state. The host and each card shall be able to drive at least the following load 10 while meeting all AC

timing requirements: 100pF with DC current 1.6mA low state and 300μ A high state. This permits the host to wire two sockets in parallel without derating the card access speeds.

9)Reset Signal: This signal is pulled up to prevent the input from floating when a CFA to PCMCIA adapter is used in a PCMCIA revision 1 host. However, to minimize DC current drain through the pull-up resistor in normal operation the pull-up should be turned off once the Reset signal has been actively driven low by the host. Consequently, the input is specified as an I2Z because the resistor is not necessarily detectable in the input current leakage test.

10)Host and card restrictions for CF Advanced Timing Modes and Ultra DMA modes: Additional Requirements for CF Advanced Timing Modes and Ultra DMA Electrical Requirements for additional required limitations on the implementation of CF Advanced Timing modes and Ultra DMA modes respectively.

Additional Requirements for CF Advanced Timing Modes

The CF Advanced Timing modes include PC Card I/O and Memory modes that are 100ns or faster, PC Card Ultra DMA modes 3 or above and True IDE PIO Modes 5,6, Multiword DMA Modes 3,4 and True IDE Ultra DMA modes 3 or above.

When operating in CF Advanced timing modes, the host shall conform to the following requirements:

1)Only one CF device shall be attached to the CF Bus.

2)The host shall not present a load of more than 40pF to the device for all signals, including any cabling.

3)The maximum cable length is 0.15 m (6 in). The cable length is measured from the card connector to the host controller. 0.46 m (18 in) cables are not supported.

4)The -WAIT and IORDY signals shall be ignored by the host.

Devices supporting CF Advanced timing modes shall also support slower timing modes, to ensure operability with systems that do not support CF Advanced timing modes

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V1.5

TS8G~32GCF600

600X CompactFlash Card

Ultra DMA Electrical Requirements

¾Host and Card signal capacitance limits for Ultra DMA operation

The host interface signal capacitance at the host connector shall be a maximum of 25 pF for each signal as measured at

1MHz.

The card interface signal capacitance at the card connector shall be a maximum of 20 pF for each signal as measured at

1MHz.

¾Series termination required for Ultra DMA operation

Series termination resistors are required at both the host and the card for operation in any of the Ultra DMA modes. Table describes typical values for series termination at the host and the device.

Table: Typical Series Termination for Ultra DMA

Signal	Host Termination	Device Termination
-HIOE (-HDMARDY,HSTROBE)	22 ohm	82 ohm
-IOWR (STOP)	22 ohm	82 ohm
-CS0, -CS1	33 ohm	82 ohm
A00, A01, A02	33 ohm	82 ohm
-DMACK	22 ohm	82 ohm
D15 through D00	33 ohm	33 ohm
DMARQ	82 ohm	22 ohm
INTRQ	82 ohm	22 ohm
IORDY (-DDMARDY, DSTROBE)	82 ohm	22 ohm
-RESET	33 ohm	82 ohm

NOTE − Only those signals requiring termination are listed in this table. If a signal is not listed, series termination is not required for operation in an Ultra DMA mode. Shows signals also requiring a pull-up or pull-down resistor at the host. The actual termination values should be selected to compensate for transceiver and trace impedance to match the characteristic cable impedance.

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TS8G~32GCF600		600X CompactFlash Card

Table: Ultra DMA Termination with Pull-up or Pull down Example

¾ Printed Circuit Board (PCB) Trace Requirements for Ultra DMA

On any PCB for a host or device supporting Ultra DMA:

9The longest D[15:00] trace shall be no more than 0.5" longer than either STROBE trace as measured from the IC pin to the connector.

9The shortest D[15:00] trace shall be no more than 0.5" shorter than either STROBE trace as measured from the IC pin to the connector.

¾Ultra DMA Mode Cabling Requirement

9Operation in Ultra DMA mode requires a crosstalk suppressing cable. The cable shall have a grounded line between each signal line.

9For True IDE mode operation using a cable with IDE (ATA) type 40 pin connectors it is recommended that the host sense the cable type using the method described in the ANSI INCITS 361-2002 AT Attachment - 6 standard, to prevent use of Ultra DMA with a 40 conductor cable.

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TS8G~32GCF600		600X CompactFlash Card

Attribute Memory Read Timing Specification

Attribute Memory access time is defined as 300 ns. Detailed timing specs are shown in Table below

Speed Version				300 ns
Item	Symbol	IEEE Symbol	Min ns.		Max ns.
Read Cycle Time	tc(R)	tAVAV	300
Address Access Time	ta(A)	tAVQV			300
Card Enable Access Time	ta(CE)	tELQV			300
Output Enable Access Time	ta(OE)	tGLQV			150
Output Disable Time from CE	tdis(CE)	tEHQZ			100
Output Disable Time from OE	tdis(OE)	tGHQZ			100
Address Setup Time	tsu (A)	tAVGL	30
Output Enable Time from CE	ten(CE)	tELQNZ	5
Output Enable Time from OE	ten(OE)	tGLQNZ	5
Data Valid from Address Change	tv(A)	tAXQX	0

Note: All times are in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -CE signal or both the -OE signal and the -WE signal shall be de-asserted between consecutive cycle operations.

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TS8G~32GCF600		600X CompactFlash Card

Configuration Register (Attribute Memory) Write Timing Specification

The Card Configuration write access time is defined as 250 ns. Detailed timing specifications are shown in Table below.

Table: Configuration Register (Attribute Memory) Write Timing

Speed Version			250 ns
Item	Symbol	Min ns		Max ns
Write Cycle Time	tc(W)	250
Write Pulse Width	tw(HWE)	150
Address Setup Time	tsu(HA)	30
Write Recovery Time	trec(HWE)	30
Data Setup Time for WE	tsu(HD-HWEH)	80
Data Hold Time	th(HD)	30

Note: All times are in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card .

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TS8G~32GCF600		600X CompactFlash Card

Common Memory Read Timing Specification

		Cycle Time Mode:		250 ns		120 ns		100 ns		80 ns
	Item	Symbol	IEEE	Min	Max	Min	Max	Min	Max	Min	Max
			Symbol	ns.	ns.	ns.	ns.	ns.	ns.	ns.	ns.
	Output Enable Access Time	ta(HOE)	tGLQV		125		60		50		45
	Output Disable Time from HOE	tdis(HOE)	tGHQZ		100		60		50		45
	Address Setup Time	tsu(HA)	tAVGL	30		15		10		10
	Address Hold Time	th(HA)	tGHAX	20		15		15		10
	CEx Setup before HOE	tsu(CEx)	tELGL	5		5		5		5
	CEx Hold following HOE	th(CEx)	tGHEH	20		15		15		10
	Wait Delay Falling from HOE	tv(IORDY-HOE)	tGLWTV		35		35		35		na1
	Data Setup for Wait Release	tv(IORDY)	tQVWTH		0		0		0		na1
	Wait Width Time2	tw(IORDY)	tWTLWTH		350		350		350		na1

Notes:1) –WAIT is not supported in this mode.

2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Dout signifies data provided by the CompactFlash Storage Card to the system. The -WAIT signal may be ignored if the -OE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12µs but is intentionally less in this specification.

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TS8G~32GCF600		600X CompactFlash Card

Common Memory Write Timing Specification

	Cycle Time Mode:		250 ns			120 ns		100 ns		80 ns
Item	Symbol	IEEE	Min		Max	Min	Max	Min	Max	Min	Max
		Symbol	ns.		ns.	ns.	ns.	ns.	ns.	ns.	ns.
Data Setup before HWE	tsu (HD-HWEH)	tDVWH	80			50		40		30
Data Hold following HWE	th(HD)	tWMDX	30			15		10		10
HWE Pulse Width	tw(HWE)	tWLWH	150			70		60		55
Address Setup Time	tsu(HA)	tAVWL	30			15		10		10
CEx Setup before HWE	tsu(CEx)	tELWL	5			5		5		5
Write Recovery Time	trec(HWE)	tWMAX	30			15		15		15
Address Hold Time	th(HA)	tGHAX	20			15		15		15
CEx Hold following HWE	th(CEx)	tGHEH	20			15		15		10
Wait Delay Falling from HWE	tv (IORDY-HWE)	tWLWTV			35		35		35		na1
WE High from Wait Release	tv(IORDY)	tWTHWH	0			0		0		na1
Wait Width Time2	tw (IORDY)	tWTLWTH			350		350		350		na1

Notes: 1) –WAIT is not supported in this mode.

2) The maximum load on -WAIT is 1 LSTTL with 50 pF (40pF below 120nsec Cycle Time) total load. All times are in nanoseconds. Din signifies data provided by the system to the CompactFlash Storage Card. The -WAIT signal may be ignored if the -HWE cycle to cycle time is greater than the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA PC Card specification of 12μs but is intentionally less in this specification.

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V1.5

TS8G~32GCF600

600X CompactFlash Card

I/O Input (Read) Timing Specification

	Cycle Time Mode:		250 ns			120 ns		100 ns		80 ns
Item	Symbol	IEEE	Min		Max	Min	Max	Min	Max	Min	Max
		Symbol	ns.		ns.	ns.	ns.	ns.	ns.	ns.	ns.
Data Delay after HIOE	td(HIOE)	tlGLQV			100		50		50		45
Data Hold following HIOE	th(HIOE)	tlGHQX	0			5		5		5
HIOE Width Time	tw(HIOE)	tlGLIGH	165			70		65		55
Address Setup before HIOE	tsuA(HIOE)	tAVIGL	70			25		25		15
Address Hold following HIOE	thA(HIOE)	tlGHAX	20			10		10		10
CEx Setup before HIOE	tsuCE(HIOE)	tELIGL	5			5		5		5
CEx Hold following HIOE	thCE(HIOE)	tlGHEH	20			10		10		10
HREG Setup before HIOE	tsuREG (HIOE)	tRGLIGL	5			5		5		5
HREG Hold following HIOE	thREG (HIOE)	tlGHRGH	0			0		0		0
Wait Delay Falling from HIOE2	tdWT(HIOE)	tlGLWTL			35		35		35		Na1
Data Delay from Wait Rising2	td(IORDY)	tWTHQV			0		0		0		Na1
Wait Width Time2	tw(IORDY)	tWTLWTH			350		350		350		Na1

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TS8G~32GCF600		600X CompactFlash Card

I/O Output (Write) Timing Specification

		Cycle Time Mode:		255 ns		120 ns		100 ns		80 ns
	Item	Symbol	IEEE	Min	Max	Min	Max	Min	Max	Min	Max
			Symbol	ns.	ns.	ns.	ns.	ns.	ns.	ns.	ns.
	Data Setup before HIOW	tsu(HIOW)	tDVIWH	60		20		20		15
	Data Hold following HIOW	th(HIOW)	tlWHDX	30		10		5		5
	HIOW Width Time	tw(HIOW)	tlWLIWH	165		70		65		55
	Address Setup before HIOW	tsuA(HIOW)	tAVIWL	70		25		25		15
	Address Hold following HIOW	thA(HIOW)	tlWHAX	20		20		10		10
	CEx Setup before HIOW	tsuCE (HIOW)	tELIWL	5		5		5		5
	CEx Hold following HIOW	thCE (HIOW)	tlWHEH	20		20		10		10
	HREG Setup before HIOW	tsuREG (HIOW)	tRGLIWL	5		5		5		5
	HREG Hold following HIOW	thREG (HIOW)	tlWHRGH	0		0		0		0
	Wait Delay Falling from HIOW2	tdWT(HIOW)	tlWLWTL		35		35		35		Na1
	HIOW high from Wait high2	tdrHIOW (IORDY)	tWTJIWH	0		0		0		Na1
	Wait Width Time2	tw(IORDY)	tWTLWTH		350		350		350		Na1

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