Siemens SAB-C540U-EN, SAB-C540U-EP, SAB-C541U-1EN, SAB-C541U-1EP Datasheet

Microcomputer Components

8-Bit CMOS Microcontroller

C540U / C541U

Data Sheet 10.97

C540U/C541U Data Sheet Revision History : 1997-10-01

Previous Releases : none (Original Version) Page / Chapters Subjects (changes since last revision)

Edition 1997-10-01 Published by Siemens AG,

Bereich Halbleiter, MarketingKommunikation, Balanstraße 73, 81541 München

Siemens AG 1997.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group. Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

with the express

8-Bit CMOS Microcontroller

Advance Information

C540U C541U

Enhanced 8-bit C500 CPU

•

– Full software/toolset compatible to standard 80C51/80C52 microcontrollers 12 MHz external operating frequency

•

– 500 ns instruction cycle Built-in PLL for USB synchronization

•

On-chip OTP program memory

•

– C540U : 4K byte – C541U : 8K byte – Alternatively up to 64K byte external program memory – Optional memory protection On-chip USB module

•

– Compliant to USB specification – Full speed or low speed operation – Five endpoints : one bidirectional control endpoint

four versatile programmable endpoints – Registers are located in special function register area – On-chip USB transceiver

Oscillator

Watchdog

Power

Saving Modes

On-Chip Emulation Support Module

The shaded units are not available in the C540U.

Semiconductor Group 3 1997-10-01

Watchdog

Timer

SSC T0

USB

Module

USB Transceiver

D+ D-

RAM

256 x 8

CPU

OTP Prog. Memory

C540U : 4 k x 8 C541U : 8 k x 8

Port 0

Port 1

Port 2

Port 3

I/O

MCA03373

Features (cont’d) :

•

Up to 64K byte external data memory

•

256 byte on-chip RAM

•

Four parallel I/O ports – P-LCC-44 package : three 8-bit ports and one 6-bit port – P-SDIP-52 package : four 8-bit ports – LED current drive capability for 3 pins (10 mA)

•

Two 16-bit timer/counters (C501 compatible)

•

SSC synchronous serial interface (SPI compatible) (only C541U) – Master and slave capable – Programmable clock polarity / clock-edge to data phase relation – LSB/MSB first selectable – 1.5 MBaud transfer rate at 12 MHz operating frequency

•

7 interrupt sources (2 external, 5 internal with 2 USB interrupts) selectable at 2 priority levels

•

Enhanced fail safe mechanisms – Programmable watchdog timer (only C541U) – Oscillator watchdog

•

Power saving modes – idle mode

)

pin or USB

– software power down mode with wake-up capability through INT0

•

On-chip emulation support logic (Enhanced Hooks Technology

•

P-LCC-44 and P-SDIP-52 packages

•

Power supply voltage range : 4.0V to 5.5V

•

Temperature Range : SAB-C540U

SAB-C541U

= 0 to 70 ° C

C540U C541U

Table 1 Ordering Information

Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

SAB-C540U-EN Q67126-C2042 P-LCC-44-2 8-Bit CMOS microcontroller (12 MHz) SAB-C540U-EP Q67120-C2043 P-SDIP-52-1 8-Bit CMOS microcontroller (12 MHz) SAB-C541U-1EN Q67126-C2001 P-LCC-44-2 8-Bit CMOS microcontroller (12 MHz) SAB-C541U-1EP Q67120-C2021 P-SDIP-52-1 8-Bit CMOS microcontroller (12 MHz)

Semiconductor Group 4 1997-10-01

C540U C541U

Figure 2 Logic Symbol

XTAL2 XTAL1

ALE PSEN EA RESET

D+ D-

C540U C541U

Port

8-Bit Digital I / O Port

1 P-LCC-44 : 6-Bit Digital I / O P-SDIP-52 : 8-Bit Digital I / O

Port

2 8-Bit Digital I / O

Port

3 8-Bit Digital I / O

MCL03374

Additional Literature

For further information about the C540U/C541U the following literature is available :

Title Ordering Number

C540U/C541U 8-Bit CMOS Microcontroller User’s Manual B158-H????-X-X-7600 C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

Semiconductor Group 5 1997-10-01

C540U C541U

P1.1 / LED1

P1.0 / LED0

D-

6543214443424140

P1.2 / SCLK 7

RESET

P3.0 / LED2

P1.3 / SRI

P3.1 / DADD

P3.2 / INT0 P3.3 / INT1

P3.4 / T0 P3.5 / T1

This pin functionality ist not available for the C540U.

10 11 12 13 14 15 16 17

18 19 20 21 22 23 24 25 26 27 28

XTAL2

P3.7 / RD

P3.6 / WR

SSUVCCU

D+

C540U C541U

XTAL1

P1.5 / SLS

P0.0 / AD0

P2.0 / A8

P2.1 / A9

P0.1 / AD1

P0.2 / AD2

P0.3 / AD3

39 38 37 36 35 34 33 32 31 30 29

P2.2 / A10

P2.3 / A11

P2.4 / A12

P0.4 / AD4 P0.5 / AD5 P0.6 / AD6 P0.7 / AD7 EA P1.4 / STO ALE PSEN P2.7 / A15 P2.6 / A14 P2.5 / A13

MCP03343

Figure 3 Pin Configuration P-LCC-44 Package (top view)

Semiconductor Group 6 1997-10-01

C540U C541U

CCU

SSU

D+

DN.C. N.C.

P1.0 / LED0 P1.1 / LED1

P1.2 / SCLK

RESET

P3.0 / LED2

P1.3 / SRI

P1.6

P3.1 / DADD

P3.2 / INT0 P3.3 / INT1

P3.4 / T0 P3.5 / T1

P3.6 / WR

P3.7 / RD

XTAL2 XTAL1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

C540U C541U

N.C.

P1.5 / SLS

P0.0 / AD0

P0.1 / AD1

P0.2 / AD2

P0.3 / AD3

P0.4 / AD4

P0.5 / AD5

P0.6 / AD6

P0.7 / AD7

P1.4 / STO

P1.7

ALE

PSEN

N.C.

P2.7 / A15

P2.6 / A14

P2.5 / A13

P2.4 / A12

P2.3 / A11

P2.2 / A10

P2.1 / A9

P2.0 / A8

N.C.

MCP03344

This pin functionality ist not available for the C540U.

Figure 4 Pin Configuration P-SDIP-52 Package (top view)

Semiconductor Group 7 1997-10-01

Table 2 Pin Deﬁnitions and Functions

Symbol Pin Numbers I/O*) Function

P-LCC-44 P-SDIP-52

D+ 3 3 I/O USB D+ Data Line

The pin D+ can be directly connected to USB cable (transceiver is integrated on-chip).

D- 4 4 I/O USB D- Data Line

The pin D- can be directly connected to USB cable (transceiver is integrated on-chip).

C540U C541U

P1.0 - P1.4 5 - 7,

12, 34, 44

5 6 7

12 34 44 – –

7 - 9, 14, 41, 51, 15, 40

7 8 9

13 41 51 15 40

I/O Port 1

is an 6-bit (P-LCC-44) or 8-bit (P-SDIP-52) quasibidirectional I/O port with internal pullup resistors. Port 1 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 1 pins being externally pulled low will source current ( I in the DC characteristics) because of the internal pullup resistors. Port 1 also contains two outputs with LED drive capability as well as the four pins of the SSC (C541U only). The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate (except when used for the compare functions). The secondary functions are assigned to the port 1 pins as follows : P1.0 / LED0 LED0 output P1.1 / LED1 LED1 output P1.2 / SCLK SSC Master Clock Output /

P1.3 / SRI SSC Receive Input (C541U only) P1.4 / STO SSC Transmit Output (C541U only) P1.5 / SLS P1.6 (P-SDIP-52 only) P1.7 (P-SDIP-52 only)

SSC Slave Clock Input (C541U only)

SSC Slave Select Inp. (C541U only)

RESET 10 12 I

RESET

A high level on this pin for the duration of two machine cycles while the oscillator is running resets the C540U/C541U. A small internal pulldown resistor permits power-on reset using only a capacitor connected to V

*) I = Input

O = Output

Semiconductor Group 8 1997-10-01

Table 2 Pin Deﬁnitions and Functions (cont’d)

Symbol Pin Numbers I/O*) Function

P-LCC-44 P-SDIP-52

P3.0 - P3.7 11, 13 - 19 13, 16 - 22 I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 3 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 3 pins being externally pulled low will source current ( I the internal pullup resistors. Port 3 also contains the interrupt, timer, serial port and external memory strobe pins that are used by various options. The output latch corresponding to a secondary function must be programmed to a one (1) for that function to operate. The secondary functions are assigned to the pins of port 3, as follows: P3.0 / LED2 LED2 output P3.1 / DADD Device attached input P3.2 / INT0

P3.3 / INT1 External interrupt 1 input /

P3.4 / T0 Timer 0 counter input P3.5 / T1 Timer 1 counter input P3.6 / WR WR control output; latches the

P3.7 / RD

C540U C541U

, in the DC characteristics) because of

External interrupt 0 input / timer 0 gate control input

timer 1 gate control input

data byte from port 0 into the external data memory RD control output; enables the external data memory

XTAL2 20 23 –

XTAL1 21 24 –

*) I = Input

O = Output

Semiconductor Group 9 1997-10-01

XTAL2

is the output of the inverting oscillator amplifier. This pin is used for the oscillator operation with crystal or ceramic resonator.

XTAL1

is the input to the inverting oscillator amplifier and input to the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. low times as well as rise/fall times specified in the AC characteristics must be observed.

Minimum and maximum high and

Table 2 Pin Deﬁnitions and Functions (cont’d)

Symbol Pin Numbers I/O*) Function

P-LCC-44 P-SDIP-52

P2.0 - P2.7 24 - 31 28 - 35 I/O Port 2

is an 8-bit quasi-bidirectional I/O port with internal pullup resistors. Port 2 pins that have 1's written to them are pulled high by the internal pullup resistors, and in that state can be used as inputs. As inputs, port 2 pins being externally pulled low will source current ( I the internal pullup resistors. Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application it uses strong internal pullup resistors when issuing 1's. During accesses to external data memory that use 8-bit addresses (MOVX @Ri), port 2 issues the contents of the P2 special function register.

C540U C541U

, in the DC characteristics) because of

PSEN

32 38 O The Program Store Enable

output is a control signal that enables the external program memory to the bus during external fetch operations. It is activated every six oscillator periods except during external data memory accesses. The signal remains high during internal program execution.

ALE 33 39 O The Address Latch enable

output is used for latching the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access.

35 42 I

External Access Enable

When held high, the C540U/C541U executes instructions from the internal ROM as long as the PC is less than 1000H for the C540U or less than 2000H for the C541U. When held low, the C540U/ C541U fetches all instructions from external program memory. For the C540U-L/C541U-L this pin must be tied low.

*) I = Input

O = Output

Semiconductor Group 10 1997-10-01

Table 2 Pin Deﬁnitions and Functions (cont’d)

Symbol Pin Numbers I/O*) Function

P-LCC-44 P-SDIP-52

P0.0 - P0.7 44 - 36 50 - 43 I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1's written to them float, and in that state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application it uses strong internal pullup resistors when issuing 1's.

C540U C541U

CCU

SSU

*) I = Input

O = Output

11 –

Supply voltage

for the on-chip USB transceiver circuitry.

22 –

Ground (0V)

for the on-chip USB transceiver circuitry.

8, 23 10, 26 –

Supply voltage

for ports and internal logic circuitry during normal, idle, and power down mode.

9, 22 11, 25 –

Ground (0V)

for ports and internal logic circuitry during normal, idle, and power down mode.

Semiconductor Group 11 1997-10-01

C540U C541U

XTAL2 XTAL1

ALE

PSEN

RESET

D+

Oscillator Watchdog

OSC & Timing

CPU

Progr. Watchdog

Timer (C541U only)

Timer 0

Timer 1

SSC (SPI) Interface

(C541U only)

PLL

USB

Module

Transceiver

Interrupt Unit

RAM

256 x 8

OTP Memory

4k x 8 (C540U) 8k x 8 (C541U)

Emulation

Support

Logic

Port 0

Port 1

Port 2

Port 3

C540U C541U

Port 0 8-Bit Digit. I/O

Port 1 6- / 8-Bit Digit. I/O

Port 2 8-Bit Digit. I/O

Port 3 8-Bit Digit. I/O

P-LCC-44 : 6-Bit Port; P-SDIP-52 : 8-Bit Port MCB03345

Figure 5 Block Diagram of the C540U/C541U

Semiconductor Group 12 1997-10-01

C540U C541U

CPU

The C540U/C541U is efficient both as a controller and as an arithmetic processor. It has extensive facilities for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15% three- byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 500ns.

Special Function Register PSW (Address D0H) Reset Value : 00H

Bit No. MSB LSB

CY AC

RS1 RS0 OV F1 PD0

Bit Function

CY Carry Flag

Used by arithmetic instruction.

AC Auxiliary Carry Flag

Used by instructions which execute BCD operations. F0 General Purpose Flag RS1

RS0

These bits are used to select one of the four register banks.

RS1 RS0 Function

0 0 Bank 0 selected, data address 00H-07 0 1 Bank 1 selected, data address 08H-0F 1 0 Bank 2 selected, data address 10H-17 1 1 Bank 3 selected, data address 18H-1F

PSW

H H H H

OV Overflow Flag

Used by arithmetic instruction. F1 General Purpose Flag P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of "one" bits in the accumulator, i.e. even parity.

Semiconductor Group 13 1997-10-01

Memory Organization

The C540U/C541U CPU manipulates operands in the following four address spaces:

– 8 or 4 KByte on-chip OTP program memory – Totally up to 64 Kbyte internal/external program memory – up to 64 Kbyte of external data memory – 256 bytes of internal data memory – a 128 byte special function register area

Figure 6 illustrates the memory address spaces of the C540U/C541U.

C540U C541U

Internal

(EA = 1)

External

FFFF

2000 1)

External (EA = 0)

1FFF 1)

FFFF

Direct

Addr.

Special

Function

External

Indirect

Addr.

Internal

RAM

Internal

RAM

0000

"Code Space" "External Data Space" "Internal Data Space"

1) For the C504U the int. / ext. program memory boundary is at 0FFF / 1000 .

MCD03375

Figure 6 C540U/C541U Memory Map Memory Map

Semiconductor Group 14 1997-10-01

C540U C541U

Reset and System Clock

The reset input is an active high input at pin RESET. Since the reset is synchronized internally, the RESET pin must be held high for at least two machine cycles (12 oscillator periods) while the oscillator is running. A pulldown resistor is internally connected to VSS to allow a power-up reset with an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting the RESET pin to VCC via a capacitor. Figure 7 shows the possible reset circuitries.

C540U C541U C541U

RESET RESET

C540U C541U

RESET

C540U

MCD03376

Figure 7 Reset Circuitries

Semiconductor Group 15 1997-10-01

C540U C541U

The oscillator and clock generation circuitry of the C540U/C541U is shown in figure 5-8. The crystal oscillator generates the system clock for the microcontroller. The USB module can be provided with the following clocks :

– Full speed operation : 48 MHz with a data rate of 12 Mbit/s – Low speed operation : 6 MHz with a data rate of 1.5 Mbit/s

The low speed clock is generated by a dividing the system clock by 2. The full speed clock is generated by a PLL, which multiplies the system clock by a fix factor of 4. This PLL can be enabled or disabled by bit PCLK of SFR DCR. Depending on full or low speed operation of the USB bit SPEED of SFR has to be set or cleared for the selection of the USB clock. Bit UCLK is a general enable bit for the USB clock.

XTAL1

12 MHz

XTAL2

Oscillator

6 MHz

C540U / C541U

Crystal

Divider PLL

by 2

12 MHz

48 MHz

Figure 8 Block Diagram of the Clock Generation Circuitry

x 4

1 0

SPEED DCR.7

System Clock of the Microcontroler

Enable

PCLK

DCR.0

to USB

Module

UCLK DCR.1

MCB03377

Semiconductor Group 16 1997-10-01

C540U C541U

The clock generator provides the internal clock signals to the chip. These signals define the internal phases, states and machine cycles. Figure 9 shows the recommended oscillator circuits for crystal and external clock operation.

XTAL2

C = 20 pF 10 pF for crystal operation

External Clock Signal

Figure 9 Recommended Oscillator Circuitries

12 MHz

N.C.

C540U C541U

XTAL1

C540U C541U

XTAL2

XTAL1

MCD03378

Semiconductor Group 17 1997-10-01

C540U C541U

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative way to control the execution of C500 MCUs and to gain extensive information on the internal operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the supprt of the Enhanced Hooks Emulation Concept. Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation and production chips are identical.

The Enhanced Hooks Technology together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate all operating modes of the different versions of the C500 microcontrollers. This includes emulation of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in single step mode and to read the SFRs after a break.

, which requires embedded logic in the C500 allows the C500

SYSCON

PCON TCON

Optional

I/O Ports

ICE-System Interface

to Emulation Hardware

RESET

ALE

PSEN

C500

MCU Interface Circuit

Port 3 Port 1

Port 0 Port 2

Target System Interface

RSYSCON

RPCON RTCON

Enhanced Hooks

RPort 0RPort 2

EH-IC

TEA TALE TPSEN

MCS02647

Figure 10 Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks Emulation Concept to control the operation of the device during emulation and to transfer informations about the programm execution and data transfer between the external emulation hardware (ICE-system) and the C500 MCU.

1 “Enhanced Hooks Technology“ is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 18 1997-10-01

C540U C541U

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in the special function register area. The special function register area consists of two portions: the standard special function register area and the mapped special function register area. One special function register of the C540U/C541U (PCON1) is located in the mapped special function register area. All other SFRs are located in the standard special function register area.

For accessing PCON1 in the mapped special function register area, bit RMAP in special function register SYSCON must be set.

Special Function Register SYSCON (Address B1H) Reset Value : XX10XXXX

Bit No. MSB LSB

76543210

Bit Function

RMAP Special function register map bit

As long as bit RMAP is set, a mapped special function register can be accessed. This bit is not cleared by hardware automatically. Thus, when non-mapped/mapped registers are to be accessed, the bit RMAP must be cleared/set by software, respectively each.

––

The functions of the shaded bits are not described in this section.

RMAP = 0 : The access to the non-mapped (standard) special function

RMAP = 1 : The access to the mapped special function register area

EALE RMAP –

(PCON1) is enabled.

––

–

SYSCON

The registers, except the program counter and the four general purpose register banks, reside in the special function register area. All SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, ..., F8H, FFH) are bitaddressable.

The 75 special function registers (SFRs) in the SFR area include pointers and registers that provide an interface between the CPU and the other on-chip peripherals. The SFRs of the C540U/C541U are listed in table 3 to table 4. In table 3 they are organized in groups which refer to the functional blocks of the C540U/C541U. Table 4 and table 4 illustrate the contents of the SFRs in numeric order of their addresses.

Semiconductor Group 19 1997-10-01

C540U C541U

Table 3 Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B DPH DPL PSW SP VR0 VR1 VR2 SYSCON

Interrupt System

IEN0 IEN1 IP0 IP1 ITCON

Ports P0

P1 P2 P3

Timer 0 / Timer 1

TCON TH0 TH1 TL0 TL1 TMOD

SSC Interface (C541U only)

SSCCON STB SRB SCF SCIEN SSCMOD

Watchdog (C541U

WDCON WDTREL

only)

Accumulator B Register Data Pointer, High Byte Data Pointer, Low Byte Program Status Word Register Stack Pointer Version Register 0 Version Register 1 Version Register 2 System Control Register

Interrupt Enable Register 0 Interrupt Enable Register 1 Interrupt Priority Register 0 Interrupt Priority Register 1 External Interrupt Trigger Condition Register

Port 0 Port 1 Port 2 Port 3

Timer 0/1 Control Register Timer 0, High Byte Timer 1, High Byte Timer 0, Low Byte Timer 1, Low Byte Timer Mode Register

SSC Control Register SSC Transmit Buffer SSC Receive Register SSC Flag Register SSC Interrupt Enable Register SSC Mode Test Register

Watchdog Timer Control Register Watchdog Timer Reload Register

E0 F0

83 82

81 FC FD FE B1

B9 9A

80 90 A0 B0

8C 8D 8A 8B 89

93 94 95

AB AC 96

H H

H H H H

H H

1) )

)

XX10XXXX 0XXX0000

XXXXX000 XXXX0000 XXXXX000 XXXX1010

H H

XX XX XXXXXX00 XXXXXX00 00

XXXX0000 00

1) Bit-addressable special function registers

2) “X“ means that the value is undefined and the location is reserved

3) The content of this SFR varies with the actual of the step C540U/C541U (eg. 01

4) This SFR is located in the mapped SFR area. For accessing this SFR, bit RMAP in SFR SYSCON must be set.

for the first step)

Semiconductor Group 20 1997-10-01

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