Siemens SAB-C517A-4R24M, SAB-C517A-4RM, SAB-C517A-L24M, SAB-C517A-LM, SAF-C517A-4R24M Datasheet

Microcomputer Components

8-Bit CMOS Microcontroller

C517A

Data Sheet 10.97

C517A Data Sheet

Revision History: Current Version: 10.97

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Edition 10.97
Published by Siemens AG,

Bereich Halbleiter, Marketing­Kommunikation, Balanstraße 73,
81541 München

© Siemens AG 1997.

All Rights Reserved.

Attention please!

As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes
and circuits implemented within components or assemblies.

The information describes the type of component and shall not be considered as assured characteristics.
Terms of delivery and rights to change design reserved.
For questions on technology, delivery and prices please contact the Semiconductor Group Offices in Germany or the Siemens Companies

and Representatives worldwide (see address list).
Due to technical requirements components may contain dangerous substances. For information on the types in question please contact

your nearest Siemens Office, Semiconductor Group.
Siemens AG is an approved CECC manufacturer.

Packing

Please use the recycling operators known to you. We can also help you – get in touch with your nearest sales office. By agreement we
will take packing material back, if it is sorted. You must bear the costs of transport.

For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs in­curred.

Components used in life-support devices or systems must be expressly authorized for such purpose!

Critical components
written approval of the Semiconductor Group of Siemens AG.

1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the

failure of that life-support device or system, or to affect its safety or effectiveness of that device or system.

2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain hu-

man life. If they fail, it is reasonable to assume that the health of the user may be endangered.

1

of the Semiconductor Group of Siemens AG, may only be used in life-support devices or systems

2

with the express

8-Bit CMOS Microcontroller

Advance Information

• Full upward compatibility with SAB 80C517A/83C517A-5

• Up to 24 MHz external operating frequency

– 500 ns instruction cycle at 24 MHz operation

• Superset of the 8051 architecture with 8 datapointers

• On-chip emulation support logic (Enhanced Hooks Technology

• 32K byte on-chip ROM (with optional ROM protection)

– alternatively up to 64K byte external program memory

• Up to 64K byte external data memory

• 256 byte on-chip RAM

• Additional 2K byte on-chip RAM (XRAM)

• Seven 8-bit parallel I/O ports

• Two input ports for analog/digital input

(further features are on next page)

TM

C517A

)

Oscillator

Watchdog

Power
Saving
Modes

On-Chip Emulation Support Module

8 Bit

USART UART

Figure 1
C517A Functional Units

Watchdog

Timer

Compare

Timer

10-Bit

A/D Converter

8 Bit

T2CCU

XRAM RAM

T0

(8 Datapointer)

T1

Port 8

Analog/

Digital

Input

256 x 82K x 8

CPU

ROM

32k x 8

Port 7 Port 6 Port 5 Port 4

Digital

Input

MDU

I/O

Port 0

Port 1

Port 2

Port 3

I/OAnalog/

I/O

I/O

I/O

I/O

I/O

MCA03317

Semiconductor Group 3 1997-10-01

C517A

Features (cont’d):

• Two full duplex serial interfaces (USART)

– 4 operating modes, fixed or variable baud rates
– programmable baud rate generators

• Four 16-bit timer/counters

– Timer 0 / 1 (C501 compatible)
– Timer 2 for 16-bit reload, compare, or capture functions
– Compare timer for compare/capture functions

• Powerful 16-bit compare/capture unit (CCU) with up to 21 high-speed or PWM output channels

and 5 capture inputs

• 10-bit A/D converter

– 12 multiplexed analog inputs
– Built-in self calibration

• Extended watchdog facilities

– 15-bit programmable watchdog timer
– Oscillator watchdog

• Power saving modes

– Slow down mode
– Idle mode (can be combined with slow down mode)
– Software power-down mode
– Hardware power-down mode

• 17 interrupt sources (7 external, 10 internal) selectable at 4 priority levels

• P-MQFP-100 packages

• Temperature Ranges: SAB-C517A T

SAF-C517A TA= -40 to 85 °C
SAH-C517A TA= -40 to 110 °C

= 0 to 70 °C

A

Table 1
Ordering Information

Type Ordering Code Package Description

(8-Bit CMOS microcontroller)

SAB-C517A-4RM Q67120-DXXXX P-MQFP-100-2 with mask programmable ROM

(18 MHz)

SAF-C517A-4RM Q67120-DXXXX P-MQFP-100-2 with mask programmable ROM

(18 MHz) ext. temp. – 40 °C to 85 °C

SAB-C517A-4R24M Q67120-DXXXX P-MQFP-100-2 with mask programmable ROM

(24 MHz)

SAF-C517A-4R24M Q67120-DXXXX P-MQFP-100-2 with mask programmable ROM

(24 MHz) ext. temp. – 40 °C to 85 °C
SAB-C517A-LM Q67127-C1071 P-MQFP-100-2 for external memory (18 MHz)
SAF-C517A-LM Q67127-C1063 P-MQFP-100-2 for external memory (18 MHz)

ext. temp. – 40 °C to 85 °C
SAB-C517A-L24M Q67127-C1072 P-MQFP-100-2 for external memory (24 MHz)

Semiconductor Group 4 1997-10-01

C517A

Note: Versions for extended temperature ranges – 40 °C to 110 °C (SAH-C517A) are available on

request. The ordering number of ROM types (DXXXX extensions) is defined after program
release (verification) of the customer.

VV

CC

SS

Port 7

8-bit Analog/

Digital Input

Port 8

4-bit Analog/

Digital Input

XTAL1

XTAL2

ALE

PSEN

EA

RESET

PE/SWD

OWE

RO

HWPD

V

AREF

V

AGND

C517A

MCL03318

Port 0
8-Bit Digital I/O

Port 1
8-Bit Digital I/O

Port 2
8-Bit Digital I/O

Port 3
8-Bit Digital I/O

Port 4
8-Bit Digital I/O

Port 5
8-Bit Digital I/O

Port 6
8-Bit Digital I/O

Figure 2
Logic Symbol

Additional Literature

For further information about the C517A the following literature is available:

Title Ordering Number

C517A 8-Bit CMOS Microcontroller User’s Manual B158-H7053-X-X-7600
C500 Microcontroller Family

B158-H6987-X-X-7600

Architecture and Instruction Set User’s Manual
C500 Microcontroller Family - Pocket Guide B158-H6986-X-X-7600

Semiconductor Group 5 1997-10-01

P1.6/CLKOUT

P1.7/T2

P3.7/RD

P3.6/WR

P3.5/T1

P3.4/T0

P3.3/INT1

P3.2/INT0

P3.1/TxD0

P3.0/RxD0

N.C.

N.C.

P7.0/AIN0

P7.1/AIN1

P7.2/AIN2

P7.3/AIN3

P7.4/AIN4

P7.5/AIN5

P7.6/AIN6

C517A

CC4/INT2/P1.4

N.C.
N.C.
N.C.

N.C.
CC3/INT6/P1.3
CC2/INT5/P1.2

CC1/INT4/P1.1

CC0/INT3/P1.0

V

SS

V

CC

XTAL2

XTAL1

P2.0/A8

P2.1/A9

P2.2/A10

P2.3/A11
P2.4/A12
P2.5/A13
P2.6/A14
P2.7/A15

PSEN

ALE

EA

N.C.
P0.0/AD0
P0.1/AD1

N.C.

N.C.
P0.2/AD2

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30

10031

9932

9833

9734

9635

9536

9437

9338

9239

9140

9041

C517A

8942

8843

8744

8645

8546

8447

8348

8249

8150

80
79
78
77
76
75
74
73
72

71
70
69
68
67
66
65
64
63
62

61
60
59
58
57
56
55
54
53
52

51

P7.7/AIN7

V

AGND

V

AREF

N.C.
N.C.
N.C.
N.C.
RESET
P4.7/CM7
P4.6/CM6
P4.5/CM5
P4.4/CM4
P4.3/CM3
PE/SWD
P4.2/CM2
P4.1/CM1
P4.0/CM0

V

CC

V

SS

RO
P8.3/AIN11
P8.2/AIN10
P8.1/AIN9
P8.0/AIN8
P6.7
P6.6
P6.5
N.C.
N.C.
N.C.

P6.3

P6.4

TxD1/P6.2

MCP03319

P0.5/AD5

P0.3/AD3 P1.5/T2EX

P0.4/AD4

HWPD

P0.6/AD6

P0.7/AD7

CCM5/P5.5

CCM6/P5.6

CCM7/P5.7

CCM4/P5.4

CCM2/P5.2

CCM3/P5.3

CCM0/P5.0

CCM1/P5.1

OWE

RxD1/P6.1

ADST/P6.0

Figure 3
Pin Configuration P-MQFP-100 Package (Top View)

Semiconductor Group 6 1997-10-01

Table 2
Pin Definitions and Functions

Symbol Pin Number I/O*) Function

P-MQFP-100

C517A

P1.0 - P1.7 9 - 6, 1,

100 - 98

9

8

7

6

1
100
99
98

I/O Port 1

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 1 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 1 pins being
externally pulled low will source current (IIL, in the DC
characteristics) because of the internal pullup resistors.
The port is used for the low-order address byte during
program verification. Port 1 also contains the interrupt,
timer, clock, capture and compare pins that are used by
various options. The output latch corresponding to a
secondary function must be programmed to a one (1) for
that function to operate (except when used for the compare
functions). The secondary functions are assigned to the
port 1 pins as follows:
P1.0 INT3 CC0 Interrupt 3 input / compare 0 output /

capture 0 input

P1.1 INT4 CC1 Interrupt 4 input / compare 1 output /

capture 1 input

P1.2 INT5 CC2 Interrupt 5 input / compare 2 output /

capture 2 input

P1.3 INT6 CC3 Interrupt 6 input / compare 3 output /

capture 3 input
P1.4 INT2 Interrupt 2 input
P1.5 T2EX Timer 2 external reload / trigger input
P1.6 CLKOUT System clock output
P1.7 T2 Counter 2 input

V

SS

10, 62 – Ground (0V)

during normal, idle, and power down operation.

V

CC

11, 63 – Supply voltage

during normal, idle, and power down mode.

*) I = Input

O = Output

Semiconductor Group 7 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

XTAL2 12 – XTAL2

is the input to the inverting oscillator amplifier and input to
the internal clock generator circuits.
To drive the device from an external clock source, XTAL2
should be driven, while XTAL1 is left unconnected.
Minimum and maximum high and low times as well as rise/
fall times specified in the AC characteristics must be
observed.

XTAL1 13 – XTAL1

is the output of the inverting oscillator amplifier. This pin is
used for the oscillator operation with crystal or ceramic
resonator.

C517A

P2.0 - P2.7 14 - 21 I/O Port 2

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 2 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 2 pins being
externally pulled low will source current (I
characteristics) because of the internal pullup resistors.
Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses
(MOVX @DPTR). In this application it uses strong internal
pullup resistors when issuing 1's. During accesses to
external data memory that use 8-bit addresses
(MOVX @Ri), port 2 issues the contents of the P2 special
function register.

PSEN 22 O The Program Store Enable

output is a control signal that enables the external program
memory to the bus during external fetch operations. It is
activated every six oscillator periods except during
external data memory accesses. The signal remains high
during internal program execution.

, in the DC

IL

ALE 23 O The Address Latch enable

output is used for latching the address into external
memory during normal operation. It is activated every six
oscillator periods except during an external data memory
access.

*) I = Input

O = Output

Semiconductor Group 8 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

EA 24 I External Access Enable

When held high, the C517A executes instructions from the
internal ROM as long as the PC is less than 8000H. When
held low, the C517A fetches all instructions from external
program memory. For the C517A-L this pin must be tied
low.

C517A

P0.0 - P0.7 26, 27,

30 - 35

I/O Port 0

is an 8-bit open-drain bidirectional I/O port. Port 0 pins that
have 1's written to them float, and in that state can be used
as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to
external program and data memory. In this application it
uses strong internal pullup resistors when issuing 1's. Port
0 also outputs the code bytes during program verification
in the C517A. External pullup resistors are required during
program verification.

HWPD 36 I Hardware Power Down

A low level on this pin for the duration of one machine cycle
while the oscillator is running resets the C517A. A low level
for a longer period will force the part into hardware power
down mode with the pins floating. There is no internal
pullup resistor connected to this pin.

P5.0 - P5.7 44 - 37 I/O Port 5

is a quasi-bidirectional I/O port with internal pull-up
resistors. Port 5 pins that have 1 s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 5 pins being
externally pulled low will source current (I
characteristics) because of the internal pull-up resistors.
This port also serves the alternate function “Concurrent
Compare” and “Set/Reset Compare”. The secondary
functions are assigned to the port 5 pins as follows:
CCM0 to CCM7 P5.0 to P5.7:

concurrent compare or Set/Reset lines

, in the DC

IL

*) I = Input

O = Output

Semiconductor Group 9 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

OWE 45 I Oscillator Watchdog Enable

A high level on this pin enables the oscillator watchdog.
When left unconnected this pin is pulled high by a weak
internal pull-up resistor. The logic level at OWE should not
be changed during normal operation. When held at low
level the oscillator watchdog function is turned off. During
hardware power down the pullup resistor is switched off.

C517A

P6.0 - P6.7 46 - 50,

54 - 56

I/O Port 6

is a quasi-bidirectional I/O port with internal pull-up
resistors. Port 6 pins that have 1 s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 6 pins being
externally pulled low will source current (I
DC characteristics) because of the internal pull-up
resistors.
Port 6 also contains the external A/D converter control pin
and the transmit and receive pins for the serial interface 1.
The output latch corresponding to a secondary function
must be programmed to a one (1) for that function to
operate.
The secondary functions are assigned to the pins of port 6,
as follows:

46
47
48

P6.0 ADST external A/D converter start pin
P6.1 RxD1 receiver data input of serial interface 1
P6.2 TxD1 transmitter data input of serial interface 1

P8.0 - P8.3 57 - 60 I Port 8

is a 4-bit unidirectional input port. Port pins can be used for
digital input, if voltage levels meet the specified input high/
low voltages, and for the higher 4-bit of the multiplexed
analog inputs of the A/D converter, simultaneously.
P8.0 - P8.3 AIN8 - AIN11 analog input 8 - 14

, in the

IL

RO 61 O Reset Output

This pin outputs the internally synchronized reset request
signal. This signal may be generated by an external
hardware reset, a watchdog timer reset or an oscillator
watchdog reset. The RO is active low.

*) I = Input

O = Output

Semiconductor Group 10 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

C517A

P4.0 - P4.7 64 - 66,

68 - 72

I/O Port 4

is an 8-bit quasi-bidirectional I/O port with internal pull-up
resistors. Port 4 pins that have 1’s written to them are
pulled high by the internal pull-up resistors, and in that
state can be used as inputs. As inputs, port 4 pins being
externally pulled low will source current (IIL, in the DC
characteristics) because of the internal pull-up resistors.

PE/SWD 67 I Power saving mode enable / Start watchdog timer

A low level at this pin allows the software to enter the power
saving modes (idle mode, slow down mode, and power
down mode). In case the low level is also seen during
reset, the watchdog timer function is off on default.
Usage of the software controlled power saving modes is
blocked, when this pin is held at high level. A high level
during reset performs an automatic start of the watchdog
timer immediately after reset.
When left unconnected this pin is pulled high by a weak
internal pull-up resistor. During hardware power down the
pullup resistor is switched off.

RESET 73 I RESET

A low level on this pin for the duration of two machine
cycles while the oscillator is running resets the C517A. A
small internal pullup resistor permits power-on reset using
only a capacitor connected to VSS.

V

AREF

V

AGND

78 – Reference voltage for the A/D converter
79 – Reference ground for the A/D converter

P7.0 - P7.7 87 - 80 Port 7

is an 8-bit unidirectional input port. Port pins can be used
for digital input, if voltage levels meet the specified input
high/low voltages, and for the lower 8-bit of the multiplexed
analog inputs of the A/D converter, simultaneously.
P7.0 - P7.7 AIN0 - AIN7 analog input 8 - 14

*) I = Input

O = Output

Semiconductor Group 11 1997-10-01

Table 2
Pin Definitions and Functions (cont’d)

Symbol Pin Number I/O*) Function

P-MQFP-100

C517A

P3.0 - P3.7 90 - 97

90

91

92

93

94
95
96

97

I/O Port 3

is an 8-bit quasi-bidirectional I/O port with internal pullup
resistors. Port 3 pins that have 1's written to them are
pulled high by the internal pullup resistors, and in that state
can be used as inputs. As inputs, port 3 pins being
externally pulled low will source current (IIL, in the DC
characteristics) because of the internal pullup resistors.
Port 3 also contains the interrupt, timer, serial port and
external memory strobe pins that are used by various
options. The output latch corresponding to a secondary
function must be programmed to a one (1) for that function
to operate. The secondary functions are assigned to the
pins of port 3, as follows:
P3.0 RxD0 Receiver data input (asynch.) or data

input/output (synch.)of serial interface 0

P3.1 TxD0 Transmitter data output (asynch.) or

clock output (synch.) of serial interface 0

P3.2 INT0 External interrupt 0 input /

timer 0 gate control input

P3.3 INT1 External interrupt 1 input /

timer 1 gate control input
P3.4 T0 Timer 0 counter input
P3.5 T1 Timer 1 counter input
P3.6 WR WR control output; latches the data byte

from port 0 into the external data

memory
P3.7 RD RD control output; enables the external

data memory

N.C. 2 - 5, 25,

28, 29, 32,
43, 44,

– Not connected

These pins of the P-MQFP-100 package need not be
connected.

51 - 53,
74 - 77
88, 89

*) I = Input

O = Output

Semiconductor Group 12 1997-10-01

XTAL1

XTAL2

Oscillator Watchdog

OSC & Timing

256 x 8

XRAMRAM

2k x 8

C517A

ROM

32k x 8

ALE

PSEN

EA

PE/SWD

RESET

HWPD

RO

OWE

CPU

8 Datapointer

Programmable

Watchdog Timer

Timer 0

Timer 1

Timer 2

Capture

Compare Unit

Compare Timer

Serial Channel 0

Programmable

Baud Rate Generator

Serial Channel 1

Programmable

Baud Rate Generator

Interrupt Unit

Emulation

Support

Logic

Port 0

Port 1

Port 2

Port 3

Port 4

Port 5

Port 6

Port 0
8-Bit Digital I/O

Port 1
8-Bit Digital I/O

Port 2
8-Bit Digital I/O

Port 3
8-Bit Digital I/O

Port 4
8-Bit Digital I/O

Port 5
8-Bit Digital I/O

Port 6
8-Bit Digital I/O

V

V

AGND

AREF

A/D Converter

S & H

10 Bit

Analog

MUX

Port 7

Port 8

Port 7
8-Bit Analog/
Digital Input

Port 8
4-Bit Analog/
Digital Input

C517A

MCB03320

Figure 4
Block Diagram of the C517A

Semiconductor Group 13 1997-10-01

C517A

CPU

The C517A is efficient both as a controller and as an arithmetic processor. It has extensive facilities
for binary and BCD arithmetic and excels in its bit-handling capabilities. Efficient use of program
memory results from an instruction set consisting of 44 % one-byte, 41 % two-byte, and 15%
three-byte instructions. With a 12 MHz crystal, 58% of the instructions are executed in 1µs (24 MHz:
500 ns).

Special Function Register PSW (Address D0H) Reset Value : 00

Bit No. MSB LSB

D7

H

Bit Function

CY Carry Flag

AC Auxiliary Carry Flag

F0 General Purpose Flag
RS1

RS0

CY AC

D6

H

Used by arithmetic instruction.

Used by instructions which execute BCD operations.

Register Bank select control bits
These bits are used to select one of the four register banks.

RS1 RS0 Function

H

D5

F0

H

D4
RS1 RS0 OV F1 PD0

H

D3

H

D2

H

D1

H

D0

H

PSW

H

0 0 Bank 0 selected, data address 00H-07
0 1 Bank 1 selected, data address 08H-0F
1 0 Bank 2 selected, data address 10H-17
1 1 Bank 3 selected, data address 18H-1F

OV Overflow Flag

Used by arithmetic instruction.
F1 General Purpose Flag
P Parity Flag

Set/cleared by hardware after each instruction to indicate an odd/even

number of “one” bits in the accumulator, i.e. even parity.

Semiconductor Group 14 1997-10-01

H
H
H
H

Memory Organization

The C517A CPU manipulates operands in the following five address spaces:

– up to 64 Kbyte of program memory (32K on-chip program memory for C517A-4R)
– up to 64 Kbyte of external data memory
– 256 bytes of internal data memory
– 2K bytes of internal XRAM data memory
– a 128 byte special function register area

Figure 5 illustrates the memory address spaces of the C517A.

FFFF

H

ext.

FFFF

H

int.

(XMAP0 = 0) (XMAP0 = 1)

ext.

C517A

int.

"Code Space"

ext.

(EA = 0)(EA = 1)

Figure 5
C517A Memory Map

8000

H

7FFF

0000

F800

H

F7FF

H

H

ext.

H

"Data Space" "Internal Data Space"

0000

H

Indirect

Address Address

FF

Internal

RAM

80

Internal

RAM

H

H

Direct

Special

Function

Regs.

7F

H

00

H

FF

H

80

H

MCB03321

Semiconductor Group 15 1997-10-01

C517A

Reset and System Clock

The reset input is an active low input at pin RESET. Since the reset is synchronized internally, the
RESET pin must be held low for at least two machine cycles (24 oscillator periods) while the
oscillator is running. A pullup resistor is internally connected to VCC to allow a power-up reset with
an external capacitor only. An automatic reset can be obtained when VCC is applied by connecting
the RESET pin to VSS via a capacitor. Figure 6 shows the possible reset circuitries.

b)a)

&

Figure 6
Reset Circuitries

+

RESET

C517A

c)

+

RESET

RESET

C517A

C517A

MCS03323

Semiconductor Group 16 1997-10-01

C517A

Figure 7 shows the recommended oscillator circuitries for crystal and external clock operation.

Crystal Oscillator Mode Driving from External Source

C

3.5 - 24
MHz

C

Crystal Mode: C = 20 pF 10 pF

(Incl. Stray Capacitance)

Figure 7
Recommended Oscillator Circuitries

XTAL1

XTAL2

N.C.

External Oscillator
Signal

XTAL1

XTAL2

MCS03245

Semiconductor Group 17 1997-10-01

C517A

Enhanced Hooks Emulation Concept

The Enhanced Hooks Emulation Concept of the C500 microcontroller family is a new, innovative
way to control the execution of C500 MCUs and to gain extensive information on the internal
operation of the controllers. Emulation of on-chip ROM based programs is possible, too.

Each production chip has built-in logic for the support of the Enhanced Hooks Emulation Concept.
Therefore, no costly bond-out chips are necessary for emulation. This also ensure that emulation
and production chips are identical.

1)

The Enhanced Hooks Technology
together with an EH-IC to function similar to a bond-out chip. This simplifies the design and reduces
costs of an ICE-system. ICE-systems using an EH-IC and a compatible C500 are able to emulate
all operating modes of the different versions of the C500 microcontrollers. This includes emulation
of ROM, ROM with code rollover and ROMless modes of operation. It is also able to operate in
single step mode and to read the SFRs after a break.

TM

, which requires embedded logic in the C500 allows the C500

SYSCON

PCON

TCON

opt.

I/O Ports

C500
MCU

RESET

EA

ALE

PSEN
Port 0

Port 2

Port 1Port 3

Target System Interface

RPORT RPORT

ICE-System interface

to emulation hardware

RSYSCON

RPCON
RTCON

Enhanced Hooks

Interface Circuit

2

0

EH-IC

TEA TALE TPSEN

MCS03254

Figure 8
Basic C500 MCU Enhanced Hooks Concept Configuration

Port 0, port 2 and some of the control lines of the C500 based MCU are used by Enhanced Hooks
Emulation Concept to control the operation of the device during emulation and to transfer
informations about the program execution and data transfer between the external emulation
hardware (ICE-system) and the C500 MCU.

1 “Enhanced Hooks Technology” is a trademark and patent of Metalink Corporation licensed to Siemens.

Semiconductor Group 18 1997-10-01

C517A

Special Function Registers

The registers, except the program counter and the four general purpose register banks, reside in
the special function register area.

The 94 special function registers (SFRs) in the standard and mapped SFR area include pointers
and registers that provide an interface between the CPU and the other on-chip peripherals. All
SFRs with addresses where address bits 0-2 are 0 (e.g. 80H, 88H, 90H, 98H, …, F8H, FFH) are
bitaddressable. The SFRs of the C517A are listed in table 3 and table 4. In table 3 they are
organized in groups which refer to the functional blocks of the C517A. Table 4 illustrates the
contents of the SFRs in numeric order of their addresses.

Semiconductor Group 19 1997-10-01

C517A

Table 3
Special Function Registers - Functional Blocks

Block Symbol Name Address Contents after

Reset

CPU ACC

B
DPH
DPL
DPSEL
PSW
SP

A/D­Converter

ADCON0

ADCON1
ADDATH
ADDATL

Interrupt
System

IEN0
IEN1

2)

2)

IEN2

2)

IP0
IP1
IRCON0
IRCON1
TCON
T2CON
S0CON
CTCON

MUL/DIV
Unit

ARCON
MD0
MD1
MD2
MD3
MD4
MD5

Timer 0 /
Timer 1

TCON
TH0
TH1
TL0
TL1
TMOD

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) ‘X’ means that the value is undefined and the location is reserved

Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word Register
Stack Pointer

2)

A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register, High Byte
A/D Converter Data Register, Low Byte

Interrupt Enable Register 0
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Priority Register 0
Interrupt Priority Register 1

2)

Interrupt Request Control Register 0
Interrupt Request Control Register 1

2)

Timer 0/1 Control Register

2)

Timer 2 Control Register

2)

Serial Channel 0 Control Register

2)

Compare Timer Control Register
Arithmetic Control Register

Multiplication/Division Register 0
Multiplication/Division Register 1
Multiplication/Division Register 2
Multiplication/Division Register 3
Multiplication/Division Register 4
Multiplication/Division Register 5

2)

Timer 0/1 Control Register
Timer 0, High Byte
Timer 1, High Byte
Timer 0, Low Byte
Timer 1, Low Byte
Timer Mode Register

E0
F0

83
82
92

D0

81

D8

DC
D9
DA

A8
B8

9A
A9
B9

C0

D1

88
C8
98

E1
EF

E9
EA
EB
EC
ED
EE

88

8C
8D
8A
8B
89

H

H
H
H

H

H

H

H

H

H

H

H

H

H
H

H
H
H

H

H

H

H
H

H

H
H
H
H

H
H
H
H
H

H

H

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

1)

00

H

00

H

00

H

00

H

XXXX X000
00

H

07

H

00

H

0XXX 0000
00

H

00XX XXXX
00

H

00

H

XX00 00X0
00

H

XX00 0000
00

H

00

H

00

H

00

H

00

H

0X00 0000
0XXXXXXX

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

3)

XX

H

00

H

00

H

00

H

00

H

00

H

00

H

3)

B

3)

B

3

B

3)

B

3)

B

3)

B

3)

B

Semiconductor Group 20 1997-10-01

C517A

Table 3
Special Function Registers - Functional Blocks (cont’d)

Block Symbol Name Address Contents after

Reset

Compare/
Capture
Unit
(CCU)
Timer 2

1) Bit-addressable special function registers

2) This special function register is listed repeatedly since some bits of it also belong to other functional blocks.

3) ‘X’ means that the value is undefined and the location is reserved

CCEN
CC4EN
CCH1
CCH2
CCH3
CCH4
CCL1
CCL2
CCL3
CCL4
CMEN
CMH0
CMH1
CMH2
CMH3
CMH4
CMH5
CMH6
CMH7
CML0
CML1
CML2
CML3
CML4
CML5
CML6
CML7
CMSEL
CRCH
CRCL

COMSETL
COMSETH
COMCLRL
COMCLRH

SETMSK
CLRMSK
CTCON

2)

CTRELH
CTRELL
TH2
TL2
T2CON

2)

IRCON0

Compare/Capture Enable Register
Compare/Capture 4 Enable Register
Compare/Capture Register 1, High Byte
Compare/Capture Register 2, High Byte
Compare/Capture Register 3, High Byte
Compare/Capture Register 4, High Byte
Compare/Capture Register 1, Low Byte
Compare/Capture Register 2, Low Byte
Compare/Capture Register 3, Low Byte
Compare/Capture Register 4, Low Byte
Compare Enable Register
Compare Register 0, High Byte
Compare Register 1, High Byte
Compare Register 2, High Byte
Compare Register 3, High Byte
Compare Register 4, High Byte
Compare Register 5, High Byte
Compare Register 6, High Byte
Compare Register 7, High Byte
Compare Register 0, Low Byte
Compare Register 1, Low Byte
Compare Register 2, Low Byte
Compare Register 3, Low Byte
Compare Register 4, Low Byte
Compare Register 5, Low Byte
Compare Register 6, Low Byte
Compare Register 7, Low Byte
Compare Input Select
Comp./Rel./Capt. Register High Byte
Comp./Rel./Capt. Register Low Byte
Compare Set Register Low Byte
Compare Set Register, High Byte
Compare Clear Register, Low Byte
Compare Clear Register, High Byte
Compare Set Mask Register
Compare Clear Mask Register
Compare Timer Control Register
Compare Timer Rel. Register, High Byte
Compare Timer Rel. Register, Low Byte
Timer 2, High Byte
Timer 2, Low Byte
Timer 2 Control Register

2)

Interrupt Request Control Register 0

C1
C9
C3
C5
C7
CF
C2
C4
C6
CE
F6
D3
D5
D7
E3
E5
E7
F3
F5
D2
D4
D6
E2
E4
E6
F2
F4
F7
CB
CA
A1
A2
A3
A4
A5
A6
E1
DF
DE
CD
CC

C8
C0

H

H
H

H
H
H

H
H
H
H
H

H
H
H

H
H
H
H
H
H

H
H
H
H
H
H

H
H
H
H
H
H
H

H
H

H

H

H
H

H
H

H
H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

00

H

0X00 0000
00

H

00

H

00

H

00

1)

1)

00
00

H
H
H

B

3

)

Semiconductor Group 21 1997-10-01