INTEGRATED CIRCUITS
DATA SHEET
74AHC373; 74AHCT373
Octal D-type transparent latch; 3-state
Product specification |
1999 Nov 23 |
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC06
Philips Semiconductors |
Product specification |
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Octal D-type transparent latch; 3-state |
74AHC373; 74AHCT373 |
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FEATURES
·ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V
·Balanced propagation delays
·All inputs have Schmitt-trigger actions
·Inputs accepts voltages higher than VCC
·Common 3-state output enable input
·Functionally identical to the ‘533’, ‘563’ and ‘573’
·For AHC only: operates with CMOS input levels
·For AHCT only: operates with TTL input levels
·Specified from -40 to +85 °C and -40 to +125 °C.
DESCRIPTION
The 74AHC/AHCT373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.
QUICK REFERENCE DATA
Ground = 0 V; Tamb = 25 °C; tr = tf £ 3.0 ns.
The 74AHC/AHCT373 are octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A Latch Enable (LE) input and an Output Enable (OE) input are common to all latches.
The ‘373’ consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the
Dn inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D-input changes.
When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the 8 latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.
The ‘373’ is functionally identical to the ‘533’, ‘563’ and ‘573’, but the ‘533’ and ‘563’ have inverted outputs and the ‘563’ and ‘573’ have a different pin arrangement.
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PARAMETER |
CONDITIONS |
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TYPICAL |
UNIT |
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AHC |
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AHCT |
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tPHL/tPLH |
propagation delay |
CL = 15 pF; VCC = 5 V |
4.3 |
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4.3 |
ns |
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Dn to Qn; LE to Qn |
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CI |
input capacitance |
VI = VCC or GND |
3.0 |
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3.0 |
pF |
CO |
output capacitance |
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4.0 |
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4.0 |
pF |
CPD |
power dissipation |
CL = 50 pF; f = 1 MHz; |
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12 |
pF |
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capacitance |
notes 1 and 2 |
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Notes
1.CPD is used to determine the dynamic power dissipation (PD in mW). PD = CPD ´ VCC2 ´ fi + å (CL ´ VCC2 ´ fo) where:
fi = input frequency in MHz; fo = output frequency in MHz;
å (CL ´ VCC2 ´ fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
1999 Nov 23 |
2 |
Philips Semiconductors |
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Product specification |
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Octal D-type transparent latch; 3-state |
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74AHC373; 74AHCT373 |
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FUNCTION TABLE |
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See note 1. |
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OPERATING MODES |
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INPUTS |
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INTERNAL |
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OUTPUTS |
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LATCHES |
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OE |
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LE |
Dn |
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Q0 to Q7 |
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Enable and read register |
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L |
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H |
L |
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L |
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L |
(transparent mode) |
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L |
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H |
H |
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H |
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H |
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Latch and read register |
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L |
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L |
I |
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L |
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L |
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L |
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L |
h |
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H |
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H |
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Latch register and |
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H |
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X |
X |
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X |
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Z |
disable outputs |
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H |
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X |
X |
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X |
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Z |
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Note
1.H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level;
I = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; X = don’t care;
Z = high-impedance OFF-state.
ORDERING INFORMATION
OUTSIDE NORTH |
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NORTH AMERICA |
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PACKAGES |
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AMERICA |
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PINS |
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MATERIAL |
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74AHC373D |
74AHC373D |
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SO |
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plastic |
SOT163-1 |
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74AHC373PW |
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74AHC373PW DH |
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TSSOP |
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plastic |
SOT360-1 |
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74AHCT373D |
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74AHCT373D |
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SO |
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plastic |
SOT163-1 |
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74AHCT373PW |
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7AHCT373PW DH |
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TSSOP |
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plastic |
SOT360-1 |
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PINNING |
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PIN |
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SYMBOL |
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DESCRIPTION |
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1 |
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output enable input (active LOW) |
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OE |
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2, 5, 6, 9, 12, 15, 16 |
Q0 to Q7 |
latch outputs |
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and 19 |
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3, 4, 7, 8, 13, 14, 17 |
D0 to D7 |
data inputs |
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and 18 |
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10 |
GND |
ground (0 V) |
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11 |
LE |
latch enable input (active HIGH) |
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20 |
VCC |
DC supply voltage |
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1999 Nov 23 |
3 |
Philips Semiconductors |
Product specification |
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Octal D-type transparent latch; 3-state |
74AHC373; 74AHCT373 |
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handbook, halfpage
OE |
1 |
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20 |
VCC |
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Q0 |
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Q7 |
handbook, halfpage |
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11 |
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2 |
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19 |
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D0 |
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D7 |
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3 |
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LE |
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3 |
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18 |
D0 |
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Q0 |
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4 |
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D1 |
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D6 |
D1 |
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Q1 |
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4 |
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Q1 |
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Q6 |
D2 |
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Q2 |
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5 |
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16 |
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8 |
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D3 |
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Q3 |
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Q2 |
373 |
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Q5 |
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13 |
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12 |
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15 |
D4 |
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Q4 |
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14 |
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15 |
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D5 |
D5 |
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Q5 |
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D2 7 |
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D6 |
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Q6 |
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D4 |
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D |
3 |
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D7 |
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Q7 |
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Q3 |
9 |
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Q4 |
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OE |
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12 |
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1 |
MNA186 |
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GND 10 |
11 |
LE |
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MNA185 |
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Fig.1 Pin configuration. |
Fig.2 Logic symbol. |
handbook, halfpage |
1 |
EN |
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11 |
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C1 |
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1D |
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4 |
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7 |
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6 |
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8 |
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9 |
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13 |
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12 |
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14 |
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15 |
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17 |
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16 |
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18 |
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19 |
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MNA187 |
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Fig.3 IEC logic symbol.
1999 Nov 23 |
4 |
Philips Semiconductors |
Product specification |
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Octal D-type transparent latch; 3-state |
74AHC373; 74AHCT373 |
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handbook, halfpage |
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3 |
D0 |
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Q0 |
2 |
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4 |
D1 |
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Q1 |
5 |
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7 |
D2 |
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Q2 |
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LE |
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D3 |
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Q3 |
handbook, halfpage |
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8 |
LATCH |
3-STATE |
9 |
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13 |
D4 |
Q4 |
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1 to 8 |
OUTPUTS |
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14 |
D5 |
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Q5 |
15 |
LE |
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17 |
D6 |
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Q6 |
16 |
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LE |
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D7 |
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Q7 |
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18 |
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D |
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Q |
11 |
LE |
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LE |
MNA189 |
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1 |
OE |
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MNA184 |
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Fig.4 Functional diagram. |
Fig.5 Logic diagram (one latch). |
D0 |
D1 |
D2 |
D3 |
D4 |
D5 |
D6 |
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D7 |
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D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
D Q |
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LATCH |
LATCH |
LATCH |
LATCH |
LATCH |
LATCH |
LATCH |
LATCH |
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1 |
2 |
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4 |
5 |
6 |
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LE LE |
LE LE |
LE LE |
LE LE |
LE LE |
LE LE |
LE LE |
LE LE |
LE |
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OE |
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Q0 |
Q1 |
Q2 |
Q3 |
Q4 |
Q5 |
Q6 |
Q7 |
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MNA199 |
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Fig.6 |
Logic diagram. |
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1999 Nov 23 |
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5 |
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Philips Semiconductors |
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Product specification |
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Octal D-type transparent latch; 3-state |
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74AHC373; 74AHCT373 |
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RECOMMENDED OPERATING CONDITIONS |
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SYMBOL |
PARAMETER |
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CONDITIONS |
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74AHC |
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74AHCT |
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UNIT |
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MIN. |
TYP. |
MAX. |
MIN. |
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TYP. |
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MAX. |
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VCC |
DC supply voltage |
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2.0 |
5.0 |
5.5 |
4.5 |
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5.0 |
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5.5 |
V |
VI |
input voltage |
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0 |
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5.5 |
0 |
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5.5 |
V |
VO |
output voltage |
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0 |
− |
VCC |
0 |
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VCC |
V |
Tamb |
operating ambient temperature |
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see DC and AC |
−40 |
+25 |
+85 |
−40 |
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+25 |
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+85 |
°C |
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characteristics per |
−40 |
+25 |
+125 |
−40 |
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+25 |
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+125 |
°C |
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device |
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tr,tf ( t/ f) |
input rise and fall rates |
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VCC = 3.3 ±0.3 V |
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100 |
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ns/V |
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VCC = 5 ±0.5 V |
− |
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20 |
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ns/V |
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL |
PARAMETER |
CONDITIONS |
MIN. |
MAX. |
UNIT |
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VCC |
DC supply voltage |
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−0.5 |
+7.0 |
V |
VI |
input voltage |
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−0.5 |
+7.0 |
V |
IIK |
DC input diode current |
VI < −0.5 V; note 1 |
− |
−20 |
mA |
IOK |
DC output diode current |
VO < −0.5 V or VO > VCC + 0.5 V; note 1 |
− |
±20 |
mA |
IO |
DC output source or sink current |
−0.5 V < VO < VCC + 0.5 V |
− |
±25 |
mA |
ICC |
DC VCC or GND current |
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±75 |
mA |
Tstg |
storage temperature |
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−65 |
+150 |
°C |
PD |
power dissipation per package |
for temperature range: −40 to +125 °C; note 2 |
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500 |
mW |
Notes
1.The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2.For SO package: above 70 °C the value of PD derates linearly with 8 mW/K.
For TSSOP package: above 60 °C the value of PD derates linearly with 5.5 mW/K.
1999 Nov 23 |
6 |
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