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M30805SGP
Datasheet
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Mitsubishi M30805SGP, M30805MG-XXXGP, M30805FGGP, M30802SGP, M30802MC-XXXGP Datasheet

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Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group

Description

1
------Table of Contents------
Description
The M16C/80 (144-pin version) group of single-chip microcomputers are built using the high-performance
silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 144-pin plastic
molded QFP. These single-chip microcomputers operate using sophisticated instructions featuring a high
level of instruction efficiency. With 16M bytes of address space, they are capable of executing instructions
at high speed. They also feature a built-in multiplier and DMAC, making them ideal for controlling office,
communications, industrial equipment, and other high-speed processing applications.
The M16C/80 (144-pin version) group includes a wide range of products with different internal memory
types and sizes and various package types.
Features
• Memory capacity..................................ROM (See ROM expansion figure.)
RAM 10 to 24 Kbytes
• Shortest instruction execution time......50ns (f(XIN)=20MHz)
• Supply voltage .....................................4.2 to 5.5V (f(XIN)=20MHz) Mask ROM and flash memory version
2.7 to 5.5V (f(XIN)=10MHz) Mask ROM and flash memory version
• Low power consumption ......................45mA (M30802MC-XXXGP)
• Interrupts..............................................29 internal and 8 external interrupt sources, 5 software
interrupt sources; 7 levels (including key input interrupt)
• Multifunction 16-bit timer......................5 output timers + 6 input timers
• Serial I/O..............................................5 channels
for UART or clock synchronous
• DMAC ..................................................4 channels (trigger: 31 sources)
• DRAMC................................................Used for EDO, FP, CAS before RAS refresh, self-refresh
• A-D converter.......................................10 bits X 8 channels (Expandable up to 10 channels)
• D-A converter.......................................8 bits X 2 channels
• CRC calculation circuit.........................1 circuit
• X-Y converter.......................................1 circuit
• Watchdog timer....................................1 line
• Programmable I/O ...............................123 lines
• Input port..............................................
_______
1 line (P85 shared with NMI pin)
• Memory expansion ..............................Available (16M bytes)
• Chip select output ................................4 lines
• Clock generating circuit .......................2 built-in clock generation circuits
(built-in feedback resistance, and external ceramic or quartz oscillator)
Applications
Audio, cameras, office equipment, communications equipment, portable equipment, etc.
CPU ..............................................................11
Reset.............................................................16
Processor Mode............................................24
Clock Generating Circuit ...............................40
Protection......................................................52
Outline of Interrupt ........................................53
Watchdog Timer............................................75
DMAC ...........................................................77
Timer.............................................................88
Serial I/O .....................................................120
Specifications written in this
manual are believed to be ac-
curate, but are not guaranteed
to be entirely free of error.
Specifications in this manual
may be changed for functional
or performance improvements.
Please make sure your manual
is the latest edition.
A-D Converter .............................................162
D-A Converter .............................................172
CRC Calculation Circuit .............................. 174
X-Y Converter .............................................176
DRAM Controller.........................................179
Programmable I/O Ports .............................186
Usage Precaution .......................................203
Electric characteristics ................................210
Flash memory version.................................257
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
2
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
P9
6
/ANEX
1
/T
X
D
4
/SDA
4
/SRxD
4
P9
5
/ANEX
0
/CLK
4
P9
2
/TB
2IN
/T
X
D
3
/SDA
3
/SRxD
3
P9
1
/TB
1IN
/R
X
D
3
/SCL
3
/STxD
3
P9
0
/TB
0IN
/CLK3
P14
6
P14
5
P14
4
P14
3
P14
1
P14
2
P14
0
BYTE
CNV
SS
P8
7
/X
CIN
P8
6
/X
COUT
X
OUT
V
SS
X
IN
V
CC
P8
0
/TA
4OUT
/U
P7
7
/TA
3IN
P7
6
/TA
3OUT
P7
4
/TA
2OUT
/W
P7
2
/CLK
2
/TA
1OUT
/V
(Note)
P7
1
/R
X
D
2
/SCL
2
/TA
0IN
/TB
5IN (Note)
P9
4
/DA
1
/TB
4IN
/CTS
4
/RTS
4
/SS
4
P9
3
/DA
0
/TB
3IN
/CTS
3
/RTS
3
/SS
3
RESET
P8
5
/NMI
P8
4
/INT
2
P8
3
/INT
1
P8
2
/INT
0
P8
1
/TA
4IN
/U
P7
5
/TA
2IN
/W
P7
3
/CTS
2
/RTS
2
/TA
1IN
/V
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
P70/TXD2/SDA2/TA0OUT
P67/TXD1
VCC
P66/RXD1
VSS
P65/CLK1
P63/TXD0
P62/RXD0
P61/CLK0
P137
P136
P135
P134
P133
VSS
P132
VCC
P131
P130
P53/BCLK/ALE/CLKOUT
P127
P126
P125
P64/CTS1/RTS1/CTS0/CLKS1
P60/CTS0/RTS0
P56/ALE/RAS
P55/HOLD
P54/HLDA/ALE
P52/RD/DW
P51/WRH/BHE/CASH
P50/WRL/WR/CASL
P47/CS0/A23
P46/CS1/A22
P45/CS2/A21
P44/CS3/A20(MA12)
P4
3
/A
19
(MA11)
V
CC
P4
2
/A
18
(MA10)
V
SS
P4
1
/A
17
(MA9)
P4
0
/A
16
(MA8)
P3
7
/A
15
(MA7)(/D
15
)
P3
6
/A
14
(MA6)(/D
14
)
P3
5
/A
13
(MA5)(/D
13
)
P3
4
/A
12
(MA4)(/D
12
)
P3
3
/A
11
(MA3)(/D
11
)
P3
2
/A
10
(MA2)(/D
10
)
P3
1
/A
9
(MA1)(/D
9
)
P12
4
P12
3
P12
2
P12
1
P12
0
V
CC
P3
0
/A
8
(MA0)(/D
8
)
P2
7
/A
7
(/D
7
)
P2
6
/A
6
(/D
6
)
P2
5
/A
5
(/D
5
)
P2
4
/A
4
(/D
4
)
P2
3
/A
3
(/D
3
)
P2
2
/A
2
(/D
2
)
P2
1
/A
1
(/D
1
)
P2
0
/A
0
(/D
0
)
V
SS
P1
4
/D
12
P1
3
/D
11
P1
2
/D
10
P1
1
/D
9
P1
5
/D
13
/INT3
P1
6
/D
14
/INT4
P1
7
/D
15
/INT5
P10/D8
P07/D7
P06/D6
P05/D5
P04/D4
P114
P113
P112
P111
P110
P03/D3
P02/D2
P01/D1
P00/D0
P157
P156
P155
P154
P153
P152
P151
VSS
P150
VCC
P103/AN3
P102/AN2
P101/AN1
AVSS
P100/AN0
VREF
AVCC
P107/AN7/KI3
P106/AN6/KI2
P105/AN5/KI1
P104/AN4/KI0
P97/ADTRG/RXD4
/SCL4/STxD4
7374757677798081828384858687888990919293949596979899
100101102103104105106107108
78
P57/RDY
123 4 76 8 9 101112 13141516 17181920 212223242526272829305 31 32 33 34 35 36
Note: This port is N-channel open drain output.
M30802-XXXGP

Pin Configuration

Figure 1.1.1 show the pin configurations (top view).
PIN CONFIGURATION (top view)
Package: 144P6Q-A
Figure 1.1.1. Pin configuration (top view)
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
Description
3
Block Diagram
Figure 1.1.2 is a block diagram of the M16C/80 (144-pin version) group.
Block diagram of the M30802MC-XXXGP
Figure 1.1.2. Block diagram of M30802MC-XXXGP
R0LR0H
R1H R1L
R2
AAAA
A
AAAA
A
AAAA
A
I/O ports
8888888
8
7
8
8
Internal peripheral functions
Timer
Timer TA0 (16 bits)
Timer TA1 (16 bits)
Timer TA2 (16 bits)
Timer TA3 (16 bits)
Timer TA4 (16 bits)
Timer TB0 (16 bits)
Timer TB1 (16 bits)
Timer TB2 (16 bits)
Timer TB3 (16 bits)
Timer TB4 (16 bits)
Timer TB5 (16 bits)
Watchdog timer
(15 bits)
D-A converter
(8 bits X 2 channels)
A-D converter
(10 bits X 8 channels
Expandable up to 10 channels)
UART /clock synchronous SI/O
(8 bits X 5 channels)
X-Y converter
(16 bits X 16 bits)
CRC arithmetic circuit (CCITT)
(Polynomial : X +X +X +1)
System clock generator
X
IN
- X
OUT
X
CIN
- X
COUT
Memory
DRAM
controller
M16C/80 series 16-bit CPU core
Registers
R0H R0L
R1H R1L
R2
R3
A0
A1
FB
SB
DRAM
controller
Multiplier
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Port P7
Port P8
Port P8
5
Port P9
Port P10
FLG
INTB
ISP
USP
PC
SVF
SVP
VCT
1216 5
ROM
(Note 1)
RAM
(Note 2)
Note 1: ROM size depends on MCU type.
Note 2: RAM size depends on MCU type.
Port P15
Port P14
Port P13
Port P12
Port P11
87885
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
4
Item Performance
Number of basic instructions 106 instructions
Shortest instruction execution time 50ns(f(XIN)=20MHz)
Memory See ROM expansion figure.
capacity 10 to 24 K bytes
I/O port 8 bits x 13, 7 bits x 2, 5 bits x 1
Input port 1 bit x 1
Multifunction 16 bits x 5
timer 16 bits x 6
Serial I/O (UART or clock synchronous) x 5
A-D converter 10 bits x (8 + 2) channels
D-A converter 8 bits x 2
DMAC 4 channels
DRAM controller CAS before RAS refresh, self-refresh, EDO, FP
CRC calculation circuit CRC-CCITT
X-Y converter 16 bits X 16 bits
Watchdog timer 15 bits x 1 (with prescaler)
Interrupt 29 internal and 8 external sources, 5 software sources, 7
levels
Clock generating circuit 2 built-in clock generation circuits
(built-in feedback resistance, and external ceramic or
quartz oscillator)
Supply voltage 4.2 to 5.5V (f(XIN)=20MHz) Mask ROM and flash
memory version
2.7 to 5.5V (f(XIN)=10MHz) Mask ROM and flash
memory version
Power consumption 45mA (f(XIN) = 20MHz without software wait,Vcc=5V)
Mask ROM 128 Kbytes version
I/O 5V
characteristics 5mA
Memory expansion Available (up to 16M bytes)
Operating ambient temperature –40 to 85
o
C
Device configuration CMOS high performance silicon gate
Package 144-pin plastic mold QFP
Table 1.1.1. Performance outline of M16C/80 (144-pin version) group
Performance Outline
Table 1.1.1 is a performance outline of M16C/80 (144-pin version) group.
ROM
RAM
P0 to P15 (except P85)
P85
TA0, TA1, TA2, TA3,TA4
TB0, TB1, TB2, TB3, TB4, TB5
UART0, UART1, UART2,
UART3, UART4
I/O withstand voltage
Output current
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
Description
5
Mitsubishi plans to release the following products in the M16C/80 (144-pin version) group:
(1) Support for mask ROM version, external ROM version and flash memory version
(2) ROM capacity
(3) Package
144P6Q : Plastic molded QFP (mask ROM version and flash memory version)
The M16C/80 (144-pin version) group products currently supported are listed in Table 1.1.2.
RAM capacityROM capacity Package type RemarksType No
10K bytes Mask ROM version
As of June, 2000
M30802MC-XXXGP 128K byte s
M30802FCGP
**
**
:Under development
Flash memo ry version
144P6Q-A
M30805FGGP
**
20K bytes
256K byte s
M30802SGP
10K bytes
External ROM version
20K bytesM30805MG-XXXGP 256K bytes
10K bytes128K byte s
M30805SGP
24K bytes
Table 1.1.2. M16C/80 (144-pin version) group
Figure 1.1.3. ROM expansion
ROM Size
(Byte)
External
ROM
128K
96K
64K
32K
Mask ROM version
Flash memory
version
External ROM version
80K
256K
M30802MC-XXXGP
M30802FCGP
M30805FGGP
M30802SGP
M30805MG-XXXGP
M30805SGP
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER
Description
6
Figure 1.1.4. Type No., memory size, and package
Package type:
GP : Package 144P6Q-A
ROM No.
Omitted for blank external ROM version
and flash memory version
ROM capacity:
C : 128K bytes
G : 256K bytes
Memory type:
M : Mask ROM version
S : External ROM version
F : Flash memory version
Type No. M 3 0 8 0 2 M C – X X X G P
M16C/80 Group
M16C Family
Shows RAM capacity, pin count, etc
(The value itself has no specific meaning)
Pin Description
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
7
V
CC
, V
SS
CNV
SS
X
IN
X
OUT
BYTE
AV
CC
AV
SS
V
REF
P0
0
to P0
7
D
0
to D
7
P1
0
to P1
7
D
8
to D
15
P2
0
to P2
7
A
0
to A
7
A
0
/D
0
to
A
7
/D
7
P3
0
to P3
7
A
8
to A
15
A
8
/D
8
to
A
15
/D
15
Signal name
Power supply
input
CNV
SS
Reset input
Clock input
Clock output
External data
bus width
select input
Analog power
supply input
Reference
voltage input
I/O port P0
I/O port P1
I/O port P2
I/O port P3
Supply 4.2 to 5.5 V to the V
CC
pin. Supply 0 V to the V
SS
pin.
Function
This pin switches between processor modes. Connect it to the V
SS
when operating in single-chip or memory expansion mode after reset.
Connect it to the V
CC
when in microprocessor mode after reset.
A “L” on this input resets the microcomputer.
These pins are provided for the main clock generating circuit. Connect
a ceramic resonator or crystal between the X
IN
and the X
OUT
pins. To
use an externally derived clock, input it to the X
IN
pin and leave the
X
OUT
pin open.
This pin selects the width of an external data bus. A 16-bit width is
selected when this input is “L”; an 8-bit width is selected when this
input is “H”. This input must be fixed to either “H” or “L”. When
not using the external bus,connect this pin to V
SS
.
This pin is a power supply input for the A-D converter. Connect this
pin to V
CC
.
This pin is a power supply input for the A-D converter. Connect this
pin to V
SS
.
This pin is a reference voltage input for the A-D converter.
This is an 8-bit CMOS I/O port. It has an input/output port direction
register that allows the user to set each pin for input or output
individually. When set for input in single chip mode, the user can
specify in units of four bits via software whether or not they are tied to a
pull-up resistance. In memory expansion and microprocessor mode,
an built-in pull-up resistance cannot be used. However, it is possible to
select pull-up resistance presence to the usable port as I/O port by
setting.
When set as a separate bus, these pins input and output data (D
0
–D
7
).
This is an 8-bit I/O port equivalent to P0. P1
5
to P1
7
also function as
external interrupt pins as selected by software.
When set as a separate bus, these pins input and output data
(D
8
–D
15
).
This is an 8-bit I/O port equivalent to P0.
These pins output 8 low-order address bits (A
0
–A
7
).
If a multiplexed bus is set, these pins input and output data (D
0
–D
7
) and
output 8 low-order address bits (A
0
–A
7
) separated in time by
multiplexing.
This is an 8-bit I/O port equivalent to P0.
These pins output 8 middle-order address bits (A
8
–A
15
).
If the external bus is set as a 16-bit wide multiplexed bus, these pins
input and output data (D
8
–D
15
) and output 8 middle-order address bits
(A
8
–A
15
) separated in time by multiplexing.
Pin name
Input
Input
Input
Output
Input
Input
Input/output
Input/output
Input/output
Input/output
I/O type
Analog power
supply input
Input/output
Output
Input/output
Input/output
Output
Input/output
RESET
MA0 to MA7
If accessing to DRAM area, these pins output row address and column
address separated in time by multiplexing.
Output
Pin Description
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
Pin Description
8
Pin Description
Signal name FunctionPin name I/O type
I/O port P5 Input/output
Input/output
Input/output
Input/output
Input/output
Input/output
Input
Input/output
Input/output
I/O port P6
I/O port P7
I/O port P8
I/O port P8
5
I/O port P9
I/O port P10
P5
0
to P5
7
P6
0
to P6
7
P7
0
to P7
7
P8
0
to P8
4
,
P8
6
,
P8
7
,
P8
5
P9
0
to P9
7
P10
0
to P10
7
This is an 8-bit I/O port equivalent to P0. P5
3
in this port outputs a
divide-by-8 or divide-by-32 clock of X
IN
or a clock of the same
frequency as X
CIN
as selected by software.
Output
Output
Output
Output
Output
Input
Output
Input
This is an 8-bit I/O port equivalent to P0. When set for input in single
chip mode, the user can specify in units of four bits via software
whether or not they are tied to a pull-up resistance. In memory
expansion and microprocessor mode, an built-in pull-up resistance
cannot be used. Pins in this port also function as UART0 and UART1 I/
O pins as selected by software.
This is an 8-bit I/O port equivalent to P6 (P7
0
and P7
1
are N-channel
open drain output). Pins in this port also function as timer A
0
–A
3
,
timer B5 or UART2 I/O pins as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as UART3 and UART4 I/O pins, Timer B0–B4 input pins, D-A converter
output pins, A-D converter extended input pins, or A-D trigger input pins
as selected by software.
This is an 8-bit I/O port equivalent to P6. Pins in this port also function
as A-D converter input pins. Furthermore, P10
4
–P10
7
also function as
input pins for the key input interrupt function.
WRL / WR,
WRH / BHE,
RD,
BCLK,
HLDA,
HOLD,
ALE,
RDY
Output WRL, WRH (WR and BHE), RD, BCLK, HLDA, and ALE
signals. WRL and WRH, and BHE and WR can be switched using
software control.
WRL, WRH, and RD selected
With a 16-bit external data bus, data is written to even addresses
when the WRL signal is “L” and to the odd addresses when the WRH
signal is “L”. Data is read when RD is “L”.
WR, BHE, and RD selected
Data is written when WR is “L”. Data is read when RD is “L”. Odd
addresses are accessed when BHE is “L”. Use this mode when using
an 8-bit external data bus.
While the input level at the HOLD pin is “L”, the microcomputer is
placed in the hold state. While in the hold state, HLDA outputs a “L”
level. ALE is used to latch the address. While the input level of the
RDY pin is “L”, the microcomputer is in the ready state.
P8
0
to P8
4
, P8
6
, and P8
7
are I/O ports with the same functions as P6.
Using software, they can be made to function as the I/O pins for timer
A4 and the input pins for external interrupts. P8
6
and P8
7
can be set
using software to function as the I/O pins for a sub clock generation
circuit. In this case, connect a quartz oscillator between P8
6
(X
COUT
pin) and P8
7
(X
CIN
pin). P8
5
is an input-only port that also functions
for NMI. The NMI interrupt is generated when the input at this pin
changes from “H” to “L”. The NMI function cannot be canceled using
software. The pull-up cannot be set for this pin.
DW,
CASL,
CASH,
RAS
Output
Output
Output
Output
When accessing to DRAM area while DW signal is “L”, write to DRAM.
CASL and CASH show timing when latching to line address. When
CASL accesses to even address, and CASH to odd, these two pins
become “L”. RAS signal shows timing when latching to row address.
P4
0
to P4
7
I/O port P4 This is an 8-bit I/O port equivalent to P0.Input/output
Output
Output
CS
0
to CS
3
These pins output CS
0
–CS
3
signals. CS
0
–CS
3
are chip select signals
used to specify an access space.
A
16
to A
22
,
A
23
Output
These pins output 8 high-order address bits (A
16
–A
22
, A
23
). Highest
address bit (A
23
) outputs inversely.
MA8 to MA12
If accessing to DRAM area, these pins output data separated in time by
multiplexing.
Pin Description
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
9
Signal name FunctionPin name I/O type
Input/outputI/O port P11P11
0
to P11
4
This is an 5-bit I/O port equivalent to P6.
Input/outputI/O port P12P12
0
to P12
7
This is an 8-bit I/O port equivalent to P6.
Input/outputI/O port P13P13
0
to P13
7
This is an 8-bit I/O port equivalent to P6.
Input/outputI/O port P14P14
0
to P14
6
This is an 7-bit I/O port equivalent to P6.
Input/outputI/O port P15P15
0
to P15
7
This is an 8-bit I/O port equivalent to P6.
Pin Description
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group

Memory

10

Operation of Functional Blocks

The M16C/80 group accommodates certain units in a single chip. These units include ROM and RAM to
store instructions and data and the central processing unit (CPU) to execute arithmetic/logic operations.
Also included are peripheral units such as timers, serial I/O, D-A converter, DMAC, CRC calculation circuit,
A-D converter, DRAM controller and I/O ports.
The following explains each unit.
Memory
Figure 1.2.1 is a memory map of the M16C/80 group. The address space extends the 16 Mbytes from
address 00000016 to FFFFFF16. From FFFFFF16 down is ROM. For example, in the M30802MC-XXXGP,
there is 128K bytes of internal ROM from FE000016 to FFFFFF16. The vector table for fixed interrupts such
_______
as the reset and NMI are mapped to FFFFDC16 to FFFFFF16. The starting address of the interrupt routine
is stored here. The address of the vector table for timer interrupts, etc., can be set as desired using the
internal register (INTB). See the section on interrupts for details.
From 00040016 up is RAM. For example, in the M30802MC-XXXGP, 10 Kbytes of internal RAM is mapped
to the space from 00040016 to 002BFF16. In addition to storing data, the RAM also stores the stack used
when calling subroutines and when interrupts are generated.
The SFR area is mapped to 00000016 to 0003FF16. This area accommodates the control registers for
peripheral devices such as I/O ports, A-D converter, serial I/O, and timers, etc. Figure 1.5.1 to 1.5.4 are
location of peripheral unit control registers. Any part of the SFR area that is not occupied is reserved and
cannot be used for other purposes.
The special page vector table is mapped to FFFE0016 to FFFFDB16. If the starting addresses of subrou-
tines or the destination addresses of jumps are stored here, subroutine call instructions and jump instruc-
tions can be used as 2-byte instructions, reducing the number of program steps.
In memory expansion mode and microprocessor mode, a part of the spaces are reserved and cannot be
used. For example, in the M30802MC-XXXGP, the following spaces cannot be used.
• The space between 002C0016 and 00800016 (Memory expansion and microprocessor modes)
• The space between F0000016 and FDFFFF16 (Memory expansion mode)
Figure 1.2.1. Memory map
000000
16
YYYYYY
16
FFFFFF
16
000400
16
008000
16
XXXXXX
16
F00000
16
AAA
A
AAA
A
External area
Internal ROM
area
SFR area
For details, see
Figures 1.5.1 to
1.5.4
Internal RAM
area
Internal reserved
area (Note 1)
Internal reserved
area (Note 2)
FFFE00
16
FFFFDC
16
FFFFFF
16
Note 1: During memory expansion and microprocessor modes, can not be used.
Note 2: In memory expansion mode, can not be used.
Undefined instruction
Overflow
BRK instruction
Address match
Watchdog timer
Reset
Special page
vector table
NMI
Address
XXXXX
16
FE0000
16
002BFF
16
M30802MC/FC
Type No.
Address
YYYYY
16
FC0000
16
0053FF
16
M30805MG/FG
002BFF
16
M30802S
0063FF
16
M30805S
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
CPU
11

Central Processing Unit (CPU)

The CPU has a total of 28 registers shown in Figure 1.3.1. Seven of these registers (R0, R1, R2, R3, A0,
A1, SB and FB) come in two sets; therefore, these have two register banks.
Figure 1.3.1. Central processing unit register
b23
b7 b0
Flag register
Address register (Note)
Static base register (Note)
Frame base register (Note)
User stack pointer
Interrupt stack pointer
Interrupt table register
Flag save register
PC save register
Vector register
DMA mode register
DMA transfer count register
DMA transfer count reload register
DMA memory address register
DMA SFR address register
DMA memory address reload register
b15 b0
b15 b0
b23
b15
b23
Data register (Note)
FLG
R0H
R1H
R2
R3
A0
A1
SB
FB
USP
ISP
INTB
PC
SVF
VCT
DMD0
DMD1
DCT0
DCT1
DRC0
DRC1
DMA0
DMA1
DSA0
DSA1
DRA0
DRA1
SVP
DMAC related register
Program counter
R2
R3
High-speed interrupt register
General register
b31
R0L
R1L
Note: These registers have two register banks.
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
CPU
12
(1) Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, R3, R2R0 and R3R1)
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). Registers R2 and R0, as well as R3 and R1 can use as 32-bit data
registers (R2R0/R3R1).
(2) Address registers (A0 and A1)
Address registers (A0 and A1) are configured with 24 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address register
relative addressing.
(3) Static base register (SB)
Static base register (SB) is configured with 24 bits, and is used for SB relative addressing.
(4) Frame base register (FB)
Frame base register (FB) is configured with 24 bits, and is used for FB relative addressing.
(5) Program counter (PC)
Program counter (PC) is configured with 24 bits, indicating the address of an instruction to be executed.
(6) Interrupt table register (INTB)
Interrupt table register (INTB) is configured with 24 bits, indicating the start address of an interrupt vector
table.
(7) User stack pointer (USP), interrupt stack pointer (ISP)
Stack pointer comes in two types: user stack pointer (USP) and interrupt stack pointer (ISP), each config-
ured with 24 bits.
Your desired type of stack pointer (USP or ISP) can be selected by a stack pointer select flag (U flag).
This flag is located at the position of bit 7 in the flag register (FLG).
Set USP and ISP to an even number so that execution efficiency is increased.
(8) Save flag register (SVF)
This register consists of 16 bits and is used to save the flag register when a high-speed interrupt is
generated.
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
CPU
13
(9) Save PC register (SVP)
This register consists of 24 bits and is used to save the program counter when a high-speed interrupt is
generated.
(10) Vector register (VCT)
This register consists of 24 bits and is used to indicate the jump address when a high-speed interrupt is
generated.
(11) DMA mode registers (DMD0/DMD1)
These registers consist of 8 bits and are used to set the transfer mode, etc. for DMA.
(12) DMA transfer count registers (DCT0/DCT1)
These registers consist of 16 bits and are used to set the number of DMA transfers performed.
(13) DMA transfer count reload registers (DRC0/DRC1)
These registers consist of 16 bits and are used to reload the DMA transfer count registers.
(14) DMA memory address registers (DMA0/DMA1)
These registers consist of 24 bits and are used to set a memory address at the source or destination of
DMA transfer.
(15) DMA SFR address registers (DSA0/DSA1)
These registers consist of 24 bits and are used to set a fixed address at the source or destination of DMA
transfer.
(16) DMA memory address reload registers (DRA0/DRA1)
These registers consist of 24 bits and are used to reload the DMA memory address registers.
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
CPU
14
(17) Flag register (FLG)
Flag register (FLG) is configured with 11 bits, each bit is used as a flag. Figure 1.3.2 shows the flag
register (FLG). The following explains the function of each flag:
• Bit 0: Carry flag (C flag)
This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.
• Bit 1: Debug flag (D flag)
This flag enables a single-step interrupt.
When this flag is “1”, a single-step interrupt is generated after instruction execution. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 2: Zero flag (Z flag)
This flag is set to “1” when an arithmetic operation resulted in 0; otherwise, cleared to “0”.
• Bit 3: Sign flag (S flag)
This flag is set to “1” when an arithmetic operation resulted in a negative value; otherwise, cleared
to “0”.
• Bit 4: Register bank select flag (B flag)
This flag chooses a register bank. Register bank 0 is selected when this flag is “0” ; register bank
1 is selected when this flag is “1”.
• Bit 5: Overflow flag (O flag)
This flag is set to “1” when an arithmetic operation resulted in overflow; otherwise, cleared to “0”.
• Bit 6: Interrupt enable flag (I flag)
This flag enables a maskable interrupt.
An interrupt is disabled when this flag is “0”, and is enabled when this flag is “1”. This flag is
cleared to “0” when the interrupt is acknowledged.
• Bit 7: Stack pointer select flag (U flag)
Interrupt stack pointer (ISP) is selected when this flag is “0” ; user stack pointer (USP) is selected
when this flag is “1”.
This flag is cleared to “0” when a hardware interrupt is acknowledged or an INT instruction of
software interrupt Nos. 0 to 31 is executed.
• Bits 8 to 11: Reserved area
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
CPU
15
Figure 1.3.2. Flag register (FLG)
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
Flag register (FLG)
CDZSBOIU
IPL
b0b15
• Bits 12 to 14: Processor interrupt priority level (IPL)
Processor interrupt priority level (IPL) is configured with three bits, for specification of up to eight
processor interrupt priority levels from level 0 to level 7.
If a requested interrupt has priority greater than the processor interrupt priority level (IPL), the interrupt
is enabled.
• Bit 15: Reserved area
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group

Reset

16
Figure 1.4.2. Reset sequence
Reset
There are two kinds of resets; hardware and software. In both cases, operation is the same after the reset.
(See “Software Reset” for details of software resets.) This section explains on hardware resets.
When the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the
reset pin level “L” (0.2VCC max.) for at least 20 cycles. When the reset pin level is then returned to the “H”
level while main clock is stable, the reset status is cancelled and program execution resumes from the
address in the reset vector table.
Figure 1.4.1 shows the example reset circuit. Figure 1.4.2 shows the reset sequence.
Figure 1.4.1. Example reset circuit
BCLK
Address
Address
Address
Microprocessor
mode BYTE = “H”
Microprocessor
mode BYTE = “L”
Content of reset vector
Single chip
mode
BCLK 24cycles
FFFFC
16
FFFFD
16
FFFFE
16
Content of reset vector
FFFFC
16
FFFFE
16
Content of reset vector
FFFFE
16
X
IN
RESET
RD
WR
CS0
RD
WR
CS0
FFFFC
16
More than 20 cycles are needed
RESET
V
CC
0.8V
RESET
V
CC
0V
0V
5V
5V
4.2V
Example when f(X
IN
) = 10MHz and V
CC
= 5V
.
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
Reset
17
____________
Table 1.4.1 shows the statuses of the other pins while the RESET pin level is “L”. Figures 1.4.3 and 1.4.4
show the internal status of the microcomputer immediately after the reset is cancelled.
____________
Table 1.4.1. Pin status when RESET pin level is “L”
Status
CNV
SS
= V
CC
CNV
SS
= V
SS
BYTE = V
SS
BYTE = V
CC
Pin name
P0
P1
P2, P3, P4
P5
0
P5
1
P5
2
P5
3
P5
4
P5
5
P5
6
P5
7
P6, P7, P8
0
to P8
4
,
P8
6
, P8
7
, P9, P10,
P11, P12, P13,
P14, P15
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Input port (floating)
Data input (floating)
Data input (floating)
Address output (undefined)
BCLK output
RAS output
WR output (“H” level is output)
RD output (“H” level is output)
RDY input (floating)
Input port (floating)
BCLK output
BHE output (undefined)
HLDA output (The output value
depends on the input to the
HOLD pin)
HOLD input (floating)
Data input (floating)
Address output (undefined)
Input port (floating) Input port (floating)
RDY input (floating)
RAS output
HOLD input (floating)
HLDA output (The output value
depends on the input to the
HOLD pin)
RD output (“H” level is output)
BHE output (undefined)
WR output (“H” level is output)
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
Reset
18
Figure 1.4.3. Device's internal status after a reset is cleared
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Note: When the V
CC
level is applied to the CNV
SS
pin, it is 03
16
at a reset.
(1) (0004
16
)···Processor mode register 0 (Note) 80
16
(2) (0005
16
)···Processor mode register 1
(3) (0006
16
)···System clock control register 0
(4) (0007
16
)···System clock control register 1
(5) (0008
16
)···Wait control register
(6) (0009
16
)···
Address match interrupt
enable register
00
(7) Protect register (000A
16
)···
000
(10)
(000F
16
)···Watchdog timer control
register
00?0????
(12)
(0014
16
)···Address match interrupt register 1
(0018
16
)···
00
16
00
16
(0040
16
)···DMAM control register ?????
DMA0 interrupt control register
(21)
(006B
16
)···
UART0 receive interrupt control
register
? 0 0 0
(22)
(006C
16
)···
? 0 0 0
(23)
(006D
16
)···
Key input interrupt control register
? 0 0 0
(20)
(006A
16
)···
Bus collision detection(UART3)
interrupt control register
0 0 0?
(8)
External data bus width control
register
(000B
16
)···
(0010
16
)···Address match interrupt register 0
(0011
16
)···
(0012
16
)···
00
16
00
16
(11)
Timer B2 interrupt control register
(15)
DMA2 interrupt control register
?000
(16)
UART2 receive/ACK interrupt control
register
?000
(17)
Timer A0 interrupt control register
?000
(18)
(0068
16
)···
UART3 receive/ACK interrupt control
register
(19)
(0069
16
)···
(24)
A-D conversion interrupt
control register
(25)
(26)
(0073
16
)··· ? 0 0 0
(0074
16
)···
(0076
16
)···
? 0 0 0
? 0 0 0
00
16
(27)
(28)
(29)
(30)
UART1 transmit interrupt control register
(31)
(32)
(33)
(34)
(35)
(36)
(37)
Timer B0 interrupt control register
Timer B2 interrupt control register
(38)
Timer B3 interrupt control register
(39)
INT5 interrupt control register
(40)
INT3 interrupt control register
(41)
INT1 interrupt control register
(45)
Three-phase output buffer register 0
(46)
Three-phase output buffer register 1
Three-phase PWM control register 0
(43)
Three-phase PWM control register 1
(44)
(42)
Timer B3,4,5 count start flag
(47)
Timer B3 mode register
(48)
Timer B4 mode register
(49)
Timer B5 mode register
(50)
UART4 transmit/receive control register 1
UART4 transmit/receive control register 0
(56)
UART4 transmit/receive mode register
(54)
(55)
(52)
(53)
UART4 special mode register 2
(51)
00
(9)
(000C
16
)···Main clock divided register
08
16
(13)
Address match interrupt register 2
(14)
Address match interrupt register 3
(0015
16
)··· 00
16
(0016
16
)··· 00
16
(0019
16
)··· 00
16
(001A
16
)··· 00
16
(001C
16
)··· 00
16
(001D
16
)··· 00
16
(001E
16
)··· 00
16
Timer A2 interrupt control register
UART4 receive/ACK interrupt control
register
Timer A4 interrupt control register
UART1 receive interrupt control
register
Timer B1 interrupt control register
Bus collision detection(UART2)
interrupt control register
DMA1 interrupt control register
UART2 transmit/NACK interrupt
control register
UART3 transmit/NACK interrupt
control register
Timer A1 interrupt control register
UART4 receive/NACK interrupt
control register
Timer A3 interrupt control register
DMA3 interrupt control register
Bus collision detection(UART4)
interrupt control register
UART0 transmit interrupt control register
INT4 interrupt control register
INT2 interrupt control register
INT0 interrupt control register
Exit priority register
XY control register
UART4 special mode register
Timer B4 interrupt control register
(006E
16
)···
(006F
16
)···
(0070
16
)···
(0071
16
)···
(0072
16
)···
000
20
16
FF
16
000
01
00
16
?000
?000
?000
?000
(0078
16
)···
(007A
16
)···
(007C
16
)···
(007E
16
)···
? 0 0 0
? 000
? 000
? 000
(0088
16
)···
(0089
16
)···
(008A
16
)···
(008B
16
)···
(008E
16
)···
(008F
16
)···
(0090
16
)···
(0091
16
)···
(0092
16
)···
? 0 0 0
? 0 0 0
? 0 0 0
? 0 0 0
(008C
16
)··· ? 0 0 0
(008D
16
)··· ? 0 0 0
? 0 0 0
? 0 0 0
? 000
? 000
? 000
00? 0000
00? 0000
(0309
16
)···
(030A
16
)··· 00
16
(030B
16
)···
00
16
(0308
16
)··· 00
16
(0300
16
)···
(031B
16
)···
(031C
16
)···
00? 0000
(031D
16
)···
00
00
00
(0093
16
)···
(0094
16
)···
(0096
16
)···
(009C
16
)···
(009E
16
)···
(009F
16
)···
(02E0
16
)···
(02F6
16
)···
? 0 0 0
? 0 0 0
? 0 0 0
(0098
16
)··· ? 0 0 0
(009A
16
)··· ? 000
? 000
? 000
0 000
00
00
00
00
00
16
(02F7
16
)···
00
16
(02F8
16
)···
00
16
(02FC
16
)···
08
16
(02FD
16
)···
02
16
?
(62)
(63)
(60)
(59)
(61)
(64)
(65)
(66)
(57)
(58)
UART4 special mode register 3
(02F5
16
)···
00
16
(67)
000 ?0000
000
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
Reset
19
Figure 1.4.4. Device's internal status after a reset is cleared
Trigger select flag
Up-down flag
Timer A0 mode register
Timer A1 mode register
Timer A2 mode register
Timer B0 mode register
Timer B1 mode register
Timer B2 mode register
Timer A3 mode register
Timer A4 mode register
One-shot start flag
UART1 transmit/receive control register 0
UART1 transmit/receive control register 1
UART transmit/receive control register 2
DMA0 cause select register
DMA1 cause select register
UART0 transmit/receive mode register
UART0 transmit/receive control register 0
UART0 transmit/receive control register 1
UART1 transmit/receive mode register
A-D control register 2
A-D control register 0
A-D control register 1
Count start flag
Clock prescaler reset flag
x : Nothing is mapped to this bit
? : Undefined
The content of other registers and RAM is undefined when the microcomputer is reset. The initial values
must therefore be set.
Port P0 direction register
Port P1 direction register
Port P2 direction register
Port P3 direction register
Port P4 direction register
Port P5 direction register
Port P6 direction register
Port P7 direction register
Port P8 direction register
Port P9 direction register
Port P10 direction register
Pull-up control register 0
Pull-up control register 1
Pull-up control register 2
Port control register
Frame base register (FB)
Address registers (A0/A1)
Interrupt table register (INTB)
User stack pointer (USP)
Interrupt stack pointer (ISP)
Static base register (SB)
Flag register (FLG)
Data registers (R0/R1/R2/R3)
(78)
(77)
(79)
(80)
(83)
(84)
(85)
(86)
(82)
(76)
(81)
(90)
(91)
(92)
(93)
(94)
(95)
(87)
(88)
(89)
(96)
(74)
(73)
(71)
(72)
(68)
(69)
(70)
(75)
(97)
(99)
(98)
(103)
(104)
(105)
(102)
(101)
(100)
(114)
(115)
(116)
(117)
(118)
(119)
(120)
(121)
(122)
(123)
(124)
(125)
(126)
(127)
(132)
(130)
(131)
(128)
(129)
(132)
(136)
(137)
(138)
(133)
(135)
(142)
(143)
(139)
(141)
(140)
(109)
(110)
(111)
(112)
(113)
(106)
(107)
(033D
16
)···
(0340
16
)···
(0341
16
)···
(0342
16
)···
(0357
16
)···
(0358
16
)···
(0359
16
)···
(0344
16
)···
(0356
16
)···
(033C
16
)···
02
16
00
16
00
16
(0343
16
)··· 00
16
00
16
(035D
16
)···
(0360
16
)···
(0364
16
)···
(0365
16
)···
(0368
16
)···
(036C
16
)···
(035A
16
)···
(035B
16
)··· 00? 0000?
(035C
16
)··· 00? 0000
00
16
08
16
02
16
(036D
16
)···
0010000
(0337
16
)··· 00
16
(032C
16
)···
(0336
16
)···
(032D
16
)···
(0325
16
)···
(0327
16
)···
(0328
16
)···
08
16
00
16
00
16
00
16
(031F
16
)···
000000
02
16
00
16
(0338
16
)··· 00
16
0
000 0?000
000 0?000
000 0?000
000 0?000
000 0?000
00? 0000
00
16
08
16
02
16
(0370
16
)··· 00 00000
0000000
000000
(0379
16
)···
(0378
16
)··· 0
00000
(0396
16
)···
(0397
16
)··· 00
16
(108)
D-A control register
(039C
16
)··· 00
16
00000
(0394
16
)···
???
0000000
000000
(037B
16
)···
(037A
16
)··· 0
00
16
00000
(03C2
16
)···
(03C3
16
)···
(03C6
16
)···
(03C7
16
)···
(03CA
16
)···
(03DA
16
)···
(03DB
16
)···
(03E2
16
)···
(03E3
16
)···
(03E6
16
)···
(03E7
16
)···
(03EA
16
)···
(03EB
16
)···
(03F0
16
)···
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
00
16
0000
16
000000
16
000000
16
(03F1
16
)··· X0
16
0
(03FF
16
)···
000000
16
000000
16
000000
16
0000
16
00
16
000000
16
??
??
??
??
??
0
0000000
0
0000
0
0
(03AF
16
)···
(03B0
16
)···
(03B2
16
)···
(03B3
16
)···
(03B4
16
)···
(03B5
16
)···
(03B6
16
)···
00
16
0
000000
(03B1
16
)···
0
00 0
00
0
Interrupt cause select register
UART3 transmit/receive control register 1
UART3 transmit/receive control register 0
UART3 transmit/receive mode register
UART3 special mode register 3
UART3 special mode register
UART2 transmit/receive control register 1
UART2 transmit/receive control register 0
UART2 transmit/receive mode register
UART2 special mode register 2
UART2 special mode register
DMA2 cause select register
DMA3 cause select register
Pull-up control register 3
DMA mode register (DMD0/DMD1)
DMA transfer count register (DCT0/DCT1)
DMA transfer count reload register
(DRC0/DRC1)
DMA memory address register (DMA0/DMA1)
DMA SFR address register (DSA0/DSA1)
DMA memory address reload register
(DRA0/DRA1)
Function select register C
Function select register A0
Function select register B0
Function select register A1
Function select register A2
Function select register A3
Function select register B1
Function select register B2
(0326
16
)···
00
16
UART3 special mode register 2
(0335
16
)···
UART2 special mode register 3
(03B7
16
)···
Function select register B3
0 00
?000??0?
(146)
(147)
(145)
(144)
Port P11 direction register
(03CB
16
)···
Port P12 direction register
(03CE
16
)··· 00
16
Port P13 direction register
(03CF
16
)··· 00
16
Port P14 direction register
(03D2
16
)···
Port P15 direction register
(03D3
16
)···
00
16
00000
00
00000
00
(03DC
16
)··· 00
16
Pull-up control register 4
(148)
(152)
(153)
(149)
(151)
(150)
(0377
16
)···Flash memory control register 0
(Note)
?
000010
(102)
(101)
0?????(0376
16
)···Flash memory control register 1
(Note)
?
Note :This register exists in the flash memory version.
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SFR
20
Figure 1.5.1. Location of peripheral unit control registers (1)
0000
16
0001
16
0002
16
0003
16
0004
16
0005
16
0006
16
0007
16
0008
16
0009
16
000A
16
000B
16
000C
16
000D
16
000E
16
000F
16
0010
16
0011
16
0012
16
0013
16
0014
16
0015
16
0016
16
0017
16
0018
16
0019
16
001A
16
001B
16
001C
16
001D
16
001E
16
001F
16
0020
16
0021
16
0022
16
0023
16
0024
16
0025
16
0026
16
0027
16
0028
16
0029
16
002A
16
002B
16
002C
16
002D
16
002E
16
002F
16
0030
16
0031
16
0032
16
0033
16
0034
16
0035
16
0036
16
0037
16
0038
16
0039
16
003A
16
003B
16
003C
16
003D
16
003E
16
003F
16
0040
16
0041
16
0042
16
0043
16
0044
16
0060
16
0061
16
0062
16
0063
16
0064
16
0065
16
0066
16
0067
16
0068
16
0069
16
006A
16
006B
16
006C
16
006D
16
006E
16
006F
16
0070
16
0071
16
0072
16
0073
16
0074
16
0075
16
0076
16
0077
16
0078
16
0079
16
007A
16
007B
16
007C
16
007D
16
007E
16
007F
16
0080
16
0081
16
0082
16
0083
16
0084
16
0085
16
0086
16
0087
16
0088
16
0089
16
008A
16
008B
16
008C
16
008D
16
008E
16
008F
16
0090
16
0091
16
0092
16
0093
16
0094
16
0095
16
0096
16
0097
16
0098
16
0099
16
009A
16
009B
16
009C
16
009D
16
009E
16
009F
16
00A0
16
00A1
16
00A2
16
00A3
16
00A4
16
Watchdog timer start register (WDTS)
Watchdog timer control register (WDC)
Processor mode register 0 (PM0)
Address match interrupt register 0 (RMAD0)
Address match interrupt register 1 (RMAD1)
Wait control register (WCR)
System clock control register 0 (CM0)
System clock control register 1 (CM1)
Address match interrupt enable register (AIER)
Protect register (PRCR)
Processor mode register 1(PM1)
External data bus widthcontrol register (DS)
Main clock division register (MCD)
Address match interrupt register 2 (RMAD2)
Address match interrupt register 3 (RMAD3)
Emulator interrupt vector table register (EIAD)
Emulator interrupt detect register (EITD)
Emulator protect register (EPRR)
ROM areaset register (ROA)
Debug monitor area set register (DBA)
Expansion area set register 0 (EXA0)
Expansion area set register 1 (EXA1)
Expansion area set register 2 (EXA2)
Expansion area set register 3 (EXA3)
DRAM control register (DRAMCONT)
DRAM reflesh interval set register (REFCNT)
Timer A1 interrupt control register (TA1IC)
UART0 transmit interrupt control register (S0TIC)
Timer A0 interrupt control register (TA0IC)
Timer A2 interrupt control register (TA2IC)
UART0 receive interrupt control register (S0RIC)
UART2 transmit/NACK interrupt control register (S2TIC)
UART1 receive interrupt control register (S1RIC)
DMA2 interrupt control register (DM1IC)
DMA0 interrupt control register (DM0IC)
Key input interrupt control register (KUPIC)
A-D conversion interrupt control register (ADIC)
Bus collision detection(UART3) interrupt control register (BCN3IC)
UART2 receive/ACK interrupt control register (S2RIC)
INT1 interrupt control register (INT1IC)
Timer B0 interrupt control register (TB0IC)
Timer B2 interrupt control register (TB2IC)
Timer A3 interrupt control register (TA3IC)
INT2 interrupt control register (INT2IC)
INT0 interrupt control register (INT0IC)
Timer B1 interrupt control register (TB1IC)
Timer A4 interrupt control register (TA4IC)
INT3 interrupt control register (INT3IC)
Timer B5 interrupt control register (TB5IC)
Timer B4 interrupt control register (TB4IC)
Timer B3 interrupt control register (TB3IC)
INT5 interrupt control register (INT5IC)
INT4 interrupt control register (INT4IC)
UART3 receive/ACK interrupt control register (S3RIC)
UART4 receive/ACK interrupt control register (S4RIC)
UART3 transmit/NACK interrupt control register (S3TIC)
UART4 transmit/NACK interrupt control register (S4TIC)
Exit priority register (RLVL)
UART1 transmit interrupt control register (S1TIC)
DMA1 interrupt control register (DM1IC)
DMA3 interrupt control register (DM3IC)
Bus collision detection(UART2) interrupt control register (BCN2IC)
Bus collision detection(UART4) interrupt control register (BCN4IC)
*
*
*
*
*
*
*
*
*
*
As this register is used exclusively for debugger purposes, user cannot use this. Do not access to the register.
(The blank area is reserved and cannot be used by user.)
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SFR
21
Figure 1.5.2. Location of peripheral unit control registers (2)
0300
16
0301
16
0302
16
0303
16
0304
16
0305
16
0306
16
0307
16
0308
16
0309
16
030A
16
030B
16
030C
16
030D
16
030E
16
030F
16
0310
16
0311
16
0312
16
0313
16
0314
16
0315
16
0316
16
0317
16
0318
16
0319
16
031A
16
031B
16
031C
16
031D
16
031E
16
031F
16
0320
16
0321
16
0322
16
0323
16
0324
16
0325
16
0326
16
0327
16
0328
16
0329
16
032A
16
032B
16
032C
16
032D
16
032E
16
032F
16
0330
16
0331
16
0332
16
0333
16
0334
16
0335
16
0336
16
0337
16
0338
16
0339
16
033A
16
033B
16
033C
16
033D
16
033E
16
033F
16
02C0
16
02C1
16
02C2
16
02C3
16
02C4
16
02C5
16
02C6
16
02C7
16
02C8
16
02C9
16
02CA
16
02CB
16
02CC
16
02CD
16
02CE
16
02CF
16
02D0
16
02D1
16
02D2
16
02D3
16
02D4
16
02D5
16
02D6
16
02D7
16
02D8
16
02D9
16
02DA
16
02DB
16
02DC
16
02DD
16
02DE
16
02DF
16
02E0
16
02E1
16
02E2
16
02E3
16
02E4
16
02E5
16
02E6
16
02E7
16
02E8
16
02E9
16
02EA
16
02EB
16
02EC
16
02ED
16
02EE
16
02EF
16
02F0
16
02F1
16
02F2
16
02F3
16
02F4
16
02F5
16
02F6
16
02F7
16
02F8
16
02F9
16
02FA
16
02FB
16
02FC
16
02FD
16
02FE
16
02FF
16
X0 register (X0R) Y0 register (Y0R)
X1 register (X1R) Y1 register (Y1R)
X2 register (X2R) Y2 register (Y2R)
X3 register (X3R) Y3 register (Y3R)
X4 register (X4R) Y4 register (Y4R)
X5 register (X5R) Y5 register (Y5R)
X6 register (X6R) Y6 register (Y6R)
X7 register (X7R) Y7 register (Y7R)
X8 register (X8R) Y8 register (Y8R)
X9 register (X9R) Y9 register (Y9R)
X10 register (X10R) Y10 register (Y10R)
X11 register (X11R) Y11 register (Y11R)
X12 register (X12R) Y12 register (Y12R)
X13 register (X13R) Y13 register (Y13R)
X14 register (X14R) Y14 register (Y14R)
X15 register (X15R) Y15 register (Y15R)
XY control register (XYC)
UART4 special mode register (U4SMR)
UART4 receive buffer register (U4RB)
UART4 transmit buffer register (U4TB)
UART4 transmit/receive control register 0 (U4C0)
UART4 transmit/receive mode register (U4MR)
UART4 transmit/receive control register 1 (U4C1)
UART4 bit rate generator (U4BRG)
UART4 special mode register 2 (U4SMR2)
Timer A1-1 register (TA11)
Timer A2-1 register (TA21)
Dead time timer(DTT)
Timer B2 interrupt occurrence frequency set counter(ICTB2)
Three-phase PWM control register 0(INVC0)
Three-phase PWM control register 1(INVC1)
Thrree-phase output buffer register 0(IDB0)
Thrree-phase output buffer register 1(IDB1)
Timer B3 register (TB3)
Timer B4 register (TB4)
Timer B5 register (TB5)
Timer B3, 4, 5 count start flag (TBSR)
Timer B3 mode register (TB3MR)
Timer B4 mode register (TB4MR)
Timer B5 mode register (TB5MR)
Interrupt cause select register (IFSR)
UART2 special mode register (U2SMR)
UART2 receive buffer register (U2RB)
UART2 transmit buffer register (U2TB)
UART2 transmit/receive control register 0 (U2C0)
UART2 transmit/receive mode register (U2MR)
UART2 transmit/receive control register 1 (U2C1)
UART2 bit rate generator (U2BRG)
Timer A4-1 register (TA41)
UART2 special mode register 2 (U2SMR2)
UART3 special mode register (U3SMR)
UART3 receive buffer register (U3RB)
UART3 transmit buffer register (U3TB)
UART3 transmit/receive control register 0 (U3C0)
UART3 transmit/receive mode register (U3MR)
UART3 transmit/receive control register 1 (U3C1)
UART3 bit rate generator (U3BRG)
UART3 special mode register 2 (U3SMR2)
UART4 special mode register 3 (U4SMR3) UART2 special mode register 3 (U2SMR3)
UART3 special mode register 3 (U3SMR3)
(The blank area is reserved and cannot be used by user.)
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SFR
22
Figure 1.5.3. Location of peripheral unit control registers (3)
0340
16
0341
16
0342
16
0343
16
0344
16
0345
16
0346
16
0347
16
0348
16
0349
16
034A
16
034B
16
034C
16
034D
16
034E
16
034F
16
0350
16
0351
16
0352
16
0353
16
0354
16
0355
16
0356
16
0357
16
0358
16
0359
16
035A
16
035B
16
035C
16
035D
16
035E
16
035F
16
0360
16
0361
16
0362
16
0363
16
0364
16
0365
16
0366
16
0367
16
0368
16
0369
16
036A
16
036B
16
036C
16
036D
16
036E
16
036F
16
0370
16
0371
16
0372
16
0373
16
0374
16
0375
16
0376
16
0377
16
0378
16
0379
16
037A
16
037B
16
037C
16
037D
16
037E
16
037F
16
0380
16
0381
16
0382
16
0383
16
0384
16
0385
16
0386
16
0387
16
0388
16
0389
16
038A
16
038B
16
038C
16
038D
16
038E
16
038F
16
0390
16
0391
16
0392
16
0393
16
0394
16
0395
16
0396
16
0397
16
0398
16
0399
16
039A
16
039B
16
039C
16
039D
16
039E
16
039F
16
03A0
16
03A1
16
03A2
16
03A3
16
03A4
16
03A5
16
03A6
16
03A7
16
03A8
16
03A9
16
03AA
16
03AB
16
03AC
16
03AD
16
03AE
16
03AF
16
03B0
16
03B1
16
03B2
16
03B3
16
03B4
16
03B5
16
03B6
16
03B7
16
03B8
16
03B9
16
03BA
16
03BB
16
03BC
16
03BD
16
03BE
16
03BF
16
Timer A0 register (TA0)
Timer A1 register (TA1)
Timer A2 register (TA2)
Timer B0 register (TB0)
Timer B1 register (TB1)
Timer B2 register (TB2)
Count start flag (TABSR)
One-shot start flag (ONSF)
Timer A0 mode register (TA0MR)
Timer A1 mode register (TA1MR)
Timer A2 mode register (TA2MR)
Timer B0 mode register (TB0MR)
Timer B1 mode register (TB1MR)
Timer B2 mode register (TB2MR)
Up-down flag (UDF)
Timer A3 register (TA3)
Timer A4 register (TA4)
Timer A3 mode register (TA3MR)
Timer A4 mode register (TA4MR)
Trigger select register (TRGSR)
Clock prescaler reset flag (CPSRF)
UART0 transmit/receive mode register (U0MR)
UART0 transmit buffer register (U0TB)
UART0 receive buffer register (U0RB)
UART1 transmit/receive mode register (U1MR)
UART1 transmit buffer register (U1TB)
UART1 receive buffer register (U1RB)
UART0 bit rate generator (U0BRG)
UART0 transmit/receive control register 0 (U0C0)
UART0 transmit/receive control register 1 (U0C1)
UART1 bit rate generator (U1BRG)
UART1 transmit/receive control register 0 (U1C0)
UART1 transmit/receive control register 1 (U1C1)
DMA1 request cause select register (DM1SL)
DMA0 request cause select register (DM0SL)
CRC data register (CRCD)
CRC input register (CRCIN)
UART transmit/receive control register 2 (UCON2)
A-D register 7 (AD7)
A-D register 0 (AD0)
A-D register 1 (AD1)
A-D register 2 (AD2)
A-D register 3 (AD3)
A-D register 4 (AD4)
A-D register 5 (AD5)
A-D register 6 (AD6)
Function select register C(PSC)
Function select register A1 (PS1)
Function select register A0 (PS0)
Function select register B0 (PSL0)
Function select register B1 (PSL1)
Function select register A3 (PS3)
Function select register A2 (PS2)
Function select register B2 (PSL2)
A-D control register 0 (ADCON0)
A-D control register 1 (ADCON1)
D-A register 0 (DA0)
D-A register 1 (DA1)
D-A control register (DACON)
A-D control register 2 (ADCON2)
DMA3 request cause select register (DM3SL)
DMA2 request cause select register (DM2SL)
Function select register B3 (PSL3)
Flash memory control register 0 (FMR0) (Note)
Flash memory control register 1 (FMR1) (Note)
Note :This register exists in the flash memory version.
(The blank area is reserved and cannot be used by user.)
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
SFR
23
Figure 1.5.4. Location of peripheral unit control registers (4)
03C0
16
03C1
16
03C2
16
03C3
16
03C4
16
03C5
16
03C6
16
03C7
16
03C8
16
03C9
16
03CA
16
03CB
16
03CC
16
03CD
16
03CE
16
03CF
16
03D0
16
03D1
16
03D2
16
03D3
16
03D4
16
03D5
16
03D6
16
03D7
16
03D8
16
03D9
16
03DA
16
03DB
16
03DC
16
03DD
16
03DE
16
03DF
16
03E0
16
03E1
16
03E2
16
03E3
16
03E4
16
03E5
16
03E6
16
03E7
16
03E8
16
03E9
16
03EA
16
03EB
16
03EC
16
03ED
16
03EE
16
03EF
16
03F0
16
03F1
16
03F2
16
03F3
16
03F4
16
03F5
16
03F6
16
03F7
16
03F8
16
03F9
16
03FA
16
03FB
16
03FC
16
03FD
16
03FE
16
03FF
16
Port P0 (P0)
Port P0 direction register (PD0)
Port P1 (P1)
Port P1 direction register (PD1)
Port P2 (P2)
Port P2 direction register (PD2)
Port P3 (P3)
Port P3 direction register (PD3)
Port P4 (P4)
Port P4 direction register (PD4)
Port P5 (P5)
Port P5 direction register (PD5)
Port P6 (P6)
Port P6 direction register (PD6)
Port P7 (P7)
Port P7 direction register (PD7)
Port P8 (P8)
Port P8 direction register (PD8)
Port P9 (P9)
Port P9 direction register (PD9)
Port P10 (P10)
Port P10 direction register (PD10)
Pull-up control register 0 (PUR0)
Pull-up control register 1 (PUR1)
Pull-up control register 2 (PUR2)
Port control register (PCR)
Pull-up control register 3 (PUR3)
Port P11 (P11)
Port P11 direction register (PD11)
Port P12 (P12)
Port P12 direction register (PD12)
Port P13 (P13)
Port P13 direction register (PD13)
Port P14 (P14)
Port P14 direction register (PD14)
Port P15 (P15)
Port P15 direction register (PD15)
Pull-up control register 4 (PUR4)
(The blank area is reserved and cannot be used by user.)
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group

Software Reset

24
Software Reset
Writing “1” to bit 3 of the processor mode register 0 (address 000416) applies a (software) reset to the
microcomputer. A software reset has the same effect as a hardware reset. The contents of internal RAM
are preserved.

Processor Mode

(1) Types of Processor Mode
One of three processor modes can be selected: single-chip mode, memory expansion mode, and micro-
processor mode. The functions of some pins, the memory map, and the access space differ according to
the selected processor mode.
• Single-chip mode
In single-chip mode, only internal memory space (SFR, internal RAM, and internal ROM) can be
accessed. Ports P0 to P10 can be used as programmable I/O ports or as I/O ports for the internal
peripheral functions.
• Memory expansion mode
In memory expansion mode, external memory can be accessed in addition to the internal memory
space (SFR, internal RAM, and internal ROM).
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
• Microprocessor mode
In microprocessor mode, the SFR, internal RAM, and external memory space can be accessed. The
internal ROM area cannot be accessed.
In this mode, some of the pins function as the address bus, the data bus, and as control signals. The
number of pins assigned to these functions depends on the bus and register settings. (See “Bus
Settings” for details.)
(2) Setting Processor Modes
The processor mode is set using the CNVSS pin and the processor mode bits (bits 1 and 0 at address
000416). Do not set the processor mode bits to “102”.
Regardless of the level of the CNVSS pin, changing the processor mode bits selects the mode. Therefore,
never change the processor mode bits when changing the contents of other bits. Also do not attempt to
shift to or from the microprocessor mode within the program stored in the internal ROM area.
• Applying VSS to CNVSS pin
The microcomputer begins operation in single-chip mode after being reset. Memory expansion mode
is selected by writing “012” to the processor mode is selected bits.
• Applying VCC to CNVSS pin
The microcomputer starts to operate in microprocessor mode after being reset.
Figure 1.6.1 and 1.6.2 show the processor mode register 0 and 1.
Figure 1.6.3 shows the memory maps applicable for each processor modes.
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
25
Processor Mode
Figure 1.6.1. Processor mode register 0
Processor mode register 0 (Note 1)
Symbol Address When reset
PM0 0004
16
80
16
(Note 2)
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
0 0: Single-chip mode
0 1: Memory expansion mode
1 0: Inhibited
1 1: Microprocessor mode
b1 b0
PM03
PM01
PM00
Processor mode bit
PM02
R/W mode select bit
(Note 7)
0 : RD,BHE,WR
1 : RD,WRH,WRL
Software reset bit
The device is reset when this bit is set to “1”.
The value of this bit is “0” when read.
PM04
0 0 : Multiplexed bus is not used
0 1 : Allocated to CS2 space
1 0 : Allocated to CS1 space
1 1 : Allocated to entire space (Note4)
b5 b4
Multiplexed bus space
select bit (Note 3)
PM05
PM07
BCLK output disable bit
(Note 5)
0 : BCLK is output (Note 6)
1 : Function set by bit 0,1 of system
clock control register 0
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new values to this register.
Note 2: If the V
CC
voltage is applied to the CNV
SS
, the value of this register when reset is 03
16
. (PM00 is set
to “1” and PM07 is set to “0”.)
Note 3: Valid in microprocessor and memory expansion modes 1, 2 and 3. Do not use multiplex bus when
mode 0 is selected. Do not set to allocated to CS2 space when mode 2 is selected.
Note 4: After the reset has been released, the M16C/80 group MCU operates using the separate bus. As a
result, in microprocessor mode, you cannot select the full CS space multiplex bus.
When you select the full CS space multiplex bus in memory expansion mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Mode 0: Multiplexed bus cannot be used.
Mode 1: CS0 to CS2 when you select full CS space.
Mode 2: CS0 to CS1 when you select full CS space.
Mode 3: CS0 to CS3 when you select full CS space.
Note 5: No BCLK is output in single chip mode even when "0" is set in PM07. When stopping clock output in
microprocessor or memory expansion mode, make the following settings: PM07="1", bit 0 (CM00) and
bit 1 (CM01) of system clock control register 0 (address 0006
16
) = "0". "L" is now output from P5
3
.
Note 6: When selecting BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
Note 7: When using 16-bit bus width in DRAM controler, set this bit to "1".
WR
Reserved bit
Must always be set to “0”
0
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
26
Processor Mode
Figure 1.6.2. Processor mode register 1
Processor mode register 1 (Note 1) :Flash memory version
Symbol Address When reset
PM1 0005
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new values to this register.
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P5
3
/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
ALE pin select bit (Note 3)
0 0 : No ALE
0 1 : P5
3
/BCLK (Note 4)
1 0 : P5
6
/RAS
1 1 : P5
4
/HLDA
b5 b4
PM15
PM14
Reserved bit
Must always be set to “0”
WR
Reserved bit
Must always be set to “1”
0
PM12
Internal memory wait bit 0 : No wait state
1 : Wait state inserted
External memory area
mode bit (Note 3)
0 0 : Mode 0 (P4
4
to P4
7
: A
20
to A
23
)
0 1 : Mode 1 (P4
4
: A
20
,
P4
5
to P4
7
: CS2 to CS0)
1 0 : Mode 2 (P4
4
, P4
5
: A
20
, A
21
,
P4
6
, P4
7
: CS1, CS0)
1 1 : Mode 3 (Note 2)
(P4
4
to P4
7
: CS3 to CS0)
b1 b0
PM11
PM10
Processor mode register 1 (Note 1) :Mask ROM version
Symbol Address When reset
PM1 0005
16
00
16
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
Note 1: Set bit 1 of the protect register (address 000A
16
) to “1” when writing new values to this register.
Note 2: When mode 3 is selected, DRAMC is not used.
Note 3: Valid in memory expansion mode or in microprocessor mode.
Note 4: When selecting P5
3
/BCLK, set bits 0 and 1 of system clock control register 0 (CM00, CM01) to "0".
ALE pin select bit (Note 3)
0 0 : No ALE
0 1 : P5
3
/BCLK (Note 4)
1 0 : P5
6
/RAS
1 1 : P5
4
/HLDA
b5 b4
PM15
PM14
Reserved bit
Must always be set to “0”
WR
Nothing is assinged. When read, the content is indeterminate.
0
PM12
Internal memory wait bit 0 : No wait state
1 : Wait state inserted
External memory area
mode bit (Note 3)
0 0 : Mode 0 (P4
4
to P4
7
: A
20
to A
23
)
0 1 : Mode 1 (P4
4
: A
20
,
P4
5
to P4
7
: CS2 to CS0)
1 0 : Mode 2 (P4
4
, P4
5
: A
20
, A
21
,
P4
6
, P4
7
: CS1, CS0)
1 1 : Mode 3 (Note 2)
(P4
4
to P4
7
: CS3 to CS0)
b1 b0
PM11
PM10
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
27
Processor Mode
Figure 1.6.3. Memory maps in each processor mode (without memory area expansion, normal mode)
Singl chip
mode
Memory expanded mode
Microprocesser mode
SFR area
Internal RAM area
Internal reserved area
Internal ROM area
No use
External area
CS2
2Mbytes
CS0
2Mbytes
No use
Internal ROM area
Internal reserved area
Internal ROM area
Internal reserved area
Internal ROM area
Internal reserved area
CS0
3Mbytes
CS1
4Mbytes
(Note2)
CS1
2Mbytes
(Note1)
External area
CS2
2Mbytes
No use
CS0
2Mbytes
CS0
4Mbytes
CS1
4Mbytes
(Note2)
000000
16
000400
16
000800
16
200000
16
400000
16
C00000
16
E00000
16
F00000
16
FFFFFF
16
Each CS0, CS1 and CS can set 0 to 3 WAIT.
Mode 0
Mode 1 Mode 2 Mode 0
MOde 1 Mode 2
SFR area
Internal RAM area
Internal reserved area
SFR area
Internal RAM area
Internal reserved area
SFR area
Internal RAM area
Internal reserved area
SFR area
Internal RAM area
Internal reserved area
SFR area
Internal RAM area
Internal reserved area
SFR area
Internal RAM area
Mode 3
Internal reserved area
SFR area
Internal RAM area
Internal ROM area
Internal reserved area
CS1
1Mbytes
Mode 3
Internal reserved area
SFR area
Internal RAM area
No use
CS2
1Mbytes
No use
Connect with
DRAM
0.05 to 8MB
(When not
connect with
DRAM, use as
external area.)
External area
Connect with
DRAM
0.05 to 8MB
(When open area
is under 8MB,
cannot use the
rest of this area.)
Connect with
DRAM
0.05 to 8MB
(When open area
is under 8MB,
cannot use the
rest of this area.)
Connect with
DRAM
0.05 to 8MB
(When open area
is under 8MB,
cannot use the
rest of this area.)
No use
(Cannot use as
DRAM area or
external area.)
Connect with
DRAM
0.05 to 8MB
(When not
connect with
DRAM, use as
external area.)
Connect with
DRAM
0.05 to 8MB
(When open area
is under 8MB,
cannot use the
rest of this area.)
No use
(Cannot use as
DRAM area or
external area.)
External area
No use
CS3
1Mbytes
CS0
1Mbytes
CS1
1Mbytes
No use
CS2
1Mbytes
No use
CS1
2Mbytes
(Note1)
No use
CS3
1Mbytes
CS0
1Mbytes
Processor Mode
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group

Bus Settings

28
Bus Settings
The BYTE pin, bit 0 to 3 of the external data bus width control register (address 000B16), bits 4 and 5 of the
processor mode register 0 (address 000416) and bit 0 and 1 of the processor mode register 1 (address
000516) are used to change the bus settings.
Table 1.7.1 shows the factors used to change the bus settings, figure 1.7.1 shows external data bus width
control register and table 1.7.2 shows external area 0 to 3 and external area mode.
Bus setting Switching factor
Switching external address bus width External data bus width control register
Switching external data bus width BYTE pin (external area 3 only)
Switching between separate and multiplex bus Bits 4 and 5 of processor mode register 0
(1) Selecting external address bus width
You can select the width of the address bus output externally from the 16 Mbytes address space, the
number of chip select signals, and the address area of the chip select signals. (Note, however, that when
____
you select “Full CS space multiplex bus”, addresses A0 to A15 are output.) The combination of bits 0 and
1 of the processor mode register 1 allow you to set the external area mode.
When using DRAM controller, the DRAM area is output by multiplexing of the time splitting of the row and
column addresses.
(2) Selecting external data bus width
You can select 8-bit or 16-bit for the width of the external data bus for external areas 0, 1, 2, and 3. When
the data bus width bit of the external data bus width control register is “0”, the data bus width is 8 bits;
when “1”, it is 16 bits. The width can be set for each of the external areas. The default bus width for
external area 3 is 16 bits when the BYTE pin is “L” after a reset, or 8 bits when the BYTE pin is “H” after
a reset. The bus width selection is valid only for the external bus (the internal bus width is always 16 bits).
During operation, fix the level of the BYTE pin to “H” or “L”.
(3) Selecting separate/multiplex bus
The bus format can be set to multiplex or separate bus using bits 4 and 5 of the processor mode register 0.
• Separate bus
In this bus configuration, input and output is performed on separate data and address buses. The data
bus width can be set to 8 bits or 16 bits using the external data bus width control register. For all
programmable external areas, P0 is the data bus when the external data bus is set to 8 bits, and P1 is
a programmable IO port. When the external data bus width is set to 16 bits for any of the external
areas, P0 and P1 (although P1 is undefined for any 8-bit bus areas) are the data bus.
When accessing memory using the separate bus configuration, you can select a software wait using
the wait control register.
• Multiplex bus
In this bus configuration, data and addresses are input and output on a time-sharing basis. For areas
for which 8-bit has been selected using the external data bus width control register, the 8 bits D0 to D7
are multiplexed with the 8 bits A0 to A7. For areas for which 16-bit has been selected using the
external data bus width control register, the 16 bits D0 to D15 are multiplexed with the 16 bits A0 to
A15. When accessing memory using the multiplex bus configuration, two waits are inserted regard-
less of whether you select “No wait” or “1 wait’ in the appropriate bit of the wait control register.
Table 1.7.1. Factors for switching bus settings
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
Bus Settings
29
____
The default after a reset is the separate bus configuration, and the full CS space multiplex bus configu-
____
ration cannot be selected in microprocessor mode. If you select “Full CS space multiplex bus”, the 16
bits from A0 to A15 are output for the address
External data bus width control register
Symbol Address When reset
DS 000B
16
XXXXX000
2
Bit name FunctionBit symbol
b7 b6 b5 b4 b3 b2 b1 b0
DS3
DS1
DS0
External area 0 data bus
width bit
DS2
External area 1 data bus
width bit
External area 2 data bus
width bit
External area 3 data bus
width bit (Note)
0 : 8 bits data bus width
1 : 16 bits data bus width
Note: The value after a reset is determined by the input via the BYTE pin.
WR
Nothing is assigned.
When write, set "0". When read, their contents are indeterminate.
0 : 8 bits data bus width
1 : 16 bits data bus width
0 : 8 bits data bus width
1 : 16 bits data bus width
0 : 8 bits data bus width
1 : 16 bits data bus width
Figure 1.7.1. External data bus width control register
Note 1: DRAMC area when using DRAMC.
Note 2:Set the external area mode (modes 0, 1, 2, and 3) using bits 0 and 1 of the processor mode register
1 (address 000516).
External area mode
(Note 2)
Mode 0 Mode 1 Mode 2 Mode 3
External
area 0
External
area 1
External
area 2
External
area 3
Memory expansion mode
Memory expansion mode
,
Microprocessor mode
Microprocessor mode
Memory expansion mode
,
Microprocessor mode
008000
16
to
1FFFFF
16
200000
16
to
3FFFFF
16
400000
16
to
BFFFFF
16
(Note 1)
C00000
16
to
EFFFFF
16
C00000
16
to
FFFFFF
16
<CS1 area>
008000
16
to
1FFFFF
16
<CS2 area>
200000
16
to
3FFFFF
16
<DRAMC area>
400000
16
to
BFFFFF
16
<CS0 area>
C00000
16
to
EFFFFF
16
<CS0 area>
E00000
16
to
FFFFFF
16
<CS1 area>
008000
16
to
1FFFFF
16
<DRAMC area>
400000
16
to
BFFFFF
16
<CS0 area>
C00000
16
to
EFFFFF
16
<CS0 area>
C00000
16
to
FFFFFF
16
<CS1 area>
100000
16
to
1FFFFF
16
<CS2 area>
200000
16
to
2FFFFF
16
<CS3 area>
C00000
16
to
CFFFFF
16
<CS0 area>
E00000
16
to
EFFFFF
16
<CS0 area>
F00000
16
to
FFFFFF
16
Memory expansion mode
,
Microprocessor mode
No area is
selected.
Table 1.7.2. External area 0 to 3 and external area mode
Under
development
Preliminary Specifications REV.B
Specifications in this manual are tentative and subject to change.
Mitsubishi microcomputers
M16C/80 (144-pin version) group
Bus Settings
30
P0
0
to P0
7
I/O port Data bus Data bus Data bus Data bus I/O port I/O port
CS1 or CS2 : multiplexed
bus, and the other :
separate bus
Separate bus
All space multiplexed
bus
Single-chip
mode
Memory expansion mode/microprocessor modes
Memory
expansion mode
Data bus width
BYTE pin level
“01”, “10”
“00”
“11” (Note 1)
All external
area is 8 bits
Some external
area is 16 bits
All external
area is 8 bits
Some external
area is 16 bits
Note 1:The default after a reset is the separate bus configuration, and "Full CS space multiplex bus" cannot be selected in
microprocessor mode. When you select "Full CS space multiplex bus" in extended memory mode, the address bus
operates with 64 Kbytes boundaries for each chip select.
Note 2: Address bus in separate bus configuration.
Note 3: The ALE output pin is selected using bits 4 and 5 of the processor mode register 1.
Note 4: When you have selected use of the DRAM controller and you access the DRAM area, these are CASL, CASH, DW, and
BCLK outputs.
Note 5: The CS signal and address bus selection are set by the external area mode.
Processor
mode
Multiplexed
bus space
select bit
CS (chip select) or address bus (A
23
)
(For details, refer to “Bus control”) (Note 5)
Outputs RD, WRL, WRH, and BCLK or RD, BHE, WR, and BCLK
(For details, refer to “Bus control”) (Note 3,4)
P1
0
to P1
7
I/O port I/O port Data bus I/O port Data bus I/O port I/O
port
P2
0
to P2
7
I/O port
Address bus Address bus
Address bus Address bus Address bus Address bus
/data bus /data bus
/data bus /data bus
P4
0
to P4
3
I/O port Address bus Address bus Address bus Address bus I/O port I/O port
P4
4
to P4
6
I/O port CS (chip select) or address bus (A
23
)
(For details, refer to “Bus control”) (Note 5)
P4
7
I/O port
P5
0
to P5
3
I/O port
P5
4
I/O port HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3) HLDA(Note 3)
P5
5
I/O port HOLD HOLD HOLD HOLD HOLD HOLD
P5
6
I/O port RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3) RAS (Note 3)
P5
7
I/O port RDY RDY RDY RDY RDY RDY
P3
0
to P3
7
I/O port
Address bus Address bus
Address bus Address bus Address bus Address bus
/data bus
/data bus
(Note 2)
(Note 2)
(Note 2)
Table 1.7.3. Each processor mode and port function
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