Datasheet S6B1713A11-xxXN, S6B1713A01-B0CZ, S6B1713A01-xxX0, S6B1713A01-xxXN, S6B1713A11-B0CY Datasheet (Samsung)

ument may be reproduced or
transmitted in any form or by any means, electronic or mechanical, for any purpose, without the express written
permission of LCD Driver IC Team.

S6B1713

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

January.2000

Ver. 4.0

Prepared by: Jae-Su, Ko

[e-mail]

Contents in this document are subject to change without notice. No part of this doc

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

S6B1713 Specification Revision History

Version Content Date

2.0 Neglect the more past version than version 2.0 Nov.1998

2.1

fOSC = 16kHz (Typ.) → 22kHz (Typ.): For removing flicker phenomenon
Temperature coefficient (when TEMPS = L): -0.0%/°C → -0.05%/°C
Modified some syntax errors

3.0

Voltage regulator reference voltage [VREF]: TBD → 2.0
Modified voltage regulator block of “Functional Description”

3.1

VLCD absolute maximum rating: 15.0V → 17.0V
Power consumption: 100µA → 80µA

3.2

Oscillator frequency (1): 19 (Min.) →17 (Min.), 25 (Max.) →27 (Max.)
Oscillator frequency (2): 22 (Min.) →20 (Min.), 28 (Max.) →30 (Max.)

3.3

Modified Y-axis values of “Pad Center Coordinates”
Modified the contents of “Referential Instruction Setup Flow”

3.4 Word-processor version change Apr.1999

3.5

4.0

Modified error: pad No.113 (COMS) Y Coordinate: -1210 → -1140 (after)
Change VDD Range : 2.4V to 5.5V → 2.4V to 3.6V

Nov.1998

Nov.1998

Oct.1999
Jan.2000

2

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

CO

NTENTS

INTRODUCTION.................................................................................................................................................. 1

FEATURES ......................................................................................................................................................... 1

BLOCK DIAGRAM.............................................................................................................................................. 3

PAD CONFIGURATION....................................................................................................................................... 4

PAD CENTER COORDINATES........................................................................................................................... 5

PIN DESCRIPTION.............................................................................................................................................. 8

POWER SUPPLY......................................................................................................................................... 8

LCD DRIVER SUPPLY................................................................................................................................. 8

SYSTEM CONTROL .................................................................................................................................... 9

MICROPROCESSOR INTERFACE .............................................................................................................11

LCD DRIVER OUTPUTS.............................................................................................................................13

FUNCTIONAL DESCRIPTION............................................................................................................................14

MICROPROCESSOR INTERFACE .............................................................................................................14

DISPLAY DATA RAM (DDRAM)..................................................................................................................18

LCD DISPLAY CIRCUITS ............................................................................................................................21

LCD DRIVER CIRCUIT................................................................................................................................23

POWER SUPPLY CIRCUITS.......................................................................................................................24

REFERECE CIRCUIT EXAMPLES..............................................................................................................31

RESET CIRCUIT.........................................................................................................................................33

INSTRUCTION DESCRIPTION...........................................................................................................................34

SPECIFICATIONS..............................................................................................................................................48

ABSOLUTE MAXIMUM RATINGS...............................................................................................................48

DC CHARACTERISTICS.............................................................................................................................49

REFERENCE DATA....................................................................................................................................52

AC CHARACTERISTICS.............................................................................................................................54

REFERENCE APPLICATIONS...........................................................................................................................58

MICROPROCESSOR INTERFACE .............................................................................................................58

CONNECTIONS BETWEEN S6B1713 AND LCD PANEL............................................................................59

TCP PIN LAYOUT (SAMPLE)......................................................................................................................64

3

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

INTRODUCTION

The S6B1713 is a driver & controller LSI for graphic dot-matrix liquid crystal display systems. It contains 65
commons and 132 segments driver circuits. This chip is connected directly to a microprocessor, accepts serial or
8-bit parallel display data and stores in an on-chip Display Data RAM of 65 x 132 bits. It provides a high-flexible
display section due to 1-to-1 correspondence between on-chip display data RAM bits and LCD panel pixels. And it
performs display data RAM read/write operation with no externally operating clock to minimize power consumption.
In addition, because it contains power supply circuits necessary to drive liquid crystal, it is possible to make a display
system with the fewest components.

FEATURES

Driver Output Circuits

− 65 common outputs / 132 segment outputs
On-chip Display Data RAM

− Capacity: 65 x 132 = 8,580 bits

Applicable Duty Ratios

Duty ratio Applicable LCD bias Maximum display area

1/65 1/7 or 1/9
1/49 1/6 or 1/8
1/33 1/5 or 1/6

Microprocessor Interface

− 8-bit parallel bi-directional interface with 6800-series or 8080-series

− Serial interface (only write operation) available

Function Set

− Various instructions sets

− H/W, S/W reset capable

Built-in Analog Circuit

− On-chip oscillator circuit

− Voltage converter (x2, x3, x4, x5)

− Voltage regulator (temperature coefficient: -0.05%/°C, -0.2%/°C)

− Voltage follower

− Electronic contrast control function (64 steps)

Operating Voltage Range

− Supply voltage (VDD): 2.4 to 3.6 V

− LCD driving voltage (VLCD = V0 - VSS): 4.0 to 15.0 V

Low Power Consumption

65 × 132
49 × 132
33 × 132

− 70 µΑ Typ. (VDD = 3V, x4 boosting, V0 = 11V, internal power supply ON)

− 10 µΑ Max. (during power save [standby] mode)

Package Type

− Gold bumped chip or TCP

1

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Series Specifications

Product code TEMPS pin Temp. coefficient

S6B1713A01-B0CZ
S6B1713A01-B0CY
S6B1713A11-B0CZ
S6B1713A11-B0CY

S6B1713A01-xxX0

S6B1713A01-xxXN

S6B1713A11-xxX0

S6B1713A11-xxXN

0

(VSS connected)

1

(VDD connected)

0

(VSS connected)

1

(VDD connected)

-0.05%/°C

-0.2%/°C

-0.05%/°C

-0.2%/°C

* xx: TCP ordering number

Package Chip thickness

670 µm
470 µm

COG

670 µm
470 µm
670 µm
470 µm

TCP

670 µm
470 µm

2

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

VSS

DB0

DB1

COMS

COM64

BLOCK DIAGRAM

SEG132

SEG131

VDD

V0
V1
V2
V3
V4

COMS

COM1

:

33 COMMON

DRIVER

CIRCUITS

COM32

SEG1

SEG3

SEG2

132 SEGMENT

DRIVER CIRCUITS

SEG130

:

:

COM33

:

33 COMMON

DRIVER

CIRCUITS

HPMB

V0

VR

INTRS

TEMPS

VOUT

C1-

C1+

C2-

C2+

C3-

C3+

DCDC5B

BSTS

V / F

CIRCUIT

V / R

CIRCUIT

V / C

CIRCUIT

PAGE

ADDRESS

CIRCUIT

SEGMENT CONTROLLER

I/O

BUFFER

DISPLAY DATA RAM

65 X 132 = 8,580 Bits

COLUMN ADDRESS

CIRCUIT

STATUS REGISTER INSTRUCTION REGISTER

COMMON CONTROLLER

LINE

ADDRESS

CIRCUIT

INSTRUCTION DECODERBUS HOLDER

DISPLAY

TIMING

GENERATOR

CIRCUIT

OSCILLATOR

MS
CL
M
FRS
DISP
DUTY0
DUTY1

CLS

MPU INTERFACE (PARALLEL & SERIAL)

DB2

DB3

DB4

DB5

DB6(SCLK)

DB7(SID)

MI

RESETB

PS

RW_WR

E_RD

RS

CS2

CS1B

Figure 1. Block Diagram

3

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

148

287

147

288

111

324

110

1

ðððð

- - - -

ððð

ðððð

- - - -

ððð

(-5065, +1302)

(+5065, +1317)

30

µ

m

30

µ

m

30

µ

m

60

µ

m

30

µ

m

42

µ

m

108

µ

m

42

µ

m

108

µ

m

(-5060, -1180)

(+5060, -1180)

PAD CONFIGURATION

ррр ррррррррррррррррррр

- - - - - - - - - -

Y

S6B1713

(TOP VIEW)

рррррррррррррррррррррр

Figure 2. S6B1713 Chip Configuration

Table 1. S6B1713 Pad Dimensions

Items Pad No.

Chip size - 10860 2920
Pad pitch

Bumped
pad size

(0,0)

- - - - - - - - - -

1 to 110 90

111 to 324 70

1 to 110 56 114
111 to 147 108 50
148 to 287 50 108
288 to 324 108 50

ррррррррррррррррррр

X

ððð

ррррррррррррррррррррррр

Size

X Y

Unit

µm

Bumped pad height 1 to 324 17 (Typ.)

COG Align Key Coordinate ILB Align Key Coordinate

30µm 30µm 30µm

30µm 30µm 30µm

42µm 108µm

42µm108µm

4

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

No.

Name

XYNo.

Name

XYNo.

Name

X

Y

1

DUMMY

-4905

-1336

51

VDD

-405

-1336

101

BSTS

4095

-1336

2

DUMMY

-4815

-1336

52

VDD

-315

-1336

102

DCDC5B

4185

-1336

3

FRS

-4725

-1336

53

VDD

-225

-1336

103

VDD

4275

-1336

4M-4635

-1336

54

VDD

-135

-1336

104

HPM

4365

-1336

5CL-4545

-1336

55

VDD

-45

-1336

105

INTRS

4455

-1336

6

DISP

-4455

-1336

56

VDD45-1336

106

VSS

4545

-1336

7

VSS

-4365

-1336

57

VOUT

135

-1336

107

TEMPS

4635

-1336

8

CS1B

-4275

-1336

58

VOUT

225

-1336

108

VDD

4725

-1336

9

CS2

-4185

-1336

59

VOUT

315

-1336

109

DUMMY

4815

-1336

10

VDD

-4095

-1336

60

VOUT

405

-1336

110

DUMMY

4905

-1336

11

RESETB

-4005

-1336

61

C3+

495

-1336

111

DUMMY

5271

-1280

12RS-3915

-1336

62

C3+

585

-1336

112

DUMMY

5271

-1210

13

VSS

-3825

-1336

63

C3+

675

-1336

113

COMS

5271

-1140

14

RW_WR

-3735

-1336

64

C3+

765

-1336

114

COM1

5271

-1070

15

E_RD

-3645

-1336

65

C3-

855

-1336

115

COM2

5271

-1000

16

VDD

-3555

-1336

66

C3-

945

-1336

116

COM3

5271

-93017DB0

-3465

-1336

67

C3-

1035

-1336

117

COM4

5271

-86018DB1

-3375

-1336

68

C3-

1125

-1336

118

COM5

5271

-79019DB2

-3285

-1336

69

C1+

1215

-1336

119

COM6

5271

-72020DB3

-3195

-1336

70

C1+

1305

-1336

120

COM7

5271

-65021DB4

-3105

-1336

71

C1+

1395

-1336

121

COM8

5271

-58022DB5

-3015

-1336

72

C1+

1485

-1336

122

COM9

5271

-51023DB6

-2925

-1336

73

C1-

1575

-1336

123

COM10

5271

-44024DB7

-2835

-1336

74

C1-

1665

-1336

124

COM11

5271

-37025VSS

-2745

-1336

75

C1-

1755

-1336

125

COM12

5271

-30026VDD

-2655

-1336

76

C1-

1845

-1336

126

COM13

5271

-23027VDD

-2565

-1336

77

C2+

1935

-1336

127

COM14

5271

-16028VDD

-2475

-1336

78

C2+

2025

-1336

128

COM15

5271

-9029DUTY0

-2385

-1336

79

C2+

2115

-1336

129

COM16

5271

-2030DUTY1

-2295

-1336

80

C2+

2205

-1336

130

COM17

5271

5031VSS

-2205

-1336

81

C2-

2295

-1336

131

COM18

5271

12032MS

-2115

-1336

82

C2-

2385

-1336

132

COM19

5271

19033CLS

-2025

-1336

83

C2-

2475

-1336

133

COM20

5271

26034VDD

-1935

-1336

84

C2-

2565

-1336

134

COM21

5271

33035MI

-1845

-1336

85

VSS

2655

-1336

135

COM22

5271

40036PS

-1755

-1336

86

VSS

2745

-1336

136

COM23

5271

47037VSS

-1665

-1336

87VR2835

-1336

137

COM24

5271

54038VSS

-1575

-1336

88VR2925

-1336

138

COM25

5271

61039VSS

-1485

-1336

89V03015

-1336

139

COM26

5271

68040VSS

-1395

-1336

90V03105

-1336

140

COM27

5271

75041VSS

-1305

-1336

91V13195

-1336

141

COM28

5271

82042VSS

-1215

-1336

92V13285

-1336

142

COM29

5271

89043VSS

-1125

-1336

93V23375

-1336

143

COM30

5271

96044VSS

-1035

-1336

94V23465

-1336

144

COM31

5271

103045VSS

-945

-1336

95V33555

-1336

145

COM32

5271

110046VSS

-855

-1336

96V33645

-1336

146

DUMMY

5271

117047VDD

-765

-1336

97V43735

-1336

147

DUMMY

5271

124048VDD

-675

-1336

98V43825

-1336

148

DUMMY

4865

130149VDD

-585

-1336

99

VSS

3915

-1336

149

DUMMY

4795

130150VDD

-495

-1336

100

VSS

4005

-1336

150

DUMMY

4725

1301

PAD CENTER COORDINATES

Table 2. Pad Center Coordinates

[Unit: µm]

5

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

200

SEG49

1225

1301

250

SEG99

-2275

1301

300

COM55

-5271

400

Table 2. Pad Center Coordinates (Continued)

[Unit: µm]

No. Name X Y No. Name X Y No. Name X Y

151 DUMMY 4655 1301 201 SEG50 1155 1301 251 SEG100 -2345 1301
152 SEG1 4585 1301 202 SEG51 1085 1301 252 SEG101 -2415 1301
153 SEG2 4515 1301 203 SEG52 1015 1301 253 SEG102 -2485 1301
154 SEG3 4445 1301 204 SEG53 945 1301 254 SEG103 -2555 1301
155 SEG4 4375 1301 205 SEG54 875 1301 255 SEG104 -2625 1301
156 SEG5 4305 1301 206 SEG55 805 1301 256 SEG105 -2695 1301
157 SEG6 4235 1301 207 SEG56 735 1301 257 SEG106 -2765 1301
158 SEG7 4165 1301 208 SEG57 665 1301 258 SEG107 -2835 1301
159 SEG8 4095 1301 209 SEG58 595 1301 259 SEG108 -2905 1301
160 SEG9 4025 1301 210 SEG59 525 1301 260 SEG109 -2975 1301
161 SEG10 3955 1301 211 SEG60 455 1301 261 SEG110 -3045 1301
162 SEG11 3885 1301 212 SEG61 385 1301 262 SEG111 -3115 1301
163 SEG12 3815 1301 213 SEG62 315 1301 263 SEG112 -3185 1301
164 SEG13 3745 1301 214 SEG63 245 1301 264 SEG113 -3255 1301
165 SEG14 3675 1301 215 SEG64 175 1301 265 SEG114 -3325 1301
166 SEG15 3605 1301 216 SEG65 105 1301 266 SEG115 -3395 1301
167 SEG16 3535 1301 217 SEG66 35 1301 267 SEG116 -3465 1301
168 SEG17 3465 1301 218 SEG67 -35 1301 268 SEG117 -3535 1301
169 SEG18 3395 1301 219 SEG68 -105 1301 269 SEG118 -3605 1301
170 SEG19 3325 1301 220 SEG69 -175 1301 270 SEG119 -3675 1301
171 SEG20 3255 1301 221 SEG70 -245 1301 271 SEG120 -3745 1301
172 SEG21 3185 1301 222 SEG71 -315 1301 272 SEG121 -3815 1301
173 SEG22 3115 1301 223 SEG72 -385 1301 273 SEG122 -3885 1301
174 SEG23 3045 1301 224 SEG73 -455 1301 274 SEG123 -3955 1301
175 SEG24 2975 1301 225 SEG74 -525 1301 275 SEG124 -4025 1301
176 SEG25 2905 1301 226 SEG75 -595 1301 276 SEG125 -4095 1301
177 SEG26 2835 1301 227 SEG76 -665 1301 277 SEG126 -4165 1301
178 SEG27 2765 1301 228 SEG77 -735 1301 278 SEG127 -4235 1301
179 SEG28 2695 1301 229 SEG78 -805 1301 279 SEG128 -4305 1301
180 SEG29 2625 1301 230 SEG79 -875 1301 280 SEG129 -4375 1301
181 SEG30 2555 1301 231 SEG80 -945 1301 281 SEG130 -4445 1301
182 SEG31 2485 1301 232 SEG81 -1015 1301 282 SEG131 -4515 1301
183 SEG32 2415 1301 233 SEG82 -1085 1301 283 SEG132 -4585 1301
184 SEG33 2345 1301 234 SEG83 -1155 1301 284 DUMMY -4655 1301
185 SEG34 2275 1301 235 SEG84 -1225 1301 285 DUMMY -4725 1301
186 SEG35 2205 1301 236 SEG85 -1295 1301 286 DUMMY -4795 1301
187 SEG36 2135 1301 237 SEG86 -1365 1301 287 DUMMY -4865 1301
188 SEG37 2065 1301 238 SEG87 -1435 1301 288 DUMMY -5271 1240
189 SEG38 1995 1301 239 SEG88 -1505 1301 289 DUMMY -5271 1170
190 SEG39 1925 1301 240 SEG89 -1575 1301 290 COMS -5271 1100
191 SEG40 1855 1301 241 SEG90 -1645 1301 291 COM64 -5271 1030
192 SEG41 1785 1301 242 SEG91 -1715 1301 292 COM63 -5271 960
193 SEG42 1715 1301 243 SEG92 -1785 1301 293 COM62 -5271 890
194 SEG43 1645 1301 244 SEG93 -1855 1301 294 COM61 -5271 820
195 SEG44 1575 1301 245 SEG94 -1925 1301 295 COM60 -5271 750
196 SEG45 1505 1301 246 SEG95 -1995 1301 296 COM59 -5271 680
197 SEG46 1435 1301 247 SEG96 -2065 1301 297 COM58 -5271 610
198 SEG47 1365 1301 248 SEG97 -2135 1301 298 COM57 -5271 540
199 SEG48 1295 1301 249 SEG98 -2205 1301 299 COM56 -5271 470

6

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Table 2. Pad Center Coordinates (Continued)

[Unit: µm]

No. Name X Y No. Name X Y No. Name X Y

301 COM54 -5271 330
302 COM53 -5271 260
303 COM52 -5271 190
304 COM51 -5271 120
305 COM50 -5271 50
306 COM49 -5271 -20
307 COM48 -5271 -90
308 COM47 -5271 -160
309 COM46 -5271 -230
310 COM45 -5271 -300
311 COM44 -5271 -370
312 COM43 -5271 -440
313 COM42 -5271 -510
314 COM41 -5271 -580
315 COM40 -5271 -650
316 COM39 -5271 -720
317 COM38 -5271 -790
318 COM37 -5271 -860
319 COM36 -5271 -930
320 COM35 -5271 -1000
321 COM34 -5271 -1070
322 COM33 -5271 -1140
323 DUMMY -5271 -1210
324 DUMMY -5271 -1280

7

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

PIN DESCRIPTION

POWER SUPPLY

Table 3. Power Supply Pin Description

Name I/O Description

VDD Supply Power supply

VSS Supply Ground

LCD driver supply voltages
The voltage determined by LCD pixel is impedance-converted by an operational amplifier

for application.
Voltages should have the following relationship;
V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS
When the internal power circuit is active, these voltages are generated as following table
according to the state of LCD Bias.

LCD bias V1 V2 V3 V4

1/9 bias (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0
1/8 bias (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0
1/7 bias (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0
1/6 bias (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/5 bias (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0

V0
V1
V2
V3
V4

I/O

LCD DRIVER SUPPLY

Table 4. LCD Driver Supply Pin Description

Name I/O Description

C1- O Capacitor 1 negative connection pin for voltage converter

C1+ O Capacitor 1 positive connection pin for voltage converter

C2- O Capacitor 2 negative connection pin for voltage converter

C2+ O Capacitor 2 positive connection pin for voltage converter

C3- O Capacitor 3 negative connection pin for voltage converter

C3+ O Capacitor 3 positive connection pin for voltage converter

VOUT I/O Voltage converter input / output pin

5 times boosting circuit enable input pin

DCDC5B

VR I

I

When this pin is low in 4 times boosting circuit, the 5-times boosting voltage appears at
VOUT.

V0 voltage adjustment pin
It is valid only when on-chip resistors are not used (INTRS = “L”) .

8

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

SYSTEM CONTROL

Table 5. System Control Pin Description

Name I/O Description

Master / Slave operation select pin

− MS = "H": master operation

− MS = "L": slave operation

The following table depends on the MS status.

MS I

CLS I

CL I/O

M I/O

FRS O

DISP I/O

INTRS I

HPM I

TEMPS I

MS CLS

H

L - Disabled Disabled

Built-in oscillator circuit enable / disable select pin

− CLS = “H” : enable

− CLS = “L” : disable (external display clock input to CL pin)

Display clock input / output pin
When the S6B1713 is used in master/slave mode (multi-chip), the CL pins must be
connected each other.

LCD AC signal input / output pin
When the S6B1713 is used in master/slave mode (multi-chip), the M pins must be
connected each other.

− MS = “H” : output

− MS = “L” : input

Static driver segment output pin
This pin is used together with the M pin.

LCD display blanking control input / output
When S6B1713 is used in master/slave mode (multi-chip), the DISP pins must be

connected each other.

− MS = “H” : output

− MS = “L” : input

Internal resistors select pin
This pin selects the resistors for adjusting V0 voltage level.

− INTRS = "H": use the internal resistors.

− INTRS = "L": use the external resistors.

V0 voltage is controlled with VR pin and external resistive divider.
Power control pin of the power supply circuit for LCD driver

− HPM = "H": high power mode

− HPM = "L": normal mode

This pin is valid in master operation.
Selects temperature coefficient of the reference voltage

− TEMPS = "L": -0.05%/°C

− TEMPS = "H": -0.2%/°C

H Enabled Enabled Output Output Output Output
L Disabled Enabled

OSC

circuit

Power
supply

circuit

CL M FRS DISP

Input Output Output Output
Input Input Output Input

9

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Table 5. System Control Pin Description (Continued)

Name I/O Description

Selects input voltages of the built-in voltage converter

BSTS I

DUTY0
DUTY1

BSTS

Voltage converter

input voltage

Remarks

L 4V VDD > 4V

H VDD

2.4V ≤ VDD ≤ 3.6V

When BSTS pin is “L” , VDD must be higher than 4V in four times boosting.
NOTE: Because the maximum voltage of VDD has been changed to 3.6V, we strongly

recommend that BSTS pin should be fixed to “H” .
The LCD driver duty ratio depends on the following table

DUTY1 DUTY0 Duty ratio

I

L L 1/33
L H 1/49

H L/H 1/65

10

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

MICROPROCESSOR INTERFACE

Table 6. Microprocessor Interface Pin Description

Name I/O Description

RESETB

PS I

MI I

CS1B

CS2

RS I

RW_WR

Reset input pin

I

When RESETB is “L”, initialization is executed.
Parallel / Serial data input select input

PS

*NOTE: In serial mode, it is impossible to read data from the on-chip RAM. And DB0 to DB5
are high impedance and E_RD and RW_WR must be fixed to either “H” or “L”.

Microprocessor interface selects input pin

− MI = "H": 6800-series MPU interface

− MI = "L": 8080-series MPU interface

Chip select input pins

I

Data / instruction I/O is enabled only when CS1B is “L” and CS2 is “H”.
When chip select is non-active, DB0 to DB7 may be high impedance.

Register select input pin

− RS = "H": DB0 to DB7 are display data

− RS = "L": DB0 to DB7 are control data

Read / Write execution control pin

MI MPU type RW_WR Description

I

Interface

mode

H Parallel

L Serial

H 6800-series

L 8080-series

Chip

select

CS1B,

CS2

CS1B,

CS2

RW

/WR

Data /

instruction

RS DB0 to DB7

RS SID(DB7) Write only SCLK(DB6)

Read / Write control input pin

− RW = “H”: read

− RW = “L”: write

Write enable clock input pin
The data ON DB0 to DB7 are latched at the rising
edge of the /WR signal.

Data Read / Write Serial clock

E_RD

RW_WR

-

11

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Table 6. Microprocessor Interface Pin Description (Continued)

Name I/O Description

Read / Write execution control pin

MI MPU type E_RD Description

Read / Write control input pin

− RW = “H”: When E is “H”, DB0 to DB7 are in an

E_RD I

H 6800-series

E

output status.

− RW = “L”: The data on DB0 to DB7 are latched at
the falling edge of the E signal.

DB0

to

DB7

I/O

L 8080-series

/RD

Read enable clock input pin
When /RD is “L”, DB0 to DB7 are in an output status.

8-bit bi-directional data bus that is connected to the standard 8-bit microprocessor data
bus. When the serial interface selected (PS = "L");

− DB0 to DB5: high impedance

− DB6: serial input clock (SCLK)

− DB7: serial input data (SID)

When chip select is not active, DB0 to DB7 may be high impedance.

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S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

LCD DRIVER OUTPUTS

Table 7. LCD Driver Outputs Pin Description

Name I/O Description

LCD segment driver outputs
The display data and the M signal control the output voltage of segment driver.

SEG1

to

SEG132

COM1

to

COM64

COMS O

O

O

Display data M

Segment driver output voltage

Normal display Reverse display
H H V0 V2
H L VSS V3
L H V2 V0
L L V3 VSS

Power save mode VSS VSS

LCD common driver outputs
The internal scanning data and M signal control the output voltage of common driver.

Scan data M Common driver output voltage

H H VSS
H L V0
L H V1
L L V4

Power save mode VSS

Common output for the icons
The output signals of two pins are same. When not used, these pins should be left open. In

multi-chip (master / slave) mode, all COMS pins on both master and slave units are the
same signal.

NOTE: DUMMY - These pins should be opened (floated).

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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

FUNCTIONAL DESCRIPTION

MICROPROCESSOR INTERFACE

Chip Select Input

There are CS1B and CS2 pins for Chip Selection. The S6B1713 can interface with an MPU only when CS1B is “L”
and CS2 is “H”. When these pins are set to any other combination, RS, E_RD, and RW_WR inputs are disabled and
DB0 to DB7 are to be high impedance. And, in case of serial interface, the internal shift register and the counter are
reset.

Parallel / Serial Interface

S6B1713 has three types of interface with an MPU, which are one serial and two parallel interfaces. This parallel or
serial interface is determined by PS pin as shown in table 8.

Table 8. Parallel / Serial Interface Mode

PS Type CS1B CS2 MI Interface mode

H Parallel CS1B CS2

L Serial CS1B CS2

Parallel Interface (PS = "H")

The 8-bit bi-directional data bus is used in parallel interface and the type of MPU is selected by MI as shown in table

9. The type of data transfer is determined by signals at RS, E_RD and RW_WR as shown in table10.

Table 9. Microprocessor Selection for Parallel Interface

MI CS1B CS2 RS E_RD RW_WR

H CS1B CS2 RS E RW DB0 to DB7 6800-series

L CS1B CS2 RS /RD /WR DB0 to DB7 8080-series

Table 10. Parallel Data Transfer

Common

RS

6800-series 8080-series

E_RD

(E)

RW_WR

(RW)

E_RD

(/RD)

RW_WR

(/WR)

H 6800-series MPU mode

L 8080-series MPU mode

*×

DB0 to DB7 MPU bus

Description

Serial-mode

*× : Don't care

H H H L H Display data read out
H H L H L Display data write

L H H L H Register status read
L H L H L Writes to internal register (instruction)

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S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Serial Interface (PS = "L")

When the S6B1713 is active, serial data (DB7) and serial clock (DB6) inputs are enabled. And not active, the internal
8-bit shift register and the 3-bit counter are reset. Serial data can be read on the rising edge of serial clock going into
DB6 and processed as 8-bit parallel data on the eighth serial clock. Serial data input is display data when RS is high
and control data when RS is low. Since the clock signal (DB6) is easy to be affected by the external noise caused by
the line length, the operation check on the actual machine is recommended.

CS1B

CS2

SID

SCLK

RS

DB6DB7DB0DB1DB2DB3DB4DB5DB6DB7

Figure 3. Serial Interface Timing

Busy Flag

The Busy Flag indicates whether the S6B1713 is operating or not. When DB7 is “H” in read status operation, this
device is in busy status and will accept only read status instruction. If the cycle time is correct, the microprocessor
needs not to check this flag before each instruction, which improves the MPU performance.

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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Data Transfer

The S6B1713 uses bus holder and internal data bus for Data Transfer with the MPU. When writing data from the
MPU to on-chip RAM, data is automatically transferred from the bus holder to the RAM as shown in figure 4. And
when reading data from on-chip RAM to the MPU, the data for the initial read cycle is stored in the bus holder
(dummy read) and the MPU reads this stored data from bus holder for the next data read cycle as shown in figure 5.
This means that a dummy read cycle must be inserted between each pair of address sets when a sequence of
address sets is executed. Therefore, the data of the specified address cannot be output with the read display data
instruction right after the address sets, but can be output at the second read of data.

MPU signals

RS

/WR

DB0 to DB7

Internal signals

/WR

BUS HOLDER

COLUMN ADDRESS

N D(N) D(N+1) D(N+2) D(N+3)

N D(N) D(N+1) D(N+2) D(N+3)

N N+1 N+2 N+3

Figure 4. Write Timing

16

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

N

D(N)

D(N+1)

D(N+2)

N

N+1

N+2

N+3

MPU signals

RS

/WR

/RD

DB0 to DB7

Internal signals

/WR

/RD

BUS HOLDER

COLUMN ADDRESS

N

Dummy D(N) D(N+1)

Figure 5. Read Timing

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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

DISPLAY DATA RAM (DDRAM)

The Display Data RAM stores pixel data for the LCD. It is 65-row by 132-column addressable array. Each pixel can
be selected when the page and column addresses are specified. The 65 rows are divided into 8 pages of 8 lines and
the 9th page with a single line (DB0 only). Data is read from or written to the 8 lines of each page directly through
DB0 to DB7. The display data of DB0 to DB7 from the microprocessor correspond to the LCD common lines as
shown in Figure 6. The microprocessor can read from and write to RAM through the I/O buffer. Since the LCD
controller operates independently, data can be written into RAM at the same time as data is being displayed without
causing the LCD flicker.

DB0 0 0 1 - - 0
DB1 1 0 0 - - 1
DB2 0 1 1 - - 0
DB3 1 0 1 - - 0

DB4 0 0 0 - - 1

COM1 - -

COM2 - ­COM3 - ­COM4 - ­COM5 - -

Display Data RAM LCD Display

Figure 6. RAM-to-LCD Data Transfer

Page Address Circuit

This circuit is for providing a Page Address to Display Data RAM shown in figure 8. It incorporates 4-bit Page
Address register changed by only the “Set Page” instruction. Page Address 8 (DB3 is “H”, but DB2, DB1 and DB0
are “L”) is a special RAM area for the icons and display data DB0 is only valid. When Page Address is above 8, it is
impossible to access to on-chip RAM.

Line Address Circuit

This circuit assigns DDRAM a Line Address corresponding to the first line (COM1) of the display. Therefore, by
setting line address repeatedly, it is possible to realize the screen scrolling and page switching without changing the
contents of on-chip RAM as shown in figure 8. It incorporates 6-bit line address register changed by only the initial
display line instruction and 6-bit counter circuit. At the beginning of each LCD frame, the contents of register are
copied to the line counter which is increased by CL signal and generates the Line Address for transferring the
132-bit RAM data to the display data latch circuit. However, display data of icons are not scrolled because the MPU
can not access Line Address of icons.

18

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Column Address Circuit

Column address circuit has a 8-bit preset counter that provides column address to the Display Data RAM as shown
in figure 8. When set Column Address MSB / LSB instruction is issued, 8-bit [Y7:Y0] is updated. And, since this
address is increased by 1 each a Read or Write Data instruction, microprocessor can access the display data
continuously. However, the counter is not increased and locked if a non-existing address above 84H. It is unlocked
if a column address is set again by set Column Address MSB / LSB instruction. And the Column Address counter is
independent of page address register.

ADC select instruction makes it possible to invert the relationship between the Column Address and the segment
outputs. It is necessary to rewrite the display data on built-in RAM after issuing ADC select instruction. Refer to the
following figure 7.

SEG output

SEG 1 SEG 2 SEG 3 SEG

4

... ...

SEG

129

SEG

130

SEG

131

SEG

132

Column address [Y7:Y0] 00H 01H 02H 03H ... ... 80H 81H 82H 83H

Display data 1 0 1 0 1 1 0 0

LCD panel display

( ADC = 0 )

... ...

LCD panel display

... ...

( ADC = 1 )

Figure 7. The Relationship between the Column Address and the Segment Outputs

Segment Control Circuit

This circuit controls the display data by the Display ON / OFF, Reverse display ON / OFF and entire display ON /
OFF instructions without changing the data in the display data RAM.

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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Page Address

DB3 DB0DB1DB2

0 0 0 0

0 0 0 1

0 0 1 0

0 0 1 1

0 1 0 0

0 1 0 1

0 1 1 0

0 1 1 1

1 0 0 0

Column

Address

LCD Output

Data

ADC=0
ADC=1

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7

DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB0

00

-

83 81 7F80 7E

82

SEG2

SEG1

02 0403 05

SEG3

SEG4

SEG5

SEG6

Page0

Page1

Page2

Page3

Page4

Page5

Page6

Page7

Page8

- - - - -

- - - - -

- - - - -

7E 7F 80 8281 8301

05 04 03 0102 00

SEG128

SEG127

SEG130

SEG129

SEG131

SEG132

Line

Address

00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH

Start

1/49

Duty

When the initial display

line address

is 1C[HEX]

1/33

Duty

COM

Output

COM1
COM2
COM3
COM4
COM5
COM6
COM7
COM8

COM9
COM10
COM11
COM12
COM13
COM14
COM15
COM16
COM17
COM18
COM19
COM20
COM21
COM22
COM23
COM24
COM25
COM26
COM27
COM28
COM29
COM30
COM31
COM32
COM33
COM34
COM35
COM36
COM37
COM38
COM39
COM40
COM41
COM42
COM43
COM44
COM45
COM46
COM47
COM48
COM49
COM50
COM51
COM52

COM53

COM54
COM55
COM56
COM57
COM58
COM59
COM60

COM61

COM62
COM63
COM64

COMS

Figure 8. Display Data RAM Map

20

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

1/65 Duty (85°C)

LCD DISPLAY CIRCUITS

Oscillator

This is completely on-chip oscillator and its frequency is nearly independent of VDD. This oscillator signal is used in
the voltage converter and display timing generation circuit.

* Test condition: Temperature: 25°C & 85°C, TEMPS=”L” , No load

VDD vs. f

osc

7.00

6.00
1/33 Duty (25°C)

1/49 Duty (25°C)
1/65 Duty (25°C)
1/33 Duty (85°C)

fosc

[kHz]

5.00

4.00

3.00
1/49 Duty (85°C)

2.00

1.00

0.00

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5
VDD [V]

Figure 9. VDD vs. fOSC

Display Timing Generator Circuit

This circuit generates some signals to be used for displaying LCD. The display clock, CL, generated by oscillation
clock, generates the clock for the line counter and the signal for the display data latch. The line address of on-chip
RAM is generated in synchronization with the display clock (CL) and the 132-bit display data is latched by the
display data latch circuit in synchronization with the display clock. The display data, which is read to the LCD driver,
is completely independent of the access to the display data RAM from the microprocessor. The display clock
generates an LCD AC signal (M) which enables the LCD driver to make a AC drive waveform, and also generates an
internal common timing signal and start signal to the common driver. Driving 2-frame AC driver waveform and
internal timing signal are shown in figure 9.

In a multiple-chip configuration, the slave chip requires the M, CL and DISP signals from the master. Table 11 shows
the M, CL, and DISP status.

Table 11. Master and Slave Timing Signal Status

Operation mode Oscillator

Master

ON (internal clock used) Output Output Output

M CL DISP

OFF (external clock used) Output Input Output

Slave - Input Input Input

21

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

64 65 1 2 3 4 5 6 7 8 9 10 11 12 58 59 60 61 62 63 64 65 1 2 3 4 5 6

CL

M

V0
V1

COM1

COM2

SEGn

V2
V3
V4
VSS

V0
V1
V2
V3
V4
VSS

V0
V1
V2
V3
V4
VSS

Figure 10. 2-frame AC Driving Waveform (Duty ratio = 1/65)

Common Output Control Circuit

This circuit controls the relationship between the number of common output and specified duty ratio. SHL Select
Instruction specifies the scanning direction of the common output pins.

Table 12. The Relationship between Duty Ratio and Common Output

Duty SHL

1/33

1/49

1/65

COM[1:16] COM[17:24] COM[25:40] COM[41:48] COM[49:64]

0 COM[1:16] *NC COM[17:32]
1 COM[32:17] *NC COM[16:1]
0 COM[1:24] *NC COM[25:48]
1 COM[48:25] *NC COM[24:1]
0 COM[1:64]
1 COM[64:1]

Common output pins

COMS

COMS

COMS

COMS

*NC: No Connection

22

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

COM16

SEG3

SEG2

SEG1

COM3

COM1

COM2

M

V

LCD DRIVER CIRCUIT

This driver circuit is configured by 66-channel common drivers (including 2 COMS channels) and 132-channel
segment drivers. This LCD panel driver voltage depends on the combination of display data and M signal.

COM1
COM2
COM3
COM4
COM5

COM6
COM7
COM8

COM9
COM10
COM11
COM12
COM13
COM14

COM15

V

DD

V0
V1
V2

V3
V4

V0
V1
V2

V3
V4

V0
V1
V2

V3
V4

V0
V1
V2

V3
V4

V0
V1
V2

V3
V4

S

E

E

E

E

E

G

G

G

1

3

2

G

G

5

4

Figure 11. Segment and Common Timing

23

V0
V1
V2

V3
V4

S

S

S

S

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

POWER SUPPLY CIRCUITS

The Power Supply circuits generate the voltage levels necessary to drive liquid crystal driver circuits with low power
consumption and the fewest components. There are voltage converter circuits, voltage regulator circuits, and
voltage follower circuits. They are valid only in master operation and controlled by power control instruction. For
details, refers to "Instruction Description". Table 13 shows the referenced combinations in using power supply
circuits.

Table 13. Recommended Power Supply Combinations

User setup

Only the internal power

supply circuits are used

Only the voltage

regulator circuits and

voltage follower circuits

are used

Only the voltage follower

circuits are used

Only the external power

supply circuits are used

Power

control

(VC VR VF)

1 1 1 ON ON ON Open Open Open

0 1 1 OFF ON ON

0 0 1 OFF OFF ON Open

0 0 0 OFF OFF OFF Open

V/C

circuits

V/R

circuits

V/F

circuits

VOUT V0 V1 to V4

External

input

Open Open

External

input

External

input

External

Open

input

24

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

VDD

C1C1 GND

VSS

VDD

V

VDD-+

+--

+

C1

GND

V

-

+

+-+

-

+

VSSV

V

Voltage Converter Circuits

These circuits boost up the electric potential between VDD and VSS to 2, 3, 4 or 5 times toward positive side and
boosted voltage is outputted from VOUT pin.

[C1 = 1.0 to 4.7 µF]

DD

V

DD

VOUT

C3+

C3 -

C2+

C2 -

C1+

C1 -

DCDC5B

SS

V

VDD

VOUT = 2 × VDD

VDD

VOUT

C3+

C3 -

C2+

C2 -

C1+

C1 -

DCDC5B

SS

V

C1

C1

VOUT = 3 × VDD

DD

V

SS

V

Figure 12. Two Times Boosting Circuit Figure 13. Three Times Boosting Circuit

DD

DD

V

VOUT

C3+

C3 -

C2+
C2 ­C1+

C1 -

DCDC5B

SS

V

­C1

C1

C1

C1

DD

VOUT = 4 × V

DD

DD

DD

V

DD

V

VOUT

C3+

C3 -

C2+
C2 ­C1+

C1 -

DCDC5B

SS

V

C1

C1

C1

C1

GND

VOUT = 5 × V

DD

V

SS

V

DD

GND

GND

Figure 14. Four Times Boosting Circuit Figure 15. Five Times Boosting Circuit

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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Voltage Regulator Circuits

The function of the internal Voltage Regulator circuits is to determine liquid crystal operating voltage, V0, by
adjusting resistors, Ra and Rb, within the range of |V0| < |VOUT|. Because VOUT is the operating voltage of
operational-amplifier circuits shown in figure 16, it is necessary to be applied internally or externally.

For the Eq. 1, we determine V0 by Ra, Rb and VEV. The Ra and Rb are connected internally or externally by INTRS
pin. And VEV called the voltage of electronic volume is determined by Eq. 2, where the parameter α is the value
selected by instruction, "Set Reference Voltage Register", within the range 0 to 63. VREF voltage at Ta = 25°C is
shown in table 14-1.

Rb
V0 = ( 1 +  ) x VEV [V] ------ (Eq. 1)

Ra
(63 - α)

VEV = ( 1 -  ) x VREF [V] ------ (Eq. 2)
300

Table 14-1. VREF Voltage at Ta = 25 °C

TEMPS Temp. coefficient VREF [V]

L
H

-0.05% / °C

-0.2% / °C

2.0

2.0

Table 14-2. Reference Voltage Parameters (α)

SV5 SV4 SV3 SV2 SV1 SV0

Reference voltage parameter (α)

0 0 0 0 0 0 0
0 0 0 0 0 1 1

:
:

:
:

:
:

:
:

:
:

:

:
1 1 1 1 1 0 62
1 1 1 1 1 1 63

:
:

26

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

GND

Ra

Rb

VSSVRV0VOUT

+

EV

V

-

Figure 16. Internal Voltage Regulator Circuit

27

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

In Case of Using Internal Resistors, Ra and Rb (INTRS = "H")

When INTRS pin is “H”, resistor Ra is connec ted internally between VR pin and VSS, and Rb is connected between
V0 and VR. We determine V0 by two instructions, "Regulator Resistor Select" and "Set Reference Voltage".

Table 15. Internal Rb / Ra Ratio depending on 3-bit Data (R2 R1 R0)

0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1

1+(Rb / Ra)

The following figure shows V0 voltage measured by adjusting internal regulator resistor ratio (Rb / Ra) and 6-bit
electronic volume registers for each temperature coefficient at Ta = 25 °C.

1.90 2.19 2.55 3.02 3.61 4.35 5.29 6.48

3-bit data settings (R2 R1 R0)

14.00
(1 1 1)

12.00

10.00

(1 1 0)
(1 0 1)
(1 0 0)

V0

[V]

8.00

6.00

(0 1 1)
(0 1 0)
(0 0 1)

4.00

(0 0 0)

2.00

0.00
0 8 16 24 32 40 48 56

Electronic volume level

Figure 17. Electronic Volume Level

28

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

In Case of Using External Resistors, Ra and Rb. (INTRS = "L")

When INTRS pin is “L”, it is necessary to connect external regulator resist or Ra between VR and VSS, and Rb
between V0 and VR.

Example: For the following requirements

1. LCD driver voltage, V0 = 10V

2. 6-bit reference voltage register = (1, 0, 0, 0, 0, 0)

3. Maximum current flowing Ra, Rb = 1 uA

From Eq. 1
Rb

10 = ( 1 +  ) x VEV [V] ------ (Eq. 3)
Ra

From Eq. 2
(63 - 32)

VEV = ( 1 -  ) x 2.0 = 1.79 [V] ------ (Eq. 4)
300

From requirement 3.
10

 = 1 [uA] ------ (Eq. 5)
Ra + Rb

From equations Eq. 3, 4 and 5
Ra = 1.79 [MΩ]
Rb = 8.21 [MΩ]

The following table shows the range of V0 depending on the above requirements.

Table 16. V0 Depending on Electronic Volume Level

Electronic volume level

0 ....... 32 ....... 63

V0 8.83 ....... 10.00 ....... 11.17

29

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Voltage Follower Circuits

VLCD voltage (V0) is resistively divided into four voltage levels (V1, V2, V3 and V4) and those output impedance are
converted by the Voltage Follower for increasing drive capability. The following table shows the relationship
between V1 to V4 level and each duty ratio.

Table 17. The Relationship between V1 to V4 level and Duty Ratio

Duty Ratio DUTY1 DUTY0

1/33 L L

1/49 L H

1/65 H L/H

LCD Bias V1 V2 V3 V4

1/5 (4/5) x V0 (3/5) x V0 (2/5) x V0 (1/5) x V0
1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/6 (5/6) x V0 (4/6) x V0 (2/6) x V0 (1/6) x V0
1/8 (7/8) x V0 (6/8) x V0 (2/8) x V0 (1/8) x V0
1/7 (6/7) x V0 (5/7) x V0 (2/7) x V0 (1/7) x V0
1/9 (8/9) x V0 (7/9) x V0 (2/9) x V0 (1/9) x V0

30

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

VDD

VDD

VOUT

V4

VOUT

C1

C1

When using internal regulator

VOUT

V4

VOUT

REFERECE CIRCUIT EXAMPLES

resistors When not using internal regulator resistors

VSS

V

C1

C1
C1

C2 - +
C2 - +
C2 - +
C2 - +
C2 - +

SS

MS INTRS

C3+
C3­C2+
C2­C1+
C1-

VR
V0

V1
V2
V3

V

C1
C1

C1

C2 - +
C2 - +

C2 - +
C2 - +
C2 - +

SS

Ra

MS INTRS

C3+
C3­C2+
C2­C1+
C1-

VR

Rb

V0
V1
V2
V3
V4

Figure 18. When Using all LCD Power Circuits (4-Time V/C: ON, V/R: ON, V/F: ON)

When using internal regulator resistors When not using internal regulator resistors

V

DD

External

Power

Supply

C2 - +
C2 - +
C2 - +
C2 - +
C2 - +

MS INTRS

C3+
C3­C2+
C2­C1+
C1-

VR
V0

V1
V2
V3

V

DD

External

Power

Supply

Ra

C2 - +
C2 - +
C2 - +
C2 - +
C2 - +

MS INTRS

C3+
C3­C2+
C2­C1+
C1-

VR

Rb

V0
V1
V2
V3
V4

V

SS

V

SS

Figure 19. When Using some LCD Power Circuits (V/C: OFF, V/R: ON, V/F: ON)

V

SS

31

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

V

DD

VOUT

V4

VOUT

V4

MS INTRS

C3+
C3­C2+

External

Power

C2­C1+
C1-

Supply

VR

V

C2 - +
C2 - +
C2 - +
C2 - +
C2 - +

SS

V0
V1
V2
V3

Figure 20. When Using some LCD Power Circuits (V/C: OFF, V/R: OFF, V/F: ON)

VDD

MS INTRS

C3+
C3­C2+

VSS

External

Power

Supply

C2­C1+
C1-

VR
V0

V1
V2
V3

Value of external Capacitance

Item Value Unit

C1 1.0 to 4.7
C2 0.47 to 1.0

µ

F

Figure 21. When Not Using any Internal LCD Power Supply Circuits (V/C: OFF, V/R: OFF, V/F: OFF)

32

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

RESET CIRCUIT

Setting RESETB to “L” or Reset instruction can initialize internal function.
When RESETB becomes “L”, following procedure is occurred.

Display ON / OFF: OFF
Entire display ON / OFF: OFF (normal)
ADC select: OFF (normal)
Reverse display ON / OFF: OFF (normal)
Power control register (VC, VR, VF) = (0, 0, 0)
LCD bias ratio: 1/7 (1/65 duty), 1/6 (1/49 duty), 1/5 (1/33 duty)
Read-modify-write: OFF
SHL select: OFF (normal)
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)
Display start line: 0 (first)
Column address: 0
Page address: 0
Regulator resistor select register: (R2, R1, R0) = (0, 0, 0)
Reference voltage set: OFF
Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0)

When RESET instruction is issued, following procedure is occurred.

Read-modify-write: OFF
Static indicator mode: OFF
Static indicator register: (S1, S0) = (0, 0)
SHL select: 0
Display start line: 0 (first)
Column address: 0
Page address: 0
Regulator resistor select register: (R2, R1, R0) = (0, 0, 0)
Reference voltage set: OFF
Reference voltage control register: (SV5, SV4, SV3, SV2, SV1, SV0) = (1, 0, 0, 0, 0, 0)

While RESETB is “L” or Reset instruction is executed, no instruction except read status can be accepted. Reset
status appears at DB4. After DB4 becomes ”L”, any instruction can be accepted. RESETB must be connected to the
reset pin of the MPU, and initialize the MPU and this LSI at the same time. The initialization by RESETB is essential
before used.

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65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

INSTRUCTION DESCRIPTION

Table 18. Instruction Table

× : Don’t care

Instruction

Read display data 1 1 Read data Read data from DDRAM
Write display data 1 0 Write data Write data into DDRAM

Read status 0 1

Display ON / OFF 0 0 1 0 1 0 1 1 1

Initial display line 0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0 Specify DDRAM line for COM1

Set reference voltage

mode

Set reference voltage

register

Set page address 0 0 1 0 1 1 P3 P2 P1 P0 Set page address

Set column address MSB

Set column address LSB 0 0 0 0 0 0 Y3 Y2 Y1 Y0 Set column address LSB

Reverse display ON / OFF 0 0 1 0 1 0 0 1 1 REV

Entire display ON / OFF 0 0 1 0 1 0 0 1 0 EON

LCD bias select 0 0 1 0 1 0 0 0 1
Set modify-read 0 0 1 1 1 0 0 0 0 0 Set modify-read mode

Reset modify-read 0 0 1 1 1 0 1 1 1 0 Release modify-read mode

Regulator resistor select 0 0 0 0 1 0 0 R2 R1 R0

Set static indicator mode 0 0 1 0 1 0 1 1 0 SM Set static indicator mode

Set static indicator register 0 0

ADC select 0 0 1 0 1 0 0 0 0 ADC

Reset 0 0 1 1 1 0 0 0 1 0 Initialize the internal functions

SHL select 0 0 1 1 0 0 SHL

Power control 0 0 0 0 1 0 1 VC VR VF Control power circuit operation

Power save - - - - - - - - - -

Test instruction 0 0 1 1 1 1

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

BUSY ADC ON/OFF

0 0 1 0 0 0 0 0 0 1 Set reference voltage Mode

0 0

0 0 0 0 0 1 Y7 Y6 Y5 Y4 Set column address MSB

× ×

× × × × × ×

RESETB

SV5 SV4 SV3 SV2 SV1 SV0 Set reference voltage register

0 0 0 0 Read the internal status

× × × ×

Turn on/off LCD panel

DON

When DON = 0: display OFF
When DON = 1: display ON

Select SEG output direction
When ADC = 0: normal direction
(SEG1→SEG132)
When ADC = 1: reverse direction
(SEG132→SEG1)

Select normal / reverse display
When REV = 0: normal display
When REV = 1: reverse display

Select normal / entire display ON
When EON = 0: normal display.
When EON = 1: entire display ON

BIAS Select LCD bias

Select COM output direction
When SHL = 0: normal direction

× × ×

S1 S0 Set static indicator register

(COM1→COM64)
When SHL = 1: reverse direction

(COM64→COM1)

Select internal resistance ratio of
the regulator resistor

Compound instruction of display
OFF and entire display ON

Don't use this instruction.

Description

34

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Read Display Data

8-bit data from Display Data RAM specified by the column address and page address can be read by this
instruction. As the column address is increased by 1 automatically after each this instruction, the
microprocessor can continuously read data from the addressed page. A dummy read is required after loading
an address into the column address register. Display Data cannot be read through the serial interface.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 1 Read data

Write Display Data

8-bit data of Display Data from the microprocessor can be written to the RAM location specified by the column
address and page address. The column address is increased by 1 automatically so that the microprocessor can
continuously write data to the addressed page.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

1 0 Write data

Set Page Address

Set Column Address

Data Write

Column = Column + 1

Data Write Continue ?

NO

Optional Status

YES

Set Page Address

Set Column Address

Dummy Data Read

Column = Column + 1

Data Read

Column = Column + 1

Data Read Continue ?

NO

Optional Status

YES

Figure 22. Sequence for Writing Display Data Figure 23. Sequence for Reading Display Data

35

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Read Status

Indicates the internal status of the S6B1713.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 1 BUSY ADC ON / OFF RESETB

0 0 0

0

Flag Description

The device is busy when internal operation or reset. Any instruction is rejected until

BUSY

BUSY goes Low.
0: chip is active, 1: chip is being busy.

ADC

ON / OFF

RESETB

Indicates the relationship between RAM column address and segment driver.
0: reverse direction (SEG132 → SEG1), 1: normal direction (SEG1 → SEG132)

Indicates display ON / OFF status
0: display ON, 1: display OFF

Indicates the initialization is in progress by RESETB signal.
0: chip is active, 1: chip is being reset.

Display ON / OFF

Turns the display ON or OFF

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 1 1 1 DON

DON = 1: display ON
DON = 0: display OFF

Initial Display Line

Sets the line address of display RAM to determine the Initial Display Line. The RAM display data is displayed at
the top row (COM1 when SHL = L, COM64 when SHL = H) of LCD panel.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 1 ST5 ST4 ST3 ST2 ST1 ST0

ST5 ST4 ST3 ST2 ST1 ST0 Line address

0 0 0 0 0 0 0
0 0 0 0 0 1 1

: : : : : : :
1 1 1 1 1 0 62
1 1 1 1 1 1 63

36

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Reference Voltage Select

Consists of 2-byte instruction
The 1st instruction sets reference voltage mode, the 2nd one updates the contents of reference voltage register.
After second instruction, reference voltage mode is released.

The 1st Instruction: Set Reference Voltage Select Mode

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 0 0 0 0 0 1

The 2nd Instruction: Set Reference Voltage Register

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0

× ×

SV5 SV4 SV3 SV2 SV1 SV0

SV5 SV4 SV3 SV2 SV1 SV0

Reference voltage parameter (α)

0 0 0 0 0 0 0
0 0 0 0 0 1 1

:
:

:
:

:
:

:
:

:
:

:

:
1 1 1 1 1 0 62
1 1 1 1 1 1 63

Setting Reference Voltage Start

1st Instruction for Mode Setting

2nd Instruction for Register Setting

Setting Reference Voltage End

Figure 24. Sequence for Setting the Reference Voltage

:
:

37

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Set Page Address

Sets the Page Address of display data RAM from the microprocessor into the Page Address register. Any RAM
data bit can be accessed when its Page Address and column address are specified. Along with the column
address, the Page Address defines the address of the display RAM to write or read display data. Changing the
Page Address doesn't effect to the display status.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

P3 P2 P1 P0 Page

0 0 0 0 0
0 0 0 1 1

: : : : :
0 1 1 1 7
1 0 0 0 8

Set Column Address

Sets the Column Address of display RAM from the microprocessor into the Column Address register. Along with
the Column Address, the Column Address defines the address of the display RAM to write or read display data.
When the microprocessor reads or writes display data to or from display RAM, column addresses are
automatically increased.

Set Column Address MSB

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 0 1 Y7 Y6 Y5 Y4

Set Column Address LSB

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 1 P3 P2 P1 P0

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Column address

0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 1

: : : : : : : : :

1 0 0 0 0 0 1 0 130
1 0 0 0 0 0 1 1 131

38

0 0 0 0 0 0 Y3 Y2 Y1 Y0

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

ADC Select

Changes the relationship between RAM column address and segment driver. The direction of segment driver
output pins can be reversed by software. This makes IC layout flexible in LCD module assembly.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 0 0 ADC

ADC = 0: normal direction (SEG1 → SEG132)
ADC = 1: reverse direction (SEG132 → SEG1)

Reverse Display ON / OFF

Reverses the display status on LCD panel without rewriting the contents of the display data RAM.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

REV RAM bit data = “1” RAM bit data = “0”

0 (normal) LCD pixel is illuminated LCD pixel is not illuminated

1 (reverse) LCD pixel is not illuminated LCD pixel is illuminated

Entire Display ON / OFF

Forces the whole LCD points to be turned on regardless of the contents of the display data RAM. At this time,
the contents of the display data RAM are held. This instruction has priority over the reverse display ON / OFF
instruction.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 1 0 EON

EON = 0: normal display
EON = 1: entire display ON

Select LCD Bias

Selects LCD bias ratio of the voltage required for driving the LCD.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 0 0 1 Bias

0 0 1 0 1 0 0 1 1 REV

Duty

ratio

DUTY1 DUTY0

Bias = 0 Bias = 1

LCD bias

1/33 0 0 1/5 1/6
1/49 0 1 1/6 1/8
1/65 1 0/1 1/7 1/9

39

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Set Modify-Read

This instruction stops the automatic increment of the column address by the read display data instruction, but
the column address is still increased by the write display data instruction. And it reduces the load of
microprocessor when the data of a specific area is repeatedly changed during cursor blinking or others. This
mode is canceled by the reset Modify-read instruction.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 0 0 0

Reset Modify-Read

This instruction cancels the Modify-read mode, and makes the column address return to its initial value just
before the set Modify-read instruction is started.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 1 1 1 0

Set Page Address

NO

Set Column Address (N)

Set Modify-Read

Dummy Read

Data Read

Data Process

Data Write

Change Complete ?

YES

Reset Modify-Read

Return Column Address (N)

Figure 25. Sequence for Cursor Display

40

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Reset

This instruction resets initial display line, column address, page address, and common output status select to
their initial status, but dose not affect the contents of display data RAM. This instruction cannot initialize the LCD
power supply which is initialized by the RESETB pin.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 1 0 0 0 1 0

SHL Select

COM output scanning direction is selected by this instruction which determines the LCD driver output status.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 1 0 0 SHL

× × ×

× : Don’ t care
SHL = 0: normal direction (COM1 → COM64)
SHL = 1: reverse direction (COM64 → COM1)

Power control

Selects one of eight power circuit functions by using 3-bit register. An external power supply and part of internal
power supply functions can be used simultaneously.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 0 0 1 0 1 VC VR VF

VC VR VF Status of internal power supply circuits

0
1

0
1

0
1

Internal voltage converter circuit is OFF

Internal voltage converter circuit is ON

Internal voltage regulator circuit is OFF

Internal voltage regulator circuit is ON

Internal voltage follower circuit is OFF

Internal voltage follower circuit is ON

41

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Regulator Resistor Select

Selects resistance ratio of the internal resistor used in the internal voltage regulator. See voltage regulator
section in power supply circuit. Refer to the table 15.

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

R2 R1 R0 1 + (Rb / Ra)

0 0 0 1.90
0 0 1 2.19
0 1 0 2.55
0 1 1 3.02
1 0 0 3.61
1 0 1 4.35
1 1 0 5.29
1 1 1 6.48

Set Static Indicator State

Consists of two bytes instruction. The first byte instruction (set Static Indicator mode) enables the second byte
instruction (set Static Indicator register) to be valid. The first byte sets the static indicator ON / OFF. When it is
on, the second byte updates the contents of static indicator register without issuing any other instruction and
this static indicator state is released after setting the data of indicator register.

0 0 0 0 1 0 0 R2 R1 R0

st

The 1

Instruction: Set Static Indicator Mode (ON / OFF)

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 1 0 1 0 1 1 0 SM

SM = 0: static indicator OFF
SM = 1: static indicator ON

The 2nd Instruction: Set Static Indicator Register

RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0

× × × × × ×

S1 S0 Status of static indicator output

0 0 OFF
0 1 ON (about 1 second blinking)
1 0 ON (about 0.5 second blinking )
1 1 ON (always ON)

S1 S0

42

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Release Sleep Mode

Power Save (Compound Instruction)

If the entire display ON / OFF instruction is issued during the display OFF state, S6B1713 enters the Power
Save status to reduce the power consumption to the static power consumption value. According to the status of
static indicator mode, power save is entered to one of two modes (sleep and standby mode). When static
indicator mode is ON, standby mode is issued, when OFF, sleep mode is issued. Power Save mode is released
by the display ON and entire display OFF instruction.

Static Indicator OFF Static Indicator ON

Power Save (Compound Instruction)

[Display OFF]

[Entire Display ON]

Sleep Mode

[Oscillator Circuit: OFF]

[LCD Power Supply Circuit: OFF]

[All COM / SEG Outputs: VSS]
[Consumption Current: < 2mA]

Power Save OFF (Compound Instruction)

[Entire Display OFF]
[Static Indicator ON]

[Display ON]

Figure 26. Power Save Routine

Standby Mode

[Oscillator Circuit: ON]

[LCD Power Supply Circuit: OFF]

[All COM/SEG Outputs: VSS]

[Consumption Current: < 10mA]

Power Save OFF (Compound Instruction)

[Entire Display OFF]

[Display ON]

Release Standby Mode

43

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Referential Instruction Setup Flow (1)

User System Setup by External Pins

Start of Initialization

Power ON (VDD - VSS) Keeping the RESETB Pin = “L”

Waiting for Stabilizing the Power

RESETB Pin = “H”

User Application Setup by Internal Instructions

[ADC Select]

[SHL Select]

[LCD Bias Select]

User LCD Power Setup by Internal Instructions

[Voltage Converter ON]

Waiting for ≥ 1ms

User LCD Power Setup by Internal Instructions

[Voltage Regulator ON]

Waiting for ≥ 1ms

User LCD Power Setup by Internal Instructions

[Voltage Follower ON]

User LCD Power Setup by Internal Instructions

[Regulator Resistor Select]

[Reference Voltage Register Set]

Waiting for Stabilizing the LCD Power Levels

End of Initialization

Figure 27. Initializing with the Built-in Power Supply Circuits

44

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Referential Instruction Setup Flow (2)

User System Setup by External pins

Start of initialization

Power On ( VDD - VSS ) keeping the RESETB pin = “L”

Waiting for stabilizing the power

RESETB pin = “H”

Set Power Save

User Application Setup by Internal Instructions

[ADC Select]

[SHL Select]

[LCD Bias Select]

User LCD Power Setup by Internal Instructions

[Regulator Resistor Select]

[Reference Voltage Register Set]

Release Power Save

Waiting for Stabilizing the LCD Power Levels

End of Initialization

Figure 28. Initializing without the Built-in Power Supply Circuits

45

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Referential Instruction Setup Flow (3)

End of Initialization

Display Data RAM Addressing by Instruction

[Initial Display Line]
[Set Page Address]

[Set Column Address]

Write Display ON / OFF by Instruction

[Display ON / OFF]

Turn Display ON / OFF by Instruction

[Display ON / OFF]

End of Data Display

Figure 29. Data Displaying

46

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Waiting for ≥ 1ms

Waiting for ≥ 1ms

Referential Instruction Setup Flow (4)

Optional Status

Turn Display ON / OFF by Instruction

[Display OFF]

User LCD Power Setup by Internal Instructions

[Voltage Regulator OFF]

Waiting for ≥ 50ms

User LCD Power Setup by Internal Instructions

[Voltage Follower OFF]

User LCD Power Setup by Internal Instructions

[Voltage Converter OFF]

Power OFF (V

DD

- VSS)

Figure 30. Power OFF

47

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

Table 19. Absolute Maximum Ratings

Parameter Symbol Rating Unit

Supply voltage range

VDD -0.3 to +7.0 V

VLCD -0.3 to +17.0 V

Input voltage range VIN -0.3 to VDD +0.3 V

Operating temperature range TOPR -40 to +85

Storage temperature range TSTR -55 to +125

NOTES:

1. VDD and VLCD are based on VSS = 0V.

2. Voltages V0 ≥ V1 ≥ V2 ≥ V3 ≥ V4 ≥ VSS must always be satisfied. (VLCD = V0 – VSS)

3. If supply voltage exceeds its absolute maximum range, this LSI may be damaged permanently.
It is desirable to use this LSI under electrical characteristic conditions during general operation.
Otherwise, this LSI may malfunction or reduced LSI reliability may result.

°C
°C

48

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

DC CHARACTERISTICS

Table 20. DC Characteristics

(VSS = 0V, VDD = 2.4 to 3.6V, Ta = -40 to 85°C)

Operating voltage (1)
Operating voltage (2)

Input voltage

Item Symbol

High VIH 0.8VDD

Low VIL VSS - 0.2VDD

Output

voltage

High VOH IOH = -0.5mA 0.8VDD

Low VOL IOL = 0.5mA VSS - 0.2VDD

VDD 2.4 - 3.6 V VDD *1

V0 4.0 - 15.0 V V0 *2

Input leakage current IIL VIN = VDD or VSS - 1.0 - + 1.0

Condition Min. Typ. Max Unit Pin used

- VDD
V *3

- VDD
V *4

µA

*5

Output leakage current

LCD driver ON

resistance

Oscillator

frequency (1)

Oscillator

frequency (2)

Voltage converter

input voltage

Voltage converter

output voltage

Voltage regulator
operating voltage

Voltage follower

operating voltage

Reference voltage

IOZ VIN = VDD or VSS - 3.0 - + 3.0

RON Ta = 25°C, V0 = 8V - 2.0 3.0 kΩ

Internal fOSC 17 22 27

External fCL

Internal fOSC 20 25 30

External fCL

Ta = 25°C
Duty ratio = 1/65

Ta = 25°C
Duty ratio = 1/49

× 2
× 3

4.25 5.50 6.75

3.33 4.17 5.00

2.4 - 3.6

2.4 - 3.6

VDD

× 4
× 5

2.4 - 3.6

2.4 - 3.0

×2 / ×3 / ×4 / ×5

VOUT

voltage conversion

95 99 - % VOUT

(no-load )

VOUT 4.0 - 15.0 V VOUT

V0 4.0 - 15.0 V V0 *9

VREF0

-0.05%/°C

1.94 2.00 2.06 V *10

Ta = 25°C

VREF1

-0.2%/°C

1.94 2.00 2.06 V *10

µA

*6

SEGn

COMn *7

kHz

kHz

CL *8

CL *8

V VDD

49

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

Dynamic Current Consumption (1) when the Built-in Power Circuit is OFF (At Operate Mode)

(Ta = 25 °C)

Item Symbol

Dynamic current
consumption (1)

IDD1

Condition Min. Typ. Max. Unit Pin used

VDD = 3.0V

V0 – VSS = 11.0V

1/65 duty ratio

- - 20 µΑ *11

Display pattern OFF

Dynamic Current Consumption (2) when the built-in power circuit is ON (At operate mode)

(Ta = 25 °C)

Item Symbol

Condition Min. Typ. Max. Unit Pin used

VDD = 3.0V,

quad boosting,

V0 – VSS = 11.0V,

1/65 duty ratio,

- 70 100

µΑ

*12

Display pattern OFF,

Dynamic current
consumption (2)

IDD2

Normal power mode

VDD = 3.0V,

quad boosting,

V0 – VSS = 11.0V,

1/65 duty ratio,

- 95 160

µΑ

*12

Display pattern checker,

Normal power mode

Current Consumption During Power Save Mode

Item Symbol

Sleep mode

current

Standby mode

current

IDDS1 During sleep - - 2.0 µA

IDDS2

Condition Min. Typ. Max. Unit Pin used

During standby

- - 10.0

(Ta = 25 °C)

µA

50

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Table 21. The Relationship between Oscillation Frequency and Frame Frequency

Duty Ratio Item fCL fM

1/65

On-chip oscillator circuit is used

fOSC



4

fOSC



8 × 65

fOSC

On-chip oscillator circuit is not used

External input (fCL)



2 × 65

1/49

On-chip oscillator circuit is used

fOSC



6

fOSC



12 × 49

fOSC

On-chip oscillator circuit is not used

External input (fCL)



2 × 49

1/33

On-chip oscillator circuit is used

fOSC



8

fOSC



16 × 33

fOSC

On-chip oscillator circuit is not used

External input (fCL)



2 × 33

(fOSC: oscillation frequency, fCL: display clock frequency, fM: LCD AC signal frequency)

[* Remark Solves]
*1. Though the wide range of operating voltages is guaranteed, a spike voltage change may affect the voltage
assurance during access from the MPU.
*2. In case of external power supply is applied.
*3. CS1B, CS2, RS, DB0 to DB7, E_RD, RW_WR, RESETB, MS, MI, PS, INTRS, HPM, TEMPS, BSTS,
DCDC5B, CLS, CL, M, DISP pins.
*4. DB0 to DB7, M, FRS, DISP, CL pins.
*5. CS1B, CS2, RS, DB [7:0], E_RD, RW_WR, RESETB, MS, MI, PS, INTRS, HPM, TEMPS, BSTS, DCDC5B,
CLS, CL, M, DISP pins.
*6. Applies when the DB [7:0], M, DISP, and CL pins are in high impedance.
*7. Resistance value when ± 0.1[mA] is applied during the ON status of the output pin SEGn or COMn.
RON= ∆V / 0.1 [kΩ] (∆V: voltage change when ± 0.1[mA] is applied in the ON status.)
*8. See table 21 for the relationship between oscillation frequency and frame frequency.
*9. The voltage regulator circuit adjusts V0 within the voltage follower operating voltage range
*10. On-chip reference voltage source of the voltage regulator circuit to adjust V0.
*11,12. Applies to the case where the on-chip oscillation circuit is used and no access is made from the MPU.
The current consumption, when the built-in power supply circuit is ON or OFF.
The current flowing through voltage regulation resistors (Ra and Rb) is not included.
It does not include the current of the LCD panel capacity, wiring capacity, etc.

51

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

REFERENCE DATA

IDD1 vs. VDD

* Test Condition: Temperature: 25°C & 85°C, V0 = 11V (External), TEMPS = 'L', 1/65 duty, Normal Power Mode

IDD1
[uA]

10.00

8.00

6.00

4.00

2.00

0.00

VDD vs. I

DD1

(Pattern Off)

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0 5.5
VDD [V]

Figure 31. Display Pattern is OFF

11.0V, 1/65 Duty (25°C)

11.0V, 1/65 Duty (85°C)

52

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

DD2

IDD2 vs. VDD

* Test Condition: Temperature: 25°C & 85°C, 1/65 duty, Quad Boosting, RR = 6, EV = 32

VDD vs. IDD2 (Pattern Off)

80.00

70.00

60.00

I

[uA]

IDD2
[uA]

50.00

40.00

30.00

20.00

10.00

0.00

180.00

160.00

140.00

120.00

100.00

80.00

60.00

40.00

20.00

0.00

1/65 Duty (25°C)
1/65 Duty (85°C)

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0
VDD [V]

Figure 32. Display Pattern is OFF

VDD vs. IDD2 (Checker Pattern)

1/65 Duty (25°C)
1/65 Duty (85°C)

2.4 2.7 3.0 3.3 3.6 4.0 4.5 5.0
VDD [V]

Figure 33. Display Pattern is Checker

53

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

t

t

t

t

0.9V

0.1V

t

, t

t

t

t

AC CHARACTERISTICS

Read / Write Characteristics (8080-series MPU)

RS

AS80

AH80

CS1B
(CS2=1)

RD, WR

DD

PW80(R)

DD

PW80(W)

DS80

CY80

DH80

DB0 to DB7
(Write)

ACC80

OD80

DB0 to DB7
(Read)

Figure 34. Read / Write Characteristics (8080-series MPU)

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Item Signal Symbol

Address setup time

Address hold time

RS

tAS80
tAH80

Min. Typ. Max. Unit Remark

13
17

- - ns

System cycle time RS tCY80 400 - - ns

Pulse width (WR) RW_WR tPW80 (W)

Pulse width (RD) E_RD tPW80 (R)

Data setup time

Data hold time

Read access time

Output disable time

DB7

to

DB0

tDS80

tDH80

tACC80

tOD80

55 - - ns

125 - - ns

35
13

-

10

- - ns

-

125

90

ns CL = 100 pF

54

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

Read / Write Characteristics (6800-series Microprocessor)

RS

tAH68tAS68

CS1B

(CS2=1)

DB0 to DB7
(Write)

DB0 to DB7
(Read)

Address setup time

Output disable time

Enable pulse

tCY68

tPW68(R), tPW68(W)

E

0.9VDD0.1VDD

tACC68

tDS68

tDH68

tOD68

Figure 35. Read / Write Characteristics (6800-series Microprocessor)

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Item Signal Symbol

Address hold time

RS

TAS68

TAH68

Min. Typ. Max. Unit Remark

13
17

- - ns

System cycle time RS TCY68 400 - - ns

Data setup time

Data hold time

Access time

Read

width

write

DB7

to

DB0

E_RD

TDS68
TDH68

TACC68

TOD68

TPW68 (R)

TPW68 (W)

35
13

-

10

125

55

- - ns

-

125

90

ns CL = 100 pF

- - -

55

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

t

t

Serial Interface Characteristics

tCHStCSS

CS1B

(CS2 = 1 )

tAHStASS

RS

tCYS

DB6

( SCLK )

0.9VDD

0.1VDD
tWLS

tWHS

DB7

( SID )

Item Signal Symbol Min. Typ. Max. Unit Remark

Serial clock cycle

SCLK high pulse width

SCLK low pulse width

Address setup time

Address hold time

Data setup time

Data hold time

CS1B setup time

CS1B hold time

DSS

DHS

Figure 36. Serial Interface Characteristics

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

DB6

(SCLK)

RS

DB7

(SID)

CS1B

tCYS

tWHS

tWLS

tASS

tAHS
tDSS

tDHS
tCSS

tCHS

450
180
135

90

360

90
90

55

180

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

-

ns

ns

ns

ns

56

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

t

Reset Input Timing

tRW

RESETB

Figure 37. Reset Input Timing

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Reset low pulse width RESETB

Item Signal Symbol

Display Control Output Timing

Min.

Typ.

Max. Unit

tRW 900 - - ns

DM

Remark

CL

M

Figure 38. Display Control Output Timing

(VDD = 2.4 to 3.6V, Ta = -40 to +85°C)

Item Signal Symbol

Min.

Typ.

Max. Unit

Remark

M delay time M tDM - 13 70 ns

57

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

VDDVDDRWERS

DB0 to DB7

RESETB

VSS/WR

/RD

RS

CS1B

OPEN

VSSVDD or V

SID

CS1B

REFERENCE APPLICATIONS

MICROPROCESSOR INTERFACE

In Case of Interfacing with 6800-series (PS = “H”, MI = “H”)

CS1B
CS2

6800-series

MPU

DB0 to DB7
RESETB

Figure 39. Interfacing with 6800-series (PS = “H”, MI = “H”)

In Case of Interfacing with 8080-series (PS = “H”, MI = “L”)

CS2

8080-series

MPU

V

DD

Figure 40. Interfacing with 8080-series (PS = “H”, MI = “L”)

CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
RESETB
MI
PS

CS1B
CS2
RS
E_RD
RW_WR
DB0 to DB7
RESETB
MI
PS

S6B1713

S6B1713

In Case of Serial Interface (PS = “L”, MI = “H/L”)

CS1B
CS2
RS
DB7(SID)
DB6(SCLK)
RESETB
DB0 to DB5
MI
PS

S6B1713

MPU

CS2
RS

SCLK
RESETB

SS

Figure 41. Serial Interface (PS = “L”, MI = “H/L”)

58

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

SEG1 ........... SEG132

SEG132 ............ SEG1

CONNECTIONS BETWEEN S6B1713 AND LCD PANEL

Single Chip Configuration (1/65 Duty Configurations)

♣ ♦ ♥ ♠ Ξ 

64 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

SEG1 ........... SEG132

COM32

:

COM1
COMS

S6B1713

( Bottom View )

COMS

COM64

:

COM33

♣ ♦ ♥ ♠ Ξ 

64 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

SEG132 ........... SEG1

COMS

COM64

:

COM33

S6B1713

( Top View )

COM32
COM1

COMS

Figure 42. SHL = 0, ADC = 0 Figure 43. SHL = 0, ADC = 1

COMS

COM1

:

COM32

S6B1713

( Top View )

COM33

:

COM64

COMS

COM33

:
COM64
COMS

S6B1713

( Bottom View )

COMS
COM1

:

COM32

:

♣ ♦ ♥ ♠ Ξ 

64 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

♣ ♦ ♥ ♠ Ξ 

64 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

Figure 44. SHL = 1, ADC = 0 Figure 45. SHL = 1, ADC = 1

59

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

SEG1 ........... SEG132

SEG132 ........... SEG1

Single Chip Configuration (1/49 Duty Configurations)

♣ ♦ ♥ ♠ Ξ 

48 × 132 pixels

♣ ♦ ♥ ♠ Ξ

COM24

:

COM1
COMS

S6B1713

( Bottom View )



COMS

COM64

:

COM41

♣ ♦ ♥ ♠ Ξ

COMS

COM64

:

COM41

♣ ♦ ♥ ♠ Ξ 

48 × 132 pixels

S6B1713

( Top View )



COM24

:
COM1
COMS

Figure 46. SHL = 0, ADC = 0 Figure 47. SHL = 0, ADC = 1

COMS
COM1

:

COM24

S6B1713

( Top View )

COM41

:

COM64

COMS

COM41

:
COM64
COMS

S6B1713

( Bottom View )

COMS
COM1

:

COM24

♣ ♦ ♥ ♠ Ξ 

48 × 132 pixels

♣ ♦ ♥ ♠ Ξ



♣ ♦ ♥ ♠ Ξ

♣ ♦ ♥ ♠ Ξ 

48 × 132 pixels



Figure 48. SHL = 1, ADC = 0 Figure 49. SHL = 1, ADC = 1

60

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

SEG1 ........... SEG132

SEG132 ............ SEG1

Single Chip Configuration (1/33 Duty Configurations)

♣ ♦ ♥ ♠ Ξ 

32 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

SEG1 ........... SEG132

COM16

:

COM1
COMS

S6B1713

( Bottom View )

COMS

COM64

:

COM49

♣ ♦ ♥ ♠ Ξ 

32 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

SEG132 ........... SEG1

COMS

COM64

:

COM49

S6B1713

( Top View )

COM16

:
COM1
COMS

Figure 50. SHL = 0, ADC = 0 Figure 51. SHL = 0, ADC = 1

COMS

COM1

:

COM16

S6B1713

( Top View )

COM49

:

COM64

COMS

COM49

:
COM64
COMS

S6B1713

( Bottom View )

COMS
COM1

:

COM16

♣ ♦ ♥ ♠ Ξ 

32 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

♣ ♦ ♥ ♠ Ξ 

32 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

Figure 52. SHL = 1, ADC = 0 Figure 53. SHL = 1, ADC = 1

61

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

SEG1 ............... SEG132

SEG1 ............... SEG132

SEG132 ................. SEG1

SEG132 ................. SEG1

Multiple Chip Configuration

- 65COM (64COM + 1COMS) × 264SEG (132SEG × 2)

♣ ♦ ♥ ♠ Ξ 

64 × 264 pixels

♣ ♦ ♥ ♠ Ξ 

COM32

COM1
COMS

COM33

:
COM64
COMS

:

S6B1713

( Bottom View )

( Master )

COMS

COM64

:

COM33

COM32

:
COM1
COMS

Figure 54. SHL = 0, ADC = 0

♦ Connect the following pins of two chips each other

- Display clock pins: CL, M

- Display control pin: DISP

- LCD power pins: V0, V1, V2, V3, V4

S6B1713

( Bottom View )

( Master )

COMS

COM1

:

COM32

♣ ♦ ♥ ♠ Ξ 

COM33

:
COM64
COMS

S6B1713

( Bottom View )

( Slave )

S6B1713

( Bottom View )

( Slave )

COMS

COM64

:

COM33

COMS

COM1

:

COM32

62

64 × 264 pixels

♣ ♦ ♥ ♠ Ξ 

Figure 55. SHL = 1, ADC = 1

♦ Connect the following pins of two chips each other

- Display clock pins: CL, M

- Display control pin: DISP

- LCD power pins: V0, V1, V2, V3, V4

S6B1713 65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD

SEG132 ................. SEG1

- 130COM (128COM + 2COMS) × 132SEG

COM33

:
COM64
COMS

♣ ♦ ♥ ♠ Ξ 

S6B1713

( Bottom View )

( Master )

128 × 132 pixels

♣ ♦ ♥ ♠ Ξ 

SEG1 ................. SEG132

COM32
:

COM1

COMS

S6B1713

( Bottom View )

( Slave )

COMS

COM1

:

COM32

COMS

COM64

:

COM33

Figure 56. 130COM (128COM + 2COMS) × 132SEG

♦ Connect the following pins of two chips each other

- Display clock pins: CL, M

- Display control pin: DISP

- LCD power pins: V0, V1, V2, V3, V4
♦ Common / Segment output direction select

- Master chip: SHL = 1, ADC = 1

- Slave chip: SHL = 0, ADC = 0

63

65 COM / 132 SEG DRIVER & CONTROLLER FOR STN LCD S6B1713

S6B1713

(TOP VIEW)

TCP PIN LAYOUT (SAMPLE)

COM33

COM34
COM35

FRS
M
CL
DISP
CS1B
CS2
RESETB
RS
RW_WR
E_RD
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DUTY0
DUTY1
MS
CLS
MI
PS

SS

V

DD

V
VOUT
C3+
C3­C1+
C1­C2+
C2­VR
V0
V1
V2
V3
V4
BSTS
DCDC5B
HPM
INTRS
TEMPS

:
:

:
COM46
COM47
COM48

:

:

:

COM62

COM63
COM64

COMS
SEG132
SEG131
SEG130
SEG129

:
:
:

:
SEG66
SEG65
SEG64
SEG63

:

:

:

:

SEG4
SEG3
SEG2
SEG1

COM32

COM31

COM30

:

:

:

COM17
COM16
COM15

:

:

:

COM3
COM2
COM1

COMS

64

Figure 57. TCP Pin Layout