Datasheet S75PL-N Datasheet (SPANSION)

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S75PL-N MirrorBit™ ORNAND™ MCPs

Stacked Multi-Chip Product (MCP)
S29PL-N: CMOS 3.0 Volt-only Simultaneous Read/Write,
Page-mode Flash Memory (NOR Interface)
S30ML-P: ORNAND Flash (NAND Interface)
3V pSRAM

S75PL-N MirrorBit™ ORNAND™ MCPs Cover Sheet

Data Sheet (Advance Information)

Notice to Readers: This document states the current technical specifications regarding the Spansion
product(s) described herein. Each product described herein may be designated as Advance Information,
Preliminary, or Full Production. See Notice On Data Sheet Designations for definitions.

Publication Number S75PL-N_00 Revision 01E Issue Date April 21, 2006

Data Sheet (Advance Information)

Notice On Data Sheet Designations

Spansion LLC issues data sheets with Advance Information or Preliminary designations to advise readers of
product information or intended specifications throughout the product life cycle, including development,
qualification, initial production, and full production. In all cases, however, readers are encouraged to verify
that they have the latest information before finalizing their design. The following descriptions of Spansion data
sheet designations are presented here to highlight their presence and definitions.

Advance Information

The Advance Information designation indicates that Spansion LLC is developing one or more specific
products, but has not committed any design to production. Information presented in a document with this
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LLC therefore places the following conditions upon Advance Information content:

“This document contains information on one or more products under development at Spansion LLC.
The information is intended to help you evaluate this product. Do not design in this product without
contacting the factory. Spansion LLC reserves the right to change or discontinue work on this
proposed product without notice.”

Preliminary

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“This document states the current technical specifications regarding the Spansion product(s)
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Combination

Some data sheets contain a combination of products with different designations (Advance Information,
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wherever necessary, typically on the first page, the ordering information page, and pages with the DC
Characteristics table and the AC Erase and Program table (in the table notes). The disclaimer on the first
page refers the reader to the notice on this page.

Full Production (No Designation on Document)

When a product has been in production for a period of time such that no changes or only nominal changes
are expected, the Preliminary designation is removed from the data sheet. Nominal changes may include
those affecting the number of ordering part numbers available, such as the addition or deletion of a speed
option, temperature range, package type, or V
description or to correct a typographical error or incorrect specification. Spansion LLC applies the following
conditions to documents in this category:

“This document states the current technical specifications regarding the Spansion product(s)
described herein. Spansion LLC deems the products to have been in sufficient production volume
such that subsequent versions of this document are not expected to change. However, typographical
or specification corrections, or modifications to the valid combinations offered may occur.”

Questions regarding these document designations may be directed to your local AMD or Fujitsu sales office.

range. Changes may also include those needed to clarify a

IO

ii S75PL-N MirrorBit™ ORNAND™ MCPs April 21, 2006 S75PL-N_00-01E

S75PL-N MirrorBit™ ORNAND™ MCPs

Stacked Multi-Chip Product (MCP)
S29PL-N: CMOS 3.0 Volt-only Simultaneous Read/Write,
Page-mode Flash Memory (NOR Interface)
S30ML-P: ORNAND Flash (NAND interface)
3V pSRAM

Data Sheet (Advance Information)

Features

 Speed

– PL-N: 70 ns (initial access, 30 ns page access)
– ML-P: 30 ns (page access)
– pSRAM: 70 ns

General Description

This document contains information for the S75PL-N MirrorBit MCP product. TheS75PL-N product consists of the following
devices:

 S29PL-N

 S30ML-P

 3V pSRAM

 107-Ball Fine-Pitch Ball Grid Array (FBGA)

– 9 x 12 x 1.4mm for ML512P based MCP's
– 11 x 13 x 1.4mm for ML01GP based MCPs

 Operating Temperature Range

– Temperature Range of –25°C to +85°C

Flash/RAM Combinations Table

S29PL127N +

S30ML512P S75PL127NBF

S30ML01GP

Product Selector Guide

Device pSRAM Density pSRAM Type

S75PL127NBF 32 Mb pSRAM Type 7

For detailed specifications, please refer to the individual data sheets:

Document Publication Identification Number (PID)

S29PL-N S29PL-N_M0

S30ML-P S30ML-GP_00

32M pSRAM Type 7 pSRAM_29

pSRAM Density

32 Mb 64 Mb

Publication Number S75PL-N_00 Revision 01E Issue Date April 21, 2006

This document contains information on one or more products under development at Spansion LLC. The information is intended to help you evaluate this product. Do not design
in this product without contacting the factory. Spansion LLC reserves the right to change or discontinue work on this proposed product without notice.

Data Sheet (Advance Information)

1. Ordering Information

The ordering part number is formed by a valid combination of the following:

S75PL 127 N B F JF W GZ 0

PACKING TYPE

0 = Tray
2 = 7” Tape and Reel
3 = 13” Tape and Reel

MODEL NUMBER

Refer to the Valid Combinations table below

TEMPERATURE RANGE

W = Wireless (–25°C to +85°C)

PACKAGE TYPE AND MATERIAL

JA = MCP BGA, 1.4 mm height, 0.8 mm pitch, Lead (Pb)-free Compliant package
JF = MCP BGA, 1.4 mm height, 0.8 mm pitch, Lead (Pb)-free package

ORNAND DATA DENSITY

F = S30ML512P
G = S30ML01GP

pSRAM DENSITY

B = 32 Mb pSRAM
C = 64 Mb pSRAM
D = 128 Mb pSRAM

PROCESS TECHNOLOGY

N = 110 nm MirrorBit™ Technology

FLASH DENSITY

256 = 256 Mb
127 = 128 Mb (Single CE#)

DEVICE FAMILY

S75PL = 3.0 Volt-only Simultaneous Read/Write, Page Mode Flash Memory with Data storage
ORNAND and pSRAM

2 S75PL-N MirrorBit™ ORNAND™ MCPs S75PL-N_00_01E April 21, 2006

Data Sheet (Advance Information)

0

2

#

#

#

#

#

1.1 Valid Combinations

Valid Combinations list configurations planned to be supported in volume for this device. Consult your local
sales office to confirm availability of specific valid combinations and to check on newly released
combinations.

Valid Combinations

Base Ordering

Part Number (2)

S75PL127NBF JAW, JFW GZ

Package &

Temperature

Model

Number

Packing

Typ e

0, 2, 3

(1), (2)

pSRAM

Typ e

Linear Mode
Access Time

Type 7 70ns 30ns 70ns

Notes:

1. 7\SHLVVWDQGDUG6SHFLI\RWKHURSWLRQVDVUHTXLUHG

2. BGA package marking omits leading “S” and packing type designator from ordering part number.

3. Contact factory for availability for any of the OPNs listed since RAM type availability may vary over time.

PL-N

ML-P Page

Mode Access

Time

pSRAM

Linear Mode

Access Time Package Name

9x12x1.4mm,

2. Block Diagram (S29PL-N and pSRAM on Bus 1, S30ML-P on Bus 2)

FMH107

107 ball

A0-A2

A21-A2

RY/BY# RY/BY# DQ0-DQ15

A0-A20

A21-A22

DQ0-DQ15

S29PL127N

F-CE# CE#
OE# OE#
F-RST# SSV#TESER VSS
F-ACC/WP# ACC/WP#

WE# WE#

VCC F-VCC
VCCQ

A0-A20

DQ0-DQ15

R-CE

R-LB# LB#
R-UB

R-CE2 R-CE2

I/O0-I/O7 I/O0-I/O7

CE#
OE#

UB#
WE#

32Mb

pSRAM

Memory

VSS
VCC R-VCC

VCCQ

N-RY/BY

N-CLE CLE
N-CE
N-ALE ALE

N-RE
N-WP# WP#
N-WE# WE#

N-PRE PRE

RY/BY#

CE#

S30ML512P
x8 ORNAND

#ER

CCV

FP#

I/O0-I/O7

VSS N-VSS

N-VCC

I/O0-I/O7

S75PL-N_00_01E April 21, 2006 S75PL-N MirrorBit™ ORNAND™ MCPs 3

3. Connection Diagrams

3.1 S75PL-N Pinout

A

B

DNU DNU DNUDNU

Index

C

No ball

D

E

F

G

Data Sheet (Advance Information)

Figure 3.1 107-ball Fine-Pitch Ball Grid Array (S75PL127NBF)

32910547681

VSSRFU RFU RFURFURFU RFURFU RFU

A7RFU RFU RFU

A6A3 A15 RFU

A5A2 A21 RFU

A4A1 A22

WP#/

LB# A8WE# A11N-RY/BY

ACC

RST#UB# A19R-CE2 A12N-RE#

RY/BY#A18 A9A20 A13N-CE#

VCCnRFUA17 A10RFU A14N-VCC

Reserved for Future Use

Legend

DNU

H

VSSA0 A16

J

K

L

M

N

P

F-CE# RFU I/O7DQ3DQ9 DQ13DQ4 DQ15N-CLE

OE#

DQ0R-CE1# VSS

DQ8

N-WP# I/O4 I/O5DQ11DQ2 DQ5RFU DQ14N-WE#

RFURFU I/O3 N-PRERFUVSS I/O1I/O0 I/O2DNU

DNU DNU DNUDNU

VSSnRFUDQ1 DQ6RFU RFUN-VSS

I/O6F-VCCDQ10 DQ12R-VCC DQ7N-ALE

NOR Flash Only

ORNAND Flash Only

pSRAM Only

Note:

Top view—balls facing down. The addresses that are shared vary by MCP combination as shown in the table below:

PL-N Addresses PL-N/pSRAM Addresses

S75PL127NBF A22-A21 A20:A0

Special Handling Instructions for FBGA Package

Special handling is required for Flash Memory products in FBGA packages.

Flash memory devices in FBGA packages may be damaged if exposed to ultrasonic cleaning methods. The
package and/or data integrity may be compromised if the package body is exposed to temperatures above
150°C for prolonged periods of time.

4 S75PL-N MirrorBit™ ORNAND™ MCPs S75PL-N_00_01E April 21, 2006

Data Sheet (Advance Information)

3.2 FMH107—107-Ball Fine Pitch Ball Grid Array (FBGA) 9 x 12 mm package

Figure 3.2 FMH107

A

0.15

D

C

(2X)

E

PIN A1

CORNER

A2

A

PACKAGE FMH 107

JEDEC N/A

D x E 12.00 mm x 9.00 mm

SYMBOL MIN NOM MAX NOTE

A --- --- 1.40 PROFILE

A1 0.17 --- --- BALL HEIGHT

A2 0.94 --- 1.11 BODY THICKNESS

D 12.00 BSC. BODY SIZE

E 9.00 BSC. BODY SIZE

D1 8.80 BSC. MATRIX FOOTPRINT

E1 7.20 BSC. MATRIX FOOTPRINT

MD 12 MATRIX SIZE D DIRECTION

ME 10 MATRIX SIZE E DIRECTION

n 107 BALL COUNT

b 0.35 0.40 0.45 BALL DIAMETER

Ø

eE 0.80 BSC. BALL PITCH

eD 0.80 BSC. BALL PITCH

SD / SE 0.40 BSC. SOLDER BALL PLACEMENT

INDEX MARK

9

TOP VIEW

A1

6

SIDE VIEW

b

107X

0.15 M CMCAB

0.08

PACKAGE

A3,A4,A5,A6,A7,A8, DEPOPULATED SOLDER BALLS

B1,M3,M4,M5,M6,M7,M8

0.15

(2X)

C

eD

D1

10

9

8

7
6

5

4

eE

3

2

1

KML

B

C

0.20

C

C

0.08

NOTES:

1. DIMENSIONING AND TOLERANCING METHODS PER

2. ALL DIMENSIONS ARE IN MILLIMETERS.

3. BALL POSITION DESIGNATION PER JEP95, SECTION

4. e REPRESENTS THE SOLDER BALL GRID PITCH.

5. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D"

6 DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL

7 SD AND SE ARE MEASURED WITH RESPECT TO

8. "+" INDICATES THE THEORETICAL CENTER OF

9. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER

7

SD

BOTTOM VIEW

ASME Y14.5M-1994.

4.3, SPP-010.

DIRECTION.

SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E"
DIRECTION.

n IS THE NUMBER OF POPULTED SOLDER BALL
POSITIONS FOR MATRIX SIZE MD X ME.

DIAMETER IN A PLANE PARALLEL TO DATUM C.

DATUMS A AND B AND DEFINE THE POSITION OF THE
CENTER SOLDER BALL IN THE OUTER ROW.

WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS
IN THE OUTER ROW SD OR SE = 0.000.

WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS
IN THE OUTER ROW, SD OR SE = e/2

DEPOPULATED BALLS.

OR INK MARK, METALLIZED MARK INDENTATION OR
OTHER MEANS.

BJHGFE CDA

SE

7

E1

PIN A1

CORNER

3512 \ 16-038.19 \ 8.9.05

S75PL-N_00_01E April 21, 2006 S75PL-N MirrorBit™ ORNAND™ MCPs 5

Data Sheet (Advance Information)

4. Revision History

4.1 Revision A (April 21, 2006)

Initial release.

Colophon

The products described in this document are designed, developed and manufactured as contemplated for general use, including without
limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured as
contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect to the
public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility,
aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in weapon system), or (2) for
any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). Please note that Spansion will not be liable to
you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. Any semiconductor
devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design
measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal
operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under
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the prior authorization by the respective government entity will be required for export of those products.

Trademarks and Notice

The contents of this document are subject to change without notice. This document may contain information on a Spansion product under
development by Spansion. Spansion reserves the right to change or discontinue work on any product without notice. The information in this
document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose,
merchantability, non-infringement of third-party rights, or any other warranty, express, implied, or statutory. Spansion assumes no liability for any
damages of any kind arising out of the use of the information in this document.

Copyright © 2006 Spansion LLC. All Rights Reserved. Spansion, the Spansion logo, MirrorBit, ORNAND, and combinations thereof are
trademarks of Spansion LLC. Other names are for informational purposes only and may be trademarks of their respective owners.

6 S75PL-N MirrorBit™ ORNAND™ MCPs S75PL-N_00_01E April 21, 2006